MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NUVOTON/TARGET_NUC472/spi_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2015-2016 Nuvoton
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16
sahilmgandhi 18:6a4db94011d3 17 #include "spi_api.h"
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 #if DEVICE_SPI
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 22 #include "pinmap.h"
sahilmgandhi 18:6a4db94011d3 23 #include "PeripheralPins.h"
sahilmgandhi 18:6a4db94011d3 24 #include "nu_modutil.h"
sahilmgandhi 18:6a4db94011d3 25 #include "nu_miscutil.h"
sahilmgandhi 18:6a4db94011d3 26 #include "nu_bitutil.h"
sahilmgandhi 18:6a4db94011d3 27
sahilmgandhi 18:6a4db94011d3 28 #if DEVICE_SPI_ASYNCH
sahilmgandhi 18:6a4db94011d3 29 #include "dma_api.h"
sahilmgandhi 18:6a4db94011d3 30 #include "dma.h"
sahilmgandhi 18:6a4db94011d3 31 #endif
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 #define NU_SPI_FRAME_MIN 8
sahilmgandhi 18:6a4db94011d3 34 #define NU_SPI_FRAME_MAX 32
sahilmgandhi 18:6a4db94011d3 35 #define NU_SPI_FIFO_DEPTH 8
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37 struct nu_spi_var {
sahilmgandhi 18:6a4db94011d3 38 #if DEVICE_SPI_ASYNCH
sahilmgandhi 18:6a4db94011d3 39 uint8_t pdma_perp_tx;
sahilmgandhi 18:6a4db94011d3 40 uint8_t pdma_perp_rx;
sahilmgandhi 18:6a4db94011d3 41 #endif
sahilmgandhi 18:6a4db94011d3 42 };
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 static struct nu_spi_var spi0_var = {
sahilmgandhi 18:6a4db94011d3 45 #if DEVICE_SPI_ASYNCH
sahilmgandhi 18:6a4db94011d3 46 .pdma_perp_tx = PDMA_SPI0_TX,
sahilmgandhi 18:6a4db94011d3 47 .pdma_perp_rx = PDMA_SPI0_RX
sahilmgandhi 18:6a4db94011d3 48 #endif
sahilmgandhi 18:6a4db94011d3 49 };
sahilmgandhi 18:6a4db94011d3 50 static struct nu_spi_var spi1_var = {
sahilmgandhi 18:6a4db94011d3 51 #if DEVICE_SPI_ASYNCH
sahilmgandhi 18:6a4db94011d3 52 .pdma_perp_tx = PDMA_SPI1_TX,
sahilmgandhi 18:6a4db94011d3 53 .pdma_perp_rx = PDMA_SPI1_RX
sahilmgandhi 18:6a4db94011d3 54 #endif
sahilmgandhi 18:6a4db94011d3 55 };
sahilmgandhi 18:6a4db94011d3 56 static struct nu_spi_var spi2_var = {
sahilmgandhi 18:6a4db94011d3 57 #if DEVICE_SPI_ASYNCH
sahilmgandhi 18:6a4db94011d3 58 .pdma_perp_tx = PDMA_SPI2_TX,
sahilmgandhi 18:6a4db94011d3 59 .pdma_perp_rx = PDMA_SPI2_RX
sahilmgandhi 18:6a4db94011d3 60 #endif
sahilmgandhi 18:6a4db94011d3 61 };
sahilmgandhi 18:6a4db94011d3 62 static struct nu_spi_var spi3_var = {
sahilmgandhi 18:6a4db94011d3 63 #if DEVICE_SPI_ASYNCH
sahilmgandhi 18:6a4db94011d3 64 .pdma_perp_tx = PDMA_SPI3_TX,
sahilmgandhi 18:6a4db94011d3 65 .pdma_perp_rx = PDMA_SPI3_RX
sahilmgandhi 18:6a4db94011d3 66 #endif
sahilmgandhi 18:6a4db94011d3 67 };
sahilmgandhi 18:6a4db94011d3 68
sahilmgandhi 18:6a4db94011d3 69 #if DEVICE_SPI_ASYNCH
sahilmgandhi 18:6a4db94011d3 70 static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t enable);
sahilmgandhi 18:6a4db94011d3 71 static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable);
sahilmgandhi 18:6a4db94011d3 72 static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit);
sahilmgandhi 18:6a4db94011d3 73 static uint32_t spi_master_read_asynch(spi_t *obj);
sahilmgandhi 18:6a4db94011d3 74 static uint32_t spi_event_check(spi_t *obj);
sahilmgandhi 18:6a4db94011d3 75 static void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable);
sahilmgandhi 18:6a4db94011d3 76 static void spi_buffer_set(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length);
sahilmgandhi 18:6a4db94011d3 77 static void spi_check_dma_usage(DMAUsage *dma_usage, int *dma_ch_tx, int *dma_ch_rx);
sahilmgandhi 18:6a4db94011d3 78 static uint8_t spi_get_data_width(spi_t *obj);
sahilmgandhi 18:6a4db94011d3 79 static int spi_is_tx_complete(spi_t *obj);
sahilmgandhi 18:6a4db94011d3 80 static int spi_is_rx_complete(spi_t *obj);
sahilmgandhi 18:6a4db94011d3 81 static int spi_writeable(spi_t * obj);
sahilmgandhi 18:6a4db94011d3 82 static int spi_readable(spi_t * obj);
sahilmgandhi 18:6a4db94011d3 83 static void spi_dma_handler_tx(uint32_t id, uint32_t event_dma);
sahilmgandhi 18:6a4db94011d3 84 static void spi_dma_handler_rx(uint32_t id, uint32_t event_dma);
sahilmgandhi 18:6a4db94011d3 85 #endif
sahilmgandhi 18:6a4db94011d3 86
sahilmgandhi 18:6a4db94011d3 87 static uint32_t spi_modinit_mask = 0;
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 static const struct nu_modinit_s spi_modinit_tab[] = {
sahilmgandhi 18:6a4db94011d3 90 {SPI_0, SPI0_MODULE, 0, 0, SPI0_RST, SPI0_IRQn, &spi0_var},
sahilmgandhi 18:6a4db94011d3 91 {SPI_1, SPI1_MODULE, 0, 0, SPI1_RST, SPI1_IRQn, &spi1_var},
sahilmgandhi 18:6a4db94011d3 92 {SPI_2, SPI2_MODULE, 0, 0, SPI2_RST, SPI2_IRQn, &spi2_var},
sahilmgandhi 18:6a4db94011d3 93 {SPI_3, SPI3_MODULE, 0, 0, SPI3_RST, SPI3_IRQn, &spi3_var},
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
sahilmgandhi 18:6a4db94011d3 96 };
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
sahilmgandhi 18:6a4db94011d3 99 // Determine which SPI_x the pins are used for
sahilmgandhi 18:6a4db94011d3 100 uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
sahilmgandhi 18:6a4db94011d3 101 uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
sahilmgandhi 18:6a4db94011d3 102 uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
sahilmgandhi 18:6a4db94011d3 103 uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
sahilmgandhi 18:6a4db94011d3 104 uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
sahilmgandhi 18:6a4db94011d3 105 uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
sahilmgandhi 18:6a4db94011d3 106 obj->spi.spi = (SPIName) pinmap_merge(spi_data, spi_cntl);
sahilmgandhi 18:6a4db94011d3 107 MBED_ASSERT((int)obj->spi.spi != NC);
sahilmgandhi 18:6a4db94011d3 108
sahilmgandhi 18:6a4db94011d3 109 const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
sahilmgandhi 18:6a4db94011d3 110 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 111 MBED_ASSERT(modinit->modname == obj->spi.spi);
sahilmgandhi 18:6a4db94011d3 112
sahilmgandhi 18:6a4db94011d3 113 // Reset this module
sahilmgandhi 18:6a4db94011d3 114 SYS_ResetModule(modinit->rsetidx);
sahilmgandhi 18:6a4db94011d3 115
sahilmgandhi 18:6a4db94011d3 116 // Enable IP clock
sahilmgandhi 18:6a4db94011d3 117 CLK_EnableModuleClock(modinit->clkidx);
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 //SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 pinmap_pinout(mosi, PinMap_SPI_MOSI);
sahilmgandhi 18:6a4db94011d3 122 pinmap_pinout(miso, PinMap_SPI_MISO);
sahilmgandhi 18:6a4db94011d3 123 pinmap_pinout(sclk, PinMap_SPI_SCLK);
sahilmgandhi 18:6a4db94011d3 124 pinmap_pinout(ssel, PinMap_SPI_SSEL);
sahilmgandhi 18:6a4db94011d3 125
sahilmgandhi 18:6a4db94011d3 126 obj->spi.pin_mosi = mosi;
sahilmgandhi 18:6a4db94011d3 127 obj->spi.pin_miso = miso;
sahilmgandhi 18:6a4db94011d3 128 obj->spi.pin_sclk = sclk;
sahilmgandhi 18:6a4db94011d3 129 obj->spi.pin_ssel = ssel;
sahilmgandhi 18:6a4db94011d3 130
sahilmgandhi 18:6a4db94011d3 131 // Configure the SPI data format and frequency
sahilmgandhi 18:6a4db94011d3 132 //spi_format(obj, 8, 0, SPI_MSB); // 8 bits, mode 0
sahilmgandhi 18:6a4db94011d3 133 //spi_frequency(obj, 1000000);
sahilmgandhi 18:6a4db94011d3 134
sahilmgandhi 18:6a4db94011d3 135 #if DEVICE_SPI_ASYNCH
sahilmgandhi 18:6a4db94011d3 136 obj->spi.dma_usage = DMA_USAGE_NEVER;
sahilmgandhi 18:6a4db94011d3 137 obj->spi.event = 0;
sahilmgandhi 18:6a4db94011d3 138 obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
sahilmgandhi 18:6a4db94011d3 139 obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
sahilmgandhi 18:6a4db94011d3 140 #endif
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142 // Mark this module to be inited.
sahilmgandhi 18:6a4db94011d3 143 int i = modinit - spi_modinit_tab;
sahilmgandhi 18:6a4db94011d3 144 spi_modinit_mask |= 1 << i;
sahilmgandhi 18:6a4db94011d3 145 }
sahilmgandhi 18:6a4db94011d3 146
sahilmgandhi 18:6a4db94011d3 147 void spi_free(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 148 {
sahilmgandhi 18:6a4db94011d3 149 #if DEVICE_SPI_ASYNCH
sahilmgandhi 18:6a4db94011d3 150 if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
sahilmgandhi 18:6a4db94011d3 151 dma_channel_free(obj->spi.dma_chn_id_tx);
sahilmgandhi 18:6a4db94011d3 152 obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
sahilmgandhi 18:6a4db94011d3 153 }
sahilmgandhi 18:6a4db94011d3 154 if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
sahilmgandhi 18:6a4db94011d3 155 dma_channel_free(obj->spi.dma_chn_id_rx);
sahilmgandhi 18:6a4db94011d3 156 obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
sahilmgandhi 18:6a4db94011d3 157 }
sahilmgandhi 18:6a4db94011d3 158 #endif
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 SPI_Close((SPI_T *) NU_MODBASE(obj->spi.spi));
sahilmgandhi 18:6a4db94011d3 161
sahilmgandhi 18:6a4db94011d3 162 const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
sahilmgandhi 18:6a4db94011d3 163 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 164 MBED_ASSERT(modinit->modname == obj->spi.spi);
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 SPI_DisableInt(((SPI_T *) NU_MODBASE(obj->spi.spi)), (SPI_FIFO_RXOVIEN_MASK | SPI_FIFO_RXTHIEN_MASK | SPI_FIFO_TXTHIEN_MASK));
sahilmgandhi 18:6a4db94011d3 167 NVIC_DisableIRQ(modinit->irq_n);
sahilmgandhi 18:6a4db94011d3 168
sahilmgandhi 18:6a4db94011d3 169 // Disable IP clock
sahilmgandhi 18:6a4db94011d3 170 CLK_DisableModuleClock(modinit->clkidx);
sahilmgandhi 18:6a4db94011d3 171
sahilmgandhi 18:6a4db94011d3 172 //((struct nu_spi_var *) modinit->var)->obj = NULL;
sahilmgandhi 18:6a4db94011d3 173
sahilmgandhi 18:6a4db94011d3 174 // Mark this module to be deinited.
sahilmgandhi 18:6a4db94011d3 175 int i = modinit - spi_modinit_tab;
sahilmgandhi 18:6a4db94011d3 176 spi_modinit_mask &= ~(1 << i);
sahilmgandhi 18:6a4db94011d3 177 }
sahilmgandhi 18:6a4db94011d3 178 void spi_format(spi_t *obj, int bits, int mode, int slave)
sahilmgandhi 18:6a4db94011d3 179 {
sahilmgandhi 18:6a4db94011d3 180 MBED_ASSERT(bits >= NU_SPI_FRAME_MIN && bits <= NU_SPI_FRAME_MAX);
sahilmgandhi 18:6a4db94011d3 181
sahilmgandhi 18:6a4db94011d3 182 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
sahilmgandhi 18:6a4db94011d3 183
sahilmgandhi 18:6a4db94011d3 184 // NOTE 1: All configurations should be ready before enabling SPI peripheral.
sahilmgandhi 18:6a4db94011d3 185 // NOTE 2: Re-configuration is allowed only as SPI peripheral is idle.
sahilmgandhi 18:6a4db94011d3 186 while (SPI_IS_BUSY(spi_base));
sahilmgandhi 18:6a4db94011d3 187 SPI_DISABLE(spi_base);
sahilmgandhi 18:6a4db94011d3 188
sahilmgandhi 18:6a4db94011d3 189 SPI_Open(spi_base,
sahilmgandhi 18:6a4db94011d3 190 slave ? SPI_SLAVE : SPI_MASTER,
sahilmgandhi 18:6a4db94011d3 191 (mode == 0) ? SPI_MODE_0 : (mode == 1) ? SPI_MODE_1 : (mode == 2) ? SPI_MODE_2 : SPI_MODE_3,
sahilmgandhi 18:6a4db94011d3 192 bits,
sahilmgandhi 18:6a4db94011d3 193 SPI_GetBusClock(spi_base));
sahilmgandhi 18:6a4db94011d3 194 // NOTE: Hardcode to be MSB first.
sahilmgandhi 18:6a4db94011d3 195 SPI_SET_MSB_FIRST(spi_base);
sahilmgandhi 18:6a4db94011d3 196
sahilmgandhi 18:6a4db94011d3 197 if (! slave) {
sahilmgandhi 18:6a4db94011d3 198 // Master
sahilmgandhi 18:6a4db94011d3 199 if (obj->spi.pin_ssel != NC) {
sahilmgandhi 18:6a4db94011d3 200 // Configure SS as low active.
sahilmgandhi 18:6a4db94011d3 201 SPI_EnableAutoSS(spi_base, SPI_SS0, SPI_SS_ACTIVE_LOW);
sahilmgandhi 18:6a4db94011d3 202 // NOTE: In NUC472 series, all SPI SS pins are SS0, so we can hardcode SS0 here.
sahilmgandhi 18:6a4db94011d3 203 }
sahilmgandhi 18:6a4db94011d3 204 else {
sahilmgandhi 18:6a4db94011d3 205 SPI_DisableAutoSS(spi_base);
sahilmgandhi 18:6a4db94011d3 206 }
sahilmgandhi 18:6a4db94011d3 207 }
sahilmgandhi 18:6a4db94011d3 208 else {
sahilmgandhi 18:6a4db94011d3 209 // Slave
sahilmgandhi 18:6a4db94011d3 210 // Configure SS as low active.
sahilmgandhi 18:6a4db94011d3 211 spi_base->SSCTL &= ~SPI_SSCTL_SSACTPOL_Msk;
sahilmgandhi 18:6a4db94011d3 212 // NOTE: SPI_SS0 is defined as the slave select input in Slave mode.
sahilmgandhi 18:6a4db94011d3 213 }
sahilmgandhi 18:6a4db94011d3 214 }
sahilmgandhi 18:6a4db94011d3 215
sahilmgandhi 18:6a4db94011d3 216 void spi_frequency(spi_t *obj, int hz)
sahilmgandhi 18:6a4db94011d3 217 {
sahilmgandhi 18:6a4db94011d3 218 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
sahilmgandhi 18:6a4db94011d3 219
sahilmgandhi 18:6a4db94011d3 220 while (SPI_IS_BUSY(spi_base));
sahilmgandhi 18:6a4db94011d3 221 SPI_DISABLE(spi_base);
sahilmgandhi 18:6a4db94011d3 222
sahilmgandhi 18:6a4db94011d3 223 SPI_SetBusClock((SPI_T *) NU_MODBASE(obj->spi.spi), hz);
sahilmgandhi 18:6a4db94011d3 224 }
sahilmgandhi 18:6a4db94011d3 225
sahilmgandhi 18:6a4db94011d3 226
sahilmgandhi 18:6a4db94011d3 227 int spi_master_write(spi_t *obj, int value)
sahilmgandhi 18:6a4db94011d3 228 {
sahilmgandhi 18:6a4db94011d3 229 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
sahilmgandhi 18:6a4db94011d3 230
sahilmgandhi 18:6a4db94011d3 231 // NOTE: Data in receive FIFO can be read out via ICE.
sahilmgandhi 18:6a4db94011d3 232 SPI_ENABLE(spi_base);
sahilmgandhi 18:6a4db94011d3 233
sahilmgandhi 18:6a4db94011d3 234 // Wait for tx buffer empty
sahilmgandhi 18:6a4db94011d3 235 while(! spi_writeable(obj));
sahilmgandhi 18:6a4db94011d3 236 SPI_WRITE_TX(spi_base, value);
sahilmgandhi 18:6a4db94011d3 237
sahilmgandhi 18:6a4db94011d3 238 // Wait for rx buffer full
sahilmgandhi 18:6a4db94011d3 239 while (! spi_readable(obj));
sahilmgandhi 18:6a4db94011d3 240 int value2 = SPI_READ_RX(spi_base);
sahilmgandhi 18:6a4db94011d3 241
sahilmgandhi 18:6a4db94011d3 242 SPI_DISABLE(spi_base);
sahilmgandhi 18:6a4db94011d3 243
sahilmgandhi 18:6a4db94011d3 244 return value2;
sahilmgandhi 18:6a4db94011d3 245 }
sahilmgandhi 18:6a4db94011d3 246
sahilmgandhi 18:6a4db94011d3 247 #if DEVICE_SPISLAVE
sahilmgandhi 18:6a4db94011d3 248 int spi_slave_receive(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 249 {
sahilmgandhi 18:6a4db94011d3 250 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
sahilmgandhi 18:6a4db94011d3 251
sahilmgandhi 18:6a4db94011d3 252 SPI_ENABLE(spi_base);
sahilmgandhi 18:6a4db94011d3 253
sahilmgandhi 18:6a4db94011d3 254 return spi_readable(obj);
sahilmgandhi 18:6a4db94011d3 255 };
sahilmgandhi 18:6a4db94011d3 256
sahilmgandhi 18:6a4db94011d3 257 int spi_slave_read(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 258 {
sahilmgandhi 18:6a4db94011d3 259 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
sahilmgandhi 18:6a4db94011d3 260
sahilmgandhi 18:6a4db94011d3 261 SPI_ENABLE(spi_base);
sahilmgandhi 18:6a4db94011d3 262
sahilmgandhi 18:6a4db94011d3 263 // Wait for rx buffer full
sahilmgandhi 18:6a4db94011d3 264 while (! spi_readable(obj));
sahilmgandhi 18:6a4db94011d3 265 int value = SPI_READ_RX(spi_base);
sahilmgandhi 18:6a4db94011d3 266 return value;
sahilmgandhi 18:6a4db94011d3 267 }
sahilmgandhi 18:6a4db94011d3 268
sahilmgandhi 18:6a4db94011d3 269 void spi_slave_write(spi_t *obj, int value)
sahilmgandhi 18:6a4db94011d3 270 {
sahilmgandhi 18:6a4db94011d3 271 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
sahilmgandhi 18:6a4db94011d3 272
sahilmgandhi 18:6a4db94011d3 273 SPI_ENABLE(spi_base);
sahilmgandhi 18:6a4db94011d3 274
sahilmgandhi 18:6a4db94011d3 275 // Wait for tx buffer empty
sahilmgandhi 18:6a4db94011d3 276 while(! spi_writeable(obj));
sahilmgandhi 18:6a4db94011d3 277 SPI_WRITE_TX(spi_base, value);
sahilmgandhi 18:6a4db94011d3 278 }
sahilmgandhi 18:6a4db94011d3 279 #endif
sahilmgandhi 18:6a4db94011d3 280
sahilmgandhi 18:6a4db94011d3 281 #if DEVICE_SPI_ASYNCH
sahilmgandhi 18:6a4db94011d3 282 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
sahilmgandhi 18:6a4db94011d3 283 {
sahilmgandhi 18:6a4db94011d3 284 //MBED_ASSERT(bits >= NU_SPI_FRAME_MIN && bits <= NU_SPI_FRAME_MAX);
sahilmgandhi 18:6a4db94011d3 285 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
sahilmgandhi 18:6a4db94011d3 286 SPI_SET_DATA_WIDTH(spi_base, bit_width);
sahilmgandhi 18:6a4db94011d3 287
sahilmgandhi 18:6a4db94011d3 288 obj->spi.dma_usage = hint;
sahilmgandhi 18:6a4db94011d3 289 spi_check_dma_usage(&obj->spi.dma_usage, &obj->spi.dma_chn_id_tx, &obj->spi.dma_chn_id_rx);
sahilmgandhi 18:6a4db94011d3 290 uint32_t data_width = spi_get_data_width(obj);
sahilmgandhi 18:6a4db94011d3 291 // Conditions to go DMA way:
sahilmgandhi 18:6a4db94011d3 292 // (1) No DMA support for non-8 multiple data width.
sahilmgandhi 18:6a4db94011d3 293 // (2) tx length >= rx length. Otherwise, as tx DMA is done, no bus activity for remaining rx.
sahilmgandhi 18:6a4db94011d3 294 if ((data_width % 8) ||
sahilmgandhi 18:6a4db94011d3 295 (tx_length < rx_length)) {
sahilmgandhi 18:6a4db94011d3 296 obj->spi.dma_usage = DMA_USAGE_NEVER;
sahilmgandhi 18:6a4db94011d3 297 dma_channel_free(obj->spi.dma_chn_id_tx);
sahilmgandhi 18:6a4db94011d3 298 obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
sahilmgandhi 18:6a4db94011d3 299 dma_channel_free(obj->spi.dma_chn_id_rx);
sahilmgandhi 18:6a4db94011d3 300 obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
sahilmgandhi 18:6a4db94011d3 301 }
sahilmgandhi 18:6a4db94011d3 302
sahilmgandhi 18:6a4db94011d3 303 // SPI IRQ is necessary for both interrupt way and DMA way
sahilmgandhi 18:6a4db94011d3 304 spi_enable_event(obj, event, 1);
sahilmgandhi 18:6a4db94011d3 305 spi_buffer_set(obj, tx, tx_length, rx, rx_length);
sahilmgandhi 18:6a4db94011d3 306
sahilmgandhi 18:6a4db94011d3 307 SPI_ENABLE(spi_base);
sahilmgandhi 18:6a4db94011d3 308
sahilmgandhi 18:6a4db94011d3 309 if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
sahilmgandhi 18:6a4db94011d3 310 // Interrupt way
sahilmgandhi 18:6a4db94011d3 311 spi_master_write_asynch(obj, NU_SPI_FIFO_DEPTH / 2);
sahilmgandhi 18:6a4db94011d3 312 spi_enable_vector_interrupt(obj, handler, 1);
sahilmgandhi 18:6a4db94011d3 313 spi_master_enable_interrupt(obj, 1);
sahilmgandhi 18:6a4db94011d3 314 } else {
sahilmgandhi 18:6a4db94011d3 315 // DMA way
sahilmgandhi 18:6a4db94011d3 316 const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
sahilmgandhi 18:6a4db94011d3 317 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 318 MBED_ASSERT(modinit->modname == obj->spi.spi);
sahilmgandhi 18:6a4db94011d3 319
sahilmgandhi 18:6a4db94011d3 320 PDMA_T *pdma_base = dma_modbase();
sahilmgandhi 18:6a4db94011d3 321
sahilmgandhi 18:6a4db94011d3 322 // Configure tx DMA
sahilmgandhi 18:6a4db94011d3 323 pdma_base->CHCTL |= 1 << obj->spi.dma_chn_id_tx; // Enable this DMA channel
sahilmgandhi 18:6a4db94011d3 324 PDMA_SetTransferMode(obj->spi.dma_chn_id_tx,
sahilmgandhi 18:6a4db94011d3 325 ((struct nu_spi_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA
sahilmgandhi 18:6a4db94011d3 326 0, // Scatter-gather disabled
sahilmgandhi 18:6a4db94011d3 327 0); // Scatter-gather descriptor address
sahilmgandhi 18:6a4db94011d3 328 PDMA_SetTransferCnt(obj->spi.dma_chn_id_tx,
sahilmgandhi 18:6a4db94011d3 329 (data_width == 8) ? PDMA_WIDTH_8 : (data_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
sahilmgandhi 18:6a4db94011d3 330 tx_length);
sahilmgandhi 18:6a4db94011d3 331 PDMA_SetTransferAddr(obj->spi.dma_chn_id_tx,
sahilmgandhi 18:6a4db94011d3 332 ((uint32_t) tx) + (data_width / 8) * tx_length, // NOTE: End of source address
sahilmgandhi 18:6a4db94011d3 333 PDMA_SAR_INC, // Source address incremental
sahilmgandhi 18:6a4db94011d3 334 (uint32_t) &spi_base->TX, // Destination address
sahilmgandhi 18:6a4db94011d3 335 PDMA_DAR_FIX); // Destination address fixed
sahilmgandhi 18:6a4db94011d3 336 PDMA_SetBurstType(obj->spi.dma_chn_id_tx,
sahilmgandhi 18:6a4db94011d3 337 PDMA_REQ_SINGLE, // Single mode
sahilmgandhi 18:6a4db94011d3 338 0); // Burst size
sahilmgandhi 18:6a4db94011d3 339 PDMA_EnableInt(obj->spi.dma_chn_id_tx,
sahilmgandhi 18:6a4db94011d3 340 0); // Interrupt type. No use here
sahilmgandhi 18:6a4db94011d3 341 // Register DMA event handler
sahilmgandhi 18:6a4db94011d3 342 dma_set_handler(obj->spi.dma_chn_id_tx, (uint32_t) spi_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
sahilmgandhi 18:6a4db94011d3 343
sahilmgandhi 18:6a4db94011d3 344 // Configure rx DMA
sahilmgandhi 18:6a4db94011d3 345 pdma_base->CHCTL |= 1 << obj->spi.dma_chn_id_rx; // Enable this DMA channel
sahilmgandhi 18:6a4db94011d3 346 PDMA_SetTransferMode(obj->spi.dma_chn_id_rx,
sahilmgandhi 18:6a4db94011d3 347 ((struct nu_spi_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA
sahilmgandhi 18:6a4db94011d3 348 0, // Scatter-gather disabled
sahilmgandhi 18:6a4db94011d3 349 0); // Scatter-gather descriptor address
sahilmgandhi 18:6a4db94011d3 350 PDMA_SetTransferCnt(obj->spi.dma_chn_id_rx,
sahilmgandhi 18:6a4db94011d3 351 (data_width == 8) ? PDMA_WIDTH_8 : (data_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
sahilmgandhi 18:6a4db94011d3 352 rx_length);
sahilmgandhi 18:6a4db94011d3 353 PDMA_SetTransferAddr(obj->spi.dma_chn_id_rx,
sahilmgandhi 18:6a4db94011d3 354 (uint32_t) &spi_base->RX, // Source address
sahilmgandhi 18:6a4db94011d3 355 PDMA_SAR_FIX, // Source address fixed
sahilmgandhi 18:6a4db94011d3 356 ((uint32_t) rx) + (data_width / 8) * rx_length, // NOTE: End of destination address
sahilmgandhi 18:6a4db94011d3 357 PDMA_DAR_INC); // Destination address incremental
sahilmgandhi 18:6a4db94011d3 358 PDMA_SetBurstType(obj->spi.dma_chn_id_rx,
sahilmgandhi 18:6a4db94011d3 359 PDMA_REQ_SINGLE, // Single mode
sahilmgandhi 18:6a4db94011d3 360 0); // Burst size
sahilmgandhi 18:6a4db94011d3 361 PDMA_EnableInt(obj->spi.dma_chn_id_rx,
sahilmgandhi 18:6a4db94011d3 362 0); // Interrupt type. No use here
sahilmgandhi 18:6a4db94011d3 363 // Register DMA event handler
sahilmgandhi 18:6a4db94011d3 364 dma_set_handler(obj->spi.dma_chn_id_rx, (uint32_t) spi_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
sahilmgandhi 18:6a4db94011d3 365
sahilmgandhi 18:6a4db94011d3 366 // Start tx/rx DMA transfer
sahilmgandhi 18:6a4db94011d3 367 spi_enable_vector_interrupt(obj, handler, 1);
sahilmgandhi 18:6a4db94011d3 368 // NOTE: It is safer to start rx DMA first and then tx DMA. Otherwise, receive FIFO is subject to overflow by tx DMA.
sahilmgandhi 18:6a4db94011d3 369 SPI_TRIGGER_RX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
sahilmgandhi 18:6a4db94011d3 370 SPI_TRIGGER_TX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
sahilmgandhi 18:6a4db94011d3 371 spi_master_enable_interrupt(obj, 1);
sahilmgandhi 18:6a4db94011d3 372 }
sahilmgandhi 18:6a4db94011d3 373 }
sahilmgandhi 18:6a4db94011d3 374
sahilmgandhi 18:6a4db94011d3 375 /**
sahilmgandhi 18:6a4db94011d3 376 * Abort an SPI transfer
sahilmgandhi 18:6a4db94011d3 377 * This is a helper function for event handling. When any of the events listed occurs, the HAL will abort any ongoing
sahilmgandhi 18:6a4db94011d3 378 * transfers
sahilmgandhi 18:6a4db94011d3 379 * @param[in] obj The SPI peripheral to stop
sahilmgandhi 18:6a4db94011d3 380 */
sahilmgandhi 18:6a4db94011d3 381 void spi_abort_asynch(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 382 {
sahilmgandhi 18:6a4db94011d3 383 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
sahilmgandhi 18:6a4db94011d3 384 PDMA_T *pdma_base = dma_modbase();
sahilmgandhi 18:6a4db94011d3 385
sahilmgandhi 18:6a4db94011d3 386 if (obj->spi.dma_usage != DMA_USAGE_NEVER) {
sahilmgandhi 18:6a4db94011d3 387 // Receive FIFO Overrun in case of tx length > rx length on DMA way
sahilmgandhi 18:6a4db94011d3 388 if (spi_base->STATUS & SPI_STATUS_RXOVIF_Msk) {
sahilmgandhi 18:6a4db94011d3 389 spi_base->STATUS = SPI_STATUS_RXOVIF_Msk;
sahilmgandhi 18:6a4db94011d3 390 }
sahilmgandhi 18:6a4db94011d3 391
sahilmgandhi 18:6a4db94011d3 392 if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
sahilmgandhi 18:6a4db94011d3 393 PDMA_DisableInt(obj->spi.dma_chn_id_tx, 0);
sahilmgandhi 18:6a4db94011d3 394 // FIXME: Next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
sahilmgandhi 18:6a4db94011d3 395 //PDMA_STOP(obj->spi.dma_chn_id_tx);
sahilmgandhi 18:6a4db94011d3 396 pdma_base->CHCTL &= ~(1 << obj->spi.dma_chn_id_tx);
sahilmgandhi 18:6a4db94011d3 397 }
sahilmgandhi 18:6a4db94011d3 398 SPI_DISABLE_TX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
sahilmgandhi 18:6a4db94011d3 399
sahilmgandhi 18:6a4db94011d3 400 if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
sahilmgandhi 18:6a4db94011d3 401 PDMA_DisableInt(obj->spi.dma_chn_id_rx, 0);
sahilmgandhi 18:6a4db94011d3 402 // FIXME: Next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
sahilmgandhi 18:6a4db94011d3 403 //PDMA_STOP(obj->spi.dma_chn_id_rx);
sahilmgandhi 18:6a4db94011d3 404 pdma_base->CHCTL &= ~(1 << obj->spi.dma_chn_id_rx);
sahilmgandhi 18:6a4db94011d3 405 }
sahilmgandhi 18:6a4db94011d3 406 SPI_DISABLE_RX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
sahilmgandhi 18:6a4db94011d3 407 }
sahilmgandhi 18:6a4db94011d3 408
sahilmgandhi 18:6a4db94011d3 409 // Necessary for both interrupt way and DMA way
sahilmgandhi 18:6a4db94011d3 410 spi_enable_vector_interrupt(obj, 0, 0);
sahilmgandhi 18:6a4db94011d3 411 spi_master_enable_interrupt(obj, 0);
sahilmgandhi 18:6a4db94011d3 412
sahilmgandhi 18:6a4db94011d3 413 // FIXME: SPI H/W may get out of state without the busy check.
sahilmgandhi 18:6a4db94011d3 414 while (SPI_IS_BUSY(spi_base));
sahilmgandhi 18:6a4db94011d3 415 SPI_DISABLE(spi_base);
sahilmgandhi 18:6a4db94011d3 416
sahilmgandhi 18:6a4db94011d3 417 SPI_ClearRxFIFO(spi_base);
sahilmgandhi 18:6a4db94011d3 418 SPI_ClearTxFIFO(spi_base);
sahilmgandhi 18:6a4db94011d3 419 }
sahilmgandhi 18:6a4db94011d3 420
sahilmgandhi 18:6a4db94011d3 421 /**
sahilmgandhi 18:6a4db94011d3 422 * Handle the SPI interrupt
sahilmgandhi 18:6a4db94011d3 423 * Read frames until the RX FIFO is empty. Write at most as many frames as were read. This way,
sahilmgandhi 18:6a4db94011d3 424 * it is unlikely that the RX FIFO will overflow.
sahilmgandhi 18:6a4db94011d3 425 * @param[in] obj The SPI peripheral that generated the interrupt
sahilmgandhi 18:6a4db94011d3 426 * @return
sahilmgandhi 18:6a4db94011d3 427 */
sahilmgandhi 18:6a4db94011d3 428 uint32_t spi_irq_handler_asynch(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 429 {
sahilmgandhi 18:6a4db94011d3 430 // Check for SPI events
sahilmgandhi 18:6a4db94011d3 431 uint32_t event = spi_event_check(obj);
sahilmgandhi 18:6a4db94011d3 432 if (event) {
sahilmgandhi 18:6a4db94011d3 433 spi_abort_asynch(obj);
sahilmgandhi 18:6a4db94011d3 434 }
sahilmgandhi 18:6a4db94011d3 435
sahilmgandhi 18:6a4db94011d3 436 return (obj->spi.event & event) | ((event & SPI_EVENT_COMPLETE) ? SPI_EVENT_INTERNAL_TRANSFER_COMPLETE : 0);
sahilmgandhi 18:6a4db94011d3 437 }
sahilmgandhi 18:6a4db94011d3 438
sahilmgandhi 18:6a4db94011d3 439 uint8_t spi_active(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 440 {
sahilmgandhi 18:6a4db94011d3 441 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
sahilmgandhi 18:6a4db94011d3 442 // FIXME
sahilmgandhi 18:6a4db94011d3 443 /*
sahilmgandhi 18:6a4db94011d3 444 if ((obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length)
sahilmgandhi 18:6a4db94011d3 445 || (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) ){
sahilmgandhi 18:6a4db94011d3 446 return 1;
sahilmgandhi 18:6a4db94011d3 447 } else {
sahilmgandhi 18:6a4db94011d3 448 // interrupts are disabled, all transaction have been completed
sahilmgandhi 18:6a4db94011d3 449 // TODO: checking rx fifo, it reports data eventhough RFDF is not set
sahilmgandhi 18:6a4db94011d3 450 return DSPI_HAL_GetIntMode(obj->spi.address, kDspiRxFifoDrainRequest);
sahilmgandhi 18:6a4db94011d3 451 }*/
sahilmgandhi 18:6a4db94011d3 452
sahilmgandhi 18:6a4db94011d3 453 //return SPI_IS_BUSY(spi_base);
sahilmgandhi 18:6a4db94011d3 454 return (spi_base->CTL & SPI_CTL_SPIEN_Msk);
sahilmgandhi 18:6a4db94011d3 455 }
sahilmgandhi 18:6a4db94011d3 456
sahilmgandhi 18:6a4db94011d3 457 int spi_allow_powerdown(void)
sahilmgandhi 18:6a4db94011d3 458 {
sahilmgandhi 18:6a4db94011d3 459 uint32_t modinit_mask = spi_modinit_mask;
sahilmgandhi 18:6a4db94011d3 460 while (modinit_mask) {
sahilmgandhi 18:6a4db94011d3 461 int spi_idx = nu_ctz(modinit_mask);
sahilmgandhi 18:6a4db94011d3 462 const struct nu_modinit_s *modinit = spi_modinit_tab + spi_idx;
sahilmgandhi 18:6a4db94011d3 463 if (modinit->modname != NC) {
sahilmgandhi 18:6a4db94011d3 464 SPI_T *spi_base = (SPI_T *) NU_MODBASE(modinit->modname);
sahilmgandhi 18:6a4db94011d3 465 // Disallow entering power-down mode if SPI transfer is enabled.
sahilmgandhi 18:6a4db94011d3 466 if (spi_base->CTL & SPI_CTL_SPIEN_Msk) {
sahilmgandhi 18:6a4db94011d3 467 return 0;
sahilmgandhi 18:6a4db94011d3 468 }
sahilmgandhi 18:6a4db94011d3 469 }
sahilmgandhi 18:6a4db94011d3 470 modinit_mask &= ~(1 << spi_idx);
sahilmgandhi 18:6a4db94011d3 471 }
sahilmgandhi 18:6a4db94011d3 472
sahilmgandhi 18:6a4db94011d3 473 return 1;
sahilmgandhi 18:6a4db94011d3 474 }
sahilmgandhi 18:6a4db94011d3 475
sahilmgandhi 18:6a4db94011d3 476 static int spi_writeable(spi_t * obj)
sahilmgandhi 18:6a4db94011d3 477 {
sahilmgandhi 18:6a4db94011d3 478 // Receive FIFO must not be full to avoid receive FIFO overflow on next transmit/receive
sahilmgandhi 18:6a4db94011d3 479 //return (! SPI_GET_TX_FIFO_FULL_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi)))) && (SPI_GET_RX_FIFO_COUNT(((SPI_T *) NU_MODBASE(obj->spi.spi))) < NU_SPI_FIFO_DEPTH);
sahilmgandhi 18:6a4db94011d3 480 return (! SPI_GET_TX_FIFO_FULL_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi))));
sahilmgandhi 18:6a4db94011d3 481 }
sahilmgandhi 18:6a4db94011d3 482
sahilmgandhi 18:6a4db94011d3 483 static int spi_readable(spi_t * obj)
sahilmgandhi 18:6a4db94011d3 484 {
sahilmgandhi 18:6a4db94011d3 485 return ! SPI_GET_RX_FIFO_EMPTY_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi)));
sahilmgandhi 18:6a4db94011d3 486 }
sahilmgandhi 18:6a4db94011d3 487
sahilmgandhi 18:6a4db94011d3 488 static void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable)
sahilmgandhi 18:6a4db94011d3 489 {
sahilmgandhi 18:6a4db94011d3 490 obj->spi.event &= ~SPI_EVENT_ALL;
sahilmgandhi 18:6a4db94011d3 491 obj->spi.event |= (event & SPI_EVENT_ALL);
sahilmgandhi 18:6a4db94011d3 492 if (event & SPI_EVENT_RX_OVERFLOW) {
sahilmgandhi 18:6a4db94011d3 493 SPI_EnableInt((SPI_T *) NU_MODBASE(obj->spi.spi), SPI_FIFO_RXOVIEN_MASK);
sahilmgandhi 18:6a4db94011d3 494 }
sahilmgandhi 18:6a4db94011d3 495 }
sahilmgandhi 18:6a4db94011d3 496
sahilmgandhi 18:6a4db94011d3 497 static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t enable)
sahilmgandhi 18:6a4db94011d3 498 {
sahilmgandhi 18:6a4db94011d3 499 const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
sahilmgandhi 18:6a4db94011d3 500 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 501 MBED_ASSERT(modinit->modname == obj->spi.spi);
sahilmgandhi 18:6a4db94011d3 502
sahilmgandhi 18:6a4db94011d3 503 if (enable) {
sahilmgandhi 18:6a4db94011d3 504 NVIC_SetVector(modinit->irq_n, handler);
sahilmgandhi 18:6a4db94011d3 505 NVIC_EnableIRQ(modinit->irq_n);
sahilmgandhi 18:6a4db94011d3 506 }
sahilmgandhi 18:6a4db94011d3 507 else {
sahilmgandhi 18:6a4db94011d3 508 //NVIC_SetVector(modinit->irq_n, handler);
sahilmgandhi 18:6a4db94011d3 509 NVIC_DisableIRQ(modinit->irq_n);
sahilmgandhi 18:6a4db94011d3 510 }
sahilmgandhi 18:6a4db94011d3 511 }
sahilmgandhi 18:6a4db94011d3 512
sahilmgandhi 18:6a4db94011d3 513 static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable)
sahilmgandhi 18:6a4db94011d3 514 {
sahilmgandhi 18:6a4db94011d3 515 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
sahilmgandhi 18:6a4db94011d3 516
sahilmgandhi 18:6a4db94011d3 517 if (enable) {
sahilmgandhi 18:6a4db94011d3 518 SPI_SetFIFOThreshold(spi_base, 4, 4);
sahilmgandhi 18:6a4db94011d3 519 //SPI_SET_SUSPEND_CYCLE(spi_base, 4);
sahilmgandhi 18:6a4db94011d3 520 // Enable tx/rx FIFO threshold interrupt
sahilmgandhi 18:6a4db94011d3 521 SPI_EnableInt(spi_base, SPI_FIFO_RXTHIEN_MASK | SPI_FIFO_TXTHIEN_MASK);
sahilmgandhi 18:6a4db94011d3 522 }
sahilmgandhi 18:6a4db94011d3 523 else {
sahilmgandhi 18:6a4db94011d3 524 SPI_DisableInt(spi_base, SPI_FIFO_RXTHIEN_MASK | SPI_FIFO_TXTHIEN_MASK);
sahilmgandhi 18:6a4db94011d3 525 }
sahilmgandhi 18:6a4db94011d3 526 }
sahilmgandhi 18:6a4db94011d3 527
sahilmgandhi 18:6a4db94011d3 528 static uint32_t spi_event_check(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 529 {
sahilmgandhi 18:6a4db94011d3 530 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
sahilmgandhi 18:6a4db94011d3 531 uint32_t event = 0;
sahilmgandhi 18:6a4db94011d3 532
sahilmgandhi 18:6a4db94011d3 533 if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
sahilmgandhi 18:6a4db94011d3 534 uint32_t n_rec = spi_master_read_asynch(obj);
sahilmgandhi 18:6a4db94011d3 535 spi_master_write_asynch(obj, n_rec);
sahilmgandhi 18:6a4db94011d3 536 }
sahilmgandhi 18:6a4db94011d3 537
sahilmgandhi 18:6a4db94011d3 538 if (spi_is_tx_complete(obj) && spi_is_rx_complete(obj)) {
sahilmgandhi 18:6a4db94011d3 539 event |= SPI_EVENT_COMPLETE;
sahilmgandhi 18:6a4db94011d3 540 }
sahilmgandhi 18:6a4db94011d3 541
sahilmgandhi 18:6a4db94011d3 542 // Receive FIFO Overrun
sahilmgandhi 18:6a4db94011d3 543 if (spi_base->STATUS & SPI_STATUS_RXOVIF_Msk) {
sahilmgandhi 18:6a4db94011d3 544 spi_base->STATUS = SPI_STATUS_RXOVIF_Msk;
sahilmgandhi 18:6a4db94011d3 545 // In case of tx length > rx length on DMA way
sahilmgandhi 18:6a4db94011d3 546 if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
sahilmgandhi 18:6a4db94011d3 547 event |= SPI_EVENT_RX_OVERFLOW;
sahilmgandhi 18:6a4db94011d3 548 }
sahilmgandhi 18:6a4db94011d3 549 }
sahilmgandhi 18:6a4db94011d3 550
sahilmgandhi 18:6a4db94011d3 551 // Receive Time-Out
sahilmgandhi 18:6a4db94011d3 552 if (spi_base->STATUS & SPI_STATUS_RXTOIF_Msk) {
sahilmgandhi 18:6a4db94011d3 553 spi_base->STATUS = SPI_STATUS_RXTOIF_Msk;
sahilmgandhi 18:6a4db94011d3 554 //event |= SPI_EVENT_ERROR;
sahilmgandhi 18:6a4db94011d3 555 }
sahilmgandhi 18:6a4db94011d3 556 // Transmit FIFO Under-Run
sahilmgandhi 18:6a4db94011d3 557 if (spi_base->STATUS & SPI_STATUS_TXUFIF_Msk) {
sahilmgandhi 18:6a4db94011d3 558 spi_base->STATUS = SPI_STATUS_TXUFIF_Msk;
sahilmgandhi 18:6a4db94011d3 559 event |= SPI_EVENT_ERROR;
sahilmgandhi 18:6a4db94011d3 560 }
sahilmgandhi 18:6a4db94011d3 561
sahilmgandhi 18:6a4db94011d3 562 return event;
sahilmgandhi 18:6a4db94011d3 563 }
sahilmgandhi 18:6a4db94011d3 564
sahilmgandhi 18:6a4db94011d3 565 /**
sahilmgandhi 18:6a4db94011d3 566 * Send words from the SPI TX buffer until the send limit is reached or the TX FIFO is full
sahilmgandhi 18:6a4db94011d3 567 * tx_limit is provided to ensure that the number of SPI frames (words) in flight can be managed.
sahilmgandhi 18:6a4db94011d3 568 * @param[in] obj The SPI object on which to operate
sahilmgandhi 18:6a4db94011d3 569 * @param[in] tx_limit The maximum number of words to send
sahilmgandhi 18:6a4db94011d3 570 * @return The number of SPI words that have been transfered
sahilmgandhi 18:6a4db94011d3 571 */
sahilmgandhi 18:6a4db94011d3 572 static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit)
sahilmgandhi 18:6a4db94011d3 573 {
sahilmgandhi 18:6a4db94011d3 574 uint32_t n_words = 0;
sahilmgandhi 18:6a4db94011d3 575 uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos;
sahilmgandhi 18:6a4db94011d3 576 uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos;
sahilmgandhi 18:6a4db94011d3 577 uint32_t max_tx = NU_MAX(tx_rmn, rx_rmn);
sahilmgandhi 18:6a4db94011d3 578 max_tx = NU_MIN(max_tx, tx_limit);
sahilmgandhi 18:6a4db94011d3 579 uint8_t data_width = spi_get_data_width(obj);
sahilmgandhi 18:6a4db94011d3 580 uint8_t bytes_per_word = (data_width + 7) / 8;
sahilmgandhi 18:6a4db94011d3 581 uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos;
sahilmgandhi 18:6a4db94011d3 582 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
sahilmgandhi 18:6a4db94011d3 583
sahilmgandhi 18:6a4db94011d3 584 while ((n_words < max_tx) && spi_writeable(obj)) {
sahilmgandhi 18:6a4db94011d3 585 if (spi_is_tx_complete(obj)) {
sahilmgandhi 18:6a4db94011d3 586 // Transmit dummy as transmit buffer is empty
sahilmgandhi 18:6a4db94011d3 587 SPI_WRITE_TX(spi_base, 0);
sahilmgandhi 18:6a4db94011d3 588 }
sahilmgandhi 18:6a4db94011d3 589 else {
sahilmgandhi 18:6a4db94011d3 590 switch (bytes_per_word) {
sahilmgandhi 18:6a4db94011d3 591 case 4:
sahilmgandhi 18:6a4db94011d3 592 SPI_WRITE_TX(spi_base, nu_get32_le(tx));
sahilmgandhi 18:6a4db94011d3 593 tx += 4;
sahilmgandhi 18:6a4db94011d3 594 break;
sahilmgandhi 18:6a4db94011d3 595 case 2:
sahilmgandhi 18:6a4db94011d3 596 SPI_WRITE_TX(spi_base, nu_get16_le(tx));
sahilmgandhi 18:6a4db94011d3 597 tx += 2;
sahilmgandhi 18:6a4db94011d3 598 break;
sahilmgandhi 18:6a4db94011d3 599 case 1:
sahilmgandhi 18:6a4db94011d3 600 SPI_WRITE_TX(spi_base, *((uint8_t *) tx));
sahilmgandhi 18:6a4db94011d3 601 tx += 1;
sahilmgandhi 18:6a4db94011d3 602 break;
sahilmgandhi 18:6a4db94011d3 603 }
sahilmgandhi 18:6a4db94011d3 604
sahilmgandhi 18:6a4db94011d3 605 obj->tx_buff.pos ++;
sahilmgandhi 18:6a4db94011d3 606 }
sahilmgandhi 18:6a4db94011d3 607 n_words ++;
sahilmgandhi 18:6a4db94011d3 608 }
sahilmgandhi 18:6a4db94011d3 609
sahilmgandhi 18:6a4db94011d3 610 //Return the number of words that have been sent
sahilmgandhi 18:6a4db94011d3 611 return n_words;
sahilmgandhi 18:6a4db94011d3 612 }
sahilmgandhi 18:6a4db94011d3 613
sahilmgandhi 18:6a4db94011d3 614 /**
sahilmgandhi 18:6a4db94011d3 615 * Read SPI words out of the RX FIFO
sahilmgandhi 18:6a4db94011d3 616 * Continues reading words out of the RX FIFO until the following condition is met:
sahilmgandhi 18:6a4db94011d3 617 * o There are no more words in the FIFO
sahilmgandhi 18:6a4db94011d3 618 * OR BOTH OF:
sahilmgandhi 18:6a4db94011d3 619 * o At least as many words as the TX buffer have been received
sahilmgandhi 18:6a4db94011d3 620 * o At least as many words as the RX buffer have been received
sahilmgandhi 18:6a4db94011d3 621 * This way, RX overflows are not generated when the TX buffer size exceeds the RX buffer size
sahilmgandhi 18:6a4db94011d3 622 * @param[in] obj The SPI object on which to operate
sahilmgandhi 18:6a4db94011d3 623 * @return Returns the number of words extracted from the RX FIFO
sahilmgandhi 18:6a4db94011d3 624 */
sahilmgandhi 18:6a4db94011d3 625 static uint32_t spi_master_read_asynch(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 626 {
sahilmgandhi 18:6a4db94011d3 627 uint32_t n_words = 0;
sahilmgandhi 18:6a4db94011d3 628 uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos;
sahilmgandhi 18:6a4db94011d3 629 uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos;
sahilmgandhi 18:6a4db94011d3 630 uint32_t max_rx = NU_MAX(tx_rmn, rx_rmn);
sahilmgandhi 18:6a4db94011d3 631 uint8_t data_width = spi_get_data_width(obj);
sahilmgandhi 18:6a4db94011d3 632 uint8_t bytes_per_word = (data_width + 7) / 8;
sahilmgandhi 18:6a4db94011d3 633 uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos;
sahilmgandhi 18:6a4db94011d3 634 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
sahilmgandhi 18:6a4db94011d3 635
sahilmgandhi 18:6a4db94011d3 636 while ((n_words < max_rx) && spi_readable(obj)) {
sahilmgandhi 18:6a4db94011d3 637 if (spi_is_rx_complete(obj)) {
sahilmgandhi 18:6a4db94011d3 638 // Disregard as receive buffer is full
sahilmgandhi 18:6a4db94011d3 639 SPI_READ_RX(spi_base);
sahilmgandhi 18:6a4db94011d3 640 }
sahilmgandhi 18:6a4db94011d3 641 else {
sahilmgandhi 18:6a4db94011d3 642 switch (bytes_per_word) {
sahilmgandhi 18:6a4db94011d3 643 case 4: {
sahilmgandhi 18:6a4db94011d3 644 uint32_t val = SPI_READ_RX(spi_base);
sahilmgandhi 18:6a4db94011d3 645 nu_set32_le(rx, val);
sahilmgandhi 18:6a4db94011d3 646 rx += 4;
sahilmgandhi 18:6a4db94011d3 647 break;
sahilmgandhi 18:6a4db94011d3 648 }
sahilmgandhi 18:6a4db94011d3 649 case 2: {
sahilmgandhi 18:6a4db94011d3 650 uint16_t val = SPI_READ_RX(spi_base);
sahilmgandhi 18:6a4db94011d3 651 nu_set16_le(rx, val);
sahilmgandhi 18:6a4db94011d3 652 rx += 2;
sahilmgandhi 18:6a4db94011d3 653 break;
sahilmgandhi 18:6a4db94011d3 654 }
sahilmgandhi 18:6a4db94011d3 655 case 1:
sahilmgandhi 18:6a4db94011d3 656 *rx ++ = SPI_READ_RX(spi_base);
sahilmgandhi 18:6a4db94011d3 657 break;
sahilmgandhi 18:6a4db94011d3 658 }
sahilmgandhi 18:6a4db94011d3 659
sahilmgandhi 18:6a4db94011d3 660 obj->rx_buff.pos ++;
sahilmgandhi 18:6a4db94011d3 661 }
sahilmgandhi 18:6a4db94011d3 662 n_words ++;
sahilmgandhi 18:6a4db94011d3 663 }
sahilmgandhi 18:6a4db94011d3 664
sahilmgandhi 18:6a4db94011d3 665 // Return the number of words received
sahilmgandhi 18:6a4db94011d3 666 return n_words;
sahilmgandhi 18:6a4db94011d3 667 }
sahilmgandhi 18:6a4db94011d3 668
sahilmgandhi 18:6a4db94011d3 669 static void spi_buffer_set(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length)
sahilmgandhi 18:6a4db94011d3 670 {
sahilmgandhi 18:6a4db94011d3 671 obj->tx_buff.buffer = (void *) tx;
sahilmgandhi 18:6a4db94011d3 672 obj->tx_buff.length = tx_length;
sahilmgandhi 18:6a4db94011d3 673 obj->tx_buff.pos = 0;
sahilmgandhi 18:6a4db94011d3 674 obj->tx_buff.width = spi_get_data_width(obj);
sahilmgandhi 18:6a4db94011d3 675 obj->rx_buff.buffer = rx;
sahilmgandhi 18:6a4db94011d3 676 obj->rx_buff.length = rx_length;
sahilmgandhi 18:6a4db94011d3 677 obj->rx_buff.pos = 0;
sahilmgandhi 18:6a4db94011d3 678 obj->rx_buff.width = spi_get_data_width(obj);
sahilmgandhi 18:6a4db94011d3 679 }
sahilmgandhi 18:6a4db94011d3 680
sahilmgandhi 18:6a4db94011d3 681 static void spi_check_dma_usage(DMAUsage *dma_usage, int *dma_ch_tx, int *dma_ch_rx)
sahilmgandhi 18:6a4db94011d3 682 {
sahilmgandhi 18:6a4db94011d3 683 if (*dma_usage != DMA_USAGE_NEVER) {
sahilmgandhi 18:6a4db94011d3 684 if (*dma_ch_tx == DMA_ERROR_OUT_OF_CHANNELS) {
sahilmgandhi 18:6a4db94011d3 685 *dma_ch_tx = dma_channel_allocate(DMA_CAP_NONE);
sahilmgandhi 18:6a4db94011d3 686 }
sahilmgandhi 18:6a4db94011d3 687 if (*dma_ch_rx == DMA_ERROR_OUT_OF_CHANNELS) {
sahilmgandhi 18:6a4db94011d3 688 *dma_ch_rx = dma_channel_allocate(DMA_CAP_NONE);
sahilmgandhi 18:6a4db94011d3 689 }
sahilmgandhi 18:6a4db94011d3 690
sahilmgandhi 18:6a4db94011d3 691 if (*dma_ch_tx == DMA_ERROR_OUT_OF_CHANNELS || *dma_ch_rx == DMA_ERROR_OUT_OF_CHANNELS) {
sahilmgandhi 18:6a4db94011d3 692 *dma_usage = DMA_USAGE_NEVER;
sahilmgandhi 18:6a4db94011d3 693 }
sahilmgandhi 18:6a4db94011d3 694 }
sahilmgandhi 18:6a4db94011d3 695
sahilmgandhi 18:6a4db94011d3 696 if (*dma_usage == DMA_USAGE_NEVER) {
sahilmgandhi 18:6a4db94011d3 697 dma_channel_free(*dma_ch_tx);
sahilmgandhi 18:6a4db94011d3 698 *dma_ch_tx = DMA_ERROR_OUT_OF_CHANNELS;
sahilmgandhi 18:6a4db94011d3 699 dma_channel_free(*dma_ch_rx);
sahilmgandhi 18:6a4db94011d3 700 *dma_ch_rx = DMA_ERROR_OUT_OF_CHANNELS;
sahilmgandhi 18:6a4db94011d3 701 }
sahilmgandhi 18:6a4db94011d3 702 }
sahilmgandhi 18:6a4db94011d3 703
sahilmgandhi 18:6a4db94011d3 704 static uint8_t spi_get_data_width(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 705 {
sahilmgandhi 18:6a4db94011d3 706 SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
sahilmgandhi 18:6a4db94011d3 707
sahilmgandhi 18:6a4db94011d3 708 uint32_t data_width = ((spi_base->CTL & SPI_CTL_DWIDTH_Msk) >> SPI_CTL_DWIDTH_Pos);
sahilmgandhi 18:6a4db94011d3 709 if (data_width == 0) {
sahilmgandhi 18:6a4db94011d3 710 data_width = 32;
sahilmgandhi 18:6a4db94011d3 711 }
sahilmgandhi 18:6a4db94011d3 712
sahilmgandhi 18:6a4db94011d3 713 return data_width;
sahilmgandhi 18:6a4db94011d3 714 }
sahilmgandhi 18:6a4db94011d3 715
sahilmgandhi 18:6a4db94011d3 716 static int spi_is_tx_complete(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 717 {
sahilmgandhi 18:6a4db94011d3 718 // ???: Exclude tx fifo empty check due to no such interrupt on DMA way
sahilmgandhi 18:6a4db94011d3 719 return (obj->tx_buff.pos == obj->tx_buff.length);
sahilmgandhi 18:6a4db94011d3 720 //return (obj->tx_buff.pos == obj->tx_buff.length && SPI_GET_TX_FIFO_EMPTY_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi))));
sahilmgandhi 18:6a4db94011d3 721 }
sahilmgandhi 18:6a4db94011d3 722
sahilmgandhi 18:6a4db94011d3 723 static int spi_is_rx_complete(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 724 {
sahilmgandhi 18:6a4db94011d3 725 return (obj->rx_buff.pos == obj->rx_buff.length);
sahilmgandhi 18:6a4db94011d3 726 }
sahilmgandhi 18:6a4db94011d3 727
sahilmgandhi 18:6a4db94011d3 728 static void spi_dma_handler_tx(uint32_t id, uint32_t event_dma)
sahilmgandhi 18:6a4db94011d3 729 {
sahilmgandhi 18:6a4db94011d3 730 spi_t *obj = (spi_t *) id;
sahilmgandhi 18:6a4db94011d3 731
sahilmgandhi 18:6a4db94011d3 732 // FIXME: Pass this error to caller
sahilmgandhi 18:6a4db94011d3 733 if (event_dma & DMA_EVENT_ABORT) {
sahilmgandhi 18:6a4db94011d3 734 }
sahilmgandhi 18:6a4db94011d3 735 // Expect SPI IRQ will catch this transfer done event
sahilmgandhi 18:6a4db94011d3 736 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
sahilmgandhi 18:6a4db94011d3 737 obj->tx_buff.pos = obj->tx_buff.length;
sahilmgandhi 18:6a4db94011d3 738 }
sahilmgandhi 18:6a4db94011d3 739 // FIXME: Pass this error to caller
sahilmgandhi 18:6a4db94011d3 740 if (event_dma & DMA_EVENT_TIMEOUT) {
sahilmgandhi 18:6a4db94011d3 741 }
sahilmgandhi 18:6a4db94011d3 742
sahilmgandhi 18:6a4db94011d3 743 const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
sahilmgandhi 18:6a4db94011d3 744 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 745 MBED_ASSERT(modinit->modname == obj->spi.spi);
sahilmgandhi 18:6a4db94011d3 746
sahilmgandhi 18:6a4db94011d3 747 void (*vec)(void) = (void (*)(void)) NVIC_GetVector(modinit->irq_n);
sahilmgandhi 18:6a4db94011d3 748 vec();
sahilmgandhi 18:6a4db94011d3 749 }
sahilmgandhi 18:6a4db94011d3 750
sahilmgandhi 18:6a4db94011d3 751 static void spi_dma_handler_rx(uint32_t id, uint32_t event_dma)
sahilmgandhi 18:6a4db94011d3 752 {
sahilmgandhi 18:6a4db94011d3 753 spi_t *obj = (spi_t *) id;
sahilmgandhi 18:6a4db94011d3 754
sahilmgandhi 18:6a4db94011d3 755 // FIXME: Pass this error to caller
sahilmgandhi 18:6a4db94011d3 756 if (event_dma & DMA_EVENT_ABORT) {
sahilmgandhi 18:6a4db94011d3 757 }
sahilmgandhi 18:6a4db94011d3 758 // Expect SPI IRQ will catch this transfer done event
sahilmgandhi 18:6a4db94011d3 759 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
sahilmgandhi 18:6a4db94011d3 760 obj->rx_buff.pos = obj->rx_buff.length;
sahilmgandhi 18:6a4db94011d3 761 }
sahilmgandhi 18:6a4db94011d3 762 // FIXME: Pass this error to caller
sahilmgandhi 18:6a4db94011d3 763 if (event_dma & DMA_EVENT_TIMEOUT) {
sahilmgandhi 18:6a4db94011d3 764 }
sahilmgandhi 18:6a4db94011d3 765
sahilmgandhi 18:6a4db94011d3 766 const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
sahilmgandhi 18:6a4db94011d3 767 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 768 MBED_ASSERT(modinit->modname == obj->spi.spi);
sahilmgandhi 18:6a4db94011d3 769
sahilmgandhi 18:6a4db94011d3 770 void (*vec)(void) = (void (*)(void)) NVIC_GetVector(modinit->irq_n);
sahilmgandhi 18:6a4db94011d3 771 vec();
sahilmgandhi 18:6a4db94011d3 772 }
sahilmgandhi 18:6a4db94011d3 773
sahilmgandhi 18:6a4db94011d3 774 #endif
sahilmgandhi 18:6a4db94011d3 775
sahilmgandhi 18:6a4db94011d3 776 #endif