MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2015-2016 Nuvoton
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16
sahilmgandhi 18:6a4db94011d3 17 #include "lp_ticker_api.h"
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 #if DEVICE_LOWPOWERTIMER
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21 #include "sleep_api.h"
sahilmgandhi 18:6a4db94011d3 22 #include "nu_modutil.h"
sahilmgandhi 18:6a4db94011d3 23 #include "nu_miscutil.h"
sahilmgandhi 18:6a4db94011d3 24 #include "mbed_critical.h"
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 // lp_ticker tick = us = timestamp
sahilmgandhi 18:6a4db94011d3 27 #define US_PER_TICK (1)
sahilmgandhi 18:6a4db94011d3 28 #define US_PER_SEC (1000 * 1000)
sahilmgandhi 18:6a4db94011d3 29
sahilmgandhi 18:6a4db94011d3 30 #define US_PER_TMR2_INT (US_PER_SEC * 10)
sahilmgandhi 18:6a4db94011d3 31 #define TMR2_CLK_PER_SEC (__LXT)
sahilmgandhi 18:6a4db94011d3 32 #define TMR2_CLK_PER_TMR2_INT ((uint32_t) ((uint64_t) US_PER_TMR2_INT * TMR2_CLK_PER_SEC / US_PER_SEC))
sahilmgandhi 18:6a4db94011d3 33 #define TMR3_CLK_PER_SEC (__LXT)
sahilmgandhi 18:6a4db94011d3 34
sahilmgandhi 18:6a4db94011d3 35 static void tmr2_vec(void);
sahilmgandhi 18:6a4db94011d3 36 static void tmr3_vec(void);
sahilmgandhi 18:6a4db94011d3 37 static void lp_ticker_arm_cd(void);
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 static int lp_ticker_inited = 0;
sahilmgandhi 18:6a4db94011d3 40 static volatile uint32_t counter_major = 0;
sahilmgandhi 18:6a4db94011d3 41 static volatile uint32_t cd_major_minor_clks = 0;
sahilmgandhi 18:6a4db94011d3 42 static volatile uint32_t cd_minor_clks = 0;
sahilmgandhi 18:6a4db94011d3 43 static volatile uint32_t wakeup_tick = (uint32_t) -1;
sahilmgandhi 18:6a4db94011d3 44
sahilmgandhi 18:6a4db94011d3 45 // NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC.
sahilmgandhi 18:6a4db94011d3 46 // NOTE: TIMER_2 for normal counting and TIMER_3 for scheduled wakeup
sahilmgandhi 18:6a4db94011d3 47 static const struct nu_modinit_s timer2_modinit = {TIMER_2, TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_LXT, 0, TMR2_RST, TMR2_IRQn, (void *) tmr2_vec};
sahilmgandhi 18:6a4db94011d3 48 static const struct nu_modinit_s timer3_modinit = {TIMER_3, TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_LXT, 0, TMR3_RST, TMR3_IRQn, (void *) tmr3_vec};
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 #define TMR_CMP_MIN 2
sahilmgandhi 18:6a4db94011d3 51 #define TMR_CMP_MAX 0xFFFFFFu
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 void lp_ticker_init(void)
sahilmgandhi 18:6a4db94011d3 54 {
sahilmgandhi 18:6a4db94011d3 55 if (lp_ticker_inited) {
sahilmgandhi 18:6a4db94011d3 56 return;
sahilmgandhi 18:6a4db94011d3 57 }
sahilmgandhi 18:6a4db94011d3 58 lp_ticker_inited = 1;
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 counter_major = 0;
sahilmgandhi 18:6a4db94011d3 61 cd_major_minor_clks = 0;
sahilmgandhi 18:6a4db94011d3 62 cd_minor_clks = 0;
sahilmgandhi 18:6a4db94011d3 63 wakeup_tick = (uint32_t) -1;
sahilmgandhi 18:6a4db94011d3 64
sahilmgandhi 18:6a4db94011d3 65 // Reset module
sahilmgandhi 18:6a4db94011d3 66 SYS_ResetModule(timer2_modinit.rsetidx);
sahilmgandhi 18:6a4db94011d3 67 SYS_ResetModule(timer3_modinit.rsetidx);
sahilmgandhi 18:6a4db94011d3 68
sahilmgandhi 18:6a4db94011d3 69 // Select IP clock source
sahilmgandhi 18:6a4db94011d3 70 CLK_SetModuleClock(timer2_modinit.clkidx, timer2_modinit.clksrc, timer2_modinit.clkdiv);
sahilmgandhi 18:6a4db94011d3 71 CLK_SetModuleClock(timer3_modinit.clkidx, timer3_modinit.clksrc, timer3_modinit.clkdiv);
sahilmgandhi 18:6a4db94011d3 72 // Enable IP clock
sahilmgandhi 18:6a4db94011d3 73 CLK_EnableModuleClock(timer2_modinit.clkidx);
sahilmgandhi 18:6a4db94011d3 74 CLK_EnableModuleClock(timer3_modinit.clkidx);
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76 // Configure clock
sahilmgandhi 18:6a4db94011d3 77 uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
sahilmgandhi 18:6a4db94011d3 78 uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_PER_SEC - 1;
sahilmgandhi 18:6a4db94011d3 79 MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127);
sahilmgandhi 18:6a4db94011d3 80 MBED_ASSERT((clk_timer2 % TMR2_CLK_PER_SEC) == 0);
sahilmgandhi 18:6a4db94011d3 81 uint32_t cmp_timer2 = TMR2_CLK_PER_TMR2_INT;
sahilmgandhi 18:6a4db94011d3 82 MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX);
sahilmgandhi 18:6a4db94011d3 83 // Continuous mode
sahilmgandhi 18:6a4db94011d3 84 ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer2 | TIMER_CTL_CNTDATEN_Msk;
sahilmgandhi 18:6a4db94011d3 85 ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CMP = cmp_timer2;
sahilmgandhi 18:6a4db94011d3 86
sahilmgandhi 18:6a4db94011d3 87 // Set vector
sahilmgandhi 18:6a4db94011d3 88 NVIC_SetVector(timer2_modinit.irq_n, (uint32_t) timer2_modinit.var);
sahilmgandhi 18:6a4db94011d3 89 NVIC_SetVector(timer3_modinit.irq_n, (uint32_t) timer3_modinit.var);
sahilmgandhi 18:6a4db94011d3 90
sahilmgandhi 18:6a4db94011d3 91 NVIC_EnableIRQ(timer2_modinit.irq_n);
sahilmgandhi 18:6a4db94011d3 92 NVIC_EnableIRQ(timer3_modinit.irq_n);
sahilmgandhi 18:6a4db94011d3 93
sahilmgandhi 18:6a4db94011d3 94 TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
sahilmgandhi 18:6a4db94011d3 95 TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
sahilmgandhi 18:6a4db94011d3 96
sahilmgandhi 18:6a4db94011d3 97 // NOTE: TIMER_Start() first and then lp_ticker_set_interrupt(); otherwise, we may get stuck in lp_ticker_read() because
sahilmgandhi 18:6a4db94011d3 98 // timer is not running.
sahilmgandhi 18:6a4db94011d3 99
sahilmgandhi 18:6a4db94011d3 100 // Start timer
sahilmgandhi 18:6a4db94011d3 101 TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
sahilmgandhi 18:6a4db94011d3 102
sahilmgandhi 18:6a4db94011d3 103 // Schedule wakeup to match semantics of lp_ticker_get_compare_match()
sahilmgandhi 18:6a4db94011d3 104 lp_ticker_set_interrupt(wakeup_tick);
sahilmgandhi 18:6a4db94011d3 105 }
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107 timestamp_t lp_ticker_read()
sahilmgandhi 18:6a4db94011d3 108 {
sahilmgandhi 18:6a4db94011d3 109 if (! lp_ticker_inited) {
sahilmgandhi 18:6a4db94011d3 110 lp_ticker_init();
sahilmgandhi 18:6a4db94011d3 111 }
sahilmgandhi 18:6a4db94011d3 112
sahilmgandhi 18:6a4db94011d3 113 TIMER_T * timer2_base = (TIMER_T *) NU_MODBASE(timer2_modinit.modname);
sahilmgandhi 18:6a4db94011d3 114
sahilmgandhi 18:6a4db94011d3 115 do {
sahilmgandhi 18:6a4db94011d3 116 uint64_t major_minor_clks;
sahilmgandhi 18:6a4db94011d3 117 uint32_t minor_clks;
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 // NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time.
sahilmgandhi 18:6a4db94011d3 120 // NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read.
sahilmgandhi 18:6a4db94011d3 121 do {
sahilmgandhi 18:6a4db94011d3 122 core_util_critical_section_enter();
sahilmgandhi 18:6a4db94011d3 123
sahilmgandhi 18:6a4db94011d3 124 // NOTE: Order of reading minor_us/carry here is significant.
sahilmgandhi 18:6a4db94011d3 125 minor_clks = TIMER_GetCounter(timer2_base);
sahilmgandhi 18:6a4db94011d3 126 uint32_t carry = (timer2_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0;
sahilmgandhi 18:6a4db94011d3 127 // When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
sahilmgandhi 18:6a4db94011d3 128 if (carry && minor_clks > (TMR2_CLK_PER_TMR2_INT / 2)) {
sahilmgandhi 18:6a4db94011d3 129 major_minor_clks = (counter_major + 1) * TMR2_CLK_PER_TMR2_INT;
sahilmgandhi 18:6a4db94011d3 130 }
sahilmgandhi 18:6a4db94011d3 131 else {
sahilmgandhi 18:6a4db94011d3 132 major_minor_clks = (counter_major + carry) * TMR2_CLK_PER_TMR2_INT + minor_clks;
sahilmgandhi 18:6a4db94011d3 133 }
sahilmgandhi 18:6a4db94011d3 134
sahilmgandhi 18:6a4db94011d3 135 core_util_critical_section_exit();
sahilmgandhi 18:6a4db94011d3 136 }
sahilmgandhi 18:6a4db94011d3 137 while (minor_clks == 0 || minor_clks == TMR2_CLK_PER_TMR2_INT);
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139 // Add power-down compensation
sahilmgandhi 18:6a4db94011d3 140 return ((uint64_t) major_minor_clks * US_PER_SEC / TMR3_CLK_PER_SEC / US_PER_TICK);
sahilmgandhi 18:6a4db94011d3 141 }
sahilmgandhi 18:6a4db94011d3 142 while (0);
sahilmgandhi 18:6a4db94011d3 143 }
sahilmgandhi 18:6a4db94011d3 144
sahilmgandhi 18:6a4db94011d3 145 void lp_ticker_set_interrupt(timestamp_t timestamp)
sahilmgandhi 18:6a4db94011d3 146 {
sahilmgandhi 18:6a4db94011d3 147 uint32_t now = lp_ticker_read();
sahilmgandhi 18:6a4db94011d3 148 wakeup_tick = timestamp;
sahilmgandhi 18:6a4db94011d3 149
sahilmgandhi 18:6a4db94011d3 150 TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
sahilmgandhi 18:6a4db94011d3 151
sahilmgandhi 18:6a4db94011d3 152 /**
sahilmgandhi 18:6a4db94011d3 153 * FIXME: Scheduled alarm may go off incorrectly due to wrap around.
sahilmgandhi 18:6a4db94011d3 154 * Conditions in which delta is negative:
sahilmgandhi 18:6a4db94011d3 155 * 1. Wrap around
sahilmgandhi 18:6a4db94011d3 156 * 2. Newly scheduled alarm is behind now
sahilmgandhi 18:6a4db94011d3 157 */
sahilmgandhi 18:6a4db94011d3 158 //int delta = (timestamp > now) ? (timestamp - now) : (uint32_t) ((uint64_t) timestamp + 0xFFFFFFFFu - now);
sahilmgandhi 18:6a4db94011d3 159 int delta = (int) (timestamp - now);
sahilmgandhi 18:6a4db94011d3 160 if (delta > 0) {
sahilmgandhi 18:6a4db94011d3 161 cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
sahilmgandhi 18:6a4db94011d3 162 lp_ticker_arm_cd();
sahilmgandhi 18:6a4db94011d3 163 }
sahilmgandhi 18:6a4db94011d3 164 else {
sahilmgandhi 18:6a4db94011d3 165 cd_major_minor_clks = cd_minor_clks = 0;
sahilmgandhi 18:6a4db94011d3 166 /**
sahilmgandhi 18:6a4db94011d3 167 * This event was in the past. Set the interrupt as pending, but don't process it here.
sahilmgandhi 18:6a4db94011d3 168 * This prevents a recurive loop under heavy load which can lead to a stack overflow.
sahilmgandhi 18:6a4db94011d3 169 */
sahilmgandhi 18:6a4db94011d3 170 NVIC_SetPendingIRQ(timer3_modinit.irq_n);
sahilmgandhi 18:6a4db94011d3 171 }
sahilmgandhi 18:6a4db94011d3 172 }
sahilmgandhi 18:6a4db94011d3 173
sahilmgandhi 18:6a4db94011d3 174 void lp_ticker_disable_interrupt(void)
sahilmgandhi 18:6a4db94011d3 175 {
sahilmgandhi 18:6a4db94011d3 176 TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
sahilmgandhi 18:6a4db94011d3 177 }
sahilmgandhi 18:6a4db94011d3 178
sahilmgandhi 18:6a4db94011d3 179 void lp_ticker_clear_interrupt(void)
sahilmgandhi 18:6a4db94011d3 180 {
sahilmgandhi 18:6a4db94011d3 181 TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
sahilmgandhi 18:6a4db94011d3 182 }
sahilmgandhi 18:6a4db94011d3 183
sahilmgandhi 18:6a4db94011d3 184 static void tmr2_vec(void)
sahilmgandhi 18:6a4db94011d3 185 {
sahilmgandhi 18:6a4db94011d3 186 TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
sahilmgandhi 18:6a4db94011d3 187 TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
sahilmgandhi 18:6a4db94011d3 188 counter_major ++;
sahilmgandhi 18:6a4db94011d3 189 }
sahilmgandhi 18:6a4db94011d3 190
sahilmgandhi 18:6a4db94011d3 191 static void tmr3_vec(void)
sahilmgandhi 18:6a4db94011d3 192 {
sahilmgandhi 18:6a4db94011d3 193 TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
sahilmgandhi 18:6a4db94011d3 194 TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
sahilmgandhi 18:6a4db94011d3 195 cd_major_minor_clks = (cd_major_minor_clks > cd_minor_clks) ? (cd_major_minor_clks - cd_minor_clks) : 0;
sahilmgandhi 18:6a4db94011d3 196 if (cd_major_minor_clks == 0) {
sahilmgandhi 18:6a4db94011d3 197 // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
sahilmgandhi 18:6a4db94011d3 198 lp_ticker_irq_handler();
sahilmgandhi 18:6a4db94011d3 199 }
sahilmgandhi 18:6a4db94011d3 200 else {
sahilmgandhi 18:6a4db94011d3 201 lp_ticker_arm_cd();
sahilmgandhi 18:6a4db94011d3 202 }
sahilmgandhi 18:6a4db94011d3 203 }
sahilmgandhi 18:6a4db94011d3 204
sahilmgandhi 18:6a4db94011d3 205 static void lp_ticker_arm_cd(void)
sahilmgandhi 18:6a4db94011d3 206 {
sahilmgandhi 18:6a4db94011d3 207 TIMER_T * timer3_base = (TIMER_T *) NU_MODBASE(timer3_modinit.modname);
sahilmgandhi 18:6a4db94011d3 208
sahilmgandhi 18:6a4db94011d3 209 // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit
sahilmgandhi 18:6a4db94011d3 210 timer3_base->CTL |= TIMER_CTL_RSTCNT_Msk;
sahilmgandhi 18:6a4db94011d3 211 // One-shot mode, Clock = 1 KHz
sahilmgandhi 18:6a4db94011d3 212 uint32_t clk_timer3 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
sahilmgandhi 18:6a4db94011d3 213 uint32_t prescale_timer3 = clk_timer3 / TMR3_CLK_PER_SEC - 1;
sahilmgandhi 18:6a4db94011d3 214 MBED_ASSERT((prescale_timer3 != (uint32_t) -1) && prescale_timer3 <= 127);
sahilmgandhi 18:6a4db94011d3 215 MBED_ASSERT((clk_timer3 % TMR3_CLK_PER_SEC) == 0);
sahilmgandhi 18:6a4db94011d3 216 timer3_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk | TIMER_CTL_CNTDATEN_Msk);
sahilmgandhi 18:6a4db94011d3 217 timer3_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer3 | TIMER_CTL_CNTDATEN_Msk;
sahilmgandhi 18:6a4db94011d3 218
sahilmgandhi 18:6a4db94011d3 219 cd_minor_clks = cd_major_minor_clks;
sahilmgandhi 18:6a4db94011d3 220 cd_minor_clks = NU_CLAMP(cd_minor_clks, TMR_CMP_MIN, TMR_CMP_MAX);
sahilmgandhi 18:6a4db94011d3 221 timer3_base->CMP = cd_minor_clks;
sahilmgandhi 18:6a4db94011d3 222
sahilmgandhi 18:6a4db94011d3 223 TIMER_EnableInt(timer3_base);
sahilmgandhi 18:6a4db94011d3 224 TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
sahilmgandhi 18:6a4db94011d3 225 TIMER_Start(timer3_base);
sahilmgandhi 18:6a4db94011d3 226 }
sahilmgandhi 18:6a4db94011d3 227 #endif