MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NUVOTON/TARGET_NUC472/gpio_irq_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2015-2016 Nuvoton
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16
sahilmgandhi 18:6a4db94011d3 17 #include "gpio_irq_api.h"
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 #if DEVICE_INTERRUPTIN
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21 #include "gpio_api.h"
sahilmgandhi 18:6a4db94011d3 22 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 23 #include "pinmap.h"
sahilmgandhi 18:6a4db94011d3 24 #include "PeripheralPins.h"
sahilmgandhi 18:6a4db94011d3 25 #include "nu_bitutil.h"
sahilmgandhi 18:6a4db94011d3 26
sahilmgandhi 18:6a4db94011d3 27 #define NU_MAX_PIN_PER_PORT 16
sahilmgandhi 18:6a4db94011d3 28
sahilmgandhi 18:6a4db94011d3 29 struct nu_gpio_irq_var {
sahilmgandhi 18:6a4db94011d3 30 gpio_irq_t * obj_arr[NU_MAX_PIN_PER_PORT];
sahilmgandhi 18:6a4db94011d3 31 IRQn_Type irq_n;
sahilmgandhi 18:6a4db94011d3 32 void (*vec)(void);
sahilmgandhi 18:6a4db94011d3 33 };
sahilmgandhi 18:6a4db94011d3 34
sahilmgandhi 18:6a4db94011d3 35 static void gpio_irq_0_vec(void);
sahilmgandhi 18:6a4db94011d3 36 static void gpio_irq_1_vec(void);
sahilmgandhi 18:6a4db94011d3 37 static void gpio_irq_2_vec(void);
sahilmgandhi 18:6a4db94011d3 38 static void gpio_irq_3_vec(void);
sahilmgandhi 18:6a4db94011d3 39 static void gpio_irq_4_vec(void);
sahilmgandhi 18:6a4db94011d3 40 static void gpio_irq_5_vec(void);
sahilmgandhi 18:6a4db94011d3 41 static void gpio_irq_6_vec(void);
sahilmgandhi 18:6a4db94011d3 42 static void gpio_irq_7_vec(void);
sahilmgandhi 18:6a4db94011d3 43 static void gpio_irq_8_vec(void);
sahilmgandhi 18:6a4db94011d3 44 static void gpio_irq(struct nu_gpio_irq_var *var);
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 //EINT0_IRQn
sahilmgandhi 18:6a4db94011d3 47 static struct nu_gpio_irq_var gpio_irq_var_arr[] = {
sahilmgandhi 18:6a4db94011d3 48 {{NULL}, GPA_IRQn, gpio_irq_0_vec},
sahilmgandhi 18:6a4db94011d3 49 {{NULL}, GPB_IRQn, gpio_irq_1_vec},
sahilmgandhi 18:6a4db94011d3 50 {{NULL}, GPC_IRQn, gpio_irq_2_vec},
sahilmgandhi 18:6a4db94011d3 51 {{NULL}, GPD_IRQn, gpio_irq_3_vec},
sahilmgandhi 18:6a4db94011d3 52 {{NULL}, GPE_IRQn, gpio_irq_4_vec},
sahilmgandhi 18:6a4db94011d3 53 {{NULL}, GPF_IRQn, gpio_irq_5_vec},
sahilmgandhi 18:6a4db94011d3 54 {{NULL}, GPG_IRQn, gpio_irq_6_vec},
sahilmgandhi 18:6a4db94011d3 55 {{NULL}, GPH_IRQn, gpio_irq_7_vec},
sahilmgandhi 18:6a4db94011d3 56 {{NULL}, GPI_IRQn, gpio_irq_8_vec}
sahilmgandhi 18:6a4db94011d3 57 };
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 #define NU_MAX_PORT (sizeof (gpio_irq_var_arr) / sizeof (gpio_irq_var_arr[0]))
sahilmgandhi 18:6a4db94011d3 60
sahilmgandhi 18:6a4db94011d3 61 #ifndef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE
sahilmgandhi 18:6a4db94011d3 62 #define MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE 0
sahilmgandhi 18:6a4db94011d3 63 #endif
sahilmgandhi 18:6a4db94011d3 64
sahilmgandhi 18:6a4db94011d3 65 #ifndef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
sahilmgandhi 18:6a4db94011d3 66 #define MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE_LIST NC
sahilmgandhi 18:6a4db94011d3 67 #endif
sahilmgandhi 18:6a4db94011d3 68 static PinName gpio_irq_debounce_arr[] = {
sahilmgandhi 18:6a4db94011d3 69 MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
sahilmgandhi 18:6a4db94011d3 70 };
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72 #ifndef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
sahilmgandhi 18:6a4db94011d3 73 #define MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_IRC10K
sahilmgandhi 18:6a4db94011d3 74 #endif
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76 #ifndef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
sahilmgandhi 18:6a4db94011d3 77 #define MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16
sahilmgandhi 18:6a4db94011d3 78 #endif
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
sahilmgandhi 18:6a4db94011d3 81 {
sahilmgandhi 18:6a4db94011d3 82 if (pin == NC) {
sahilmgandhi 18:6a4db94011d3 83 return -1;
sahilmgandhi 18:6a4db94011d3 84 }
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
sahilmgandhi 18:6a4db94011d3 87 uint32_t port_index = NU_PINNAME_TO_PORT(pin);
sahilmgandhi 18:6a4db94011d3 88 if (pin_index >= NU_MAX_PIN_PER_PORT || port_index >= NU_MAX_PORT) {
sahilmgandhi 18:6a4db94011d3 89 return -1;
sahilmgandhi 18:6a4db94011d3 90 }
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92 obj->pin = pin;
sahilmgandhi 18:6a4db94011d3 93 obj->irq_handler = (uint32_t) handler;
sahilmgandhi 18:6a4db94011d3 94 obj->irq_id = id;
sahilmgandhi 18:6a4db94011d3 95
sahilmgandhi 18:6a4db94011d3 96 GPIO_T *gpio_base = NU_PORT_BASE(port_index);
sahilmgandhi 18:6a4db94011d3 97 //gpio_set(pin);
sahilmgandhi 18:6a4db94011d3 98
sahilmgandhi 18:6a4db94011d3 99 {
sahilmgandhi 18:6a4db94011d3 100 #if MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE
sahilmgandhi 18:6a4db94011d3 101 // Suppress compiler warning
sahilmgandhi 18:6a4db94011d3 102 (void) gpio_irq_debounce_arr;
sahilmgandhi 18:6a4db94011d3 103
sahilmgandhi 18:6a4db94011d3 104 // Configure de-bounce clock source and sampling cycle time
sahilmgandhi 18:6a4db94011d3 105 GPIO_SET_DEBOUNCE_TIME(MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
sahilmgandhi 18:6a4db94011d3 106 GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
sahilmgandhi 18:6a4db94011d3 107 #else
sahilmgandhi 18:6a4db94011d3 108 // Enable de-bounce if the pin is in the de-bounce enable list
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 // De-bounce defaults to disabled.
sahilmgandhi 18:6a4db94011d3 111 GPIO_DISABLE_DEBOUNCE(gpio_base, 1 << pin_index);
sahilmgandhi 18:6a4db94011d3 112
sahilmgandhi 18:6a4db94011d3 113 PinName *debounce_pos = gpio_irq_debounce_arr;
sahilmgandhi 18:6a4db94011d3 114 PinName *debounce_end = gpio_irq_debounce_arr + sizeof (gpio_irq_debounce_arr) / sizeof (gpio_irq_debounce_arr[0]);
sahilmgandhi 18:6a4db94011d3 115 for (; debounce_pos != debounce_end && *debounce_pos != NC; debounce_pos ++) {
sahilmgandhi 18:6a4db94011d3 116 uint32_t pin_index_debunce = NU_PINNAME_TO_PIN(*debounce_pos);
sahilmgandhi 18:6a4db94011d3 117 uint32_t port_index_debounce = NU_PINNAME_TO_PORT(*debounce_pos);
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 if (pin_index == pin_index_debunce &&
sahilmgandhi 18:6a4db94011d3 120 port_index == port_index_debounce) {
sahilmgandhi 18:6a4db94011d3 121 // Configure de-bounce clock source and sampling cycle time
sahilmgandhi 18:6a4db94011d3 122 GPIO_SET_DEBOUNCE_TIME(MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
sahilmgandhi 18:6a4db94011d3 123 GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
sahilmgandhi 18:6a4db94011d3 124 break;
sahilmgandhi 18:6a4db94011d3 125 }
sahilmgandhi 18:6a4db94011d3 126 }
sahilmgandhi 18:6a4db94011d3 127 #endif
sahilmgandhi 18:6a4db94011d3 128 }
sahilmgandhi 18:6a4db94011d3 129
sahilmgandhi 18:6a4db94011d3 130 struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132 var->obj_arr[pin_index] = obj;
sahilmgandhi 18:6a4db94011d3 133
sahilmgandhi 18:6a4db94011d3 134 // NOTE: InterruptIn requires IRQ enabled by default.
sahilmgandhi 18:6a4db94011d3 135 gpio_irq_enable(obj);
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137 return 0;
sahilmgandhi 18:6a4db94011d3 138 }
sahilmgandhi 18:6a4db94011d3 139
sahilmgandhi 18:6a4db94011d3 140 void gpio_irq_free(gpio_irq_t *obj)
sahilmgandhi 18:6a4db94011d3 141 {
sahilmgandhi 18:6a4db94011d3 142 uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
sahilmgandhi 18:6a4db94011d3 143 uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
sahilmgandhi 18:6a4db94011d3 144 struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
sahilmgandhi 18:6a4db94011d3 145
sahilmgandhi 18:6a4db94011d3 146 NVIC_DisableIRQ(var->irq_n);
sahilmgandhi 18:6a4db94011d3 147 NU_PORT_BASE(port_index)->INTEN = 0;
sahilmgandhi 18:6a4db94011d3 148
sahilmgandhi 18:6a4db94011d3 149 MBED_ASSERT(pin_index < NU_MAX_PIN_PER_PORT);
sahilmgandhi 18:6a4db94011d3 150 var->obj_arr[pin_index] = NULL;
sahilmgandhi 18:6a4db94011d3 151 }
sahilmgandhi 18:6a4db94011d3 152
sahilmgandhi 18:6a4db94011d3 153 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
sahilmgandhi 18:6a4db94011d3 154 {
sahilmgandhi 18:6a4db94011d3 155 uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
sahilmgandhi 18:6a4db94011d3 156 uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
sahilmgandhi 18:6a4db94011d3 157 GPIO_T *gpio_base = NU_PORT_BASE(port_index);
sahilmgandhi 18:6a4db94011d3 158
sahilmgandhi 18:6a4db94011d3 159 switch (event) {
sahilmgandhi 18:6a4db94011d3 160 case IRQ_RISE:
sahilmgandhi 18:6a4db94011d3 161 if (enable) {
sahilmgandhi 18:6a4db94011d3 162 GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_RISING);
sahilmgandhi 18:6a4db94011d3 163 }
sahilmgandhi 18:6a4db94011d3 164 else {
sahilmgandhi 18:6a4db94011d3 165 gpio_base->INTEN &= ~(GPIO_INT_RISING << pin_index);
sahilmgandhi 18:6a4db94011d3 166 }
sahilmgandhi 18:6a4db94011d3 167 break;
sahilmgandhi 18:6a4db94011d3 168
sahilmgandhi 18:6a4db94011d3 169 case IRQ_FALL:
sahilmgandhi 18:6a4db94011d3 170 if (enable) {
sahilmgandhi 18:6a4db94011d3 171 GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_FALLING);
sahilmgandhi 18:6a4db94011d3 172 }
sahilmgandhi 18:6a4db94011d3 173 else {
sahilmgandhi 18:6a4db94011d3 174 gpio_base->INTEN &= ~(GPIO_INT_FALLING << pin_index);
sahilmgandhi 18:6a4db94011d3 175 }
sahilmgandhi 18:6a4db94011d3 176 break;
sahilmgandhi 18:6a4db94011d3 177 }
sahilmgandhi 18:6a4db94011d3 178 }
sahilmgandhi 18:6a4db94011d3 179
sahilmgandhi 18:6a4db94011d3 180 void gpio_irq_enable(gpio_irq_t *obj)
sahilmgandhi 18:6a4db94011d3 181 {
sahilmgandhi 18:6a4db94011d3 182 //uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
sahilmgandhi 18:6a4db94011d3 183 uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
sahilmgandhi 18:6a4db94011d3 184 struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
sahilmgandhi 18:6a4db94011d3 185
sahilmgandhi 18:6a4db94011d3 186 NVIC_SetVector(var->irq_n, (uint32_t) var->vec);
sahilmgandhi 18:6a4db94011d3 187 NVIC_EnableIRQ(var->irq_n);
sahilmgandhi 18:6a4db94011d3 188 }
sahilmgandhi 18:6a4db94011d3 189
sahilmgandhi 18:6a4db94011d3 190 void gpio_irq_disable(gpio_irq_t *obj)
sahilmgandhi 18:6a4db94011d3 191 {
sahilmgandhi 18:6a4db94011d3 192 //uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
sahilmgandhi 18:6a4db94011d3 193 uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
sahilmgandhi 18:6a4db94011d3 194 struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
sahilmgandhi 18:6a4db94011d3 195
sahilmgandhi 18:6a4db94011d3 196 NVIC_DisableIRQ(var->irq_n);
sahilmgandhi 18:6a4db94011d3 197 }
sahilmgandhi 18:6a4db94011d3 198
sahilmgandhi 18:6a4db94011d3 199 static void gpio_irq_0_vec(void)
sahilmgandhi 18:6a4db94011d3 200 {
sahilmgandhi 18:6a4db94011d3 201 gpio_irq(gpio_irq_var_arr + 0);
sahilmgandhi 18:6a4db94011d3 202 }
sahilmgandhi 18:6a4db94011d3 203 static void gpio_irq_1_vec(void)
sahilmgandhi 18:6a4db94011d3 204 {
sahilmgandhi 18:6a4db94011d3 205 gpio_irq(gpio_irq_var_arr + 1);
sahilmgandhi 18:6a4db94011d3 206 }
sahilmgandhi 18:6a4db94011d3 207 static void gpio_irq_2_vec(void)
sahilmgandhi 18:6a4db94011d3 208 {
sahilmgandhi 18:6a4db94011d3 209 gpio_irq(gpio_irq_var_arr + 2);
sahilmgandhi 18:6a4db94011d3 210 }
sahilmgandhi 18:6a4db94011d3 211 static void gpio_irq_3_vec(void)
sahilmgandhi 18:6a4db94011d3 212 {
sahilmgandhi 18:6a4db94011d3 213 gpio_irq(gpio_irq_var_arr + 3);
sahilmgandhi 18:6a4db94011d3 214 }
sahilmgandhi 18:6a4db94011d3 215 static void gpio_irq_4_vec(void)
sahilmgandhi 18:6a4db94011d3 216 {
sahilmgandhi 18:6a4db94011d3 217 gpio_irq(gpio_irq_var_arr + 4);
sahilmgandhi 18:6a4db94011d3 218 }
sahilmgandhi 18:6a4db94011d3 219 static void gpio_irq_5_vec(void)
sahilmgandhi 18:6a4db94011d3 220 {
sahilmgandhi 18:6a4db94011d3 221 gpio_irq(gpio_irq_var_arr + 5);
sahilmgandhi 18:6a4db94011d3 222 }
sahilmgandhi 18:6a4db94011d3 223 static void gpio_irq_6_vec(void)
sahilmgandhi 18:6a4db94011d3 224 {
sahilmgandhi 18:6a4db94011d3 225 gpio_irq(gpio_irq_var_arr + 6);
sahilmgandhi 18:6a4db94011d3 226 }
sahilmgandhi 18:6a4db94011d3 227 static void gpio_irq_7_vec(void)
sahilmgandhi 18:6a4db94011d3 228 {
sahilmgandhi 18:6a4db94011d3 229 gpio_irq(gpio_irq_var_arr + 7);
sahilmgandhi 18:6a4db94011d3 230 }
sahilmgandhi 18:6a4db94011d3 231 static void gpio_irq_8_vec(void)
sahilmgandhi 18:6a4db94011d3 232 {
sahilmgandhi 18:6a4db94011d3 233 gpio_irq(gpio_irq_var_arr + 8);
sahilmgandhi 18:6a4db94011d3 234 }
sahilmgandhi 18:6a4db94011d3 235
sahilmgandhi 18:6a4db94011d3 236 static void gpio_irq(struct nu_gpio_irq_var *var)
sahilmgandhi 18:6a4db94011d3 237 {
sahilmgandhi 18:6a4db94011d3 238 uint32_t port_index = var->irq_n - GPA_IRQn;
sahilmgandhi 18:6a4db94011d3 239 GPIO_T *gpio_base = NU_PORT_BASE(port_index);
sahilmgandhi 18:6a4db94011d3 240
sahilmgandhi 18:6a4db94011d3 241 uint32_t intsrc = gpio_base->INTSRC;
sahilmgandhi 18:6a4db94011d3 242 uint32_t inten = gpio_base->INTEN;
sahilmgandhi 18:6a4db94011d3 243 while (intsrc) {
sahilmgandhi 18:6a4db94011d3 244 int pin_index = nu_ctz(intsrc);
sahilmgandhi 18:6a4db94011d3 245 gpio_irq_t *obj = var->obj_arr[pin_index];
sahilmgandhi 18:6a4db94011d3 246 if (inten & (GPIO_INT_RISING << pin_index)) {
sahilmgandhi 18:6a4db94011d3 247 if (GPIO_PIN_ADDR(port_index, pin_index)) {
sahilmgandhi 18:6a4db94011d3 248 if (obj->irq_handler) {
sahilmgandhi 18:6a4db94011d3 249 ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_RISE);
sahilmgandhi 18:6a4db94011d3 250 }
sahilmgandhi 18:6a4db94011d3 251 }
sahilmgandhi 18:6a4db94011d3 252 }
sahilmgandhi 18:6a4db94011d3 253
sahilmgandhi 18:6a4db94011d3 254 if (inten & (GPIO_INT_FALLING << pin_index)) {
sahilmgandhi 18:6a4db94011d3 255 if (! GPIO_PIN_ADDR(port_index, pin_index)) {
sahilmgandhi 18:6a4db94011d3 256 if (obj->irq_handler) {
sahilmgandhi 18:6a4db94011d3 257 ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_FALL);
sahilmgandhi 18:6a4db94011d3 258 }
sahilmgandhi 18:6a4db94011d3 259 }
sahilmgandhi 18:6a4db94011d3 260 }
sahilmgandhi 18:6a4db94011d3 261
sahilmgandhi 18:6a4db94011d3 262 intsrc &= ~(1 << pin_index);
sahilmgandhi 18:6a4db94011d3 263 }
sahilmgandhi 18:6a4db94011d3 264 // Clear all interrupt flags
sahilmgandhi 18:6a4db94011d3 265 gpio_base->INTSRC = gpio_base->INTSRC;
sahilmgandhi 18:6a4db94011d3 266 }
sahilmgandhi 18:6a4db94011d3 267
sahilmgandhi 18:6a4db94011d3 268 #endif