MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_spi.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /****************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file spi.c
sahilmgandhi 18:6a4db94011d3 3 * @version V0.10
sahilmgandhi 18:6a4db94011d3 4 * $Revision: 15 $
sahilmgandhi 18:6a4db94011d3 5 * $Date: 14/09/30 1:10p $
sahilmgandhi 18:6a4db94011d3 6 * @brief NUC472/NUC442 SPI driver source file
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * @note
sahilmgandhi 18:6a4db94011d3 9 * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
sahilmgandhi 18:6a4db94011d3 10 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 11 #include "NUC472_442.h"
sahilmgandhi 18:6a4db94011d3 12
sahilmgandhi 18:6a4db94011d3 13 /** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
sahilmgandhi 18:6a4db94011d3 14 @{
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16
sahilmgandhi 18:6a4db94011d3 17 /** @addtogroup NUC472_442_SPI_Driver SPI Driver
sahilmgandhi 18:6a4db94011d3 18 @{
sahilmgandhi 18:6a4db94011d3 19 */
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21
sahilmgandhi 18:6a4db94011d3 22 /** @addtogroup NUC472_442_SPI_EXPORTED_FUNCTIONS SPI Exported Functions
sahilmgandhi 18:6a4db94011d3 23 @{
sahilmgandhi 18:6a4db94011d3 24 */
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 /**
sahilmgandhi 18:6a4db94011d3 27 * @brief This function make SPI module be ready to transfer.
sahilmgandhi 18:6a4db94011d3 28 * By default, the SPI transfer sequence is MSB first and
sahilmgandhi 18:6a4db94011d3 29 * the automatic slave select function is disabled. In
sahilmgandhi 18:6a4db94011d3 30 * Slave mode, the u32BusClock must be NULL and the SPI clock
sahilmgandhi 18:6a4db94011d3 31 * divider setting will be 0.
sahilmgandhi 18:6a4db94011d3 32 * @param[in] spi is the base address of SPI module.
sahilmgandhi 18:6a4db94011d3 33 * @param[in] u32MasterSlave decides the SPI module is operating in master mode or in slave mode. Valid values are:
sahilmgandhi 18:6a4db94011d3 34 * - \ref SPI_SLAVE
sahilmgandhi 18:6a4db94011d3 35 * - \ref SPI_MASTER
sahilmgandhi 18:6a4db94011d3 36 * @param[in] u32SPIMode decides the transfer timing. Valid values are:
sahilmgandhi 18:6a4db94011d3 37 * - \ref SPI_MODE_0
sahilmgandhi 18:6a4db94011d3 38 * - \ref SPI_MODE_1
sahilmgandhi 18:6a4db94011d3 39 * - \ref SPI_MODE_2
sahilmgandhi 18:6a4db94011d3 40 * - \ref SPI_MODE_3
sahilmgandhi 18:6a4db94011d3 41 * @param[in] u32DataWidth decides the data width of a SPI transaction.
sahilmgandhi 18:6a4db94011d3 42 * @param[in] u32BusClock is the expected frequency of SPI bus clock in Hz.
sahilmgandhi 18:6a4db94011d3 43 * @return Actual frequency of SPI peripheral clock.
sahilmgandhi 18:6a4db94011d3 44 */
sahilmgandhi 18:6a4db94011d3 45 uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
sahilmgandhi 18:6a4db94011d3 46 {
sahilmgandhi 18:6a4db94011d3 47 if(u32DataWidth == 32)
sahilmgandhi 18:6a4db94011d3 48 u32DataWidth = 0;
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode);
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 return ( SPI_SetBusClock(spi, u32BusClock) );
sahilmgandhi 18:6a4db94011d3 53 }
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 /**
sahilmgandhi 18:6a4db94011d3 56 * @brief Reset SPI module and disable SPI peripheral clock.
sahilmgandhi 18:6a4db94011d3 57 * @param[in] spi is the base address of SPI module.
sahilmgandhi 18:6a4db94011d3 58 * @return none
sahilmgandhi 18:6a4db94011d3 59 */
sahilmgandhi 18:6a4db94011d3 60 void SPI_Close(SPI_T *spi)
sahilmgandhi 18:6a4db94011d3 61 {
sahilmgandhi 18:6a4db94011d3 62 /* Reset SPI */
sahilmgandhi 18:6a4db94011d3 63 if((uint32_t)spi == SPI0_BASE) {
sahilmgandhi 18:6a4db94011d3 64 SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk;
sahilmgandhi 18:6a4db94011d3 65 SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk;
sahilmgandhi 18:6a4db94011d3 66 } else if((uint32_t)spi == SPI1_BASE) {
sahilmgandhi 18:6a4db94011d3 67 SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk;
sahilmgandhi 18:6a4db94011d3 68 SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk;
sahilmgandhi 18:6a4db94011d3 69 } else if((uint32_t)spi == SPI2_BASE) {
sahilmgandhi 18:6a4db94011d3 70 SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk;
sahilmgandhi 18:6a4db94011d3 71 SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk;
sahilmgandhi 18:6a4db94011d3 72 } else {
sahilmgandhi 18:6a4db94011d3 73 SYS->IPRST1 |= SYS_IPRST1_SPI3RST_Msk;
sahilmgandhi 18:6a4db94011d3 74 SYS->IPRST1 &= ~SYS_IPRST1_SPI3RST_Msk;
sahilmgandhi 18:6a4db94011d3 75 }
sahilmgandhi 18:6a4db94011d3 76 }
sahilmgandhi 18:6a4db94011d3 77
sahilmgandhi 18:6a4db94011d3 78 /**
sahilmgandhi 18:6a4db94011d3 79 * @brief Clear Rx FIFO buffer.
sahilmgandhi 18:6a4db94011d3 80 * @param[in] spi is the base address of SPI module.
sahilmgandhi 18:6a4db94011d3 81 * @return none
sahilmgandhi 18:6a4db94011d3 82 */
sahilmgandhi 18:6a4db94011d3 83 void SPI_ClearRxFIFO(SPI_T *spi)
sahilmgandhi 18:6a4db94011d3 84 {
sahilmgandhi 18:6a4db94011d3 85 spi->FIFOCTL |= SPI_FIFOCTL_RXRST_Msk;
sahilmgandhi 18:6a4db94011d3 86 }
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 /**
sahilmgandhi 18:6a4db94011d3 89 * @brief Clear Tx FIFO buffer.
sahilmgandhi 18:6a4db94011d3 90 * @param[in] spi is the base address of SPI module.
sahilmgandhi 18:6a4db94011d3 91 * @return none
sahilmgandhi 18:6a4db94011d3 92 */
sahilmgandhi 18:6a4db94011d3 93 void SPI_ClearTxFIFO(SPI_T *spi)
sahilmgandhi 18:6a4db94011d3 94 {
sahilmgandhi 18:6a4db94011d3 95 spi->FIFOCTL |= SPI_FIFOCTL_TXRST_Msk;
sahilmgandhi 18:6a4db94011d3 96 }
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 /**
sahilmgandhi 18:6a4db94011d3 99 * @brief Disable the automatic slave select function.
sahilmgandhi 18:6a4db94011d3 100 * @param[in] spi is the base address of SPI module.
sahilmgandhi 18:6a4db94011d3 101 * @return none
sahilmgandhi 18:6a4db94011d3 102 */
sahilmgandhi 18:6a4db94011d3 103 void SPI_DisableAutoSS(SPI_T *spi)
sahilmgandhi 18:6a4db94011d3 104 {
sahilmgandhi 18:6a4db94011d3 105 spi->SSCTL &= ~SPI_SSCTL_AUTOSS_Msk;
sahilmgandhi 18:6a4db94011d3 106 }
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 /**
sahilmgandhi 18:6a4db94011d3 109 * @brief Enable the automatic slave select function. Only available in Master mode.
sahilmgandhi 18:6a4db94011d3 110 * @param[in] spi is the base address of SPI module.
sahilmgandhi 18:6a4db94011d3 111 * @param[in] u32SSPinMask specifies slave select pins. Valid values are:
sahilmgandhi 18:6a4db94011d3 112 * - \ref SPI_SS0
sahilmgandhi 18:6a4db94011d3 113 * - \ref SPI_SS1
sahilmgandhi 18:6a4db94011d3 114 * @param[in] u32ActiveLevel specifies the active level of slave select signal. Valid values are:
sahilmgandhi 18:6a4db94011d3 115 * - \ref SPI_SS_ACTIVE_HIGH
sahilmgandhi 18:6a4db94011d3 116 * - \ref SPI_SS_ACTIVE_LOW
sahilmgandhi 18:6a4db94011d3 117 * @return none
sahilmgandhi 18:6a4db94011d3 118 */
sahilmgandhi 18:6a4db94011d3 119 void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
sahilmgandhi 18:6a4db94011d3 120 {
sahilmgandhi 18:6a4db94011d3 121 spi->SSCTL |= (u32SSPinMask | u32ActiveLevel) | SPI_SSCTL_AUTOSS_Msk;
sahilmgandhi 18:6a4db94011d3 122 }
sahilmgandhi 18:6a4db94011d3 123
sahilmgandhi 18:6a4db94011d3 124 /**
sahilmgandhi 18:6a4db94011d3 125 * @brief Set the SPI bus clock. Only available in Master mode.
sahilmgandhi 18:6a4db94011d3 126 * @param[in] spi is the base address of SPI module.
sahilmgandhi 18:6a4db94011d3 127 * @param[in] u32BusClock is the expected frequency of SPI bus clock.
sahilmgandhi 18:6a4db94011d3 128 * @return Actual frequency of SPI peripheral clock.
sahilmgandhi 18:6a4db94011d3 129 */
sahilmgandhi 18:6a4db94011d3 130 uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
sahilmgandhi 18:6a4db94011d3 131 {
sahilmgandhi 18:6a4db94011d3 132 uint32_t u32ClkSrc, u32Div = 0;
sahilmgandhi 18:6a4db94011d3 133
sahilmgandhi 18:6a4db94011d3 134 if(spi == SPI0) {
sahilmgandhi 18:6a4db94011d3 135 if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI0SEL_Msk) == CLK_CLKSEL1_SPI0SEL_PCLK)
sahilmgandhi 18:6a4db94011d3 136 u32ClkSrc = CLK_GetPCLKFreq();
sahilmgandhi 18:6a4db94011d3 137 else
sahilmgandhi 18:6a4db94011d3 138 u32ClkSrc = CLK_GetPLLClockFreq();
sahilmgandhi 18:6a4db94011d3 139 } else if(spi == SPI1) {
sahilmgandhi 18:6a4db94011d3 140 if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI1SEL_Msk) == CLK_CLKSEL1_SPI1SEL_PCLK)
sahilmgandhi 18:6a4db94011d3 141 u32ClkSrc = CLK_GetPCLKFreq();
sahilmgandhi 18:6a4db94011d3 142 else
sahilmgandhi 18:6a4db94011d3 143 u32ClkSrc = CLK_GetPLLClockFreq();
sahilmgandhi 18:6a4db94011d3 144 } else if(spi == SPI2) {
sahilmgandhi 18:6a4db94011d3 145 if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI1SEL_Msk) == CLK_CLKSEL1_SPI2SEL_PCLK)
sahilmgandhi 18:6a4db94011d3 146 u32ClkSrc = CLK_GetPCLKFreq();
sahilmgandhi 18:6a4db94011d3 147 else
sahilmgandhi 18:6a4db94011d3 148 u32ClkSrc = CLK_GetPLLClockFreq();
sahilmgandhi 18:6a4db94011d3 149 } else {
sahilmgandhi 18:6a4db94011d3 150 if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI3SEL_Msk) == CLK_CLKSEL1_SPI3SEL_PCLK)
sahilmgandhi 18:6a4db94011d3 151 u32ClkSrc = CLK_GetPCLKFreq();
sahilmgandhi 18:6a4db94011d3 152 else
sahilmgandhi 18:6a4db94011d3 153 u32ClkSrc = CLK_GetPLLClockFreq();
sahilmgandhi 18:6a4db94011d3 154 }
sahilmgandhi 18:6a4db94011d3 155
sahilmgandhi 18:6a4db94011d3 156
sahilmgandhi 18:6a4db94011d3 157 if(u32BusClock != 0 ) {
sahilmgandhi 18:6a4db94011d3 158 u32Div = (u32ClkSrc / u32BusClock) - 1;
sahilmgandhi 18:6a4db94011d3 159 if(u32Div > SPI_CLKDIV_DIVIDER_Msk)
sahilmgandhi 18:6a4db94011d3 160 u32Div = SPI_CLKDIV_DIVIDER_Msk;
sahilmgandhi 18:6a4db94011d3 161 }
sahilmgandhi 18:6a4db94011d3 162
sahilmgandhi 18:6a4db94011d3 163 spi->CLKDIV = (spi->CLKDIV & ~SPI_CLKDIV_DIVIDER_Msk) | u32Div;
sahilmgandhi 18:6a4db94011d3 164
sahilmgandhi 18:6a4db94011d3 165 return ( u32ClkSrc / (u32Div+1) );
sahilmgandhi 18:6a4db94011d3 166 }
sahilmgandhi 18:6a4db94011d3 167
sahilmgandhi 18:6a4db94011d3 168 /**
sahilmgandhi 18:6a4db94011d3 169 * @brief Set Tx FIFO threshold and Rx FIFO threshold configurations.
sahilmgandhi 18:6a4db94011d3 170 * @param[in] spi is the base address of SPI module.
sahilmgandhi 18:6a4db94011d3 171 * @param[in] u32TxThreshold decides the Tx FIFO threshold.
sahilmgandhi 18:6a4db94011d3 172 * @param[in] u32RxThreshold decides the Rx FIFO threshold.
sahilmgandhi 18:6a4db94011d3 173 * @return none
sahilmgandhi 18:6a4db94011d3 174 */
sahilmgandhi 18:6a4db94011d3 175 void SPI_SetFIFOThreshold(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
sahilmgandhi 18:6a4db94011d3 176 {
sahilmgandhi 18:6a4db94011d3 177 spi->FIFOCTL = (spi->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk) |
sahilmgandhi 18:6a4db94011d3 178 (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) |
sahilmgandhi 18:6a4db94011d3 179 (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos));
sahilmgandhi 18:6a4db94011d3 180 }
sahilmgandhi 18:6a4db94011d3 181
sahilmgandhi 18:6a4db94011d3 182 /**
sahilmgandhi 18:6a4db94011d3 183 * @brief Get the actual frequency of SPI bus clock. Only available in Master mode.
sahilmgandhi 18:6a4db94011d3 184 * @param[in] spi is the base address of SPI module.
sahilmgandhi 18:6a4db94011d3 185 * @return Actual SPI bus clock frequency.
sahilmgandhi 18:6a4db94011d3 186 */
sahilmgandhi 18:6a4db94011d3 187 uint32_t SPI_GetBusClock(SPI_T *spi)
sahilmgandhi 18:6a4db94011d3 188 {
sahilmgandhi 18:6a4db94011d3 189 uint32_t u32Div;
sahilmgandhi 18:6a4db94011d3 190 uint32_t u32ClkSrc;
sahilmgandhi 18:6a4db94011d3 191
sahilmgandhi 18:6a4db94011d3 192 if(spi == SPI0) {
sahilmgandhi 18:6a4db94011d3 193 if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI0SEL_Msk) == CLK_CLKSEL1_SPI0SEL_PCLK)
sahilmgandhi 18:6a4db94011d3 194 u32ClkSrc = CLK_GetPCLKFreq();
sahilmgandhi 18:6a4db94011d3 195 else
sahilmgandhi 18:6a4db94011d3 196 u32ClkSrc = CLK_GetPLLClockFreq();
sahilmgandhi 18:6a4db94011d3 197 } else if(spi == SPI1) {
sahilmgandhi 18:6a4db94011d3 198 if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI1SEL_Msk) == CLK_CLKSEL1_SPI1SEL_PCLK)
sahilmgandhi 18:6a4db94011d3 199 u32ClkSrc = CLK_GetPCLKFreq();
sahilmgandhi 18:6a4db94011d3 200 else
sahilmgandhi 18:6a4db94011d3 201 u32ClkSrc = CLK_GetPLLClockFreq();
sahilmgandhi 18:6a4db94011d3 202 } else if(spi == SPI2) {
sahilmgandhi 18:6a4db94011d3 203 if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI2SEL_Msk) == CLK_CLKSEL1_SPI2SEL_PCLK)
sahilmgandhi 18:6a4db94011d3 204 u32ClkSrc = CLK_GetPCLKFreq();
sahilmgandhi 18:6a4db94011d3 205 else
sahilmgandhi 18:6a4db94011d3 206 u32ClkSrc = CLK_GetPLLClockFreq();
sahilmgandhi 18:6a4db94011d3 207 } else {
sahilmgandhi 18:6a4db94011d3 208 if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI3SEL_Msk) == CLK_CLKSEL1_SPI3SEL_PCLK)
sahilmgandhi 18:6a4db94011d3 209 u32ClkSrc = CLK_GetPCLKFreq();
sahilmgandhi 18:6a4db94011d3 210 else
sahilmgandhi 18:6a4db94011d3 211 u32ClkSrc = CLK_GetPLLClockFreq();
sahilmgandhi 18:6a4db94011d3 212 }
sahilmgandhi 18:6a4db94011d3 213
sahilmgandhi 18:6a4db94011d3 214 u32Div = spi->CLKDIV & SPI_CLKDIV_DIVIDER_Msk;
sahilmgandhi 18:6a4db94011d3 215 return (u32ClkSrc / (u32Div + 1));
sahilmgandhi 18:6a4db94011d3 216 }
sahilmgandhi 18:6a4db94011d3 217
sahilmgandhi 18:6a4db94011d3 218 /**
sahilmgandhi 18:6a4db94011d3 219 * @brief Enable FIFO related interrupts specified by u32Mask parameter.
sahilmgandhi 18:6a4db94011d3 220 * @param[in] spi is the base address of SPI module.
sahilmgandhi 18:6a4db94011d3 221 * @param[in] u32Mask is the combination of all related interrupt enable bits.
sahilmgandhi 18:6a4db94011d3 222 * Each bit corresponds to a interrupt bit.
sahilmgandhi 18:6a4db94011d3 223 * This parameter decides which interrupts will be enabled. Valid values are:
sahilmgandhi 18:6a4db94011d3 224 * - \ref SPI_UNITIEN_MASK
sahilmgandhi 18:6a4db94011d3 225 * - \ref SPI_SSINAIEN_MASK
sahilmgandhi 18:6a4db94011d3 226 * - \ref SPI_SSACTIEN_MASK
sahilmgandhi 18:6a4db94011d3 227 * - \ref SPI_SLVURIEN_MASK
sahilmgandhi 18:6a4db94011d3 228 * - \ref SPI_SLVBEIEN_MASK
sahilmgandhi 18:6a4db94011d3 229 * - \ref SPI_SLVTOIEN_MASK
sahilmgandhi 18:6a4db94011d3 230 * - \ref SPI_FIFO_TXTHIEN_MASK
sahilmgandhi 18:6a4db94011d3 231 * - \ref SPI_FIFO_RXTHIEN_MASK
sahilmgandhi 18:6a4db94011d3 232 * - \ref SPI_FIFO_RXOVIEN_MASK
sahilmgandhi 18:6a4db94011d3 233 * - \ref SPI_FIFO_TXUFIEN_MASK
sahilmgandhi 18:6a4db94011d3 234 * - \ref SPI_FIFO_RXTOIEN_MASK
sahilmgandhi 18:6a4db94011d3 235 * @return none
sahilmgandhi 18:6a4db94011d3 236 */
sahilmgandhi 18:6a4db94011d3 237 void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
sahilmgandhi 18:6a4db94011d3 238 {
sahilmgandhi 18:6a4db94011d3 239 if((u32Mask & SPI_UNITIEN_MASK) == SPI_UNITIEN_MASK)
sahilmgandhi 18:6a4db94011d3 240 spi->CTL |= SPI_CTL_UNITIEN_Msk;
sahilmgandhi 18:6a4db94011d3 241
sahilmgandhi 18:6a4db94011d3 242 if((u32Mask & SPI_SSINAIEN_MASK) == SPI_SSINAIEN_MASK)
sahilmgandhi 18:6a4db94011d3 243 spi->SSCTL |= SPI_SSCTL_SSINAIEN_Msk;
sahilmgandhi 18:6a4db94011d3 244
sahilmgandhi 18:6a4db94011d3 245 if((u32Mask & SPI_SSACTIEN_MASK) == SPI_SSACTIEN_MASK)
sahilmgandhi 18:6a4db94011d3 246 spi->SSCTL |= SPI_SSCTL_SSACTIEN_Msk;
sahilmgandhi 18:6a4db94011d3 247
sahilmgandhi 18:6a4db94011d3 248 if((u32Mask & SPI_SLVURIEN_MASK) == SPI_SLVURIEN_MASK)
sahilmgandhi 18:6a4db94011d3 249 spi->SSCTL |= SPI_SSCTL_SLVURIEN_Msk;
sahilmgandhi 18:6a4db94011d3 250
sahilmgandhi 18:6a4db94011d3 251 if((u32Mask & SPI_SLVBEIEN_MASK) == SPI_SLVBEIEN_MASK)
sahilmgandhi 18:6a4db94011d3 252 spi->SSCTL |= SPI_SSCTL_SLVBEIEN_Msk;
sahilmgandhi 18:6a4db94011d3 253
sahilmgandhi 18:6a4db94011d3 254 if((u32Mask & SPI_SLVTOIEN_MASK) == SPI_SLVTOIEN_MASK)
sahilmgandhi 18:6a4db94011d3 255 spi->SSCTL |= SPI_SSCTL_SLVTOIEN_Msk;
sahilmgandhi 18:6a4db94011d3 256
sahilmgandhi 18:6a4db94011d3 257 if((u32Mask & SPI_FIFO_TXTHIEN_MASK) == SPI_FIFO_TXTHIEN_MASK)
sahilmgandhi 18:6a4db94011d3 258 spi->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk;
sahilmgandhi 18:6a4db94011d3 259
sahilmgandhi 18:6a4db94011d3 260 if((u32Mask & SPI_FIFO_RXTHIEN_MASK) == SPI_FIFO_RXTHIEN_MASK)
sahilmgandhi 18:6a4db94011d3 261 spi->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk;
sahilmgandhi 18:6a4db94011d3 262
sahilmgandhi 18:6a4db94011d3 263 if((u32Mask & SPI_FIFO_RXOVIEN_MASK) == SPI_FIFO_RXOVIEN_MASK)
sahilmgandhi 18:6a4db94011d3 264 spi->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk;
sahilmgandhi 18:6a4db94011d3 265
sahilmgandhi 18:6a4db94011d3 266 if((u32Mask & SPI_FIFO_TXUFIEN_MASK) == SPI_FIFO_TXUFIEN_MASK)
sahilmgandhi 18:6a4db94011d3 267 spi->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk;
sahilmgandhi 18:6a4db94011d3 268
sahilmgandhi 18:6a4db94011d3 269 if((u32Mask & SPI_FIFO_RXTOIEN_MASK) == SPI_FIFO_RXTOIEN_MASK)
sahilmgandhi 18:6a4db94011d3 270 spi->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk;
sahilmgandhi 18:6a4db94011d3 271 }
sahilmgandhi 18:6a4db94011d3 272
sahilmgandhi 18:6a4db94011d3 273 /**
sahilmgandhi 18:6a4db94011d3 274 * @brief Disable FIFO related interrupts specified by u32Mask parameter.
sahilmgandhi 18:6a4db94011d3 275 * @param[in] spi is the base address of SPI module.
sahilmgandhi 18:6a4db94011d3 276 * @param[in] u32Mask is the combination of all related interrupt enable bits.
sahilmgandhi 18:6a4db94011d3 277 * Each bit corresponds to a interrupt bit.
sahilmgandhi 18:6a4db94011d3 278 * This parameter decides which interrupts will be enabled. Valid values are:
sahilmgandhi 18:6a4db94011d3 279 * - \ref SPI_UNITIEN_MASK
sahilmgandhi 18:6a4db94011d3 280 * - \ref SPI_SSINAIEN_MASK
sahilmgandhi 18:6a4db94011d3 281 * - \ref SPI_SSACTIEN_MASK
sahilmgandhi 18:6a4db94011d3 282 * - \ref SPI_SLVURIEN_MASK
sahilmgandhi 18:6a4db94011d3 283 * - \ref SPI_SLVBEIEN_MASK
sahilmgandhi 18:6a4db94011d3 284 * - \ref SPI_SLVTOIEN_MASK
sahilmgandhi 18:6a4db94011d3 285 * - \ref SPI_FIFO_TXTHIEN_MASK
sahilmgandhi 18:6a4db94011d3 286 * - \ref SPI_FIFO_RXTHIEN_MASK
sahilmgandhi 18:6a4db94011d3 287 * - \ref SPI_FIFO_RXOVIEN_MASK
sahilmgandhi 18:6a4db94011d3 288 * - \ref SPI_FIFO_TXUFIEN_MASK
sahilmgandhi 18:6a4db94011d3 289 * - \ref SPI_FIFO_RXTOIEN_MASK
sahilmgandhi 18:6a4db94011d3 290 * @return none
sahilmgandhi 18:6a4db94011d3 291 */
sahilmgandhi 18:6a4db94011d3 292 void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
sahilmgandhi 18:6a4db94011d3 293 {
sahilmgandhi 18:6a4db94011d3 294 if((u32Mask & SPI_UNITIEN_MASK) == SPI_UNITIEN_MASK)
sahilmgandhi 18:6a4db94011d3 295 spi->CTL &= ~SPI_CTL_UNITIEN_Msk;
sahilmgandhi 18:6a4db94011d3 296
sahilmgandhi 18:6a4db94011d3 297 if((u32Mask & SPI_SSINAIEN_MASK) == SPI_SSINAIEN_MASK)
sahilmgandhi 18:6a4db94011d3 298 spi->SSCTL &= ~SPI_SSCTL_SSINAIEN_Msk;
sahilmgandhi 18:6a4db94011d3 299
sahilmgandhi 18:6a4db94011d3 300 if((u32Mask & SPI_SSACTIEN_MASK) == SPI_SSACTIEN_MASK)
sahilmgandhi 18:6a4db94011d3 301 spi->SSCTL &= ~SPI_SSCTL_SSACTIEN_Msk;
sahilmgandhi 18:6a4db94011d3 302
sahilmgandhi 18:6a4db94011d3 303 if((u32Mask & SPI_SLVURIEN_MASK) == SPI_SLVURIEN_MASK)
sahilmgandhi 18:6a4db94011d3 304 spi->SSCTL &= ~SPI_SSCTL_SLVURIEN_Msk;
sahilmgandhi 18:6a4db94011d3 305
sahilmgandhi 18:6a4db94011d3 306 if((u32Mask & SPI_SLVBEIEN_MASK) == SPI_SLVBEIEN_MASK)
sahilmgandhi 18:6a4db94011d3 307 spi->SSCTL &= ~SPI_SSCTL_SLVBEIEN_Msk;
sahilmgandhi 18:6a4db94011d3 308
sahilmgandhi 18:6a4db94011d3 309 if((u32Mask & SPI_SLVTOIEN_MASK) == SPI_SLVTOIEN_MASK)
sahilmgandhi 18:6a4db94011d3 310 spi->SSCTL &= ~SPI_SSCTL_SLVTOIEN_Msk;
sahilmgandhi 18:6a4db94011d3 311
sahilmgandhi 18:6a4db94011d3 312 if((u32Mask & SPI_FIFO_TXTHIEN_MASK) == SPI_FIFO_TXTHIEN_MASK)
sahilmgandhi 18:6a4db94011d3 313 spi->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk;
sahilmgandhi 18:6a4db94011d3 314
sahilmgandhi 18:6a4db94011d3 315 if((u32Mask & SPI_FIFO_RXTHIEN_MASK) == SPI_FIFO_RXTHIEN_MASK)
sahilmgandhi 18:6a4db94011d3 316 spi->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk;
sahilmgandhi 18:6a4db94011d3 317
sahilmgandhi 18:6a4db94011d3 318 if((u32Mask & SPI_FIFO_RXOVIEN_MASK) == SPI_FIFO_RXOVIEN_MASK)
sahilmgandhi 18:6a4db94011d3 319 spi->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk;
sahilmgandhi 18:6a4db94011d3 320
sahilmgandhi 18:6a4db94011d3 321 if((u32Mask & SPI_FIFO_TXUFIEN_MASK) == SPI_FIFO_TXUFIEN_MASK)
sahilmgandhi 18:6a4db94011d3 322 spi->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk;
sahilmgandhi 18:6a4db94011d3 323
sahilmgandhi 18:6a4db94011d3 324 if((u32Mask & SPI_FIFO_RXTOIEN_MASK) == SPI_FIFO_RXTOIEN_MASK)
sahilmgandhi 18:6a4db94011d3 325 spi->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk;
sahilmgandhi 18:6a4db94011d3 326 }
sahilmgandhi 18:6a4db94011d3 327
sahilmgandhi 18:6a4db94011d3 328 /*@}*/ /* end of group NUC472_442_SPI_EXPORTED_FUNCTIONS */
sahilmgandhi 18:6a4db94011d3 329
sahilmgandhi 18:6a4db94011d3 330 /*@}*/ /* end of group NUC472_442_SPI_Driver */
sahilmgandhi 18:6a4db94011d3 331
sahilmgandhi 18:6a4db94011d3 332 /*@}*/ /* end of group NUC472_442_Device_Driver */
sahilmgandhi 18:6a4db94011d3 333
sahilmgandhi 18:6a4db94011d3 334 /*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/