MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_scuart.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file sc.h
sahilmgandhi 18:6a4db94011d3 3 * @version V1.00
sahilmgandhi 18:6a4db94011d3 4 * $Revision: 8 $
sahilmgandhi 18:6a4db94011d3 5 * $Date: 14/05/29 1:13p $
sahilmgandhi 18:6a4db94011d3 6 * @brief NUC472/NUC442 Smartcard UART mode (SCUART) driver header file
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * @note
sahilmgandhi 18:6a4db94011d3 9 * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
sahilmgandhi 18:6a4db94011d3 10 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 11 #ifndef __SCUART_H__
sahilmgandhi 18:6a4db94011d3 12 #define __SCUART_H__
sahilmgandhi 18:6a4db94011d3 13
sahilmgandhi 18:6a4db94011d3 14 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 15 extern "C"
sahilmgandhi 18:6a4db94011d3 16 {
sahilmgandhi 18:6a4db94011d3 17 #endif
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19
sahilmgandhi 18:6a4db94011d3 20 /** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
sahilmgandhi 18:6a4db94011d3 21 @{
sahilmgandhi 18:6a4db94011d3 22 */
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24 /** @addtogroup NUC472_442_SCUART_Driver SCUART Driver
sahilmgandhi 18:6a4db94011d3 25 @{
sahilmgandhi 18:6a4db94011d3 26 */
sahilmgandhi 18:6a4db94011d3 27
sahilmgandhi 18:6a4db94011d3 28 /** @addtogroup NUC472_442_SCUART_EXPORTED_CONSTANTS SCUART Exported Constants
sahilmgandhi 18:6a4db94011d3 29 @{
sahilmgandhi 18:6a4db94011d3 30 */
sahilmgandhi 18:6a4db94011d3 31 #define SCUART_CHAR_LEN_5 (0x3ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 5 bits \hideinitializer */
sahilmgandhi 18:6a4db94011d3 32 #define SCUART_CHAR_LEN_6 (0x2ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 6 bits \hideinitializer */
sahilmgandhi 18:6a4db94011d3 33 #define SCUART_CHAR_LEN_7 (0x1ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 7 bits \hideinitializer */
sahilmgandhi 18:6a4db94011d3 34 #define SCUART_CHAR_LEN_8 (0) /*!< Set SCUART word length to 8 bits \hideinitializer */
sahilmgandhi 18:6a4db94011d3 35
sahilmgandhi 18:6a4db94011d3 36 #define SCUART_PARITY_NONE (SC_UARTCTL_PBOFF_Msk) /*!< Set SCUART transfer with no parity \hideinitializer */
sahilmgandhi 18:6a4db94011d3 37 #define SCUART_PARITY_ODD (SC_UARTCTL_OPE_Msk) /*!< Set SCUART transfer with odd parity \hideinitializer */
sahilmgandhi 18:6a4db94011d3 38 #define SCUART_PARITY_EVEN (0) /*!< Set SCUART transfer with even parity \hideinitializer */
sahilmgandhi 18:6a4db94011d3 39
sahilmgandhi 18:6a4db94011d3 40 #define SCUART_STOP_BIT_1 (SC_CTL_NSB_Msk) /*!< Set SCUART transfer with one stop bit \hideinitializer */
sahilmgandhi 18:6a4db94011d3 41 #define SCUART_STOP_BIT_2 (0) /*!< Set SCUART transfer with two stop bits \hideinitializer */
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 /*@}*/ /* end of group NUC472_442_SCUART_EXPORTED_CONSTANTS */
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46
sahilmgandhi 18:6a4db94011d3 47 /** @addtogroup NUC472_442_SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions
sahilmgandhi 18:6a4db94011d3 48 @{
sahilmgandhi 18:6a4db94011d3 49 */
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 /* TX Macros */
sahilmgandhi 18:6a4db94011d3 52 /**
sahilmgandhi 18:6a4db94011d3 53 * @brief Write Data to Tx data register
sahilmgandhi 18:6a4db94011d3 54 * @param[in] sc The base address of smartcard module.
sahilmgandhi 18:6a4db94011d3 55 * @param[in] u8Data Data byte to transmit
sahilmgandhi 18:6a4db94011d3 56 * @return None
sahilmgandhi 18:6a4db94011d3 57 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 58 */
sahilmgandhi 18:6a4db94011d3 59 #define SCUART_WRITE(sc, u8Data) ((sc)->DAT = (u8Data))
sahilmgandhi 18:6a4db94011d3 60
sahilmgandhi 18:6a4db94011d3 61 /**
sahilmgandhi 18:6a4db94011d3 62 * @brief Get TX FIFO empty flag status from register
sahilmgandhi 18:6a4db94011d3 63 * @param[in] sc The base address of smartcard module
sahilmgandhi 18:6a4db94011d3 64 * @return Transmit FIFO empty status
sahilmgandhi 18:6a4db94011d3 65 * @retval 0 Transmit FIFO is not empty
sahilmgandhi 18:6a4db94011d3 66 * @retval SC_STATUS_TXEMPTY_Msk Transmit FIFO is empty
sahilmgandhi 18:6a4db94011d3 67 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 68 */
sahilmgandhi 18:6a4db94011d3 69 #define SCUART_GET_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXEMPTY_Msk)
sahilmgandhi 18:6a4db94011d3 70
sahilmgandhi 18:6a4db94011d3 71 /**
sahilmgandhi 18:6a4db94011d3 72 * @brief Get TX FIFO full flag status from register
sahilmgandhi 18:6a4db94011d3 73 * @param[in] sc The base address of smartcard module
sahilmgandhi 18:6a4db94011d3 74 * @return Transmit FIFO full status
sahilmgandhi 18:6a4db94011d3 75 * @retval 0 Transmit FIFO is not full
sahilmgandhi 18:6a4db94011d3 76 * @retval SC_STATUS_TXFULL_Msk Transmit FIFO is full
sahilmgandhi 18:6a4db94011d3 77 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 78 */
sahilmgandhi 18:6a4db94011d3 79 #define SCUART_GET_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk)
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 /**
sahilmgandhi 18:6a4db94011d3 82 * @brief Wait specified smartcard port transmission complete
sahilmgandhi 18:6a4db94011d3 83 * @param[in] sc The base address of smartcard module
sahilmgandhi 18:6a4db94011d3 84 * @return None
sahilmgandhi 18:6a4db94011d3 85 * @note This Macro blocks until transmit complete.
sahilmgandhi 18:6a4db94011d3 86 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 87 */
sahilmgandhi 18:6a4db94011d3 88 #define SCUART_WAIT_TX_EMPTY(sc) while((sc)->STATUS & SC_STATUS_TXACT_Msk)
sahilmgandhi 18:6a4db94011d3 89
sahilmgandhi 18:6a4db94011d3 90 /**
sahilmgandhi 18:6a4db94011d3 91 * @brief Check specified smartcard port transmit FIFO is full or not
sahilmgandhi 18:6a4db94011d3 92 * @param[in] sc The base address of smartcard module
sahilmgandhi 18:6a4db94011d3 93 * @return Transmit FIFO full status
sahilmgandhi 18:6a4db94011d3 94 * @retval 0 Transmit FIFO is not full
sahilmgandhi 18:6a4db94011d3 95 * @retval 1 Transmit FIFO is full
sahilmgandhi 18:6a4db94011d3 96 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 97 */
sahilmgandhi 18:6a4db94011d3 98 #define SCUART_IS_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk ? 1 : 0)
sahilmgandhi 18:6a4db94011d3 99
sahilmgandhi 18:6a4db94011d3 100 /**
sahilmgandhi 18:6a4db94011d3 101 * @brief Check specified smartcard port transmission is over
sahilmgandhi 18:6a4db94011d3 102 * @param[in] sc The base address of smartcard module
sahilmgandhi 18:6a4db94011d3 103 * @return Transmit complete status
sahilmgandhi 18:6a4db94011d3 104 * @retval 0 Transmit is not complete
sahilmgandhi 18:6a4db94011d3 105 * @retval 1 Transmit complete
sahilmgandhi 18:6a4db94011d3 106 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 107 */
sahilmgandhi 18:6a4db94011d3 108 #define SCUART_IS_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXACT_Msk ? 0 : 1)
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 /* RX Macros */
sahilmgandhi 18:6a4db94011d3 112
sahilmgandhi 18:6a4db94011d3 113 /**
sahilmgandhi 18:6a4db94011d3 114 * @brief Read Rx data register
sahilmgandhi 18:6a4db94011d3 115 * @param[in] sc The base address of smartcard module
sahilmgandhi 18:6a4db94011d3 116 * @return The oldest data byte in RX FIFO
sahilmgandhi 18:6a4db94011d3 117 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 118 */
sahilmgandhi 18:6a4db94011d3 119 #define SCUART_READ(sc) ((sc)->DAT)
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 /**
sahilmgandhi 18:6a4db94011d3 122 * @brief Get RX FIFO empty flag status from register
sahilmgandhi 18:6a4db94011d3 123 * @param[in] sc The base address of smartcard module
sahilmgandhi 18:6a4db94011d3 124 * @return Receive FIFO empty status
sahilmgandhi 18:6a4db94011d3 125 * @retval 0 Receive FIFO is not empty
sahilmgandhi 18:6a4db94011d3 126 * @retval SC_STATUS_RXEMPTY_Msk Receive FIFO is empty
sahilmgandhi 18:6a4db94011d3 127 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 128 */
sahilmgandhi 18:6a4db94011d3 129 #define SCUART_GET_RX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_RXEMPTY_Msk)
sahilmgandhi 18:6a4db94011d3 130
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132 /**
sahilmgandhi 18:6a4db94011d3 133 * @brief Get RX FIFO full flag status from register
sahilmgandhi 18:6a4db94011d3 134 * @param[in] sc The base address of smartcard module
sahilmgandhi 18:6a4db94011d3 135 * @return Receive FIFO full status
sahilmgandhi 18:6a4db94011d3 136 * @retval 0 Receive FIFO is not full
sahilmgandhi 18:6a4db94011d3 137 * @retval SC_STATUS_RXFULLF_Msk Receive FIFO is full
sahilmgandhi 18:6a4db94011d3 138 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 139 */
sahilmgandhi 18:6a4db94011d3 140 #define SCUART_GET_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk)
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142 /**
sahilmgandhi 18:6a4db94011d3 143 * @brief Check if receive data number in FIFO reach FIFO trigger level or not
sahilmgandhi 18:6a4db94011d3 144 * @param[in] sc The base address of smartcard module
sahilmgandhi 18:6a4db94011d3 145 * @return Receive FIFO data status
sahilmgandhi 18:6a4db94011d3 146 * @retval 0 The number of bytes in receive FIFO is less than trigger level
sahilmgandhi 18:6a4db94011d3 147 * @retval 1 The number of bytes in receive FIFO equals or larger than trigger level
sahilmgandhi 18:6a4db94011d3 148 * @note If receive trigger level is \b not 1 byte, this macro return 0 does not necessary indicates there is \b no data in FIFO
sahilmgandhi 18:6a4db94011d3 149 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 150 */
sahilmgandhi 18:6a4db94011d3 151 #define SCUART_IS_RX_READY(sc) ((sc)->INTSTS & SC_INTSTS_RDAIF_Msk ? 1 : 0)
sahilmgandhi 18:6a4db94011d3 152
sahilmgandhi 18:6a4db94011d3 153 /**
sahilmgandhi 18:6a4db94011d3 154 * @brief Check specified smartcard port receive FIFO is full or not
sahilmgandhi 18:6a4db94011d3 155 * @param[in] sc The base address of smartcard module
sahilmgandhi 18:6a4db94011d3 156 * @return Receive FIFO full status
sahilmgandhi 18:6a4db94011d3 157 * @retval 0 Receive FIFO is not full
sahilmgandhi 18:6a4db94011d3 158 * @retval 1 Receive FIFO is full
sahilmgandhi 18:6a4db94011d3 159 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 160 */
sahilmgandhi 18:6a4db94011d3 161 #define SCUART_IS_RX_FULL(sc) ((sc)->STATUS & SC_SR_RX_FULL_F_Msk ? 1 : 0)
sahilmgandhi 18:6a4db94011d3 162
sahilmgandhi 18:6a4db94011d3 163 /* Interrupt Macros */
sahilmgandhi 18:6a4db94011d3 164
sahilmgandhi 18:6a4db94011d3 165 /**
sahilmgandhi 18:6a4db94011d3 166 * @brief Enable specified interrupts
sahilmgandhi 18:6a4db94011d3 167 * @param[in] sc The base address of smartcard module
sahilmgandhi 18:6a4db94011d3 168 * @param[in] u32Mask Interrupt masks to enable, a combination of following bits
sahilmgandhi 18:6a4db94011d3 169 * - \ref SC_INTEN_RXTOIF_Msk
sahilmgandhi 18:6a4db94011d3 170 * - \ref SC_INTEN_TERRIEN_Msk
sahilmgandhi 18:6a4db94011d3 171 * - \ref SC_INTEN_TBEIEN_Msk
sahilmgandhi 18:6a4db94011d3 172 * - \ref SC_INTEN_RDAIEN_Msk
sahilmgandhi 18:6a4db94011d3 173 * @return None
sahilmgandhi 18:6a4db94011d3 174 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 175 */
sahilmgandhi 18:6a4db94011d3 176 #define SCUART_ENABLE_INT(sc, u32Mask) ((sc)->INTEN |= (u32Mask))
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178 /**
sahilmgandhi 18:6a4db94011d3 179 * @brief Disable specified interrupts
sahilmgandhi 18:6a4db94011d3 180 * @param[in] sc The base address of smartcard module
sahilmgandhi 18:6a4db94011d3 181 * @param[in] u32Mask Interrupt masks to disable, a combination of following bits
sahilmgandhi 18:6a4db94011d3 182 * - \ref SC_INTEN_RXTOIF_Msk
sahilmgandhi 18:6a4db94011d3 183 * - \ref SC_INTEN_TERRIEN_Msk
sahilmgandhi 18:6a4db94011d3 184 * - \ref SC_INTEN_TBEIEN_Msk
sahilmgandhi 18:6a4db94011d3 185 * - \ref SC_INTEN_RDAIEN_Msk
sahilmgandhi 18:6a4db94011d3 186 * @return None
sahilmgandhi 18:6a4db94011d3 187 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 188 */
sahilmgandhi 18:6a4db94011d3 189 #define SCUART_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask))
sahilmgandhi 18:6a4db94011d3 190
sahilmgandhi 18:6a4db94011d3 191 /**
sahilmgandhi 18:6a4db94011d3 192 * @brief Get specified interrupt flag/status
sahilmgandhi 18:6a4db94011d3 193 * @param[in] sc The base address of smartcard module
sahilmgandhi 18:6a4db94011d3 194 * @param[in] u32Type Interrupt flag/status to check, could be one of following value
sahilmgandhi 18:6a4db94011d3 195 * - \ref SC_INTSTS_RBTOIF_Msk
sahilmgandhi 18:6a4db94011d3 196 * - \ref SC_INTSTS_TERRIF_Msk
sahilmgandhi 18:6a4db94011d3 197 * - \ref SC_INTSTS_TBEIF_Msk
sahilmgandhi 18:6a4db94011d3 198 * - \ref SC_INTSTS_RDAIF_Msk
sahilmgandhi 18:6a4db94011d3 199 * @return The status of specified interrupt
sahilmgandhi 18:6a4db94011d3 200 * @retval 0 Specified interrupt does not happened
sahilmgandhi 18:6a4db94011d3 201 * @retval 1 Specified interrupt happened
sahilmgandhi 18:6a4db94011d3 202 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 203 */
sahilmgandhi 18:6a4db94011d3 204 #define SCUART_GET_INT_FLAG(sc, u32Type) ((sc)->INTSTS & u32Type ? 1 : 0)
sahilmgandhi 18:6a4db94011d3 205
sahilmgandhi 18:6a4db94011d3 206 /**
sahilmgandhi 18:6a4db94011d3 207 * @brief Clear specified interrupt flag/status
sahilmgandhi 18:6a4db94011d3 208 * @param[in] sc The base address of smartcard module
sahilmgandhi 18:6a4db94011d3 209 * @param[in] u32Type Interrupt flag/status to clear, could be the combination of following values
sahilmgandhi 18:6a4db94011d3 210 * - \ref SC_INTSTS_RBTOIF_Msk
sahilmgandhi 18:6a4db94011d3 211 * - \ref SC_INTSTS_TERRIF_Msk
sahilmgandhi 18:6a4db94011d3 212 * - \ref SC_INTSTS_TBEIF_Msk
sahilmgandhi 18:6a4db94011d3 213 * @return None
sahilmgandhi 18:6a4db94011d3 214 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 215 */
sahilmgandhi 18:6a4db94011d3 216 #define SCUART_CLR_INT_FLAG(sc, u32Type) ((sc)->INTSTS = u32Type)
sahilmgandhi 18:6a4db94011d3 217
sahilmgandhi 18:6a4db94011d3 218 /**
sahilmgandhi 18:6a4db94011d3 219 * @brief Get receive error flag/status
sahilmgandhi 18:6a4db94011d3 220 * @param[in] sc The base address of smartcard module
sahilmgandhi 18:6a4db94011d3 221 * @return Current receive error status, could one of following errors:
sahilmgandhi 18:6a4db94011d3 222 * @retval SC_STATUS_PEF_Msk Parity error
sahilmgandhi 18:6a4db94011d3 223 * @retval SC_STATUS_FEF_Msk Frame error
sahilmgandhi 18:6a4db94011d3 224 * @retval SC_STATUS_BEF_Msk Break error
sahilmgandhi 18:6a4db94011d3 225 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 226 */
sahilmgandhi 18:6a4db94011d3 227 #define SCUART_GET_ERR_FLAG(sc) ((sc)->STATUS & (SC_STATUS_PEF_Msk | SC_STATUS_FEF_Msk | SC_STATUS_BEF_Msk))
sahilmgandhi 18:6a4db94011d3 228
sahilmgandhi 18:6a4db94011d3 229 /**
sahilmgandhi 18:6a4db94011d3 230 * @brief Clear specified receive error flag/status
sahilmgandhi 18:6a4db94011d3 231 * @param[in] sc The base address of smartcard module
sahilmgandhi 18:6a4db94011d3 232 * @param[in] u32Mask Receive error flag/status to clear, combination following values
sahilmgandhi 18:6a4db94011d3 233 * - \ref SC_STATUS_PEF_Msk
sahilmgandhi 18:6a4db94011d3 234 * - \ref SC_STATUS_FEF_Msk
sahilmgandhi 18:6a4db94011d3 235 * - \ref SC_STATUS_BEF_Msk
sahilmgandhi 18:6a4db94011d3 236 * @return None
sahilmgandhi 18:6a4db94011d3 237 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 238 */
sahilmgandhi 18:6a4db94011d3 239 #define SCUART_CLR_ERR_FLAG(sc, u32Mask) ((sc)->STATUS = u32Mask)
sahilmgandhi 18:6a4db94011d3 240
sahilmgandhi 18:6a4db94011d3 241 void SCUART_Close(SC_T* sc);
sahilmgandhi 18:6a4db94011d3 242 uint32_t SCUART_Open(SC_T* sc, uint32_t u32baudrate);
sahilmgandhi 18:6a4db94011d3 243 uint32_t SCUART_Read(SC_T* sc, uint8_t *pu8RxBuf, uint32_t u32ReadBytes);
sahilmgandhi 18:6a4db94011d3 244 uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits);
sahilmgandhi 18:6a4db94011d3 245 void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC);
sahilmgandhi 18:6a4db94011d3 246 void SCUART_Write(SC_T* sc,uint8_t *pu8TxBuf, uint32_t u32WriteBytes);
sahilmgandhi 18:6a4db94011d3 247
sahilmgandhi 18:6a4db94011d3 248 /*@}*/ /* end of group NUC472_442_SCUART_EXPORTED_FUNCTIONS */
sahilmgandhi 18:6a4db94011d3 249
sahilmgandhi 18:6a4db94011d3 250 /*@}*/ /* end of group NUC472_442_SCUART_Driver */
sahilmgandhi 18:6a4db94011d3 251
sahilmgandhi 18:6a4db94011d3 252 /*@}*/ /* end of group NUC472_442_Device_Driver */
sahilmgandhi 18:6a4db94011d3 253
sahilmgandhi 18:6a4db94011d3 254 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 255 }
sahilmgandhi 18:6a4db94011d3 256 #endif
sahilmgandhi 18:6a4db94011d3 257
sahilmgandhi 18:6a4db94011d3 258 #endif //__SCUART_H__
sahilmgandhi 18:6a4db94011d3 259
sahilmgandhi 18:6a4db94011d3 260 /*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/