MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_pwm.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file pwm.h
sahilmgandhi 18:6a4db94011d3 3 * @version V1.00
sahilmgandhi 18:6a4db94011d3 4 * $Revision: 22 $
sahilmgandhi 18:6a4db94011d3 5 * $Date: 15/11/16 2:08p $
sahilmgandhi 18:6a4db94011d3 6 * @brief NUC472/NUC442 PWM driver header file
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * @note
sahilmgandhi 18:6a4db94011d3 9 * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
sahilmgandhi 18:6a4db94011d3 10 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 11 #ifndef __PWM_H__
sahilmgandhi 18:6a4db94011d3 12 #define __PWM_H__
sahilmgandhi 18:6a4db94011d3 13
sahilmgandhi 18:6a4db94011d3 14 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 15 extern "C"
sahilmgandhi 18:6a4db94011d3 16 {
sahilmgandhi 18:6a4db94011d3 17 #endif
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19
sahilmgandhi 18:6a4db94011d3 20 /** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
sahilmgandhi 18:6a4db94011d3 21 @{
sahilmgandhi 18:6a4db94011d3 22 */
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24 /** @addtogroup NUC472_442_PWM_Driver PWM Driver
sahilmgandhi 18:6a4db94011d3 25 @{
sahilmgandhi 18:6a4db94011d3 26 */
sahilmgandhi 18:6a4db94011d3 27
sahilmgandhi 18:6a4db94011d3 28 /** @addtogroup NUC472_442_PWM_EXPORTED_CONSTANTS PWM Exported Constants
sahilmgandhi 18:6a4db94011d3 29 @{
sahilmgandhi 18:6a4db94011d3 30 */
sahilmgandhi 18:6a4db94011d3 31 #define PWM_CHANNEL_NUM (6) /*!< PWM channel number \hideinitializer */
sahilmgandhi 18:6a4db94011d3 32 #define PWM_CH0 (0UL) /*!< PWM channel 0 \hideinitializer */
sahilmgandhi 18:6a4db94011d3 33 #define PWM_CH1 (1UL) /*!< PWM channel 1 \hideinitializer */
sahilmgandhi 18:6a4db94011d3 34 #define PWM_CH2 (2UL) /*!< PWM channel 2 \hideinitializer */
sahilmgandhi 18:6a4db94011d3 35 #define PWM_CH3 (3UL) /*!< PWM channel 3 \hideinitializer */
sahilmgandhi 18:6a4db94011d3 36 #define PWM_CH4 (4UL) /*!< PWM channel 4 \hideinitializer */
sahilmgandhi 18:6a4db94011d3 37 #define PWM_CH5 (5UL) /*!< PWM channel 5 \hideinitializer */
sahilmgandhi 18:6a4db94011d3 38 #define PWM_CH_0_MASK (1UL) /*!< PWM channel 0 mask \hideinitializer */
sahilmgandhi 18:6a4db94011d3 39 #define PWM_CH_1_MASK (2UL) /*!< PWM channel 1 mask \hideinitializer */
sahilmgandhi 18:6a4db94011d3 40 #define PWM_CH_2_MASK (4UL) /*!< PWM channel 2 mask \hideinitializer */
sahilmgandhi 18:6a4db94011d3 41 #define PWM_CH_3_MASK (8UL) /*!< PWM channel 3 mask \hideinitializer */
sahilmgandhi 18:6a4db94011d3 42 #define PWM_CH_4_MASK (16UL) /*!< PWM channel 4 mask \hideinitializer */
sahilmgandhi 18:6a4db94011d3 43 #define PWM_CH_5_MASK (32UL) /*!< PWM channel 5 mask \hideinitializer */
sahilmgandhi 18:6a4db94011d3 44 #define PWM_CLK_DIV_1 (4UL) /*!< PWM clock divide by 1 \hideinitializer */
sahilmgandhi 18:6a4db94011d3 45 #define PWM_CLK_DIV_2 (0UL) /*!< PWM clock divide by 2 \hideinitializer */
sahilmgandhi 18:6a4db94011d3 46 #define PWM_CLK_DIV_4 (1UL) /*!< PWM clock divide by 4 \hideinitializer */
sahilmgandhi 18:6a4db94011d3 47 #define PWM_CLK_DIV_8 (2UL) /*!< PWM clock divide by 8 \hideinitializer */
sahilmgandhi 18:6a4db94011d3 48 #define PWM_CLK_DIV_16 (3UL) /*!< PWM clock divide by 16 \hideinitializer */
sahilmgandhi 18:6a4db94011d3 49 #define PWM_EDGE_ALIGNED (0UL) /*!< PWM working in edge aligned type \hideinitializer */
sahilmgandhi 18:6a4db94011d3 50 #define PWM_CENTER_ALIGNED (1UL) /*!< PWM working in center aligned type \hideinitializer */
sahilmgandhi 18:6a4db94011d3 51 #define PWM_TRIGGER_ADC_RISING_EDGE_POINT (0x1000000UL) /*!< PWM trigger ADC while output rising edge is detected \hideinitializer */
sahilmgandhi 18:6a4db94011d3 52 #define PWM_TRIGGER_ADC_FALLING_EDGE_POINT (0x10000UL) /*!< PWM trigger ADC while output falling edge is detected \hideinitializer */
sahilmgandhi 18:6a4db94011d3 53 #define PWM_TRIGGER_ADC_CENTER_POINT (0x100UL) /*!< PWM trigger ADC while counter matches (CNR + 1) \hideinitializer */
sahilmgandhi 18:6a4db94011d3 54 #define PWM_TRIGGER_ADC_PERIOD_POINT (0x1UL) /*!< PWM trigger ADC while counter down count to 0 \hideinitializer */
sahilmgandhi 18:6a4db94011d3 55 #define PWM_BRK0_BKP0 (PWM_BRKCTL_BRK0EN_Msk) /*!< Brake0 signal source from external pin BKP0 \hideinitializer */
sahilmgandhi 18:6a4db94011d3 56 #define PWM_BRK0_CPO0 (PWM_BRKCTL_CPO0BKEN_Msk) /*!< Brake0 signal source from analog comparator 0 output \hideinitializer */
sahilmgandhi 18:6a4db94011d3 57 #define PWM_BRK0_CPO1 (PWM_BRKCTL_CPO1BKEN_Msk) /*!< Brake0 signal source from analog comparator 1 output \hideinitializer */
sahilmgandhi 18:6a4db94011d3 58 #define PWM_BRK0_CPO2 (PWM_BRKCTL_CPO2BKEN_Msk) /*!< Brake0 signal source from analog comparator 2 output \hideinitializer */
sahilmgandhi 18:6a4db94011d3 59 #define PWM_BRK1_LVDBK (PWM_BRKCTL_LVDBKEN_Msk) /*!< Brake1 signal source from level detect \hideinitializer */
sahilmgandhi 18:6a4db94011d3 60 #define PWM_BK1SEL_BKP1 (0UL << PWM_BRKCTL_BK1SEL_Pos) /*!< Brake1 signal source from external pin BKP1 \hideinitializer */
sahilmgandhi 18:6a4db94011d3 61 #define PWM_BK1SEL_CPO0 (1UL << PWM_BRKCTL_BK1SEL_Pos) /*!< Brake1 signal source from analog comparator 0 output \hideinitializer */
sahilmgandhi 18:6a4db94011d3 62 #define PWM_BK1SEL_CPO1 (2UL << PWM_BRKCTL_BK1SEL_Pos) /*!< Brake1 signal source from analog comparator 1 output \hideinitializer */
sahilmgandhi 18:6a4db94011d3 63 #define PWM_PERIOD_INT_UNDERFLOW (0) /*!< PWM period interrupt trigger if counter underflow \hideinitializer */
sahilmgandhi 18:6a4db94011d3 64 #define PWM_PERIOD_INT_MATCH_CNR (1UL) /*!< PWM period interrupt trigger if counter match CNR \hideinitializer */
sahilmgandhi 18:6a4db94011d3 65 #define PWM_DUTY_INT_MATCH_CMR_DN (0) /*!< PWM duty interrupt if counter match CNR during down counting \hideinitializer */
sahilmgandhi 18:6a4db94011d3 66 #define PWM_DUTY_INT_MATCH_CMR_UP (0x100UL) /*!< PWM duty interrupt if counter match CNR during up counting \hideinitializer */
sahilmgandhi 18:6a4db94011d3 67 #define PWM_FALLING_LATCH_INT_ENABLE (0x1000000UL) /*!< PWM falling latch interrupt enable \hideinitializer */
sahilmgandhi 18:6a4db94011d3 68 #define PWM_RISING_LATCH_INT_ENABLE (0x10000UL) /*!< PWM rising latch interrupt enable \hideinitializer */
sahilmgandhi 18:6a4db94011d3 69 #define PWM_RISING_FALLING_LATCH_INT_ENABLE (0x1010000UL) /*!< PWM rising latch interrupt enable \hideinitializer */
sahilmgandhi 18:6a4db94011d3 70 #define PWM_FALLING_LATCH_INT_FLAG (PWM_FALLING_LATCH_INT_ENABLE) /*!< PWM falling latch condition happened \hideinitializer */
sahilmgandhi 18:6a4db94011d3 71 #define PWM_RISING_LATCH_INT_FLAG (PWM_RISING_LATCH_INT_ENABLE) /*!< PWM rising latch condition happened \hideinitializer */
sahilmgandhi 18:6a4db94011d3 72 #define PWM_RISING_FALLING_LATCH_INT_FLAG (PWM_RISING_FALLING_LATCH_INT_ENABLE) /*!< PWM rising latch condition happened \hideinitializer */
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 /*@}*/ /* end of group NUC472_442_PWM_EXPORTED_CONSTANTS */
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 /** @addtogroup NUC472_442_PWM_EXPORTED_FUNCTIONS PWM Exported Functions
sahilmgandhi 18:6a4db94011d3 78 @{
sahilmgandhi 18:6a4db94011d3 79 */
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 /**
sahilmgandhi 18:6a4db94011d3 82 * @brief This macro enable complementary mode
sahilmgandhi 18:6a4db94011d3 83 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 84 * @return None
sahilmgandhi 18:6a4db94011d3 85 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 86 */
sahilmgandhi 18:6a4db94011d3 87 #define PWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL = (pwm)->CTL | PWM_CTL_OUTMODE_Msk)
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 /**
sahilmgandhi 18:6a4db94011d3 90 * @brief This macro disable complementary mode, and enable independent mode.
sahilmgandhi 18:6a4db94011d3 91 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 92 * @return None
sahilmgandhi 18:6a4db94011d3 93 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 94 */
sahilmgandhi 18:6a4db94011d3 95 #define PWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL = (pwm)->CTL & ~PWM_CTL_OUTMODE_Msk)
sahilmgandhi 18:6a4db94011d3 96
sahilmgandhi 18:6a4db94011d3 97 /**
sahilmgandhi 18:6a4db94011d3 98 * @brief This macro enable group mode
sahilmgandhi 18:6a4db94011d3 99 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 100 * @return None
sahilmgandhi 18:6a4db94011d3 101 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 102 */
sahilmgandhi 18:6a4db94011d3 103 #define PWM_ENABLE_GROUP_MODE(pwm) ((pwm)->CTL = (pwm)->CTL | PWM_CTL_GROUPEN_Msk)
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105 /**
sahilmgandhi 18:6a4db94011d3 106 * @brief This macro disable group mode
sahilmgandhi 18:6a4db94011d3 107 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 108 * @return None
sahilmgandhi 18:6a4db94011d3 109 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 110 */
sahilmgandhi 18:6a4db94011d3 111 #define PWM_DISABLE_GROUP_MODE(pwm) ((pwm)->CTL = (pwm)->CTL & ~PWM_CTL_GROUPEN_Msk)
sahilmgandhi 18:6a4db94011d3 112
sahilmgandhi 18:6a4db94011d3 113 /**
sahilmgandhi 18:6a4db94011d3 114 * @brief This macro enable synchronous mode
sahilmgandhi 18:6a4db94011d3 115 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 116 * @return None
sahilmgandhi 18:6a4db94011d3 117 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 118 */
sahilmgandhi 18:6a4db94011d3 119 #define PWM_ENABLE_SYNC_MODE(pwm) ((pwm)->CTL = (pwm)->CTL | PWM_CTL_SYNCEN_Msk)
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 /**
sahilmgandhi 18:6a4db94011d3 122 * @brief This macro disable synchronous mode, and enable independent mode.
sahilmgandhi 18:6a4db94011d3 123 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 124 * @return None
sahilmgandhi 18:6a4db94011d3 125 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 126 */
sahilmgandhi 18:6a4db94011d3 127 #define PWM_DISABLE_SYNC_MODE(pwm) ((pwm)->CTL = (pwm)->CTL & ~PWM_CTL_SYNCEN_Msk)
sahilmgandhi 18:6a4db94011d3 128
sahilmgandhi 18:6a4db94011d3 129 /**
sahilmgandhi 18:6a4db94011d3 130 * @brief This macro enable output inverter of specified channel(s)
sahilmgandhi 18:6a4db94011d3 131 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 132 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
sahilmgandhi 18:6a4db94011d3 133 * Bit 0 represents channel 0, bit 1 represents channel 1...
sahilmgandhi 18:6a4db94011d3 134 * @return None
sahilmgandhi 18:6a4db94011d3 135 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 136 */
sahilmgandhi 18:6a4db94011d3 137 #define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) ((pwm)->CTL = (((pwm)->CTL & ~PWM_CTL_PINV_Msk) | ((u32ChannelMask) << PWM_CTL_PINV_Pos)))
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139 /**
sahilmgandhi 18:6a4db94011d3 140 * @brief This macro get captured rising data
sahilmgandhi 18:6a4db94011d3 141 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 142 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 143 * @return None
sahilmgandhi 18:6a4db94011d3 144 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 145 */
sahilmgandhi 18:6a4db94011d3 146 #define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&(pwm)->RCAPDAT0 + 2 * (u32ChannelNum)))
sahilmgandhi 18:6a4db94011d3 147
sahilmgandhi 18:6a4db94011d3 148 /**
sahilmgandhi 18:6a4db94011d3 149 * @brief This macro get captured falling data
sahilmgandhi 18:6a4db94011d3 150 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 151 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 152 * @return None
sahilmgandhi 18:6a4db94011d3 153 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 154 */
sahilmgandhi 18:6a4db94011d3 155 #define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&(pwm)->FCAPDAT0 + 2 * (u32ChannelNum)))
sahilmgandhi 18:6a4db94011d3 156
sahilmgandhi 18:6a4db94011d3 157 /**
sahilmgandhi 18:6a4db94011d3 158 * @brief This macro mask output output logic to high or low
sahilmgandhi 18:6a4db94011d3 159 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 160 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
sahilmgandhi 18:6a4db94011d3 161 * Bit 0 represents channel 0, bit 1 represents channel 1...
sahilmgandhi 18:6a4db94011d3 162 * @param[in] u32LevelMask Output logic to high or low
sahilmgandhi 18:6a4db94011d3 163 * @return None
sahilmgandhi 18:6a4db94011d3 164 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 165 */
sahilmgandhi 18:6a4db94011d3 166 #define PWM_MASK_OUTPUT(pwm, u32ChannelMask, u32LevelMask) ((pwm)->MSKEN |= (u32ChannelMask))
sahilmgandhi 18:6a4db94011d3 167
sahilmgandhi 18:6a4db94011d3 168 /**
sahilmgandhi 18:6a4db94011d3 169 * @brief This macro set the prescaler of the selected channel
sahilmgandhi 18:6a4db94011d3 170 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 171 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 172 * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFF
sahilmgandhi 18:6a4db94011d3 173 * @return None
sahilmgandhi 18:6a4db94011d3 174 * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed,
sahilmgandhi 18:6a4db94011d3 175 * channel 1 will also be affected.
sahilmgandhi 18:6a4db94011d3 176 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 177 */
sahilmgandhi 18:6a4db94011d3 178 #define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) \
sahilmgandhi 18:6a4db94011d3 179 (pwm->CLKPSC = ((pwm)->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8)))
sahilmgandhi 18:6a4db94011d3 180
sahilmgandhi 18:6a4db94011d3 181 /**
sahilmgandhi 18:6a4db94011d3 182 * @brief This macro set the divider of the selected channel
sahilmgandhi 18:6a4db94011d3 183 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 184 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 185 * @param[in] u32Divider Clock divider of specified channel. Valid values are
sahilmgandhi 18:6a4db94011d3 186 * - \ref PWM_CLK_DIV_1
sahilmgandhi 18:6a4db94011d3 187 * - \ref PWM_CLK_DIV_2
sahilmgandhi 18:6a4db94011d3 188 * - \ref PWM_CLK_DIV_4
sahilmgandhi 18:6a4db94011d3 189 * - \ref PWM_CLK_DIV_8
sahilmgandhi 18:6a4db94011d3 190 * - \ref PWM_CLK_DIV_16
sahilmgandhi 18:6a4db94011d3 191 * @return None
sahilmgandhi 18:6a4db94011d3 192 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 193 */
sahilmgandhi 18:6a4db94011d3 194 #define PWM_SET_DIVIDER(pwm, u32ChannelNum, u32Divider) \
sahilmgandhi 18:6a4db94011d3 195 ((pwm)->CLKDIV = ((pwm)->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << ((u32ChannelNum) * 4))) | ((u32Divider) << ((u32ChannelNum) * 4)))
sahilmgandhi 18:6a4db94011d3 196
sahilmgandhi 18:6a4db94011d3 197 /**
sahilmgandhi 18:6a4db94011d3 198 * @brief This macro set the duty of the selected channel
sahilmgandhi 18:6a4db94011d3 199 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 200 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 201 * @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF
sahilmgandhi 18:6a4db94011d3 202 * @return None
sahilmgandhi 18:6a4db94011d3 203 * @note This new setting will take effect on next PWM period
sahilmgandhi 18:6a4db94011d3 204 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 205 */
sahilmgandhi 18:6a4db94011d3 206 #define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) ((pwm)->CMPDAT[(u32ChannelNum)] = (u32CMR))
sahilmgandhi 18:6a4db94011d3 207
sahilmgandhi 18:6a4db94011d3 208 /**
sahilmgandhi 18:6a4db94011d3 209 * @brief This macro set the period of the selected channel
sahilmgandhi 18:6a4db94011d3 210 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 211 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 212 * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
sahilmgandhi 18:6a4db94011d3 213 * @return None
sahilmgandhi 18:6a4db94011d3 214 * @note This new setting will take effect on next PWM period
sahilmgandhi 18:6a4db94011d3 215 * @note PWM counter will stop if period length set to 0
sahilmgandhi 18:6a4db94011d3 216 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 217 */
sahilmgandhi 18:6a4db94011d3 218 #define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) ((pwm)->PERIOD[(u32ChannelNum)] = (u32CNR))
sahilmgandhi 18:6a4db94011d3 219
sahilmgandhi 18:6a4db94011d3 220 /**
sahilmgandhi 18:6a4db94011d3 221 * @brief This macro set the PWM aligned type
sahilmgandhi 18:6a4db94011d3 222 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 223 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
sahilmgandhi 18:6a4db94011d3 224 * Bit 0 represents channel 0, bit 1 represents channel 1...
sahilmgandhi 18:6a4db94011d3 225 * @param[in] u32AlignedType PWM aligned type, valid values are:
sahilmgandhi 18:6a4db94011d3 226 * - \ref PWM_EDGE_ALIGNED
sahilmgandhi 18:6a4db94011d3 227 * - \ref PWM_CENTER_ALIGNED
sahilmgandhi 18:6a4db94011d3 228 * @return None
sahilmgandhi 18:6a4db94011d3 229 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 230 */
sahilmgandhi 18:6a4db94011d3 231 #define PWM_SET_ALIGNED_TYPE(pwm, u32ChannelMask, u32AlignedType) \
sahilmgandhi 18:6a4db94011d3 232 do { \
sahilmgandhi 18:6a4db94011d3 233 (pwm)->CTL = ((pwm)->CTL & ~PWM_CTL_CNTTYPE_Msk); \
sahilmgandhi 18:6a4db94011d3 234 if ((u32AlignedType) == PWM_CENTER_ALIGNED) \
sahilmgandhi 18:6a4db94011d3 235 (pwm)->CTL = ((pwm)->CTL | ((u32ChannelMask) << PWM_CTL_CNTTYPE_Pos)); \
sahilmgandhi 18:6a4db94011d3 236 } while(0)
sahilmgandhi 18:6a4db94011d3 237
sahilmgandhi 18:6a4db94011d3 238
sahilmgandhi 18:6a4db94011d3 239 uint32_t PWM_ConfigOutputChannel(PWM_T *pwm,
sahilmgandhi 18:6a4db94011d3 240 uint32_t u32ChannelNum,
sahilmgandhi 18:6a4db94011d3 241 uint32_t u32Frequency,
sahilmgandhi 18:6a4db94011d3 242 uint32_t u32DutyCycle);
sahilmgandhi 18:6a4db94011d3 243 uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm,
sahilmgandhi 18:6a4db94011d3 244 uint32_t u32ChannelNum,
sahilmgandhi 18:6a4db94011d3 245 uint32_t u32Frequency,
sahilmgandhi 18:6a4db94011d3 246 uint32_t u32DutyCycle,
sahilmgandhi 18:6a4db94011d3 247 uint32_t u32Frequency2);
sahilmgandhi 18:6a4db94011d3 248 uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
sahilmgandhi 18:6a4db94011d3 249 uint32_t u32ChannelNum,
sahilmgandhi 18:6a4db94011d3 250 uint32_t u32UnitTimeNsec,
sahilmgandhi 18:6a4db94011d3 251 uint32_t u32CaptureEdge);
sahilmgandhi 18:6a4db94011d3 252 void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask);
sahilmgandhi 18:6a4db94011d3 253 void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask);
sahilmgandhi 18:6a4db94011d3 254 void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask);
sahilmgandhi 18:6a4db94011d3 255 void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
sahilmgandhi 18:6a4db94011d3 256 void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 257 void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
sahilmgandhi 18:6a4db94011d3 258 uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 259 void PWM_EnableFaultBrake(PWM_T *pwm,
sahilmgandhi 18:6a4db94011d3 260 uint32_t u32ChannelMask,
sahilmgandhi 18:6a4db94011d3 261 uint32_t u32LevelMask,
sahilmgandhi 18:6a4db94011d3 262 uint32_t u32BrakeSource);
sahilmgandhi 18:6a4db94011d3 263 void PWM_ClearFaultBrakeFlag(PWM_T *pwm, uint32_t u32BrakeSource);
sahilmgandhi 18:6a4db94011d3 264 void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
sahilmgandhi 18:6a4db94011d3 265 void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
sahilmgandhi 18:6a4db94011d3 266 void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
sahilmgandhi 18:6a4db94011d3 267 void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
sahilmgandhi 18:6a4db94011d3 268 void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration);
sahilmgandhi 18:6a4db94011d3 269 void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 270 void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
sahilmgandhi 18:6a4db94011d3 271 void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
sahilmgandhi 18:6a4db94011d3 272 void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
sahilmgandhi 18:6a4db94011d3 273 uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 274 void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
sahilmgandhi 18:6a4db94011d3 275 void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 276 void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 277 uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 278 void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
sahilmgandhi 18:6a4db94011d3 279 void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
sahilmgandhi 18:6a4db94011d3 280 void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
sahilmgandhi 18:6a4db94011d3 281 uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
sahilmgandhi 18:6a4db94011d3 282 void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
sahilmgandhi 18:6a4db94011d3 283 void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 284 void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 285 uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 286
sahilmgandhi 18:6a4db94011d3 287
sahilmgandhi 18:6a4db94011d3 288
sahilmgandhi 18:6a4db94011d3 289 /*@}*/ /* end of group NUC472_442_PWM_EXPORTED_FUNCTIONS */
sahilmgandhi 18:6a4db94011d3 290
sahilmgandhi 18:6a4db94011d3 291 /*@}*/ /* end of group NUC472_442_PWM_Driver */
sahilmgandhi 18:6a4db94011d3 292
sahilmgandhi 18:6a4db94011d3 293 /*@}*/ /* end of group NUC472_442_Device_Driver */
sahilmgandhi 18:6a4db94011d3 294
sahilmgandhi 18:6a4db94011d3 295 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 296 }
sahilmgandhi 18:6a4db94011d3 297 #endif
sahilmgandhi 18:6a4db94011d3 298
sahilmgandhi 18:6a4db94011d3 299 #endif //__PWM_H__
sahilmgandhi 18:6a4db94011d3 300
sahilmgandhi 18:6a4db94011d3 301 /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/