MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_pwm.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file PWM.c
sahilmgandhi 18:6a4db94011d3 3 * @version V1.00
sahilmgandhi 18:6a4db94011d3 4 * $Revision: 26 $
sahilmgandhi 18:6a4db94011d3 5 * $Date: 15/11/18 2:34p $
sahilmgandhi 18:6a4db94011d3 6 * @brief NUC472/NUC442 PWM driver source file
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * @note
sahilmgandhi 18:6a4db94011d3 9 * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
sahilmgandhi 18:6a4db94011d3 10 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 11 #include "NUC472_442.h"
sahilmgandhi 18:6a4db94011d3 12
sahilmgandhi 18:6a4db94011d3 13 /** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
sahilmgandhi 18:6a4db94011d3 14 @{
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16
sahilmgandhi 18:6a4db94011d3 17 /** @addtogroup NUC472_442_PWM_Driver PWM Driver
sahilmgandhi 18:6a4db94011d3 18 @{
sahilmgandhi 18:6a4db94011d3 19 */
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21
sahilmgandhi 18:6a4db94011d3 22 /** @addtogroup NUC472_442_PWM_EXPORTED_FUNCTIONS PWM Exported Functions
sahilmgandhi 18:6a4db94011d3 23 @{
sahilmgandhi 18:6a4db94011d3 24 */
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 /**
sahilmgandhi 18:6a4db94011d3 27 * @brief This function config PWM generator and get the nearest frequency in edge aligned auto-reload mode
sahilmgandhi 18:6a4db94011d3 28 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 29 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 30 * @param[in] u32Frequency Target generator frequency
sahilmgandhi 18:6a4db94011d3 31 * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
sahilmgandhi 18:6a4db94011d3 32 * @return Nearest frequency clock in nano second
sahilmgandhi 18:6a4db94011d3 33 * @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
sahilmgandhi 18:6a4db94011d3 34 * existing frequency of other channel.
sahilmgandhi 18:6a4db94011d3 35 */
sahilmgandhi 18:6a4db94011d3 36 uint32_t PWM_ConfigOutputChannel (PWM_T *pwm,
sahilmgandhi 18:6a4db94011d3 37 uint32_t u32ChannelNum,
sahilmgandhi 18:6a4db94011d3 38 uint32_t u32Frequency,
sahilmgandhi 18:6a4db94011d3 39 uint32_t u32DutyCycle)
sahilmgandhi 18:6a4db94011d3 40 {
sahilmgandhi 18:6a4db94011d3 41 return PWM_ConfigOutputChannel2(pwm, u32ChannelNum, u32Frequency, u32DutyCycle, 1);
sahilmgandhi 18:6a4db94011d3 42 }
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 /**
sahilmgandhi 18:6a4db94011d3 45 * @brief This function config PWM generator and get the nearest frequency in edge aligned auto-reload mode
sahilmgandhi 18:6a4db94011d3 46 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 47 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 48 * @param[in] u32Frequency Target generator frequency = u32Frequency / u32Frequency2
sahilmgandhi 18:6a4db94011d3 49 * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
sahilmgandhi 18:6a4db94011d3 50 * @param[in] u32Frequency2 Target generator frequency = u32Frequency / u32Frequency2
sahilmgandhi 18:6a4db94011d3 51 * @return Nearest frequency clock in nano second
sahilmgandhi 18:6a4db94011d3 52 * @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
sahilmgandhi 18:6a4db94011d3 53 * existing frequency of other channel.
sahilmgandhi 18:6a4db94011d3 54 */
sahilmgandhi 18:6a4db94011d3 55 uint32_t PWM_ConfigOutputChannel2 (PWM_T *pwm,
sahilmgandhi 18:6a4db94011d3 56 uint32_t u32ChannelNum,
sahilmgandhi 18:6a4db94011d3 57 uint32_t u32Frequency,
sahilmgandhi 18:6a4db94011d3 58 uint32_t u32DutyCycle,
sahilmgandhi 18:6a4db94011d3 59 uint32_t u32Frequency2)
sahilmgandhi 18:6a4db94011d3 60 {
sahilmgandhi 18:6a4db94011d3 61 uint32_t i;
sahilmgandhi 18:6a4db94011d3 62 uint32_t u32PWM_CLock = __HIRC;
sahilmgandhi 18:6a4db94011d3 63 uint8_t u8Divider = 1, u8Prescale = 0xFF;
sahilmgandhi 18:6a4db94011d3 64 uint16_t u16CNR = 0xFFFF;
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66 if (pwm == PWM0) {
sahilmgandhi 18:6a4db94011d3 67 if (u32ChannelNum < 2) {
sahilmgandhi 18:6a4db94011d3 68 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 0)
sahilmgandhi 18:6a4db94011d3 69 u32PWM_CLock = __HXT;
sahilmgandhi 18:6a4db94011d3 70 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 1)
sahilmgandhi 18:6a4db94011d3 71 u32PWM_CLock = __LXT;
sahilmgandhi 18:6a4db94011d3 72 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 2)
sahilmgandhi 18:6a4db94011d3 73 u32PWM_CLock = CLK_GetPCLKFreq();
sahilmgandhi 18:6a4db94011d3 74 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 3)
sahilmgandhi 18:6a4db94011d3 75 u32PWM_CLock = __HIRC;
sahilmgandhi 18:6a4db94011d3 76 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 4)
sahilmgandhi 18:6a4db94011d3 77 u32PWM_CLock = __LIRC;
sahilmgandhi 18:6a4db94011d3 78 } else if (u32ChannelNum < 4) {
sahilmgandhi 18:6a4db94011d3 79 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (0 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
sahilmgandhi 18:6a4db94011d3 80 u32PWM_CLock = __HXT;
sahilmgandhi 18:6a4db94011d3 81 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (1 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
sahilmgandhi 18:6a4db94011d3 82 u32PWM_CLock = __LXT;
sahilmgandhi 18:6a4db94011d3 83 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (2 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
sahilmgandhi 18:6a4db94011d3 84 u32PWM_CLock = CLK_GetPCLKFreq();
sahilmgandhi 18:6a4db94011d3 85 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (3 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
sahilmgandhi 18:6a4db94011d3 86 u32PWM_CLock = __HIRC;
sahilmgandhi 18:6a4db94011d3 87 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (4 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
sahilmgandhi 18:6a4db94011d3 88 u32PWM_CLock = __LIRC;
sahilmgandhi 18:6a4db94011d3 89 } else if (u32ChannelNum < 6) {
sahilmgandhi 18:6a4db94011d3 90 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (0 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
sahilmgandhi 18:6a4db94011d3 91 u32PWM_CLock = __HXT;
sahilmgandhi 18:6a4db94011d3 92 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (1 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
sahilmgandhi 18:6a4db94011d3 93 u32PWM_CLock = __LXT;
sahilmgandhi 18:6a4db94011d3 94 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (2 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
sahilmgandhi 18:6a4db94011d3 95 u32PWM_CLock = CLK_GetPCLKFreq();
sahilmgandhi 18:6a4db94011d3 96 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (3 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
sahilmgandhi 18:6a4db94011d3 97 u32PWM_CLock = __HIRC;
sahilmgandhi 18:6a4db94011d3 98 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (4 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
sahilmgandhi 18:6a4db94011d3 99 u32PWM_CLock = __LIRC;
sahilmgandhi 18:6a4db94011d3 100 }
sahilmgandhi 18:6a4db94011d3 101 } else if (pwm == PWM1) {
sahilmgandhi 18:6a4db94011d3 102 if (u32ChannelNum < 2) {
sahilmgandhi 18:6a4db94011d3 103 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
sahilmgandhi 18:6a4db94011d3 104 u32PWM_CLock = __HXT;
sahilmgandhi 18:6a4db94011d3 105 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
sahilmgandhi 18:6a4db94011d3 106 u32PWM_CLock = __LXT;
sahilmgandhi 18:6a4db94011d3 107 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
sahilmgandhi 18:6a4db94011d3 108 u32PWM_CLock = CLK_GetPCLKFreq();
sahilmgandhi 18:6a4db94011d3 109 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
sahilmgandhi 18:6a4db94011d3 110 u32PWM_CLock = __HIRC;
sahilmgandhi 18:6a4db94011d3 111 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
sahilmgandhi 18:6a4db94011d3 112 u32PWM_CLock = __LIRC;
sahilmgandhi 18:6a4db94011d3 113 } else if (u32ChannelNum < 4) {
sahilmgandhi 18:6a4db94011d3 114 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
sahilmgandhi 18:6a4db94011d3 115 u32PWM_CLock = __HXT;
sahilmgandhi 18:6a4db94011d3 116 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
sahilmgandhi 18:6a4db94011d3 117 u32PWM_CLock = __LXT;
sahilmgandhi 18:6a4db94011d3 118 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
sahilmgandhi 18:6a4db94011d3 119 u32PWM_CLock = CLK_GetPCLKFreq();
sahilmgandhi 18:6a4db94011d3 120 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
sahilmgandhi 18:6a4db94011d3 121 u32PWM_CLock = __HIRC;
sahilmgandhi 18:6a4db94011d3 122 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
sahilmgandhi 18:6a4db94011d3 123 u32PWM_CLock = __LIRC;
sahilmgandhi 18:6a4db94011d3 124 } else if (u32ChannelNum < 6) {
sahilmgandhi 18:6a4db94011d3 125 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
sahilmgandhi 18:6a4db94011d3 126 u32PWM_CLock = __HXT;
sahilmgandhi 18:6a4db94011d3 127 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
sahilmgandhi 18:6a4db94011d3 128 u32PWM_CLock = __LXT;
sahilmgandhi 18:6a4db94011d3 129 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
sahilmgandhi 18:6a4db94011d3 130 u32PWM_CLock = CLK_GetPCLKFreq();
sahilmgandhi 18:6a4db94011d3 131 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
sahilmgandhi 18:6a4db94011d3 132 u32PWM_CLock = __HIRC;
sahilmgandhi 18:6a4db94011d3 133 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
sahilmgandhi 18:6a4db94011d3 134 u32PWM_CLock = __LIRC;
sahilmgandhi 18:6a4db94011d3 135 }
sahilmgandhi 18:6a4db94011d3 136 }
sahilmgandhi 18:6a4db94011d3 137
sahilmgandhi 18:6a4db94011d3 138 for(; u8Divider < 17; u8Divider <<= 1) { // clk divider could only be 1, 2, 4, 8, 16
sahilmgandhi 18:6a4db94011d3 139 // Note: Support frequency < 1
sahilmgandhi 18:6a4db94011d3 140 i = (uint64_t) u32PWM_CLock * u32Frequency2 / u32Frequency / u8Divider;
sahilmgandhi 18:6a4db94011d3 141 // If target value is larger than CNR * prescale, need to use a larger divider
sahilmgandhi 18:6a4db94011d3 142 if(i > (0x10000 * 0x100))
sahilmgandhi 18:6a4db94011d3 143 continue;
sahilmgandhi 18:6a4db94011d3 144
sahilmgandhi 18:6a4db94011d3 145 // CNR = 0xFFFF + 1, get a prescaler that CNR value is below 0xFFFF
sahilmgandhi 18:6a4db94011d3 146 u8Prescale = (i + 0xFFFF)/ 0x10000;
sahilmgandhi 18:6a4db94011d3 147
sahilmgandhi 18:6a4db94011d3 148 // u8Prescale must at least be 2, otherwise the output stop
sahilmgandhi 18:6a4db94011d3 149 if(u8Prescale < 3)
sahilmgandhi 18:6a4db94011d3 150 u8Prescale = 2;
sahilmgandhi 18:6a4db94011d3 151
sahilmgandhi 18:6a4db94011d3 152 i /= u8Prescale;
sahilmgandhi 18:6a4db94011d3 153
sahilmgandhi 18:6a4db94011d3 154 if(i <= 0x10000) {
sahilmgandhi 18:6a4db94011d3 155 if(i == 1)
sahilmgandhi 18:6a4db94011d3 156 u16CNR = 1; // Too fast, and PWM cannot generate expected frequency...
sahilmgandhi 18:6a4db94011d3 157 else
sahilmgandhi 18:6a4db94011d3 158 u16CNR = i;
sahilmgandhi 18:6a4db94011d3 159 break;
sahilmgandhi 18:6a4db94011d3 160 }
sahilmgandhi 18:6a4db94011d3 161
sahilmgandhi 18:6a4db94011d3 162 }
sahilmgandhi 18:6a4db94011d3 163 // Store return value here 'cos we're gonna change u8Divider & u8Prescale & u16CNR to the real value to fill into register
sahilmgandhi 18:6a4db94011d3 164 i = u32PWM_CLock / (u8Prescale * u8Divider * u16CNR);
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 u8Prescale -= 1;
sahilmgandhi 18:6a4db94011d3 167 u16CNR -= 1;
sahilmgandhi 18:6a4db94011d3 168 // convert to real register value
sahilmgandhi 18:6a4db94011d3 169 if(u8Divider == 1)
sahilmgandhi 18:6a4db94011d3 170 u8Divider = 4;
sahilmgandhi 18:6a4db94011d3 171 else if (u8Divider == 2)
sahilmgandhi 18:6a4db94011d3 172 u8Divider = 0;
sahilmgandhi 18:6a4db94011d3 173 else if (u8Divider == 4)
sahilmgandhi 18:6a4db94011d3 174 u8Divider = 1;
sahilmgandhi 18:6a4db94011d3 175 else if (u8Divider == 8)
sahilmgandhi 18:6a4db94011d3 176 u8Divider = 2;
sahilmgandhi 18:6a4db94011d3 177 else // 16
sahilmgandhi 18:6a4db94011d3 178 u8Divider = 3;
sahilmgandhi 18:6a4db94011d3 179
sahilmgandhi 18:6a4db94011d3 180 // every two channels share a prescaler
sahilmgandhi 18:6a4db94011d3 181 while((pwm->SBS[u32ChannelNum] & 1) == 1);
sahilmgandhi 18:6a4db94011d3 182 pwm->CLKPSC = (pwm->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << ((u32ChannelNum >> 1) * 8))) | (u8Prescale << ((u32ChannelNum >> 1) * 8));
sahilmgandhi 18:6a4db94011d3 183 pwm->CLKDIV = (pwm->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum));
sahilmgandhi 18:6a4db94011d3 184 pwm->CTL |= 1 << (PWM_CTL_CNTMODE_Pos + u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 185 if(u32DutyCycle == 0)
sahilmgandhi 18:6a4db94011d3 186 pwm->CMPDAT[u32ChannelNum] = 0;
sahilmgandhi 18:6a4db94011d3 187 else
sahilmgandhi 18:6a4db94011d3 188 pwm->CMPDAT[u32ChannelNum] = u32DutyCycle * (u16CNR + 1) / 100 - 1;
sahilmgandhi 18:6a4db94011d3 189 pwm->PERIOD[u32ChannelNum] = u16CNR;
sahilmgandhi 18:6a4db94011d3 190
sahilmgandhi 18:6a4db94011d3 191 return(i);
sahilmgandhi 18:6a4db94011d3 192 }
sahilmgandhi 18:6a4db94011d3 193
sahilmgandhi 18:6a4db94011d3 194 /**
sahilmgandhi 18:6a4db94011d3 195 * @brief This function config PWM capture and get the nearest unit time
sahilmgandhi 18:6a4db94011d3 196 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 197 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 198 * @param[in] u32UnitTimeNsec Unit time of counter
sahilmgandhi 18:6a4db94011d3 199 * @param[in] u32CaptureEdge Condition to latch the counter
sahilmgandhi 18:6a4db94011d3 200 * @return Nearest unit time in nano second
sahilmgandhi 18:6a4db94011d3 201 * @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
sahilmgandhi 18:6a4db94011d3 202 * existing frequency of other channel.
sahilmgandhi 18:6a4db94011d3 203 */
sahilmgandhi 18:6a4db94011d3 204 uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
sahilmgandhi 18:6a4db94011d3 205 uint32_t u32ChannelNum,
sahilmgandhi 18:6a4db94011d3 206 uint32_t u32UnitTimeNsec,
sahilmgandhi 18:6a4db94011d3 207 uint32_t u32CaptureEdge)
sahilmgandhi 18:6a4db94011d3 208 {
sahilmgandhi 18:6a4db94011d3 209 uint32_t i;
sahilmgandhi 18:6a4db94011d3 210 uint32_t u32PWM_CLock = __HIRC;
sahilmgandhi 18:6a4db94011d3 211 uint8_t u8Divider = 1, u8Prescale = 0xFF;
sahilmgandhi 18:6a4db94011d3 212 uint16_t u16CNR = 0xFFFF;
sahilmgandhi 18:6a4db94011d3 213
sahilmgandhi 18:6a4db94011d3 214 if (pwm == PWM0) {
sahilmgandhi 18:6a4db94011d3 215 if (u32ChannelNum < 2) {
sahilmgandhi 18:6a4db94011d3 216 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 0)
sahilmgandhi 18:6a4db94011d3 217 u32PWM_CLock = __HXT;
sahilmgandhi 18:6a4db94011d3 218 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 1)
sahilmgandhi 18:6a4db94011d3 219 u32PWM_CLock = __LXT;
sahilmgandhi 18:6a4db94011d3 220 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 2)
sahilmgandhi 18:6a4db94011d3 221 u32PWM_CLock = CLK_GetPCLKFreq();
sahilmgandhi 18:6a4db94011d3 222 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 3)
sahilmgandhi 18:6a4db94011d3 223 u32PWM_CLock = __HIRC;
sahilmgandhi 18:6a4db94011d3 224 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 4)
sahilmgandhi 18:6a4db94011d3 225 u32PWM_CLock = __LIRC;
sahilmgandhi 18:6a4db94011d3 226 } else if (u32ChannelNum < 4) {
sahilmgandhi 18:6a4db94011d3 227 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (0 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
sahilmgandhi 18:6a4db94011d3 228 u32PWM_CLock = __HXT;
sahilmgandhi 18:6a4db94011d3 229 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (1 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
sahilmgandhi 18:6a4db94011d3 230 u32PWM_CLock = __LXT;
sahilmgandhi 18:6a4db94011d3 231 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (2 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
sahilmgandhi 18:6a4db94011d3 232 u32PWM_CLock = CLK_GetPCLKFreq();
sahilmgandhi 18:6a4db94011d3 233 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (3 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
sahilmgandhi 18:6a4db94011d3 234 u32PWM_CLock = __HIRC;
sahilmgandhi 18:6a4db94011d3 235 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (4 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
sahilmgandhi 18:6a4db94011d3 236 u32PWM_CLock = __LIRC;
sahilmgandhi 18:6a4db94011d3 237 } else if (u32ChannelNum < 6) {
sahilmgandhi 18:6a4db94011d3 238 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (0 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
sahilmgandhi 18:6a4db94011d3 239 u32PWM_CLock = __HXT;
sahilmgandhi 18:6a4db94011d3 240 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (1 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
sahilmgandhi 18:6a4db94011d3 241 u32PWM_CLock = __LXT;
sahilmgandhi 18:6a4db94011d3 242 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (2 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
sahilmgandhi 18:6a4db94011d3 243 u32PWM_CLock = CLK_GetPCLKFreq();
sahilmgandhi 18:6a4db94011d3 244 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (3 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
sahilmgandhi 18:6a4db94011d3 245 u32PWM_CLock = __HIRC;
sahilmgandhi 18:6a4db94011d3 246 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (4 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
sahilmgandhi 18:6a4db94011d3 247 u32PWM_CLock = __LIRC;
sahilmgandhi 18:6a4db94011d3 248 }
sahilmgandhi 18:6a4db94011d3 249 } else if (pwm == PWM1) {
sahilmgandhi 18:6a4db94011d3 250 if (u32ChannelNum < 2) {
sahilmgandhi 18:6a4db94011d3 251 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
sahilmgandhi 18:6a4db94011d3 252 u32PWM_CLock = __HXT;
sahilmgandhi 18:6a4db94011d3 253 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
sahilmgandhi 18:6a4db94011d3 254 u32PWM_CLock = __LXT;
sahilmgandhi 18:6a4db94011d3 255 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
sahilmgandhi 18:6a4db94011d3 256 u32PWM_CLock = CLK_GetPCLKFreq();
sahilmgandhi 18:6a4db94011d3 257 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
sahilmgandhi 18:6a4db94011d3 258 u32PWM_CLock = __HIRC;
sahilmgandhi 18:6a4db94011d3 259 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
sahilmgandhi 18:6a4db94011d3 260 u32PWM_CLock = __LIRC;
sahilmgandhi 18:6a4db94011d3 261 } else if (u32ChannelNum < 4) {
sahilmgandhi 18:6a4db94011d3 262 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
sahilmgandhi 18:6a4db94011d3 263 u32PWM_CLock = __HXT;
sahilmgandhi 18:6a4db94011d3 264 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
sahilmgandhi 18:6a4db94011d3 265 u32PWM_CLock = __LXT;
sahilmgandhi 18:6a4db94011d3 266 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
sahilmgandhi 18:6a4db94011d3 267 u32PWM_CLock = CLK_GetPCLKFreq();
sahilmgandhi 18:6a4db94011d3 268 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
sahilmgandhi 18:6a4db94011d3 269 u32PWM_CLock = __HIRC;
sahilmgandhi 18:6a4db94011d3 270 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
sahilmgandhi 18:6a4db94011d3 271 u32PWM_CLock = __LIRC;
sahilmgandhi 18:6a4db94011d3 272 } else if (u32ChannelNum < 6) {
sahilmgandhi 18:6a4db94011d3 273 if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
sahilmgandhi 18:6a4db94011d3 274 u32PWM_CLock = __HXT;
sahilmgandhi 18:6a4db94011d3 275 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
sahilmgandhi 18:6a4db94011d3 276 u32PWM_CLock = __LXT;
sahilmgandhi 18:6a4db94011d3 277 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
sahilmgandhi 18:6a4db94011d3 278 u32PWM_CLock = CLK_GetPCLKFreq();
sahilmgandhi 18:6a4db94011d3 279 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
sahilmgandhi 18:6a4db94011d3 280 u32PWM_CLock = __HIRC;
sahilmgandhi 18:6a4db94011d3 281 else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
sahilmgandhi 18:6a4db94011d3 282 u32PWM_CLock = __LIRC;
sahilmgandhi 18:6a4db94011d3 283 }
sahilmgandhi 18:6a4db94011d3 284 }
sahilmgandhi 18:6a4db94011d3 285
sahilmgandhi 18:6a4db94011d3 286 for(; u8Divider < 17; u8Divider <<= 1) { // clk divider could only be 1, 2, 4, 8, 16
sahilmgandhi 18:6a4db94011d3 287 i = ((u32PWM_CLock / u8Divider) * u32UnitTimeNsec) / 1000000000;
sahilmgandhi 18:6a4db94011d3 288
sahilmgandhi 18:6a4db94011d3 289 // If target value is larger than 0xFF, need to use a larger divider
sahilmgandhi 18:6a4db94011d3 290 if(i > (0xFF))
sahilmgandhi 18:6a4db94011d3 291 continue;
sahilmgandhi 18:6a4db94011d3 292
sahilmgandhi 18:6a4db94011d3 293 u8Prescale = i;
sahilmgandhi 18:6a4db94011d3 294
sahilmgandhi 18:6a4db94011d3 295 // u8Prescale must at least be 2, otherwise the output stop
sahilmgandhi 18:6a4db94011d3 296 if(u8Prescale < 3)
sahilmgandhi 18:6a4db94011d3 297 u8Prescale = 2;
sahilmgandhi 18:6a4db94011d3 298
sahilmgandhi 18:6a4db94011d3 299 break;
sahilmgandhi 18:6a4db94011d3 300 }
sahilmgandhi 18:6a4db94011d3 301
sahilmgandhi 18:6a4db94011d3 302 // Store return value here 'cos we're gonna change u8Divider & u8Prescale & u16CNR to the real value to fill into register
sahilmgandhi 18:6a4db94011d3 303 i = (u8Prescale * u8Divider) * 1000000000/ u32PWM_CLock;
sahilmgandhi 18:6a4db94011d3 304
sahilmgandhi 18:6a4db94011d3 305 u8Prescale -= 1;
sahilmgandhi 18:6a4db94011d3 306 u16CNR -= 1;
sahilmgandhi 18:6a4db94011d3 307 // convert to real register value
sahilmgandhi 18:6a4db94011d3 308 if(u8Divider == 1)
sahilmgandhi 18:6a4db94011d3 309 u8Divider = 4;
sahilmgandhi 18:6a4db94011d3 310 else if (u8Divider == 2)
sahilmgandhi 18:6a4db94011d3 311 u8Divider = 0;
sahilmgandhi 18:6a4db94011d3 312 else if (u8Divider == 4)
sahilmgandhi 18:6a4db94011d3 313 u8Divider = 1;
sahilmgandhi 18:6a4db94011d3 314 else if (u8Divider == 8)
sahilmgandhi 18:6a4db94011d3 315 u8Divider = 2;
sahilmgandhi 18:6a4db94011d3 316 else // 16
sahilmgandhi 18:6a4db94011d3 317 u8Divider = 3;
sahilmgandhi 18:6a4db94011d3 318
sahilmgandhi 18:6a4db94011d3 319 // every two channels share a prescaler
sahilmgandhi 18:6a4db94011d3 320 while((pwm->SBS[u32ChannelNum] & 1) == 1);
sahilmgandhi 18:6a4db94011d3 321 pwm->CLKPSC = (pwm->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << ((u32ChannelNum >> 1) * 8))) | (u8Prescale << ((u32ChannelNum >> 1) * 8));
sahilmgandhi 18:6a4db94011d3 322 pwm->CLKDIV = (pwm->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum));
sahilmgandhi 18:6a4db94011d3 323 pwm->CTL |= 1 << (PWM_CTL_CNTMODE_Pos + u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 324 pwm->PERIOD[u32ChannelNum] = u16CNR;
sahilmgandhi 18:6a4db94011d3 325
sahilmgandhi 18:6a4db94011d3 326 return(i);
sahilmgandhi 18:6a4db94011d3 327 }
sahilmgandhi 18:6a4db94011d3 328
sahilmgandhi 18:6a4db94011d3 329 /**
sahilmgandhi 18:6a4db94011d3 330 * @brief This function start PWM module
sahilmgandhi 18:6a4db94011d3 331 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 332 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
sahilmgandhi 18:6a4db94011d3 333 * Bit 0 is channel 0, bit 1 is channel 1...
sahilmgandhi 18:6a4db94011d3 334 * @return None
sahilmgandhi 18:6a4db94011d3 335 */
sahilmgandhi 18:6a4db94011d3 336 void PWM_Start (PWM_T *pwm, uint32_t u32ChannelMask)
sahilmgandhi 18:6a4db94011d3 337 {
sahilmgandhi 18:6a4db94011d3 338 pwm->CNTEN |= u32ChannelMask;
sahilmgandhi 18:6a4db94011d3 339 }
sahilmgandhi 18:6a4db94011d3 340
sahilmgandhi 18:6a4db94011d3 341 /**
sahilmgandhi 18:6a4db94011d3 342 * @brief This function stop PWM module
sahilmgandhi 18:6a4db94011d3 343 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 344 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
sahilmgandhi 18:6a4db94011d3 345 * Bit 0 is channel 0, bit 1 is channel 1...
sahilmgandhi 18:6a4db94011d3 346 * @return None
sahilmgandhi 18:6a4db94011d3 347 */
sahilmgandhi 18:6a4db94011d3 348 void PWM_Stop (PWM_T *pwm, uint32_t u32ChannelMask)
sahilmgandhi 18:6a4db94011d3 349 {
sahilmgandhi 18:6a4db94011d3 350 uint32_t i;
sahilmgandhi 18:6a4db94011d3 351 for(i = 0; i < PWM_CHANNEL_NUM; i ++) {
sahilmgandhi 18:6a4db94011d3 352 if(u32ChannelMask & (1 << i)) {
sahilmgandhi 18:6a4db94011d3 353 *(__IO uint32_t *) (&pwm->CNTEN + 1 * i) = 0;
sahilmgandhi 18:6a4db94011d3 354 }
sahilmgandhi 18:6a4db94011d3 355 }
sahilmgandhi 18:6a4db94011d3 356
sahilmgandhi 18:6a4db94011d3 357 }
sahilmgandhi 18:6a4db94011d3 358
sahilmgandhi 18:6a4db94011d3 359 /**
sahilmgandhi 18:6a4db94011d3 360 * @brief This function stop PWM generation immediately by clear channel enable bit
sahilmgandhi 18:6a4db94011d3 361 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 362 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
sahilmgandhi 18:6a4db94011d3 363 * Bit 0 is channel 0, bit 1 is channel 1...
sahilmgandhi 18:6a4db94011d3 364 * @return None
sahilmgandhi 18:6a4db94011d3 365 */
sahilmgandhi 18:6a4db94011d3 366 void PWM_ForceStop (PWM_T *pwm, uint32_t u32ChannelMask)
sahilmgandhi 18:6a4db94011d3 367 {
sahilmgandhi 18:6a4db94011d3 368 pwm->CNTEN &= ~u32ChannelMask;
sahilmgandhi 18:6a4db94011d3 369 }
sahilmgandhi 18:6a4db94011d3 370
sahilmgandhi 18:6a4db94011d3 371 /**
sahilmgandhi 18:6a4db94011d3 372 * @brief This function enable selected channel to trigger ADC
sahilmgandhi 18:6a4db94011d3 373 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 374 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 375 * @param[in] u32Condition The condition to trigger ADC. Combination of following conditions:
sahilmgandhi 18:6a4db94011d3 376 * - \ref PWM_TRIGGER_ADC_PERIOD_POINT
sahilmgandhi 18:6a4db94011d3 377 * - \ref PWM_TRIGGER_ADC_CENTER_POINT
sahilmgandhi 18:6a4db94011d3 378 * - \ref PWM_TRIGGER_ADC_FALLING_EDGE_POINT
sahilmgandhi 18:6a4db94011d3 379 * - \ref PWM_TRIGGER_ADC_RISING_EDGE_POINT
sahilmgandhi 18:6a4db94011d3 380 * @return None
sahilmgandhi 18:6a4db94011d3 381 */
sahilmgandhi 18:6a4db94011d3 382 void PWM_EnableADCTrigger (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
sahilmgandhi 18:6a4db94011d3 383 {
sahilmgandhi 18:6a4db94011d3 384 pwm->TRGADCTL = (pwm->TRGADCTL & ~((PWM_TRIGGER_ADC_PERIOD_POINT |
sahilmgandhi 18:6a4db94011d3 385 PWM_TRIGGER_ADC_CENTER_POINT |
sahilmgandhi 18:6a4db94011d3 386 PWM_TRIGGER_ADC_FALLING_EDGE_POINT |
sahilmgandhi 18:6a4db94011d3 387 PWM_TRIGGER_ADC_RISING_EDGE_POINT ) << (1 * u32ChannelNum))) | (u32Condition << (1 * u32ChannelNum));
sahilmgandhi 18:6a4db94011d3 388 }
sahilmgandhi 18:6a4db94011d3 389
sahilmgandhi 18:6a4db94011d3 390 /**
sahilmgandhi 18:6a4db94011d3 391 * @brief This function disable selected channel to trigger ADC
sahilmgandhi 18:6a4db94011d3 392 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 393 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 394 * @return None
sahilmgandhi 18:6a4db94011d3 395 */
sahilmgandhi 18:6a4db94011d3 396 void PWM_DisableADCTrigger (PWM_T *pwm, uint32_t u32ChannelNum)
sahilmgandhi 18:6a4db94011d3 397 {
sahilmgandhi 18:6a4db94011d3 398 pwm->TRGADCTL = (pwm->TRGADCTL & ~((PWM_TRIGGER_ADC_PERIOD_POINT |
sahilmgandhi 18:6a4db94011d3 399 PWM_TRIGGER_ADC_CENTER_POINT |
sahilmgandhi 18:6a4db94011d3 400 PWM_TRIGGER_ADC_FALLING_EDGE_POINT |
sahilmgandhi 18:6a4db94011d3 401 PWM_TRIGGER_ADC_RISING_EDGE_POINT ) << (1 * u32ChannelNum)));
sahilmgandhi 18:6a4db94011d3 402 }
sahilmgandhi 18:6a4db94011d3 403
sahilmgandhi 18:6a4db94011d3 404 /**
sahilmgandhi 18:6a4db94011d3 405 * @brief This function clear selected channel trigger ADC flag
sahilmgandhi 18:6a4db94011d3 406 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 407 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 408 * @param[in] u32Condition PWM triggered ADC flag to be cleared. A combination of following flags:
sahilmgandhi 18:6a4db94011d3 409 * - \ref PWM_TRIGGER_ADC_PERIOD_POINT
sahilmgandhi 18:6a4db94011d3 410 * - \ref PWM_TRIGGER_ADC_CENTER_POINT
sahilmgandhi 18:6a4db94011d3 411 * - \ref PWM_TRIGGER_ADC_FALLING_EDGE_POINT
sahilmgandhi 18:6a4db94011d3 412 * - \ref PWM_TRIGGER_ADC_RISING_EDGE_POINT
sahilmgandhi 18:6a4db94011d3 413 * @return None
sahilmgandhi 18:6a4db94011d3 414 */
sahilmgandhi 18:6a4db94011d3 415 void PWM_ClearADCTriggerFlag (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
sahilmgandhi 18:6a4db94011d3 416 {
sahilmgandhi 18:6a4db94011d3 417 pwm->TRGADCSTS |= (u32Condition << (1 * u32ChannelNum));
sahilmgandhi 18:6a4db94011d3 418 }
sahilmgandhi 18:6a4db94011d3 419
sahilmgandhi 18:6a4db94011d3 420 /**
sahilmgandhi 18:6a4db94011d3 421 * @brief This function get selected channel trigger ADC flag
sahilmgandhi 18:6a4db94011d3 422 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 423 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 424 * @return Combination of following trigger conditions which triggered ADC
sahilmgandhi 18:6a4db94011d3 425 * - \ref PWM_TRIGGER_ADC_PERIOD_POINT
sahilmgandhi 18:6a4db94011d3 426 * - \ref PWM_TRIGGER_ADC_CENTER_POINT
sahilmgandhi 18:6a4db94011d3 427 * - \ref PWM_TRIGGER_ADC_FALLING_EDGE_POINT
sahilmgandhi 18:6a4db94011d3 428 * - \ref PWM_TRIGGER_ADC_FALLING_EDGE_POINT
sahilmgandhi 18:6a4db94011d3 429 */
sahilmgandhi 18:6a4db94011d3 430 uint32_t PWM_GetADCTriggerFlag (PWM_T *pwm, uint32_t u32ChannelNum)
sahilmgandhi 18:6a4db94011d3 431 {
sahilmgandhi 18:6a4db94011d3 432 uint32_t u32Ret;
sahilmgandhi 18:6a4db94011d3 433
sahilmgandhi 18:6a4db94011d3 434 u32Ret = pwm->TRGADCSTS >> u32ChannelNum;
sahilmgandhi 18:6a4db94011d3 435
sahilmgandhi 18:6a4db94011d3 436 return (u32Ret & (PWM_TRIGGER_ADC_PERIOD_POINT |
sahilmgandhi 18:6a4db94011d3 437 PWM_TRIGGER_ADC_CENTER_POINT |
sahilmgandhi 18:6a4db94011d3 438 PWM_TRIGGER_ADC_FALLING_EDGE_POINT |
sahilmgandhi 18:6a4db94011d3 439 PWM_TRIGGER_ADC_FALLING_EDGE_POINT));
sahilmgandhi 18:6a4db94011d3 440 }
sahilmgandhi 18:6a4db94011d3 441
sahilmgandhi 18:6a4db94011d3 442 /**
sahilmgandhi 18:6a4db94011d3 443 * @brief This function enable fault brake of selected channels
sahilmgandhi 18:6a4db94011d3 444 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 445 * @param[in] u32ChannelMask This parameter is not used
sahilmgandhi 18:6a4db94011d3 446 * @param[in] u32LevelMask Output high or low while fault brake occurs, each bit represent the level of a channel
sahilmgandhi 18:6a4db94011d3 447 * while fault brake occurs. Bit 0 represents channel 0, bit 1 represents channel 1...
sahilmgandhi 18:6a4db94011d3 448 * , bit 6 represent D6, and bit 7 represents D7
sahilmgandhi 18:6a4db94011d3 449 * @param[in] u32BrakeSource Fault brake source, could be one of following source
sahilmgandhi 18:6a4db94011d3 450 * - \ref PWM_BRK0_BKP0
sahilmgandhi 18:6a4db94011d3 451 * - \ref PWM_BRK0_CPO0
sahilmgandhi 18:6a4db94011d3 452 * - \ref PWM_BRK0_CPO1
sahilmgandhi 18:6a4db94011d3 453 * - \ref PWM_BRK0_CPO2
sahilmgandhi 18:6a4db94011d3 454 * - \ref PWM_BRK1_LVDBK
sahilmgandhi 18:6a4db94011d3 455 * - \ref PWM_BK1SEL_BKP1
sahilmgandhi 18:6a4db94011d3 456 * - \ref PWM_BK1SEL_CPO0
sahilmgandhi 18:6a4db94011d3 457 * - \ref PWM_BK1SEL_CPO1
sahilmgandhi 18:6a4db94011d3 458 * @return None
sahilmgandhi 18:6a4db94011d3 459 */
sahilmgandhi 18:6a4db94011d3 460 void PWM_EnableFaultBrake (PWM_T *pwm,
sahilmgandhi 18:6a4db94011d3 461 uint32_t u32ChannelMask,
sahilmgandhi 18:6a4db94011d3 462 uint32_t u32LevelMask,
sahilmgandhi 18:6a4db94011d3 463 uint32_t u32BrakeSource)
sahilmgandhi 18:6a4db94011d3 464 {
sahilmgandhi 18:6a4db94011d3 465 if ((u32BrakeSource == PWM_BRK0_BKP0)||(u32BrakeSource == PWM_BRK0_CPO0)||(u32BrakeSource == PWM_BRK0_CPO1)||(u32BrakeSource == PWM_BRK0_CPO2))
sahilmgandhi 18:6a4db94011d3 466 pwm->BRKCTL |= (u32BrakeSource | PWM_BRKCTL_BRK0EN_Msk);
sahilmgandhi 18:6a4db94011d3 467 else if (u32BrakeSource == PWM_BRK1_LVDBK)
sahilmgandhi 18:6a4db94011d3 468 pwm->BRKCTL |= PWM_BRKCTL_LVDBKEN_Msk;
sahilmgandhi 18:6a4db94011d3 469 else
sahilmgandhi 18:6a4db94011d3 470 pwm->BRKCTL = (pwm->BRKCTL & ~PWM_BRKCTL_BK1SEL_Msk) | u32BrakeSource | PWM_BRKCTL_BRK1EN_Msk;
sahilmgandhi 18:6a4db94011d3 471
sahilmgandhi 18:6a4db94011d3 472 pwm->BRKCTL = (pwm->BRKCTL & ~PWM_BRKCTL_BKOD_Msk) | (u32LevelMask << PWM_BRKCTL_BKOD_Pos);
sahilmgandhi 18:6a4db94011d3 473
sahilmgandhi 18:6a4db94011d3 474 }
sahilmgandhi 18:6a4db94011d3 475
sahilmgandhi 18:6a4db94011d3 476 /**
sahilmgandhi 18:6a4db94011d3 477 * @brief This function clear fault brake flag
sahilmgandhi 18:6a4db94011d3 478 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 479 * @param[in] u32BrakeSource Fault brake source 0 or 1
sahilmgandhi 18:6a4db94011d3 480 * 0: brake 0, 1: brake 1
sahilmgandhi 18:6a4db94011d3 481 * @return None
sahilmgandhi 18:6a4db94011d3 482 * @note After fault brake occurred, application must clear fault brake source before re-enable PWM output
sahilmgandhi 18:6a4db94011d3 483 */
sahilmgandhi 18:6a4db94011d3 484 void PWM_ClearFaultBrakeFlag (PWM_T *pwm, uint32_t u32BrakeSource)
sahilmgandhi 18:6a4db94011d3 485 {
sahilmgandhi 18:6a4db94011d3 486 if (u32BrakeSource == 0)
sahilmgandhi 18:6a4db94011d3 487 pwm->INTSTS = (PWM_INTSTS_BRKLK0_Msk | PWM_INTSTS_BRKIF0_Msk);
sahilmgandhi 18:6a4db94011d3 488 else
sahilmgandhi 18:6a4db94011d3 489 pwm->INTSTS = PWM_INTSTS_BRKIF1_Msk;
sahilmgandhi 18:6a4db94011d3 490 }
sahilmgandhi 18:6a4db94011d3 491
sahilmgandhi 18:6a4db94011d3 492 /**
sahilmgandhi 18:6a4db94011d3 493 * @brief This function enables PWM capture of selected channels
sahilmgandhi 18:6a4db94011d3 494 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 495 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
sahilmgandhi 18:6a4db94011d3 496 * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
sahilmgandhi 18:6a4db94011d3 497 * @return None
sahilmgandhi 18:6a4db94011d3 498 */
sahilmgandhi 18:6a4db94011d3 499 void PWM_EnableCapture (PWM_T *pwm, uint32_t u32ChannelMask)
sahilmgandhi 18:6a4db94011d3 500 {
sahilmgandhi 18:6a4db94011d3 501 pwm->CAPCTL |= u32ChannelMask;
sahilmgandhi 18:6a4db94011d3 502 pwm->CAPINEN |= u32ChannelMask;
sahilmgandhi 18:6a4db94011d3 503 pwm->CTL |= (u32ChannelMask << PWM_CTL_CNTMODE_Pos);
sahilmgandhi 18:6a4db94011d3 504 }
sahilmgandhi 18:6a4db94011d3 505
sahilmgandhi 18:6a4db94011d3 506 /**
sahilmgandhi 18:6a4db94011d3 507 * @brief This function disables PWM capture of selected channels
sahilmgandhi 18:6a4db94011d3 508 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 509 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
sahilmgandhi 18:6a4db94011d3 510 * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
sahilmgandhi 18:6a4db94011d3 511 * @return None
sahilmgandhi 18:6a4db94011d3 512 */
sahilmgandhi 18:6a4db94011d3 513 void PWM_DisableCapture (PWM_T *pwm, uint32_t u32ChannelMask)
sahilmgandhi 18:6a4db94011d3 514 {
sahilmgandhi 18:6a4db94011d3 515 pwm->CAPCTL &= ~u32ChannelMask;
sahilmgandhi 18:6a4db94011d3 516 pwm->CAPINEN &= ~u32ChannelMask;
sahilmgandhi 18:6a4db94011d3 517 }
sahilmgandhi 18:6a4db94011d3 518
sahilmgandhi 18:6a4db94011d3 519 /**
sahilmgandhi 18:6a4db94011d3 520 * @brief This function enables PWM output generation of selected channels
sahilmgandhi 18:6a4db94011d3 521 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 522 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
sahilmgandhi 18:6a4db94011d3 523 * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
sahilmgandhi 18:6a4db94011d3 524 * @return None
sahilmgandhi 18:6a4db94011d3 525 */
sahilmgandhi 18:6a4db94011d3 526 void PWM_EnableOutput (PWM_T *pwm, uint32_t u32ChannelMask)
sahilmgandhi 18:6a4db94011d3 527 {
sahilmgandhi 18:6a4db94011d3 528 pwm->POEN |= u32ChannelMask;
sahilmgandhi 18:6a4db94011d3 529 }
sahilmgandhi 18:6a4db94011d3 530
sahilmgandhi 18:6a4db94011d3 531 /**
sahilmgandhi 18:6a4db94011d3 532 * @brief This function disables PWM output generation of selected channels
sahilmgandhi 18:6a4db94011d3 533 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 534 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
sahilmgandhi 18:6a4db94011d3 535 * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output...
sahilmgandhi 18:6a4db94011d3 536 * @return None
sahilmgandhi 18:6a4db94011d3 537 */
sahilmgandhi 18:6a4db94011d3 538 void PWM_DisableOutput (PWM_T *pwm, uint32_t u32ChannelMask)
sahilmgandhi 18:6a4db94011d3 539 {
sahilmgandhi 18:6a4db94011d3 540 pwm->POEN &= ~u32ChannelMask;
sahilmgandhi 18:6a4db94011d3 541 }
sahilmgandhi 18:6a4db94011d3 542
sahilmgandhi 18:6a4db94011d3 543 /**
sahilmgandhi 18:6a4db94011d3 544 * @brief This function enable Dead zone of selected channel
sahilmgandhi 18:6a4db94011d3 545 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 546 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 547 * @param[in] u32Duration Dead Zone length in PWM clock count, valid values are between 0~0xFF, but 0 means there is no
sahilmgandhi 18:6a4db94011d3 548 * dead zone.
sahilmgandhi 18:6a4db94011d3 549 * @return None
sahilmgandhi 18:6a4db94011d3 550 */
sahilmgandhi 18:6a4db94011d3 551 void PWM_EnableDeadZone (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration)
sahilmgandhi 18:6a4db94011d3 552 {
sahilmgandhi 18:6a4db94011d3 553 // every two channels shares the same setting
sahilmgandhi 18:6a4db94011d3 554 u32ChannelNum >>= 1;
sahilmgandhi 18:6a4db94011d3 555 // set duration
sahilmgandhi 18:6a4db94011d3 556 pwm->DTCTL = (pwm->DTCTL & ~(PWM_DTCTL_DTCNT01_Msk << (8 * u32ChannelNum))) | (u32Duration << (8 * u32ChannelNum));
sahilmgandhi 18:6a4db94011d3 557 // enable dead zone
sahilmgandhi 18:6a4db94011d3 558 pwm->DTCTL |= (PWM_DTCTL_DTEN01_Msk << u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 559 }
sahilmgandhi 18:6a4db94011d3 560
sahilmgandhi 18:6a4db94011d3 561 /**
sahilmgandhi 18:6a4db94011d3 562 * @brief This function disable Dead zone of selected channel
sahilmgandhi 18:6a4db94011d3 563 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 564 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 565 * @return None
sahilmgandhi 18:6a4db94011d3 566 */
sahilmgandhi 18:6a4db94011d3 567 void PWM_DisableDeadZone (PWM_T *pwm, uint32_t u32ChannelNum)
sahilmgandhi 18:6a4db94011d3 568 {
sahilmgandhi 18:6a4db94011d3 569 // every two channels shares the same setting
sahilmgandhi 18:6a4db94011d3 570 u32ChannelNum >>= 1;
sahilmgandhi 18:6a4db94011d3 571 // enable dead zone
sahilmgandhi 18:6a4db94011d3 572 pwm->DTCTL &= ~(PWM_DTCTL_DTEN01_Msk << u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 573 }
sahilmgandhi 18:6a4db94011d3 574
sahilmgandhi 18:6a4db94011d3 575 /**
sahilmgandhi 18:6a4db94011d3 576 * @brief This function enable capture interrupt of selected channel
sahilmgandhi 18:6a4db94011d3 577 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 578 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 579 * @param[in] u32Edge Capture interrupt type. It could be either
sahilmgandhi 18:6a4db94011d3 580 * - \ref PWM_FALLING_LATCH_INT_ENABLE
sahilmgandhi 18:6a4db94011d3 581 * - \ref PWM_RISING_LATCH_INT_ENABLE
sahilmgandhi 18:6a4db94011d3 582 * - \ref PWM_RISING_FALLING_LATCH_INT_ENABLE
sahilmgandhi 18:6a4db94011d3 583 * @return None
sahilmgandhi 18:6a4db94011d3 584 */
sahilmgandhi 18:6a4db94011d3 585 void PWM_EnableCaptureInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
sahilmgandhi 18:6a4db94011d3 586 {
sahilmgandhi 18:6a4db94011d3 587 // enable capture interrupt
sahilmgandhi 18:6a4db94011d3 588 pwm->INTEN |= (u32Edge << u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 589 }
sahilmgandhi 18:6a4db94011d3 590
sahilmgandhi 18:6a4db94011d3 591 /**
sahilmgandhi 18:6a4db94011d3 592 * @brief This function disable capture interrupt of selected channel
sahilmgandhi 18:6a4db94011d3 593 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 594 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 595 * @param[in] u32Edge Capture interrupt type. It could be either
sahilmgandhi 18:6a4db94011d3 596 * - \ref PWM_FALLING_LATCH_INT_ENABLE
sahilmgandhi 18:6a4db94011d3 597 * - \ref PWM_RISING_LATCH_INT_ENABLE
sahilmgandhi 18:6a4db94011d3 598 * - \ref PWM_RISING_FALLING_LATCH_INT_ENABLE
sahilmgandhi 18:6a4db94011d3 599 * @return None
sahilmgandhi 18:6a4db94011d3 600 */
sahilmgandhi 18:6a4db94011d3 601 void PWM_DisableCaptureInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
sahilmgandhi 18:6a4db94011d3 602 {
sahilmgandhi 18:6a4db94011d3 603 // disable capture interrupt
sahilmgandhi 18:6a4db94011d3 604 pwm->INTEN &= ~(u32Edge << u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 605 }
sahilmgandhi 18:6a4db94011d3 606
sahilmgandhi 18:6a4db94011d3 607 /**
sahilmgandhi 18:6a4db94011d3 608 * @brief This function clear capture interrupt flag of selected channel
sahilmgandhi 18:6a4db94011d3 609 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 610 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 611 * @param[in] u32Edge Capture interrupt type. It could be either
sahilmgandhi 18:6a4db94011d3 612 * - \ref PWM_FALLING_LATCH_INT_ENABLE
sahilmgandhi 18:6a4db94011d3 613 * - \ref PWM_RISING_LATCH_INT_ENABLE
sahilmgandhi 18:6a4db94011d3 614 * - \ref PWM_RISING_FALLING_LATCH_INT_ENABLE
sahilmgandhi 18:6a4db94011d3 615 * @return None
sahilmgandhi 18:6a4db94011d3 616 */
sahilmgandhi 18:6a4db94011d3 617 void PWM_ClearCaptureIntFlag (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
sahilmgandhi 18:6a4db94011d3 618 {
sahilmgandhi 18:6a4db94011d3 619 // disable capture interrupt flag
sahilmgandhi 18:6a4db94011d3 620 pwm->INTSTS = (u32Edge << u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 621 }
sahilmgandhi 18:6a4db94011d3 622
sahilmgandhi 18:6a4db94011d3 623 /**
sahilmgandhi 18:6a4db94011d3 624 * @brief This function get capture interrupt flag of selected channel
sahilmgandhi 18:6a4db94011d3 625 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 626 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 627 * @return Capture interrupt flag of specified channel
sahilmgandhi 18:6a4db94011d3 628 * @retval 0 Capture interrupt did not occurred
sahilmgandhi 18:6a4db94011d3 629 * @retval PWM_RISING_LATCH_INT_FLAG Rising edge latch interrupt occurred
sahilmgandhi 18:6a4db94011d3 630 * @retval PWM_FALLING_LATCH_INT_FLAG Falling edge latch interrupt occurred
sahilmgandhi 18:6a4db94011d3 631 * @retval PWM_RISING_FALLING_LATCH_INT_FLAG Rising and falling edge latch interrupt occurred
sahilmgandhi 18:6a4db94011d3 632 */
sahilmgandhi 18:6a4db94011d3 633 uint32_t PWM_GetCaptureIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
sahilmgandhi 18:6a4db94011d3 634 {
sahilmgandhi 18:6a4db94011d3 635 return ((pwm->INTSTS >> u32ChannelNum) & PWM_RISING_FALLING_LATCH_INT_FLAG);
sahilmgandhi 18:6a4db94011d3 636 }
sahilmgandhi 18:6a4db94011d3 637
sahilmgandhi 18:6a4db94011d3 638 /**
sahilmgandhi 18:6a4db94011d3 639 * @brief This function enable duty interrupt of selected channel
sahilmgandhi 18:6a4db94011d3 640 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 641 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 642 * @param[in] u32IntDutyType Duty interrupt type. It could be either
sahilmgandhi 18:6a4db94011d3 643 * - \ref PWM_DUTY_INT_MATCH_CMR_UP
sahilmgandhi 18:6a4db94011d3 644 * - \ref PWM_DUTY_INT_MATCH_CMR_DN
sahilmgandhi 18:6a4db94011d3 645 * @return None
sahilmgandhi 18:6a4db94011d3 646 */
sahilmgandhi 18:6a4db94011d3 647 void PWM_EnableDutyInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
sahilmgandhi 18:6a4db94011d3 648 {
sahilmgandhi 18:6a4db94011d3 649 // set duty interrupt type
sahilmgandhi 18:6a4db94011d3 650 pwm->INTCTL = (pwm->INTCTL & ~(PWM_DUTY_INT_MATCH_CMR_UP << u32ChannelNum)) | (u32IntDutyType << u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 651 // enable duty interrupt
sahilmgandhi 18:6a4db94011d3 652 pwm->INTEN |= ((1 << PWM_INTEN_DIEN_Pos) << u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 653 }
sahilmgandhi 18:6a4db94011d3 654
sahilmgandhi 18:6a4db94011d3 655 /**
sahilmgandhi 18:6a4db94011d3 656 * @brief This function disable duty interrupt of selected channel
sahilmgandhi 18:6a4db94011d3 657 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 658 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 659 * @return None
sahilmgandhi 18:6a4db94011d3 660 */
sahilmgandhi 18:6a4db94011d3 661 void PWM_DisableDutyInt (PWM_T *pwm, uint32_t u32ChannelNum)
sahilmgandhi 18:6a4db94011d3 662 {
sahilmgandhi 18:6a4db94011d3 663 pwm->INTEN &= ~((1 << PWM_INTEN_DIEN_Pos) << u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 664 }
sahilmgandhi 18:6a4db94011d3 665
sahilmgandhi 18:6a4db94011d3 666 /**
sahilmgandhi 18:6a4db94011d3 667 * @brief This function clears duty interrupt flag of selected channel
sahilmgandhi 18:6a4db94011d3 668 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 669 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 670 * @return None
sahilmgandhi 18:6a4db94011d3 671 */
sahilmgandhi 18:6a4db94011d3 672 void PWM_ClearDutyIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
sahilmgandhi 18:6a4db94011d3 673 {
sahilmgandhi 18:6a4db94011d3 674 // write 1 clear
sahilmgandhi 18:6a4db94011d3 675 pwm->INTSTS = (1 << PWM_INTSTS_DIF_Pos) << u32ChannelNum;
sahilmgandhi 18:6a4db94011d3 676 }
sahilmgandhi 18:6a4db94011d3 677
sahilmgandhi 18:6a4db94011d3 678 /**
sahilmgandhi 18:6a4db94011d3 679 * @brief This function get duty interrupt flag of selected channel
sahilmgandhi 18:6a4db94011d3 680 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 681 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 682 * @return Duty interrupt flag of specified channel
sahilmgandhi 18:6a4db94011d3 683 * @retval 0 Duty interrupt did not occurred
sahilmgandhi 18:6a4db94011d3 684 * @retval 1 Duty interrupt occurred
sahilmgandhi 18:6a4db94011d3 685 */
sahilmgandhi 18:6a4db94011d3 686 uint32_t PWM_GetDutyIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
sahilmgandhi 18:6a4db94011d3 687 {
sahilmgandhi 18:6a4db94011d3 688 return(pwm->INTSTS & ((1 << PWM_INTSTS_DIF_Pos) << u32ChannelNum) ? 1 : 0);
sahilmgandhi 18:6a4db94011d3 689 }
sahilmgandhi 18:6a4db94011d3 690
sahilmgandhi 18:6a4db94011d3 691 /**
sahilmgandhi 18:6a4db94011d3 692 * @brief This function enable fault brake interrupt
sahilmgandhi 18:6a4db94011d3 693 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 694 * @param[in] u32BrakeSource This parameter is not used
sahilmgandhi 18:6a4db94011d3 695 * @return None
sahilmgandhi 18:6a4db94011d3 696 */
sahilmgandhi 18:6a4db94011d3 697 void PWM_EnableFaultBrakeInt (PWM_T *pwm, uint32_t u32BrakeSource)
sahilmgandhi 18:6a4db94011d3 698 {
sahilmgandhi 18:6a4db94011d3 699 pwm->INTEN |= PWM_INTEN_BRKIEN_Msk;
sahilmgandhi 18:6a4db94011d3 700 }
sahilmgandhi 18:6a4db94011d3 701
sahilmgandhi 18:6a4db94011d3 702 /**
sahilmgandhi 18:6a4db94011d3 703 * @brief This function disable fault brake interrupt
sahilmgandhi 18:6a4db94011d3 704 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 705 * @param[in] u32BrakeSource This parameter is not used
sahilmgandhi 18:6a4db94011d3 706 * @return None
sahilmgandhi 18:6a4db94011d3 707 */
sahilmgandhi 18:6a4db94011d3 708 void PWM_DisableFaultBrakeInt (PWM_T *pwm, uint32_t u32BrakeSource)
sahilmgandhi 18:6a4db94011d3 709 {
sahilmgandhi 18:6a4db94011d3 710 pwm->INTEN &= ~PWM_INTEN_BRKIEN_Msk;
sahilmgandhi 18:6a4db94011d3 711 }
sahilmgandhi 18:6a4db94011d3 712
sahilmgandhi 18:6a4db94011d3 713 /**
sahilmgandhi 18:6a4db94011d3 714 * @brief This function clear fault brake interrupt of selected source
sahilmgandhi 18:6a4db94011d3 715 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 716 * @param[in] u32BrakeSource Fault brake source, could be either
sahilmgandhi 18:6a4db94011d3 717 * - \ref PWM_INTSTS_BRKIF0_Msk, or
sahilmgandhi 18:6a4db94011d3 718 * - \ref PWM_INTSTS_BRKIF1_Msk
sahilmgandhi 18:6a4db94011d3 719 * @return None
sahilmgandhi 18:6a4db94011d3 720 */
sahilmgandhi 18:6a4db94011d3 721 void PWM_ClearFaultBrakeIntFlag (PWM_T *pwm, uint32_t u32BrakeSource)
sahilmgandhi 18:6a4db94011d3 722 {
sahilmgandhi 18:6a4db94011d3 723 pwm->INTSTS = u32BrakeSource;
sahilmgandhi 18:6a4db94011d3 724 }
sahilmgandhi 18:6a4db94011d3 725
sahilmgandhi 18:6a4db94011d3 726 /**
sahilmgandhi 18:6a4db94011d3 727 * @brief This function get fault brake interrupt of selected source
sahilmgandhi 18:6a4db94011d3 728 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 729 * @param[in] u32BrakeSource Fault brake source, could be either
sahilmgandhi 18:6a4db94011d3 730 * - \ref PWM_INTSTS_BRKIF0_Msk, or
sahilmgandhi 18:6a4db94011d3 731 * - \ref PWM_INTSTS_BRKIF1_Msk
sahilmgandhi 18:6a4db94011d3 732 * @return Fault brake interrupt flag of specified source
sahilmgandhi 18:6a4db94011d3 733 * @retval 0 Fault brake interrupt did not occurred
sahilmgandhi 18:6a4db94011d3 734 * @retval 1 Fault brake interrupt occurred
sahilmgandhi 18:6a4db94011d3 735 */
sahilmgandhi 18:6a4db94011d3 736 uint32_t PWM_GetFaultBrakeIntFlag (PWM_T *pwm, uint32_t u32BrakeSource)
sahilmgandhi 18:6a4db94011d3 737 {
sahilmgandhi 18:6a4db94011d3 738 return (pwm->INTSTS & u32BrakeSource ? 1 : 0);
sahilmgandhi 18:6a4db94011d3 739 }
sahilmgandhi 18:6a4db94011d3 740
sahilmgandhi 18:6a4db94011d3 741 /**
sahilmgandhi 18:6a4db94011d3 742 * @brief This function enable period interrupt of selected channel
sahilmgandhi 18:6a4db94011d3 743 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 744 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 745 * @param[in] u32IntPeriodType Period interrupt type, could be either
sahilmgandhi 18:6a4db94011d3 746 * - \ref PWM_PERIOD_INT_UNDERFLOW
sahilmgandhi 18:6a4db94011d3 747 * - \ref PWM_PERIOD_INT_MATCH_CNR
sahilmgandhi 18:6a4db94011d3 748 * @return None
sahilmgandhi 18:6a4db94011d3 749 * @note All channels share the same period interrupt type setting.
sahilmgandhi 18:6a4db94011d3 750 */
sahilmgandhi 18:6a4db94011d3 751 void PWM_EnablePeriodInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
sahilmgandhi 18:6a4db94011d3 752 {
sahilmgandhi 18:6a4db94011d3 753 // set period interrupt type
sahilmgandhi 18:6a4db94011d3 754 pwm->INTCTL = (pwm->INTCTL & ~(PWM_PERIOD_INT_MATCH_CNR << u32ChannelNum)) | (u32IntPeriodType << u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 755 // enable period interrupt
sahilmgandhi 18:6a4db94011d3 756 pwm->INTEN |= ((1 << PWM_INTEN_PIEN_Pos) << u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 757 }
sahilmgandhi 18:6a4db94011d3 758
sahilmgandhi 18:6a4db94011d3 759 /**
sahilmgandhi 18:6a4db94011d3 760 * @brief This function disable period interrupt of selected channel
sahilmgandhi 18:6a4db94011d3 761 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 762 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 763 * @return None
sahilmgandhi 18:6a4db94011d3 764 */
sahilmgandhi 18:6a4db94011d3 765 void PWM_DisablePeriodInt (PWM_T *pwm, uint32_t u32ChannelNum)
sahilmgandhi 18:6a4db94011d3 766 {
sahilmgandhi 18:6a4db94011d3 767 pwm->INTEN &= ~((1 << PWM_INTEN_PIEN_Pos) << u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 768 }
sahilmgandhi 18:6a4db94011d3 769
sahilmgandhi 18:6a4db94011d3 770 /**
sahilmgandhi 18:6a4db94011d3 771 * @brief This function clear period interrupt of selected channel
sahilmgandhi 18:6a4db94011d3 772 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 773 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 774 * @return None
sahilmgandhi 18:6a4db94011d3 775 */
sahilmgandhi 18:6a4db94011d3 776 void PWM_ClearPeriodIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
sahilmgandhi 18:6a4db94011d3 777 {
sahilmgandhi 18:6a4db94011d3 778 // write 1 clear
sahilmgandhi 18:6a4db94011d3 779 pwm->INTSTS = ((1 << PWM_INTSTS_PIF_Pos) << u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 780 }
sahilmgandhi 18:6a4db94011d3 781
sahilmgandhi 18:6a4db94011d3 782 /**
sahilmgandhi 18:6a4db94011d3 783 * @brief This function get period interrupt of selected channel
sahilmgandhi 18:6a4db94011d3 784 * @param[in] pwm The base address of PWM module
sahilmgandhi 18:6a4db94011d3 785 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 786 * @return Period interrupt flag of specified channel
sahilmgandhi 18:6a4db94011d3 787 * @retval 0 Period interrupt did not occurred
sahilmgandhi 18:6a4db94011d3 788 * @retval 1 Period interrupt occurred
sahilmgandhi 18:6a4db94011d3 789 */
sahilmgandhi 18:6a4db94011d3 790 uint32_t PWM_GetPeriodIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
sahilmgandhi 18:6a4db94011d3 791 {
sahilmgandhi 18:6a4db94011d3 792 return(pwm->INTSTS & ((1 << PWM_INTSTS_PIF_Pos) << u32ChannelNum) ? 1 : 0);
sahilmgandhi 18:6a4db94011d3 793 }
sahilmgandhi 18:6a4db94011d3 794
sahilmgandhi 18:6a4db94011d3 795
sahilmgandhi 18:6a4db94011d3 796
sahilmgandhi 18:6a4db94011d3 797 /*@}*/ /* end of group NUC472_442_PWM_EXPORTED_FUNCTIONS */
sahilmgandhi 18:6a4db94011d3 798
sahilmgandhi 18:6a4db94011d3 799 /*@}*/ /* end of group NUC472_442_PWM_Driver */
sahilmgandhi 18:6a4db94011d3 800
sahilmgandhi 18:6a4db94011d3 801 /*@}*/ /* end of group NUC472_442_Device_Driver */
sahilmgandhi 18:6a4db94011d3 802
sahilmgandhi 18:6a4db94011d3 803 /*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/