MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_pdma.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file pdma.c
sahilmgandhi 18:6a4db94011d3 3 * @version V1.00
sahilmgandhi 18:6a4db94011d3 4 * $Revision: 7 $
sahilmgandhi 18:6a4db94011d3 5 * $Date: 14/05/29 1:13p $
sahilmgandhi 18:6a4db94011d3 6 * @brief NUC472/NUC442 PDMA driver source file
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * @note
sahilmgandhi 18:6a4db94011d3 9 * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
sahilmgandhi 18:6a4db94011d3 10 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 11 #include "NUC472_442.h"
sahilmgandhi 18:6a4db94011d3 12
sahilmgandhi 18:6a4db94011d3 13
sahilmgandhi 18:6a4db94011d3 14 static uint8_t u32ChSelect[PDMA_CH_MAX];
sahilmgandhi 18:6a4db94011d3 15
sahilmgandhi 18:6a4db94011d3 16 /** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
sahilmgandhi 18:6a4db94011d3 17 @{
sahilmgandhi 18:6a4db94011d3 18 */
sahilmgandhi 18:6a4db94011d3 19
sahilmgandhi 18:6a4db94011d3 20 /** @addtogroup NUC472_442_PDMA_Driver PDMA Driver
sahilmgandhi 18:6a4db94011d3 21 @{
sahilmgandhi 18:6a4db94011d3 22 */
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25 /** @addtogroup NUC472_442_PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
sahilmgandhi 18:6a4db94011d3 26 @{
sahilmgandhi 18:6a4db94011d3 27 */
sahilmgandhi 18:6a4db94011d3 28
sahilmgandhi 18:6a4db94011d3 29 /**
sahilmgandhi 18:6a4db94011d3 30 * @brief PDMA Open
sahilmgandhi 18:6a4db94011d3 31 *
sahilmgandhi 18:6a4db94011d3 32 * @param[in] u32Mask Channel enable bits.
sahilmgandhi 18:6a4db94011d3 33 *
sahilmgandhi 18:6a4db94011d3 34 * @return None
sahilmgandhi 18:6a4db94011d3 35 *
sahilmgandhi 18:6a4db94011d3 36 * @details This function enable the PDMA channels.
sahilmgandhi 18:6a4db94011d3 37 */
sahilmgandhi 18:6a4db94011d3 38 void PDMA_Open(uint32_t u32Mask)
sahilmgandhi 18:6a4db94011d3 39 {
sahilmgandhi 18:6a4db94011d3 40 int volatile i;
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 for (i=0; i<PDMA_CH_MAX; i++) {
sahilmgandhi 18:6a4db94011d3 43 PDMA->DSCT[i].CTL = 0;
sahilmgandhi 18:6a4db94011d3 44 u32ChSelect[i] = 0x1f;
sahilmgandhi 18:6a4db94011d3 45 }
sahilmgandhi 18:6a4db94011d3 46
sahilmgandhi 18:6a4db94011d3 47 PDMA->CHCTL |= u32Mask;
sahilmgandhi 18:6a4db94011d3 48 }
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 /**
sahilmgandhi 18:6a4db94011d3 51 * @brief PDMA Close
sahilmgandhi 18:6a4db94011d3 52 *
sahilmgandhi 18:6a4db94011d3 53 * @param[in] None
sahilmgandhi 18:6a4db94011d3 54 *
sahilmgandhi 18:6a4db94011d3 55 * @return None
sahilmgandhi 18:6a4db94011d3 56 *
sahilmgandhi 18:6a4db94011d3 57 * @details This function disable all PDMA channels.
sahilmgandhi 18:6a4db94011d3 58 */
sahilmgandhi 18:6a4db94011d3 59 void PDMA_Close(void)
sahilmgandhi 18:6a4db94011d3 60 {
sahilmgandhi 18:6a4db94011d3 61 PDMA->CHCTL = 0;
sahilmgandhi 18:6a4db94011d3 62 }
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 /**
sahilmgandhi 18:6a4db94011d3 65 * @brief Set PDMA Transfer Count
sahilmgandhi 18:6a4db94011d3 66 *
sahilmgandhi 18:6a4db94011d3 67 * @param[in] u32Ch The selected channel
sahilmgandhi 18:6a4db94011d3 68 * @param[in] u32Width Data width. PDMA_WIDTH_8, PDMA_WIDTH_16, or PDMA_WIDTH_32
sahilmgandhi 18:6a4db94011d3 69 * @param[in] u32TransCount Transfer count
sahilmgandhi 18:6a4db94011d3 70 *
sahilmgandhi 18:6a4db94011d3 71 * @return None
sahilmgandhi 18:6a4db94011d3 72 *
sahilmgandhi 18:6a4db94011d3 73 * @details This function set the selected channel data width and transfer count.
sahilmgandhi 18:6a4db94011d3 74 */
sahilmgandhi 18:6a4db94011d3 75 void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
sahilmgandhi 18:6a4db94011d3 76 {
sahilmgandhi 18:6a4db94011d3 77 PDMA->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXCNT_Msk | PDMA_DSCT_CTL_TXWIDTH_Msk);
sahilmgandhi 18:6a4db94011d3 78 PDMA->DSCT[u32Ch].CTL |= (u32Width | ((u32TransCount-1) << PDMA_DSCT_CTL_TXCNT_Pos));
sahilmgandhi 18:6a4db94011d3 79 }
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 /**
sahilmgandhi 18:6a4db94011d3 82 * @brief Set PDMA Transfer Address
sahilmgandhi 18:6a4db94011d3 83 *
sahilmgandhi 18:6a4db94011d3 84 * @param[in] u32Ch The selected channel
sahilmgandhi 18:6a4db94011d3 85 * @param[in] u32SrcAddr Source address
sahilmgandhi 18:6a4db94011d3 86 * @param[in] u32SrcCtrl Source control attribute. PDMA_SAR_INC or PDMA_SAR_FIX
sahilmgandhi 18:6a4db94011d3 87 * @param[in] u32DstAddr destination address
sahilmgandhi 18:6a4db94011d3 88 * @param[in] u32DstCtrl destination control attribute. PDMA_DAR_INC or PDMA_DAR_FIX
sahilmgandhi 18:6a4db94011d3 89 *
sahilmgandhi 18:6a4db94011d3 90 * @return None
sahilmgandhi 18:6a4db94011d3 91 *
sahilmgandhi 18:6a4db94011d3 92 * @details This function set the selected channel source/destination address and attribute.
sahilmgandhi 18:6a4db94011d3 93 */
sahilmgandhi 18:6a4db94011d3 94 void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
sahilmgandhi 18:6a4db94011d3 95 {
sahilmgandhi 18:6a4db94011d3 96 PDMA->DSCT[u32Ch].ENDSA = u32SrcAddr;
sahilmgandhi 18:6a4db94011d3 97 PDMA->DSCT[u32Ch].ENDDA = u32DstAddr;
sahilmgandhi 18:6a4db94011d3 98 PDMA->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_SAINC_Msk | PDMA_DSCT_CTL_DAINC_Msk);
sahilmgandhi 18:6a4db94011d3 99 PDMA->DSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl);
sahilmgandhi 18:6a4db94011d3 100 }
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102 /**
sahilmgandhi 18:6a4db94011d3 103 * @brief Set PDMA Transfer Mode
sahilmgandhi 18:6a4db94011d3 104 *
sahilmgandhi 18:6a4db94011d3 105 * @param[in] u32Ch The selected channel
sahilmgandhi 18:6a4db94011d3 106 * @param[in] u32Peripheral The selected peripheral. PDMA_SPI0_TX, PDMA_UART0_TX, PDMA_I2S_TX,...PDMA_MEM
sahilmgandhi 18:6a4db94011d3 107 * @param[in] u32ScatterEn Scatter-gather mode enable
sahilmgandhi 18:6a4db94011d3 108 * @param[in] u32DescAddr Scatter-gather descriptor address
sahilmgandhi 18:6a4db94011d3 109 *
sahilmgandhi 18:6a4db94011d3 110 * @return None
sahilmgandhi 18:6a4db94011d3 111 *
sahilmgandhi 18:6a4db94011d3 112 * @details This function set the selected channel transfer mode. Include peripheral setting.
sahilmgandhi 18:6a4db94011d3 113 */
sahilmgandhi 18:6a4db94011d3 114 void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
sahilmgandhi 18:6a4db94011d3 115 {
sahilmgandhi 18:6a4db94011d3 116 u32ChSelect[u32Ch] = u32Peripheral;
sahilmgandhi 18:6a4db94011d3 117 switch (u32Ch) {
sahilmgandhi 18:6a4db94011d3 118 case 0:
sahilmgandhi 18:6a4db94011d3 119 PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC0_Msk) | u32Peripheral;
sahilmgandhi 18:6a4db94011d3 120 break;
sahilmgandhi 18:6a4db94011d3 121 case 1:
sahilmgandhi 18:6a4db94011d3 122 PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC1_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC1_Pos);
sahilmgandhi 18:6a4db94011d3 123 break;
sahilmgandhi 18:6a4db94011d3 124 case 2:
sahilmgandhi 18:6a4db94011d3 125 PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC2_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC2_Pos);
sahilmgandhi 18:6a4db94011d3 126 break;
sahilmgandhi 18:6a4db94011d3 127 case 3:
sahilmgandhi 18:6a4db94011d3 128 PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC3_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC3_Pos);
sahilmgandhi 18:6a4db94011d3 129 break;
sahilmgandhi 18:6a4db94011d3 130 case 4:
sahilmgandhi 18:6a4db94011d3 131 PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC4_Msk) | u32Peripheral;
sahilmgandhi 18:6a4db94011d3 132 break;
sahilmgandhi 18:6a4db94011d3 133 case 5:
sahilmgandhi 18:6a4db94011d3 134 PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC5_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC5_Pos);
sahilmgandhi 18:6a4db94011d3 135 break;
sahilmgandhi 18:6a4db94011d3 136 case 6:
sahilmgandhi 18:6a4db94011d3 137 PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC6_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC6_Pos);
sahilmgandhi 18:6a4db94011d3 138 break;
sahilmgandhi 18:6a4db94011d3 139 case 7:
sahilmgandhi 18:6a4db94011d3 140 PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC7_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC7_Pos);
sahilmgandhi 18:6a4db94011d3 141 break;
sahilmgandhi 18:6a4db94011d3 142 case 8:
sahilmgandhi 18:6a4db94011d3 143 PDMA->REQSEL8_11 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL8_11_REQSRC8_Msk) | u32Peripheral;
sahilmgandhi 18:6a4db94011d3 144 break;
sahilmgandhi 18:6a4db94011d3 145 case 9:
sahilmgandhi 18:6a4db94011d3 146 PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL8_11_REQSRC9_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC9_Pos);
sahilmgandhi 18:6a4db94011d3 147 break;
sahilmgandhi 18:6a4db94011d3 148 case 10:
sahilmgandhi 18:6a4db94011d3 149 PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL8_11_REQSRC10_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC10_Pos);
sahilmgandhi 18:6a4db94011d3 150 break;
sahilmgandhi 18:6a4db94011d3 151 case 11:
sahilmgandhi 18:6a4db94011d3 152 PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL8_11_REQSRC11_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC11_Pos);
sahilmgandhi 18:6a4db94011d3 153 break;
sahilmgandhi 18:6a4db94011d3 154 case 12:
sahilmgandhi 18:6a4db94011d3 155 PDMA->REQSEL12_15 = (PDMA->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC12_Msk) | u32Peripheral;
sahilmgandhi 18:6a4db94011d3 156 break;
sahilmgandhi 18:6a4db94011d3 157 case 13:
sahilmgandhi 18:6a4db94011d3 158 PDMA->REQSEL12_15 = (PDMA->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC13_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC13_Pos);
sahilmgandhi 18:6a4db94011d3 159 break;
sahilmgandhi 18:6a4db94011d3 160 case 14:
sahilmgandhi 18:6a4db94011d3 161 PDMA->REQSEL12_15 = (PDMA->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC14_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC14_Pos);
sahilmgandhi 18:6a4db94011d3 162 break;
sahilmgandhi 18:6a4db94011d3 163 case 15:
sahilmgandhi 18:6a4db94011d3 164 PDMA->REQSEL12_15 = (PDMA->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC15_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC15_Pos);
sahilmgandhi 18:6a4db94011d3 165 break;
sahilmgandhi 18:6a4db94011d3 166 default:
sahilmgandhi 18:6a4db94011d3 167 ;
sahilmgandhi 18:6a4db94011d3 168 }
sahilmgandhi 18:6a4db94011d3 169
sahilmgandhi 18:6a4db94011d3 170 if (u32ScatterEn) {
sahilmgandhi 18:6a4db94011d3 171 PDMA->DSCT[u32Ch].CTL = (PDMA->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER;
sahilmgandhi 18:6a4db94011d3 172 PDMA->DSCT[u32Ch].NEXT = u32DescAddr - (PDMA->SCATBA);
sahilmgandhi 18:6a4db94011d3 173 } else
sahilmgandhi 18:6a4db94011d3 174 PDMA->DSCT[u32Ch].CTL = (PDMA->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC;
sahilmgandhi 18:6a4db94011d3 175 }
sahilmgandhi 18:6a4db94011d3 176
sahilmgandhi 18:6a4db94011d3 177 /**
sahilmgandhi 18:6a4db94011d3 178 * @brief Set PDMA Burst Type
sahilmgandhi 18:6a4db94011d3 179 *
sahilmgandhi 18:6a4db94011d3 180 * @param[in] u32Ch The selected channel
sahilmgandhi 18:6a4db94011d3 181 * @param[in] u32BurstType Burst mode or single mode
sahilmgandhi 18:6a4db94011d3 182 * @param[in] u32BurstSize Set the size of burst mode
sahilmgandhi 18:6a4db94011d3 183 *
sahilmgandhi 18:6a4db94011d3 184 * @return None
sahilmgandhi 18:6a4db94011d3 185 *
sahilmgandhi 18:6a4db94011d3 186 * @details This function set the selected channel burst type and size.
sahilmgandhi 18:6a4db94011d3 187 */
sahilmgandhi 18:6a4db94011d3 188 void PDMA_SetBurstType(uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize)
sahilmgandhi 18:6a4db94011d3 189 {
sahilmgandhi 18:6a4db94011d3 190 PDMA->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXTYPE_Msk | PDMA_DSCT_CTL_BURSIZE_Msk);
sahilmgandhi 18:6a4db94011d3 191 PDMA->DSCT[u32Ch].CTL |= (u32BurstType | u32BurstSize);
sahilmgandhi 18:6a4db94011d3 192 }
sahilmgandhi 18:6a4db94011d3 193
sahilmgandhi 18:6a4db94011d3 194 /**
sahilmgandhi 18:6a4db94011d3 195 * @brief Set PDMA TimeOut Count
sahilmgandhi 18:6a4db94011d3 196 *
sahilmgandhi 18:6a4db94011d3 197 * @param[in] u32Ch The selected channel
sahilmgandhi 18:6a4db94011d3 198 * @param[in] u32OnOff Enable/disable time out function
sahilmgandhi 18:6a4db94011d3 199 * @param[in] u32TimeOutCnt Timeout count
sahilmgandhi 18:6a4db94011d3 200 *
sahilmgandhi 18:6a4db94011d3 201 * @return None
sahilmgandhi 18:6a4db94011d3 202 *
sahilmgandhi 18:6a4db94011d3 203 * @details This function set the timeout count.
sahilmgandhi 18:6a4db94011d3 204 */
sahilmgandhi 18:6a4db94011d3 205 void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
sahilmgandhi 18:6a4db94011d3 206 {
sahilmgandhi 18:6a4db94011d3 207 switch(u32Ch) {
sahilmgandhi 18:6a4db94011d3 208 case 0:
sahilmgandhi 18:6a4db94011d3 209 PDMA->TOC0_1 = (PDMA->TOC0_1 & ~PDMA_TOC0_1_TOC0_Msk) | u32TimeOutCnt;
sahilmgandhi 18:6a4db94011d3 210 break;
sahilmgandhi 18:6a4db94011d3 211 case 1:
sahilmgandhi 18:6a4db94011d3 212 PDMA->TOC0_1 = (PDMA->TOC0_1 & ~PDMA_TOC0_1_TOC1_Msk) | (u32TimeOutCnt << PDMA_TOC0_1_TOC1_Pos);
sahilmgandhi 18:6a4db94011d3 213 break;
sahilmgandhi 18:6a4db94011d3 214 case 2:
sahilmgandhi 18:6a4db94011d3 215 PDMA->TOC2_3 = (PDMA->TOC2_3 & ~PDMA_TOC2_3_TOC2_Msk) | u32TimeOutCnt;
sahilmgandhi 18:6a4db94011d3 216 break;
sahilmgandhi 18:6a4db94011d3 217 case 3:
sahilmgandhi 18:6a4db94011d3 218 PDMA->TOC2_3 = (PDMA->TOC2_3 & ~PDMA_TOC2_3_TOC3_Msk) | (u32TimeOutCnt << PDMA_TOC2_3_TOC3_Pos);
sahilmgandhi 18:6a4db94011d3 219 break;
sahilmgandhi 18:6a4db94011d3 220 case 4:
sahilmgandhi 18:6a4db94011d3 221 PDMA->TOC4_5 = (PDMA->TOC4_5 & ~PDMA_TOC4_5_TOC4_Msk) | u32TimeOutCnt;
sahilmgandhi 18:6a4db94011d3 222 break;
sahilmgandhi 18:6a4db94011d3 223 case 5:
sahilmgandhi 18:6a4db94011d3 224 PDMA->TOC4_5 = (PDMA->TOC4_5 & ~PDMA_TOC4_5_TOC5_Msk) | (u32TimeOutCnt << PDMA_TOC4_5_TOC5_Pos);
sahilmgandhi 18:6a4db94011d3 225 break;
sahilmgandhi 18:6a4db94011d3 226 case 6:
sahilmgandhi 18:6a4db94011d3 227 PDMA->TOC6_7 = (PDMA->TOC6_7 & ~PDMA_TOC6_7_TOC6_Msk) | u32TimeOutCnt;
sahilmgandhi 18:6a4db94011d3 228 break;
sahilmgandhi 18:6a4db94011d3 229 case 7:
sahilmgandhi 18:6a4db94011d3 230 PDMA->TOC6_7 = (PDMA->TOC6_7 & ~PDMA_TOC6_7_TOC7_Msk) | (u32TimeOutCnt << PDMA_TOC6_7_TOC7_Pos);
sahilmgandhi 18:6a4db94011d3 231 break;
sahilmgandhi 18:6a4db94011d3 232 case 8:
sahilmgandhi 18:6a4db94011d3 233 PDMA->TOC8_9 = (PDMA->TOC8_9 & ~PDMA_TOC8_9_TOC8_Msk) | u32TimeOutCnt;
sahilmgandhi 18:6a4db94011d3 234 break;
sahilmgandhi 18:6a4db94011d3 235 case 9:
sahilmgandhi 18:6a4db94011d3 236 PDMA->TOC8_9 = (PDMA->TOC8_9 & ~PDMA_TOC8_9_TOC9_Msk) | (u32TimeOutCnt << PDMA_TOC8_9_TOC9_Pos);
sahilmgandhi 18:6a4db94011d3 237 break;
sahilmgandhi 18:6a4db94011d3 238 case 10:
sahilmgandhi 18:6a4db94011d3 239 PDMA->TOC10_11 = (PDMA->TOC10_11 & ~PDMA_TOC10_11_TOC10_Msk) | u32TimeOutCnt;
sahilmgandhi 18:6a4db94011d3 240 break;
sahilmgandhi 18:6a4db94011d3 241 case 11:
sahilmgandhi 18:6a4db94011d3 242 PDMA->TOC10_11 = (PDMA->TOC10_11 & ~PDMA_TOC10_11_TOC11_Msk) | (u32TimeOutCnt << PDMA_TOC10_11_TOC11_Pos);
sahilmgandhi 18:6a4db94011d3 243 break;
sahilmgandhi 18:6a4db94011d3 244 case 12:
sahilmgandhi 18:6a4db94011d3 245 PDMA->TOC12_13 = (PDMA->TOC12_13 & ~PDMA_TOC12_13_TOC12_Msk) | u32TimeOutCnt;
sahilmgandhi 18:6a4db94011d3 246 break;
sahilmgandhi 18:6a4db94011d3 247 case 13:
sahilmgandhi 18:6a4db94011d3 248 PDMA->TOC12_13 = (PDMA->TOC12_13 & ~PDMA_TOC12_13_TOC13_Msk) | (u32TimeOutCnt << PDMA_TOC12_13_TOC13_Pos);
sahilmgandhi 18:6a4db94011d3 249 break;
sahilmgandhi 18:6a4db94011d3 250 case 14:
sahilmgandhi 18:6a4db94011d3 251 PDMA->TOC14_15 = (PDMA->TOC14_15 & ~PDMA_TOC14_15_TOC14_Msk) | u32TimeOutCnt;
sahilmgandhi 18:6a4db94011d3 252 break;
sahilmgandhi 18:6a4db94011d3 253 case 15:
sahilmgandhi 18:6a4db94011d3 254 PDMA->TOC14_15 = (PDMA->TOC14_15 & ~PDMA_TOC14_15_TOC15_Msk) | (u32TimeOutCnt << PDMA_TOC14_15_TOC15_Pos);
sahilmgandhi 18:6a4db94011d3 255 break;
sahilmgandhi 18:6a4db94011d3 256 default:
sahilmgandhi 18:6a4db94011d3 257 ;
sahilmgandhi 18:6a4db94011d3 258 }
sahilmgandhi 18:6a4db94011d3 259 }
sahilmgandhi 18:6a4db94011d3 260
sahilmgandhi 18:6a4db94011d3 261
sahilmgandhi 18:6a4db94011d3 262 /**
sahilmgandhi 18:6a4db94011d3 263 * @brief Trigger PDMA
sahilmgandhi 18:6a4db94011d3 264 *
sahilmgandhi 18:6a4db94011d3 265 * @param[in] u32Ch The selected channel
sahilmgandhi 18:6a4db94011d3 266 *
sahilmgandhi 18:6a4db94011d3 267 * @return None
sahilmgandhi 18:6a4db94011d3 268 *
sahilmgandhi 18:6a4db94011d3 269 * @details This function trigger the selected channel.
sahilmgandhi 18:6a4db94011d3 270 */
sahilmgandhi 18:6a4db94011d3 271 void PDMA_Trigger(uint32_t u32Ch)
sahilmgandhi 18:6a4db94011d3 272 {
sahilmgandhi 18:6a4db94011d3 273 if (u32ChSelect[u32Ch] == PDMA_MEM)
sahilmgandhi 18:6a4db94011d3 274 PDMA->SWREQ = (1 << u32Ch);
sahilmgandhi 18:6a4db94011d3 275 }
sahilmgandhi 18:6a4db94011d3 276
sahilmgandhi 18:6a4db94011d3 277 /**
sahilmgandhi 18:6a4db94011d3 278 * @brief Enable Interrupt
sahilmgandhi 18:6a4db94011d3 279 *
sahilmgandhi 18:6a4db94011d3 280 * @param[in] u32Ch The selected channel
sahilmgandhi 18:6a4db94011d3 281 * @param[in] u32Mask The Interrupt Type
sahilmgandhi 18:6a4db94011d3 282 *
sahilmgandhi 18:6a4db94011d3 283 * @return None
sahilmgandhi 18:6a4db94011d3 284 *
sahilmgandhi 18:6a4db94011d3 285 * @details This function enable the selected channel interrupt.
sahilmgandhi 18:6a4db94011d3 286 */
sahilmgandhi 18:6a4db94011d3 287 void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask)
sahilmgandhi 18:6a4db94011d3 288 {
sahilmgandhi 18:6a4db94011d3 289 PDMA->INTEN |= (1 << u32Ch);
sahilmgandhi 18:6a4db94011d3 290 }
sahilmgandhi 18:6a4db94011d3 291
sahilmgandhi 18:6a4db94011d3 292 /**
sahilmgandhi 18:6a4db94011d3 293 * @brief Disable Interrupt
sahilmgandhi 18:6a4db94011d3 294 *
sahilmgandhi 18:6a4db94011d3 295 * @param[in] u32Ch The selected channel
sahilmgandhi 18:6a4db94011d3 296 * @param[in] u32Mask The Interrupt Type
sahilmgandhi 18:6a4db94011d3 297 *
sahilmgandhi 18:6a4db94011d3 298 * @return None
sahilmgandhi 18:6a4db94011d3 299 *
sahilmgandhi 18:6a4db94011d3 300 * @details This function disable the selected channel interrupt.
sahilmgandhi 18:6a4db94011d3 301 */
sahilmgandhi 18:6a4db94011d3 302 void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask)
sahilmgandhi 18:6a4db94011d3 303 {
sahilmgandhi 18:6a4db94011d3 304 PDMA->INTEN &= ~(1 << u32Ch);
sahilmgandhi 18:6a4db94011d3 305 }
sahilmgandhi 18:6a4db94011d3 306
sahilmgandhi 18:6a4db94011d3 307 /*@}*/ /* end of group NUC472_442_PDMA_EXPORTED_FUNCTIONS */
sahilmgandhi 18:6a4db94011d3 308
sahilmgandhi 18:6a4db94011d3 309 /*@}*/ /* end of group NUC472_442_PDMA_Driver */
sahilmgandhi 18:6a4db94011d3 310
sahilmgandhi 18:6a4db94011d3 311 /*@}*/ /* end of group NUC472_442_Device_Driver */
sahilmgandhi 18:6a4db94011d3 312
sahilmgandhi 18:6a4db94011d3 313 /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/