Mouse code for the MacroRat
mbed-dev/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_i2s.h@46:b156ef445742, 2017-06-03 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sat Jun 03 00:22:44 2017 +0000
- Revision:
- 46:b156ef445742
- Parent:
- 18:6a4db94011d3
Final code for internal battlebot competition.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /****************************************************************************** |
sahilmgandhi | 18:6a4db94011d3 | 2 | * @file i2s.h |
sahilmgandhi | 18:6a4db94011d3 | 3 | * @version V0.10 |
sahilmgandhi | 18:6a4db94011d3 | 4 | * $Revision: 10 $ |
sahilmgandhi | 18:6a4db94011d3 | 5 | * $Date: 14/09/30 1:12p $ |
sahilmgandhi | 18:6a4db94011d3 | 6 | * @brief NUC472/NUC442 I2S driver header file |
sahilmgandhi | 18:6a4db94011d3 | 7 | * |
sahilmgandhi | 18:6a4db94011d3 | 8 | * @note |
sahilmgandhi | 18:6a4db94011d3 | 9 | * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. |
sahilmgandhi | 18:6a4db94011d3 | 10 | *****************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 11 | #ifndef __I2S_H__ |
sahilmgandhi | 18:6a4db94011d3 | 12 | #define __I2S_H__ |
sahilmgandhi | 18:6a4db94011d3 | 13 | |
sahilmgandhi | 18:6a4db94011d3 | 14 | #include "NUC472_442.h" |
sahilmgandhi | 18:6a4db94011d3 | 15 | |
sahilmgandhi | 18:6a4db94011d3 | 16 | #ifdef __cplusplus |
sahilmgandhi | 18:6a4db94011d3 | 17 | extern "C" |
sahilmgandhi | 18:6a4db94011d3 | 18 | { |
sahilmgandhi | 18:6a4db94011d3 | 19 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 20 | |
sahilmgandhi | 18:6a4db94011d3 | 21 | /** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver |
sahilmgandhi | 18:6a4db94011d3 | 22 | @{ |
sahilmgandhi | 18:6a4db94011d3 | 23 | */ |
sahilmgandhi | 18:6a4db94011d3 | 24 | |
sahilmgandhi | 18:6a4db94011d3 | 25 | /** @addtogroup NUC472_442_I2S_Driver I2S Driver |
sahilmgandhi | 18:6a4db94011d3 | 26 | @{ |
sahilmgandhi | 18:6a4db94011d3 | 27 | */ |
sahilmgandhi | 18:6a4db94011d3 | 28 | |
sahilmgandhi | 18:6a4db94011d3 | 29 | /** @addtogroup NUC472_442_I2S_EXPORTED_CONSTANTS I2S Exported Constants |
sahilmgandhi | 18:6a4db94011d3 | 30 | @{ |
sahilmgandhi | 18:6a4db94011d3 | 31 | */ |
sahilmgandhi | 18:6a4db94011d3 | 32 | #define I2S_DATABIT_8 (0 << I2S_CTL_WDWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 33 | #define I2S_DATABIT_16 (1 << I2S_CTL_WDWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 34 | #define I2S_DATABIT_24 (2 << I2S_CTL_WDWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 35 | #define I2S_DATABIT_32 (3 << I2S_CTL_WDWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 36 | |
sahilmgandhi | 18:6a4db94011d3 | 37 | /* Audio Format */ |
sahilmgandhi | 18:6a4db94011d3 | 38 | #define I2S_MONO I2S_CTL_MONO_Msk /*!< Mono channel \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 39 | #define I2S_STEREO 0 /*!< Stereo channel \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 40 | |
sahilmgandhi | 18:6a4db94011d3 | 41 | /* I2S Data Format */ |
sahilmgandhi | 18:6a4db94011d3 | 42 | #define I2S_FORMAT_MSB I2S_CTL_FORMAT_Msk /*!< MSB data format \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 43 | #define I2S_FORMAT_I2S 0 /*!< I2S data format \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 44 | #define I2S_FORMAT_PCMB I2S_CTL_FORMAT_Msk /*!< PCMB data format \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 45 | #define I2S_FORMAT_PCMA 0 /*!< PCMA data format \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 46 | |
sahilmgandhi | 18:6a4db94011d3 | 47 | /* I2S Interface */ |
sahilmgandhi | 18:6a4db94011d3 | 48 | #define I2S_PCM I2S_CTL_PCMEN_Msk /*!< PCM interface is selected \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 49 | #define I2S_I2S 0 /*!< I2S interface is selected \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 50 | |
sahilmgandhi | 18:6a4db94011d3 | 51 | /* I2S Operation mode */ |
sahilmgandhi | 18:6a4db94011d3 | 52 | #define I2S_MODE_SLAVE I2S_CTL_SLAVE_Msk /*!< As slave mode \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 53 | #define I2S_MODE_MASTER 0 /*!< As master mode \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 54 | |
sahilmgandhi | 18:6a4db94011d3 | 55 | /* I2S FIFO Threshold */ |
sahilmgandhi | 18:6a4db94011d3 | 56 | #define I2S_FIFO_TX_LEVEL_WORD_0 0 /*!< TX threshold is 0 word \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 57 | #define I2S_FIFO_TX_LEVEL_WORD_1 (1 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 1 word \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 58 | #define I2S_FIFO_TX_LEVEL_WORD_2 (2 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 2 words \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 59 | #define I2S_FIFO_TX_LEVEL_WORD_3 (3 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 3 words \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 60 | #define I2S_FIFO_TX_LEVEL_WORD_4 (4 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 4 words \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 61 | #define I2S_FIFO_TX_LEVEL_WORD_5 (5 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 5 words \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 62 | #define I2S_FIFO_TX_LEVEL_WORD_6 (6 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 6 words \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 63 | #define I2S_FIFO_TX_LEVEL_WORD_7 (7 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 7 words \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 64 | |
sahilmgandhi | 18:6a4db94011d3 | 65 | #define I2S_FIFO_RX_LEVEL_WORD_1 0 /*!< RX threshold is 1 word \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 66 | #define I2S_FIFO_RX_LEVEL_WORD_2 (1 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 2 words \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 67 | #define I2S_FIFO_RX_LEVEL_WORD_3 (2 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 3 words \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 68 | #define I2S_FIFO_RX_LEVEL_WORD_4 (3 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 4 words \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 69 | #define I2S_FIFO_RX_LEVEL_WORD_5 (4 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 5 words \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 70 | #define I2S_FIFO_RX_LEVEL_WORD_6 (5 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 6 words \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 71 | #define I2S_FIFO_RX_LEVEL_WORD_7 (6 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 7 words \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 72 | #define I2S_FIFO_RX_LEVEL_WORD_8 (7 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 8 words \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 73 | |
sahilmgandhi | 18:6a4db94011d3 | 74 | /* I2S Record Channel */ |
sahilmgandhi | 18:6a4db94011d3 | 75 | #define I2S_MONO_RIGHT 0 /*!< Record mono right channel \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 76 | #define I2S_MONO_LEFT I2S_CTL_RXLCH_Msk /*!< Record mono left channel \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 77 | |
sahilmgandhi | 18:6a4db94011d3 | 78 | /* I2S Channel */ |
sahilmgandhi | 18:6a4db94011d3 | 79 | #define I2S_RIGHT 0 /*!< Select right channel \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 80 | #define I2S_LEFT 1 /*!< Select left channel \hideinitializer */ |
sahilmgandhi | 18:6a4db94011d3 | 81 | |
sahilmgandhi | 18:6a4db94011d3 | 82 | /*@}*/ /* end of group NUC472_442_I2S_EXPORTED_CONSTANTS */ |
sahilmgandhi | 18:6a4db94011d3 | 83 | |
sahilmgandhi | 18:6a4db94011d3 | 84 | /** @addtogroup NUC472_442_I2S_EXPORTED_FUNCTIONS I2S Exported Functions |
sahilmgandhi | 18:6a4db94011d3 | 85 | @{ |
sahilmgandhi | 18:6a4db94011d3 | 86 | */ |
sahilmgandhi | 18:6a4db94011d3 | 87 | /*---------------------------------------------------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 88 | /* inline functions */ |
sahilmgandhi | 18:6a4db94011d3 | 89 | /*---------------------------------------------------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 90 | /** |
sahilmgandhi | 18:6a4db94011d3 | 91 | * @brief Enable zero cross detect function. |
sahilmgandhi | 18:6a4db94011d3 | 92 | * @param[in] i2s is the base address of I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 93 | * @param[in] u32ChMask is the mask for left or right channel. Valid values are: |
sahilmgandhi | 18:6a4db94011d3 | 94 | * - \ref I2S_RIGHT |
sahilmgandhi | 18:6a4db94011d3 | 95 | * - \ref I2S_LEFT |
sahilmgandhi | 18:6a4db94011d3 | 96 | * @return none |
sahilmgandhi | 18:6a4db94011d3 | 97 | * \hideinitializer |
sahilmgandhi | 18:6a4db94011d3 | 98 | */ |
sahilmgandhi | 18:6a4db94011d3 | 99 | static __INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask) |
sahilmgandhi | 18:6a4db94011d3 | 100 | { |
sahilmgandhi | 18:6a4db94011d3 | 101 | if(u32ChMask == I2S_RIGHT) |
sahilmgandhi | 18:6a4db94011d3 | 102 | i2s->CTL |= I2S_CTL_RZCEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 103 | else |
sahilmgandhi | 18:6a4db94011d3 | 104 | i2s->CTL |= I2S_CTL_LZCEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 105 | } |
sahilmgandhi | 18:6a4db94011d3 | 106 | |
sahilmgandhi | 18:6a4db94011d3 | 107 | /** |
sahilmgandhi | 18:6a4db94011d3 | 108 | * @brief Disable zero cross detect function. |
sahilmgandhi | 18:6a4db94011d3 | 109 | * @param[in] i2s is the base address of I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 110 | * @param[in] u32ChMask is the mask for left or right channel. Valid values are: |
sahilmgandhi | 18:6a4db94011d3 | 111 | * - \ref I2S_RIGHT |
sahilmgandhi | 18:6a4db94011d3 | 112 | * - \ref I2S_LEFT |
sahilmgandhi | 18:6a4db94011d3 | 113 | * @return none |
sahilmgandhi | 18:6a4db94011d3 | 114 | * \hideinitializer |
sahilmgandhi | 18:6a4db94011d3 | 115 | */ |
sahilmgandhi | 18:6a4db94011d3 | 116 | static __INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask) |
sahilmgandhi | 18:6a4db94011d3 | 117 | { |
sahilmgandhi | 18:6a4db94011d3 | 118 | if(u32ChMask == I2S_RIGHT) |
sahilmgandhi | 18:6a4db94011d3 | 119 | i2s->CTL &= ~I2S_CTL_RZCEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 120 | else |
sahilmgandhi | 18:6a4db94011d3 | 121 | i2s->CTL &= ~I2S_CTL_LZCEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 122 | } |
sahilmgandhi | 18:6a4db94011d3 | 123 | |
sahilmgandhi | 18:6a4db94011d3 | 124 | /** |
sahilmgandhi | 18:6a4db94011d3 | 125 | * @brief Enable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO. |
sahilmgandhi | 18:6a4db94011d3 | 126 | * @param[in] i2s is the base address of I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 127 | * @return none |
sahilmgandhi | 18:6a4db94011d3 | 128 | * \hideinitializer |
sahilmgandhi | 18:6a4db94011d3 | 129 | */ |
sahilmgandhi | 18:6a4db94011d3 | 130 | #define I2S_ENABLE_TXDMA(i2s) ( (i2s)->CTL |= I2S_CTL_TXPDMAEN_Msk ) |
sahilmgandhi | 18:6a4db94011d3 | 131 | |
sahilmgandhi | 18:6a4db94011d3 | 132 | /** |
sahilmgandhi | 18:6a4db94011d3 | 133 | * @brief Disable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO. |
sahilmgandhi | 18:6a4db94011d3 | 134 | * @param[in] i2s is the base address of I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 135 | * @return none |
sahilmgandhi | 18:6a4db94011d3 | 136 | * \hideinitializer |
sahilmgandhi | 18:6a4db94011d3 | 137 | */ |
sahilmgandhi | 18:6a4db94011d3 | 138 | #define I2S_DISABLE_TXDMA(i2s) ( (i2s)->CTL &= ~I2S_CTL_TXPDMAEN_Msk ) |
sahilmgandhi | 18:6a4db94011d3 | 139 | |
sahilmgandhi | 18:6a4db94011d3 | 140 | /** |
sahilmgandhi | 18:6a4db94011d3 | 141 | * @brief Enable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO. |
sahilmgandhi | 18:6a4db94011d3 | 142 | * @param[in] i2s is the base address of I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 143 | * @return none |
sahilmgandhi | 18:6a4db94011d3 | 144 | * \hideinitializer |
sahilmgandhi | 18:6a4db94011d3 | 145 | */ |
sahilmgandhi | 18:6a4db94011d3 | 146 | #define I2S_ENABLE_RXDMA(i2s) ( (i2s)->CTL |= I2S_CTL_RXPDMAEN_Msk ) |
sahilmgandhi | 18:6a4db94011d3 | 147 | |
sahilmgandhi | 18:6a4db94011d3 | 148 | /** |
sahilmgandhi | 18:6a4db94011d3 | 149 | * @brief Disable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO. |
sahilmgandhi | 18:6a4db94011d3 | 150 | * @param[in] i2s is the base address of I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 151 | * @return none |
sahilmgandhi | 18:6a4db94011d3 | 152 | * \hideinitializer |
sahilmgandhi | 18:6a4db94011d3 | 153 | */ |
sahilmgandhi | 18:6a4db94011d3 | 154 | #define I2S_DISABLE_RXDMA(i2s) ( (i2s)->CTL &= ~I2S_CTL_RXPDMAEN_Msk ) |
sahilmgandhi | 18:6a4db94011d3 | 155 | |
sahilmgandhi | 18:6a4db94011d3 | 156 | /** |
sahilmgandhi | 18:6a4db94011d3 | 157 | * @brief Enable I2S Tx function . |
sahilmgandhi | 18:6a4db94011d3 | 158 | * @param[in] i2s is the base address of I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 159 | * @return none |
sahilmgandhi | 18:6a4db94011d3 | 160 | * \hideinitializer |
sahilmgandhi | 18:6a4db94011d3 | 161 | */ |
sahilmgandhi | 18:6a4db94011d3 | 162 | #define I2S_ENABLE_TX(i2s) ( (i2s)->CTL |= I2S_CTL_TXEN_Msk ) |
sahilmgandhi | 18:6a4db94011d3 | 163 | |
sahilmgandhi | 18:6a4db94011d3 | 164 | /** |
sahilmgandhi | 18:6a4db94011d3 | 165 | * @brief Disable I2S Tx function . |
sahilmgandhi | 18:6a4db94011d3 | 166 | * @param[in] i2s is the base address of I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 167 | * @return none |
sahilmgandhi | 18:6a4db94011d3 | 168 | * \hideinitializer |
sahilmgandhi | 18:6a4db94011d3 | 169 | */ |
sahilmgandhi | 18:6a4db94011d3 | 170 | #define I2S_DISABLE_TX(i2s) ( (i2s)->CTL &= ~I2S_CTL_TXEN_Msk ) |
sahilmgandhi | 18:6a4db94011d3 | 171 | |
sahilmgandhi | 18:6a4db94011d3 | 172 | /** |
sahilmgandhi | 18:6a4db94011d3 | 173 | * @brief Enable I2S Rx function . |
sahilmgandhi | 18:6a4db94011d3 | 174 | * @param[in] i2s is the base address of I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 175 | * @return none |
sahilmgandhi | 18:6a4db94011d3 | 176 | * \hideinitializer |
sahilmgandhi | 18:6a4db94011d3 | 177 | */ |
sahilmgandhi | 18:6a4db94011d3 | 178 | #define I2S_ENABLE_RX(i2s) ( (i2s)->CTL |= I2S_CTL_RXEN_Msk ) |
sahilmgandhi | 18:6a4db94011d3 | 179 | |
sahilmgandhi | 18:6a4db94011d3 | 180 | /** |
sahilmgandhi | 18:6a4db94011d3 | 181 | * @brief Disable I2S Rx function . |
sahilmgandhi | 18:6a4db94011d3 | 182 | * @param[in] i2s is the base address of I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 183 | * @return none |
sahilmgandhi | 18:6a4db94011d3 | 184 | * \hideinitializer |
sahilmgandhi | 18:6a4db94011d3 | 185 | */ |
sahilmgandhi | 18:6a4db94011d3 | 186 | #define I2S_DISABLE_RX(i2s) ( (i2s)->CTL &= ~I2S_CTL_RXEN_Msk ) |
sahilmgandhi | 18:6a4db94011d3 | 187 | |
sahilmgandhi | 18:6a4db94011d3 | 188 | /** |
sahilmgandhi | 18:6a4db94011d3 | 189 | * @brief Enable Tx Mute function . |
sahilmgandhi | 18:6a4db94011d3 | 190 | * @param[in] i2s is the base address of I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 191 | * @return none |
sahilmgandhi | 18:6a4db94011d3 | 192 | * \hideinitializer |
sahilmgandhi | 18:6a4db94011d3 | 193 | */ |
sahilmgandhi | 18:6a4db94011d3 | 194 | #define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->CTL |= I2S_CTL_MUTE_Msk ) |
sahilmgandhi | 18:6a4db94011d3 | 195 | |
sahilmgandhi | 18:6a4db94011d3 | 196 | /** |
sahilmgandhi | 18:6a4db94011d3 | 197 | * @brief Disable Tx Mute function . |
sahilmgandhi | 18:6a4db94011d3 | 198 | * @param[in] i2s is the base address of I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 199 | * @return none |
sahilmgandhi | 18:6a4db94011d3 | 200 | * \hideinitializer |
sahilmgandhi | 18:6a4db94011d3 | 201 | */ |
sahilmgandhi | 18:6a4db94011d3 | 202 | #define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->CTL &= ~I2S_CTL_MUTE_Msk ) |
sahilmgandhi | 18:6a4db94011d3 | 203 | |
sahilmgandhi | 18:6a4db94011d3 | 204 | /** |
sahilmgandhi | 18:6a4db94011d3 | 205 | * @brief Clear Tx FIFO. Internal pointer is reset to FIFO start point. |
sahilmgandhi | 18:6a4db94011d3 | 206 | * @param[in] i2s is the base address of I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 207 | * @return none |
sahilmgandhi | 18:6a4db94011d3 | 208 | * \hideinitializer |
sahilmgandhi | 18:6a4db94011d3 | 209 | */ |
sahilmgandhi | 18:6a4db94011d3 | 210 | #define I2S_CLR_TX_FIFO(i2s) ( (i2s)->CTL |= I2S_CTL_TXCLR_Msk ) |
sahilmgandhi | 18:6a4db94011d3 | 211 | |
sahilmgandhi | 18:6a4db94011d3 | 212 | /** |
sahilmgandhi | 18:6a4db94011d3 | 213 | * @brief Clear Rx FIFO. Internal pointer is reset to FIFO start point. |
sahilmgandhi | 18:6a4db94011d3 | 214 | * @param[in] i2s is the base address of I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 215 | * @return none |
sahilmgandhi | 18:6a4db94011d3 | 216 | * \hideinitializer |
sahilmgandhi | 18:6a4db94011d3 | 217 | */ |
sahilmgandhi | 18:6a4db94011d3 | 218 | #define I2S_CLR_RX_FIFO(i2s) ( (i2s)->CTL |= I2S_CTL_RXCLR_Msk ) |
sahilmgandhi | 18:6a4db94011d3 | 219 | |
sahilmgandhi | 18:6a4db94011d3 | 220 | /** |
sahilmgandhi | 18:6a4db94011d3 | 221 | * @brief This function sets the recording source channel when mono mode is used. |
sahilmgandhi | 18:6a4db94011d3 | 222 | * @param[in] i2s is the base address of I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 223 | * @param[in] u32Ch left or right channel. Valid values are: |
sahilmgandhi | 18:6a4db94011d3 | 224 | * - \ref I2S_MONO_LEFT |
sahilmgandhi | 18:6a4db94011d3 | 225 | * - \ref I2S_MONO_RIGHT |
sahilmgandhi | 18:6a4db94011d3 | 226 | * @return none |
sahilmgandhi | 18:6a4db94011d3 | 227 | * \hideinitializer |
sahilmgandhi | 18:6a4db94011d3 | 228 | */ |
sahilmgandhi | 18:6a4db94011d3 | 229 | static __INLINE void I2S_SET_MONO_RX_CHANNEL(I2S_T *i2s, uint32_t u32Ch) |
sahilmgandhi | 18:6a4db94011d3 | 230 | { |
sahilmgandhi | 18:6a4db94011d3 | 231 | u32Ch == I2S_MONO_LEFT ? |
sahilmgandhi | 18:6a4db94011d3 | 232 | (i2s->CTL |= I2S_CTL_RXLCH_Msk) : |
sahilmgandhi | 18:6a4db94011d3 | 233 | (i2s->CTL &= ~I2S_CTL_RXLCH_Msk); |
sahilmgandhi | 18:6a4db94011d3 | 234 | } |
sahilmgandhi | 18:6a4db94011d3 | 235 | |
sahilmgandhi | 18:6a4db94011d3 | 236 | /** |
sahilmgandhi | 18:6a4db94011d3 | 237 | * @brief Write data to I2S Tx FIFO. |
sahilmgandhi | 18:6a4db94011d3 | 238 | * @param[in] i2s is the base address of I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 239 | * @param[in] u32Data: The data written to FIFO. |
sahilmgandhi | 18:6a4db94011d3 | 240 | * @return none |
sahilmgandhi | 18:6a4db94011d3 | 241 | * \hideinitializer |
sahilmgandhi | 18:6a4db94011d3 | 242 | */ |
sahilmgandhi | 18:6a4db94011d3 | 243 | #define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TX = u32Data ) |
sahilmgandhi | 18:6a4db94011d3 | 244 | |
sahilmgandhi | 18:6a4db94011d3 | 245 | /** |
sahilmgandhi | 18:6a4db94011d3 | 246 | * @brief Read Rx FIFO. |
sahilmgandhi | 18:6a4db94011d3 | 247 | * @param[in] i2s is the base address of I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 248 | * @return Data in Rx FIFO. |
sahilmgandhi | 18:6a4db94011d3 | 249 | * \hideinitializer |
sahilmgandhi | 18:6a4db94011d3 | 250 | */ |
sahilmgandhi | 18:6a4db94011d3 | 251 | #define I2S_READ_RX_FIFO(i2s) ( (i2s)->RX ) |
sahilmgandhi | 18:6a4db94011d3 | 252 | |
sahilmgandhi | 18:6a4db94011d3 | 253 | /** |
sahilmgandhi | 18:6a4db94011d3 | 254 | * @brief This function gets the interrupt flag according to the mask parameter. |
sahilmgandhi | 18:6a4db94011d3 | 255 | * @param[in] i2s is the base address of I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 256 | * @param[in] u32Mask is the mask for the all interrupt flags. |
sahilmgandhi | 18:6a4db94011d3 | 257 | * @return The masked bit value of interrupt flag. |
sahilmgandhi | 18:6a4db94011d3 | 258 | * \hideinitializer |
sahilmgandhi | 18:6a4db94011d3 | 259 | */ |
sahilmgandhi | 18:6a4db94011d3 | 260 | #define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS & u32Mask ) |
sahilmgandhi | 18:6a4db94011d3 | 261 | |
sahilmgandhi | 18:6a4db94011d3 | 262 | /** |
sahilmgandhi | 18:6a4db94011d3 | 263 | * @brief This function clears the interrupt flag according to the mask parameter. |
sahilmgandhi | 18:6a4db94011d3 | 264 | * @param[in] i2s is the base address of I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 265 | * @param[in] u32Mask is the mask for the all interrupt flags. |
sahilmgandhi | 18:6a4db94011d3 | 266 | * @return none |
sahilmgandhi | 18:6a4db94011d3 | 267 | * \hideinitializer |
sahilmgandhi | 18:6a4db94011d3 | 268 | */ |
sahilmgandhi | 18:6a4db94011d3 | 269 | #define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS |= u32Mask ) |
sahilmgandhi | 18:6a4db94011d3 | 270 | |
sahilmgandhi | 18:6a4db94011d3 | 271 | /** |
sahilmgandhi | 18:6a4db94011d3 | 272 | * @brief Get transmit FIFO level |
sahilmgandhi | 18:6a4db94011d3 | 273 | * @param[in] i2s is the base address of I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 274 | * @return FIFO level |
sahilmgandhi | 18:6a4db94011d3 | 275 | * \hideinitializer |
sahilmgandhi | 18:6a4db94011d3 | 276 | */ |
sahilmgandhi | 18:6a4db94011d3 | 277 | #define I2S_GET_TX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS & I2S_STATUS_TXCNT_Msk) >> I2S_STATUS_TXCNT_Pos) & 0xF ) |
sahilmgandhi | 18:6a4db94011d3 | 278 | |
sahilmgandhi | 18:6a4db94011d3 | 279 | /** |
sahilmgandhi | 18:6a4db94011d3 | 280 | * @brief Get receive FIFO level |
sahilmgandhi | 18:6a4db94011d3 | 281 | * @param[in] i2s is the base address of I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 282 | * @return FIFO level |
sahilmgandhi | 18:6a4db94011d3 | 283 | * \hideinitializer |
sahilmgandhi | 18:6a4db94011d3 | 284 | */ |
sahilmgandhi | 18:6a4db94011d3 | 285 | #define I2S_GET_RX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS & I2S_STATUS_RXCNT_Msk) >> I2S_STATUS_RXCNT_Pos) & 0xF ) |
sahilmgandhi | 18:6a4db94011d3 | 286 | |
sahilmgandhi | 18:6a4db94011d3 | 287 | uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat, uint32_t u32AudioInterface); |
sahilmgandhi | 18:6a4db94011d3 | 288 | void I2S_Close(I2S_T *i2s); |
sahilmgandhi | 18:6a4db94011d3 | 289 | void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask); |
sahilmgandhi | 18:6a4db94011d3 | 290 | void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask); |
sahilmgandhi | 18:6a4db94011d3 | 291 | uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock); |
sahilmgandhi | 18:6a4db94011d3 | 292 | void I2S_DisableMCLK(I2S_T *i2s); |
sahilmgandhi | 18:6a4db94011d3 | 293 | |
sahilmgandhi | 18:6a4db94011d3 | 294 | /*@}*/ /* end of group NUC472_442_I2S_EXPORTED_FUNCTIONS */ |
sahilmgandhi | 18:6a4db94011d3 | 295 | |
sahilmgandhi | 18:6a4db94011d3 | 296 | |
sahilmgandhi | 18:6a4db94011d3 | 297 | /*@}*/ /* end of group NUC472_442_I2S_Driver */ |
sahilmgandhi | 18:6a4db94011d3 | 298 | |
sahilmgandhi | 18:6a4db94011d3 | 299 | /*@}*/ /* end of group NUC472_442_Device_Driver */ |
sahilmgandhi | 18:6a4db94011d3 | 300 | |
sahilmgandhi | 18:6a4db94011d3 | 301 | #ifdef __cplusplus |
sahilmgandhi | 18:6a4db94011d3 | 302 | } |
sahilmgandhi | 18:6a4db94011d3 | 303 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 304 | |
sahilmgandhi | 18:6a4db94011d3 | 305 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 306 | |
sahilmgandhi | 18:6a4db94011d3 | 307 | /*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/ |
sahilmgandhi | 18:6a4db94011d3 | 308 |