MouseCode - Mouse code for the MacroRat

MacroRat » Code » MouseCode

Mouse code for the MacroRat

Dependencies: ITG3200 QEI

mbed-dev/targets/TARGET_NUVOTON/TARGET_NUC472/device/NUC472_442.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:: sahilmgandhi
Date:: Sat Jun 03 00:22:44 2017 +0000
Revision:: 46:b156ef445742
Parent:: 18:6a4db94011d3

Final code for internal battlebot competition.

Who changed what in which revision?

User	Revision	Line number	New contents of line
sahilmgandhi	18:6a4db94011d3	1	/************************************************************************//
sahilmgandhi	18:6a4db94011d3	2	* @file NUC472_442.h
sahilmgandhi	18:6a4db94011d3	3	* @version V1.00
sahilmgandhi	18:6a4db94011d3	4	* $Revision: 156 $
sahilmgandhi	18:6a4db94011d3	5	* $Date: 14/10/08 9:26a $
sahilmgandhi	18:6a4db94011d3	6	* @brief NUC472/NUC442 peripheral access layer header file.
sahilmgandhi	18:6a4db94011d3	7	* This file contains all the peripheral register's definitions,
sahilmgandhi	18:6a4db94011d3	8	* bits definitions and memory mapping for NuMicro NUC472/NUC442 MCU.
sahilmgandhi	18:6a4db94011d3	9	* @note
sahilmgandhi	18:6a4db94011d3	10	* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
sahilmgandhi	18:6a4db94011d3	11	*****************************************************************************/
sahilmgandhi	18:6a4db94011d3	12	/**
sahilmgandhi	18:6a4db94011d3	13	\mainpage NuMicro NUC472/NUC442 MCU Driver Reference Guide
sahilmgandhi	18:6a4db94011d3	14	*
sahilmgandhi	18:6a4db94011d3	15	* <b>Introduction</b>
sahilmgandhi	18:6a4db94011d3	16	*
sahilmgandhi	18:6a4db94011d3	17	* This user manual describes the usage of NUC472/NUC442 MCU device driver
sahilmgandhi	18:6a4db94011d3	18	*
sahilmgandhi	18:6a4db94011d3	19	* <b>Disclaimer</b>
sahilmgandhi	18:6a4db94011d3	20	*
sahilmgandhi	18:6a4db94011d3	21	* The Software is furnished "AS IS", without warranty as to performance or results, and
sahilmgandhi	18:6a4db94011d3	22	* the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all
sahilmgandhi	18:6a4db94011d3	23	* warranties, express, implied or otherwise, with regard to the Software, its use, or
sahilmgandhi	18:6a4db94011d3	24	* operation, including without limitation any and all warranties of merchantability, fitness
sahilmgandhi	18:6a4db94011d3	25	* for a particular purpose, and non-infringement of intellectual property rights.
sahilmgandhi	18:6a4db94011d3	26	*
sahilmgandhi	18:6a4db94011d3	27	* <b>Important Notice</b>
sahilmgandhi	18:6a4db94011d3	28	*
sahilmgandhi	18:6a4db94011d3	29	* Nuvoton Products are neither intended nor warranted for usage in systems or equipment,
sahilmgandhi	18:6a4db94011d3	30	* any malfunction or failure of which may cause loss of human life, bodily injury or severe
sahilmgandhi	18:6a4db94011d3	31	* property damage. Such applications are deemed, "Insecure Usage".
sahilmgandhi	18:6a4db94011d3	32	*
sahilmgandhi	18:6a4db94011d3	33	* Insecure usage includes, but is not limited to: equipment for surgical implementation,
sahilmgandhi	18:6a4db94011d3	34	* atomic energy control instruments, airplane or spaceship instruments, the control or
sahilmgandhi	18:6a4db94011d3	35	* operation of dynamic, brake or safety systems designed for vehicular use, traffic signal
sahilmgandhi	18:6a4db94011d3	36	* instruments, all types of safety devices, and other applications intended to support or
sahilmgandhi	18:6a4db94011d3	37	* sustain life.
sahilmgandhi	18:6a4db94011d3	38	*
sahilmgandhi	18:6a4db94011d3	39	* All Insecure Usage shall be made at customer's risk, and in the event that third parties
sahilmgandhi	18:6a4db94011d3	40	* lay claims to Nuvoton as a result of customer's Insecure Usage, customer shall indemnify
sahilmgandhi	18:6a4db94011d3	41	* the damages and liabilities thus incurred by Nuvoton.
sahilmgandhi	18:6a4db94011d3	42	*
sahilmgandhi	18:6a4db94011d3	43	* Please note that all data and specifications are subject to change without notice. All the
sahilmgandhi	18:6a4db94011d3	44	* trademarks of products and companies mentioned in this document belong to their respective
sahilmgandhi	18:6a4db94011d3	45	* owners.
sahilmgandhi	18:6a4db94011d3	46	*
sahilmgandhi	18:6a4db94011d3	47	* <b>Copyright Notice</b>
sahilmgandhi	18:6a4db94011d3	48	*
sahilmgandhi	18:6a4db94011d3	49	* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
sahilmgandhi	18:6a4db94011d3	50	*/
sahilmgandhi	18:6a4db94011d3	51	/**
sahilmgandhi	18:6a4db94011d3	52	* \page pg1 NuMicro NUC472/NUC442 BSP Directory Structure
sahilmgandhi	18:6a4db94011d3	53	* Please refer to Readme.pdf under BSP root directory for the BSP directory structure
sahilmgandhi	18:6a4db94011d3	54	*
sahilmgandhi	18:6a4db94011d3	55	* \page pg2 Revision History
sahilmgandhi	18:6a4db94011d3	56	*
sahilmgandhi	18:6a4db94011d3	57	* <b>Revision 3.01.001</b>
sahilmgandhi	18:6a4db94011d3	58	* \li Removed NVIC_EnableIRQ() function call in I2S_Open() and SD_Open().
sahilmgandhi	18:6a4db94011d3	59	* \li Removed PI definition and add GPI definition.
sahilmgandhi	18:6a4db94011d3	60	* \li Removed uCOS-II and uCOS-III samples.
sahilmgandhi	18:6a4db94011d3	61	* \li Renamed CAN_NOTMAL_MODE to CAN_NORMAL_MODE.
sahilmgandhi	18:6a4db94011d3	62	* \li Renamed UBSD_() macros to USBD_().
sahilmgandhi	18:6a4db94011d3	63	* \li Renamed USBH registers and related bit name.
sahilmgandhi	18:6a4db94011d3	64	* \li Renamed PD13MFP_SC3_SS0 to PD13MFP_SPI1_SS0.
sahilmgandhi	18:6a4db94011d3	65	* \li Replaced the USBH_ProcessHubEvents() and usb_hub_events() return type from void to int.
sahilmgandhi	18:6a4db94011d3	66	* \li Updated original USBH HID library with Nuvoton HID library with less footprint.
sahilmgandhi	18:6a4db94011d3	67	* \li Updated bit filed definition of register VREFCTL.
sahilmgandhi	18:6a4db94011d3	68	* \li Enable branch buffer starting from version E MCU.
sahilmgandhi	18:6a4db94011d3	69	* \li Added RTX support.
sahilmgandhi	18:6a4db94011d3	70	* \li Added EADC driver.
sahilmgandhi	18:6a4db94011d3	71	* \li Added Cortex-M4 BitBand and MPU sample codes.
sahilmgandhi	18:6a4db94011d3	72	* \li Added ADC_PDMA, EADC_ADINT_Trigger, EADC_Compare, EADC_STADC_Trigger, EADC_SWTRG_Trigger, EADC_Timer_Trigger, I2S_NAU8822_PDMA, ISP_Updater,
sahilmgandhi	18:6a4db94011d3	73	* USBD_Bulk, USBD_HID_Mouse_Vendor, USBD_HID_MouseKeyboard, USBD_HID_Transfer, USBD_VCOM_SerialEmulator, USBD_VENDOR_LBK, USBH_VENDOR_LBK samples.
sahilmgandhi	18:6a4db94011d3	74	*
sahilmgandhi	18:6a4db94011d3	75	* <b>Revision 3.01.000</b>
sahilmgandhi	18:6a4db94011d3	76	* \li Rename registers and bit fields.
sahilmgandhi	18:6a4db94011d3	77	* \li Added Analog comparator (ACMP) driver
sahilmgandhi	18:6a4db94011d3	78	* \li Added I2S, ACMP ,and USBD sample codes
sahilmgandhi	18:6a4db94011d3	79	* \li Minor bug fix.
sahilmgandhi	18:6a4db94011d3	80	*
sahilmgandhi	18:6a4db94011d3	81	* <b>Revision 3.00.001</b>
sahilmgandhi	18:6a4db94011d3	82	* \li Improved PWM driver performance.
sahilmgandhi	18:6a4db94011d3	83	* \li Renamed EPWM register PWM0/2/4 to PWM_CH0/2/4.
sahilmgandhi	18:6a4db94011d3	84	* \li Updated IAR project files to support Nu-Link IAR driver v6287 or above.
sahilmgandhi	18:6a4db94011d3	85	* \li Removed learning board sample code directory NUC472-LB.
sahilmgandhi	18:6a4db94011d3	86	* \li Added wave player and hard fault sample.
sahilmgandhi	18:6a4db94011d3	87	* \li Minor bug fix.
sahilmgandhi	18:6a4db94011d3	88	*
sahilmgandhi	18:6a4db94011d3	89	* <b>Revision 3.00.000</b>
sahilmgandhi	18:6a4db94011d3	90	* \li Moved Smartcard library one directory level up to "Library\SmartcardLib\".
sahilmgandhi	18:6a4db94011d3	91	* \li Added OTG dual role sample code and Learning Board G-sensor sample code.
sahilmgandhi	18:6a4db94011d3	92	* \li Added FreeRTOS LwIP IAR project file.
sahilmgandhi	18:6a4db94011d3	93	* \li Renamed RTC_GetDatAndTime() to RTC_GetDateAndTime().
sahilmgandhi	18:6a4db94011d3	94	* \li Changed Major number from 1 to 3.
sahilmgandhi	18:6a4db94011d3	95	* \li Minor bug fix.
sahilmgandhi	18:6a4db94011d3	96	*
sahilmgandhi	18:6a4db94011d3	97	* <b>Revision 1.00.000</b>
sahilmgandhi	18:6a4db94011d3	98	* \li Added CAN, SD, SC, SCUART driver and samples.
sahilmgandhi	18:6a4db94011d3	99	* \li Added smartcard 7816-3 library.
sahilmgandhi	18:6a4db94011d3	100	* \li Added NUC472 Tiny Board sample.
sahilmgandhi	18:6a4db94011d3	101	* \li Renamed I2C_GetClockBusFreq() to I2C_GetBusClockFreq().
sahilmgandhi	18:6a4db94011d3	102	* \li Renamed I2C_SetClockBusFreq() to I2C_SetBusClockFreq().
sahilmgandhi	18:6a4db94011d3	103	* \li Renamed I2C_SetSlaveMask() to I2C_SetSlaveAddrMask().
sahilmgandhi	18:6a4db94011d3	104	* \li Minor bug fix.
sahilmgandhi	18:6a4db94011d3	105	*
sahilmgandhi	18:6a4db94011d3	106	* <b>Revision 0.10.000</b>
sahilmgandhi	18:6a4db94011d3	107	* \li Added I2S, PDMA driver.
sahilmgandhi	18:6a4db94011d3	108	* \li Added Learning Board and Standard Driver samples.
sahilmgandhi	18:6a4db94011d3	109	* \li Added FreeRTOS lwIP sample.
sahilmgandhi	18:6a4db94011d3	110	*
sahilmgandhi	18:6a4db94011d3	111	* <b>Revision 0.09.000</b>
sahilmgandhi	18:6a4db94011d3	112	* \li Added CAP, EBI, I2C, PWM, SPI, USBD, USBH drivers and samples.
sahilmgandhi	18:6a4db94011d3	113	* \li Added uCOS-II and uCOS-III samples.
sahilmgandhi	18:6a4db94011d3	114	* \li Added FreeRTOS source code and sample.
sahilmgandhi	18:6a4db94011d3	115	*
sahilmgandhi	18:6a4db94011d3	116	* <b>Revision 0.08.000</b>
sahilmgandhi	18:6a4db94011d3	117	* \li Preliminary release.
sahilmgandhi	18:6a4db94011d3	118	*/
sahilmgandhi	18:6a4db94011d3	119	#ifndef __NUC472_442_H__
sahilmgandhi	18:6a4db94011d3	120	#define __NUC472_442_H__
sahilmgandhi	18:6a4db94011d3	121
sahilmgandhi	18:6a4db94011d3	122	#ifdef __cplusplus
sahilmgandhi	18:6a4db94011d3	123	extern "C" {
sahilmgandhi	18:6a4db94011d3	124	#endif
sahilmgandhi	18:6a4db94011d3	125
sahilmgandhi	18:6a4db94011d3	126	/******************************************************************************/
sahilmgandhi	18:6a4db94011d3	127	/* Processor and Core Peripherals */
sahilmgandhi	18:6a4db94011d3	128	/******************************************************************************/
sahilmgandhi	18:6a4db94011d3	129	/** @addtogroup NUC472_442_CMSIS NUC472/NUC442 Device CMSIS Definitions
sahilmgandhi	18:6a4db94011d3	130	Configuration of the Cortex-M4 Processor and Core Peripherals
sahilmgandhi	18:6a4db94011d3	131	@{
sahilmgandhi	18:6a4db94011d3	132	*/
sahilmgandhi	18:6a4db94011d3	133
sahilmgandhi	18:6a4db94011d3	134	/**
sahilmgandhi	18:6a4db94011d3	135	* @details Interrupt Number Definition.
sahilmgandhi	18:6a4db94011d3	136	*/
sahilmgandhi	18:6a4db94011d3	137	typedef enum IRQn {
sahilmgandhi	18:6a4db94011d3	138	/**** Cortex-M4 Processor Exceptions Numbers *************************************************/
sahilmgandhi	18:6a4db94011d3	139	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
sahilmgandhi	18:6a4db94011d3	140	MemoryManagement_IRQn = -12, /!< 4 Memory Management Interrupt /
sahilmgandhi	18:6a4db94011d3	141	BusFault_IRQn = -11, /!< 5 Bus Fault Interrupt /
sahilmgandhi	18:6a4db94011d3	142	UsageFault_IRQn = -10, /!< 6 Usage Fault Interrupt /
sahilmgandhi	18:6a4db94011d3	143	SVCall_IRQn = -5, /!< 11 SV Call Interrupt /
sahilmgandhi	18:6a4db94011d3	144	DebugMonitor_IRQn = -4, /!< 12 Debug Monitor Interrupt /
sahilmgandhi	18:6a4db94011d3	145	PendSV_IRQn = -2, /!< 14 Pend SV Interrupt /
sahilmgandhi	18:6a4db94011d3	146	SysTick_IRQn = -1, /!< 15 System Tick Interrupt /
sahilmgandhi	18:6a4db94011d3	147
sahilmgandhi	18:6a4db94011d3	148	/**** NUC472/NUC442 Specific Interrupt Numbers ******************************************************/
sahilmgandhi	18:6a4db94011d3	149
sahilmgandhi	18:6a4db94011d3	150	BOD_IRQn = 0, /!< Brown Out detection Interrupt /
sahilmgandhi	18:6a4db94011d3	151	IRC_IRQn = 1, /!< Internal RC Interrupt /
sahilmgandhi	18:6a4db94011d3	152	PWRWU_IRQn = 2, /!< Power Down Wake Up Interrupt /
sahilmgandhi	18:6a4db94011d3	153	SRAMF_IRQn = 3, /!< SRAM Parity Check Failed Interrupt /
sahilmgandhi	18:6a4db94011d3	154	CLKF_IRQn = 4, /!< Clock Detection Failed Interrupt /
sahilmgandhi	18:6a4db94011d3	155	RTC_IRQn = 6, /!< Real Time Clock Interrupt /
sahilmgandhi	18:6a4db94011d3	156	TAMPER_IRQn = 7, /!< Tamper detection Interrupt /
sahilmgandhi	18:6a4db94011d3	157	EINT0_IRQn = 8, /!< External Input 0 Interrupt /
sahilmgandhi	18:6a4db94011d3	158	EINT1_IRQn = 9, /!< External Input 1 Interrupt /
sahilmgandhi	18:6a4db94011d3	159	EINT2_IRQn = 10, /!< External Input 2 Interrupt /
sahilmgandhi	18:6a4db94011d3	160	EINT3_IRQn = 11, /!< External Input 3 Interrupt /
sahilmgandhi	18:6a4db94011d3	161	EINT4_IRQn = 12, /!< External Input 4 Interrupt /
sahilmgandhi	18:6a4db94011d3	162	EINT5_IRQn = 13, /!< External Input 5 Interrupt /
sahilmgandhi	18:6a4db94011d3	163	EINT6_IRQn = 14, /!< External Input 6 Interrupt /
sahilmgandhi	18:6a4db94011d3	164	EINT7_IRQn = 15, /!< External Input 7 Interrupt /
sahilmgandhi	18:6a4db94011d3	165	GPA_IRQn = 16, /!< GPIO Port A Interrupt /
sahilmgandhi	18:6a4db94011d3	166	GPB_IRQn = 17, /!< GPIO Port B Interrupt /
sahilmgandhi	18:6a4db94011d3	167	GPC_IRQn = 18, /!< GPIO Port C Interrupt /
sahilmgandhi	18:6a4db94011d3	168	GPD_IRQn = 19, /!< GPIO Port D Interrupt /
sahilmgandhi	18:6a4db94011d3	169	GPE_IRQn = 20, /!< GPIO Port E Interrupt /
sahilmgandhi	18:6a4db94011d3	170	GPF_IRQn = 21, /!< GPIO Port F Interrupt /
sahilmgandhi	18:6a4db94011d3	171	GPG_IRQn = 22, /!< GPIO Port G Interrupt /
sahilmgandhi	18:6a4db94011d3	172	GPH_IRQn = 23, /!< GPIO Port H Interrupt /
sahilmgandhi	18:6a4db94011d3	173	GPI_IRQn = 24, /!< GPIO Port I Interrupt /
sahilmgandhi	18:6a4db94011d3	174	TMR0_IRQn = 32, /!< Timer 0 Interrupt /
sahilmgandhi	18:6a4db94011d3	175	TMR1_IRQn = 33, /!< Timer 1 Interrupt /
sahilmgandhi	18:6a4db94011d3	176	TMR2_IRQn = 34, /!< Timer 2 Interrupt /
sahilmgandhi	18:6a4db94011d3	177	TMR3_IRQn = 35, /!< Timer 3 Interrupt /
sahilmgandhi	18:6a4db94011d3	178	PDMA_IRQn = 40, /!< Peripheral DMA Interrupt /
sahilmgandhi	18:6a4db94011d3	179	ADC_IRQn = 42, /!< ADC Interrupt /
sahilmgandhi	18:6a4db94011d3	180	WDT_IRQn = 46, /!< Watch Dog Timer Interrupt /
sahilmgandhi	18:6a4db94011d3	181	WWDT_IRQn = 47, /!< Window Watch Dog Timer Interrupt /
sahilmgandhi	18:6a4db94011d3	182	EADC0_IRQn = 48, /!< Enhanced ADC 0 Interrupt /
sahilmgandhi	18:6a4db94011d3	183	EADC1_IRQn = 49, /!< Enhanced ADC 1 Interrupt /
sahilmgandhi	18:6a4db94011d3	184	EADC2_IRQn = 50, /!< Enhanced ADC 2 Interrupt /
sahilmgandhi	18:6a4db94011d3	185	EADC3_IRQn = 51, /!< Enhanced ADC 3 Interrupt /
sahilmgandhi	18:6a4db94011d3	186	ACMP_IRQn = 56, /!< Analog Comparator Interrupt /
sahilmgandhi	18:6a4db94011d3	187	OPA0_IRQn = 60, /!< OPA 0 Interrupt /
sahilmgandhi	18:6a4db94011d3	188	OPA1_IRQn = 61, /!< OPA 1 Interrupt /
sahilmgandhi	18:6a4db94011d3	189	ICAP0_IRQn = 62, /!< Input Capture 0 Interrupt /
sahilmgandhi	18:6a4db94011d3	190	ICAP1_IRQn = 63, /!< Input Capture 1 Interrupt /
sahilmgandhi	18:6a4db94011d3	191	PWM0CH0_IRQn = 64, /!< PWM 0 Channel 0 Interrupt /
sahilmgandhi	18:6a4db94011d3	192	PWM0CH1_IRQn = 65, /!< PWM 0 Channel 1 Interrupt /
sahilmgandhi	18:6a4db94011d3	193	PWM0CH2_IRQn = 66, /!< PWM 0 Channel 2 Interrupt /
sahilmgandhi	18:6a4db94011d3	194	PWM0CH3_IRQn = 67, /!< PWM 0 Channel 3 Interrupt /
sahilmgandhi	18:6a4db94011d3	195	PWM0CH4_IRQn = 68, /!< PWM 0 Channel 4 Interrupt /
sahilmgandhi	18:6a4db94011d3	196	PWM0CH5_IRQn = 69, /!< PWM 0 Channel 5 Interrupt /
sahilmgandhi	18:6a4db94011d3	197	PWM0_BRK_IRQn = 70, /!< PWM 0 Break Interrupt /
sahilmgandhi	18:6a4db94011d3	198	QEI0_IRQn = 71, /!< QEI 0 Interrupt /
sahilmgandhi	18:6a4db94011d3	199	PWM1CH0_IRQn = 72, /!< PWM 1 Channel 0 Interrupt /
sahilmgandhi	18:6a4db94011d3	200	PWM1CH1_IRQn = 73, /!< PWM 1 Channel 1 Interrupt /
sahilmgandhi	18:6a4db94011d3	201	PWM1CH2_IRQn = 74, /!< PWM 1 Channel 2 Interrupt /
sahilmgandhi	18:6a4db94011d3	202	PWM1CH3_IRQn = 75, /!< PWM 1 Channel 3 Interrupt /
sahilmgandhi	18:6a4db94011d3	203	PWM1CH4_IRQn = 76, /!< PWM 1 Channel 4 Interrupt /
sahilmgandhi	18:6a4db94011d3	204	PWM1CH5_IRQn = 77, /!< PWM 1 Channel 5 Interrupt /
sahilmgandhi	18:6a4db94011d3	205	PWM1_BRK_IRQn = 78, /!< PWM 1 Break Interrupt /
sahilmgandhi	18:6a4db94011d3	206	QEI1_IRQn = 79, /!< QEI 1 Interrupt /
sahilmgandhi	18:6a4db94011d3	207	EPWM0_IRQn = 80, /!< Enhanced PWM 0 Interrupt /
sahilmgandhi	18:6a4db94011d3	208	EPWM0BRK_IRQn = 81, /!< Enhanced PWM 0 Break Interrupt /
sahilmgandhi	18:6a4db94011d3	209	EPWM1_IRQn = 82, /!< Enhanced PWM 1 Interrupt /
sahilmgandhi	18:6a4db94011d3	210	EPWM1BRK_IRQn = 83, /!< Enhanced PWM 1 Break Interrupt /
sahilmgandhi	18:6a4db94011d3	211	USBD_IRQn = 88, /!< USB FS Device Interrupt /
sahilmgandhi	18:6a4db94011d3	212	USBH_IRQn = 89, /!< USB FS Host Interrupt /
sahilmgandhi	18:6a4db94011d3	213	USB_OTG_IRQn = 90, /!< USB OTG Interrupt /
sahilmgandhi	18:6a4db94011d3	214	EMAC_TX_IRQn = 92, /!< Ethernet MAC TX Interrupt /
sahilmgandhi	18:6a4db94011d3	215	EMAC_RX_IRQn = 93, /!< Ethernet MAC RX Interrupt /
sahilmgandhi	18:6a4db94011d3	216	SPI0_IRQn = 96, /!< SPI 0 Interrupt /
sahilmgandhi	18:6a4db94011d3	217	SPI1_IRQn = 97, /!< SPI 1 Interrupt /
sahilmgandhi	18:6a4db94011d3	218	SPI2_IRQn = 98, /!< SPI 2 Interrupt /
sahilmgandhi	18:6a4db94011d3	219	SPI3_IRQn = 99, /!< SPI 3 Interrupt /
sahilmgandhi	18:6a4db94011d3	220	UART0_IRQn = 104, /!< UART 0 Interrupt /
sahilmgandhi	18:6a4db94011d3	221	UART1_IRQn = 105, /!< UART 1 Interrupt /
sahilmgandhi	18:6a4db94011d3	222	UART2_IRQn = 106, /!< UART 2 Interrupt /
sahilmgandhi	18:6a4db94011d3	223	UART3_IRQn = 107, /!< UART 3 Interrupt /
sahilmgandhi	18:6a4db94011d3	224	UART4_IRQn = 108, /!< UART 4 Interrupt /
sahilmgandhi	18:6a4db94011d3	225	UART5_IRQn = 109, /!< UART 5 Interrupt /
sahilmgandhi	18:6a4db94011d3	226	I2C0_IRQn = 112, /!< I2C 0 Interrupt /
sahilmgandhi	18:6a4db94011d3	227	I2C1_IRQn = 113, /!< I2C 1 Interrupt /
sahilmgandhi	18:6a4db94011d3	228	I2C2_IRQn = 114, /!< I2C 2 Interrupt /
sahilmgandhi	18:6a4db94011d3	229	I2C3_IRQn = 115, /!< I2C 3 Interrupt /
sahilmgandhi	18:6a4db94011d3	230	I2C4_IRQn = 116, /!< I2C 4 Interrupt /
sahilmgandhi	18:6a4db94011d3	231	SC0_IRQn = 120, /!< Smart Card 0 Interrupt /
sahilmgandhi	18:6a4db94011d3	232	SC1_IRQn = 121, /!< Smart Card 1 Interrupt /
sahilmgandhi	18:6a4db94011d3	233	SC2_IRQn = 122, /!< Smart Card 2 Interrupt /
sahilmgandhi	18:6a4db94011d3	234	SC3_IRQn = 123, /!< Smart Card 3 Interrupt /
sahilmgandhi	18:6a4db94011d3	235	SC4_IRQn = 124, /!< Smart Card 4 Interrupt /
sahilmgandhi	18:6a4db94011d3	236	SC5_IRQn = 125, /!< Smart Card 5 Interrupt /
sahilmgandhi	18:6a4db94011d3	237	CAN0_IRQn = 128, /!< CAN 0 Interrupt /
sahilmgandhi	18:6a4db94011d3	238	CAN1_IRQn = 129, /!< CAN 1 Interrupt /
sahilmgandhi	18:6a4db94011d3	239	I2S0_IRQn = 132, /!< I2S 0 Interrupt /
sahilmgandhi	18:6a4db94011d3	240	I2S1_IRQn = 133, /!< I2S 1 Interrupt /
sahilmgandhi	18:6a4db94011d3	241	SD_IRQn = 136, /!< SD Host Interrupt /
sahilmgandhi	18:6a4db94011d3	242	PS2D_IRQn = 138, /!< PS/2 device Interrupt /
sahilmgandhi	18:6a4db94011d3	243	CAP_IRQn = 139, /!< VCAP Interrupt /
sahilmgandhi	18:6a4db94011d3	244	CRPT_IRQn = 140, /!< Cryptographic Accelerator Interrupt /
sahilmgandhi	18:6a4db94011d3	245	CRC_IRQn = 141, /!< CRC Interrupt /
sahilmgandhi	18:6a4db94011d3	246	}
sahilmgandhi	18:6a4db94011d3	247	IRQn_Type;
sahilmgandhi	18:6a4db94011d3	248
sahilmgandhi	18:6a4db94011d3	249
sahilmgandhi	18:6a4db94011d3	250	/*
sahilmgandhi	18:6a4db94011d3	251	* ==========================================================================
sahilmgandhi	18:6a4db94011d3	252	* ----------- Processor and Core Peripheral Section ------------------------
sahilmgandhi	18:6a4db94011d3	253	* ==========================================================================
sahilmgandhi	18:6a4db94011d3	254	*/
sahilmgandhi	18:6a4db94011d3	255
sahilmgandhi	18:6a4db94011d3	256	/* Configuration of the Cortex-M# Processor and Core Peripherals */
sahilmgandhi	18:6a4db94011d3	257	#define __CM4_REV 0x0201 /!< Core Revision r2p1 /
sahilmgandhi	18:6a4db94011d3	258	#define __NVIC_PRIO_BITS 4 /!< Number of Bits used for Priority Levels /
sahilmgandhi	18:6a4db94011d3	259	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
sahilmgandhi	18:6a4db94011d3	260	#define __MPU_PRESENT 1 /!< MPU present or not /
sahilmgandhi	18:6a4db94011d3	261	#define __FPU_PRESENT 1 /!< FPU present or not /
sahilmgandhi	18:6a4db94011d3	262
sahilmgandhi	18:6a4db94011d3	263	/@}/ /* end of group NUC472_442_CMSIS */
sahilmgandhi	18:6a4db94011d3	264
sahilmgandhi	18:6a4db94011d3	265
sahilmgandhi	18:6a4db94011d3	266	#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
sahilmgandhi	18:6a4db94011d3	267	#include "system_NUC472_442.h" /* NUC472/NUC442 System include file */
sahilmgandhi	18:6a4db94011d3	268	#include <stdint.h>
sahilmgandhi	18:6a4db94011d3	269
sahilmgandhi	18:6a4db94011d3	270	/******************************************************************************/
sahilmgandhi	18:6a4db94011d3	271	/* Device Specific Peripheral registers structures */
sahilmgandhi	18:6a4db94011d3	272	/******************************************************************************/
sahilmgandhi	18:6a4db94011d3	273	/** @addtogroup NUC472_442_Peripherals NUC472/NUC442 Control Register
sahilmgandhi	18:6a4db94011d3	274	NUC472/NUC442 Device Specific Peripheral registers structures
sahilmgandhi	18:6a4db94011d3	275	@{
sahilmgandhi	18:6a4db94011d3	276	*/
sahilmgandhi	18:6a4db94011d3	277
sahilmgandhi	18:6a4db94011d3	278	#if defined ( __CC_ARM )
sahilmgandhi	18:6a4db94011d3	279	#pragma anon_unions
sahilmgandhi	18:6a4db94011d3	280	#endif
sahilmgandhi	18:6a4db94011d3	281
sahilmgandhi	18:6a4db94011d3	282
sahilmgandhi	18:6a4db94011d3	283	/---------------------- Analog Comparator Controller -------------------------/
sahilmgandhi	18:6a4db94011d3	284	/**
sahilmgandhi	18:6a4db94011d3	285	@addtogroup ACMP Analog Comparator Controller(ACMP)
sahilmgandhi	18:6a4db94011d3	286	Memory Mapped Structure for ACMP Controller
sahilmgandhi	18:6a4db94011d3	287	@{ */
sahilmgandhi	18:6a4db94011d3	288
sahilmgandhi	18:6a4db94011d3	289	typedef struct {
sahilmgandhi	18:6a4db94011d3	290
sahilmgandhi	18:6a4db94011d3	291
sahilmgandhi	18:6a4db94011d3	292	/**
sahilmgandhi	18:6a4db94011d3	293	* CTL0, CTL1, CTL2
sahilmgandhi	18:6a4db94011d3	294	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	295	* Offset: 0x00~0x08 Analog Comparator 0/1/2 Control Register
sahilmgandhi	18:6a4db94011d3	296	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	297	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	298	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	299	* \|[0] \|ACMPEN \|Comparator 0 Enable Control
sahilmgandhi	18:6a4db94011d3	300	* \| \| \|0 = Comparator 0 Disabled.
sahilmgandhi	18:6a4db94011d3	301	* \| \| \|1 = Comparator 0 Enabled.
sahilmgandhi	18:6a4db94011d3	302	* \| \| \|Note: The comparator output needs to wait 2 us stable time after ACMPEN is set.
sahilmgandhi	18:6a4db94011d3	303	* \|[1] \|ACMPIE \|Comparator 0 Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	304	* \| \| \|0 = Comparator 0 interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	305	* \| \| \|1 = Comparator 0 interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	306	* \|[2] \|HYSEN \|Comparator 0 Hysteresis Enable Control
sahilmgandhi	18:6a4db94011d3	307	* \| \| \|0 = Comparator 0 hysteresis Disabled (Default).
sahilmgandhi	18:6a4db94011d3	308	* \| \| \|1 = Comparator 0 hysteresis Enabled (typical range is 20 mV).
sahilmgandhi	18:6a4db94011d3	309	* \|[3] \|ACMPOINV \|Comparator 0 Output Inverse
sahilmgandhi	18:6a4db94011d3	310	* \| \| \|0 = Comparator 0 output inverse Disabled.
sahilmgandhi	18:6a4db94011d3	311	* \| \| \|1 = Comparator 0 output inverse Enabled.
sahilmgandhi	18:6a4db94011d3	312	* \|[4] \|NEGSEL \|Comparator 0 Negative Input Selection
sahilmgandhi	18:6a4db94011d3	313	* \| \| \|0 = The source of comparator 0 negative input is from ACMP0_N pin.
sahilmgandhi	18:6a4db94011d3	314	* \| \| \|1 = The internal comparator reference voltage (Band-gap voltage or CRV) is selected as the source of comparator 0 negative input.
sahilmgandhi	18:6a4db94011d3	315	* \|[5:7] \|POSSEL \|Comparator 0 Positive Input Selection
sahilmgandhi	18:6a4db94011d3	316	* \| \| \|000= Input from ACMP0_P0.
sahilmgandhi	18:6a4db94011d3	317	* \| \| \|001= Input from ACMP0_P1.
sahilmgandhi	18:6a4db94011d3	318	* \| \| \|010= Input from ACMP0_P2.
sahilmgandhi	18:6a4db94011d3	319	* \| \| \|011= Input from ACMP0_P3.
sahilmgandhi	18:6a4db94011d3	320	* \| \| \|100= Input from OPA0.
sahilmgandhi	18:6a4db94011d3	321	* \| \| \|The other options are reserved.
sahilmgandhi	18:6a4db94011d3	322	*/
sahilmgandhi	18:6a4db94011d3	323	__IO uint32_t CTL[3];
sahilmgandhi	18:6a4db94011d3	324
sahilmgandhi	18:6a4db94011d3	325	/**
sahilmgandhi	18:6a4db94011d3	326	* STATUS
sahilmgandhi	18:6a4db94011d3	327	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	328	* Offset: 0x0C Analog Comparator Status Register
sahilmgandhi	18:6a4db94011d3	329	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	330	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	331	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	332	* \|[0] \|ACMPIF0 \|Comparator 0 Flag
sahilmgandhi	18:6a4db94011d3	333	* \| \| \|This bit is set by hardware whenever the comparator 0 output changes state.
sahilmgandhi	18:6a4db94011d3	334	* \| \| \|This will cause an interrupt if ACMP_CTL0[1] is set to 1.
sahilmgandhi	18:6a4db94011d3	335	* \| \| \|Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	336	* \|[1] \|ACMPIF1 \|Comparator 1 Flag
sahilmgandhi	18:6a4db94011d3	337	* \| \| \|This bit is set by hardware whenever the comparator 1 output changes state.
sahilmgandhi	18:6a4db94011d3	338	* \| \| \|This will cause an interrupt if ACMP_CTL1[1] is set to 1.
sahilmgandhi	18:6a4db94011d3	339	* \| \| \|Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	340	* \|[2] \|ACMPIF2 \|Comparator 2 Flag
sahilmgandhi	18:6a4db94011d3	341	* \| \| \|This bit is set by hardware whenever the comparator 2 output changes state.
sahilmgandhi	18:6a4db94011d3	342	* \| \| \|This will cause an interrupt if ACMP_CTL2[1] is set to 1.
sahilmgandhi	18:6a4db94011d3	343	* \| \| \|Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	344	* \|[3] \|ACMPO0 \|Comparator 0 Output
sahilmgandhi	18:6a4db94011d3	345	* \| \| \|Synchronized to the APB clock to allow reading by software.
sahilmgandhi	18:6a4db94011d3	346	* \| \| \|Cleared when the comparator 0 is disabled (ACMP_CTL0[0] = 0).
sahilmgandhi	18:6a4db94011d3	347	* \|[4] \|ACMPO1 \|Comparator 1 Output
sahilmgandhi	18:6a4db94011d3	348	* \| \| \|Synchronized to the APB clock to allow reading by software.
sahilmgandhi	18:6a4db94011d3	349	* \| \| \|Cleared when the comparator 1 is disabled (ACMP_CTL1[0] = 0).
sahilmgandhi	18:6a4db94011d3	350	* \|[5] \|ACMPO2 \|Comparator 2 Output
sahilmgandhi	18:6a4db94011d3	351	* \| \| \|Synchronized to the APB clock to allow reading by software.
sahilmgandhi	18:6a4db94011d3	352	* \| \| \|Cleared when the comparator 2 is disabled (ACMP_CTL2[0] = 0).
sahilmgandhi	18:6a4db94011d3	353	*/
sahilmgandhi	18:6a4db94011d3	354	__IO uint32_t STATUS;
sahilmgandhi	18:6a4db94011d3	355
sahilmgandhi	18:6a4db94011d3	356	/**
sahilmgandhi	18:6a4db94011d3	357	* VREF
sahilmgandhi	18:6a4db94011d3	358	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	359	* Offset: 0x10 Analog Comparator Reference Voltage Control Register
sahilmgandhi	18:6a4db94011d3	360	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	361	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	362	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	363	* \|[0:3] \|CRVCTL \|Comparator Reference Voltage Setting
sahilmgandhi	18:6a4db94011d3	364	* \| \| \|CRV = CRV source voltage * (1/6+VREF[3:0]/24).
sahilmgandhi	18:6a4db94011d3	365	* \|[6] \|CRVSSEL \|CRV Source Voltage Selection
sahilmgandhi	18:6a4db94011d3	366	* \| \| \|0 = VDDA is selected as CRV source voltage.
sahilmgandhi	18:6a4db94011d3	367	* \| \| \|1 = Internal reference voltage is selected as CRV source voltage.
sahilmgandhi	18:6a4db94011d3	368	* \|[7] \|IREFSEL \|Internal Reference Selection
sahilmgandhi	18:6a4db94011d3	369	* \| \| \|0 = Band-gap voltage is selected as internal reference.
sahilmgandhi	18:6a4db94011d3	370	* \| \| \|1 = CRV is selected as internal reference.
sahilmgandhi	18:6a4db94011d3	371	*/
sahilmgandhi	18:6a4db94011d3	372	__IO uint32_t VREF;
sahilmgandhi	18:6a4db94011d3	373
sahilmgandhi	18:6a4db94011d3	374	} ACMP_T;
sahilmgandhi	18:6a4db94011d3	375
sahilmgandhi	18:6a4db94011d3	376	/**
sahilmgandhi	18:6a4db94011d3	377	@addtogroup ACMP_CONST ACMP Bit Field Definition
sahilmgandhi	18:6a4db94011d3	378	Constant Definitions for ACMP Controller
sahilmgandhi	18:6a4db94011d3	379	@{ */
sahilmgandhi	18:6a4db94011d3	380
sahilmgandhi	18:6a4db94011d3	381	#define ACMP_CTL_ACMPEN_Pos (0) /!< ACMP CTL: ACMPEN Position /
sahilmgandhi	18:6a4db94011d3	382	#define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /!< ACMP CTL: ACMPEN Mask /
sahilmgandhi	18:6a4db94011d3	383
sahilmgandhi	18:6a4db94011d3	384	#define ACMP_CTL_ACMPIE_Pos (1) /!< ACMP CTL: ACMPIE Position /
sahilmgandhi	18:6a4db94011d3	385	#define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /!< ACMP CTL: ACMPIE Mask /
sahilmgandhi	18:6a4db94011d3	386
sahilmgandhi	18:6a4db94011d3	387	#define ACMP_CTL_HYSEN_Pos (2) /!< ACMP CTL: HYSEN Position /
sahilmgandhi	18:6a4db94011d3	388	#define ACMP_CTL_HYSEN_Msk (0x1ul << ACMP_CTL_HYSEN_Pos) /!< ACMP CTL: HYSEN Mask /
sahilmgandhi	18:6a4db94011d3	389
sahilmgandhi	18:6a4db94011d3	390	#define ACMP_CTL_ACMPOINV_Pos (3) /!< ACMP CTL: ACMPOINV Position /
sahilmgandhi	18:6a4db94011d3	391	#define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /!< ACMP CTL: ACMPOINV Mask /
sahilmgandhi	18:6a4db94011d3	392
sahilmgandhi	18:6a4db94011d3	393	#define ACMP_CTL_NEGSEL_Pos (4) /!< ACMP CTL: NEGSEL Position /
sahilmgandhi	18:6a4db94011d3	394	#define ACMP_CTL_NEGSEL_Msk (0x1ul << ACMP_CTL_NEGSEL_Pos) /!< ACMP CTL: NEGSEL Mask /
sahilmgandhi	18:6a4db94011d3	395
sahilmgandhi	18:6a4db94011d3	396	#define ACMP_CTL_POSSEL_Pos (5) /!< ACMP CTL: POSSEL Position /
sahilmgandhi	18:6a4db94011d3	397	#define ACMP_CTL_POSSEL_Msk (0x7ul << ACMP_CTL_POSSEL_Pos) /!< ACMP CTL: POSSEL Mask /
sahilmgandhi	18:6a4db94011d3	398
sahilmgandhi	18:6a4db94011d3	399	#define ACMP_STATUS_ACMPIF0_Pos (0) /!< ACMP STATUS: ACMPIF0 Position /
sahilmgandhi	18:6a4db94011d3	400	#define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /!< ACMP STATUS: ACMPIF0 Mask /
sahilmgandhi	18:6a4db94011d3	401
sahilmgandhi	18:6a4db94011d3	402	#define ACMP_STATUS_ACMPIF1_Pos (1) /!< ACMP STATUS: ACMPIF1 Position /
sahilmgandhi	18:6a4db94011d3	403	#define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /!< ACMP STATUS: ACMPIF1 Mask /
sahilmgandhi	18:6a4db94011d3	404
sahilmgandhi	18:6a4db94011d3	405	#define ACMP_STATUS_ACMPIF2_Pos (2) /!< ACMP STATUS: ACMPIF2 Position /
sahilmgandhi	18:6a4db94011d3	406	#define ACMP_STATUS_ACMPIF2_Msk (0x1ul << ACMP_STATUS_ACMPIF2_Pos) /!< ACMP STATUS: ACMPIF2 Mask /
sahilmgandhi	18:6a4db94011d3	407
sahilmgandhi	18:6a4db94011d3	408	#define ACMP_STATUS_ACMPO0_Pos (3) /!< ACMP STATUS: ACMPO0 Position /
sahilmgandhi	18:6a4db94011d3	409	#define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /!< ACMP STATUS: ACMPO0 Mask /
sahilmgandhi	18:6a4db94011d3	410
sahilmgandhi	18:6a4db94011d3	411	#define ACMP_STATUS_ACMPO1_Pos (4) /!< ACMP STATUS: ACMPO1 Position /
sahilmgandhi	18:6a4db94011d3	412	#define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /!< ACMP STATUS: ACMPO1 Mask /
sahilmgandhi	18:6a4db94011d3	413
sahilmgandhi	18:6a4db94011d3	414	#define ACMP_STATUS_ACMPO2_Pos (5) /!< ACMP STATUS: ACMPO2 Position /
sahilmgandhi	18:6a4db94011d3	415	#define ACMP_STATUS_ACMPO2_Msk (0x1ul << ACMP_STATUS_ACMPO2_Pos) /!< ACMP STATUS: ACMPO2 Mask /
sahilmgandhi	18:6a4db94011d3	416
sahilmgandhi	18:6a4db94011d3	417	#define ACMP_VREF_CRVCTL_Pos (0) /!< ACMP VREF: CRVCTL Position /
sahilmgandhi	18:6a4db94011d3	418	#define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) /!< ACMP VREF: CRVCTL Mask /
sahilmgandhi	18:6a4db94011d3	419
sahilmgandhi	18:6a4db94011d3	420	#define ACMP_VREF_CRVSSEL_Pos (6) /!< ACMP VREF: CRVSSEL Position /
sahilmgandhi	18:6a4db94011d3	421	#define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) /!< ACMP VREF: CRVSSEL Mask /
sahilmgandhi	18:6a4db94011d3	422
sahilmgandhi	18:6a4db94011d3	423	#define ACMP_VREF_IREFSEL_Pos (7) /!< ACMP VREF: IREFSEL Position /
sahilmgandhi	18:6a4db94011d3	424	#define ACMP_VREF_IREFSEL_Msk (0x1ul << ACMP_VREF_IREFSEL_Pos) /!< ACMP VREF: IREFSEL Mask /
sahilmgandhi	18:6a4db94011d3	425
sahilmgandhi	18:6a4db94011d3	426	/*@}/ /* ACMP_CONST */
sahilmgandhi	18:6a4db94011d3	427	/*@}/ /* end of ACMP register group */
sahilmgandhi	18:6a4db94011d3	428
sahilmgandhi	18:6a4db94011d3	429
sahilmgandhi	18:6a4db94011d3	430	/---------------------- Analog to Digital Converter -------------------------/
sahilmgandhi	18:6a4db94011d3	431	/**
sahilmgandhi	18:6a4db94011d3	432	@addtogroup ADC Analog to Digital Converter(ADC)
sahilmgandhi	18:6a4db94011d3	433	Memory Mapped Structure for ADC Controller
sahilmgandhi	18:6a4db94011d3	434	@{ */
sahilmgandhi	18:6a4db94011d3	435
sahilmgandhi	18:6a4db94011d3	436	typedef struct {
sahilmgandhi	18:6a4db94011d3	437
sahilmgandhi	18:6a4db94011d3	438
sahilmgandhi	18:6a4db94011d3	439	/**
sahilmgandhi	18:6a4db94011d3	440	* DAT
sahilmgandhi	18:6a4db94011d3	441	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	442	* Offset: 0x00~0x34 ADC Data Register 0~13
sahilmgandhi	18:6a4db94011d3	443	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	444	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	445	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	446	* \|[0:15] \|RESULT \|A/D Conversion Result
sahilmgandhi	18:6a4db94011d3	447	* \| \| \|This field contains conversion result of ADC.
sahilmgandhi	18:6a4db94011d3	448	* \| \| \|When DMOF (ADC_CTL[31]) bit is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].
sahilmgandhi	18:6a4db94011d3	449	* \| \| \|When DMOF (ADC_CTL[31]) bit set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12].
sahilmgandhi	18:6a4db94011d3	450	* \|[16] \|OV \|Overrun Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	451	* \| \| \|0 = Data in RESULT (ADC_DATx[15:0]) is recent conversion result.
sahilmgandhi	18:6a4db94011d3	452	* \| \| \|1 = Data in RESULT (ADC_DATx[15:0]) is overwrite.
sahilmgandhi	18:6a4db94011d3	453	* \| \| \|If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1 and previous conversion result is gone.
sahilmgandhi	18:6a4db94011d3	454	* \| \| \|It is cleared by hardware after ADC_DAT register is read.
sahilmgandhi	18:6a4db94011d3	455	* \|[17] \|VALID \|Valid Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	456	* \| \| \|0 = Data in RESULT (ADC_DATx[15:0]) bits is not valid.
sahilmgandhi	18:6a4db94011d3	457	* \| \| \|1 = Data in RESULT (ADC_DATx[15:0]) bits is valid.
sahilmgandhi	18:6a4db94011d3	458	* \| \| \|This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read.
sahilmgandhi	18:6a4db94011d3	459	*/
sahilmgandhi	18:6a4db94011d3	460	__I uint32_t DAT[14];
sahilmgandhi	18:6a4db94011d3	461
sahilmgandhi	18:6a4db94011d3	462
sahilmgandhi	18:6a4db94011d3	463	uint32_t RESERVE0[2];
sahilmgandhi	18:6a4db94011d3	464
sahilmgandhi	18:6a4db94011d3	465
sahilmgandhi	18:6a4db94011d3	466	/**
sahilmgandhi	18:6a4db94011d3	467	* CTL
sahilmgandhi	18:6a4db94011d3	468	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	469	* Offset: 0x40 ADC Control Register
sahilmgandhi	18:6a4db94011d3	470	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	471	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	472	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	473	* \|[0] \|ADCEN \|ADC Enable Control
sahilmgandhi	18:6a4db94011d3	474	* \| \| \|0 = ADC analog circuit Disabled.
sahilmgandhi	18:6a4db94011d3	475	* \| \| \|1 = ADC analog circuit Enabled.
sahilmgandhi	18:6a4db94011d3	476	* \| \| \|Before disabling ADC clock, this bit should be cleared to 0 by software.
sahilmgandhi	18:6a4db94011d3	477	* \|[1] \|ADCIEN \|ADC Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	478	* \| \| \|0 = ADC interrupt function Disabled.
sahilmgandhi	18:6a4db94011d3	479	* \| \| \|1 = ADC interrupt function Enabled.
sahilmgandhi	18:6a4db94011d3	480	* \| \| \|A/D conversion end interrupt request is generated if ADCIEN (ADC_CTL[1]) bit is set to 1.
sahilmgandhi	18:6a4db94011d3	481	* \|[2:3] \|OPMODE \|ADC Operation Mode
sahilmgandhi	18:6a4db94011d3	482	* \| \| \|00 = Single conversion.
sahilmgandhi	18:6a4db94011d3	483	* \| \| \|01 = Reserved.
sahilmgandhi	18:6a4db94011d3	484	* \| \| \|10 = Single-cycle scan.
sahilmgandhi	18:6a4db94011d3	485	* \| \| \|11 = Continuous scan.
sahilmgandhi	18:6a4db94011d3	486	* \| \| \|When changing the operation mode, software should disable SWTRG (ADC_CTL[11]) bit firstly.
sahilmgandhi	18:6a4db94011d3	487	* \|[4:5] \|HWTRGSEL \|External Hardware Trigger Source
sahilmgandhi	18:6a4db94011d3	488	* \| \| \|00 = A/D conversion is started by external pin (STADC).
sahilmgandhi	18:6a4db94011d3	489	* \| \| \|01 = Reserved.
sahilmgandhi	18:6a4db94011d3	490	* \| \| \|10 = Reserved.
sahilmgandhi	18:6a4db94011d3	491	* \| \| \|11 = PWM0 or PWM1 trigger condition is matched.
sahilmgandhi	18:6a4db94011d3	492	* \| \| \|Software should disable HWTRGCOND (ADC_CTL[8]) and SWTRG (ADC_CTL[11]) before changing HWTRGSEL (ADC_CTL[5:4]).
sahilmgandhi	18:6a4db94011d3	493	* \| \| \|In hardware trigger mode, the SWTRG (ADC_CTL[11]) bit is set by hardware trigger source.
sahilmgandhi	18:6a4db94011d3	494	* \|[6:7] \|HWTRGCOND \|External Pin Trigger Conditions
sahilmgandhi	18:6a4db94011d3	495	* \| \| \|These two bits decide external pin (STADC) trigger event.
sahilmgandhi	18:6a4db94011d3	496	* \| \| \|The signal must be kept at stable state at least 8 system clocks for level trigger and 4 system clocks at high and low state for edge trigger.
sahilmgandhi	18:6a4db94011d3	497	* \| \| \|00 = Low level.
sahilmgandhi	18:6a4db94011d3	498	* \| \| \|01 = High level.
sahilmgandhi	18:6a4db94011d3	499	* \| \| \|10 = Falling edge.
sahilmgandhi	18:6a4db94011d3	500	* \| \| \|11 = Rising edge.
sahilmgandhi	18:6a4db94011d3	501	* \|[8] \|HWTRGEN \|External Hardware Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	502	* \| \| \|Enable or disable hardware triggering of A/D conversion.
sahilmgandhi	18:6a4db94011d3	503	* \| \| \|The hardware trigger source include external pin (STADC) or PWM trigger which is controlled by HWTRGSEL (ADC_CTL[5:4]) register.
sahilmgandhi	18:6a4db94011d3	504	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	505	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	506	* \| \| \|ADC hardware trigger function is only supported in single-cycle scan mode.
sahilmgandhi	18:6a4db94011d3	507	* \|[9] \|PDMAEN \|PDMA Transfer Enable Control
sahilmgandhi	18:6a4db94011d3	508	* \| \| \|0 = PDMA data transfer Disabled.
sahilmgandhi	18:6a4db94011d3	509	* \| \| \|1 = PDMA data transfer in ADC_DATx Enabled.
sahilmgandhi	18:6a4db94011d3	510	* \| \| \|When A/D conversion is completed, the converted data is loaded into ADC_DATx, software can enable this bit to generate a PDMA data transfer request.
sahilmgandhi	18:6a4db94011d3	511	* \| \| \|When PDMAEN (ADC_CTL[9]) is set to 1, software must set ADCIEN (ADC_CTL[1]) bit to 0 to disable interrupt.
sahilmgandhi	18:6a4db94011d3	512	* \|[10] \|DIFFEN \|Differential Input Mode Enable Control
sahilmgandhi	18:6a4db94011d3	513	* \| \| \|0 = Single-end analog input mode.
sahilmgandhi	18:6a4db94011d3	514	* \| \| \|1 = Differential analog input mode.
sahilmgandhi	18:6a4db94011d3	515	* \| \| \|The A/D analog input ADC0_CH0/ADC0_CH1 consists of a differential pair.
sahilmgandhi	18:6a4db94011d3	516	* \| \| \|So as ADC0_CH2/ADC0_CH3, ADC0_CH4/ADC0_CH5, ADC0_CH6/ADC0_CH7, ADC0_CH8/ADC0_CH9 and ADC0_CH10/ADC0_CH11.
sahilmgandhi	18:6a4db94011d3	517	* \| \| \|The even channel defines as plus analog input voltage (Vplus) and the odd channel defines as minus analog input voltage (Vminus).
sahilmgandhi	18:6a4db94011d3	518	* \| \| \|Differential input voltage (Vdiff) = Vplus - Vminus, where Vplus
sahilmgandhi	18:6a4db94011d3	519	* \| \| \|is the analog input; Vminus is the inverted analog input.
sahilmgandhi	18:6a4db94011d3	520	* \| \| \|In differential input mode, only the even number of the two corresponding channels needs to be enabled in ADCHER (ADC_CHEN[11:0]).
sahilmgandhi	18:6a4db94011d3	521	* \| \| \|The conversion result will be placed to the corresponding data register of the enabled channel.
sahilmgandhi	18:6a4db94011d3	522	* \|[11] \|SWTRG \|A/D Conversion Start
sahilmgandhi	18:6a4db94011d3	523	* \| \| \|0 = Conversion stopped and A/D converter enter idle state.
sahilmgandhi	18:6a4db94011d3	524	* \| \| \|1 = Conversion start.
sahilmgandhi	18:6a4db94011d3	525	* \| \| \|The SWTRG (ADC_CTL[11]) bit can be set to 1 from two sources: software and hardware trigger.
sahilmgandhi	18:6a4db94011d3	526	* \| \| \|The SWTRG (ADC_CTL[11]) bit will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode.
sahilmgandhi	18:6a4db94011d3	527	* \| \| \|In continuous scan mode, A/D conversion is continuously performed until software write 0 to this bit or chip reset.
sahilmgandhi	18:6a4db94011d3	528	* \|[16:23] \|PWMTRGDLY \|PWM Trigger Delay Time
sahilmgandhi	18:6a4db94011d3	529	* \| \| \|Setting this field will delay ADC start conversion time after PWM trigger comes.
sahilmgandhi	18:6a4db94011d3	530	* \| \| \|PWM trigger delay time is 4 * system clock * PWMTRGDLY (ADC_CTL[23:16])
sahilmgandhi	18:6a4db94011d3	531	* \|[31] \|DMOF \|ADC Differential Input Mode Output Format
sahilmgandhi	18:6a4db94011d3	532	* \| \| \|0 = A/D conversion result will be filled in RESULT (ADC_DATx[15:0]) registers with unsigned format.
sahilmgandhi	18:6a4db94011d3	533	* \| \| \|1 = A/D conversion result will be filled in RESULT (ADC_DATx[15:0]) registers with 2'complement format.
sahilmgandhi	18:6a4db94011d3	534	*/
sahilmgandhi	18:6a4db94011d3	535	__IO uint32_t CTL;
sahilmgandhi	18:6a4db94011d3	536
sahilmgandhi	18:6a4db94011d3	537	/**
sahilmgandhi	18:6a4db94011d3	538	* CHEN
sahilmgandhi	18:6a4db94011d3	539	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	540	* Offset: 0x44 ADC Channel Enable Control Register
sahilmgandhi	18:6a4db94011d3	541	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	542	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	543	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	544	* \|[0:11] \|CHEN \|Analog Input Channel Enable Control
sahilmgandhi	18:6a4db94011d3	545	* \| \| \|Set CHEN (ADC_CHEN[11:0]) to enable the corresponding analog input channel (ADC0_CH1 ~ ADC0_CH11).
sahilmgandhi	18:6a4db94011d3	546	* \| \| \|If DIFFEN bit is set to 1, only the even number channels need to be enabled.
sahilmgandhi	18:6a4db94011d3	547	* \| \| \|0 = ADC input channel Disabled.
sahilmgandhi	18:6a4db94011d3	548	* \| \| \|1 = ADC input channel Enabled.
sahilmgandhi	18:6a4db94011d3	549	* \|[16] \|ADTSEN \|Internal Temperature Sensor Selection
sahilmgandhi	18:6a4db94011d3	550	* \| \| \|0 = Internal temperature sensor is not selected to be the analog input source of ADC.
sahilmgandhi	18:6a4db94011d3	551	* \| \| \|1 = Internal temperature sensor is selected to be the analog input source of ADC.
sahilmgandhi	18:6a4db94011d3	552	* \| \| \|ADC can only work at Single mode when software selects the temperature sensor voltage as the analog input source of ADC
sahilmgandhi	18:6a4db94011d3	553	* \|[17] \|ADBGEN \|Internal Band-Gap Selection
sahilmgandhi	18:6a4db94011d3	554	* \| \| \|0 = Internal band-gap is not selected to be the analog input source of ADC.
sahilmgandhi	18:6a4db94011d3	555	* \| \| \|1 = Internal band-gap is selected to be the analog input source of ADC.
sahilmgandhi	18:6a4db94011d3	556	* \| \| \|ADC can only work at Single mode when software selects the band-gap voltage as the analog input source of ADC
sahilmgandhi	18:6a4db94011d3	557	*/
sahilmgandhi	18:6a4db94011d3	558	__IO uint32_t CHEN;
sahilmgandhi	18:6a4db94011d3	559
sahilmgandhi	18:6a4db94011d3	560	/**
sahilmgandhi	18:6a4db94011d3	561	* CMP
sahilmgandhi	18:6a4db94011d3	562	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	563	* Offset: 0x48 ADC Compare Register 0/1
sahilmgandhi	18:6a4db94011d3	564	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	565	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	566	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	567	* \|[0] \|ADCMPEN \|Compare Enable Control
sahilmgandhi	18:6a4db94011d3	568	* \| \| \|0 = Compare function Disabled.
sahilmgandhi	18:6a4db94011d3	569	* \| \| \|1 = Compare function Enabled.
sahilmgandhi	18:6a4db94011d3	570	* \| \| \|Set this bit to 1 to enable ADC controller to compare CMPDAT (ADC_CMPx[27:16]) with the conversion result of the channel specified by CMPCH (ADC_CMPx[6:3]) when the conversion data of the specified channel is loaded into ADC_DATx register.
sahilmgandhi	18:6a4db94011d3	571	* \|[1] \|ADCMPIE \|Compare Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	572	* \| \| \|0 = Compare function interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	573	* \| \| \|1 = Compare function interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	574	* \| \| \|If the compare function is enabled and the compare condition matches the setting of CMPCOND (ADC_CMPx[2]) and CMPMCNT(ADC_CMPx[11:8]), ADCMPFx (ADC_STATUS0[2:1]) bit will be asserted, in the meanwhile, if ADCMPIE (ADC_CMPx[1])is set to 1, a compare interrupt request is generated.
sahilmgandhi	18:6a4db94011d3	575	* \|[2] \|CMPCOND \|Compare Condition
sahilmgandhi	18:6a4db94011d3	576	* \| \| \|0 = Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPDAT (ADC_CMPx[27:16]), the internal match counter will increase one.
sahilmgandhi	18:6a4db94011d3	577	* \| \| \|1 = Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPDAT (ADC_CMPx[27:16]), the internal match counter will increase one.
sahilmgandhi	18:6a4db94011d3	578	* \| \| \|Note: When the internal counter reaches the value to CMPMCNT (ADC_CMPx[11:8]) + 1, the ADCMPFx (ADC_STATUS0[2:1]) bit will be set.
sahilmgandhi	18:6a4db94011d3	579	* \|[3:6] \|CMPCH \|Compare Channel Selection
sahilmgandhi	18:6a4db94011d3	580	* \| \| \|0000 = Channel 0 conversion result is selected to be compared.
sahilmgandhi	18:6a4db94011d3	581	* \| \| \|0001 = Channel 1 conversion result is selected to be compared.
sahilmgandhi	18:6a4db94011d3	582	* \| \| \|0010 = Channel 2 conversion result is selected to be compared.
sahilmgandhi	18:6a4db94011d3	583	* \| \| \|0011 = Channel 3 conversion result is selected to be compared.
sahilmgandhi	18:6a4db94011d3	584	* \| \| \|0100 = Channel 4 conversion result is selected to be compared.
sahilmgandhi	18:6a4db94011d3	585	* \| \| \|0101 = Channel 5 conversion result is selected to be compared.
sahilmgandhi	18:6a4db94011d3	586	* \| \| \|0110 = Channel 6 conversion result is selected to be compared.
sahilmgandhi	18:6a4db94011d3	587	* \| \| \|0111 = Channel 7 conversion result is selected to be compared.
sahilmgandhi	18:6a4db94011d3	588	* \| \| \|1000 = Channel 8 conversion result is selected to be compared.
sahilmgandhi	18:6a4db94011d3	589	* \| \| \|1001 = Channel 9 conversion result is selected to be compared.
sahilmgandhi	18:6a4db94011d3	590	* \| \| \|1010 = Channel 10 conversion result is selected to be compared.
sahilmgandhi	18:6a4db94011d3	591	* \| \| \|1011 = Channel 11 conversion result is selected to be compared.
sahilmgandhi	18:6a4db94011d3	592	* \| \| \|1100 = band-gap voltage result is selected to be compared.
sahilmgandhi	18:6a4db94011d3	593	* \| \| \|1101 = temperature sensor conversion result is selected to be compared.
sahilmgandhi	18:6a4db94011d3	594	* \| \| \|Others = reserved.
sahilmgandhi	18:6a4db94011d3	595	* \|[8:11] \|CMPMCNT \|Compare Match Count
sahilmgandhi	18:6a4db94011d3	596	* \| \| \|When the specified ADC channel analog conversion result matches the compare condition defined by CMPCOND (ADC_CMPx[2]), the internal match counter will increase 1.
sahilmgandhi	18:6a4db94011d3	597	* \| \| \|When the internal counter reaches the value to CMPMCNT (ADC_CMPx[11:8]) + 1, the ADCMPFx (ADC_STATUS0[2:1]) bit will be set.
sahilmgandhi	18:6a4db94011d3	598	* \|[16:27] \|CMPDAT \|Compared Data
sahilmgandhi	18:6a4db94011d3	599	* \| \| \|When DMOF (ADC_CTL[31]) bit is set to 0, ADC comparator compares CMPDAT (ADC_CTL[27:16]) with conversion result with unsigned format.
sahilmgandhi	18:6a4db94011d3	600	* \| \| \|CMPDAT (ADC_CTL[27:16]) should be filled in unsigned format.
sahilmgandhi	18:6a4db94011d3	601	* \| \| \|When DMOF (ADC_CTL[31]) bit is set to 1, ADC comparator compares CMPDAT (ADC_CTL[27:16]) with conversion result with 2'complement format.
sahilmgandhi	18:6a4db94011d3	602	* \| \| \|CMPDAT (ADC_CTL[27:16]) should be filled in 2'complement format.
sahilmgandhi	18:6a4db94011d3	603	*/
sahilmgandhi	18:6a4db94011d3	604	__IO uint32_t CMP[2];
sahilmgandhi	18:6a4db94011d3	605
sahilmgandhi	18:6a4db94011d3	606	/**
sahilmgandhi	18:6a4db94011d3	607	* STATUS0
sahilmgandhi	18:6a4db94011d3	608	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	609	* Offset: 0x50 ADC Status Register 0
sahilmgandhi	18:6a4db94011d3	610	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	611	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	612	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	613	* \|[0] \|ADIF \|ADC Interrupt Flag
sahilmgandhi	18:6a4db94011d3	614	* \| \| \|A status flag that indicates the end of A/D conversion.
sahilmgandhi	18:6a4db94011d3	615	* \| \| \|ADIF (ADC_STATUS0[0]) is set to 1 at these two conditions:
sahilmgandhi	18:6a4db94011d3	616	* \| \| \|1. When A/D conversion ends in Single mode
sahilmgandhi	18:6a4db94011d3	617	* \| \| \|2. When A/D conversion ends on all specified channels in Scan mode
sahilmgandhi	18:6a4db94011d3	618	* \| \| \|Note: This flag can be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	619	* \|[1] \|ADCMPF0 \|Compare Flag
sahilmgandhi	18:6a4db94011d3	620	* \| \| \|When the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1.
sahilmgandhi	18:6a4db94011d3	621	* \| \| \|And it is cleared by writing 1 to self.
sahilmgandhi	18:6a4db94011d3	622	* \| \| \|0 = Conversion result in ADC_DATx does not meet ADCMPR0 setting.
sahilmgandhi	18:6a4db94011d3	623	* \| \| \|1 = Conversion result in ADC_DATx meets ADCMPR0 setting.
sahilmgandhi	18:6a4db94011d3	624	* \|[2] \|ADCMPF1 \|Compare Flag
sahilmgandhi	18:6a4db94011d3	625	* \| \| \|When the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1.
sahilmgandhi	18:6a4db94011d3	626	* \| \| \|And it is cleared by writing 1 to self.
sahilmgandhi	18:6a4db94011d3	627	* \| \| \|0 = Conversion result in ADC_DATx does not meet ADCMPR1 setting.
sahilmgandhi	18:6a4db94011d3	628	* \| \| \|1 = Conversion result in ADC_DATx meets ADCMPR1 setting.
sahilmgandhi	18:6a4db94011d3	629	* \|[3] \|BUSY \|BUSY/IDLE (Read Only)
sahilmgandhi	18:6a4db94011d3	630	* \| \| \|0 = ADC is in idle state.
sahilmgandhi	18:6a4db94011d3	631	* \| \| \|1 = ADC is doing conversion.
sahilmgandhi	18:6a4db94011d3	632	* \| \| \|This bit is mirror of as SWTRG (ADC_CTL[11]) bit.
sahilmgandhi	18:6a4db94011d3	633	* \|[4:7] \|CHANNEL \|Current Conversion Channel (Read Only)
sahilmgandhi	18:6a4db94011d3	634	* \| \| \|This field reflects the current conversion channel when BUSY (ADC_STATUS0[3]) = 1.
sahilmgandhi	18:6a4db94011d3	635	* \| \| \|When BUSY (ADC_STATUS0[3]) = 0, it shows the number of the next converted channel.
sahilmgandhi	18:6a4db94011d3	636	*/
sahilmgandhi	18:6a4db94011d3	637	__IO uint32_t STATUS0;
sahilmgandhi	18:6a4db94011d3	638
sahilmgandhi	18:6a4db94011d3	639	/**
sahilmgandhi	18:6a4db94011d3	640	* STATUS1
sahilmgandhi	18:6a4db94011d3	641	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	642	* Offset: 0x54 ADC Status Register 1
sahilmgandhi	18:6a4db94011d3	643	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	644	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	645	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	646	* \|[0:13] \|VALID \|Data Valid Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	647	* \| \| \|It is a mirror of VALID (ADC_DATx[17]) bit.
sahilmgandhi	18:6a4db94011d3	648	* \|[16:29] \|OV \|Overrun Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	649	* \| \| \|It is a mirror to OV (ADC_DATx[16]) bit.
sahilmgandhi	18:6a4db94011d3	650	*/
sahilmgandhi	18:6a4db94011d3	651	__I uint32_t STATUS1;
sahilmgandhi	18:6a4db94011d3	652	uint32_t RESERVE1[2];
sahilmgandhi	18:6a4db94011d3	653
sahilmgandhi	18:6a4db94011d3	654
sahilmgandhi	18:6a4db94011d3	655	/**
sahilmgandhi	18:6a4db94011d3	656	* CURDAT
sahilmgandhi	18:6a4db94011d3	657	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	658	* Offset: 0x60 ADC PDMA Current Transfer Data Register
sahilmgandhi	18:6a4db94011d3	659	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	660	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	661	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	662	* \|[0:17] \|CURDAT \|ADC PDMA Current Transfer Data Bit (Read Only)
sahilmgandhi	18:6a4db94011d3	663	* \| \| \|When PDMA transferring, read this register can monitor current PDMA transfer data.
sahilmgandhi	18:6a4db94011d3	664	*/
sahilmgandhi	18:6a4db94011d3	665	__I uint32_t CURDAT;
sahilmgandhi	18:6a4db94011d3	666
sahilmgandhi	18:6a4db94011d3	667	} ADC_T;
sahilmgandhi	18:6a4db94011d3	668
sahilmgandhi	18:6a4db94011d3	669	/**
sahilmgandhi	18:6a4db94011d3	670	@addtogroup ADC_CONST ADC Bit Field Definition
sahilmgandhi	18:6a4db94011d3	671	Constant Definitions for ADC Controller
sahilmgandhi	18:6a4db94011d3	672	@{ */
sahilmgandhi	18:6a4db94011d3	673
sahilmgandhi	18:6a4db94011d3	674	#define ADC_DAT0_RESULT_Pos (0) /!< ADC DAT0: RESULT Position /
sahilmgandhi	18:6a4db94011d3	675	#define ADC_DAT0_RESULT_Msk (0xfffful << ADC_DAT0_RESULT_Pos) /!< ADC DAT0: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	676
sahilmgandhi	18:6a4db94011d3	677	#define ADC_DAT0_OV_Pos (16) /!< ADC DAT0: OV Position /
sahilmgandhi	18:6a4db94011d3	678	#define ADC_DAT0_OV_Msk (0x1ul << ADC_DAT0_OV_Pos) /!< ADC DAT0: OV Mask /
sahilmgandhi	18:6a4db94011d3	679
sahilmgandhi	18:6a4db94011d3	680	#define ADC_DAT0_VALID_Pos (17) /!< ADC DAT0: VALID Position /
sahilmgandhi	18:6a4db94011d3	681	#define ADC_DAT0_VALID_Msk (0x1ul << ADC_DAT0_VALID_Pos) /!< ADC DAT0: VALID Mask /
sahilmgandhi	18:6a4db94011d3	682
sahilmgandhi	18:6a4db94011d3	683	#define ADC_DAT1_RESULT_Pos (0) /!< ADC DAT1: RESULT Position /
sahilmgandhi	18:6a4db94011d3	684	#define ADC_DAT1_RESULT_Msk (0xfffful << ADC_DAT1_RESULT_Pos) /!< ADC DAT1: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	685
sahilmgandhi	18:6a4db94011d3	686	#define ADC_DAT1_OV_Pos (16) /!< ADC DAT1: OV Position /
sahilmgandhi	18:6a4db94011d3	687	#define ADC_DAT1_OV_Msk (0x1ul << ADC_DAT1_OV_Pos) /!< ADC DAT1: OV Mask /
sahilmgandhi	18:6a4db94011d3	688
sahilmgandhi	18:6a4db94011d3	689	#define ADC_DAT1_VALID_Pos (17) /!< ADC DAT1: VALID Position /
sahilmgandhi	18:6a4db94011d3	690	#define ADC_DAT1_VALID_Msk (0x1ul << ADC_DAT1_VALID_Pos) /!< ADC DAT1: VALID Mask /
sahilmgandhi	18:6a4db94011d3	691
sahilmgandhi	18:6a4db94011d3	692	#define ADC_DAT2_RESULT_Pos (0) /!< ADC DAT2: RESULT Position /
sahilmgandhi	18:6a4db94011d3	693	#define ADC_DAT2_RESULT_Msk (0xfffful << ADC_DAT2_RESULT_Pos) /!< ADC DAT2: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	694
sahilmgandhi	18:6a4db94011d3	695	#define ADC_DAT2_OV_Pos (16) /!< ADC DAT2: OV Position /
sahilmgandhi	18:6a4db94011d3	696	#define ADC_DAT2_OV_Msk (0x1ul << ADC_DAT2_OV_Pos) /!< ADC DAT2: OV Mask /
sahilmgandhi	18:6a4db94011d3	697
sahilmgandhi	18:6a4db94011d3	698	#define ADC_DAT2_VALID_Pos (17) /!< ADC DAT2: VALID Position /
sahilmgandhi	18:6a4db94011d3	699	#define ADC_DAT2_VALID_Msk (0x1ul << ADC_DAT2_VALID_Pos) /!< ADC DAT2: VALID Mask /
sahilmgandhi	18:6a4db94011d3	700
sahilmgandhi	18:6a4db94011d3	701	#define ADC_DAT3_RESULT_Pos (0) /!< ADC DAT3: RESULT Position /
sahilmgandhi	18:6a4db94011d3	702	#define ADC_DAT3_RESULT_Msk (0xfffful << ADC_DAT3_RESULT_Pos) /!< ADC DAT3: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	703
sahilmgandhi	18:6a4db94011d3	704	#define ADC_DAT3_OV_Pos (16) /!< ADC DAT3: OV Position /
sahilmgandhi	18:6a4db94011d3	705	#define ADC_DAT3_OV_Msk (0x1ul << ADC_DAT3_OV_Pos) /!< ADC DAT3: OV Mask /
sahilmgandhi	18:6a4db94011d3	706
sahilmgandhi	18:6a4db94011d3	707	#define ADC_DAT3_VALID_Pos (17) /!< ADC DAT3: VALID Position /
sahilmgandhi	18:6a4db94011d3	708	#define ADC_DAT3_VALID_Msk (0x1ul << ADC_DAT3_VALID_Pos) /!< ADC DAT3: VALID Mask /
sahilmgandhi	18:6a4db94011d3	709
sahilmgandhi	18:6a4db94011d3	710	#define ADC_DAT4_RESULT_Pos (0) /!< ADC DAT4: RESULT Position /
sahilmgandhi	18:6a4db94011d3	711	#define ADC_DAT4_RESULT_Msk (0xfffful << ADC_DAT4_RESULT_Pos) /!< ADC DAT4: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	712
sahilmgandhi	18:6a4db94011d3	713	#define ADC_DAT4_OV_Pos (16) /!< ADC DAT4: OV Position /
sahilmgandhi	18:6a4db94011d3	714	#define ADC_DAT4_OV_Msk (0x1ul << ADC_DAT4_OV_Pos) /!< ADC DAT4: OV Mask /
sahilmgandhi	18:6a4db94011d3	715
sahilmgandhi	18:6a4db94011d3	716	#define ADC_DAT4_VALID_Pos (17) /!< ADC DAT4: VALID Position /
sahilmgandhi	18:6a4db94011d3	717	#define ADC_DAT4_VALID_Msk (0x1ul << ADC_DAT4_VALID_Pos) /!< ADC DAT4: VALID Mask /
sahilmgandhi	18:6a4db94011d3	718
sahilmgandhi	18:6a4db94011d3	719	#define ADC_DAT5_RESULT_Pos (0) /!< ADC DAT5: RESULT Position /
sahilmgandhi	18:6a4db94011d3	720	#define ADC_DAT5_RESULT_Msk (0xfffful << ADC_DAT5_RESULT_Pos) /!< ADC DAT5: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	721
sahilmgandhi	18:6a4db94011d3	722	#define ADC_DAT5_OV_Pos (16) /!< ADC DAT5: OV Position /
sahilmgandhi	18:6a4db94011d3	723	#define ADC_DAT5_OV_Msk (0x1ul << ADC_DAT5_OV_Pos) /!< ADC DAT5: OV Mask /
sahilmgandhi	18:6a4db94011d3	724
sahilmgandhi	18:6a4db94011d3	725	#define ADC_DAT5_VALID_Pos (17) /!< ADC DAT5: VALID Position /
sahilmgandhi	18:6a4db94011d3	726	#define ADC_DAT5_VALID_Msk (0x1ul << ADC_DAT5_VALID_Pos) /!< ADC DAT5: VALID Mask /
sahilmgandhi	18:6a4db94011d3	727
sahilmgandhi	18:6a4db94011d3	728	#define ADC_DAT6_RESULT_Pos (0) /!< ADC DAT6: RESULT Position /
sahilmgandhi	18:6a4db94011d3	729	#define ADC_DAT6_RESULT_Msk (0xfffful << ADC_DAT6_RESULT_Pos) /!< ADC DAT6: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	730
sahilmgandhi	18:6a4db94011d3	731	#define ADC_DAT6_OV_Pos (16) /!< ADC DAT6: OV Position /
sahilmgandhi	18:6a4db94011d3	732	#define ADC_DAT6_OV_Msk (0x1ul << ADC_DAT6_OV_Pos) /!< ADC DAT6: OV Mask /
sahilmgandhi	18:6a4db94011d3	733
sahilmgandhi	18:6a4db94011d3	734	#define ADC_DAT6_VALID_Pos (17) /!< ADC DAT6: VALID Position /
sahilmgandhi	18:6a4db94011d3	735	#define ADC_DAT6_VALID_Msk (0x1ul << ADC_DAT6_VALID_Pos) /!< ADC DAT6: VALID Mask /
sahilmgandhi	18:6a4db94011d3	736
sahilmgandhi	18:6a4db94011d3	737	#define ADC_DAT7_RESULT_Pos (0) /!< ADC DAT7: RESULT Position /
sahilmgandhi	18:6a4db94011d3	738	#define ADC_DAT7_RESULT_Msk (0xfffful << ADC_DAT7_RESULT_Pos) /!< ADC DAT7: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	739
sahilmgandhi	18:6a4db94011d3	740	#define ADC_DAT7_OV_Pos (16) /!< ADC DAT7: OV Position /
sahilmgandhi	18:6a4db94011d3	741	#define ADC_DAT7_OV_Msk (0x1ul << ADC_DAT7_OV_Pos) /!< ADC DAT7: OV Mask /
sahilmgandhi	18:6a4db94011d3	742
sahilmgandhi	18:6a4db94011d3	743	#define ADC_DAT7_VALID_Pos (17) /!< ADC DAT7: VALID Position /
sahilmgandhi	18:6a4db94011d3	744	#define ADC_DAT7_VALID_Msk (0x1ul << ADC_DAT7_VALID_Pos) /!< ADC DAT7: VALID Mask /
sahilmgandhi	18:6a4db94011d3	745
sahilmgandhi	18:6a4db94011d3	746	#define ADC_DAT8_RESULT_Pos (0) /!< ADC DAT8: RESULT Position /
sahilmgandhi	18:6a4db94011d3	747	#define ADC_DAT8_RESULT_Msk (0xfffful << ADC_DAT8_RESULT_Pos) /!< ADC DAT8: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	748
sahilmgandhi	18:6a4db94011d3	749	#define ADC_DAT8_OV_Pos (16) /!< ADC DAT8: OV Position /
sahilmgandhi	18:6a4db94011d3	750	#define ADC_DAT8_OV_Msk (0x1ul << ADC_DAT8_OV_Pos) /!< ADC DAT8: OV Mask /
sahilmgandhi	18:6a4db94011d3	751
sahilmgandhi	18:6a4db94011d3	752	#define ADC_DAT8_VALID_Pos (17) /!< ADC DAT8: VALID Position /
sahilmgandhi	18:6a4db94011d3	753	#define ADC_DAT8_VALID_Msk (0x1ul << ADC_DAT8_VALID_Pos) /!< ADC DAT8: VALID Mask /
sahilmgandhi	18:6a4db94011d3	754
sahilmgandhi	18:6a4db94011d3	755	#define ADC_DAT9_RESULT_Pos (0) /!< ADC DAT9: RESULT Position /
sahilmgandhi	18:6a4db94011d3	756	#define ADC_DAT9_RESULT_Msk (0xfffful << ADC_DAT9_RESULT_Pos) /!< ADC DAT9: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	757
sahilmgandhi	18:6a4db94011d3	758	#define ADC_DAT9_OV_Pos (16) /!< ADC DAT9: OV Position /
sahilmgandhi	18:6a4db94011d3	759	#define ADC_DAT9_OV_Msk (0x1ul << ADC_DAT9_OV_Pos) /!< ADC DAT9: OV Mask /
sahilmgandhi	18:6a4db94011d3	760
sahilmgandhi	18:6a4db94011d3	761	#define ADC_DAT9_VALID_Pos (17) /!< ADC DAT9: VALID Position /
sahilmgandhi	18:6a4db94011d3	762	#define ADC_DAT9_VALID_Msk (0x1ul << ADC_DAT9_VALID_Pos) /!< ADC DAT9: VALID Mask /
sahilmgandhi	18:6a4db94011d3	763
sahilmgandhi	18:6a4db94011d3	764	#define ADC_DAT10_RESULT_Pos (0) /!< ADC DAT10: RESULT Position /
sahilmgandhi	18:6a4db94011d3	765	#define ADC_DAT10_RESULT_Msk (0xfffful << ADC_DAT10_RESULT_Pos) /!< ADC DAT10: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	766
sahilmgandhi	18:6a4db94011d3	767	#define ADC_DAT10_OV_Pos (16) /!< ADC DAT10: OV Position /
sahilmgandhi	18:6a4db94011d3	768	#define ADC_DAT10_OV_Msk (0x1ul << ADC_DAT10_OV_Pos) /!< ADC DAT10: OV Mask /
sahilmgandhi	18:6a4db94011d3	769
sahilmgandhi	18:6a4db94011d3	770	#define ADC_DAT10_VALID_Pos (17) /!< ADC DAT10: VALID Position /
sahilmgandhi	18:6a4db94011d3	771	#define ADC_DAT10_VALID_Msk (0x1ul << ADC_DAT10_VALID_Pos) /!< ADC DAT10: VALID Mask /
sahilmgandhi	18:6a4db94011d3	772
sahilmgandhi	18:6a4db94011d3	773	#define ADC_DAT11_RESULT_Pos (0) /!< ADC DAT11: RESULT Position /
sahilmgandhi	18:6a4db94011d3	774	#define ADC_DAT11_RESULT_Msk (0xfffful << ADC_DAT11_RESULT_Pos) /!< ADC DAT11: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	775
sahilmgandhi	18:6a4db94011d3	776	#define ADC_DAT11_OV_Pos (16) /!< ADC DAT11: OV Position /
sahilmgandhi	18:6a4db94011d3	777	#define ADC_DAT11_OV_Msk (0x1ul << ADC_DAT11_OV_Pos) /!< ADC DAT11: OV Mask /
sahilmgandhi	18:6a4db94011d3	778
sahilmgandhi	18:6a4db94011d3	779	#define ADC_DAT11_VALID_Pos (17) /!< ADC DAT11: VALID Position /
sahilmgandhi	18:6a4db94011d3	780	#define ADC_DAT11_VALID_Msk (0x1ul << ADC_DAT11_VALID_Pos) /!< ADC DAT11: VALID Mask /
sahilmgandhi	18:6a4db94011d3	781
sahilmgandhi	18:6a4db94011d3	782	#define ADC_DAT12_RESULT_Pos (0) /!< ADC DAT12: RESULT Position /
sahilmgandhi	18:6a4db94011d3	783	#define ADC_DAT12_RESULT_Msk (0xfffful << ADC_DAT12_RESULT_Pos) /!< ADC DAT12: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	784
sahilmgandhi	18:6a4db94011d3	785	#define ADC_DAT12_OV_Pos (16) /!< ADC DAT12: OV Position /
sahilmgandhi	18:6a4db94011d3	786	#define ADC_DAT12_OV_Msk (0x1ul << ADC_DAT12_OV_Pos) /!< ADC DAT12: OV Mask /
sahilmgandhi	18:6a4db94011d3	787
sahilmgandhi	18:6a4db94011d3	788	#define ADC_DAT12_VALID_Pos (17) /!< ADC DAT12: VALID Position /
sahilmgandhi	18:6a4db94011d3	789	#define ADC_DAT12_VALID_Msk (0x1ul << ADC_DAT12_VALID_Pos) /!< ADC DAT12: VALID Mask /
sahilmgandhi	18:6a4db94011d3	790
sahilmgandhi	18:6a4db94011d3	791	#define ADC_DAT13_RESULT_Pos (0) /!< ADC DAT13: RESULT Position /
sahilmgandhi	18:6a4db94011d3	792	#define ADC_DAT13_RESULT_Msk (0xfffful << ADC_DAT13_RESULT_Pos) /!< ADC DAT13: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	793
sahilmgandhi	18:6a4db94011d3	794	#define ADC_DAT13_OV_Pos (16) /!< ADC DAT13: OV Position /
sahilmgandhi	18:6a4db94011d3	795	#define ADC_DAT13_OV_Msk (0x1ul << ADC_DAT13_OV_Pos) /!< ADC DAT13: OV Mask /
sahilmgandhi	18:6a4db94011d3	796
sahilmgandhi	18:6a4db94011d3	797	#define ADC_DAT13_VALID_Pos (17) /!< ADC DAT13: VALID Position /
sahilmgandhi	18:6a4db94011d3	798	#define ADC_DAT13_VALID_Msk (0x1ul << ADC_DAT13_VALID_Pos) /!< ADC DAT13: VALID Mask /
sahilmgandhi	18:6a4db94011d3	799
sahilmgandhi	18:6a4db94011d3	800	#define ADC_CTL_ADCEN_Pos (0) /!< ADC CTL: ADCEN Position /
sahilmgandhi	18:6a4db94011d3	801	#define ADC_CTL_ADCEN_Msk (0x1ul << ADC_CTL_ADCEN_Pos) /!< ADC CTL: ADCEN Mask /
sahilmgandhi	18:6a4db94011d3	802
sahilmgandhi	18:6a4db94011d3	803	#define ADC_CTL_ADCIEN_Pos (1) /!< ADC CTL: ADCIEN Position /
sahilmgandhi	18:6a4db94011d3	804	#define ADC_CTL_ADCIEN_Msk (0x1ul << ADC_CTL_ADCIEN_Pos) /!< ADC CTL: ADCIEN Mask /
sahilmgandhi	18:6a4db94011d3	805
sahilmgandhi	18:6a4db94011d3	806	#define ADC_CTL_OPMODE_Pos (2) /!< ADC CTL: OPMODE Position /
sahilmgandhi	18:6a4db94011d3	807	#define ADC_CTL_OPMODE_Msk (0x3ul << ADC_CTL_OPMODE_Pos) /!< ADC CTL: OPMODE Mask /
sahilmgandhi	18:6a4db94011d3	808
sahilmgandhi	18:6a4db94011d3	809	#define ADC_CTL_HWTRGSEL_Pos (4) /!< ADC CTL: HWTRGSEL Position /
sahilmgandhi	18:6a4db94011d3	810	#define ADC_CTL_HWTRGSEL_Msk (0x3ul << ADC_CTL_HWTRGSEL_Pos) /!< ADC CTL: HWTRGSEL Mask /
sahilmgandhi	18:6a4db94011d3	811
sahilmgandhi	18:6a4db94011d3	812	#define ADC_CTL_HWTRGCOND_Pos (6) /!< ADC CTL: HWTRGCOND Position /
sahilmgandhi	18:6a4db94011d3	813	#define ADC_CTL_HWTRGCOND_Msk (0x3ul << ADC_CTL_HWTRGCOND_Pos) /!< ADC CTL: HWTRGCOND Mask /
sahilmgandhi	18:6a4db94011d3	814
sahilmgandhi	18:6a4db94011d3	815	#define ADC_CTL_HWTRGEN_Pos (8) /!< ADC CTL: HWTRGEN Position /
sahilmgandhi	18:6a4db94011d3	816	#define ADC_CTL_HWTRGEN_Msk (0x1ul << ADC_CTL_HWTRGEN_Pos) /!< ADC CTL: HWTRGEN Mask /
sahilmgandhi	18:6a4db94011d3	817
sahilmgandhi	18:6a4db94011d3	818	#define ADC_CTL_PDMAEN_Pos (9) /!< ADC CTL: PDMAEN Position /
sahilmgandhi	18:6a4db94011d3	819	#define ADC_CTL_PDMAEN_Msk (0x1ul << ADC_CTL_PDMAEN_Pos) /!< ADC CTL: PDMAEN Mask /
sahilmgandhi	18:6a4db94011d3	820
sahilmgandhi	18:6a4db94011d3	821	#define ADC_CTL_DIFFEN_Pos (10) /!< ADC CTL: DIFFEN Position /
sahilmgandhi	18:6a4db94011d3	822	#define ADC_CTL_DIFFEN_Msk (0x1ul << ADC_CTL_DIFFEN_Pos) /!< ADC CTL: DIFFEN Mask /
sahilmgandhi	18:6a4db94011d3	823
sahilmgandhi	18:6a4db94011d3	824	#define ADC_CTL_SWTRG_Pos (11) /!< ADC CTL: SWTRG Position /
sahilmgandhi	18:6a4db94011d3	825	#define ADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos) /!< ADC CTL: SWTRG Mask /
sahilmgandhi	18:6a4db94011d3	826
sahilmgandhi	18:6a4db94011d3	827	#define ADC_CTL_PWMTRGDLY_Pos (16) /!< ADC CTL: PWMTRGDLY Position /
sahilmgandhi	18:6a4db94011d3	828	#define ADC_CTL_PWMTRGDLY_Msk (0xfful << ADC_CTL_PWMTRGDLY_Pos) /!< ADC CTL: PWMTRGDLY Mask /
sahilmgandhi	18:6a4db94011d3	829
sahilmgandhi	18:6a4db94011d3	830	#define ADC_CTL_DMOF_Pos (31) /!< ADC CTL: DMOF Position /
sahilmgandhi	18:6a4db94011d3	831	#define ADC_CTL_DMOF_Msk (0x1ul << ADC_CTL_DMOF_Pos) /!< ADC CTL: DMOF Mask /
sahilmgandhi	18:6a4db94011d3	832
sahilmgandhi	18:6a4db94011d3	833	#define ADC_CHEN_CHEN_Pos (0) /!< ADC CHEN: CHEN Position /
sahilmgandhi	18:6a4db94011d3	834	#define ADC_CHEN_CHEN_Msk (0xffful << ADC_CHEN_CHEN_Pos) /!< ADC CHEN: CHEN Mask /
sahilmgandhi	18:6a4db94011d3	835
sahilmgandhi	18:6a4db94011d3	836	#define ADC_CHEN_ADTSEN_Pos (16) /!< ADC CHEN: ADTSEN Position /
sahilmgandhi	18:6a4db94011d3	837	#define ADC_CHEN_ADTSEN_Msk (0x1ul << ADC_CHEN_ADTSEN_Pos) /!< ADC CHEN: ADTSEN Mask /
sahilmgandhi	18:6a4db94011d3	838
sahilmgandhi	18:6a4db94011d3	839	#define ADC_CHEN_ADBGEN_Pos (17) /!< ADC CHEN: ADBGEN Position /
sahilmgandhi	18:6a4db94011d3	840	#define ADC_CHEN_ADBGEN_Msk (0x1ul << ADC_CHEN_ADBGEN_Pos) /!< ADC CHEN: ADBGEN Mask /
sahilmgandhi	18:6a4db94011d3	841
sahilmgandhi	18:6a4db94011d3	842	#define ADC_CMP0_ADCMPEN_Pos (0) /!< ADC CMP0: ADCMPEN Position /
sahilmgandhi	18:6a4db94011d3	843	#define ADC_CMP0_ADCMPEN_Msk (0x1ul << ADC_CMP0_ADCMPEN_Pos) /!< ADC CMP0: ADCMPEN Mask /
sahilmgandhi	18:6a4db94011d3	844
sahilmgandhi	18:6a4db94011d3	845	#define ADC_CMP0_ADCMPIE_Pos (1) /!< ADC CMP0: ADCMPIE Position /
sahilmgandhi	18:6a4db94011d3	846	#define ADC_CMP0_ADCMPIE_Msk (0x1ul << ADC_CMP0_ADCMPIE_Pos) /!< ADC CMP0: ADCMPIE Mask /
sahilmgandhi	18:6a4db94011d3	847
sahilmgandhi	18:6a4db94011d3	848	#define ADC_CMP0_CMPCOND_Pos (2) /!< ADC CMP0: CMPCOND Position /
sahilmgandhi	18:6a4db94011d3	849	#define ADC_CMP0_CMPCOND_Msk (0x1ul << ADC_CMP0_CMPCOND_Pos) /!< ADC CMP0: CMPCOND Mask /
sahilmgandhi	18:6a4db94011d3	850
sahilmgandhi	18:6a4db94011d3	851	#define ADC_CMP0_CMPCH_Pos (3) /!< ADC CMP0: CMPCH Position /
sahilmgandhi	18:6a4db94011d3	852	#define ADC_CMP0_CMPCH_Msk (0xful << ADC_CMP0_CMPCH_Pos) /!< ADC CMP0: CMPCH Mask /
sahilmgandhi	18:6a4db94011d3	853
sahilmgandhi	18:6a4db94011d3	854	#define ADC_CMP0_CMPMCNT_Pos (8) /!< ADC CMP0: CMPMCNT Position /
sahilmgandhi	18:6a4db94011d3	855	#define ADC_CMP0_CMPMCNT_Msk (0xful << ADC_CMP0_CMPMCNT_Pos) /!< ADC CMP0: CMPMCNT Mask /
sahilmgandhi	18:6a4db94011d3	856
sahilmgandhi	18:6a4db94011d3	857	#define ADC_CMP0_CMPDAT_Pos (16) /!< ADC CMP0: CMPDAT Position /
sahilmgandhi	18:6a4db94011d3	858	#define ADC_CMP0_CMPDAT_Msk (0xffful << ADC_CMP0_CMPDAT_Pos) /!< ADC CMP0: CMPDAT Mask /
sahilmgandhi	18:6a4db94011d3	859
sahilmgandhi	18:6a4db94011d3	860	#define ADC_CMP1_ADCMPEN_Pos (0) /!< ADC CMP1: ADCMPEN Position /
sahilmgandhi	18:6a4db94011d3	861	#define ADC_CMP1_ADCMPEN_Msk (0x1ul << ADC_CMP1_ADCMPEN_Pos) /!< ADC CMP1: ADCMPEN Mask /
sahilmgandhi	18:6a4db94011d3	862
sahilmgandhi	18:6a4db94011d3	863	#define ADC_CMP1_ADCMPIE_Pos (1) /!< ADC CMP1: ADCMPIE Position /
sahilmgandhi	18:6a4db94011d3	864	#define ADC_CMP1_ADCMPIE_Msk (0x1ul << ADC_CMP1_ADCMPIE_Pos) /!< ADC CMP1: ADCMPIE Mask /
sahilmgandhi	18:6a4db94011d3	865
sahilmgandhi	18:6a4db94011d3	866	#define ADC_CMP1_CMPCOND_Pos (2) /!< ADC CMP1: CMPCOND Position /
sahilmgandhi	18:6a4db94011d3	867	#define ADC_CMP1_CMPCOND_Msk (0x1ul << ADC_CMP1_CMPCOND_Pos) /!< ADC CMP1: CMPCOND Mask /
sahilmgandhi	18:6a4db94011d3	868
sahilmgandhi	18:6a4db94011d3	869	#define ADC_CMP1_CMPCH_Pos (3) /!< ADC CMP1: CMPCH Position /
sahilmgandhi	18:6a4db94011d3	870	#define ADC_CMP1_CMPCH_Msk (0xful << ADC_CMP1_CMPCH_Pos) /!< ADC CMP1: CMPCH Mask /
sahilmgandhi	18:6a4db94011d3	871
sahilmgandhi	18:6a4db94011d3	872	#define ADC_CMP1_CMPMCNT_Pos (8) /!< ADC CMP1: CMPMCNT Position /
sahilmgandhi	18:6a4db94011d3	873	#define ADC_CMP1_CMPMCNT_Msk (0xful << ADC_CMP1_CMPMCNT_Pos) /!< ADC CMP1: CMPMCNT Mask /
sahilmgandhi	18:6a4db94011d3	874
sahilmgandhi	18:6a4db94011d3	875	#define ADC_CMP1_CMPDAT_Pos (16) /!< ADC CMP1: CMPDAT Position /
sahilmgandhi	18:6a4db94011d3	876	#define ADC_CMP1_CMPDAT_Msk (0xffful << ADC_CMP1_CMPDAT_Pos) /!< ADC CMP1: CMPDAT Mask /
sahilmgandhi	18:6a4db94011d3	877
sahilmgandhi	18:6a4db94011d3	878	#define ADC_STATUS0_ADIF_Pos (0) /!< ADC STATUS0: ADIF Position /
sahilmgandhi	18:6a4db94011d3	879	#define ADC_STATUS0_ADIF_Msk (0x1ul << ADC_STATUS0_ADIF_Pos) /!< ADC STATUS0: ADIF Mask /
sahilmgandhi	18:6a4db94011d3	880
sahilmgandhi	18:6a4db94011d3	881	#define ADC_STATUS0_ADCMPF0_Pos (1) /!< ADC STATUS0: ADCMPF0 Position /
sahilmgandhi	18:6a4db94011d3	882	#define ADC_STATUS0_ADCMPF0_Msk (0x1ul << ADC_STATUS0_ADCMPF0_Pos) /!< ADC STATUS0: ADCMPF0 Mask /
sahilmgandhi	18:6a4db94011d3	883
sahilmgandhi	18:6a4db94011d3	884	#define ADC_STATUS0_ADCMPF1_Pos (2) /!< ADC STATUS0: ADCMPF1 Position /
sahilmgandhi	18:6a4db94011d3	885	#define ADC_STATUS0_ADCMPF1_Msk (0x1ul << ADC_STATUS0_ADCMPF1_Pos) /!< ADC STATUS0: ADCMPF1 Mask /
sahilmgandhi	18:6a4db94011d3	886
sahilmgandhi	18:6a4db94011d3	887	#define ADC_STATUS0_BUSY_Pos (3) /!< ADC STATUS0: BUSY Position /
sahilmgandhi	18:6a4db94011d3	888	#define ADC_STATUS0_BUSY_Msk (0x1ul << ADC_STATUS0_BUSY_Pos) /!< ADC STATUS0: BUSY Mask /
sahilmgandhi	18:6a4db94011d3	889
sahilmgandhi	18:6a4db94011d3	890	#define ADC_STATUS0_CHANNEL_Pos (4) /!< ADC STATUS0: CHANNEL Position /
sahilmgandhi	18:6a4db94011d3	891	#define ADC_STATUS0_CHANNEL_Msk (0xful << ADC_STATUS0_CHANNEL_Pos) /!< ADC STATUS0: CHANNEL Mask /
sahilmgandhi	18:6a4db94011d3	892
sahilmgandhi	18:6a4db94011d3	893	#define ADC_STATUS1_VALID_Pos (0) /!< ADC STATUS1: VALID Position /
sahilmgandhi	18:6a4db94011d3	894	#define ADC_STATUS1_VALID_Msk (0x3ffful << ADC_STATUS1_VALID_Pos) /!< ADC STATUS1: VALID Mask /
sahilmgandhi	18:6a4db94011d3	895
sahilmgandhi	18:6a4db94011d3	896	#define ADC_STATUS1_OV_Pos (16) /!< ADC STATUS1: OV Position /
sahilmgandhi	18:6a4db94011d3	897	#define ADC_STATUS1_OV_Msk (0x3ffful << ADC_STATUS1_OV_Pos) /!< ADC STATUS1: OV Mask /
sahilmgandhi	18:6a4db94011d3	898
sahilmgandhi	18:6a4db94011d3	899	#define ADC_CURDAT_CURDAT_Pos (0) /!< ADC CURDAT: CURDAT Position /
sahilmgandhi	18:6a4db94011d3	900	#define ADC_CURDAT_CURDAT_Msk (0x3fffful << ADC_CURDAT_CURDAT_Pos) /!< ADC CURDAT: CURDAT Mask /
sahilmgandhi	18:6a4db94011d3	901
sahilmgandhi	18:6a4db94011d3	902	/*@}/ /* ADC_CONST */
sahilmgandhi	18:6a4db94011d3	903	/*@}/ /* end of ADC register group */
sahilmgandhi	18:6a4db94011d3	904
sahilmgandhi	18:6a4db94011d3	905
sahilmgandhi	18:6a4db94011d3	906	/---------------------- Controller Area Network Controller -------------------------/
sahilmgandhi	18:6a4db94011d3	907	/**
sahilmgandhi	18:6a4db94011d3	908	@addtogroup CAN Controller Area Network Controller(CAN)
sahilmgandhi	18:6a4db94011d3	909	Memory Mapped Structure for CAN Controller
sahilmgandhi	18:6a4db94011d3	910	@{ */
sahilmgandhi	18:6a4db94011d3	911
sahilmgandhi	18:6a4db94011d3	912	typedef struct {
sahilmgandhi	18:6a4db94011d3	913
sahilmgandhi	18:6a4db94011d3	914	/**
sahilmgandhi	18:6a4db94011d3	915	* CAN_IFn_CREQ
sahilmgandhi	18:6a4db94011d3	916	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	917	* Offset: 0x20, 0x80 IFn (Register Map Note 2) Command Request Registers
sahilmgandhi	18:6a4db94011d3	918	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	919	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	920	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	921	* \|[0:5] \|MessageNumber\|Message Number
sahilmgandhi	18:6a4db94011d3	922	* \| \| \|0x01-0x20: Valid Message Number, the Message Object in the Message
sahilmgandhi	18:6a4db94011d3	923	* \| \| \|RAM is selected for data transfer.
sahilmgandhi	18:6a4db94011d3	924	* \| \| \|0x00: Not a valid Message Number, interpreted as 0x20.
sahilmgandhi	18:6a4db94011d3	925	* \| \| \|0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F.
sahilmgandhi	18:6a4db94011d3	926	* \|[15] \|Busy \|Busy Flag
sahilmgandhi	18:6a4db94011d3	927	* \| \| \|0 = Read/write action has finished.
sahilmgandhi	18:6a4db94011d3	928	* \| \| \|1 = Writing to the IFn Command Request Register is in progress.
sahilmgandhi	18:6a4db94011d3	929	* \| \| \|This bit can only be read by the software.
sahilmgandhi	18:6a4db94011d3	930	*/
sahilmgandhi	18:6a4db94011d3	931	__IO uint32_t CREQ;
sahilmgandhi	18:6a4db94011d3	932
sahilmgandhi	18:6a4db94011d3	933	/**
sahilmgandhi	18:6a4db94011d3	934	* CAN_IFn_CMASK
sahilmgandhi	18:6a4db94011d3	935	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	936	* Offset: 0x24, 0x84 IFn Command Mask Register
sahilmgandhi	18:6a4db94011d3	937	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	938	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	939	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	940	* \|[0] \|DAT_B \|Access Data Bytes [7:4]
sahilmgandhi	18:6a4db94011d3	941	* \| \| \|Write Operation:
sahilmgandhi	18:6a4db94011d3	942	* \| \| \|0 = Data Bytes [7:4] unchanged.
sahilmgandhi	18:6a4db94011d3	943	* \| \| \|1 = Transfer Data Bytes [7:4] to Message Object.
sahilmgandhi	18:6a4db94011d3	944	* \| \| \|Read Operation:
sahilmgandhi	18:6a4db94011d3	945	* \| \| \|0 = Data Bytes [7:4] unchanged.
sahilmgandhi	18:6a4db94011d3	946	* \| \| \|1 = Transfer Data Bytes [7:4] to IFn Message Buffer Register.
sahilmgandhi	18:6a4db94011d3	947	* \|[1] \|DAT_A \|Access Data Bytes [3:0]
sahilmgandhi	18:6a4db94011d3	948	* \| \| \|Write Operation:
sahilmgandhi	18:6a4db94011d3	949	* \| \| \|0 = Data Bytes [3:0] unchanged.
sahilmgandhi	18:6a4db94011d3	950	* \| \| \|1 = Transfer Data Bytes [3:0] to Message Object.
sahilmgandhi	18:6a4db94011d3	951	* \| \| \|Read Operation:
sahilmgandhi	18:6a4db94011d3	952	* \| \| \|0 = Data Bytes [3:0] unchanged.
sahilmgandhi	18:6a4db94011d3	953	* \| \| \|1 = Transfer Data Bytes [3:0] to IFn Message Buffer Register.
sahilmgandhi	18:6a4db94011d3	954	* \|[2] \|TxRqst_NewDat\|Access Transmission Request Bit When Write Operation
sahilmgandhi	18:6a4db94011d3	955	* \| \| \|0 = TxRqst bit unchanged.
sahilmgandhi	18:6a4db94011d3	956	* \| \| \|1 = Set TxRqst bit.
sahilmgandhi	18:6a4db94011d3	957	* \| \| \|Note: If a transmission is requested by programming bit TxRqst/NewDat in the IFn Command Mask Register, bit TxRqst in the IFn Message Control Register will be ignored.
sahilmgandhi	18:6a4db94011d3	958	* \| \| \|Access New Data Bit when Read Operation.
sahilmgandhi	18:6a4db94011d3	959	* \| \| \|0 = NewDat bit remains unchanged.
sahilmgandhi	18:6a4db94011d3	960	* \| \| \|1 = Clear NewDat bit in the Message Object.
sahilmgandhi	18:6a4db94011d3	961	* \| \| \|Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat.
sahilmgandhi	18:6a4db94011d3	962	* \| \| \|The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits.
sahilmgandhi	18:6a4db94011d3	963	* \|[3] \|ClrIntPnd \|Clear Interrupt Pending Bit
sahilmgandhi	18:6a4db94011d3	964	* \| \| \|Write Operation:
sahilmgandhi	18:6a4db94011d3	965	* \| \| \|When writing to a Message Object, this bit is ignored.
sahilmgandhi	18:6a4db94011d3	966	* \| \| \|Read Operation:
sahilmgandhi	18:6a4db94011d3	967	* \| \| \|0 = IntPnd bit (CAN_IFn_MCON[13]) remains unchanged.
sahilmgandhi	18:6a4db94011d3	968	* \| \| \|1 = Clear IntPnd bit in the Message Object.
sahilmgandhi	18:6a4db94011d3	969	* \|[4] \|Control \|Control Access Control Bits
sahilmgandhi	18:6a4db94011d3	970	* \| \| \|Write Operation:
sahilmgandhi	18:6a4db94011d3	971	* \| \| \|0 = Control Bits unchanged.
sahilmgandhi	18:6a4db94011d3	972	* \| \| \|1 = Transfer Control Bits to Message Object.
sahilmgandhi	18:6a4db94011d3	973	* \| \| \|Read Operation:
sahilmgandhi	18:6a4db94011d3	974	* \| \| \|0 = Control Bits unchanged.
sahilmgandhi	18:6a4db94011d3	975	* \| \| \|1 = Transfer Control Bits to IFn Message Buffer Register.
sahilmgandhi	18:6a4db94011d3	976	* \|[5] \|Arb \|Access Arbitration Bits
sahilmgandhi	18:6a4db94011d3	977	* \| \| \|Write Operation:
sahilmgandhi	18:6a4db94011d3	978	* \| \| \|0 = Arbitration bits unchanged.
sahilmgandhi	18:6a4db94011d3	979	* \| \| \|1 = Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_APB2[15]) to Message Object.
sahilmgandhi	18:6a4db94011d3	980	* \| \| \|Read Operation:
sahilmgandhi	18:6a4db94011d3	981	* \| \| \|0 = Arbitration bits unchanged.
sahilmgandhi	18:6a4db94011d3	982	* \| \| \|1 = Transfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register.
sahilmgandhi	18:6a4db94011d3	983	* \|[6] \|Mask \|Access Mask Bits
sahilmgandhi	18:6a4db94011d3	984	* \| \| \|Write Operation:
sahilmgandhi	18:6a4db94011d3	985	* \| \| \|0 = Mask bits unchanged.
sahilmgandhi	18:6a4db94011d3	986	* \| \| \|1 = Transfer Identifier Mask + MDir + MXtd to Message Object.
sahilmgandhi	18:6a4db94011d3	987	* \| \| \|Read Operation:
sahilmgandhi	18:6a4db94011d3	988	* \| \| \|0 = Mask bits unchanged.
sahilmgandhi	18:6a4db94011d3	989	* \| \| \|1 = Transfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register.
sahilmgandhi	18:6a4db94011d3	990	* \|[7] \|WR_RD \|Write / Read Mode
sahilmgandhi	18:6a4db94011d3	991	* \| \| \|0 = Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers.
sahilmgandhi	18:6a4db94011d3	992	* \| \| \|1 = Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register.
sahilmgandhi	18:6a4db94011d3	993	*/
sahilmgandhi	18:6a4db94011d3	994	__IO uint32_t CMASK;
sahilmgandhi	18:6a4db94011d3	995
sahilmgandhi	18:6a4db94011d3	996	/**
sahilmgandhi	18:6a4db94011d3	997	* CAN_IFn_MASK1
sahilmgandhi	18:6a4db94011d3	998	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	999	* Offset: 0x28, 0x88 IFn Mask 1 Register
sahilmgandhi	18:6a4db94011d3	1000	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1001	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1002	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1003	* \|[0:15] \|Msk150 \|Identifier Mask 15-0
sahilmgandhi	18:6a4db94011d3	1004	* \| \| \|0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
sahilmgandhi	18:6a4db94011d3	1005	* \| \| \|1 = The corresponding identifier bit is used for acceptance filtering.
sahilmgandhi	18:6a4db94011d3	1006	*/
sahilmgandhi	18:6a4db94011d3	1007	__IO uint32_t MASK1;
sahilmgandhi	18:6a4db94011d3	1008
sahilmgandhi	18:6a4db94011d3	1009	/**
sahilmgandhi	18:6a4db94011d3	1010	* CAN_IFn_MASK2
sahilmgandhi	18:6a4db94011d3	1011	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1012	* Offset: 0x2C, 0x8C IFn Mask 2 Register
sahilmgandhi	18:6a4db94011d3	1013	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1014	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1015	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1016	* \|[0:12] \|Msk2816 \|Identifier Mask 28-16
sahilmgandhi	18:6a4db94011d3	1017	* \| \| \|0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
sahilmgandhi	18:6a4db94011d3	1018	* \| \| \|1 = The corresponding identifier bit is used for acceptance filtering.
sahilmgandhi	18:6a4db94011d3	1019	* \|[14] \|MDir \|Mask Message Direction
sahilmgandhi	18:6a4db94011d3	1020	* \| \| \|0 = The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering.
sahilmgandhi	18:6a4db94011d3	1021	* \| \| \|1 = The message direction bit (Dir) is used for acceptance filtering.
sahilmgandhi	18:6a4db94011d3	1022	* \|[15] \|MXtd \|Mask Extended Identifier
sahilmgandhi	18:6a4db94011d3	1023	* \| \| \|0 = The extended identifier bit (IDE) has no effect on the acceptance filtering.
sahilmgandhi	18:6a4db94011d3	1024	* \| \| \|1 = The extended identifier bit (IDE) is used for acceptance filtering.
sahilmgandhi	18:6a4db94011d3	1025	* \| \| \|Note: When 11-bit ("standard") Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]).
sahilmgandhi	18:6a4db94011d3	1026	* \| \| \|For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered.
sahilmgandhi	18:6a4db94011d3	1027	*/
sahilmgandhi	18:6a4db94011d3	1028	__IO uint32_t MASK2;
sahilmgandhi	18:6a4db94011d3	1029
sahilmgandhi	18:6a4db94011d3	1030	/**
sahilmgandhi	18:6a4db94011d3	1031	* CAN_IFn_ARB1
sahilmgandhi	18:6a4db94011d3	1032	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1033	* Offset: 0x30, 0x90 IFn Arbitration 1 Register
sahilmgandhi	18:6a4db94011d3	1034	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1035	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1036	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1037	* \|[0:15] \|ID150 \|Message Identifier 15-0
sahilmgandhi	18:6a4db94011d3	1038	* \| \| \|ID28 - ID0, 29-bit Identifier ("Extended Frame").
sahilmgandhi	18:6a4db94011d3	1039	* \| \| \|ID28 - ID18, 11-bit Identifier ("Standard Frame")
sahilmgandhi	18:6a4db94011d3	1040	*/
sahilmgandhi	18:6a4db94011d3	1041	__IO uint32_t ARB1;
sahilmgandhi	18:6a4db94011d3	1042
sahilmgandhi	18:6a4db94011d3	1043	/**
sahilmgandhi	18:6a4db94011d3	1044	* CAN_IFn_ARB2
sahilmgandhi	18:6a4db94011d3	1045	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1046	* Offset: 0x34, 0x94 IFn Arbitration 2 Register
sahilmgandhi	18:6a4db94011d3	1047	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1048	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1049	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1050	* \|[0:12] \|ID2816 \|Message Identifier 28-16
sahilmgandhi	18:6a4db94011d3	1051	* \| \| \|ID28 - ID0, 29-bit Identifier ("Extended Frame").
sahilmgandhi	18:6a4db94011d3	1052	* \| \| \|ID28 - ID18, 11-bit Identifier ("Standard Frame")
sahilmgandhi	18:6a4db94011d3	1053	* \|[13] \|Dir \|Message Direction
sahilmgandhi	18:6a4db94011d3	1054	* \| \| \|0 = Direction is receive.
sahilmgandhi	18:6a4db94011d3	1055	* \| \| \|On TxRqst, a Remote Frame with the identifier of this Message Object is transmitted.
sahilmgandhi	18:6a4db94011d3	1056	* \| \| \|On reception of a Data Frame with matching identifier, that message is stored in this Message Object.
sahilmgandhi	18:6a4db94011d3	1057	* \| \| \|1 = Direction is transmit.
sahilmgandhi	18:6a4db94011d3	1058	* \| \| \|On TxRqst, the respective Message Object is transmitted as a Data Frame.
sahilmgandhi	18:6a4db94011d3	1059	* \| \| \|On reception of a Remote Frame with matching identifier, the TxRqst bit (CAN_IFn_CMASK[2]) of this Message Object is set (if RmtEn (CAN_IFn_MCON[9]) = one).
sahilmgandhi	18:6a4db94011d3	1060	* \|[14] \|Xtd \|Extended Identifier
sahilmgandhi	18:6a4db94011d3	1061	* \| \| \|0 = The 11-bit ("standard") Identifier will be used for this Message Object.
sahilmgandhi	18:6a4db94011d3	1062	* \| \| \|1 = The 29-bit ("extended") Identifier will be used for this Message Object.
sahilmgandhi	18:6a4db94011d3	1063	* \|[15] \|MsgVal \|Message Valid
sahilmgandhi	18:6a4db94011d3	1064	* \| \| \|0 = The Message Object is ignored by the Message Handler.
sahilmgandhi	18:6a4db94011d3	1065	* \| \| \|1 = The Message Object is configured and should be considered by the Message Handler.
sahilmgandhi	18:6a4db94011d3	1066	* \| \| \|Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]).
sahilmgandhi	18:6a4db94011d3	1067	* \| \| \|This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_APB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required.
sahilmgandhi	18:6a4db94011d3	1068	*/
sahilmgandhi	18:6a4db94011d3	1069	__IO uint32_t ARB2;
sahilmgandhi	18:6a4db94011d3	1070
sahilmgandhi	18:6a4db94011d3	1071	/**
sahilmgandhi	18:6a4db94011d3	1072	* CAN_IFn_MCON
sahilmgandhi	18:6a4db94011d3	1073	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1074	* Offset: 0x38, 0x98 IFn Message Control Register
sahilmgandhi	18:6a4db94011d3	1075	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1076	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1077	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1078	* \|[0:3] \|DLC \|Data Length Code
sahilmgandhi	18:6a4db94011d3	1079	* \| \| \|0-8: Data Frame has 0-8 data bytes.
sahilmgandhi	18:6a4db94011d3	1080	* \| \| \|9-15: Data Frame has 8 data bytes
sahilmgandhi	18:6a4db94011d3	1081	* \| \| \|Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes.
sahilmgandhi	18:6a4db94011d3	1082	* \| \| \|When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.
sahilmgandhi	18:6a4db94011d3	1083	* \| \| \|Data 0: 1st data byte of a CAN Data Frame
sahilmgandhi	18:6a4db94011d3	1084	* \| \| \|Data 1: 2nd data byte of a CAN Data Frame
sahilmgandhi	18:6a4db94011d3	1085	* \| \| \|Data 2: 3rd data byte of a CAN Data Frame
sahilmgandhi	18:6a4db94011d3	1086	* \| \| \|Data 3: 4th data byte of a CAN Data Frame
sahilmgandhi	18:6a4db94011d3	1087	* \| \| \|Data 4: 5th data byte of a CAN Data Frame
sahilmgandhi	18:6a4db94011d3	1088	* \| \| \|Data 5: 6th data byte of a CAN Data Frame
sahilmgandhi	18:6a4db94011d3	1089	* \| \| \|Data 6: 7th data byte of a CAN Data Frame
sahilmgandhi	18:6a4db94011d3	1090	* \| \| \|Data 7 : 8th data byte of a CAN Data Frame
sahilmgandhi	18:6a4db94011d3	1091	* \| \| \|Note: The Data 0 Byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data 7 byte is the last.
sahilmgandhi	18:6a4db94011d3	1092	* \| \| \|When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object.
sahilmgandhi	18:6a4db94011d3	1093	* \| \| \|If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values.
sahilmgandhi	18:6a4db94011d3	1094	* \|[7] \|EoB \|End Of Buffer
sahilmgandhi	18:6a4db94011d3	1095	* \| \| \|0 = Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer.
sahilmgandhi	18:6a4db94011d3	1096	* \| \| \|1 = Single Message Object or last Message Object of a FIFO Buffer.
sahilmgandhi	18:6a4db94011d3	1097	* \| \| \|Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer.
sahilmgandhi	18:6a4db94011d3	1098	* \| \| \|For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one.
sahilmgandhi	18:6a4db94011d3	1099	* \|[8] \|TxRqst \|Transmit Request
sahilmgandhi	18:6a4db94011d3	1100	* \| \| \|0 = This Message Object is not waiting for transmission.
sahilmgandhi	18:6a4db94011d3	1101	* \| \| \|1 = The transmission of this Message Object is requested and is not yet done.
sahilmgandhi	18:6a4db94011d3	1102	* \|[9] \|RmtEn \|Remote Enable Control
sahilmgandhi	18:6a4db94011d3	1103	* \| \| \|0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged.
sahilmgandhi	18:6a4db94011d3	1104	* \| \| \|1 = At the reception of a Remote Frame, TxRqst is set.
sahilmgandhi	18:6a4db94011d3	1105	* \|[10] \|RxIE \|Receive Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	1106	* \| \| \|0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame.
sahilmgandhi	18:6a4db94011d3	1107	* \| \| \|1 = IntPnd will be set after a successful reception of a frame.
sahilmgandhi	18:6a4db94011d3	1108	* \|[11] \|TxIE \|Transmit Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	1109	* \| \| \|0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame.
sahilmgandhi	18:6a4db94011d3	1110	* \| \| \|1 = IntPnd will be set after a successful transmission of a frame.
sahilmgandhi	18:6a4db94011d3	1111	* \|[12] \|UMask \|Use Acceptance Mask
sahilmgandhi	18:6a4db94011d3	1112	* \| \| \|0 = Mask ignored.
sahilmgandhi	18:6a4db94011d3	1113	* \| \| \|1 = Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering.
sahilmgandhi	18:6a4db94011d3	1114	* \| \| \|Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_APB2[15]) is set to one.
sahilmgandhi	18:6a4db94011d3	1115	* \|[13] \|IntPnd \|Interrupt Pending
sahilmgandhi	18:6a4db94011d3	1116	* \| \| \|0 = This message object is not the source of an interrupt.
sahilmgandhi	18:6a4db94011d3	1117	* \| \| \|1 = This message object is the source of an interrupt.
sahilmgandhi	18:6a4db94011d3	1118	* \| \| \|The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.
sahilmgandhi	18:6a4db94011d3	1119	* \|[14] \|MsgLst \|Message Lost (only valid for Message Objects with direction = receive).
sahilmgandhi	18:6a4db94011d3	1120	* \| \| \|0 = No message lost since last time this bit was reset by the CPU.
sahilmgandhi	18:6a4db94011d3	1121	* \| \| \|1 = The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message.
sahilmgandhi	18:6a4db94011d3	1122	* \|[15] \|NewDat \|New Data
sahilmgandhi	18:6a4db94011d3	1123	* \| \| \|0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software.
sahilmgandhi	18:6a4db94011d3	1124	* \| \| \|1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
sahilmgandhi	18:6a4db94011d3	1125	*/
sahilmgandhi	18:6a4db94011d3	1126	__IO uint32_t MCON;
sahilmgandhi	18:6a4db94011d3	1127
sahilmgandhi	18:6a4db94011d3	1128	/**
sahilmgandhi	18:6a4db94011d3	1129	* CAN_IFn_DAT_A1
sahilmgandhi	18:6a4db94011d3	1130	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1131	* Offset: 0x3C, 0x9C IFn Data A1 Register (Register Map Note 3)
sahilmgandhi	18:6a4db94011d3	1132	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1133	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1134	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1135	* \|[0:7] \|Data0 \|Data Byte 0
sahilmgandhi	18:6a4db94011d3	1136	* \| \| \|1st data byte of a CAN Data Frame
sahilmgandhi	18:6a4db94011d3	1137	* \|[8:15] \|Data1 \|Data Byte 1
sahilmgandhi	18:6a4db94011d3	1138	* \| \| \|2nd data byte of a CAN Data Frame
sahilmgandhi	18:6a4db94011d3	1139	*/
sahilmgandhi	18:6a4db94011d3	1140	__IO uint32_t DAT_A1;
sahilmgandhi	18:6a4db94011d3	1141
sahilmgandhi	18:6a4db94011d3	1142	/**
sahilmgandhi	18:6a4db94011d3	1143	* CAN_IFn_DAT_A2
sahilmgandhi	18:6a4db94011d3	1144	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1145	* Offset: 0x40, 0xA0 IFn Data A2 Register (Register Map Note 3)
sahilmgandhi	18:6a4db94011d3	1146	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1147	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1148	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1149	* \|[0:7] \|Data2 \|Data Byte 2
sahilmgandhi	18:6a4db94011d3	1150	* \| \| \|3rd data byte of CAN Data Frame
sahilmgandhi	18:6a4db94011d3	1151	* \|[8:15] \|Data3 \|Data Byte 3
sahilmgandhi	18:6a4db94011d3	1152	* \| \| \|4th data byte of CAN Data Frame
sahilmgandhi	18:6a4db94011d3	1153	*/
sahilmgandhi	18:6a4db94011d3	1154	__IO uint32_t DAT_A2;
sahilmgandhi	18:6a4db94011d3	1155
sahilmgandhi	18:6a4db94011d3	1156	/**
sahilmgandhi	18:6a4db94011d3	1157	* CAN_IFn_DAT_B1
sahilmgandhi	18:6a4db94011d3	1158	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1159	* Offset: 0x44, 0xA4 IFn Data B1 Register (Register Map Note 3)
sahilmgandhi	18:6a4db94011d3	1160	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1161	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1162	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1163	* \|[0:7] \|Data4 \|Data Byte 4
sahilmgandhi	18:6a4db94011d3	1164	* \| \| \|5th data byte of CAN Data Frame
sahilmgandhi	18:6a4db94011d3	1165	* \|[8:15] \|Data5 \|Data Byte 5
sahilmgandhi	18:6a4db94011d3	1166	* \| \| \|6th data byte of CAN Data Frame
sahilmgandhi	18:6a4db94011d3	1167	*/
sahilmgandhi	18:6a4db94011d3	1168	__IO uint32_t DAT_B1;
sahilmgandhi	18:6a4db94011d3	1169
sahilmgandhi	18:6a4db94011d3	1170	/**
sahilmgandhi	18:6a4db94011d3	1171	* CAN_IFn_DAT_B2
sahilmgandhi	18:6a4db94011d3	1172	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1173	* Offset: 0x48, 0xA8 IFn Data B2 Register (Register Map Note 3)
sahilmgandhi	18:6a4db94011d3	1174	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1175	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1176	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1177	* \|[0:7] \|Data6 \|Data Byte 6
sahilmgandhi	18:6a4db94011d3	1178	* \| \| \|7th data byte of CAN Data Frame.
sahilmgandhi	18:6a4db94011d3	1179	* \|[8:15] \|Data7 \|Data Byte 7
sahilmgandhi	18:6a4db94011d3	1180	* \| \| \|8th data byte of CAN Data Frame.
sahilmgandhi	18:6a4db94011d3	1181	*/
sahilmgandhi	18:6a4db94011d3	1182	__IO uint32_t DAT_B2;
sahilmgandhi	18:6a4db94011d3	1183
sahilmgandhi	18:6a4db94011d3	1184	__I uint32_t RESERVE0[13];
sahilmgandhi	18:6a4db94011d3	1185
sahilmgandhi	18:6a4db94011d3	1186	} CAN_IF_T;
sahilmgandhi	18:6a4db94011d3	1187
sahilmgandhi	18:6a4db94011d3	1188	typedef struct {
sahilmgandhi	18:6a4db94011d3	1189
sahilmgandhi	18:6a4db94011d3	1190	/**
sahilmgandhi	18:6a4db94011d3	1191	* CAN_CON
sahilmgandhi	18:6a4db94011d3	1192	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1193	* Offset: 0x00 Control Register
sahilmgandhi	18:6a4db94011d3	1194	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1195	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1196	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1197	* \|[0] \|Init \|Init Initialization
sahilmgandhi	18:6a4db94011d3	1198	* \| \| \|0 = Normal Operation.
sahilmgandhi	18:6a4db94011d3	1199	* \| \| \|1 = Initialization is started.
sahilmgandhi	18:6a4db94011d3	1200	* \|[1] \|IE \|Module Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	1201	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	1202	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	1203	* \|[2] \|SIE \|Status Change Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	1204	* \| \| \|0 = Disabled - No Status Change Interrupt will be generated.
sahilmgandhi	18:6a4db94011d3	1205	* \| \| \|1 = Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected.
sahilmgandhi	18:6a4db94011d3	1206	* \|[3] \|EIE \|Error Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	1207	* \| \| \|0 = Disabled - No Error Status Interrupt will be generated.
sahilmgandhi	18:6a4db94011d3	1208	* \| \| \|1 = Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt.
sahilmgandhi	18:6a4db94011d3	1209	* \|[5] \|DAR \|Automatic Re-Transmission Disable Control
sahilmgandhi	18:6a4db94011d3	1210	* \| \| \|0 = Automatic Retransmission of disturbed messages enabled.
sahilmgandhi	18:6a4db94011d3	1211	* \| \| \|1 = Automatic Retransmission disabled.
sahilmgandhi	18:6a4db94011d3	1212	* \|[6] \|CCE \|Configuration Change Enable Control
sahilmgandhi	18:6a4db94011d3	1213	* \| \| \|0 = No write access to the Bit Timing Register.
sahilmgandhi	18:6a4db94011d3	1214	* \| \| \|1 = Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1).
sahilmgandhi	18:6a4db94011d3	1215	* \|[7] \|Test \|Test Mode Enable Control
sahilmgandhi	18:6a4db94011d3	1216	* \| \| \|0 = Normal Operation.
sahilmgandhi	18:6a4db94011d3	1217	* \| \| \|1 = Test Mode.
sahilmgandhi	18:6a4db94011d3	1218	*/
sahilmgandhi	18:6a4db94011d3	1219	__IO uint32_t CON;
sahilmgandhi	18:6a4db94011d3	1220
sahilmgandhi	18:6a4db94011d3	1221	/**
sahilmgandhi	18:6a4db94011d3	1222	* CAN_STATUS
sahilmgandhi	18:6a4db94011d3	1223	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1224	* Offset: 0x04 Status Register
sahilmgandhi	18:6a4db94011d3	1225	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1226	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1227	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1228	* \|[0:2] \|LEC \|Last Error Code (Type Of The Last Error To Occur On The CAN Bus)
sahilmgandhi	18:6a4db94011d3	1229	* \| \| \|The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus.
sahilmgandhi	18:6a4db94011d3	1230	* \| \| \|This field will be cleared to '0' when a message has been transferred (reception or transmission) without error.
sahilmgandhi	18:6a4db94011d3	1231	* \| \| \|The unused code '7' may be written by the CPU to check for updates.
sahilmgandhi	18:6a4db94011d3	1232	* \| \| \|The following table describes the error code.
sahilmgandhi	18:6a4db94011d3	1233	* \|[3] \|TxOK \|Transmitted A Message Successfully
sahilmgandhi	18:6a4db94011d3	1234	* \| \| \|0 = Since this bit was reset by the CPU, no message has been successfully transmitted.
sahilmgandhi	18:6a4db94011d3	1235	* \| \| \|This bit is never reset by the CAN Core.
sahilmgandhi	18:6a4db94011d3	1236	* \| \| \|1 = Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted.
sahilmgandhi	18:6a4db94011d3	1237	* \|[4] \|RxOK \|Received A Message Successfully
sahilmgandhi	18:6a4db94011d3	1238	* \| \| \|0 = No message has been successfully received since this bit was last reset by the CPU.
sahilmgandhi	18:6a4db94011d3	1239	* \| \| \|This bit is never reset by the CAN Core.
sahilmgandhi	18:6a4db94011d3	1240	* \| \| \|1 = A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering).
sahilmgandhi	18:6a4db94011d3	1241	* \|[5] \|EPass \|Error Passive (Read Only)
sahilmgandhi	18:6a4db94011d3	1242	* \| \| \|0 = The CAN Core is error active.
sahilmgandhi	18:6a4db94011d3	1243	* \| \| \|1 = The CAN Core is in the error passive state as defined in the CAN Specification.
sahilmgandhi	18:6a4db94011d3	1244	* \|[6] \|EWarn \|Error Warning Status (Read Only)
sahilmgandhi	18:6a4db94011d3	1245	* \| \| \|0 = Both error counters are below the error warning limit of 96.
sahilmgandhi	18:6a4db94011d3	1246	* \| \| \|1 = At least one of the error counters in the EML has reached the error warning limit of 96.
sahilmgandhi	18:6a4db94011d3	1247	* \|[7] \|BOff \|Bus-Off Status (Read Only)
sahilmgandhi	18:6a4db94011d3	1248	* \| \| \|0 = The CAN module is not in bus-off state.
sahilmgandhi	18:6a4db94011d3	1249	* \| \| \|1 = The CAN module is in bus-off state.
sahilmgandhi	18:6a4db94011d3	1250	*/
sahilmgandhi	18:6a4db94011d3	1251	__IO uint32_t STATUS;
sahilmgandhi	18:6a4db94011d3	1252
sahilmgandhi	18:6a4db94011d3	1253	/**
sahilmgandhi	18:6a4db94011d3	1254	* CAN_ERR
sahilmgandhi	18:6a4db94011d3	1255	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1256	* Offset: 0x08 Error Counter Register
sahilmgandhi	18:6a4db94011d3	1257	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1258	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1259	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1260	* \|[0:7] \|TEC \|Transmit Error Counter
sahilmgandhi	18:6a4db94011d3	1261	* \| \| \|Actual state of the Transmit Error Counter. Values between 0 and 255.
sahilmgandhi	18:6a4db94011d3	1262	* \|[8:14] \|REC \|Receive Error Counter
sahilmgandhi	18:6a4db94011d3	1263	* \| \| \|Actual state of the Receive Error Counter. Values between 0 and 127.
sahilmgandhi	18:6a4db94011d3	1264	* \|[15] \|RP \|Receive Error Passive
sahilmgandhi	18:6a4db94011d3	1265	* \| \| \|0 = The Receive Error Counter is below the error passive level.
sahilmgandhi	18:6a4db94011d3	1266	* \| \| \|1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification.
sahilmgandhi	18:6a4db94011d3	1267	*/
sahilmgandhi	18:6a4db94011d3	1268	__IO uint32_t ERR;
sahilmgandhi	18:6a4db94011d3	1269
sahilmgandhi	18:6a4db94011d3	1270	/**
sahilmgandhi	18:6a4db94011d3	1271	* CAN_BTIME
sahilmgandhi	18:6a4db94011d3	1272	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1273	* Offset: 0x0C Bit Timing Register
sahilmgandhi	18:6a4db94011d3	1274	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1275	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1276	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1277	* \|[0:5] \|BRP \|Baud Rate Prescaler
sahilmgandhi	18:6a4db94011d3	1278	* \| \| \|0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta.
sahilmgandhi	18:6a4db94011d3	1279	* \| \| \|The bit time is built up from a multiple of this quanta.
sahilmgandhi	18:6a4db94011d3	1280	* \| \| \|Valid values for the Baud Rate Prescaler are [ 0 ... 63 ].
sahilmgandhi	18:6a4db94011d3	1281	* \| \| \|The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
sahilmgandhi	18:6a4db94011d3	1282	* \|[6:7] \|SJW \|(Re)Synchronization Jump Width
sahilmgandhi	18:6a4db94011d3	1283	* \| \| \|0x0-0x3: Valid programmed values are [0 ... 3].
sahilmgandhi	18:6a4db94011d3	1284	* \| \| \|The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
sahilmgandhi	18:6a4db94011d3	1285	* \|[8:11] \|TSeg1 \|Time Segment Before The Sample Point Minus Sync_Seg
sahilmgandhi	18:6a4db94011d3	1286	* \| \| \|0x01-0x0F: valid values for TSeg1 are [1 ... 15].
sahilmgandhi	18:6a4db94011d3	1287	* \| \| \|The actual interpretation by the hardware of this value is such that one more than the value programmed is used.
sahilmgandhi	18:6a4db94011d3	1288	* \|[12:14] \|TSeg2 \|Time Segment After Sample Point
sahilmgandhi	18:6a4db94011d3	1289	* \| \| \|0x0-0x7: Valid values for TSeg2 are [0 ... 7].
sahilmgandhi	18:6a4db94011d3	1290	* \| \| \|The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
sahilmgandhi	18:6a4db94011d3	1291	*/
sahilmgandhi	18:6a4db94011d3	1292	__IO uint32_t BTIME;
sahilmgandhi	18:6a4db94011d3	1293
sahilmgandhi	18:6a4db94011d3	1294	/**
sahilmgandhi	18:6a4db94011d3	1295	* CAN_IIDR
sahilmgandhi	18:6a4db94011d3	1296	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1297	* Offset: 0x10 Interrupt Identifier Register
sahilmgandhi	18:6a4db94011d3	1298	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1299	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1300	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1301	* \|[0:15] \|IntId \|Interrupt Identifier (Indicates The Source Of The Interrupt)
sahilmgandhi	18:6a4db94011d3	1302	* \| \| \|If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order.
sahilmgandhi	18:6a4db94011d3	1303	* \| \| \|An interrupt remains pending until the application software has cleared it.
sahilmgandhi	18:6a4db94011d3	1304	* \| \| \|If IntId is different from 0x0000 and IE (CAN_IFn_MCON[1]) is set, the IRQ interrupt signal to the EIC is active.
sahilmgandhi	18:6a4db94011d3	1305	* \| \| \|The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.
sahilmgandhi	18:6a4db94011d3	1306	* \| \| \|The Status Interrupt has the highest priority.
sahilmgandhi	18:6a4db94011d3	1307	* \| \| \|Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number.
sahilmgandhi	18:6a4db94011d3	1308	* \| \| \|A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]).
sahilmgandhi	18:6a4db94011d3	1309	* \| \| \|The Status Interrupt is cleared by reading the Status Register.
sahilmgandhi	18:6a4db94011d3	1310	*/
sahilmgandhi	18:6a4db94011d3	1311	__IO uint32_t IIDR;
sahilmgandhi	18:6a4db94011d3	1312
sahilmgandhi	18:6a4db94011d3	1313	/**
sahilmgandhi	18:6a4db94011d3	1314	* CAN_TEST
sahilmgandhi	18:6a4db94011d3	1315	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1316	* Offset: 0x14 Test Register (Register Map Note 1)
sahilmgandhi	18:6a4db94011d3	1317	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1318	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1319	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1320	* \|[0:1] \|Res \|Reserved
sahilmgandhi	18:6a4db94011d3	1321	* \| \| \|There are reserved bits.
sahilmgandhi	18:6a4db94011d3	1322	* \| \| \|These bits are always read as '0' and must always be written with '0'.
sahilmgandhi	18:6a4db94011d3	1323	* \|[2] \|Basic \|Basic Mode
sahilmgandhi	18:6a4db94011d3	1324	* \| \| \|0 = Basic Mode disabled.
sahilmgandhi	18:6a4db94011d3	1325	* \| \| \|1= IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.
sahilmgandhi	18:6a4db94011d3	1326	* \|[3] \|Silent \|Silent Mode
sahilmgandhi	18:6a4db94011d3	1327	* \| \| \|0 = Normal operation.
sahilmgandhi	18:6a4db94011d3	1328	* \| \| \|1 = The module is in Silent Mode.
sahilmgandhi	18:6a4db94011d3	1329	* \|[4] \|LBack \|Loop Back Mode Enable Control
sahilmgandhi	18:6a4db94011d3	1330	* \| \| \|0 = Loop Back Mode is disabled.
sahilmgandhi	18:6a4db94011d3	1331	* \| \| \|1 = Loop Back Mode is enabled.
sahilmgandhi	18:6a4db94011d3	1332	* \|[5:6] \|Tx10 \|Tx[1:0]: Control Of CAN_TX Pin
sahilmgandhi	18:6a4db94011d3	1333	* \| \| \|00 = Reset value, CAN_TX pin is controlled by the CAN Core.
sahilmgandhi	18:6a4db94011d3	1334	* \| \| \|01 = Sample Point can be monitored at CAN_TX pin.
sahilmgandhi	18:6a4db94011d3	1335	* \| \| \|10 = CAN_TX pin drives a dominant ('0') value.
sahilmgandhi	18:6a4db94011d3	1336	* \| \| \|11 = CAN_TX pin drives a recessive ('1') value.
sahilmgandhi	18:6a4db94011d3	1337	* \|[7] \|Rx \|Monitors The Actual Value Of CAN_RX Pin (Read Only)
sahilmgandhi	18:6a4db94011d3	1338	* \| \| \|0 = The CAN bus is dominant (CAN_RX = '0').
sahilmgandhi	18:6a4db94011d3	1339	* \| \| \|1 = The CAN bus is recessive (CAN_RX = '1').
sahilmgandhi	18:6a4db94011d3	1340	*/
sahilmgandhi	18:6a4db94011d3	1341	__IO uint32_t TEST;
sahilmgandhi	18:6a4db94011d3	1342
sahilmgandhi	18:6a4db94011d3	1343	/**
sahilmgandhi	18:6a4db94011d3	1344	* CAN_BRPE
sahilmgandhi	18:6a4db94011d3	1345	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1346	* Offset: 0x18 Baud Rate Prescaler Extension Register
sahilmgandhi	18:6a4db94011d3	1347	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1348	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1349	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1350	* \|[0:3] \|BRPE \|BRPE: Baud Rate Prescaler Extension
sahilmgandhi	18:6a4db94011d3	1351	* \| \| \|0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023.
sahilmgandhi	18:6a4db94011d3	1352	* \| \| \|The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used.
sahilmgandhi	18:6a4db94011d3	1353	*/
sahilmgandhi	18:6a4db94011d3	1354	__IO uint32_t BRPE;
sahilmgandhi	18:6a4db94011d3	1355
sahilmgandhi	18:6a4db94011d3	1356	__I uint32_t RESERVE0[1];
sahilmgandhi	18:6a4db94011d3	1357
sahilmgandhi	18:6a4db94011d3	1358	__IO CAN_IF_T IF[2];
sahilmgandhi	18:6a4db94011d3	1359
sahilmgandhi	18:6a4db94011d3	1360	__I uint32_t RESERVE1[8];
sahilmgandhi	18:6a4db94011d3	1361
sahilmgandhi	18:6a4db94011d3	1362	/**
sahilmgandhi	18:6a4db94011d3	1363	* CAN_TXREQ1
sahilmgandhi	18:6a4db94011d3	1364	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1365	* Offset: 0x100 Transmission Request Register 1
sahilmgandhi	18:6a4db94011d3	1366	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1367	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1368	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1369	* \|[0:15] \|TxRqst161 \|Transmission Request Bits 16-1 (Of All Message Objects)
sahilmgandhi	18:6a4db94011d3	1370	* \| \| \|0 = This Message Object is not waiting for transmission.
sahilmgandhi	18:6a4db94011d3	1371	* \| \| \|1 = The transmission of this Message Object is requested and is not yet done.
sahilmgandhi	18:6a4db94011d3	1372	* \| \| \|These bits are read only.
sahilmgandhi	18:6a4db94011d3	1373	*/
sahilmgandhi	18:6a4db94011d3	1374	__IO uint32_t TXREQ1;
sahilmgandhi	18:6a4db94011d3	1375
sahilmgandhi	18:6a4db94011d3	1376	/**
sahilmgandhi	18:6a4db94011d3	1377	* CAN_TXREQ2
sahilmgandhi	18:6a4db94011d3	1378	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1379	* Offset: 0x104 Transmission Request Register 2
sahilmgandhi	18:6a4db94011d3	1380	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1381	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1382	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1383	* \|[0:15] \|TxRqst3217\|Transmission Request Bits 32-17 (Of All Message Objects)
sahilmgandhi	18:6a4db94011d3	1384	* \| \| \|0 = This Message Object is not waiting for transmission.
sahilmgandhi	18:6a4db94011d3	1385	* \| \| \|1 = The transmission of this Message Object is requested and is not yet done.
sahilmgandhi	18:6a4db94011d3	1386	* \| \| \|These bits are read only.
sahilmgandhi	18:6a4db94011d3	1387	*/
sahilmgandhi	18:6a4db94011d3	1388	__IO uint32_t TXREQ2;
sahilmgandhi	18:6a4db94011d3	1389
sahilmgandhi	18:6a4db94011d3	1390	__I uint32_t RESERVE2[6];
sahilmgandhi	18:6a4db94011d3	1391
sahilmgandhi	18:6a4db94011d3	1392	/**
sahilmgandhi	18:6a4db94011d3	1393	* CAN_NDAT1
sahilmgandhi	18:6a4db94011d3	1394	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1395	* Offset: 0x120 New Data Register 1
sahilmgandhi	18:6a4db94011d3	1396	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1397	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1398	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1399	* \|[0:15] \|NewData161\|New Data Bits 16-1 (Of All Message Objects)
sahilmgandhi	18:6a4db94011d3	1400	* \| \| \|0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
sahilmgandhi	18:6a4db94011d3	1401	* \| \| \|1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
sahilmgandhi	18:6a4db94011d3	1402	*/
sahilmgandhi	18:6a4db94011d3	1403	__IO uint32_t NDAT1;
sahilmgandhi	18:6a4db94011d3	1404
sahilmgandhi	18:6a4db94011d3	1405	/**
sahilmgandhi	18:6a4db94011d3	1406	* CAN_NDAT2
sahilmgandhi	18:6a4db94011d3	1407	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1408	* Offset: 0x124 New Data Register 2
sahilmgandhi	18:6a4db94011d3	1409	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1410	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1411	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1412	* \|[0:15] \|NewData3217\|New Data Bits 32-17 (Of All Message Objects)
sahilmgandhi	18:6a4db94011d3	1413	* \| \| \|0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
sahilmgandhi	18:6a4db94011d3	1414	* \| \| \|1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
sahilmgandhi	18:6a4db94011d3	1415	*/
sahilmgandhi	18:6a4db94011d3	1416	__IO uint32_t NDAT2;
sahilmgandhi	18:6a4db94011d3	1417
sahilmgandhi	18:6a4db94011d3	1418	__I uint32_t RESERVE3[6];
sahilmgandhi	18:6a4db94011d3	1419
sahilmgandhi	18:6a4db94011d3	1420	/**
sahilmgandhi	18:6a4db94011d3	1421	* CAN_IPND1
sahilmgandhi	18:6a4db94011d3	1422	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1423	* Offset: 0x140 Interrupt Pending Register 1
sahilmgandhi	18:6a4db94011d3	1424	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1425	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1426	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1427	* \|[0:15] \|IntPnd161 \|Interrupt Pending Bits 16-1 (Of All Message Objects)
sahilmgandhi	18:6a4db94011d3	1428	* \| \| \|0 = This message object is not the source of an interrupt.
sahilmgandhi	18:6a4db94011d3	1429	* \| \| \|1 = This message object is the source of an interrupt.
sahilmgandhi	18:6a4db94011d3	1430	*/
sahilmgandhi	18:6a4db94011d3	1431	__IO uint32_t IPND1;
sahilmgandhi	18:6a4db94011d3	1432
sahilmgandhi	18:6a4db94011d3	1433	/**
sahilmgandhi	18:6a4db94011d3	1434	* CAN_IPND2
sahilmgandhi	18:6a4db94011d3	1435	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1436	* Offset: 0x144 Interrupt Pending Register 2
sahilmgandhi	18:6a4db94011d3	1437	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1438	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1439	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1440	* \|[0:15] \|IntPnd3217\|Interrupt Pending Bits 32-17(Of All Message Objects)
sahilmgandhi	18:6a4db94011d3	1441	* \| \| \|0 = This message object is not the source of an interrupt.
sahilmgandhi	18:6a4db94011d3	1442	* \| \| \|1 = This message object is the source of an interrupt.
sahilmgandhi	18:6a4db94011d3	1443	*/
sahilmgandhi	18:6a4db94011d3	1444	__IO uint32_t IPND2;
sahilmgandhi	18:6a4db94011d3	1445
sahilmgandhi	18:6a4db94011d3	1446	__I uint32_t RESERVE4[6];
sahilmgandhi	18:6a4db94011d3	1447
sahilmgandhi	18:6a4db94011d3	1448	/**
sahilmgandhi	18:6a4db94011d3	1449	* CAN_MVLD1
sahilmgandhi	18:6a4db94011d3	1450	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1451	* Offset: 0x160 Message Valid Register 1
sahilmgandhi	18:6a4db94011d3	1452	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1453	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1454	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1455	* \|[0:15] \|MsgVal161 \|Message Valid Bits 16-1 (Of All Message Objects) (Read Only)
sahilmgandhi	18:6a4db94011d3	1456	* \| \| \|0 = This Message Object is ignored by the Message Handler.
sahilmgandhi	18:6a4db94011d3	1457	* \| \| \|1 = This Message Object is configured and should be considered by the Message Handler.
sahilmgandhi	18:6a4db94011d3	1458	* \| \| \|Ex.
sahilmgandhi	18:6a4db94011d3	1459	* \| \| \|CAN_MVLD1[0] means Message object No.1 is valid or not.
sahilmgandhi	18:6a4db94011d3	1460	* \| \| \|If CAN_MVLD1[0] is set, message object No.1 is configured.
sahilmgandhi	18:6a4db94011d3	1461	*/
sahilmgandhi	18:6a4db94011d3	1462	__IO uint32_t MVLD1;
sahilmgandhi	18:6a4db94011d3	1463
sahilmgandhi	18:6a4db94011d3	1464	/**
sahilmgandhi	18:6a4db94011d3	1465	* CAN_MVLD2
sahilmgandhi	18:6a4db94011d3	1466	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1467	* Offset: 0x164 Message Valid Register 2
sahilmgandhi	18:6a4db94011d3	1468	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1469	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1470	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1471	* \|[0:15] \|MsgVal3217\|Message Valid Bits 32-17 (Of All Message Objects) (Read Only)
sahilmgandhi	18:6a4db94011d3	1472	* \| \| \|0 = This Message Object is ignored by the Message Handler.
sahilmgandhi	18:6a4db94011d3	1473	* \| \| \|1 = This Message Object is configured and should be considered by the Message Handler.
sahilmgandhi	18:6a4db94011d3	1474	* \| \| \|Ex.CAN_MVLD2[15] means Message object No.32 is valid or not.
sahilmgandhi	18:6a4db94011d3	1475	* \| \| \|If CAN_MVLD2[15] is set, message object No.32 is configured.
sahilmgandhi	18:6a4db94011d3	1476	*/
sahilmgandhi	18:6a4db94011d3	1477	__IO uint32_t MVLD2;
sahilmgandhi	18:6a4db94011d3	1478
sahilmgandhi	18:6a4db94011d3	1479	/**
sahilmgandhi	18:6a4db94011d3	1480	* CAN_WU_EN
sahilmgandhi	18:6a4db94011d3	1481	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1482	* Offset: 0x168 Wake-up Enable Register
sahilmgandhi	18:6a4db94011d3	1483	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1484	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1485	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1486	* \|[0] \|WAKUP_EN \|Wake-Up Enable Control
sahilmgandhi	18:6a4db94011d3	1487	* \| \| \|0 = The wake-up function Disabled.
sahilmgandhi	18:6a4db94011d3	1488	* \| \| \|1 = The wake-up function Enabled.
sahilmgandhi	18:6a4db94011d3	1489	* \| \| \|Note: User can wake-up system when there is a falling edge in the CAN_Rx pin.
sahilmgandhi	18:6a4db94011d3	1490	*/
sahilmgandhi	18:6a4db94011d3	1491	__IO uint32_t WU_EN;
sahilmgandhi	18:6a4db94011d3	1492
sahilmgandhi	18:6a4db94011d3	1493	/**
sahilmgandhi	18:6a4db94011d3	1494	* CAN_WU_STATUS
sahilmgandhi	18:6a4db94011d3	1495	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1496	* Offset: 0x16C Wake-up Status Register
sahilmgandhi	18:6a4db94011d3	1497	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1498	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1499	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1500	* \|[0] \|WAKUP_STS \|Wake-Up Status
sahilmgandhi	18:6a4db94011d3	1501	* \| \| \|0 = No wake-up event occurred.
sahilmgandhi	18:6a4db94011d3	1502	* \| \| \|1 = Wake-up event occurred.
sahilmgandhi	18:6a4db94011d3	1503	* \| \| \|Note: This bit can be cleared by writing '0'.
sahilmgandhi	18:6a4db94011d3	1504	*/
sahilmgandhi	18:6a4db94011d3	1505	__IO uint32_t WU_STATUS;
sahilmgandhi	18:6a4db94011d3	1506	} CAN_T;
sahilmgandhi	18:6a4db94011d3	1507
sahilmgandhi	18:6a4db94011d3	1508	/**
sahilmgandhi	18:6a4db94011d3	1509	@addtogroup CAN_CONST CAN Bit Field Definition
sahilmgandhi	18:6a4db94011d3	1510	Constant Definitions for CAN Controller
sahilmgandhi	18:6a4db94011d3	1511	@{ */
sahilmgandhi	18:6a4db94011d3	1512
sahilmgandhi	18:6a4db94011d3	1513	#define CAN_CON_TEST_Pos 7 /!< CAN CON: TEST Position /
sahilmgandhi	18:6a4db94011d3	1514	#define CAN_CON_TEST_Msk (1ul << CAN_CON_TEST_Pos) /!< CAN CON: TEST Mask /
sahilmgandhi	18:6a4db94011d3	1515
sahilmgandhi	18:6a4db94011d3	1516	#define CAN_CON_CCE_Pos 6 /!< CAN CON: CCE Position /
sahilmgandhi	18:6a4db94011d3	1517	#define CAN_CON_CCE_Msk (1ul << CAN_CON_CCE_Pos) /!< CAN CON: CCE Mask /
sahilmgandhi	18:6a4db94011d3	1518
sahilmgandhi	18:6a4db94011d3	1519	#define CAN_CON_DAR_Pos 5 /!< CAN CON: DAR Position /
sahilmgandhi	18:6a4db94011d3	1520	#define CAN_CON_DAR_Msk (1ul << CAN_CON_DAR_Pos) /!< CAN CON: DAR Mask /
sahilmgandhi	18:6a4db94011d3	1521
sahilmgandhi	18:6a4db94011d3	1522	#define CAN_CON_EIE_Pos 3 /!< CAN CON: EIE Position /
sahilmgandhi	18:6a4db94011d3	1523	#define CAN_CON_EIE_Msk (1ul << CAN_CON_EIE_Pos) /!< CAN CON: EIE Mask /
sahilmgandhi	18:6a4db94011d3	1524
sahilmgandhi	18:6a4db94011d3	1525	#define CAN_CON_SIE_Pos 2 /!< CAN CON: SIE Position /
sahilmgandhi	18:6a4db94011d3	1526	#define CAN_CON_SIE_Msk (1ul << CAN_CON_SIE_Pos) /!< CAN CON: SIE Mask /
sahilmgandhi	18:6a4db94011d3	1527
sahilmgandhi	18:6a4db94011d3	1528	#define CAN_CON_IE_Pos 1 /!< CAN CON: IE Position /
sahilmgandhi	18:6a4db94011d3	1529	#define CAN_CON_IE_Msk (1ul << CAN_CON_IE_Pos) /!< CAN CON: IE Mask /
sahilmgandhi	18:6a4db94011d3	1530
sahilmgandhi	18:6a4db94011d3	1531	#define CAN_CON_INIT_Pos 0 /!< CAN CON: INIT Position /
sahilmgandhi	18:6a4db94011d3	1532	#define CAN_CON_INIT_Msk (1ul << CAN_CON_INIT_Pos) /!< CAN CON: INIT Mask /
sahilmgandhi	18:6a4db94011d3	1533
sahilmgandhi	18:6a4db94011d3	1534	#define CAN_STATUS_BOFF_Pos 7 /!< CAN STATUS: BOFF Position /
sahilmgandhi	18:6a4db94011d3	1535	#define CAN_STATUS_BOFF_Msk (1ul << CAN_STATUS_BOFF_Pos) /!< CAN STATUS: BOFF Mask /
sahilmgandhi	18:6a4db94011d3	1536
sahilmgandhi	18:6a4db94011d3	1537	#define CAN_STATUS_EWARN_Pos 6 /!< CAN STATUS: EWARN Position /
sahilmgandhi	18:6a4db94011d3	1538	#define CAN_STATUS_EWARN_Msk (1ul << CAN_STATUS_EWARN_Pos) /!< CAN STATUS: EWARN Mask /
sahilmgandhi	18:6a4db94011d3	1539
sahilmgandhi	18:6a4db94011d3	1540	#define CAN_STATUS_EPASS_Pos 5 /!< CAN STATUS: EPASS Position /
sahilmgandhi	18:6a4db94011d3	1541	#define CAN_STATUS_EPASS_Msk (1ul << CAN_STATUS_EPASS_Pos) /!< CAN STATUS: EPASS Mask /
sahilmgandhi	18:6a4db94011d3	1542
sahilmgandhi	18:6a4db94011d3	1543	#define CAN_STATUS_RXOK_Pos 4 /!< CAN STATUS: RXOK Position /
sahilmgandhi	18:6a4db94011d3	1544	#define CAN_STATUS_RXOK_Msk (1ul << CAN_STATUS_RXOK_Pos) /!< CAN STATUS: RXOK Mask /
sahilmgandhi	18:6a4db94011d3	1545
sahilmgandhi	18:6a4db94011d3	1546	#define CAN_STATUS_TXOK_Pos 3 /!< CAN STATUS: TXOK Position /
sahilmgandhi	18:6a4db94011d3	1547	#define CAN_STATUS_TXOK_Msk (1ul << CAN_STATUS_TXOK_Pos) /!< CAN STATUS: TXOK Mask /
sahilmgandhi	18:6a4db94011d3	1548
sahilmgandhi	18:6a4db94011d3	1549	#define CAN_STATUS_LEC_Pos 0 /!< CAN STATUS: LEC Position /
sahilmgandhi	18:6a4db94011d3	1550	#define CAN_STATUS_LEC_Msk (0x3ul << CAN_STATUS_LEC_Pos) /!< CAN STATUS: LEC Mask /
sahilmgandhi	18:6a4db94011d3	1551
sahilmgandhi	18:6a4db94011d3	1552	#define CAN_ERR_RP_Pos 15 /!< CAN ERR: RP Position /
sahilmgandhi	18:6a4db94011d3	1553	#define CAN_ERR_RP_Msk (1ul << CAN_ERR_RP_Pos) /!< CAN ERR: RP Mask /
sahilmgandhi	18:6a4db94011d3	1554
sahilmgandhi	18:6a4db94011d3	1555	#define CAN_ERR_REC_Pos 8 /!< CAN ERR: REC Position /
sahilmgandhi	18:6a4db94011d3	1556	#define CAN_ERR_REC_Msk (0x7Ful << CAN_ERR_REC_Pos) /!< CAN ERR: REC Mask /
sahilmgandhi	18:6a4db94011d3	1557
sahilmgandhi	18:6a4db94011d3	1558	#define CAN_ERR_TEC_Pos 0 /!< CAN ERR: TEC Position /
sahilmgandhi	18:6a4db94011d3	1559	#define CAN_ERR_TEC_Msk (0xFFul << CAN_ERR_TEC_Pos) /!< CAN ERR: TEC Mask /
sahilmgandhi	18:6a4db94011d3	1560
sahilmgandhi	18:6a4db94011d3	1561	#define CAN_BTIME_TSEG2_Pos 12 /!< CAN BTIME: TSEG2 Position /
sahilmgandhi	18:6a4db94011d3	1562	#define CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos) /!< CAN BTIME: TSEG2 Mask /
sahilmgandhi	18:6a4db94011d3	1563
sahilmgandhi	18:6a4db94011d3	1564	#define CAN_BTIME_TSEG1_Pos 8 /!< CAN BTIME: TSEG1 Position /
sahilmgandhi	18:6a4db94011d3	1565	#define CAN_BTIME_TSEG1_Msk (0xFul << CAN_BTIME_TSEG1_Pos) /!< CAN BTIME: TSEG1 Mask /
sahilmgandhi	18:6a4db94011d3	1566
sahilmgandhi	18:6a4db94011d3	1567	#define CAN_BTIME_SJW_Pos 6 /!< CAN BTIME: SJW Position /
sahilmgandhi	18:6a4db94011d3	1568	#define CAN_BTIME_SJW_Msk (0x3ul << CAN_BTIME_SJW_Pos) /!< CAN BTIME: SJW Mask /
sahilmgandhi	18:6a4db94011d3	1569
sahilmgandhi	18:6a4db94011d3	1570	#define CAN_BTIME_BRP_Pos 0 /!< CAN BTIME: BRP Position /
sahilmgandhi	18:6a4db94011d3	1571	#define CAN_BTIME_BRP_Msk (0x3Ful << CAN_BTIME_BRP_Pos) /!< CAN BTIME: BRP Mask /
sahilmgandhi	18:6a4db94011d3	1572
sahilmgandhi	18:6a4db94011d3	1573	#define CAN_IIDR_INTID_Pos 0 /!< CAN IIDR: INTID Position /
sahilmgandhi	18:6a4db94011d3	1574	#define CAN_IIDR_INTID_Msk (0xFFFFul << CAN_IIDR_INTID_Pos) /!< CAN IIDR: INTID Mask /
sahilmgandhi	18:6a4db94011d3	1575
sahilmgandhi	18:6a4db94011d3	1576	#define CAN_TEST_RX_Pos 7 /!< CAN TEST: RX Position /
sahilmgandhi	18:6a4db94011d3	1577	#define CAN_TEST_RX_Msk (1ul << CAN_TEST_RX_Pos) /!< CAN TEST: RX Mask /
sahilmgandhi	18:6a4db94011d3	1578
sahilmgandhi	18:6a4db94011d3	1579	#define CAN_TEST_TX_Pos 5 /!< CAN TEST: TX Position /
sahilmgandhi	18:6a4db94011d3	1580	#define CAN_TEST_TX_Msk (0x3ul << CAN_TEST_TX_Pos) /!< CAN TEST: TX Mask /
sahilmgandhi	18:6a4db94011d3	1581
sahilmgandhi	18:6a4db94011d3	1582	#define CAN_TEST_LBACK_Pos 4 /!< CAN TEST: LBACK Position /
sahilmgandhi	18:6a4db94011d3	1583	#define CAN_TEST_LBACK_Msk (1ul << CAN_TEST_LBACK_Pos) /!< CAN TEST: LBACK Mask /
sahilmgandhi	18:6a4db94011d3	1584
sahilmgandhi	18:6a4db94011d3	1585	#define CAN_TEST_SILENT_Pos 3 /!< CAN TEST: Silent Position /
sahilmgandhi	18:6a4db94011d3	1586	#define CAN_TEST_SILENT_Msk (1ul << CAN_TEST_SILENT_Pos) /!< CAN TEST: Silent Mask /
sahilmgandhi	18:6a4db94011d3	1587
sahilmgandhi	18:6a4db94011d3	1588	#define CAN_TEST_BASIC_Pos 2 /!< CAN TEST: Basic Position /
sahilmgandhi	18:6a4db94011d3	1589	#define CAN_TEST_BASIC_Msk (1ul << CAN_TEST_BASIC_Pos) /!< CAN TEST: Basic Mask /
sahilmgandhi	18:6a4db94011d3	1590
sahilmgandhi	18:6a4db94011d3	1591	#define CAN_BRPE_BRPE_Pos 0 /!< CAN BRPE: BRPE Position /
sahilmgandhi	18:6a4db94011d3	1592	#define CAN_BRPE_BRPE_Msk (0xFul << CAN_BRPE_BRPE_Pos) /!< CAN BRPE: BRPE Mask /
sahilmgandhi	18:6a4db94011d3	1593
sahilmgandhi	18:6a4db94011d3	1594	#define CAN_IF_CREQ_BUSY_Pos 15 /!< CAN IFnCREQ: BUSY Position /
sahilmgandhi	18:6a4db94011d3	1595	#define CAN_IF_CREQ_BUSY_Msk (1ul << CAN_IF_CREQ_BUSY_Pos) /!< CAN IFnCREQ: BUSY Mask /
sahilmgandhi	18:6a4db94011d3	1596
sahilmgandhi	18:6a4db94011d3	1597	#define CAN_IF_CREQ_MSGNUM_Pos 0 /!< CAN IFnCREQ: MSGNUM Position /
sahilmgandhi	18:6a4db94011d3	1598	#define CAN_IF_CREQ_MSGNUM_Msk (0x3Ful << CAN_IF_CREQ_MSGNUM_Pos) /!< CAN IFnCREQ: MSGNUM Mask /
sahilmgandhi	18:6a4db94011d3	1599
sahilmgandhi	18:6a4db94011d3	1600	#define CAN_IF_CMASK_WRRD_Pos 7 /!< CAN IFnCMASK: WRRD Position /
sahilmgandhi	18:6a4db94011d3	1601	#define CAN_IF_CMASK_WRRD_Msk (1ul << CAN_IF_CMASK_WRRD_Pos) /!< CAN IFnCMASK: WRRD Mask /
sahilmgandhi	18:6a4db94011d3	1602
sahilmgandhi	18:6a4db94011d3	1603	#define CAN_IF_CMASK_MASK_Pos 6 /!< CAN IFnCMASK: MASK Position /
sahilmgandhi	18:6a4db94011d3	1604	#define CAN_IF_CMASK_MASK_Msk (1ul << CAN_IF_CMASK_MASK_Pos) /!< CAN IFnCMASK: MASK Mask /
sahilmgandhi	18:6a4db94011d3	1605
sahilmgandhi	18:6a4db94011d3	1606	#define CAN_IF_CMASK_ARB_Pos 5 /!< CAN IFnCMASK: ARB Position /
sahilmgandhi	18:6a4db94011d3	1607	#define CAN_IF_CMASK_ARB_Msk (1ul << CAN_IF_CMASK_ARB_Pos) /!< CAN IFnCMASK: ARB Mask /
sahilmgandhi	18:6a4db94011d3	1608
sahilmgandhi	18:6a4db94011d3	1609	#define CAN_IF_CMASK_CONTROL_Pos 4 /!< CAN IFnCMASK: CONTROL Position /
sahilmgandhi	18:6a4db94011d3	1610	#define CAN_IF_CMASK_CONTROL_Msk (1ul << CAN_IF_CMASK_CONTROL_Pos) /!< CAN IFnCMASK: CONTROL Mask /
sahilmgandhi	18:6a4db94011d3	1611
sahilmgandhi	18:6a4db94011d3	1612	#define CAN_IF_CMASK_CLRINTPND_Pos 3 /!< CAN IFnCMASK: CLRINTPND Position /
sahilmgandhi	18:6a4db94011d3	1613	#define CAN_IF_CMASK_CLRINTPND_Msk (1ul << CAN_IF_CMASK_CLRINTPND_Pos) /!< CAN IFnCMASK: CLRINTPND Mask /
sahilmgandhi	18:6a4db94011d3	1614
sahilmgandhi	18:6a4db94011d3	1615	#define CAN_IF_CMASK_TXRQSTNEWDAT_Pos 2 /!< CAN IFnCMASK: TXRQSTNEWDAT Position /
sahilmgandhi	18:6a4db94011d3	1616	#define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) /!< CAN IFnCMASK: TXRQSTNEWDAT Mask /
sahilmgandhi	18:6a4db94011d3	1617
sahilmgandhi	18:6a4db94011d3	1618	#define CAN_IF_CMASK_DATAA_Pos 1 /!< CAN IFnCMASK: DATAA Position /
sahilmgandhi	18:6a4db94011d3	1619	#define CAN_IF_CMASK_DATAA_Msk (1ul << CAN_IF_CMASK_DATAA_Pos) /!< CAN IFnCMASK: DATAA Mask /
sahilmgandhi	18:6a4db94011d3	1620
sahilmgandhi	18:6a4db94011d3	1621	#define CAN_IF_CMASK_DATAB_Pos 0 /!< CAN IFnCMASK: DATAB Position /
sahilmgandhi	18:6a4db94011d3	1622	#define CAN_IF_CMASK_DATAB_Msk (1ul << CAN_IF_CMASK_DATAB_Pos) /!< CAN IFnCMASK: DATAB Mask /
sahilmgandhi	18:6a4db94011d3	1623
sahilmgandhi	18:6a4db94011d3	1624	#define CAN_IF_MASK1_MSK_Pos 0 /!< CAN IFnMASK1: MSK Position /
sahilmgandhi	18:6a4db94011d3	1625	#define CAN_IF_MASK1_MSK_Msk (0xFFul << CAN_IF_MASK1_MSK_Pos) /!< CAN IFnMASK1: MSK Mask /
sahilmgandhi	18:6a4db94011d3	1626
sahilmgandhi	18:6a4db94011d3	1627	#define CAN_IF_MASK2_MXTD_Pos 15 /!< CAN IFnMASK2: MXTD Position /
sahilmgandhi	18:6a4db94011d3	1628	#define CAN_IF_MASK2_MXTD_Msk (1ul << CAN_IF_MASK2_MXTD_Pos) /!< CAN IFnMASK2: MXTD Mask /
sahilmgandhi	18:6a4db94011d3	1629
sahilmgandhi	18:6a4db94011d3	1630	#define CAN_IF_MASK2_MDIR_Pos 14 /!< CAN IFnMASK2: MDIR Position /
sahilmgandhi	18:6a4db94011d3	1631	#define CAN_IF_MASK2_MDIR_Msk (1ul << CAN_IF_MASK2_MDIR_Pos) /!< CAN IFnMASK2: MDIR Mask /
sahilmgandhi	18:6a4db94011d3	1632
sahilmgandhi	18:6a4db94011d3	1633	#define CAN_IF_MASK2_MSK_Pos 0 /!< CAN IFnMASK2: MSK Position /
sahilmgandhi	18:6a4db94011d3	1634	#define CAN_IF_MASK2_MSK_Msk (0x1FFul << CAN_IF_MASK2_MSK_Pos) /!< CAN IFnMASK2: MSK Mask /
sahilmgandhi	18:6a4db94011d3	1635
sahilmgandhi	18:6a4db94011d3	1636	#define CAN_IF_ARB1_ID_Pos 0 /!< CAN IFnARB1: ID Position /
sahilmgandhi	18:6a4db94011d3	1637	#define CAN_IF_ARB1_ID_Msk (0xFFFFul << CAN_IF_ARB1_ID_Pos) /!< CAN IFnARB1: ID Mask /
sahilmgandhi	18:6a4db94011d3	1638
sahilmgandhi	18:6a4db94011d3	1639	#define CAN_IF_ARB2_MSGVAL_Pos 15 /!< CAN IFnARB2: MSGVAL Position /
sahilmgandhi	18:6a4db94011d3	1640	#define CAN_IF_ARB2_MSGVAL_Msk (1ul << CAN_IF_ARB2_MSGVAL_Pos) /!< CAN IFnARB2: MSGVAL Mask /
sahilmgandhi	18:6a4db94011d3	1641
sahilmgandhi	18:6a4db94011d3	1642	#define CAN_IF_ARB2_XTD_Pos 14 /!< CAN IFnARB2: XTD Position /
sahilmgandhi	18:6a4db94011d3	1643	#define CAN_IF_ARB2_XTD_Msk (1ul << CAN_IF_ARB2_XTD_Pos) /!< CAN IFnARB2: XTD Mask /
sahilmgandhi	18:6a4db94011d3	1644
sahilmgandhi	18:6a4db94011d3	1645	#define CAN_IF_ARB2_DIR_Pos 13 /!< CAN IFnARB2: DIR Position /
sahilmgandhi	18:6a4db94011d3	1646	#define CAN_IF_ARB2_DIR_Msk (1ul << CAN_IF_ARB2_DIR_Pos) /!< CAN IFnARB2: DIR Mask /
sahilmgandhi	18:6a4db94011d3	1647
sahilmgandhi	18:6a4db94011d3	1648	#define CAN_IF_ARB2_ID_Pos 0 /!< CAN IFnARB2: ID Position /
sahilmgandhi	18:6a4db94011d3	1649	#define CAN_IF_ARB2_ID_Msk (0x1FFFul << CAN_IF_ARB2_ID_Pos) /!< CAN IFnARB2: ID Mask /
sahilmgandhi	18:6a4db94011d3	1650
sahilmgandhi	18:6a4db94011d3	1651	#define CAN_IF_MCON_NEWDAT_Pos 15 /!< CAN IFnMCON: NEWDAT Position /
sahilmgandhi	18:6a4db94011d3	1652	#define CAN_IF_MCON_NEWDAT_Msk (1ul << CAN_IF_MCON_NEWDAT_Pos) /!< CAN IFnMCON: NEWDAT Mask /
sahilmgandhi	18:6a4db94011d3	1653
sahilmgandhi	18:6a4db94011d3	1654	#define CAN_IF_MCON_MSGLST_Pos 14 /!< CAN IFnMCON: MSGLST Position /
sahilmgandhi	18:6a4db94011d3	1655	#define CAN_IF_MCON_MSGLST_Msk (1ul << CAN_IF_MCON_MSGLST_Pos) /!< CAN IFnMCON: MSGLST Mask /
sahilmgandhi	18:6a4db94011d3	1656
sahilmgandhi	18:6a4db94011d3	1657	#define CAN_IF_MCON_INTPND_Pos 13 /!< CAN IFnMCON: INTPND Position /
sahilmgandhi	18:6a4db94011d3	1658	#define CAN_IF_MCON_INTPND_Msk (1ul << CAN_IF_MCON_INTPND_Pos) /!< CAN IFnMCON: INTPND Mask /
sahilmgandhi	18:6a4db94011d3	1659
sahilmgandhi	18:6a4db94011d3	1660	#define CAN_IF_MCON_UMASK_Pos 12 /!< CAN IFnMCON: UMASK Position /
sahilmgandhi	18:6a4db94011d3	1661	#define CAN_IF_MCON_UMASK_Msk (1ul << CAN_IF_MCON_UMASK_Pos) /!< CAN IFnMCON: UMASK Mask /
sahilmgandhi	18:6a4db94011d3	1662
sahilmgandhi	18:6a4db94011d3	1663	#define CAN_IF_MCON_TXIE_Pos 11 /!< CAN IFnMCON: TXIE Position /
sahilmgandhi	18:6a4db94011d3	1664	#define CAN_IF_MCON_TXIE_Msk (1ul << CAN_IF_MCON_TXIE_Pos) /!< CAN IFnMCON: TXIE Mask /
sahilmgandhi	18:6a4db94011d3	1665
sahilmgandhi	18:6a4db94011d3	1666	#define CAN_IF_MCON_RXIE_Pos 10 /!< CAN IFnMCON: RXIE Position /
sahilmgandhi	18:6a4db94011d3	1667	#define CAN_IF_MCON_RXIE_Msk (1ul << CAN_IF_MCON_RXIE_Pos) /!< CAN IFnMCON: RXIE Mask /
sahilmgandhi	18:6a4db94011d3	1668
sahilmgandhi	18:6a4db94011d3	1669	#define CAN_IF_MCON_RMTEN_Pos 9 /!< CAN IFnMCON: RMTEN Position /
sahilmgandhi	18:6a4db94011d3	1670	#define CAN_IF_MCON_RMTEN_Msk (1ul << CAN_IF_MCON_RMTEN_Pos) /!< CAN IFnMCON: RMTEN Mask /
sahilmgandhi	18:6a4db94011d3	1671
sahilmgandhi	18:6a4db94011d3	1672	#define CAN_IF_MCON_TXRQST_Pos 8 /!< CAN IFnMCON: TXRQST Position /
sahilmgandhi	18:6a4db94011d3	1673	#define CAN_IF_MCON_TXRQST_Msk (1ul << CAN_IF_MCON_TXRQST_Pos) /!< CAN IFnMCON: TXRQST Mask /
sahilmgandhi	18:6a4db94011d3	1674
sahilmgandhi	18:6a4db94011d3	1675	#define CAN_IF_MCON_EOB_Pos 7 /!< CAN IFnMCON: EOB Position /
sahilmgandhi	18:6a4db94011d3	1676	#define CAN_IF_MCON_EOB_Msk (1ul << CAN_IF_MCON_EOB_Pos) /!< CAN IFnMCON: EOB Mask /
sahilmgandhi	18:6a4db94011d3	1677
sahilmgandhi	18:6a4db94011d3	1678	#define CAN_IF_MCON_DLC_Pos 0 /!< CAN IFnMCON: DLC Position /
sahilmgandhi	18:6a4db94011d3	1679	#define CAN_IF_MCON_DLC_Msk (0xFul << CAN_IF_MCON_DLC_Pos) /!< CAN IFnMCON: DLC Mask /
sahilmgandhi	18:6a4db94011d3	1680
sahilmgandhi	18:6a4db94011d3	1681	#define CAN_IF_DAT_A1_DATA1_Pos 8 /!< CAN IFnDATAA1: DATA1 Position /
sahilmgandhi	18:6a4db94011d3	1682	#define CAN_IF_DAT_A1_DATA1_Msk (0xFFul << CAN_IF_DAT_A1_DATA1_Pos) /!< CAN IFnDATAA1: DATA1 Mask /
sahilmgandhi	18:6a4db94011d3	1683
sahilmgandhi	18:6a4db94011d3	1684	#define CAN_IF_DAT_A1_DATA0_Pos 0 /!< CAN IFnDATAA1: DATA0 Position /
sahilmgandhi	18:6a4db94011d3	1685	#define CAN_IF_DAT_A1_DATA0_Msk (0xFFul << CAN_IF_DAT_A1_DATA0_Pos) /!< CAN IFnDATAA1: DATA0 Mask /
sahilmgandhi	18:6a4db94011d3	1686
sahilmgandhi	18:6a4db94011d3	1687	#define CAN_IF_DAT_A2_DATA3_Pos 8 /!< CAN IFnDATAA1: DATA3 Position /
sahilmgandhi	18:6a4db94011d3	1688	#define CAN_IF_DAT_A2_DATA3_Msk (0xFFul << CAN_IF_DAT_A2_DATA3_Pos) /!< CAN IFnDATAA1: DATA3 Mask /
sahilmgandhi	18:6a4db94011d3	1689
sahilmgandhi	18:6a4db94011d3	1690	#define CAN_IF_DAT_A2_DATA2_Pos 0 /!< CAN IFnDATAA1: DATA2 Position /
sahilmgandhi	18:6a4db94011d3	1691	#define CAN_IF_DAT_A2_DATA2_Msk (0xFFul << CAN_IF_DAT_A2_DATA2_Pos) /!< CAN IFnDATAA1: DATA2 Mask /
sahilmgandhi	18:6a4db94011d3	1692
sahilmgandhi	18:6a4db94011d3	1693	#define CAN_IF_DAT_B1_DATA5_Pos 8 /!< CAN IFnDATAB1: DATA5 Position /
sahilmgandhi	18:6a4db94011d3	1694	#define CAN_IF_DAT_B1_DATA5_Msk (0xFFul << CAN_IF_DAT_B1_DATA5_Pos) /!< CAN IFnDATAB1: DATA5 Mask /
sahilmgandhi	18:6a4db94011d3	1695
sahilmgandhi	18:6a4db94011d3	1696	#define CAN_IF_DAT_B1_DATA4_Pos 0 /!< CAN IFnDATAB1: DATA4 Position /
sahilmgandhi	18:6a4db94011d3	1697	#define CAN_IF_DAT_B1_DATA4_Msk (0xFFul << CAN_IF_DAT_B1_DATA4_Pos) /!< CAN IFnDATAB1: DATA4 Mask /
sahilmgandhi	18:6a4db94011d3	1698
sahilmgandhi	18:6a4db94011d3	1699	#define CAN_IF_DAT_B2_DATA7_Pos 8 /!< CAN IFnDATAB2: DATA7 Position /
sahilmgandhi	18:6a4db94011d3	1700	#define CAN_IF_DAT_B2_DATA7_Msk (0xFFul << CAN_IF_DAT_B2_DATA7_Pos) /!< CAN IFnDATAB2: DATA7 Mask /
sahilmgandhi	18:6a4db94011d3	1701
sahilmgandhi	18:6a4db94011d3	1702	#define CAN_IF_DAT_B2_DATA6_Pos 0 /!< CAN IFnDATAB2: DATA6 Position /
sahilmgandhi	18:6a4db94011d3	1703	#define CAN_IF_DAT_B2_DATA6_Msk (0xFFul << CAN_IF_DAT_B2_DATA6_Pos) /!< CAN IFnDATAB2: DATA6 Mask /
sahilmgandhi	18:6a4db94011d3	1704
sahilmgandhi	18:6a4db94011d3	1705	#define CAN_IF_TXRQST1_TXRQST_Pos 0 /!< CAN IFnTXRQST1: TXRQST Position /
sahilmgandhi	18:6a4db94011d3	1706	#define CAN_IF_TXRQST1_TXRQST_Msk (0xFFFFul << CAN_IF_TXRQST1_TXRQST_Pos) /!< CAN IFnTXRQST1: TXRQST Mask /
sahilmgandhi	18:6a4db94011d3	1707
sahilmgandhi	18:6a4db94011d3	1708	#define CAN_IF_TXRQST2_TXRQST_Pos 0 /!< CAN IFnTXRQST2: TXRQST Position /
sahilmgandhi	18:6a4db94011d3	1709	#define CAN_IF_TXRQST2_TXRQST_Msk (0xFFFFul << CAN_IF_TXRQST2_TXRQST_Pos) /!< CAN IFnTXRQST2: TXRQST Mask /
sahilmgandhi	18:6a4db94011d3	1710
sahilmgandhi	18:6a4db94011d3	1711	#define CAN_IF_NDAT1_NEWDATA_Pos 0 /!< CAN IFnNDAT1: NEWDATA Position /
sahilmgandhi	18:6a4db94011d3	1712	#define CAN_IF_NDAT1_NEWDATA_Msk (0xFFFFul << CAN_IF_NDAT1_NEWDATA_Pos) /!< CAN IFnNDAT1: NEWDATA Mask /
sahilmgandhi	18:6a4db94011d3	1713
sahilmgandhi	18:6a4db94011d3	1714	#define CAN_IF_NDAT2_NEWDATA_Pos 0 /!< CAN IFnNDAT2: NEWDATA Position /
sahilmgandhi	18:6a4db94011d3	1715	#define CAN_IF_NDAT2_NEWDATA_Msk (0xFFFFul << CAN_IF_NDAT2_NEWDATA_Pos) /!< CAN IFnNDAT2: NEWDATA Mask /
sahilmgandhi	18:6a4db94011d3	1716
sahilmgandhi	18:6a4db94011d3	1717	#define CAN_IF_IPND1_INTPND_Pos 0 /!< CAN IFnIPND1: INTPND Position /
sahilmgandhi	18:6a4db94011d3	1718	#define CAN_IF_IPND1_INTPND_Msk (0xFFFFul << CAN_IF_IPND1_INTPND_Pos) /!< CAN IFnIPND1: INTPND Mask /
sahilmgandhi	18:6a4db94011d3	1719
sahilmgandhi	18:6a4db94011d3	1720	#define CAN_IF_IPND2_INTPND_Pos 0 /!< CAN IFnIPND2: INTPND Position /
sahilmgandhi	18:6a4db94011d3	1721	#define CAN_IF_IPND2_INTPND_Msk (0xFFFFul << CAN_IF_IPND2_INTPND_Pos) /!< CAN IFnIPND2: INTPND Mask /
sahilmgandhi	18:6a4db94011d3	1722
sahilmgandhi	18:6a4db94011d3	1723	#define CAN_IF_MVLD1_MSGVAL_Pos 0 /!< CAN IFnMVLD1: MSGVAL Position /
sahilmgandhi	18:6a4db94011d3	1724	#define CAN_IF_MVLD1_MSGVAL_Msk (0xFFFFul << CAN_IF_MVLD1_MSGVAL_Pos) /!< CAN IFnMVLD1: MSGVAL Mask /
sahilmgandhi	18:6a4db94011d3	1725
sahilmgandhi	18:6a4db94011d3	1726	#define CAN_IF_MVLD2_MSGVAL_Pos 0 /!< CAN IFnMVLD2: MSGVAL Position /
sahilmgandhi	18:6a4db94011d3	1727	#define CAN_IF_MVLD2_MSGVAL_Msk (0xFFFFul << CAN_IF_MVLD2_MSGVAL_Pos) /!< CAN IFnMVLD2: MSGVAL Mask /
sahilmgandhi	18:6a4db94011d3	1728
sahilmgandhi	18:6a4db94011d3	1729	#define CAN_WUEN_WAKUP_EN_Pos 0 /!< CAN WUEN: WAKUP_EN Position /
sahilmgandhi	18:6a4db94011d3	1730	#define CAN_WUEN_WAKUP_EN_Msk (1ul << CAN_WUEN_WAKUP_EN_Pos) /!< CAN WUEN: WAKUP_EN Mask /
sahilmgandhi	18:6a4db94011d3	1731
sahilmgandhi	18:6a4db94011d3	1732	#define CAN_WUSTATUS_WAKUP_STS_Pos 0 /!< CAN WUSTATUS: WAKUP_STS Position /
sahilmgandhi	18:6a4db94011d3	1733	#define CAN_WUSTATUS_WAKUP_STS_Msk (1ul << CAN_WUSTATUS_WAKUP_STS_Pos) /!< CAN WUSTATUS: WAKUP_STS Mask /
sahilmgandhi	18:6a4db94011d3	1734
sahilmgandhi	18:6a4db94011d3	1735	/*@}/ /* CAN_CONST */
sahilmgandhi	18:6a4db94011d3	1736	/*@}/ /* end of CAN register group */
sahilmgandhi	18:6a4db94011d3	1737
sahilmgandhi	18:6a4db94011d3	1738
sahilmgandhi	18:6a4db94011d3	1739	/---------------------- Capture Engine -------------------------/
sahilmgandhi	18:6a4db94011d3	1740	/**
sahilmgandhi	18:6a4db94011d3	1741	@addtogroup CAP Capture Engine(CAP)
sahilmgandhi	18:6a4db94011d3	1742	Memory Mapped Structure for CAP Controller
sahilmgandhi	18:6a4db94011d3	1743	@{ */
sahilmgandhi	18:6a4db94011d3	1744
sahilmgandhi	18:6a4db94011d3	1745	typedef struct {
sahilmgandhi	18:6a4db94011d3	1746
sahilmgandhi	18:6a4db94011d3	1747
sahilmgandhi	18:6a4db94011d3	1748	/**
sahilmgandhi	18:6a4db94011d3	1749	* CTL
sahilmgandhi	18:6a4db94011d3	1750	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1751	* Offset: 0x00 Image Capture Interface Control Register
sahilmgandhi	18:6a4db94011d3	1752	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1753	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1754	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1755	* \|[0] \|CAPEN \|Image Capture Interface Enable
sahilmgandhi	18:6a4db94011d3	1756	* \| \| \|0 = Image Capture Interface Disabled.
sahilmgandhi	18:6a4db94011d3	1757	* \| \| \|1 = Image Capture Interface Enabled.
sahilmgandhi	18:6a4db94011d3	1758	* \|[3] \|ADDRSW \|Packet Buffer Address Switch
sahilmgandhi	18:6a4db94011d3	1759	* \| \| \|0 = Packet buffer address switch Disabled.
sahilmgandhi	18:6a4db94011d3	1760	* \| \| \|1 = Packet buffer address switch Enabled.
sahilmgandhi	18:6a4db94011d3	1761	* \|[5] \|PLNEN \|Planar Output Enable
sahilmgandhi	18:6a4db94011d3	1762	* \| \| \|0 = Planar output Disabled.
sahilmgandhi	18:6a4db94011d3	1763	* \| \| \|1 = Planar output Enabled.
sahilmgandhi	18:6a4db94011d3	1764	* \|[6] \|PKTEN \|Packet Output Enable
sahilmgandhi	18:6a4db94011d3	1765	* \| \| \|0 = Packet output Disabled.
sahilmgandhi	18:6a4db94011d3	1766	* \| \| \|1 = Packet output Enabled.
sahilmgandhi	18:6a4db94011d3	1767	* \|[16] \|SHUTTER \|Image Capture Interface Automatically Disable The Capture Inteface After A Frame Had Been Captured
sahilmgandhi	18:6a4db94011d3	1768	* \| \| \|0 = Shutter Disabled.
sahilmgandhi	18:6a4db94011d3	1769	* \| \| \|1 = Shutter Enabled.
sahilmgandhi	18:6a4db94011d3	1770	* \|[20] \|UPDATE \|Update Register At New Frame
sahilmgandhi	18:6a4db94011d3	1771	* \| \| \|0 = Update register at new frame Disabled.
sahilmgandhi	18:6a4db94011d3	1772	* \| \| \|1 = Update register at new frame Enabled (Auto clear to 0 when register updated).
sahilmgandhi	18:6a4db94011d3	1773	* \|[24] \|VPRST \|Capture Interface Reset
sahilmgandhi	18:6a4db94011d3	1774	* \| \| \|0 = Capture interface reset Disabled.
sahilmgandhi	18:6a4db94011d3	1775	* \| \| \|1 = Capture interface reset Enabled.
sahilmgandhi	18:6a4db94011d3	1776	*/
sahilmgandhi	18:6a4db94011d3	1777	__IO uint32_t CTL;
sahilmgandhi	18:6a4db94011d3	1778
sahilmgandhi	18:6a4db94011d3	1779	/**
sahilmgandhi	18:6a4db94011d3	1780	* PAR
sahilmgandhi	18:6a4db94011d3	1781	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1782	* Offset: 0x04 Image Capture Interface Parameter Register
sahilmgandhi	18:6a4db94011d3	1783	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1784	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1785	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1786	* \|[0] \|INFMT \|Sensor Input Data Format
sahilmgandhi	18:6a4db94011d3	1787	* \| \| \|0 = YCbCr422.
sahilmgandhi	18:6a4db94011d3	1788	* \| \| \|1 = RGB565.
sahilmgandhi	18:6a4db94011d3	1789	* \|[1] \|SENTYPE \|Sensor Input Type
sahilmgandhi	18:6a4db94011d3	1790	* \| \| \|0 = CCIR601.
sahilmgandhi	18:6a4db94011d3	1791	* \| \| \|1 = CCIR656, VSync & Hsync embedded in the data signal.
sahilmgandhi	18:6a4db94011d3	1792	* \|[2:3] \|INDATORD \|Sensor Input Data Order
sahilmgandhi	18:6a4db94011d3	1793	* \| \| \|If INFMT = 0 (YCbCr),.
sahilmgandhi	18:6a4db94011d3	1794	* \| \| \| Byte 0 1 2 3
sahilmgandhi	18:6a4db94011d3	1795	* \| \| \|00 = Y0 U0 Y1 V0.
sahilmgandhi	18:6a4db94011d3	1796	* \| \| \|01 = Y0 V0 Y1 U0.
sahilmgandhi	18:6a4db94011d3	1797	* \| \| \|10 = U0 Y0 V0 Y1.
sahilmgandhi	18:6a4db94011d3	1798	* \| \| \|11 = V0 Y0 U0 Y1.
sahilmgandhi	18:6a4db94011d3	1799	* \| \| \|If INFMT = 1 (RGB565),.
sahilmgandhi	18:6a4db94011d3	1800	* \| \| \|00
sahilmgandhi	18:6a4db94011d3	1801	* \| \| \|Byte 0
sahilmgandhi	18:6a4db94011d3	1802	* \| \| \|R[4:0] G[5:3]
sahilmgandhi	18:6a4db94011d3	1803	* \| \| \|Byte 1
sahilmgandhi	18:6a4db94011d3	1804	* \| \| \|G[2:0] B[4:0]
sahilmgandhi	18:6a4db94011d3	1805	* \| \| \|01
sahilmgandhi	18:6a4db94011d3	1806	* \| \| \|Byte 0
sahilmgandhi	18:6a4db94011d3	1807	* \| \| \|B[4:0] G[5:3]
sahilmgandhi	18:6a4db94011d3	1808	* \| \| \|Byte 1
sahilmgandhi	18:6a4db94011d3	1809	* \| \| \|G[2:0] R[4:0]
sahilmgandhi	18:6a4db94011d3	1810	* \| \| \|10
sahilmgandhi	18:6a4db94011d3	1811	* \| \| \|Byte 0
sahilmgandhi	18:6a4db94011d3	1812	* \| \| \|G[2:0] B[4:0]
sahilmgandhi	18:6a4db94011d3	1813	* \| \| \|Byte 1
sahilmgandhi	18:6a4db94011d3	1814	* \| \| \|R[4:0] G[5:3]
sahilmgandhi	18:6a4db94011d3	1815	* \| \| \|11
sahilmgandhi	18:6a4db94011d3	1816	* \| \| \|Byte 0
sahilmgandhi	18:6a4db94011d3	1817	* \| \| \|G[2:0] R[4:0]
sahilmgandhi	18:6a4db94011d3	1818	* \| \| \|Byte 1
sahilmgandhi	18:6a4db94011d3	1819	* \| \| \|R[4:0] G[5:3]
sahilmgandhi	18:6a4db94011d3	1820	* \|[4:5] \|OUTFMT \|Image Data Format Output To System Memory
sahilmgandhi	18:6a4db94011d3	1821	* \| \| \|00 = YCbCr422.
sahilmgandhi	18:6a4db94011d3	1822	* \| \| \|01 = Only output Y.
sahilmgandhi	18:6a4db94011d3	1823	* \| \| \|10 = RGB555.
sahilmgandhi	18:6a4db94011d3	1824	* \| \| \|11 = RGB565.
sahilmgandhi	18:6a4db94011d3	1825	* \|[6] \|RANGE \|Scale Input YUV CCIR601 Color Range To Full Range
sahilmgandhi	18:6a4db94011d3	1826	* \| \| \|0 = default.
sahilmgandhi	18:6a4db94011d3	1827	* \| \| \|1 = Scale to full range.
sahilmgandhi	18:6a4db94011d3	1828	* \|[7] \|PLNFMT \|Planar Output YUV Format
sahilmgandhi	18:6a4db94011d3	1829	* \| \| \|0 = YUV422.
sahilmgandhi	18:6a4db94011d3	1830	* \| \| \|1 = YUV420.
sahilmgandhi	18:6a4db94011d3	1831	* \|[8] \|PCLKP \|Sensor Pixel Clock Polarity
sahilmgandhi	18:6a4db94011d3	1832	* \| \| \|0 = Input video data and signals are latched by falling edge of Pixel Clock.
sahilmgandhi	18:6a4db94011d3	1833	* \| \| \|1 = Input video data and signals are latched by rising edge of Pixel Clock.
sahilmgandhi	18:6a4db94011d3	1834	* \|[9] \|HSP \|Sensor Hsync Polarity
sahilmgandhi	18:6a4db94011d3	1835	* \| \| \|0 = Sync Low.
sahilmgandhi	18:6a4db94011d3	1836	* \| \| \|1 = Sync High.
sahilmgandhi	18:6a4db94011d3	1837	* \|[10] \|VSP \|Sensor Vsync Polarity
sahilmgandhi	18:6a4db94011d3	1838	* \| \| \|0 = Sync Low.
sahilmgandhi	18:6a4db94011d3	1839	* \| \| \|1 = Sync High.
sahilmgandhi	18:6a4db94011d3	1840	* \|[11:12] \|COLORCTL \|Special COLORCTL Processing
sahilmgandhi	18:6a4db94011d3	1841	* \| \| \|00 = Normal Color.
sahilmgandhi	18:6a4db94011d3	1842	* \| \| \|01 = Sepia effect, corresponding U,V component value is set at register CAP_SEPIA.
sahilmgandhi	18:6a4db94011d3	1843	* \| \| \|10 = Negative picture.
sahilmgandhi	18:6a4db94011d3	1844	* \| \| \|11 = Posterize image, the Y, U, V components posterizing factor are set at register CAP_POSTERIZE.
sahilmgandhi	18:6a4db94011d3	1845	* \|[18] \|FBB \|Field By Blank
sahilmgandhi	18:6a4db94011d3	1846	* \| \| \|Hardware will tag field0 or field1 by vertical blanking instead of FIELD flag in ccir-656 mode.
sahilmgandhi	18:6a4db94011d3	1847	* \| \| \|0 = Field by blank Disabled.
sahilmgandhi	18:6a4db94011d3	1848	* \| \| \|1 = Field by blank Enabled.
sahilmgandhi	18:6a4db94011d3	1849	*/
sahilmgandhi	18:6a4db94011d3	1850	__IO uint32_t PAR;
sahilmgandhi	18:6a4db94011d3	1851
sahilmgandhi	18:6a4db94011d3	1852	/**
sahilmgandhi	18:6a4db94011d3	1853	* INT
sahilmgandhi	18:6a4db94011d3	1854	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1855	* Offset: 0x08 Image Capture Interface Interrupt Register
sahilmgandhi	18:6a4db94011d3	1856	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1857	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1858	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1859	* \|[0] \|VINTF \|Video Frame End Interrupt
sahilmgandhi	18:6a4db94011d3	1860	* \| \| \|If this bit shows 1, receiving a frame completed.
sahilmgandhi	18:6a4db94011d3	1861	* \| \| \|Write 1 to clear it.
sahilmgandhi	18:6a4db94011d3	1862	* \|[1] \|MEINTF \|Bus Master Transfer Error Interrupt
sahilmgandhi	18:6a4db94011d3	1863	* \| \| \|If this bit shows 1, Transfer Error occurred. Write 1 to clear it.
sahilmgandhi	18:6a4db94011d3	1864	* \|[3] \|ADDRMINTF \|Memory Address Match Interrupt
sahilmgandhi	18:6a4db94011d3	1865	* \| \| \|If this bit shows 1, Memory Address Match Interrupt occurred.
sahilmgandhi	18:6a4db94011d3	1866	* \| \| \|Write 1 to clear it.
sahilmgandhi	18:6a4db94011d3	1867	* \|[4] \|MDINTF \|Motion Detection Output Finish Interrupt
sahilmgandhi	18:6a4db94011d3	1868	* \| \| \|If this bit shows 1, Motion Detection Output Finish Interrupt occurred.
sahilmgandhi	18:6a4db94011d3	1869	* \| \| \|Write 1 to clear it.
sahilmgandhi	18:6a4db94011d3	1870	* \|[16] \|VIEN \|Video Frame End Interrupt Enable
sahilmgandhi	18:6a4db94011d3	1871	* \| \| \|0 = Video frame end interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	1872	* \| \| \|1 = Video frame end interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	1873	* \|[17] \|MEIEN \|System Memory Error Interrupt Enable
sahilmgandhi	18:6a4db94011d3	1874	* \| \| \|0 = System memory error interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	1875	* \| \| \|1 = System memory error interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	1876	* \|[19] \|ADDRMIEN \|Address Match Interrupt Enable
sahilmgandhi	18:6a4db94011d3	1877	* \| \| \|0 = Address match interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	1878	* \| \| \|1 = Address match interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	1879	* \|[20] \|MDIEN \|Motion Detection Output Finish Interrupt Enable
sahilmgandhi	18:6a4db94011d3	1880	* \| \| \|0 = CAP_MD finish interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	1881	* \| \| \|1 = CAP_MD finish interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	1882	*/
sahilmgandhi	18:6a4db94011d3	1883	__IO uint32_t INT;
sahilmgandhi	18:6a4db94011d3	1884
sahilmgandhi	18:6a4db94011d3	1885	/**
sahilmgandhi	18:6a4db94011d3	1886	* POSTERIZE
sahilmgandhi	18:6a4db94011d3	1887	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1888	* Offset: 0x0C YUV Component Posterizing Factor Register
sahilmgandhi	18:6a4db94011d3	1889	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1890	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1891	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1892	* \|[0:7] \|VCOMP \|V Component Posterizing Factor
sahilmgandhi	18:6a4db94011d3	1893	* \| \| \|Final_V_Out = Original_V[7:0] & V_Posterizing_Factor.
sahilmgandhi	18:6a4db94011d3	1894	* \|[8:15] \|UCOMP \|U Component Posterizing Factor
sahilmgandhi	18:6a4db94011d3	1895	* \| \| \|Final_U_Out = Original_U[7:0] & U_Posterizing_Factor.
sahilmgandhi	18:6a4db94011d3	1896	* \|[16:23] \|YCOMP \|Y Component Posterizing Factor
sahilmgandhi	18:6a4db94011d3	1897	* \| \| \|Final_Y_Out = Original_Y[7:0] & Y_Posterizing_Factor.
sahilmgandhi	18:6a4db94011d3	1898	*/
sahilmgandhi	18:6a4db94011d3	1899	__IO uint32_t POSTERIZE;
sahilmgandhi	18:6a4db94011d3	1900
sahilmgandhi	18:6a4db94011d3	1901	/**
sahilmgandhi	18:6a4db94011d3	1902	* MD
sahilmgandhi	18:6a4db94011d3	1903	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1904	* Offset: 0x10 Motion Detection Register
sahilmgandhi	18:6a4db94011d3	1905	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1906	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1907	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1908	* \|[0] \|MDEN \|Motion Detection Enable
sahilmgandhi	18:6a4db94011d3	1909	* \| \| \|0 = CAP_MD Disabled.
sahilmgandhi	18:6a4db94011d3	1910	* \| \| \|1 = CAP_MD Enabled.
sahilmgandhi	18:6a4db94011d3	1911	* \|[8] \|MDBS \|Motion Detection Block Size
sahilmgandhi	18:6a4db94011d3	1912	* \| \| \|0 = 16x16.
sahilmgandhi	18:6a4db94011d3	1913	* \| \| \|1 = 8x8.
sahilmgandhi	18:6a4db94011d3	1914	* \|[9] \|MDSM \|Motion Detection Save Mode
sahilmgandhi	18:6a4db94011d3	1915	* \| \| \|0 = 1 bit DIFF + 7 bit Y Differential.
sahilmgandhi	18:6a4db94011d3	1916	* \| \| \|1 = 1 bit DIFF only.
sahilmgandhi	18:6a4db94011d3	1917	* \|[10:11] \|MDDF \|Motion Detection Detect Frequency
sahilmgandhi	18:6a4db94011d3	1918	* \| \| \|00 = Each frame.
sahilmgandhi	18:6a4db94011d3	1919	* \| \| \|01 = Every 2 frame.
sahilmgandhi	18:6a4db94011d3	1920	* \| \| \|10 = Every 3 frame.
sahilmgandhi	18:6a4db94011d3	1921	* \| \| \|11 = Every 4 frame.
sahilmgandhi	18:6a4db94011d3	1922	* \|[16:20] \|MDTHR \|Motion Detection Differential Threshold
sahilmgandhi	18:6a4db94011d3	1923	*/
sahilmgandhi	18:6a4db94011d3	1924	__IO uint32_t MD;
sahilmgandhi	18:6a4db94011d3	1925
sahilmgandhi	18:6a4db94011d3	1926	/**
sahilmgandhi	18:6a4db94011d3	1927	* MDADDR
sahilmgandhi	18:6a4db94011d3	1928	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1929	* Offset: 0x14 Motion Detection Output Address Register
sahilmgandhi	18:6a4db94011d3	1930	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1931	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1932	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1933	* \|[0:31] \|MDADDR \|Motion Detection Output Address Register (Word Alignment)
sahilmgandhi	18:6a4db94011d3	1934	*/
sahilmgandhi	18:6a4db94011d3	1935	__IO uint32_t MDADDR;
sahilmgandhi	18:6a4db94011d3	1936
sahilmgandhi	18:6a4db94011d3	1937	/**
sahilmgandhi	18:6a4db94011d3	1938	* MDYADDR
sahilmgandhi	18:6a4db94011d3	1939	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1940	* Offset: 0x18 Motion Detection Temp Y Output Address Register
sahilmgandhi	18:6a4db94011d3	1941	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1942	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1943	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1944	* \|[0:31] \|MDYADDR \|Motion Detection Temp Y Output Address Register (Word Alignment)
sahilmgandhi	18:6a4db94011d3	1945	*/
sahilmgandhi	18:6a4db94011d3	1946	__IO uint32_t MDYADDR;
sahilmgandhi	18:6a4db94011d3	1947
sahilmgandhi	18:6a4db94011d3	1948	/**
sahilmgandhi	18:6a4db94011d3	1949	* SEPIA
sahilmgandhi	18:6a4db94011d3	1950	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1951	* Offset: 0x1C Sepia Effect Control Register
sahilmgandhi	18:6a4db94011d3	1952	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1953	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1954	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1955	* \|[0:7] \|VCOMP \|Define the constant V component while Sepia color effect is turned on.
sahilmgandhi	18:6a4db94011d3	1956	* \|[8:15] \|UCOMP \|Define the constant U component while Sepia color effect is turned on.
sahilmgandhi	18:6a4db94011d3	1957	*/
sahilmgandhi	18:6a4db94011d3	1958	__IO uint32_t SEPIA;
sahilmgandhi	18:6a4db94011d3	1959
sahilmgandhi	18:6a4db94011d3	1960	/**
sahilmgandhi	18:6a4db94011d3	1961	* CWSP
sahilmgandhi	18:6a4db94011d3	1962	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1963	* Offset: 0x20 Cropping Window Starting Address Register
sahilmgandhi	18:6a4db94011d3	1964	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1965	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1966	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1967	* \|[0:11] \|CWSADDRH \|Cropping Window Horizontal Starting Address
sahilmgandhi	18:6a4db94011d3	1968	* \|[16:26] \|CWSADDRV \|Cropping Window Vertical Starting Address
sahilmgandhi	18:6a4db94011d3	1969	*/
sahilmgandhi	18:6a4db94011d3	1970	__IO uint32_t CWSP;
sahilmgandhi	18:6a4db94011d3	1971
sahilmgandhi	18:6a4db94011d3	1972	/**
sahilmgandhi	18:6a4db94011d3	1973	* CWS
sahilmgandhi	18:6a4db94011d3	1974	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1975	* Offset: 0x24 Cropping Window Size Register
sahilmgandhi	18:6a4db94011d3	1976	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1977	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1978	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1979	* \|[0:11] \|CIWW \|Cropping Image Window Width
sahilmgandhi	18:6a4db94011d3	1980	* \|[16:26] \|CIWH \|Cropping Image Window Height
sahilmgandhi	18:6a4db94011d3	1981	*/
sahilmgandhi	18:6a4db94011d3	1982	__IO uint32_t CWS;
sahilmgandhi	18:6a4db94011d3	1983
sahilmgandhi	18:6a4db94011d3	1984	/**
sahilmgandhi	18:6a4db94011d3	1985	* PKTSL
sahilmgandhi	18:6a4db94011d3	1986	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	1987	* Offset: 0x28 Packet Scaling Vertical/Horizontal Factor Register (LSB)
sahilmgandhi	18:6a4db94011d3	1988	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	1989	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	1990	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	1991	* \|[0:7] \|PKTSHML \|Packet Scaling Horizontal Factor M (Lower 8-Bit)
sahilmgandhi	18:6a4db94011d3	1992	* \| \| \|Specifies the lower 8-bit of denominator part (M) of the horizontal scaling factor.
sahilmgandhi	18:6a4db94011d3	1993	* \| \| \|The lower 8-bit will be cascaded with higher 8-bit (PKDSHMH) to form a 16-bit denominator (M) of vertical factor.
sahilmgandhi	18:6a4db94011d3	1994	* \| \| \|The output image width will be equal to the image width * N/M.
sahilmgandhi	18:6a4db94011d3	1995	* \| \| \|Note: The value of N must be equal to or less than M.
sahilmgandhi	18:6a4db94011d3	1996	* \|[8:15] \|PKTSHNL \|Packet Scaling Horizontal Factor N (Lower 8-Bit)
sahilmgandhi	18:6a4db94011d3	1997	* \| \| \|Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor.
sahilmgandhi	18:6a4db94011d3	1998	* \| \| \|The lower 8-bit will be cascaded with higher 8-bit (PKDSHNH) to form a 16-bit numerator of horizontal factor.
sahilmgandhi	18:6a4db94011d3	1999	* \|[16:23] \|PKTSVML \|Packet Scaling Vertical Factor M (Lower 8-Bit)
sahilmgandhi	18:6a4db94011d3	2000	* \| \| \|Specify the lower 8-bit of denominator part (M) of the vertical scaling factor.
sahilmgandhi	18:6a4db94011d3	2001	* \| \| \|The lower 8-bit will be cascaded with higher 8-bit (PKDSVMH) to form a 16-bit denominator (M) of vertical factor.
sahilmgandhi	18:6a4db94011d3	2002	* \| \| \|The output image width will be equal to the image height * N/M.
sahilmgandhi	18:6a4db94011d3	2003	* \| \| \|Note: The value of N must be equal to or less than M.
sahilmgandhi	18:6a4db94011d3	2004	* \|[24:31] \|PKTSVNL \|Packet Scaling Vertical Factor N (Lower 8-Bit)
sahilmgandhi	18:6a4db94011d3	2005	* \| \| \|Specify the lower 8-bit of numerator part (N) of the vertical scaling factor.
sahilmgandhi	18:6a4db94011d3	2006	* \| \| \|The lower 8-bit will be cascaded with higher 8-bit (PKDSVNH) to form a 16-bit numerator of vertical factor
sahilmgandhi	18:6a4db94011d3	2007	*/
sahilmgandhi	18:6a4db94011d3	2008	__IO uint32_t PKTSL;
sahilmgandhi	18:6a4db94011d3	2009
sahilmgandhi	18:6a4db94011d3	2010	/**
sahilmgandhi	18:6a4db94011d3	2011	* PLNSL
sahilmgandhi	18:6a4db94011d3	2012	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	2013	* Offset: 0x2C Planar Scaling Vertical/Horizontal Factor Register (LSB)
sahilmgandhi	18:6a4db94011d3	2014	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	2015	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	2016	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	2017	* \|[0:7] \|PLNSHML \|Planar Scaling Horizontal Factor M (Lower 8-Bit)
sahilmgandhi	18:6a4db94011d3	2018	* \| \| \|Specify the lower 8-bit of denominator part (M) of the horizontal scaling factor.
sahilmgandhi	18:6a4db94011d3	2019	* \| \| \|The lower 8-bit will be cascaded with higher 8-bit (PNDSHMH) to form a 16-bit denominator (M) of vertical factor.
sahilmgandhi	18:6a4db94011d3	2020	* \| \| \|The output image width will be equal to the image width * N/M.
sahilmgandhi	18:6a4db94011d3	2021	* \| \| \|Note: The value of N must be equal to or less than M.
sahilmgandhi	18:6a4db94011d3	2022	* \|[8:15] \|PLNSHNL \|Planar Scaling Horizontal Factor N (Lower 8-Bit)
sahilmgandhi	18:6a4db94011d3	2023	* \| \| \|Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor.
sahilmgandhi	18:6a4db94011d3	2024	* \| \| \|The lower 8-bit will be cascaded with higher 8-bit (PNDSHNH) to form a 16-bit numerator of horizontal factor.
sahilmgandhi	18:6a4db94011d3	2025	* \|[16:23] \|PLNSVML \|Planar Scaling Vertical Factor M (Lower 8-Bit)
sahilmgandhi	18:6a4db94011d3	2026	* \| \| \|Specify the lower 8-bit of denominator part (M) of the vertical scaling factor.
sahilmgandhi	18:6a4db94011d3	2027	* \| \| \|The lower 8-bit will be cascaded with higher 8-bit (PNDSVMH) to form a 16-bit denominator (M) of vertical factor.
sahilmgandhi	18:6a4db94011d3	2028	* \| \| \|The output image width will be equal to the image height * N/M.
sahilmgandhi	18:6a4db94011d3	2029	* \| \| \|Note: The value of N must be equal to or less than M.
sahilmgandhi	18:6a4db94011d3	2030	* \|[24:31] \|PLNSVNL \|Planar Scaling Vertical Factor N (Lower 8-Bit)
sahilmgandhi	18:6a4db94011d3	2031	* \| \| \|Specify the lower 8-bit of numerator part (N) of the vertical scaling factor.
sahilmgandhi	18:6a4db94011d3	2032	* \| \| \|The lower 8-bit will be cascaded with higher 8-bit (PNDSVNH) to form a 16-bit numerator of vertical factor.
sahilmgandhi	18:6a4db94011d3	2033	*/
sahilmgandhi	18:6a4db94011d3	2034	__IO uint32_t PLNSL;
sahilmgandhi	18:6a4db94011d3	2035
sahilmgandhi	18:6a4db94011d3	2036	/**
sahilmgandhi	18:6a4db94011d3	2037	* FRCTL
sahilmgandhi	18:6a4db94011d3	2038	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	2039	* Offset: 0x30 Scaling Frame Rate Factor Register
sahilmgandhi	18:6a4db94011d3	2040	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	2041	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	2042	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	2043	* \|[0:5] \|FRM \|Scaling Frame Rate Factor M
sahilmgandhi	18:6a4db94011d3	2044	* \| \| \|Specify the denominator part (M) of the frame rate scaling factor.
sahilmgandhi	18:6a4db94011d3	2045	* \| \| \|The output image frame rate will be equal to input image frame rate * (N/M).
sahilmgandhi	18:6a4db94011d3	2046	* \| \| \|Note: The value of N must be equal to or less than M.
sahilmgandhi	18:6a4db94011d3	2047	* \|[8:13] \|FRN \|Scaling Frame Rate Factor N
sahilmgandhi	18:6a4db94011d3	2048	* \| \| \|Specify the denominator part (N) of the frame rate scaling factor.
sahilmgandhi	18:6a4db94011d3	2049	*/
sahilmgandhi	18:6a4db94011d3	2050	__IO uint32_t FRCTL;
sahilmgandhi	18:6a4db94011d3	2051
sahilmgandhi	18:6a4db94011d3	2052	/**
sahilmgandhi	18:6a4db94011d3	2053	* STRIDE
sahilmgandhi	18:6a4db94011d3	2054	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	2055	* Offset: 0x34 Frame Output Pixel Stride Width Register
sahilmgandhi	18:6a4db94011d3	2056	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	2057	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	2058	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	2059	* \|[0:13] \|PKTSTRIDE \|Packet Frame Output Pixel Stride Width
sahilmgandhi	18:6a4db94011d3	2060	* \| \| \|The output pixel stride size of packet pipe.
sahilmgandhi	18:6a4db94011d3	2061	* \|[16:29] \|PLNSTRIDE \|Planar Frame Output Pixel Stride Width
sahilmgandhi	18:6a4db94011d3	2062	* \| \| \|The output pixel stride size of planar pipe.
sahilmgandhi	18:6a4db94011d3	2063	*/
sahilmgandhi	18:6a4db94011d3	2064	__IO uint32_t STRIDE;
sahilmgandhi	18:6a4db94011d3	2065	uint32_t RESERVE0[1];
sahilmgandhi	18:6a4db94011d3	2066
sahilmgandhi	18:6a4db94011d3	2067
sahilmgandhi	18:6a4db94011d3	2068	/**
sahilmgandhi	18:6a4db94011d3	2069	* FIFOTH
sahilmgandhi	18:6a4db94011d3	2070	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	2071	* Offset: 0x3C FIFO Threshold Register
sahilmgandhi	18:6a4db94011d3	2072	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	2073	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	2074	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	2075	* \|[0:3] \|PLNVFTH \|Planar V FIFO Threshold
sahilmgandhi	18:6a4db94011d3	2076	* \|[8:11] \|PLNUFTH \|Planar U FIFO Threshold
sahilmgandhi	18:6a4db94011d3	2077	* \|[16:20] \|PLNYFTH \|Planar Y FIFO Threshold
sahilmgandhi	18:6a4db94011d3	2078	* \|[24:28] \|PKTFTH \|Packet FIFO Threshold
sahilmgandhi	18:6a4db94011d3	2079	* \|[31] \|OVF \|FIFO Overflow Flag
sahilmgandhi	18:6a4db94011d3	2080	*/
sahilmgandhi	18:6a4db94011d3	2081	__IO uint32_t FIFOTH;
sahilmgandhi	18:6a4db94011d3	2082
sahilmgandhi	18:6a4db94011d3	2083	/**
sahilmgandhi	18:6a4db94011d3	2084	* CMPADDR
sahilmgandhi	18:6a4db94011d3	2085	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	2086	* Offset: 0x40 Compare Memory Base Address Register
sahilmgandhi	18:6a4db94011d3	2087	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	2088	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	2089	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	2090	* \|[0:31] \|CMPADDR \|Compare Memory Base Address
sahilmgandhi	18:6a4db94011d3	2091	* \| \| \|Word aligns address; ignore the bits [1:0].
sahilmgandhi	18:6a4db94011d3	2092	*/
sahilmgandhi	18:6a4db94011d3	2093	__IO uint32_t CMPADDR;
sahilmgandhi	18:6a4db94011d3	2094	uint32_t RESERVE1[1];
sahilmgandhi	18:6a4db94011d3	2095
sahilmgandhi	18:6a4db94011d3	2096
sahilmgandhi	18:6a4db94011d3	2097	/**
sahilmgandhi	18:6a4db94011d3	2098	* PKTSM
sahilmgandhi	18:6a4db94011d3	2099	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	2100	* Offset: 0x48 Packet Scaling Vertical/Horizontal Factor Register (MSB)
sahilmgandhi	18:6a4db94011d3	2101	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	2102	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	2103	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	2104	* \|[0:7] \|PKTSHMH \|Packet Scaling Horizontal Factor M (Higher 8-Bit)
sahilmgandhi	18:6a4db94011d3	2105	* \| \| \|Specify the lower 8-bit of denominator part (M) of the horizontal scaling factor.
sahilmgandhi	18:6a4db94011d3	2106	* \| \| \|Please refer to the register CAP_PKTSL?for the detailed operation.
sahilmgandhi	18:6a4db94011d3	2107	* \|[8:15] \|PKTSHNH \|Packet Scaling Horizontal Factor N (Higher 8-Bit)
sahilmgandhi	18:6a4db94011d3	2108	* \| \| \|Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor.
sahilmgandhi	18:6a4db94011d3	2109	* \| \| \|Please refer to the register CAP_PKTSL for the detailed operation.
sahilmgandhi	18:6a4db94011d3	2110	* \|[16:23] \|PKTSVMH \|Packet Scaling Vertical Factor M (Higher 8-Bit)
sahilmgandhi	18:6a4db94011d3	2111	* \| \| \|Specify the lower 8-bit of denominator part (M) of the vertical scaling factor.
sahilmgandhi	18:6a4db94011d3	2112	* \| \| \|Please refer to the register CAP_PKTSL to check the cooperation between these two registers.
sahilmgandhi	18:6a4db94011d3	2113	* \|[24:31] \|PKTSVNH \|Packet Scaling Vertical Factor N (Higher 8-Bit)
sahilmgandhi	18:6a4db94011d3	2114	* \| \| \|Specify the higher 8-bit of numerator part (N) of the vertical scaling factor.
sahilmgandhi	18:6a4db94011d3	2115	* \| \| \|Please refer to the register CAP_PKTSL?to check the cooperation between these two registers.
sahilmgandhi	18:6a4db94011d3	2116	*/
sahilmgandhi	18:6a4db94011d3	2117	__IO uint32_t PKTSM;
sahilmgandhi	18:6a4db94011d3	2118
sahilmgandhi	18:6a4db94011d3	2119	/**
sahilmgandhi	18:6a4db94011d3	2120	* PLNSM
sahilmgandhi	18:6a4db94011d3	2121	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	2122	* Offset: 0x4C Planar Scaling Vertical/Horizontal Factor Register (MSB)
sahilmgandhi	18:6a4db94011d3	2123	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	2124	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	2125	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	2126	* \|[0:7] \|PLNSHMH \|Planar Scaling Horizontal Factor M (Higher 8-Bit)
sahilmgandhi	18:6a4db94011d3	2127	* \| \| \|Specifies the higher 8-bit of denominator part (M) of the horizontal scaling factor
sahilmgandhi	18:6a4db94011d3	2128	* \| \| \|For detailed programming, please refer to the register CAP_PLNSL?
sahilmgandhi	18:6a4db94011d3	2129	* \|[8:15] \|PLNSHNH \|Planar Scaling Horizontal Factor N (Higher 8-Bit)
sahilmgandhi	18:6a4db94011d3	2130	* \| \| \|Specifies the higher 8-bit of numerator part (N) of the horizontal scaling factor.
sahilmgandhi	18:6a4db94011d3	2131	* \| \| \|For detailed programming, please refer to the register CAP_PLNSL?
sahilmgandhi	18:6a4db94011d3	2132	* \|[16:23] \|PLNSVMH \|Planar Scaling Vertical Factor M (Higher 8-Bit)
sahilmgandhi	18:6a4db94011d3	2133	* \| \| \|Specifies the lower 8-bit of denominator part (M) of the vertical scaling factor.
sahilmgandhi	18:6a4db94011d3	2134	* \| \| \|For detailed programming, please refer to the register CAP_PLNSL?
sahilmgandhi	18:6a4db94011d3	2135	* \|[24:31] \|PLNSVNH \|Planar Scaling Vertical Factor N (Higher 8-Bit)
sahilmgandhi	18:6a4db94011d3	2136	* \| \| \|Specifies the higher 8-bit of numerator part (N) of the vertical scaling factor.
sahilmgandhi	18:6a4db94011d3	2137	* \| \| \|For detailed programming, please refer to the register CAP_PLNSL?
sahilmgandhi	18:6a4db94011d3	2138	*/
sahilmgandhi	18:6a4db94011d3	2139	__IO uint32_t PLNSM;
sahilmgandhi	18:6a4db94011d3	2140
sahilmgandhi	18:6a4db94011d3	2141	/**
sahilmgandhi	18:6a4db94011d3	2142	* CURADDRP
sahilmgandhi	18:6a4db94011d3	2143	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	2144	* Offset: 0x50 Current Packet System Memory Address Register
sahilmgandhi	18:6a4db94011d3	2145	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	2146	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	2147	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	2148	* \|[0:31] \|CURADDR \|Current Packet Output Memory Address
sahilmgandhi	18:6a4db94011d3	2149	*/
sahilmgandhi	18:6a4db94011d3	2150	__I uint32_t CURADDRP;
sahilmgandhi	18:6a4db94011d3	2151
sahilmgandhi	18:6a4db94011d3	2152	/**
sahilmgandhi	18:6a4db94011d3	2153	* CURADDRY
sahilmgandhi	18:6a4db94011d3	2154	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	2155	* Offset: 0x54 Current Planar Y System Memory Address Register
sahilmgandhi	18:6a4db94011d3	2156	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	2157	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	2158	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	2159	* \|[0:31] \|CURADDR \|Current Planar Y Output Memory Address
sahilmgandhi	18:6a4db94011d3	2160	*/
sahilmgandhi	18:6a4db94011d3	2161	__I uint32_t CURADDRY;
sahilmgandhi	18:6a4db94011d3	2162
sahilmgandhi	18:6a4db94011d3	2163	/**
sahilmgandhi	18:6a4db94011d3	2164	* CURADDRU
sahilmgandhi	18:6a4db94011d3	2165	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	2166	* Offset: 0x58 Current Planar U System Memory Address Register
sahilmgandhi	18:6a4db94011d3	2167	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	2168	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	2169	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	2170	* \|[0:31] \|CURADDR \|Current Planar U Output Memory Address
sahilmgandhi	18:6a4db94011d3	2171	*/
sahilmgandhi	18:6a4db94011d3	2172	__I uint32_t CURADDRU;
sahilmgandhi	18:6a4db94011d3	2173
sahilmgandhi	18:6a4db94011d3	2174	/**
sahilmgandhi	18:6a4db94011d3	2175	* CURVADDR
sahilmgandhi	18:6a4db94011d3	2176	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	2177	* Offset: 0x5C Current Planar V System Memory Address Register
sahilmgandhi	18:6a4db94011d3	2178	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	2179	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	2180	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	2181	* \|[0:31] \|CURADDR \|Current Planar V Output Memory Address
sahilmgandhi	18:6a4db94011d3	2182	*/
sahilmgandhi	18:6a4db94011d3	2183	__I uint32_t CURVADDR;
sahilmgandhi	18:6a4db94011d3	2184
sahilmgandhi	18:6a4db94011d3	2185	/**
sahilmgandhi	18:6a4db94011d3	2186	* PKTBA0
sahilmgandhi	18:6a4db94011d3	2187	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	2188	* Offset: 0x60 System Memory Packet Base Address 0 Register
sahilmgandhi	18:6a4db94011d3	2189	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	2190	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	2191	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	2192	* \|[0:31] \|BASEADDR \|System Memory Packet Base Address 0
sahilmgandhi	18:6a4db94011d3	2193	* \| \| \|Word aligns address; ignore the bits [1:0].
sahilmgandhi	18:6a4db94011d3	2194	*/
sahilmgandhi	18:6a4db94011d3	2195	__IO uint32_t PKTBA0;
sahilmgandhi	18:6a4db94011d3	2196
sahilmgandhi	18:6a4db94011d3	2197	/**
sahilmgandhi	18:6a4db94011d3	2198	* PKTBA1
sahilmgandhi	18:6a4db94011d3	2199	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	2200	* Offset: 0x64 System Memory Packet Base Address 1 Register
sahilmgandhi	18:6a4db94011d3	2201	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	2202	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	2203	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	2204	* \|[0:31] \|BASEADDR \|System Memory Packet Base Address 1
sahilmgandhi	18:6a4db94011d3	2205	* \| \| \|Word aligns address; ignore the bits [1:0].
sahilmgandhi	18:6a4db94011d3	2206	*/
sahilmgandhi	18:6a4db94011d3	2207	__IO uint32_t PKTBA1;
sahilmgandhi	18:6a4db94011d3	2208	uint32_t RESERVE2[6];
sahilmgandhi	18:6a4db94011d3	2209
sahilmgandhi	18:6a4db94011d3	2210
sahilmgandhi	18:6a4db94011d3	2211	/**
sahilmgandhi	18:6a4db94011d3	2212	* YBA
sahilmgandhi	18:6a4db94011d3	2213	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	2214	* Offset: 0x80 System Memory Planar Y Base Address Register
sahilmgandhi	18:6a4db94011d3	2215	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	2216	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	2217	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	2218	* \|[0:31] \|BASEADDR \|System Memory Planar Y Base Address
sahilmgandhi	18:6a4db94011d3	2219	* \| \| \|Word aligns address; ignore the bits [1:0].
sahilmgandhi	18:6a4db94011d3	2220	*/
sahilmgandhi	18:6a4db94011d3	2221	__IO uint32_t YBA;
sahilmgandhi	18:6a4db94011d3	2222
sahilmgandhi	18:6a4db94011d3	2223	/**
sahilmgandhi	18:6a4db94011d3	2224	* UBA
sahilmgandhi	18:6a4db94011d3	2225	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	2226	* Offset: 0x84 System Memory Planar U Base Address Register
sahilmgandhi	18:6a4db94011d3	2227	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	2228	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	2229	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	2230	* \|[0:31] \|BASEADDR \|System Memory Planar U Base Address
sahilmgandhi	18:6a4db94011d3	2231	* \| \| \|Word aligns address; ignore the bits [1:0].
sahilmgandhi	18:6a4db94011d3	2232	*/
sahilmgandhi	18:6a4db94011d3	2233	__IO uint32_t UBA;
sahilmgandhi	18:6a4db94011d3	2234
sahilmgandhi	18:6a4db94011d3	2235	/**
sahilmgandhi	18:6a4db94011d3	2236	* VBA
sahilmgandhi	18:6a4db94011d3	2237	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	2238	* Offset: 0x88 System Memory Planar V Base Address Register
sahilmgandhi	18:6a4db94011d3	2239	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	2240	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	2241	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	2242	* \|[0:31] \|BASEADDR \|System Memory Planar V Base Address
sahilmgandhi	18:6a4db94011d3	2243	* \| \| \|Word aligns address; ignore the bits [1:0].
sahilmgandhi	18:6a4db94011d3	2244	*/
sahilmgandhi	18:6a4db94011d3	2245	__IO uint32_t VBA;
sahilmgandhi	18:6a4db94011d3	2246
sahilmgandhi	18:6a4db94011d3	2247	} CAP_T;
sahilmgandhi	18:6a4db94011d3	2248
sahilmgandhi	18:6a4db94011d3	2249	/**
sahilmgandhi	18:6a4db94011d3	2250	@addtogroup CAP_CONST CAP Bit Field Definition
sahilmgandhi	18:6a4db94011d3	2251	Constant Definitions for CAP Controller
sahilmgandhi	18:6a4db94011d3	2252	@{ */
sahilmgandhi	18:6a4db94011d3	2253
sahilmgandhi	18:6a4db94011d3	2254	#define CAP_CTL_CAPEN_Pos (0) /!< CAP CTL: CAPEN Position /
sahilmgandhi	18:6a4db94011d3	2255	#define CAP_CTL_CAPEN_Msk (0x1ul << CAP_CTL_CAPEN_Pos) /!< CAP CTL: CAPEN Mask /
sahilmgandhi	18:6a4db94011d3	2256
sahilmgandhi	18:6a4db94011d3	2257	#define CAP_CTL_ADDRSW_Pos (3) /!< CAP CTL: ADDRSW Position /
sahilmgandhi	18:6a4db94011d3	2258	#define CAP_CTL_ADDRSW_Msk (0x1ul << CAP_CTL_ADDRSW_Pos) /!< CAP CTL: ADDRSW Mask /
sahilmgandhi	18:6a4db94011d3	2259
sahilmgandhi	18:6a4db94011d3	2260	#define CAP_CTL_PLNEN_Pos (5) /!< CAP CTL: PLNEN Position /
sahilmgandhi	18:6a4db94011d3	2261	#define CAP_CTL_PLNEN_Msk (0x1ul << CAP_CTL_PLNEN_Pos) /!< CAP CTL: PLNEN Mask /
sahilmgandhi	18:6a4db94011d3	2262
sahilmgandhi	18:6a4db94011d3	2263	#define CAP_CTL_PKTEN_Pos (6) /!< CAP CTL: PKTEN Position /
sahilmgandhi	18:6a4db94011d3	2264	#define CAP_CTL_PKTEN_Msk (0x1ul << CAP_CTL_PKTEN_Pos) /!< CAP CTL: PKTEN Mask /
sahilmgandhi	18:6a4db94011d3	2265
sahilmgandhi	18:6a4db94011d3	2266	#define CAP_CTL_SHUTTER_Pos (16) /!< CAP CTL: SHUTTER Position /
sahilmgandhi	18:6a4db94011d3	2267	#define CAP_CTL_SHUTTER_Msk (0x1ul << CAP_CTL_SHUTTER_Pos) /!< CAP CTL: SHUTTER Mask /
sahilmgandhi	18:6a4db94011d3	2268
sahilmgandhi	18:6a4db94011d3	2269	#define CAP_CTL_UPDATE_Pos (20) /!< CAP CTL: UPDATE Position /
sahilmgandhi	18:6a4db94011d3	2270	#define CAP_CTL_UPDATE_Msk (0x1ul << CAP_CTL_UPDATE_Pos) /!< CAP CTL: UPDATE Mask /
sahilmgandhi	18:6a4db94011d3	2271
sahilmgandhi	18:6a4db94011d3	2272	#define CAP_CTL_VPRST_Pos (24) /!< CAP CTL: VPRST Position /
sahilmgandhi	18:6a4db94011d3	2273	#define CAP_CTL_VPRST_Msk (0x1ul << CAP_CTL_VPRST_Pos) /!< CAP CTL: VPRST Mask /
sahilmgandhi	18:6a4db94011d3	2274
sahilmgandhi	18:6a4db94011d3	2275	#define CAP_PAR_INFMT_Pos (0) /!< CAP PAR: INFMT Position /
sahilmgandhi	18:6a4db94011d3	2276	#define CAP_PAR_INFMT_Msk (0x1ul << CAP_PAR_INFMT_Pos) /!< CAP PAR: INFMT Mask /
sahilmgandhi	18:6a4db94011d3	2277
sahilmgandhi	18:6a4db94011d3	2278	#define CAP_PAR_SENTYPE_Pos (1) /!< CAP PAR: SENTYPE Position /
sahilmgandhi	18:6a4db94011d3	2279	#define CAP_PAR_SENTYPE_Msk (0x1ul << CAP_PAR_SENTYPE_Pos) /!< CAP PAR: SENTYPE Mask /
sahilmgandhi	18:6a4db94011d3	2280
sahilmgandhi	18:6a4db94011d3	2281	#define CAP_PAR_INDATORD_Pos (2) /!< CAP PAR: INDATORD Position /
sahilmgandhi	18:6a4db94011d3	2282	#define CAP_PAR_INDATORD_Msk (0x3ul << CAP_PAR_INDATORD_Pos) /!< CAP PAR: INDATORD Mask /
sahilmgandhi	18:6a4db94011d3	2283
sahilmgandhi	18:6a4db94011d3	2284	#define CAP_PAR_OUTFMT_Pos (4) /!< CAP PAR: OUTFMT Position /
sahilmgandhi	18:6a4db94011d3	2285	#define CAP_PAR_OUTFMT_Msk (0x3ul << CAP_PAR_OUTFMT_Pos) /!< CAP PAR: OUTFMT Mask /
sahilmgandhi	18:6a4db94011d3	2286
sahilmgandhi	18:6a4db94011d3	2287	#define CAP_PAR_RANGE_Pos (6) /!< CAP PAR: RANGE Position /
sahilmgandhi	18:6a4db94011d3	2288	#define CAP_PAR_RANGE_Msk (0x1ul << CAP_PAR_RANGE_Pos) /!< CAP PAR: RANGE Mask /
sahilmgandhi	18:6a4db94011d3	2289
sahilmgandhi	18:6a4db94011d3	2290	#define CAP_PAR_PLNFMT_Pos (7) /!< CAP PAR: PLNFMT Position /
sahilmgandhi	18:6a4db94011d3	2291	#define CAP_PAR_PLNFMT_Msk (0x1ul << CAP_PAR_PLNFMT_Pos) /!< CAP PAR: PLNFMT Mask /
sahilmgandhi	18:6a4db94011d3	2292
sahilmgandhi	18:6a4db94011d3	2293	#define CAP_PAR_PCLKP_Pos (8) /!< CAP PAR: PCLKP Position /
sahilmgandhi	18:6a4db94011d3	2294	#define CAP_PAR_PCLKP_Msk (0x1ul << CAP_PAR_PCLKP_Pos) /!< CAP PAR: PCLKP Mask /
sahilmgandhi	18:6a4db94011d3	2295
sahilmgandhi	18:6a4db94011d3	2296	#define CAP_PAR_HSP_Pos (9) /!< CAP PAR: HSP Position /
sahilmgandhi	18:6a4db94011d3	2297	#define CAP_PAR_HSP_Msk (0x1ul << CAP_PAR_HSP_Pos) /!< CAP PAR: HSP Mask /
sahilmgandhi	18:6a4db94011d3	2298
sahilmgandhi	18:6a4db94011d3	2299	#define CAP_PAR_VSP_Pos (10) /!< CAP PAR: VSP Position /
sahilmgandhi	18:6a4db94011d3	2300	#define CAP_PAR_VSP_Msk (0x1ul << CAP_PAR_VSP_Pos) /!< CAP PAR: VSP Mask /
sahilmgandhi	18:6a4db94011d3	2301
sahilmgandhi	18:6a4db94011d3	2302	#define CAP_PAR_COLORCTL_Pos (11) /!< CAP PAR: COLORCTL Position /
sahilmgandhi	18:6a4db94011d3	2303	#define CAP_PAR_COLORCTL_Msk (0x3ul << CAP_PAR_COLORCTL_Pos) /!< CAP PAR: COLORCTL Mask /
sahilmgandhi	18:6a4db94011d3	2304
sahilmgandhi	18:6a4db94011d3	2305	#define CAP_PAR_FBB_Pos (18) /!< CAP PAR: FBB Position /
sahilmgandhi	18:6a4db94011d3	2306	#define CAP_PAR_FBB_Msk (0x1ul << CAP_PAR_FBB_Pos) /!< CAP PAR: FBB Mask /
sahilmgandhi	18:6a4db94011d3	2307
sahilmgandhi	18:6a4db94011d3	2308	#define CAP_INT_VINTF_Pos (0) /!< CAP INT: VINTF Position /
sahilmgandhi	18:6a4db94011d3	2309	#define CAP_INT_VINTF_Msk (0x1ul << CAP_INT_VINTF_Pos) /!< CAP INT: VINTF Mask /
sahilmgandhi	18:6a4db94011d3	2310
sahilmgandhi	18:6a4db94011d3	2311	#define CAP_INT_MEINTF_Pos (1) /!< CAP INT: MEINTF Position /
sahilmgandhi	18:6a4db94011d3	2312	#define CAP_INT_MEINTF_Msk (0x1ul << CAP_INT_MEINTF_Pos) /!< CAP INT: MEINTF Mask /
sahilmgandhi	18:6a4db94011d3	2313
sahilmgandhi	18:6a4db94011d3	2314	#define CAP_INT_ADDRMINTF_Pos (3) /!< CAP INT: ADDRMINTF Position /
sahilmgandhi	18:6a4db94011d3	2315	#define CAP_INT_ADDRMINTF_Msk (0x1ul << CAP_INT_ADDRMINTF_Pos) /!< CAP INT: ADDRMINTF Mask /
sahilmgandhi	18:6a4db94011d3	2316
sahilmgandhi	18:6a4db94011d3	2317	#define CAP_INT_MDINTF_Pos (4) /!< CAP INT: MDINTF Position /
sahilmgandhi	18:6a4db94011d3	2318	#define CAP_INT_MDINTF_Msk (0x1ul << CAP_INT_MDINTF_Pos) /!< CAP INT: MDINTF Mask /
sahilmgandhi	18:6a4db94011d3	2319
sahilmgandhi	18:6a4db94011d3	2320	#define CAP_INT_VIEN_Pos (16) /!< CAP INT: VIEN Position /
sahilmgandhi	18:6a4db94011d3	2321	#define CAP_INT_VIEN_Msk (0x1ul << CAP_INT_VIEN_Pos) /!< CAP INT: VIEN Mask /
sahilmgandhi	18:6a4db94011d3	2322
sahilmgandhi	18:6a4db94011d3	2323	#define CAP_INT_MEIEN_Pos (17) /!< CAP INT: MEIEN Position /
sahilmgandhi	18:6a4db94011d3	2324	#define CAP_INT_MEIEN_Msk (0x1ul << CAP_INT_MEIEN_Pos) /!< CAP INT: MEIEN Mask /
sahilmgandhi	18:6a4db94011d3	2325
sahilmgandhi	18:6a4db94011d3	2326	#define CAP_INT_ADDRMIEN_Pos (19) /!< CAP INT: ADDRMIEN Position /
sahilmgandhi	18:6a4db94011d3	2327	#define CAP_INT_ADDRMIEN_Msk (0x1ul << CAP_INT_ADDRMIEN_Pos) /!< CAP INT: ADDRMIEN Mask /
sahilmgandhi	18:6a4db94011d3	2328
sahilmgandhi	18:6a4db94011d3	2329	#define CAP_INT_MDIEN_Pos (20) /!< CAP INT: MDIEN Position /
sahilmgandhi	18:6a4db94011d3	2330	#define CAP_INT_MDIEN_Msk (0x1ul << CAP_INT_MDIEN_Pos) /!< CAP INT: MDIEN Mask /
sahilmgandhi	18:6a4db94011d3	2331
sahilmgandhi	18:6a4db94011d3	2332	#define CAP_POSTERIZE_VCOMP_Pos (0) /!< CAP POSTERIZE: VCOMP Position /
sahilmgandhi	18:6a4db94011d3	2333	#define CAP_POSTERIZE_VCOMP_Msk (0xfful << CAP_POSTERIZE_VCOMP_Pos) /!< CAP POSTERIZE: VCOMP Mask /
sahilmgandhi	18:6a4db94011d3	2334
sahilmgandhi	18:6a4db94011d3	2335	#define CAP_POSTERIZE_UCOMP_Pos (8) /!< CAP POSTERIZE: UCOMP Position /
sahilmgandhi	18:6a4db94011d3	2336	#define CAP_POSTERIZE_UCOMP_Msk (0xfful << CAP_POSTERIZE_UCOMP_Pos) /!< CAP POSTERIZE: UCOMP Mask /
sahilmgandhi	18:6a4db94011d3	2337
sahilmgandhi	18:6a4db94011d3	2338	#define CAP_POSTERIZE_YCOMP_Pos (16) /!< CAP POSTERIZE: YCOMP Position /
sahilmgandhi	18:6a4db94011d3	2339	#define CAP_POSTERIZE_YCOMP_Msk (0xfful << CAP_POSTERIZE_YCOMP_Pos) /!< CAP POSTERIZE: YCOMP Mask /
sahilmgandhi	18:6a4db94011d3	2340
sahilmgandhi	18:6a4db94011d3	2341	#define CAP_MD_MDEN_Pos (0) /!< CAP MD: MDEN Position /
sahilmgandhi	18:6a4db94011d3	2342	#define CAP_MD_MDEN_Msk (0x1ul << CAP_MD_MDEN_Pos) /!< CAP MD: MDEN Mask /
sahilmgandhi	18:6a4db94011d3	2343
sahilmgandhi	18:6a4db94011d3	2344	#define CAP_MD_MDBS_Pos (8) /!< CAP MD: MDBS Position /
sahilmgandhi	18:6a4db94011d3	2345	#define CAP_MD_MDBS_Msk (0x1ul << CAP_MD_MDBS_Pos) /!< CAP MD: MDBS Mask /
sahilmgandhi	18:6a4db94011d3	2346
sahilmgandhi	18:6a4db94011d3	2347	#define CAP_MD_MDSM_Pos (9) /!< CAP MD: MDSM Position /
sahilmgandhi	18:6a4db94011d3	2348	#define CAP_MD_MDSM_Msk (0x1ul << CAP_MD_MDSM_Pos) /!< CAP MD: MDSM Mask /
sahilmgandhi	18:6a4db94011d3	2349
sahilmgandhi	18:6a4db94011d3	2350	#define CAP_MD_MDDF_Pos (10) /!< CAP MD: MDDF Position /
sahilmgandhi	18:6a4db94011d3	2351	#define CAP_MD_MDDF_Msk (0x3ul << CAP_MD_MDDF_Pos) /!< CAP MD: MDDF Mask /
sahilmgandhi	18:6a4db94011d3	2352
sahilmgandhi	18:6a4db94011d3	2353	#define CAP_MD_MDTHR_Pos (16) /!< CAP MD: MDTHR Position /
sahilmgandhi	18:6a4db94011d3	2354	#define CAP_MD_MDTHR_Msk (0x1ful << CAP_MD_MDTHR_Pos) /!< CAP MD: MDTHR Mask /
sahilmgandhi	18:6a4db94011d3	2355
sahilmgandhi	18:6a4db94011d3	2356	#define CAP_MDADDR_MDADDR_Pos (0) /!< CAP MDADDR: MDADDR Position /
sahilmgandhi	18:6a4db94011d3	2357	#define CAP_MDADDR_MDADDR_Msk (0xfffffffful << CAP_MDADDR_MDADDR_Pos) /!< CAP MDADDR: MDADDR Mask /
sahilmgandhi	18:6a4db94011d3	2358
sahilmgandhi	18:6a4db94011d3	2359	#define CAP_MDYADDR_MDYADDR_Pos (0) /!< CAP MDYADDR: MDYADDR Position /
sahilmgandhi	18:6a4db94011d3	2360	#define CAP_MDYADDR_MDYADDR_Msk (0xfffffffful << CAP_MDYADDR_MDYADDR_Pos) /!< CAP MDYADDR: MDYADDR Mask /
sahilmgandhi	18:6a4db94011d3	2361
sahilmgandhi	18:6a4db94011d3	2362	#define CAP_SEPIA_VCOMP_Pos (0) /!< CAP SEPIA: VCOMP Position /
sahilmgandhi	18:6a4db94011d3	2363	#define CAP_SEPIA_VCOMP_Msk (0xfful << CAP_SEPIA_VCOMP_Pos) /!< CAP SEPIA: VCOMP Mask /
sahilmgandhi	18:6a4db94011d3	2364
sahilmgandhi	18:6a4db94011d3	2365	#define CAP_SEPIA_UCOMP_Pos (8) /!< CAP SEPIA: UCOMP Position /
sahilmgandhi	18:6a4db94011d3	2366	#define CAP_SEPIA_UCOMP_Msk (0xfful << CAP_SEPIA_UCOMP_Pos) /!< CAP SEPIA: UCOMP Mask /
sahilmgandhi	18:6a4db94011d3	2367
sahilmgandhi	18:6a4db94011d3	2368	#define CAP_CWSP_CWSADDRH_Pos (0) /!< CAP CWSP: CWSADDRH Position /
sahilmgandhi	18:6a4db94011d3	2369	#define CAP_CWSP_CWSADDRH_Msk (0xffful << CAP_CWSP_CWSADDRH_Pos) /!< CAP CWSP: CWSADDRH Mask /
sahilmgandhi	18:6a4db94011d3	2370
sahilmgandhi	18:6a4db94011d3	2371	#define CAP_CWSP_CWSADDRV_Pos (16) /!< CAP CWSP: CWSADDRV Position /
sahilmgandhi	18:6a4db94011d3	2372	#define CAP_CWSP_CWSADDRV_Msk (0x7fful << CAP_CWSP_CWSADDRV_Pos) /!< CAP CWSP: CWSADDRV Mask /
sahilmgandhi	18:6a4db94011d3	2373
sahilmgandhi	18:6a4db94011d3	2374	#define CAP_CWS_CWW_Pos (0) /!< CAP CWS: CWW Position /
sahilmgandhi	18:6a4db94011d3	2375	#define CAP_CWS_CWW_Msk (0xffful << CAP_CWS_CWW_Pos) /!< CAP CWS: CWW Mask /
sahilmgandhi	18:6a4db94011d3	2376
sahilmgandhi	18:6a4db94011d3	2377	#define CAP_CWS_CWH_Pos (16) /!< CAP CWS: CIWH Position /
sahilmgandhi	18:6a4db94011d3	2378	#define CAP_CWS_CWH_Msk (0x7fful << CAP_CWS_CWH_Pos) /!< CAP CWS: CIWH Mask /
sahilmgandhi	18:6a4db94011d3	2379
sahilmgandhi	18:6a4db94011d3	2380	#define CAP_PKTSL_PKTSHML_Pos (0) /!< CAP PKTSL: PKTSHML Position /
sahilmgandhi	18:6a4db94011d3	2381	#define CAP_PKTSL_PKTSHML_Msk (0xfful << CAP_PKTSL_PKTSHML_Pos) /!< CAP PKTSL: PKTSHML Mask /
sahilmgandhi	18:6a4db94011d3	2382
sahilmgandhi	18:6a4db94011d3	2383	#define CAP_PKTSL_PKTSHNL_Pos (8) /!< CAP PKTSL: PKTSHNL Position /
sahilmgandhi	18:6a4db94011d3	2384	#define CAP_PKTSL_PKTSHNL_Msk (0xfful << CAP_PKTSL_PKTSHNL_Pos) /!< CAP PKTSL: PKTSHNL Mask /
sahilmgandhi	18:6a4db94011d3	2385
sahilmgandhi	18:6a4db94011d3	2386	#define CAP_PKTSL_PKTSVML_Pos (16) /!< CAP PKTSL: PKTSVML Position /
sahilmgandhi	18:6a4db94011d3	2387	#define CAP_PKTSL_PKTSVML_Msk (0xfful << CAP_PKTSL_PKTSVML_Pos) /!< CAP PKTSL: PKTSVML Mask /
sahilmgandhi	18:6a4db94011d3	2388
sahilmgandhi	18:6a4db94011d3	2389	#define CAP_PKTSL_PKTSVNL_Pos (24) /!< CAP PKTSL: PKTSVNL Position /
sahilmgandhi	18:6a4db94011d3	2390	#define CAP_PKTSL_PKTSVNL_Msk (0xfful << CAP_PKTSL_PKTSVNL_Pos) /!< CAP PKTSL: PKTSVNL Mask /
sahilmgandhi	18:6a4db94011d3	2391
sahilmgandhi	18:6a4db94011d3	2392	#define CAP_PLNSL_PLNSHML_Pos (0) /!< CAP PLNSL: PLNSHML Position /
sahilmgandhi	18:6a4db94011d3	2393	#define CAP_PLNSL_PLNSHML_Msk (0xfful << CAP_PLNSL_PLNSHML_Pos) /!< CAP PLNSL: PLNSHML Mask /
sahilmgandhi	18:6a4db94011d3	2394
sahilmgandhi	18:6a4db94011d3	2395	#define CAP_PLNSL_PLNSHNL_Pos (8) /!< CAP PLNSL: PLNSHNL Position /
sahilmgandhi	18:6a4db94011d3	2396	#define CAP_PLNSL_PLNSHNL_Msk (0xfful << CAP_PLNSL_PLNSHNL_Pos) /!< CAP PLNSL: PLNSHNL Mask /
sahilmgandhi	18:6a4db94011d3	2397
sahilmgandhi	18:6a4db94011d3	2398	#define CAP_PLNSL_PLNSVML_Pos (16) /!< CAP PLNSL: PLNSVML Position /
sahilmgandhi	18:6a4db94011d3	2399	#define CAP_PLNSL_PLNSVML_Msk (0xfful << CAP_PLNSL_PLNSVML_Pos) /!< CAP PLNSL: PLNSVML Mask /
sahilmgandhi	18:6a4db94011d3	2400
sahilmgandhi	18:6a4db94011d3	2401	#define CAP_PLNSL_PLNSVNL_Pos (24) /!< CAP PLNSL: PLNSVNL Position /
sahilmgandhi	18:6a4db94011d3	2402	#define CAP_PLNSL_PLNSVNL_Msk (0xfful << CAP_PLNSL_PLNSVNL_Pos) /!< CAP PLNSL: PLNSVNL Mask /
sahilmgandhi	18:6a4db94011d3	2403
sahilmgandhi	18:6a4db94011d3	2404	#define CAP_FRCTL_FRM_Pos (0) /!< CAP FRCTL: FRM Position /
sahilmgandhi	18:6a4db94011d3	2405	#define CAP_FRCTL_FRM_Msk (0x3ful << CAP_FRCTL_FRM_Pos) /!< CAP FRCTL: FRM Mask /
sahilmgandhi	18:6a4db94011d3	2406
sahilmgandhi	18:6a4db94011d3	2407	#define CAP_FRCTL_FRN_Pos (8) /!< CAP FRCTL: FRN Position /
sahilmgandhi	18:6a4db94011d3	2408	#define CAP_FRCTL_FRN_Msk (0x3ful << CAP_FRCTL_FRN_Pos) /!< CAP FRCTL: FRN Mask /
sahilmgandhi	18:6a4db94011d3	2409
sahilmgandhi	18:6a4db94011d3	2410	#define CAP_STRIDE_PKTSTRIDE_Pos (0) /!< CAP STRIDE: PKTSTRIDE Position /
sahilmgandhi	18:6a4db94011d3	2411	#define CAP_STRIDE_PKTSTRIDE_Msk (0x3ffful << CAP_STRIDE_PKTSTRIDE_Pos) /!< CAP STRIDE: PKTSTRIDE Mask /
sahilmgandhi	18:6a4db94011d3	2412
sahilmgandhi	18:6a4db94011d3	2413	#define CAP_STRIDE_PLNSTRIDE_Pos (16) /!< CAP STRIDE: PLNSTRIDE Position /
sahilmgandhi	18:6a4db94011d3	2414	#define CAP_STRIDE_PLNSTRIDE_Msk (0x3ffful << CAP_STRIDE_PLNSTRIDE_Pos) /!< CAP STRIDE: PLNSTRIDE Mask /
sahilmgandhi	18:6a4db94011d3	2415
sahilmgandhi	18:6a4db94011d3	2416	#define CAP_FIFOTH_PLNVFTH_Pos (0) /!< CAP FIFOTH: PLNVFTH Position /
sahilmgandhi	18:6a4db94011d3	2417	#define CAP_FIFOTH_PLNVFTH_Msk (0xful << CAP_FIFOTH_PLNVFTH_Pos) /!< CAP FIFOTH: PLNVFTH Mask /
sahilmgandhi	18:6a4db94011d3	2418
sahilmgandhi	18:6a4db94011d3	2419	#define CAP_FIFOTH_PLNUFTH_Pos (8) /!< CAP FIFOTH: PLNUFTH Position /
sahilmgandhi	18:6a4db94011d3	2420	#define CAP_FIFOTH_PLNUFTH_Msk (0xful << CAP_FIFOTH_PLNUFTH_Pos) /!< CAP FIFOTH: PLNUFTH Mask /
sahilmgandhi	18:6a4db94011d3	2421
sahilmgandhi	18:6a4db94011d3	2422	#define CAP_FIFOTH_PLNYFTH_Pos (16) /!< CAP FIFOTH: PLNYFTH Position /
sahilmgandhi	18:6a4db94011d3	2423	#define CAP_FIFOTH_PLNYFTH_Msk (0x1ful << CAP_FIFOTH_PLNYFTH_Pos) /!< CAP FIFOTH: PLNYFTH Mask /
sahilmgandhi	18:6a4db94011d3	2424
sahilmgandhi	18:6a4db94011d3	2425	#define CAP_FIFOTH_PKTFTH_Pos (24) /!< CAP FIFOTH: PKTFTH Position /
sahilmgandhi	18:6a4db94011d3	2426	#define CAP_FIFOTH_PKTFTH_Msk (0x1ful << CAP_FIFOTH_PKTFTH_Pos) /!< CAP FIFOTH: PKTFTH Mask /
sahilmgandhi	18:6a4db94011d3	2427
sahilmgandhi	18:6a4db94011d3	2428	#define CAP_FIFOTH_OVF_Pos (31) /!< CAP FIFOTH: OVF Position /
sahilmgandhi	18:6a4db94011d3	2429	#define CAP_FIFOTH_OVF_Msk (0x1ul << CAP_FIFOTH_OVF_Pos) /!< CAP FIFOTH: OVF Mask /
sahilmgandhi	18:6a4db94011d3	2430
sahilmgandhi	18:6a4db94011d3	2431	#define CAP_CMPADDR_CMPADDR_Pos (0) /!< CAP CMPADDR: CMPADDR Position /
sahilmgandhi	18:6a4db94011d3	2432	#define CAP_CMPADDR_CMPADDR_Msk (0xfffffffful << CAP_CMPADDR_CMPADDR_Pos) /!< CAP CMPADDR: CMPADDR Mask /
sahilmgandhi	18:6a4db94011d3	2433
sahilmgandhi	18:6a4db94011d3	2434	#define CAP_PKTSM_PKTSHMH_Pos (0) /!< CAP PKTSM: PKTSHMH Position /
sahilmgandhi	18:6a4db94011d3	2435	#define CAP_PKTSM_PKTSHMH_Msk (0xfful << CAP_PKTSM_PKTSHMH_Pos) /!< CAP PKTSM: PKTSHMH Mask /
sahilmgandhi	18:6a4db94011d3	2436
sahilmgandhi	18:6a4db94011d3	2437	#define CAP_PKTSM_PKTSHNH_Pos (8) /!< CAP PKTSM: PKTSHNH Position /
sahilmgandhi	18:6a4db94011d3	2438	#define CAP_PKTSM_PKTSHNH_Msk (0xfful << CAP_PKTSM_PKTSHNH_Pos) /!< CAP PKTSM: PKTSHNH Mask /
sahilmgandhi	18:6a4db94011d3	2439
sahilmgandhi	18:6a4db94011d3	2440	#define CAP_PKTSM_PKTSVMH_Pos (16) /!< CAP PKTSM: PKTSVMH Position /
sahilmgandhi	18:6a4db94011d3	2441	#define CAP_PKTSM_PKTSVMH_Msk (0xfful << CAP_PKTSM_PKTSVMH_Pos) /!< CAP PKTSM: PKTSVMH Mask /
sahilmgandhi	18:6a4db94011d3	2442
sahilmgandhi	18:6a4db94011d3	2443	#define CAP_PKTSM_PKTSVNH_Pos (24) /!< CAP PKTSM: PKTSVNH Position /
sahilmgandhi	18:6a4db94011d3	2444	#define CAP_PKTSM_PKTSVNH_Msk (0xfful << CAP_PKTSM_PKTSVNH_Pos) /!< CAP PKTSM: PKTSVNH Mask /
sahilmgandhi	18:6a4db94011d3	2445
sahilmgandhi	18:6a4db94011d3	2446	#define CAP_PLNSM_PLNSHMH_Pos (0) /!< CAP PLNSM: PLNSHMH Position /
sahilmgandhi	18:6a4db94011d3	2447	#define CAP_PLNSM_PLNSHMH_Msk (0xfful << CAP_PLNSM_PLNSHMH_Pos) /!< CAP PLNSM: PLNSHMH Mask /
sahilmgandhi	18:6a4db94011d3	2448
sahilmgandhi	18:6a4db94011d3	2449	#define CAP_PLNSM_PLNSHNH_Pos (8) /!< CAP PLNSM: PLNSHNH Position /
sahilmgandhi	18:6a4db94011d3	2450	#define CAP_PLNSM_PLNSHNH_Msk (0xfful << CAP_PLNSM_PLNSHNH_Pos) /!< CAP PLNSM: PLNSHNH Mask /
sahilmgandhi	18:6a4db94011d3	2451
sahilmgandhi	18:6a4db94011d3	2452	#define CAP_PLNSM_PLNSVMH_Pos (16) /!< CAP PLNSM: PLNSVMH Position /
sahilmgandhi	18:6a4db94011d3	2453	#define CAP_PLNSM_PLNSVMH_Msk (0xfful << CAP_PLNSM_PLNSVMH_Pos) /!< CAP PLNSM: PLNSVMH Mask /
sahilmgandhi	18:6a4db94011d3	2454
sahilmgandhi	18:6a4db94011d3	2455	#define CAP_PLNSM_PLNSVNH_Pos (24) /!< CAP PLNSM: PLNSVNH Position /
sahilmgandhi	18:6a4db94011d3	2456	#define CAP_PLNSM_PLNSVNH_Msk (0xfful << CAP_PLNSM_PLNSVNH_Pos) /!< CAP PLNSM: PLNSVNH Mask /
sahilmgandhi	18:6a4db94011d3	2457
sahilmgandhi	18:6a4db94011d3	2458	#define CAP_CURADDRP_CURADDR_Pos (0) /!< CAP CURADDRP: CURADDR Position /
sahilmgandhi	18:6a4db94011d3	2459	#define CAP_CURADDRP_CURADDR_Msk (0xfffffffful << CAP_CURADDRP_CURADDR_Pos) /!< CAP CURADDRP: CURADDR Mask /
sahilmgandhi	18:6a4db94011d3	2460
sahilmgandhi	18:6a4db94011d3	2461	#define CAP_CURADDRY_CURADDR_Pos (0) /!< CAP CURADDRY: CURADDR Position /
sahilmgandhi	18:6a4db94011d3	2462	#define CAP_CURADDRY_CURADDR_Msk (0xfffffffful << CAP_CURADDRY_CURADDR_Pos) /!< CAP CURADDRY: CURADDR Mask /
sahilmgandhi	18:6a4db94011d3	2463
sahilmgandhi	18:6a4db94011d3	2464	#define CAP_CURADDRU_CURADDR_Pos (0) /!< CAP CURADDRU: CURADDR Position /
sahilmgandhi	18:6a4db94011d3	2465	#define CAP_CURADDRU_CURADDR_Msk (0xfffffffful << CAP_CURADDRU_CURADDR_Pos) /!< CAP CURADDRU: CURADDR Mask /
sahilmgandhi	18:6a4db94011d3	2466
sahilmgandhi	18:6a4db94011d3	2467	#define CAP_CURVADDR_CURADDR_Pos (0) /!< CAP CURVADDR: CURADDR Position /
sahilmgandhi	18:6a4db94011d3	2468	#define CAP_CURVADDR_CURADDR_Msk (0xfffffffful << CAP_CURVADDR_CURADDR_Pos) /!< CAP CURVADDR: CURADDR Mask /
sahilmgandhi	18:6a4db94011d3	2469
sahilmgandhi	18:6a4db94011d3	2470	#define CAP_PKTBA0_BASEADDR_Pos (0) /!< CAP PKTBA0: BASEADDR Position /
sahilmgandhi	18:6a4db94011d3	2471	#define CAP_PKTBA0_BASEADDR_Msk (0xfffffffful << CAP_PKTBA0_BASEADDR_Pos) /!< CAP PKTBA0: BASEADDR Mask /
sahilmgandhi	18:6a4db94011d3	2472
sahilmgandhi	18:6a4db94011d3	2473	#define CAP_PKTBA1_BASEADDR_Pos (0) /!< CAP PKTBA1: BASEADDR Position /
sahilmgandhi	18:6a4db94011d3	2474	#define CAP_PKTBA1_BASEADDR_Msk (0xfffffffful << CAP_PKTBA1_BASEADDR_Pos) /!< CAP PKTBA1: BASEADDR Mask /
sahilmgandhi	18:6a4db94011d3	2475
sahilmgandhi	18:6a4db94011d3	2476	#define CAP_YBA_BASEADDR_Pos (0) /!< CAP YBA: BASEADDR Position /
sahilmgandhi	18:6a4db94011d3	2477	#define CAP_YBA_BASEADDR_Msk (0xfffffffful << CAP_YBA_BASEADDR_Pos) /!< CAP YBA: BASEADDR Mask /
sahilmgandhi	18:6a4db94011d3	2478
sahilmgandhi	18:6a4db94011d3	2479	#define CAP_UBA_BASEADDR_Pos (0) /!< CAP UBA: BASEADDR Position /
sahilmgandhi	18:6a4db94011d3	2480	#define CAP_UBA_BASEADDR_Msk (0xfffffffful << CAP_UBA_BASEADDR_Pos) /!< CAP UBA: BASEADDR Mask /
sahilmgandhi	18:6a4db94011d3	2481
sahilmgandhi	18:6a4db94011d3	2482	#define CAP_VBA_BASEADDR_Pos (0) /!< CAP VBA: BASEADDR Position /
sahilmgandhi	18:6a4db94011d3	2483	#define CAP_VBA_BASEADDR_Msk (0xfffffffful << CAP_VBA_BASEADDR_Pos) /!< CAP VBA: BASEADDR Mask /
sahilmgandhi	18:6a4db94011d3	2484
sahilmgandhi	18:6a4db94011d3	2485	/*@}/ /* CAP_CONST */
sahilmgandhi	18:6a4db94011d3	2486	/*@}/ /* end of CAP register group */
sahilmgandhi	18:6a4db94011d3	2487
sahilmgandhi	18:6a4db94011d3	2488
sahilmgandhi	18:6a4db94011d3	2489	/---------------------- Enhanced Input Capture Timer -------------------------/
sahilmgandhi	18:6a4db94011d3	2490	/**
sahilmgandhi	18:6a4db94011d3	2491	@addtogroup ECAP Enhanced Input Capture Timer(ECAP)
sahilmgandhi	18:6a4db94011d3	2492	Memory Mapped Structure for ECAP Controller
sahilmgandhi	18:6a4db94011d3	2493	@{ */
sahilmgandhi	18:6a4db94011d3	2494
sahilmgandhi	18:6a4db94011d3	2495	typedef struct {
sahilmgandhi	18:6a4db94011d3	2496
sahilmgandhi	18:6a4db94011d3	2497
sahilmgandhi	18:6a4db94011d3	2498	/**
sahilmgandhi	18:6a4db94011d3	2499	* CNT
sahilmgandhi	18:6a4db94011d3	2500	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	2501	* Offset: 0x00 Input Capture Counter (24-bit up counter)
sahilmgandhi	18:6a4db94011d3	2502	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	2503	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	2504	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	2505	* \|[0:23] \|VAL \|Input Capture Timer/Counter
sahilmgandhi	18:6a4db94011d3	2506	* \| \| \|The input Capture Timer/Counter is a 24-bit up-counting counter.
sahilmgandhi	18:6a4db94011d3	2507	* \| \| \|The clock source for the counter is from the clock divider output which the CAP_CLK is software optionally divided by 1,4,16 or 32.
sahilmgandhi	18:6a4db94011d3	2508	*/
sahilmgandhi	18:6a4db94011d3	2509	__IO uint32_t CNT;
sahilmgandhi	18:6a4db94011d3	2510
sahilmgandhi	18:6a4db94011d3	2511	/**
sahilmgandhi	18:6a4db94011d3	2512	* HOLD0
sahilmgandhi	18:6a4db94011d3	2513	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	2514	* Offset: 0x04 Input Capture Counter Hold Register 0
sahilmgandhi	18:6a4db94011d3	2515	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	2516	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	2517	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	2518	* \|[0:23] \|VAL \|Input Capture Counter Hold Register
sahilmgandhi	18:6a4db94011d3	2519	* \| \| \|When an active input capture channel detects a valid edge signal change, the ECAP_CNT value is latched into the corresponding holding register.
sahilmgandhi	18:6a4db94011d3	2520	* \| \| \|Each input channel has itself holding register named by ECAP_HOLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
sahilmgandhi	18:6a4db94011d3	2521	*/
sahilmgandhi	18:6a4db94011d3	2522	__IO uint32_t HOLD0;
sahilmgandhi	18:6a4db94011d3	2523
sahilmgandhi	18:6a4db94011d3	2524	/**
sahilmgandhi	18:6a4db94011d3	2525	* HOLD1
sahilmgandhi	18:6a4db94011d3	2526	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	2527	* Offset: 0x08 Input Capture Counter Hold Register 1
sahilmgandhi	18:6a4db94011d3	2528	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	2529	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	2530	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	2531	* \|[0:23] \|VAL \|Input Capture Counter Hold Register
sahilmgandhi	18:6a4db94011d3	2532	* \| \| \|When an active input capture channel detects a valid edge signal change, the ECAP_CNT value is latched into the corresponding holding register.
sahilmgandhi	18:6a4db94011d3	2533	* \| \| \|Each input channel has itself holding register named by ECAP_HOLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
sahilmgandhi	18:6a4db94011d3	2534	*/
sahilmgandhi	18:6a4db94011d3	2535	__IO uint32_t HOLD1;
sahilmgandhi	18:6a4db94011d3	2536
sahilmgandhi	18:6a4db94011d3	2537	/**
sahilmgandhi	18:6a4db94011d3	2538	* HOLD2
sahilmgandhi	18:6a4db94011d3	2539	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	2540	* Offset: 0x0C Input Capture Counter Hold Register 2
sahilmgandhi	18:6a4db94011d3	2541	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	2542	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	2543	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	2544	* \|[0:23] \|VAL \|Input Capture Counter Hold Register
sahilmgandhi	18:6a4db94011d3	2545	* \| \| \|When an active input capture channel detects a valid edge signal change, the ECAP_CNT value is latched into the corresponding holding register.
sahilmgandhi	18:6a4db94011d3	2546	* \| \| \|Each input channel has itself holding register named by ECAP_HOLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
sahilmgandhi	18:6a4db94011d3	2547	*/
sahilmgandhi	18:6a4db94011d3	2548	__IO uint32_t HOLD2;
sahilmgandhi	18:6a4db94011d3	2549
sahilmgandhi	18:6a4db94011d3	2550	/**
sahilmgandhi	18:6a4db94011d3	2551	* CNTCMP
sahilmgandhi	18:6a4db94011d3	2552	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	2553	* Offset: 0x10 Input Capture Counter Compare Register
sahilmgandhi	18:6a4db94011d3	2554	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	2555	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	2556	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	2557	* \|[0:23] \|VAL \|Input Capture Counter Compare Register
sahilmgandhi	18:6a4db94011d3	2558	* \| \| \|If the compare function is enabled (CMPEN = 1), the compare register is loaded with the value that the compare function compares the capture counter (ECAP_CNT) with.
sahilmgandhi	18:6a4db94011d3	2559	* \| \| \|If the reload control is enabled (RLDEN = 1), an overflow event or capture events will trigger the hardware to reload ECAP_CNTCMP into ECAP_CNT.
sahilmgandhi	18:6a4db94011d3	2560	*/
sahilmgandhi	18:6a4db94011d3	2561	__IO uint32_t CNTCMP;
sahilmgandhi	18:6a4db94011d3	2562
sahilmgandhi	18:6a4db94011d3	2563	/**
sahilmgandhi	18:6a4db94011d3	2564	* CTL0
sahilmgandhi	18:6a4db94011d3	2565	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	2566	* Offset: 0x14 Input Capture Control Register 0
sahilmgandhi	18:6a4db94011d3	2567	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	2568	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	2569	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	2570	* \|[0:1] \|NFDIS \|Noise Filter Clock Pre-Divide Selection
sahilmgandhi	18:6a4db94011d3	2571	* \| \| \|To determine the sampling frequency of the Noise Filter clock
sahilmgandhi	18:6a4db94011d3	2572	* \| \| \|00 = CAP_CLK.
sahilmgandhi	18:6a4db94011d3	2573	* \| \| \|01 = CAP_CLK/2.
sahilmgandhi	18:6a4db94011d3	2574	* \| \| \|10 = CAP_CLK/4.
sahilmgandhi	18:6a4db94011d3	2575	* \| \| \|11 = CAP_CLK/16.
sahilmgandhi	18:6a4db94011d3	2576	* \|[3] \|CAPNF_DIS \|Input Capture Noise Filter Disable Control
sahilmgandhi	18:6a4db94011d3	2577	* \| \| \|0 = Noise filter of Input Capture Enabled.
sahilmgandhi	18:6a4db94011d3	2578	* \| \| \|1 = Noise filter of Input Capture Disabled.
sahilmgandhi	18:6a4db94011d3	2579	* \|[4] \|CAPEN0 \|Port Pin IC0 Input To Input Capture Unit Enable Control
sahilmgandhi	18:6a4db94011d3	2580	* \| \| \|0 = IC0 input to Input Capture Unit Disabled.
sahilmgandhi	18:6a4db94011d3	2581	* \| \| \|1 = IC0 input to Input Capture Unit Enabled.
sahilmgandhi	18:6a4db94011d3	2582	* \|[5] \|CAPEN1 \|Port Pin IC1 Input To Input Capture Unit Enable Control
sahilmgandhi	18:6a4db94011d3	2583	* \| \| \|0 = IC1 input to Input Capture Unit Disabled.
sahilmgandhi	18:6a4db94011d3	2584	* \| \| \|1 = IC1 input to Input Capture Unit Enabled.
sahilmgandhi	18:6a4db94011d3	2585	* \|[6] \|CAPEN2 \|Port Pin IC2 Input To Input Capture Unit Enable Control
sahilmgandhi	18:6a4db94011d3	2586	* \| \| \|0 = IC2 input to Input Capture Unit Disabled.
sahilmgandhi	18:6a4db94011d3	2587	* \| \| \|1 = IC2 input to Input Capture Unit Enabled.
sahilmgandhi	18:6a4db94011d3	2588	* \|[8:9] \|CAPSEL0 \|CAP0 Input Source Selection
sahilmgandhi	18:6a4db94011d3	2589	* \| \| \|00 = CAP0 input is from port pin IC0.
sahilmgandhi	18:6a4db94011d3	2590	* \| \| \|01 = CAP0 input is from signal CPO0 (Analog comparator 0 output).
sahilmgandhi	18:6a4db94011d3	2591	* \| \| \|10 = CAP0 input is from signal CHA of QEI controller unit x.
sahilmgandhi	18:6a4db94011d3	2592	* \| \| \|11 = CAP0 input is from signal OPDO0 (OP0 digital output).
sahilmgandhi	18:6a4db94011d3	2593	* \| \| \|Note: Input capture unit n matches QEI or comparator unit x, where x = 0~1.
sahilmgandhi	18:6a4db94011d3	2594	* \|[10:11] \|CAPSEL1 \|CAP1 Input Source Selection
sahilmgandhi	18:6a4db94011d3	2595	* \| \| \|00 = CAP1 input is from port pin IC1.
sahilmgandhi	18:6a4db94011d3	2596	* \| \| \|01 = CAP1 input is from signal CPO1 (Analog comparator 1 output).
sahilmgandhi	18:6a4db94011d3	2597	* \| \| \|10 = CAP1 input is from signal CHB of QEI controller unit x.
sahilmgandhi	18:6a4db94011d3	2598	* \| \| \|11 = CAP1 input is from signal OPDO1 (OP1 digital output).
sahilmgandhi	18:6a4db94011d3	2599	* \| \| \|Note: Input capture unit n matches QEI or comparator unit x, where x = 0~1.
sahilmgandhi	18:6a4db94011d3	2600	* \|[12:13] \|CAPSEL2 \|CAP2 Input Source Selection
sahilmgandhi	18:6a4db94011d3	2601	* \| \| \|00 = CAP2 input is from port pin IC2.
sahilmgandhi	18:6a4db94011d3	2602	* \| \| \|01 = CAP2 input is from signal CPO2 (Analog comparator 2 output).
sahilmgandhi	18:6a4db94011d3	2603	* \| \| \|10 = CAP2 input is from signal CHX of QEI controller unit x.
sahilmgandhi	18:6a4db94011d3	2604	* \| \| \|11 = CAP2 input is from signal ADCMPOx (ADC compare output x).
sahilmgandhi	18:6a4db94011d3	2605	* \| \| \|Note: Input capture unit n matches QEI or comparator unit x, where x = 0~1.
sahilmgandhi	18:6a4db94011d3	2606	* \|[16] \|CAPIEN0 \|Input Capture Channel 0 Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	2607	* \| \| \|0 = The flag CAPF0 can trigger Input Capture interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	2608	* \| \| \|1 = The flag CAPF0 can trigger Input Capture interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	2609	* \|[17] \|CAPIEN1 \|Input Capture Channel 1 Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	2610	* \| \| \|0 = The flag CAPF1 can trigger Input Capture interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	2611	* \| \| \|1 = The flag CAPF1 can trigger Input Capture interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	2612	* \|[18] \|CAPIEN2 \|Input Capture Channel 2 Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	2613	* \| \| \|0 = The flag CAPF2 can trigger Input Capture interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	2614	* \| \| \|1 = The flag CAPF2 can trigger Input Capture interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	2615	* \|[20] \|OVIEN \|OVF Trigger Input Capture Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	2616	* \| \| \|0 = The flag OVUNF can trigger Input Capture interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	2617	* \| \| \|1 = The flag OVUNF can trigger Input Capture interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	2618	* \|[21] \|CMPIEN \|CMPF Trigger Input Capture Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	2619	* \| \| \|0 = The flag CMPF can trigger Input Capture interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	2620	* \| \| \|1 = The flag CMPF can trigger Input Capture interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	2621	* \|[24] \|CNTEN \|Input Capture Counter Start
sahilmgandhi	18:6a4db94011d3	2622	* \| \| \|Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with capture clock input (CAP_CLK).
sahilmgandhi	18:6a4db94011d3	2623	* \| \| \|0 = ECAP_CNT stop counting.
sahilmgandhi	18:6a4db94011d3	2624	* \| \| \|1 = ECAP_CNT starts up-counting.
sahilmgandhi	18:6a4db94011d3	2625	* \|[25] \|CMPCLR \|Input Capture Counter Cleared By Compare-Match Control
sahilmgandhi	18:6a4db94011d3	2626	* \| \| \|If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAMCMPF = 1) occurs.
sahilmgandhi	18:6a4db94011d3	2627	* \| \| \|0 = Compare-match event (CAMCMPF) can clear capture counter (ECAP_CNT) Disabled.
sahilmgandhi	18:6a4db94011d3	2628	* \| \| \|1 = Compare-match event (CAMCMPF) can clear capture counter (ECAP_CNT) Enabled.
sahilmgandhi	18:6a4db94011d3	2629	* \|[26] \|CPTCLR \|Input Capture Counter Cleared By Capture Events Control
sahilmgandhi	18:6a4db94011d3	2630	* \| \| \|If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to zero when any one of capture events (CAPF0~3) occurs.
sahilmgandhi	18:6a4db94011d3	2631	* \| \| \|0 = Capture events (CAPF0~3) can clear capture counter (ECAP_CNT) Disabled.
sahilmgandhi	18:6a4db94011d3	2632	* \| \| \|1 = Capture events (CAPF0~3) can clear capture counter (ECAP_CNT) Enabled.
sahilmgandhi	18:6a4db94011d3	2633	* \|[27] \|RLDEN \|Reload Function Enable Control
sahilmgandhi	18:6a4db94011d3	2634	* \| \| \|Setting this bit to enable the reload function.
sahilmgandhi	18:6a4db94011d3	2635	* \| \| \|If the reload control is enabled, an overflow event (OVF) or capture events (CAPFx) will trigger the hardware to reload ECAP_CNTCMP into ECAP_CNT.
sahilmgandhi	18:6a4db94011d3	2636	* \| \| \|0 = The reload function Disabled.
sahilmgandhi	18:6a4db94011d3	2637	* \| \| \|1 = The reload function Enabled.
sahilmgandhi	18:6a4db94011d3	2638	* \|[28] \|CMPEN \|Compare Function Enable Control
sahilmgandhi	18:6a4db94011d3	2639	* \| \| \|The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CMPF will be set.
sahilmgandhi	18:6a4db94011d3	2640	* \| \| \|0 = The compare function Disabled.
sahilmgandhi	18:6a4db94011d3	2641	* \| \| \|1 = The compare function Enabled.
sahilmgandhi	18:6a4db94011d3	2642	* \|[29] \|CAPEN \|Input Capture Timer/Counter Enable Control
sahilmgandhi	18:6a4db94011d3	2643	* \| \| \|0 = Input Capture function Disabled.
sahilmgandhi	18:6a4db94011d3	2644	* \| \| \|1 = Input Capture function Enabled.
sahilmgandhi	18:6a4db94011d3	2645	*/
sahilmgandhi	18:6a4db94011d3	2646	__IO uint32_t CTL0;
sahilmgandhi	18:6a4db94011d3	2647
sahilmgandhi	18:6a4db94011d3	2648	/**
sahilmgandhi	18:6a4db94011d3	2649	* CTL1
sahilmgandhi	18:6a4db94011d3	2650	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	2651	* Offset: 0x18 Input Capture Control Register 1
sahilmgandhi	18:6a4db94011d3	2652	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	2653	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	2654	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	2655	* \|[0:1] \|EDGESEL0 \|Channel 0 Captured Edge Selection
sahilmgandhi	18:6a4db94011d3	2656	* \| \| \|Input capture can detect falling edge change only, rising edge change only or one of both edge change
sahilmgandhi	18:6a4db94011d3	2657	* \| \| \|00 = Detect rising edge.
sahilmgandhi	18:6a4db94011d3	2658	* \| \| \|01 = Detect falling edge.
sahilmgandhi	18:6a4db94011d3	2659	* \| \| \|1x = Detect either rising or falling edge.
sahilmgandhi	18:6a4db94011d3	2660	* \|[2:3] \|EDGESEL1 \|Channel 1 Captured Edge Selection
sahilmgandhi	18:6a4db94011d3	2661	* \| \| \|Input capture can detect falling edge change only, rising edge change only or one of both edge change
sahilmgandhi	18:6a4db94011d3	2662	* \| \| \|00 = Detect rising edge.
sahilmgandhi	18:6a4db94011d3	2663	* \| \| \|01 = Detect falling edge.
sahilmgandhi	18:6a4db94011d3	2664	* \| \| \|1x = Detect either rising or falling edge.
sahilmgandhi	18:6a4db94011d3	2665	* \|[4:5] \|EDGESEL2 \|Channel 2 Captured Edge Selection
sahilmgandhi	18:6a4db94011d3	2666	* \| \| \|Input capture can detect falling edge change or rising edge change only, or one of both edge changes.
sahilmgandhi	18:6a4db94011d3	2667	* \| \| \|00 = Detect rising edge.
sahilmgandhi	18:6a4db94011d3	2668	* \| \| \|01 = Detect falling edge.
sahilmgandhi	18:6a4db94011d3	2669	* \| \| \|1x = Detect either rising or falling edge.
sahilmgandhi	18:6a4db94011d3	2670	* \|[8:10] \|RLDSEL \|ECAP_CNT Reload Trigger Source Selection
sahilmgandhi	18:6a4db94011d3	2671	* \| \| \|If the reload function is enabled RLDEN (ECAP_CTL0[27]) = 1, when a reload trigger event comes, the ECAP_CNT is reloaded with ECAP_CNTCMP.
sahilmgandhi	18:6a4db94011d3	2672	* \| \| \|RLDSEL[2:0] determines the ECAP_CNT reload trigger source
sahilmgandhi	18:6a4db94011d3	2673	* \| \| \|000 = CAPF0.
sahilmgandhi	18:6a4db94011d3	2674	* \| \| \|001 = CAPF1.
sahilmgandhi	18:6a4db94011d3	2675	* \| \| \|010 = CAPF2.
sahilmgandhi	18:6a4db94011d3	2676	* \| \| \|100 = OVF.
sahilmgandhi	18:6a4db94011d3	2677	* \| \| \|Others = Reserved.
sahilmgandhi	18:6a4db94011d3	2678	* \|[12:14] \|CLKSEL \|Capture Timer Clock Divide Selection
sahilmgandhi	18:6a4db94011d3	2679	* \| \| \|The capture timer clock has a pre-divider with four divided options controlled by CLKSEL[1:0].
sahilmgandhi	18:6a4db94011d3	2680	* \| \| \|000 = CAP_CLK/1.
sahilmgandhi	18:6a4db94011d3	2681	* \| \| \|001 = CAP_CLK/4.
sahilmgandhi	18:6a4db94011d3	2682	* \| \| \|010 = CAP_CLK/16.
sahilmgandhi	18:6a4db94011d3	2683	* \| \| \|011 = CAP_CLK/32.
sahilmgandhi	18:6a4db94011d3	2684	* \| \| \|100 = CAP_CLK/64.
sahilmgandhi	18:6a4db94011d3	2685	* \| \| \|101 = CAP_CLK/96.
sahilmgandhi	18:6a4db94011d3	2686	* \| \| \|110 = CAP_CLK/112.
sahilmgandhi	18:6a4db94011d3	2687	* \| \| \|111 = CAP_CLK/128.
sahilmgandhi	18:6a4db94011d3	2688	* \|[16:17] \|SRCSEL \|Capture Timer/Counter Clock Source Selection
sahilmgandhi	18:6a4db94011d3	2689	* \| \| \|Select the capture timer/counter clock source.
sahilmgandhi	18:6a4db94011d3	2690	* \| \| \|00 = CAP_CLK (default).
sahilmgandhi	18:6a4db94011d3	2691	* \| \| \|01 = CAP0.
sahilmgandhi	18:6a4db94011d3	2692	* \| \| \|10 = CAP1.
sahilmgandhi	18:6a4db94011d3	2693	* \| \| \|11 = CAP2.
sahilmgandhi	18:6a4db94011d3	2694	*/
sahilmgandhi	18:6a4db94011d3	2695	__IO uint32_t CTL1;
sahilmgandhi	18:6a4db94011d3	2696
sahilmgandhi	18:6a4db94011d3	2697	/**
sahilmgandhi	18:6a4db94011d3	2698	* STATUS
sahilmgandhi	18:6a4db94011d3	2699	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	2700	* Offset: 0x1C Input Capture Status Register
sahilmgandhi	18:6a4db94011d3	2701	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	2702	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	2703	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	2704	* \|[0] \|CAPF0 \|Input Capture Channel 0 Captured Flag
sahilmgandhi	18:6a4db94011d3	2705	* \| \| \|When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPF0 to high.
sahilmgandhi	18:6a4db94011d3	2706	* \| \| \|0 = No valid edge change is detected at CAP0 input.
sahilmgandhi	18:6a4db94011d3	2707	* \| \| \|1 = A valid edge change is detected at CAP0 input.
sahilmgandhi	18:6a4db94011d3	2708	* \| \| \|Note: This bit is only cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	2709	* \|[1] \|CAPF1 \|Input Capture Channel 1 Captured Flag
sahilmgandhi	18:6a4db94011d3	2710	* \| \| \|When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPF1 to high.
sahilmgandhi	18:6a4db94011d3	2711	* \| \| \|0 = No valid edge change is detected at CAP1 input.
sahilmgandhi	18:6a4db94011d3	2712	* \| \| \|1 = A valid edge change is detected at CAP1 input.
sahilmgandhi	18:6a4db94011d3	2713	* \| \| \|Note: This bit is only cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	2714	* \|[2] \|CAPF2 \|Input Capture Channel 2 Captured Flag
sahilmgandhi	18:6a4db94011d3	2715	* \| \| \|When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPF2 to high.
sahilmgandhi	18:6a4db94011d3	2716	* \| \| \|0 = No valid edge change is detected at CAP2 input.
sahilmgandhi	18:6a4db94011d3	2717	* \| \| \|1 = A valid edge change is detected at CAP2 input.
sahilmgandhi	18:6a4db94011d3	2718	* \| \| \|Note: This bit is only cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	2719	* \|[4] \|CMPF \|Input Capture Compare-Match Flag
sahilmgandhi	18:6a4db94011d3	2720	* \| \| \|If the input capture compare function is enabled, the flag is set by hardware while capture counter (ECAP_CNT) up counts and reach to the ECAP_CNTCMP value.
sahilmgandhi	18:6a4db94011d3	2721	* \| \| \|0 = ECAP_CNT does not match with ECAP_CNTCMP value.
sahilmgandhi	18:6a4db94011d3	2722	* \| \| \|1 = ECAP_CNT counts to the same as ECAP_CNTCMP value.
sahilmgandhi	18:6a4db94011d3	2723	* \| \| \|Note: This bit is only cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	2724	* \|[5] \|OVF \|Input Capture Counter Overflow Flag
sahilmgandhi	18:6a4db94011d3	2725	* \| \| \|Flag is set by hardware when input capture up counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.
sahilmgandhi	18:6a4db94011d3	2726	* \| \| \|0 = No overflow occurs in ECAP_CNT.
sahilmgandhi	18:6a4db94011d3	2727	* \| \| \|1 = ECAP_CNT overflows.
sahilmgandhi	18:6a4db94011d3	2728	* \| \| \|Note: This bit is only cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	2729	*/
sahilmgandhi	18:6a4db94011d3	2730	__IO uint32_t STATUS;
sahilmgandhi	18:6a4db94011d3	2731
sahilmgandhi	18:6a4db94011d3	2732	} ECAP_T;
sahilmgandhi	18:6a4db94011d3	2733
sahilmgandhi	18:6a4db94011d3	2734	/**
sahilmgandhi	18:6a4db94011d3	2735	@addtogroup ECAP_CONST ECAP Bit Field Definition
sahilmgandhi	18:6a4db94011d3	2736	Constant Definitions for ECAP Controller
sahilmgandhi	18:6a4db94011d3	2737	@{ */
sahilmgandhi	18:6a4db94011d3	2738
sahilmgandhi	18:6a4db94011d3	2739	#define ECAP_CNT_VAL_Pos (0) /!< ECAP CNT: VAL Position /
sahilmgandhi	18:6a4db94011d3	2740	#define ECAP_CNT_VAL_Msk (0xfffffful << ECAP_CNT_VAL_Pos) /!< ECAP CNT: VAL Mask /
sahilmgandhi	18:6a4db94011d3	2741
sahilmgandhi	18:6a4db94011d3	2742	#define ECAP_HOLD0_VAL_Pos (0) /!< ECAP HOLD0: VAL Position /
sahilmgandhi	18:6a4db94011d3	2743	#define ECAP_HOLD0_VAL_Msk (0xfffffful << ECAP_HOLD0_VAL_Pos) /!< ECAP HOLD0: VAL Mask /
sahilmgandhi	18:6a4db94011d3	2744
sahilmgandhi	18:6a4db94011d3	2745	#define ECAP_HOLD1_VAL_Pos (0) /!< ECAP HOLD1: VAL Position /
sahilmgandhi	18:6a4db94011d3	2746	#define ECAP_HOLD1_VAL_Msk (0xfffffful << ECAP_HOLD1_VAL_Pos) /!< ECAP HOLD1: VAL Mask /
sahilmgandhi	18:6a4db94011d3	2747
sahilmgandhi	18:6a4db94011d3	2748	#define ECAP_HOLD2_VAL_Pos (0) /!< ECAP HOLD2: VAL Position /
sahilmgandhi	18:6a4db94011d3	2749	#define ECAP_HOLD2_VAL_Msk (0xfffffful << ECAP_HOLD2_VAL_Pos) /!< ECAP HOLD2: VAL Mask /
sahilmgandhi	18:6a4db94011d3	2750
sahilmgandhi	18:6a4db94011d3	2751	#define ECAP_CNTCMP_VAL_Pos (0) /!< ECAP CNTCMP: VAL Position /
sahilmgandhi	18:6a4db94011d3	2752	#define ECAP_CNTCMP_VAL_Msk (0xfffffful << ECAP_CNTCMP_VAL_Pos) /!< ECAP CNTCMP: VAL Mask /
sahilmgandhi	18:6a4db94011d3	2753
sahilmgandhi	18:6a4db94011d3	2754	#define ECAP_CTL0_NFDIS_Pos (0) /!< ECAP CTL0: NFDIS Position /
sahilmgandhi	18:6a4db94011d3	2755	#define ECAP_CTL0_NFDIS_Msk (0x3ul << ECAP_CTL0_NFDIS_Pos) /!< ECAP CTL0: NFDIS Mask /
sahilmgandhi	18:6a4db94011d3	2756
sahilmgandhi	18:6a4db94011d3	2757	#define ECAP_CTL0_CAPNF_DIS_Pos (3) /!< ECAP CTL0: CAPNF_DIS Position /
sahilmgandhi	18:6a4db94011d3	2758	#define ECAP_CTL0_CAPNF_DIS_Msk (0x1ul << ECAP_CTL0_CAPNF_DIS_Pos) /!< ECAP CTL0: CAPNF_DIS Mask /
sahilmgandhi	18:6a4db94011d3	2759
sahilmgandhi	18:6a4db94011d3	2760	#define ECAP_CTL0_CAPEN0_Pos (4) /!< ECAP CTL0: CAPEN0 Position /
sahilmgandhi	18:6a4db94011d3	2761	#define ECAP_CTL0_CAPEN0_Msk (0x1ul << ECAP_CTL0_CAPEN0_Pos) /!< ECAP CTL0: CAPEN0 Mask /
sahilmgandhi	18:6a4db94011d3	2762
sahilmgandhi	18:6a4db94011d3	2763	#define ECAP_CTL0_CAPEN1_Pos (5) /!< ECAP CTL0: CAPEN1 Position /
sahilmgandhi	18:6a4db94011d3	2764	#define ECAP_CTL0_CAPEN1_Msk (0x1ul << ECAP_CTL0_CAPEN1_Pos) /!< ECAP CTL0: CAPEN1 Mask /
sahilmgandhi	18:6a4db94011d3	2765
sahilmgandhi	18:6a4db94011d3	2766	#define ECAP_CTL0_CAPEN2_Pos (6) /!< ECAP CTL0: CAPEN2 Position /
sahilmgandhi	18:6a4db94011d3	2767	#define ECAP_CTL0_CAPEN2_Msk (0x1ul << ECAP_CTL0_CAPEN2_Pos) /!< ECAP CTL0: CAPEN2 Mask /
sahilmgandhi	18:6a4db94011d3	2768
sahilmgandhi	18:6a4db94011d3	2769	#define ECAP_CTL0_CAPSEL0_Pos (8) /!< ECAP CTL0: CAPSEL0 Position /
sahilmgandhi	18:6a4db94011d3	2770	#define ECAP_CTL0_CAPSEL0_Msk (0x3ul << ECAP_CTL0_CAPSEL0_Pos) /!< ECAP CTL0: CAPSEL0 Mask /
sahilmgandhi	18:6a4db94011d3	2771
sahilmgandhi	18:6a4db94011d3	2772	#define ECAP_CTL0_CAPSEL1_Pos (10) /!< ECAP CTL0: CAPSEL1 Position /
sahilmgandhi	18:6a4db94011d3	2773	#define ECAP_CTL0_CAPSEL1_Msk (0x3ul << ECAP_CTL0_CAPSEL1_Pos) /!< ECAP CTL0: CAPSEL1 Mask /
sahilmgandhi	18:6a4db94011d3	2774
sahilmgandhi	18:6a4db94011d3	2775	#define ECAP_CTL0_CAPSEL2_Pos (12) /!< ECAP CTL0: CAPSEL2 Position /
sahilmgandhi	18:6a4db94011d3	2776	#define ECAP_CTL0_CAPSEL2_Msk (0x3ul << ECAP_CTL0_CAPSEL2_Pos) /!< ECAP CTL0: CAPSEL2 Mask /
sahilmgandhi	18:6a4db94011d3	2777
sahilmgandhi	18:6a4db94011d3	2778	#define ECAP_CTL0_CAPIEN0_Pos (16) /!< ECAP CTL0: CAPIEN0 Position /
sahilmgandhi	18:6a4db94011d3	2779	#define ECAP_CTL0_CAPIEN0_Msk (0x1ul << ECAP_CTL0_CAPIEN0_Pos) /!< ECAP CTL0: CAPIEN0 Mask /
sahilmgandhi	18:6a4db94011d3	2780
sahilmgandhi	18:6a4db94011d3	2781	#define ECAP_CTL0_CAPIEN1_Pos (17) /!< ECAP CTL0: CAPIEN1 Position /
sahilmgandhi	18:6a4db94011d3	2782	#define ECAP_CTL0_CAPIEN1_Msk (0x1ul << ECAP_CTL0_CAPIEN1_Pos) /!< ECAP CTL0: CAPIEN1 Mask /
sahilmgandhi	18:6a4db94011d3	2783
sahilmgandhi	18:6a4db94011d3	2784	#define ECAP_CTL0_CAPIEN2_Pos (18) /!< ECAP CTL0: CAPIEN2 Position /
sahilmgandhi	18:6a4db94011d3	2785	#define ECAP_CTL0_CAPIEN2_Msk (0x1ul << ECAP_CTL0_CAPIEN2_Pos) /!< ECAP CTL0: CAPIEN2 Mask /
sahilmgandhi	18:6a4db94011d3	2786
sahilmgandhi	18:6a4db94011d3	2787	#define ECAP_CTL0_OVIEN_Pos (20) /!< ECAP CTL0: OVIEN Position /
sahilmgandhi	18:6a4db94011d3	2788	#define ECAP_CTL0_OVIEN_Msk (0x1ul << ECAP_CTL0_OVIEN_Pos) /!< ECAP CTL0: OVIEN Mask /
sahilmgandhi	18:6a4db94011d3	2789
sahilmgandhi	18:6a4db94011d3	2790	#define ECAP_CTL0_CMPIEN_Pos (21) /!< ECAP CTL0: CMPIEN Position /
sahilmgandhi	18:6a4db94011d3	2791	#define ECAP_CTL0_CMPIEN_Msk (0x1ul << ECAP_CTL0_CMPIEN_Pos) /!< ECAP CTL0: CMPIEN Mask /
sahilmgandhi	18:6a4db94011d3	2792
sahilmgandhi	18:6a4db94011d3	2793	#define ECAP_CTL0_CNTEN_Pos (24) /!< ECAP CTL0: CNTEN Position /
sahilmgandhi	18:6a4db94011d3	2794	#define ECAP_CTL0_CNTEN_Msk (0x1ul << ECAP_CTL0_CNTEN_Pos) /!< ECAP CTL0: CNTEN Mask /
sahilmgandhi	18:6a4db94011d3	2795
sahilmgandhi	18:6a4db94011d3	2796	#define ECAP_CTL0_CMPCLR_Pos (25) /!< ECAP CTL0: CMPCLR Position /
sahilmgandhi	18:6a4db94011d3	2797	#define ECAP_CTL0_CMPCLR_Msk (0x1ul << ECAP_CTL0_CMPCLR_Pos) /!< ECAP CTL0: CMPCLR Mask /
sahilmgandhi	18:6a4db94011d3	2798
sahilmgandhi	18:6a4db94011d3	2799	#define ECAP_CTL0_CPTCLR_Pos (26) /!< ECAP CTL0: CPTCLR Position /
sahilmgandhi	18:6a4db94011d3	2800	#define ECAP_CTL0_CPTCLR_Msk (0x1ul << ECAP_CTL0_CPTCLR_Pos) /!< ECAP CTL0: CPTCLR Mask /
sahilmgandhi	18:6a4db94011d3	2801
sahilmgandhi	18:6a4db94011d3	2802	#define ECAP_CTL0_RLDEN_Pos (27) /!< ECAP CTL0: RLDEN Position /
sahilmgandhi	18:6a4db94011d3	2803	#define ECAP_CTL0_RLDEN_Msk (0x1ul << ECAP_CTL0_RLDEN_Pos) /!< ECAP CTL0: RLDEN Mask /
sahilmgandhi	18:6a4db94011d3	2804
sahilmgandhi	18:6a4db94011d3	2805	#define ECAP_CTL0_CMPEN_Pos (28) /!< ECAP CTL0: CMPEN Position /
sahilmgandhi	18:6a4db94011d3	2806	#define ECAP_CTL0_CMPEN_Msk (0x1ul << ECAP_CTL0_CMPEN_Pos) /!< ECAP CTL0: CMPEN Mask /
sahilmgandhi	18:6a4db94011d3	2807
sahilmgandhi	18:6a4db94011d3	2808	#define ECAP_CTL0_CAPEN_Pos (29) /!< ECAP CTL0: CAPEN Position /
sahilmgandhi	18:6a4db94011d3	2809	#define ECAP_CTL0_CAPEN_Msk (0x1ul << ECAP_CTL0_CAPEN_Pos) /!< ECAP CTL0: CAPEN Mask /
sahilmgandhi	18:6a4db94011d3	2810
sahilmgandhi	18:6a4db94011d3	2811	#define ECAP_CTL1_EDGESEL0_Pos (0) /!< ECAP CTL1: EDGESEL0 Position /
sahilmgandhi	18:6a4db94011d3	2812	#define ECAP_CTL1_EDGESEL0_Msk (0x3ul << ECAP_CTL1_EDGESEL0_Pos) /!< ECAP CTL1: EDGESEL0 Mask /
sahilmgandhi	18:6a4db94011d3	2813
sahilmgandhi	18:6a4db94011d3	2814	#define ECAP_CTL1_EDGESEL1_Pos (2) /!< ECAP CTL1: EDGESEL1 Position /
sahilmgandhi	18:6a4db94011d3	2815	#define ECAP_CTL1_EDGESEL1_Msk (0x3ul << ECAP_CTL1_EDGESEL1_Pos) /!< ECAP CTL1: EDGESEL1 Mask /
sahilmgandhi	18:6a4db94011d3	2816
sahilmgandhi	18:6a4db94011d3	2817	#define ECAP_CTL1_EDGESEL2_Pos (4) /!< ECAP CTL1: EDGESEL2 Position /
sahilmgandhi	18:6a4db94011d3	2818	#define ECAP_CTL1_EDGESEL2_Msk (0x3ul << ECAP_CTL1_EDGESEL2_Pos) /!< ECAP CTL1: EDGESEL2 Mask /
sahilmgandhi	18:6a4db94011d3	2819
sahilmgandhi	18:6a4db94011d3	2820	#define ECAP_CTL1_RLDSEL_Pos (8) /!< ECAP CTL1: RLDSEL Position /
sahilmgandhi	18:6a4db94011d3	2821	#define ECAP_CTL1_RLDSEL_Msk (0x7ul << ECAP_CTL1_RLDSEL_Pos) /!< ECAP CTL1: RLDSEL Mask /
sahilmgandhi	18:6a4db94011d3	2822
sahilmgandhi	18:6a4db94011d3	2823	#define ECAP_CTL1_CLKSEL_Pos (12) /!< ECAP CTL1: CLKSEL Position /
sahilmgandhi	18:6a4db94011d3	2824	#define ECAP_CTL1_CLKSEL_Msk (0x7ul << ECAP_CTL1_CLKSEL_Pos) /!< ECAP CTL1: CLKSEL Mask /
sahilmgandhi	18:6a4db94011d3	2825
sahilmgandhi	18:6a4db94011d3	2826	#define ECAP_CTL1_SRCSEL_Pos (16) /!< ECAP CTL1: SRCSEL Position /
sahilmgandhi	18:6a4db94011d3	2827	#define ECAP_CTL1_SRCSEL_Msk (0x3ul << ECAP_CTL1_SRCSEL_Pos) /!< ECAP CTL1: SRCSEL Mask /
sahilmgandhi	18:6a4db94011d3	2828
sahilmgandhi	18:6a4db94011d3	2829	#define ECAP_STATUS_CAPF0_Pos (0) /!< ECAP STATUS: CAPF0 Position /
sahilmgandhi	18:6a4db94011d3	2830	#define ECAP_STATUS_CAPF0_Msk (0x1ul << ECAP_STATUS_CAPF0_Pos) /!< ECAP STATUS: CAPF0 Mask /
sahilmgandhi	18:6a4db94011d3	2831
sahilmgandhi	18:6a4db94011d3	2832	#define ECAP_STATUS_CAPF1_Pos (1) /!< ECAP STATUS: CAPF1 Position /
sahilmgandhi	18:6a4db94011d3	2833	#define ECAP_STATUS_CAPF1_Msk (0x1ul << ECAP_STATUS_CAPF1_Pos) /!< ECAP STATUS: CAPF1 Mask /
sahilmgandhi	18:6a4db94011d3	2834
sahilmgandhi	18:6a4db94011d3	2835	#define ECAP_STATUS_CAPF2_Pos (2) /!< ECAP STATUS: CAPF2 Position /
sahilmgandhi	18:6a4db94011d3	2836	#define ECAP_STATUS_CAPF2_Msk (0x1ul << ECAP_STATUS_CAPF2_Pos) /!< ECAP STATUS: CAPF2 Mask /
sahilmgandhi	18:6a4db94011d3	2837
sahilmgandhi	18:6a4db94011d3	2838	#define ECAP_STATUS_CMPF_Pos (4) /!< ECAP STATUS: CMPF Position /
sahilmgandhi	18:6a4db94011d3	2839	#define ECAP_STATUS_CMPF_Msk (0x1ul << ECAP_STATUS_CMPF_Pos) /!< ECAP STATUS: CMPF Mask /
sahilmgandhi	18:6a4db94011d3	2840
sahilmgandhi	18:6a4db94011d3	2841	#define ECAP_STATUS_OVF_Pos (5) /!< ECAP STATUS: OVF Position /
sahilmgandhi	18:6a4db94011d3	2842	#define ECAP_STATUS_OVF_Msk (0x1ul << ECAP_STATUS_OVF_Pos) /!< ECAP STATUS: OVF Mask /
sahilmgandhi	18:6a4db94011d3	2843
sahilmgandhi	18:6a4db94011d3	2844	/*@}/ /* ECAP_CONST */
sahilmgandhi	18:6a4db94011d3	2845	/*@}/ /* end of ECAP register group */
sahilmgandhi	18:6a4db94011d3	2846
sahilmgandhi	18:6a4db94011d3	2847
sahilmgandhi	18:6a4db94011d3	2848	/---------------------- System Clock Controller -------------------------/
sahilmgandhi	18:6a4db94011d3	2849	/**
sahilmgandhi	18:6a4db94011d3	2850	@addtogroup CLK System Clock Controller(CLK)
sahilmgandhi	18:6a4db94011d3	2851	Memory Mapped Structure for CLK Controller
sahilmgandhi	18:6a4db94011d3	2852	@{ */
sahilmgandhi	18:6a4db94011d3	2853
sahilmgandhi	18:6a4db94011d3	2854	typedef struct {
sahilmgandhi	18:6a4db94011d3	2855
sahilmgandhi	18:6a4db94011d3	2856
sahilmgandhi	18:6a4db94011d3	2857	/**
sahilmgandhi	18:6a4db94011d3	2858	* PWRCTL
sahilmgandhi	18:6a4db94011d3	2859	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	2860	* Offset: 0x00 System Power-down Control Register
sahilmgandhi	18:6a4db94011d3	2861	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	2862	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	2863	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	2864	* \|[0] \|HXTEN \|4~24 MHz External High-Speed Crystal Enable Control (Write Protect)
sahilmgandhi	18:6a4db94011d3	2865	* \| \| \|The bit default value is set by flash controller user configuration register config0 [26:24].
sahilmgandhi	18:6a4db94011d3	2866	* \| \| \|When the default clock source is from 4~24 MHz external high-speed crystal, this bit is set to 1 automatically
sahilmgandhi	18:6a4db94011d3	2867	* \| \| \|0 = HXT Disabled.
sahilmgandhi	18:6a4db94011d3	2868	* \| \| \|1 = HXT Enabled.
sahilmgandhi	18:6a4db94011d3	2869	* \|[1] \|LXTEN \|LXT Enable Control (Write Protect)
sahilmgandhi	18:6a4db94011d3	2870	* \| \| \|0 = LXT Disabled.
sahilmgandhi	18:6a4db94011d3	2871	* \| \| \|1 = LXT (Normal operation) Enabled.
sahilmgandhi	18:6a4db94011d3	2872	* \|[2] \|HIRCEN \|HIRC Enable Control (Write Protect)
sahilmgandhi	18:6a4db94011d3	2873	* \| \| \|0 = HIRC Disabled.
sahilmgandhi	18:6a4db94011d3	2874	* \| \| \|1 = HIRC Enabled.
sahilmgandhi	18:6a4db94011d3	2875	* \|[3] \|LIRCEN \|10 KHz Internal Low-Speed Oscillator Enable Control (Write Protect)
sahilmgandhi	18:6a4db94011d3	2876	* \| \| \|0 = LIRC Disabled.
sahilmgandhi	18:6a4db94011d3	2877	* \| \| \|1 = LIRC Enabled (default 1).
sahilmgandhi	18:6a4db94011d3	2878	* \|[4] \|PDWKDLY \|Wake-Up Delay Counter Enable Control (Write Protect)
sahilmgandhi	18:6a4db94011d3	2879	* \| \| \|When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
sahilmgandhi	18:6a4db94011d3	2880	* \| \| \|The delayed clock cycle is 4096 clock cycles when chip work at HXT, and 256 clock cycles when chip works at HIRC.
sahilmgandhi	18:6a4db94011d3	2881	* \| \| \|0 = Clock cycles delay Disabled.
sahilmgandhi	18:6a4db94011d3	2882	* \| \| \|1 = Clock cycles delay Enabled.
sahilmgandhi	18:6a4db94011d3	2883	* \|[5] \|PDWKIEN \|Power-Down Mode Wake-Up Interrupt Enable Control (Write Protect)
sahilmgandhi	18:6a4db94011d3	2884	* \| \| \|0 = Power-down Mode Wake-up Interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	2885	* \| \| \|1 = Power-down Mode Wake-up Interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	2886	* \| \| \|Note: The interrupt will occur when both PDWKIF and PDWKIEN are high.
sahilmgandhi	18:6a4db94011d3	2887	* \|[6] \|PDWKIF \|Power-Down Mode Wake-Up Interrupt Status
sahilmgandhi	18:6a4db94011d3	2888	* \| \| \|Set by "power-down wake-up event", it indicates that resume from Power-down mode"
sahilmgandhi	18:6a4db94011d3	2889	* \| \| \|The flag is set if the GPIO, USB, UART, WDT, CAN, ACMP, BOD, RTC or SDHOST wake-up occurred
sahilmgandhi	18:6a4db94011d3	2890	* \| \| \|Note1: Write 1 to clear the bit to 0.
sahilmgandhi	18:6a4db94011d3	2891	* \| \| \|Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
sahilmgandhi	18:6a4db94011d3	2892	* \|[7] \|PDEN \|System Power-Down Enable Control (Write Protect)
sahilmgandhi	18:6a4db94011d3	2893	* \| \| \|When this bit is set to 1, Power-down mode is enabled and chip power-down behavior will depend on the PDEN bit.
sahilmgandhi	18:6a4db94011d3	2894	* \| \| \|(a) If the PDEN is 0, then the chip enters Power-down mode immediately after
sahilmgandhi	18:6a4db94011d3	2895	* \| \| \|the PWR_DOWN_EN bit set. ( default)
sahilmgandhi	18:6a4db94011d3	2896	* \| \| \|(b) if the PDEN is 1, then the chip keeps active till the CPU sleep mode is also
sahilmgandhi	18:6a4db94011d3	2897	* \| \| \|active and then the chip enters Power-down mode
sahilmgandhi	18:6a4db94011d3	2898	* \| \| \|When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set
sahilmgandhi	18:6a4db94011d3	2899	* \| \| \|this bit again for next power-down.
sahilmgandhi	18:6a4db94011d3	2900	* \| \| \|In Power-down mode, HXT and the HIRC will be disabled in this mode, but the LXT and
sahilmgandhi	18:6a4db94011d3	2901	* \| \| \|LIRC are not controlled by Power-down mode.
sahilmgandhi	18:6a4db94011d3	2902	* \| \| \|In Power-down mode, the PLL and system clock are disabled, and ignored the clock
sahilmgandhi	18:6a4db94011d3	2903	* \| \| \|source selection. The clocks of peripheral are not controlled by Power-down mode, if the
sahilmgandhi	18:6a4db94011d3	2904	* \| \| \|peripheral clock source is from LXT or the LIRC.
sahilmgandhi	18:6a4db94011d3	2905	* \| \| \|0 = Chip operating normally or chip in idle mode by WFI command.
sahilmgandhi	18:6a4db94011d3	2906	* \| \| \|1 = Chip enters Power-down mode instant or waits CPU sleep command WFI.
sahilmgandhi	18:6a4db94011d3	2907	* \|[8] \|PDWTCPU \|This Bit Control The Power-Down Entry Condition (Write Protect)
sahilmgandhi	18:6a4db94011d3	2908	* \| \| \|0 = Chip enters Power-down mode when the PWR_DOWN_EN bit is set to 1.
sahilmgandhi	18:6a4db94011d3	2909	* \| \| \|1 = Chip enters Power-down mode when the both PDEN and PWR_DOWN_EN bits are set to 1 and CPU run WFI instruction.
sahilmgandhi	18:6a4db94011d3	2910	* \|[9] \|DBPDEN \|Chip Entering Power-Down Even ICE Connected
sahilmgandhi	18:6a4db94011d3	2911	* \| \| \|0 = Chip enters power-down disabled in Debug mode.
sahilmgandhi	18:6a4db94011d3	2912	* \| \| \|1 = Chip enters power-down enabled in Debug mode.
sahilmgandhi	18:6a4db94011d3	2913	*/
sahilmgandhi	18:6a4db94011d3	2914	__IO uint32_t PWRCTL;
sahilmgandhi	18:6a4db94011d3	2915
sahilmgandhi	18:6a4db94011d3	2916	/**
sahilmgandhi	18:6a4db94011d3	2917	* AHBCLK
sahilmgandhi	18:6a4db94011d3	2918	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	2919	* Offset: 0x04 AHB Devices Clock Enable Control Register
sahilmgandhi	18:6a4db94011d3	2920	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	2921	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	2922	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	2923	* \|[1] \|PDMACKEN \|PDMA Controller Clock Enable Control
sahilmgandhi	18:6a4db94011d3	2924	* \| \| \|0 = PDMA engine clock Disabled.
sahilmgandhi	18:6a4db94011d3	2925	* \| \| \|1 = PDMA engine clock Enabled.
sahilmgandhi	18:6a4db94011d3	2926	* \|[2] \|ISPCKEN \|Flash ISP Controller Clock Enable Control
sahilmgandhi	18:6a4db94011d3	2927	* \| \| \|0 = Flash ISP engine clock Disabled.
sahilmgandhi	18:6a4db94011d3	2928	* \| \| \|1 = Flash ISP engine clock Enabled.
sahilmgandhi	18:6a4db94011d3	2929	* \|[3] \|EBICKEN \|EBI Controller Clock Enable Control
sahilmgandhi	18:6a4db94011d3	2930	* \| \| \|0 = EBI engine clock Disabled.
sahilmgandhi	18:6a4db94011d3	2931	* \| \| \|1 = EBI engine clock Enabled.
sahilmgandhi	18:6a4db94011d3	2932	* \|[4] \|USBHCKEN \|USB HOST Controller Clock Enable Control
sahilmgandhi	18:6a4db94011d3	2933	* \| \| \|0 = USB HOST engine clock Disabled.
sahilmgandhi	18:6a4db94011d3	2934	* \| \| \|1 = USB HOST engine clock Enabled.
sahilmgandhi	18:6a4db94011d3	2935	* \|[5] \|EMACCKEN \|Ethernet Controller Clock Enable Control (NUC472 Only)
sahilmgandhi	18:6a4db94011d3	2936	* \| \| \|0 = Ethernet Controller engine clock Disabled.
sahilmgandhi	18:6a4db94011d3	2937	* \| \| \|1 = Ethernet Controller engine clock Enabled.
sahilmgandhi	18:6a4db94011d3	2938	* \|[6] \|SDHCKEN \|SDHOST Controller Clock Enable Control
sahilmgandhi	18:6a4db94011d3	2939	* \| \| \|0 = SDHOST engine clock Disabled.
sahilmgandhi	18:6a4db94011d3	2940	* \| \| \|1 = SDHOST engine clock Enabled.
sahilmgandhi	18:6a4db94011d3	2941	* \|[7] \|CRCCKEN \|CRC Generator Controller Clock Enable Control
sahilmgandhi	18:6a4db94011d3	2942	* \| \| \|0 = CRC engine clock Disabled.
sahilmgandhi	18:6a4db94011d3	2943	* \| \| \|1 = CRC engine clock Enabled.
sahilmgandhi	18:6a4db94011d3	2944	* \|[8] \|CAPCKEN \|Image Capture Interface Controller Clock Enable Control
sahilmgandhi	18:6a4db94011d3	2945	* \| \| \|0 = CAP controller's clock Disabled.
sahilmgandhi	18:6a4db94011d3	2946	* \| \| \|1 = CAP controller's clock Enabled.
sahilmgandhi	18:6a4db94011d3	2947	* \|[9] \|SENCKEN \|Sensor Clock Enable Control
sahilmgandhi	18:6a4db94011d3	2948	* \| \| \|0 = Sensor clock Disabled.
sahilmgandhi	18:6a4db94011d3	2949	* \| \| \|1 = Sensor clock Enabled.
sahilmgandhi	18:6a4db94011d3	2950	* \|[10] \|USBDCKEN \|USB 2.0 Device Clock Enable Control
sahilmgandhi	18:6a4db94011d3	2951	* \| \| \|0 = USB device controller's clock Disabled.
sahilmgandhi	18:6a4db94011d3	2952	* \| \| \|1 = USB device controller's clock Enabled.
sahilmgandhi	18:6a4db94011d3	2953	* \|[12] \|CRPTCKEN \|Cryptographic Accelerator Clock Enable Control
sahilmgandhi	18:6a4db94011d3	2954	* \| \| \|0 = Cryptographic Accelerator clock Disabled.
sahilmgandhi	18:6a4db94011d3	2955	* \| \| \|1 = Cryptographic Accelerator clock Enabled.
sahilmgandhi	18:6a4db94011d3	2956	*/
sahilmgandhi	18:6a4db94011d3	2957	__IO uint32_t AHBCLK;
sahilmgandhi	18:6a4db94011d3	2958
sahilmgandhi	18:6a4db94011d3	2959	/**
sahilmgandhi	18:6a4db94011d3	2960	* APBCLK0
sahilmgandhi	18:6a4db94011d3	2961	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	2962	* Offset: 0x08 APB Devices Clock Enable Control Register 0
sahilmgandhi	18:6a4db94011d3	2963	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	2964	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	2965	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	2966	* \|[0] \|WDTCKEN \|Watchdog Timer Clock Enable Control (Write Protect)
sahilmgandhi	18:6a4db94011d3	2967	* \| \| \|This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
sahilmgandhi	18:6a4db94011d3	2968	* \| \| \|Refer to the register REGWRPROT at address GCR_BA+0x100.
sahilmgandhi	18:6a4db94011d3	2969	* \| \| \|0 = Watchdog Timer Clock Disabled.
sahilmgandhi	18:6a4db94011d3	2970	* \| \| \|1 = Watchdog Timer Clock Enabled.
sahilmgandhi	18:6a4db94011d3	2971	* \|[1] \|RTCCKEN \|Real-Time-Clock APB Interface Clock Enable Control
sahilmgandhi	18:6a4db94011d3	2972	* \| \| \|This bit is used to control the RTC APB clock only, The RTC engine clock source is from the 32.768 kHz external low-speed crystal.
sahilmgandhi	18:6a4db94011d3	2973	* \| \| \|0 = RTC Clock Disabled.
sahilmgandhi	18:6a4db94011d3	2974	* \| \| \|1 = RTC Clock Enabled.
sahilmgandhi	18:6a4db94011d3	2975	* \|[2] \|TMR0CKEN \|Timer0 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	2976	* \| \| \|0 = Timer0 Clock Disabled.
sahilmgandhi	18:6a4db94011d3	2977	* \| \| \|1 = Timer0 Clock Enabled.
sahilmgandhi	18:6a4db94011d3	2978	* \|[3] \|TMR1CKEN \|Timer1 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	2979	* \| \| \|0 = Timer1 Clock Disabled.
sahilmgandhi	18:6a4db94011d3	2980	* \| \| \|1 = Timer1 Clock Enabled.
sahilmgandhi	18:6a4db94011d3	2981	* \|[4] \|TMR2CKEN \|Timer2 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	2982	* \| \| \|0 = Timer2 Clock Disabled.
sahilmgandhi	18:6a4db94011d3	2983	* \| \| \|1 = Timer2 Clock Enabled.
sahilmgandhi	18:6a4db94011d3	2984	* \|[5] \|TMR3CKEN \|Timer3 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	2985	* \| \| \|0 = Timer3 Clock Disabled.
sahilmgandhi	18:6a4db94011d3	2986	* \| \| \|1 = Timer3 Clock Enabled.
sahilmgandhi	18:6a4db94011d3	2987	* \|[6] \|CLKOCKEN \|Clock Output Enable Control
sahilmgandhi	18:6a4db94011d3	2988	* \| \| \|0 = Clock Output Disabled.
sahilmgandhi	18:6a4db94011d3	2989	* \| \| \|1 = Clock Output Enabled.
sahilmgandhi	18:6a4db94011d3	2990	* \|[7] \|ACMPCKEN \|Analog Comparator Clock Enable Control
sahilmgandhi	18:6a4db94011d3	2991	* \| \| \|0 = Analog Comparator Clock Disabled.
sahilmgandhi	18:6a4db94011d3	2992	* \| \| \|1 = Analog Comparator Clock Enabled.
sahilmgandhi	18:6a4db94011d3	2993	* \|[8] \|I2C0CKEN \|I2C0 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	2994	* \| \| \|0 = I2C0 Clock Disabled.
sahilmgandhi	18:6a4db94011d3	2995	* \| \| \|1 = I2C0 Clock Enabled.
sahilmgandhi	18:6a4db94011d3	2996	* \|[9] \|I2C1CKEN \|I2C1 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	2997	* \| \| \|0 = I2C1 Clock Disabled.
sahilmgandhi	18:6a4db94011d3	2998	* \| \| \|1 = I2C1 Clock Enabled.
sahilmgandhi	18:6a4db94011d3	2999	* \|[10] \|I2C2CKEN \|I2C2 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3000	* \| \| \|0 = I2C2 Clock Disabled.
sahilmgandhi	18:6a4db94011d3	3001	* \| \| \|1 = I2C2 Clock Enabled.
sahilmgandhi	18:6a4db94011d3	3002	* \|[11] \|I2C3CKEN \|I2C3 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3003	* \| \| \|0 = I2C3 Clock Disabled.
sahilmgandhi	18:6a4db94011d3	3004	* \| \| \|1 = I2C3 Clock Enabled.
sahilmgandhi	18:6a4db94011d3	3005	* \|[12] \|SPI0CKEN \|SPI0 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3006	* \| \| \|0 = SPI0 Clock Disabled.
sahilmgandhi	18:6a4db94011d3	3007	* \| \| \|1= SPI0 Clock Enabled.
sahilmgandhi	18:6a4db94011d3	3008	* \|[13] \|SPI1CKEN \|SPI1 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3009	* \| \| \|0 = SPI1 Clock Disabled.
sahilmgandhi	18:6a4db94011d3	3010	* \| \| \|1 = SPI1 Clock Enabled.
sahilmgandhi	18:6a4db94011d3	3011	* \|[14] \|SPI2CKEN \|SPI2 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3012	* \| \| \|0 = SPI2 Clock Disabled.
sahilmgandhi	18:6a4db94011d3	3013	* \| \| \|1 = SPI2 Clock Enabled.
sahilmgandhi	18:6a4db94011d3	3014	* \|[15] \|SPI3CKEN \|SPI3 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3015	* \| \| \|0 = SPI3 Clock Disabled.
sahilmgandhi	18:6a4db94011d3	3016	* \| \| \|1 = SPI3 Clock Enabled.
sahilmgandhi	18:6a4db94011d3	3017	* \|[16] \|UART0CKEN \|UART0 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3018	* \| \| \|0 = UART0 clock Disabled.
sahilmgandhi	18:6a4db94011d3	3019	* \| \| \|1 = UART0 clock Enabled.
sahilmgandhi	18:6a4db94011d3	3020	* \|[17] \|UART1CKEN \|UART1 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3021	* \| \| \|0 = UART1 clock Disabled.
sahilmgandhi	18:6a4db94011d3	3022	* \| \| \|1 = UART1 clock Enabled.
sahilmgandhi	18:6a4db94011d3	3023	* \|[18] \|UART2CKEN \|UART2 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3024	* \| \| \|0 = UART2 clock Disabled.
sahilmgandhi	18:6a4db94011d3	3025	* \| \| \|1 = UART2 clock Enabled.
sahilmgandhi	18:6a4db94011d3	3026	* \|[19] \|UART3CKEN \|UART3 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3027	* \| \| \|0 = UART3 clock Disabled.
sahilmgandhi	18:6a4db94011d3	3028	* \| \| \|1 = UART3 clock Enabled.
sahilmgandhi	18:6a4db94011d3	3029	* \|[20] \|UART4CKEN \|UART4 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3030	* \| \| \|0 = UART4 clock Disabled.
sahilmgandhi	18:6a4db94011d3	3031	* \| \| \|1 = UART4 clock Enabled.
sahilmgandhi	18:6a4db94011d3	3032	* \|[21] \|UART5CKEN \|UART5 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3033	* \| \| \|0 = UART5 clock Disabled.
sahilmgandhi	18:6a4db94011d3	3034	* \| \| \|1 = UART5 clock Enabled.
sahilmgandhi	18:6a4db94011d3	3035	* \|[24] \|CAN0CKEN \|CAN Bus Controller-0 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3036	* \| \| \|0 = CAN0 clock Disabled.
sahilmgandhi	18:6a4db94011d3	3037	* \| \| \|1 = CAN0 clock Enabled.
sahilmgandhi	18:6a4db94011d3	3038	* \|[25] \|CAN1CKEN \|CAN Bus Controller-1 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3039	* \| \| \|0 = CAN1 clock Disabled.
sahilmgandhi	18:6a4db94011d3	3040	* \| \| \|1 = CAN1 clock Enabled.
sahilmgandhi	18:6a4db94011d3	3041	* \|[26] \|OTGCKEN \|USB 2.0 OTG Device Controller Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3042	* \| \| \|0 = OTG clock Disabled.
sahilmgandhi	18:6a4db94011d3	3043	* \| \| \|1 = OTG clock Enabled.
sahilmgandhi	18:6a4db94011d3	3044	* \|[28] \|ADCCKEN \|Analog-Digital-Converter (ADC) Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3045	* \| \| \|0 = ADC clock Disabled.
sahilmgandhi	18:6a4db94011d3	3046	* \| \| \|1 = ADC clock Enabled.
sahilmgandhi	18:6a4db94011d3	3047	* \|[29] \|I2S0CKEN \|I2S0 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3048	* \| \| \|0 = I2S Clock Disabled.
sahilmgandhi	18:6a4db94011d3	3049	* \| \| \|1 = I2S Clock Enabled.
sahilmgandhi	18:6a4db94011d3	3050	* \|[30] \|I2S1CKEN \|I2S1 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3051	* \| \| \|0 = I2S1 Clock Disabled.
sahilmgandhi	18:6a4db94011d3	3052	* \| \| \|1 = I2S1 Clock Enabled.
sahilmgandhi	18:6a4db94011d3	3053	* \|[31] \|PS2CKEN \|PS/2 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3054	* \| \| \|0 = PS/2 clock Disabled.
sahilmgandhi	18:6a4db94011d3	3055	* \| \| \|1 = PS/2 clock Enabled.
sahilmgandhi	18:6a4db94011d3	3056	*/
sahilmgandhi	18:6a4db94011d3	3057	__IO uint32_t APBCLK0;
sahilmgandhi	18:6a4db94011d3	3058
sahilmgandhi	18:6a4db94011d3	3059	/**
sahilmgandhi	18:6a4db94011d3	3060	* APBCLK1
sahilmgandhi	18:6a4db94011d3	3061	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	3062	* Offset: 0x0C APB Devices Clock Enable Control Register 1
sahilmgandhi	18:6a4db94011d3	3063	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	3064	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	3065	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	3066	* \|[0] \|SC0CKEN \|SC0 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3067	* \| \| \|0 = SC0 Clock Disabled.
sahilmgandhi	18:6a4db94011d3	3068	* \| \| \|1 = SC0 Clock Enabled.
sahilmgandhi	18:6a4db94011d3	3069	* \|[1] \|SC1CKEN \|SC1 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3070	* \| \| \|0 = SC1 Clock Disabled.
sahilmgandhi	18:6a4db94011d3	3071	* \| \| \|1 = SC1 Clock Enabled.
sahilmgandhi	18:6a4db94011d3	3072	* \|[2] \|SC2CKEN \|SC2 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3073	* \| \| \|0 = SC2 Clock Disabled.
sahilmgandhi	18:6a4db94011d3	3074	* \| \| \|1 = SC2 Clock Enabled.
sahilmgandhi	18:6a4db94011d3	3075	* \|[3] \|SC3CKEN \|SC3 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3076	* \| \| \|0 = SC3 Clock Disabled.
sahilmgandhi	18:6a4db94011d3	3077	* \| \| \|1 = SC3 Clock Enabled.
sahilmgandhi	18:6a4db94011d3	3078	* \|[4] \|SC4CKEN \|SC4 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3079	* \| \| \|0 = SC4 Clock Disabled.
sahilmgandhi	18:6a4db94011d3	3080	* \| \| \|1 = SC4 Clock Enabled.
sahilmgandhi	18:6a4db94011d3	3081	* \|[5] \|SC5CKEN \|SC5 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3082	* \| \| \|0 = SC5 Clock Disabled.
sahilmgandhi	18:6a4db94011d3	3083	* \| \| \|1 = SC5 Clock Enabled.
sahilmgandhi	18:6a4db94011d3	3084	* \|[8] \|I2C4CKEN \|I2C4 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3085	* \| \| \|0 = I2C4 Clock Disabled.
sahilmgandhi	18:6a4db94011d3	3086	* \| \| \|1 = I2C4 Clock Enabled.
sahilmgandhi	18:6a4db94011d3	3087	* \|[16] \|PWM0CH01CKEN\|PWM0_01 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3088	* \| \| \|0 = PWM0_01 Clock Disabled.
sahilmgandhi	18:6a4db94011d3	3089	* \| \| \|1 = PWM0_01 Clock Enabled.
sahilmgandhi	18:6a4db94011d3	3090	* \|[17] \|PWM0CH23CKEN\|PWM0_23 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3091	* \| \| \|0 = PWM0_23 Clock Disabled.
sahilmgandhi	18:6a4db94011d3	3092	* \| \| \|1 = PWM0_23 Clock Enabled.
sahilmgandhi	18:6a4db94011d3	3093	* \|[18] \|PWM0CH45CKEN\|PWM0_45 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3094	* \| \| \|0 = PWM0_45 Clock Disabled.
sahilmgandhi	18:6a4db94011d3	3095	* \| \| \|1 = PWM0_45 Clock Enabled.
sahilmgandhi	18:6a4db94011d3	3096	* \|[19] \|PWM1CH01CKEN\|PWM1_01 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3097	* \| \| \|0 = PWM1_01 Clock Disabled.
sahilmgandhi	18:6a4db94011d3	3098	* \| \| \|1 = PWM1_01 Clock Enabled.
sahilmgandhi	18:6a4db94011d3	3099	* \|[20] \|PWM1CH23CKEN\|PWM1_23 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3100	* \| \| \|0 = PWM1_23 Clock Disabled.
sahilmgandhi	18:6a4db94011d3	3101	* \| \| \|1 = PWM1_23 Clock Enabled.
sahilmgandhi	18:6a4db94011d3	3102	* \|[21] \|PWM1CH45CKEN\|PWM1_45 Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3103	* \| \| \|0 = PWM1_45 Clock Disabled.
sahilmgandhi	18:6a4db94011d3	3104	* \| \| \|1 = PWM1_45 Clock Enabled.
sahilmgandhi	18:6a4db94011d3	3105	* \|[22] \|QEI0CKEN \|Quadrature Encoder Interface (QEI0) Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3106	* \| \| \|0 = QEI0 clock Disabled.
sahilmgandhi	18:6a4db94011d3	3107	* \| \| \|1 = QEI0 clock Enabled.
sahilmgandhi	18:6a4db94011d3	3108	* \|[23] \|QEI1CKEN \|Quadrature Encoder Interface (QEI1) Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3109	* \| \| \|0 = QEI1 clock Disabled.
sahilmgandhi	18:6a4db94011d3	3110	* \| \| \|1 = QEI1 clock Enabled.
sahilmgandhi	18:6a4db94011d3	3111	* \|[26] \|ECAP0CKEN \|Enhance CAP (ECAP0) Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3112	* \| \| \|0 = ECAP0 clock Disabled.
sahilmgandhi	18:6a4db94011d3	3113	* \| \| \|1 = ECAP0 clock Enabled.
sahilmgandhi	18:6a4db94011d3	3114	* \|[27] \|ECAP1CKEN \|Enhance CAP (ECAP1) Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3115	* \| \| \|0 = ECAP1 clock Disabled.
sahilmgandhi	18:6a4db94011d3	3116	* \| \| \|1 = ECAP1 clock Enabled.
sahilmgandhi	18:6a4db94011d3	3117	* \|[28] \|EPWM0CKEN \|Enhance PWM0 (EPWM) Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3118	* \| \| \|0 = EPWM0 clock Disabled.
sahilmgandhi	18:6a4db94011d3	3119	* \| \| \|1 = EPWM0 clock Enabled.
sahilmgandhi	18:6a4db94011d3	3120	* \|[29] \|EPWM1CKEN \|Enhance PWM1 (EPWM) Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3121	* \| \| \|0 = EPWM1 clock Disabled.
sahilmgandhi	18:6a4db94011d3	3122	* \| \| \|1 = EPWM1 clock Enabled.
sahilmgandhi	18:6a4db94011d3	3123	* \|[30] \|OPACKEN \|OP Amplifier (OPA) Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3124	* \| \| \|0 = OPA clock Disabled.
sahilmgandhi	18:6a4db94011d3	3125	* \| \| \|1 = OPA clock Enabled.
sahilmgandhi	18:6a4db94011d3	3126	* \|[31] \|EADCCKEN \|Enhance Analog-Digital-Converter (E ADC) Clock Enable Control
sahilmgandhi	18:6a4db94011d3	3127	* \| \| \|0 = EADC clock Disabled.
sahilmgandhi	18:6a4db94011d3	3128	* \| \| \|1 = EADC clock Enabled.
sahilmgandhi	18:6a4db94011d3	3129	*/
sahilmgandhi	18:6a4db94011d3	3130	__IO uint32_t APBCLK1;
sahilmgandhi	18:6a4db94011d3	3131
sahilmgandhi	18:6a4db94011d3	3132	/**
sahilmgandhi	18:6a4db94011d3	3133	* CLKSEL0
sahilmgandhi	18:6a4db94011d3	3134	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	3135	* Offset: 0x10 Clock Source Select Control Register 0
sahilmgandhi	18:6a4db94011d3	3136	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	3137	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	3138	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	3139	* \|[0:2] \|HCLKSEL \|HCLK Clock Source Selection (Write Protect)
sahilmgandhi	18:6a4db94011d3	3140	* \| \| \|Before clock switching, the related clock sources (both pre-select and new-select) must be turned on
sahilmgandhi	18:6a4db94011d3	3141	* \| \| \|1.
sahilmgandhi	18:6a4db94011d3	3142	* \| \| \|The 3-bit default value is reloaded from the value of CFOSC (Config0[26:24]) in user configuration register of Flash controller by any reset.
sahilmgandhi	18:6a4db94011d3	3143	* \| \| \|Therefore the default value is either 000b or 111b.
sahilmgandhi	18:6a4db94011d3	3144	* \| \| \|2.
sahilmgandhi	18:6a4db94011d3	3145	* \| \| \|These bits are protected bit, it means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
sahilmgandhi	18:6a4db94011d3	3146	* \| \| \|Refer to the register REGWRPROT at address GCR_BA+0x100.
sahilmgandhi	18:6a4db94011d3	3147	* \| \| \|000 = Clock source from HXT clock.
sahilmgandhi	18:6a4db94011d3	3148	* \| \| \|001 = Clock source from LXT clock.
sahilmgandhi	18:6a4db94011d3	3149	* \| \| \|010 = Clock source from PLL clock.
sahilmgandhi	18:6a4db94011d3	3150	* \| \| \|011 = Clock source from LIRC clock.
sahilmgandhi	18:6a4db94011d3	3151	* \| \| \|100 = Clock source from PLL2 clock.
sahilmgandhi	18:6a4db94011d3	3152	* \| \| \|111 = Clock source from HIRC clock.
sahilmgandhi	18:6a4db94011d3	3153	* \| \| \|Other = Reserved.
sahilmgandhi	18:6a4db94011d3	3154	* \|[3:5] \|STCLKSEL \|Cortex(TM)-M4 SysTick Clock Source Selection (Write Protect)
sahilmgandhi	18:6a4db94011d3	3155	* \| \| \|If SYST_CSR[2]=0, SysTick uses listed clock source below.
sahilmgandhi	18:6a4db94011d3	3156	* \| \| \|These bits are protected bit.
sahilmgandhi	18:6a4db94011d3	3157	* \| \| \|It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
sahilmgandhi	18:6a4db94011d3	3158	* \| \| \|Refer to the register REGWRPROT at address GCR_BA+0x100.
sahilmgandhi	18:6a4db94011d3	3159	* \| \| \|000 = Clock source from HXT clock.
sahilmgandhi	18:6a4db94011d3	3160	* \| \| \|001 = Clock source from LXT clock.
sahilmgandhi	18:6a4db94011d3	3161	* \| \| \|010 = Clock source from HXT clock/2.
sahilmgandhi	18:6a4db94011d3	3162	* \| \| \|011 = Clock source from HCLK/2.
sahilmgandhi	18:6a4db94011d3	3163	* \| \| \|111 = Clock source from HIRC clock/2.
sahilmgandhi	18:6a4db94011d3	3164	* \|[6] \|PCLKSEL \|PCLK Clock Source Selection (Write Protect)
sahilmgandhi	18:6a4db94011d3	3165	* \| \| \|These bits are protected bit.
sahilmgandhi	18:6a4db94011d3	3166	* \| \| \|It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
sahilmgandhi	18:6a4db94011d3	3167	* \| \| \|Refer to the register REGWRPROT at address GCR_BA+0x100.
sahilmgandhi	18:6a4db94011d3	3168	* \| \| \|0 = Clock source from HCLK.
sahilmgandhi	18:6a4db94011d3	3169	* \| \| \|1 = Clock source from HCLK/2.
sahilmgandhi	18:6a4db94011d3	3170	* \|[8] \|USBHSEL \|USB Host Clock Source Selection (Write Protect)
sahilmgandhi	18:6a4db94011d3	3171	* \| \| \|These bits are protected bit.
sahilmgandhi	18:6a4db94011d3	3172	* \| \| \|It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
sahilmgandhi	18:6a4db94011d3	3173	* \| \| \|Refer to the register REGWRPROT at address GCR_BA+0x100.
sahilmgandhi	18:6a4db94011d3	3174	* \| \| \|0 = Clock source from PLL2.
sahilmgandhi	18:6a4db94011d3	3175	* \| \| \|1 = Clock source from PLL.
sahilmgandhi	18:6a4db94011d3	3176	* \|[16:17] \|CAPSEL \|Image Capture Interface Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3177	* \| \| \|These bits are protected bit.
sahilmgandhi	18:6a4db94011d3	3178	* \| \| \|It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
sahilmgandhi	18:6a4db94011d3	3179	* \| \| \|Refer to the register REGWRPROT at address GCR_BA+0x100.
sahilmgandhi	18:6a4db94011d3	3180	* \| \| \|00 = Clock source from HXT clock.
sahilmgandhi	18:6a4db94011d3	3181	* \| \| \|01 = Clock source from PLL clock.
sahilmgandhi	18:6a4db94011d3	3182	* \| \| \|10 = Clock source from HCLK.
sahilmgandhi	18:6a4db94011d3	3183	* \| \| \|11 = Clock source from HIRC clock.
sahilmgandhi	18:6a4db94011d3	3184	* \|[20:21] \|SDHSEL \|SDHOST Engine Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3185	* \| \| \|These bits are protected bit.
sahilmgandhi	18:6a4db94011d3	3186	* \| \| \|It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
sahilmgandhi	18:6a4db94011d3	3187	* \| \| \|Refer to the register REGWRPROT at address GCR_BA+0x100.
sahilmgandhi	18:6a4db94011d3	3188	* \| \| \|00 = Clock source from HXT clock.
sahilmgandhi	18:6a4db94011d3	3189	* \| \| \|01 = Clock source from PLL clock.
sahilmgandhi	18:6a4db94011d3	3190	* \| \| \|10 = Clock source from HCLK.
sahilmgandhi	18:6a4db94011d3	3191	* \| \| \|11 = Clock source from HIRC clock.
sahilmgandhi	18:6a4db94011d3	3192	*/
sahilmgandhi	18:6a4db94011d3	3193	__IO uint32_t CLKSEL0;
sahilmgandhi	18:6a4db94011d3	3194
sahilmgandhi	18:6a4db94011d3	3195	/**
sahilmgandhi	18:6a4db94011d3	3196	* CLKSEL1
sahilmgandhi	18:6a4db94011d3	3197	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	3198	* Offset: 0x14 Clock Source Select Control Register 1
sahilmgandhi	18:6a4db94011d3	3199	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	3200	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	3201	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	3202	* \|[0:1] \|WDTSEL \|Watchdog Timer Clock Source Selection (Write Protect)
sahilmgandhi	18:6a4db94011d3	3203	* \| \| \|These bits are protected bit,and programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
sahilmgandhi	18:6a4db94011d3	3204	* \| \| \|Refer to the register REGWRPROT at address GCR_BA+0x100.
sahilmgandhi	18:6a4db94011d3	3205	* \| \| \|00 = Clock source from 4~24 MHz external high-speed crystal clock.
sahilmgandhi	18:6a4db94011d3	3206	* \| \| \|01 = Clock source from LXT clock.
sahilmgandhi	18:6a4db94011d3	3207	* \| \| \|10 = Clock source from HCLK/2048 clock.
sahilmgandhi	18:6a4db94011d3	3208	* \| \| \|11 = Clock source from LIRC clock.
sahilmgandhi	18:6a4db94011d3	3209	* \|[2:3] \|EADCSEL \|ADC Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3210	* \| \| \|00 = Clock source from HXT clock.
sahilmgandhi	18:6a4db94011d3	3211	* \| \| \|01 = Clock source from PLL clock.
sahilmgandhi	18:6a4db94011d3	3212	* \| \| \|10 = Clock source from PCLK.
sahilmgandhi	18:6a4db94011d3	3213	* \| \| \|11 = Clock source from HIRC clock.
sahilmgandhi	18:6a4db94011d3	3214	* \|[4] \|SPI0SEL \|SPI0 Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3215	* \| \| \|0 = Clock source from PLL clock.
sahilmgandhi	18:6a4db94011d3	3216	* \| \| \|1 = Clock source from PCLK.
sahilmgandhi	18:6a4db94011d3	3217	* \|[5] \|SPI1SEL \|SPI1 Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3218	* \| \| \|0 = Clock source from PLL clock.
sahilmgandhi	18:6a4db94011d3	3219	* \| \| \|1 = Clock source from PCLK.
sahilmgandhi	18:6a4db94011d3	3220	* \|[6] \|SPI2SEL \|SPI2 Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3221	* \| \| \|0 = Clock source from PLL clock.
sahilmgandhi	18:6a4db94011d3	3222	* \| \| \|1 = Clock source from PCLK.
sahilmgandhi	18:6a4db94011d3	3223	* \|[7] \|SPI3SEL \|SPI3 Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3224	* \| \| \|0 = Clock source from PLL clock.
sahilmgandhi	18:6a4db94011d3	3225	* \| \| \|1 = Clock source from PCLK.
sahilmgandhi	18:6a4db94011d3	3226	* \|[8:10] \|TMR0SEL \|TIMER0 Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3227	* \| \| \|000 = Clock source from HXT clock.
sahilmgandhi	18:6a4db94011d3	3228	* \| \| \|001 = Clock source from LXT clock.
sahilmgandhi	18:6a4db94011d3	3229	* \| \| \|010 = Clock source from PCLK.
sahilmgandhi	18:6a4db94011d3	3230	* \| \| \|011 = Clock source from external trigger.
sahilmgandhi	18:6a4db94011d3	3231	* \| \| \|101 = Clock source from LIRC clock.
sahilmgandhi	18:6a4db94011d3	3232	* \| \| \|111 = Clock source from HIRC clock.
sahilmgandhi	18:6a4db94011d3	3233	* \| \| \|Others = reserved.
sahilmgandhi	18:6a4db94011d3	3234	* \|[12:14] \|TMR1SEL \|TIMER1 Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3235	* \| \| \|000 = Clock source from HXT clock.
sahilmgandhi	18:6a4db94011d3	3236	* \| \| \|001 = Clock source from LXT clock.
sahilmgandhi	18:6a4db94011d3	3237	* \| \| \|010 = Clock source from PCLK.
sahilmgandhi	18:6a4db94011d3	3238	* \| \| \|011 = Clock source from external trigger.
sahilmgandhi	18:6a4db94011d3	3239	* \| \| \|101 = Clock source from LIRC clock.
sahilmgandhi	18:6a4db94011d3	3240	* \| \| \|111 = Clock source from HIRC clock.
sahilmgandhi	18:6a4db94011d3	3241	* \| \| \|Others = reserved.
sahilmgandhi	18:6a4db94011d3	3242	* \|[16:18] \|TMR2SEL \|TIMER2 Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3243	* \| \| \|000 = Clock source from HXT clock.
sahilmgandhi	18:6a4db94011d3	3244	* \| \| \|001 = Clock source from LXT clock.
sahilmgandhi	18:6a4db94011d3	3245	* \| \| \|010 = Clock source from PCLK.
sahilmgandhi	18:6a4db94011d3	3246	* \| \| \|011 = Clock source from external trigger.
sahilmgandhi	18:6a4db94011d3	3247	* \| \| \|101 = Clock source from LIRC clock.
sahilmgandhi	18:6a4db94011d3	3248	* \| \| \|111 = Clock source from HIRC clock.
sahilmgandhi	18:6a4db94011d3	3249	* \| \| \|Others = reserved.
sahilmgandhi	18:6a4db94011d3	3250	* \|[20:22] \|TMR3SEL \|TIMER3 Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3251	* \| \| \|000 = Clock source from HXT clock.
sahilmgandhi	18:6a4db94011d3	3252	* \| \| \|001 = Clock source from LXT clock.
sahilmgandhi	18:6a4db94011d3	3253	* \| \| \|010 = Clock source from PCLK.
sahilmgandhi	18:6a4db94011d3	3254	* \| \| \|011 = Clock source from external trigger.
sahilmgandhi	18:6a4db94011d3	3255	* \| \| \|101 = Clock source from LIRC clock.
sahilmgandhi	18:6a4db94011d3	3256	* \| \| \|111 = Clock source from HIRC clock.
sahilmgandhi	18:6a4db94011d3	3257	* \| \| \|Others = reserved.
sahilmgandhi	18:6a4db94011d3	3258	* \|[24:25] \|UARTSEL \|UART Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3259	* \| \| \|00 = Clock source from HXT clock.
sahilmgandhi	18:6a4db94011d3	3260	* \| \| \|01 = Clock source from PLL clock.
sahilmgandhi	18:6a4db94011d3	3261	* \| \| \|10/11 = Clock source from HIRC clock.
sahilmgandhi	18:6a4db94011d3	3262	* \|[28:29] \|CLKOSEL \|Clock Divider Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3263	* \| \| \|00 = Clock source from HXT clock.
sahilmgandhi	18:6a4db94011d3	3264	* \| \| \|01 = Clock source from LXT clock.
sahilmgandhi	18:6a4db94011d3	3265	* \| \| \|10 = Clock source from HCLK.
sahilmgandhi	18:6a4db94011d3	3266	* \| \| \|11 = Clock source from HIRC clock.
sahilmgandhi	18:6a4db94011d3	3267	* \|[30:31] \|WWDTSEL \|Window Watchdog Timer Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3268	* \| \| \|00 = Reserved.
sahilmgandhi	18:6a4db94011d3	3269	* \| \| \|01 = Reserved.
sahilmgandhi	18:6a4db94011d3	3270	* \| \| \|10 = Clock source from HCLK/2048 clock.
sahilmgandhi	18:6a4db94011d3	3271	* \| \| \|11 = Clock source from LIRC clock.
sahilmgandhi	18:6a4db94011d3	3272	*/
sahilmgandhi	18:6a4db94011d3	3273	__IO uint32_t CLKSEL1;
sahilmgandhi	18:6a4db94011d3	3274
sahilmgandhi	18:6a4db94011d3	3275	/**
sahilmgandhi	18:6a4db94011d3	3276	* CLKSEL2
sahilmgandhi	18:6a4db94011d3	3277	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	3278	* Offset: 0x18 Clock Source Select Control Register 2
sahilmgandhi	18:6a4db94011d3	3279	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	3280	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	3281	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	3282	* \|[0:2] \|PWM0CH01SEL\|PWM0_0 And PWM0_1 Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3283	* \| \| \|PWM0_0 and PWM0_1 uses the same Engine clock source, both of them use the same prescaler.
sahilmgandhi	18:6a4db94011d3	3284	* \| \| \|The Engine clock source of PWM0_0 and PWM0_1 is defined by PWM0CH01SEL[2:0].
sahilmgandhi	18:6a4db94011d3	3285	* \| \| \|000 = Clock source from HXT clock.
sahilmgandhi	18:6a4db94011d3	3286	* \| \| \|001 = Clock source from LXT clock.
sahilmgandhi	18:6a4db94011d3	3287	* \| \| \|010 = Clock source from PCLK.
sahilmgandhi	18:6a4db94011d3	3288	* \| \| \|011 = Clock source from HIRC clock.
sahilmgandhi	18:6a4db94011d3	3289	* \| \| \|100 = Clock source from LIRC clock.
sahilmgandhi	18:6a4db94011d3	3290	* \| \| \|Other = Reserved.
sahilmgandhi	18:6a4db94011d3	3291	* \|[4:6] \|PPWM0CH23SEL\|PWM0_2 And PWM0_3 Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3292	* \| \| \|PWM0_2 and PWM0_3 uses the same Engine clock source, both of them use the same prescaler.
sahilmgandhi	18:6a4db94011d3	3293	* \| \| \|The Engine clock source of PWM0_2 and PWM0_3 is defined by PPWM0CH23SEL[2:0].
sahilmgandhi	18:6a4db94011d3	3294	* \| \| \|000 = Clock source from HXT clock.
sahilmgandhi	18:6a4db94011d3	3295	* \| \| \|001 = Clock source from LXT clock.
sahilmgandhi	18:6a4db94011d3	3296	* \| \| \|010 = Clock source from PCLK.
sahilmgandhi	18:6a4db94011d3	3297	* \| \| \|011 = Clock source from HIRC clock.
sahilmgandhi	18:6a4db94011d3	3298	* \| \| \|100 = Clock source from LIRC clock.
sahilmgandhi	18:6a4db94011d3	3299	* \| \| \|Other = Reserved.
sahilmgandhi	18:6a4db94011d3	3300	* \|[8:10] \|PWM0CH45SEL\|PWM0_4 And PWM0_5 Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3301	* \| \| \|PWM0_4 and PWM0_5 used the same Engine clock source; both of them use the same prescaler.
sahilmgandhi	18:6a4db94011d3	3302	* \| \| \|The Engine clock source of PWM0_4 and PWM0_5 is defined by PWM0CH45SEL[2:0].
sahilmgandhi	18:6a4db94011d3	3303	* \| \| \|000 = Clock source from HXT clock.
sahilmgandhi	18:6a4db94011d3	3304	* \| \| \|001 = Clock source from LXT clock.
sahilmgandhi	18:6a4db94011d3	3305	* \| \| \|010 = Clock source from PCLK.
sahilmgandhi	18:6a4db94011d3	3306	* \| \| \|011 = Clock source from HIRC clock.
sahilmgandhi	18:6a4db94011d3	3307	* \| \| \|100 = Clock source from LIRC clock.
sahilmgandhi	18:6a4db94011d3	3308	* \| \| \|Other = Reserved.
sahilmgandhi	18:6a4db94011d3	3309	* \|[12:14] \|PWM1CH01SEL\|PWM1_0 And PWM1_1 Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3310	* \| \| \|PWM1_0 and PWM1_1 uses the same Engine clock source, both of them use the same prescaler.
sahilmgandhi	18:6a4db94011d3	3311	* \| \| \|The Engine clock source of PWM1_0 and PWM1_1 is defined by PWM1CH01SEL[2:0].
sahilmgandhi	18:6a4db94011d3	3312	* \| \| \|000 = Clock source from HXT clock.
sahilmgandhi	18:6a4db94011d3	3313	* \| \| \|001 = Clock source from LXT clock.
sahilmgandhi	18:6a4db94011d3	3314	* \| \| \|010 = Clock source from PCLK.
sahilmgandhi	18:6a4db94011d3	3315	* \| \| \|011 = Clock source from HIRC clock.
sahilmgandhi	18:6a4db94011d3	3316	* \| \| \|100 = Clock source from LIRC clock.
sahilmgandhi	18:6a4db94011d3	3317	* \| \| \|Other = Reserved.
sahilmgandhi	18:6a4db94011d3	3318	* \|[16:18] \|PWM1CH23SEL\|PWM1_2 And PWM1_3 Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3319	* \| \| \|PWM1_2 and PWM1_3 uses the same Engine clock source, both of them use the same prescaler.
sahilmgandhi	18:6a4db94011d3	3320	* \| \| \|The Engine clock source of PWM1_2 and PWM1_3 is defined by PWM1CH23SEL[2:0].
sahilmgandhi	18:6a4db94011d3	3321	* \| \| \|000 = Clock source from HXT clock.
sahilmgandhi	18:6a4db94011d3	3322	* \| \| \|001 = Clock source from LXT clock.
sahilmgandhi	18:6a4db94011d3	3323	* \| \| \|010 = Clock source from PCLK.
sahilmgandhi	18:6a4db94011d3	3324	* \| \| \|011 = Clock source from HIRC clock.
sahilmgandhi	18:6a4db94011d3	3325	* \| \| \|100= Clock source from LIRC clock.
sahilmgandhi	18:6a4db94011d3	3326	* \| \| \|Other = Reserved.
sahilmgandhi	18:6a4db94011d3	3327	* \|[20:22] \|PWM1CH45SEL\|PWM1_4 And PWM1_5 Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3328	* \| \| \|PWM1_4 and PWM1_5 used the same Engine clock source; both of them use the same prescaler.
sahilmgandhi	18:6a4db94011d3	3329	* \| \| \|The Engine clock source of PWM1_4 and PWM1_5 is defined by PWM1CH45SEL[2:0].
sahilmgandhi	18:6a4db94011d3	3330	* \| \| \|000 = Clock source from HXT clock.
sahilmgandhi	18:6a4db94011d3	3331	* \| \| \|001 = Clock source from LXT clock.
sahilmgandhi	18:6a4db94011d3	3332	* \| \| \|010 = Clock source from PCLK.
sahilmgandhi	18:6a4db94011d3	3333	* \| \| \|011 = Clock source from HIRC clock.
sahilmgandhi	18:6a4db94011d3	3334	* \| \| \|100 = Clock source from LIRC clock.
sahilmgandhi	18:6a4db94011d3	3335	* \| \| \|Other = Reserved.
sahilmgandhi	18:6a4db94011d3	3336	*/
sahilmgandhi	18:6a4db94011d3	3337	__IO uint32_t CLKSEL2;
sahilmgandhi	18:6a4db94011d3	3338
sahilmgandhi	18:6a4db94011d3	3339	/**
sahilmgandhi	18:6a4db94011d3	3340	* CLKSEL3
sahilmgandhi	18:6a4db94011d3	3341	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	3342	* Offset: 0x1C Clock Source Select Control Register 3
sahilmgandhi	18:6a4db94011d3	3343	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	3344	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	3345	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	3346	* \|[0:1] \|SC0SEL \|SC0 Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3347	* \| \| \|00 = Clock source from HXT clock.
sahilmgandhi	18:6a4db94011d3	3348	* \| \| \|01 = Clock source from PLL clock.
sahilmgandhi	18:6a4db94011d3	3349	* \| \| \|10 = PCLK.
sahilmgandhi	18:6a4db94011d3	3350	* \| \| \|11 = Clock source from HIRC clock.
sahilmgandhi	18:6a4db94011d3	3351	* \|[2:3] \|SC1SEL \|SC1 Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3352	* \| \| \|00 = Clock source from HXT clock.
sahilmgandhi	18:6a4db94011d3	3353	* \| \| \|01 = Clock source from PLL clock.
sahilmgandhi	18:6a4db94011d3	3354	* \| \| \|10 = PCLK.
sahilmgandhi	18:6a4db94011d3	3355	* \| \| \|11 = Clock source from HIRC clock.
sahilmgandhi	18:6a4db94011d3	3356	* \|[4:5] \|SC2SEL \|SC2 Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3357	* \| \| \|00 = Clock source from HXT clock.
sahilmgandhi	18:6a4db94011d3	3358	* \| \| \|01 = Clock source from PLL clock.
sahilmgandhi	18:6a4db94011d3	3359	* \| \| \|10 = PCLK.
sahilmgandhi	18:6a4db94011d3	3360	* \| \| \|11 = Clock source from HIRC clock.
sahilmgandhi	18:6a4db94011d3	3361	* \|[6:7] \|SC3SEL \|SC3 Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3362	* \| \| \|00 = Clock source from HXT clock.
sahilmgandhi	18:6a4db94011d3	3363	* \| \| \|01 = Clock source from PLL clock.
sahilmgandhi	18:6a4db94011d3	3364	* \| \| \|10 = PCLK.
sahilmgandhi	18:6a4db94011d3	3365	* \| \| \|11 = Clock source from HIRC clock.
sahilmgandhi	18:6a4db94011d3	3366	* \|[8:9] \|SC4SEL \|SC4 Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3367	* \| \| \|00 = Clock source from HXT clock.
sahilmgandhi	18:6a4db94011d3	3368	* \| \| \|01 = Clock source from PLL clock.
sahilmgandhi	18:6a4db94011d3	3369	* \| \| \|10 = PCLK.
sahilmgandhi	18:6a4db94011d3	3370	* \| \| \|11 = Clock source from HIRC clock.
sahilmgandhi	18:6a4db94011d3	3371	* \|[10:11] \|SC5SEL \|SC5 Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3372	* \| \| \|00 = Clock source from HXT clock.
sahilmgandhi	18:6a4db94011d3	3373	* \| \| \|01 = Clock source from PLL clock.
sahilmgandhi	18:6a4db94011d3	3374	* \| \| \|10 = PCLK.
sahilmgandhi	18:6a4db94011d3	3375	* \| \| \|11 = Clock source from HIRC clock.
sahilmgandhi	18:6a4db94011d3	3376	* \|[16:17] \|I2S0SEL \|I2S0 Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3377	* \| \| \|00 = Clock source from HXT clock.
sahilmgandhi	18:6a4db94011d3	3378	* \| \| \|01 = Clock source from PLL clock.
sahilmgandhi	18:6a4db94011d3	3379	* \| \| \|10 = Clock source from PCLK.
sahilmgandhi	18:6a4db94011d3	3380	* \| \| \|11 = Clock source from HIRC clock.
sahilmgandhi	18:6a4db94011d3	3381	* \|[18:19] \|I2S1SEL \|I2S1 Clock Source Selection
sahilmgandhi	18:6a4db94011d3	3382	* \| \| \|00 = Clock source from HXT clock.
sahilmgandhi	18:6a4db94011d3	3383	* \| \| \|01 = Clock source from PLL clock.
sahilmgandhi	18:6a4db94011d3	3384	* \| \| \|10 = Clock source from PCLK.
sahilmgandhi	18:6a4db94011d3	3385	* \| \| \|11 = Clock source from HIRC clock.
sahilmgandhi	18:6a4db94011d3	3386	*/
sahilmgandhi	18:6a4db94011d3	3387	__IO uint32_t CLKSEL3;
sahilmgandhi	18:6a4db94011d3	3388
sahilmgandhi	18:6a4db94011d3	3389	/**
sahilmgandhi	18:6a4db94011d3	3390	* CLKDIV0
sahilmgandhi	18:6a4db94011d3	3391	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	3392	* Offset: 0x20 Clock Divider Number Register 0
sahilmgandhi	18:6a4db94011d3	3393	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	3394	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	3395	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	3396	* \|[0:3] \|HCLKDIV \|HCLK Clock Divide Number From HCLK Clock Source
sahilmgandhi	18:6a4db94011d3	3397	* \| \| \|HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1).
sahilmgandhi	18:6a4db94011d3	3398	* \|[4:7] \|USBHDIV \|USB Host Clock Divide Number From PLL Clock
sahilmgandhi	18:6a4db94011d3	3399	* \| \| \|USB Host clock frequency = (PLL frequency) / (USBHDIV + 1).
sahilmgandhi	18:6a4db94011d3	3400	* \|[8:11] \|UARTDIV \|UART Clock Divide Number From UART Clock Source
sahilmgandhi	18:6a4db94011d3	3401	* \| \| \|UART clock frequency = (UART clock source frequency) / (UARTDIV + 1).
sahilmgandhi	18:6a4db94011d3	3402	* \|[16:23] \|ADCDIV \|ADC Clock Divide Number From ADC Clock Source
sahilmgandhi	18:6a4db94011d3	3403	* \| \| \|ADC clock frequency = (ADC clock source frequency) / (ADCDIV + 1).
sahilmgandhi	18:6a4db94011d3	3404	* \|[24:31] \|SDHDIV \|SDHOST Clock Divide Number From SDHOST Clock Source
sahilmgandhi	18:6a4db94011d3	3405	* \| \| \|SDHOST clock frequency = (SDHOST clock source frequency) / (SDHDIV + 1).
sahilmgandhi	18:6a4db94011d3	3406	*/
sahilmgandhi	18:6a4db94011d3	3407	__IO uint32_t CLKDIV0;
sahilmgandhi	18:6a4db94011d3	3408
sahilmgandhi	18:6a4db94011d3	3409	/**
sahilmgandhi	18:6a4db94011d3	3410	* CLKDIV1
sahilmgandhi	18:6a4db94011d3	3411	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	3412	* Offset: 0x24 Clock Divider Number Register 1
sahilmgandhi	18:6a4db94011d3	3413	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	3414	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	3415	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	3416	* \|[0:7] \|SC0DIV \|SC0 Clock Divide Number From SC0 Clock Source
sahilmgandhi	18:6a4db94011d3	3417	* \| \| \|SC0 clock frequency = (SC0 clock source frequency ) / (SC0DIV+ 1).
sahilmgandhi	18:6a4db94011d3	3418	* \|[8:15] \|SC1DIV \|SC1 Clock Divide Number From SC1 Clock Source
sahilmgandhi	18:6a4db94011d3	3419	* \| \| \|SC1 clock frequency = (SC1 clock source frequency ) / (SC1DIV + 1).
sahilmgandhi	18:6a4db94011d3	3420	* \|[16:23] \|SC2DIV \|SC2 Clock Divide Number From SC2 Clock Source
sahilmgandhi	18:6a4db94011d3	3421	* \| \| \|SC2 clock frequency = (SC2 clock source frequency ) / (SC2DIV + 1).
sahilmgandhi	18:6a4db94011d3	3422	* \|[24:31] \|SC3DIV \|SC3 Clock Divide Number From SC3 Clock Source
sahilmgandhi	18:6a4db94011d3	3423	* \| \| \|SC3 clock frequency = (SC3 clock source frequency ) / (SC3DIV+ 1).
sahilmgandhi	18:6a4db94011d3	3424	*/
sahilmgandhi	18:6a4db94011d3	3425	__IO uint32_t CLKDIV1;
sahilmgandhi	18:6a4db94011d3	3426
sahilmgandhi	18:6a4db94011d3	3427	/**
sahilmgandhi	18:6a4db94011d3	3428	* CLKDIV2
sahilmgandhi	18:6a4db94011d3	3429	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	3430	* Offset: 0x28 Clock Divider Number Register 2
sahilmgandhi	18:6a4db94011d3	3431	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	3432	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	3433	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	3434	* \|[0:7] \|SC4DIV \|SC4 Clock Divide Number From SC4 Clock Source
sahilmgandhi	18:6a4db94011d3	3435	* \| \| \|SC4 clock frequency = (SC4 clock source frequency ) / (SC4DIV + 1).
sahilmgandhi	18:6a4db94011d3	3436	* \|[8:15] \|SC5DIV \|SC5 Clock Divide Number From SC5 Clock Source
sahilmgandhi	18:6a4db94011d3	3437	* \| \| \|SC5 clock frequency = (SC5 clock source frequency ) / (SC5DIV + 1).
sahilmgandhi	18:6a4db94011d3	3438	*/
sahilmgandhi	18:6a4db94011d3	3439	__IO uint32_t CLKDIV2;
sahilmgandhi	18:6a4db94011d3	3440
sahilmgandhi	18:6a4db94011d3	3441	/**
sahilmgandhi	18:6a4db94011d3	3442	* CLKDIV3
sahilmgandhi	18:6a4db94011d3	3443	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	3444	* Offset: 0x2C Clock Divider Number Register 3
sahilmgandhi	18:6a4db94011d3	3445	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	3446	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	3447	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	3448	* \|[0:7] \|CAPDIV \|Image Capture Seneor Clock Divide Number From ICAP Clock Source
sahilmgandhi	18:6a4db94011d3	3449	* \| \| \|Image sensor clock frequency = (ICAP clock source frequency) / (ICAPDIV + 1).
sahilmgandhi	18:6a4db94011d3	3450	* \|[8:15] \|VSENSEDIV \|Video Pixel Clock Divide Number From ICAP Clock Source
sahilmgandhi	18:6a4db94011d3	3451	* \| \| \|Video pixel clock frequency = (ICAP clock source frequency) / (VSENSEDIV + 1).
sahilmgandhi	18:6a4db94011d3	3452	* \|[16:23] \|EMACDIV \|Ethernet Clock Divide Number Form HCLK (NUC472 Only)
sahilmgandhi	18:6a4db94011d3	3453	* \| \| \|EMAC MDCLK clock frequency = (HCLK) / (EMACDIV + 1).
sahilmgandhi	18:6a4db94011d3	3454	*/
sahilmgandhi	18:6a4db94011d3	3455	__IO uint32_t CLKDIV3;
sahilmgandhi	18:6a4db94011d3	3456	uint32_t RESERVE0[4];
sahilmgandhi	18:6a4db94011d3	3457
sahilmgandhi	18:6a4db94011d3	3458
sahilmgandhi	18:6a4db94011d3	3459	/**
sahilmgandhi	18:6a4db94011d3	3460	* PLLCTL
sahilmgandhi	18:6a4db94011d3	3461	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	3462	* Offset: 0x40 PLL Control Register
sahilmgandhi	18:6a4db94011d3	3463	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	3464	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	3465	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	3466	* \|[0:8] \|FBDIV \|PLL Feedback Divider Control Pins
sahilmgandhi	18:6a4db94011d3	3467	* \| \| \|Refer to the formulas below the table.
sahilmgandhi	18:6a4db94011d3	3468	* \|[9:13] \|INDIV \|PLL Input Divider Control Pins
sahilmgandhi	18:6a4db94011d3	3469	* \| \| \|Refer to the formulas below the table.
sahilmgandhi	18:6a4db94011d3	3470	* \|[14:15] \|OUTDV \|PLL Output Divider Control Pins
sahilmgandhi	18:6a4db94011d3	3471	* \| \| \|Refer to the formulas below the table.
sahilmgandhi	18:6a4db94011d3	3472	* \|[16] \|PD \|Power-Down Mode
sahilmgandhi	18:6a4db94011d3	3473	* \| \| \|If set the PWR_DOWN_EN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.
sahilmgandhi	18:6a4db94011d3	3474	* \| \| \|0 = PLL is in normal mode.
sahilmgandhi	18:6a4db94011d3	3475	* \| \| \|1 = PLL is in Power-down mode (default).
sahilmgandhi	18:6a4db94011d3	3476	* \|[17] \|BP \|PLL Bypass Control
sahilmgandhi	18:6a4db94011d3	3477	* \| \| \|0 = PLL is in normal mode (default).
sahilmgandhi	18:6a4db94011d3	3478	* \| \| \|1 = PLL clock output is same as clock input (XTALin).
sahilmgandhi	18:6a4db94011d3	3479	* \|[18] \|OE \|PLL OE (FOUT Enable) Pin Control
sahilmgandhi	18:6a4db94011d3	3480	* \| \| \|0 = PLL FOUT Enabled.
sahilmgandhi	18:6a4db94011d3	3481	* \| \| \|1 = PLL FOUT is fixed low.
sahilmgandhi	18:6a4db94011d3	3482	* \|[19] \|PLLSRC \|PLL Source Clock Selection
sahilmgandhi	18:6a4db94011d3	3483	* \| \| \|0 = PLL source clock from HXT.
sahilmgandhi	18:6a4db94011d3	3484	* \| \| \|1 = PLL source clock from HIRC.
sahilmgandhi	18:6a4db94011d3	3485	* \|[20] \|PLLREMAP \|PLL Remap Enable Bit
sahilmgandhi	18:6a4db94011d3	3486	* \| \| \|0 = PLL remap enable.
sahilmgandhi	18:6a4db94011d3	3487	* \| \| \|1 = PLL remap disable.
sahilmgandhi	18:6a4db94011d3	3488	*/
sahilmgandhi	18:6a4db94011d3	3489	__IO uint32_t PLLCTL;
sahilmgandhi	18:6a4db94011d3	3490
sahilmgandhi	18:6a4db94011d3	3491	/**
sahilmgandhi	18:6a4db94011d3	3492	* PLL2CTL
sahilmgandhi	18:6a4db94011d3	3493	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	3494	* Offset: 0x44 PLL2 Control Register
sahilmgandhi	18:6a4db94011d3	3495	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	3496	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	3497	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	3498	* \|[0:7] \|PLL2DIV \|PLL2 Divider Control
sahilmgandhi	18:6a4db94011d3	3499	* \| \| \|PLL2 clock frequency = (480 MHz) / 2 / (PLL2DIV + 1).
sahilmgandhi	18:6a4db94011d3	3500	* \| \| \|Note: Max. PLL frequency 240 MHz when XTL12M.
sahilmgandhi	18:6a4db94011d3	3501	* \|[8] \|PLL2CKEN \|USB OHY 480 MHz Enable Control
sahilmgandhi	18:6a4db94011d3	3502	* \| \| \|This bit enables USB PHY PLL (480 MHz), and user needs to care extend 12 MHz source.
sahilmgandhi	18:6a4db94011d3	3503	* \| \| \|0 = USB PHY PLL (480 MHz) Disabled.
sahilmgandhi	18:6a4db94011d3	3504	* \| \| \|1 = USB PHY PLL (480 MHz) Enabled.
sahilmgandhi	18:6a4db94011d3	3505	*/
sahilmgandhi	18:6a4db94011d3	3506	__IO uint32_t PLL2CTL;
sahilmgandhi	18:6a4db94011d3	3507	uint32_t RESERVE1[2];
sahilmgandhi	18:6a4db94011d3	3508
sahilmgandhi	18:6a4db94011d3	3509
sahilmgandhi	18:6a4db94011d3	3510	/**
sahilmgandhi	18:6a4db94011d3	3511	* STATUS
sahilmgandhi	18:6a4db94011d3	3512	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	3513	* Offset: 0x50 Clock Status Monitor Register
sahilmgandhi	18:6a4db94011d3	3514	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	3515	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	3516	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	3517	* \|[0] \|HXTSTB \|4~24 MHz External High-Speed Crystal Clock(HXT) Source Stable Flag
sahilmgandhi	18:6a4db94011d3	3518	* \| \| \|0 = HXT clock is not stable or disabled.
sahilmgandhi	18:6a4db94011d3	3519	* \| \| \|1 = HXT clock is stable.
sahilmgandhi	18:6a4db94011d3	3520	* \| \| \|Note: This bit is read only.
sahilmgandhi	18:6a4db94011d3	3521	* \|[1] \|LXTSTB \|32.768 KHz External Low-Speed Crystal Clock(LXT) Source Stable Flag
sahilmgandhi	18:6a4db94011d3	3522	* \| \| \|0 = LXT clock is not stable or disabled.
sahilmgandhi	18:6a4db94011d3	3523	* \| \| \|1 = LXT clock is stabled.
sahilmgandhi	18:6a4db94011d3	3524	* \| \| \|Note: This is read only.
sahilmgandhi	18:6a4db94011d3	3525	* \|[2] \|PLLSTB \|Internal PLL Clock Source Stable Flag
sahilmgandhi	18:6a4db94011d3	3526	* \| \| \|0 = Internal PLL clock is not stable or disabled.
sahilmgandhi	18:6a4db94011d3	3527	* \| \| \|1 = Internal PLL clock is stable.
sahilmgandhi	18:6a4db94011d3	3528	* \| \| \|Note: This bit is read only.
sahilmgandhi	18:6a4db94011d3	3529	* \|[3] \|LIRCSTB \|10 KHz Internal Low-Speed Oscillator Clock (LIRC)Source Stable Flag
sahilmgandhi	18:6a4db94011d3	3530	* \| \| \|0 = LIRC clock is not stable or disabled.
sahilmgandhi	18:6a4db94011d3	3531	* \| \| \|1 = LIRC clock is stable.
sahilmgandhi	18:6a4db94011d3	3532	* \| \| \|Note: This bit is read only.
sahilmgandhi	18:6a4db94011d3	3533	* \|[4] \|HIRCSTB \|22.1184 MHz Internal High-Speed Oscillator Clock (HIRC) Clock Source Stable Flag
sahilmgandhi	18:6a4db94011d3	3534	* \| \| \|0 = HIRC clock is not stable or disabled.
sahilmgandhi	18:6a4db94011d3	3535	* \| \| \|1 = HIRC clock is stable.
sahilmgandhi	18:6a4db94011d3	3536	* \| \| \|Note: This bit is read only.
sahilmgandhi	18:6a4db94011d3	3537	* \|[5] \|PLL2STB \|Internal PLL2 Clock Source Stable Flag
sahilmgandhi	18:6a4db94011d3	3538	* \| \| \|0 = Internal PLL2 clock is not stable or disabled.
sahilmgandhi	18:6a4db94011d3	3539	* \| \| \|1 = Internal PLL2 clock is stable.
sahilmgandhi	18:6a4db94011d3	3540	* \| \| \|Note: This bit is read only.
sahilmgandhi	18:6a4db94011d3	3541	* \|[7] \|CLKSFAIL \|Clock Switching Fail Flag
sahilmgandhi	18:6a4db94011d3	3542	* \| \| \|0 = Clock switching success.
sahilmgandhi	18:6a4db94011d3	3543	* \| \| \|1 = Clock switching failure.
sahilmgandhi	18:6a4db94011d3	3544	* \| \| \|Note1: This bit is updated when software switches system clock source.
sahilmgandhi	18:6a4db94011d3	3545	* \| \| \|If switch target clock is stable, this bit will be set to 0.
sahilmgandhi	18:6a4db94011d3	3546	* \| \| \|If switch target clock is not stable, this bit will be set to 1.
sahilmgandhi	18:6a4db94011d3	3547	* \| \| \|Note2: Write 1 to clear the bit to 0.
sahilmgandhi	18:6a4db94011d3	3548	*/
sahilmgandhi	18:6a4db94011d3	3549	__IO uint32_t STATUS;
sahilmgandhi	18:6a4db94011d3	3550	uint32_t RESERVE2[3];
sahilmgandhi	18:6a4db94011d3	3551
sahilmgandhi	18:6a4db94011d3	3552
sahilmgandhi	18:6a4db94011d3	3553	/**
sahilmgandhi	18:6a4db94011d3	3554	* CLKOCTL
sahilmgandhi	18:6a4db94011d3	3555	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	3556	* Offset: 0x60 Frequency Divider Control Register
sahilmgandhi	18:6a4db94011d3	3557	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	3558	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	3559	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	3560	* \|[0:3] \|FSEL \|Divider Output Frequency Selection
sahilmgandhi	18:6a4db94011d3	3561	* \| \| \|The formula of output frequency is:
sahilmgandhi	18:6a4db94011d3	3562	* \| \| \|Fout = Fin/2(N+1).
sahilmgandhi	18:6a4db94011d3	3563	* \| \| \|Fin is the input clock frequency.
sahilmgandhi	18:6a4db94011d3	3564	* \| \| \|Fout is the frequency of divider output clock.
sahilmgandhi	18:6a4db94011d3	3565	* \| \| \|N is the 4-bit value of FSEL[3:0].
sahilmgandhi	18:6a4db94011d3	3566	* \|[4] \|CLKOEN \|Clock Output Enable Control
sahilmgandhi	18:6a4db94011d3	3567	* \| \| \|0 = Clock Output disabled.
sahilmgandhi	18:6a4db94011d3	3568	* \| \| \|1 = Clock Output enabled.
sahilmgandhi	18:6a4db94011d3	3569	* \|[5] \|DIV1EN \|Frequency Divider 1 Enable Control
sahilmgandhi	18:6a4db94011d3	3570	* \| \| \|0 = Divider output frequency is dependent on FSEL value when FDIVEN is enabled.
sahilmgandhi	18:6a4db94011d3	3571	* \| \| \|1 = Divider output frequency is input clock frequency.
sahilmgandhi	18:6a4db94011d3	3572	*/
sahilmgandhi	18:6a4db94011d3	3573	__IO uint32_t CLKOCTL;
sahilmgandhi	18:6a4db94011d3	3574	uint32_t RESERVE3[3];
sahilmgandhi	18:6a4db94011d3	3575
sahilmgandhi	18:6a4db94011d3	3576
sahilmgandhi	18:6a4db94011d3	3577	/**
sahilmgandhi	18:6a4db94011d3	3578	* CLKDCTL
sahilmgandhi	18:6a4db94011d3	3579	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	3580	* Offset: 0x70 Clock Fail Detector Control Register
sahilmgandhi	18:6a4db94011d3	3581	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	3582	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	3583	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	3584	* \|[0] \|SYSFDEN \|System Clock Detector Enable Control
sahilmgandhi	18:6a4db94011d3	3585	* \| \| \|0 = system clock fail interrupt disabled.
sahilmgandhi	18:6a4db94011d3	3586	* \| \| \|1 = system clock fail interrupt enabled.
sahilmgandhi	18:6a4db94011d3	3587	* \|[1] \|SYSFIEN \|System Clock Detector Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	3588	* \| \| \|0 = system clock fail interrupt disabled.
sahilmgandhi	18:6a4db94011d3	3589	* \| \| \|1 = system clock fail interrupt enabled.
sahilmgandhi	18:6a4db94011d3	3590	* \|[2] \|SYSFIF \|System Clock Detect Fail Flag
sahilmgandhi	18:6a4db94011d3	3591	* \| \| \|0 = System clock normal.
sahilmgandhi	18:6a4db94011d3	3592	* \| \| \|1 = System clock abnormal (write " 1" to clear).
sahilmgandhi	18:6a4db94011d3	3593	* \|[8] \|IRCDEN \|Internal RC Clock Detector Enable Control
sahilmgandhi	18:6a4db94011d3	3594	* \| \| \|0 = IRC clock fail interrupt disabled.
sahilmgandhi	18:6a4db94011d3	3595	* \| \| \|1 = IRC clock fail interrupt enabled.
sahilmgandhi	18:6a4db94011d3	3596	* \|[9] \|IRCFIEN \|Internal RC Clock Detector Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	3597	* \| \| \|0 = IRC clock fail interrupt disabled.
sahilmgandhi	18:6a4db94011d3	3598	* \| \| \|1 = IRC clock fail interrupt enabled.
sahilmgandhi	18:6a4db94011d3	3599	* \|[10] \|IRCFIF \|Internal RC Clock Fail Flag
sahilmgandhi	18:6a4db94011d3	3600	* \| \| \|0 = IRC clock normal.
sahilmgandhi	18:6a4db94011d3	3601	* \| \| \|1 = IRC abnormal (write "1" to clear) .
sahilmgandhi	18:6a4db94011d3	3602	*/
sahilmgandhi	18:6a4db94011d3	3603	__IO uint32_t CLKDCTL;
sahilmgandhi	18:6a4db94011d3	3604
sahilmgandhi	18:6a4db94011d3	3605	} CLK_T;
sahilmgandhi	18:6a4db94011d3	3606
sahilmgandhi	18:6a4db94011d3	3607	/**
sahilmgandhi	18:6a4db94011d3	3608	@addtogroup CLK_CONST CLK Bit Field Definition
sahilmgandhi	18:6a4db94011d3	3609	Constant Definitions for CLK Controller
sahilmgandhi	18:6a4db94011d3	3610	@{ */
sahilmgandhi	18:6a4db94011d3	3611
sahilmgandhi	18:6a4db94011d3	3612	#define CLK_PWRCTL_HXTEN_Pos (0) /!< CLK PWRCTL: HXTEN Position /
sahilmgandhi	18:6a4db94011d3	3613	#define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /!< CLK PWRCTL: HXTEN Mask /
sahilmgandhi	18:6a4db94011d3	3614
sahilmgandhi	18:6a4db94011d3	3615	#define CLK_PWRCTL_LXTEN_Pos (1) /!< CLK PWRCTL: LXTEN Position /
sahilmgandhi	18:6a4db94011d3	3616	#define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /!< CLK PWRCTL: LXTEN Mask /
sahilmgandhi	18:6a4db94011d3	3617
sahilmgandhi	18:6a4db94011d3	3618	#define CLK_PWRCTL_HIRCEN_Pos (2) /!< CLK PWRCTL: HIRCEN Position /
sahilmgandhi	18:6a4db94011d3	3619	#define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /!< CLK PWRCTL: HIRCEN Mask /
sahilmgandhi	18:6a4db94011d3	3620
sahilmgandhi	18:6a4db94011d3	3621	#define CLK_PWRCTL_LIRCEN_Pos (3) /!< CLK PWRCTL: LIRCEN Position /
sahilmgandhi	18:6a4db94011d3	3622	#define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /!< CLK PWRCTL: LIRCEN Mask /
sahilmgandhi	18:6a4db94011d3	3623
sahilmgandhi	18:6a4db94011d3	3624	#define CLK_PWRCTL_PDWKDLY_Pos (4) /!< CLK PWRCTL: PDWKDLY Position /
sahilmgandhi	18:6a4db94011d3	3625	#define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) /!< CLK PWRCTL: PDWKDLY Mask /
sahilmgandhi	18:6a4db94011d3	3626
sahilmgandhi	18:6a4db94011d3	3627	#define CLK_PWRCTL_PDWKIEN_Pos (5) /!< CLK PWRCTL: PDWKIEN Position /
sahilmgandhi	18:6a4db94011d3	3628	#define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /!< CLK PWRCTL: PDWKIEN Mask /
sahilmgandhi	18:6a4db94011d3	3629
sahilmgandhi	18:6a4db94011d3	3630	#define CLK_PWRCTL_PDWKIF_Pos (6) /!< CLK PWRCTL: PDWKIF Position /
sahilmgandhi	18:6a4db94011d3	3631	#define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /!< CLK PWRCTL: PDWKIF Mask /
sahilmgandhi	18:6a4db94011d3	3632
sahilmgandhi	18:6a4db94011d3	3633	#define CLK_PWRCTL_PDEN_Pos (7) /!< CLK PWRCTL: PDEN Position /
sahilmgandhi	18:6a4db94011d3	3634	#define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /!< CLK PWRCTL: PDEN Mask /
sahilmgandhi	18:6a4db94011d3	3635
sahilmgandhi	18:6a4db94011d3	3636	#define CLK_PWRCTL_PDWTCPU_Pos (8) /!< CLK PWRCTL: PDWTCPU Position /
sahilmgandhi	18:6a4db94011d3	3637	#define CLK_PWRCTL_PDWTCPU_Msk (0x1ul << CLK_PWRCTL_PDWTCPU_Pos) /!< CLK PWRCTL: PDWTCPU Mask /
sahilmgandhi	18:6a4db94011d3	3638
sahilmgandhi	18:6a4db94011d3	3639	#define CLK_PWRCTL_DBPDEN_Pos (9) /!< CLK PWRCTL: DBPDEN Position /
sahilmgandhi	18:6a4db94011d3	3640	#define CLK_PWRCTL_DBPDEN_Msk (0x1ul << CLK_PWRCTL_DBPDEN_Pos) /!< CLK PWRCTL: DBPDEN Mask /
sahilmgandhi	18:6a4db94011d3	3641
sahilmgandhi	18:6a4db94011d3	3642	#define CLK_AHBCLK_PDMACKEN_Pos (1) /!< CLK AHBCLK: PDMACKEN Position /
sahilmgandhi	18:6a4db94011d3	3643	#define CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos) /!< CLK AHBCLK: PDMACKEN Mask /
sahilmgandhi	18:6a4db94011d3	3644
sahilmgandhi	18:6a4db94011d3	3645	#define CLK_AHBCLK_ISPCKEN_Pos (2) /!< CLK AHBCLK: ISPCKEN Position /
sahilmgandhi	18:6a4db94011d3	3646	#define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) /!< CLK AHBCLK: ISPCKEN Mask /
sahilmgandhi	18:6a4db94011d3	3647
sahilmgandhi	18:6a4db94011d3	3648	#define CLK_AHBCLK_EBICKEN_Pos (3) /!< CLK AHBCLK: EBICKEN Position /
sahilmgandhi	18:6a4db94011d3	3649	#define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) /!< CLK AHBCLK: EBICKEN Mask /
sahilmgandhi	18:6a4db94011d3	3650
sahilmgandhi	18:6a4db94011d3	3651	#define CLK_AHBCLK_USBHCKEN_Pos (4) /!< CLK AHBCLK: USBHCKEN Position /
sahilmgandhi	18:6a4db94011d3	3652	#define CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos) /!< CLK AHBCLK: USBHCKEN Mask /
sahilmgandhi	18:6a4db94011d3	3653
sahilmgandhi	18:6a4db94011d3	3654	#define CLK_AHBCLK_EMACCKEN_Pos (5) /!< CLK AHBCLK: EMACCKEN Position /
sahilmgandhi	18:6a4db94011d3	3655	#define CLK_AHBCLK_EMACCKEN_Msk (0x1ul << CLK_AHBCLK_EMACCKEN_Pos) /!< CLK AHBCLK: EMACCKEN Mask /
sahilmgandhi	18:6a4db94011d3	3656
sahilmgandhi	18:6a4db94011d3	3657	#define CLK_AHBCLK_SDHCKEN_Pos (6) /!< CLK AHBCLK: SDHCKEN Position /
sahilmgandhi	18:6a4db94011d3	3658	#define CLK_AHBCLK_SDHCKEN_Msk (0x1ul << CLK_AHBCLK_SDHCKEN_Pos) /!< CLK AHBCLK: SDHCKEN Mask /
sahilmgandhi	18:6a4db94011d3	3659
sahilmgandhi	18:6a4db94011d3	3660	#define CLK_AHBCLK_CRCCKEN_Pos (7) /!< CLK AHBCLK: CRCCKEN Position /
sahilmgandhi	18:6a4db94011d3	3661	#define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) /!< CLK AHBCLK: CRCCKEN Mask /
sahilmgandhi	18:6a4db94011d3	3662
sahilmgandhi	18:6a4db94011d3	3663	#define CLK_AHBCLK_CAPCKEN_Pos (8) /!< CLK AHBCLK: CAPCKEN Position /
sahilmgandhi	18:6a4db94011d3	3664	#define CLK_AHBCLK_CAPCKEN_Msk (0x1ul << CLK_AHBCLK_CAPCKEN_Pos) /!< CLK AHBCLK: CAPCKEN Mask /
sahilmgandhi	18:6a4db94011d3	3665
sahilmgandhi	18:6a4db94011d3	3666	#define CLK_AHBCLK_SENCKEN_Pos (9) /!< CLK AHBCLK: SENCKEN Position /
sahilmgandhi	18:6a4db94011d3	3667	#define CLK_AHBCLK_SENCKEN_Msk (0x1ul << CLK_AHBCLK_SENCKEN_Pos) /!< CLK AHBCLK: SENCKEN Mask /
sahilmgandhi	18:6a4db94011d3	3668
sahilmgandhi	18:6a4db94011d3	3669	#define CLK_AHBCLK_USBDCKEN_Pos (10) /!< CLK AHBCLK: USBDCKEN Position /
sahilmgandhi	18:6a4db94011d3	3670	#define CLK_AHBCLK_USBDCKEN_Msk (0x1ul << CLK_AHBCLK_USBDCKEN_Pos) /!< CLK AHBCLK: USBDCKEN Mask /
sahilmgandhi	18:6a4db94011d3	3671
sahilmgandhi	18:6a4db94011d3	3672	#define CLK_AHBCLK_CRPTCKEN_Pos (12) /!< CLK AHBCLK: CRPTCKEN Position /
sahilmgandhi	18:6a4db94011d3	3673	#define CLK_AHBCLK_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK_CRPTCKEN_Pos) /!< CLK AHBCLK: CRPTCKEN Mask /
sahilmgandhi	18:6a4db94011d3	3674
sahilmgandhi	18:6a4db94011d3	3675	#define CLK_APBCLK0_WDTCKEN_Pos (0) /!< CLK APBCLK0: WDTCKEN Position /
sahilmgandhi	18:6a4db94011d3	3676	#define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) /!< CLK APBCLK0: WDTCKEN Mask /
sahilmgandhi	18:6a4db94011d3	3677
sahilmgandhi	18:6a4db94011d3	3678	#define CLK_APBCLK0_RTCCKEN_Pos (1) /!< CLK APBCLK0: RTCCKEN Position /
sahilmgandhi	18:6a4db94011d3	3679	#define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /!< CLK APBCLK0: RTCCKEN Mask /
sahilmgandhi	18:6a4db94011d3	3680
sahilmgandhi	18:6a4db94011d3	3681	#define CLK_APBCLK0_TMR0CKEN_Pos (2) /!< CLK APBCLK0: TMR0CKEN Position /
sahilmgandhi	18:6a4db94011d3	3682	#define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /!< CLK APBCLK0: TMR0CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3683
sahilmgandhi	18:6a4db94011d3	3684	#define CLK_APBCLK0_TMR1CKEN_Pos (3) /!< CLK APBCLK0: TMR1CKEN Position /
sahilmgandhi	18:6a4db94011d3	3685	#define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /!< CLK APBCLK0: TMR1CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3686
sahilmgandhi	18:6a4db94011d3	3687	#define CLK_APBCLK0_TMR2CKEN_Pos (4) /!< CLK APBCLK0: TMR2CKEN Position /
sahilmgandhi	18:6a4db94011d3	3688	#define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /!< CLK APBCLK0: TMR2CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3689
sahilmgandhi	18:6a4db94011d3	3690	#define CLK_APBCLK0_TMR3CKEN_Pos (5) /!< CLK APBCLK0: TMR3CKEN Position /
sahilmgandhi	18:6a4db94011d3	3691	#define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /!< CLK APBCLK0: TMR3CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3692
sahilmgandhi	18:6a4db94011d3	3693	#define CLK_APBCLK0_CLKOCKEN_Pos (6) /!< CLK APBCLK0: CLKOCKEN Position /
sahilmgandhi	18:6a4db94011d3	3694	#define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /!< CLK APBCLK0: CLKOCKEN Mask /
sahilmgandhi	18:6a4db94011d3	3695
sahilmgandhi	18:6a4db94011d3	3696	#define CLK_APBCLK0_ACMPCKEN_Pos (7) /!< CLK APBCLK0: ACMPCKEN Position /
sahilmgandhi	18:6a4db94011d3	3697	#define CLK_APBCLK0_ACMPCKEN_Msk (0x1ul << CLK_APBCLK0_ACMPCKEN_Pos) /!< CLK APBCLK0: ACMPCKEN Mask /
sahilmgandhi	18:6a4db94011d3	3698
sahilmgandhi	18:6a4db94011d3	3699	#define CLK_APBCLK0_I2C0CKEN_Pos (8) /!< CLK APBCLK0: I2C0CKEN Position /
sahilmgandhi	18:6a4db94011d3	3700	#define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /!< CLK APBCLK0: I2C0CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3701
sahilmgandhi	18:6a4db94011d3	3702	#define CLK_APBCLK0_I2C1CKEN_Pos (9) /!< CLK APBCLK0: I2C1CKEN Position /
sahilmgandhi	18:6a4db94011d3	3703	#define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /!< CLK APBCLK0: I2C1CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3704
sahilmgandhi	18:6a4db94011d3	3705	#define CLK_APBCLK0_I2C2CKEN_Pos (10) /!< CLK APBCLK0: I2C2CKEN Position /
sahilmgandhi	18:6a4db94011d3	3706	#define CLK_APBCLK0_I2C2CKEN_Msk (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos) /!< CLK APBCLK0: I2C2CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3707
sahilmgandhi	18:6a4db94011d3	3708	#define CLK_APBCLK0_I2C3CKEN_Pos (11) /!< CLK APBCLK0: I2C3CKEN Position /
sahilmgandhi	18:6a4db94011d3	3709	#define CLK_APBCLK0_I2C3CKEN_Msk (0x1ul << CLK_APBCLK0_I2C3CKEN_Pos) /!< CLK APBCLK0: I2C3CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3710
sahilmgandhi	18:6a4db94011d3	3711	#define CLK_APBCLK0_SPI0CKEN_Pos (12) /!< CLK APBCLK0: SPI0CKEN Position /
sahilmgandhi	18:6a4db94011d3	3712	#define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /!< CLK APBCLK0: SPI0CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3713
sahilmgandhi	18:6a4db94011d3	3714	#define CLK_APBCLK0_SPI1CKEN_Pos (13) /!< CLK APBCLK0: SPI1CKEN Position /
sahilmgandhi	18:6a4db94011d3	3715	#define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) /!< CLK APBCLK0: SPI1CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3716
sahilmgandhi	18:6a4db94011d3	3717	#define CLK_APBCLK0_SPI2CKEN_Pos (14) /!< CLK APBCLK0: SPI2CKEN Position /
sahilmgandhi	18:6a4db94011d3	3718	#define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) /!< CLK APBCLK0: SPI2CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3719
sahilmgandhi	18:6a4db94011d3	3720	#define CLK_APBCLK0_SPI3CKEN_Pos (15) /!< CLK APBCLK0: SPI3CKEN Position /
sahilmgandhi	18:6a4db94011d3	3721	#define CLK_APBCLK0_SPI3CKEN_Msk (0x1ul << CLK_APBCLK0_SPI3CKEN_Pos) /!< CLK APBCLK0: SPI3CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3722
sahilmgandhi	18:6a4db94011d3	3723	#define CLK_APBCLK0_UART0CKEN_Pos (16) /!< CLK APBCLK0: UART0CKEN Position /
sahilmgandhi	18:6a4db94011d3	3724	#define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /!< CLK APBCLK0: UART0CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3725
sahilmgandhi	18:6a4db94011d3	3726	#define CLK_APBCLK0_UART1CKEN_Pos (17) /!< CLK APBCLK0: UART1CKEN Position /
sahilmgandhi	18:6a4db94011d3	3727	#define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /!< CLK APBCLK0: UART1CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3728
sahilmgandhi	18:6a4db94011d3	3729	#define CLK_APBCLK0_UART2CKEN_Pos (18) /!< CLK APBCLK0: UART2CKEN Position /
sahilmgandhi	18:6a4db94011d3	3730	#define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /!< CLK APBCLK0: UART2CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3731
sahilmgandhi	18:6a4db94011d3	3732	#define CLK_APBCLK0_UART3CKEN_Pos (19) /!< CLK APBCLK0: UART3CKEN Position /
sahilmgandhi	18:6a4db94011d3	3733	#define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /!< CLK APBCLK0: UART3CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3734
sahilmgandhi	18:6a4db94011d3	3735	#define CLK_APBCLK0_UART4CKEN_Pos (20) /!< CLK APBCLK0: UART4CKEN Position /
sahilmgandhi	18:6a4db94011d3	3736	#define CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos) /!< CLK APBCLK0: UART4CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3737
sahilmgandhi	18:6a4db94011d3	3738	#define CLK_APBCLK0_UART5CKEN_Pos (21) /!< CLK APBCLK0: UART5CKEN Position /
sahilmgandhi	18:6a4db94011d3	3739	#define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) /!< CLK APBCLK0: UART5CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3740
sahilmgandhi	18:6a4db94011d3	3741	#define CLK_APBCLK0_CAN0CKEN_Pos (24) /!< CLK APBCLK0: CAN0CKEN Position /
sahilmgandhi	18:6a4db94011d3	3742	#define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos) /!< CLK APBCLK0: CAN0CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3743
sahilmgandhi	18:6a4db94011d3	3744	#define CLK_APBCLK0_CAN1CKEN_Pos (25) /!< CLK APBCLK0: CAN1CKEN Position /
sahilmgandhi	18:6a4db94011d3	3745	#define CLK_APBCLK0_CAN1CKEN_Msk (0x1ul << CLK_APBCLK0_CAN1CKEN_Pos) /!< CLK APBCLK0: CAN1CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3746
sahilmgandhi	18:6a4db94011d3	3747	#define CLK_APBCLK0_OTGCKEN_Pos (26) /!< CLK APBCLK0: OTGCKEN Position /
sahilmgandhi	18:6a4db94011d3	3748	#define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) /!< CLK APBCLK0: OTGCKEN Mask /
sahilmgandhi	18:6a4db94011d3	3749
sahilmgandhi	18:6a4db94011d3	3750	#define CLK_APBCLK0_ADCCKEN_Pos (28) /!< CLK APBCLK0: ADCCKEN Position /
sahilmgandhi	18:6a4db94011d3	3751	#define CLK_APBCLK0_ADCCKEN_Msk (0x1ul << CLK_APBCLK0_ADCCKEN_Pos) /!< CLK APBCLK0: ADCCKEN Mask /
sahilmgandhi	18:6a4db94011d3	3752
sahilmgandhi	18:6a4db94011d3	3753	#define CLK_APBCLK0_I2S0CKEN_Pos (29) /!< CLK APBCLK0: I2S0CKEN Position /
sahilmgandhi	18:6a4db94011d3	3754	#define CLK_APBCLK0_I2S0CKEN_Msk (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos) /!< CLK APBCLK0: I2S0CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3755
sahilmgandhi	18:6a4db94011d3	3756	#define CLK_APBCLK0_I2S1CKEN_Pos (30) /!< CLK APBCLK0: I2S1CKEN Position /
sahilmgandhi	18:6a4db94011d3	3757	#define CLK_APBCLK0_I2S1CKEN_Msk (0x1ul << CLK_APBCLK0_I2S1CKEN_Pos) /!< CLK APBCLK0: I2S1CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3758
sahilmgandhi	18:6a4db94011d3	3759	#define CLK_APBCLK0_PS2CKEN_Pos (31) /!< CLK APBCLK0: PS2CKEN Position /
sahilmgandhi	18:6a4db94011d3	3760	#define CLK_APBCLK0_PS2CKEN_Msk (0x1ul << CLK_APBCLK0_PS2CKEN_Pos) /!< CLK APBCLK0: PS2CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3761
sahilmgandhi	18:6a4db94011d3	3762	#define CLK_APBCLK1_SC0CKEN_Pos (0) /!< CLK APBCLK1: SC0CKEN Position /
sahilmgandhi	18:6a4db94011d3	3763	#define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) /!< CLK APBCLK1: SC0CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3764
sahilmgandhi	18:6a4db94011d3	3765	#define CLK_APBCLK1_SC1CKEN_Pos (1) /!< CLK APBCLK1: SC1CKEN Position /
sahilmgandhi	18:6a4db94011d3	3766	#define CLK_APBCLK1_SC1CKEN_Msk (0x1ul << CLK_APBCLK1_SC1CKEN_Pos) /!< CLK APBCLK1: SC1CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3767
sahilmgandhi	18:6a4db94011d3	3768	#define CLK_APBCLK1_SC2CKEN_Pos (2) /!< CLK APBCLK1: SC2CKEN Position /
sahilmgandhi	18:6a4db94011d3	3769	#define CLK_APBCLK1_SC2CKEN_Msk (0x1ul << CLK_APBCLK1_SC2CKEN_Pos) /!< CLK APBCLK1: SC2CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3770
sahilmgandhi	18:6a4db94011d3	3771	#define CLK_APBCLK1_SC3CKEN_Pos (3) /!< CLK APBCLK1: SC3CKEN Position /
sahilmgandhi	18:6a4db94011d3	3772	#define CLK_APBCLK1_SC3CKEN_Msk (0x1ul << CLK_APBCLK1_SC3CKEN_Pos) /!< CLK APBCLK1: SC3CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3773
sahilmgandhi	18:6a4db94011d3	3774	#define CLK_APBCLK1_SC4CKEN_Pos (4) /!< CLK APBCLK1: SC4CKEN Position /
sahilmgandhi	18:6a4db94011d3	3775	#define CLK_APBCLK1_SC4CKEN_Msk (0x1ul << CLK_APBCLK1_SC4CKEN_Pos) /!< CLK APBCLK1: SC4CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3776
sahilmgandhi	18:6a4db94011d3	3777	#define CLK_APBCLK1_SC5CKEN_Pos (5) /!< CLK APBCLK1: SC5CKEN Position /
sahilmgandhi	18:6a4db94011d3	3778	#define CLK_APBCLK1_SC5CKEN_Msk (0x1ul << CLK_APBCLK1_SC5CKEN_Pos) /!< CLK APBCLK1: SC5CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3779
sahilmgandhi	18:6a4db94011d3	3780	#define CLK_APBCLK1_I2C4CKEN_Pos (8) /!< CLK APBCLK1: I2C4CKEN Position /
sahilmgandhi	18:6a4db94011d3	3781	#define CLK_APBCLK1_I2C4CKEN_Msk (0x1ul << CLK_APBCLK1_I2C4CKEN_Pos) /!< CLK APBCLK1: I2C4CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3782
sahilmgandhi	18:6a4db94011d3	3783	#define CLK_APBCLK1_PWM0CH01CKEN_Pos (16) /!< CLK APBCLK1: PWM0CH01CKEN Position /
sahilmgandhi	18:6a4db94011d3	3784	#define CLK_APBCLK1_PWM0CH01CKEN_Msk (0x1ul << CLK_APBCLK1_PWM0CH01CKEN_Pos) /!< CLK APBCLK1: PWM0CH01CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3785
sahilmgandhi	18:6a4db94011d3	3786	#define CLK_APBCLK1_PWM0CH23CKEN_Pos (17) /!< CLK APBCLK1: PWM0CH23CKEN Position /
sahilmgandhi	18:6a4db94011d3	3787	#define CLK_APBCLK1_PWM0CH23CKEN_Msk (0x1ul << CLK_APBCLK1_PWM0CH23CKEN_Pos) /!< CLK APBCLK1: PWM0CH23CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3788
sahilmgandhi	18:6a4db94011d3	3789	#define CLK_APBCLK1_PWM0CH45CKEN_Pos (18) /!< CLK APBCLK1: PWM0CH45CKEN Position /
sahilmgandhi	18:6a4db94011d3	3790	#define CLK_APBCLK1_PWM0CH45CKEN_Msk (0x1ul << CLK_APBCLK1_PWM0CH45CKEN_Pos) /!< CLK APBCLK1: PWM0CH45CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3791
sahilmgandhi	18:6a4db94011d3	3792	#define CLK_APBCLK1_PWM1CH01CKEN_Pos (19) /!< CLK APBCLK1: PWM1CH01CKEN Position /
sahilmgandhi	18:6a4db94011d3	3793	#define CLK_APBCLK1_PWM1CH01CKEN_Msk (0x1ul << CLK_APBCLK1_PWM1CH01CKEN_Pos) /!< CLK APBCLK1: PWM1CH01CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3794
sahilmgandhi	18:6a4db94011d3	3795	#define CLK_APBCLK1_PWM1CH23CKEN_Pos (20) /!< CLK APBCLK1: PWM1CH23CKEN Position /
sahilmgandhi	18:6a4db94011d3	3796	#define CLK_APBCLK1_PWM1CH23CKEN_Msk (0x1ul << CLK_APBCLK1_PWM1CH23CKEN_Pos) /!< CLK APBCLK1: PWM1CH23CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3797
sahilmgandhi	18:6a4db94011d3	3798	#define CLK_APBCLK1_PWM1CH45CKEN_Pos (21) /!< CLK APBCLK1: PWM1CH45CKEN Position /
sahilmgandhi	18:6a4db94011d3	3799	#define CLK_APBCLK1_PWM1CH45CKEN_Msk (0x1ul << CLK_APBCLK1_PWM1CH45CKEN_Pos) /!< CLK APBCLK1: PWM1CH45CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3800
sahilmgandhi	18:6a4db94011d3	3801	#define CLK_APBCLK1_QEI0CKEN_Pos (22) /!< CLK APBCLK1: QEI0CKEN Position /
sahilmgandhi	18:6a4db94011d3	3802	#define CLK_APBCLK1_QEI0CKEN_Msk (0x1ul << CLK_APBCLK1_QEI0CKEN_Pos) /!< CLK APBCLK1: QEI0CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3803
sahilmgandhi	18:6a4db94011d3	3804	#define CLK_APBCLK1_QEI1CKEN_Pos (23) /!< CLK APBCLK1: QEI1CKEN Position /
sahilmgandhi	18:6a4db94011d3	3805	#define CLK_APBCLK1_QEI1CKEN_Msk (0x1ul << CLK_APBCLK1_QEI1CKEN_Pos) /!< CLK APBCLK1: QEI1CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3806
sahilmgandhi	18:6a4db94011d3	3807	#define CLK_APBCLK1_ECAP0CKEN_Pos (26) /!< CLK APBCLK1: ECAP0CKEN Position /
sahilmgandhi	18:6a4db94011d3	3808	#define CLK_APBCLK1_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos) /!< CLK APBCLK1: ECAP0CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3809
sahilmgandhi	18:6a4db94011d3	3810	#define CLK_APBCLK1_ECAP1CKEN_Pos (27) /!< CLK APBCLK1: ECAP1CKEN Position /
sahilmgandhi	18:6a4db94011d3	3811	#define CLK_APBCLK1_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos) /!< CLK APBCLK1: ECAP1CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3812
sahilmgandhi	18:6a4db94011d3	3813	#define CLK_APBCLK1_EPWM0CKEN_Pos (28) /!< CLK APBCLK1: EPWM0CKEN Position /
sahilmgandhi	18:6a4db94011d3	3814	#define CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos) /!< CLK APBCLK1: EPWM0CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3815
sahilmgandhi	18:6a4db94011d3	3816	#define CLK_APBCLK1_EPWM1CKEN_Pos (29) /!< CLK APBCLK1: EPWM1CKEN Position /
sahilmgandhi	18:6a4db94011d3	3817	#define CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos) /!< CLK APBCLK1: EPWM1CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3818
sahilmgandhi	18:6a4db94011d3	3819	#define CLK_APBCLK1_OPACKEN_Pos (30) /!< CLK APBCLK1: OPACKEN Position /
sahilmgandhi	18:6a4db94011d3	3820	#define CLK_APBCLK1_OPACKEN_Msk (0x1ul << CLK_APBCLK1_OPACKEN_Pos) /!< CLK APBCLK1: OPACKEN Mask /
sahilmgandhi	18:6a4db94011d3	3821
sahilmgandhi	18:6a4db94011d3	3822	#define CLK_APBCLK1_EADCCKEN_Pos (31) /!< CLK APBCLK1: EADCCKEN Position /
sahilmgandhi	18:6a4db94011d3	3823	#define CLK_APBCLK1_EADCCKEN_Msk (0x1ul << CLK_APBCLK1_EADCCKEN_Pos) /!< CLK APBCLK1: EADCCKEN Mask /
sahilmgandhi	18:6a4db94011d3	3824
sahilmgandhi	18:6a4db94011d3	3825	#define CLK_CLKSEL0_HCLKSEL_Pos (0) /!< CLK CLKSEL0: HCLKSEL Position /
sahilmgandhi	18:6a4db94011d3	3826	#define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) /!< CLK CLKSEL0: HCLKSEL Mask /
sahilmgandhi	18:6a4db94011d3	3827
sahilmgandhi	18:6a4db94011d3	3828	#define CLK_CLKSEL0_STCLKSEL_Pos (3) /!< CLK CLKSEL0: STCLKSEL Position /
sahilmgandhi	18:6a4db94011d3	3829	#define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /!< CLK CLKSEL0: STCLKSEL Mask /
sahilmgandhi	18:6a4db94011d3	3830
sahilmgandhi	18:6a4db94011d3	3831	#define CLK_CLKSEL0_PCLKSEL_Pos (6) /!< CLK CLKSEL0: PCLKSEL Position /
sahilmgandhi	18:6a4db94011d3	3832	#define CLK_CLKSEL0_PCLKSEL_Msk (0x1ul << CLK_CLKSEL0_PCLKSEL_Pos) /!< CLK CLKSEL0: PCLKSEL Mask /
sahilmgandhi	18:6a4db94011d3	3833
sahilmgandhi	18:6a4db94011d3	3834	#define CLK_CLKSEL0_USBHSEL_Pos (8) /!< CLK CLKSEL0: USBHSEL Position /
sahilmgandhi	18:6a4db94011d3	3835	#define CLK_CLKSEL0_USBHSEL_Msk (0x1ul << CLK_CLKSEL0_USBHSEL_Pos) /!< CLK CLKSEL0: USBHSEL Mask /
sahilmgandhi	18:6a4db94011d3	3836
sahilmgandhi	18:6a4db94011d3	3837	#define CLK_CLKSEL0_CAPSEL_Pos (16) /!< CLK CLKSEL0: CAPSEL Position /
sahilmgandhi	18:6a4db94011d3	3838	#define CLK_CLKSEL0_CAPSEL_Msk (0x3ul << CLK_CLKSEL0_CAPSEL_Pos) /!< CLK CLKSEL0: CAPSEL Mask /
sahilmgandhi	18:6a4db94011d3	3839
sahilmgandhi	18:6a4db94011d3	3840	#define CLK_CLKSEL0_SDHSEL_Pos (20) /!< CLK CLKSEL0: SDHSEL Position /
sahilmgandhi	18:6a4db94011d3	3841	#define CLK_CLKSEL0_SDHSEL_Msk (0x3ul << CLK_CLKSEL0_SDHSEL_Pos) /!< CLK CLKSEL0: SDHSEL Mask /
sahilmgandhi	18:6a4db94011d3	3842
sahilmgandhi	18:6a4db94011d3	3843	#define CLK_CLKSEL1_WDTSEL_Pos (0) /!< CLK CLKSEL1: WDTSEL Position /
sahilmgandhi	18:6a4db94011d3	3844	#define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /!< CLK CLKSEL1: WDTSEL Mask /
sahilmgandhi	18:6a4db94011d3	3845
sahilmgandhi	18:6a4db94011d3	3846	#define CLK_CLKSEL1_ADCSEL_Pos (2) /!< CLK CLKSEL1: ADCSEL Position /
sahilmgandhi	18:6a4db94011d3	3847	#define CLK_CLKSEL1_ADCSEL_Msk (0x3ul << CLK_CLKSEL1_ADCSEL_Pos) /!< CLK CLKSEL1: ADCSEL Mask /
sahilmgandhi	18:6a4db94011d3	3848
sahilmgandhi	18:6a4db94011d3	3849	#define CLK_CLKSEL1_SPI0SEL_Pos (4) /!< CLK CLKSEL1: SPI0SEL Position /
sahilmgandhi	18:6a4db94011d3	3850	#define CLK_CLKSEL1_SPI0SEL_Msk (0x1ul << CLK_CLKSEL1_SPI0SEL_Pos) /!< CLK CLKSEL1: SPI0SEL Mask /
sahilmgandhi	18:6a4db94011d3	3851
sahilmgandhi	18:6a4db94011d3	3852	#define CLK_CLKSEL1_SPI1SEL_Pos (5) /!< CLK CLKSEL1: SPI1SEL Position /
sahilmgandhi	18:6a4db94011d3	3853	#define CLK_CLKSEL1_SPI1SEL_Msk (0x1ul << CLK_CLKSEL1_SPI1SEL_Pos) /!< CLK CLKSEL1: SPI1SEL Mask /
sahilmgandhi	18:6a4db94011d3	3854
sahilmgandhi	18:6a4db94011d3	3855	#define CLK_CLKSEL1_SPI2SEL_Pos (6) /!< CLK CLKSEL1: SPI2SEL Position /
sahilmgandhi	18:6a4db94011d3	3856	#define CLK_CLKSEL1_SPI2SEL_Msk (0x1ul << CLK_CLKSEL1_SPI2SEL_Pos) /!< CLK CLKSEL1: SPI2SEL Mask /
sahilmgandhi	18:6a4db94011d3	3857
sahilmgandhi	18:6a4db94011d3	3858	#define CLK_CLKSEL1_SPI3SEL_Pos (7) /!< CLK CLKSEL1: SPI3SEL Position /
sahilmgandhi	18:6a4db94011d3	3859	#define CLK_CLKSEL1_SPI3SEL_Msk (0x1ul << CLK_CLKSEL1_SPI3SEL_Pos) /!< CLK CLKSEL1: SPI3SEL Mask /
sahilmgandhi	18:6a4db94011d3	3860
sahilmgandhi	18:6a4db94011d3	3861	#define CLK_CLKSEL1_TMR0SEL_Pos (8) /!< CLK CLKSEL1: TMR0SEL Position /
sahilmgandhi	18:6a4db94011d3	3862	#define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /!< CLK CLKSEL1: TMR0SEL Mask /
sahilmgandhi	18:6a4db94011d3	3863
sahilmgandhi	18:6a4db94011d3	3864	#define CLK_CLKSEL1_TMR1SEL_Pos (12) /!< CLK CLKSEL1: TMR1SEL Position /
sahilmgandhi	18:6a4db94011d3	3865	#define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /!< CLK CLKSEL1: TMR1SEL Mask /
sahilmgandhi	18:6a4db94011d3	3866
sahilmgandhi	18:6a4db94011d3	3867	#define CLK_CLKSEL1_TMR2SEL_Pos (16) /!< CLK CLKSEL1: TMR2SEL Position /
sahilmgandhi	18:6a4db94011d3	3868	#define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /!< CLK CLKSEL1: TMR2SEL Mask /
sahilmgandhi	18:6a4db94011d3	3869
sahilmgandhi	18:6a4db94011d3	3870	#define CLK_CLKSEL1_TMR3SEL_Pos (20) /!< CLK CLKSEL1: TMR3SEL Position /
sahilmgandhi	18:6a4db94011d3	3871	#define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /!< CLK CLKSEL1: TMR3SEL Mask /
sahilmgandhi	18:6a4db94011d3	3872
sahilmgandhi	18:6a4db94011d3	3873	#define CLK_CLKSEL1_UARTSEL_Pos (24) /!< CLK CLKSEL1: UARTSEL Position /
sahilmgandhi	18:6a4db94011d3	3874	#define CLK_CLKSEL1_UARTSEL_Msk (0x3ul << CLK_CLKSEL1_UARTSEL_Pos) /!< CLK CLKSEL1: UARTSEL Mask /
sahilmgandhi	18:6a4db94011d3	3875
sahilmgandhi	18:6a4db94011d3	3876	#define CLK_CLKSEL1_CLKOSEL_Pos (28) /!< CLK CLKSEL1: CLKOSEL Position /
sahilmgandhi	18:6a4db94011d3	3877	#define CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos) /!< CLK CLKSEL1: CLKOSEL Mask /
sahilmgandhi	18:6a4db94011d3	3878
sahilmgandhi	18:6a4db94011d3	3879	#define CLK_CLKSEL1_WWDTSEL_Pos (30) /!< CLK CLKSEL1: WWDTSEL Position /
sahilmgandhi	18:6a4db94011d3	3880	#define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /!< CLK CLKSEL1: WWDTSEL Mask /
sahilmgandhi	18:6a4db94011d3	3881
sahilmgandhi	18:6a4db94011d3	3882	#define CLK_CLKSEL2_PWM0CH01SEL_Pos (0) /!< CLK CLKSEL2: PWM0CH01SEL Position /
sahilmgandhi	18:6a4db94011d3	3883	#define CLK_CLKSEL2_PWM0CH01SEL_Msk (0x7ul << CLK_CLKSEL2_PWM0CH01SEL_Pos) /!< CLK CLKSEL2: PWM0CH01SEL Mask /
sahilmgandhi	18:6a4db94011d3	3884
sahilmgandhi	18:6a4db94011d3	3885	#define CLK_CLKSEL2_PWM0CH23SEL_Pos (4) /!< CLK CLKSEL2: PWM0CH23SEL Position /
sahilmgandhi	18:6a4db94011d3	3886	#define CLK_CLKSEL2_PWM0CH23SEL_Msk (0x7ul << CLK_CLKSEL2_PWM0CH23SEL_Pos) /!< CLK CLKSEL2: PWM0CH23SEL Mask /
sahilmgandhi	18:6a4db94011d3	3887
sahilmgandhi	18:6a4db94011d3	3888	#define CLK_CLKSEL2_PWM0CH45SEL_Pos (8) /!< CLK CLKSEL2: PWM0CH45SEL Position /
sahilmgandhi	18:6a4db94011d3	3889	#define CLK_CLKSEL2_PWM0CH45SEL_Msk (0x7ul << CLK_CLKSEL2_PWM0CH45SEL_Pos) /!< CLK CLKSEL2: PWM0CH45SEL Mask /
sahilmgandhi	18:6a4db94011d3	3890
sahilmgandhi	18:6a4db94011d3	3891	#define CLK_CLKSEL2_PWM1CH01SEL_Pos (12) /!< CLK CLKSEL2: PWM1CH01SEL Position /
sahilmgandhi	18:6a4db94011d3	3892	#define CLK_CLKSEL2_PWM1CH01SEL_Msk (0x7ul << CLK_CLKSEL2_PWM1CH01SEL_Pos) /!< CLK CLKSEL2: PWM1CH01SEL Mask /
sahilmgandhi	18:6a4db94011d3	3893
sahilmgandhi	18:6a4db94011d3	3894	#define CLK_CLKSEL2_PWM1CH23SEL_Pos (16) /!< CLK CLKSEL2: PWM1CH23SEL Position /
sahilmgandhi	18:6a4db94011d3	3895	#define CLK_CLKSEL2_PWM1CH23SEL_Msk (0x7ul << CLK_CLKSEL2_PWM1CH23SEL_Pos) /!< CLK CLKSEL2: PWM1CH23SEL Mask /
sahilmgandhi	18:6a4db94011d3	3896
sahilmgandhi	18:6a4db94011d3	3897	#define CLK_CLKSEL2_PWM1CH45SEL_Pos (20) /!< CLK CLKSEL2: PWM1CH45SEL Position /
sahilmgandhi	18:6a4db94011d3	3898	#define CLK_CLKSEL2_PWM1CH45SEL_Msk (0x7ul << CLK_CLKSEL2_PWM1CH45SEL_Pos) /!< CLK CLKSEL2: PWM1CH45SEL Mask /
sahilmgandhi	18:6a4db94011d3	3899
sahilmgandhi	18:6a4db94011d3	3900	#define CLK_CLKSEL3_SC0SEL_Pos (0) /!< CLK CLKSEL3: SC0SEL Position /
sahilmgandhi	18:6a4db94011d3	3901	#define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /!< CLK CLKSEL3: SC0SEL Mask /
sahilmgandhi	18:6a4db94011d3	3902
sahilmgandhi	18:6a4db94011d3	3903	#define CLK_CLKSEL3_SC1SEL_Pos (2) /!< CLK CLKSEL3: SC1SEL Position /
sahilmgandhi	18:6a4db94011d3	3904	#define CLK_CLKSEL3_SC1SEL_Msk (0x3ul << CLK_CLKSEL3_SC1SEL_Pos) /!< CLK CLKSEL3: SC1SEL Mask /
sahilmgandhi	18:6a4db94011d3	3905
sahilmgandhi	18:6a4db94011d3	3906	#define CLK_CLKSEL3_SC2SEL_Pos (4) /!< CLK CLKSEL3: SC2SEL Position /
sahilmgandhi	18:6a4db94011d3	3907	#define CLK_CLKSEL3_SC2SEL_Msk (0x3ul << CLK_CLKSEL3_SC2SEL_Pos) /!< CLK CLKSEL3: SC2SEL Mask /
sahilmgandhi	18:6a4db94011d3	3908
sahilmgandhi	18:6a4db94011d3	3909	#define CLK_CLKSEL3_SC3SEL_Pos (6) /!< CLK CLKSEL3: SC3SEL Position /
sahilmgandhi	18:6a4db94011d3	3910	#define CLK_CLKSEL3_SC3SEL_Msk (0x3ul << CLK_CLKSEL3_SC3SEL_Pos) /!< CLK CLKSEL3: SC3SEL Mask /
sahilmgandhi	18:6a4db94011d3	3911
sahilmgandhi	18:6a4db94011d3	3912	#define CLK_CLKSEL3_SC4SEL_Pos (8) /!< CLK CLKSEL3: SC4SEL Position /
sahilmgandhi	18:6a4db94011d3	3913	#define CLK_CLKSEL3_SC4SEL_Msk (0x3ul << CLK_CLKSEL3_SC4SEL_Pos) /!< CLK CLKSEL3: SC4SEL Mask /
sahilmgandhi	18:6a4db94011d3	3914
sahilmgandhi	18:6a4db94011d3	3915	#define CLK_CLKSEL3_SC5SEL_Pos (10) /!< CLK CLKSEL3: SC5SEL Position /
sahilmgandhi	18:6a4db94011d3	3916	#define CLK_CLKSEL3_SC5SEL_Msk (0x3ul << CLK_CLKSEL3_SC5SEL_Pos) /!< CLK CLKSEL3: SC5SEL Mask /
sahilmgandhi	18:6a4db94011d3	3917
sahilmgandhi	18:6a4db94011d3	3918	#define CLK_CLKSEL3_I2S0SEL_Pos (16) /!< CLK CLKSEL3: I2S0SEL Position /
sahilmgandhi	18:6a4db94011d3	3919	#define CLK_CLKSEL3_I2S0SEL_Msk (0x3ul << CLK_CLKSEL3_I2S0SEL_Pos) /!< CLK CLKSEL3: I2S0SEL Mask /
sahilmgandhi	18:6a4db94011d3	3920
sahilmgandhi	18:6a4db94011d3	3921	#define CLK_CLKSEL3_I2S1SEL_Pos (18) /!< CLK CLKSEL3: I2S1SEL Position /
sahilmgandhi	18:6a4db94011d3	3922	#define CLK_CLKSEL3_I2S1SEL_Msk (0x3ul << CLK_CLKSEL3_I2S1SEL_Pos) /!< CLK CLKSEL3: I2S1SEL Mask /
sahilmgandhi	18:6a4db94011d3	3923
sahilmgandhi	18:6a4db94011d3	3924	#define CLK_CLKDIV0_HCLKDIV_Pos (0) /!< CLK CLKDIV0: HCLKDIV Position /
sahilmgandhi	18:6a4db94011d3	3925	#define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) /!< CLK CLKDIV0: HCLKDIV Mask /
sahilmgandhi	18:6a4db94011d3	3926
sahilmgandhi	18:6a4db94011d3	3927	#define CLK_CLKDIV0_USBHDIV_Pos (4) /!< CLK CLKDIV0: USBHDIV Position /
sahilmgandhi	18:6a4db94011d3	3928	#define CLK_CLKDIV0_USBHDIV_Msk (0xful << CLK_CLKDIV0_USBHDIV_Pos) /!< CLK CLKDIV0: USBHDIV Mask /
sahilmgandhi	18:6a4db94011d3	3929
sahilmgandhi	18:6a4db94011d3	3930	#define CLK_CLKDIV0_UARTDIV_Pos (8) /!< CLK CLKDIV0: UARTDIV Position /
sahilmgandhi	18:6a4db94011d3	3931	#define CLK_CLKDIV0_UARTDIV_Msk (0xful << CLK_CLKDIV0_UARTDIV_Pos) /!< CLK CLKDIV0: UARTDIV Mask /
sahilmgandhi	18:6a4db94011d3	3932
sahilmgandhi	18:6a4db94011d3	3933	#define CLK_CLKDIV0_ADCDIV_Pos (16) /!< CLK CLKDIV0: ADCDIV Position /
sahilmgandhi	18:6a4db94011d3	3934	#define CLK_CLKDIV0_ADCDIV_Msk (0xfful << CLK_CLKDIV0_ADCDIV_Pos) /!< CLK CLKDIV0: ADCDIV Mask /
sahilmgandhi	18:6a4db94011d3	3935
sahilmgandhi	18:6a4db94011d3	3936	#define CLK_CLKDIV0_SDHDIV_Pos (24) /!< CLK CLKDIV0: SDHDIV Position /
sahilmgandhi	18:6a4db94011d3	3937	#define CLK_CLKDIV0_SDHDIV_Msk (0xfful << CLK_CLKDIV0_SDHDIV_Pos) /!< CLK CLKDIV0: SDHDIV Mask /
sahilmgandhi	18:6a4db94011d3	3938
sahilmgandhi	18:6a4db94011d3	3939	#define CLK_CLKDIV1_SC0DIV_Pos (0) /!< CLK CLKDIV1: SC0DIV Position /
sahilmgandhi	18:6a4db94011d3	3940	#define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) /!< CLK CLKDIV1: SC0DIV Mask /
sahilmgandhi	18:6a4db94011d3	3941
sahilmgandhi	18:6a4db94011d3	3942	#define CLK_CLKDIV1_SC1DIV_Pos (8) /!< CLK CLKDIV1: SC1DIV Position /
sahilmgandhi	18:6a4db94011d3	3943	#define CLK_CLKDIV1_SC1DIV_Msk (0xfful << CLK_CLKDIV1_SC1DIV_Pos) /!< CLK CLKDIV1: SC1DIV Mask /
sahilmgandhi	18:6a4db94011d3	3944
sahilmgandhi	18:6a4db94011d3	3945	#define CLK_CLKDIV1_SC2DIV_Pos (16) /!< CLK CLKDIV1: SC2DIV Position /
sahilmgandhi	18:6a4db94011d3	3946	#define CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos) /!< CLK CLKDIV1: SC2DIV Mask /
sahilmgandhi	18:6a4db94011d3	3947
sahilmgandhi	18:6a4db94011d3	3948	#define CLK_CLKDIV1_SC3DIV_Pos (24) /!< CLK CLKDIV1: SC3DIV Position /
sahilmgandhi	18:6a4db94011d3	3949	#define CLK_CLKDIV1_SC3DIV_Msk (0xfful << CLK_CLKDIV1_SC3DIV_Pos) /!< CLK CLKDIV1: SC3DIV Mask /
sahilmgandhi	18:6a4db94011d3	3950
sahilmgandhi	18:6a4db94011d3	3951	#define CLK_CLKDIV2_SC4DIV_Pos (0) /!< CLK CLKDIV2: SC4DIV Position /
sahilmgandhi	18:6a4db94011d3	3952	#define CLK_CLKDIV2_SC4DIV_Msk (0xfful << CLK_CLKDIV2_SC4DIV_Pos) /!< CLK CLKDIV2: SC4DIV Mask /
sahilmgandhi	18:6a4db94011d3	3953
sahilmgandhi	18:6a4db94011d3	3954	#define CLK_CLKDIV2_SC5DIV_Pos (8) /!< CLK CLKDIV2: SC5DIV Position /
sahilmgandhi	18:6a4db94011d3	3955	#define CLK_CLKDIV2_SC5DIV_Msk (0xfful << CLK_CLKDIV2_SC5DIV_Pos) /!< CLK CLKDIV2: SC5DIV Mask /
sahilmgandhi	18:6a4db94011d3	3956
sahilmgandhi	18:6a4db94011d3	3957	#define CLK_CLKDIV3_CAPDIV_Pos (0) /!< CLK CLKDIV3: CAPDIV Position /
sahilmgandhi	18:6a4db94011d3	3958	#define CLK_CLKDIV3_CAPDIV_Msk (0xfful << CLK_CLKDIV3_CAPDIV_Pos) /!< CLK CLKDIV3: CAPDIV Mask /
sahilmgandhi	18:6a4db94011d3	3959
sahilmgandhi	18:6a4db94011d3	3960	#define CLK_CLKDIV3_VSENSEDIV_Pos (8) /!< CLK CLKDIV3: VSENSEDIV Position /
sahilmgandhi	18:6a4db94011d3	3961	#define CLK_CLKDIV3_VSENSEDIV_Msk (0xfful << CLK_CLKDIV3_VSENSEDIV_Pos) /!< CLK CLKDIV3: VSENSEDIV Mask /
sahilmgandhi	18:6a4db94011d3	3962
sahilmgandhi	18:6a4db94011d3	3963	#define CLK_CLKDIV3_EMACDIV_Pos (16) /!< CLK CLKDIV3: EMACDIV Position /
sahilmgandhi	18:6a4db94011d3	3964	#define CLK_CLKDIV3_EMACDIV_Msk (0xfful << CLK_CLKDIV3_EMACDIV_Pos) /!< CLK CLKDIV3: EMACDIV Mask /
sahilmgandhi	18:6a4db94011d3	3965
sahilmgandhi	18:6a4db94011d3	3966	#define CLK_PLLCTL_FBDIV_Pos (0) /!< CLK PLLCTL: FBDIV Position /
sahilmgandhi	18:6a4db94011d3	3967	#define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /!< CLK PLLCTL: FBDIV Mask /
sahilmgandhi	18:6a4db94011d3	3968
sahilmgandhi	18:6a4db94011d3	3969	#define CLK_PLLCTL_INDIV_Pos (9) /!< CLK PLLCTL: INDIV Position /
sahilmgandhi	18:6a4db94011d3	3970	#define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) /!< CLK PLLCTL: INDIV Mask /
sahilmgandhi	18:6a4db94011d3	3971
sahilmgandhi	18:6a4db94011d3	3972	#define CLK_PLLCTL_OUTDV_Pos (14) /!< CLK PLLCTL: OUTDV Position /
sahilmgandhi	18:6a4db94011d3	3973	#define CLK_PLLCTL_OUTDV_Msk (0x3ul << CLK_PLLCTL_OUTDV_Pos) /!< CLK PLLCTL: OUTDV Mask /
sahilmgandhi	18:6a4db94011d3	3974
sahilmgandhi	18:6a4db94011d3	3975	#define CLK_PLLCTL_PD_Pos (16) /!< CLK PLLCTL: PD Position /
sahilmgandhi	18:6a4db94011d3	3976	#define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /!< CLK PLLCTL: PD Mask /
sahilmgandhi	18:6a4db94011d3	3977
sahilmgandhi	18:6a4db94011d3	3978	#define CLK_PLLCTL_BP_Pos (17) /!< CLK PLLCTL: BP Position /
sahilmgandhi	18:6a4db94011d3	3979	#define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /!< CLK PLLCTL: BP Mask /
sahilmgandhi	18:6a4db94011d3	3980
sahilmgandhi	18:6a4db94011d3	3981	#define CLK_PLLCTL_OE_Pos (18) /!< CLK PLLCTL: OE Position /
sahilmgandhi	18:6a4db94011d3	3982	#define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) /!< CLK PLLCTL: OE Mask /
sahilmgandhi	18:6a4db94011d3	3983
sahilmgandhi	18:6a4db94011d3	3984	#define CLK_PLLCTL_PLLSRC_Pos (19) /!< CLK PLLCTL: PLLSRC Position /
sahilmgandhi	18:6a4db94011d3	3985	#define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /!< CLK PLLCTL: PLLSRC Mask /
sahilmgandhi	18:6a4db94011d3	3986
sahilmgandhi	18:6a4db94011d3	3987	#define CLK_PLLCTL_PLLREMAP_Pos (20) /!< CLK PLLCTL: PLLREMAP Position /
sahilmgandhi	18:6a4db94011d3	3988	#define CLK_PLLCTL_PLLREMAP_Msk (0x1ul << CLK_PLLCTL_PLLREMAP_Pos) /!< CLK PLLCTL: PLLREMAP Mask /
sahilmgandhi	18:6a4db94011d3	3989
sahilmgandhi	18:6a4db94011d3	3990	#define CLK_PLL2CTL_PLL2DIV_Pos (0) /!< CLK PLL2CTL: PLL2DIV Position /
sahilmgandhi	18:6a4db94011d3	3991	#define CLK_PLL2CTL_PLL2DIV_Msk (0xfful << CLK_PLL2CTL_PLL2DIV_Pos) /!< CLK PLL2CTL: PLL2DIV Mask /
sahilmgandhi	18:6a4db94011d3	3992
sahilmgandhi	18:6a4db94011d3	3993	#define CLK_PLL2CTL_PLL2CKEN_Pos (8) /!< CLK PLL2CTL: PLL2CKEN Position /
sahilmgandhi	18:6a4db94011d3	3994	#define CLK_PLL2CTL_PLL2CKEN_Msk (0x1ul << CLK_PLL2CTL_PLL2CKEN_Pos) /!< CLK PLL2CTL: PLL2CKEN Mask /
sahilmgandhi	18:6a4db94011d3	3995
sahilmgandhi	18:6a4db94011d3	3996	#define CLK_STATUS_HXTSTB_Pos (0) /!< CLK STATUS: HXTSTB Position /
sahilmgandhi	18:6a4db94011d3	3997	#define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /!< CLK STATUS: HXTSTB Mask /
sahilmgandhi	18:6a4db94011d3	3998
sahilmgandhi	18:6a4db94011d3	3999	#define CLK_STATUS_LXTSTB_Pos (1) /!< CLK STATUS: LXTSTB Position /
sahilmgandhi	18:6a4db94011d3	4000	#define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /!< CLK STATUS: LXTSTB Mask /
sahilmgandhi	18:6a4db94011d3	4001
sahilmgandhi	18:6a4db94011d3	4002	#define CLK_STATUS_PLLSTB_Pos (2) /!< CLK STATUS: PLLSTB Position /
sahilmgandhi	18:6a4db94011d3	4003	#define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /!< CLK STATUS: PLLSTB Mask /
sahilmgandhi	18:6a4db94011d3	4004
sahilmgandhi	18:6a4db94011d3	4005	#define CLK_STATUS_LIRCSTB_Pos (3) /!< CLK STATUS: LIRCSTB Position /
sahilmgandhi	18:6a4db94011d3	4006	#define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /!< CLK STATUS: LIRCSTB Mask /
sahilmgandhi	18:6a4db94011d3	4007
sahilmgandhi	18:6a4db94011d3	4008	#define CLK_STATUS_HIRCSTB_Pos (4) /!< CLK STATUS: HIRCSTB Position /
sahilmgandhi	18:6a4db94011d3	4009	#define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /!< CLK STATUS: HIRCSTB Mask /
sahilmgandhi	18:6a4db94011d3	4010
sahilmgandhi	18:6a4db94011d3	4011	#define CLK_STATUS_PLL2STB_Pos (5) /!< CLK STATUS: PLL2STB Position /
sahilmgandhi	18:6a4db94011d3	4012	#define CLK_STATUS_PLL2STB_Msk (0x1ul << CLK_STATUS_PLL2STB_Pos) /!< CLK STATUS: PLL2STB Mask /
sahilmgandhi	18:6a4db94011d3	4013
sahilmgandhi	18:6a4db94011d3	4014	#define CLK_STATUS_CLKSFAIL_Pos (7) /!< CLK STATUS: CLKSFAIL Position /
sahilmgandhi	18:6a4db94011d3	4015	#define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /!< CLK STATUS: CLKSFAIL Mask /
sahilmgandhi	18:6a4db94011d3	4016
sahilmgandhi	18:6a4db94011d3	4017	#define CLK_CLKOCTL_FSEL_Pos (0) /!< CLK CLKOCTL: FSEL Position /
sahilmgandhi	18:6a4db94011d3	4018	#define CLK_CLKOCTL_FSEL_Msk (0xful << CLK_CLKOCTL_FSEL_Pos) /!< CLK CLKOCTL: FSEL Mask /
sahilmgandhi	18:6a4db94011d3	4019
sahilmgandhi	18:6a4db94011d3	4020	#define CLK_CLKOCTL_CLKOEN_Pos (4) /!< CLK CLKOCTL: CLKOEN Position /
sahilmgandhi	18:6a4db94011d3	4021	#define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /!< CLK CLKOCTL: CLKOEN Mask /
sahilmgandhi	18:6a4db94011d3	4022
sahilmgandhi	18:6a4db94011d3	4023	#define CLK_CLKOCTL_DIV1EN_Pos (5) /!< CLK CLKOCTL: DIV1EN Position /
sahilmgandhi	18:6a4db94011d3	4024	#define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /!< CLK CLKOCTL: DIV1EN Mask /
sahilmgandhi	18:6a4db94011d3	4025
sahilmgandhi	18:6a4db94011d3	4026	#define CLK_CLKDCTL_SYSFDEN_Pos (0) /!< CLK CLKDCTL: SYSFDEN Position /
sahilmgandhi	18:6a4db94011d3	4027	#define CLK_CLKDCTL_SYSFDEN_Msk (0x1ul << CLK_CLKDCTL_SYSFDEN_Pos) /!< CLK CLKDCTL: SYSFDEN Mask /
sahilmgandhi	18:6a4db94011d3	4028
sahilmgandhi	18:6a4db94011d3	4029	#define CLK_CLKDCTL_SYSFIEN_Pos (1) /!< CLK CLKDCTL: SYSFIEN Position /
sahilmgandhi	18:6a4db94011d3	4030	#define CLK_CLKDCTL_SYSFIEN_Msk (0x1ul << CLK_CLKDCTL_SYSFIEN_Pos) /!< CLK CLKDCTL: SYSFIEN Mask /
sahilmgandhi	18:6a4db94011d3	4031
sahilmgandhi	18:6a4db94011d3	4032	#define CLK_CLKDCTL_SYSFIF_Pos (2) /!< CLK CLKDCTL: SYSFIF Position /
sahilmgandhi	18:6a4db94011d3	4033	#define CLK_CLKDCTL_SYSFIF_Msk (0x1ul << CLK_CLKDCTL_SYSFIF_Pos) /!< CLK CLKDCTL: SYSFIF Mask /
sahilmgandhi	18:6a4db94011d3	4034
sahilmgandhi	18:6a4db94011d3	4035	#define CLK_CLKDCTL_IRCDEN_Pos (8) /!< CLK CLKDCTL: IRCDEN Position /
sahilmgandhi	18:6a4db94011d3	4036	#define CLK_CLKDCTL_IRCDEN_Msk (0x1ul << CLK_CLKDCTL_IRCDEN_Pos) /!< CLK CLKDCTL: IRCDEN Mask /
sahilmgandhi	18:6a4db94011d3	4037
sahilmgandhi	18:6a4db94011d3	4038	#define CLK_CLKDCTL_IRCFIEN_Pos (9) /!< CLK CLKDCTL: IRCFIEN Position /
sahilmgandhi	18:6a4db94011d3	4039	#define CLK_CLKDCTL_IRCFIEN_Msk (0x1ul << CLK_CLKDCTL_IRCFIEN_Pos) /!< CLK CLKDCTL: IRCFIEN Mask /
sahilmgandhi	18:6a4db94011d3	4040
sahilmgandhi	18:6a4db94011d3	4041	#define CLK_CLKDCTL_IRCFIF_Pos (10) /!< CLK CLKDCTL: IRCFIF Position /
sahilmgandhi	18:6a4db94011d3	4042	#define CLK_CLKDCTL_IRCFIF_Msk (0x1ul << CLK_CLKDCTL_IRCFIF_Pos) /!< CLK CLKDCTL: IRCFIF Mask /
sahilmgandhi	18:6a4db94011d3	4043
sahilmgandhi	18:6a4db94011d3	4044	/*@}/ /* CLK_CONST */
sahilmgandhi	18:6a4db94011d3	4045	/*@}/ /* end of CLK register group */
sahilmgandhi	18:6a4db94011d3	4046
sahilmgandhi	18:6a4db94011d3	4047
sahilmgandhi	18:6a4db94011d3	4048	/---------------------- Cyclic Redundancy Check Controller -------------------------/
sahilmgandhi	18:6a4db94011d3	4049	/**
sahilmgandhi	18:6a4db94011d3	4050	@addtogroup CRC Cyclic Redundancy Check Controller(CRC)
sahilmgandhi	18:6a4db94011d3	4051	Memory Mapped Structure for CRC Controller
sahilmgandhi	18:6a4db94011d3	4052	@{ */
sahilmgandhi	18:6a4db94011d3	4053
sahilmgandhi	18:6a4db94011d3	4054	typedef struct {
sahilmgandhi	18:6a4db94011d3	4055
sahilmgandhi	18:6a4db94011d3	4056
sahilmgandhi	18:6a4db94011d3	4057	/**
sahilmgandhi	18:6a4db94011d3	4058	* CTL
sahilmgandhi	18:6a4db94011d3	4059	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4060	* Offset: 0x00 CRC Control Register
sahilmgandhi	18:6a4db94011d3	4061	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4062	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4063	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4064	* \|[0] \|CRCEN \|CRC Channel Enable Control
sahilmgandhi	18:6a4db94011d3	4065	* \| \| \|0 = CRC function Disabled.
sahilmgandhi	18:6a4db94011d3	4066	* \| \| \|1 = CRC function Enabled.
sahilmgandhi	18:6a4db94011d3	4067	* \|[1] \|CRCRST \|CRC Engine Reset
sahilmgandhi	18:6a4db94011d3	4068	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	4069	* \| \| \|1 = Reset the internal CRC state machine and internal buffer.
sahilmgandhi	18:6a4db94011d3	4070	* \| \| \|The contents of control register will not be cleared.
sahilmgandhi	18:6a4db94011d3	4071	* \| \| \|This bit will automatically be cleared after few clock cycles.
sahilmgandhi	18:6a4db94011d3	4072	* \| \| \|Note: Setting this bit will reload the initial seed value.
sahilmgandhi	18:6a4db94011d3	4073	* \|[24] \|DATREV \|Write Data Order Reverse
sahilmgandhi	18:6a4db94011d3	4074	* \| \| \|0 = No bit order reversed for CRC write data in.
sahilmgandhi	18:6a4db94011d3	4075	* \| \| \|1 = Bit order reversed for CRC write data in (per byte).
sahilmgandhi	18:6a4db94011d3	4076	* \| \| \|Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB
sahilmgandhi	18:6a4db94011d3	4077	* \|[25] \|CHKSREV \|Checksum Reverse
sahilmgandhi	18:6a4db94011d3	4078	* \| \| \|0 = No bit order reverse for CRC checksum.
sahilmgandhi	18:6a4db94011d3	4079	* \| \| \|1 = Bit order reverse for CRC checksum.
sahilmgandhi	18:6a4db94011d3	4080	* \| \| \|Note: If the checksum data is 0XDD7B0F2E, the bit order reversed for CRC checksum is 0x74F0DEBB.
sahilmgandhi	18:6a4db94011d3	4081	* \|[26] \|DATFMT \|Write Data Complement
sahilmgandhi	18:6a4db94011d3	4082	* \| \| \|0 = No bit order reversed for CRC write data in.
sahilmgandhi	18:6a4db94011d3	4083	* \| \| \|1 = 1's complement for CRC write data in.
sahilmgandhi	18:6a4db94011d3	4084	* \|[27] \|CHKSFMT \|Checksum Complement
sahilmgandhi	18:6a4db94011d3	4085	* \| \| \|0 = No bit order reverse for CRC checksum.
sahilmgandhi	18:6a4db94011d3	4086	* \| \| \|1 = 1's complement for CRC checksum.
sahilmgandhi	18:6a4db94011d3	4087	* \|[28:29] \|DATLEN \|CPU Write Data Length
sahilmgandhi	18:6a4db94011d3	4088	* \| \| \|This field indicates the write data length.
sahilmgandhi	18:6a4db94011d3	4089	* \| \| \|00 = Data length is 8-bit mode.
sahilmgandhi	18:6a4db94011d3	4090	* \| \| \|01 = Data length is 16-bit mode.
sahilmgandhi	18:6a4db94011d3	4091	* \| \| \|1x = Data length is 32-bit mode.
sahilmgandhi	18:6a4db94011d3	4092	* \| \| \|Note: When the data length is 8-bit mode, the valid data is DATA [7:0]; if the data length is 16-bit mode, the valid data is DATA [15:0].
sahilmgandhi	18:6a4db94011d3	4093	* \|[30:31] \|CRCMODE \|CRC Polynomial Mode Selection
sahilmgandhi	18:6a4db94011d3	4094	* \| \| \|00 = CRC-CCITT Polynomial mode.
sahilmgandhi	18:6a4db94011d3	4095	* \| \| \|01 = CRC-8 Polynomial mode.
sahilmgandhi	18:6a4db94011d3	4096	* \| \| \|10 = CRC-16 Polynomial mode.
sahilmgandhi	18:6a4db94011d3	4097	* \| \| \|11 = CRC-32 Polynomial mode.
sahilmgandhi	18:6a4db94011d3	4098	*/
sahilmgandhi	18:6a4db94011d3	4099	__IO uint32_t CTL;
sahilmgandhi	18:6a4db94011d3	4100
sahilmgandhi	18:6a4db94011d3	4101	/**
sahilmgandhi	18:6a4db94011d3	4102	* DAT
sahilmgandhi	18:6a4db94011d3	4103	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4104	* Offset: 0x04 CRC Write Data Register
sahilmgandhi	18:6a4db94011d3	4105	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4106	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4107	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4108	* \|[0:31] \|DATA \|CRC Write Data Bits
sahilmgandhi	18:6a4db94011d3	4109	* \| \| \|Software can write data to this field to perform CRC operation, or uses PDMA function to get the data from memory
sahilmgandhi	18:6a4db94011d3	4110	* \| \| \|Note1: The CRC_CTL [DATFMT] and CRC_CTL [DATREV] bit setting will affect this field; for example, if DATREV = 1, if the write data in DATA register is 0xAABBCCDD, the read data from DATA register will be 0x55DD33BB.
sahilmgandhi	18:6a4db94011d3	4111	*/
sahilmgandhi	18:6a4db94011d3	4112	__IO uint32_t DAT;
sahilmgandhi	18:6a4db94011d3	4113
sahilmgandhi	18:6a4db94011d3	4114	/**
sahilmgandhi	18:6a4db94011d3	4115	* SEED
sahilmgandhi	18:6a4db94011d3	4116	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4117	* Offset: 0x08 CRC Seed Register
sahilmgandhi	18:6a4db94011d3	4118	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4119	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4120	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4121	* \|[0:31] \|SEED \|CRC Seed Bits
sahilmgandhi	18:6a4db94011d3	4122	* \| \| \|This field indicates the CRC seed value.
sahilmgandhi	18:6a4db94011d3	4123	*/
sahilmgandhi	18:6a4db94011d3	4124	__IO uint32_t SEED;
sahilmgandhi	18:6a4db94011d3	4125
sahilmgandhi	18:6a4db94011d3	4126	/**
sahilmgandhi	18:6a4db94011d3	4127	* CHECKSUM
sahilmgandhi	18:6a4db94011d3	4128	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4129	* Offset: 0x0C CRC Checksum Register
sahilmgandhi	18:6a4db94011d3	4130	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4131	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4132	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4133	* \|[0:31] \|CHECKSUM \|CRC Checksum Bits
sahilmgandhi	18:6a4db94011d3	4134	* \| \| \|This field indicates the CRC checksum.
sahilmgandhi	18:6a4db94011d3	4135	*/
sahilmgandhi	18:6a4db94011d3	4136	__I uint32_t CHECKSUM;
sahilmgandhi	18:6a4db94011d3	4137
sahilmgandhi	18:6a4db94011d3	4138	} CRC_T;
sahilmgandhi	18:6a4db94011d3	4139
sahilmgandhi	18:6a4db94011d3	4140	/**
sahilmgandhi	18:6a4db94011d3	4141	@addtogroup CRC_CONST CRC Bit Field Definition
sahilmgandhi	18:6a4db94011d3	4142	Constant Definitions for CRC Controller
sahilmgandhi	18:6a4db94011d3	4143	@{ */
sahilmgandhi	18:6a4db94011d3	4144
sahilmgandhi	18:6a4db94011d3	4145	#define CRC_CTL_CRCEN_Pos (0) /!< CRC CTL: CRCEN Position /
sahilmgandhi	18:6a4db94011d3	4146	#define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /!< CRC CTL: CRCEN Mask /
sahilmgandhi	18:6a4db94011d3	4147
sahilmgandhi	18:6a4db94011d3	4148	#define CRC_CTL_CRCRST_Pos (1) /!< CRC CTL: CRCRST Position /
sahilmgandhi	18:6a4db94011d3	4149	#define CRC_CTL_CRCRST_Msk (0x1ul << CRC_CTL_CRCRST_Pos) /!< CRC CTL: CRCRST Mask /
sahilmgandhi	18:6a4db94011d3	4150
sahilmgandhi	18:6a4db94011d3	4151	#define CRC_CTL_DATREV_Pos (24) /!< CRC CTL: DATREV Position /
sahilmgandhi	18:6a4db94011d3	4152	#define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /!< CRC CTL: DATREV Mask /
sahilmgandhi	18:6a4db94011d3	4153
sahilmgandhi	18:6a4db94011d3	4154	#define CRC_CTL_CHKSREV_Pos (25) /!< CRC CTL: CHKSREV Position /
sahilmgandhi	18:6a4db94011d3	4155	#define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /!< CRC CTL: CHKSREV Mask /
sahilmgandhi	18:6a4db94011d3	4156
sahilmgandhi	18:6a4db94011d3	4157	#define CRC_CTL_DATFMT_Pos (26) /!< CRC CTL: DATFMT Position /
sahilmgandhi	18:6a4db94011d3	4158	#define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /!< CRC CTL: DATFMT Mask /
sahilmgandhi	18:6a4db94011d3	4159
sahilmgandhi	18:6a4db94011d3	4160	#define CRC_CTL_CHKSFMT_Pos (27) /!< CRC CTL: CHKSFMT Position /
sahilmgandhi	18:6a4db94011d3	4161	#define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /!< CRC CTL: CHKSFMT Mask /
sahilmgandhi	18:6a4db94011d3	4162
sahilmgandhi	18:6a4db94011d3	4163	#define CRC_CTL_DATLEN_Pos (28) /!< CRC CTL: DATLEN Position /
sahilmgandhi	18:6a4db94011d3	4164	#define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /!< CRC CTL: DATLEN Mask /
sahilmgandhi	18:6a4db94011d3	4165
sahilmgandhi	18:6a4db94011d3	4166	#define CRC_CTL_CRCMODE_Pos (30) /!< CRC CTL: CRCMODE Position /
sahilmgandhi	18:6a4db94011d3	4167	#define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /!< CRC CTL: CRCMODE Mask /
sahilmgandhi	18:6a4db94011d3	4168
sahilmgandhi	18:6a4db94011d3	4169	#define CRC_DAT_DATA_Pos (0) /!< CRC DAT: DATA Position /
sahilmgandhi	18:6a4db94011d3	4170	#define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /!< CRC DAT: DATA Mask /
sahilmgandhi	18:6a4db94011d3	4171
sahilmgandhi	18:6a4db94011d3	4172	#define CRC_SEED_SEED_Pos (0) /!< CRC SEED: SEED Position /
sahilmgandhi	18:6a4db94011d3	4173	#define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /!< CRC SEED: SEED Mask /
sahilmgandhi	18:6a4db94011d3	4174
sahilmgandhi	18:6a4db94011d3	4175	#define CRC_CHECKSUM_CHECKSUM_Pos (0) /!< CRC CHECKSUM: CHECKSUM Position /
sahilmgandhi	18:6a4db94011d3	4176	#define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /!< CRC CHECKSUM: CHECKSUM Mask /
sahilmgandhi	18:6a4db94011d3	4177
sahilmgandhi	18:6a4db94011d3	4178	/*@}/ /* CRC_CONST */
sahilmgandhi	18:6a4db94011d3	4179	/*@}/ /* end of CRC register group */
sahilmgandhi	18:6a4db94011d3	4180
sahilmgandhi	18:6a4db94011d3	4181
sahilmgandhi	18:6a4db94011d3	4182	/---------------------- Cryptographic Accelerator -------------------------/
sahilmgandhi	18:6a4db94011d3	4183	/**
sahilmgandhi	18:6a4db94011d3	4184	@addtogroup CRPT Cryptographic Accelerator(CRPT)
sahilmgandhi	18:6a4db94011d3	4185	Memory Mapped Structure for CRPT Controller
sahilmgandhi	18:6a4db94011d3	4186	@{ */
sahilmgandhi	18:6a4db94011d3	4187
sahilmgandhi	18:6a4db94011d3	4188	typedef struct {
sahilmgandhi	18:6a4db94011d3	4189	/**
sahilmgandhi	18:6a4db94011d3	4190	* INTEN
sahilmgandhi	18:6a4db94011d3	4191	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4192	* Offset: 0x00 Crypto Interrupt Enable Control Register
sahilmgandhi	18:6a4db94011d3	4193	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4194	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4195	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4196	* \|[0] \|AESIEN \|AES Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	4197	* \| \| \|0 = AES interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	4198	* \| \| \|1 = AES interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	4199	* \| \| \|In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine.
sahilmgandhi	18:6a4db94011d3	4200	* \| \| \|In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation.
sahilmgandhi	18:6a4db94011d3	4201	* \|[1] \|AESERRIEN \|AES Error Flag Enable Control
sahilmgandhi	18:6a4db94011d3	4202	* \| \| \|0 = AES error interrupt flag Disabled.
sahilmgandhi	18:6a4db94011d3	4203	* \| \| \|1 = AES error interrupt flag Enabled.
sahilmgandhi	18:6a4db94011d3	4204	* \|[8] \|TDESIEN \|TDES/DES Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	4205	* \| \| \|0 = TDES/DES interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	4206	* \| \| \|1 = TDES/DES interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	4207	* \| \| \|In DMA mode, an interrupt will be triggered when amount of data set in TDES_DMA_CNT is fed into the TDES engine.
sahilmgandhi	18:6a4db94011d3	4208	* \| \| \|In Non-DMA mode, an interrupt will be triggered when the TDES engine finishes the operation.
sahilmgandhi	18:6a4db94011d3	4209	* \|[9] \|TDESERRIEN\|TDES/DES Error Flag Enable Control
sahilmgandhi	18:6a4db94011d3	4210	* \| \| \|0 = TDES/DES error interrupt flag Disabled.
sahilmgandhi	18:6a4db94011d3	4211	* \| \| \|1 = TDES/DES error interrupt flag Enabled.
sahilmgandhi	18:6a4db94011d3	4212	* \|[16] \|PRNGIEN \|PRNG Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	4213	* \| \| \|0 = PRNG interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	4214	* \| \| \|1 = PRNG interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	4215	* \|[24] \|SHAIEN \|SHA Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	4216	* \| \| \|0 = SHA interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	4217	* \| \| \|1 = SHA interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	4218	* \| \| \|In DMA mode, an interrupt will be triggered when amount of data set in SHA _DMA_CNT is fed into the SHA engine.
sahilmgandhi	18:6a4db94011d3	4219	* \| \| \|In Non-DMA mode, an interrupt will be triggered when the SHA engine finishes the operation.
sahilmgandhi	18:6a4db94011d3	4220	* \|[25] \|SHAERRIEN \|SHA Error Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	4221	* \| \| \|0 = SHA error interrupt flag Disabled.
sahilmgandhi	18:6a4db94011d3	4222	* \| \| \|1 = SHA error interrupt flag Enabled.
sahilmgandhi	18:6a4db94011d3	4223	*/
sahilmgandhi	18:6a4db94011d3	4224	__IO uint32_t INTEN;
sahilmgandhi	18:6a4db94011d3	4225
sahilmgandhi	18:6a4db94011d3	4226	/**
sahilmgandhi	18:6a4db94011d3	4227	* INTSTS
sahilmgandhi	18:6a4db94011d3	4228	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4229	* Offset: 0x04 Crypto Interrupt Flag
sahilmgandhi	18:6a4db94011d3	4230	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4231	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4232	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4233	* \|[0] \|AESIF \|AES Finish Interrupt Flag
sahilmgandhi	18:6a4db94011d3	4234	* \| \| \|This bit is cleared by writing 1, and it has no effect by writing 0.
sahilmgandhi	18:6a4db94011d3	4235	* \| \| \|0 = No AES interrupt.
sahilmgandhi	18:6a4db94011d3	4236	* \| \| \|1 = AES encryption/decryption done interrupt.
sahilmgandhi	18:6a4db94011d3	4237	* \|[1] \|AESERRIF \|AES Error Flag
sahilmgandhi	18:6a4db94011d3	4238	* \| \| \|This bit is cleared by writing 1, and it has no effect by writing 0.
sahilmgandhi	18:6a4db94011d3	4239	* \| \| \|0 = No AES error.
sahilmgandhi	18:6a4db94011d3	4240	* \| \| \|1 = AES encryption/decryption done interrupt.
sahilmgandhi	18:6a4db94011d3	4241	* \|[8] \|TDESIF \|TDES/DES Finish Interrupt Flag
sahilmgandhi	18:6a4db94011d3	4242	* \| \| \|This bit is cleared by writing 1, and it has no effect by writing 0.
sahilmgandhi	18:6a4db94011d3	4243	* \| \| \|0 = No TDES/DES interrupt.
sahilmgandhi	18:6a4db94011d3	4244	* \| \| \|1 = TDES/DES encryption/decryption done interrupt.
sahilmgandhi	18:6a4db94011d3	4245	* \|[9] \|TDESERRIF \|TDES/DES Error Flag
sahilmgandhi	18:6a4db94011d3	4246	* \| \| \|This bit includes the operating and setting error.
sahilmgandhi	18:6a4db94011d3	4247	* \| \| \|The detailed flag is shown in the TDES _FLAG register.
sahilmgandhi	18:6a4db94011d3	4248	* \| \| \|This includes operating and setting error.
sahilmgandhi	18:6a4db94011d3	4249	* \| \| \|This bit is cleared by writing 1, and it has no effect by writing 0.
sahilmgandhi	18:6a4db94011d3	4250	* \| \| \|0 = No TDES/DES error.
sahilmgandhi	18:6a4db94011d3	4251	* \| \| \|1 = TDES/DES encryption/decryption error interrupt.
sahilmgandhi	18:6a4db94011d3	4252	* \|[16] \|PRNGIF \|PRNG Finish Interrupt Flag
sahilmgandhi	18:6a4db94011d3	4253	* \| \| \|This bit is cleared by writing 1, and it has no effect by writing 0.
sahilmgandhi	18:6a4db94011d3	4254	* \| \| \|0 = No PRNG interrupt.
sahilmgandhi	18:6a4db94011d3	4255	* \| \| \|1 = PRNG key generation done interrupt.
sahilmgandhi	18:6a4db94011d3	4256	* \|[24] \|SHAIF \|SHA Finish Interrupt Flag
sahilmgandhi	18:6a4db94011d3	4257	* \| \| \|This bit is cleared by writing 1, and it has no effect by writing 0.
sahilmgandhi	18:6a4db94011d3	4258	* \| \| \|0 = No SHA interrupt.
sahilmgandhi	18:6a4db94011d3	4259	* \| \| \|1 = SHA operation done interrupt.
sahilmgandhi	18:6a4db94011d3	4260	* \|[25] \|SHAERRIF \|SHA Error Flag
sahilmgandhi	18:6a4db94011d3	4261	* \| \| \|This register includes operating and setting error. The detail flag is shown in SHA _FLAG register.
sahilmgandhi	18:6a4db94011d3	4262	* \| \| \|This bit is cleared by writing 1, and it has no effect by writing 0.
sahilmgandhi	18:6a4db94011d3	4263	* \| \| \|0 = No SHA error.
sahilmgandhi	18:6a4db94011d3	4264	* \| \| \|1 = SHA error interrupt.
sahilmgandhi	18:6a4db94011d3	4265	*/
sahilmgandhi	18:6a4db94011d3	4266	__IO uint32_t INTSTS;
sahilmgandhi	18:6a4db94011d3	4267
sahilmgandhi	18:6a4db94011d3	4268	/**
sahilmgandhi	18:6a4db94011d3	4269	* PRNG_CTL
sahilmgandhi	18:6a4db94011d3	4270	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4271	* Offset: 0x08 PRNG Control Register
sahilmgandhi	18:6a4db94011d3	4272	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4273	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4274	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4275	* \|[0] \|START \|Start PRNG Engine
sahilmgandhi	18:6a4db94011d3	4276	* \| \| \|0 = Stop PRNG engine.
sahilmgandhi	18:6a4db94011d3	4277	* \| \| \|1 = Generate new key and store the new key to register CRPT_PRNG_KEYx , which will be cleared when the new key is generated.
sahilmgandhi	18:6a4db94011d3	4278	* \|[1] \|SEEDRLD \|Reload New Seed For PRNG Engine
sahilmgandhi	18:6a4db94011d3	4279	* \| \| \|0 = Generating key based on the current seed.
sahilmgandhi	18:6a4db94011d3	4280	* \| \| \|1 = Reload new seed.
sahilmgandhi	18:6a4db94011d3	4281	* \|[2:3] \|KEYSZ \|PRNG Generate Key Size
sahilmgandhi	18:6a4db94011d3	4282	* \| \| \|00 = 64 bits.
sahilmgandhi	18:6a4db94011d3	4283	* \| \| \|01 = 128 bits.
sahilmgandhi	18:6a4db94011d3	4284	* \| \| \|10 = 192 bits.
sahilmgandhi	18:6a4db94011d3	4285	* \| \| \|11 = 256 bits.
sahilmgandhi	18:6a4db94011d3	4286	* \|[8] \|BUSY \|PRNG Busy (Read Only)
sahilmgandhi	18:6a4db94011d3	4287	* \| \| \|0 = PRNG engine is idle.
sahilmgandhi	18:6a4db94011d3	4288	* \| \| \|1 = Indicate that the PRNG engine is generating CRPT_PRNG_KEYx.
sahilmgandhi	18:6a4db94011d3	4289	*/
sahilmgandhi	18:6a4db94011d3	4290	__IO uint32_t PRNG_CTL;
sahilmgandhi	18:6a4db94011d3	4291
sahilmgandhi	18:6a4db94011d3	4292	/**
sahilmgandhi	18:6a4db94011d3	4293	* PRNG_SEED
sahilmgandhi	18:6a4db94011d3	4294	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4295	* Offset: 0x0C Seed for PRNG
sahilmgandhi	18:6a4db94011d3	4296	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4297	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4298	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4299	* \|[0:31] \|CRPT_PRNG_SEED\|Seed For PRNG (Write Only)
sahilmgandhi	18:6a4db94011d3	4300	* \| \| \|The bits store the seed for PRNG engine.
sahilmgandhi	18:6a4db94011d3	4301	*/
sahilmgandhi	18:6a4db94011d3	4302	__O uint32_t PRNG_SEED;
sahilmgandhi	18:6a4db94011d3	4303
sahilmgandhi	18:6a4db94011d3	4304	/**
sahilmgandhi	18:6a4db94011d3	4305	* PRNG_KEY0
sahilmgandhi	18:6a4db94011d3	4306	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4307	* Offset: 0x10 PRNG Generated Key0
sahilmgandhi	18:6a4db94011d3	4308	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4309	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4310	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4311	* \|[0:31] \|KEYx \|Store PRNG Generated Key (Read Only)
sahilmgandhi	18:6a4db94011d3	4312	* \| \| \|The bits store the key that is generated by PRNG.
sahilmgandhi	18:6a4db94011d3	4313	*/
sahilmgandhi	18:6a4db94011d3	4314	__I uint32_t PRNG_KEY0;
sahilmgandhi	18:6a4db94011d3	4315
sahilmgandhi	18:6a4db94011d3	4316	/**
sahilmgandhi	18:6a4db94011d3	4317	* PRNG_KEY1
sahilmgandhi	18:6a4db94011d3	4318	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4319	* Offset: 0x14 PRNG Generated Key1
sahilmgandhi	18:6a4db94011d3	4320	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4321	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4322	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4323	* \|[0:31] \|KEYx \|Store PRNG Generated Key (Read Only)
sahilmgandhi	18:6a4db94011d3	4324	* \| \| \|The bits store the key that is generated by PRNG.
sahilmgandhi	18:6a4db94011d3	4325	*/
sahilmgandhi	18:6a4db94011d3	4326	__I uint32_t PRNG_KEY1;
sahilmgandhi	18:6a4db94011d3	4327
sahilmgandhi	18:6a4db94011d3	4328	/**
sahilmgandhi	18:6a4db94011d3	4329	* PRNG_KEY2
sahilmgandhi	18:6a4db94011d3	4330	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4331	* Offset: 0x18 PRNG Generated Key2
sahilmgandhi	18:6a4db94011d3	4332	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4333	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4334	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4335	* \|[0:31] \|KEYx \|Store PRNG Generated Key (Read Only)
sahilmgandhi	18:6a4db94011d3	4336	* \| \| \|The bits store the key that is generated by PRNG.
sahilmgandhi	18:6a4db94011d3	4337	*/
sahilmgandhi	18:6a4db94011d3	4338	__I uint32_t PRNG_KEY2;
sahilmgandhi	18:6a4db94011d3	4339
sahilmgandhi	18:6a4db94011d3	4340	/**
sahilmgandhi	18:6a4db94011d3	4341	* PRNG_KEY3
sahilmgandhi	18:6a4db94011d3	4342	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4343	* Offset: 0x1C PRNG Generated Key3
sahilmgandhi	18:6a4db94011d3	4344	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4345	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4346	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4347	* \|[0:31] \|KEYx \|Store PRNG Generated Key (Read Only)
sahilmgandhi	18:6a4db94011d3	4348	* \| \| \|The bits store the key that is generated by PRNG.
sahilmgandhi	18:6a4db94011d3	4349	*/
sahilmgandhi	18:6a4db94011d3	4350	__I uint32_t PRNG_KEY3;
sahilmgandhi	18:6a4db94011d3	4351
sahilmgandhi	18:6a4db94011d3	4352	/**
sahilmgandhi	18:6a4db94011d3	4353	* PRNG_KEY4
sahilmgandhi	18:6a4db94011d3	4354	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4355	* Offset: 0x20 PRNG Generated Key4
sahilmgandhi	18:6a4db94011d3	4356	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4357	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4358	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4359	* \|[0:31] \|KEYx \|Store PRNG Generated Key (Read Only)
sahilmgandhi	18:6a4db94011d3	4360	* \| \| \|The bits store the key that is generated by PRNG.
sahilmgandhi	18:6a4db94011d3	4361	*/
sahilmgandhi	18:6a4db94011d3	4362	__I uint32_t PRNG_KEY4;
sahilmgandhi	18:6a4db94011d3	4363
sahilmgandhi	18:6a4db94011d3	4364	/**
sahilmgandhi	18:6a4db94011d3	4365	* PRNG_KEY5
sahilmgandhi	18:6a4db94011d3	4366	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4367	* Offset: 0x24 PRNG Generated Key5
sahilmgandhi	18:6a4db94011d3	4368	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4369	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4370	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4371	* \|[0:31] \|KEYx \|Store PRNG Generated Key (Read Only)
sahilmgandhi	18:6a4db94011d3	4372	* \| \| \|The bits store the key that is generated by PRNG.
sahilmgandhi	18:6a4db94011d3	4373	*/
sahilmgandhi	18:6a4db94011d3	4374	__I uint32_t PRNG_KEY5;
sahilmgandhi	18:6a4db94011d3	4375
sahilmgandhi	18:6a4db94011d3	4376	/**
sahilmgandhi	18:6a4db94011d3	4377	* PRNG_KEY6
sahilmgandhi	18:6a4db94011d3	4378	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4379	* Offset: 0x28 PRNG Generated Key6
sahilmgandhi	18:6a4db94011d3	4380	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4381	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4382	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4383	* \|[0:31] \|KEYx \|Store PRNG Generated Key (Read Only)
sahilmgandhi	18:6a4db94011d3	4384	* \| \| \|The bits store the key that is generated by PRNG.
sahilmgandhi	18:6a4db94011d3	4385	*/
sahilmgandhi	18:6a4db94011d3	4386	__I uint32_t PRNG_KEY6;
sahilmgandhi	18:6a4db94011d3	4387
sahilmgandhi	18:6a4db94011d3	4388	/**
sahilmgandhi	18:6a4db94011d3	4389	* PRNG_KEY7
sahilmgandhi	18:6a4db94011d3	4390	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4391	* Offset: 0x2C PRNG Generated Key7
sahilmgandhi	18:6a4db94011d3	4392	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4393	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4394	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4395	* \|[0:31] \|KEYx \|Store PRNG Generated Key (Read Only)
sahilmgandhi	18:6a4db94011d3	4396	* \| \| \|The bits store the key that is generated by PRNG.
sahilmgandhi	18:6a4db94011d3	4397	*/
sahilmgandhi	18:6a4db94011d3	4398	__I uint32_t PRNG_KEY7;
sahilmgandhi	18:6a4db94011d3	4399	uint32_t RESERVE0[8];
sahilmgandhi	18:6a4db94011d3	4400
sahilmgandhi	18:6a4db94011d3	4401
sahilmgandhi	18:6a4db94011d3	4402	/**
sahilmgandhi	18:6a4db94011d3	4403	* AES_FDBCK0
sahilmgandhi	18:6a4db94011d3	4404	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4405	* Offset: 0x50 AES Engine Output Feedback Data after Cryptographic Operation
sahilmgandhi	18:6a4db94011d3	4406	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4407	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4408	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4409	* \|[0:31] \|FDBCK \|AES Feedback Information
sahilmgandhi	18:6a4db94011d3	4410	* \| \| \|The feedback value is 128 bits in size.
sahilmgandhi	18:6a4db94011d3	4411	* \| \| \|The AES engine uses the data from AES_FEEEDBACK as the data inputted to AES_IV for the next block in DMA cascade mode.
sahilmgandhi	18:6a4db94011d3	4412	* \| \| \|The AES engine outputs feedback information for IV in the next block's operation.
sahilmgandhi	18:6a4db94011d3	4413	* \| \| \|Software can use this feedback information to implement more than four DMA channels.
sahilmgandhi	18:6a4db94011d3	4414	* \| \| \|Software can store that feedback value temporarily.
sahilmgandhi	18:6a4db94011d3	4415	* \| \| \|After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting.
sahilmgandhi	18:6a4db94011d3	4416	*/
sahilmgandhi	18:6a4db94011d3	4417	__I uint32_t AES_FDBCK0;
sahilmgandhi	18:6a4db94011d3	4418
sahilmgandhi	18:6a4db94011d3	4419	/**
sahilmgandhi	18:6a4db94011d3	4420	* AES_FDBCK1
sahilmgandhi	18:6a4db94011d3	4421	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4422	* Offset: 0x54 AES Engine Output Feedback Data after Cryptographic Operation
sahilmgandhi	18:6a4db94011d3	4423	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4424	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4425	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4426	* \|[0:31] \|FDBCK \|AES Feedback Information
sahilmgandhi	18:6a4db94011d3	4427	* \| \| \|The feedback value is 128 bits in size.
sahilmgandhi	18:6a4db94011d3	4428	* \| \| \|The AES engine uses the data from AES_FEEEDBACK as the data inputted to AES_IV for the next block in DMA cascade mode.
sahilmgandhi	18:6a4db94011d3	4429	* \| \| \|The AES engine outputs feedback information for IV in the next block's operation.
sahilmgandhi	18:6a4db94011d3	4430	* \| \| \|Software can use this feedback information to implement more than four DMA channels.
sahilmgandhi	18:6a4db94011d3	4431	* \| \| \|Software can store that feedback value temporarily.
sahilmgandhi	18:6a4db94011d3	4432	* \| \| \|After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting.
sahilmgandhi	18:6a4db94011d3	4433	*/
sahilmgandhi	18:6a4db94011d3	4434	__I uint32_t AES_FDBCK1;
sahilmgandhi	18:6a4db94011d3	4435
sahilmgandhi	18:6a4db94011d3	4436	/**
sahilmgandhi	18:6a4db94011d3	4437	* AES_FDBCK2
sahilmgandhi	18:6a4db94011d3	4438	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4439	* Offset: 0x58 AES Engine Output Feedback Data after Cryptographic Operation
sahilmgandhi	18:6a4db94011d3	4440	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4441	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4442	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4443	* \|[0:31] \|FDBCK \|AES Feedback Information
sahilmgandhi	18:6a4db94011d3	4444	* \| \| \|The feedback value is 128 bits in size.
sahilmgandhi	18:6a4db94011d3	4445	* \| \| \|The AES engine uses the data from AES_FEEEDBACK as the data inputted to AES_IV for the next block in DMA cascade mode.
sahilmgandhi	18:6a4db94011d3	4446	* \| \| \|The AES engine outputs feedback information for IV in the next block's operation.
sahilmgandhi	18:6a4db94011d3	4447	* \| \| \|Software can use this feedback information to implement more than four DMA channels.
sahilmgandhi	18:6a4db94011d3	4448	* \| \| \|Software can store that feedback value temporarily.
sahilmgandhi	18:6a4db94011d3	4449	* \| \| \|After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting.
sahilmgandhi	18:6a4db94011d3	4450	*/
sahilmgandhi	18:6a4db94011d3	4451	__I uint32_t AES_FDBCK2;
sahilmgandhi	18:6a4db94011d3	4452
sahilmgandhi	18:6a4db94011d3	4453	/**
sahilmgandhi	18:6a4db94011d3	4454	* AES_FDBCK3
sahilmgandhi	18:6a4db94011d3	4455	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4456	* Offset: 0x5C AES Engine Output Feedback Data after Cryptographic Operation
sahilmgandhi	18:6a4db94011d3	4457	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4458	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4459	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4460	* \|[0:31] \|FDBCK \|AES Feedback Information
sahilmgandhi	18:6a4db94011d3	4461	* \| \| \|The feedback value is 128 bits in size.
sahilmgandhi	18:6a4db94011d3	4462	* \| \| \|The AES engine uses the data from AES_FEEEDBACK as the data inputted to AES_IV for the next block in DMA cascade mode.
sahilmgandhi	18:6a4db94011d3	4463	* \| \| \|The AES engine outputs feedback information for IV in the next block's operation.
sahilmgandhi	18:6a4db94011d3	4464	* \| \| \|Software can use this feedback information to implement more than four DMA channels.
sahilmgandhi	18:6a4db94011d3	4465	* \| \| \|Software can store that feedback value temporarily.
sahilmgandhi	18:6a4db94011d3	4466	* \| \| \|After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting.
sahilmgandhi	18:6a4db94011d3	4467	*/
sahilmgandhi	18:6a4db94011d3	4468	__I uint32_t AES_FDBCK3;
sahilmgandhi	18:6a4db94011d3	4469
sahilmgandhi	18:6a4db94011d3	4470	/**
sahilmgandhi	18:6a4db94011d3	4471	* TDES_FDBCKH
sahilmgandhi	18:6a4db94011d3	4472	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4473	* Offset: 0x60 TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation
sahilmgandhi	18:6a4db94011d3	4474	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4475	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4476	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4477	* \|[0:31] \|FDBCK \|TDES/DES Feedback
sahilmgandhi	18:6a4db94011d3	4478	* \| \| \|The feedback value is 64 bits in size.
sahilmgandhi	18:6a4db94011d3	4479	* \| \| \|The TDES/DES engine uses the data from CRPT_TDES_FEEEDBACK as the data inputted to CRPT_TDES_IV for the next block in DMA cascade mode.
sahilmgandhi	18:6a4db94011d3	4480	* \| \| \|The feedback register is for CBC, CFB, and OFB mode.
sahilmgandhi	18:6a4db94011d3	4481	* \| \| \|TDES/DES engine outputs feedback information for IV in the next block's operation.
sahilmgandhi	18:6a4db94011d3	4482	* \| \| \|Software can use this feedback information to implement more than four DMA channels.
sahilmgandhi	18:6a4db94011d3	4483	* \| \| \|Software can store that feedback value temporarily.
sahilmgandhi	18:6a4db94011d3	4484	* \| \| \|After switching back, fill the stored feedback value to this register in the same channel operation.
sahilmgandhi	18:6a4db94011d3	4485	* \| \| \|Then can continue the operation with the original setting.
sahilmgandhi	18:6a4db94011d3	4486	*/
sahilmgandhi	18:6a4db94011d3	4487	__I uint32_t TDES_FDBCKH;
sahilmgandhi	18:6a4db94011d3	4488
sahilmgandhi	18:6a4db94011d3	4489	/**
sahilmgandhi	18:6a4db94011d3	4490	* TDES_FDBCKL
sahilmgandhi	18:6a4db94011d3	4491	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4492	* Offset: 0x64 TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation
sahilmgandhi	18:6a4db94011d3	4493	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4494	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4495	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4496	* \|[0:31] \|FDBCK \|TDES/DES Feedback
sahilmgandhi	18:6a4db94011d3	4497	* \| \| \|The feedback value is 64 bits in size.
sahilmgandhi	18:6a4db94011d3	4498	* \| \| \|The TDES/DES engine uses the data from CRPT_TDES_FEEEDBACK as the data inputted to CRPT_TDES_IV for the next block in DMA cascade mode.
sahilmgandhi	18:6a4db94011d3	4499	* \| \| \|The feedback register is for CBC, CFB, and OFB mode.
sahilmgandhi	18:6a4db94011d3	4500	* \| \| \|TDES/DES engine outputs feedback information for IV in the next block's operation.
sahilmgandhi	18:6a4db94011d3	4501	* \| \| \|Software can use this feedback information to implement more than four DMA channels.
sahilmgandhi	18:6a4db94011d3	4502	* \| \| \|Software can store that feedback value temporarily.
sahilmgandhi	18:6a4db94011d3	4503	* \| \| \|After switching back, fill the stored feedback value to this register in the same channel operation.
sahilmgandhi	18:6a4db94011d3	4504	* \| \| \|Then can continue the operation with the original setting.
sahilmgandhi	18:6a4db94011d3	4505	*/
sahilmgandhi	18:6a4db94011d3	4506	__I uint32_t TDES_FDBCKL;
sahilmgandhi	18:6a4db94011d3	4507	uint32_t RESERVE1[38];
sahilmgandhi	18:6a4db94011d3	4508
sahilmgandhi	18:6a4db94011d3	4509
sahilmgandhi	18:6a4db94011d3	4510	/**
sahilmgandhi	18:6a4db94011d3	4511	* AES_CTL
sahilmgandhi	18:6a4db94011d3	4512	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4513	* Offset: 0x100 AES Control Register
sahilmgandhi	18:6a4db94011d3	4514	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4515	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4516	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4517	* \|[0] \|START \|AES Engine Start
sahilmgandhi	18:6a4db94011d3	4518	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	4519	* \| \| \|1 = Start AES engine. BUSY flag will be set.
sahilmgandhi	18:6a4db94011d3	4520	* \| \| \|Note: This bit is always 0 when it's read back.
sahilmgandhi	18:6a4db94011d3	4521	* \|[1] \|STOP \|AES Engine Stop
sahilmgandhi	18:6a4db94011d3	4522	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	4523	* \| \| \|1 = Stop AES engine.
sahilmgandhi	18:6a4db94011d3	4524	* \| \| \|Note: This bit is always 0 when it's read back.
sahilmgandhi	18:6a4db94011d3	4525	* \|[2:3] \|KEYSZ \|AES Key Size
sahilmgandhi	18:6a4db94011d3	4526	* \| \| \|This bit defines three different key size for AES operation.
sahilmgandhi	18:6a4db94011d3	4527	* \| \| \|2'b00 = 128 bits key.
sahilmgandhi	18:6a4db94011d3	4528	* \| \| \|2'b01 = 192 bits key.
sahilmgandhi	18:6a4db94011d3	4529	* \| \| \|2'b10 = 256 bits key.
sahilmgandhi	18:6a4db94011d3	4530	* \| \| \|2'b11 = Reserved.
sahilmgandhi	18:6a4db94011d3	4531	* \| \| \|If the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect.
sahilmgandhi	18:6a4db94011d3	4532	* \|[5] \|DMALAST \|AES Last Block
sahilmgandhi	18:6a4db94011d3	4533	* \| \| \|In DMA mode, this bit must be set as beginning the last DMA cascade round.
sahilmgandhi	18:6a4db94011d3	4534	* \| \| \|In Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode.
sahilmgandhi	18:6a4db94011d3	4535	* \| \| \|This bit is always 0 when it's read back. Must be written again once START is triggered.
sahilmgandhi	18:6a4db94011d3	4536	* \|[6] \|DMACSCAD \|AES Engine DMA With Cascade Mode
sahilmgandhi	18:6a4db94011d3	4537	* \| \| \|0 = DMA cascade function Disabled.
sahilmgandhi	18:6a4db94011d3	4538	* \| \| \|1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation.
sahilmgandhi	18:6a4db94011d3	4539	* \|[7] \|DMAEN \|AES Engine DMA Enable Control
sahilmgandhi	18:6a4db94011d3	4540	* \| \| \|0 = AES DMA engine Disabled.
sahilmgandhi	18:6a4db94011d3	4541	* \| \| \|The AES engine operates in Non-DMA mode, and gets data from the port CRPT_AES_DATIN.
sahilmgandhi	18:6a4db94011d3	4542	* \| \| \|1 = AES DMA engine Enabled.
sahilmgandhi	18:6a4db94011d3	4543	* \| \| \|The AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
sahilmgandhi	18:6a4db94011d3	4544	* \|[8:15] \|OPMODE \|AES Engine Operation Modes
sahilmgandhi	18:6a4db94011d3	4545	* \| \| \|0x00 = ECB (Electronic Codebook Mode)
sahilmgandhi	18:6a4db94011d3	4546	* \| \| \|0x01 = CBC (Cipher Block Chaining Mode).
sahilmgandhi	18:6a4db94011d3	4547	* \| \| \|0x02 = CFB (Cipher Feedback Mode).
sahilmgandhi	18:6a4db94011d3	4548	* \| \| \|0x03 = OFB (Output Feedback Mode).
sahilmgandhi	18:6a4db94011d3	4549	* \| \| \|0x04 = CTR (Counter Mode).
sahilmgandhi	18:6a4db94011d3	4550	* \| \| \|0x10 = CBC-CS1 (CBC Ciphertext-Stealing 1 Mode).
sahilmgandhi	18:6a4db94011d3	4551	* \| \| \|0x11 = CBC-CS2 (CBC Ciphertext-Stealing 2 Mode).
sahilmgandhi	18:6a4db94011d3	4552	* \| \| \|0x12 = CBC-CS3 (CBC Ciphertext-Stealing 3 Mode).
sahilmgandhi	18:6a4db94011d3	4553	* \|[16] \|ENCRPT \|AES Encryption/Decryption
sahilmgandhi	18:6a4db94011d3	4554	* \| \| \|0 = AES engine executes decryption operation.
sahilmgandhi	18:6a4db94011d3	4555	* \| \| \|1 = AES engine executes encryption operation.
sahilmgandhi	18:6a4db94011d3	4556	* \|[22] \|OUTSWAP \|AES Engine Output Data Swap
sahilmgandhi	18:6a4db94011d3	4557	* \| \| \|0 = Keep the original order.
sahilmgandhi	18:6a4db94011d3	4558	* \| \| \|1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
sahilmgandhi	18:6a4db94011d3	4559	* \|[23] \|INSWAP \|AES Engine Input Data Swap
sahilmgandhi	18:6a4db94011d3	4560	* \| \| \|0 = Keep the original order.
sahilmgandhi	18:6a4db94011d3	4561	* \| \| \|1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
sahilmgandhi	18:6a4db94011d3	4562	* \|[24:25] \|CHANNEL \|AES Engine Working Channel
sahilmgandhi	18:6a4db94011d3	4563	* \| \| \|00 = Current control register setting is for channel 0.
sahilmgandhi	18:6a4db94011d3	4564	* \| \| \|01 = Current control register setting is for channel 1.
sahilmgandhi	18:6a4db94011d3	4565	* \| \| \|10 = Current control register setting is for channel 2.
sahilmgandhi	18:6a4db94011d3	4566	* \| \| \|11 = Current control register setting is for channel 3.
sahilmgandhi	18:6a4db94011d3	4567	* \|[26:30] \|KEYUNPRT \|Unprotect Key
sahilmgandhi	18:6a4db94011d3	4568	* \| \| \|Writing 0 to CRPT_AES_CTL [31] and "10110" to CRPT_AES_CTL [30:26] is to unprotect the AES key.
sahilmgandhi	18:6a4db94011d3	4569	* \| \| \|The KEYUNPRT can be read and written.
sahilmgandhi	18:6a4db94011d3	4570	* \| \| \|When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
sahilmgandhi	18:6a4db94011d3	4571	* \|[31] \|KEYPRT \|Protect Key
sahilmgandhi	18:6a4db94011d3	4572	* \| \| \|Read as a flag to reflect KEYPRT.
sahilmgandhi	18:6a4db94011d3	4573	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	4574	* \| \| \|1 = Protect the content of the AES key from reading.
sahilmgandhi	18:6a4db94011d3	4575	* \| \| \|The return value for reading CRPT_AESn_KEYx is not the content of the registers CRPT_AESn_KEYx.
sahilmgandhi	18:6a4db94011d3	4576	* \| \| \|Once it is set, it can be cleared by asserting KEYUNPRT.
sahilmgandhi	18:6a4db94011d3	4577	* \| \| \|And the key content would be cleared as well.
sahilmgandhi	18:6a4db94011d3	4578	*/
sahilmgandhi	18:6a4db94011d3	4579	__IO uint32_t AES_CTL;
sahilmgandhi	18:6a4db94011d3	4580
sahilmgandhi	18:6a4db94011d3	4581	/**
sahilmgandhi	18:6a4db94011d3	4582	* AES_STS
sahilmgandhi	18:6a4db94011d3	4583	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4584	* Offset: 0x104 AES Engine Flag
sahilmgandhi	18:6a4db94011d3	4585	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4586	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4587	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4588	* \|[0] \|BUSY \|AES Engine Busy
sahilmgandhi	18:6a4db94011d3	4589	* \| \| \|0 = The AES engine is idle or finished.
sahilmgandhi	18:6a4db94011d3	4590	* \| \| \|1 = The AES engine is under processing.
sahilmgandhi	18:6a4db94011d3	4591	* \|[8] \|INBUFEMPTY\|AES Input Buffer Empty
sahilmgandhi	18:6a4db94011d3	4592	* \| \| \|0 = There are some data in input buffer waiting for the AES engine to process.
sahilmgandhi	18:6a4db94011d3	4593	* \| \| \|1 = AES input buffer is empty.
sahilmgandhi	18:6a4db94011d3	4594	* \| \| \|Software needs to feed data to the AES engine.
sahilmgandhi	18:6a4db94011d3	4595	* \| \| \|Otherwise, the AES engine will be pending to wait for input data.
sahilmgandhi	18:6a4db94011d3	4596	* \|[9] \|INBUFFULL \|AES Input Buffer Full Flag
sahilmgandhi	18:6a4db94011d3	4597	* \| \| \|0 = AES input buffer is not full. Software can feed the data into the AES engine.
sahilmgandhi	18:6a4db94011d3	4598	* \| \| \|1 = AES input buffer is full.
sahilmgandhi	18:6a4db94011d3	4599	* \| \| \|Software cannot feed data to the AES engine.
sahilmgandhi	18:6a4db94011d3	4600	* \| \| \|Otherwise, the flag INBUFERR will be set to 1.
sahilmgandhi	18:6a4db94011d3	4601	* \|[10] \|INBUFERR \|AES Input Buffer Error Flag
sahilmgandhi	18:6a4db94011d3	4602	* \| \| \|0 = No error.
sahilmgandhi	18:6a4db94011d3	4603	* \| \| \|1 = Error happens during feeding data to the AES engine.
sahilmgandhi	18:6a4db94011d3	4604	* \|[12] \|CNTERR \|AES_CNT Setting Error
sahilmgandhi	18:6a4db94011d3	4605	* \| \| \|0 = No error in AES_CNT setting.
sahilmgandhi	18:6a4db94011d3	4606	* \| \| \|1 = AES_CNT is not a multiply of 16 in ECB, CBC, CFB, OFB, and CTR mode.
sahilmgandhi	18:6a4db94011d3	4607	* \|[16] \|OUTBUFEMPTY\|AES Out Buffer Empty
sahilmgandhi	18:6a4db94011d3	4608	* \| \| \|0 = AES output buffer is not empty. There are some valid data kept in output buffer.
sahilmgandhi	18:6a4db94011d3	4609	* \| \| \|1 = AES output buffer is empty.
sahilmgandhi	18:6a4db94011d3	4610	* \| \| \|Software cannot get data from AES_DATA_OUT.
sahilmgandhi	18:6a4db94011d3	4611	* \| \| \|Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty.
sahilmgandhi	18:6a4db94011d3	4612	* \|[17] \|OUTBUFFULL\|AES Out Buffer Full Flag
sahilmgandhi	18:6a4db94011d3	4613	* \| \| \|0 = AES output buffer is not full.
sahilmgandhi	18:6a4db94011d3	4614	* \| \| \|1 = AES output buffer is full, and software needs to get data from AES_DATA_OUT.
sahilmgandhi	18:6a4db94011d3	4615	* \| \| \|Otherwise, the AES engine will be pending since the output buffer is full.
sahilmgandhi	18:6a4db94011d3	4616	* \|[18] \|OUTBUFERR \|AES Out Buffer Error Flag
sahilmgandhi	18:6a4db94011d3	4617	* \| \| \|0 = No error.
sahilmgandhi	18:6a4db94011d3	4618	* \| \| \|1 = Error happens during getting the result from AES engine.
sahilmgandhi	18:6a4db94011d3	4619	* \|[20] \|BUSERR \|AES DMA Access Bus Error Flag
sahilmgandhi	18:6a4db94011d3	4620	* \| \| \|0 = No error.
sahilmgandhi	18:6a4db94011d3	4621	* \| \| \|1 = Bus error will stop DMA operation and AES engine.
sahilmgandhi	18:6a4db94011d3	4622	*/
sahilmgandhi	18:6a4db94011d3	4623	__I uint32_t AES_STS;
sahilmgandhi	18:6a4db94011d3	4624
sahilmgandhi	18:6a4db94011d3	4625	/**
sahilmgandhi	18:6a4db94011d3	4626	* AES_DATIN
sahilmgandhi	18:6a4db94011d3	4627	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4628	* Offset: 0x108 AES Engine Data Input Port Register
sahilmgandhi	18:6a4db94011d3	4629	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4630	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4631	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4632	* \|[0:31] \|DATIN \|AES Engine Input Port
sahilmgandhi	18:6a4db94011d3	4633	* \| \| \|CPU feeds data to AES engine through this port by checking CRPT_AES_STS. Feed data as INBUFFULL is 0.
sahilmgandhi	18:6a4db94011d3	4634	*/
sahilmgandhi	18:6a4db94011d3	4635	__IO uint32_t AES_DATIN;
sahilmgandhi	18:6a4db94011d3	4636
sahilmgandhi	18:6a4db94011d3	4637	/**
sahilmgandhi	18:6a4db94011d3	4638	* AES_DATOUT
sahilmgandhi	18:6a4db94011d3	4639	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4640	* Offset: 0x10C AES Engine Data Output Port Register
sahilmgandhi	18:6a4db94011d3	4641	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4642	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4643	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4644	* \|[0:31] \|DATOUT \|AES Engine Output Port
sahilmgandhi	18:6a4db94011d3	4645	* \| \| \|CPU gets results from the AES engine through this port by checking CRPT_AES_STS.
sahilmgandhi	18:6a4db94011d3	4646	* \| \| \|Get data as OUTBUFEMPTY is 0.
sahilmgandhi	18:6a4db94011d3	4647	*/
sahilmgandhi	18:6a4db94011d3	4648	__I uint32_t AES_DATOUT;
sahilmgandhi	18:6a4db94011d3	4649
sahilmgandhi	18:6a4db94011d3	4650	/**
sahilmgandhi	18:6a4db94011d3	4651	* AES0_KEY0
sahilmgandhi	18:6a4db94011d3	4652	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4653	* Offset: 0x110 AES Key Word 0 Register for Channel 0
sahilmgandhi	18:6a4db94011d3	4654	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4655	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4656	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4657	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	4658	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4659	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	4660	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	4661	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	4662	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4663	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4664	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4665	*/
sahilmgandhi	18:6a4db94011d3	4666	__IO uint32_t AES0_KEY0;
sahilmgandhi	18:6a4db94011d3	4667
sahilmgandhi	18:6a4db94011d3	4668	/**
sahilmgandhi	18:6a4db94011d3	4669	* AES0_KEY1
sahilmgandhi	18:6a4db94011d3	4670	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4671	* Offset: 0x114 AES Key Word 1 Register for Channel 0
sahilmgandhi	18:6a4db94011d3	4672	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4673	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4674	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4675	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	4676	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4677	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	4678	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	4679	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	4680	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4681	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4682	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4683	*/
sahilmgandhi	18:6a4db94011d3	4684	__IO uint32_t AES0_KEY1;
sahilmgandhi	18:6a4db94011d3	4685
sahilmgandhi	18:6a4db94011d3	4686	/**
sahilmgandhi	18:6a4db94011d3	4687	* AES0_KEY2
sahilmgandhi	18:6a4db94011d3	4688	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4689	* Offset: 0x118 AES Key Word 2 Register for Channel 0
sahilmgandhi	18:6a4db94011d3	4690	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4691	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4692	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4693	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	4694	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4695	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	4696	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	4697	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	4698	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4699	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4700	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4701	*/
sahilmgandhi	18:6a4db94011d3	4702	__IO uint32_t AES0_KEY2;
sahilmgandhi	18:6a4db94011d3	4703
sahilmgandhi	18:6a4db94011d3	4704	/**
sahilmgandhi	18:6a4db94011d3	4705	* AES0_KEY3
sahilmgandhi	18:6a4db94011d3	4706	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4707	* Offset: 0x11C AES Key Word 3 Register for Channel 0
sahilmgandhi	18:6a4db94011d3	4708	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4709	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4710	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4711	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	4712	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4713	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	4714	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	4715	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	4716	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4717	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4718	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4719	*/
sahilmgandhi	18:6a4db94011d3	4720	__IO uint32_t AES0_KEY3;
sahilmgandhi	18:6a4db94011d3	4721
sahilmgandhi	18:6a4db94011d3	4722	/**
sahilmgandhi	18:6a4db94011d3	4723	* AES0_KEY4
sahilmgandhi	18:6a4db94011d3	4724	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4725	* Offset: 0x120 AES Key Word 4 Register for Channel 0
sahilmgandhi	18:6a4db94011d3	4726	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4727	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4728	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4729	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	4730	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4731	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	4732	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	4733	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	4734	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4735	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4736	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4737	*/
sahilmgandhi	18:6a4db94011d3	4738	__IO uint32_t AES0_KEY4;
sahilmgandhi	18:6a4db94011d3	4739
sahilmgandhi	18:6a4db94011d3	4740	/**
sahilmgandhi	18:6a4db94011d3	4741	* AES0_KEY5
sahilmgandhi	18:6a4db94011d3	4742	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4743	* Offset: 0x124 AES Key Word 5 Register for Channel 0
sahilmgandhi	18:6a4db94011d3	4744	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4745	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4746	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4747	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	4748	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4749	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	4750	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	4751	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	4752	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4753	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4754	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4755	*/
sahilmgandhi	18:6a4db94011d3	4756	__IO uint32_t AES0_KEY5;
sahilmgandhi	18:6a4db94011d3	4757
sahilmgandhi	18:6a4db94011d3	4758	/**
sahilmgandhi	18:6a4db94011d3	4759	* AES0_KEY6
sahilmgandhi	18:6a4db94011d3	4760	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4761	* Offset: 0x128 AES Key Word 6 Register for Channel 0
sahilmgandhi	18:6a4db94011d3	4762	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4763	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4764	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4765	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	4766	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4767	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	4768	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	4769	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	4770	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4771	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4772	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4773	*/
sahilmgandhi	18:6a4db94011d3	4774	__IO uint32_t AES0_KEY6;
sahilmgandhi	18:6a4db94011d3	4775
sahilmgandhi	18:6a4db94011d3	4776	/**
sahilmgandhi	18:6a4db94011d3	4777	* AES0_KEY7
sahilmgandhi	18:6a4db94011d3	4778	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4779	* Offset: 0x12C AES Key Word 7 Register for Channel 0
sahilmgandhi	18:6a4db94011d3	4780	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4781	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4782	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4783	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	4784	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4785	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	4786	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	4787	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	4788	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4789	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4790	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4791	*/
sahilmgandhi	18:6a4db94011d3	4792	__IO uint32_t AES0_KEY7;
sahilmgandhi	18:6a4db94011d3	4793
sahilmgandhi	18:6a4db94011d3	4794	/**
sahilmgandhi	18:6a4db94011d3	4795	* AES0_IV0
sahilmgandhi	18:6a4db94011d3	4796	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4797	* Offset: 0x130 AES Initial Vector Word 0 Register for Channel 0
sahilmgandhi	18:6a4db94011d3	4798	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4799	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4800	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4801	* \|[0:31] \|IV \|AES Initial Vector Word X
sahilmgandhi	18:6a4db94011d3	4802	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	4803	* \| \| \|x = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	4804	* \| \| \|Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
sahilmgandhi	18:6a4db94011d3	4805	* \| \| \|Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
sahilmgandhi	18:6a4db94011d3	4806	*/
sahilmgandhi	18:6a4db94011d3	4807	__IO uint32_t AES0_IV0;
sahilmgandhi	18:6a4db94011d3	4808
sahilmgandhi	18:6a4db94011d3	4809	/**
sahilmgandhi	18:6a4db94011d3	4810	* AES0_IV1
sahilmgandhi	18:6a4db94011d3	4811	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4812	* Offset: 0x134 AES Initial Vector Word 1 Register for Channel 0
sahilmgandhi	18:6a4db94011d3	4813	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4814	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4815	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4816	* \|[0:31] \|IV \|AES Initial Vector Word X
sahilmgandhi	18:6a4db94011d3	4817	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	4818	* \| \| \|x = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	4819	* \| \| \|Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
sahilmgandhi	18:6a4db94011d3	4820	* \| \| \|Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
sahilmgandhi	18:6a4db94011d3	4821	*/
sahilmgandhi	18:6a4db94011d3	4822	__IO uint32_t AES0_IV1;
sahilmgandhi	18:6a4db94011d3	4823
sahilmgandhi	18:6a4db94011d3	4824	/**
sahilmgandhi	18:6a4db94011d3	4825	* AES0_IV2
sahilmgandhi	18:6a4db94011d3	4826	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4827	* Offset: 0x138 AES Initial Vector Word 2 Register for Channel 0
sahilmgandhi	18:6a4db94011d3	4828	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4829	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4830	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4831	* \|[0:31] \|IV \|AES Initial Vector Word X
sahilmgandhi	18:6a4db94011d3	4832	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	4833	* \| \| \|x = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	4834	* \| \| \|Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
sahilmgandhi	18:6a4db94011d3	4835	* \| \| \|Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
sahilmgandhi	18:6a4db94011d3	4836	*/
sahilmgandhi	18:6a4db94011d3	4837	__IO uint32_t AES0_IV2;
sahilmgandhi	18:6a4db94011d3	4838
sahilmgandhi	18:6a4db94011d3	4839	/**
sahilmgandhi	18:6a4db94011d3	4840	* AES0_IV3
sahilmgandhi	18:6a4db94011d3	4841	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4842	* Offset: 0x13C AES Initial Vector Word 3 Register for Channel 0
sahilmgandhi	18:6a4db94011d3	4843	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4844	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4845	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4846	* \|[0:31] \|IV \|AES Initial Vector Word X
sahilmgandhi	18:6a4db94011d3	4847	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	4848	* \| \| \|x = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	4849	* \| \| \|Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
sahilmgandhi	18:6a4db94011d3	4850	* \| \| \|Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
sahilmgandhi	18:6a4db94011d3	4851	*/
sahilmgandhi	18:6a4db94011d3	4852	__IO uint32_t AES0_IV3;
sahilmgandhi	18:6a4db94011d3	4853
sahilmgandhi	18:6a4db94011d3	4854	/**
sahilmgandhi	18:6a4db94011d3	4855	* AES0_SADDR
sahilmgandhi	18:6a4db94011d3	4856	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4857	* Offset: 0x140 AES DMA Source Address Register for Channel 0
sahilmgandhi	18:6a4db94011d3	4858	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4859	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4860	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4861	* \|[0:31] \|SADDR \|AES DMA Source Address
sahilmgandhi	18:6a4db94011d3	4862	* \| \| \|The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
sahilmgandhi	18:6a4db94011d3	4863	* \| \| \|The AES_SADR keeps the source address of the data buffer where the source text is stored.
sahilmgandhi	18:6a4db94011d3	4864	* \| \| \|Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation.
sahilmgandhi	18:6a4db94011d3	4865	* \| \| \|The start of source address should be located at word boundary.
sahilmgandhi	18:6a4db94011d3	4866	* \| \| \|In other words, bit 1 and 0 of AES_SADR are ignored.
sahilmgandhi	18:6a4db94011d3	4867	* \| \| \|AES_SADR can be read and written.
sahilmgandhi	18:6a4db94011d3	4868	* \| \| \|Writing to AES_SADR while the AES accelerator is operating doesn't affect the current AES operation.
sahilmgandhi	18:6a4db94011d3	4869	* \| \| \|But the value of AES_SADR will be updated later on.
sahilmgandhi	18:6a4db94011d3	4870	* \| \| \|Consequently, software can prepare the DMA source address for the next AES operation.
sahilmgandhi	18:6a4db94011d3	4871	* \| \| \|In DMA mode, software can update the next AES_SADR before triggering START.
sahilmgandhi	18:6a4db94011d3	4872	* \| \| \|The value of AES_SADR and AES_DADR can be the same.
sahilmgandhi	18:6a4db94011d3	4873	*/
sahilmgandhi	18:6a4db94011d3	4874	__IO uint32_t AES0_SADDR;
sahilmgandhi	18:6a4db94011d3	4875
sahilmgandhi	18:6a4db94011d3	4876	/**
sahilmgandhi	18:6a4db94011d3	4877	* AES0_DADDR
sahilmgandhi	18:6a4db94011d3	4878	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4879	* Offset: 0x144 AES DMA Destination Address Register for Channel 0
sahilmgandhi	18:6a4db94011d3	4880	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4881	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4882	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4883	* \|[0:31] \|DADDR \|AES DMA Destination Address
sahilmgandhi	18:6a4db94011d3	4884	* \| \| \|The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO.
sahilmgandhi	18:6a4db94011d3	4885	* \| \| \|The AES_DADR keeps the destination address of the data buffer where the engine output's text will be stored.
sahilmgandhi	18:6a4db94011d3	4886	* \| \| \|Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished.
sahilmgandhi	18:6a4db94011d3	4887	* \| \| \|The start of destination address should be located at word boundary.
sahilmgandhi	18:6a4db94011d3	4888	* \| \| \|In other words, bit 1 and 0 of AES_DADR are ignored.
sahilmgandhi	18:6a4db94011d3	4889	* \| \| \|AES_DADR can be read and written.
sahilmgandhi	18:6a4db94011d3	4890	* \| \| \|Writing to AES_DADR while the AES accelerator is operating doesn't affect the current AES operation.
sahilmgandhi	18:6a4db94011d3	4891	* \| \| \|But the value of AES_DADR will be updated later on.
sahilmgandhi	18:6a4db94011d3	4892	* \| \| \|Consequently, software can prepare the destination address for the next AES operation.
sahilmgandhi	18:6a4db94011d3	4893	* \| \| \|In DMA mode, software can update the next AES_DADR before triggering START.
sahilmgandhi	18:6a4db94011d3	4894	* \| \| \|The value of AES_SADR and AES_DADR can be the same.
sahilmgandhi	18:6a4db94011d3	4895	*/
sahilmgandhi	18:6a4db94011d3	4896	__IO uint32_t AES0_DADDR;
sahilmgandhi	18:6a4db94011d3	4897
sahilmgandhi	18:6a4db94011d3	4898	/**
sahilmgandhi	18:6a4db94011d3	4899	* AES0_CNT
sahilmgandhi	18:6a4db94011d3	4900	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4901	* Offset: 0x148 AES Byte Count Register for Channel 0
sahilmgandhi	18:6a4db94011d3	4902	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4903	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4904	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4905	* \|[0:31] \|CNT \|AES Byte Count
sahilmgandhi	18:6a4db94011d3	4906	* \| \| \|The AES_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode.
sahilmgandhi	18:6a4db94011d3	4907	* \| \| \|The AES_CNT is 32-bit and the maximum of byte count is 4G bytes.
sahilmgandhi	18:6a4db94011d3	4908	* \| \| \|AES_CNT can be read and written.
sahilmgandhi	18:6a4db94011d3	4909	* \| \| \|Writing to AES_CNT while the AES accelerator is operating doesn't affect the current AES operation.
sahilmgandhi	18:6a4db94011d3	4910	* \| \| \|But the value of AES_CNT will be updated later on.
sahilmgandhi	18:6a4db94011d3	4911	* \| \| \|Consequently, software can prepare the byte count of data for the next AES operation.
sahilmgandhi	18:6a4db94011d3	4912	* \| \| \|According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block.
sahilmgandhi	18:6a4db94011d3	4913	* \| \| \|Operations that are less than one block will output unexpected result.
sahilmgandhi	18:6a4db94011d3	4914	* \| \| \|In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, AES_CNT must be set as byte count for the last block of data before feeding in the last block of data.
sahilmgandhi	18:6a4db94011d3	4915	* \| \| \|In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, AES_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
sahilmgandhi	18:6a4db94011d3	4916	*/
sahilmgandhi	18:6a4db94011d3	4917	__IO uint32_t AES0_CNT;
sahilmgandhi	18:6a4db94011d3	4918
sahilmgandhi	18:6a4db94011d3	4919	/**
sahilmgandhi	18:6a4db94011d3	4920	* AES1_KEY0
sahilmgandhi	18:6a4db94011d3	4921	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4922	* Offset: 0x14C AES Key Word 0 Register for Channel 1
sahilmgandhi	18:6a4db94011d3	4923	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4924	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4925	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4926	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	4927	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4928	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	4929	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	4930	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	4931	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4932	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4933	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4934	*/
sahilmgandhi	18:6a4db94011d3	4935	__IO uint32_t AES1_KEY0;
sahilmgandhi	18:6a4db94011d3	4936
sahilmgandhi	18:6a4db94011d3	4937	/**
sahilmgandhi	18:6a4db94011d3	4938	* AES1_KEY1
sahilmgandhi	18:6a4db94011d3	4939	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4940	* Offset: 0x150 AES Key Word 1 Register for Channel 1
sahilmgandhi	18:6a4db94011d3	4941	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4942	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4943	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4944	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	4945	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4946	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	4947	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	4948	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	4949	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4950	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4951	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4952	*/
sahilmgandhi	18:6a4db94011d3	4953	__IO uint32_t AES1_KEY1;
sahilmgandhi	18:6a4db94011d3	4954
sahilmgandhi	18:6a4db94011d3	4955	/**
sahilmgandhi	18:6a4db94011d3	4956	* AES1_KEY2
sahilmgandhi	18:6a4db94011d3	4957	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4958	* Offset: 0x154 AES Key Word 2 Register for Channel 1
sahilmgandhi	18:6a4db94011d3	4959	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4960	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4961	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4962	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	4963	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4964	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	4965	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	4966	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	4967	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4968	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4969	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4970	*/
sahilmgandhi	18:6a4db94011d3	4971	__IO uint32_t AES1_KEY2;
sahilmgandhi	18:6a4db94011d3	4972
sahilmgandhi	18:6a4db94011d3	4973	/**
sahilmgandhi	18:6a4db94011d3	4974	* AES1_KEY3
sahilmgandhi	18:6a4db94011d3	4975	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4976	* Offset: 0x158 AES Key Word 3 Register for Channel 1
sahilmgandhi	18:6a4db94011d3	4977	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4978	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4979	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4980	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	4981	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4982	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	4983	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	4984	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	4985	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4986	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4987	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	4988	*/
sahilmgandhi	18:6a4db94011d3	4989	__IO uint32_t AES1_KEY3;
sahilmgandhi	18:6a4db94011d3	4990
sahilmgandhi	18:6a4db94011d3	4991	/**
sahilmgandhi	18:6a4db94011d3	4992	* AES1_KEY4
sahilmgandhi	18:6a4db94011d3	4993	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	4994	* Offset: 0x15C AES Key Word 4 Register for Channel 1
sahilmgandhi	18:6a4db94011d3	4995	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	4996	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	4997	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	4998	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	4999	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5000	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5001	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	5002	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	5003	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5004	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5005	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5006	*/
sahilmgandhi	18:6a4db94011d3	5007	__IO uint32_t AES1_KEY4;
sahilmgandhi	18:6a4db94011d3	5008
sahilmgandhi	18:6a4db94011d3	5009	/**
sahilmgandhi	18:6a4db94011d3	5010	* AES1_KEY5
sahilmgandhi	18:6a4db94011d3	5011	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5012	* Offset: 0x160 AES Key Word 5 Register for Channel 1
sahilmgandhi	18:6a4db94011d3	5013	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5014	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5015	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5016	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	5017	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5018	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5019	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	5020	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	5021	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5022	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5023	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5024	*/
sahilmgandhi	18:6a4db94011d3	5025	__IO uint32_t AES1_KEY5;
sahilmgandhi	18:6a4db94011d3	5026
sahilmgandhi	18:6a4db94011d3	5027	/**
sahilmgandhi	18:6a4db94011d3	5028	* AES1_KEY6
sahilmgandhi	18:6a4db94011d3	5029	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5030	* Offset: 0x164 AES Key Word 6 Register for Channel 1
sahilmgandhi	18:6a4db94011d3	5031	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5032	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5033	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5034	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	5035	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5036	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5037	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	5038	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	5039	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5040	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5041	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5042	*/
sahilmgandhi	18:6a4db94011d3	5043	__IO uint32_t AES1_KEY6;
sahilmgandhi	18:6a4db94011d3	5044
sahilmgandhi	18:6a4db94011d3	5045	/**
sahilmgandhi	18:6a4db94011d3	5046	* AES1_KEY7
sahilmgandhi	18:6a4db94011d3	5047	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5048	* Offset: 0x168 AES Key Word 7 Register for Channel 1
sahilmgandhi	18:6a4db94011d3	5049	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5050	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5051	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5052	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	5053	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5054	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5055	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	5056	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	5057	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5058	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5059	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5060	*/
sahilmgandhi	18:6a4db94011d3	5061	__IO uint32_t AES1_KEY7;
sahilmgandhi	18:6a4db94011d3	5062
sahilmgandhi	18:6a4db94011d3	5063	/**
sahilmgandhi	18:6a4db94011d3	5064	* AES1_IV0
sahilmgandhi	18:6a4db94011d3	5065	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5066	* Offset: 0x16C AES Initial Vector Word 0 Register for Channel 1
sahilmgandhi	18:6a4db94011d3	5067	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5068	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5069	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5070	* \|[0:31] \|IV \|AES Initial Vector Word X
sahilmgandhi	18:6a4db94011d3	5071	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5072	* \| \| \|x = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5073	* \| \| \|Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
sahilmgandhi	18:6a4db94011d3	5074	* \| \| \|Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
sahilmgandhi	18:6a4db94011d3	5075	*/
sahilmgandhi	18:6a4db94011d3	5076	__IO uint32_t AES1_IV0;
sahilmgandhi	18:6a4db94011d3	5077
sahilmgandhi	18:6a4db94011d3	5078	/**
sahilmgandhi	18:6a4db94011d3	5079	* AES1_IV1
sahilmgandhi	18:6a4db94011d3	5080	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5081	* Offset: 0x170 AES Initial Vector Word 1 Register for Channel 1
sahilmgandhi	18:6a4db94011d3	5082	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5083	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5084	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5085	* \|[0:31] \|IV \|AES Initial Vector Word X
sahilmgandhi	18:6a4db94011d3	5086	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5087	* \| \| \|x = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5088	* \| \| \|Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
sahilmgandhi	18:6a4db94011d3	5089	* \| \| \|Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
sahilmgandhi	18:6a4db94011d3	5090	*/
sahilmgandhi	18:6a4db94011d3	5091	__IO uint32_t AES1_IV1;
sahilmgandhi	18:6a4db94011d3	5092
sahilmgandhi	18:6a4db94011d3	5093	/**
sahilmgandhi	18:6a4db94011d3	5094	* AES1_IV2
sahilmgandhi	18:6a4db94011d3	5095	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5096	* Offset: 0x174 AES Initial Vector Word 2 Register for Channel 1
sahilmgandhi	18:6a4db94011d3	5097	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5098	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5099	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5100	* \|[0:31] \|IV \|AES Initial Vector Word X
sahilmgandhi	18:6a4db94011d3	5101	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5102	* \| \| \|x = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5103	* \| \| \|Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
sahilmgandhi	18:6a4db94011d3	5104	* \| \| \|Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
sahilmgandhi	18:6a4db94011d3	5105	*/
sahilmgandhi	18:6a4db94011d3	5106	__IO uint32_t AES1_IV2;
sahilmgandhi	18:6a4db94011d3	5107
sahilmgandhi	18:6a4db94011d3	5108	/**
sahilmgandhi	18:6a4db94011d3	5109	* AES1_IV3
sahilmgandhi	18:6a4db94011d3	5110	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5111	* Offset: 0x178 AES Initial Vector Word 3 Register for Channel 1
sahilmgandhi	18:6a4db94011d3	5112	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5113	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5114	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5115	* \|[0:31] \|IV \|AES Initial Vector Word X
sahilmgandhi	18:6a4db94011d3	5116	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5117	* \| \| \|x = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5118	* \| \| \|Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
sahilmgandhi	18:6a4db94011d3	5119	* \| \| \|Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
sahilmgandhi	18:6a4db94011d3	5120	*/
sahilmgandhi	18:6a4db94011d3	5121	__IO uint32_t AES1_IV3;
sahilmgandhi	18:6a4db94011d3	5122
sahilmgandhi	18:6a4db94011d3	5123	/**
sahilmgandhi	18:6a4db94011d3	5124	* AES1_SADDR
sahilmgandhi	18:6a4db94011d3	5125	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5126	* Offset: 0x17C AES DMA Source Address Register for Channel 1
sahilmgandhi	18:6a4db94011d3	5127	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5128	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5129	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5130	* \|[0:31] \|SADDR \|AES DMA Source Address
sahilmgandhi	18:6a4db94011d3	5131	* \| \| \|The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
sahilmgandhi	18:6a4db94011d3	5132	* \| \| \|The AES_SADR keeps the source address of the data buffer where the source text is stored.
sahilmgandhi	18:6a4db94011d3	5133	* \| \| \|Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation.
sahilmgandhi	18:6a4db94011d3	5134	* \| \| \|The start of source address should be located at word boundary.
sahilmgandhi	18:6a4db94011d3	5135	* \| \| \|In other words, bit 1 and 0 of AES_SADR are ignored.
sahilmgandhi	18:6a4db94011d3	5136	* \| \| \|AES_SADR can be read and written.
sahilmgandhi	18:6a4db94011d3	5137	* \| \| \|Writing to AES_SADR while the AES accelerator is operating doesn't affect the current AES operation.
sahilmgandhi	18:6a4db94011d3	5138	* \| \| \|But the value of AES_SADR will be updated later on.
sahilmgandhi	18:6a4db94011d3	5139	* \| \| \|Consequently, software can prepare the DMA source address for the next AES operation.
sahilmgandhi	18:6a4db94011d3	5140	* \| \| \|In DMA mode, software can update the next AES_SADR before triggering START.
sahilmgandhi	18:6a4db94011d3	5141	* \| \| \|The value of AES_SADR and AES_DADR can be the same.
sahilmgandhi	18:6a4db94011d3	5142	*/
sahilmgandhi	18:6a4db94011d3	5143	__IO uint32_t AES1_SADDR;
sahilmgandhi	18:6a4db94011d3	5144
sahilmgandhi	18:6a4db94011d3	5145	/**
sahilmgandhi	18:6a4db94011d3	5146	* AES1_DADDR
sahilmgandhi	18:6a4db94011d3	5147	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5148	* Offset: 0x180 AES DMA Destination Address Register for Channel 1
sahilmgandhi	18:6a4db94011d3	5149	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5150	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5151	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5152	* \|[0:31] \|DADDR \|AES DMA Destination Address
sahilmgandhi	18:6a4db94011d3	5153	* \| \| \|The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO.
sahilmgandhi	18:6a4db94011d3	5154	* \| \| \|The AES_DADR keeps the destination address of the data buffer where the engine output's text will be stored.
sahilmgandhi	18:6a4db94011d3	5155	* \| \| \|Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished.
sahilmgandhi	18:6a4db94011d3	5156	* \| \| \|The start of destination address should be located at word boundary.
sahilmgandhi	18:6a4db94011d3	5157	* \| \| \|In other words, bit 1 and 0 of AES_DADR are ignored.
sahilmgandhi	18:6a4db94011d3	5158	* \| \| \|AES_DADR can be read and written.
sahilmgandhi	18:6a4db94011d3	5159	* \| \| \|Writing to AES_DADR while the AES accelerator is operating doesn't affect the current AES operation.
sahilmgandhi	18:6a4db94011d3	5160	* \| \| \|But the value of AES_DADR will be updated later on.
sahilmgandhi	18:6a4db94011d3	5161	* \| \| \|Consequently, software can prepare the destination address for the next AES operation.
sahilmgandhi	18:6a4db94011d3	5162	* \| \| \|In DMA mode, software can update the next AES_DADR before triggering START.
sahilmgandhi	18:6a4db94011d3	5163	* \| \| \|The value of AES_SADR and AES_DADR can be the same.
sahilmgandhi	18:6a4db94011d3	5164	*/
sahilmgandhi	18:6a4db94011d3	5165	__IO uint32_t AES1_DADDR;
sahilmgandhi	18:6a4db94011d3	5166
sahilmgandhi	18:6a4db94011d3	5167	/**
sahilmgandhi	18:6a4db94011d3	5168	* AES1_CNT
sahilmgandhi	18:6a4db94011d3	5169	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5170	* Offset: 0x184 AES Byte Count Register for Channel 1
sahilmgandhi	18:6a4db94011d3	5171	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5172	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5173	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5174	* \|[0:31] \|CNT \|AES Byte Count
sahilmgandhi	18:6a4db94011d3	5175	* \| \| \|The AES_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode.
sahilmgandhi	18:6a4db94011d3	5176	* \| \| \|The AES_CNT is 32-bit and the maximum of byte count is 4G bytes.
sahilmgandhi	18:6a4db94011d3	5177	* \| \| \|AES_CNT can be read and written.
sahilmgandhi	18:6a4db94011d3	5178	* \| \| \|Writing to AES_CNT while the AES accelerator is operating doesn't affect the current AES operation.
sahilmgandhi	18:6a4db94011d3	5179	* \| \| \|But the value of AES_CNT will be updated later on.
sahilmgandhi	18:6a4db94011d3	5180	* \| \| \|Consequently, software can prepare the byte count of data for the next AES operation.
sahilmgandhi	18:6a4db94011d3	5181	* \| \| \|According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block.
sahilmgandhi	18:6a4db94011d3	5182	* \| \| \|Operations that are less than one block will output unexpected result.
sahilmgandhi	18:6a4db94011d3	5183	* \| \| \|In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, AES_CNT must be set as byte count for the last block of data before feeding in the last block of data.
sahilmgandhi	18:6a4db94011d3	5184	* \| \| \|In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, AES_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
sahilmgandhi	18:6a4db94011d3	5185	*/
sahilmgandhi	18:6a4db94011d3	5186	__IO uint32_t AES1_CNT;
sahilmgandhi	18:6a4db94011d3	5187
sahilmgandhi	18:6a4db94011d3	5188	/**
sahilmgandhi	18:6a4db94011d3	5189	* AES2_KEY0
sahilmgandhi	18:6a4db94011d3	5190	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5191	* Offset: 0x188 AES Key Word 0 Register for Channel 2
sahilmgandhi	18:6a4db94011d3	5192	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5193	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5194	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5195	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	5196	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5197	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5198	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	5199	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	5200	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5201	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5202	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5203	*/
sahilmgandhi	18:6a4db94011d3	5204	__IO uint32_t AES2_KEY0;
sahilmgandhi	18:6a4db94011d3	5205
sahilmgandhi	18:6a4db94011d3	5206	/**
sahilmgandhi	18:6a4db94011d3	5207	* AES2_KEY1
sahilmgandhi	18:6a4db94011d3	5208	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5209	* Offset: 0x18C AES Key Word 1 Register for Channel 2
sahilmgandhi	18:6a4db94011d3	5210	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5211	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5212	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5213	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	5214	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5215	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5216	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	5217	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	5218	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5219	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5220	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5221	*/
sahilmgandhi	18:6a4db94011d3	5222	__IO uint32_t AES2_KEY1;
sahilmgandhi	18:6a4db94011d3	5223
sahilmgandhi	18:6a4db94011d3	5224	/**
sahilmgandhi	18:6a4db94011d3	5225	* AES2_KEY2
sahilmgandhi	18:6a4db94011d3	5226	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5227	* Offset: 0x190 AES Key Word 2 Register for Channel 2
sahilmgandhi	18:6a4db94011d3	5228	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5229	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5230	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5231	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	5232	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5233	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5234	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	5235	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	5236	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5237	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5238	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5239	*/
sahilmgandhi	18:6a4db94011d3	5240	__IO uint32_t AES2_KEY2;
sahilmgandhi	18:6a4db94011d3	5241
sahilmgandhi	18:6a4db94011d3	5242	/**
sahilmgandhi	18:6a4db94011d3	5243	* AES2_KEY3
sahilmgandhi	18:6a4db94011d3	5244	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5245	* Offset: 0x194 AES Key Word 3 Register for Channel 2
sahilmgandhi	18:6a4db94011d3	5246	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5247	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5248	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5249	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	5250	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5251	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5252	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	5253	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	5254	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5255	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5256	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5257	*/
sahilmgandhi	18:6a4db94011d3	5258	__IO uint32_t AES2_KEY3;
sahilmgandhi	18:6a4db94011d3	5259
sahilmgandhi	18:6a4db94011d3	5260	/**
sahilmgandhi	18:6a4db94011d3	5261	* AES2_KEY4
sahilmgandhi	18:6a4db94011d3	5262	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5263	* Offset: 0x198 AES Key Word 4 Register for Channel 2
sahilmgandhi	18:6a4db94011d3	5264	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5265	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5266	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5267	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	5268	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5269	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5270	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	5271	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	5272	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5273	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5274	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5275	*/
sahilmgandhi	18:6a4db94011d3	5276	__IO uint32_t AES2_KEY4;
sahilmgandhi	18:6a4db94011d3	5277
sahilmgandhi	18:6a4db94011d3	5278	/**
sahilmgandhi	18:6a4db94011d3	5279	* AES2_KEY5
sahilmgandhi	18:6a4db94011d3	5280	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5281	* Offset: 0x19C AES Key Word 5 Register for Channel 2
sahilmgandhi	18:6a4db94011d3	5282	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5283	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5284	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5285	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	5286	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5287	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5288	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	5289	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	5290	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5291	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5292	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5293	*/
sahilmgandhi	18:6a4db94011d3	5294	__IO uint32_t AES2_KEY5;
sahilmgandhi	18:6a4db94011d3	5295
sahilmgandhi	18:6a4db94011d3	5296	/**
sahilmgandhi	18:6a4db94011d3	5297	* AES2_KEY6
sahilmgandhi	18:6a4db94011d3	5298	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5299	* Offset: 0x1A0 AES Key Word 6 Register for Channel 2
sahilmgandhi	18:6a4db94011d3	5300	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5301	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5302	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5303	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	5304	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5305	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5306	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	5307	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	5308	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5309	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5310	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5311	*/
sahilmgandhi	18:6a4db94011d3	5312	__IO uint32_t AES2_KEY6;
sahilmgandhi	18:6a4db94011d3	5313
sahilmgandhi	18:6a4db94011d3	5314	/**
sahilmgandhi	18:6a4db94011d3	5315	* AES2_KEY7
sahilmgandhi	18:6a4db94011d3	5316	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5317	* Offset: 0x1A4 AES Key Word 7 Register for Channel 2
sahilmgandhi	18:6a4db94011d3	5318	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5319	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5320	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5321	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	5322	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5323	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5324	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	5325	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	5326	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5327	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5328	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5329	*/
sahilmgandhi	18:6a4db94011d3	5330	__IO uint32_t AES2_KEY7;
sahilmgandhi	18:6a4db94011d3	5331
sahilmgandhi	18:6a4db94011d3	5332	/**
sahilmgandhi	18:6a4db94011d3	5333	* AES2_IV0
sahilmgandhi	18:6a4db94011d3	5334	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5335	* Offset: 0x1A8 AES Initial Vector Word 0 Register for Channel 2
sahilmgandhi	18:6a4db94011d3	5336	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5337	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5338	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5339	* \|[0:31] \|IV \|AES Initial Vector Word X
sahilmgandhi	18:6a4db94011d3	5340	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5341	* \| \| \|x = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5342	* \| \| \|Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
sahilmgandhi	18:6a4db94011d3	5343	* \| \| \|Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
sahilmgandhi	18:6a4db94011d3	5344	*/
sahilmgandhi	18:6a4db94011d3	5345	__IO uint32_t AES2_IV0;
sahilmgandhi	18:6a4db94011d3	5346
sahilmgandhi	18:6a4db94011d3	5347	/**
sahilmgandhi	18:6a4db94011d3	5348	* AES2_IV1
sahilmgandhi	18:6a4db94011d3	5349	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5350	* Offset: 0x1AC AES Initial Vector Word 1 Register for Channel 2
sahilmgandhi	18:6a4db94011d3	5351	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5352	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5353	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5354	* \|[0:31] \|IV \|AES Initial Vector Word X
sahilmgandhi	18:6a4db94011d3	5355	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5356	* \| \| \|x = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5357	* \| \| \|Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
sahilmgandhi	18:6a4db94011d3	5358	* \| \| \|Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
sahilmgandhi	18:6a4db94011d3	5359	*/
sahilmgandhi	18:6a4db94011d3	5360	__IO uint32_t AES2_IV1;
sahilmgandhi	18:6a4db94011d3	5361
sahilmgandhi	18:6a4db94011d3	5362	/**
sahilmgandhi	18:6a4db94011d3	5363	* AES2_IV2
sahilmgandhi	18:6a4db94011d3	5364	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5365	* Offset: 0x1B0 AES Initial Vector Word 2 Register for Channel 2
sahilmgandhi	18:6a4db94011d3	5366	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5367	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5368	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5369	* \|[0:31] \|IV \|AES Initial Vector Word X
sahilmgandhi	18:6a4db94011d3	5370	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5371	* \| \| \|x = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5372	* \| \| \|Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
sahilmgandhi	18:6a4db94011d3	5373	* \| \| \|Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
sahilmgandhi	18:6a4db94011d3	5374	*/
sahilmgandhi	18:6a4db94011d3	5375	__IO uint32_t AES2_IV2;
sahilmgandhi	18:6a4db94011d3	5376
sahilmgandhi	18:6a4db94011d3	5377	/**
sahilmgandhi	18:6a4db94011d3	5378	* AES2_IV3
sahilmgandhi	18:6a4db94011d3	5379	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5380	* Offset: 0x1B4 AES Initial Vector Word 3 Register for Channel 2
sahilmgandhi	18:6a4db94011d3	5381	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5382	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5383	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5384	* \|[0:31] \|IV \|AES Initial Vector Word X
sahilmgandhi	18:6a4db94011d3	5385	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5386	* \| \| \|x = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5387	* \| \| \|Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
sahilmgandhi	18:6a4db94011d3	5388	* \| \| \|Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
sahilmgandhi	18:6a4db94011d3	5389	*/
sahilmgandhi	18:6a4db94011d3	5390	__IO uint32_t AES2_IV3;
sahilmgandhi	18:6a4db94011d3	5391
sahilmgandhi	18:6a4db94011d3	5392	/**
sahilmgandhi	18:6a4db94011d3	5393	* AES2_SADDR
sahilmgandhi	18:6a4db94011d3	5394	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5395	* Offset: 0x1B8 AES DMA Source Address Register for Channel 2
sahilmgandhi	18:6a4db94011d3	5396	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5397	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5398	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5399	* \|[0:31] \|SADDR \|AES DMA Source Address
sahilmgandhi	18:6a4db94011d3	5400	* \| \| \|The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
sahilmgandhi	18:6a4db94011d3	5401	* \| \| \|The AES_SADR keeps the source address of the data buffer where the source text is stored.
sahilmgandhi	18:6a4db94011d3	5402	* \| \| \|Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation.
sahilmgandhi	18:6a4db94011d3	5403	* \| \| \|The start of source address should be located at word boundary.
sahilmgandhi	18:6a4db94011d3	5404	* \| \| \|In other words, bit 1 and 0 of AES_SADR are ignored.
sahilmgandhi	18:6a4db94011d3	5405	* \| \| \|AES_SADR can be read and written.
sahilmgandhi	18:6a4db94011d3	5406	* \| \| \|Writing to AES_SADR while the AES accelerator is operating doesn't affect the current AES operation.
sahilmgandhi	18:6a4db94011d3	5407	* \| \| \|But the value of AES_SADR will be updated later on.
sahilmgandhi	18:6a4db94011d3	5408	* \| \| \|Consequently, software can prepare the DMA source address for the next AES operation.
sahilmgandhi	18:6a4db94011d3	5409	* \| \| \|In DMA mode, software can update the next AES_SADR before triggering START.
sahilmgandhi	18:6a4db94011d3	5410	* \| \| \|The value of AES_SADR and AES_DADR can be the same.
sahilmgandhi	18:6a4db94011d3	5411	*/
sahilmgandhi	18:6a4db94011d3	5412	__IO uint32_t AES2_SADDR;
sahilmgandhi	18:6a4db94011d3	5413
sahilmgandhi	18:6a4db94011d3	5414	/**
sahilmgandhi	18:6a4db94011d3	5415	* AES2_DADDR
sahilmgandhi	18:6a4db94011d3	5416	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5417	* Offset: 0x1BC AES DMA Destination Address Register for Channel 2
sahilmgandhi	18:6a4db94011d3	5418	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5419	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5420	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5421	* \|[0:31] \|DADDR \|AES DMA Destination Address
sahilmgandhi	18:6a4db94011d3	5422	* \| \| \|The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO.
sahilmgandhi	18:6a4db94011d3	5423	* \| \| \|The AES_DADR keeps the destination address of the data buffer where the engine output's text will be stored.
sahilmgandhi	18:6a4db94011d3	5424	* \| \| \|Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished.
sahilmgandhi	18:6a4db94011d3	5425	* \| \| \|The start of destination address should be located at word boundary.
sahilmgandhi	18:6a4db94011d3	5426	* \| \| \|In other words, bit 1 and 0 of AES_DADR are ignored.
sahilmgandhi	18:6a4db94011d3	5427	* \| \| \|AES_DADR can be read and written.
sahilmgandhi	18:6a4db94011d3	5428	* \| \| \|Writing to AES_DADR while the AES accelerator is operating doesn't affect the current AES operation.
sahilmgandhi	18:6a4db94011d3	5429	* \| \| \|But the value of AES_DADR will be updated later on.
sahilmgandhi	18:6a4db94011d3	5430	* \| \| \|Consequently, software can prepare the destination address for the next AES operation.
sahilmgandhi	18:6a4db94011d3	5431	* \| \| \|In DMA mode, software can update the next AES_DADR before triggering START.
sahilmgandhi	18:6a4db94011d3	5432	* \| \| \|The value of AES_SADR and AES_DADR can be the same.
sahilmgandhi	18:6a4db94011d3	5433	*/
sahilmgandhi	18:6a4db94011d3	5434	__IO uint32_t AES2_DADDR;
sahilmgandhi	18:6a4db94011d3	5435
sahilmgandhi	18:6a4db94011d3	5436	/**
sahilmgandhi	18:6a4db94011d3	5437	* AES2_CNT
sahilmgandhi	18:6a4db94011d3	5438	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5439	* Offset: 0x1C0 AES Byte Count Register for Channel 2
sahilmgandhi	18:6a4db94011d3	5440	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5441	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5442	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5443	* \|[0:31] \|CNT \|AES Byte Count
sahilmgandhi	18:6a4db94011d3	5444	* \| \| \|The AES_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode.
sahilmgandhi	18:6a4db94011d3	5445	* \| \| \|The AES_CNT is 32-bit and the maximum of byte count is 4G bytes.
sahilmgandhi	18:6a4db94011d3	5446	* \| \| \|AES_CNT can be read and written.
sahilmgandhi	18:6a4db94011d3	5447	* \| \| \|Writing to AES_CNT while the AES accelerator is operating doesn't affect the current AES operation.
sahilmgandhi	18:6a4db94011d3	5448	* \| \| \|But the value of AES_CNT will be updated later on.
sahilmgandhi	18:6a4db94011d3	5449	* \| \| \|Consequently, software can prepare the byte count of data for the next AES operation.
sahilmgandhi	18:6a4db94011d3	5450	* \| \| \|According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block.
sahilmgandhi	18:6a4db94011d3	5451	* \| \| \|Operations that are less than one block will output unexpected result.
sahilmgandhi	18:6a4db94011d3	5452	* \| \| \|In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, AES_CNT must be set as byte count for the last block of data before feeding in the last block of data.
sahilmgandhi	18:6a4db94011d3	5453	* \| \| \|In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, AES_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
sahilmgandhi	18:6a4db94011d3	5454	*/
sahilmgandhi	18:6a4db94011d3	5455	__IO uint32_t AES2_CNT;
sahilmgandhi	18:6a4db94011d3	5456
sahilmgandhi	18:6a4db94011d3	5457	/**
sahilmgandhi	18:6a4db94011d3	5458	* AES3_KEY0
sahilmgandhi	18:6a4db94011d3	5459	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5460	* Offset: 0x1C4 AES Key Word 0 Register for Channel 3
sahilmgandhi	18:6a4db94011d3	5461	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5462	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5463	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5464	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	5465	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5466	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5467	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	5468	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	5469	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5470	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5471	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5472	*/
sahilmgandhi	18:6a4db94011d3	5473	__IO uint32_t AES3_KEY0;
sahilmgandhi	18:6a4db94011d3	5474
sahilmgandhi	18:6a4db94011d3	5475	/**
sahilmgandhi	18:6a4db94011d3	5476	* AES3_KEY1
sahilmgandhi	18:6a4db94011d3	5477	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5478	* Offset: 0x1C8 AES Key Word 1 Register for Channel 3
sahilmgandhi	18:6a4db94011d3	5479	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5480	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5481	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5482	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	5483	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5484	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5485	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	5486	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	5487	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5488	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5489	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5490	*/
sahilmgandhi	18:6a4db94011d3	5491	__IO uint32_t AES3_KEY1;
sahilmgandhi	18:6a4db94011d3	5492
sahilmgandhi	18:6a4db94011d3	5493	/**
sahilmgandhi	18:6a4db94011d3	5494	* AES3_KEY2
sahilmgandhi	18:6a4db94011d3	5495	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5496	* Offset: 0x1CC AES Key Word 2 Register for Channel 3
sahilmgandhi	18:6a4db94011d3	5497	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5498	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5499	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5500	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	5501	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5502	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5503	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	5504	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	5505	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5506	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5507	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5508	*/
sahilmgandhi	18:6a4db94011d3	5509	__IO uint32_t AES3_KEY2;
sahilmgandhi	18:6a4db94011d3	5510
sahilmgandhi	18:6a4db94011d3	5511	/**
sahilmgandhi	18:6a4db94011d3	5512	* AES3_KEY3
sahilmgandhi	18:6a4db94011d3	5513	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5514	* Offset: 0x1D0 AES Key Word 3 Register for Channel 3
sahilmgandhi	18:6a4db94011d3	5515	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5516	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5517	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5518	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	5519	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5520	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5521	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	5522	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	5523	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5524	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5525	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5526	*/
sahilmgandhi	18:6a4db94011d3	5527	__IO uint32_t AES3_KEY3;
sahilmgandhi	18:6a4db94011d3	5528
sahilmgandhi	18:6a4db94011d3	5529	/**
sahilmgandhi	18:6a4db94011d3	5530	* AES3_KEY4
sahilmgandhi	18:6a4db94011d3	5531	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5532	* Offset: 0x1D4 AES Key Word 4 Register for Channel 3
sahilmgandhi	18:6a4db94011d3	5533	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5534	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5535	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5536	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	5537	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5538	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5539	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	5540	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	5541	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5542	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5543	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5544	*/
sahilmgandhi	18:6a4db94011d3	5545	__IO uint32_t AES3_KEY4;
sahilmgandhi	18:6a4db94011d3	5546
sahilmgandhi	18:6a4db94011d3	5547	/**
sahilmgandhi	18:6a4db94011d3	5548	* AES3_KEY5
sahilmgandhi	18:6a4db94011d3	5549	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5550	* Offset: 0x1D8 AES Key Word 5 Register for Channel 3
sahilmgandhi	18:6a4db94011d3	5551	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5552	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5553	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5554	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	5555	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5556	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5557	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	5558	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	5559	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5560	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5561	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5562	*/
sahilmgandhi	18:6a4db94011d3	5563	__IO uint32_t AES3_KEY5;
sahilmgandhi	18:6a4db94011d3	5564
sahilmgandhi	18:6a4db94011d3	5565	/**
sahilmgandhi	18:6a4db94011d3	5566	* AES3_KEY6
sahilmgandhi	18:6a4db94011d3	5567	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5568	* Offset: 0x1DC AES Key Word 6 Register for Channel 3
sahilmgandhi	18:6a4db94011d3	5569	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5570	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5571	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5572	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	5573	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5574	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5575	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	5576	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	5577	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5578	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5579	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5580	*/
sahilmgandhi	18:6a4db94011d3	5581	__IO uint32_t AES3_KEY6;
sahilmgandhi	18:6a4db94011d3	5582
sahilmgandhi	18:6a4db94011d3	5583	/**
sahilmgandhi	18:6a4db94011d3	5584	* AES3_KEY7
sahilmgandhi	18:6a4db94011d3	5585	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5586	* Offset: 0x1E0 AES Key Word 7 Register for Channel 3
sahilmgandhi	18:6a4db94011d3	5587	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5588	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5589	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5590	* \|[0:31] \|KEY \|AES Key X
sahilmgandhi	18:6a4db94011d3	5591	* \| \| \|The KEY keeps the security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5592	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5593	* \| \| \|x = 0, 1..7.
sahilmgandhi	18:6a4db94011d3	5594	* \| \| \|The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
sahilmgandhi	18:6a4db94011d3	5595	* \| \| \|{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5596	* \| \| \|{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5597	* \| \| \|{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
sahilmgandhi	18:6a4db94011d3	5598	*/
sahilmgandhi	18:6a4db94011d3	5599	__IO uint32_t AES3_KEY7;
sahilmgandhi	18:6a4db94011d3	5600
sahilmgandhi	18:6a4db94011d3	5601	/**
sahilmgandhi	18:6a4db94011d3	5602	* AES3_IV0
sahilmgandhi	18:6a4db94011d3	5603	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5604	* Offset: 0x1E4 AES Initial Vector Word 0 Register for Channel 3
sahilmgandhi	18:6a4db94011d3	5605	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5606	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5607	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5608	* \|[0:31] \|IV \|AES Initial Vector Word X
sahilmgandhi	18:6a4db94011d3	5609	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5610	* \| \| \|x = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5611	* \| \| \|Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
sahilmgandhi	18:6a4db94011d3	5612	* \| \| \|Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
sahilmgandhi	18:6a4db94011d3	5613	*/
sahilmgandhi	18:6a4db94011d3	5614	__IO uint32_t AES3_IV0;
sahilmgandhi	18:6a4db94011d3	5615
sahilmgandhi	18:6a4db94011d3	5616	/**
sahilmgandhi	18:6a4db94011d3	5617	* AES3_IV1
sahilmgandhi	18:6a4db94011d3	5618	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5619	* Offset: 0x1E8 AES Initial Vector Word 1 Register for Channel 3
sahilmgandhi	18:6a4db94011d3	5620	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5621	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5622	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5623	* \|[0:31] \|IV \|AES Initial Vector Word X
sahilmgandhi	18:6a4db94011d3	5624	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5625	* \| \| \|x = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5626	* \| \| \|Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
sahilmgandhi	18:6a4db94011d3	5627	* \| \| \|Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
sahilmgandhi	18:6a4db94011d3	5628	*/
sahilmgandhi	18:6a4db94011d3	5629	__IO uint32_t AES3_IV1;
sahilmgandhi	18:6a4db94011d3	5630
sahilmgandhi	18:6a4db94011d3	5631	/**
sahilmgandhi	18:6a4db94011d3	5632	* AES3_IV2
sahilmgandhi	18:6a4db94011d3	5633	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5634	* Offset: 0x1EC AES Initial Vector Word 2 Register for Channel 3
sahilmgandhi	18:6a4db94011d3	5635	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5636	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5637	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5638	* \|[0:31] \|IV \|AES Initial Vector Word X
sahilmgandhi	18:6a4db94011d3	5639	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5640	* \| \| \|x = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5641	* \| \| \|Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
sahilmgandhi	18:6a4db94011d3	5642	* \| \| \|Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
sahilmgandhi	18:6a4db94011d3	5643	*/
sahilmgandhi	18:6a4db94011d3	5644	__IO uint32_t AES3_IV2;
sahilmgandhi	18:6a4db94011d3	5645
sahilmgandhi	18:6a4db94011d3	5646	/**
sahilmgandhi	18:6a4db94011d3	5647	* AES3_IV3
sahilmgandhi	18:6a4db94011d3	5648	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5649	* Offset: 0x1F0 AES Initial Vector Word 3 Register for Channel 3
sahilmgandhi	18:6a4db94011d3	5650	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5651	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5652	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5653	* \|[0:31] \|IV \|AES Initial Vector Word X
sahilmgandhi	18:6a4db94011d3	5654	* \| \| \|n = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5655	* \| \| \|x = 0, 1..3.
sahilmgandhi	18:6a4db94011d3	5656	* \| \| \|Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
sahilmgandhi	18:6a4db94011d3	5657	* \| \| \|Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
sahilmgandhi	18:6a4db94011d3	5658	*/
sahilmgandhi	18:6a4db94011d3	5659	__IO uint32_t AES3_IV3;
sahilmgandhi	18:6a4db94011d3	5660
sahilmgandhi	18:6a4db94011d3	5661	/**
sahilmgandhi	18:6a4db94011d3	5662	* AES3_SADDR
sahilmgandhi	18:6a4db94011d3	5663	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5664	* Offset: 0x1F4 AES DMA Source Address Register for Channel 3
sahilmgandhi	18:6a4db94011d3	5665	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5666	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5667	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5668	* \|[0:31] \|SADDR \|AES DMA Source Address
sahilmgandhi	18:6a4db94011d3	5669	* \| \| \|The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
sahilmgandhi	18:6a4db94011d3	5670	* \| \| \|The AES_SADR keeps the source address of the data buffer where the source text is stored.
sahilmgandhi	18:6a4db94011d3	5671	* \| \| \|Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation.
sahilmgandhi	18:6a4db94011d3	5672	* \| \| \|The start of source address should be located at word boundary.
sahilmgandhi	18:6a4db94011d3	5673	* \| \| \|In other words, bit 1 and 0 of AES_SADR are ignored.
sahilmgandhi	18:6a4db94011d3	5674	* \| \| \|AES_SADR can be read and written.
sahilmgandhi	18:6a4db94011d3	5675	* \| \| \|Writing to AES_SADR while the AES accelerator is operating doesn't affect the current AES operation.
sahilmgandhi	18:6a4db94011d3	5676	* \| \| \|But the value of AES_SADR will be updated later on.
sahilmgandhi	18:6a4db94011d3	5677	* \| \| \|Consequently, software can prepare the DMA source address for the next AES operation.
sahilmgandhi	18:6a4db94011d3	5678	* \| \| \|In DMA mode, software can update the next AES_SADR before triggering START.
sahilmgandhi	18:6a4db94011d3	5679	* \| \| \|The value of AES_SADR and AES_DADR can be the same.
sahilmgandhi	18:6a4db94011d3	5680	*/
sahilmgandhi	18:6a4db94011d3	5681	__IO uint32_t AES3_SADDR;
sahilmgandhi	18:6a4db94011d3	5682
sahilmgandhi	18:6a4db94011d3	5683	/**
sahilmgandhi	18:6a4db94011d3	5684	* AES3_DADDR
sahilmgandhi	18:6a4db94011d3	5685	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5686	* Offset: 0x1F8 AES DMA Destination Address Register for Channel 3
sahilmgandhi	18:6a4db94011d3	5687	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5688	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5689	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5690	* \|[0:31] \|DADDR \|AES DMA Destination Address
sahilmgandhi	18:6a4db94011d3	5691	* \| \| \|The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO.
sahilmgandhi	18:6a4db94011d3	5692	* \| \| \|The AES_DADR keeps the destination address of the data buffer where the engine output's text will be stored.
sahilmgandhi	18:6a4db94011d3	5693	* \| \| \|Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished.
sahilmgandhi	18:6a4db94011d3	5694	* \| \| \|The start of destination address should be located at word boundary.
sahilmgandhi	18:6a4db94011d3	5695	* \| \| \|In other words, bit 1 and 0 of AES_DADR are ignored.
sahilmgandhi	18:6a4db94011d3	5696	* \| \| \|AES_DADR can be read and written.
sahilmgandhi	18:6a4db94011d3	5697	* \| \| \|Writing to AES_DADR while the AES accelerator is operating doesn't affect the current AES operation.
sahilmgandhi	18:6a4db94011d3	5698	* \| \| \|But the value of AES_DADR will be updated later on.
sahilmgandhi	18:6a4db94011d3	5699	* \| \| \|Consequently, software can prepare the destination address for the next AES operation.
sahilmgandhi	18:6a4db94011d3	5700	* \| \| \|In DMA mode, software can update the next AES_DADR before triggering START.
sahilmgandhi	18:6a4db94011d3	5701	* \| \| \|The value of AES_SADR and AES_DADR can be the same.
sahilmgandhi	18:6a4db94011d3	5702	*/
sahilmgandhi	18:6a4db94011d3	5703	__IO uint32_t AES3_DADDR;
sahilmgandhi	18:6a4db94011d3	5704
sahilmgandhi	18:6a4db94011d3	5705	/**
sahilmgandhi	18:6a4db94011d3	5706	* AES3_CNT
sahilmgandhi	18:6a4db94011d3	5707	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5708	* Offset: 0x1FC AES Byte Count Register for Channel 3
sahilmgandhi	18:6a4db94011d3	5709	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5710	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5711	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5712	* \|[0:31] \|CNT \|AES Byte Count
sahilmgandhi	18:6a4db94011d3	5713	* \| \| \|The AES_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode.
sahilmgandhi	18:6a4db94011d3	5714	* \| \| \|The AES_CNT is 32-bit and the maximum of byte count is 4G bytes.
sahilmgandhi	18:6a4db94011d3	5715	* \| \| \|AES_CNT can be read and written.
sahilmgandhi	18:6a4db94011d3	5716	* \| \| \|Writing to AES_CNT while the AES accelerator is operating doesn't affect the current AES operation.
sahilmgandhi	18:6a4db94011d3	5717	* \| \| \|But the value of AES_CNT will be updated later on.
sahilmgandhi	18:6a4db94011d3	5718	* \| \| \|Consequently, software can prepare the byte count of data for the next AES operation.
sahilmgandhi	18:6a4db94011d3	5719	* \| \| \|According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block.
sahilmgandhi	18:6a4db94011d3	5720	* \| \| \|Operations that are less than one block will output unexpected result.
sahilmgandhi	18:6a4db94011d3	5721	* \| \| \|In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, AES_CNT must be set as byte count for the last block of data before feeding in the last block of data.
sahilmgandhi	18:6a4db94011d3	5722	* \| \| \|In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, AES_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
sahilmgandhi	18:6a4db94011d3	5723	*/
sahilmgandhi	18:6a4db94011d3	5724	__IO uint32_t AES3_CNT;
sahilmgandhi	18:6a4db94011d3	5725
sahilmgandhi	18:6a4db94011d3	5726	/**
sahilmgandhi	18:6a4db94011d3	5727	* TDES_CTL
sahilmgandhi	18:6a4db94011d3	5728	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5729	* Offset: 0x200 TDES/DES Control Register
sahilmgandhi	18:6a4db94011d3	5730	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5731	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5732	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5733	* \|[0] \|START \|TDES/DES Engine Start
sahilmgandhi	18:6a4db94011d3	5734	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	5735	* \| \| \|1 = Start TDES/DES engine. The flag BUSY would be set.
sahilmgandhi	18:6a4db94011d3	5736	* \| \| \|Note: The bit is always 0 when it's read back.
sahilmgandhi	18:6a4db94011d3	5737	* \|[1] \|STOP \|TDES/DES Engine Stop
sahilmgandhi	18:6a4db94011d3	5738	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	5739	* \| \| \|1 = Stop TDES/DES engine.
sahilmgandhi	18:6a4db94011d3	5740	* \| \| \|Note: The bit is always 0 when it's read back.
sahilmgandhi	18:6a4db94011d3	5741	* \|[2] \|TMODE \|TDES/DES Engine Operating Mode
sahilmgandhi	18:6a4db94011d3	5742	* \| \| \|0 = Set DES mode for TDES/DES engine.
sahilmgandhi	18:6a4db94011d3	5743	* \| \| \|1 = Set Triple DES mode for TDES/DES engine.
sahilmgandhi	18:6a4db94011d3	5744	* \|[3] \|3KEYS \|TDES/DES Key Number
sahilmgandhi	18:6a4db94011d3	5745	* \| \| \|0 = Select KEY1 and KEY2 in TDES/DES engine.
sahilmgandhi	18:6a4db94011d3	5746	* \| \| \|1 = Triple keys in TDES/DES engine Enabled.
sahilmgandhi	18:6a4db94011d3	5747	* \|[5] \|DMALAST \|TDES/DES Engine Start For The Last Block
sahilmgandhi	18:6a4db94011d3	5748	* \| \| \|In DMA mode, this bit must be set as beginning the last DMA cascade round.
sahilmgandhi	18:6a4db94011d3	5749	* \| \| \|In Non-DMA mode, this bit must be set as feeding in last block of data.
sahilmgandhi	18:6a4db94011d3	5750	* \|[6] \|DMACSCAD \|TDES/DES Engine DMA With Cascade Mode
sahilmgandhi	18:6a4db94011d3	5751	* \| \| \|0 = DMA cascade function Disabled.
sahilmgandhi	18:6a4db94011d3	5752	* \| \| \|1 = In DMA Cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation.
sahilmgandhi	18:6a4db94011d3	5753	* \|[7] \|DMAEN \|TDES/DES Engine DMA Enable Control
sahilmgandhi	18:6a4db94011d3	5754	* \| \| \|0 = TDES_DMA engine Disabled.
sahilmgandhi	18:6a4db94011d3	5755	* \| \| \|TDES engine operates in Non-DMA mode, and get data from the port CRPT_TDES_DATIN.
sahilmgandhi	18:6a4db94011d3	5756	* \| \| \|1 = TDES_DMA engine Enabled.
sahilmgandhi	18:6a4db94011d3	5757	* \| \| \|TDES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
sahilmgandhi	18:6a4db94011d3	5758	* \|[8:10] \|OPMODE \|TDES/DES Engine Operation Mode
sahilmgandhi	18:6a4db94011d3	5759	* \| \| \|0x00 = ECB (Electronic Codebook Mode).
sahilmgandhi	18:6a4db94011d3	5760	* \| \| \|0x01 = CBC (Cipher Block Chaining Mode).
sahilmgandhi	18:6a4db94011d3	5761	* \| \| \|0x02 = CFB (Cipher Feedback Mode).
sahilmgandhi	18:6a4db94011d3	5762	* \| \| \|0x03 = OFB (Output Feedback Mode).
sahilmgandhi	18:6a4db94011d3	5763	* \| \| \|0x04 = CTR (Counter Mode).
sahilmgandhi	18:6a4db94011d3	5764	* \| \| \|Others = CTR (Counter Mode).
sahilmgandhi	18:6a4db94011d3	5765	* \|[16] \|ENCRPT \|TDES/DES Encryption/Decryption
sahilmgandhi	18:6a4db94011d3	5766	* \| \| \|0 = TDES engine executes decryption operation.
sahilmgandhi	18:6a4db94011d3	5767	* \| \| \|1 = TDES engine executes encryption operation.
sahilmgandhi	18:6a4db94011d3	5768	* \|[21] \|BLKSWAP \|TDES/DES Engine Block Double Word Endian Swap
sahilmgandhi	18:6a4db94011d3	5769	* \| \| \|0 = Keep the original order, e.g. {WORD_H, WORD_L}.
sahilmgandhi	18:6a4db94011d3	5770	* \| \| \|1 = When this bit is set to 1, the TDES engine would exchange high and low word in the sequence {WORD_L, WORD_H}.
sahilmgandhi	18:6a4db94011d3	5771	* \|[22] \|OUTSWAP \|TDES/DES Engine Output Data Swap
sahilmgandhi	18:6a4db94011d3	5772	* \| \| \|0 = Keep the original order.
sahilmgandhi	18:6a4db94011d3	5773	* \| \| \|1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
sahilmgandhi	18:6a4db94011d3	5774	* \|[23] \|INSWAP \|TDES/DES Engine Input Data Swap
sahilmgandhi	18:6a4db94011d3	5775	* \| \| \|0 = Keep the original order.
sahilmgandhi	18:6a4db94011d3	5776	* \| \| \|1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
sahilmgandhi	18:6a4db94011d3	5777	* \|[24:25] \|CHANNEL \|TDES/DES Engine Working Channel
sahilmgandhi	18:6a4db94011d3	5778	* \| \| \|00 = Current control register setting is for channel 0.
sahilmgandhi	18:6a4db94011d3	5779	* \| \| \|01 = Current control register setting is for channel 1.
sahilmgandhi	18:6a4db94011d3	5780	* \| \| \|10 = Current control register setting is for channel 2.
sahilmgandhi	18:6a4db94011d3	5781	* \| \| \|11 = Current control register setting is for channel 3.
sahilmgandhi	18:6a4db94011d3	5782	* \|[26:30] \|KEYUNPRT \|Unprotect Key
sahilmgandhi	18:6a4db94011d3	5783	* \| \| \|Writing 0 to CRPT_TDES_CTL [31] and "10110" to CRPT_TDES_CTL [30:26] is to unprotect TDES key.
sahilmgandhi	18:6a4db94011d3	5784	* \| \| \|The KEYUNPRT can be read and written.
sahilmgandhi	18:6a4db94011d3	5785	* \| \| \|When it is written as the TDES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
sahilmgandhi	18:6a4db94011d3	5786	* \|[31] \|KEYPRT \|Protect Key
sahilmgandhi	18:6a4db94011d3	5787	* \| \| \|Read as a flag to reflect KEYPRT.
sahilmgandhi	18:6a4db94011d3	5788	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	5789	* \| \| \|1 = This bit is to protect the content of TDES key from reading.
sahilmgandhi	18:6a4db94011d3	5790	* \| \| \|The return value for reading CRPT_ TDESn_KEYxH/L is not the content in the registers CRPT_ TDESn_KEYxH/L.
sahilmgandhi	18:6a4db94011d3	5791	* \| \| \|Once it is set, it can be cleared by asserting KEYUNPRT.
sahilmgandhi	18:6a4db94011d3	5792	* \| \| \|The key content would be cleared as well.
sahilmgandhi	18:6a4db94011d3	5793	*/
sahilmgandhi	18:6a4db94011d3	5794	__IO uint32_t TDES_CTL;
sahilmgandhi	18:6a4db94011d3	5795
sahilmgandhi	18:6a4db94011d3	5796	/**
sahilmgandhi	18:6a4db94011d3	5797	* TDES_STS
sahilmgandhi	18:6a4db94011d3	5798	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5799	* Offset: 0x204 TDES/DES Engine Flag
sahilmgandhi	18:6a4db94011d3	5800	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5801	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5802	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5803	* \|[0] \|BUSY \|TDES/DES Engine Busy
sahilmgandhi	18:6a4db94011d3	5804	* \| \| \|0 = TDES/DES engine is idle or finished.
sahilmgandhi	18:6a4db94011d3	5805	* \| \| \|1 = TDES/DES engine is under processing.
sahilmgandhi	18:6a4db94011d3	5806	* \|[8] \|INBUFEMPTY\|TDES/DES In Buffer Empty
sahilmgandhi	18:6a4db94011d3	5807	* \| \| \|0 = There are some data in input buffer waiting for the TDES/DES engine to process.
sahilmgandhi	18:6a4db94011d3	5808	* \| \| \|1 = TDES/DES input buffer is empty.
sahilmgandhi	18:6a4db94011d3	5809	* \| \| \|Software needs to feed data to the TDES/DES engine.
sahilmgandhi	18:6a4db94011d3	5810	* \| \| \|Otherwise, the TDES/DES engine will be pending to wait for input data.
sahilmgandhi	18:6a4db94011d3	5811	* \|[9] \|INBUFFULL \|TDES/DES In Buffer Full Flag
sahilmgandhi	18:6a4db94011d3	5812	* \| \| \|0 = TDES/DES input buffer is not full. Software can feed the data into the TDES/DES engine.
sahilmgandhi	18:6a4db94011d3	5813	* \| \| \|1 = TDES input buffer is full.
sahilmgandhi	18:6a4db94011d3	5814	* \| \| \|Software cannot feed data to the TDES/DES engine.
sahilmgandhi	18:6a4db94011d3	5815	* \| \| \|Otherwise, the flag INBUFERR will be set to 1.
sahilmgandhi	18:6a4db94011d3	5816	* \|[10] \|INBUFERR \|TDES/DES In Buffer Error Flag
sahilmgandhi	18:6a4db94011d3	5817	* \| \| \|0 = No error.
sahilmgandhi	18:6a4db94011d3	5818	* \| \| \|1 = Error happens during feeding data to the TDES/DES engine.
sahilmgandhi	18:6a4db94011d3	5819	* \|[16] \|OUTBUFEMPTY\|TDES/DES Output Buffer Empty Flag
sahilmgandhi	18:6a4db94011d3	5820	* \| \| \|0 = TDES/DES output buffer is not empty. There are some valid data kept in output buffer.
sahilmgandhi	18:6a4db94011d3	5821	* \| \| \|1 = TDES/DES output buffer is empty, Software cannot get data from TDES_DATA_OUT.
sahilmgandhi	18:6a4db94011d3	5822	* \| \| \|Otherwise the flag OUTBUFERR will be set to 1, since output buffer is empty.
sahilmgandhi	18:6a4db94011d3	5823	* \|[17] \|OUTBUFFULL\|TDES/DES Output Buffer Full Flag
sahilmgandhi	18:6a4db94011d3	5824	* \| \| \|0 = TDES/DES output buffer is not full.
sahilmgandhi	18:6a4db94011d3	5825	* \| \| \|1 = TDES/DES output buffer is full, and software needs to get data from TDES_DATA_OUT.
sahilmgandhi	18:6a4db94011d3	5826	* \| \| \|Otherwise, the TDES/DES engine will be pending since output buffer is full.
sahilmgandhi	18:6a4db94011d3	5827	* \|[18] \|OUTBUFERR \|TDES/DES Out Buffer Error Flag
sahilmgandhi	18:6a4db94011d3	5828	* \| \| \|0 = No error.
sahilmgandhi	18:6a4db94011d3	5829	* \| \| \|1 = Error happens during getting test result from TDES/DES engine.
sahilmgandhi	18:6a4db94011d3	5830	* \|[20] \|BUSERR \|TDES/DES DMA Access Bus Error Flag
sahilmgandhi	18:6a4db94011d3	5831	* \| \| \|0 = No error.
sahilmgandhi	18:6a4db94011d3	5832	* \| \| \|1 = Bus error will stop DMA operation and TDES/DES engine.
sahilmgandhi	18:6a4db94011d3	5833	*/
sahilmgandhi	18:6a4db94011d3	5834	__I uint32_t TDES_STS;
sahilmgandhi	18:6a4db94011d3	5835
sahilmgandhi	18:6a4db94011d3	5836	/**
sahilmgandhi	18:6a4db94011d3	5837	* TDES0_KEY1H
sahilmgandhi	18:6a4db94011d3	5838	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5839	* Offset: 0x208 TDES/DES Key 1 High Word Register for Channel 0
sahilmgandhi	18:6a4db94011d3	5840	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5841	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5842	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5843	* \|[0:31] \|KEYH_KEYL \|TDES/DES Key X High/Low Word
sahilmgandhi	18:6a4db94011d3	5844	* \| \| \|The key registers for TDES/DES algorithm calculation
sahilmgandhi	18:6a4db94011d3	5845	* \| \| \|The security key for the TDES/DES accelerator is 64 bits.
sahilmgandhi	18:6a4db94011d3	5846	* \| \| \|Thus, it needs two 32-bit registers to store a security key.
sahilmgandhi	18:6a4db94011d3	5847	* \| \| \|The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
sahilmgandhi	18:6a4db94011d3	5848	*/
sahilmgandhi	18:6a4db94011d3	5849	__IO uint32_t TDES0_KEY1H;
sahilmgandhi	18:6a4db94011d3	5850
sahilmgandhi	18:6a4db94011d3	5851	/**
sahilmgandhi	18:6a4db94011d3	5852	* TDES0_KEY1L
sahilmgandhi	18:6a4db94011d3	5853	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5854	* Offset: 0x20C TDES/DES Key 1 Low Word Register for Channel 0
sahilmgandhi	18:6a4db94011d3	5855	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5856	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5857	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5858	* \|[0:31] \|KEYH_KEYL \|TDES/DES Key X High/Low Word
sahilmgandhi	18:6a4db94011d3	5859	* \| \| \|The key registers for TDES/DES algorithm calculation
sahilmgandhi	18:6a4db94011d3	5860	* \| \| \|The security key for the TDES/DES accelerator is 64 bits.
sahilmgandhi	18:6a4db94011d3	5861	* \| \| \|Thus, it needs two 32-bit registers to store a security key.
sahilmgandhi	18:6a4db94011d3	5862	* \| \| \|The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
sahilmgandhi	18:6a4db94011d3	5863	*/
sahilmgandhi	18:6a4db94011d3	5864	__IO uint32_t TDES0_KEY1L;
sahilmgandhi	18:6a4db94011d3	5865
sahilmgandhi	18:6a4db94011d3	5866	/**
sahilmgandhi	18:6a4db94011d3	5867	* TDES0_KEY2H
sahilmgandhi	18:6a4db94011d3	5868	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5869	* Offset: 0x210 TDES Key 2 High Word Register for Channel 0
sahilmgandhi	18:6a4db94011d3	5870	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5871	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5872	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5873	* \|[0:31] \|KEYH_KEYL \|TDES/DES Key X High/Low Word
sahilmgandhi	18:6a4db94011d3	5874	* \| \| \|The key registers for TDES/DES algorithm calculation
sahilmgandhi	18:6a4db94011d3	5875	* \| \| \|The security key for the TDES/DES accelerator is 64 bits.
sahilmgandhi	18:6a4db94011d3	5876	* \| \| \|Thus, it needs two 32-bit registers to store a security key.
sahilmgandhi	18:6a4db94011d3	5877	* \| \| \|The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
sahilmgandhi	18:6a4db94011d3	5878	*/
sahilmgandhi	18:6a4db94011d3	5879	__IO uint32_t TDES0_KEY2H;
sahilmgandhi	18:6a4db94011d3	5880
sahilmgandhi	18:6a4db94011d3	5881	/**
sahilmgandhi	18:6a4db94011d3	5882	* TDES0_KEY2L
sahilmgandhi	18:6a4db94011d3	5883	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5884	* Offset: 0x214 TDES Key 2 Low Word Register for Channel 0
sahilmgandhi	18:6a4db94011d3	5885	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5886	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5887	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5888	* \|[0:31] \|KEYH_KEYL \|TDES/DES Key X High/Low Word
sahilmgandhi	18:6a4db94011d3	5889	* \| \| \|The key registers for TDES/DES algorithm calculation
sahilmgandhi	18:6a4db94011d3	5890	* \| \| \|The security key for the TDES/DES accelerator is 64 bits.
sahilmgandhi	18:6a4db94011d3	5891	* \| \| \|Thus, it needs two 32-bit registers to store a security key.
sahilmgandhi	18:6a4db94011d3	5892	* \| \| \|The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
sahilmgandhi	18:6a4db94011d3	5893	*/
sahilmgandhi	18:6a4db94011d3	5894	__IO uint32_t TDES0_KEY2L;
sahilmgandhi	18:6a4db94011d3	5895
sahilmgandhi	18:6a4db94011d3	5896	/**
sahilmgandhi	18:6a4db94011d3	5897	* TDES0_KEY3H
sahilmgandhi	18:6a4db94011d3	5898	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5899	* Offset: 0x218 TDES Key 3 High Word Register for Channel 0
sahilmgandhi	18:6a4db94011d3	5900	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5901	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5902	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5903	* \|[0:31] \|KEYH_KEYL \|TDES/DES Key X High/Low Word
sahilmgandhi	18:6a4db94011d3	5904	* \| \| \|The key registers for TDES/DES algorithm calculation
sahilmgandhi	18:6a4db94011d3	5905	* \| \| \|The security key for the TDES/DES accelerator is 64 bits.
sahilmgandhi	18:6a4db94011d3	5906	* \| \| \|Thus, it needs two 32-bit registers to store a security key.
sahilmgandhi	18:6a4db94011d3	5907	* \| \| \|The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
sahilmgandhi	18:6a4db94011d3	5908	*/
sahilmgandhi	18:6a4db94011d3	5909	__IO uint32_t TDES0_KEY3H;
sahilmgandhi	18:6a4db94011d3	5910
sahilmgandhi	18:6a4db94011d3	5911	/**
sahilmgandhi	18:6a4db94011d3	5912	* TDES0_KEY3L
sahilmgandhi	18:6a4db94011d3	5913	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5914	* Offset: 0x21C TDES Key 3 Low Word Register for Channel 0
sahilmgandhi	18:6a4db94011d3	5915	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5916	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5917	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5918	* \|[0:31] \|KEYH_KEYL \|TDES/DES Key X High/Low Word
sahilmgandhi	18:6a4db94011d3	5919	* \| \| \|The key registers for TDES/DES algorithm calculation
sahilmgandhi	18:6a4db94011d3	5920	* \| \| \|The security key for the TDES/DES accelerator is 64 bits.
sahilmgandhi	18:6a4db94011d3	5921	* \| \| \|Thus, it needs two 32-bit registers to store a security key.
sahilmgandhi	18:6a4db94011d3	5922	* \| \| \|The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
sahilmgandhi	18:6a4db94011d3	5923	*/
sahilmgandhi	18:6a4db94011d3	5924	__IO uint32_t TDES0_KEY3L;
sahilmgandhi	18:6a4db94011d3	5925
sahilmgandhi	18:6a4db94011d3	5926	/**
sahilmgandhi	18:6a4db94011d3	5927	* TDES0_IVH
sahilmgandhi	18:6a4db94011d3	5928	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5929	* Offset: 0x220 TDES/DES Initial Vector High Word Register for Channel 0
sahilmgandhi	18:6a4db94011d3	5930	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5931	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5932	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5933	* \|[0:31] \|IVH_IVL \|TDES/DES Initial Vector High/Low Word
sahilmgandhi	18:6a4db94011d3	5934	* \| \| \|Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode.
sahilmgandhi	18:6a4db94011d3	5935	* \| \| \|IV is Nonce counter for TDES/DES engine in CTR mode.
sahilmgandhi	18:6a4db94011d3	5936	*/
sahilmgandhi	18:6a4db94011d3	5937	__IO uint32_t TDES0_IVH;
sahilmgandhi	18:6a4db94011d3	5938
sahilmgandhi	18:6a4db94011d3	5939	/**
sahilmgandhi	18:6a4db94011d3	5940	* TDES0_IVL
sahilmgandhi	18:6a4db94011d3	5941	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5942	* Offset: 0x224 TDES/DES Initial Vector Low Word Register for Channel 0
sahilmgandhi	18:6a4db94011d3	5943	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5944	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5945	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5946	* \|[0:31] \|IVH_IVL \|TDES/DES Initial Vector High/Low Word
sahilmgandhi	18:6a4db94011d3	5947	* \| \| \|Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode.
sahilmgandhi	18:6a4db94011d3	5948	* \| \| \|IV is Nonce counter for TDES/DES engine in CTR mode.
sahilmgandhi	18:6a4db94011d3	5949	*/
sahilmgandhi	18:6a4db94011d3	5950	__IO uint32_t TDES0_IVL;
sahilmgandhi	18:6a4db94011d3	5951
sahilmgandhi	18:6a4db94011d3	5952	/**
sahilmgandhi	18:6a4db94011d3	5953	* TDES0_SADDR
sahilmgandhi	18:6a4db94011d3	5954	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5955	* Offset: 0x228 TDES/DES DMA Source Address Register for Channel 0
sahilmgandhi	18:6a4db94011d3	5956	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5957	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5958	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5959	* \|[0:31] \|SADDR \|TDES/DES DMA Source Address
sahilmgandhi	18:6a4db94011d3	5960	* \| \| \|The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
sahilmgandhi	18:6a4db94011d3	5961	* \| \| \|The TDES_SADR keeps the source address of the data buffer where the source text is stored.
sahilmgandhi	18:6a4db94011d3	5962	* \| \| \|Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation.
sahilmgandhi	18:6a4db94011d3	5963	* \| \| \|The start of source address should be located at word boundary.
sahilmgandhi	18:6a4db94011d3	5964	* \| \| \|In other words, bit 1 and 0 of TDES_SADR are ignored.
sahilmgandhi	18:6a4db94011d3	5965	* \| \| \|TDES_SADR can be read and written.
sahilmgandhi	18:6a4db94011d3	5966	* \| \| \|Writing to TDES_SADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
sahilmgandhi	18:6a4db94011d3	5967	* \| \| \|But the value of TDES_SADR will be updated later on.
sahilmgandhi	18:6a4db94011d3	5968	* \| \| \|Consequently, software can prepare the DMA source address for the next TDES/DES operation.
sahilmgandhi	18:6a4db94011d3	5969	* \| \| \|In DMA mode, software can update the next TDES_SADR before triggering START.
sahilmgandhi	18:6a4db94011d3	5970	* \| \| \|TDES_SADR and TDES_DADR can be the same in the value.
sahilmgandhi	18:6a4db94011d3	5971	*/
sahilmgandhi	18:6a4db94011d3	5972	__IO uint32_t TDES0_SADDR;
sahilmgandhi	18:6a4db94011d3	5973
sahilmgandhi	18:6a4db94011d3	5974	/**
sahilmgandhi	18:6a4db94011d3	5975	* TDES0_DADDR
sahilmgandhi	18:6a4db94011d3	5976	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5977	* Offset: 0x22C TDES/DES DMA Destination Address Register for Channel 0
sahilmgandhi	18:6a4db94011d3	5978	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	5979	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	5980	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	5981	* \|[0:31] \|DADDR \|TDES/DES DMA Destination Address
sahilmgandhi	18:6a4db94011d3	5982	* \| \| \|The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO.
sahilmgandhi	18:6a4db94011d3	5983	* \| \| \|The TDES_DADR keeps the destination address of the data buffer where the engine output's text will be stored.
sahilmgandhi	18:6a4db94011d3	5984	* \| \| \|Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished.
sahilmgandhi	18:6a4db94011d3	5985	* \| \| \|The start of destination address should be located at word boundary.
sahilmgandhi	18:6a4db94011d3	5986	* \| \| \|In other words, bit 1 and 0 of TDES_DADR are ignored.
sahilmgandhi	18:6a4db94011d3	5987	* \| \| \|TDES_DADR can be read and written.
sahilmgandhi	18:6a4db94011d3	5988	* \| \| \|Writing to TDES_DADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
sahilmgandhi	18:6a4db94011d3	5989	* \| \| \|But the value of TDES_DADR will be updated later on.
sahilmgandhi	18:6a4db94011d3	5990	* \| \| \|Consequently, software can prepare the destination address for the next TDES/DES operation.
sahilmgandhi	18:6a4db94011d3	5991	* \| \| \|In DMA mode, software can update the next TDES_DADR before triggering START.
sahilmgandhi	18:6a4db94011d3	5992	* \| \| \|TDES_SADR and TDES_DADR can be the same in the value.
sahilmgandhi	18:6a4db94011d3	5993	*/
sahilmgandhi	18:6a4db94011d3	5994	__IO uint32_t TDES0_DADDR;
sahilmgandhi	18:6a4db94011d3	5995
sahilmgandhi	18:6a4db94011d3	5996	/**
sahilmgandhi	18:6a4db94011d3	5997	* TDES0_CNT
sahilmgandhi	18:6a4db94011d3	5998	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	5999	* Offset: 0x230 TDES/DES Byte Count Register for Channel 0
sahilmgandhi	18:6a4db94011d3	6000	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6001	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6002	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6003	* \|[0:31] \|CNT \|TDES/DES Byte Count
sahilmgandhi	18:6a4db94011d3	6004	* \| \| \|The TDES_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode.
sahilmgandhi	18:6a4db94011d3	6005	* \| \| \|The TDES_CNT is 32-bit and the maximum of byte count is 4G bytes.
sahilmgandhi	18:6a4db94011d3	6006	* \| \| \|TDES_CNT can be read and written.
sahilmgandhi	18:6a4db94011d3	6007	* \| \| \|Writing to TDES_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
sahilmgandhi	18:6a4db94011d3	6008	* \| \| \|But the value of TDES_CNT will be updated later on.
sahilmgandhi	18:6a4db94011d3	6009	* \| \| \|Consequently, software can prepare the byte count of data for the next TDES /DES operation.
sahilmgandhi	18:6a4db94011d3	6010	* \| \| \|In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, TDES_CNT must be set as byte count for the last block of data before feeding in the last block of data.
sahilmgandhi	18:6a4db94011d3	6011	*/
sahilmgandhi	18:6a4db94011d3	6012	__IO uint32_t TDES0_CNT;
sahilmgandhi	18:6a4db94011d3	6013
sahilmgandhi	18:6a4db94011d3	6014	/**
sahilmgandhi	18:6a4db94011d3	6015	* TDES_DATIN
sahilmgandhi	18:6a4db94011d3	6016	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6017	* Offset: 0x234 TDES/DES Engine Input data Word Register
sahilmgandhi	18:6a4db94011d3	6018	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6019	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6020	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6021	* \|[0:31] \|DATIN \|TDES/DES Engine Input Port
sahilmgandhi	18:6a4db94011d3	6022	* \| \| \|CPU feeds data to TDES/DES engine through this port by checking CRPT_TDES_STS.
sahilmgandhi	18:6a4db94011d3	6023	* \| \| \|Feed data as INBUFFULL is 0.
sahilmgandhi	18:6a4db94011d3	6024	*/
sahilmgandhi	18:6a4db94011d3	6025	__IO uint32_t TDES_DATIN;
sahilmgandhi	18:6a4db94011d3	6026
sahilmgandhi	18:6a4db94011d3	6027	/**
sahilmgandhi	18:6a4db94011d3	6028	* TDES_DATOUT
sahilmgandhi	18:6a4db94011d3	6029	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6030	* Offset: 0x238 TDES/DES Engine Output data Word Register
sahilmgandhi	18:6a4db94011d3	6031	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6032	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6033	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6034	* \|[0:31] \|DATOUT \|TDES/DES Engine Output Port
sahilmgandhi	18:6a4db94011d3	6035	* \| \| \|CPU gets result from the TDES/DES engine through this port by checking CRPT_TDES_STS.
sahilmgandhi	18:6a4db94011d3	6036	* \| \| \|Get data as OUTBUFEMPTY is 0.
sahilmgandhi	18:6a4db94011d3	6037	*/
sahilmgandhi	18:6a4db94011d3	6038	__I uint32_t TDES_DATOUT;
sahilmgandhi	18:6a4db94011d3	6039	uint32_t RESERVE2[3];
sahilmgandhi	18:6a4db94011d3	6040
sahilmgandhi	18:6a4db94011d3	6041
sahilmgandhi	18:6a4db94011d3	6042	/**
sahilmgandhi	18:6a4db94011d3	6043	* TDES1_KEY1H
sahilmgandhi	18:6a4db94011d3	6044	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6045	* Offset: 0x248 TDES/DES Key 1 High Word Register for Channel 1
sahilmgandhi	18:6a4db94011d3	6046	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6047	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6048	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6049	* \|[0:31] \|KEYH_KEYL \|TDES/DES Key X High/Low Word
sahilmgandhi	18:6a4db94011d3	6050	* \| \| \|The key registers for TDES/DES algorithm calculation
sahilmgandhi	18:6a4db94011d3	6051	* \| \| \|The security key for the TDES/DES accelerator is 64 bits.
sahilmgandhi	18:6a4db94011d3	6052	* \| \| \|Thus, it needs two 32-bit registers to store a security key.
sahilmgandhi	18:6a4db94011d3	6053	* \| \| \|The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
sahilmgandhi	18:6a4db94011d3	6054	*/
sahilmgandhi	18:6a4db94011d3	6055	__IO uint32_t TDES1_KEY1H;
sahilmgandhi	18:6a4db94011d3	6056
sahilmgandhi	18:6a4db94011d3	6057	/**
sahilmgandhi	18:6a4db94011d3	6058	* TDES1_KEY1L
sahilmgandhi	18:6a4db94011d3	6059	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6060	* Offset: 0x24C TDES/DES Key 1 Low Word Register for Channel 1
sahilmgandhi	18:6a4db94011d3	6061	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6062	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6063	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6064	* \|[0:31] \|KEYH_KEYL \|TDES/DES Key X High/Low Word
sahilmgandhi	18:6a4db94011d3	6065	* \| \| \|The key registers for TDES/DES algorithm calculation
sahilmgandhi	18:6a4db94011d3	6066	* \| \| \|The security key for the TDES/DES accelerator is 64 bits.
sahilmgandhi	18:6a4db94011d3	6067	* \| \| \|Thus, it needs two 32-bit registers to store a security key.
sahilmgandhi	18:6a4db94011d3	6068	* \| \| \|The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
sahilmgandhi	18:6a4db94011d3	6069	*/
sahilmgandhi	18:6a4db94011d3	6070	__IO uint32_t TDES1_KEY1L;
sahilmgandhi	18:6a4db94011d3	6071
sahilmgandhi	18:6a4db94011d3	6072	/**
sahilmgandhi	18:6a4db94011d3	6073	* TDES1_KEY2H
sahilmgandhi	18:6a4db94011d3	6074	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6075	* Offset: 0x250 TDES Key 2 High Word Register for Channel 1
sahilmgandhi	18:6a4db94011d3	6076	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6077	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6078	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6079	* \|[0:31] \|KEYH_KEYL \|TDES/DES Key X High/Low Word
sahilmgandhi	18:6a4db94011d3	6080	* \| \| \|The key registers for TDES/DES algorithm calculation
sahilmgandhi	18:6a4db94011d3	6081	* \| \| \|The security key for the TDES/DES accelerator is 64 bits.
sahilmgandhi	18:6a4db94011d3	6082	* \| \| \|Thus, it needs two 32-bit registers to store a security key.
sahilmgandhi	18:6a4db94011d3	6083	* \| \| \|The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
sahilmgandhi	18:6a4db94011d3	6084	*/
sahilmgandhi	18:6a4db94011d3	6085	__IO uint32_t TDES1_KEY2H;
sahilmgandhi	18:6a4db94011d3	6086
sahilmgandhi	18:6a4db94011d3	6087	/**
sahilmgandhi	18:6a4db94011d3	6088	* TDES1_KEY2L
sahilmgandhi	18:6a4db94011d3	6089	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6090	* Offset: 0x254 TDES Key 2 Low Word Register for Channel 1
sahilmgandhi	18:6a4db94011d3	6091	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6092	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6093	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6094	* \|[0:31] \|KEYH_KEYL \|TDES/DES Key X High/Low Word
sahilmgandhi	18:6a4db94011d3	6095	* \| \| \|The key registers for TDES/DES algorithm calculation
sahilmgandhi	18:6a4db94011d3	6096	* \| \| \|The security key for the TDES/DES accelerator is 64 bits.
sahilmgandhi	18:6a4db94011d3	6097	* \| \| \|Thus, it needs two 32-bit registers to store a security key.
sahilmgandhi	18:6a4db94011d3	6098	* \| \| \|The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
sahilmgandhi	18:6a4db94011d3	6099	*/
sahilmgandhi	18:6a4db94011d3	6100	__IO uint32_t TDES1_KEY2L;
sahilmgandhi	18:6a4db94011d3	6101
sahilmgandhi	18:6a4db94011d3	6102	/**
sahilmgandhi	18:6a4db94011d3	6103	* TDES1_KEY3H
sahilmgandhi	18:6a4db94011d3	6104	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6105	* Offset: 0x258 TDES Key 3 High Word Register for Channel 1
sahilmgandhi	18:6a4db94011d3	6106	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6107	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6108	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6109	* \|[0:31] \|KEYH_KEYL \|TDES/DES Key X High/Low Word
sahilmgandhi	18:6a4db94011d3	6110	* \| \| \|The key registers for TDES/DES algorithm calculation
sahilmgandhi	18:6a4db94011d3	6111	* \| \| \|The security key for the TDES/DES accelerator is 64 bits.
sahilmgandhi	18:6a4db94011d3	6112	* \| \| \|Thus, it needs two 32-bit registers to store a security key.
sahilmgandhi	18:6a4db94011d3	6113	* \| \| \|The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
sahilmgandhi	18:6a4db94011d3	6114	*/
sahilmgandhi	18:6a4db94011d3	6115	__IO uint32_t TDES1_KEY3H;
sahilmgandhi	18:6a4db94011d3	6116
sahilmgandhi	18:6a4db94011d3	6117	/**
sahilmgandhi	18:6a4db94011d3	6118	* TDES1_KEY3L
sahilmgandhi	18:6a4db94011d3	6119	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6120	* Offset: 0x25C TDES Key 3 Low Word Register for Channel 1
sahilmgandhi	18:6a4db94011d3	6121	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6122	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6123	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6124	* \|[0:31] \|KEYH_KEYL \|TDES/DES Key X High/Low Word
sahilmgandhi	18:6a4db94011d3	6125	* \| \| \|The key registers for TDES/DES algorithm calculation
sahilmgandhi	18:6a4db94011d3	6126	* \| \| \|The security key for the TDES/DES accelerator is 64 bits.
sahilmgandhi	18:6a4db94011d3	6127	* \| \| \|Thus, it needs two 32-bit registers to store a security key.
sahilmgandhi	18:6a4db94011d3	6128	* \| \| \|The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
sahilmgandhi	18:6a4db94011d3	6129	*/
sahilmgandhi	18:6a4db94011d3	6130	__IO uint32_t TDES1_KEY3L;
sahilmgandhi	18:6a4db94011d3	6131
sahilmgandhi	18:6a4db94011d3	6132	/**
sahilmgandhi	18:6a4db94011d3	6133	* TDES1_IVH
sahilmgandhi	18:6a4db94011d3	6134	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6135	* Offset: 0x260 TDES/DES Initial Vector High Word Register for Channel 1
sahilmgandhi	18:6a4db94011d3	6136	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6137	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6138	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6139	* \|[0:31] \|IVH_IVL \|TDES/DES Initial Vector High/Low Word
sahilmgandhi	18:6a4db94011d3	6140	* \| \| \|Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode.
sahilmgandhi	18:6a4db94011d3	6141	* \| \| \|IV is Nonce counter for TDES/DES engine in CTR mode.
sahilmgandhi	18:6a4db94011d3	6142	*/
sahilmgandhi	18:6a4db94011d3	6143	__IO uint32_t TDES1_IVH;
sahilmgandhi	18:6a4db94011d3	6144
sahilmgandhi	18:6a4db94011d3	6145	/**
sahilmgandhi	18:6a4db94011d3	6146	* TDES1_IVL
sahilmgandhi	18:6a4db94011d3	6147	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6148	* Offset: 0x264 TDES/DES Initial Vector Low Word Register for Channel 1
sahilmgandhi	18:6a4db94011d3	6149	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6150	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6151	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6152	* \|[0:31] \|IVH_IVL \|TDES/DES Initial Vector High/Low Word
sahilmgandhi	18:6a4db94011d3	6153	* \| \| \|Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode.
sahilmgandhi	18:6a4db94011d3	6154	* \| \| \|IV is Nonce counter for TDES/DES engine in CTR mode.
sahilmgandhi	18:6a4db94011d3	6155	*/
sahilmgandhi	18:6a4db94011d3	6156	__IO uint32_t TDES1_IVL;
sahilmgandhi	18:6a4db94011d3	6157
sahilmgandhi	18:6a4db94011d3	6158	/**
sahilmgandhi	18:6a4db94011d3	6159	* TDES1_SADDR
sahilmgandhi	18:6a4db94011d3	6160	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6161	* Offset: 0x268 TDES/DES DMA Source Address Register for Channel 1
sahilmgandhi	18:6a4db94011d3	6162	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6163	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6164	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6165	* \|[0:31] \|SADDR \|TDES/DES DMA Source Address
sahilmgandhi	18:6a4db94011d3	6166	* \| \| \|The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
sahilmgandhi	18:6a4db94011d3	6167	* \| \| \|The TDES_SADR keeps the source address of the data buffer where the source text is stored.
sahilmgandhi	18:6a4db94011d3	6168	* \| \| \|Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation.
sahilmgandhi	18:6a4db94011d3	6169	* \| \| \|The start of source address should be located at word boundary.
sahilmgandhi	18:6a4db94011d3	6170	* \| \| \|In other words, bit 1 and 0 of TDES_SADR are ignored.
sahilmgandhi	18:6a4db94011d3	6171	* \| \| \|TDES_SADR can be read and written.
sahilmgandhi	18:6a4db94011d3	6172	* \| \| \|Writing to TDES_SADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
sahilmgandhi	18:6a4db94011d3	6173	* \| \| \|But the value of TDES_SADR will be updated later on.
sahilmgandhi	18:6a4db94011d3	6174	* \| \| \|Consequently, software can prepare the DMA source address for the next TDES/DES operation.
sahilmgandhi	18:6a4db94011d3	6175	* \| \| \|In DMA mode, software can update the next TDES_SADR before triggering START.
sahilmgandhi	18:6a4db94011d3	6176	* \| \| \|TDES_SADR and TDES_DADR can be the same in the value.
sahilmgandhi	18:6a4db94011d3	6177	*/
sahilmgandhi	18:6a4db94011d3	6178	__IO uint32_t TDES1_SADDR;
sahilmgandhi	18:6a4db94011d3	6179
sahilmgandhi	18:6a4db94011d3	6180	/**
sahilmgandhi	18:6a4db94011d3	6181	* TDES1_DADDR
sahilmgandhi	18:6a4db94011d3	6182	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6183	* Offset: 0x26C TDES/DES DMA Destination Address Register for Channel 1
sahilmgandhi	18:6a4db94011d3	6184	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6185	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6186	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6187	* \|[0:31] \|DADDR \|TDES/DES DMA Destination Address
sahilmgandhi	18:6a4db94011d3	6188	* \| \| \|The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO.
sahilmgandhi	18:6a4db94011d3	6189	* \| \| \|The TDES_DADR keeps the destination address of the data buffer where the engine output's text will be stored.
sahilmgandhi	18:6a4db94011d3	6190	* \| \| \|Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished.
sahilmgandhi	18:6a4db94011d3	6191	* \| \| \|The start of destination address should be located at word boundary.
sahilmgandhi	18:6a4db94011d3	6192	* \| \| \|In other words, bit 1 and 0 of TDES_DADR are ignored.
sahilmgandhi	18:6a4db94011d3	6193	* \| \| \|TDES_DADR can be read and written.
sahilmgandhi	18:6a4db94011d3	6194	* \| \| \|Writing to TDES_DADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
sahilmgandhi	18:6a4db94011d3	6195	* \| \| \|But the value of TDES_DADR will be updated later on.
sahilmgandhi	18:6a4db94011d3	6196	* \| \| \|Consequently, software can prepare the destination address for the next TDES/DES operation.
sahilmgandhi	18:6a4db94011d3	6197	* \| \| \|In DMA mode, software can update the next TDES_DADR before triggering START.
sahilmgandhi	18:6a4db94011d3	6198	* \| \| \|TDES_SADR and TDES_DADR can be the same in the value.
sahilmgandhi	18:6a4db94011d3	6199	*/
sahilmgandhi	18:6a4db94011d3	6200	__IO uint32_t TDES1_DADDR;
sahilmgandhi	18:6a4db94011d3	6201
sahilmgandhi	18:6a4db94011d3	6202	/**
sahilmgandhi	18:6a4db94011d3	6203	* TDES1_CNT
sahilmgandhi	18:6a4db94011d3	6204	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6205	* Offset: 0x270 TDES/DES Byte Count Register for Channel 1
sahilmgandhi	18:6a4db94011d3	6206	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6207	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6208	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6209	* \|[0:31] \|CNT \|TDES/DES Byte Count
sahilmgandhi	18:6a4db94011d3	6210	* \| \| \|The TDES_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode.
sahilmgandhi	18:6a4db94011d3	6211	* \| \| \|The TDES_CNT is 32-bit and the maximum of byte count is 4G bytes.
sahilmgandhi	18:6a4db94011d3	6212	* \| \| \|TDES_CNT can be read and written.
sahilmgandhi	18:6a4db94011d3	6213	* \| \| \|Writing to TDES_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
sahilmgandhi	18:6a4db94011d3	6214	* \| \| \|But the value of TDES_CNT will be updated later on.
sahilmgandhi	18:6a4db94011d3	6215	* \| \| \|Consequently, software can prepare the byte count of data for the next TDES /DES operation.
sahilmgandhi	18:6a4db94011d3	6216	* \| \| \|In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, TDES_CNT must be set as byte count for the last block of data before feeding in the last block of data.
sahilmgandhi	18:6a4db94011d3	6217	*/
sahilmgandhi	18:6a4db94011d3	6218	__IO uint32_t TDES1_CNT;
sahilmgandhi	18:6a4db94011d3	6219	uint32_t RESERVE3[5];
sahilmgandhi	18:6a4db94011d3	6220
sahilmgandhi	18:6a4db94011d3	6221
sahilmgandhi	18:6a4db94011d3	6222	/**
sahilmgandhi	18:6a4db94011d3	6223	* TDES2_KEY1H
sahilmgandhi	18:6a4db94011d3	6224	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6225	* Offset: 0x288 TDES/DES Key 1 High Word Register for Channel 2
sahilmgandhi	18:6a4db94011d3	6226	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6227	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6228	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6229	* \|[0:31] \|KEYH_KEYL \|TDES/DES Key X High/Low Word
sahilmgandhi	18:6a4db94011d3	6230	* \| \| \|The key registers for TDES/DES algorithm calculation
sahilmgandhi	18:6a4db94011d3	6231	* \| \| \|The security key for the TDES/DES accelerator is 64 bits.
sahilmgandhi	18:6a4db94011d3	6232	* \| \| \|Thus, it needs two 32-bit registers to store a security key.
sahilmgandhi	18:6a4db94011d3	6233	* \| \| \|The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
sahilmgandhi	18:6a4db94011d3	6234	*/
sahilmgandhi	18:6a4db94011d3	6235	__IO uint32_t TDES2_KEY1H;
sahilmgandhi	18:6a4db94011d3	6236
sahilmgandhi	18:6a4db94011d3	6237	/**
sahilmgandhi	18:6a4db94011d3	6238	* TDES2_KEY1L
sahilmgandhi	18:6a4db94011d3	6239	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6240	* Offset: 0x28C TDES/DES Key 1 Low Word Register for Channel 2
sahilmgandhi	18:6a4db94011d3	6241	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6242	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6243	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6244	* \|[0:31] \|KEYH_KEYL \|TDES/DES Key X High/Low Word
sahilmgandhi	18:6a4db94011d3	6245	* \| \| \|The key registers for TDES/DES algorithm calculation
sahilmgandhi	18:6a4db94011d3	6246	* \| \| \|The security key for the TDES/DES accelerator is 64 bits.
sahilmgandhi	18:6a4db94011d3	6247	* \| \| \|Thus, it needs two 32-bit registers to store a security key.
sahilmgandhi	18:6a4db94011d3	6248	* \| \| \|The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
sahilmgandhi	18:6a4db94011d3	6249	*/
sahilmgandhi	18:6a4db94011d3	6250	__IO uint32_t TDES2_KEY1L;
sahilmgandhi	18:6a4db94011d3	6251
sahilmgandhi	18:6a4db94011d3	6252	/**
sahilmgandhi	18:6a4db94011d3	6253	* TDES2_KEY2H
sahilmgandhi	18:6a4db94011d3	6254	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6255	* Offset: 0x290 TDES Key 2 High Word Register for Channel 2
sahilmgandhi	18:6a4db94011d3	6256	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6257	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6258	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6259	* \|[0:31] \|KEYH_KEYL \|TDES/DES Key X High/Low Word
sahilmgandhi	18:6a4db94011d3	6260	* \| \| \|The key registers for TDES/DES algorithm calculation
sahilmgandhi	18:6a4db94011d3	6261	* \| \| \|The security key for the TDES/DES accelerator is 64 bits.
sahilmgandhi	18:6a4db94011d3	6262	* \| \| \|Thus, it needs two 32-bit registers to store a security key.
sahilmgandhi	18:6a4db94011d3	6263	* \| \| \|The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
sahilmgandhi	18:6a4db94011d3	6264	*/
sahilmgandhi	18:6a4db94011d3	6265	__IO uint32_t TDES2_KEY2H;
sahilmgandhi	18:6a4db94011d3	6266
sahilmgandhi	18:6a4db94011d3	6267	/**
sahilmgandhi	18:6a4db94011d3	6268	* TDES2_KEY2L
sahilmgandhi	18:6a4db94011d3	6269	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6270	* Offset: 0x294 TDES Key 2 Low Word Register for Channel 2
sahilmgandhi	18:6a4db94011d3	6271	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6272	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6273	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6274	* \|[0:31] \|KEYH_KEYL \|TDES/DES Key X High/Low Word
sahilmgandhi	18:6a4db94011d3	6275	* \| \| \|The key registers for TDES/DES algorithm calculation
sahilmgandhi	18:6a4db94011d3	6276	* \| \| \|The security key for the TDES/DES accelerator is 64 bits.
sahilmgandhi	18:6a4db94011d3	6277	* \| \| \|Thus, it needs two 32-bit registers to store a security key.
sahilmgandhi	18:6a4db94011d3	6278	* \| \| \|The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
sahilmgandhi	18:6a4db94011d3	6279	*/
sahilmgandhi	18:6a4db94011d3	6280	__IO uint32_t TDES2_KEY2L;
sahilmgandhi	18:6a4db94011d3	6281
sahilmgandhi	18:6a4db94011d3	6282	/**
sahilmgandhi	18:6a4db94011d3	6283	* TDES2_KEY3H
sahilmgandhi	18:6a4db94011d3	6284	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6285	* Offset: 0x298 TDES Key 3 High Word Register for Channel 2
sahilmgandhi	18:6a4db94011d3	6286	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6287	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6288	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6289	* \|[0:31] \|KEYH_KEYL \|TDES/DES Key X High/Low Word
sahilmgandhi	18:6a4db94011d3	6290	* \| \| \|The key registers for TDES/DES algorithm calculation
sahilmgandhi	18:6a4db94011d3	6291	* \| \| \|The security key for the TDES/DES accelerator is 64 bits.
sahilmgandhi	18:6a4db94011d3	6292	* \| \| \|Thus, it needs two 32-bit registers to store a security key.
sahilmgandhi	18:6a4db94011d3	6293	* \| \| \|The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
sahilmgandhi	18:6a4db94011d3	6294	*/
sahilmgandhi	18:6a4db94011d3	6295	__IO uint32_t TDES2_KEY3H;
sahilmgandhi	18:6a4db94011d3	6296
sahilmgandhi	18:6a4db94011d3	6297	/**
sahilmgandhi	18:6a4db94011d3	6298	* TDES2_KEY3L
sahilmgandhi	18:6a4db94011d3	6299	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6300	* Offset: 0x29C TDES Key 3 Low Word Register for Channel 2
sahilmgandhi	18:6a4db94011d3	6301	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6302	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6303	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6304	* \|[0:31] \|KEYH_KEYL \|TDES/DES Key X High/Low Word
sahilmgandhi	18:6a4db94011d3	6305	* \| \| \|The key registers for TDES/DES algorithm calculation
sahilmgandhi	18:6a4db94011d3	6306	* \| \| \|The security key for the TDES/DES accelerator is 64 bits.
sahilmgandhi	18:6a4db94011d3	6307	* \| \| \|Thus, it needs two 32-bit registers to store a security key.
sahilmgandhi	18:6a4db94011d3	6308	* \| \| \|The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
sahilmgandhi	18:6a4db94011d3	6309	*/
sahilmgandhi	18:6a4db94011d3	6310	__IO uint32_t TDES2_KEY3L;
sahilmgandhi	18:6a4db94011d3	6311
sahilmgandhi	18:6a4db94011d3	6312	/**
sahilmgandhi	18:6a4db94011d3	6313	* TDES2_IVH
sahilmgandhi	18:6a4db94011d3	6314	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6315	* Offset: 0x2A0 TDES/DES Initial Vector High Word Register for Channel 2
sahilmgandhi	18:6a4db94011d3	6316	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6317	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6318	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6319	* \|[0:31] \|IVH_IVL \|TDES/DES Initial Vector High/Low Word
sahilmgandhi	18:6a4db94011d3	6320	* \| \| \|Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode.
sahilmgandhi	18:6a4db94011d3	6321	* \| \| \|IV is Nonce counter for TDES/DES engine in CTR mode.
sahilmgandhi	18:6a4db94011d3	6322	*/
sahilmgandhi	18:6a4db94011d3	6323	__IO uint32_t TDES2_IVH;
sahilmgandhi	18:6a4db94011d3	6324
sahilmgandhi	18:6a4db94011d3	6325	/**
sahilmgandhi	18:6a4db94011d3	6326	* TDES2_IVL
sahilmgandhi	18:6a4db94011d3	6327	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6328	* Offset: 0x2A4 TDES/DES Initial Vector Low Word Register for Channel 2
sahilmgandhi	18:6a4db94011d3	6329	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6330	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6331	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6332	* \|[0:31] \|IVH_IVL \|TDES/DES Initial Vector High/Low Word
sahilmgandhi	18:6a4db94011d3	6333	* \| \| \|Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode.
sahilmgandhi	18:6a4db94011d3	6334	* \| \| \|IV is Nonce counter for TDES/DES engine in CTR mode.
sahilmgandhi	18:6a4db94011d3	6335	*/
sahilmgandhi	18:6a4db94011d3	6336	__IO uint32_t TDES2_IVL;
sahilmgandhi	18:6a4db94011d3	6337
sahilmgandhi	18:6a4db94011d3	6338	/**
sahilmgandhi	18:6a4db94011d3	6339	* TDES2_SADDR
sahilmgandhi	18:6a4db94011d3	6340	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6341	* Offset: 0x2A8 TDES/DES DMA Source Address Register for Channel 2
sahilmgandhi	18:6a4db94011d3	6342	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6343	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6344	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6345	* \|[0:31] \|SADDR \|TDES/DES DMA Source Address
sahilmgandhi	18:6a4db94011d3	6346	* \| \| \|The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
sahilmgandhi	18:6a4db94011d3	6347	* \| \| \|The TDES_SADR keeps the source address of the data buffer where the source text is stored.
sahilmgandhi	18:6a4db94011d3	6348	* \| \| \|Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation.
sahilmgandhi	18:6a4db94011d3	6349	* \| \| \|The start of source address should be located at word boundary.
sahilmgandhi	18:6a4db94011d3	6350	* \| \| \|In other words, bit 1 and 0 of TDES_SADR are ignored.
sahilmgandhi	18:6a4db94011d3	6351	* \| \| \|TDES_SADR can be read and written.
sahilmgandhi	18:6a4db94011d3	6352	* \| \| \|Writing to TDES_SADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
sahilmgandhi	18:6a4db94011d3	6353	* \| \| \|But the value of TDES_SADR will be updated later on.
sahilmgandhi	18:6a4db94011d3	6354	* \| \| \|Consequently, software can prepare the DMA source address for the next TDES/DES operation.
sahilmgandhi	18:6a4db94011d3	6355	* \| \| \|In DMA mode, software can update the next TDES_SADR before triggering START.
sahilmgandhi	18:6a4db94011d3	6356	* \| \| \|TDES_SADR and TDES_DADR can be the same in the value.
sahilmgandhi	18:6a4db94011d3	6357	*/
sahilmgandhi	18:6a4db94011d3	6358	__IO uint32_t TDES2_SADDR;
sahilmgandhi	18:6a4db94011d3	6359
sahilmgandhi	18:6a4db94011d3	6360	/**
sahilmgandhi	18:6a4db94011d3	6361	* TDES2_DADDR
sahilmgandhi	18:6a4db94011d3	6362	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6363	* Offset: 0x2AC TDES/DES DMA Destination Address Register for Channel 2
sahilmgandhi	18:6a4db94011d3	6364	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6365	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6366	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6367	* \|[0:31] \|DADDR \|TDES/DES DMA Destination Address
sahilmgandhi	18:6a4db94011d3	6368	* \| \| \|The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO.
sahilmgandhi	18:6a4db94011d3	6369	* \| \| \|The TDES_DADR keeps the destination address of the data buffer where the engine output's text will be stored.
sahilmgandhi	18:6a4db94011d3	6370	* \| \| \|Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished.
sahilmgandhi	18:6a4db94011d3	6371	* \| \| \|The start of destination address should be located at word boundary.
sahilmgandhi	18:6a4db94011d3	6372	* \| \| \|In other words, bit 1 and 0 of TDES_DADR are ignored.
sahilmgandhi	18:6a4db94011d3	6373	* \| \| \|TDES_DADR can be read and written.
sahilmgandhi	18:6a4db94011d3	6374	* \| \| \|Writing to TDES_DADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
sahilmgandhi	18:6a4db94011d3	6375	* \| \| \|But the value of TDES_DADR will be updated later on.
sahilmgandhi	18:6a4db94011d3	6376	* \| \| \|Consequently, software can prepare the destination address for the next TDES/DES operation.
sahilmgandhi	18:6a4db94011d3	6377	* \| \| \|In DMA mode, software can update the next TDES_DADR before triggering START.
sahilmgandhi	18:6a4db94011d3	6378	* \| \| \|TDES_SADR and TDES_DADR can be the same in the value.
sahilmgandhi	18:6a4db94011d3	6379	*/
sahilmgandhi	18:6a4db94011d3	6380	__IO uint32_t TDES2_DADDR;
sahilmgandhi	18:6a4db94011d3	6381
sahilmgandhi	18:6a4db94011d3	6382	/**
sahilmgandhi	18:6a4db94011d3	6383	* TDES2_CNT
sahilmgandhi	18:6a4db94011d3	6384	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6385	* Offset: 0x2B0 TDES/DES Byte Count Register for Channel 2
sahilmgandhi	18:6a4db94011d3	6386	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6387	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6388	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6389	* \|[0:31] \|CNT \|TDES/DES Byte Count
sahilmgandhi	18:6a4db94011d3	6390	* \| \| \|The TDES_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode.
sahilmgandhi	18:6a4db94011d3	6391	* \| \| \|The TDES_CNT is 32-bit and the maximum of byte count is 4G bytes.
sahilmgandhi	18:6a4db94011d3	6392	* \| \| \|TDES_CNT can be read and written.
sahilmgandhi	18:6a4db94011d3	6393	* \| \| \|Writing to TDES_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
sahilmgandhi	18:6a4db94011d3	6394	* \| \| \|But the value of TDES_CNT will be updated later on.
sahilmgandhi	18:6a4db94011d3	6395	* \| \| \|Consequently, software can prepare the byte count of data for the next TDES /DES operation.
sahilmgandhi	18:6a4db94011d3	6396	* \| \| \|In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, TDES_CNT must be set as byte count for the last block of data before feeding in the last block of data.
sahilmgandhi	18:6a4db94011d3	6397	*/
sahilmgandhi	18:6a4db94011d3	6398	__IO uint32_t TDES2_CNT;
sahilmgandhi	18:6a4db94011d3	6399	uint32_t RESERVE4[5];
sahilmgandhi	18:6a4db94011d3	6400
sahilmgandhi	18:6a4db94011d3	6401
sahilmgandhi	18:6a4db94011d3	6402	/**
sahilmgandhi	18:6a4db94011d3	6403	* TDES3_KEY1H
sahilmgandhi	18:6a4db94011d3	6404	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6405	* Offset: 0x2C8 TDES/DES Key 1 High Word Register for Channel 3
sahilmgandhi	18:6a4db94011d3	6406	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6407	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6408	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6409	* \|[0:31] \|KEYH_KEYL \|TDES/DES Key X High/Low Word
sahilmgandhi	18:6a4db94011d3	6410	* \| \| \|The key registers for TDES/DES algorithm calculation
sahilmgandhi	18:6a4db94011d3	6411	* \| \| \|The security key for the TDES/DES accelerator is 64 bits.
sahilmgandhi	18:6a4db94011d3	6412	* \| \| \|Thus, it needs two 32-bit registers to store a security key.
sahilmgandhi	18:6a4db94011d3	6413	* \| \| \|The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
sahilmgandhi	18:6a4db94011d3	6414	*/
sahilmgandhi	18:6a4db94011d3	6415	__IO uint32_t TDES3_KEY1H;
sahilmgandhi	18:6a4db94011d3	6416
sahilmgandhi	18:6a4db94011d3	6417	/**
sahilmgandhi	18:6a4db94011d3	6418	* TDES3_KEY1L
sahilmgandhi	18:6a4db94011d3	6419	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6420	* Offset: 0x2CC TDES/DES Key 1 Low Word Register for Channel 3
sahilmgandhi	18:6a4db94011d3	6421	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6422	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6423	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6424	* \|[0:31] \|KEYH_KEYL \|TDES/DES Key X High/Low Word
sahilmgandhi	18:6a4db94011d3	6425	* \| \| \|The key registers for TDES/DES algorithm calculation
sahilmgandhi	18:6a4db94011d3	6426	* \| \| \|The security key for the TDES/DES accelerator is 64 bits.
sahilmgandhi	18:6a4db94011d3	6427	* \| \| \|Thus, it needs two 32-bit registers to store a security key.
sahilmgandhi	18:6a4db94011d3	6428	* \| \| \|The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
sahilmgandhi	18:6a4db94011d3	6429	*/
sahilmgandhi	18:6a4db94011d3	6430	__IO uint32_t TDES3_KEY1L;
sahilmgandhi	18:6a4db94011d3	6431
sahilmgandhi	18:6a4db94011d3	6432	/**
sahilmgandhi	18:6a4db94011d3	6433	* TDES3_KEY2H
sahilmgandhi	18:6a4db94011d3	6434	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6435	* Offset: 0x2D0 TDES Key 2 High Word Register for Channel 3
sahilmgandhi	18:6a4db94011d3	6436	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6437	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6438	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6439	* \|[0:31] \|KEYH_KEYL \|TDES/DES Key X High/Low Word
sahilmgandhi	18:6a4db94011d3	6440	* \| \| \|The key registers for TDES/DES algorithm calculation
sahilmgandhi	18:6a4db94011d3	6441	* \| \| \|The security key for the TDES/DES accelerator is 64 bits.
sahilmgandhi	18:6a4db94011d3	6442	* \| \| \|Thus, it needs two 32-bit registers to store a security key.
sahilmgandhi	18:6a4db94011d3	6443	* \| \| \|The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
sahilmgandhi	18:6a4db94011d3	6444	*/
sahilmgandhi	18:6a4db94011d3	6445	__IO uint32_t TDES3_KEY2H;
sahilmgandhi	18:6a4db94011d3	6446
sahilmgandhi	18:6a4db94011d3	6447	/**
sahilmgandhi	18:6a4db94011d3	6448	* TDES3_KEY2L
sahilmgandhi	18:6a4db94011d3	6449	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6450	* Offset: 0x2D4 TDES Key 2 Low Word Register for Channel 3
sahilmgandhi	18:6a4db94011d3	6451	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6452	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6453	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6454	* \|[0:31] \|KEYH_KEYL \|TDES/DES Key X High/Low Word
sahilmgandhi	18:6a4db94011d3	6455	* \| \| \|The key registers for TDES/DES algorithm calculation
sahilmgandhi	18:6a4db94011d3	6456	* \| \| \|The security key for the TDES/DES accelerator is 64 bits.
sahilmgandhi	18:6a4db94011d3	6457	* \| \| \|Thus, it needs two 32-bit registers to store a security key.
sahilmgandhi	18:6a4db94011d3	6458	* \| \| \|The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
sahilmgandhi	18:6a4db94011d3	6459	*/
sahilmgandhi	18:6a4db94011d3	6460	__IO uint32_t TDES3_KEY2L;
sahilmgandhi	18:6a4db94011d3	6461
sahilmgandhi	18:6a4db94011d3	6462	/**
sahilmgandhi	18:6a4db94011d3	6463	* TDES3_KEY3H
sahilmgandhi	18:6a4db94011d3	6464	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6465	* Offset: 0x2D8 TDES Key 3 High Word Register for Channel 3
sahilmgandhi	18:6a4db94011d3	6466	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6467	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6468	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6469	* \|[0:31] \|KEYH_KEYL \|TDES/DES Key X High/Low Word
sahilmgandhi	18:6a4db94011d3	6470	* \| \| \|The key registers for TDES/DES algorithm calculation
sahilmgandhi	18:6a4db94011d3	6471	* \| \| \|The security key for the TDES/DES accelerator is 64 bits.
sahilmgandhi	18:6a4db94011d3	6472	* \| \| \|Thus, it needs two 32-bit registers to store a security key.
sahilmgandhi	18:6a4db94011d3	6473	* \| \| \|The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
sahilmgandhi	18:6a4db94011d3	6474	*/
sahilmgandhi	18:6a4db94011d3	6475	__IO uint32_t TDES3_KEY3H;
sahilmgandhi	18:6a4db94011d3	6476
sahilmgandhi	18:6a4db94011d3	6477	/**
sahilmgandhi	18:6a4db94011d3	6478	* TDES3_KEY3L
sahilmgandhi	18:6a4db94011d3	6479	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6480	* Offset: 0x2DC TDES Key 3 Low Word Register for Channel 3
sahilmgandhi	18:6a4db94011d3	6481	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6482	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6483	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6484	* \|[0:31] \|KEYH_KEYL \|TDES/DES Key X High/Low Word
sahilmgandhi	18:6a4db94011d3	6485	* \| \| \|The key registers for TDES/DES algorithm calculation
sahilmgandhi	18:6a4db94011d3	6486	* \| \| \|The security key for the TDES/DES accelerator is 64 bits.
sahilmgandhi	18:6a4db94011d3	6487	* \| \| \|Thus, it needs two 32-bit registers to store a security key.
sahilmgandhi	18:6a4db94011d3	6488	* \| \| \|The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
sahilmgandhi	18:6a4db94011d3	6489	*/
sahilmgandhi	18:6a4db94011d3	6490	__IO uint32_t TDES3_KEY3L;
sahilmgandhi	18:6a4db94011d3	6491
sahilmgandhi	18:6a4db94011d3	6492	/**
sahilmgandhi	18:6a4db94011d3	6493	* TDES3_IVH
sahilmgandhi	18:6a4db94011d3	6494	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6495	* Offset: 0x2E0 TDES/DES Initial Vector High Word Register for Channel 3
sahilmgandhi	18:6a4db94011d3	6496	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6497	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6498	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6499	* \|[0:31] \|IVH_IVL \|TDES/DES Initial Vector High/Low Word
sahilmgandhi	18:6a4db94011d3	6500	* \| \| \|Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode.
sahilmgandhi	18:6a4db94011d3	6501	* \| \| \|IV is Nonce counter for TDES/DES engine in CTR mode.
sahilmgandhi	18:6a4db94011d3	6502	*/
sahilmgandhi	18:6a4db94011d3	6503	__IO uint32_t TDES3_IVH;
sahilmgandhi	18:6a4db94011d3	6504
sahilmgandhi	18:6a4db94011d3	6505	/**
sahilmgandhi	18:6a4db94011d3	6506	* TDES3_IVL
sahilmgandhi	18:6a4db94011d3	6507	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6508	* Offset: 0x2E4 TDES/DES Initial Vector Low Word Register for Channel 3
sahilmgandhi	18:6a4db94011d3	6509	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6510	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6511	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6512	* \|[0:31] \|IVH_IVL \|TDES/DES Initial Vector High/Low Word
sahilmgandhi	18:6a4db94011d3	6513	* \| \| \|Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode.
sahilmgandhi	18:6a4db94011d3	6514	* \| \| \|IV is Nonce counter for TDES/DES engine in CTR mode.
sahilmgandhi	18:6a4db94011d3	6515	*/
sahilmgandhi	18:6a4db94011d3	6516	__IO uint32_t TDES3_IVL;
sahilmgandhi	18:6a4db94011d3	6517
sahilmgandhi	18:6a4db94011d3	6518	/**
sahilmgandhi	18:6a4db94011d3	6519	* TDES3_SADDR
sahilmgandhi	18:6a4db94011d3	6520	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6521	* Offset: 0x2E8 TDES/DES DMA Source Address Register for Channel 3
sahilmgandhi	18:6a4db94011d3	6522	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6523	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6524	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6525	* \|[0:31] \|SADDR \|TDES/DES DMA Source Address
sahilmgandhi	18:6a4db94011d3	6526	* \| \| \|The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
sahilmgandhi	18:6a4db94011d3	6527	* \| \| \|The TDES_SADR keeps the source address of the data buffer where the source text is stored.
sahilmgandhi	18:6a4db94011d3	6528	* \| \| \|Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation.
sahilmgandhi	18:6a4db94011d3	6529	* \| \| \|The start of source address should be located at word boundary.
sahilmgandhi	18:6a4db94011d3	6530	* \| \| \|In other words, bit 1 and 0 of TDES_SADR are ignored.
sahilmgandhi	18:6a4db94011d3	6531	* \| \| \|TDES_SADR can be read and written.
sahilmgandhi	18:6a4db94011d3	6532	* \| \| \|Writing to TDES_SADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
sahilmgandhi	18:6a4db94011d3	6533	* \| \| \|But the value of TDES_SADR will be updated later on.
sahilmgandhi	18:6a4db94011d3	6534	* \| \| \|Consequently, software can prepare the DMA source address for the next TDES/DES operation.
sahilmgandhi	18:6a4db94011d3	6535	* \| \| \|In DMA mode, software can update the next TDES_SADR before triggering START.
sahilmgandhi	18:6a4db94011d3	6536	* \| \| \|TDES_SADR and TDES_DADR can be the same in the value.
sahilmgandhi	18:6a4db94011d3	6537	*/
sahilmgandhi	18:6a4db94011d3	6538	__IO uint32_t TDES3_SADDR;
sahilmgandhi	18:6a4db94011d3	6539
sahilmgandhi	18:6a4db94011d3	6540	/**
sahilmgandhi	18:6a4db94011d3	6541	* TDES3_DADDR
sahilmgandhi	18:6a4db94011d3	6542	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6543	* Offset: 0x2EC TDES/DES DMA Destination Address Register for Channel 3
sahilmgandhi	18:6a4db94011d3	6544	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6545	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6546	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6547	* \|[0:31] \|DADDR \|TDES/DES DMA Destination Address
sahilmgandhi	18:6a4db94011d3	6548	* \| \| \|The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO.
sahilmgandhi	18:6a4db94011d3	6549	* \| \| \|The TDES_DADR keeps the destination address of the data buffer where the engine output's text will be stored.
sahilmgandhi	18:6a4db94011d3	6550	* \| \| \|Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished.
sahilmgandhi	18:6a4db94011d3	6551	* \| \| \|The start of destination address should be located at word boundary.
sahilmgandhi	18:6a4db94011d3	6552	* \| \| \|In other words, bit 1 and 0 of TDES_DADR are ignored.
sahilmgandhi	18:6a4db94011d3	6553	* \| \| \|TDES_DADR can be read and written.
sahilmgandhi	18:6a4db94011d3	6554	* \| \| \|Writing to TDES_DADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
sahilmgandhi	18:6a4db94011d3	6555	* \| \| \|But the value of TDES_DADR will be updated later on.
sahilmgandhi	18:6a4db94011d3	6556	* \| \| \|Consequently, software can prepare the destination address for the next TDES/DES operation.
sahilmgandhi	18:6a4db94011d3	6557	* \| \| \|In DMA mode, software can update the next TDES_DADR before triggering START.
sahilmgandhi	18:6a4db94011d3	6558	* \| \| \|TDES_SADR and TDES_DADR can be the same in the value.
sahilmgandhi	18:6a4db94011d3	6559	*/
sahilmgandhi	18:6a4db94011d3	6560	__IO uint32_t TDES3_DADDR;
sahilmgandhi	18:6a4db94011d3	6561
sahilmgandhi	18:6a4db94011d3	6562	/**
sahilmgandhi	18:6a4db94011d3	6563	* TDES3_CNT
sahilmgandhi	18:6a4db94011d3	6564	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6565	* Offset: 0x2F0 TDES/DES Byte Count Register for Channel 3
sahilmgandhi	18:6a4db94011d3	6566	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6567	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6568	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6569	* \|[0:31] \|CNT \|TDES/DES Byte Count
sahilmgandhi	18:6a4db94011d3	6570	* \| \| \|The TDES_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode.
sahilmgandhi	18:6a4db94011d3	6571	* \| \| \|The TDES_CNT is 32-bit and the maximum of byte count is 4G bytes.
sahilmgandhi	18:6a4db94011d3	6572	* \| \| \|TDES_CNT can be read and written.
sahilmgandhi	18:6a4db94011d3	6573	* \| \| \|Writing to TDES_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
sahilmgandhi	18:6a4db94011d3	6574	* \| \| \|But the value of TDES_CNT will be updated later on.
sahilmgandhi	18:6a4db94011d3	6575	* \| \| \|Consequently, software can prepare the byte count of data for the next TDES /DES operation.
sahilmgandhi	18:6a4db94011d3	6576	* \| \| \|In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, TDES_CNT must be set as byte count for the last block of data before feeding in the last block of data.
sahilmgandhi	18:6a4db94011d3	6577	*/
sahilmgandhi	18:6a4db94011d3	6578	__IO uint32_t TDES3_CNT;
sahilmgandhi	18:6a4db94011d3	6579	uint32_t RESERVE5[3];
sahilmgandhi	18:6a4db94011d3	6580
sahilmgandhi	18:6a4db94011d3	6581
sahilmgandhi	18:6a4db94011d3	6582	/**
sahilmgandhi	18:6a4db94011d3	6583	* SHA_CTL
sahilmgandhi	18:6a4db94011d3	6584	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6585	* Offset: 0x300 SHA Control Register
sahilmgandhi	18:6a4db94011d3	6586	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6587	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6588	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6589	* \|[0] \|START \|SHA Engine Start
sahilmgandhi	18:6a4db94011d3	6590	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	6591	* \| \| \|1 = Start SHA engine. BUSY flag will be set.
sahilmgandhi	18:6a4db94011d3	6592	* \| \| \|Note: This bit is always 0 when it's read back.
sahilmgandhi	18:6a4db94011d3	6593	* \|[1] \|STOP \|SHA Engine Stop
sahilmgandhi	18:6a4db94011d3	6594	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	6595	* \| \| \|1 = Stop SHA engine.
sahilmgandhi	18:6a4db94011d3	6596	* \| \| \|Note: This bit is always 0 when it's read back.
sahilmgandhi	18:6a4db94011d3	6597	* \|[5] \|DMALAST \|SHA Last Block
sahilmgandhi	18:6a4db94011d3	6598	* \| \| \|In DMA mode, this bit must be set as beginning the last DMA cascade round.
sahilmgandhi	18:6a4db94011d3	6599	* \| \| \|In Non-DMA mode, this bit must be set as feeding in last byte of data.
sahilmgandhi	18:6a4db94011d3	6600	* \|[7] \|DMAEN \|SHA Engine DMA Enable Control
sahilmgandhi	18:6a4db94011d3	6601	* \| \| \|0 = SHA_DMA engine Disabled.
sahilmgandhi	18:6a4db94011d3	6602	* \| \| \|The SHA engine operates in Non-DMA mode, and gets data from the port CRPT_SHA_DATIN.
sahilmgandhi	18:6a4db94011d3	6603	* \| \| \|1 = SHA_DMA engine Enabled.
sahilmgandhi	18:6a4db94011d3	6604	* \| \| \|The SHA engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
sahilmgandhi	18:6a4db94011d3	6605	* \|[8:10] \|OPMODE \|SHA Engine Operation Modes
sahilmgandhi	18:6a4db94011d3	6606	* \| \| \|000 = SHA160.
sahilmgandhi	18:6a4db94011d3	6607	* \| \| \|100 = SHA256.
sahilmgandhi	18:6a4db94011d3	6608	* \| \| \|101 = SHA224.
sahilmgandhi	18:6a4db94011d3	6609	* \| \| \|Note: These bits can be read and written, but writing to them wouldn't take effect as BUSY is 1.
sahilmgandhi	18:6a4db94011d3	6610	* \|[22] \|OUTSWAP \|SHA Engine Output Data Swap
sahilmgandhi	18:6a4db94011d3	6611	* \| \| \|0 = Keep the original order.
sahilmgandhi	18:6a4db94011d3	6612	* \| \| \|1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
sahilmgandhi	18:6a4db94011d3	6613	* \|[23] \|INSWAP \|SHA Engine Input Data Swap
sahilmgandhi	18:6a4db94011d3	6614	* \| \| \|0 = Keep the original order.
sahilmgandhi	18:6a4db94011d3	6615	* \| \| \|1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
sahilmgandhi	18:6a4db94011d3	6616	*/
sahilmgandhi	18:6a4db94011d3	6617	__IO uint32_t SHA_CTL;
sahilmgandhi	18:6a4db94011d3	6618
sahilmgandhi	18:6a4db94011d3	6619	/**
sahilmgandhi	18:6a4db94011d3	6620	* SHA_STS
sahilmgandhi	18:6a4db94011d3	6621	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6622	* Offset: 0x304 SHA Status Flag
sahilmgandhi	18:6a4db94011d3	6623	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6624	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6625	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6626	* \|[0] \|BUSY \|SHA Engine Busy
sahilmgandhi	18:6a4db94011d3	6627	* \| \| \|0 = SHA engine is idle or finished.
sahilmgandhi	18:6a4db94011d3	6628	* \| \| \|1 = SHA engine is busy.
sahilmgandhi	18:6a4db94011d3	6629	* \|[1] \|DMABUSY \|SHA Engine DMA Busy Flag
sahilmgandhi	18:6a4db94011d3	6630	* \| \| \|0 = SHA DMA engine is idle or finished.
sahilmgandhi	18:6a4db94011d3	6631	* \| \| \|1 = SHA DMA engine is busy.
sahilmgandhi	18:6a4db94011d3	6632	* \|[8] \|DMAERR \|SHA Engine DMA Error Flag
sahilmgandhi	18:6a4db94011d3	6633	* \| \| \|0 = Show the SHA engine access normal.
sahilmgandhi	18:6a4db94011d3	6634	* \| \| \|1 = Show the SHA engine access error.
sahilmgandhi	18:6a4db94011d3	6635	* \|[16] \|DATINREQ \|SHA Non-DMA Mode Data Input Request
sahilmgandhi	18:6a4db94011d3	6636	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	6637	* \| \| \|1 = Request SHA Non-DMA mode data input.
sahilmgandhi	18:6a4db94011d3	6638	*/
sahilmgandhi	18:6a4db94011d3	6639	__I uint32_t SHA_STS;
sahilmgandhi	18:6a4db94011d3	6640
sahilmgandhi	18:6a4db94011d3	6641	/**
sahilmgandhi	18:6a4db94011d3	6642	* SHA_DGST0
sahilmgandhi	18:6a4db94011d3	6643	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6644	* Offset: 0x308 SHA Digest Message 0
sahilmgandhi	18:6a4db94011d3	6645	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6646	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6647	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6648	* \|[0:31] \|DGST \|SHA Digest Message Word
sahilmgandhi	18:6a4db94011d3	6649	* \| \| \|For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.
sahilmgandhi	18:6a4db94011d3	6650	* \| \| \|For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.
sahilmgandhi	18:6a4db94011d3	6651	* \| \| \|For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7.
sahilmgandhi	18:6a4db94011d3	6652	*/
sahilmgandhi	18:6a4db94011d3	6653	__I uint32_t SHA_DGST0;
sahilmgandhi	18:6a4db94011d3	6654
sahilmgandhi	18:6a4db94011d3	6655	/**
sahilmgandhi	18:6a4db94011d3	6656	* SHA_DGST1
sahilmgandhi	18:6a4db94011d3	6657	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6658	* Offset: 0x30C SHA Digest Message 1
sahilmgandhi	18:6a4db94011d3	6659	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6660	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6661	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6662	* \|[0:31] \|DGST \|SHA Digest Message Word
sahilmgandhi	18:6a4db94011d3	6663	* \| \| \|For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.
sahilmgandhi	18:6a4db94011d3	6664	* \| \| \|For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.
sahilmgandhi	18:6a4db94011d3	6665	* \| \| \|For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7.
sahilmgandhi	18:6a4db94011d3	6666	*/
sahilmgandhi	18:6a4db94011d3	6667	__I uint32_t SHA_DGST1;
sahilmgandhi	18:6a4db94011d3	6668
sahilmgandhi	18:6a4db94011d3	6669	/**
sahilmgandhi	18:6a4db94011d3	6670	* SHA_DGST2
sahilmgandhi	18:6a4db94011d3	6671	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6672	* Offset: 0x310 SHA Digest Message 2
sahilmgandhi	18:6a4db94011d3	6673	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6674	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6675	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6676	* \|[0:31] \|DGST \|SHA Digest Message Word
sahilmgandhi	18:6a4db94011d3	6677	* \| \| \|For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.
sahilmgandhi	18:6a4db94011d3	6678	* \| \| \|For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.
sahilmgandhi	18:6a4db94011d3	6679	* \| \| \|For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7.
sahilmgandhi	18:6a4db94011d3	6680	*/
sahilmgandhi	18:6a4db94011d3	6681	__I uint32_t SHA_DGST2;
sahilmgandhi	18:6a4db94011d3	6682
sahilmgandhi	18:6a4db94011d3	6683	/**
sahilmgandhi	18:6a4db94011d3	6684	* SHA_DGST3
sahilmgandhi	18:6a4db94011d3	6685	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6686	* Offset: 0x314 SHA Digest Message 3
sahilmgandhi	18:6a4db94011d3	6687	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6688	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6689	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6690	* \|[0:31] \|DGST \|SHA Digest Message Word
sahilmgandhi	18:6a4db94011d3	6691	* \| \| \|For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.
sahilmgandhi	18:6a4db94011d3	6692	* \| \| \|For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.
sahilmgandhi	18:6a4db94011d3	6693	* \| \| \|For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7.
sahilmgandhi	18:6a4db94011d3	6694	*/
sahilmgandhi	18:6a4db94011d3	6695	__I uint32_t SHA_DGST3;
sahilmgandhi	18:6a4db94011d3	6696
sahilmgandhi	18:6a4db94011d3	6697	/**
sahilmgandhi	18:6a4db94011d3	6698	* SHA_DGST4
sahilmgandhi	18:6a4db94011d3	6699	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6700	* Offset: 0x318 SHA Digest Message 4
sahilmgandhi	18:6a4db94011d3	6701	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6702	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6703	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6704	* \|[0:31] \|DGST \|SHA Digest Message Word
sahilmgandhi	18:6a4db94011d3	6705	* \| \| \|For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.
sahilmgandhi	18:6a4db94011d3	6706	* \| \| \|For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.
sahilmgandhi	18:6a4db94011d3	6707	* \| \| \|For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7.
sahilmgandhi	18:6a4db94011d3	6708	*/
sahilmgandhi	18:6a4db94011d3	6709	__I uint32_t SHA_DGST4;
sahilmgandhi	18:6a4db94011d3	6710
sahilmgandhi	18:6a4db94011d3	6711	/**
sahilmgandhi	18:6a4db94011d3	6712	* SHA_DGST5
sahilmgandhi	18:6a4db94011d3	6713	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6714	* Offset: 0x31C SHA Digest Message 5
sahilmgandhi	18:6a4db94011d3	6715	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6716	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6717	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6718	* \|[0:31] \|DGST \|SHA Digest Message Word
sahilmgandhi	18:6a4db94011d3	6719	* \| \| \|For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.
sahilmgandhi	18:6a4db94011d3	6720	* \| \| \|For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.
sahilmgandhi	18:6a4db94011d3	6721	* \| \| \|For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7.
sahilmgandhi	18:6a4db94011d3	6722	*/
sahilmgandhi	18:6a4db94011d3	6723	__I uint32_t SHA_DGST5;
sahilmgandhi	18:6a4db94011d3	6724
sahilmgandhi	18:6a4db94011d3	6725	/**
sahilmgandhi	18:6a4db94011d3	6726	* SHA_DGST6
sahilmgandhi	18:6a4db94011d3	6727	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6728	* Offset: 0x320 SHA Digest Message 6
sahilmgandhi	18:6a4db94011d3	6729	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6730	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6731	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6732	* \|[0:31] \|DGST \|SHA Digest Message Word
sahilmgandhi	18:6a4db94011d3	6733	* \| \| \|For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.
sahilmgandhi	18:6a4db94011d3	6734	* \| \| \|For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.
sahilmgandhi	18:6a4db94011d3	6735	* \| \| \|For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7.
sahilmgandhi	18:6a4db94011d3	6736	*/
sahilmgandhi	18:6a4db94011d3	6737	__I uint32_t SHA_DGST6;
sahilmgandhi	18:6a4db94011d3	6738
sahilmgandhi	18:6a4db94011d3	6739	/**
sahilmgandhi	18:6a4db94011d3	6740	* SHA_DGST7
sahilmgandhi	18:6a4db94011d3	6741	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6742	* Offset: 0x324 SHA Digest Message 7
sahilmgandhi	18:6a4db94011d3	6743	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6744	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6745	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6746	* \|[0:31] \|DGST \|SHA Digest Message Word
sahilmgandhi	18:6a4db94011d3	6747	* \| \| \|For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.
sahilmgandhi	18:6a4db94011d3	6748	* \| \| \|For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.
sahilmgandhi	18:6a4db94011d3	6749	* \| \| \|For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7.
sahilmgandhi	18:6a4db94011d3	6750	*/
sahilmgandhi	18:6a4db94011d3	6751	__I uint32_t SHA_DGST7;
sahilmgandhi	18:6a4db94011d3	6752	uint32_t RESERVE6[8];
sahilmgandhi	18:6a4db94011d3	6753
sahilmgandhi	18:6a4db94011d3	6754
sahilmgandhi	18:6a4db94011d3	6755	/**
sahilmgandhi	18:6a4db94011d3	6756	* SHA_KEYCNT
sahilmgandhi	18:6a4db94011d3	6757	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6758	* Offset: 0x348 SHA Key Byte Count Register
sahilmgandhi	18:6a4db94011d3	6759	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6760	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6761	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6762	* \|[0:31] \|KEYCNT \|SHA Key Byte Count
sahilmgandhi	18:6a4db94011d3	6763	* \| \| \|The CRPT_SHA_KEYCNT keeps the byte count of key that SHA engine operates.
sahilmgandhi	18:6a4db94011d3	6764	* \| \| \|The register is 32-bit and the maximum byte count is 4G bytes.
sahilmgandhi	18:6a4db94011d3	6765	* \| \| \|It can be read and written.
sahilmgandhi	18:6a4db94011d3	6766	* \| \| \|Writing to the register CRPT_SHA_KEYCNT as the SHA accelerator operating doesn't affect the current SHA operation.
sahilmgandhi	18:6a4db94011d3	6767	* \| \| \|But the value of SHA _KEY_CNT will be updated later on.
sahilmgandhi	18:6a4db94011d3	6768	* \| \| \|Consequently, software can prepare the key count for the next SHA operation.
sahilmgandhi	18:6a4db94011d3	6769	*/
sahilmgandhi	18:6a4db94011d3	6770	__IO uint32_t SHA_KEYCNT;
sahilmgandhi	18:6a4db94011d3	6771
sahilmgandhi	18:6a4db94011d3	6772	/**
sahilmgandhi	18:6a4db94011d3	6773	* SHA_SADDR
sahilmgandhi	18:6a4db94011d3	6774	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6775	* Offset: 0x34C SHA DMA Source Address Register
sahilmgandhi	18:6a4db94011d3	6776	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6777	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6778	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6779	* \|[0:31] \|SADDR \|SHA DMA Source Address
sahilmgandhi	18:6a4db94011d3	6780	* \| \| \|The SHA accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
sahilmgandhi	18:6a4db94011d3	6781	* \| \| \|The CRPT_SHA_SADDR keeps the source address of the data buffer where the source text is stored.
sahilmgandhi	18:6a4db94011d3	6782	* \| \| \|Based on the source address, the SHA accelerator can read the plain text from system memory and do SHA operation.
sahilmgandhi	18:6a4db94011d3	6783	* \| \| \|The start of source address should be located at word boundary.
sahilmgandhi	18:6a4db94011d3	6784	* \| \| \|In other words, bit 1 and 0 of CRPT_SHA_SADDR are ignored.
sahilmgandhi	18:6a4db94011d3	6785	* \| \| \|CRPT_SHA_SADDR can be read and written.
sahilmgandhi	18:6a4db94011d3	6786	* \| \| \|Writing to CRPT_SHA_SADDR while the SHA accelerator is operating doesn't affect the current SHA operation.
sahilmgandhi	18:6a4db94011d3	6787	* \| \| \|But the value of CRPT_SHA_SADDR will be updated later on.
sahilmgandhi	18:6a4db94011d3	6788	* \| \| \|Consequently, software can prepare the DMA source address for the next SHA operation.
sahilmgandhi	18:6a4db94011d3	6789	* \| \| \|In DMA mode, software can update the next TDES_SADR before triggering START.
sahilmgandhi	18:6a4db94011d3	6790	* \| \| \|TDES_SADR and TDES_DADR can be the same in the value.
sahilmgandhi	18:6a4db94011d3	6791	*/
sahilmgandhi	18:6a4db94011d3	6792	__IO uint32_t SHA_SADDR;
sahilmgandhi	18:6a4db94011d3	6793
sahilmgandhi	18:6a4db94011d3	6794	/**
sahilmgandhi	18:6a4db94011d3	6795	* SHA_DMACNT
sahilmgandhi	18:6a4db94011d3	6796	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6797	* Offset: 0x350 SHA Byte Count Register
sahilmgandhi	18:6a4db94011d3	6798	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6799	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6800	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6801	* \|[0:31] \|DMACNT \|SHA Operation Byte Count
sahilmgandhi	18:6a4db94011d3	6802	* \| \| \|The CRPT_SHA_DMACNT keeps the byte count of source text that is for the SHA engine operating in DMA mode.
sahilmgandhi	18:6a4db94011d3	6803	* \| \| \|The CRPT_SHA_DMACNT is 32-bit and the maximum of byte count is 4G bytes.
sahilmgandhi	18:6a4db94011d3	6804	* \| \| \|CRPT_SHA_DMACNT can be read and written.
sahilmgandhi	18:6a4db94011d3	6805	* \| \| \|Writing to CRPT_SHA_DMACNT while the SHA accelerator is operating doesn't affect the current SHA operation.
sahilmgandhi	18:6a4db94011d3	6806	* \| \| \|But the value of CRPT_SHA_DMACNT will be updated later on.
sahilmgandhi	18:6a4db94011d3	6807	* \| \| \|Consequently, software can prepare the byte count of data for the next SHA operation.
sahilmgandhi	18:6a4db94011d3	6808	* \| \| \|In Non-DMA mode, CRPT_SHA_DMACNT must be set as the byte count of the last block before feeding in the last block of data.
sahilmgandhi	18:6a4db94011d3	6809	*/
sahilmgandhi	18:6a4db94011d3	6810	__IO uint32_t SHA_DMACNT;
sahilmgandhi	18:6a4db94011d3	6811
sahilmgandhi	18:6a4db94011d3	6812	/**
sahilmgandhi	18:6a4db94011d3	6813	* SHA_DATIN
sahilmgandhi	18:6a4db94011d3	6814	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	6815	* Offset: 0x354 SHA Engine Non-DMA Mode Data Input Port Register
sahilmgandhi	18:6a4db94011d3	6816	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	6817	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	6818	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	6819	* \|[0:31] \|DATIN \|SHA Engine Input Port
sahilmgandhi	18:6a4db94011d3	6820	* \| \| \|CPU feeds data to SHA engine through this port by checking CRPT_SHA_STS. Feed data as DATINREQ is 1.
sahilmgandhi	18:6a4db94011d3	6821	*/
sahilmgandhi	18:6a4db94011d3	6822	__IO uint32_t SHA_DATIN;
sahilmgandhi	18:6a4db94011d3	6823
sahilmgandhi	18:6a4db94011d3	6824	} CRPT_T;
sahilmgandhi	18:6a4db94011d3	6825
sahilmgandhi	18:6a4db94011d3	6826	/**
sahilmgandhi	18:6a4db94011d3	6827	@addtogroup CRPT_CONST CRPT Bit Field Definition
sahilmgandhi	18:6a4db94011d3	6828	Constant Definitions for CRPT Controller
sahilmgandhi	18:6a4db94011d3	6829	@{ */
sahilmgandhi	18:6a4db94011d3	6830
sahilmgandhi	18:6a4db94011d3	6831	#define CRPT_INTEN_AESIEN_Pos (0) /!< CRPT INTEN: AESIEN Position /
sahilmgandhi	18:6a4db94011d3	6832	#define CRPT_INTEN_AESIEN_Msk (0x1ul << CRPT_INTEN_AESIEN_Pos) /!< CRPT INTEN: AESIEN Mask /
sahilmgandhi	18:6a4db94011d3	6833
sahilmgandhi	18:6a4db94011d3	6834	#define CRPT_INTEN_AESERRIEN_Pos (1) /!< CRPT INTEN: AESERRIEN Position /
sahilmgandhi	18:6a4db94011d3	6835	#define CRPT_INTEN_AESERRIEN_Msk (0x1ul << CRPT_INTEN_AESERRIEN_Pos) /!< CRPT INTEN: AESERRIEN Mask /
sahilmgandhi	18:6a4db94011d3	6836
sahilmgandhi	18:6a4db94011d3	6837	#define CRPT_INTEN_TDESIEN_Pos (8) /!< CRPT INTEN: TDESIEN Position /
sahilmgandhi	18:6a4db94011d3	6838	#define CRPT_INTEN_TDESIEN_Msk (0x1ul << CRPT_INTEN_TDESIEN_Pos) /!< CRPT INTEN: TDESIEN Mask /
sahilmgandhi	18:6a4db94011d3	6839
sahilmgandhi	18:6a4db94011d3	6840	#define CRPT_INTEN_TDESERRIEN_Pos (9) /!< CRPT INTEN: TDESERRIEN Position /
sahilmgandhi	18:6a4db94011d3	6841	#define CRPT_INTEN_TDESERRIEN_Msk (0x1ul << CRPT_INTEN_TDESERRIEN_Pos) /!< CRPT INTEN: TDESERRIEN Mask /
sahilmgandhi	18:6a4db94011d3	6842
sahilmgandhi	18:6a4db94011d3	6843	#define CRPT_INTEN_PRNGIEN_Pos (16) /!< CRPT INTEN: PRNGIEN Position /
sahilmgandhi	18:6a4db94011d3	6844	#define CRPT_INTEN_PRNGIEN_Msk (0x1ul << CRPT_INTEN_PRNGIEN_Pos) /!< CRPT INTEN: PRNGIEN Mask /
sahilmgandhi	18:6a4db94011d3	6845
sahilmgandhi	18:6a4db94011d3	6846	#define CRPT_INTEN_SHAIEN_Pos (24) /!< CRPT INTEN: SHAIEN Position /
sahilmgandhi	18:6a4db94011d3	6847	#define CRPT_INTEN_SHAIEN_Msk (0x1ul << CRPT_INTEN_SHAIEN_Pos) /!< CRPT INTEN: SHAIEN Mask /
sahilmgandhi	18:6a4db94011d3	6848
sahilmgandhi	18:6a4db94011d3	6849	#define CRPT_INTEN_SHAERRIEN_Pos (25) /!< CRPT INTEN: SHAERRIEN Position /
sahilmgandhi	18:6a4db94011d3	6850	#define CRPT_INTEN_SHAERRIEN_Msk (0x1ul << CRPT_INTEN_SHAERRIEN_Pos) /!< CRPT INTEN: SHAERRIEN Mask /
sahilmgandhi	18:6a4db94011d3	6851
sahilmgandhi	18:6a4db94011d3	6852	#define CRPT_INTSTS_AESIF_Pos (0) /!< CRPT INTSTS: AESIF Position /
sahilmgandhi	18:6a4db94011d3	6853	#define CRPT_INTSTS_AESIF_Msk (0x1ul << CRPT_INTSTS_AESIF_Pos) /!< CRPT INTSTS: AESIF Mask /
sahilmgandhi	18:6a4db94011d3	6854
sahilmgandhi	18:6a4db94011d3	6855	#define CRPT_INTSTS_AESERRIF_Pos (1) /!< CRPT INTSTS: AESERRIF Position /
sahilmgandhi	18:6a4db94011d3	6856	#define CRPT_INTSTS_AESERRIF_Msk (0x1ul << CRPT_INTSTS_AESERRIF_Pos) /!< CRPT INTSTS: AESERRIF Mask /
sahilmgandhi	18:6a4db94011d3	6857
sahilmgandhi	18:6a4db94011d3	6858	#define CRPT_INTSTS_TDESIF_Pos (8) /!< CRPT INTSTS: TDESIF Position /
sahilmgandhi	18:6a4db94011d3	6859	#define CRPT_INTSTS_TDESIF_Msk (0x1ul << CRPT_INTSTS_TDESIF_Pos) /!< CRPT INTSTS: TDESIF Mask /
sahilmgandhi	18:6a4db94011d3	6860
sahilmgandhi	18:6a4db94011d3	6861	#define CRPT_INTSTS_TDESERRIF_Pos (9) /!< CRPT INTSTS: TDESERRIF Position /
sahilmgandhi	18:6a4db94011d3	6862	#define CRPT_INTSTS_TDESERRIF_Msk (0x1ul << CRPT_INTSTS_TDESERRIF_Pos) /!< CRPT INTSTS: TDESERRIF Mask /
sahilmgandhi	18:6a4db94011d3	6863
sahilmgandhi	18:6a4db94011d3	6864	#define CRPT_INTSTS_PRNGIF_Pos (16) /!< CRPT INTSTS: PRNGIF Position /
sahilmgandhi	18:6a4db94011d3	6865	#define CRPT_INTSTS_PRNGIF_Msk (0x1ul << CRPT_INTSTS_PRNGIF_Pos) /!< CRPT INTSTS: PRNGIF Mask /
sahilmgandhi	18:6a4db94011d3	6866
sahilmgandhi	18:6a4db94011d3	6867	#define CRPT_INTSTS_SHAIF_Pos (24) /!< CRPT INTSTS: SHAIF Position /
sahilmgandhi	18:6a4db94011d3	6868	#define CRPT_INTSTS_SHAIF_Msk (0x1ul << CRPT_INTSTS_SHAIF_Pos) /!< CRPT INTSTS: SHAIF Mask /
sahilmgandhi	18:6a4db94011d3	6869
sahilmgandhi	18:6a4db94011d3	6870	#define CRPT_INTSTS_SHAERRIF_Pos (25) /!< CRPT INTSTS: SHAERRIF Position /
sahilmgandhi	18:6a4db94011d3	6871	#define CRPT_INTSTS_SHAERRIF_Msk (0x1ul << CRPT_INTSTS_SHAERRIF_Pos) /!< CRPT INTSTS: SHAERRIF Mask /
sahilmgandhi	18:6a4db94011d3	6872
sahilmgandhi	18:6a4db94011d3	6873	#define CRPT_PRNG_CTL_START_Pos (0) /!< CRPT PRNG_CTL: START Position /
sahilmgandhi	18:6a4db94011d3	6874	#define CRPT_PRNG_CTL_START_Msk (0x1ul << CRPT_PRNG_CTL_START_Pos) /!< CRPT PRNG_CTL: START Mask /
sahilmgandhi	18:6a4db94011d3	6875
sahilmgandhi	18:6a4db94011d3	6876	#define CRPT_PRNG_CTL_SEEDRLD_Pos (1) /!< CRPT PRNG_CTL: SEEDRLD Position /
sahilmgandhi	18:6a4db94011d3	6877	#define CRPT_PRNG_CTL_SEEDRLD_Msk (0x1ul << CRPT_PRNG_CTL_SEEDRLD_Pos) /!< CRPT PRNG_CTL: SEEDRLD Mask /
sahilmgandhi	18:6a4db94011d3	6878
sahilmgandhi	18:6a4db94011d3	6879	#define CRPT_PRNG_CTL_KEYSZ_Pos (2) /!< CRPT PRNG_CTL: KEYSZ Position /
sahilmgandhi	18:6a4db94011d3	6880	#define CRPT_PRNG_CTL_KEYSZ_Msk (0x3ul << CRPT_PRNG_CTL_KEYSZ_Pos) /!< CRPT PRNG_CTL: KEYSZ Mask /
sahilmgandhi	18:6a4db94011d3	6881
sahilmgandhi	18:6a4db94011d3	6882	#define CRPT_PRNG_CTL_BUSY_Pos (8) /!< CRPT PRNG_CTL: BUSY Position /
sahilmgandhi	18:6a4db94011d3	6883	#define CRPT_PRNG_CTL_BUSY_Msk (0x1ul << CRPT_PRNG_CTL_BUSY_Pos) /!< CRPT PRNG_CTL: BUSY Mask /
sahilmgandhi	18:6a4db94011d3	6884
sahilmgandhi	18:6a4db94011d3	6885	#define CRPT_PRNG_SEED_SEED_Pos (0) /!< CRPT PRNG_SEED: SEED Position /
sahilmgandhi	18:6a4db94011d3	6886	#define CRPT_PRNG_SEED_SEED_Msk (0xfffffffful << CRPT_PRNG_SEED_SEED_Pos) /!< CRPT PRNG_SEED: SEED Mask /
sahilmgandhi	18:6a4db94011d3	6887
sahilmgandhi	18:6a4db94011d3	6888	#define CRPT_PRNG_KEY0_KEY_Pos (0) /!< CRPT PRNG_KEY0: KEY Position /
sahilmgandhi	18:6a4db94011d3	6889	#define CRPT_PRNG_KEY0_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY0_KEY_Pos) /!< CRPT PRNG_KEY0: KEY Mask /
sahilmgandhi	18:6a4db94011d3	6890
sahilmgandhi	18:6a4db94011d3	6891	#define CRPT_PRNG_KEY1_KEY_Pos (0) /!< CRPT PRNG_KEY1: KEY Position /
sahilmgandhi	18:6a4db94011d3	6892	#define CRPT_PRNG_KEY1_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY1_KEY_Pos) /!< CRPT PRNG_KEY1: KEY Mask /
sahilmgandhi	18:6a4db94011d3	6893
sahilmgandhi	18:6a4db94011d3	6894	#define CRPT_PRNG_KEY2_KEY_Pos (0) /!< CRPT PRNG_KEY2: KEY Position /
sahilmgandhi	18:6a4db94011d3	6895	#define CRPT_PRNG_KEY2_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY2_KEY_Pos) /!< CRPT PRNG_KEY2: KEY Mask /
sahilmgandhi	18:6a4db94011d3	6896
sahilmgandhi	18:6a4db94011d3	6897	#define CRPT_PRNG_KEY3_KEY_Pos (0) /!< CRPT PRNG_KEY3: KEY Position /
sahilmgandhi	18:6a4db94011d3	6898	#define CRPT_PRNG_KEY3_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY3_KEY_Pos) /!< CRPT PRNG_KEY3: KEY Mask /
sahilmgandhi	18:6a4db94011d3	6899
sahilmgandhi	18:6a4db94011d3	6900	#define CRPT_PRNG_KEY4_KEY_Pos (0) /!< CRPT PRNG_KEY4: KEY Position /
sahilmgandhi	18:6a4db94011d3	6901	#define CRPT_PRNG_KEY4_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY4_KEY_Pos) /!< CRPT PRNG_KEY4: KEY Mask /
sahilmgandhi	18:6a4db94011d3	6902
sahilmgandhi	18:6a4db94011d3	6903	#define CRPT_PRNG_KEY5_KEY_Pos (0) /!< CRPT PRNG_KEY5: KEY Position /
sahilmgandhi	18:6a4db94011d3	6904	#define CRPT_PRNG_KEY5_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY5_KEY_Pos) /!< CRPT PRNG_KEY5: KEY Mask /
sahilmgandhi	18:6a4db94011d3	6905
sahilmgandhi	18:6a4db94011d3	6906	#define CRPT_PRNG_KEY6_KEY_Pos (0) /!< CRPT PRNG_KEY6: KEY Position /
sahilmgandhi	18:6a4db94011d3	6907	#define CRPT_PRNG_KEY6_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY6_KEY_Pos) /!< CRPT PRNG_KEY6: KEY Mask /
sahilmgandhi	18:6a4db94011d3	6908
sahilmgandhi	18:6a4db94011d3	6909	#define CRPT_PRNG_KEY7_KEY_Pos (0) /!< CRPT PRNG_KEY7: KEY Position /
sahilmgandhi	18:6a4db94011d3	6910	#define CRPT_PRNG_KEY7_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY7_KEY_Pos) /!< CRPT PRNG_KEY7: KEY Mask /
sahilmgandhi	18:6a4db94011d3	6911
sahilmgandhi	18:6a4db94011d3	6912	#define CRPT_AES_FDBCK0_FDBCK_Pos (0) /!< CRPT AES_FDBCK0: FDBCK Position /
sahilmgandhi	18:6a4db94011d3	6913	#define CRPT_AES_FDBCK0_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK0_FDBCK_Pos) /!< CRPT AES_FDBCK0: FDBCK Mask /
sahilmgandhi	18:6a4db94011d3	6914
sahilmgandhi	18:6a4db94011d3	6915	#define CRPT_AES_FDBCK1_FDBCK_Pos (0) /!< CRPT AES_FDBCK1: FDBCK Position /
sahilmgandhi	18:6a4db94011d3	6916	#define CRPT_AES_FDBCK1_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK1_FDBCK_Pos) /!< CRPT AES_FDBCK1: FDBCK Mask /
sahilmgandhi	18:6a4db94011d3	6917
sahilmgandhi	18:6a4db94011d3	6918	#define CRPT_AES_FDBCK2_FDBCK_Pos (0) /!< CRPT AES_FDBCK2: FDBCK Position /
sahilmgandhi	18:6a4db94011d3	6919	#define CRPT_AES_FDBCK2_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK2_FDBCK_Pos) /!< CRPT AES_FDBCK2: FDBCK Mask /
sahilmgandhi	18:6a4db94011d3	6920
sahilmgandhi	18:6a4db94011d3	6921	#define CRPT_AES_FDBCK3_FDBCK_Pos (0) /!< CRPT AES_FDBCK3: FDBCK Position /
sahilmgandhi	18:6a4db94011d3	6922	#define CRPT_AES_FDBCK3_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK3_FDBCK_Pos) /!< CRPT AES_FDBCK3: FDBCK Mask /
sahilmgandhi	18:6a4db94011d3	6923
sahilmgandhi	18:6a4db94011d3	6924	#define CRPT_TDES_FDBCKH_FDBCK_Pos (0) /!< CRPT TDES_FDBCKH: FDBCK Position /
sahilmgandhi	18:6a4db94011d3	6925	#define CRPT_TDES_FDBCKH_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKH_FDBCK_Pos) /!< CRPT TDES_FDBCKH: FDBCK Mask /
sahilmgandhi	18:6a4db94011d3	6926
sahilmgandhi	18:6a4db94011d3	6927	#define CRPT_TDES_FDBCKL_FDBCK_Pos (0) /!< CRPT TDES_FDBCKL: FDBCK Position /
sahilmgandhi	18:6a4db94011d3	6928	#define CRPT_TDES_FDBCKL_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKL_FDBCK_Pos) /!< CRPT TDES_FDBCKL: FDBCK Mask /
sahilmgandhi	18:6a4db94011d3	6929
sahilmgandhi	18:6a4db94011d3	6930	#define CRPT_AES_CTL_START_Pos (0) /!< CRPT AES_CTL: START Position /
sahilmgandhi	18:6a4db94011d3	6931	#define CRPT_AES_CTL_START_Msk (0x1ul << CRPT_AES_CTL_START_Pos) /!< CRPT AES_CTL: START Mask /
sahilmgandhi	18:6a4db94011d3	6932
sahilmgandhi	18:6a4db94011d3	6933	#define CRPT_AES_CTL_STOP_Pos (1) /!< CRPT AES_CTL: STOP Position /
sahilmgandhi	18:6a4db94011d3	6934	#define CRPT_AES_CTL_STOP_Msk (0x1ul << CRPT_AES_CTL_STOP_Pos) /!< CRPT AES_CTL: STOP Mask /
sahilmgandhi	18:6a4db94011d3	6935
sahilmgandhi	18:6a4db94011d3	6936	#define CRPT_AES_CTL_KEYSZ_Pos (2) /!< CRPT AES_CTL: KEYSZ Position /
sahilmgandhi	18:6a4db94011d3	6937	#define CRPT_AES_CTL_KEYSZ_Msk (0x3ul << CRPT_AES_CTL_KEYSZ_Pos) /!< CRPT AES_CTL: KEYSZ Mask /
sahilmgandhi	18:6a4db94011d3	6938
sahilmgandhi	18:6a4db94011d3	6939	#define CRPT_AES_CTL_DMALAST_Pos (5) /!< CRPT AES_CTL: DMALAST Position /
sahilmgandhi	18:6a4db94011d3	6940	#define CRPT_AES_CTL_DMALAST_Msk (0x1ul << CRPT_AES_CTL_DMALAST_Pos) /!< CRPT AES_CTL: DMALAST Mask /
sahilmgandhi	18:6a4db94011d3	6941
sahilmgandhi	18:6a4db94011d3	6942	#define CRPT_AES_CTL_DMACSCAD_Pos (6) /!< CRPT AES_CTL: DMACSCAD Position /
sahilmgandhi	18:6a4db94011d3	6943	#define CRPT_AES_CTL_DMACSCAD_Msk (0x1ul << CRPT_AES_CTL_DMACSCAD_Pos) /!< CRPT AES_CTL: DMACSCAD Mask /
sahilmgandhi	18:6a4db94011d3	6944
sahilmgandhi	18:6a4db94011d3	6945	#define CRPT_AES_CTL_DMAEN_Pos (7) /!< CRPT AES_CTL: DMAEN Position /
sahilmgandhi	18:6a4db94011d3	6946	#define CRPT_AES_CTL_DMAEN_Msk (0x1ul << CRPT_AES_CTL_DMAEN_Pos) /!< CRPT AES_CTL: DMAEN Mask /
sahilmgandhi	18:6a4db94011d3	6947
sahilmgandhi	18:6a4db94011d3	6948	#define CRPT_AES_CTL_OPMODE_Pos (8) /!< CRPT AES_CTL: OPMODE Position /
sahilmgandhi	18:6a4db94011d3	6949	#define CRPT_AES_CTL_OPMODE_Msk (0xfful << CRPT_AES_CTL_OPMODE_Pos) /!< CRPT AES_CTL: OPMODE Mask /
sahilmgandhi	18:6a4db94011d3	6950
sahilmgandhi	18:6a4db94011d3	6951	#define CRPT_AES_CTL_ENCRPT_Pos (16) /!< CRPT AES_CTL: ENCRPT Position /
sahilmgandhi	18:6a4db94011d3	6952	#define CRPT_AES_CTL_ENCRPT_Msk (0x1ul << CRPT_AES_CTL_ENCRPT_Pos) /!< CRPT AES_CTL: ENCRPT Mask /
sahilmgandhi	18:6a4db94011d3	6953
sahilmgandhi	18:6a4db94011d3	6954	#define CRPT_AES_CTL_OUTSWAP_Pos (22) /!< CRPT AES_CTL: OUTSWAP Position /
sahilmgandhi	18:6a4db94011d3	6955	#define CRPT_AES_CTL_OUTSWAP_Msk (0x1ul << CRPT_AES_CTL_OUTSWAP_Pos) /!< CRPT AES_CTL: OUTSWAP Mask /
sahilmgandhi	18:6a4db94011d3	6956
sahilmgandhi	18:6a4db94011d3	6957	#define CRPT_AES_CTL_INSWAP_Pos (23) /!< CRPT AES_CTL: INSWAP Position /
sahilmgandhi	18:6a4db94011d3	6958	#define CRPT_AES_CTL_INSWAP_Msk (0x1ul << CRPT_AES_CTL_INSWAP_Pos) /!< CRPT AES_CTL: INSWAP Mask /
sahilmgandhi	18:6a4db94011d3	6959
sahilmgandhi	18:6a4db94011d3	6960	#define CRPT_AES_CTL_CHANNEL_Pos (24) /!< CRPT AES_CTL: CHANNEL Position /
sahilmgandhi	18:6a4db94011d3	6961	#define CRPT_AES_CTL_CHANNEL_Msk (0x3ul << CRPT_AES_CTL_CHANNEL_Pos) /!< CRPT AES_CTL: CHANNEL Mask /
sahilmgandhi	18:6a4db94011d3	6962
sahilmgandhi	18:6a4db94011d3	6963	#define CRPT_AES_CTL_KEYUNPRT_Pos (26) /!< CRPT AES_CTL: KEYUNPRT Position /
sahilmgandhi	18:6a4db94011d3	6964	#define CRPT_AES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_AES_CTL_KEYUNPRT_Pos) /!< CRPT AES_CTL: KEYUNPRT Mask /
sahilmgandhi	18:6a4db94011d3	6965
sahilmgandhi	18:6a4db94011d3	6966	#define CRPT_AES_CTL_KEYPRT_Pos (31) /!< CRPT AES_CTL: KEYPRT Position /
sahilmgandhi	18:6a4db94011d3	6967	#define CRPT_AES_CTL_KEYPRT_Msk (0x1ul << CRPT_AES_CTL_KEYPRT_Pos) /!< CRPT AES_CTL: KEYPRT Mask /
sahilmgandhi	18:6a4db94011d3	6968
sahilmgandhi	18:6a4db94011d3	6969	#define CRPT_AES_STS_BUSY_Pos (0) /!< CRPT AES_STS: BUSY Position /
sahilmgandhi	18:6a4db94011d3	6970	#define CRPT_AES_STS_BUSY_Msk (0x1ul << CRPT_AES_STS_BUSY_Pos) /!< CRPT AES_STS: BUSY Mask /
sahilmgandhi	18:6a4db94011d3	6971
sahilmgandhi	18:6a4db94011d3	6972	#define CRPT_AES_STS_INBUFEMPTY_Pos (8) /!< CRPT AES_STS: INBUFEMPTY Position /
sahilmgandhi	18:6a4db94011d3	6973	#define CRPT_AES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_INBUFEMPTY_Pos) /!< CRPT AES_STS: INBUFEMPTY Mask /
sahilmgandhi	18:6a4db94011d3	6974
sahilmgandhi	18:6a4db94011d3	6975	#define CRPT_AES_STS_INBUFFULL_Pos (9) /!< CRPT AES_STS: INBUFFULL Position /
sahilmgandhi	18:6a4db94011d3	6976	#define CRPT_AES_STS_INBUFFULL_Msk (0x1ul << CRPT_AES_STS_INBUFFULL_Pos) /!< CRPT AES_STS: INBUFFULL Mask /
sahilmgandhi	18:6a4db94011d3	6977
sahilmgandhi	18:6a4db94011d3	6978	#define CRPT_AES_STS_INBUFERR_Pos (10) /!< CRPT AES_STS: INBUFERR Position /
sahilmgandhi	18:6a4db94011d3	6979	#define CRPT_AES_STS_INBUFERR_Msk (0x1ul << CRPT_AES_STS_INBUFERR_Pos) /!< CRPT AES_STS: INBUFERR Mask /
sahilmgandhi	18:6a4db94011d3	6980
sahilmgandhi	18:6a4db94011d3	6981	#define CRPT_AES_STS_CNTERR_Pos (12) /!< CRPT AES_STS: CNTERR Position /
sahilmgandhi	18:6a4db94011d3	6982	#define CRPT_AES_STS_CNTERR_Msk (0x1ul << CRPT_AES_STS_CNTERR_Pos) /!< CRPT AES_STS: CNTERR Mask /
sahilmgandhi	18:6a4db94011d3	6983
sahilmgandhi	18:6a4db94011d3	6984	#define CRPT_AES_STS_OUTBUFEMPTY_Pos (16) /!< CRPT AES_STS: OUTBUFEMPTY Position /
sahilmgandhi	18:6a4db94011d3	6985	#define CRPT_AES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_OUTBUFEMPTY_Pos) /!< CRPT AES_STS: OUTBUFEMPTY Mask /
sahilmgandhi	18:6a4db94011d3	6986
sahilmgandhi	18:6a4db94011d3	6987	#define CRPT_AES_STS_OUTBUFFULL_Pos (17) /!< CRPT AES_STS: OUTBUFFULL Position /
sahilmgandhi	18:6a4db94011d3	6988	#define CRPT_AES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_AES_STS_OUTBUFFULL_Pos) /!< CRPT AES_STS: OUTBUFFULL Mask /
sahilmgandhi	18:6a4db94011d3	6989
sahilmgandhi	18:6a4db94011d3	6990	#define CRPT_AES_STS_OUTBUFERR_Pos (18) /!< CRPT AES_STS: OUTBUFERR Position /
sahilmgandhi	18:6a4db94011d3	6991	#define CRPT_AES_STS_OUTBUFERR_Msk (0x1ul << CRPT_AES_STS_OUTBUFERR_Pos) /!< CRPT AES_STS: OUTBUFERR Mask /
sahilmgandhi	18:6a4db94011d3	6992
sahilmgandhi	18:6a4db94011d3	6993	#define CRPT_AES_STS_BUSERR_Pos (20) /!< CRPT AES_STS: BUSERR Position /
sahilmgandhi	18:6a4db94011d3	6994	#define CRPT_AES_STS_BUSERR_Msk (0x1ul << CRPT_AES_STS_BUSERR_Pos) /!< CRPT AES_STS: BUSERR Mask /
sahilmgandhi	18:6a4db94011d3	6995
sahilmgandhi	18:6a4db94011d3	6996	#define CRPT_AES_DATIN_DATIN_Pos (0) /!< CRPT AES_DATIN: DATIN Position /
sahilmgandhi	18:6a4db94011d3	6997	#define CRPT_AES_DATIN_DATIN_Msk (0xfffffffful << CRPT_AES_DATIN_DATIN_Pos) /!< CRPT AES_DATIN: DATIN Mask /
sahilmgandhi	18:6a4db94011d3	6998
sahilmgandhi	18:6a4db94011d3	6999	#define CRPT_AES_DATOUT_DATOUT_Pos (0) /!< CRPT AES_DATOUT: DATOUT Position /
sahilmgandhi	18:6a4db94011d3	7000	#define CRPT_AES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_AES_DATOUT_DATOUT_Pos) /!< CRPT AES_DATOUT: DATOUT Mask /
sahilmgandhi	18:6a4db94011d3	7001
sahilmgandhi	18:6a4db94011d3	7002	#define CRPT_AES0_KEY0_KEY_Pos (0) /!< CRPT AES0_KEY0: KEY Position /
sahilmgandhi	18:6a4db94011d3	7003	#define CRPT_AES0_KEY0_KEY_Msk (0xfffffffful << CRPT_AES0_KEY0_KEY_Pos) /!< CRPT AES0_KEY0: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7004
sahilmgandhi	18:6a4db94011d3	7005	#define CRPT_AES0_KEY1_KEY_Pos (0) /!< CRPT AES0_KEY1: KEY Position /
sahilmgandhi	18:6a4db94011d3	7006	#define CRPT_AES0_KEY1_KEY_Msk (0xfffffffful << CRPT_AES0_KEY1_KEY_Pos) /!< CRPT AES0_KEY1: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7007
sahilmgandhi	18:6a4db94011d3	7008	#define CRPT_AES0_KEY2_KEY_Pos (0) /!< CRPT AES0_KEY2: KEY Position /
sahilmgandhi	18:6a4db94011d3	7009	#define CRPT_AES0_KEY2_KEY_Msk (0xfffffffful << CRPT_AES0_KEY2_KEY_Pos) /!< CRPT AES0_KEY2: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7010
sahilmgandhi	18:6a4db94011d3	7011	#define CRPT_AES0_KEY3_KEY_Pos (0) /!< CRPT AES0_KEY3: KEY Position /
sahilmgandhi	18:6a4db94011d3	7012	#define CRPT_AES0_KEY3_KEY_Msk (0xfffffffful << CRPT_AES0_KEY3_KEY_Pos) /!< CRPT AES0_KEY3: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7013
sahilmgandhi	18:6a4db94011d3	7014	#define CRPT_AES0_KEY4_KEY_Pos (0) /!< CRPT AES0_KEY4: KEY Position /
sahilmgandhi	18:6a4db94011d3	7015	#define CRPT_AES0_KEY4_KEY_Msk (0xfffffffful << CRPT_AES0_KEY4_KEY_Pos) /!< CRPT AES0_KEY4: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7016
sahilmgandhi	18:6a4db94011d3	7017	#define CRPT_AES0_KEY5_KEY_Pos (0) /!< CRPT AES0_KEY5: KEY Position /
sahilmgandhi	18:6a4db94011d3	7018	#define CRPT_AES0_KEY5_KEY_Msk (0xfffffffful << CRPT_AES0_KEY5_KEY_Pos) /!< CRPT AES0_KEY5: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7019
sahilmgandhi	18:6a4db94011d3	7020	#define CRPT_AES0_KEY6_KEY_Pos (0) /!< CRPT AES0_KEY6: KEY Position /
sahilmgandhi	18:6a4db94011d3	7021	#define CRPT_AES0_KEY6_KEY_Msk (0xfffffffful << CRPT_AES0_KEY6_KEY_Pos) /!< CRPT AES0_KEY6: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7022
sahilmgandhi	18:6a4db94011d3	7023	#define CRPT_AES0_KEY7_KEY_Pos (0) /!< CRPT AES0_KEY7: KEY Position /
sahilmgandhi	18:6a4db94011d3	7024	#define CRPT_AES0_KEY7_KEY_Msk (0xfffffffful << CRPT_AES0_KEY7_KEY_Pos) /!< CRPT AES0_KEY7: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7025
sahilmgandhi	18:6a4db94011d3	7026	#define CRPT_AES0_IV0_IV_Pos (0) /!< CRPT AES0_IV0: IV Position /
sahilmgandhi	18:6a4db94011d3	7027	#define CRPT_AES0_IV0_IV_Msk (0xfffffffful << CRPT_AES0_IV0_IV_Pos) /!< CRPT AES0_IV0: IV Mask /
sahilmgandhi	18:6a4db94011d3	7028
sahilmgandhi	18:6a4db94011d3	7029	#define CRPT_AES0_IV1_IV_Pos (0) /!< CRPT AES0_IV1: IV Position /
sahilmgandhi	18:6a4db94011d3	7030	#define CRPT_AES0_IV1_IV_Msk (0xfffffffful << CRPT_AES0_IV1_IV_Pos) /!< CRPT AES0_IV1: IV Mask /
sahilmgandhi	18:6a4db94011d3	7031
sahilmgandhi	18:6a4db94011d3	7032	#define CRPT_AES0_IV2_IV_Pos (0) /!< CRPT AES0_IV2: IV Position /
sahilmgandhi	18:6a4db94011d3	7033	#define CRPT_AES0_IV2_IV_Msk (0xfffffffful << CRPT_AES0_IV2_IV_Pos) /!< CRPT AES0_IV2: IV Mask /
sahilmgandhi	18:6a4db94011d3	7034
sahilmgandhi	18:6a4db94011d3	7035	#define CRPT_AES0_IV3_IV_Pos (0) /!< CRPT AES0_IV3: IV Position /
sahilmgandhi	18:6a4db94011d3	7036	#define CRPT_AES0_IV3_IV_Msk (0xfffffffful << CRPT_AES0_IV3_IV_Pos) /!< CRPT AES0_IV3: IV Mask /
sahilmgandhi	18:6a4db94011d3	7037
sahilmgandhi	18:6a4db94011d3	7038	#define CRPT_AES0_SADDR_SADDR_Pos (0) /!< CRPT AES0_SADDR: SADDR Position /
sahilmgandhi	18:6a4db94011d3	7039	#define CRPT_AES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES0_SADDR_SADDR_Pos) /!< CRPT AES0_SADDR: SADDR Mask /
sahilmgandhi	18:6a4db94011d3	7040
sahilmgandhi	18:6a4db94011d3	7041	#define CRPT_AES0_DADDR_DADDR_Pos (0) /!< CRPT AES0_DADDR: DADDR Position /
sahilmgandhi	18:6a4db94011d3	7042	#define CRPT_AES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES0_DADDR_DADDR_Pos) /!< CRPT AES0_DADDR: DADDR Mask /
sahilmgandhi	18:6a4db94011d3	7043
sahilmgandhi	18:6a4db94011d3	7044	#define CRPT_AES0_CNT_CNT_Pos (0) /!< CRPT AES0_CNT: CNT Position /
sahilmgandhi	18:6a4db94011d3	7045	#define CRPT_AES0_CNT_CNT_Msk (0xfffffffful << CRPT_AES0_CNT_CNT_Pos) /!< CRPT AES0_CNT: CNT Mask /
sahilmgandhi	18:6a4db94011d3	7046
sahilmgandhi	18:6a4db94011d3	7047	#define CRPT_AES1_KEY0_KEY_Pos (0) /!< CRPT AES1_KEY0: KEY Position /
sahilmgandhi	18:6a4db94011d3	7048	#define CRPT_AES1_KEY0_KEY_Msk (0xfffffffful << CRPT_AES1_KEY0_KEY_Pos) /!< CRPT AES1_KEY0: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7049
sahilmgandhi	18:6a4db94011d3	7050	#define CRPT_AES1_KEY1_KEY_Pos (0) /!< CRPT AES1_KEY1: KEY Position /
sahilmgandhi	18:6a4db94011d3	7051	#define CRPT_AES1_KEY1_KEY_Msk (0xfffffffful << CRPT_AES1_KEY1_KEY_Pos) /!< CRPT AES1_KEY1: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7052
sahilmgandhi	18:6a4db94011d3	7053	#define CRPT_AES1_KEY2_KEY_Pos (0) /!< CRPT AES1_KEY2: KEY Position /
sahilmgandhi	18:6a4db94011d3	7054	#define CRPT_AES1_KEY2_KEY_Msk (0xfffffffful << CRPT_AES1_KEY2_KEY_Pos) /!< CRPT AES1_KEY2: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7055
sahilmgandhi	18:6a4db94011d3	7056	#define CRPT_AES1_KEY3_KEY_Pos (0) /!< CRPT AES1_KEY3: KEY Position /
sahilmgandhi	18:6a4db94011d3	7057	#define CRPT_AES1_KEY3_KEY_Msk (0xfffffffful << CRPT_AES1_KEY3_KEY_Pos) /!< CRPT AES1_KEY3: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7058
sahilmgandhi	18:6a4db94011d3	7059	#define CRPT_AES1_KEY4_KEY_Pos (0) /!< CRPT AES1_KEY4: KEY Position /
sahilmgandhi	18:6a4db94011d3	7060	#define CRPT_AES1_KEY4_KEY_Msk (0xfffffffful << CRPT_AES1_KEY4_KEY_Pos) /!< CRPT AES1_KEY4: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7061
sahilmgandhi	18:6a4db94011d3	7062	#define CRPT_AES1_KEY5_KEY_Pos (0) /!< CRPT AES1_KEY5: KEY Position /
sahilmgandhi	18:6a4db94011d3	7063	#define CRPT_AES1_KEY5_KEY_Msk (0xfffffffful << CRPT_AES1_KEY5_KEY_Pos) /!< CRPT AES1_KEY5: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7064
sahilmgandhi	18:6a4db94011d3	7065	#define CRPT_AES1_KEY6_KEY_Pos (0) /!< CRPT AES1_KEY6: KEY Position /
sahilmgandhi	18:6a4db94011d3	7066	#define CRPT_AES1_KEY6_KEY_Msk (0xfffffffful << CRPT_AES1_KEY6_KEY_Pos) /!< CRPT AES1_KEY6: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7067
sahilmgandhi	18:6a4db94011d3	7068	#define CRPT_AES1_KEY7_KEY_Pos (0) /!< CRPT AES1_KEY7: KEY Position /
sahilmgandhi	18:6a4db94011d3	7069	#define CRPT_AES1_KEY7_KEY_Msk (0xfffffffful << CRPT_AES1_KEY7_KEY_Pos) /!< CRPT AES1_KEY7: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7070
sahilmgandhi	18:6a4db94011d3	7071	#define CRPT_AES1_IV0_IV_Pos (0) /!< CRPT AES1_IV0: IV Position /
sahilmgandhi	18:6a4db94011d3	7072	#define CRPT_AES1_IV0_IV_Msk (0xfffffffful << CRPT_AES1_IV0_IV_Pos) /!< CRPT AES1_IV0: IV Mask /
sahilmgandhi	18:6a4db94011d3	7073
sahilmgandhi	18:6a4db94011d3	7074	#define CRPT_AES1_IV1_IV_Pos (0) /!< CRPT AES1_IV1: IV Position /
sahilmgandhi	18:6a4db94011d3	7075	#define CRPT_AES1_IV1_IV_Msk (0xfffffffful << CRPT_AES1_IV1_IV_Pos) /!< CRPT AES1_IV1: IV Mask /
sahilmgandhi	18:6a4db94011d3	7076
sahilmgandhi	18:6a4db94011d3	7077	#define CRPT_AES1_IV2_IV_Pos (0) /!< CRPT AES1_IV2: IV Position /
sahilmgandhi	18:6a4db94011d3	7078	#define CRPT_AES1_IV2_IV_Msk (0xfffffffful << CRPT_AES1_IV2_IV_Pos) /!< CRPT AES1_IV2: IV Mask /
sahilmgandhi	18:6a4db94011d3	7079
sahilmgandhi	18:6a4db94011d3	7080	#define CRPT_AES1_IV3_IV_Pos (0) /!< CRPT AES1_IV3: IV Position /
sahilmgandhi	18:6a4db94011d3	7081	#define CRPT_AES1_IV3_IV_Msk (0xfffffffful << CRPT_AES1_IV3_IV_Pos) /!< CRPT AES1_IV3: IV Mask /
sahilmgandhi	18:6a4db94011d3	7082
sahilmgandhi	18:6a4db94011d3	7083	#define CRPT_AES1_SADDR_SADDR_Pos (0) /!< CRPT AES1_SADDR: SADDR Position /
sahilmgandhi	18:6a4db94011d3	7084	#define CRPT_AES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES1_SADDR_SADDR_Pos) /!< CRPT AES1_SADDR: SADDR Mask /
sahilmgandhi	18:6a4db94011d3	7085
sahilmgandhi	18:6a4db94011d3	7086	#define CRPT_AES1_DADDR_DADDR_Pos (0) /!< CRPT AES1_DADDR: DADDR Position /
sahilmgandhi	18:6a4db94011d3	7087	#define CRPT_AES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES1_DADDR_DADDR_Pos) /!< CRPT AES1_DADDR: DADDR Mask /
sahilmgandhi	18:6a4db94011d3	7088
sahilmgandhi	18:6a4db94011d3	7089	#define CRPT_AES1_CNT_CNT_Pos (0) /!< CRPT AES1_CNT: CNT Position /
sahilmgandhi	18:6a4db94011d3	7090	#define CRPT_AES1_CNT_CNT_Msk (0xfffffffful << CRPT_AES1_CNT_CNT_Pos) /!< CRPT AES1_CNT: CNT Mask /
sahilmgandhi	18:6a4db94011d3	7091
sahilmgandhi	18:6a4db94011d3	7092	#define CRPT_AES2_KEY0_KEY_Pos (0) /!< CRPT AES2_KEY0: KEY Position /
sahilmgandhi	18:6a4db94011d3	7093	#define CRPT_AES2_KEY0_KEY_Msk (0xfffffffful << CRPT_AES2_KEY0_KEY_Pos) /!< CRPT AES2_KEY0: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7094
sahilmgandhi	18:6a4db94011d3	7095	#define CRPT_AES2_KEY1_KEY_Pos (0) /!< CRPT AES2_KEY1: KEY Position /
sahilmgandhi	18:6a4db94011d3	7096	#define CRPT_AES2_KEY1_KEY_Msk (0xfffffffful << CRPT_AES2_KEY1_KEY_Pos) /!< CRPT AES2_KEY1: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7097
sahilmgandhi	18:6a4db94011d3	7098	#define CRPT_AES2_KEY2_KEY_Pos (0) /!< CRPT AES2_KEY2: KEY Position /
sahilmgandhi	18:6a4db94011d3	7099	#define CRPT_AES2_KEY2_KEY_Msk (0xfffffffful << CRPT_AES2_KEY2_KEY_Pos) /!< CRPT AES2_KEY2: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7100
sahilmgandhi	18:6a4db94011d3	7101	#define CRPT_AES2_KEY3_KEY_Pos (0) /!< CRPT AES2_KEY3: KEY Position /
sahilmgandhi	18:6a4db94011d3	7102	#define CRPT_AES2_KEY3_KEY_Msk (0xfffffffful << CRPT_AES2_KEY3_KEY_Pos) /!< CRPT AES2_KEY3: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7103
sahilmgandhi	18:6a4db94011d3	7104	#define CRPT_AES2_KEY4_KEY_Pos (0) /!< CRPT AES2_KEY4: KEY Position /
sahilmgandhi	18:6a4db94011d3	7105	#define CRPT_AES2_KEY4_KEY_Msk (0xfffffffful << CRPT_AES2_KEY4_KEY_Pos) /!< CRPT AES2_KEY4: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7106
sahilmgandhi	18:6a4db94011d3	7107	#define CRPT_AES2_KEY5_KEY_Pos (0) /!< CRPT AES2_KEY5: KEY Position /
sahilmgandhi	18:6a4db94011d3	7108	#define CRPT_AES2_KEY5_KEY_Msk (0xfffffffful << CRPT_AES2_KEY5_KEY_Pos) /!< CRPT AES2_KEY5: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7109
sahilmgandhi	18:6a4db94011d3	7110	#define CRPT_AES2_KEY6_KEY_Pos (0) /!< CRPT AES2_KEY6: KEY Position /
sahilmgandhi	18:6a4db94011d3	7111	#define CRPT_AES2_KEY6_KEY_Msk (0xfffffffful << CRPT_AES2_KEY6_KEY_Pos) /!< CRPT AES2_KEY6: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7112
sahilmgandhi	18:6a4db94011d3	7113	#define CRPT_AES2_KEY7_KEY_Pos (0) /!< CRPT AES2_KEY7: KEY Position /
sahilmgandhi	18:6a4db94011d3	7114	#define CRPT_AES2_KEY7_KEY_Msk (0xfffffffful << CRPT_AES2_KEY7_KEY_Pos) /!< CRPT AES2_KEY7: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7115
sahilmgandhi	18:6a4db94011d3	7116	#define CRPT_AES2_IV0_IV_Pos (0) /!< CRPT AES2_IV0: IV Position /
sahilmgandhi	18:6a4db94011d3	7117	#define CRPT_AES2_IV0_IV_Msk (0xfffffffful << CRPT_AES2_IV0_IV_Pos) /!< CRPT AES2_IV0: IV Mask /
sahilmgandhi	18:6a4db94011d3	7118
sahilmgandhi	18:6a4db94011d3	7119	#define CRPT_AES2_IV1_IV_Pos (0) /!< CRPT AES2_IV1: IV Position /
sahilmgandhi	18:6a4db94011d3	7120	#define CRPT_AES2_IV1_IV_Msk (0xfffffffful << CRPT_AES2_IV1_IV_Pos) /!< CRPT AES2_IV1: IV Mask /
sahilmgandhi	18:6a4db94011d3	7121
sahilmgandhi	18:6a4db94011d3	7122	#define CRPT_AES2_IV2_IV_Pos (0) /!< CRPT AES2_IV2: IV Position /
sahilmgandhi	18:6a4db94011d3	7123	#define CRPT_AES2_IV2_IV_Msk (0xfffffffful << CRPT_AES2_IV2_IV_Pos) /!< CRPT AES2_IV2: IV Mask /
sahilmgandhi	18:6a4db94011d3	7124
sahilmgandhi	18:6a4db94011d3	7125	#define CRPT_AES2_IV3_IV_Pos (0) /!< CRPT AES2_IV3: IV Position /
sahilmgandhi	18:6a4db94011d3	7126	#define CRPT_AES2_IV3_IV_Msk (0xfffffffful << CRPT_AES2_IV3_IV_Pos) /!< CRPT AES2_IV3: IV Mask /
sahilmgandhi	18:6a4db94011d3	7127
sahilmgandhi	18:6a4db94011d3	7128	#define CRPT_AES2_SADDR_SADDR_Pos (0) /!< CRPT AES2_SADDR: SADDR Position /
sahilmgandhi	18:6a4db94011d3	7129	#define CRPT_AES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES2_SADDR_SADDR_Pos) /!< CRPT AES2_SADDR: SADDR Mask /
sahilmgandhi	18:6a4db94011d3	7130
sahilmgandhi	18:6a4db94011d3	7131	#define CRPT_AES2_DADDR_DADDR_Pos (0) /!< CRPT AES2_DADDR: DADDR Position /
sahilmgandhi	18:6a4db94011d3	7132	#define CRPT_AES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES2_DADDR_DADDR_Pos) /!< CRPT AES2_DADDR: DADDR Mask /
sahilmgandhi	18:6a4db94011d3	7133
sahilmgandhi	18:6a4db94011d3	7134	#define CRPT_AES2_CNT_CNT_Pos (0) /!< CRPT AES2_CNT: CNT Position /
sahilmgandhi	18:6a4db94011d3	7135	#define CRPT_AES2_CNT_CNT_Msk (0xfffffffful << CRPT_AES2_CNT_CNT_Pos) /!< CRPT AES2_CNT: CNT Mask /
sahilmgandhi	18:6a4db94011d3	7136
sahilmgandhi	18:6a4db94011d3	7137	#define CRPT_AES3_KEY0_KEY_Pos (0) /!< CRPT AES3_KEY0: KEY Position /
sahilmgandhi	18:6a4db94011d3	7138	#define CRPT_AES3_KEY0_KEY_Msk (0xfffffffful << CRPT_AES3_KEY0_KEY_Pos) /!< CRPT AES3_KEY0: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7139
sahilmgandhi	18:6a4db94011d3	7140	#define CRPT_AES3_KEY1_KEY_Pos (0) /!< CRPT AES3_KEY1: KEY Position /
sahilmgandhi	18:6a4db94011d3	7141	#define CRPT_AES3_KEY1_KEY_Msk (0xfffffffful << CRPT_AES3_KEY1_KEY_Pos) /!< CRPT AES3_KEY1: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7142
sahilmgandhi	18:6a4db94011d3	7143	#define CRPT_AES3_KEY2_KEY_Pos (0) /!< CRPT AES3_KEY2: KEY Position /
sahilmgandhi	18:6a4db94011d3	7144	#define CRPT_AES3_KEY2_KEY_Msk (0xfffffffful << CRPT_AES3_KEY2_KEY_Pos) /!< CRPT AES3_KEY2: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7145
sahilmgandhi	18:6a4db94011d3	7146	#define CRPT_AES3_KEY3_KEY_Pos (0) /!< CRPT AES3_KEY3: KEY Position /
sahilmgandhi	18:6a4db94011d3	7147	#define CRPT_AES3_KEY3_KEY_Msk (0xfffffffful << CRPT_AES3_KEY3_KEY_Pos) /!< CRPT AES3_KEY3: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7148
sahilmgandhi	18:6a4db94011d3	7149	#define CRPT_AES3_KEY4_KEY_Pos (0) /!< CRPT AES3_KEY4: KEY Position /
sahilmgandhi	18:6a4db94011d3	7150	#define CRPT_AES3_KEY4_KEY_Msk (0xfffffffful << CRPT_AES3_KEY4_KEY_Pos) /!< CRPT AES3_KEY4: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7151
sahilmgandhi	18:6a4db94011d3	7152	#define CRPT_AES3_KEY5_KEY_Pos (0) /!< CRPT AES3_KEY5: KEY Position /
sahilmgandhi	18:6a4db94011d3	7153	#define CRPT_AES3_KEY5_KEY_Msk (0xfffffffful << CRPT_AES3_KEY5_KEY_Pos) /!< CRPT AES3_KEY5: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7154
sahilmgandhi	18:6a4db94011d3	7155	#define CRPT_AES3_KEY6_KEY_Pos (0) /!< CRPT AES3_KEY6: KEY Position /
sahilmgandhi	18:6a4db94011d3	7156	#define CRPT_AES3_KEY6_KEY_Msk (0xfffffffful << CRPT_AES3_KEY6_KEY_Pos) /!< CRPT AES3_KEY6: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7157
sahilmgandhi	18:6a4db94011d3	7158	#define CRPT_AES3_KEY7_KEY_Pos (0) /!< CRPT AES3_KEY7: KEY Position /
sahilmgandhi	18:6a4db94011d3	7159	#define CRPT_AES3_KEY7_KEY_Msk (0xfffffffful << CRPT_AES3_KEY7_KEY_Pos) /!< CRPT AES3_KEY7: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7160
sahilmgandhi	18:6a4db94011d3	7161	#define CRPT_AES3_IV0_IV_Pos (0) /!< CRPT AES3_IV0: IV Position /
sahilmgandhi	18:6a4db94011d3	7162	#define CRPT_AES3_IV0_IV_Msk (0xfffffffful << CRPT_AES3_IV0_IV_Pos) /!< CRPT AES3_IV0: IV Mask /
sahilmgandhi	18:6a4db94011d3	7163
sahilmgandhi	18:6a4db94011d3	7164	#define CRPT_AES3_IV1_IV_Pos (0) /!< CRPT AES3_IV1: IV Position /
sahilmgandhi	18:6a4db94011d3	7165	#define CRPT_AES3_IV1_IV_Msk (0xfffffffful << CRPT_AES3_IV1_IV_Pos) /!< CRPT AES3_IV1: IV Mask /
sahilmgandhi	18:6a4db94011d3	7166
sahilmgandhi	18:6a4db94011d3	7167	#define CRPT_AES3_IV2_IV_Pos (0) /!< CRPT AES3_IV2: IV Position /
sahilmgandhi	18:6a4db94011d3	7168	#define CRPT_AES3_IV2_IV_Msk (0xfffffffful << CRPT_AES3_IV2_IV_Pos) /!< CRPT AES3_IV2: IV Mask /
sahilmgandhi	18:6a4db94011d3	7169
sahilmgandhi	18:6a4db94011d3	7170	#define CRPT_AES3_IV3_IV_Pos (0) /!< CRPT AES3_IV3: IV Position /
sahilmgandhi	18:6a4db94011d3	7171	#define CRPT_AES3_IV3_IV_Msk (0xfffffffful << CRPT_AES3_IV3_IV_Pos) /!< CRPT AES3_IV3: IV Mask /
sahilmgandhi	18:6a4db94011d3	7172
sahilmgandhi	18:6a4db94011d3	7173	#define CRPT_AES3_SADDR_SADDR_Pos (0) /!< CRPT AES3_SADDR: SADDR Position /
sahilmgandhi	18:6a4db94011d3	7174	#define CRPT_AES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES3_SADDR_SADDR_Pos) /!< CRPT AES3_SADDR: SADDR Mask /
sahilmgandhi	18:6a4db94011d3	7175
sahilmgandhi	18:6a4db94011d3	7176	#define CRPT_AES3_DADDR_DADDR_Pos (0) /!< CRPT AES3_DADDR: DADDR Position /
sahilmgandhi	18:6a4db94011d3	7177	#define CRPT_AES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES3_DADDR_DADDR_Pos) /!< CRPT AES3_DADDR: DADDR Mask /
sahilmgandhi	18:6a4db94011d3	7178
sahilmgandhi	18:6a4db94011d3	7179	#define CRPT_AES3_CNT_CNT_Pos (0) /!< CRPT AES3_CNT: CNT Position /
sahilmgandhi	18:6a4db94011d3	7180	#define CRPT_AES3_CNT_CNT_Msk (0xfffffffful << CRPT_AES3_CNT_CNT_Pos) /!< CRPT AES3_CNT: CNT Mask /
sahilmgandhi	18:6a4db94011d3	7181
sahilmgandhi	18:6a4db94011d3	7182	#define CRPT_TDES_CTL_START_Pos (0) /!< CRPT TDES_CTL: START Position /
sahilmgandhi	18:6a4db94011d3	7183	#define CRPT_TDES_CTL_START_Msk (0x1ul << CRPT_TDES_CTL_START_Pos) /!< CRPT TDES_CTL: START Mask /
sahilmgandhi	18:6a4db94011d3	7184
sahilmgandhi	18:6a4db94011d3	7185	#define CRPT_TDES_CTL_STOP_Pos (1) /!< CRPT TDES_CTL: STOP Position /
sahilmgandhi	18:6a4db94011d3	7186	#define CRPT_TDES_CTL_STOP_Msk (0x1ul << CRPT_TDES_CTL_STOP_Pos) /!< CRPT TDES_CTL: STOP Mask /
sahilmgandhi	18:6a4db94011d3	7187
sahilmgandhi	18:6a4db94011d3	7188	#define CRPT_TDES_CTL_TMODE_Pos (2) /!< CRPT TDES_CTL: TMODE Position /
sahilmgandhi	18:6a4db94011d3	7189	#define CRPT_TDES_CTL_TMODE_Msk (0x1ul << CRPT_TDES_CTL_TMODE_Pos) /!< CRPT TDES_CTL: TMODE Mask /
sahilmgandhi	18:6a4db94011d3	7190
sahilmgandhi	18:6a4db94011d3	7191	#define CRPT_TDES_CTL_3KEYS_Pos (3) /!< CRPT TDES_CTL: 3KEYS Position /
sahilmgandhi	18:6a4db94011d3	7192	#define CRPT_TDES_CTL_3KEYS_Msk (0x1ul << CRPT_TDES_CTL_3KEYS_Pos) /!< CRPT TDES_CTL: 3KEYS Mask /
sahilmgandhi	18:6a4db94011d3	7193
sahilmgandhi	18:6a4db94011d3	7194	#define CRPT_TDES_CTL_DMALAST_Pos (5) /!< CRPT TDES_CTL: DMALAST Position /
sahilmgandhi	18:6a4db94011d3	7195	#define CRPT_TDES_CTL_DMALAST_Msk (0x1ul << CRPT_TDES_CTL_DMALAST_Pos) /!< CRPT TDES_CTL: DMALAST Mask /
sahilmgandhi	18:6a4db94011d3	7196
sahilmgandhi	18:6a4db94011d3	7197	#define CRPT_TDES_CTL_DMACSCAD_Pos (6) /!< CRPT TDES_CTL: DMACSCAD Position /
sahilmgandhi	18:6a4db94011d3	7198	#define CRPT_TDES_CTL_DMACSCAD_Msk (0x1ul << CRPT_TDES_CTL_DMACSCAD_Pos) /!< CRPT TDES_CTL: DMACSCAD Mask /
sahilmgandhi	18:6a4db94011d3	7199
sahilmgandhi	18:6a4db94011d3	7200	#define CRPT_TDES_CTL_DMAEN_Pos (7) /!< CRPT TDES_CTL: DMAEN Position /
sahilmgandhi	18:6a4db94011d3	7201	#define CRPT_TDES_CTL_DMAEN_Msk (0x1ul << CRPT_TDES_CTL_DMAEN_Pos) /!< CRPT TDES_CTL: DMAEN Mask /
sahilmgandhi	18:6a4db94011d3	7202
sahilmgandhi	18:6a4db94011d3	7203	#define CRPT_TDES_CTL_OPMODE_Pos (8) /!< CRPT TDES_CTL: OPMODE Position /
sahilmgandhi	18:6a4db94011d3	7204	#define CRPT_TDES_CTL_OPMODE_Msk (0x7ul << CRPT_TDES_CTL_OPMODE_Pos) /!< CRPT TDES_CTL: OPMODE Mask /
sahilmgandhi	18:6a4db94011d3	7205
sahilmgandhi	18:6a4db94011d3	7206	#define CRPT_TDES_CTL_ENCRPT_Pos (16) /!< CRPT TDES_CTL: ENCRPT Position /
sahilmgandhi	18:6a4db94011d3	7207	#define CRPT_TDES_CTL_ENCRPT_Msk (0x1ul << CRPT_TDES_CTL_ENCRPT_Pos) /!< CRPT TDES_CTL: ENCRPT Mask /
sahilmgandhi	18:6a4db94011d3	7208
sahilmgandhi	18:6a4db94011d3	7209	#define CRPT_TDES_CTL_BLKSWAP_Pos (21) /!< CRPT TDES_CTL: BLKSWAP Position /
sahilmgandhi	18:6a4db94011d3	7210	#define CRPT_TDES_CTL_BLKSWAP_Msk (0x1ul << CRPT_TDES_CTL_BLKSWAP_Pos) /!< CRPT TDES_CTL: BLKSWAP Mask /
sahilmgandhi	18:6a4db94011d3	7211
sahilmgandhi	18:6a4db94011d3	7212	#define CRPT_TDES_CTL_OUTSWAP_Pos (22) /!< CRPT TDES_CTL: OUTSWAP Position /
sahilmgandhi	18:6a4db94011d3	7213	#define CRPT_TDES_CTL_OUTSWAP_Msk (0x1ul << CRPT_TDES_CTL_OUTSWAP_Pos) /!< CRPT TDES_CTL: OUTSWAP Mask /
sahilmgandhi	18:6a4db94011d3	7214
sahilmgandhi	18:6a4db94011d3	7215	#define CRPT_TDES_CTL_INSWAP_Pos (23) /!< CRPT TDES_CTL: INSWAP Position /
sahilmgandhi	18:6a4db94011d3	7216	#define CRPT_TDES_CTL_INSWAP_Msk (0x1ul << CRPT_TDES_CTL_INSWAP_Pos) /!< CRPT TDES_CTL: INSWAP Mask /
sahilmgandhi	18:6a4db94011d3	7217
sahilmgandhi	18:6a4db94011d3	7218	#define CRPT_TDES_CTL_CHANNEL_Pos (24) /!< CRPT TDES_CTL: CHANNEL Position /
sahilmgandhi	18:6a4db94011d3	7219	#define CRPT_TDES_CTL_CHANNEL_Msk (0x3ul << CRPT_TDES_CTL_CHANNEL_Pos) /!< CRPT TDES_CTL: CHANNEL Mask /
sahilmgandhi	18:6a4db94011d3	7220
sahilmgandhi	18:6a4db94011d3	7221	#define CRPT_TDES_CTL_KEYUNPRT_Pos (26) /!< CRPT TDES_CTL: KEYUNPRT Position /
sahilmgandhi	18:6a4db94011d3	7222	#define CRPT_TDES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_TDES_CTL_KEYUNPRT_Pos) /!< CRPT TDES_CTL: KEYUNPRT Mask /
sahilmgandhi	18:6a4db94011d3	7223
sahilmgandhi	18:6a4db94011d3	7224	#define CRPT_TDES_CTL_KEYPRT_Pos (31) /!< CRPT TDES_CTL: KEYPRT Position /
sahilmgandhi	18:6a4db94011d3	7225	#define CRPT_TDES_CTL_KEYPRT_Msk (0x1ul << CRPT_TDES_CTL_KEYPRT_Pos) /!< CRPT TDES_CTL: KEYPRT Mask /
sahilmgandhi	18:6a4db94011d3	7226
sahilmgandhi	18:6a4db94011d3	7227	#define CRPT_TDES_STS_BUSY_Pos (0) /!< CRPT TDES_STS: BUSY Position /
sahilmgandhi	18:6a4db94011d3	7228	#define CRPT_TDES_STS_BUSY_Msk (0x1ul << CRPT_TDES_STS_BUSY_Pos) /!< CRPT TDES_STS: BUSY Mask /
sahilmgandhi	18:6a4db94011d3	7229
sahilmgandhi	18:6a4db94011d3	7230	#define CRPT_TDES_STS_INBUFEMPTY_Pos (8) /!< CRPT TDES_STS: INBUFEMPTY Position /
sahilmgandhi	18:6a4db94011d3	7231	#define CRPT_TDES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_INBUFEMPTY_Pos) /!< CRPT TDES_STS: INBUFEMPTY Mask /
sahilmgandhi	18:6a4db94011d3	7232
sahilmgandhi	18:6a4db94011d3	7233	#define CRPT_TDES_STS_INBUFFULL_Pos (9) /!< CRPT TDES_STS: INBUFFULL Position /
sahilmgandhi	18:6a4db94011d3	7234	#define CRPT_TDES_STS_INBUFFULL_Msk (0x1ul << CRPT_TDES_STS_INBUFFULL_Pos) /!< CRPT TDES_STS: INBUFFULL Mask /
sahilmgandhi	18:6a4db94011d3	7235
sahilmgandhi	18:6a4db94011d3	7236	#define CRPT_TDES_STS_INBUFERR_Pos (10) /!< CRPT TDES_STS: INBUFERR Position /
sahilmgandhi	18:6a4db94011d3	7237	#define CRPT_TDES_STS_INBUFERR_Msk (0x1ul << CRPT_TDES_STS_INBUFERR_Pos) /!< CRPT TDES_STS: INBUFERR Mask /
sahilmgandhi	18:6a4db94011d3	7238
sahilmgandhi	18:6a4db94011d3	7239	#define CRPT_TDES_STS_OUTBUFEMPTY_Pos (16) /!< CRPT TDES_STS: OUTBUFEMPTY Position /
sahilmgandhi	18:6a4db94011d3	7240	#define CRPT_TDES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_OUTBUFEMPTY_Pos) /!< CRPT TDES_STS: OUTBUFEMPTY Mask /
sahilmgandhi	18:6a4db94011d3	7241
sahilmgandhi	18:6a4db94011d3	7242	#define CRPT_TDES_STS_OUTBUFFULL_Pos (17) /!< CRPT TDES_STS: OUTBUFFULL Position /
sahilmgandhi	18:6a4db94011d3	7243	#define CRPT_TDES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_TDES_STS_OUTBUFFULL_Pos) /!< CRPT TDES_STS: OUTBUFFULL Mask /
sahilmgandhi	18:6a4db94011d3	7244
sahilmgandhi	18:6a4db94011d3	7245	#define CRPT_TDES_STS_OUTBUFERR_Pos (18) /!< CRPT TDES_STS: OUTBUFERR Position /
sahilmgandhi	18:6a4db94011d3	7246	#define CRPT_TDES_STS_OUTBUFERR_Msk (0x1ul << CRPT_TDES_STS_OUTBUFERR_Pos) /!< CRPT TDES_STS: OUTBUFERR Mask /
sahilmgandhi	18:6a4db94011d3	7247
sahilmgandhi	18:6a4db94011d3	7248	#define CRPT_TDES_STS_BUSERR_Pos (20) /!< CRPT TDES_STS: BUSERR Position /
sahilmgandhi	18:6a4db94011d3	7249	#define CRPT_TDES_STS_BUSERR_Msk (0x1ul << CRPT_TDES_STS_BUSERR_Pos) /!< CRPT TDES_STS: BUSERR Mask /
sahilmgandhi	18:6a4db94011d3	7250
sahilmgandhi	18:6a4db94011d3	7251	#define CRPT_TDES0_KEY1H_KEY_Pos (0) /!< CRPT TDES0_KEY1H: KEY Position /
sahilmgandhi	18:6a4db94011d3	7252	#define CRPT_TDES0_KEY1H_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY1H_KEY_Pos) /!< CRPT TDES0_KEY1H: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7253
sahilmgandhi	18:6a4db94011d3	7254	#define CRPT_TDES0_KEY1L_KEY_Pos (0) /!< CRPT TDES0_KEY1L: KEY Position /
sahilmgandhi	18:6a4db94011d3	7255	#define CRPT_TDES0_KEY1L_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY1L_KEY_Pos) /!< CRPT TDES0_KEY1L: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7256
sahilmgandhi	18:6a4db94011d3	7257	#define CRPT_TDES0_KEY2H_KEY_Pos (0) /!< CRPT TDES0_KEY2H: KEY Position /
sahilmgandhi	18:6a4db94011d3	7258	#define CRPT_TDES0_KEY2H_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY2H_KEY_Pos) /!< CRPT TDES0_KEY2H: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7259
sahilmgandhi	18:6a4db94011d3	7260	#define CRPT_TDES0_KEY2L_KEY_Pos (0) /!< CRPT TDES0_KEY2L: KEY Position /
sahilmgandhi	18:6a4db94011d3	7261	#define CRPT_TDES0_KEY2L_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY2L_KEY_Pos) /!< CRPT TDES0_KEY2L: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7262
sahilmgandhi	18:6a4db94011d3	7263	#define CRPT_TDES0_KEY3H_KEY_Pos (0) /!< CRPT TDES0_KEY3H: KEY Position /
sahilmgandhi	18:6a4db94011d3	7264	#define CRPT_TDES0_KEY3H_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY3H_KEY_Pos) /!< CRPT TDES0_KEY3H: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7265
sahilmgandhi	18:6a4db94011d3	7266	#define CRPT_TDES0_KEY3L_KEY_Pos (0) /!< CRPT TDES0_KEY3L: KEY Position /
sahilmgandhi	18:6a4db94011d3	7267	#define CRPT_TDES0_KEY3L_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY3L_KEY_Pos) /!< CRPT TDES0_KEY3L: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7268
sahilmgandhi	18:6a4db94011d3	7269	#define CRPT_TDES0_IVH_IV_Pos (0) /!< CRPT TDES0_IVH: IV Position /
sahilmgandhi	18:6a4db94011d3	7270	#define CRPT_TDES0_IVH_IV_Msk (0xfffffffful << CRPT_TDES0_IVH_IV_Pos) /!< CRPT TDES0_IVH: IV Mask /
sahilmgandhi	18:6a4db94011d3	7271
sahilmgandhi	18:6a4db94011d3	7272	#define CRPT_TDES0_IVL_IV_Pos (0) /!< CRPT TDES0_IVL: IV Position /
sahilmgandhi	18:6a4db94011d3	7273	#define CRPT_TDES0_IVL_IV_Msk (0xfffffffful << CRPT_TDES0_IVL_IV_Pos) /!< CRPT TDES0_IVL: IV Mask /
sahilmgandhi	18:6a4db94011d3	7274
sahilmgandhi	18:6a4db94011d3	7275	#define CRPT_TDES0_SADDR_SADDR_Pos (0) /!< CRPT TDES0_SADDR: SADDR Position /
sahilmgandhi	18:6a4db94011d3	7276	#define CRPT_TDES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES0_SADDR_SADDR_Pos) /!< CRPT TDES0_SADDR: SADDR Mask /
sahilmgandhi	18:6a4db94011d3	7277
sahilmgandhi	18:6a4db94011d3	7278	#define CRPT_TDES0_DADDR_DADDR_Pos (0) /!< CRPT TDES0_DADDR: DADDR Position /
sahilmgandhi	18:6a4db94011d3	7279	#define CRPT_TDES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES0_DADDR_DADDR_Pos) /!< CRPT TDES0_DADDR: DADDR Mask /
sahilmgandhi	18:6a4db94011d3	7280
sahilmgandhi	18:6a4db94011d3	7281	#define CRPT_TDES0_CNT_CNT_Pos (0) /!< CRPT TDES0_CNT: CNT Position /
sahilmgandhi	18:6a4db94011d3	7282	#define CRPT_TDES0_CNT_CNT_Msk (0xfffffffful << CRPT_TDES0_CNT_CNT_Pos) /!< CRPT TDES0_CNT: CNT Mask /
sahilmgandhi	18:6a4db94011d3	7283
sahilmgandhi	18:6a4db94011d3	7284	#define CRPT_TDES_DATIN_DATIN_Pos (0) /!< CRPT TDES_DATIN: DATIN Position /
sahilmgandhi	18:6a4db94011d3	7285	#define CRPT_TDES_DATIN_DATIN_Msk (0xfffffffful << CRPT_TDES_DATIN_DATIN_Pos) /!< CRPT TDES_DATIN: DATIN Mask /
sahilmgandhi	18:6a4db94011d3	7286
sahilmgandhi	18:6a4db94011d3	7287	#define CRPT_TDES_DATOUT_DATOUT_Pos (0) /!< CRPT TDES_DATOUT: DATOUT Position /
sahilmgandhi	18:6a4db94011d3	7288	#define CRPT_TDES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_TDES_DATOUT_DATOUT_Pos) /!< CRPT TDES_DATOUT: DATOUT Mask /
sahilmgandhi	18:6a4db94011d3	7289
sahilmgandhi	18:6a4db94011d3	7290	#define CRPT_TDES1_KEY1H_KEY_Pos (0) /!< CRPT TDES1_KEY1H: KEY Position /
sahilmgandhi	18:6a4db94011d3	7291	#define CRPT_TDES1_KEY1H_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY1H_KEY_Pos) /!< CRPT TDES1_KEY1H: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7292
sahilmgandhi	18:6a4db94011d3	7293	#define CRPT_TDES1_KEY1L_KEYL_Pos (0) /!< CRPT TDES1_KEY1L: KEY Position /
sahilmgandhi	18:6a4db94011d3	7294	#define CRPT_TDES1_KEY1L_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY1L_KEY_Pos) /!< CRPT TDES1_KEY1L: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7295
sahilmgandhi	18:6a4db94011d3	7296	#define CRPT_TDES1_KEY2H_KEY_Pos (0) /!< CRPT TDES1_KEY2H: KEY Position /
sahilmgandhi	18:6a4db94011d3	7297	#define CRPT_TDES1_KEY2H_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY2H_KEY_Pos) /!< CRPT TDES1_KEY2H: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7298
sahilmgandhi	18:6a4db94011d3	7299	#define CRPT_TDES1_KEY2L_KEY_Pos (0) /!< CRPT TDES1_KEY2L: KEY Position /
sahilmgandhi	18:6a4db94011d3	7300	#define CRPT_TDES1_KEY2L_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY2L_KEY_Pos) /!< CRPT TDES1_KEY2L: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7301
sahilmgandhi	18:6a4db94011d3	7302	#define CRPT_TDES1_KEY3H_KEY_Pos (0) /!< CRPT TDES1_KEY3H: KEY Position /
sahilmgandhi	18:6a4db94011d3	7303	#define CRPT_TDES1_KEY3H_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY3H_KEY_Pos) /!< CRPT TDES1_KEY3H: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7304
sahilmgandhi	18:6a4db94011d3	7305	#define CRPT_TDES1_KEY3L_KEY_Pos (0) /!< CRPT TDES1_KEY3L: KEY Position /
sahilmgandhi	18:6a4db94011d3	7306	#define CRPT_TDES1_KEY3L_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY3L_KEY_Pos) /!< CRPT TDES1_KEY3L: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7307
sahilmgandhi	18:6a4db94011d3	7308	#define CRPT_TDES1_IVH_IV_Pos (0) /!< CRPT TDES1_IVH: IV Position /
sahilmgandhi	18:6a4db94011d3	7309	#define CRPT_TDES1_IVH_IV_Msk (0xfffffffful << CRPT_TDES1_IVH_IV_Pos) /!< CRPT TDES1_IVH: IV Mask /
sahilmgandhi	18:6a4db94011d3	7310
sahilmgandhi	18:6a4db94011d3	7311	#define CRPT_TDES1_IVL_IV_Pos (0) /!< CRPT TDES1_IVL: IV Position /
sahilmgandhi	18:6a4db94011d3	7312	#define CRPT_TDES1_IVL_IV_Msk (0xfffffffful << CRPT_TDES1_IVL_IV_Pos) /!< CRPT TDES1_IVL: IV Mask /
sahilmgandhi	18:6a4db94011d3	7313
sahilmgandhi	18:6a4db94011d3	7314	#define CRPT_TDES1_SADDR_SADDR_Pos (0) /!< CRPT TDES1_SADDR: SADDR Position /
sahilmgandhi	18:6a4db94011d3	7315	#define CRPT_TDES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES1_SADDR_SADDR_Pos) /!< CRPT TDES1_SADDR: SADDR Mask /
sahilmgandhi	18:6a4db94011d3	7316
sahilmgandhi	18:6a4db94011d3	7317	#define CRPT_TDES1_DADDR_DADDR_Pos (0) /!< CRPT TDES1_DADDR: DADDR Position /
sahilmgandhi	18:6a4db94011d3	7318	#define CRPT_TDES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES1_DADDR_DADDR_Pos) /!< CRPT TDES1_DADDR: DADDR Mask /
sahilmgandhi	18:6a4db94011d3	7319
sahilmgandhi	18:6a4db94011d3	7320	#define CRPT_TDES1_CNT_CNT_Pos (0) /!< CRPT TDES1_CNT: CNT Position /
sahilmgandhi	18:6a4db94011d3	7321	#define CRPT_TDES1_CNT_CNT_Msk (0xfffffffful << CRPT_TDES1_CNT_CNT_Pos) /!< CRPT TDES1_CNT: CNT Mask /
sahilmgandhi	18:6a4db94011d3	7322
sahilmgandhi	18:6a4db94011d3	7323	#define CRPT_TDES2_KEY1H_KEY_Pos (0) /!< CRPT TDES2_KEY1H: KEY Position /
sahilmgandhi	18:6a4db94011d3	7324	#define CRPT_TDES2_KEY1H_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY1H_KEY_Pos) /!< CRPT TDES2_KEY1H: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7325
sahilmgandhi	18:6a4db94011d3	7326	#define CRPT_TDES2_KEY1L_KEY_Pos (0) /!< CRPT TDES2_KEY1L: KEY Position /
sahilmgandhi	18:6a4db94011d3	7327	#define CRPT_TDES2_KEY1L_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY1L_KEY_Pos) /!< CRPT TDES2_KEY1L: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7328
sahilmgandhi	18:6a4db94011d3	7329	#define CRPT_TDES2_KEY2H_KEY_Pos (0) /!< CRPT TDES2_KEY2H: KEY Position /
sahilmgandhi	18:6a4db94011d3	7330	#define CRPT_TDES2_KEY2H_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY2H_KEY_Pos) /!< CRPT TDES2_KEY2H: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7331
sahilmgandhi	18:6a4db94011d3	7332	#define CRPT_TDES2_KEY2L_KEY_Pos (0) /!< CRPT TDES2_KEY2L: KEY Position /
sahilmgandhi	18:6a4db94011d3	7333	#define CRPT_TDES2_KEY2L_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY2L_KEY_Pos) /!< CRPT TDES2_KEY2L: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7334
sahilmgandhi	18:6a4db94011d3	7335	#define CRPT_TDES2_KEY3H_KEY_Pos (0) /!< CRPT TDES2_KEY3H: KEY Position /
sahilmgandhi	18:6a4db94011d3	7336	#define CRPT_TDES2_KEY3H_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY3H_KEY_Pos) /!< CRPT TDES2_KEY3H: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7337
sahilmgandhi	18:6a4db94011d3	7338	#define CRPT_TDES2_KEY3L_KEY_Pos (0) /!< CRPT TDES2_KEY3L: KEY Position /
sahilmgandhi	18:6a4db94011d3	7339	#define CRPT_TDES2_KEY3L_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY3L_KEY_Pos) /!< CRPT TDES2_KEY3L: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7340
sahilmgandhi	18:6a4db94011d3	7341	#define CRPT_TDES2_IVH_IV_Pos (0) /!< CRPT TDES2_IVH: IV Position /
sahilmgandhi	18:6a4db94011d3	7342	#define CRPT_TDES2_IVH_IV_Msk (0xfffffffful << CRPT_TDES2_IVH_IV_Pos) /!< CRPT TDES2_IVH: IV Mask /
sahilmgandhi	18:6a4db94011d3	7343
sahilmgandhi	18:6a4db94011d3	7344	#define CRPT_TDES2_IVL_IV_Pos (0) /!< CRPT TDES2_IVL: IV Position /
sahilmgandhi	18:6a4db94011d3	7345	#define CRPT_TDES2_IVL_IV_Msk (0xfffffffful << CRPT_TDES2_IVL_IV_Pos) /!< CRPT TDES2_IVL: IV Mask /
sahilmgandhi	18:6a4db94011d3	7346
sahilmgandhi	18:6a4db94011d3	7347	#define CRPT_TDES2_SADDR_SADDR_Pos (0) /!< CRPT TDES2_SADDR: SADDR Position /
sahilmgandhi	18:6a4db94011d3	7348	#define CRPT_TDES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES2_SADDR_SADDR_Pos) /!< CRPT TDES2_SADDR: SADDR Mask /
sahilmgandhi	18:6a4db94011d3	7349
sahilmgandhi	18:6a4db94011d3	7350	#define CRPT_TDES2_DADDR_DADDR_Pos (0) /!< CRPT TDES2_DADDR: DADDR Position /
sahilmgandhi	18:6a4db94011d3	7351	#define CRPT_TDES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES2_DADDR_DADDR_Pos) /!< CRPT TDES2_DADDR: DADDR Mask /
sahilmgandhi	18:6a4db94011d3	7352
sahilmgandhi	18:6a4db94011d3	7353	#define CRPT_TDES2_CNT_CNT_Pos (0) /!< CRPT TDES2_CNT: CNT Position /
sahilmgandhi	18:6a4db94011d3	7354	#define CRPT_TDES2_CNT_CNT_Msk (0xfffffffful << CRPT_TDES2_CNT_CNT_Pos) /!< CRPT TDES2_CNT: CNT Mask /
sahilmgandhi	18:6a4db94011d3	7355
sahilmgandhi	18:6a4db94011d3	7356	#define CRPT_TDES3_KEY1H_KEY_Pos (0) /!< CRPT TDES3_KEY1H: KEY Position /
sahilmgandhi	18:6a4db94011d3	7357	#define CRPT_TDES3_KEY1H_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY1H_KEY_Pos) /!< CRPT TDES3_KEY1H: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7358
sahilmgandhi	18:6a4db94011d3	7359	#define CRPT_TDES3_KEY1L_KEY_Pos (0) /!< CRPT TDES3_KEY1L: KEY Position /
sahilmgandhi	18:6a4db94011d3	7360	#define CRPT_TDES3_KEY1L_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY1L_KEY_Pos) /!< CRPT TDES3_KEY1L: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7361
sahilmgandhi	18:6a4db94011d3	7362	#define CRPT_TDES3_KEY2H_KEY_Pos (0) /!< CRPT TDES3_KEY2H: KEY Position /
sahilmgandhi	18:6a4db94011d3	7363	#define CRPT_TDES3_KEY2H_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY2H_KEY_Pos) /!< CRPT TDES3_KEY2H: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7364
sahilmgandhi	18:6a4db94011d3	7365	#define CRPT_TDES3_KEY2L_KEY_Pos (0) /!< CRPT TDES3_KEY2L: KEY Position /
sahilmgandhi	18:6a4db94011d3	7366	#define CRPT_TDES3_KEY2L_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY2L_KEY_Pos) /!< CRPT TDES3_KEY2L: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7367
sahilmgandhi	18:6a4db94011d3	7368	#define CRPT_TDES3_KEY3H_KEY_Pos (0) /!< CRPT TDES3_KEY3H: KEY Position /
sahilmgandhi	18:6a4db94011d3	7369	#define CRPT_TDES3_KEY3H_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY3H_KEY_Pos) /!< CRPT TDES3_KEY3H: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7370
sahilmgandhi	18:6a4db94011d3	7371	#define CRPT_TDES3_KEY3L_KEY_Pos (0) /!< CRPT TDES3_KEY3L: KEY Position /
sahilmgandhi	18:6a4db94011d3	7372	#define CRPT_TDES3_KEY3L_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY3L_KEY_Pos) /!< CRPT TDES3_KEY3L: KEY Mask /
sahilmgandhi	18:6a4db94011d3	7373
sahilmgandhi	18:6a4db94011d3	7374	#define CRPT_TDES3_IVH_IV_Pos (0) /!< CRPT TDES3_IVH: IV Position /
sahilmgandhi	18:6a4db94011d3	7375	#define CRPT_TDES3_IVH_IV_Msk (0xfffffffful << CRPT_TDES3_IVH_IV_Pos) /!< CRPT TDES3_IVH: IV Mask /
sahilmgandhi	18:6a4db94011d3	7376
sahilmgandhi	18:6a4db94011d3	7377	#define CRPT_TDES3_IVL_IV_Pos (0) /!< CRPT TDES3_IVL: IV Position /
sahilmgandhi	18:6a4db94011d3	7378	#define CRPT_TDES3_IVL_IV_Msk (0xfffffffful << CRPT_TDES3_IVL_IV_Pos) /!< CRPT TDES3_IVL: IV Mask /
sahilmgandhi	18:6a4db94011d3	7379
sahilmgandhi	18:6a4db94011d3	7380	#define CRPT_TDES3_SADDR_SADDR_Pos (0) /!< CRPT TDES3_SADDR: SADDR Position /
sahilmgandhi	18:6a4db94011d3	7381	#define CRPT_TDES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES3_SADDR_SADDR_Pos) /!< CRPT TDES3_SADDR: SADDR Mask /
sahilmgandhi	18:6a4db94011d3	7382
sahilmgandhi	18:6a4db94011d3	7383	#define CRPT_TDES3_DADDR_DADDR_Pos (0) /!< CRPT TDES3_DADDR: DADDR Position /
sahilmgandhi	18:6a4db94011d3	7384	#define CRPT_TDES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES3_DADDR_DADDR_Pos) /!< CRPT TDES3_DADDR: DADDR Mask /
sahilmgandhi	18:6a4db94011d3	7385
sahilmgandhi	18:6a4db94011d3	7386	#define CRPT_TDES3_CNT_CNT_Pos (0) /!< CRPT TDES3_CNT: CNT Position /
sahilmgandhi	18:6a4db94011d3	7387	#define CRPT_TDES3_CNT_CNT_Msk (0xfffffffful << CRPT_TDES3_CNT_CNT_Pos) /!< CRPT TDES3_CNT: CNT Mask /
sahilmgandhi	18:6a4db94011d3	7388
sahilmgandhi	18:6a4db94011d3	7389	#define CRPT_SHA_CTL_START_Pos (0) /!< CRPT SHA_CTL: START Position /
sahilmgandhi	18:6a4db94011d3	7390	#define CRPT_SHA_CTL_START_Msk (0x1ul << CRPT_SHA_CTL_START_Pos) /!< CRPT SHA_CTL: START Mask /
sahilmgandhi	18:6a4db94011d3	7391
sahilmgandhi	18:6a4db94011d3	7392	#define CRPT_SHA_CTL_STOP_Pos (1) /!< CRPT SHA_CTL: STOP Position /
sahilmgandhi	18:6a4db94011d3	7393	#define CRPT_SHA_CTL_STOP_Msk (0x1ul << CRPT_SHA_CTL_STOP_Pos) /!< CRPT SHA_CTL: STOP Mask /
sahilmgandhi	18:6a4db94011d3	7394
sahilmgandhi	18:6a4db94011d3	7395	#define CRPT_SHA_CTL_DMALAST_Pos (5) /!< CRPT SHA_CTL: DMALAST Position /
sahilmgandhi	18:6a4db94011d3	7396	#define CRPT_SHA_CTL_DMALAST_Msk (0x1ul << CRPT_SHA_CTL_DMALAST_Pos) /!< CRPT SHA_CTL: DMALAST Mask /
sahilmgandhi	18:6a4db94011d3	7397
sahilmgandhi	18:6a4db94011d3	7398	#define CRPT_SHA_CTL_DMAEN_Pos (7) /!< CRPT SHA_CTL: DMAEN Position /
sahilmgandhi	18:6a4db94011d3	7399	#define CRPT_SHA_CTL_DMAEN_Msk (0x1ul << CRPT_SHA_CTL_DMAEN_Pos) /!< CRPT SHA_CTL: DMAEN Mask /
sahilmgandhi	18:6a4db94011d3	7400
sahilmgandhi	18:6a4db94011d3	7401	#define CRPT_SHA_CTL_OPMODE_Pos (8) /!< CRPT SHA_CTL: OPMODE Position /
sahilmgandhi	18:6a4db94011d3	7402	#define CRPT_SHA_CTL_OPMODE_Msk (0x7ul << CRPT_SHA_CTL_OPMODE_Pos) /!< CRPT SHA_CTL: OPMODE Mask /
sahilmgandhi	18:6a4db94011d3	7403
sahilmgandhi	18:6a4db94011d3	7404	#define CRPT_SHA_CTL_OUTSWAP_Pos (22) /!< CRPT SHA_CTL: OUTSWAP Position /
sahilmgandhi	18:6a4db94011d3	7405	#define CRPT_SHA_CTL_OUTSWAP_Msk (0x1ul << CRPT_SHA_CTL_OUTSWAP_Pos) /!< CRPT SHA_CTL: OUTSWAP Mask /
sahilmgandhi	18:6a4db94011d3	7406
sahilmgandhi	18:6a4db94011d3	7407	#define CRPT_SHA_CTL_INSWAP_Pos (23) /!< CRPT SHA_CTL: INSWAP Position /
sahilmgandhi	18:6a4db94011d3	7408	#define CRPT_SHA_CTL_INSWAP_Msk (0x1ul << CRPT_SHA_CTL_INSWAP_Pos) /!< CRPT SHA_CTL: INSWAP Mask /
sahilmgandhi	18:6a4db94011d3	7409
sahilmgandhi	18:6a4db94011d3	7410	#define CRPT_SHA_STS_BUSY_Pos (0) /!< CRPT SHA_STS: BUSY Position /
sahilmgandhi	18:6a4db94011d3	7411	#define CRPT_SHA_STS_BUSY_Msk (0x1ul << CRPT_SHA_STS_BUSY_Pos) /!< CRPT SHA_STS: BUSY Mask /
sahilmgandhi	18:6a4db94011d3	7412
sahilmgandhi	18:6a4db94011d3	7413	#define CRPT_SHA_STS_DMABUSY_Pos (1) /!< CRPT SHA_STS: DMABUSY Position /
sahilmgandhi	18:6a4db94011d3	7414	#define CRPT_SHA_STS_DMABUSY_Msk (0x1ul << CRPT_SHA_STS_DMABUSY_Pos) /!< CRPT SHA_STS: DMABUSY Mask /
sahilmgandhi	18:6a4db94011d3	7415
sahilmgandhi	18:6a4db94011d3	7416	#define CRPT_SHA_STS_DMAERR_Pos (8) /!< CRPT SHA_STS: DMAERR Position /
sahilmgandhi	18:6a4db94011d3	7417	#define CRPT_SHA_STS_DMAERR_Msk (0x1ul << CRPT_SHA_STS_DMAERR_Pos) /!< CRPT SHA_STS: DMAERR Mask /
sahilmgandhi	18:6a4db94011d3	7418
sahilmgandhi	18:6a4db94011d3	7419	#define CRPT_SHA_STS_DATINREQ_Pos (16) /!< CRPT SHA_STS: DATINREQ Position /
sahilmgandhi	18:6a4db94011d3	7420	#define CRPT_SHA_STS_DATINREQ_Msk (0x1ul << CRPT_SHA_STS_DATINREQ_Pos) /!< CRPT SHA_STS: DATINREQ Mask /
sahilmgandhi	18:6a4db94011d3	7421
sahilmgandhi	18:6a4db94011d3	7422	#define CRPT_SHA_DGST0_DGST_Pos (0) /!< CRPT SHA_DGST0: DGST Position /
sahilmgandhi	18:6a4db94011d3	7423	#define CRPT_SHA_DGST0_DGST_Msk (0xfffffffful << CRPT_SHA_DGST0_DGST_Pos) /!< CRPT SHA_DGST0: DGST Mask /
sahilmgandhi	18:6a4db94011d3	7424
sahilmgandhi	18:6a4db94011d3	7425	#define CRPT_SHA_DGST1_DGST_Pos (0) /!< CRPT SHA_DGST1: DGST Position /
sahilmgandhi	18:6a4db94011d3	7426	#define CRPT_SHA_DGST1_DGST_Msk (0xfffffffful << CRPT_SHA_DGST1_DGST_Pos) /!< CRPT SHA_DGST1: DGST Mask /
sahilmgandhi	18:6a4db94011d3	7427
sahilmgandhi	18:6a4db94011d3	7428	#define CRPT_SHA_DGST2_DGST_Pos (0) /!< CRPT SHA_DGST2: DGST Position /
sahilmgandhi	18:6a4db94011d3	7429	#define CRPT_SHA_DGST2_DGST_Msk (0xfffffffful << CRPT_SHA_DGST2_DGST_Pos) /!< CRPT SHA_DGST2: DGST Mask /
sahilmgandhi	18:6a4db94011d3	7430
sahilmgandhi	18:6a4db94011d3	7431	#define CRPT_SHA_DGST3_DGST_Pos (0) /!< CRPT SHA_DGST3: DGST Position /
sahilmgandhi	18:6a4db94011d3	7432	#define CRPT_SHA_DGST3_DGST_Msk (0xfffffffful << CRPT_SHA_DGST3_DGST_Pos) /!< CRPT SHA_DGST3: DGST Mask /
sahilmgandhi	18:6a4db94011d3	7433
sahilmgandhi	18:6a4db94011d3	7434	#define CRPT_SHA_DGST4_DGST_Pos (0) /!< CRPT SHA_DGST4: DGST Position /
sahilmgandhi	18:6a4db94011d3	7435	#define CRPT_SHA_DGST4_DGST_Msk (0xfffffffful << CRPT_SHA_DGST4_DGST_Pos) /!< CRPT SHA_DGST4: DGST Mask /
sahilmgandhi	18:6a4db94011d3	7436
sahilmgandhi	18:6a4db94011d3	7437	#define CRPT_SHA_DGST5_DGST_Pos (0) /!< CRPT SHA_DGST5: DGST Position /
sahilmgandhi	18:6a4db94011d3	7438	#define CRPT_SHA_DGST5_DGST_Msk (0xfffffffful << CRPT_SHA_DGST5_DGST_Pos) /!< CRPT SHA_DGST5: DGST Mask /
sahilmgandhi	18:6a4db94011d3	7439
sahilmgandhi	18:6a4db94011d3	7440	#define CRPT_SHA_DGST6_DGST_Pos (0) /!< CRPT SHA_DGST6: DGST Position /
sahilmgandhi	18:6a4db94011d3	7441	#define CRPT_SHA_DGST6_DGST_Msk (0xfffffffful << CRPT_SHA_DGST6_DGST_Pos) /!< CRPT SHA_DGST6: DGST Mask /
sahilmgandhi	18:6a4db94011d3	7442
sahilmgandhi	18:6a4db94011d3	7443	#define CRPT_SHA_DGST7_DGST_Pos (0) /!< CRPT SHA_DGST7: DGST Position /
sahilmgandhi	18:6a4db94011d3	7444	#define CRPT_SHA_DGST7_DGST_Msk (0xfffffffful << CRPT_SHA_DGST7_DGST_Pos) /!< CRPT SHA_DGST7: DGST Mask /
sahilmgandhi	18:6a4db94011d3	7445
sahilmgandhi	18:6a4db94011d3	7446	#define CRPT_SHA_KEYCNT_KEYCNT_Pos (0) /!< CRPT SHA_KEYCNT: KEYCNT Position /
sahilmgandhi	18:6a4db94011d3	7447	#define CRPT_SHA_KEYCNT_KEYCNT_Msk (0xfffffffful << CRPT_SHA_KEYCNT_KEYCNT_Pos) /!< CRPT SHA_KEYCNT: KEYCNT Mask /
sahilmgandhi	18:6a4db94011d3	7448
sahilmgandhi	18:6a4db94011d3	7449	#define CRPT_SHA_SADDR_SADDR_Pos (0) /!< CRPT SHA_SADDR: SADDR Position /
sahilmgandhi	18:6a4db94011d3	7450	#define CRPT_SHA_SADDR_SADDR_Msk (0xfffffffful << CRPT_SHA_SADDR_SADDR_Pos) /!< CRPT SHA_SADDR: SADDR Mask /
sahilmgandhi	18:6a4db94011d3	7451
sahilmgandhi	18:6a4db94011d3	7452	#define CRPT_SHA_DMACNT_DMACNT_Pos (0) /!< CRPT SHA_DMACNT: DMACNT Position /
sahilmgandhi	18:6a4db94011d3	7453	#define CRPT_SHA_DMACNT_DMACNT_Msk (0xfffffffful << CRPT_SHA_DMACNT_DMACNT_Pos) /!< CRPT SHA_DMACNT: DMACNT Mask /
sahilmgandhi	18:6a4db94011d3	7454
sahilmgandhi	18:6a4db94011d3	7455	#define CRPT_SHA_DATIN_DATIN_Pos (0) /!< CRPT SHA_DATIN: DATIN Position /
sahilmgandhi	18:6a4db94011d3	7456	#define CRPT_SHA_DATIN_DATIN_Msk (0xfffffffful << CRPT_SHA_DATIN_DATIN_Pos) /!< CRPT SHA_DATIN: DATIN Mask /
sahilmgandhi	18:6a4db94011d3	7457
sahilmgandhi	18:6a4db94011d3	7458	/*@}/ /* CRPT_CONST */
sahilmgandhi	18:6a4db94011d3	7459	/*@}/ /* end of CRPT register group */
sahilmgandhi	18:6a4db94011d3	7460
sahilmgandhi	18:6a4db94011d3	7461
sahilmgandhi	18:6a4db94011d3	7462	/---------------------- Enhanced Analog to Digital Converter -------------------------/
sahilmgandhi	18:6a4db94011d3	7463	/**
sahilmgandhi	18:6a4db94011d3	7464	@addtogroup EADC Enhanced Analog to Digital Converter(EADC)
sahilmgandhi	18:6a4db94011d3	7465	Memory Mapped Structure for EADC Controller
sahilmgandhi	18:6a4db94011d3	7466	@{ */
sahilmgandhi	18:6a4db94011d3	7467
sahilmgandhi	18:6a4db94011d3	7468	typedef struct {
sahilmgandhi	18:6a4db94011d3	7469
sahilmgandhi	18:6a4db94011d3	7470
sahilmgandhi	18:6a4db94011d3	7471	/**
sahilmgandhi	18:6a4db94011d3	7472	* AD0DAT0
sahilmgandhi	18:6a4db94011d3	7473	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	7474	* Offset: 0x00 A/D Data Register 0 for SAMPLE00
sahilmgandhi	18:6a4db94011d3	7475	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	7476	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	7477	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	7478	* \|[0:11] \|RESULT \|A/D Conversion Result
sahilmgandhi	18:6a4db94011d3	7479	* \| \| \|This field contains 12 bits conversion result.
sahilmgandhi	18:6a4db94011d3	7480	* \|[16] \|OV \|Overrun Flag
sahilmgandhi	18:6a4db94011d3	7481	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
sahilmgandhi	18:6a4db94011d3	7482	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
sahilmgandhi	18:6a4db94011d3	7483	* \| \| \|If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
sahilmgandhi	18:6a4db94011d3	7484	* \| \| \|It is cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7485	* \|[17] \|VALID \|Valid Flag
sahilmgandhi	18:6a4db94011d3	7486	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
sahilmgandhi	18:6a4db94011d3	7487	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
sahilmgandhi	18:6a4db94011d3	7488	* \| \| \|This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7489	*/
sahilmgandhi	18:6a4db94011d3	7490	__I uint32_t AD0DAT0;
sahilmgandhi	18:6a4db94011d3	7491
sahilmgandhi	18:6a4db94011d3	7492	/**
sahilmgandhi	18:6a4db94011d3	7493	* AD0DAT1
sahilmgandhi	18:6a4db94011d3	7494	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	7495	* Offset: 0x04 A/D Data Register 1 for SAMPLE01
sahilmgandhi	18:6a4db94011d3	7496	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	7497	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	7498	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	7499	* \|[0:11] \|RESULT \|A/D Conversion Result
sahilmgandhi	18:6a4db94011d3	7500	* \| \| \|This field contains 12 bits conversion result.
sahilmgandhi	18:6a4db94011d3	7501	* \|[16] \|OV \|Overrun Flag
sahilmgandhi	18:6a4db94011d3	7502	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
sahilmgandhi	18:6a4db94011d3	7503	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
sahilmgandhi	18:6a4db94011d3	7504	* \| \| \|If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
sahilmgandhi	18:6a4db94011d3	7505	* \| \| \|It is cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7506	* \|[17] \|VALID \|Valid Flag
sahilmgandhi	18:6a4db94011d3	7507	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
sahilmgandhi	18:6a4db94011d3	7508	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
sahilmgandhi	18:6a4db94011d3	7509	* \| \| \|This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7510	*/
sahilmgandhi	18:6a4db94011d3	7511	__I uint32_t AD0DAT1;
sahilmgandhi	18:6a4db94011d3	7512
sahilmgandhi	18:6a4db94011d3	7513	/**
sahilmgandhi	18:6a4db94011d3	7514	* AD0DAT2
sahilmgandhi	18:6a4db94011d3	7515	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	7516	* Offset: 0x08 A/D Data Register 2 for SAMPLE02
sahilmgandhi	18:6a4db94011d3	7517	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	7518	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	7519	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	7520	* \|[0:11] \|RESULT \|A/D Conversion Result
sahilmgandhi	18:6a4db94011d3	7521	* \| \| \|This field contains 12 bits conversion result.
sahilmgandhi	18:6a4db94011d3	7522	* \|[16] \|OV \|Overrun Flag
sahilmgandhi	18:6a4db94011d3	7523	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
sahilmgandhi	18:6a4db94011d3	7524	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
sahilmgandhi	18:6a4db94011d3	7525	* \| \| \|If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
sahilmgandhi	18:6a4db94011d3	7526	* \| \| \|It is cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7527	* \|[17] \|VALID \|Valid Flag
sahilmgandhi	18:6a4db94011d3	7528	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
sahilmgandhi	18:6a4db94011d3	7529	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
sahilmgandhi	18:6a4db94011d3	7530	* \| \| \|This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7531	*/
sahilmgandhi	18:6a4db94011d3	7532	__I uint32_t AD0DAT2;
sahilmgandhi	18:6a4db94011d3	7533
sahilmgandhi	18:6a4db94011d3	7534	/**
sahilmgandhi	18:6a4db94011d3	7535	* AD0DAT3
sahilmgandhi	18:6a4db94011d3	7536	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	7537	* Offset: 0x0C A/D Data Register 3 for SAMPLE03
sahilmgandhi	18:6a4db94011d3	7538	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	7539	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	7540	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	7541	* \|[0:11] \|RESULT \|A/D Conversion Result
sahilmgandhi	18:6a4db94011d3	7542	* \| \| \|This field contains 12 bits conversion result.
sahilmgandhi	18:6a4db94011d3	7543	* \|[16] \|OV \|Overrun Flag
sahilmgandhi	18:6a4db94011d3	7544	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
sahilmgandhi	18:6a4db94011d3	7545	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
sahilmgandhi	18:6a4db94011d3	7546	* \| \| \|If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
sahilmgandhi	18:6a4db94011d3	7547	* \| \| \|It is cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7548	* \|[17] \|VALID \|Valid Flag
sahilmgandhi	18:6a4db94011d3	7549	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
sahilmgandhi	18:6a4db94011d3	7550	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
sahilmgandhi	18:6a4db94011d3	7551	* \| \| \|This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7552	*/
sahilmgandhi	18:6a4db94011d3	7553	__I uint32_t AD0DAT3;
sahilmgandhi	18:6a4db94011d3	7554
sahilmgandhi	18:6a4db94011d3	7555	/**
sahilmgandhi	18:6a4db94011d3	7556	* AD0DAT4
sahilmgandhi	18:6a4db94011d3	7557	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	7558	* Offset: 0x10 A/D Data Register 4 for SAMPLE04
sahilmgandhi	18:6a4db94011d3	7559	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	7560	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	7561	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	7562	* \|[0:11] \|RESULT \|A/D Conversion Result
sahilmgandhi	18:6a4db94011d3	7563	* \| \| \|This field contains 12 bits conversion result.
sahilmgandhi	18:6a4db94011d3	7564	* \|[16] \|OV \|Overrun Flag
sahilmgandhi	18:6a4db94011d3	7565	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
sahilmgandhi	18:6a4db94011d3	7566	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
sahilmgandhi	18:6a4db94011d3	7567	* \| \| \|If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
sahilmgandhi	18:6a4db94011d3	7568	* \| \| \|It is cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7569	* \|[17] \|VALID \|Valid Flag
sahilmgandhi	18:6a4db94011d3	7570	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
sahilmgandhi	18:6a4db94011d3	7571	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
sahilmgandhi	18:6a4db94011d3	7572	* \| \| \|This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7573	*/
sahilmgandhi	18:6a4db94011d3	7574	__I uint32_t AD0DAT4;
sahilmgandhi	18:6a4db94011d3	7575
sahilmgandhi	18:6a4db94011d3	7576	/**
sahilmgandhi	18:6a4db94011d3	7577	* AD0DAT5
sahilmgandhi	18:6a4db94011d3	7578	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	7579	* Offset: 0x14 A/D Data Register 5 for SAMPLE05
sahilmgandhi	18:6a4db94011d3	7580	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	7581	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	7582	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	7583	* \|[0:11] \|RESULT \|A/D Conversion Result
sahilmgandhi	18:6a4db94011d3	7584	* \| \| \|This field contains 12 bits conversion result.
sahilmgandhi	18:6a4db94011d3	7585	* \|[16] \|OV \|Overrun Flag
sahilmgandhi	18:6a4db94011d3	7586	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
sahilmgandhi	18:6a4db94011d3	7587	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
sahilmgandhi	18:6a4db94011d3	7588	* \| \| \|If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
sahilmgandhi	18:6a4db94011d3	7589	* \| \| \|It is cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7590	* \|[17] \|VALID \|Valid Flag
sahilmgandhi	18:6a4db94011d3	7591	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
sahilmgandhi	18:6a4db94011d3	7592	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
sahilmgandhi	18:6a4db94011d3	7593	* \| \| \|This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7594	*/
sahilmgandhi	18:6a4db94011d3	7595	__I uint32_t AD0DAT5;
sahilmgandhi	18:6a4db94011d3	7596
sahilmgandhi	18:6a4db94011d3	7597	/**
sahilmgandhi	18:6a4db94011d3	7598	* AD0DAT6
sahilmgandhi	18:6a4db94011d3	7599	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	7600	* Offset: 0x18 A/D Data Register 6 for SAMPLE06
sahilmgandhi	18:6a4db94011d3	7601	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	7602	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	7603	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	7604	* \|[0:11] \|RESULT \|A/D Conversion Result
sahilmgandhi	18:6a4db94011d3	7605	* \| \| \|This field contains 12 bits conversion result.
sahilmgandhi	18:6a4db94011d3	7606	* \|[16] \|OV \|Overrun Flag
sahilmgandhi	18:6a4db94011d3	7607	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
sahilmgandhi	18:6a4db94011d3	7608	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
sahilmgandhi	18:6a4db94011d3	7609	* \| \| \|If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
sahilmgandhi	18:6a4db94011d3	7610	* \| \| \|It is cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7611	* \|[17] \|VALID \|Valid Flag
sahilmgandhi	18:6a4db94011d3	7612	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
sahilmgandhi	18:6a4db94011d3	7613	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
sahilmgandhi	18:6a4db94011d3	7614	* \| \| \|This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7615	*/
sahilmgandhi	18:6a4db94011d3	7616	__I uint32_t AD0DAT6;
sahilmgandhi	18:6a4db94011d3	7617
sahilmgandhi	18:6a4db94011d3	7618	/**
sahilmgandhi	18:6a4db94011d3	7619	* AD0DAT7
sahilmgandhi	18:6a4db94011d3	7620	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	7621	* Offset: 0x1C A/D Data Register 7 for SAMPLE07
sahilmgandhi	18:6a4db94011d3	7622	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	7623	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	7624	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	7625	* \|[0:11] \|RESULT \|A/D Conversion Result
sahilmgandhi	18:6a4db94011d3	7626	* \| \| \|This field contains 12 bits conversion result.
sahilmgandhi	18:6a4db94011d3	7627	* \|[16] \|OV \|Overrun Flag
sahilmgandhi	18:6a4db94011d3	7628	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
sahilmgandhi	18:6a4db94011d3	7629	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
sahilmgandhi	18:6a4db94011d3	7630	* \| \| \|If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
sahilmgandhi	18:6a4db94011d3	7631	* \| \| \|It is cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7632	* \|[17] \|VALID \|Valid Flag
sahilmgandhi	18:6a4db94011d3	7633	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
sahilmgandhi	18:6a4db94011d3	7634	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
sahilmgandhi	18:6a4db94011d3	7635	* \| \| \|This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7636	*/
sahilmgandhi	18:6a4db94011d3	7637	__I uint32_t AD0DAT7;
sahilmgandhi	18:6a4db94011d3	7638
sahilmgandhi	18:6a4db94011d3	7639	/**
sahilmgandhi	18:6a4db94011d3	7640	* AD1DAT0
sahilmgandhi	18:6a4db94011d3	7641	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	7642	* Offset: 0x20 A/D Data Register 8 for SAMPLE10
sahilmgandhi	18:6a4db94011d3	7643	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	7644	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	7645	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	7646	* \|[0:11] \|RESULT \|A/D Conversion Result
sahilmgandhi	18:6a4db94011d3	7647	* \| \| \|This field contains 12 bits conversion result.
sahilmgandhi	18:6a4db94011d3	7648	* \|[16] \|OV \|Overrun Flag
sahilmgandhi	18:6a4db94011d3	7649	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
sahilmgandhi	18:6a4db94011d3	7650	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
sahilmgandhi	18:6a4db94011d3	7651	* \| \| \|If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
sahilmgandhi	18:6a4db94011d3	7652	* \| \| \|It is cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7653	* \|[17] \|VALID \|Valid Flag
sahilmgandhi	18:6a4db94011d3	7654	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
sahilmgandhi	18:6a4db94011d3	7655	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
sahilmgandhi	18:6a4db94011d3	7656	* \| \| \|This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7657	*/
sahilmgandhi	18:6a4db94011d3	7658	__I uint32_t AD1DAT0;
sahilmgandhi	18:6a4db94011d3	7659
sahilmgandhi	18:6a4db94011d3	7660	/**
sahilmgandhi	18:6a4db94011d3	7661	* AD1DAT1
sahilmgandhi	18:6a4db94011d3	7662	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	7663	* Offset: 0x24 A/D Data Register 9 for SAMPLE11
sahilmgandhi	18:6a4db94011d3	7664	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	7665	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	7666	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	7667	* \|[0:11] \|RESULT \|A/D Conversion Result
sahilmgandhi	18:6a4db94011d3	7668	* \| \| \|This field contains 12 bits conversion result.
sahilmgandhi	18:6a4db94011d3	7669	* \|[16] \|OV \|Overrun Flag
sahilmgandhi	18:6a4db94011d3	7670	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
sahilmgandhi	18:6a4db94011d3	7671	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
sahilmgandhi	18:6a4db94011d3	7672	* \| \| \|If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
sahilmgandhi	18:6a4db94011d3	7673	* \| \| \|It is cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7674	* \|[17] \|VALID \|Valid Flag
sahilmgandhi	18:6a4db94011d3	7675	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
sahilmgandhi	18:6a4db94011d3	7676	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
sahilmgandhi	18:6a4db94011d3	7677	* \| \| \|This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7678	*/
sahilmgandhi	18:6a4db94011d3	7679	__I uint32_t AD1DAT1;
sahilmgandhi	18:6a4db94011d3	7680
sahilmgandhi	18:6a4db94011d3	7681	/**
sahilmgandhi	18:6a4db94011d3	7682	* AD1DAT2
sahilmgandhi	18:6a4db94011d3	7683	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	7684	* Offset: 0x28 A/D Data Register 10 for SAMPLE12
sahilmgandhi	18:6a4db94011d3	7685	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	7686	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	7687	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	7688	* \|[0:11] \|RESULT \|A/D Conversion Result
sahilmgandhi	18:6a4db94011d3	7689	* \| \| \|This field contains 12 bits conversion result.
sahilmgandhi	18:6a4db94011d3	7690	* \|[16] \|OV \|Overrun Flag
sahilmgandhi	18:6a4db94011d3	7691	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
sahilmgandhi	18:6a4db94011d3	7692	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
sahilmgandhi	18:6a4db94011d3	7693	* \| \| \|If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
sahilmgandhi	18:6a4db94011d3	7694	* \| \| \|It is cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7695	* \|[17] \|VALID \|Valid Flag
sahilmgandhi	18:6a4db94011d3	7696	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
sahilmgandhi	18:6a4db94011d3	7697	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
sahilmgandhi	18:6a4db94011d3	7698	* \| \| \|This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7699	*/
sahilmgandhi	18:6a4db94011d3	7700	__I uint32_t AD1DAT2;
sahilmgandhi	18:6a4db94011d3	7701
sahilmgandhi	18:6a4db94011d3	7702	/**
sahilmgandhi	18:6a4db94011d3	7703	* AD1DAT3
sahilmgandhi	18:6a4db94011d3	7704	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	7705	* Offset: 0x2C A/D Data Register 11 for SAMPLE13
sahilmgandhi	18:6a4db94011d3	7706	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	7707	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	7708	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	7709	* \|[0:11] \|RESULT \|A/D Conversion Result
sahilmgandhi	18:6a4db94011d3	7710	* \| \| \|This field contains 12 bits conversion result.
sahilmgandhi	18:6a4db94011d3	7711	* \|[16] \|OV \|Overrun Flag
sahilmgandhi	18:6a4db94011d3	7712	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
sahilmgandhi	18:6a4db94011d3	7713	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
sahilmgandhi	18:6a4db94011d3	7714	* \| \| \|If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
sahilmgandhi	18:6a4db94011d3	7715	* \| \| \|It is cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7716	* \|[17] \|VALID \|Valid Flag
sahilmgandhi	18:6a4db94011d3	7717	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
sahilmgandhi	18:6a4db94011d3	7718	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
sahilmgandhi	18:6a4db94011d3	7719	* \| \| \|This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7720	*/
sahilmgandhi	18:6a4db94011d3	7721	__I uint32_t AD1DAT3;
sahilmgandhi	18:6a4db94011d3	7722
sahilmgandhi	18:6a4db94011d3	7723	/**
sahilmgandhi	18:6a4db94011d3	7724	* AD1DAT4
sahilmgandhi	18:6a4db94011d3	7725	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	7726	* Offset: 0x30 A/D Data Register 12 for SAMPLE14
sahilmgandhi	18:6a4db94011d3	7727	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	7728	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	7729	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	7730	* \|[0:11] \|RESULT \|A/D Conversion Result
sahilmgandhi	18:6a4db94011d3	7731	* \| \| \|This field contains 12 bits conversion result.
sahilmgandhi	18:6a4db94011d3	7732	* \|[16] \|OV \|Overrun Flag
sahilmgandhi	18:6a4db94011d3	7733	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
sahilmgandhi	18:6a4db94011d3	7734	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
sahilmgandhi	18:6a4db94011d3	7735	* \| \| \|If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
sahilmgandhi	18:6a4db94011d3	7736	* \| \| \|It is cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7737	* \|[17] \|VALID \|Valid Flag
sahilmgandhi	18:6a4db94011d3	7738	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
sahilmgandhi	18:6a4db94011d3	7739	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
sahilmgandhi	18:6a4db94011d3	7740	* \| \| \|This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7741	*/
sahilmgandhi	18:6a4db94011d3	7742	__I uint32_t AD1DAT4;
sahilmgandhi	18:6a4db94011d3	7743
sahilmgandhi	18:6a4db94011d3	7744	/**
sahilmgandhi	18:6a4db94011d3	7745	* AD1DAT5
sahilmgandhi	18:6a4db94011d3	7746	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	7747	* Offset: 0x34 A/D Data Register 13 for SAMPLE15
sahilmgandhi	18:6a4db94011d3	7748	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	7749	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	7750	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	7751	* \|[0:11] \|RESULT \|A/D Conversion Result
sahilmgandhi	18:6a4db94011d3	7752	* \| \| \|This field contains 12 bits conversion result.
sahilmgandhi	18:6a4db94011d3	7753	* \|[16] \|OV \|Overrun Flag
sahilmgandhi	18:6a4db94011d3	7754	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
sahilmgandhi	18:6a4db94011d3	7755	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
sahilmgandhi	18:6a4db94011d3	7756	* \| \| \|If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
sahilmgandhi	18:6a4db94011d3	7757	* \| \| \|It is cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7758	* \|[17] \|VALID \|Valid Flag
sahilmgandhi	18:6a4db94011d3	7759	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
sahilmgandhi	18:6a4db94011d3	7760	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
sahilmgandhi	18:6a4db94011d3	7761	* \| \| \|This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7762	*/
sahilmgandhi	18:6a4db94011d3	7763	__I uint32_t AD1DAT5;
sahilmgandhi	18:6a4db94011d3	7764
sahilmgandhi	18:6a4db94011d3	7765	/**
sahilmgandhi	18:6a4db94011d3	7766	* AD1DAT6
sahilmgandhi	18:6a4db94011d3	7767	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	7768	* Offset: 0x38 A/D Data Register 14 for SAMPLE16
sahilmgandhi	18:6a4db94011d3	7769	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	7770	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	7771	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	7772	* \|[0:11] \|RESULT \|A/D Conversion Result
sahilmgandhi	18:6a4db94011d3	7773	* \| \| \|This field contains 12 bits conversion result.
sahilmgandhi	18:6a4db94011d3	7774	* \|[16] \|OV \|Overrun Flag
sahilmgandhi	18:6a4db94011d3	7775	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
sahilmgandhi	18:6a4db94011d3	7776	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
sahilmgandhi	18:6a4db94011d3	7777	* \| \| \|If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
sahilmgandhi	18:6a4db94011d3	7778	* \| \| \|It is cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7779	* \|[17] \|VALID \|Valid Flag
sahilmgandhi	18:6a4db94011d3	7780	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
sahilmgandhi	18:6a4db94011d3	7781	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
sahilmgandhi	18:6a4db94011d3	7782	* \| \| \|This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7783	*/
sahilmgandhi	18:6a4db94011d3	7784	__I uint32_t AD1DAT6;
sahilmgandhi	18:6a4db94011d3	7785
sahilmgandhi	18:6a4db94011d3	7786	/**
sahilmgandhi	18:6a4db94011d3	7787	* AD1DAT7
sahilmgandhi	18:6a4db94011d3	7788	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	7789	* Offset: 0x3C A/D Data Register 15 for SAMPLE17
sahilmgandhi	18:6a4db94011d3	7790	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	7791	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	7792	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	7793	* \|[0:11] \|RESULT \|A/D Conversion Result
sahilmgandhi	18:6a4db94011d3	7794	* \| \| \|This field contains 12 bits conversion result.
sahilmgandhi	18:6a4db94011d3	7795	* \|[16] \|OV \|Overrun Flag
sahilmgandhi	18:6a4db94011d3	7796	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
sahilmgandhi	18:6a4db94011d3	7797	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
sahilmgandhi	18:6a4db94011d3	7798	* \| \| \|If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
sahilmgandhi	18:6a4db94011d3	7799	* \| \| \|It is cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7800	* \|[17] \|VALID \|Valid Flag
sahilmgandhi	18:6a4db94011d3	7801	* \| \| \|0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
sahilmgandhi	18:6a4db94011d3	7802	* \| \| \|1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
sahilmgandhi	18:6a4db94011d3	7803	* \| \| \|This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	7804	*/
sahilmgandhi	18:6a4db94011d3	7805	__I uint32_t AD1DAT7;
sahilmgandhi	18:6a4db94011d3	7806
sahilmgandhi	18:6a4db94011d3	7807	/**
sahilmgandhi	18:6a4db94011d3	7808	* CTL
sahilmgandhi	18:6a4db94011d3	7809	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	7810	* Offset: 0x40 A/D Control Register
sahilmgandhi	18:6a4db94011d3	7811	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	7812	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	7813	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	7814	* \|[0] \|ADCEN \|A/D Converter Enable Control
sahilmgandhi	18:6a4db94011d3	7815	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	7816	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	7817	* \| \| \|Before starting A/D conversion function, this bit should be set to 1.
sahilmgandhi	18:6a4db94011d3	7818	* \| \| \|Clear it to 0 to disable A/D converter analog circuit power consumption.
sahilmgandhi	18:6a4db94011d3	7819	* \|[1] \|ADCRST \|ADC0, ADC1 A/D Converter Control Circuits Reset
sahilmgandhi	18:6a4db94011d3	7820	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	7821	* \| \| \|1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value.
sahilmgandhi	18:6a4db94011d3	7822	* \| \| \|The ADCRST (EADC_CTL [1]) bit remains 1 during ADC reset, when ADC reset end, the ADCRST (EADC_CTL [1]) bit is automatically cleared to 0.
sahilmgandhi	18:6a4db94011d3	7823	* \|[2] \|ADCIEN0 \|Specific SAMPLE A/D ADINT0 Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	7824	* \| \| \|0 = Specific SAMPLE A/D ADINT0 interrupt function Disabled.
sahilmgandhi	18:6a4db94011d3	7825	* \| \| \|1 = Specific SAMPLE A/D ADINT0 interrupt function Enabled.
sahilmgandhi	18:6a4db94011d3	7826	* \| \| \|The A/D converter generates a conversion end ADIF0 (EADC_STATUS1 [0]) flag upon the end of specific SAMPLE A/D conversion.
sahilmgandhi	18:6a4db94011d3	7827	* \| \| \|If ADCIEN0 (EADC_CTL [2]) bit is set then conversion end interrupt request ADINT0 is generated.
sahilmgandhi	18:6a4db94011d3	7828	* \|[3] \|ADCIEN1 \|Specific SAMPLE A/D ADINT1 Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	7829	* \| \| \|0 = Specific SAMPLE A/D ADINT1 interrupt function Disabled.
sahilmgandhi	18:6a4db94011d3	7830	* \| \| \|1 = Specific SAMPLE A/D ADINT1 interrupt function Enabled.
sahilmgandhi	18:6a4db94011d3	7831	* \| \| \|The A/D converter generates a conversion end ADIF0 (EADC_STATUS1 [1]) flag upon the end of specific SAMPLE A/D conversion.
sahilmgandhi	18:6a4db94011d3	7832	* \| \| \|If ADCIEN1 EADC_CTL [3]) bit is set then conversion end interrupt request ADINT1 is generated.
sahilmgandhi	18:6a4db94011d3	7833	* \|[4] \|ADCIEN2 \|Specific SAMPLE A/D ADINT2 Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	7834	* \| \| \|0 = Specific SAMPLE A/D ADINT2 interrupt function Disabled.
sahilmgandhi	18:6a4db94011d3	7835	* \| \| \|1 = Specific SAMPLE A/D ADINT2 interrupt function Enabled.
sahilmgandhi	18:6a4db94011d3	7836	* \| \| \|The A/D converter generates a conversion end ADIF2 (EADC_STATUS1 [2]) flag upon the end of specific SAMPLE A/D conversion.
sahilmgandhi	18:6a4db94011d3	7837	* \| \| \|If ADCIEN2 (EADC_CTL [4]) bit is set then conversion end interrupt request ADINT2 is generated.
sahilmgandhi	18:6a4db94011d3	7838	* \|[5] \|ADCIEN3 \|Specific SAMPLE A/D ADINT3 Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	7839	* \| \| \|0 = Specific SAMPLE A/D ADINT3 interrupt function Disabled.
sahilmgandhi	18:6a4db94011d3	7840	* \| \| \|1 = Specific SAMPLE A/D ADINT3 interrupt function Enabled.
sahilmgandhi	18:6a4db94011d3	7841	* \| \| \|The A/D converter generates a conversion end ADIF3 (EADC_STATUS1 [3]) flag upon the end of specific SAMPLE A/D conversion.
sahilmgandhi	18:6a4db94011d3	7842	* \| \| \|If ADCIEN3 (EADC_CTL [5]) bit is set then conversion end interrupt request ADINT3 is generated.
sahilmgandhi	18:6a4db94011d3	7843	*/
sahilmgandhi	18:6a4db94011d3	7844	__IO uint32_t CTL;
sahilmgandhi	18:6a4db94011d3	7845	uint32_t RESERVE0[1];
sahilmgandhi	18:6a4db94011d3	7846
sahilmgandhi	18:6a4db94011d3	7847
sahilmgandhi	18:6a4db94011d3	7848	/**
sahilmgandhi	18:6a4db94011d3	7849	* SWTRG
sahilmgandhi	18:6a4db94011d3	7850	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	7851	* Offset: 0x48 A/D SAMPLE Software Start Register
sahilmgandhi	18:6a4db94011d3	7852	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	7853	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	7854	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	7855	* \|[0:7] \|SWTRG7_0 \|A/D SAMPLE07~SAMPLE00 Software Force To Start ADC Conversion
sahilmgandhi	18:6a4db94011d3	7856	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	7857	* \| \| \|1 = Start an ADC conversion when the priority is given to SAMPLE0x.
sahilmgandhi	18:6a4db94011d3	7858	* \| \| \|Note: x = 0~7.
sahilmgandhi	18:6a4db94011d3	7859	* \|[8:15] \|SWTRG15_8 \|A/D SAMPLE17~SAMPLE10 Software Force To Start ADC Conversion
sahilmgandhi	18:6a4db94011d3	7860	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	7861	* \| \| \|1 = Start an ADC conversion when the priority is given to SAMPLE1x.
sahilmgandhi	18:6a4db94011d3	7862	* \| \| \|Note: x = 0~7.
sahilmgandhi	18:6a4db94011d3	7863	*/
sahilmgandhi	18:6a4db94011d3	7864	__O uint32_t SWTRG;
sahilmgandhi	18:6a4db94011d3	7865
sahilmgandhi	18:6a4db94011d3	7866	/**
sahilmgandhi	18:6a4db94011d3	7867	* PENDSTS
sahilmgandhi	18:6a4db94011d3	7868	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	7869	* Offset: 0x4C A/D Start of Conversion Pending Flag Register
sahilmgandhi	18:6a4db94011d3	7870	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	7871	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	7872	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	7873	* \|[0:7] \|STPF7_0 \|A/D SAMPLE07~SAMPLE00 Start Of Conversion Pending Flag
sahilmgandhi	18:6a4db94011d3	7874	* \| \| \|0 = There is no pending conversion for SAMPLE0x.
sahilmgandhi	18:6a4db94011d3	7875	* \| \| \|1 = SAMPLE0x ADC start of conversion is pending.
sahilmgandhi	18:6a4db94011d3	7876	* \| \| \|Note: This bit remains 1 during pending state, when the respective ADC conversion is started, the STPF bit is automatically cleared to 0.
sahilmgandhi	18:6a4db94011d3	7877	* \| \| \|Note: x = 0~7.
sahilmgandhi	18:6a4db94011d3	7878	* \|[8:15] \|STPF15_8 \|A/D SAMPLE17~SAMPLE10 Start Of Conversion Pending Flag
sahilmgandhi	18:6a4db94011d3	7879	* \| \| \|0 = There is no pending conversion for SAMPLE1x.
sahilmgandhi	18:6a4db94011d3	7880	* \| \| \|1 = SAMPLE1x ADC start of conversion is pending.
sahilmgandhi	18:6a4db94011d3	7881	* \| \| \|Note: This bit remains 1 during pending state, when the respective ADC conversion is started, the STPF bit is automatically cleared to 0.
sahilmgandhi	18:6a4db94011d3	7882	* \| \| \|Note: x = 0~7.
sahilmgandhi	18:6a4db94011d3	7883	*/
sahilmgandhi	18:6a4db94011d3	7884	__I uint32_t PENDSTS;
sahilmgandhi	18:6a4db94011d3	7885
sahilmgandhi	18:6a4db94011d3	7886	/**
sahilmgandhi	18:6a4db94011d3	7887	* ADIFOV
sahilmgandhi	18:6a4db94011d3	7888	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	7889	* Offset: 0x50 A/D ADINT3~0 Interrupt Flag Overrun Register
sahilmgandhi	18:6a4db94011d3	7890	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	7891	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	7892	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	7893	* \|[0] \|ADFOV0 \|A/D ADINT0 Interrupt Flag Overrun
sahilmgandhi	18:6a4db94011d3	7894	* \| \| \|0 = ADINT0 interrupt flag is not overwritten to 1.
sahilmgandhi	18:6a4db94011d3	7895	* \| \| \|1 = ADINT0 interrupt flag is overwritten to 1.
sahilmgandhi	18:6a4db94011d3	7896	* \| \| \|Note: This bit is cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	7897	* \|[1] \|ADFOV1 \|A/D ADINT1 Interrupt Flag Overrun
sahilmgandhi	18:6a4db94011d3	7898	* \| \| \|0 = ADINT1 interrupt flag is not overwritten to 1.
sahilmgandhi	18:6a4db94011d3	7899	* \| \| \|1 = ADINT1 interrupt flag is overwritten to 1.
sahilmgandhi	18:6a4db94011d3	7900	* \| \| \|Note: This bit is cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	7901	* \|[2] \|ADFOV2 \|A/D ADINT2 Interrupt Flag Overrun
sahilmgandhi	18:6a4db94011d3	7902	* \| \| \|0 = ADINT2 interrupt flag is not overwritten to 1.
sahilmgandhi	18:6a4db94011d3	7903	* \| \| \|1 = ADINT2 interrupt flag is overwritten to 1.
sahilmgandhi	18:6a4db94011d3	7904	* \| \| \|Note: This bit is cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	7905	* \|[3] \|ADFOV3 \|A/D ADINT3 Interrupt Flag Overrun
sahilmgandhi	18:6a4db94011d3	7906	* \| \| \|0 = ADINT3 interrupt flag is not overwritten to 1.
sahilmgandhi	18:6a4db94011d3	7907	* \| \| \|1 = ADINT3 interrupt flag is overwritten to 1.
sahilmgandhi	18:6a4db94011d3	7908	* \| \| \|Note: This bit is cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	7909	*/
sahilmgandhi	18:6a4db94011d3	7910	__IO uint32_t ADIFOV;
sahilmgandhi	18:6a4db94011d3	7911
sahilmgandhi	18:6a4db94011d3	7912	/**
sahilmgandhi	18:6a4db94011d3	7913	* OVSTS
sahilmgandhi	18:6a4db94011d3	7914	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	7915	* Offset: 0x54 A/D SAMPLE Start of Conversion Overrun Flag Register
sahilmgandhi	18:6a4db94011d3	7916	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	7917	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	7918	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	7919	* \|[0:7] \|SPOVF7_0 \|A/D SAMPLE07~SAMPLE00 Start Of Conversion Overrun Flag
sahilmgandhi	18:6a4db94011d3	7920	* \| \| \|0 = No SAMPLE0x event overrun.
sahilmgandhi	18:6a4db94011d3	7921	* \| \| \|1 = Indicates a new SAMPLE0x event is generated while an old one event is pending.
sahilmgandhi	18:6a4db94011d3	7922	* \| \| \|If there is a new trigger event comes when the SAMPLE is pending for the last trigger event, the overrun is happened and the SPOVF bit will be set as 1.
sahilmgandhi	18:6a4db94011d3	7923	* \| \| \|Note: This bit is cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	7924	* \| \| \|Note: x = 0~7.
sahilmgandhi	18:6a4db94011d3	7925	* \|[8:15] \|SPOVF15_8 \|A/D SAMPLE17~SAMPLE10 Start Of Conversion Overrun Flag
sahilmgandhi	18:6a4db94011d3	7926	* \| \| \|0 = No SAMPLE1x event overrun.
sahilmgandhi	18:6a4db94011d3	7927	* \| \| \|1 = Indicates a new SAMPLE1x event is generated while an old one event is pending.
sahilmgandhi	18:6a4db94011d3	7928	* \| \| \|If there is a new trigger event comes when the SAMPLE is pending for the last trigger event, the overrun is happened and the SPOVF bit will be set as 1.
sahilmgandhi	18:6a4db94011d3	7929	* \| \| \|Note: This bit is cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	7930	* \| \| \|Note: x = 0~7.
sahilmgandhi	18:6a4db94011d3	7931	*/
sahilmgandhi	18:6a4db94011d3	7932	__IO uint32_t OVSTS;
sahilmgandhi	18:6a4db94011d3	7933
sahilmgandhi	18:6a4db94011d3	7934	/**
sahilmgandhi	18:6a4db94011d3	7935	* AD0SPCTL0
sahilmgandhi	18:6a4db94011d3	7936	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	7937	* Offset: 0x58 A/D SAMPLE00 Control Register
sahilmgandhi	18:6a4db94011d3	7938	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	7939	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	7940	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	7941	* \|[0:3] \|CHSEL \|A/D SAMPLE0,1 Channel Selection
sahilmgandhi	18:6a4db94011d3	7942	* \| \| \|0000 = ADCn_CH0.
sahilmgandhi	18:6a4db94011d3	7943	* \| \| \|0001 = ADCn_CH1.
sahilmgandhi	18:6a4db94011d3	7944	* \| \| \|0010 = ADCn_CH2.
sahilmgandhi	18:6a4db94011d3	7945	* \| \| \|0011 = ADCn_CH3.
sahilmgandhi	18:6a4db94011d3	7946	* \| \| \|0100 = ADCn_CH4.
sahilmgandhi	18:6a4db94011d3	7947	* \| \| \|0101 = ADCn_CH5.
sahilmgandhi	18:6a4db94011d3	7948	* \| \| \|0110 = ADCn_CH6.
sahilmgandhi	18:6a4db94011d3	7949	* \| \| \|0111 = ADCn_CH7.
sahilmgandhi	18:6a4db94011d3	7950	* \| \| \|For SAMPLE0
sahilmgandhi	18:6a4db94011d3	7951	* \| \| \|1000 = VBG.
sahilmgandhi	18:6a4db94011d3	7952	* \| \| \|1001 = VTEMP.
sahilmgandhi	18:6a4db94011d3	7953	* \| \| \|1010 = AVSS.
sahilmgandhi	18:6a4db94011d3	7954	* \| \| \|1011 = OP0.
sahilmgandhi	18:6a4db94011d3	7955	* \| \| \|For SAMPLE1
sahilmgandhi	18:6a4db94011d3	7956	* \| \| \|1000= OP1.
sahilmgandhi	18:6a4db94011d3	7957	* \|[4:7] \|TRGSEL \|A/D SAMPLE Start Of Conversion Trigger Source Selection
sahilmgandhi	18:6a4db94011d3	7958	* \| \| \|0000 = Disable hardware trigger.
sahilmgandhi	18:6a4db94011d3	7959	* \| \| \|0001 = External pin (STADC) trigger.
sahilmgandhi	18:6a4db94011d3	7960	* \| \| \|0010 = ADC ADINT0 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	7961	* \| \| \|0011 = ADC ADINT1 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	7962	* \| \| \|0100 = Timer0 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	7963	* \| \| \|0101 = Timer1 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	7964	* \| \| \|0110 = Timer2 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	7965	* \| \| \|0111 = Timer3 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	7966	* \| \| \|1000 = EPWM0_CH0 trigger.
sahilmgandhi	18:6a4db94011d3	7967	* \| \| \|1001 = EPWM0_CH2 trigger.
sahilmgandhi	18:6a4db94011d3	7968	* \| \| \|1010 = EPWM0_CH4 trigger.
sahilmgandhi	18:6a4db94011d3	7969	* \| \| \|1011 = EPWM1_CH0 trigger.
sahilmgandhi	18:6a4db94011d3	7970	* \| \| \|1100 = EPWM1_CH2 trigger.
sahilmgandhi	18:6a4db94011d3	7971	* \| \| \|1101 = EPWM1_CH4 trigger.
sahilmgandhi	18:6a4db94011d3	7972	* \| \| \|1110 = PWM0_CH0 trigger.
sahilmgandhi	18:6a4db94011d3	7973	* \| \| \|1111 = PWM0_CH1 trigger.
sahilmgandhi	18:6a4db94011d3	7974	* \|[8:15] \|TRGDLYCNT \|A/D SAMPLE Start Of Conversion Trigger Delay Time
sahilmgandhi	18:6a4db94011d3	7975	* \| \| \|Trigger delay time = (TRGDLYCNT + 4) x Trigger delay clock period.
sahilmgandhi	18:6a4db94011d3	7976	* \|[16:17] \|TRGDLYDIV \|A/D SAMPLE Start Of Conversion Trigger Delay Clock Divider Selection
sahilmgandhi	18:6a4db94011d3	7977	* \| \| \|Trigger delay clock frequency:
sahilmgandhi	18:6a4db94011d3	7978	* \| \| \|00 = ADC_CLK/1.
sahilmgandhi	18:6a4db94011d3	7979	* \| \| \|01 = ADC_CLK/2.
sahilmgandhi	18:6a4db94011d3	7980	* \| \| \|10 = ADC_CLK/4.
sahilmgandhi	18:6a4db94011d3	7981	* \| \| \|11 = ADC_CLK/16.
sahilmgandhi	18:6a4db94011d3	7982	* \|[20] \|EXTREN \|A/D External Pin Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	7983	* \| \| \|0 = A/D external pin rising edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	7984	* \| \| \|1 = A/D external pin rising edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	7985	* \|[21] \|EXTFEN \|A/D External Pin Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	7986	* \| \| \|0 = A/D external pin falling edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	7987	* \| \| \|1 = A/D external pin falling edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	7988	*/
sahilmgandhi	18:6a4db94011d3	7989	__IO uint32_t AD0SPCTL0;
sahilmgandhi	18:6a4db94011d3	7990
sahilmgandhi	18:6a4db94011d3	7991	/**
sahilmgandhi	18:6a4db94011d3	7992	* AD0SPCTL1
sahilmgandhi	18:6a4db94011d3	7993	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	7994	* Offset: 0x5C A/D SAMPLE01 Control Register
sahilmgandhi	18:6a4db94011d3	7995	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	7996	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	7997	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	7998	* \|[0:3] \|CHSEL \|A/D SAMPLE0,1 Channel Selection
sahilmgandhi	18:6a4db94011d3	7999	* \| \| \|0000 = ADCn_CH0.
sahilmgandhi	18:6a4db94011d3	8000	* \| \| \|0001 = ADCn_CH1.
sahilmgandhi	18:6a4db94011d3	8001	* \| \| \|0010 = ADCn_CH2.
sahilmgandhi	18:6a4db94011d3	8002	* \| \| \|0011 = ADCn_CH3.
sahilmgandhi	18:6a4db94011d3	8003	* \| \| \|0100 = ADCn_CH4.
sahilmgandhi	18:6a4db94011d3	8004	* \| \| \|0101 = ADCn_CH5.
sahilmgandhi	18:6a4db94011d3	8005	* \| \| \|0110 = ADCn_CH6.
sahilmgandhi	18:6a4db94011d3	8006	* \| \| \|0111 = ADCn_CH7.
sahilmgandhi	18:6a4db94011d3	8007	* \| \| \|For SAMPLE0
sahilmgandhi	18:6a4db94011d3	8008	* \| \| \|1000 = VBG.
sahilmgandhi	18:6a4db94011d3	8009	* \| \| \|1001 = VTEMP.
sahilmgandhi	18:6a4db94011d3	8010	* \| \| \|1010 = AVSS.
sahilmgandhi	18:6a4db94011d3	8011	* \| \| \|1011 = OP0.
sahilmgandhi	18:6a4db94011d3	8012	* \| \| \|For SAMPLE1
sahilmgandhi	18:6a4db94011d3	8013	* \| \| \|1000= OP1.
sahilmgandhi	18:6a4db94011d3	8014	* \|[4:7] \|TRGSEL \|A/D SAMPLE Start Of Conversion Trigger Source Selection
sahilmgandhi	18:6a4db94011d3	8015	* \| \| \|0000 = Disable hardware trigger.
sahilmgandhi	18:6a4db94011d3	8016	* \| \| \|0001 = External pin (STADC) trigger.
sahilmgandhi	18:6a4db94011d3	8017	* \| \| \|0010 = ADC ADINT0 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8018	* \| \| \|0011 = ADC ADINT1 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8019	* \| \| \|0100 = Timer0 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8020	* \| \| \|0101 = Timer1 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8021	* \| \| \|0110 = Timer2 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8022	* \| \| \|0111 = Timer3 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8023	* \| \| \|1000 = EPWM0_CH0 trigger.
sahilmgandhi	18:6a4db94011d3	8024	* \| \| \|1001 = EPWM0_CH2 trigger.
sahilmgandhi	18:6a4db94011d3	8025	* \| \| \|1010 = EPWM0_CH4 trigger.
sahilmgandhi	18:6a4db94011d3	8026	* \| \| \|1011 = EPWM1_CH0 trigger.
sahilmgandhi	18:6a4db94011d3	8027	* \| \| \|1100 = EPWM1_CH2 trigger.
sahilmgandhi	18:6a4db94011d3	8028	* \| \| \|1101 = EPWM1_CH4 trigger.
sahilmgandhi	18:6a4db94011d3	8029	* \| \| \|1110 = PWM0_CH0 trigger.
sahilmgandhi	18:6a4db94011d3	8030	* \| \| \|1111 = PWM0_CH1 trigger.
sahilmgandhi	18:6a4db94011d3	8031	* \|[8:15] \|TRGDLYCNT \|A/D SAMPLE Start Of Conversion Trigger Delay Time
sahilmgandhi	18:6a4db94011d3	8032	* \| \| \|Trigger delay time = (TRGDLYCNT + 4) x Trigger delay clock period.
sahilmgandhi	18:6a4db94011d3	8033	* \|[16:17] \|TRGDLYDIV \|A/D SAMPLE Start Of Conversion Trigger Delay Clock Divider Selection
sahilmgandhi	18:6a4db94011d3	8034	* \| \| \|Trigger delay clock frequency:
sahilmgandhi	18:6a4db94011d3	8035	* \| \| \|00 = ADC_CLK/1.
sahilmgandhi	18:6a4db94011d3	8036	* \| \| \|01 = ADC_CLK/2.
sahilmgandhi	18:6a4db94011d3	8037	* \| \| \|10 = ADC_CLK/4.
sahilmgandhi	18:6a4db94011d3	8038	* \| \| \|11 = ADC_CLK/16.
sahilmgandhi	18:6a4db94011d3	8039	* \|[20] \|EXTREN \|A/D External Pin Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8040	* \| \| \|0 = A/D external pin rising edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8041	* \| \| \|1 = A/D external pin rising edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8042	* \|[21] \|EXTFEN \|A/D External Pin Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8043	* \| \| \|0 = A/D external pin falling edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8044	* \| \| \|1 = A/D external pin falling edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8045	*/
sahilmgandhi	18:6a4db94011d3	8046	__IO uint32_t AD0SPCTL1;
sahilmgandhi	18:6a4db94011d3	8047
sahilmgandhi	18:6a4db94011d3	8048	/**
sahilmgandhi	18:6a4db94011d3	8049	* AD0SPCTL2
sahilmgandhi	18:6a4db94011d3	8050	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	8051	* Offset: 0x60 A/D SAMPLE02 Control Register
sahilmgandhi	18:6a4db94011d3	8052	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	8053	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	8054	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	8055	* \|[0:3] \|CHSEL \|A/D SAMPLE0,1 Channel Selection
sahilmgandhi	18:6a4db94011d3	8056	* \| \| \|0000 = ADCn_CH0.
sahilmgandhi	18:6a4db94011d3	8057	* \| \| \|0001 = ADCn_CH1.
sahilmgandhi	18:6a4db94011d3	8058	* \| \| \|0010 = ADCn_CH2.
sahilmgandhi	18:6a4db94011d3	8059	* \| \| \|0011 = ADCn_CH3.
sahilmgandhi	18:6a4db94011d3	8060	* \| \| \|0100 = ADCn_CH4.
sahilmgandhi	18:6a4db94011d3	8061	* \| \| \|0101 = ADCn_CH5.
sahilmgandhi	18:6a4db94011d3	8062	* \| \| \|0110 = ADCn_CH6.
sahilmgandhi	18:6a4db94011d3	8063	* \| \| \|0111 = ADCn_CH7.
sahilmgandhi	18:6a4db94011d3	8064	* \| \| \|For SAMPLE0
sahilmgandhi	18:6a4db94011d3	8065	* \| \| \|1000 = VBG.
sahilmgandhi	18:6a4db94011d3	8066	* \| \| \|1001 = VTEMP.
sahilmgandhi	18:6a4db94011d3	8067	* \| \| \|1010 = AVSS.
sahilmgandhi	18:6a4db94011d3	8068	* \| \| \|1011 = OP0.
sahilmgandhi	18:6a4db94011d3	8069	* \| \| \|For SAMPLE1
sahilmgandhi	18:6a4db94011d3	8070	* \| \| \|1000= OP1.
sahilmgandhi	18:6a4db94011d3	8071	* \|[4:7] \|TRGSEL \|A/D SAMPLE Start Of Conversion Trigger Source Selection
sahilmgandhi	18:6a4db94011d3	8072	* \| \| \|0000 = Disable hardware trigger.
sahilmgandhi	18:6a4db94011d3	8073	* \| \| \|0001 = External pin (STADC) trigger.
sahilmgandhi	18:6a4db94011d3	8074	* \| \| \|0010 = ADC ADINT0 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8075	* \| \| \|0011 = ADC ADINT1 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8076	* \| \| \|0100 = Timer0 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8077	* \| \| \|0101 = Timer1 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8078	* \| \| \|0110 = Timer2 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8079	* \| \| \|0111 = Timer3 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8080	* \| \| \|1000 = EPWM0_CH0 trigger.
sahilmgandhi	18:6a4db94011d3	8081	* \| \| \|1001 = EPWM0_CH2 trigger.
sahilmgandhi	18:6a4db94011d3	8082	* \| \| \|1010 = EPWM0_CH4 trigger.
sahilmgandhi	18:6a4db94011d3	8083	* \| \| \|1011 = EPWM1_CH0 trigger.
sahilmgandhi	18:6a4db94011d3	8084	* \| \| \|1100 = EPWM1_CH2 trigger.
sahilmgandhi	18:6a4db94011d3	8085	* \| \| \|1101 = EPWM1_CH4 trigger.
sahilmgandhi	18:6a4db94011d3	8086	* \| \| \|1110 = PWM0_CH0 trigger.
sahilmgandhi	18:6a4db94011d3	8087	* \| \| \|1111 = PWM0_CH1 trigger.
sahilmgandhi	18:6a4db94011d3	8088	* \|[8:15] \|TRGDLYCNT \|A/D SAMPLE Start Of Conversion Trigger Delay Time
sahilmgandhi	18:6a4db94011d3	8089	* \| \| \|Trigger delay time = (TRGDLYCNT + 4) x Trigger delay clock period.
sahilmgandhi	18:6a4db94011d3	8090	* \|[16:17] \|TRGDLYDIV \|A/D SAMPLE Start Of Conversion Trigger Delay Clock Divider Selection
sahilmgandhi	18:6a4db94011d3	8091	* \| \| \|Trigger delay clock frequency:
sahilmgandhi	18:6a4db94011d3	8092	* \| \| \|00 = ADC_CLK/1.
sahilmgandhi	18:6a4db94011d3	8093	* \| \| \|01 = ADC_CLK/2.
sahilmgandhi	18:6a4db94011d3	8094	* \| \| \|10 = ADC_CLK/4.
sahilmgandhi	18:6a4db94011d3	8095	* \| \| \|11 = ADC_CLK/16.
sahilmgandhi	18:6a4db94011d3	8096	* \|[20] \|EXTREN \|A/D External Pin Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8097	* \| \| \|0 = A/D external pin rising edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8098	* \| \| \|1 = A/D external pin rising edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8099	* \|[21] \|EXTFEN \|A/D External Pin Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8100	* \| \| \|0 = A/D external pin falling edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8101	* \| \| \|1 = A/D external pin falling edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8102	*/
sahilmgandhi	18:6a4db94011d3	8103	__IO uint32_t AD0SPCTL2;
sahilmgandhi	18:6a4db94011d3	8104
sahilmgandhi	18:6a4db94011d3	8105	/**
sahilmgandhi	18:6a4db94011d3	8106	* AD0SPCTL3
sahilmgandhi	18:6a4db94011d3	8107	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	8108	* Offset: 0x64 A/D SAMPLE03 Control Register
sahilmgandhi	18:6a4db94011d3	8109	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	8110	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	8111	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	8112	* \|[0:3] \|CHSEL \|A/D SAMPLE0,1 Channel Selection
sahilmgandhi	18:6a4db94011d3	8113	* \| \| \|0000 = ADCn_CH0.
sahilmgandhi	18:6a4db94011d3	8114	* \| \| \|0001 = ADCn_CH1.
sahilmgandhi	18:6a4db94011d3	8115	* \| \| \|0010 = ADCn_CH2.
sahilmgandhi	18:6a4db94011d3	8116	* \| \| \|0011 = ADCn_CH3.
sahilmgandhi	18:6a4db94011d3	8117	* \| \| \|0100 = ADCn_CH4.
sahilmgandhi	18:6a4db94011d3	8118	* \| \| \|0101 = ADCn_CH5.
sahilmgandhi	18:6a4db94011d3	8119	* \| \| \|0110 = ADCn_CH6.
sahilmgandhi	18:6a4db94011d3	8120	* \| \| \|0111 = ADCn_CH7.
sahilmgandhi	18:6a4db94011d3	8121	* \| \| \|For SAMPLE0
sahilmgandhi	18:6a4db94011d3	8122	* \| \| \|1000 = VBG.
sahilmgandhi	18:6a4db94011d3	8123	* \| \| \|1001 = VTEMP.
sahilmgandhi	18:6a4db94011d3	8124	* \| \| \|1010 = AVSS.
sahilmgandhi	18:6a4db94011d3	8125	* \| \| \|1011 = OP0.
sahilmgandhi	18:6a4db94011d3	8126	* \| \| \|For SAMPLE1
sahilmgandhi	18:6a4db94011d3	8127	* \| \| \|1000= OP1.
sahilmgandhi	18:6a4db94011d3	8128	* \|[4:7] \|TRGSEL \|A/D SAMPLE Start Of Conversion Trigger Source Selection
sahilmgandhi	18:6a4db94011d3	8129	* \| \| \|0000 = Disable hardware trigger.
sahilmgandhi	18:6a4db94011d3	8130	* \| \| \|0001 = External pin (STADC) trigger.
sahilmgandhi	18:6a4db94011d3	8131	* \| \| \|0010 = ADC ADINT0 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8132	* \| \| \|0011 = ADC ADINT1 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8133	* \| \| \|0100 = Timer0 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8134	* \| \| \|0101 = Timer1 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8135	* \| \| \|0110 = Timer2 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8136	* \| \| \|0111 = Timer3 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8137	* \| \| \|1000 = EPWM0_CH0 trigger.
sahilmgandhi	18:6a4db94011d3	8138	* \| \| \|1001 = EPWM0_CH2 trigger.
sahilmgandhi	18:6a4db94011d3	8139	* \| \| \|1010 = EPWM0_CH4 trigger.
sahilmgandhi	18:6a4db94011d3	8140	* \| \| \|1011 = EPWM1_CH0 trigger.
sahilmgandhi	18:6a4db94011d3	8141	* \| \| \|1100 = EPWM1_CH2 trigger.
sahilmgandhi	18:6a4db94011d3	8142	* \| \| \|1101 = EPWM1_CH4 trigger.
sahilmgandhi	18:6a4db94011d3	8143	* \| \| \|1110 = PWM0_CH0 trigger.
sahilmgandhi	18:6a4db94011d3	8144	* \| \| \|1111 = PWM0_CH1 trigger.
sahilmgandhi	18:6a4db94011d3	8145	* \|[8:15] \|TRGDLYCNT \|A/D SAMPLE Start Of Conversion Trigger Delay Time
sahilmgandhi	18:6a4db94011d3	8146	* \| \| \|Trigger delay time = (TRGDLYCNT + 4) x Trigger delay clock period.
sahilmgandhi	18:6a4db94011d3	8147	* \|[16:17] \|TRGDLYDIV \|A/D SAMPLE Start Of Conversion Trigger Delay Clock Divider Selection
sahilmgandhi	18:6a4db94011d3	8148	* \| \| \|Trigger delay clock frequency:
sahilmgandhi	18:6a4db94011d3	8149	* \| \| \|00 = ADC_CLK/1.
sahilmgandhi	18:6a4db94011d3	8150	* \| \| \|01 = ADC_CLK/2.
sahilmgandhi	18:6a4db94011d3	8151	* \| \| \|10 = ADC_CLK/4.
sahilmgandhi	18:6a4db94011d3	8152	* \| \| \|11 = ADC_CLK/16.
sahilmgandhi	18:6a4db94011d3	8153	* \|[20] \|EXTREN \|A/D External Pin Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8154	* \| \| \|0 = A/D external pin rising edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8155	* \| \| \|1 = A/D external pin rising edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8156	* \|[21] \|EXTFEN \|A/D External Pin Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8157	* \| \| \|0 = A/D external pin falling edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8158	* \| \| \|1 = A/D external pin falling edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8159	*/
sahilmgandhi	18:6a4db94011d3	8160	__IO uint32_t AD0SPCTL3;
sahilmgandhi	18:6a4db94011d3	8161
sahilmgandhi	18:6a4db94011d3	8162	/**
sahilmgandhi	18:6a4db94011d3	8163	* AD0SPCTL4
sahilmgandhi	18:6a4db94011d3	8164	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	8165	* Offset: 0x68 A/D SAMPLE04 Control Register
sahilmgandhi	18:6a4db94011d3	8166	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	8167	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	8168	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	8169	* \|[0:3] \|CHSEL \|A/D SAMPLE0,1 Channel Selection
sahilmgandhi	18:6a4db94011d3	8170	* \| \| \|0000 = ADCn_CH0.
sahilmgandhi	18:6a4db94011d3	8171	* \| \| \|0001 = ADCn_CH1.
sahilmgandhi	18:6a4db94011d3	8172	* \| \| \|0010 = ADCn_CH2.
sahilmgandhi	18:6a4db94011d3	8173	* \| \| \|0011 = ADCn_CH3.
sahilmgandhi	18:6a4db94011d3	8174	* \| \| \|0100 = ADCn_CH4.
sahilmgandhi	18:6a4db94011d3	8175	* \| \| \|0101 = ADCn_CH5.
sahilmgandhi	18:6a4db94011d3	8176	* \| \| \|0110 = ADCn_CH6.
sahilmgandhi	18:6a4db94011d3	8177	* \| \| \|0111 = ADCn_CH7.
sahilmgandhi	18:6a4db94011d3	8178	* \| \| \|For SAMPLE0
sahilmgandhi	18:6a4db94011d3	8179	* \| \| \|1000 = VBG.
sahilmgandhi	18:6a4db94011d3	8180	* \| \| \|1001 = VTEMP.
sahilmgandhi	18:6a4db94011d3	8181	* \| \| \|1010 = AVSS.
sahilmgandhi	18:6a4db94011d3	8182	* \| \| \|1011 = OP0.
sahilmgandhi	18:6a4db94011d3	8183	* \| \| \|For SAMPLE1
sahilmgandhi	18:6a4db94011d3	8184	* \| \| \|1000= OP1.
sahilmgandhi	18:6a4db94011d3	8185	* \|[4:6] \|TRGSEL \|A/D SAMPLE Start Of Conversion Trigger Source Selection
sahilmgandhi	18:6a4db94011d3	8186	* \| \| \|000 = Disable hardware trigger.
sahilmgandhi	18:6a4db94011d3	8187	* \| \| \|001 = External pin (STADC) trigger.
sahilmgandhi	18:6a4db94011d3	8188	* \| \| \|010 = ADC ADINT0 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8189	* \| \| \|011 = ADC ADINT1 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8190	* \| \| \|100 = Timer0 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8191	* \| \| \|101 = Timer1 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8192	* \| \| \|110 = Timer2 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8193	* \| \| \|111 = Timer3 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8194	* \|[20] \|EXTREN \|A/D External Pin Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8195	* \| \| \|0 = A/D external pin rising edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8196	* \| \| \|1 = A/D external pin rising edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8197	* \|[21] \|EXTFEN \|A/D External Pin Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8198	* \| \| \|0 = A/D external pin falling edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8199	* \| \| \|1 = A/D external pin falling edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8200	*/
sahilmgandhi	18:6a4db94011d3	8201	__IO uint32_t AD0SPCTL4;
sahilmgandhi	18:6a4db94011d3	8202
sahilmgandhi	18:6a4db94011d3	8203	/**
sahilmgandhi	18:6a4db94011d3	8204	* AD0SPCTL5
sahilmgandhi	18:6a4db94011d3	8205	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	8206	* Offset: 0x6C A/D SAMPLE05 Control Register
sahilmgandhi	18:6a4db94011d3	8207	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	8208	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	8209	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	8210	* \|[0:3] \|CHSEL \|A/D SAMPLE0,1 Channel Selection
sahilmgandhi	18:6a4db94011d3	8211	* \| \| \|0000 = ADCn_CH0.
sahilmgandhi	18:6a4db94011d3	8212	* \| \| \|0001 = ADCn_CH1.
sahilmgandhi	18:6a4db94011d3	8213	* \| \| \|0010 = ADCn_CH2.
sahilmgandhi	18:6a4db94011d3	8214	* \| \| \|0011 = ADCn_CH3.
sahilmgandhi	18:6a4db94011d3	8215	* \| \| \|0100 = ADCn_CH4.
sahilmgandhi	18:6a4db94011d3	8216	* \| \| \|0101 = ADCn_CH5.
sahilmgandhi	18:6a4db94011d3	8217	* \| \| \|0110 = ADCn_CH6.
sahilmgandhi	18:6a4db94011d3	8218	* \| \| \|0111 = ADCn_CH7.
sahilmgandhi	18:6a4db94011d3	8219	* \| \| \|For SAMPLE0
sahilmgandhi	18:6a4db94011d3	8220	* \| \| \|1000 = VBG.
sahilmgandhi	18:6a4db94011d3	8221	* \| \| \|1001 = VTEMP.
sahilmgandhi	18:6a4db94011d3	8222	* \| \| \|1010 = AVSS.
sahilmgandhi	18:6a4db94011d3	8223	* \| \| \|1011 = OP0.
sahilmgandhi	18:6a4db94011d3	8224	* \| \| \|For SAMPLE1
sahilmgandhi	18:6a4db94011d3	8225	* \| \| \|1000= OP1.
sahilmgandhi	18:6a4db94011d3	8226	* \|[4:6] \|TRGSEL \|A/D SAMPLE Start Of Conversion Trigger Source Selection
sahilmgandhi	18:6a4db94011d3	8227	* \| \| \|000 = Disable hardware trigger.
sahilmgandhi	18:6a4db94011d3	8228	* \| \| \|001 = External pin (STADC) trigger.
sahilmgandhi	18:6a4db94011d3	8229	* \| \| \|010 = ADC ADINT0 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8230	* \| \| \|011 = ADC ADINT1 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8231	* \| \| \|100 = Timer0 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8232	* \| \| \|101 = Timer1 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8233	* \| \| \|110 = Timer2 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8234	* \| \| \|111 = Timer3 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8235	* \|[20] \|EXTREN \|A/D External Pin Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8236	* \| \| \|0 = A/D external pin rising edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8237	* \| \| \|1 = A/D external pin rising edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8238	* \|[21] \|EXTFEN \|A/D External Pin Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8239	* \| \| \|0 = A/D external pin falling edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8240	* \| \| \|1 = A/D external pin falling edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8241	*/
sahilmgandhi	18:6a4db94011d3	8242	__IO uint32_t AD0SPCTL5;
sahilmgandhi	18:6a4db94011d3	8243
sahilmgandhi	18:6a4db94011d3	8244	/**
sahilmgandhi	18:6a4db94011d3	8245	* AD0SPCTL6
sahilmgandhi	18:6a4db94011d3	8246	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	8247	* Offset: 0x70 A/D SAMPLE06 Control Register
sahilmgandhi	18:6a4db94011d3	8248	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	8249	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	8250	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	8251	* \|[0:3] \|CHSEL \|A/D SAMPLE0,1 Channel Selection
sahilmgandhi	18:6a4db94011d3	8252	* \| \| \|0000 = ADCn_CH0.
sahilmgandhi	18:6a4db94011d3	8253	* \| \| \|0001 = ADCn_CH1.
sahilmgandhi	18:6a4db94011d3	8254	* \| \| \|0010 = ADCn_CH2.
sahilmgandhi	18:6a4db94011d3	8255	* \| \| \|0011 = ADCn_CH3.
sahilmgandhi	18:6a4db94011d3	8256	* \| \| \|0100 = ADCn_CH4.
sahilmgandhi	18:6a4db94011d3	8257	* \| \| \|0101 = ADCn_CH5.
sahilmgandhi	18:6a4db94011d3	8258	* \| \| \|0110 = ADCn_CH6.
sahilmgandhi	18:6a4db94011d3	8259	* \| \| \|0111 = ADCn_CH7.
sahilmgandhi	18:6a4db94011d3	8260	* \| \| \|For SAMPLE0
sahilmgandhi	18:6a4db94011d3	8261	* \| \| \|1000 = VBG.
sahilmgandhi	18:6a4db94011d3	8262	* \| \| \|1001 = VTEMP.
sahilmgandhi	18:6a4db94011d3	8263	* \| \| \|1010 = AVSS.
sahilmgandhi	18:6a4db94011d3	8264	* \| \| \|1011 = OP0.
sahilmgandhi	18:6a4db94011d3	8265	* \| \| \|For SAMPLE1
sahilmgandhi	18:6a4db94011d3	8266	* \| \| \|1000= OP1.
sahilmgandhi	18:6a4db94011d3	8267	* \|[4:6] \|TRGSEL \|A/D SAMPLE Start Of Conversion Trigger Source Selection
sahilmgandhi	18:6a4db94011d3	8268	* \| \| \|000 = Disable hardware trigger.
sahilmgandhi	18:6a4db94011d3	8269	* \| \| \|001 = External pin (STADC) trigger.
sahilmgandhi	18:6a4db94011d3	8270	* \| \| \|010 = ADC ADINT0 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8271	* \| \| \|011 = ADC ADINT1 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8272	* \| \| \|100 = Timer0 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8273	* \| \| \|101 = Timer1 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8274	* \| \| \|110 = Timer2 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8275	* \| \| \|111 = Timer3 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8276	* \|[20] \|EXTREN \|A/D External Pin Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8277	* \| \| \|0 = A/D external pin rising edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8278	* \| \| \|1 = A/D external pin rising edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8279	* \|[21] \|EXTFEN \|A/D External Pin Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8280	* \| \| \|0 = A/D external pin falling edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8281	* \| \| \|1 = A/D external pin falling edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8282	*/
sahilmgandhi	18:6a4db94011d3	8283	__IO uint32_t AD0SPCTL6;
sahilmgandhi	18:6a4db94011d3	8284
sahilmgandhi	18:6a4db94011d3	8285	/**
sahilmgandhi	18:6a4db94011d3	8286	* AD0SPCTL7
sahilmgandhi	18:6a4db94011d3	8287	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	8288	* Offset: 0x74 A/D SAMPLE07 Control Register
sahilmgandhi	18:6a4db94011d3	8289	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	8290	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	8291	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	8292	* \|[0:3] \|CHSEL \|A/D SAMPLE0,1 Channel Selection
sahilmgandhi	18:6a4db94011d3	8293	* \| \| \|0000 = ADCn_CH0.
sahilmgandhi	18:6a4db94011d3	8294	* \| \| \|0001 = ADCn_CH1.
sahilmgandhi	18:6a4db94011d3	8295	* \| \| \|0010 = ADCn_CH2.
sahilmgandhi	18:6a4db94011d3	8296	* \| \| \|0011 = ADCn_CH3.
sahilmgandhi	18:6a4db94011d3	8297	* \| \| \|0100 = ADCn_CH4.
sahilmgandhi	18:6a4db94011d3	8298	* \| \| \|0101 = ADCn_CH5.
sahilmgandhi	18:6a4db94011d3	8299	* \| \| \|0110 = ADCn_CH6.
sahilmgandhi	18:6a4db94011d3	8300	* \| \| \|0111 = ADCn_CH7.
sahilmgandhi	18:6a4db94011d3	8301	* \| \| \|For SAMPLE0
sahilmgandhi	18:6a4db94011d3	8302	* \| \| \|1000 = VBG.
sahilmgandhi	18:6a4db94011d3	8303	* \| \| \|1001 = VTEMP.
sahilmgandhi	18:6a4db94011d3	8304	* \| \| \|1010 = AVSS.
sahilmgandhi	18:6a4db94011d3	8305	* \| \| \|1011 = OP0.
sahilmgandhi	18:6a4db94011d3	8306	* \| \| \|For SAMPLE1
sahilmgandhi	18:6a4db94011d3	8307	* \| \| \|1000= OP1.
sahilmgandhi	18:6a4db94011d3	8308	* \|[4:6] \|TRGSEL \|A/D SAMPLE Start Of Conversion Trigger Source Selection
sahilmgandhi	18:6a4db94011d3	8309	* \| \| \|000 = Disable hardware trigger.
sahilmgandhi	18:6a4db94011d3	8310	* \| \| \|001 = External pin (STADC) trigger.
sahilmgandhi	18:6a4db94011d3	8311	* \| \| \|010 = ADC ADINT0 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8312	* \| \| \|011 = ADC ADINT1 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8313	* \| \| \|100 = Timer0 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8314	* \| \| \|101 = Timer1 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8315	* \| \| \|110 = Timer2 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8316	* \| \| \|111 = Timer3 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8317	* \|[20] \|EXTREN \|A/D External Pin Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8318	* \| \| \|0 = A/D external pin rising edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8319	* \| \| \|1 = A/D external pin rising edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8320	* \|[21] \|EXTFEN \|A/D External Pin Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8321	* \| \| \|0 = A/D external pin falling edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8322	* \| \| \|1 = A/D external pin falling edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8323	*/
sahilmgandhi	18:6a4db94011d3	8324	__IO uint32_t AD0SPCTL7;
sahilmgandhi	18:6a4db94011d3	8325
sahilmgandhi	18:6a4db94011d3	8326	/**
sahilmgandhi	18:6a4db94011d3	8327	* AD1SPCTL0
sahilmgandhi	18:6a4db94011d3	8328	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	8329	* Offset: 0x78 A/D SAMPLE10 Control Register
sahilmgandhi	18:6a4db94011d3	8330	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	8331	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	8332	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	8333	* \|[0:3] \|CHSEL \|A/D SAMPLE0,1 Channel Selection
sahilmgandhi	18:6a4db94011d3	8334	* \| \| \|0000 = ADCn_CH0.
sahilmgandhi	18:6a4db94011d3	8335	* \| \| \|0001 = ADCn_CH1.
sahilmgandhi	18:6a4db94011d3	8336	* \| \| \|0010 = ADCn_CH2.
sahilmgandhi	18:6a4db94011d3	8337	* \| \| \|0011 = ADCn_CH3.
sahilmgandhi	18:6a4db94011d3	8338	* \| \| \|0100 = ADCn_CH4.
sahilmgandhi	18:6a4db94011d3	8339	* \| \| \|0101 = ADCn_CH5.
sahilmgandhi	18:6a4db94011d3	8340	* \| \| \|0110 = ADCn_CH6.
sahilmgandhi	18:6a4db94011d3	8341	* \| \| \|0111 = ADCn_CH7.
sahilmgandhi	18:6a4db94011d3	8342	* \| \| \|For SAMPLE0
sahilmgandhi	18:6a4db94011d3	8343	* \| \| \|1000 = VBG.
sahilmgandhi	18:6a4db94011d3	8344	* \| \| \|1001 = VTEMP.
sahilmgandhi	18:6a4db94011d3	8345	* \| \| \|1010 = AVSS.
sahilmgandhi	18:6a4db94011d3	8346	* \| \| \|1011 = OP0.
sahilmgandhi	18:6a4db94011d3	8347	* \| \| \|For SAMPLE1
sahilmgandhi	18:6a4db94011d3	8348	* \| \| \|1000= OP1.
sahilmgandhi	18:6a4db94011d3	8349	* \|[4:7] \|TRGSEL \|A/D SAMPLE Start Of Conversion Trigger Source Selection
sahilmgandhi	18:6a4db94011d3	8350	* \| \| \|0000 = Disable hardware trigger.
sahilmgandhi	18:6a4db94011d3	8351	* \| \| \|0001 = External pin (STADC) trigger.
sahilmgandhi	18:6a4db94011d3	8352	* \| \| \|0010 = ADC ADINT0 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8353	* \| \| \|0011 = ADC ADINT1 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8354	* \| \| \|0100 = Timer0 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8355	* \| \| \|0101 = Timer1 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8356	* \| \| \|0110 = Timer2 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8357	* \| \| \|0111 = Timer3 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8358	* \| \| \|1000 = EPWM0_CH0 trigger.
sahilmgandhi	18:6a4db94011d3	8359	* \| \| \|1001 = EPWM0_CH2 trigger.
sahilmgandhi	18:6a4db94011d3	8360	* \| \| \|1010 = EPWM0_CH4 trigger.
sahilmgandhi	18:6a4db94011d3	8361	* \| \| \|1011 = EPWM1_CH0 trigger.
sahilmgandhi	18:6a4db94011d3	8362	* \| \| \|1100 = EPWM1_CH2 trigger.
sahilmgandhi	18:6a4db94011d3	8363	* \| \| \|1101 = EPWM1_CH4 trigger.
sahilmgandhi	18:6a4db94011d3	8364	* \| \| \|1110 = PWM0_CH0 trigger.
sahilmgandhi	18:6a4db94011d3	8365	* \| \| \|1111 = PWM0_CH1 trigger.
sahilmgandhi	18:6a4db94011d3	8366	* \|[8:15] \|TRGDLYCNT \|A/D SAMPLE Start Of Conversion Trigger Delay Time
sahilmgandhi	18:6a4db94011d3	8367	* \| \| \|Trigger delay time = (TRGDLYCNT + 4) x Trigger delay clock period.
sahilmgandhi	18:6a4db94011d3	8368	* \|[16:17] \|TRGDLYDIV \|A/D SAMPLE Start Of Conversion Trigger Delay Clock Divider Selection
sahilmgandhi	18:6a4db94011d3	8369	* \| \| \|Trigger delay clock frequency:
sahilmgandhi	18:6a4db94011d3	8370	* \| \| \|00 = ADC_CLK/1.
sahilmgandhi	18:6a4db94011d3	8371	* \| \| \|01 = ADC_CLK/2.
sahilmgandhi	18:6a4db94011d3	8372	* \| \| \|10 = ADC_CLK/4.
sahilmgandhi	18:6a4db94011d3	8373	* \| \| \|11 = ADC_CLK/16.
sahilmgandhi	18:6a4db94011d3	8374	* \|[20] \|EXTREN \|A/D External Pin Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8375	* \| \| \|0 = A/D external pin rising edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8376	* \| \| \|1 = A/D external pin rising edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8377	* \|[21] \|EXTFEN \|A/D External Pin Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8378	* \| \| \|0 = A/D external pin falling edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8379	* \| \| \|1 = A/D external pin falling edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8380	*/
sahilmgandhi	18:6a4db94011d3	8381	__IO uint32_t AD1SPCTL0;
sahilmgandhi	18:6a4db94011d3	8382
sahilmgandhi	18:6a4db94011d3	8383	/**
sahilmgandhi	18:6a4db94011d3	8384	* AD1SPCTL1
sahilmgandhi	18:6a4db94011d3	8385	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	8386	* Offset: 0x7C A/D SAMPLE11 Control Register
sahilmgandhi	18:6a4db94011d3	8387	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	8388	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	8389	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	8390	* \|[0:3] \|CHSEL \|A/D SAMPLE0,1 Channel Selection
sahilmgandhi	18:6a4db94011d3	8391	* \| \| \|0000 = ADCn_CH0.
sahilmgandhi	18:6a4db94011d3	8392	* \| \| \|0001 = ADCn_CH1.
sahilmgandhi	18:6a4db94011d3	8393	* \| \| \|0010 = ADCn_CH2.
sahilmgandhi	18:6a4db94011d3	8394	* \| \| \|0011 = ADCn_CH3.
sahilmgandhi	18:6a4db94011d3	8395	* \| \| \|0100 = ADCn_CH4.
sahilmgandhi	18:6a4db94011d3	8396	* \| \| \|0101 = ADCn_CH5.
sahilmgandhi	18:6a4db94011d3	8397	* \| \| \|0110 = ADCn_CH6.
sahilmgandhi	18:6a4db94011d3	8398	* \| \| \|0111 = ADCn_CH7.
sahilmgandhi	18:6a4db94011d3	8399	* \| \| \|For SAMPLE0
sahilmgandhi	18:6a4db94011d3	8400	* \| \| \|1000 = VBG.
sahilmgandhi	18:6a4db94011d3	8401	* \| \| \|1001 = VTEMP.
sahilmgandhi	18:6a4db94011d3	8402	* \| \| \|1010 = AVSS.
sahilmgandhi	18:6a4db94011d3	8403	* \| \| \|1011 = OP0.
sahilmgandhi	18:6a4db94011d3	8404	* \| \| \|For SAMPLE1
sahilmgandhi	18:6a4db94011d3	8405	* \| \| \|1000= OP1.
sahilmgandhi	18:6a4db94011d3	8406	* \|[4:7] \|TRGSEL \|A/D SAMPLE Start Of Conversion Trigger Source Selection
sahilmgandhi	18:6a4db94011d3	8407	* \| \| \|0000 = Disable hardware trigger.
sahilmgandhi	18:6a4db94011d3	8408	* \| \| \|0001 = External pin (STADC) trigger.
sahilmgandhi	18:6a4db94011d3	8409	* \| \| \|0010 = ADC ADINT0 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8410	* \| \| \|0011 = ADC ADINT1 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8411	* \| \| \|0100 = Timer0 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8412	* \| \| \|0101 = Timer1 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8413	* \| \| \|0110 = Timer2 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8414	* \| \| \|0111 = Timer3 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8415	* \| \| \|1000 = EPWM0_CH0 trigger.
sahilmgandhi	18:6a4db94011d3	8416	* \| \| \|1001 = EPWM0_CH2 trigger.
sahilmgandhi	18:6a4db94011d3	8417	* \| \| \|1010 = EPWM0_CH4 trigger.
sahilmgandhi	18:6a4db94011d3	8418	* \| \| \|1011 = EPWM1_CH0 trigger.
sahilmgandhi	18:6a4db94011d3	8419	* \| \| \|1100 = EPWM1_CH2 trigger.
sahilmgandhi	18:6a4db94011d3	8420	* \| \| \|1101 = EPWM1_CH4 trigger.
sahilmgandhi	18:6a4db94011d3	8421	* \| \| \|1110 = PWM0_CH0 trigger.
sahilmgandhi	18:6a4db94011d3	8422	* \| \| \|1111 = PWM0_CH1 trigger.
sahilmgandhi	18:6a4db94011d3	8423	* \|[8:15] \|TRGDLYCNT \|A/D SAMPLE Start Of Conversion Trigger Delay Time
sahilmgandhi	18:6a4db94011d3	8424	* \| \| \|Trigger delay time = (TRGDLYCNT + 4) x Trigger delay clock period.
sahilmgandhi	18:6a4db94011d3	8425	* \|[16:17] \|TRGDLYDIV \|A/D SAMPLE Start Of Conversion Trigger Delay Clock Divider Selection
sahilmgandhi	18:6a4db94011d3	8426	* \| \| \|Trigger delay clock frequency:
sahilmgandhi	18:6a4db94011d3	8427	* \| \| \|00 = ADC_CLK/1.
sahilmgandhi	18:6a4db94011d3	8428	* \| \| \|01 = ADC_CLK/2.
sahilmgandhi	18:6a4db94011d3	8429	* \| \| \|10 = ADC_CLK/4.
sahilmgandhi	18:6a4db94011d3	8430	* \| \| \|11 = ADC_CLK/16.
sahilmgandhi	18:6a4db94011d3	8431	* \|[20] \|EXTREN \|A/D External Pin Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8432	* \| \| \|0 = A/D external pin rising edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8433	* \| \| \|1 = A/D external pin rising edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8434	* \|[21] \|EXTFEN \|A/D External Pin Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8435	* \| \| \|0 = A/D external pin falling edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8436	* \| \| \|1 = A/D external pin falling edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8437	*/
sahilmgandhi	18:6a4db94011d3	8438	__IO uint32_t AD1SPCTL1;
sahilmgandhi	18:6a4db94011d3	8439
sahilmgandhi	18:6a4db94011d3	8440	/**
sahilmgandhi	18:6a4db94011d3	8441	* AD1SPCTL2
sahilmgandhi	18:6a4db94011d3	8442	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	8443	* Offset: 0x80 A/D SAMPLE12 Control Register
sahilmgandhi	18:6a4db94011d3	8444	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	8445	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	8446	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	8447	* \|[0:3] \|CHSEL \|A/D SAMPLE0,1 Channel Selection
sahilmgandhi	18:6a4db94011d3	8448	* \| \| \|0000 = ADCn_CH0.
sahilmgandhi	18:6a4db94011d3	8449	* \| \| \|0001 = ADCn_CH1.
sahilmgandhi	18:6a4db94011d3	8450	* \| \| \|0010 = ADCn_CH2.
sahilmgandhi	18:6a4db94011d3	8451	* \| \| \|0011 = ADCn_CH3.
sahilmgandhi	18:6a4db94011d3	8452	* \| \| \|0100 = ADCn_CH4.
sahilmgandhi	18:6a4db94011d3	8453	* \| \| \|0101 = ADCn_CH5.
sahilmgandhi	18:6a4db94011d3	8454	* \| \| \|0110 = ADCn_CH6.
sahilmgandhi	18:6a4db94011d3	8455	* \| \| \|0111 = ADCn_CH7.
sahilmgandhi	18:6a4db94011d3	8456	* \| \| \|For SAMPLE0
sahilmgandhi	18:6a4db94011d3	8457	* \| \| \|1000 = VBG.
sahilmgandhi	18:6a4db94011d3	8458	* \| \| \|1001 = VTEMP.
sahilmgandhi	18:6a4db94011d3	8459	* \| \| \|1010 = AVSS.
sahilmgandhi	18:6a4db94011d3	8460	* \| \| \|1011 = OP0.
sahilmgandhi	18:6a4db94011d3	8461	* \| \| \|For SAMPLE1
sahilmgandhi	18:6a4db94011d3	8462	* \| \| \|1000= OP1.
sahilmgandhi	18:6a4db94011d3	8463	* \|[4:7] \|TRGSEL \|A/D SAMPLE Start Of Conversion Trigger Source Selection
sahilmgandhi	18:6a4db94011d3	8464	* \| \| \|0000 = Disable hardware trigger.
sahilmgandhi	18:6a4db94011d3	8465	* \| \| \|0001 = External pin (STADC) trigger.
sahilmgandhi	18:6a4db94011d3	8466	* \| \| \|0010 = ADC ADINT0 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8467	* \| \| \|0011 = ADC ADINT1 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8468	* \| \| \|0100 = Timer0 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8469	* \| \| \|0101 = Timer1 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8470	* \| \| \|0110 = Timer2 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8471	* \| \| \|0111 = Timer3 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8472	* \| \| \|1000 = EPWM0_CH0 trigger.
sahilmgandhi	18:6a4db94011d3	8473	* \| \| \|1001 = EPWM0_CH2 trigger.
sahilmgandhi	18:6a4db94011d3	8474	* \| \| \|1010 = EPWM0_CH4 trigger.
sahilmgandhi	18:6a4db94011d3	8475	* \| \| \|1011 = EPWM1_CH0 trigger.
sahilmgandhi	18:6a4db94011d3	8476	* \| \| \|1100 = EPWM1_CH2 trigger.
sahilmgandhi	18:6a4db94011d3	8477	* \| \| \|1101 = EPWM1_CH4 trigger.
sahilmgandhi	18:6a4db94011d3	8478	* \| \| \|1110 = PWM0_CH0 trigger.
sahilmgandhi	18:6a4db94011d3	8479	* \| \| \|1111 = PWM0_CH1 trigger.
sahilmgandhi	18:6a4db94011d3	8480	* \|[8:15] \|TRGDLYCNT \|A/D SAMPLE Start Of Conversion Trigger Delay Time
sahilmgandhi	18:6a4db94011d3	8481	* \| \| \|Trigger delay time = (TRGDLYCNT + 4) x Trigger delay clock period.
sahilmgandhi	18:6a4db94011d3	8482	* \|[16:17] \|TRGDLYDIV \|A/D SAMPLE Start Of Conversion Trigger Delay Clock Divider Selection
sahilmgandhi	18:6a4db94011d3	8483	* \| \| \|Trigger delay clock frequency:
sahilmgandhi	18:6a4db94011d3	8484	* \| \| \|00 = ADC_CLK/1.
sahilmgandhi	18:6a4db94011d3	8485	* \| \| \|01 = ADC_CLK/2.
sahilmgandhi	18:6a4db94011d3	8486	* \| \| \|10 = ADC_CLK/4.
sahilmgandhi	18:6a4db94011d3	8487	* \| \| \|11 = ADC_CLK/16.
sahilmgandhi	18:6a4db94011d3	8488	* \|[20] \|EXTREN \|A/D External Pin Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8489	* \| \| \|0 = A/D external pin rising edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8490	* \| \| \|1 = A/D external pin rising edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8491	* \|[21] \|EXTFEN \|A/D External Pin Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8492	* \| \| \|0 = A/D external pin falling edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8493	* \| \| \|1 = A/D external pin falling edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8494	*/
sahilmgandhi	18:6a4db94011d3	8495	__IO uint32_t AD1SPCTL2;
sahilmgandhi	18:6a4db94011d3	8496
sahilmgandhi	18:6a4db94011d3	8497	/**
sahilmgandhi	18:6a4db94011d3	8498	* AD1SPCTL3
sahilmgandhi	18:6a4db94011d3	8499	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	8500	* Offset: 0x84 A/D SAMPLE13 Control Register
sahilmgandhi	18:6a4db94011d3	8501	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	8502	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	8503	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	8504	* \|[0:3] \|CHSEL \|A/D SAMPLE0,1 Channel Selection
sahilmgandhi	18:6a4db94011d3	8505	* \| \| \|0000 = ADCn_CH0.
sahilmgandhi	18:6a4db94011d3	8506	* \| \| \|0001 = ADCn_CH1.
sahilmgandhi	18:6a4db94011d3	8507	* \| \| \|0010 = ADCn_CH2.
sahilmgandhi	18:6a4db94011d3	8508	* \| \| \|0011 = ADCn_CH3.
sahilmgandhi	18:6a4db94011d3	8509	* \| \| \|0100 = ADCn_CH4.
sahilmgandhi	18:6a4db94011d3	8510	* \| \| \|0101 = ADCn_CH5.
sahilmgandhi	18:6a4db94011d3	8511	* \| \| \|0110 = ADCn_CH6.
sahilmgandhi	18:6a4db94011d3	8512	* \| \| \|0111 = ADCn_CH7.
sahilmgandhi	18:6a4db94011d3	8513	* \| \| \|For SAMPLE0
sahilmgandhi	18:6a4db94011d3	8514	* \| \| \|1000 = VBG.
sahilmgandhi	18:6a4db94011d3	8515	* \| \| \|1001 = VTEMP.
sahilmgandhi	18:6a4db94011d3	8516	* \| \| \|1010 = AVSS.
sahilmgandhi	18:6a4db94011d3	8517	* \| \| \|1011 = OP0.
sahilmgandhi	18:6a4db94011d3	8518	* \| \| \|For SAMPLE1
sahilmgandhi	18:6a4db94011d3	8519	* \| \| \|1000= OP1.
sahilmgandhi	18:6a4db94011d3	8520	* \|[4:7] \|TRGSEL \|A/D SAMPLE Start Of Conversion Trigger Source Selection
sahilmgandhi	18:6a4db94011d3	8521	* \| \| \|0000 = Disable hardware trigger.
sahilmgandhi	18:6a4db94011d3	8522	* \| \| \|0001 = External pin (STADC) trigger.
sahilmgandhi	18:6a4db94011d3	8523	* \| \| \|0010 = ADC ADINT0 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8524	* \| \| \|0011 = ADC ADINT1 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8525	* \| \| \|0100 = Timer0 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8526	* \| \| \|0101 = Timer1 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8527	* \| \| \|0110 = Timer2 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8528	* \| \| \|0111 = Timer3 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8529	* \| \| \|1000 = EPWM0_CH0 trigger.
sahilmgandhi	18:6a4db94011d3	8530	* \| \| \|1001 = EPWM0_CH2 trigger.
sahilmgandhi	18:6a4db94011d3	8531	* \| \| \|1010 = EPWM0_CH4 trigger.
sahilmgandhi	18:6a4db94011d3	8532	* \| \| \|1011 = EPWM1_CH0 trigger.
sahilmgandhi	18:6a4db94011d3	8533	* \| \| \|1100 = EPWM1_CH2 trigger.
sahilmgandhi	18:6a4db94011d3	8534	* \| \| \|1101 = EPWM1_CH4 trigger.
sahilmgandhi	18:6a4db94011d3	8535	* \| \| \|1110 = PWM0_CH0 trigger.
sahilmgandhi	18:6a4db94011d3	8536	* \| \| \|1111 = PWM0_CH1 trigger.
sahilmgandhi	18:6a4db94011d3	8537	* \|[8:15] \|TRGDLYCNT \|A/D SAMPLE Start Of Conversion Trigger Delay Time
sahilmgandhi	18:6a4db94011d3	8538	* \| \| \|Trigger delay time = (TRGDLYCNT + 4) x Trigger delay clock period.
sahilmgandhi	18:6a4db94011d3	8539	* \|[16:17] \|TRGDLYDIV \|A/D SAMPLE Start Of Conversion Trigger Delay Clock Divider Selection
sahilmgandhi	18:6a4db94011d3	8540	* \| \| \|Trigger delay clock frequency:
sahilmgandhi	18:6a4db94011d3	8541	* \| \| \|00 = ADC_CLK/1.
sahilmgandhi	18:6a4db94011d3	8542	* \| \| \|01 = ADC_CLK/2.
sahilmgandhi	18:6a4db94011d3	8543	* \| \| \|10 = ADC_CLK/4.
sahilmgandhi	18:6a4db94011d3	8544	* \| \| \|11 = ADC_CLK/16.
sahilmgandhi	18:6a4db94011d3	8545	* \|[20] \|EXTREN \|A/D External Pin Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8546	* \| \| \|0 = A/D external pin rising edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8547	* \| \| \|1 = A/D external pin rising edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8548	* \|[21] \|EXTFEN \|A/D External Pin Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8549	* \| \| \|0 = A/D external pin falling edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8550	* \| \| \|1 = A/D external pin falling edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8551	*/
sahilmgandhi	18:6a4db94011d3	8552	__IO uint32_t AD1SPCTL3;
sahilmgandhi	18:6a4db94011d3	8553
sahilmgandhi	18:6a4db94011d3	8554	/**
sahilmgandhi	18:6a4db94011d3	8555	* AD1SPCTL4
sahilmgandhi	18:6a4db94011d3	8556	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	8557	* Offset: 0x88 A/D SAMPLE14 Control Register
sahilmgandhi	18:6a4db94011d3	8558	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	8559	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	8560	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	8561	* \|[0:3] \|CHSEL \|A/D SAMPLE0,1 Channel Selection
sahilmgandhi	18:6a4db94011d3	8562	* \| \| \|0000 = ADCn_CH0.
sahilmgandhi	18:6a4db94011d3	8563	* \| \| \|0001 = ADCn_CH1.
sahilmgandhi	18:6a4db94011d3	8564	* \| \| \|0010 = ADCn_CH2.
sahilmgandhi	18:6a4db94011d3	8565	* \| \| \|0011 = ADCn_CH3.
sahilmgandhi	18:6a4db94011d3	8566	* \| \| \|0100 = ADCn_CH4.
sahilmgandhi	18:6a4db94011d3	8567	* \| \| \|0101 = ADCn_CH5.
sahilmgandhi	18:6a4db94011d3	8568	* \| \| \|0110 = ADCn_CH6.
sahilmgandhi	18:6a4db94011d3	8569	* \| \| \|0111 = ADCn_CH7.
sahilmgandhi	18:6a4db94011d3	8570	* \| \| \|For SAMPLE0
sahilmgandhi	18:6a4db94011d3	8571	* \| \| \|1000 = VBG.
sahilmgandhi	18:6a4db94011d3	8572	* \| \| \|1001 = VTEMP.
sahilmgandhi	18:6a4db94011d3	8573	* \| \| \|1010 = AVSS.
sahilmgandhi	18:6a4db94011d3	8574	* \| \| \|1011 = OP0.
sahilmgandhi	18:6a4db94011d3	8575	* \| \| \|For SAMPLE1
sahilmgandhi	18:6a4db94011d3	8576	* \| \| \|1000= OP1.
sahilmgandhi	18:6a4db94011d3	8577	* \|[4:6] \|TRGSEL \|A/D SAMPLE Start Of Conversion Trigger Source Selection
sahilmgandhi	18:6a4db94011d3	8578	* \| \| \|000 = Disable hardware trigger.
sahilmgandhi	18:6a4db94011d3	8579	* \| \| \|001 = External pin (STADC) trigger.
sahilmgandhi	18:6a4db94011d3	8580	* \| \| \|010 = ADC ADINT0 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8581	* \| \| \|011 = ADC ADINT1 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8582	* \| \| \|100 = Timer0 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8583	* \| \| \|101 = Timer1 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8584	* \| \| \|110 = Timer2 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8585	* \| \| \|111 = Timer3 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8586	* \|[20] \|EXTREN \|A/D External Pin Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8587	* \| \| \|0 = A/D external pin rising edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8588	* \| \| \|1 = A/D external pin rising edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8589	* \|[21] \|EXTFEN \|A/D External Pin Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8590	* \| \| \|0 = A/D external pin falling edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8591	* \| \| \|1 = A/D external pin falling edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8592	*/
sahilmgandhi	18:6a4db94011d3	8593	__IO uint32_t AD1SPCTL4;
sahilmgandhi	18:6a4db94011d3	8594
sahilmgandhi	18:6a4db94011d3	8595	/**
sahilmgandhi	18:6a4db94011d3	8596	* AD1SPCTL5
sahilmgandhi	18:6a4db94011d3	8597	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	8598	* Offset: 0x8C A/D SAMPLE15 Control Register
sahilmgandhi	18:6a4db94011d3	8599	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	8600	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	8601	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	8602	* \|[0:3] \|CHSEL \|A/D SAMPLE0,1 Channel Selection
sahilmgandhi	18:6a4db94011d3	8603	* \| \| \|0000 = ADCn_CH0.
sahilmgandhi	18:6a4db94011d3	8604	* \| \| \|0001 = ADCn_CH1.
sahilmgandhi	18:6a4db94011d3	8605	* \| \| \|0010 = ADCn_CH2.
sahilmgandhi	18:6a4db94011d3	8606	* \| \| \|0011 = ADCn_CH3.
sahilmgandhi	18:6a4db94011d3	8607	* \| \| \|0100 = ADCn_CH4.
sahilmgandhi	18:6a4db94011d3	8608	* \| \| \|0101 = ADCn_CH5.
sahilmgandhi	18:6a4db94011d3	8609	* \| \| \|0110 = ADCn_CH6.
sahilmgandhi	18:6a4db94011d3	8610	* \| \| \|0111 = ADCn_CH7.
sahilmgandhi	18:6a4db94011d3	8611	* \| \| \|For SAMPLE0
sahilmgandhi	18:6a4db94011d3	8612	* \| \| \|1000 = VBG.
sahilmgandhi	18:6a4db94011d3	8613	* \| \| \|1001 = VTEMP.
sahilmgandhi	18:6a4db94011d3	8614	* \| \| \|1010 = AVSS.
sahilmgandhi	18:6a4db94011d3	8615	* \| \| \|1011 = OP0.
sahilmgandhi	18:6a4db94011d3	8616	* \| \| \|For SAMPLE1
sahilmgandhi	18:6a4db94011d3	8617	* \| \| \|1000= OP1.
sahilmgandhi	18:6a4db94011d3	8618	* \|[4:6] \|TRGSEL \|A/D SAMPLE Start Of Conversion Trigger Source Selection
sahilmgandhi	18:6a4db94011d3	8619	* \| \| \|000 = Disable hardware trigger.
sahilmgandhi	18:6a4db94011d3	8620	* \| \| \|001 = External pin (STADC) trigger.
sahilmgandhi	18:6a4db94011d3	8621	* \| \| \|010 = ADC ADINT0 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8622	* \| \| \|011 = ADC ADINT1 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8623	* \| \| \|100 = Timer0 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8624	* \| \| \|101 = Timer1 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8625	* \| \| \|110 = Timer2 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8626	* \| \| \|111 = Timer3 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8627	* \|[20] \|EXTREN \|A/D External Pin Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8628	* \| \| \|0 = A/D external pin rising edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8629	* \| \| \|1 = A/D external pin rising edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8630	* \|[21] \|EXTFEN \|A/D External Pin Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8631	* \| \| \|0 = A/D external pin falling edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8632	* \| \| \|1 = A/D external pin falling edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8633	*/
sahilmgandhi	18:6a4db94011d3	8634	__IO uint32_t AD1SPCTL5;
sahilmgandhi	18:6a4db94011d3	8635
sahilmgandhi	18:6a4db94011d3	8636	/**
sahilmgandhi	18:6a4db94011d3	8637	* AD1SPCTL6
sahilmgandhi	18:6a4db94011d3	8638	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	8639	* Offset: 0x90 A/D SAMPLE16 Control Register
sahilmgandhi	18:6a4db94011d3	8640	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	8641	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	8642	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	8643	* \|[0:3] \|CHSEL \|A/D SAMPLE0,1 Channel Selection
sahilmgandhi	18:6a4db94011d3	8644	* \| \| \|0000 = ADCn_CH0.
sahilmgandhi	18:6a4db94011d3	8645	* \| \| \|0001 = ADCn_CH1.
sahilmgandhi	18:6a4db94011d3	8646	* \| \| \|0010 = ADCn_CH2.
sahilmgandhi	18:6a4db94011d3	8647	* \| \| \|0011 = ADCn_CH3.
sahilmgandhi	18:6a4db94011d3	8648	* \| \| \|0100 = ADCn_CH4.
sahilmgandhi	18:6a4db94011d3	8649	* \| \| \|0101 = ADCn_CH5.
sahilmgandhi	18:6a4db94011d3	8650	* \| \| \|0110 = ADCn_CH6.
sahilmgandhi	18:6a4db94011d3	8651	* \| \| \|0111 = ADCn_CH7.
sahilmgandhi	18:6a4db94011d3	8652	* \| \| \|For SAMPLE0
sahilmgandhi	18:6a4db94011d3	8653	* \| \| \|1000 = VBG.
sahilmgandhi	18:6a4db94011d3	8654	* \| \| \|1001 = VTEMP.
sahilmgandhi	18:6a4db94011d3	8655	* \| \| \|1010 = AVSS.
sahilmgandhi	18:6a4db94011d3	8656	* \| \| \|1011 = OP0.
sahilmgandhi	18:6a4db94011d3	8657	* \| \| \|For SAMPLE1
sahilmgandhi	18:6a4db94011d3	8658	* \| \| \|1000= OP1.
sahilmgandhi	18:6a4db94011d3	8659	* \|[4:6] \|TRGSEL \|A/D SAMPLE Start Of Conversion Trigger Source Selection
sahilmgandhi	18:6a4db94011d3	8660	* \| \| \|000 = Disable hardware trigger.
sahilmgandhi	18:6a4db94011d3	8661	* \| \| \|001 = External pin (STADC) trigger.
sahilmgandhi	18:6a4db94011d3	8662	* \| \| \|010 = ADC ADINT0 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8663	* \| \| \|011 = ADC ADINT1 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8664	* \| \| \|100 = Timer0 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8665	* \| \| \|101 = Timer1 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8666	* \| \| \|110 = Timer2 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8667	* \| \| \|111 = Timer3 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8668	* \|[20] \|EXTREN \|A/D External Pin Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8669	* \| \| \|0 = A/D external pin rising edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8670	* \| \| \|1 = A/D external pin rising edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8671	* \|[21] \|EXTFEN \|A/D External Pin Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8672	* \| \| \|0 = A/D external pin falling edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8673	* \| \| \|1 = A/D external pin falling edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8674	*/
sahilmgandhi	18:6a4db94011d3	8675	__IO uint32_t AD1SPCTL6;
sahilmgandhi	18:6a4db94011d3	8676
sahilmgandhi	18:6a4db94011d3	8677	/**
sahilmgandhi	18:6a4db94011d3	8678	* AD1SPCTL7
sahilmgandhi	18:6a4db94011d3	8679	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	8680	* Offset: 0x94 A/D SAMPLE17 Control Register
sahilmgandhi	18:6a4db94011d3	8681	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	8682	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	8683	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	8684	* \|[0:3] \|CHSEL \|A/D SAMPLE0,1 Channel Selection
sahilmgandhi	18:6a4db94011d3	8685	* \| \| \|0000 = ADCn_CH0.
sahilmgandhi	18:6a4db94011d3	8686	* \| \| \|0001 = ADCn_CH1.
sahilmgandhi	18:6a4db94011d3	8687	* \| \| \|0010 = ADCn_CH2.
sahilmgandhi	18:6a4db94011d3	8688	* \| \| \|0011 = ADCn_CH3.
sahilmgandhi	18:6a4db94011d3	8689	* \| \| \|0100 = ADCn_CH4.
sahilmgandhi	18:6a4db94011d3	8690	* \| \| \|0101 = ADCn_CH5.
sahilmgandhi	18:6a4db94011d3	8691	* \| \| \|0110 = ADCn_CH6.
sahilmgandhi	18:6a4db94011d3	8692	* \| \| \|0111 = ADCn_CH7.
sahilmgandhi	18:6a4db94011d3	8693	* \| \| \|For SAMPLE0
sahilmgandhi	18:6a4db94011d3	8694	* \| \| \|1000 = VBG.
sahilmgandhi	18:6a4db94011d3	8695	* \| \| \|1001 = VTEMP.
sahilmgandhi	18:6a4db94011d3	8696	* \| \| \|1010 = AVSS.
sahilmgandhi	18:6a4db94011d3	8697	* \| \| \|1011 = OP0.
sahilmgandhi	18:6a4db94011d3	8698	* \| \| \|For SAMPLE1
sahilmgandhi	18:6a4db94011d3	8699	* \| \| \|1000= OP1.
sahilmgandhi	18:6a4db94011d3	8700	* \|[4:6] \|TRGSEL \|A/D SAMPLE Start Of Conversion Trigger Source Selection
sahilmgandhi	18:6a4db94011d3	8701	* \| \| \|000 = Disable hardware trigger.
sahilmgandhi	18:6a4db94011d3	8702	* \| \| \|001 = External pin (STADC) trigger.
sahilmgandhi	18:6a4db94011d3	8703	* \| \| \|010 = ADC ADINT0 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8704	* \| \| \|011 = ADC ADINT1 interrupt EOC pulse trigger.
sahilmgandhi	18:6a4db94011d3	8705	* \| \| \|100 = Timer0 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8706	* \| \| \|101 = Timer1 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8707	* \| \| \|110 = Timer2 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8708	* \| \| \|111 = Timer3 overflow pulse trigger.
sahilmgandhi	18:6a4db94011d3	8709	* \|[20] \|EXTREN \|A/D External Pin Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8710	* \| \| \|0 = A/D external pin rising edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8711	* \| \| \|1 = A/D external pin rising edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8712	* \|[21] \|EXTFEN \|A/D External Pin Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	8713	* \| \| \|0 = A/D external pin falling edge trigger Disabled.
sahilmgandhi	18:6a4db94011d3	8714	* \| \| \|1 = A/D external pin falling edge trigger Enabled.
sahilmgandhi	18:6a4db94011d3	8715	*/
sahilmgandhi	18:6a4db94011d3	8716	__IO uint32_t AD1SPCTL7;
sahilmgandhi	18:6a4db94011d3	8717	uint32_t RESERVE1[3];
sahilmgandhi	18:6a4db94011d3	8718
sahilmgandhi	18:6a4db94011d3	8719
sahilmgandhi	18:6a4db94011d3	8720	/**
sahilmgandhi	18:6a4db94011d3	8721	* SIMUSEL
sahilmgandhi	18:6a4db94011d3	8722	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	8723	* Offset: 0xA4 A/D SAMPLE Simultaneous Sampling Mode Select Register
sahilmgandhi	18:6a4db94011d3	8724	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	8725	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	8726	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	8727	* \|[0] \|SIMUSEL0 \|A/D SAMPLE00, SAMPLE10 Simultaneous Sampling Mode Selection
sahilmgandhi	18:6a4db94011d3	8728	* \| \| \|0 = SAMPLE00, SAMPLE10 are in single sampling mode, both SAMPLE00 and SAMPLE10's 3 bits of CHSEL define the ADC channels to be converted.
sahilmgandhi	18:6a4db94011d3	8729	* \| \| \|1 = SAMPLE00, SAMPLE10 are in simultaneous sampling mode, Only SAMPLE00 can trigger the both ADC conversions of SAMPLE00 and SAMPLE10, SAMPLE10 trigger select TRGSEL is ignored.
sahilmgandhi	18:6a4db94011d3	8730	* \| \| \|If SAMPLE00's CHSEL = 1, and SAMPLE10's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal.
sahilmgandhi	18:6a4db94011d3	8731	* \|[1] \|SIMUSEL1 \|A/D SAMPLE01, SAMPLE11 Simultaneous Sampling Mode Selection
sahilmgandhi	18:6a4db94011d3	8732	* \| \| \|0 = SAMPLE01, SAMPLE11 are in single sampling mode, both SAMPLE01 and SAMPLE11's 3 bits of CHSEL define the ADC channels to be converted.
sahilmgandhi	18:6a4db94011d3	8733	* \| \| \|1 = SAMPLE01, SAMPLE11 are in simultaneous sampling mode, Only SAMPLE01 can trigger the both ADC conversions of SAMPLE01 and SAMPLE11, SAMPLE11 trigger select TRGSEL is ignored.
sahilmgandhi	18:6a4db94011d3	8734	* \| \| \|If SAMPLE01's CHSEL = 1, and SAMPLE11's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal.
sahilmgandhi	18:6a4db94011d3	8735	* \|[2] \|SIMUSEL2 \|A/D SAMPLE02, SAMPLE12 Simultaneous Sampling Mode Selection
sahilmgandhi	18:6a4db94011d3	8736	* \| \| \|0 = SAMPLE02, SAMPLE12 are in single sampling mode, both SAMPLE02 and SAMPLE12's 3 bits of CHSEL define the ADC channels to be converted.
sahilmgandhi	18:6a4db94011d3	8737	* \| \| \|1 = SAMPLE02, SAMPLE12 are in simultaneous sampling mode, Only SAMPLE02 can trigger the both ADC conversions of SAMPLE02 and SAMPLE12, SAMPLE12 trigger select TRGSEL is ignored.
sahilmgandhi	18:6a4db94011d3	8738	* \| \| \|If SAMPLE02's CHSEL = 1, and SAMPLE12's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal.
sahilmgandhi	18:6a4db94011d3	8739	* \|[3] \|SIMUSEL3 \|A/D SAMPLE03, SAMPLE13 Simultaneous Sampling Mode Selection
sahilmgandhi	18:6a4db94011d3	8740	* \| \| \|0 = SAMPLE03, SAMPLE13 are in single sampling mode, both SAMPLE03 and SAMPLE13's 3 bits of CHSEL define the ADC channels to be converted.
sahilmgandhi	18:6a4db94011d3	8741	* \| \| \|1 = SAMPLE03, SAMPLE13 are in simultaneous sampling mode, Only SAMPLE03 can trigger the both ADC conversions of SAMPLE03 and SAMPLE13, SAMPLE13 trigger select TRGSEL is ignored.
sahilmgandhi	18:6a4db94011d3	8742	* \| \| \|If SAMPLE03's CHSEL = 1, and SAMPLE13's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal.
sahilmgandhi	18:6a4db94011d3	8743	* \|[4] \|SIMUSEL4 \|A/D SAMPLE04, SAMPLE14 Simultaneous Sampling Mode Selection
sahilmgandhi	18:6a4db94011d3	8744	* \| \| \|0 = SAMPLE04, SAMPLE14 are in single sampling mode, both SAMPLE04 and SAMPLE14's 3 bits of CHSEL define the ADC channels to be converted.
sahilmgandhi	18:6a4db94011d3	8745	* \| \| \|1 = SAMPLE04, SAMPLE14 are in simultaneous sampling mode, Only SAMPLE04 can trigger the both ADC conversions of SAMPLE04 and SAMPLE14, SAMPLE14 trigger select TRGSEL is ignored.
sahilmgandhi	18:6a4db94011d3	8746	* \| \| \|If SAMPLE04's CHSEL = 1, and SAMPLE14's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal.
sahilmgandhi	18:6a4db94011d3	8747	* \|[5] \|SIMUSEL5 \|A/D SAMPLE05, SAMPLE15 Simultaneous Sampling Mode Selection
sahilmgandhi	18:6a4db94011d3	8748	* \| \| \|0 = SAMPLE05, SAMPLE15 are in single sampling mode, both SAMPLE05 and SAMPLE15's 3 bits of CHSEL define the ADC channels to be converted.
sahilmgandhi	18:6a4db94011d3	8749	* \| \| \|1 = SAMPLE05, SAMPLE15 are in simultaneous sampling mode, Only SAMPLE05 can trigger the both ADC conversions of SAMPLE05 and SAMPLE15, SAMPLE15 trigger select TRGSEL is ignored.
sahilmgandhi	18:6a4db94011d3	8750	* \| \| \|if SAMPLE05's CHSEL = 1, and SAMPLE15's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal.
sahilmgandhi	18:6a4db94011d3	8751	* \|[6] \|SIMUSEL6 \|A/D SAMPLE06, SAMPLE16 Simultaneous Sampling Mode Selection
sahilmgandhi	18:6a4db94011d3	8752	* \| \| \|0 = SAMPLE06, SAMPLE16 are in single sampling mode, both SAMPLE06 and SAMPLE16's 3 bits of CHSEL define the ADC channels to be converted.
sahilmgandhi	18:6a4db94011d3	8753	* \| \| \|1 = SAMPLE06, SAMPLE16 are in simultaneous sampling mode, Only SAMPLE06 can trigger the both ADC conversions of SAMPLE06 and SAMPLE16, SAMPLE16 trigger select TRGSEL is ignored.
sahilmgandhi	18:6a4db94011d3	8754	* \| \| \|If SAMPLE06's CHSEL = 1, and SAMPLE16's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal.
sahilmgandhi	18:6a4db94011d3	8755	* \|[7] \|SIMUSEL7 \|A/D SAMPLE07, SAMPLE17 Simultaneous Sampling Mode Selection
sahilmgandhi	18:6a4db94011d3	8756	* \| \| \|0 = SAMPLE07, SAMPLE17 are in single sampling mode, both SAMPLE07 and SAMPLE17's 3 bits of CHSEL define the ADC channels to be converted.
sahilmgandhi	18:6a4db94011d3	8757	* \| \| \|1 = SAMPLE07, SAMPLE17 are in simultaneous sampling mode, Only SAMPLE07 can trigger the both ADC conversions of SAMPLE07 and SAMPLE17, SAMPLE17 trigger select TRGSEL is ignored.
sahilmgandhi	18:6a4db94011d3	8758	* \| \| \|If SAMPLE07's CHSEL = 1, SAMPLE17's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal.
sahilmgandhi	18:6a4db94011d3	8759	*/
sahilmgandhi	18:6a4db94011d3	8760	__IO uint32_t SIMUSEL;
sahilmgandhi	18:6a4db94011d3	8761
sahilmgandhi	18:6a4db94011d3	8762	/**
sahilmgandhi	18:6a4db94011d3	8763	* CMP0/1
sahilmgandhi	18:6a4db94011d3	8764	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	8765	* Offset: 0xA8 A/D Result Compare Register 0
sahilmgandhi	18:6a4db94011d3	8766	* Offset: 0xAC A/D Result Compare Register 1
sahilmgandhi	18:6a4db94011d3	8767	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	8768	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	8769	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	8770	* \|[0] \|ADCMPEN \|A/D Result Compare Enable Control
sahilmgandhi	18:6a4db94011d3	8771	* \| \| \|0 = Compare Disabled.
sahilmgandhi	18:6a4db94011d3	8772	* \| \| \|1 = Compare Enabled.
sahilmgandhi	18:6a4db94011d3	8773	* \| \| \|Set this bit to 1 to enable compare CMPDAT (EADC_CMPx[27:16]) with specified SAMPLE conversion result when converted data is loaded into ADDR register.
sahilmgandhi	18:6a4db94011d3	8774	* \|[1] \|ADCMPIE \|A/D Result Compare Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	8775	* \| \| \|0 = Compare function interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	8776	* \| \| \|1 = Compare function interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	8777	* \| \| \|If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPx[2]) and CMPMCNT (EADC_CMPx[11:8]), ADCMPF (EADC_STATUS1 [7:6]) bit will be asserted, in the meanwhile, if ADCMPIE (EADC_CMPx[1]) is set to 1, a compare interrupt request is generated.
sahilmgandhi	18:6a4db94011d3	8778	* \|[2] \|CMPCOND \|Compare Condition
sahilmgandhi	18:6a4db94011d3	8779	* \| \| \|0= Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPDAT (EADC_CMPx[27:16]), the internal match counter will increase one.
sahilmgandhi	18:6a4db94011d3	8780	* \| \| \|1= Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPx[27:16]), the internal match counter will increase one.
sahilmgandhi	18:6a4db94011d3	8781	* \| \| \|Note: When the internal counter reaches the value to CMPMCNT (EADC_CMPx[11:8]) + 1, the CMPF bit will be set.
sahilmgandhi	18:6a4db94011d3	8782	* \|[3:5] \|CMPSPL \|Compare SAMPLE Selection
sahilmgandhi	18:6a4db94011d3	8783	* \| \| \|000 = SAMPLE00 conversion result EADC_AD0DAT0 is selected to be compared.
sahilmgandhi	18:6a4db94011d3	8784	* \| \| \|001 = SAMPLE01 conversion result EADC_AD0DAT1 is selected to be compared.
sahilmgandhi	18:6a4db94011d3	8785	* \| \| \|010 = SAMPLE02 conversion result EADC_AD0DAT2 is selected to be compared.
sahilmgandhi	18:6a4db94011d3	8786	* \| \| \|011 = SAMPLE03 conversion result EADC_AD0DAT3 is selected to be compared.
sahilmgandhi	18:6a4db94011d3	8787	* \| \| \|100 = SAMPLE10 conversion result EADC_AD1DAT0 is selected to be compared.
sahilmgandhi	18:6a4db94011d3	8788	* \| \| \|101 = SAMPLE11 conversion result EADC_AD1DAT1 is selected to be compared.
sahilmgandhi	18:6a4db94011d3	8789	* \| \| \|110 = SAMPLE12 conversion result EADC_AD1DAT2 is selected to be compared.
sahilmgandhi	18:6a4db94011d3	8790	* \| \| \|111 = SAMPLE13 conversion result EADC_AD1DAT3 is selected to be compared.
sahilmgandhi	18:6a4db94011d3	8791	* \|[8:11] \|CMPMCNT \|Compare Match Count
sahilmgandhi	18:6a4db94011d3	8792	* \| \| \|When the specified A/D SAMPLE analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPx[2]), the internal match counter will increase 1.
sahilmgandhi	18:6a4db94011d3	8793	* \| \| \|When the internal counter reaches the value to CMPMCNT (EADC_CMPx[11:8] + 1, the ADCMPF (EADC_STATUS1 [7:6]) bit will be set.
sahilmgandhi	18:6a4db94011d3	8794	* \|[16:27] \|CMPDAT \|Compared Data
sahilmgandhi	18:6a4db94011d3	8795	* \| \| \|The 12 bits data is used to compare with conversion result of specified SAMPLE.
sahilmgandhi	18:6a4db94011d3	8796	* \| \| \|Software can use it to monitor the external analog input pin voltage transition without imposing a load on software.
sahilmgandhi	18:6a4db94011d3	8797	*/
sahilmgandhi	18:6a4db94011d3	8798	__IO uint32_t CMP[2];
sahilmgandhi	18:6a4db94011d3	8799
sahilmgandhi	18:6a4db94011d3	8800	/**
sahilmgandhi	18:6a4db94011d3	8801	* STATUS0
sahilmgandhi	18:6a4db94011d3	8802	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	8803	* Offset: 0xB0 A/D Status Register 0
sahilmgandhi	18:6a4db94011d3	8804	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	8805	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	8806	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	8807	* \|[0:7] \|VALID7_0 \|ADDR07~ ADDR00 Data Valid Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	8808	* \| \| \|It is a mirror of VALID bit in SAMPLE0 A/D result data register EADC_AD0DAT0x.
sahilmgandhi	18:6a4db94011d3	8809	* \| \| \|Note: x = 0~7.
sahilmgandhi	18:6a4db94011d3	8810	* \|[8:15] \|VALID15_8 \|ADDR17~ ADDR10 Data Valid Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	8811	* \| \| \|It is a mirror of VALID bit in SAMPLE1 A/D result data register EADC_AD0DAT1x.
sahilmgandhi	18:6a4db94011d3	8812	* \| \| \|Note: x = 0~7.
sahilmgandhi	18:6a4db94011d3	8813	* \|[16:23] \|OV7_0 \|ADDR07~ ADDR00 Overrun Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	8814	* \| \| \|It is a mirror to OV bit in SAMPLE0 A/D result data register EADC_AD0DAT0x.
sahilmgandhi	18:6a4db94011d3	8815	* \| \| \|Note: x = 0~7.
sahilmgandhi	18:6a4db94011d3	8816	* \|[24:31] \|OV15_8 \|ADDR17~ADDR10 Overrun Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	8817	* \| \| \|It is a mirror to OV bit in SAMPLE1 A/D result data register EADC_AD0DAT1x.
sahilmgandhi	18:6a4db94011d3	8818	* \| \| \|Note: x = 0~7.
sahilmgandhi	18:6a4db94011d3	8819	*/
sahilmgandhi	18:6a4db94011d3	8820	__I uint32_t STATUS0;
sahilmgandhi	18:6a4db94011d3	8821
sahilmgandhi	18:6a4db94011d3	8822	/**
sahilmgandhi	18:6a4db94011d3	8823	* STATUS1
sahilmgandhi	18:6a4db94011d3	8824	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	8825	* Offset: 0xB4 A/D Status Register 1
sahilmgandhi	18:6a4db94011d3	8826	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	8827	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	8828	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	8829	* \|[0] \|ADIF0 \|A/D ADINT0 Interrupt Flag
sahilmgandhi	18:6a4db94011d3	8830	* \| \| \|0 = No ADINT0 interrupt pulse received.
sahilmgandhi	18:6a4db94011d3	8831	* \| \| \|1 = ADINT0 interrupt pulse has been received.
sahilmgandhi	18:6a4db94011d3	8832	* \| \| \|Note1: This bit is cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	8833	* \| \| \|Note2:This bit indicates whether an A/D conversion of specific SAMPLE has been completed
sahilmgandhi	18:6a4db94011d3	8834	* \|[1] \|ADIF1 \|A/D ADINT1 Interrupt Flag
sahilmgandhi	18:6a4db94011d3	8835	* \| \| \|0 = No ADINT1 interrupt pulse received.
sahilmgandhi	18:6a4db94011d3	8836	* \| \| \|1 = ADINT1 interrupt pulse has been received.
sahilmgandhi	18:6a4db94011d3	8837	* \| \| \|Note1: This bit is cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	8838	* \| \| \|Note2:This bit indicates whether an A/D conversion of specific SAMPLE has been completed
sahilmgandhi	18:6a4db94011d3	8839	* \|[2] \|ADIF2 \|A/D ADINT2 Interrupt Flag
sahilmgandhi	18:6a4db94011d3	8840	* \| \| \|0 = no ADINT2 interrupt pulse received.
sahilmgandhi	18:6a4db94011d3	8841	* \| \| \|1 = ADINT2 interrupt pulse has been received.
sahilmgandhi	18:6a4db94011d3	8842	* \| \| \|Note1: This bit is cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	8843	* \| \| \|Note2:This bit indicates whether an A/D conversion of specific SAMPLE has been completed
sahilmgandhi	18:6a4db94011d3	8844	* \|[3] \|ADIF3 \|A/D ADINT3 Interrupt Flag
sahilmgandhi	18:6a4db94011d3	8845	* \| \| \|0 = No ADINT3 interrupt pulse received.
sahilmgandhi	18:6a4db94011d3	8846	* \| \| \|1 = ADINT3 interrupt pulse has been received.
sahilmgandhi	18:6a4db94011d3	8847	* \| \| \|Note1: This bit is cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	8848	* \| \| \|Note2:This bit indicates whether an A/D conversion of specific SAMPLE has been completed
sahilmgandhi	18:6a4db94011d3	8849	* \|[4] \|ADCMPO0 \|ADC Compare 0 Output Status
sahilmgandhi	18:6a4db94011d3	8850	* \| \| \|The 12 bits compare0 data CMPDAT EADC_CMP0 [27:16]) is used to compare with conversion result of specified SAMPLE.
sahilmgandhi	18:6a4db94011d3	8851	* \| \| \|Software can use it to monitor the external analog input pin voltage status.
sahilmgandhi	18:6a4db94011d3	8852	* \| \| \|0 = Conversion result in ADDR less than CMPDAT (EADC_CMP0 [27:16]) setting.
sahilmgandhi	18:6a4db94011d3	8853	* \| \| \|1 = Conversion result in ADDR great than or equal CMPDAT (EADC_CMP0 [27:16]) setting.
sahilmgandhi	18:6a4db94011d3	8854	* \|[5] \|ADCMPO1 \|ADC Compare 1 Output Status
sahilmgandhi	18:6a4db94011d3	8855	* \| \| \|The 12 bits compare1 data CMPDAT (EADC_CMP1 [27:16]) is used to compare with conversion result of specified SAMPLE.
sahilmgandhi	18:6a4db94011d3	8856	* \| \| \|Software can use it to monitor the external analog input pin voltage status.
sahilmgandhi	18:6a4db94011d3	8857	* \| \| \|0 = Conversion result in ADDR less than CMPDAT EADC_CMP1 [27:16]) setting.
sahilmgandhi	18:6a4db94011d3	8858	* \| \| \|1 = Conversion result in ADDR great than or equal CMPDAT (EADC_CMP1 [27:16]) setting.
sahilmgandhi	18:6a4db94011d3	8859	* \|[6] \|ADCMPF0 \|ADC Compare 0 Flag
sahilmgandhi	18:6a4db94011d3	8860	* \| \| \|When the specific SAMPLE A/D conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.
sahilmgandhi	18:6a4db94011d3	8861	* \| \| \|0 = Conversion result in ADDR does not meet EADC_CMP0 setting.
sahilmgandhi	18:6a4db94011d3	8862	* \| \| \|1 = Conversion result in ADDR meets EADC_CMP0 setting.
sahilmgandhi	18:6a4db94011d3	8863	* \| \| \|Note: This bit is cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	8864	* \|[7] \|ADCMPF1 \|ADC Compare 1 Flag
sahilmgandhi	18:6a4db94011d3	8865	* \| \| \|When the specific SAMPLE A/D conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.
sahilmgandhi	18:6a4db94011d3	8866	* \| \| \|0 = Conversion result in ADDR does not meet EADC_CMP1 setting.
sahilmgandhi	18:6a4db94011d3	8867	* \| \| \|1 = Conversion result in ADDR meets EADC_CMP1 setting.
sahilmgandhi	18:6a4db94011d3	8868	* \| \| \|Note: This bit is cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	8869	* \|[8] \|BUSY0 \|Busy/Idle (Read Only)
sahilmgandhi	18:6a4db94011d3	8870	* \| \| \|0 = A/D converter 0 (ADC0) is in idle state.
sahilmgandhi	18:6a4db94011d3	8871	* \| \| \|1 = A/D converter 0 (ADC0) is doing conversion.
sahilmgandhi	18:6a4db94011d3	8872	* \|[12:15] \|CHANNEL0 \|Current Conversion Channel (Read Only)
sahilmgandhi	18:6a4db94011d3	8873	* \| \| \|This filed reflects ADC0 current conversion channel when BUSY0 (EADC_STATUS1 [8]) = 1.
sahilmgandhi	18:6a4db94011d3	8874	* \| \| \|When BUSY0 (EADC_STATUS1 [8]) = 0, it shows the last converted channel.
sahilmgandhi	18:6a4db94011d3	8875	* \| \| \|0000 = ADC0_CH0.
sahilmgandhi	18:6a4db94011d3	8876	* \| \| \|0001 = ADC0_CH1.
sahilmgandhi	18:6a4db94011d3	8877	* \| \| \|0010 = ADC0_CH2.
sahilmgandhi	18:6a4db94011d3	8878	* \| \| \|0011 = ADC0_CH3.
sahilmgandhi	18:6a4db94011d3	8879	* \| \| \|0100 = ADC0_CH4.
sahilmgandhi	18:6a4db94011d3	8880	* \| \| \|0100 = ADC0_CH5.
sahilmgandhi	18:6a4db94011d3	8881	* \| \| \|0110 = ADC0_CH6.
sahilmgandhi	18:6a4db94011d3	8882	* \| \| \|0111 = ADC0_CH7.
sahilmgandhi	18:6a4db94011d3	8883	* \| \| \|1000 = VBG.
sahilmgandhi	18:6a4db94011d3	8884	* \| \| \|1001 = VTEMP.
sahilmgandhi	18:6a4db94011d3	8885	* \| \| \|1010 = AVSS.
sahilmgandhi	18:6a4db94011d3	8886	* \| \| \|1011 = OPA0_O.
sahilmgandhi	18:6a4db94011d3	8887	* \| \| \|Other = reserved.
sahilmgandhi	18:6a4db94011d3	8888	* \|[16] \|BUSY1 \|Busy/Idle
sahilmgandhi	18:6a4db94011d3	8889	* \| \| \|0 = A/D converter 1 (ADC1) is in idle state.
sahilmgandhi	18:6a4db94011d3	8890	* \| \| \|1 = A/D converter 1 (ADC1) is doing conversion.
sahilmgandhi	18:6a4db94011d3	8891	* \|[20:23] \|CHANNEL1 \|Current Conversion Channel (Read Only)
sahilmgandhi	18:6a4db94011d3	8892	* \| \| \|This filed reflects ADC1 current conversion channel when BUSY1 (EADC_STATUS1 [16]) = 1.
sahilmgandhi	18:6a4db94011d3	8893	* \| \| \|When BUSY1 (EADC_STATUS1 [16]) = 0, it shows the last converted channel.
sahilmgandhi	18:6a4db94011d3	8894	* \| \| \|0000 = ADC1_CH0.
sahilmgandhi	18:6a4db94011d3	8895	* \| \| \|0001 = ADC1_CH1.
sahilmgandhi	18:6a4db94011d3	8896	* \| \| \|0010 = ADC1_CH2.
sahilmgandhi	18:6a4db94011d3	8897	* \| \| \|0011 = ADC1_CH3.
sahilmgandhi	18:6a4db94011d3	8898	* \| \| \|0100 = ADC1_CH4.
sahilmgandhi	18:6a4db94011d3	8899	* \| \| \|0101 = ADC1_CH5.
sahilmgandhi	18:6a4db94011d3	8900	* \| \| \|0110 = ADC1_CH6.
sahilmgandhi	18:6a4db94011d3	8901	* \| \| \|0111 = ADC1_CH7.
sahilmgandhi	18:6a4db94011d3	8902	* \| \| \|1000 = OPA1_O.
sahilmgandhi	18:6a4db94011d3	8903	* \| \| \|Other = reversed.
sahilmgandhi	18:6a4db94011d3	8904	* \|[24] \|ADOVIF \|All A/D Interrupt Flag Overrun Bits Check
sahilmgandhi	18:6a4db94011d3	8905	* \| \| \|0 = None of ADINT interrupt flag ADFOVx (ADIFOVR [15:0]) is overwritten to 1.
sahilmgandhi	18:6a4db94011d3	8906	* \| \| \|1 = Any one of ADINT interrupt flag ADFOVx (ADIFOVR [15:0]) is overwritten to 1.
sahilmgandhi	18:6a4db94011d3	8907	* \| \| \|Note: This bit will keep 1 when any ADFOVx (ADIFOVR [15:0]) Flag is equal to 1.
sahilmgandhi	18:6a4db94011d3	8908	* \|[25] \|STOVF \|For All A/D SAMPLE Start Of Conversion Overrun Flags Check
sahilmgandhi	18:6a4db94011d3	8909	* \| \| \|0 = None of SAMPLE event overrun flag SPOVFx (ADSPOVFR [15:0]) is set to 1.
sahilmgandhi	18:6a4db94011d3	8910	* \| \| \|1 = Any one of SAMPLE event overrun flag SPOVFx (ADSPOVFR [15:0]) is set to 1.
sahilmgandhi	18:6a4db94011d3	8911	* \| \| \|Note: This bit will keep 1 when any SPOVFx (ADSPOVFR [15:0]) Flag is equal to 1.
sahilmgandhi	18:6a4db94011d3	8912	* \|[26] \|AVALID \|For All SAMPLE A/D Result Data Register ADDR Data Valid Flag Check
sahilmgandhi	18:6a4db94011d3	8913	* \| \| \|0 = None of SAMPLE data register valid flag VALIDx (EADC_ADnDATx[17]) is set to 1.
sahilmgandhi	18:6a4db94011d3	8914	* \| \| \|1 = Any one of SAMPLE data register valid flag VALIDx (EADC_ADnDATx[17]) is set to 1.
sahilmgandhi	18:6a4db94011d3	8915	* \| \| \|Note: This bit will keep 1 when any VALIDx (EADC_ADnDATx[17]) Flag is equal to 1.
sahilmgandhi	18:6a4db94011d3	8916	* \|[27] \|AOV \|For All SAMPLE A/D Result Data Register Overrun Flags Check
sahilmgandhi	18:6a4db94011d3	8917	* \| \| \|0 = None of SAMPLE data register overrun flag OVx (EADC_ADnDATx[16]) is set to 1.
sahilmgandhi	18:6a4db94011d3	8918	* \| \| \|1 = Any one of SAMPLE data register overrun flag OVx (EADC_ADnDATx[16]) is set to 1.
sahilmgandhi	18:6a4db94011d3	8919	* \| \| \|Note: This bit will keep 1 when any OVx (EADC_ADnDATx[16]) Flag is equal to 1.
sahilmgandhi	18:6a4db94011d3	8920	*/
sahilmgandhi	18:6a4db94011d3	8921	__IO uint32_t STATUS1;
sahilmgandhi	18:6a4db94011d3	8922
sahilmgandhi	18:6a4db94011d3	8923	/**
sahilmgandhi	18:6a4db94011d3	8924	* EXTSMPT
sahilmgandhi	18:6a4db94011d3	8925	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	8926	* Offset: 0xB8 A/D Timing Control Register
sahilmgandhi	18:6a4db94011d3	8927	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	8928	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	8929	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	8930	* \|[0:7] \|EXTSMPT0 \|ADC0 Extend Sampling Time
sahilmgandhi	18:6a4db94011d3	8931	* \| \| \|When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.
sahilmgandhi	18:6a4db94011d3	8932	* \| \| \|The range of start delay time is from 0~255 ADC clock.
sahilmgandhi	18:6a4db94011d3	8933	* \|[16:23] \|EXTSMPT1 \|ADC1 Extend Sampling Time
sahilmgandhi	18:6a4db94011d3	8934	* \| \| \|When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.
sahilmgandhi	18:6a4db94011d3	8935	* \| \| \|The range of start delay time is from 0~255 ADC clock.
sahilmgandhi	18:6a4db94011d3	8936	*/
sahilmgandhi	18:6a4db94011d3	8937	__IO uint32_t EXTSMPT;
sahilmgandhi	18:6a4db94011d3	8938	uint32_t RESERVE2[17];
sahilmgandhi	18:6a4db94011d3	8939
sahilmgandhi	18:6a4db94011d3	8940
sahilmgandhi	18:6a4db94011d3	8941	/**
sahilmgandhi	18:6a4db94011d3	8942	* AD0DDAT0
sahilmgandhi	18:6a4db94011d3	8943	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	8944	* Offset: 0x100 A/D double Data Register 0 for SAMPLE00
sahilmgandhi	18:6a4db94011d3	8945	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	8946	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	8947	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	8948	* \|[0:11] \|RESULT \|A/D Conversion Result
sahilmgandhi	18:6a4db94011d3	8949	* \| \| \|This field contains 12 bits conversion result.
sahilmgandhi	18:6a4db94011d3	8950	* \|[16] \|VALID \|Valid Flag
sahilmgandhi	18:6a4db94011d3	8951	* \| \| \|0 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is not valid.
sahilmgandhi	18:6a4db94011d3	8952	* \| \| \|1 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is valid.
sahilmgandhi	18:6a4db94011d3	8953	* \| \| \|This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	8954	*/
sahilmgandhi	18:6a4db94011d3	8955	__I uint32_t AD0DDAT0;
sahilmgandhi	18:6a4db94011d3	8956
sahilmgandhi	18:6a4db94011d3	8957	/**
sahilmgandhi	18:6a4db94011d3	8958	* AD0DDAT1
sahilmgandhi	18:6a4db94011d3	8959	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	8960	* Offset: 0x104 A/D double Data Register 1 for SAMPLE01
sahilmgandhi	18:6a4db94011d3	8961	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	8962	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	8963	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	8964	* \|[0:11] \|RESULT \|A/D Conversion Result
sahilmgandhi	18:6a4db94011d3	8965	* \| \| \|This field contains 12 bits conversion result.
sahilmgandhi	18:6a4db94011d3	8966	* \|[16] \|VALID \|Valid Flag
sahilmgandhi	18:6a4db94011d3	8967	* \| \| \|0 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is not valid.
sahilmgandhi	18:6a4db94011d3	8968	* \| \| \|1 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is valid.
sahilmgandhi	18:6a4db94011d3	8969	* \| \| \|This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	8970	*/
sahilmgandhi	18:6a4db94011d3	8971	__I uint32_t AD0DDAT1;
sahilmgandhi	18:6a4db94011d3	8972
sahilmgandhi	18:6a4db94011d3	8973	/**
sahilmgandhi	18:6a4db94011d3	8974	* AD0DDAT2
sahilmgandhi	18:6a4db94011d3	8975	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	8976	* Offset: 0x108 A/D double Data Register 2 for SAMPLE02
sahilmgandhi	18:6a4db94011d3	8977	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	8978	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	8979	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	8980	* \|[0:11] \|RESULT \|A/D Conversion Result
sahilmgandhi	18:6a4db94011d3	8981	* \| \| \|This field contains 12 bits conversion result.
sahilmgandhi	18:6a4db94011d3	8982	* \|[16] \|VALID \|Valid Flag
sahilmgandhi	18:6a4db94011d3	8983	* \| \| \|0 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is not valid.
sahilmgandhi	18:6a4db94011d3	8984	* \| \| \|1 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is valid.
sahilmgandhi	18:6a4db94011d3	8985	* \| \| \|This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	8986	*/
sahilmgandhi	18:6a4db94011d3	8987	__I uint32_t AD0DDAT2;
sahilmgandhi	18:6a4db94011d3	8988
sahilmgandhi	18:6a4db94011d3	8989	/**
sahilmgandhi	18:6a4db94011d3	8990	* AD0DDAT3
sahilmgandhi	18:6a4db94011d3	8991	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	8992	* Offset: 0x10C A/D double Data Register 3 for SAMPLE03
sahilmgandhi	18:6a4db94011d3	8993	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	8994	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	8995	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	8996	* \|[0:11] \|RESULT \|A/D Conversion Result
sahilmgandhi	18:6a4db94011d3	8997	* \| \| \|This field contains 12 bits conversion result.
sahilmgandhi	18:6a4db94011d3	8998	* \|[16] \|VALID \|Valid Flag
sahilmgandhi	18:6a4db94011d3	8999	* \| \| \|0 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is not valid.
sahilmgandhi	18:6a4db94011d3	9000	* \| \| \|1 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is valid.
sahilmgandhi	18:6a4db94011d3	9001	* \| \| \|This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	9002	*/
sahilmgandhi	18:6a4db94011d3	9003	__I uint32_t AD0DDAT3;
sahilmgandhi	18:6a4db94011d3	9004	uint32_t RESERVE3[4];
sahilmgandhi	18:6a4db94011d3	9005
sahilmgandhi	18:6a4db94011d3	9006
sahilmgandhi	18:6a4db94011d3	9007	/**
sahilmgandhi	18:6a4db94011d3	9008	* AD1DDAT0
sahilmgandhi	18:6a4db94011d3	9009	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	9010	* Offset: 0x120 A/D double Data Register 0 for SAMPLE10
sahilmgandhi	18:6a4db94011d3	9011	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	9012	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	9013	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	9014	* \|[0:11] \|RESULT \|A/D Conversion Result
sahilmgandhi	18:6a4db94011d3	9015	* \| \| \|This field contains 12 bits conversion result.
sahilmgandhi	18:6a4db94011d3	9016	* \|[16] \|VALID \|Valid Flag
sahilmgandhi	18:6a4db94011d3	9017	* \| \| \|0 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is not valid.
sahilmgandhi	18:6a4db94011d3	9018	* \| \| \|1 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is valid.
sahilmgandhi	18:6a4db94011d3	9019	* \| \| \|This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	9020	*/
sahilmgandhi	18:6a4db94011d3	9021	__I uint32_t AD1DDAT0;
sahilmgandhi	18:6a4db94011d3	9022
sahilmgandhi	18:6a4db94011d3	9023	/**
sahilmgandhi	18:6a4db94011d3	9024	* AD1DDAT1
sahilmgandhi	18:6a4db94011d3	9025	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	9026	* Offset: 0x124 A/D double Data Register 1 for SAMPLE11
sahilmgandhi	18:6a4db94011d3	9027	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	9028	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	9029	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	9030	* \|[0:11] \|RESULT \|A/D Conversion Result
sahilmgandhi	18:6a4db94011d3	9031	* \| \| \|This field contains 12 bits conversion result.
sahilmgandhi	18:6a4db94011d3	9032	* \|[16] \|VALID \|Valid Flag
sahilmgandhi	18:6a4db94011d3	9033	* \| \| \|0 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is not valid.
sahilmgandhi	18:6a4db94011d3	9034	* \| \| \|1 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is valid.
sahilmgandhi	18:6a4db94011d3	9035	* \| \| \|This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	9036	*/
sahilmgandhi	18:6a4db94011d3	9037	__I uint32_t AD1DDAT1;
sahilmgandhi	18:6a4db94011d3	9038
sahilmgandhi	18:6a4db94011d3	9039	/**
sahilmgandhi	18:6a4db94011d3	9040	* AD1DDAT2
sahilmgandhi	18:6a4db94011d3	9041	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	9042	* Offset: 0x128 A/D double Data Register 2 for SAMPLE12
sahilmgandhi	18:6a4db94011d3	9043	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	9044	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	9045	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	9046	* \|[0:11] \|RESULT \|A/D Conversion Result
sahilmgandhi	18:6a4db94011d3	9047	* \| \| \|This field contains 12 bits conversion result.
sahilmgandhi	18:6a4db94011d3	9048	* \|[16] \|VALID \|Valid Flag
sahilmgandhi	18:6a4db94011d3	9049	* \| \| \|0 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is not valid.
sahilmgandhi	18:6a4db94011d3	9050	* \| \| \|1 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is valid.
sahilmgandhi	18:6a4db94011d3	9051	* \| \| \|This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	9052	*/
sahilmgandhi	18:6a4db94011d3	9053	__I uint32_t AD1DDAT2;
sahilmgandhi	18:6a4db94011d3	9054
sahilmgandhi	18:6a4db94011d3	9055	/**
sahilmgandhi	18:6a4db94011d3	9056	* AD1DDAT3
sahilmgandhi	18:6a4db94011d3	9057	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	9058	* Offset: 0x12C A/D double Data Register 3 for SAMPLE13
sahilmgandhi	18:6a4db94011d3	9059	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	9060	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	9061	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	9062	* \|[0:11] \|RESULT \|A/D Conversion Result
sahilmgandhi	18:6a4db94011d3	9063	* \| \| \|This field contains 12 bits conversion result.
sahilmgandhi	18:6a4db94011d3	9064	* \|[16] \|VALID \|Valid Flag
sahilmgandhi	18:6a4db94011d3	9065	* \| \| \|0 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is not valid.
sahilmgandhi	18:6a4db94011d3	9066	* \| \| \|1 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is valid.
sahilmgandhi	18:6a4db94011d3	9067	* \| \| \|This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
sahilmgandhi	18:6a4db94011d3	9068	*/
sahilmgandhi	18:6a4db94011d3	9069	__I uint32_t AD1DDAT3;
sahilmgandhi	18:6a4db94011d3	9070
sahilmgandhi	18:6a4db94011d3	9071	/**
sahilmgandhi	18:6a4db94011d3	9072	* DBMEN
sahilmgandhi	18:6a4db94011d3	9073	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	9074	* Offset: 0x130 A/D Double Buffer Mode select
sahilmgandhi	18:6a4db94011d3	9075	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	9076	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	9077	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	9078	* \|[0] \|AD0DBM0 \|Double Buffer Mode For SAMPLE00
sahilmgandhi	18:6a4db94011d3	9079	* \| \| \|0 = SAMPLE00 has one sample result register. (default).
sahilmgandhi	18:6a4db94011d3	9080	* \| \| \|1 =SAMPLE00 has two sample result registers.
sahilmgandhi	18:6a4db94011d3	9081	* \|[1] \|AD0DBM1 \|Double Buffer Mode For SAMPLE01
sahilmgandhi	18:6a4db94011d3	9082	* \| \| \|0 = SAMPLE01 has one sample result register. (default).
sahilmgandhi	18:6a4db94011d3	9083	* \| \| \|1 = SAMPLE01 has two sample result registers.
sahilmgandhi	18:6a4db94011d3	9084	* \|[2] \|AD0DBM2 \|Double Buffer Mode For SAMPLE02
sahilmgandhi	18:6a4db94011d3	9085	* \| \| \|0 = SAMPLE02 has one sample result register. (default).
sahilmgandhi	18:6a4db94011d3	9086	* \| \| \|1 =SAMPLE02 has two sample result registers.
sahilmgandhi	18:6a4db94011d3	9087	* \|[3] \|AD0DBM3 \|Double Buffer Mode For SAMPLE03
sahilmgandhi	18:6a4db94011d3	9088	* \| \| \|0 = SAMPLE03 has one sample result register. (default).
sahilmgandhi	18:6a4db94011d3	9089	* \| \| \|1 =SAMPLE03 has two sample result registers.
sahilmgandhi	18:6a4db94011d3	9090	* \|[8] \|AD1DBM0 \|Double Buffer Mode For SAMPLE10
sahilmgandhi	18:6a4db94011d3	9091	* \| \| \|0 = SAMPLE10 has one sample result register. (default)
sahilmgandhi	18:6a4db94011d3	9092	* \| \| \|1 =SAMPLE10 has two sample result registers.
sahilmgandhi	18:6a4db94011d3	9093	* \|[9] \|AD1DBM1 \|Double Buffer Mode For SAMPLE11
sahilmgandhi	18:6a4db94011d3	9094	* \| \| \|0 = SAMPLE11 has one sample result register. (default).
sahilmgandhi	18:6a4db94011d3	9095	* \| \| \|1 =SAMPLE11 has two sample result registers.
sahilmgandhi	18:6a4db94011d3	9096	* \|[10] \|AD1DBM2 \|Double Buffer Mode For SAMPLE12
sahilmgandhi	18:6a4db94011d3	9097	* \| \| \|0 = SAMPLE12 has one sample result register. (default).
sahilmgandhi	18:6a4db94011d3	9098	* \| \| \|1 =SAMPLE12 has two sample result registers.
sahilmgandhi	18:6a4db94011d3	9099	* \|[11] \|AD1DBM3 \|Double Buffer Mode For SAMPLE13
sahilmgandhi	18:6a4db94011d3	9100	* \| \| \|0 = SAMPLE13 has one sample result register. (default)
sahilmgandhi	18:6a4db94011d3	9101	* \| \| \|1 =SAMPLE13 has two sample result registers.
sahilmgandhi	18:6a4db94011d3	9102	*/
sahilmgandhi	18:6a4db94011d3	9103	__IO uint32_t DBMEN;
sahilmgandhi	18:6a4db94011d3	9104
sahilmgandhi	18:6a4db94011d3	9105	/**
sahilmgandhi	18:6a4db94011d3	9106	* INTSRC0
sahilmgandhi	18:6a4db94011d3	9107	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	9108	* Offset: 0x134 A/D Interrupt 0 Source Enable Control Register
sahilmgandhi	18:6a4db94011d3	9109	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	9110	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	9111	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	9112	* \|[0] \|AD0SPIE0 \|SAMPLE00 Interrupt Mask Enable Control
sahilmgandhi	18:6a4db94011d3	9113	* \| \| \|0 = SAMPLE00 interrupt mask Disabled.
sahilmgandhi	18:6a4db94011d3	9114	* \| \| \|1 = SAMPLE00 interrupt mask Enabled.
sahilmgandhi	18:6a4db94011d3	9115	* \|[1] \|AD0SPIE1 \|SAMPLE01 Interrupt Mask Enable Control
sahilmgandhi	18:6a4db94011d3	9116	* \| \| \|0 = SAMPLE01 interrupt mask Disabled.
sahilmgandhi	18:6a4db94011d3	9117	* \| \| \|1 = SAMPLE01 interrupt mask Enabled.
sahilmgandhi	18:6a4db94011d3	9118	* \|[2] \|AD0SPIE2 \|SAMPLE02 Interrupt Mask Enable Control
sahilmgandhi	18:6a4db94011d3	9119	* \| \| \|0 = SAMPLE02 interrupt mask Disabled.
sahilmgandhi	18:6a4db94011d3	9120	* \| \| \|1 = SAMPLE02 interrupt mask Enabled.
sahilmgandhi	18:6a4db94011d3	9121	* \|[3] \|AD0SPIE3 \|SAMPLE03 Interrupt Mask Enable Control
sahilmgandhi	18:6a4db94011d3	9122	* \| \| \|0 = SAMPLE03 interrupt mask Disabled.
sahilmgandhi	18:6a4db94011d3	9123	* \| \| \|1 = SAMPLE03 interrupt mask Enabled.
sahilmgandhi	18:6a4db94011d3	9124	* \|[4] \|AD0SPIE4 \|SAMPLE04 Interrupt Mask Enable Control
sahilmgandhi	18:6a4db94011d3	9125	* \| \| \|0 = SAMPLE04 interrupt mask Disabled.
sahilmgandhi	18:6a4db94011d3	9126	* \| \| \|1 = SAMPLE04 interrupt mask Enabled.
sahilmgandhi	18:6a4db94011d3	9127	* \|[5] \|AD0SPIE5 \|SAMPLE05 Interrupt Mask Enable Control
sahilmgandhi	18:6a4db94011d3	9128	* \| \| \|0 = SAMPLE05 interrupt mask Disabled.
sahilmgandhi	18:6a4db94011d3	9129	* \| \| \|1 = SAMPLE05 interrupt mask Enabled.
sahilmgandhi	18:6a4db94011d3	9130	* \|[6] \|AD0SPIE6 \|SAMPLE06 Interrupt Mask Enable Control
sahilmgandhi	18:6a4db94011d3	9131	* \| \| \|0 = SAMPLE06 interrupt mask Disabled.
sahilmgandhi	18:6a4db94011d3	9132	* \| \| \|1 = SAMPLE06 interrupt mask Enabled.
sahilmgandhi	18:6a4db94011d3	9133	* \|[7] \|AD0SPIE7 \|SAMPLE07 Interrupt Mask Enable Control
sahilmgandhi	18:6a4db94011d3	9134	* \| \| \|0 = SAMPLE07 interrupt mask Disabled.
sahilmgandhi	18:6a4db94011d3	9135	* \| \| \|1 = SAMPLE07 interrupt mask Enabled.
sahilmgandhi	18:6a4db94011d3	9136	* \|[8] \|AD1SPIE0 \|SAMPLE10 Interrupt Mask Enable Control
sahilmgandhi	18:6a4db94011d3	9137	* \| \| \|0 = SAMPLE10 interrupt mask Disabled.
sahilmgandhi	18:6a4db94011d3	9138	* \| \| \|1 = SAMPLE10 interrupt mask Enabled.
sahilmgandhi	18:6a4db94011d3	9139	* \|[9] \|AD1SPIE1 \|SAMPLE11 Interrupt Mask Enable Control
sahilmgandhi	18:6a4db94011d3	9140	* \| \| \|0 = SAMPLE11 interrupt mask Disabled.
sahilmgandhi	18:6a4db94011d3	9141	* \| \| \|1 = SAMPLE11 interrupt mask Enabled.
sahilmgandhi	18:6a4db94011d3	9142	* \|[10] \|AD1SPIE2 \|SAMPLE12 Interrupt Mask Enable Control
sahilmgandhi	18:6a4db94011d3	9143	* \| \| \|0 = SAMPLE12 interrupt mask Disabled.
sahilmgandhi	18:6a4db94011d3	9144	* \| \| \|1 = SAMPLE12 interrupt mask Enabled.
sahilmgandhi	18:6a4db94011d3	9145	* \|[11] \|AD1SPIE3 \|SAMPLE13 Interrupt Mask Enable Control
sahilmgandhi	18:6a4db94011d3	9146	* \| \| \|0 = SAMPLE13 interrupt mask Disabled.
sahilmgandhi	18:6a4db94011d3	9147	* \| \| \|1 = SAMPLE13 interrupt mask Enabled.
sahilmgandhi	18:6a4db94011d3	9148	* \|[12] \|AD1SPIE4 \|SAMPLE14 Interrupt Mask Enable Control
sahilmgandhi	18:6a4db94011d3	9149	* \| \| \|0 = SAMPLE14 interrupt mask Disabled.
sahilmgandhi	18:6a4db94011d3	9150	* \| \| \|1 = SAMPLE14 interrupt mask Enabled.
sahilmgandhi	18:6a4db94011d3	9151	* \|[13] \|AD1SPIE5 \|SAMPLE15 Interrupt Mask Enable Control
sahilmgandhi	18:6a4db94011d3	9152	* \| \| \|0 = SAMPLE15 interrupt mask Disabled.
sahilmgandhi	18:6a4db94011d3	9153	* \| \| \|1 = SAMPLE15 interrupt mask Enabled.
sahilmgandhi	18:6a4db94011d3	9154	* \|[14] \|AD1SPIE6 \|SAMPLE16 Interrupt Mask Enable Control
sahilmgandhi	18:6a4db94011d3	9155	* \| \| \|0 = SAMPLE16 interrupt mask Disabled.
sahilmgandhi	18:6a4db94011d3	9156	* \| \| \|1 = SAMPLE16 interrupt mask Enabled.
sahilmgandhi	18:6a4db94011d3	9157	* \|[15] \|AD1SPIE7 \|SAMPLE17 Interrupt Mask Enable Control
sahilmgandhi	18:6a4db94011d3	9158	* \| \| \|0 = SAMPLE17 interrupt mask Disabled.
sahilmgandhi	18:6a4db94011d3	9159	* \| \| \|1 = SAMPLE17 interrupt mask Enabled.
sahilmgandhi	18:6a4db94011d3	9160	*/
sahilmgandhi	18:6a4db94011d3	9161	__IO uint32_t INTSRC[4];
sahilmgandhi	18:6a4db94011d3	9162
sahilmgandhi	18:6a4db94011d3	9163	/**
sahilmgandhi	18:6a4db94011d3	9164	* AD0TRGEN0
sahilmgandhi	18:6a4db94011d3	9165	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	9166	* Offset: 0x144 A/D trigger condition for SAMPLE00
sahilmgandhi	18:6a4db94011d3	9167	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	9168	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	9169	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	9170	* \|[0] \|EPWM00REN \|EPWM0_CH0 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9171	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9172	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9173	* \|[1] \|EPWM00FEN \|EPWM0_CH0 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9174	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9175	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9176	* \|[2] \|EPWM00PEN \|EPWM0_CH0 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9177	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9178	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9179	* \|[3] \|EPWM00CEN \|EPWM0_CH0 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9180	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9181	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9182	* \|[4] \|EPWM02REN \|EPWM0_CH2 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9183	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9184	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9185	* \|[5] \|EPWM02FEN \|EPWM0_CH2 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9186	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9187	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9188	* \|[6] \|EPWM02PEN \|EPWM0_CH2 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9189	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9190	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9191	* \|[7] \|EPWM02CEN \|EPWM0_CH2 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9192	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9193	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9194	* \|[8] \|EPWM04REN \|EPWM0_CH4 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9195	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9196	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9197	* \|[9] \|EPWM04FEN \|EPWM0_CH4 Falling Rdge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9198	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9199	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9200	* \|[10] \|EPWM04PEN \|EPWM0_CH4 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9201	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9202	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9203	* \|[11] \|EPWM04CEN \|EPWM0_CH4 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9204	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9205	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9206	* \|[12] \|EPWM10REN \|EPWM1_CH0 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9207	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9208	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9209	* \|[13] \|EPWM10FEN \|EPWM1_CH0 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9210	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9211	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9212	* \|[14] \|EPWM10PEN \|EPWM1_CH0 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9213	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9214	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9215	* \|[15] \|EPWM10CEN \|EPWM1_CH0 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9216	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9217	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9218	* \|[16] \|EPWM12REN \|EPWM1_CH2 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9219	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9220	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9221	* \|[17] \|EPWM120FEN\|EPWM1_CH2 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9222	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9223	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9224	* \|[18] \|EPWM12PEN \|EPWM1_CH2 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9225	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9226	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9227	* \|[19] \|EPWM12CEN \|EPWM1_CH2 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9228	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9229	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9230	* \|[20] \|EPWM14REN \|EPWM1_CH4 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9231	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9232	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9233	* \|[21] \|EPWM14FEN \|EPWM1_CH4 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9234	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9235	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9236	* \|[22] \|EPWM14PEN \|EPWM1_CH4 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9237	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9238	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9239	* \|[23] \|EPWM14CEN \|EPWM1_CH4 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9240	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9241	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9242	* \|[24] \|PWM00REN \|PWM0_CH0 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9243	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9244	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9245	* \|[25] \|PWM00FEN \|PWM0_CH0 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9246	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9247	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9248	* \|[26] \|PWM00PEN \|PWM0_CH0 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9249	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9250	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9251	* \|[27] \|PWM00CEN \|PWM0_CH0 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9252	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9253	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9254	* \|[28] \|PWM01REN \|PWM0_CH1 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9255	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9256	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9257	* \|[29] \|PWM01FEN \|PWM0_CH1 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9258	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9259	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9260	* \|[30] \|PWM01PEN \|PWM0_CH1 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9261	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9262	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9263	* \|[31] \|PWM01CEN \|PWM0_CH1 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9264	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9265	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9266	*/
sahilmgandhi	18:6a4db94011d3	9267	__IO uint32_t AD0TRGEN0;
sahilmgandhi	18:6a4db94011d3	9268
sahilmgandhi	18:6a4db94011d3	9269	/**
sahilmgandhi	18:6a4db94011d3	9270	* AD0TRGEN1
sahilmgandhi	18:6a4db94011d3	9271	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	9272	* Offset: 0x148 A/D trigger condition for SAMPLE01
sahilmgandhi	18:6a4db94011d3	9273	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	9274	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	9275	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	9276	* \|[0] \|EPWM00REN \|EPWM0_CH0 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9277	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9278	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9279	* \|[1] \|EPWM00FEN \|EPWM0_CH0 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9280	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9281	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9282	* \|[2] \|EPWM00PEN \|EPWM0_CH0 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9283	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9284	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9285	* \|[3] \|EPWM00CEN \|EPWM0_CH0 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9286	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9287	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9288	* \|[4] \|EPWM02REN \|EPWM0_CH2 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9289	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9290	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9291	* \|[5] \|EPWM02FEN \|EPWM0_CH2 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9292	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9293	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9294	* \|[6] \|EPWM02PEN \|EPWM0_CH2 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9295	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9296	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9297	* \|[7] \|EPWM02CEN \|EPWM0_CH2 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9298	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9299	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9300	* \|[8] \|EPWM04REN \|EPWM0_CH4 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9301	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9302	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9303	* \|[9] \|EPWM04FEN \|EPWM0_CH4 Falling Rdge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9304	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9305	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9306	* \|[10] \|EPWM04PEN \|EPWM0_CH4 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9307	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9308	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9309	* \|[11] \|EPWM04CEN \|EPWM0_CH4 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9310	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9311	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9312	* \|[12] \|EPWM10REN \|EPWM1_CH0 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9313	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9314	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9315	* \|[13] \|EPWM10FEN \|EPWM1_CH0 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9316	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9317	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9318	* \|[14] \|EPWM10PEN \|EPWM1_CH0 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9319	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9320	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9321	* \|[15] \|EPWM10CEN \|EPWM1_CH0 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9322	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9323	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9324	* \|[16] \|EPWM12REN \|EPWM1_CH2 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9325	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9326	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9327	* \|[17] \|EPWM120FEN\|EPWM1_CH2 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9328	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9329	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9330	* \|[18] \|EPWM12PEN \|EPWM1_CH2 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9331	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9332	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9333	* \|[19] \|EPWM12CEN \|EPWM1_CH2 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9334	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9335	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9336	* \|[20] \|EPWM14REN \|EPWM1_CH4 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9337	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9338	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9339	* \|[21] \|EPWM14FEN \|EPWM1_CH4 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9340	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9341	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9342	* \|[22] \|EPWM14PEN \|EPWM1_CH4 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9343	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9344	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9345	* \|[23] \|EPWM14CEN \|EPWM1_CH4 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9346	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9347	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9348	* \|[24] \|PWM00REN \|PWM0_CH0 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9349	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9350	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9351	* \|[25] \|PWM00FEN \|PWM0_CH0 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9352	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9353	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9354	* \|[26] \|PWM00PEN \|PWM0_CH0 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9355	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9356	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9357	* \|[27] \|PWM00CEN \|PWM0_CH0 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9358	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9359	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9360	* \|[28] \|PWM01REN \|PWM0_CH1 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9361	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9362	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9363	* \|[29] \|PWM01FEN \|PWM0_CH1 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9364	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9365	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9366	* \|[30] \|PWM01PEN \|PWM0_CH1 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9367	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9368	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9369	* \|[31] \|PWM01CEN \|PWM0_CH1 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9370	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9371	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9372	*/
sahilmgandhi	18:6a4db94011d3	9373	__IO uint32_t AD0TRGEN1;
sahilmgandhi	18:6a4db94011d3	9374
sahilmgandhi	18:6a4db94011d3	9375	/**
sahilmgandhi	18:6a4db94011d3	9376	* AD0TRGEN2
sahilmgandhi	18:6a4db94011d3	9377	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	9378	* Offset: 0x14C A/D trigger condition for SAMPLE02
sahilmgandhi	18:6a4db94011d3	9379	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	9380	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	9381	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	9382	* \|[0] \|EPWM00REN \|EPWM0_CH0 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9383	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9384	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9385	* \|[1] \|EPWM00FEN \|EPWM0_CH0 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9386	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9387	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9388	* \|[2] \|EPWM00PEN \|EPWM0_CH0 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9389	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9390	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9391	* \|[3] \|EPWM00CEN \|EPWM0_CH0 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9392	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9393	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9394	* \|[4] \|EPWM02REN \|EPWM0_CH2 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9395	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9396	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9397	* \|[5] \|EPWM02FEN \|EPWM0_CH2 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9398	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9399	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9400	* \|[6] \|EPWM02PEN \|EPWM0_CH2 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9401	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9402	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9403	* \|[7] \|EPWM02CEN \|EPWM0_CH2 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9404	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9405	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9406	* \|[8] \|EPWM04REN \|EPWM0_CH4 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9407	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9408	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9409	* \|[9] \|EPWM04FEN \|EPWM0_CH4 Falling Rdge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9410	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9411	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9412	* \|[10] \|EPWM04PEN \|EPWM0_CH4 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9413	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9414	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9415	* \|[11] \|EPWM04CEN \|EPWM0_CH4 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9416	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9417	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9418	* \|[12] \|EPWM10REN \|EPWM1_CH0 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9419	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9420	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9421	* \|[13] \|EPWM10FEN \|EPWM1_CH0 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9422	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9423	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9424	* \|[14] \|EPWM10PEN \|EPWM1_CH0 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9425	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9426	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9427	* \|[15] \|EPWM10CEN \|EPWM1_CH0 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9428	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9429	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9430	* \|[16] \|EPWM12REN \|EPWM1_CH2 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9431	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9432	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9433	* \|[17] \|EPWM120FEN\|EPWM1_CH2 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9434	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9435	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9436	* \|[18] \|EPWM12PEN \|EPWM1_CH2 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9437	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9438	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9439	* \|[19] \|EPWM12CEN \|EPWM1_CH2 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9440	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9441	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9442	* \|[20] \|EPWM14REN \|EPWM1_CH4 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9443	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9444	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9445	* \|[21] \|EPWM14FEN \|EPWM1_CH4 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9446	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9447	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9448	* \|[22] \|EPWM14PEN \|EPWM1_CH4 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9449	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9450	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9451	* \|[23] \|EPWM14CEN \|EPWM1_CH4 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9452	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9453	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9454	* \|[24] \|PWM00REN \|PWM0_CH0 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9455	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9456	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9457	* \|[25] \|PWM00FEN \|PWM0_CH0 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9458	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9459	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9460	* \|[26] \|PWM00PEN \|PWM0_CH0 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9461	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9462	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9463	* \|[27] \|PWM00CEN \|PWM0_CH0 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9464	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9465	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9466	* \|[28] \|PWM01REN \|PWM0_CH1 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9467	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9468	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9469	* \|[29] \|PWM01FEN \|PWM0_CH1 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9470	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9471	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9472	* \|[30] \|PWM01PEN \|PWM0_CH1 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9473	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9474	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9475	* \|[31] \|PWM01CEN \|PWM0_CH1 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9476	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9477	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9478	*/
sahilmgandhi	18:6a4db94011d3	9479	__IO uint32_t AD0TRGEN2;
sahilmgandhi	18:6a4db94011d3	9480
sahilmgandhi	18:6a4db94011d3	9481	/**
sahilmgandhi	18:6a4db94011d3	9482	* AD0TRGEN3
sahilmgandhi	18:6a4db94011d3	9483	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	9484	* Offset: 0x150 A/D trigger condition for SAMPLE03
sahilmgandhi	18:6a4db94011d3	9485	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	9486	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	9487	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	9488	* \|[0] \|EPWM00REN \|EPWM0_CH0 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9489	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9490	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9491	* \|[1] \|EPWM00FEN \|EPWM0_CH0 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9492	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9493	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9494	* \|[2] \|EPWM00PEN \|EPWM0_CH0 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9495	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9496	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9497	* \|[3] \|EPWM00CEN \|EPWM0_CH0 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9498	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9499	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9500	* \|[4] \|EPWM02REN \|EPWM0_CH2 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9501	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9502	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9503	* \|[5] \|EPWM02FEN \|EPWM0_CH2 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9504	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9505	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9506	* \|[6] \|EPWM02PEN \|EPWM0_CH2 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9507	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9508	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9509	* \|[7] \|EPWM02CEN \|EPWM0_CH2 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9510	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9511	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9512	* \|[8] \|EPWM04REN \|EPWM0_CH4 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9513	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9514	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9515	* \|[9] \|EPWM04FEN \|EPWM0_CH4 Falling Rdge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9516	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9517	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9518	* \|[10] \|EPWM04PEN \|EPWM0_CH4 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9519	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9520	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9521	* \|[11] \|EPWM04CEN \|EPWM0_CH4 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9522	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9523	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9524	* \|[12] \|EPWM10REN \|EPWM1_CH0 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9525	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9526	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9527	* \|[13] \|EPWM10FEN \|EPWM1_CH0 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9528	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9529	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9530	* \|[14] \|EPWM10PEN \|EPWM1_CH0 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9531	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9532	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9533	* \|[15] \|EPWM10CEN \|EPWM1_CH0 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9534	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9535	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9536	* \|[16] \|EPWM12REN \|EPWM1_CH2 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9537	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9538	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9539	* \|[17] \|EPWM120FEN\|EPWM1_CH2 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9540	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9541	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9542	* \|[18] \|EPWM12PEN \|EPWM1_CH2 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9543	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9544	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9545	* \|[19] \|EPWM12CEN \|EPWM1_CH2 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9546	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9547	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9548	* \|[20] \|EPWM14REN \|EPWM1_CH4 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9549	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9550	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9551	* \|[21] \|EPWM14FEN \|EPWM1_CH4 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9552	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9553	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9554	* \|[22] \|EPWM14PEN \|EPWM1_CH4 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9555	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9556	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9557	* \|[23] \|EPWM14CEN \|EPWM1_CH4 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9558	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9559	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9560	* \|[24] \|PWM00REN \|PWM0_CH0 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9561	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9562	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9563	* \|[25] \|PWM00FEN \|PWM0_CH0 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9564	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9565	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9566	* \|[26] \|PWM00PEN \|PWM0_CH0 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9567	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9568	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9569	* \|[27] \|PWM00CEN \|PWM0_CH0 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9570	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9571	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9572	* \|[28] \|PWM01REN \|PWM0_CH1 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9573	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9574	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9575	* \|[29] \|PWM01FEN \|PWM0_CH1 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9576	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9577	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9578	* \|[30] \|PWM01PEN \|PWM0_CH1 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9579	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9580	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9581	* \|[31] \|PWM01CEN \|PWM0_CH1 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9582	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9583	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9584	*/
sahilmgandhi	18:6a4db94011d3	9585	__IO uint32_t AD0TRGEN3;
sahilmgandhi	18:6a4db94011d3	9586
sahilmgandhi	18:6a4db94011d3	9587	/**
sahilmgandhi	18:6a4db94011d3	9588	* AD1TRGEN0
sahilmgandhi	18:6a4db94011d3	9589	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	9590	* Offset: 0x154 A/D trigger condition for SAMPLE10
sahilmgandhi	18:6a4db94011d3	9591	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	9592	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	9593	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	9594	* \|[0] \|EPWM00REN \|EPWM0_CH0 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9595	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9596	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9597	* \|[1] \|EPWM00FEN \|EPWM0_CH0 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9598	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9599	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9600	* \|[2] \|EPWM00PEN \|EPWM0_CH0 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9601	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9602	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9603	* \|[3] \|EPWM00CEN \|EPWM0_CH0 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9604	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9605	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9606	* \|[4] \|EPWM02REN \|EPWM0_CH2 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9607	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9608	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9609	* \|[5] \|EPWM02FEN \|EPWM0_CH2 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9610	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9611	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9612	* \|[6] \|EPWM02PEN \|EPWM0_CH2 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9613	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9614	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9615	* \|[7] \|EPWM02CEN \|EPWM0_CH2 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9616	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9617	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9618	* \|[8] \|EPWM04REN \|EPWM0_CH4 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9619	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9620	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9621	* \|[9] \|EPWM04FEN \|EPWM0_CH4 Falling Rdge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9622	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9623	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9624	* \|[10] \|EPWM04PEN \|EPWM0_CH4 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9625	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9626	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9627	* \|[11] \|EPWM04CEN \|EPWM0_CH4 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9628	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9629	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9630	* \|[12] \|EPWM10REN \|EPWM1_CH0 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9631	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9632	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9633	* \|[13] \|EPWM10FEN \|EPWM1_CH0 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9634	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9635	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9636	* \|[14] \|EPWM10PEN \|EPWM1_CH0 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9637	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9638	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9639	* \|[15] \|EPWM10CEN \|EPWM1_CH0 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9640	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9641	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9642	* \|[16] \|EPWM12REN \|EPWM1_CH2 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9643	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9644	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9645	* \|[17] \|EPWM120FEN\|EPWM1_CH2 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9646	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9647	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9648	* \|[18] \|EPWM12PEN \|EPWM1_CH2 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9649	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9650	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9651	* \|[19] \|EPWM12CEN \|EPWM1_CH2 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9652	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9653	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9654	* \|[20] \|EPWM14REN \|EPWM1_CH4 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9655	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9656	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9657	* \|[21] \|EPWM14FEN \|EPWM1_CH4 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9658	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9659	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9660	* \|[22] \|EPWM14PEN \|EPWM1_CH4 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9661	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9662	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9663	* \|[23] \|EPWM14CEN \|EPWM1_CH4 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9664	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9665	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9666	* \|[24] \|PWM00REN \|PWM0_CH0 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9667	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9668	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9669	* \|[25] \|PWM00FEN \|PWM0_CH0 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9670	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9671	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9672	* \|[26] \|PWM00PEN \|PWM0_CH0 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9673	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9674	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9675	* \|[27] \|PWM00CEN \|PWM0_CH0 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9676	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9677	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9678	* \|[28] \|PWM01REN \|PWM0_CH1 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9679	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9680	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9681	* \|[29] \|PWM01FEN \|PWM0_CH1 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9682	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9683	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9684	* \|[30] \|PWM01PEN \|PWM0_CH1 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9685	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9686	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9687	* \|[31] \|PWM01CEN \|PWM0_CH1 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9688	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9689	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9690	*/
sahilmgandhi	18:6a4db94011d3	9691	__IO uint32_t AD1TRGEN0;
sahilmgandhi	18:6a4db94011d3	9692
sahilmgandhi	18:6a4db94011d3	9693	/**
sahilmgandhi	18:6a4db94011d3	9694	* AD1TRGEN1
sahilmgandhi	18:6a4db94011d3	9695	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	9696	* Offset: 0x158 A/D trigger condition for SAMPLE11
sahilmgandhi	18:6a4db94011d3	9697	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	9698	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	9699	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	9700	* \|[0] \|EPWM00REN \|EPWM0_CH0 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9701	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9702	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9703	* \|[1] \|EPWM00FEN \|EPWM0_CH0 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9704	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9705	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9706	* \|[2] \|EPWM00PEN \|EPWM0_CH0 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9707	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9708	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9709	* \|[3] \|EPWM00CEN \|EPWM0_CH0 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9710	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9711	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9712	* \|[4] \|EPWM02REN \|EPWM0_CH2 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9713	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9714	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9715	* \|[5] \|EPWM02FEN \|EPWM0_CH2 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9716	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9717	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9718	* \|[6] \|EPWM02PEN \|EPWM0_CH2 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9719	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9720	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9721	* \|[7] \|EPWM02CEN \|EPWM0_CH2 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9722	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9723	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9724	* \|[8] \|EPWM04REN \|EPWM0_CH4 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9725	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9726	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9727	* \|[9] \|EPWM04FEN \|EPWM0_CH4 Falling Rdge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9728	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9729	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9730	* \|[10] \|EPWM04PEN \|EPWM0_CH4 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9731	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9732	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9733	* \|[11] \|EPWM04CEN \|EPWM0_CH4 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9734	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9735	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9736	* \|[12] \|EPWM10REN \|EPWM1_CH0 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9737	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9738	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9739	* \|[13] \|EPWM10FEN \|EPWM1_CH0 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9740	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9741	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9742	* \|[14] \|EPWM10PEN \|EPWM1_CH0 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9743	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9744	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9745	* \|[15] \|EPWM10CEN \|EPWM1_CH0 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9746	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9747	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9748	* \|[16] \|EPWM12REN \|EPWM1_CH2 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9749	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9750	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9751	* \|[17] \|EPWM120FEN\|EPWM1_CH2 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9752	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9753	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9754	* \|[18] \|EPWM12PEN \|EPWM1_CH2 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9755	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9756	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9757	* \|[19] \|EPWM12CEN \|EPWM1_CH2 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9758	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9759	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9760	* \|[20] \|EPWM14REN \|EPWM1_CH4 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9761	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9762	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9763	* \|[21] \|EPWM14FEN \|EPWM1_CH4 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9764	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9765	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9766	* \|[22] \|EPWM14PEN \|EPWM1_CH4 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9767	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9768	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9769	* \|[23] \|EPWM14CEN \|EPWM1_CH4 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9770	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9771	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9772	* \|[24] \|PWM00REN \|PWM0_CH0 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9773	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9774	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9775	* \|[25] \|PWM00FEN \|PWM0_CH0 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9776	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9777	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9778	* \|[26] \|PWM00PEN \|PWM0_CH0 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9779	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9780	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9781	* \|[27] \|PWM00CEN \|PWM0_CH0 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9782	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9783	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9784	* \|[28] \|PWM01REN \|PWM0_CH1 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9785	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9786	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9787	* \|[29] \|PWM01FEN \|PWM0_CH1 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9788	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9789	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9790	* \|[30] \|PWM01PEN \|PWM0_CH1 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9791	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9792	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9793	* \|[31] \|PWM01CEN \|PWM0_CH1 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9794	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9795	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9796	*/
sahilmgandhi	18:6a4db94011d3	9797	__IO uint32_t AD1TRGEN1;
sahilmgandhi	18:6a4db94011d3	9798
sahilmgandhi	18:6a4db94011d3	9799	/**
sahilmgandhi	18:6a4db94011d3	9800	* AD1TRGEN2
sahilmgandhi	18:6a4db94011d3	9801	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	9802	* Offset: 0x15C A/D trigger condition for SAMPLE12
sahilmgandhi	18:6a4db94011d3	9803	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	9804	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	9805	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	9806	* \|[0] \|EPWM00REN \|EPWM0_CH0 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9807	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9808	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9809	* \|[1] \|EPWM00FEN \|EPWM0_CH0 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9810	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9811	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9812	* \|[2] \|EPWM00PEN \|EPWM0_CH0 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9813	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9814	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9815	* \|[3] \|EPWM00CEN \|EPWM0_CH0 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9816	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9817	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9818	* \|[4] \|EPWM02REN \|EPWM0_CH2 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9819	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9820	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9821	* \|[5] \|EPWM02FEN \|EPWM0_CH2 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9822	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9823	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9824	* \|[6] \|EPWM02PEN \|EPWM0_CH2 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9825	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9826	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9827	* \|[7] \|EPWM02CEN \|EPWM0_CH2 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9828	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9829	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9830	* \|[8] \|EPWM04REN \|EPWM0_CH4 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9831	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9832	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9833	* \|[9] \|EPWM04FEN \|EPWM0_CH4 Falling Rdge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9834	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9835	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9836	* \|[10] \|EPWM04PEN \|EPWM0_CH4 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9837	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9838	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9839	* \|[11] \|EPWM04CEN \|EPWM0_CH4 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9840	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9841	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9842	* \|[12] \|EPWM10REN \|EPWM1_CH0 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9843	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9844	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9845	* \|[13] \|EPWM10FEN \|EPWM1_CH0 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9846	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9847	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9848	* \|[14] \|EPWM10PEN \|EPWM1_CH0 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9849	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9850	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9851	* \|[15] \|EPWM10CEN \|EPWM1_CH0 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9852	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9853	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9854	* \|[16] \|EPWM12REN \|EPWM1_CH2 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9855	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9856	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9857	* \|[17] \|EPWM120FEN\|EPWM1_CH2 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9858	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9859	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9860	* \|[18] \|EPWM12PEN \|EPWM1_CH2 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9861	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9862	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9863	* \|[19] \|EPWM12CEN \|EPWM1_CH2 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9864	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9865	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9866	* \|[20] \|EPWM14REN \|EPWM1_CH4 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9867	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9868	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9869	* \|[21] \|EPWM14FEN \|EPWM1_CH4 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9870	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9871	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9872	* \|[22] \|EPWM14PEN \|EPWM1_CH4 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9873	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9874	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9875	* \|[23] \|EPWM14CEN \|EPWM1_CH4 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9876	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9877	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9878	* \|[24] \|PWM00REN \|PWM0_CH0 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9879	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9880	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9881	* \|[25] \|PWM00FEN \|PWM0_CH0 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9882	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9883	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9884	* \|[26] \|PWM00PEN \|PWM0_CH0 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9885	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9886	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9887	* \|[27] \|PWM00CEN \|PWM0_CH0 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9888	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9889	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9890	* \|[28] \|PWM01REN \|PWM0_CH1 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9891	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9892	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9893	* \|[29] \|PWM01FEN \|PWM0_CH1 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9894	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9895	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9896	* \|[30] \|PWM01PEN \|PWM0_CH1 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9897	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9898	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9899	* \|[31] \|PWM01CEN \|PWM0_CH1 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9900	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9901	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9902	*/
sahilmgandhi	18:6a4db94011d3	9903	__IO uint32_t AD1TRGEN2;
sahilmgandhi	18:6a4db94011d3	9904
sahilmgandhi	18:6a4db94011d3	9905	/**
sahilmgandhi	18:6a4db94011d3	9906	* AD1TRGEN3
sahilmgandhi	18:6a4db94011d3	9907	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	9908	* Offset: 0x160 A/D trigger condition for SAMPLE13
sahilmgandhi	18:6a4db94011d3	9909	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	9910	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	9911	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	9912	* \|[0] \|EPWM00REN \|EPWM0_CH0 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9913	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9914	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9915	* \|[1] \|EPWM00FEN \|EPWM0_CH0 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9916	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9917	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9918	* \|[2] \|EPWM00PEN \|EPWM0_CH0 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9919	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9920	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9921	* \|[3] \|EPWM00CEN \|EPWM0_CH0 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9922	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9923	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9924	* \|[4] \|EPWM02REN \|EPWM0_CH2 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9925	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9926	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9927	* \|[5] \|EPWM02FEN \|EPWM0_CH2 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9928	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9929	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9930	* \|[6] \|EPWM02PEN \|EPWM0_CH2 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9931	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9932	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9933	* \|[7] \|EPWM02CEN \|EPWM0_CH2 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9934	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9935	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9936	* \|[8] \|EPWM04REN \|EPWM0_CH4 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9937	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9938	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9939	* \|[9] \|EPWM04FEN \|EPWM0_CH4 Falling Rdge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9940	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9941	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9942	* \|[10] \|EPWM04PEN \|EPWM0_CH4 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9943	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9944	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9945	* \|[11] \|EPWM04CEN \|EPWM0_CH4 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9946	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9947	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9948	* \|[12] \|EPWM10REN \|EPWM1_CH0 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9949	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9950	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9951	* \|[13] \|EPWM10FEN \|EPWM1_CH0 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9952	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9953	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9954	* \|[14] \|EPWM10PEN \|EPWM1_CH0 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9955	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9956	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9957	* \|[15] \|EPWM10CEN \|EPWM1_CH0 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9958	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9959	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9960	* \|[16] \|EPWM12REN \|EPWM1_CH2 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9961	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9962	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9963	* \|[17] \|EPWM120FEN\|EPWM1_CH2 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9964	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9965	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9966	* \|[18] \|EPWM12PEN \|EPWM1_CH2 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9967	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9968	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9969	* \|[19] \|EPWM12CEN \|EPWM1_CH2 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9970	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9971	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9972	* \|[20] \|EPWM14REN \|EPWM1_CH4 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9973	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9974	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9975	* \|[21] \|EPWM14FEN \|EPWM1_CH4 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9976	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9977	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9978	* \|[22] \|EPWM14PEN \|EPWM1_CH4 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9979	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9980	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9981	* \|[23] \|EPWM14CEN \|EPWM1_CH4 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9982	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9983	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9984	* \|[24] \|PWM00REN \|PWM0_CH0 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9985	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9986	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9987	* \|[25] \|PWM00FEN \|PWM0_CH0 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9988	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9989	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9990	* \|[26] \|PWM00PEN \|PWM0_CH0 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9991	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9992	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9993	* \|[27] \|PWM00CEN \|PWM0_CH0 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9994	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9995	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9996	* \|[28] \|PWM01REN \|PWM0_CH1 Rising Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	9997	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	9998	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	9999	* \|[29] \|PWM01FEN \|PWM0_CH1 Falling Edge Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	10000	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	10001	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	10002	* \|[30] \|PWM01PEN \|PWM0_CH1 Period Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	10003	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	10004	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	10005	* \|[31] \|PWM01CEN \|PWM0_CH1 Center Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	10006	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	10007	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	10008	*/
sahilmgandhi	18:6a4db94011d3	10009	__IO uint32_t AD1TRGEN3;
sahilmgandhi	18:6a4db94011d3	10010
sahilmgandhi	18:6a4db94011d3	10011	} EADC_T;
sahilmgandhi	18:6a4db94011d3	10012
sahilmgandhi	18:6a4db94011d3	10013	/**
sahilmgandhi	18:6a4db94011d3	10014	@addtogroup EADC_CONST EADC Bit Field Definition
sahilmgandhi	18:6a4db94011d3	10015	Constant Definitions for EADC Controller
sahilmgandhi	18:6a4db94011d3	10016	@{ */
sahilmgandhi	18:6a4db94011d3	10017
sahilmgandhi	18:6a4db94011d3	10018	#define EADC_AD0DAT0_RESULT_Pos (0) /!< EADC AD0DAT0: RESULT Position /
sahilmgandhi	18:6a4db94011d3	10019	#define EADC_AD0DAT0_RESULT_Msk (0xffful << EADC_AD0DAT0_RESULT_Pos) /!< EADC AD0DAT0: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	10020
sahilmgandhi	18:6a4db94011d3	10021	#define EADC_AD0DAT0_OV_Pos (16) /!< EADC AD0DAT0: OV Position /
sahilmgandhi	18:6a4db94011d3	10022	#define EADC_AD0DAT0_OV_Msk (0x1ul << EADC_AD0DAT0_OV_Pos) /!< EADC AD0DAT0: OV Mask /
sahilmgandhi	18:6a4db94011d3	10023
sahilmgandhi	18:6a4db94011d3	10024	#define EADC_AD0DAT0_VALID_Pos (17) /!< EADC AD0DAT0: VALID Position /
sahilmgandhi	18:6a4db94011d3	10025	#define EADC_AD0DAT0_VALID_Msk (0x1ul << EADC_AD0DAT0_VALID_Pos) /!< EADC AD0DAT0: VALID Mask /
sahilmgandhi	18:6a4db94011d3	10026
sahilmgandhi	18:6a4db94011d3	10027	#define EADC_AD0DAT1_RESULT_Pos (0) /!< EADC AD0DAT1: RESULT Position /
sahilmgandhi	18:6a4db94011d3	10028	#define EADC_AD0DAT1_RESULT_Msk (0xffful << EADC_AD0DAT1_RESULT_Pos) /!< EADC AD0DAT1: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	10029
sahilmgandhi	18:6a4db94011d3	10030	#define EADC_AD0DAT1_OV_Pos (16) /!< EADC AD0DAT1: OV Position /
sahilmgandhi	18:6a4db94011d3	10031	#define EADC_AD0DAT1_OV_Msk (0x1ul << EADC_AD0DAT1_OV_Pos) /!< EADC AD0DAT1: OV Mask /
sahilmgandhi	18:6a4db94011d3	10032
sahilmgandhi	18:6a4db94011d3	10033	#define EADC_AD0DAT1_VALID_Pos (17) /!< EADC AD0DAT1: VALID Position /
sahilmgandhi	18:6a4db94011d3	10034	#define EADC_AD0DAT1_VALID_Msk (0x1ul << EADC_AD0DAT1_VALID_Pos) /!< EADC AD0DAT1: VALID Mask /
sahilmgandhi	18:6a4db94011d3	10035
sahilmgandhi	18:6a4db94011d3	10036	#define EADC_AD0DAT2_RESULT_Pos (0) /!< EADC AD0DAT2: RESULT Position /
sahilmgandhi	18:6a4db94011d3	10037	#define EADC_AD0DAT2_RESULT_Msk (0xffful << EADC_AD0DAT2_RESULT_Pos) /!< EADC AD0DAT2: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	10038
sahilmgandhi	18:6a4db94011d3	10039	#define EADC_AD0DAT2_OV_Pos (16) /!< EADC AD0DAT2: OV Position /
sahilmgandhi	18:6a4db94011d3	10040	#define EADC_AD0DAT2_OV_Msk (0x1ul << EADC_AD0DAT2_OV_Pos) /!< EADC AD0DAT2: OV Mask /
sahilmgandhi	18:6a4db94011d3	10041
sahilmgandhi	18:6a4db94011d3	10042	#define EADC_AD0DAT2_VALID_Pos (17) /!< EADC AD0DAT2: VALID Position /
sahilmgandhi	18:6a4db94011d3	10043	#define EADC_AD0DAT2_VALID_Msk (0x1ul << EADC_AD0DAT2_VALID_Pos) /!< EADC AD0DAT2: VALID Mask /
sahilmgandhi	18:6a4db94011d3	10044
sahilmgandhi	18:6a4db94011d3	10045	#define EADC_AD0DAT3_RESULT_Pos (0) /!< EADC AD0DAT3: RESULT Position /
sahilmgandhi	18:6a4db94011d3	10046	#define EADC_AD0DAT3_RESULT_Msk (0xffful << EADC_AD0DAT3_RESULT_Pos) /!< EADC AD0DAT3: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	10047
sahilmgandhi	18:6a4db94011d3	10048	#define EADC_AD0DAT3_OV_Pos (16) /!< EADC AD0DAT3: OV Position /
sahilmgandhi	18:6a4db94011d3	10049	#define EADC_AD0DAT3_OV_Msk (0x1ul << EADC_AD0DAT3_OV_Pos) /!< EADC AD0DAT3: OV Mask /
sahilmgandhi	18:6a4db94011d3	10050
sahilmgandhi	18:6a4db94011d3	10051	#define EADC_AD0DAT3_VALID_Pos (17) /!< EADC AD0DAT3: VALID Position /
sahilmgandhi	18:6a4db94011d3	10052	#define EADC_AD0DAT3_VALID_Msk (0x1ul << EADC_AD0DAT3_VALID_Pos) /!< EADC AD0DAT3: VALID Mask /
sahilmgandhi	18:6a4db94011d3	10053
sahilmgandhi	18:6a4db94011d3	10054	#define EADC_AD0DAT4_RESULT_Pos (0) /!< EADC AD0DAT4: RESULT Position /
sahilmgandhi	18:6a4db94011d3	10055	#define EADC_AD0DAT4_RESULT_Msk (0xffful << EADC_AD0DAT4_RESULT_Pos) /!< EADC AD0DAT4: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	10056
sahilmgandhi	18:6a4db94011d3	10057	#define EADC_AD0DAT4_OV_Pos (16) /!< EADC AD0DAT4: OV Position /
sahilmgandhi	18:6a4db94011d3	10058	#define EADC_AD0DAT4_OV_Msk (0x1ul << EADC_AD0DAT4_OV_Pos) /!< EADC AD0DAT4: OV Mask /
sahilmgandhi	18:6a4db94011d3	10059
sahilmgandhi	18:6a4db94011d3	10060	#define EADC_AD0DAT4_VALID_Pos (17) /!< EADC AD0DAT4: VALID Position /
sahilmgandhi	18:6a4db94011d3	10061	#define EADC_AD0DAT4_VALID_Msk (0x1ul << EADC_AD0DAT4_VALID_Pos) /!< EADC AD0DAT4: VALID Mask /
sahilmgandhi	18:6a4db94011d3	10062
sahilmgandhi	18:6a4db94011d3	10063	#define EADC_AD0DAT5_RESULT_Pos (0) /!< EADC AD0DAT5: RESULT Position /
sahilmgandhi	18:6a4db94011d3	10064	#define EADC_AD0DAT5_RESULT_Msk (0xffful << EADC_AD0DAT5_RESULT_Pos) /!< EADC AD0DAT5: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	10065
sahilmgandhi	18:6a4db94011d3	10066	#define EADC_AD0DAT5_OV_Pos (16) /!< EADC AD0DAT5: OV Position /
sahilmgandhi	18:6a4db94011d3	10067	#define EADC_AD0DAT5_OV_Msk (0x1ul << EADC_AD0DAT5_OV_Pos) /!< EADC AD0DAT5: OV Mask /
sahilmgandhi	18:6a4db94011d3	10068
sahilmgandhi	18:6a4db94011d3	10069	#define EADC_AD0DAT5_VALID_Pos (17) /!< EADC AD0DAT5: VALID Position /
sahilmgandhi	18:6a4db94011d3	10070	#define EADC_AD0DAT5_VALID_Msk (0x1ul << EADC_AD0DAT5_VALID_Pos) /!< EADC AD0DAT5: VALID Mask /
sahilmgandhi	18:6a4db94011d3	10071
sahilmgandhi	18:6a4db94011d3	10072	#define EADC_AD0DAT6_RESULT_Pos (0) /!< EADC AD0DAT6: RESULT Position /
sahilmgandhi	18:6a4db94011d3	10073	#define EADC_AD0DAT6_RESULT_Msk (0xffful << EADC_AD0DAT6_RESULT_Pos) /!< EADC AD0DAT6: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	10074
sahilmgandhi	18:6a4db94011d3	10075	#define EADC_AD0DAT6_OV_Pos (16) /!< EADC AD0DAT6: OV Position /
sahilmgandhi	18:6a4db94011d3	10076	#define EADC_AD0DAT6_OV_Msk (0x1ul << EADC_AD0DAT6_OV_Pos) /!< EADC AD0DAT6: OV Mask /
sahilmgandhi	18:6a4db94011d3	10077
sahilmgandhi	18:6a4db94011d3	10078	#define EADC_AD0DAT6_VALID_Pos (17) /!< EADC AD0DAT6: VALID Position /
sahilmgandhi	18:6a4db94011d3	10079	#define EADC_AD0DAT6_VALID_Msk (0x1ul << EADC_AD0DAT6_VALID_Pos) /!< EADC AD0DAT6: VALID Mask /
sahilmgandhi	18:6a4db94011d3	10080
sahilmgandhi	18:6a4db94011d3	10081	#define EADC_AD0DAT7_RESULT_Pos (0) /!< EADC AD0DAT7: RESULT Position /
sahilmgandhi	18:6a4db94011d3	10082	#define EADC_AD0DAT7_RESULT_Msk (0xffful << EADC_AD0DAT7_RESULT_Pos) /!< EADC AD0DAT7: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	10083
sahilmgandhi	18:6a4db94011d3	10084	#define EADC_AD0DAT7_OV_Pos (16) /!< EADC AD0DAT7: OV Position /
sahilmgandhi	18:6a4db94011d3	10085	#define EADC_AD0DAT7_OV_Msk (0x1ul << EADC_AD0DAT7_OV_Pos) /!< EADC AD0DAT7: OV Mask /
sahilmgandhi	18:6a4db94011d3	10086
sahilmgandhi	18:6a4db94011d3	10087	#define EADC_AD0DAT7_VALID_Pos (17) /!< EADC AD0DAT7: VALID Position /
sahilmgandhi	18:6a4db94011d3	10088	#define EADC_AD0DAT7_VALID_Msk (0x1ul << EADC_AD0DAT7_VALID_Pos) /!< EADC AD0DAT7: VALID Mask /
sahilmgandhi	18:6a4db94011d3	10089
sahilmgandhi	18:6a4db94011d3	10090	#define EADC_AD1DAT0_RESULT_Pos (0) /!< EADC AD1DAT0: RESULT Position /
sahilmgandhi	18:6a4db94011d3	10091	#define EADC_AD1DAT0_RESULT_Msk (0xffful << EADC_AD1DAT0_RESULT_Pos) /!< EADC AD1DAT0: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	10092
sahilmgandhi	18:6a4db94011d3	10093	#define EADC_AD1DAT0_OV_Pos (16) /!< EADC AD1DAT0: OV Position /
sahilmgandhi	18:6a4db94011d3	10094	#define EADC_AD1DAT0_OV_Msk (0x1ul << EADC_AD1DAT0_OV_Pos) /!< EADC AD1DAT0: OV Mask /
sahilmgandhi	18:6a4db94011d3	10095
sahilmgandhi	18:6a4db94011d3	10096	#define EADC_AD1DAT0_VALID_Pos (17) /!< EADC AD1DAT0: VALID Position /
sahilmgandhi	18:6a4db94011d3	10097	#define EADC_AD1DAT0_VALID_Msk (0x1ul << EADC_AD1DAT0_VALID_Pos) /!< EADC AD1DAT0: VALID Mask /
sahilmgandhi	18:6a4db94011d3	10098
sahilmgandhi	18:6a4db94011d3	10099	#define EADC_AD1DAT1_RESULT_Pos (0) /!< EADC AD1DAT1: RESULT Position /
sahilmgandhi	18:6a4db94011d3	10100	#define EADC_AD1DAT1_RESULT_Msk (0xffful << EADC_AD1DAT1_RESULT_Pos) /!< EADC AD1DAT1: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	10101
sahilmgandhi	18:6a4db94011d3	10102	#define EADC_AD1DAT1_OV_Pos (16) /!< EADC AD1DAT1: OV Position /
sahilmgandhi	18:6a4db94011d3	10103	#define EADC_AD1DAT1_OV_Msk (0x1ul << EADC_AD1DAT1_OV_Pos) /!< EADC AD1DAT1: OV Mask /
sahilmgandhi	18:6a4db94011d3	10104
sahilmgandhi	18:6a4db94011d3	10105	#define EADC_AD1DAT1_VALID_Pos (17) /!< EADC AD1DAT1: VALID Position /
sahilmgandhi	18:6a4db94011d3	10106	#define EADC_AD1DAT1_VALID_Msk (0x1ul << EADC_AD1DAT1_VALID_Pos) /!< EADC AD1DAT1: VALID Mask /
sahilmgandhi	18:6a4db94011d3	10107
sahilmgandhi	18:6a4db94011d3	10108	#define EADC_AD1DAT2_RESULT_Pos (0) /!< EADC AD1DAT2: RESULT Position /
sahilmgandhi	18:6a4db94011d3	10109	#define EADC_AD1DAT2_RESULT_Msk (0xffful << EADC_AD1DAT2_RESULT_Pos) /!< EADC AD1DAT2: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	10110
sahilmgandhi	18:6a4db94011d3	10111	#define EADC_AD1DAT2_OV_Pos (16) /!< EADC AD1DAT2: OV Position /
sahilmgandhi	18:6a4db94011d3	10112	#define EADC_AD1DAT2_OV_Msk (0x1ul << EADC_AD1DAT2_OV_Pos) /!< EADC AD1DAT2: OV Mask /
sahilmgandhi	18:6a4db94011d3	10113
sahilmgandhi	18:6a4db94011d3	10114	#define EADC_AD1DAT2_VALID_Pos (17) /!< EADC AD1DAT2: VALID Position /
sahilmgandhi	18:6a4db94011d3	10115	#define EADC_AD1DAT2_VALID_Msk (0x1ul << EADC_AD1DAT2_VALID_Pos) /!< EADC AD1DAT2: VALID Mask /
sahilmgandhi	18:6a4db94011d3	10116
sahilmgandhi	18:6a4db94011d3	10117	#define EADC_AD1DAT3_RESULT_Pos (0) /!< EADC AD1DAT3: RESULT Position /
sahilmgandhi	18:6a4db94011d3	10118	#define EADC_AD1DAT3_RESULT_Msk (0xffful << EADC_AD1DAT3_RESULT_Pos) /!< EADC AD1DAT3: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	10119
sahilmgandhi	18:6a4db94011d3	10120	#define EADC_AD1DAT3_OV_Pos (16) /!< EADC AD1DAT3: OV Position /
sahilmgandhi	18:6a4db94011d3	10121	#define EADC_AD1DAT3_OV_Msk (0x1ul << EADC_AD1DAT3_OV_Pos) /!< EADC AD1DAT3: OV Mask /
sahilmgandhi	18:6a4db94011d3	10122
sahilmgandhi	18:6a4db94011d3	10123	#define EADC_AD1DAT3_VALID_Pos (17) /!< EADC AD1DAT3: VALID Position /
sahilmgandhi	18:6a4db94011d3	10124	#define EADC_AD1DAT3_VALID_Msk (0x1ul << EADC_AD1DAT3_VALID_Pos) /!< EADC AD1DAT3: VALID Mask /
sahilmgandhi	18:6a4db94011d3	10125
sahilmgandhi	18:6a4db94011d3	10126	#define EADC_AD1DAT4_RESULT_Pos (0) /!< EADC AD1DAT4: RESULT Position /
sahilmgandhi	18:6a4db94011d3	10127	#define EADC_AD1DAT4_RESULT_Msk (0xffful << EADC_AD1DAT4_RESULT_Pos) /!< EADC AD1DAT4: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	10128
sahilmgandhi	18:6a4db94011d3	10129	#define EADC_AD1DAT4_OV_Pos (16) /!< EADC AD1DAT4: OV Position /
sahilmgandhi	18:6a4db94011d3	10130	#define EADC_AD1DAT4_OV_Msk (0x1ul << EADC_AD1DAT4_OV_Pos) /!< EADC AD1DAT4: OV Mask /
sahilmgandhi	18:6a4db94011d3	10131
sahilmgandhi	18:6a4db94011d3	10132	#define EADC_AD1DAT4_VALID_Pos (17) /!< EADC AD1DAT4: VALID Position /
sahilmgandhi	18:6a4db94011d3	10133	#define EADC_AD1DAT4_VALID_Msk (0x1ul << EADC_AD1DAT4_VALID_Pos) /!< EADC AD1DAT4: VALID Mask /
sahilmgandhi	18:6a4db94011d3	10134
sahilmgandhi	18:6a4db94011d3	10135	#define EADC_AD1DAT5_RESULT_Pos (0) /!< EADC AD1DAT5: RESULT Position /
sahilmgandhi	18:6a4db94011d3	10136	#define EADC_AD1DAT5_RESULT_Msk (0xffful << EADC_AD1DAT5_RESULT_Pos) /!< EADC AD1DAT5: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	10137
sahilmgandhi	18:6a4db94011d3	10138	#define EADC_AD1DAT5_OV_Pos (16) /!< EADC AD1DAT5: OV Position /
sahilmgandhi	18:6a4db94011d3	10139	#define EADC_AD1DAT5_OV_Msk (0x1ul << EADC_AD1DAT5_OV_Pos) /!< EADC AD1DAT5: OV Mask /
sahilmgandhi	18:6a4db94011d3	10140
sahilmgandhi	18:6a4db94011d3	10141	#define EADC_AD1DAT5_VALID_Pos (17) /!< EADC AD1DAT5: VALID Position /
sahilmgandhi	18:6a4db94011d3	10142	#define EADC_AD1DAT5_VALID_Msk (0x1ul << EADC_AD1DAT5_VALID_Pos) /!< EADC AD1DAT5: VALID Mask /
sahilmgandhi	18:6a4db94011d3	10143
sahilmgandhi	18:6a4db94011d3	10144	#define EADC_AD1DAT6_RESULT_Pos (0) /!< EADC AD1DAT6: RESULT Position /
sahilmgandhi	18:6a4db94011d3	10145	#define EADC_AD1DAT6_RESULT_Msk (0xffful << EADC_AD1DAT6_RESULT_Pos) /!< EADC AD1DAT6: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	10146
sahilmgandhi	18:6a4db94011d3	10147	#define EADC_AD1DAT6_OV_Pos (16) /!< EADC AD1DAT6: OV Position /
sahilmgandhi	18:6a4db94011d3	10148	#define EADC_AD1DAT6_OV_Msk (0x1ul << EADC_AD1DAT6_OV_Pos) /!< EADC AD1DAT6: OV Mask /
sahilmgandhi	18:6a4db94011d3	10149
sahilmgandhi	18:6a4db94011d3	10150	#define EADC_AD1DAT6_VALID_Pos (17) /!< EADC AD1DAT6: VALID Position /
sahilmgandhi	18:6a4db94011d3	10151	#define EADC_AD1DAT6_VALID_Msk (0x1ul << EADC_AD1DAT6_VALID_Pos) /!< EADC AD1DAT6: VALID Mask /
sahilmgandhi	18:6a4db94011d3	10152
sahilmgandhi	18:6a4db94011d3	10153	#define EADC_AD1DAT7_RESULT_Pos (0) /!< EADC AD1DAT7: RESULT Position /
sahilmgandhi	18:6a4db94011d3	10154	#define EADC_AD1DAT7_RESULT_Msk (0xffful << EADC_AD1DAT7_RESULT_Pos) /!< EADC AD1DAT7: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	10155
sahilmgandhi	18:6a4db94011d3	10156	#define EADC_AD1DAT7_OV_Pos (16) /!< EADC AD1DAT7: OV Position /
sahilmgandhi	18:6a4db94011d3	10157	#define EADC_AD1DAT7_OV_Msk (0x1ul << EADC_AD1DAT7_OV_Pos) /!< EADC AD1DAT7: OV Mask /
sahilmgandhi	18:6a4db94011d3	10158
sahilmgandhi	18:6a4db94011d3	10159	#define EADC_AD1DAT7_VALID_Pos (17) /!< EADC AD1DAT7: VALID Position /
sahilmgandhi	18:6a4db94011d3	10160	#define EADC_AD1DAT7_VALID_Msk (0x1ul << EADC_AD1DAT7_VALID_Pos) /!< EADC AD1DAT7: VALID Mask /
sahilmgandhi	18:6a4db94011d3	10161
sahilmgandhi	18:6a4db94011d3	10162	#define EADC_CTL_ADCEN_Pos (0) /!< EADC CTL: ADCEN Position /
sahilmgandhi	18:6a4db94011d3	10163	#define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) /!< EADC CTL: ADCEN Mask /
sahilmgandhi	18:6a4db94011d3	10164
sahilmgandhi	18:6a4db94011d3	10165	#define EADC_CTL_ADCRST_Pos (1) /!< EADC CTL: ADCRST Position /
sahilmgandhi	18:6a4db94011d3	10166	#define EADC_CTL_ADCRST_Msk (0x1ul << EADC_CTL_ADCRST_Pos) /!< EADC CTL: ADCRST Mask /
sahilmgandhi	18:6a4db94011d3	10167
sahilmgandhi	18:6a4db94011d3	10168	#define EADC_CTL_ADCIEN0_Pos (2) /!< EADC CTL: ADCIEN0 Position /
sahilmgandhi	18:6a4db94011d3	10169	#define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) /!< EADC CTL: ADCIEN0 Mask /
sahilmgandhi	18:6a4db94011d3	10170
sahilmgandhi	18:6a4db94011d3	10171	#define EADC_CTL_ADCIEN1_Pos (3) /!< EADC CTL: ADCIEN1 Position /
sahilmgandhi	18:6a4db94011d3	10172	#define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) /!< EADC CTL: ADCIEN1 Mask /
sahilmgandhi	18:6a4db94011d3	10173
sahilmgandhi	18:6a4db94011d3	10174	#define EADC_CTL_ADCIEN2_Pos (4) /!< EADC CTL: ADCIEN2 Position /
sahilmgandhi	18:6a4db94011d3	10175	#define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) /!< EADC CTL: ADCIEN2 Mask /
sahilmgandhi	18:6a4db94011d3	10176
sahilmgandhi	18:6a4db94011d3	10177	#define EADC_CTL_ADCIEN3_Pos (5) /!< EADC CTL: ADCIEN3 Position /
sahilmgandhi	18:6a4db94011d3	10178	#define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) /!< EADC CTL: ADCIEN3 Mask /
sahilmgandhi	18:6a4db94011d3	10179
sahilmgandhi	18:6a4db94011d3	10180	#define EADC_SWTRG_SWTRG7_0_Pos (0) /!< EADC SWTRG: SWTRG7_0 Position /
sahilmgandhi	18:6a4db94011d3	10181	#define EADC_SWTRG_SWTRG7_0_Msk (0xfful << EADC_SWTRG_SWTRG7_0_Pos) /!< EADC SWTRG: SWTRG7_0 Mask /
sahilmgandhi	18:6a4db94011d3	10182
sahilmgandhi	18:6a4db94011d3	10183	#define EADC_SWTRG_SWTRG15_8_Pos (8) /!< EADC SWTRG: SWTRG15_8 Position /
sahilmgandhi	18:6a4db94011d3	10184	#define EADC_SWTRG_SWTRG15_8_Msk (0xfful << EADC_SWTRG_SWTRG15_8_Pos) /!< EADC SWTRG: SWTRG15_8 Mask /
sahilmgandhi	18:6a4db94011d3	10185
sahilmgandhi	18:6a4db94011d3	10186	#define EADC_PENDSTS_STPF7_0_Pos (0) /!< EADC PENDSTS: STPF7_0 Position /
sahilmgandhi	18:6a4db94011d3	10187	#define EADC_PENDSTS_STPF7_0_Msk (0xfful << EADC_PENDSTS_STPF7_0_Pos) /!< EADC PENDSTS: STPF7_0 Mask /
sahilmgandhi	18:6a4db94011d3	10188
sahilmgandhi	18:6a4db94011d3	10189	#define EADC_PENDSTS_STPF15_8_Pos (8) /!< EADC PENDSTS: STPF15_8 Position /
sahilmgandhi	18:6a4db94011d3	10190	#define EADC_PENDSTS_STPF15_8_Msk (0xfful << EADC_PENDSTS_STPF15_8_Pos) /!< EADC PENDSTS: STPF15_8 Mask /
sahilmgandhi	18:6a4db94011d3	10191
sahilmgandhi	18:6a4db94011d3	10192	#define EADC_ADIFOV_ADFOV0_Pos (0) /!< EADC ADIFOV: ADFOV0 Position /
sahilmgandhi	18:6a4db94011d3	10193	#define EADC_ADIFOV_ADFOV0_Msk (0x1ul << EADC_ADIFOV_ADFOV0_Pos) /!< EADC ADIFOV: ADFOV0 Mask /
sahilmgandhi	18:6a4db94011d3	10194
sahilmgandhi	18:6a4db94011d3	10195	#define EADC_ADIFOV_ADFOV1_Pos (1) /!< EADC ADIFOV: ADFOV1 Position /
sahilmgandhi	18:6a4db94011d3	10196	#define EADC_ADIFOV_ADFOV1_Msk (0x1ul << EADC_ADIFOV_ADFOV1_Pos) /!< EADC ADIFOV: ADFOV1 Mask /
sahilmgandhi	18:6a4db94011d3	10197
sahilmgandhi	18:6a4db94011d3	10198	#define EADC_ADIFOV_ADFOV2_Pos (2) /!< EADC ADIFOV: ADFOV2 Position /
sahilmgandhi	18:6a4db94011d3	10199	#define EADC_ADIFOV_ADFOV2_Msk (0x1ul << EADC_ADIFOV_ADFOV2_Pos) /!< EADC ADIFOV: ADFOV2 Mask /
sahilmgandhi	18:6a4db94011d3	10200
sahilmgandhi	18:6a4db94011d3	10201	#define EADC_ADIFOV_ADFOV3_Pos (3) /!< EADC ADIFOV: ADFOV3 Position /
sahilmgandhi	18:6a4db94011d3	10202	#define EADC_ADIFOV_ADFOV3_Msk (0x1ul << EADC_ADIFOV_ADFOV3_Pos) /!< EADC ADIFOV: ADFOV3 Mask /
sahilmgandhi	18:6a4db94011d3	10203
sahilmgandhi	18:6a4db94011d3	10204	#define EADC_OVSTS_SPOVF7_0_Pos (0) /!< EADC OVSTS: SPOVF7_0 Position /
sahilmgandhi	18:6a4db94011d3	10205	#define EADC_OVSTS_SPOVF7_0_Msk (0xfful << EADC_OVSTS_SPOVF7_0_Pos) /!< EADC OVSTS: SPOVF7_0 Mask /
sahilmgandhi	18:6a4db94011d3	10206
sahilmgandhi	18:6a4db94011d3	10207	#define EADC_OVSTS_SPOVF15_8_Pos (8) /!< EADC OVSTS: SPOVF15_8 Position /
sahilmgandhi	18:6a4db94011d3	10208	#define EADC_OVSTS_SPOVF15_8_Msk (0xfful << EADC_OVSTS_SPOVF15_8_Pos) /!< EADC OVSTS: SPOVF15_8 Mask /
sahilmgandhi	18:6a4db94011d3	10209
sahilmgandhi	18:6a4db94011d3	10210	#define EADC_AD0SPCTL0_CHSEL_Pos (0) /!< EADC AD0SPCTL0: CHSEL Position /
sahilmgandhi	18:6a4db94011d3	10211	#define EADC_AD0SPCTL0_CHSEL_Msk (0xful << EADC_AD0SPCTL0_CHSEL_Pos) /!< EADC AD0SPCTL0: CHSEL Mask /
sahilmgandhi	18:6a4db94011d3	10212
sahilmgandhi	18:6a4db94011d3	10213	#define EADC_AD0SPCTL0_TRGSEL_Pos (4) /!< EADC AD0SPCTL0: TRGSEL Position /
sahilmgandhi	18:6a4db94011d3	10214	#define EADC_AD0SPCTL0_TRGSEL_Msk (0xful << EADC_AD0SPCTL0_TRGSEL_Pos) /!< EADC AD0SPCTL0: TRGSEL Mask /
sahilmgandhi	18:6a4db94011d3	10215
sahilmgandhi	18:6a4db94011d3	10216	#define EADC_AD0SPCTL0_TRGDLYCNT_Pos (8) /!< EADC AD0SPCTL0: TRGDLYCNT Position /
sahilmgandhi	18:6a4db94011d3	10217	#define EADC_AD0SPCTL0_TRGDLYCNT_Msk (0xfful << EADC_AD0SPCTL0_TRGDLYCNT_Pos) /!< EADC AD0SPCTL0: TRGDLYCNT Mask /
sahilmgandhi	18:6a4db94011d3	10218
sahilmgandhi	18:6a4db94011d3	10219	#define EADC_AD0SPCTL0_TRGDLYDIV_Pos (16) /!< EADC AD0SPCTL0: TRGDLYDIV Position /
sahilmgandhi	18:6a4db94011d3	10220	#define EADC_AD0SPCTL0_TRGDLYDIV_Msk (0x3ul << EADC_AD0SPCTL0_TRGDLYDIV_Pos) /!< EADC AD0SPCTL0: TRGDLYDIV Mask /
sahilmgandhi	18:6a4db94011d3	10221
sahilmgandhi	18:6a4db94011d3	10222	#define EADC_AD0SPCTL0_EXTREN_Pos (20) /!< EADC AD0SPCTL0: EXTREN Position /
sahilmgandhi	18:6a4db94011d3	10223	#define EADC_AD0SPCTL0_EXTREN_Msk (0x1ul << EADC_AD0SPCTL0_EXTREN_Pos) /!< EADC AD0SPCTL0: EXTREN Mask /
sahilmgandhi	18:6a4db94011d3	10224
sahilmgandhi	18:6a4db94011d3	10225	#define EADC_AD0SPCTL0_EXTFEN_Pos (21) /!< EADC AD0SPCTL0: EXTFEN Position /
sahilmgandhi	18:6a4db94011d3	10226	#define EADC_AD0SPCTL0_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL0_EXTFEN_Pos) /!< EADC AD0SPCTL0: EXTFEN Mask /
sahilmgandhi	18:6a4db94011d3	10227
sahilmgandhi	18:6a4db94011d3	10228	#define EADC_AD0SPCTL1_CHSEL_Pos (0) /!< EADC AD0SPCTL1: CHSEL Position /
sahilmgandhi	18:6a4db94011d3	10229	#define EADC_AD0SPCTL1_CHSEL_Msk (0xful << EADC_AD0SPCTL1_CHSEL_Pos) /!< EADC AD0SPCTL1: CHSEL Mask /
sahilmgandhi	18:6a4db94011d3	10230
sahilmgandhi	18:6a4db94011d3	10231	#define EADC_AD0SPCTL1_TRGSEL_Pos (4) /!< EADC AD0SPCTL1: TRGSEL Position /
sahilmgandhi	18:6a4db94011d3	10232	#define EADC_AD0SPCTL1_TRGSEL_Msk (0xful << EADC_AD0SPCTL1_TRGSEL_Pos) /!< EADC AD0SPCTL1: TRGSEL Mask /
sahilmgandhi	18:6a4db94011d3	10233
sahilmgandhi	18:6a4db94011d3	10234	#define EADC_AD0SPCTL1_TRGDLYCNT_Pos (8) /!< EADC AD0SPCTL1: TRGDLYCNT Position /
sahilmgandhi	18:6a4db94011d3	10235	#define EADC_AD0SPCTL1_TRGDLYCNT_Msk (0xfful << EADC_AD0SPCTL1_TRGDLYCNT_Pos) /!< EADC AD0SPCTL1: TRGDLYCNT Mask /
sahilmgandhi	18:6a4db94011d3	10236
sahilmgandhi	18:6a4db94011d3	10237	#define EADC_AD0SPCTL1_TRGDLYDIV_Pos (16) /!< EADC AD0SPCTL1: TRGDLYDIV Position /
sahilmgandhi	18:6a4db94011d3	10238	#define EADC_AD0SPCTL1_TRGDLYDIV_Msk (0x3ul << EADC_AD0SPCTL1_TRGDLYDIV_Pos) /!< EADC AD0SPCTL1: TRGDLYDIV Mask /
sahilmgandhi	18:6a4db94011d3	10239
sahilmgandhi	18:6a4db94011d3	10240	#define EADC_AD0SPCTL1_EXTREN_Pos (20) /!< EADC AD0SPCTL1: EXTREN Position /
sahilmgandhi	18:6a4db94011d3	10241	#define EADC_AD0SPCTL1_EXTREN_Msk (0x1ul << EADC_AD0SPCTL1_EXTREN_Pos) /!< EADC AD0SPCTL1: EXTREN Mask /
sahilmgandhi	18:6a4db94011d3	10242
sahilmgandhi	18:6a4db94011d3	10243	#define EADC_AD0SPCTL1_EXTFEN_Pos (21) /!< EADC AD0SPCTL1: EXTFEN Position /
sahilmgandhi	18:6a4db94011d3	10244	#define EADC_AD0SPCTL1_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL1_EXTFEN_Pos) /!< EADC AD0SPCTL1: EXTFEN Mask /
sahilmgandhi	18:6a4db94011d3	10245
sahilmgandhi	18:6a4db94011d3	10246	#define EADC_AD0SPCTL2_CHSEL_Pos (0) /!< EADC AD0SPCTL2: CHSEL Position /
sahilmgandhi	18:6a4db94011d3	10247	#define EADC_AD0SPCTL2_CHSEL_Msk (0xful << EADC_AD0SPCTL2_CHSEL_Pos) /!< EADC AD0SPCTL2: CHSEL Mask /
sahilmgandhi	18:6a4db94011d3	10248
sahilmgandhi	18:6a4db94011d3	10249	#define EADC_AD0SPCTL2_TRGSEL_Pos (4) /!< EADC AD0SPCTL2: TRGSEL Position /
sahilmgandhi	18:6a4db94011d3	10250	#define EADC_AD0SPCTL2_TRGSEL_Msk (0xful << EADC_AD0SPCTL2_TRGSEL_Pos) /!< EADC AD0SPCTL2: TRGSEL Mask /
sahilmgandhi	18:6a4db94011d3	10251
sahilmgandhi	18:6a4db94011d3	10252	#define EADC_AD0SPCTL2_TRGDLYCNT_Pos (8) /!< EADC AD0SPCTL2: TRGDLYCNT Position /
sahilmgandhi	18:6a4db94011d3	10253	#define EADC_AD0SPCTL2_TRGDLYCNT_Msk (0xfful << EADC_AD0SPCTL2_TRGDLYCNT_Pos) /!< EADC AD0SPCTL2: TRGDLYCNT Mask /
sahilmgandhi	18:6a4db94011d3	10254
sahilmgandhi	18:6a4db94011d3	10255	#define EADC_AD0SPCTL2_TRGDLYDIV_Pos (16) /!< EADC AD0SPCTL2: TRGDLYDIV Position /
sahilmgandhi	18:6a4db94011d3	10256	#define EADC_AD0SPCTL2_TRGDLYDIV_Msk (0x3ul << EADC_AD0SPCTL2_TRGDLYDIV_Pos) /!< EADC AD0SPCTL2: TRGDLYDIV Mask /
sahilmgandhi	18:6a4db94011d3	10257
sahilmgandhi	18:6a4db94011d3	10258	#define EADC_AD0SPCTL2_EXTREN_Pos (20) /!< EADC AD0SPCTL2: EXTREN Position /
sahilmgandhi	18:6a4db94011d3	10259	#define EADC_AD0SPCTL2_EXTREN_Msk (0x1ul << EADC_AD0SPCTL2_EXTREN_Pos) /!< EADC AD0SPCTL2: EXTREN Mask /
sahilmgandhi	18:6a4db94011d3	10260
sahilmgandhi	18:6a4db94011d3	10261	#define EADC_AD0SPCTL2_EXTFEN_Pos (21) /!< EADC AD0SPCTL2: EXTFEN Position /
sahilmgandhi	18:6a4db94011d3	10262	#define EADC_AD0SPCTL2_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL2_EXTFEN_Pos) /!< EADC AD0SPCTL2: EXTFEN Mask /
sahilmgandhi	18:6a4db94011d3	10263
sahilmgandhi	18:6a4db94011d3	10264	#define EADC_AD0SPCTL3_CHSEL_Pos (0) /!< EADC AD0SPCTL3: CHSEL Position /
sahilmgandhi	18:6a4db94011d3	10265	#define EADC_AD0SPCTL3_CHSEL_Msk (0xful << EADC_AD0SPCTL3_CHSEL_Pos) /!< EADC AD0SPCTL3: CHSEL Mask /
sahilmgandhi	18:6a4db94011d3	10266
sahilmgandhi	18:6a4db94011d3	10267	#define EADC_AD0SPCTL3_TRGSEL_Pos (4) /!< EADC AD0SPCTL3: TRGSEL Position /
sahilmgandhi	18:6a4db94011d3	10268	#define EADC_AD0SPCTL3_TRGSEL_Msk (0xful << EADC_AD0SPCTL3_TRGSEL_Pos) /!< EADC AD0SPCTL3: TRGSEL Mask /
sahilmgandhi	18:6a4db94011d3	10269
sahilmgandhi	18:6a4db94011d3	10270	#define EADC_AD0SPCTL3_TRGDLYCNT_Pos (8) /!< EADC AD0SPCTL3: TRGDLYCNT Position /
sahilmgandhi	18:6a4db94011d3	10271	#define EADC_AD0SPCTL3_TRGDLYCNT_Msk (0xfful << EADC_AD0SPCTL3_TRGDLYCNT_Pos) /!< EADC AD0SPCTL3: TRGDLYCNT Mask /
sahilmgandhi	18:6a4db94011d3	10272
sahilmgandhi	18:6a4db94011d3	10273	#define EADC_AD0SPCTL3_TRGDLYDIV_Pos (16) /!< EADC AD0SPCTL3: TRGDLYDIV Position /
sahilmgandhi	18:6a4db94011d3	10274	#define EADC_AD0SPCTL3_TRGDLYDIV_Msk (0x3ul << EADC_AD0SPCTL3_TRGDLYDIV_Pos) /!< EADC AD0SPCTL3: TRGDLYDIV Mask /
sahilmgandhi	18:6a4db94011d3	10275
sahilmgandhi	18:6a4db94011d3	10276	#define EADC_AD0SPCTL3_EXTREN_Pos (20) /!< EADC AD0SPCTL3: EXTREN Position /
sahilmgandhi	18:6a4db94011d3	10277	#define EADC_AD0SPCTL3_EXTREN_Msk (0x1ul << EADC_AD0SPCTL3_EXTREN_Pos) /!< EADC AD0SPCTL3: EXTREN Mask /
sahilmgandhi	18:6a4db94011d3	10278
sahilmgandhi	18:6a4db94011d3	10279	#define EADC_AD0SPCTL3_EXTFEN_Pos (21) /!< EADC AD0SPCTL3: EXTFEN Position /
sahilmgandhi	18:6a4db94011d3	10280	#define EADC_AD0SPCTL3_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL3_EXTFEN_Pos) /!< EADC AD0SPCTL3: EXTFEN Mask /
sahilmgandhi	18:6a4db94011d3	10281
sahilmgandhi	18:6a4db94011d3	10282	#define EADC_AD0SPCTL4_CHSEL_Pos (0) /!< EADC AD0SPCTL4: CHSEL Position /
sahilmgandhi	18:6a4db94011d3	10283	#define EADC_AD0SPCTL4_CHSEL_Msk (0xful << EADC_AD0SPCTL4_CHSEL_Pos) /!< EADC AD0SPCTL4: CHSEL Mask /
sahilmgandhi	18:6a4db94011d3	10284
sahilmgandhi	18:6a4db94011d3	10285	#define EADC_AD0SPCTL4_TRGSEL_Pos (4) /!< EADC AD0SPCTL4: TRGSEL Position /
sahilmgandhi	18:6a4db94011d3	10286	#define EADC_AD0SPCTL4_TRGSEL_Msk (0x7ul << EADC_AD0SPCTL4_TRGSEL_Pos) /!< EADC AD0SPCTL4: TRGSEL Mask /
sahilmgandhi	18:6a4db94011d3	10287
sahilmgandhi	18:6a4db94011d3	10288	#define EADC_AD0SPCTL4_EXTREN_Pos (20) /!< EADC AD0SPCTL4: EXTREN Position /
sahilmgandhi	18:6a4db94011d3	10289	#define EADC_AD0SPCTL4_EXTREN_Msk (0x1ul << EADC_AD0SPCTL4_EXTREN_Pos) /!< EADC AD0SPCTL4: EXTREN Mask /
sahilmgandhi	18:6a4db94011d3	10290
sahilmgandhi	18:6a4db94011d3	10291	#define EADC_AD0SPCTL4_EXTFEN_Pos (21) /!< EADC AD0SPCTL4: EXTFEN Position /
sahilmgandhi	18:6a4db94011d3	10292	#define EADC_AD0SPCTL4_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL4_EXTFEN_Pos) /!< EADC AD0SPCTL4: EXTFEN Mask /
sahilmgandhi	18:6a4db94011d3	10293
sahilmgandhi	18:6a4db94011d3	10294	#define EADC_AD0SPCTL5_CHSEL_Pos (0) /!< EADC AD0SPCTL5: CHSEL Position /
sahilmgandhi	18:6a4db94011d3	10295	#define EADC_AD0SPCTL5_CHSEL_Msk (0xful << EADC_AD0SPCTL5_CHSEL_Pos) /!< EADC AD0SPCTL5: CHSEL Mask /
sahilmgandhi	18:6a4db94011d3	10296
sahilmgandhi	18:6a4db94011d3	10297	#define EADC_AD0SPCTL5_TRGSEL_Pos (4) /!< EADC AD0SPCTL5: TRGSEL Position /
sahilmgandhi	18:6a4db94011d3	10298	#define EADC_AD0SPCTL5_TRGSEL_Msk (0x7ul << EADC_AD0SPCTL5_TRGSEL_Pos) /!< EADC AD0SPCTL5: TRGSEL Mask /
sahilmgandhi	18:6a4db94011d3	10299
sahilmgandhi	18:6a4db94011d3	10300	#define EADC_AD0SPCTL5_EXTREN_Pos (20) /!< EADC AD0SPCTL5: EXTREN Position /
sahilmgandhi	18:6a4db94011d3	10301	#define EADC_AD0SPCTL5_EXTREN_Msk (0x1ul << EADC_AD0SPCTL5_EXTREN_Pos) /!< EADC AD0SPCTL5: EXTREN Mask /
sahilmgandhi	18:6a4db94011d3	10302
sahilmgandhi	18:6a4db94011d3	10303	#define EADC_AD0SPCTL5_EXTFEN_Pos (21) /!< EADC AD0SPCTL5: EXTFEN Position /
sahilmgandhi	18:6a4db94011d3	10304	#define EADC_AD0SPCTL5_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL5_EXTFEN_Pos) /!< EADC AD0SPCTL5: EXTFEN Mask /
sahilmgandhi	18:6a4db94011d3	10305
sahilmgandhi	18:6a4db94011d3	10306	#define EADC_AD0SPCTL6_CHSEL_Pos (0) /!< EADC AD0SPCTL6: CHSEL Position /
sahilmgandhi	18:6a4db94011d3	10307	#define EADC_AD0SPCTL6_CHSEL_Msk (0xful << EADC_AD0SPCTL6_CHSEL_Pos) /!< EADC AD0SPCTL6: CHSEL Mask /
sahilmgandhi	18:6a4db94011d3	10308
sahilmgandhi	18:6a4db94011d3	10309	#define EADC_AD0SPCTL6_TRGSEL_Pos (4) /!< EADC AD0SPCTL6: TRGSEL Position /
sahilmgandhi	18:6a4db94011d3	10310	#define EADC_AD0SPCTL6_TRGSEL_Msk (0x7ul << EADC_AD0SPCTL6_TRGSEL_Pos) /!< EADC AD0SPCTL6: TRGSEL Mask /
sahilmgandhi	18:6a4db94011d3	10311
sahilmgandhi	18:6a4db94011d3	10312	#define EADC_AD0SPCTL6_EXTREN_Pos (20) /!< EADC AD0SPCTL6: EXTREN Position /
sahilmgandhi	18:6a4db94011d3	10313	#define EADC_AD0SPCTL6_EXTREN_Msk (0x1ul << EADC_AD0SPCTL6_EXTREN_Pos) /!< EADC AD0SPCTL6: EXTREN Mask /
sahilmgandhi	18:6a4db94011d3	10314
sahilmgandhi	18:6a4db94011d3	10315	#define EADC_AD0SPCTL6_EXTFEN_Pos (21) /!< EADC AD0SPCTL6: EXTFEN Position /
sahilmgandhi	18:6a4db94011d3	10316	#define EADC_AD0SPCTL6_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL6_EXTFEN_Pos) /!< EADC AD0SPCTL6: EXTFEN Mask /
sahilmgandhi	18:6a4db94011d3	10317
sahilmgandhi	18:6a4db94011d3	10318	#define EADC_AD0SPCTL7_CHSEL_Pos (0) /!< EADC AD0SPCTL7: CHSEL Position /
sahilmgandhi	18:6a4db94011d3	10319	#define EADC_AD0SPCTL7_CHSEL_Msk (0xful << EADC_AD0SPCTL7_CHSEL_Pos) /!< EADC AD0SPCTL7: CHSEL Mask /
sahilmgandhi	18:6a4db94011d3	10320
sahilmgandhi	18:6a4db94011d3	10321	#define EADC_AD0SPCTL7_TRGSEL_Pos (4) /!< EADC AD0SPCTL7: TRGSEL Position /
sahilmgandhi	18:6a4db94011d3	10322	#define EADC_AD0SPCTL7_TRGSEL_Msk (0x7ul << EADC_AD0SPCTL7_TRGSEL_Pos) /!< EADC AD0SPCTL7: TRGSEL Mask /
sahilmgandhi	18:6a4db94011d3	10323
sahilmgandhi	18:6a4db94011d3	10324	#define EADC_AD0SPCTL7_EXTREN_Pos (20) /!< EADC AD0SPCTL7: EXTREN Position /
sahilmgandhi	18:6a4db94011d3	10325	#define EADC_AD0SPCTL7_EXTREN_Msk (0x1ul << EADC_AD0SPCTL7_EXTREN_Pos) /!< EADC AD0SPCTL7: EXTREN Mask /
sahilmgandhi	18:6a4db94011d3	10326
sahilmgandhi	18:6a4db94011d3	10327	#define EADC_AD0SPCTL7_EXTFEN_Pos (21) /!< EADC AD0SPCTL7: EXTFEN Position /
sahilmgandhi	18:6a4db94011d3	10328	#define EADC_AD0SPCTL7_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL7_EXTFEN_Pos) /!< EADC AD0SPCTL7: EXTFEN Mask /
sahilmgandhi	18:6a4db94011d3	10329
sahilmgandhi	18:6a4db94011d3	10330	#define EADC_AD1SPCTL0_CHSEL_Pos (0) /!< EADC AD1SPCTL0: CHSEL Position /
sahilmgandhi	18:6a4db94011d3	10331	#define EADC_AD1SPCTL0_CHSEL_Msk (0xful << EADC_AD1SPCTL0_CHSEL_Pos) /!< EADC AD1SPCTL0: CHSEL Mask /
sahilmgandhi	18:6a4db94011d3	10332
sahilmgandhi	18:6a4db94011d3	10333	#define EADC_AD1SPCTL0_TRGSEL_Pos (4) /!< EADC AD1SPCTL0: TRGSEL Position /
sahilmgandhi	18:6a4db94011d3	10334	#define EADC_AD1SPCTL0_TRGSEL_Msk (0xful << EADC_AD1SPCTL0_TRGSEL_Pos) /!< EADC AD1SPCTL0: TRGSEL Mask /
sahilmgandhi	18:6a4db94011d3	10335
sahilmgandhi	18:6a4db94011d3	10336	#define EADC_AD1SPCTL0_TRGDLYCNT_Pos (8) /!< EADC AD1SPCTL0: TRGDLYCNT Position /
sahilmgandhi	18:6a4db94011d3	10337	#define EADC_AD1SPCTL0_TRGDLYCNT_Msk (0xfful << EADC_AD1SPCTL0_TRGDLYCNT_Pos) /!< EADC AD1SPCTL0: TRGDLYCNT Mask /
sahilmgandhi	18:6a4db94011d3	10338
sahilmgandhi	18:6a4db94011d3	10339	#define EADC_AD1SPCTL0_TRGDLYDIV_Pos (16) /!< EADC AD1SPCTL0: TRGDLYDIV Position /
sahilmgandhi	18:6a4db94011d3	10340	#define EADC_AD1SPCTL0_TRGDLYDIV_Msk (0x3ul << EADC_AD1SPCTL0_TRGDLYDIV_Pos) /!< EADC AD1SPCTL0: TRGDLYDIV Mask /
sahilmgandhi	18:6a4db94011d3	10341
sahilmgandhi	18:6a4db94011d3	10342	#define EADC_AD1SPCTL0_EXTREN_Pos (20) /!< EADC AD1SPCTL0: EXTREN Position /
sahilmgandhi	18:6a4db94011d3	10343	#define EADC_AD1SPCTL0_EXTREN_Msk (0x1ul << EADC_AD1SPCTL0_EXTREN_Pos) /!< EADC AD1SPCTL0: EXTREN Mask /
sahilmgandhi	18:6a4db94011d3	10344
sahilmgandhi	18:6a4db94011d3	10345	#define EADC_AD1SPCTL0_EXTFEN_Pos (21) /!< EADC AD1SPCTL0: EXTFEN Position /
sahilmgandhi	18:6a4db94011d3	10346	#define EADC_AD1SPCTL0_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL0_EXTFEN_Pos) /!< EADC AD1SPCTL0: EXTFEN Mask /
sahilmgandhi	18:6a4db94011d3	10347
sahilmgandhi	18:6a4db94011d3	10348	#define EADC_AD1SPCTL1_CHSEL_Pos (0) /!< EADC AD1SPCTL1: CHSEL Position /
sahilmgandhi	18:6a4db94011d3	10349	#define EADC_AD1SPCTL1_CHSEL_Msk (0xful << EADC_AD1SPCTL1_CHSEL_Pos) /!< EADC AD1SPCTL1: CHSEL Mask /
sahilmgandhi	18:6a4db94011d3	10350
sahilmgandhi	18:6a4db94011d3	10351	#define EADC_AD1SPCTL1_TRGSEL_Pos (4) /!< EADC AD1SPCTL1: TRGSEL Position /
sahilmgandhi	18:6a4db94011d3	10352	#define EADC_AD1SPCTL1_TRGSEL_Msk (0xful << EADC_AD1SPCTL1_TRGSEL_Pos) /!< EADC AD1SPCTL1: TRGSEL Mask /
sahilmgandhi	18:6a4db94011d3	10353
sahilmgandhi	18:6a4db94011d3	10354	#define EADC_AD1SPCTL1_TRGDLYCNT_Pos (8) /!< EADC AD1SPCTL1: TRGDLYCNT Position /
sahilmgandhi	18:6a4db94011d3	10355	#define EADC_AD1SPCTL1_TRGDLYCNT_Msk (0xfful << EADC_AD1SPCTL1_TRGDLYCNT_Pos) /!< EADC AD1SPCTL1: TRGDLYCNT Mask /
sahilmgandhi	18:6a4db94011d3	10356
sahilmgandhi	18:6a4db94011d3	10357	#define EADC_AD1SPCTL1_TRGDLYDIV_Pos (16) /!< EADC AD1SPCTL1: TRGDLYDIV Position /
sahilmgandhi	18:6a4db94011d3	10358	#define EADC_AD1SPCTL1_TRGDLYDIV_Msk (0x3ul << EADC_AD1SPCTL1_TRGDLYDIV_Pos) /!< EADC AD1SPCTL1: TRGDLYDIV Mask /
sahilmgandhi	18:6a4db94011d3	10359
sahilmgandhi	18:6a4db94011d3	10360	#define EADC_AD1SPCTL1_EXTREN_Pos (20) /!< EADC AD1SPCTL1: EXTREN Position /
sahilmgandhi	18:6a4db94011d3	10361	#define EADC_AD1SPCTL1_EXTREN_Msk (0x1ul << EADC_AD1SPCTL1_EXTREN_Pos) /!< EADC AD1SPCTL1: EXTREN Mask /
sahilmgandhi	18:6a4db94011d3	10362
sahilmgandhi	18:6a4db94011d3	10363	#define EADC_AD1SPCTL1_EXTFEN_Pos (21) /!< EADC AD1SPCTL1: EXTFEN Position /
sahilmgandhi	18:6a4db94011d3	10364	#define EADC_AD1SPCTL1_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL1_EXTFEN_Pos) /!< EADC AD1SPCTL1: EXTFEN Mask /
sahilmgandhi	18:6a4db94011d3	10365
sahilmgandhi	18:6a4db94011d3	10366	#define EADC_AD1SPCTL2_CHSEL_Pos (0) /!< EADC AD1SPCTL2: CHSEL Position /
sahilmgandhi	18:6a4db94011d3	10367	#define EADC_AD1SPCTL2_CHSEL_Msk (0xful << EADC_AD1SPCTL2_CHSEL_Pos) /!< EADC AD1SPCTL2: CHSEL Mask /
sahilmgandhi	18:6a4db94011d3	10368
sahilmgandhi	18:6a4db94011d3	10369	#define EADC_AD1SPCTL2_TRGSEL_Pos (4) /!< EADC AD1SPCTL2: TRGSEL Position /
sahilmgandhi	18:6a4db94011d3	10370	#define EADC_AD1SPCTL2_TRGSEL_Msk (0xful << EADC_AD1SPCTL2_TRGSEL_Pos) /!< EADC AD1SPCTL2: TRGSEL Mask /
sahilmgandhi	18:6a4db94011d3	10371
sahilmgandhi	18:6a4db94011d3	10372	#define EADC_AD1SPCTL2_TRGDLYCNT_Pos (8) /!< EADC AD1SPCTL2: TRGDLYCNT Position /
sahilmgandhi	18:6a4db94011d3	10373	#define EADC_AD1SPCTL2_TRGDLYCNT_Msk (0xfful << EADC_AD1SPCTL2_TRGDLYCNT_Pos) /!< EADC AD1SPCTL2: TRGDLYCNT Mask /
sahilmgandhi	18:6a4db94011d3	10374
sahilmgandhi	18:6a4db94011d3	10375	#define EADC_AD1SPCTL2_TRGDLYDIV_Pos (16) /!< EADC AD1SPCTL2: TRGDLYDIV Position /
sahilmgandhi	18:6a4db94011d3	10376	#define EADC_AD1SPCTL2_TRGDLYDIV_Msk (0x3ul << EADC_AD1SPCTL2_TRGDLYDIV_Pos) /!< EADC AD1SPCTL2: TRGDLYDIV Mask /
sahilmgandhi	18:6a4db94011d3	10377
sahilmgandhi	18:6a4db94011d3	10378	#define EADC_AD1SPCTL2_EXTREN_Pos (20) /!< EADC AD1SPCTL2: EXTREN Position /
sahilmgandhi	18:6a4db94011d3	10379	#define EADC_AD1SPCTL2_EXTREN_Msk (0x1ul << EADC_AD1SPCTL2_EXTREN_Pos) /!< EADC AD1SPCTL2: EXTREN Mask /
sahilmgandhi	18:6a4db94011d3	10380
sahilmgandhi	18:6a4db94011d3	10381	#define EADC_AD1SPCTL2_EXTFEN_Pos (21) /!< EADC AD1SPCTL2: EXTFEN Position /
sahilmgandhi	18:6a4db94011d3	10382	#define EADC_AD1SPCTL2_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL2_EXTFEN_Pos) /!< EADC AD1SPCTL2: EXTFEN Mask /
sahilmgandhi	18:6a4db94011d3	10383
sahilmgandhi	18:6a4db94011d3	10384	#define EADC_AD1SPCTL3_CHSEL_Pos (0) /!< EADC AD1SPCTL3: CHSEL Position /
sahilmgandhi	18:6a4db94011d3	10385	#define EADC_AD1SPCTL3_CHSEL_Msk (0xful << EADC_AD1SPCTL3_CHSEL_Pos) /!< EADC AD1SPCTL3: CHSEL Mask /
sahilmgandhi	18:6a4db94011d3	10386
sahilmgandhi	18:6a4db94011d3	10387	#define EADC_AD1SPCTL3_TRGSEL_Pos (4) /!< EADC AD1SPCTL3: TRGSEL Position /
sahilmgandhi	18:6a4db94011d3	10388	#define EADC_AD1SPCTL3_TRGSEL_Msk (0xful << EADC_AD1SPCTL3_TRGSEL_Pos) /!< EADC AD1SPCTL3: TRGSEL Mask /
sahilmgandhi	18:6a4db94011d3	10389
sahilmgandhi	18:6a4db94011d3	10390	#define EADC_AD1SPCTL3_TRGDLYCNT_Pos (8) /!< EADC AD1SPCTL3: TRGDLYCNT Position /
sahilmgandhi	18:6a4db94011d3	10391	#define EADC_AD1SPCTL3_TRGDLYCNT_Msk (0xfful << EADC_AD1SPCTL3_TRGDLYCNT_Pos) /!< EADC AD1SPCTL3: TRGDLYCNT Mask /
sahilmgandhi	18:6a4db94011d3	10392
sahilmgandhi	18:6a4db94011d3	10393	#define EADC_AD1SPCTL3_TRGDLYDIV_Pos (16) /!< EADC AD1SPCTL3: TRGDLYDIV Position /
sahilmgandhi	18:6a4db94011d3	10394	#define EADC_AD1SPCTL3_TRGDLYDIV_Msk (0x3ul << EADC_AD1SPCTL3_TRGDLYDIV_Pos) /!< EADC AD1SPCTL3: TRGDLYDIV Mask /
sahilmgandhi	18:6a4db94011d3	10395
sahilmgandhi	18:6a4db94011d3	10396	#define EADC_AD1SPCTL3_EXTREN_Pos (20) /!< EADC AD1SPCTL3: EXTREN Position /
sahilmgandhi	18:6a4db94011d3	10397	#define EADC_AD1SPCTL3_EXTREN_Msk (0x1ul << EADC_AD1SPCTL3_EXTREN_Pos) /!< EADC AD1SPCTL3: EXTREN Mask /
sahilmgandhi	18:6a4db94011d3	10398
sahilmgandhi	18:6a4db94011d3	10399	#define EADC_AD1SPCTL3_EXTFEN_Pos (21) /!< EADC AD1SPCTL3: EXTFEN Position /
sahilmgandhi	18:6a4db94011d3	10400	#define EADC_AD1SPCTL3_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL3_EXTFEN_Pos) /!< EADC AD1SPCTL3: EXTFEN Mask /
sahilmgandhi	18:6a4db94011d3	10401
sahilmgandhi	18:6a4db94011d3	10402	#define EADC_AD1SPCTL4_CHSEL_Pos (0) /!< EADC AD1SPCTL4: CHSEL Position /
sahilmgandhi	18:6a4db94011d3	10403	#define EADC_AD1SPCTL4_CHSEL_Msk (0xful << EADC_AD1SPCTL4_CHSEL_Pos) /!< EADC AD1SPCTL4: CHSEL Mask /
sahilmgandhi	18:6a4db94011d3	10404
sahilmgandhi	18:6a4db94011d3	10405	#define EADC_AD1SPCTL4_TRGSEL_Pos (4) /!< EADC AD1SPCTL4: TRGSEL Position /
sahilmgandhi	18:6a4db94011d3	10406	#define EADC_AD1SPCTL4_TRGSEL_Msk (0x7ul << EADC_AD1SPCTL4_TRGSEL_Pos) /!< EADC AD1SPCTL4: TRGSEL Mask /
sahilmgandhi	18:6a4db94011d3	10407
sahilmgandhi	18:6a4db94011d3	10408	#define EADC_AD1SPCTL4_EXTREN_Pos (20) /!< EADC AD1SPCTL4: EXTREN Position /
sahilmgandhi	18:6a4db94011d3	10409	#define EADC_AD1SPCTL4_EXTREN_Msk (0x1ul << EADC_AD1SPCTL4_EXTREN_Pos) /!< EADC AD1SPCTL4: EXTREN Mask /
sahilmgandhi	18:6a4db94011d3	10410
sahilmgandhi	18:6a4db94011d3	10411	#define EADC_AD1SPCTL4_EXTFEN_Pos (21) /!< EADC AD1SPCTL4: EXTFEN Position /
sahilmgandhi	18:6a4db94011d3	10412	#define EADC_AD1SPCTL4_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL4_EXTFEN_Pos) /!< EADC AD1SPCTL4: EXTFEN Mask /
sahilmgandhi	18:6a4db94011d3	10413
sahilmgandhi	18:6a4db94011d3	10414	#define EADC_AD1SPCTL5_CHSEL_Pos (0) /!< EADC AD1SPCTL5: CHSEL Position /
sahilmgandhi	18:6a4db94011d3	10415	#define EADC_AD1SPCTL5_CHSEL_Msk (0xful << EADC_AD1SPCTL5_CHSEL_Pos) /!< EADC AD1SPCTL5: CHSEL Mask /
sahilmgandhi	18:6a4db94011d3	10416
sahilmgandhi	18:6a4db94011d3	10417	#define EADC_AD1SPCTL5_TRGSEL_Pos (4) /!< EADC AD1SPCTL5: TRGSEL Position /
sahilmgandhi	18:6a4db94011d3	10418	#define EADC_AD1SPCTL5_TRGSEL_Msk (0x7ul << EADC_AD1SPCTL5_TRGSEL_Pos) /!< EADC AD1SPCTL5: TRGSEL Mask /
sahilmgandhi	18:6a4db94011d3	10419
sahilmgandhi	18:6a4db94011d3	10420	#define EADC_AD1SPCTL5_EXTREN_Pos (20) /!< EADC AD1SPCTL5: EXTREN Position /
sahilmgandhi	18:6a4db94011d3	10421	#define EADC_AD1SPCTL5_EXTREN_Msk (0x1ul << EADC_AD1SPCTL5_EXTREN_Pos) /!< EADC AD1SPCTL5: EXTREN Mask /
sahilmgandhi	18:6a4db94011d3	10422
sahilmgandhi	18:6a4db94011d3	10423	#define EADC_AD1SPCTL5_EXTFEN_Pos (21) /!< EADC AD1SPCTL5: EXTFEN Position /
sahilmgandhi	18:6a4db94011d3	10424	#define EADC_AD1SPCTL5_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL5_EXTFEN_Pos) /!< EADC AD1SPCTL5: EXTFEN Mask /
sahilmgandhi	18:6a4db94011d3	10425
sahilmgandhi	18:6a4db94011d3	10426	#define EADC_AD1SPCTL6_CHSEL_Pos (0) /!< EADC AD1SPCTL6: CHSEL Position /
sahilmgandhi	18:6a4db94011d3	10427	#define EADC_AD1SPCTL6_CHSEL_Msk (0xful << EADC_AD1SPCTL6_CHSEL_Pos) /!< EADC AD1SPCTL6: CHSEL Mask /
sahilmgandhi	18:6a4db94011d3	10428
sahilmgandhi	18:6a4db94011d3	10429	#define EADC_AD1SPCTL6_TRGSEL_Pos (4) /!< EADC AD1SPCTL6: TRGSEL Position /
sahilmgandhi	18:6a4db94011d3	10430	#define EADC_AD1SPCTL6_TRGSEL_Msk (0x7ul << EADC_AD1SPCTL6_TRGSEL_Pos) /!< EADC AD1SPCTL6: TRGSEL Mask /
sahilmgandhi	18:6a4db94011d3	10431
sahilmgandhi	18:6a4db94011d3	10432	#define EADC_AD1SPCTL6_EXTREN_Pos (20) /!< EADC AD1SPCTL6: EXTREN Position /
sahilmgandhi	18:6a4db94011d3	10433	#define EADC_AD1SPCTL6_EXTREN_Msk (0x1ul << EADC_AD1SPCTL6_EXTREN_Pos) /!< EADC AD1SPCTL6: EXTREN Mask /
sahilmgandhi	18:6a4db94011d3	10434
sahilmgandhi	18:6a4db94011d3	10435	#define EADC_AD1SPCTL6_EXTFEN_Pos (21) /!< EADC AD1SPCTL6: EXTFEN Position /
sahilmgandhi	18:6a4db94011d3	10436	#define EADC_AD1SPCTL6_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL6_EXTFEN_Pos) /!< EADC AD1SPCTL6: EXTFEN Mask /
sahilmgandhi	18:6a4db94011d3	10437
sahilmgandhi	18:6a4db94011d3	10438	#define EADC_AD1SPCTL7_CHSEL_Pos (0) /!< EADC AD1SPCTL7: CHSEL Position /
sahilmgandhi	18:6a4db94011d3	10439	#define EADC_AD1SPCTL7_CHSEL_Msk (0xful << EADC_AD1SPCTL7_CHSEL_Pos) /!< EADC AD1SPCTL7: CHSEL Mask /
sahilmgandhi	18:6a4db94011d3	10440
sahilmgandhi	18:6a4db94011d3	10441	#define EADC_AD1SPCTL7_TRGSEL_Pos (4) /!< EADC AD1SPCTL7: TRGSEL Position /
sahilmgandhi	18:6a4db94011d3	10442	#define EADC_AD1SPCTL7_TRGSEL_Msk (0x7ul << EADC_AD1SPCTL7_TRGSEL_Pos) /!< EADC AD1SPCTL7: TRGSEL Mask /
sahilmgandhi	18:6a4db94011d3	10443
sahilmgandhi	18:6a4db94011d3	10444	#define EADC_AD1SPCTL7_EXTREN_Pos (20) /!< EADC AD1SPCTL7: EXTREN Position /
sahilmgandhi	18:6a4db94011d3	10445	#define EADC_AD1SPCTL7_EXTREN_Msk (0x1ul << EADC_AD1SPCTL7_EXTREN_Pos) /!< EADC AD1SPCTL7: EXTREN Mask /
sahilmgandhi	18:6a4db94011d3	10446
sahilmgandhi	18:6a4db94011d3	10447	#define EADC_AD1SPCTL7_EXTFEN_Pos (21) /!< EADC AD1SPCTL7: EXTFEN Position /
sahilmgandhi	18:6a4db94011d3	10448	#define EADC_AD1SPCTL7_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL7_EXTFEN_Pos) /!< EADC AD1SPCTL7: EXTFEN Mask /
sahilmgandhi	18:6a4db94011d3	10449
sahilmgandhi	18:6a4db94011d3	10450	#define EADC_SIMUSEL_SIMUSEL0_Pos (0) /!< EADC SIMUSEL: SIMUSEL0 Position /
sahilmgandhi	18:6a4db94011d3	10451	#define EADC_SIMUSEL_SIMUSEL0_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL0_Pos) /!< EADC SIMUSEL: SIMUSEL0 Mask /
sahilmgandhi	18:6a4db94011d3	10452
sahilmgandhi	18:6a4db94011d3	10453	#define EADC_SIMUSEL_SIMUSEL1_Pos (1) /!< EADC SIMUSEL: SIMUSEL1 Position /
sahilmgandhi	18:6a4db94011d3	10454	#define EADC_SIMUSEL_SIMUSEL1_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL1_Pos) /!< EADC SIMUSEL: SIMUSEL1 Mask /
sahilmgandhi	18:6a4db94011d3	10455
sahilmgandhi	18:6a4db94011d3	10456	#define EADC_SIMUSEL_SIMUSEL2_Pos (2) /!< EADC SIMUSEL: SIMUSEL2 Position /
sahilmgandhi	18:6a4db94011d3	10457	#define EADC_SIMUSEL_SIMUSEL2_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL2_Pos) /!< EADC SIMUSEL: SIMUSEL2 Mask /
sahilmgandhi	18:6a4db94011d3	10458
sahilmgandhi	18:6a4db94011d3	10459	#define EADC_SIMUSEL_SIMUSEL3_Pos (3) /!< EADC SIMUSEL: SIMUSEL3 Position /
sahilmgandhi	18:6a4db94011d3	10460	#define EADC_SIMUSEL_SIMUSEL3_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL3_Pos) /!< EADC SIMUSEL: SIMUSEL3 Mask /
sahilmgandhi	18:6a4db94011d3	10461
sahilmgandhi	18:6a4db94011d3	10462	#define EADC_SIMUSEL_SIMUSEL4_Pos (4) /!< EADC SIMUSEL: SIMUSEL4 Position /
sahilmgandhi	18:6a4db94011d3	10463	#define EADC_SIMUSEL_SIMUSEL4_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL4_Pos) /!< EADC SIMUSEL: SIMUSEL4 Mask /
sahilmgandhi	18:6a4db94011d3	10464
sahilmgandhi	18:6a4db94011d3	10465	#define EADC_SIMUSEL_SIMUSEL5_Pos (5) /!< EADC SIMUSEL: SIMUSEL5 Position /
sahilmgandhi	18:6a4db94011d3	10466	#define EADC_SIMUSEL_SIMUSEL5_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL5_Pos) /!< EADC SIMUSEL: SIMUSEL5 Mask /
sahilmgandhi	18:6a4db94011d3	10467
sahilmgandhi	18:6a4db94011d3	10468	#define EADC_SIMUSEL_SIMUSEL6_Pos (6) /!< EADC SIMUSEL: SIMUSEL6 Position /
sahilmgandhi	18:6a4db94011d3	10469	#define EADC_SIMUSEL_SIMUSEL6_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL6_Pos) /!< EADC SIMUSEL: SIMUSEL6 Mask /
sahilmgandhi	18:6a4db94011d3	10470
sahilmgandhi	18:6a4db94011d3	10471	#define EADC_SIMUSEL_SIMUSEL7_Pos (7) /!< EADC SIMUSEL: SIMUSEL7 Position /
sahilmgandhi	18:6a4db94011d3	10472	#define EADC_SIMUSEL_SIMUSEL7_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL7_Pos) /!< EADC SIMUSEL: SIMUSEL7 Mask /
sahilmgandhi	18:6a4db94011d3	10473
sahilmgandhi	18:6a4db94011d3	10474	#define EADC_CMP0_ADCMPEN_Pos (0) /!< EADC CMP0: ADCMPEN Position /
sahilmgandhi	18:6a4db94011d3	10475	#define EADC_CMP0_ADCMPEN_Msk (0x1ul << EADC_CMP0_ADCMPEN_Pos) /!< EADC CMP0: ADCMPEN Mask /
sahilmgandhi	18:6a4db94011d3	10476
sahilmgandhi	18:6a4db94011d3	10477	#define EADC_CMP0_ADCMPIE_Pos (1) /!< EADC CMP0: ADCMPIE Position /
sahilmgandhi	18:6a4db94011d3	10478	#define EADC_CMP0_ADCMPIE_Msk (0x1ul << EADC_CMP0_ADCMPIE_Pos) /!< EADC CMP0: ADCMPIE Mask /
sahilmgandhi	18:6a4db94011d3	10479
sahilmgandhi	18:6a4db94011d3	10480	#define EADC_CMP0_CMPCOND_Pos (2) /!< EADC CMP0: CMPCOND Position /
sahilmgandhi	18:6a4db94011d3	10481	#define EADC_CMP0_CMPCOND_Msk (0x1ul << EADC_CMP0_CMPCOND_Pos) /!< EADC CMP0: CMPCOND Mask /
sahilmgandhi	18:6a4db94011d3	10482
sahilmgandhi	18:6a4db94011d3	10483	#define EADC_CMP0_CMPSPL_Pos (3) /!< EADC CMP0: CMPSPL Position /
sahilmgandhi	18:6a4db94011d3	10484	#define EADC_CMP0_CMPSPL_Msk (0x7ul << EADC_CMP0_CMPSPL_Pos) /!< EADC CMP0: CMPSPL Mask /
sahilmgandhi	18:6a4db94011d3	10485
sahilmgandhi	18:6a4db94011d3	10486	#define EADC_CMP0_CMPMCNT_Pos (8) /!< EADC CMP0: CMPMCNT Position /
sahilmgandhi	18:6a4db94011d3	10487	#define EADC_CMP0_CMPMCNT_Msk (0xful << EADC_CMP0_CMPMCNT_Pos) /!< EADC CMP0: CMPMCNT Mask /
sahilmgandhi	18:6a4db94011d3	10488
sahilmgandhi	18:6a4db94011d3	10489	#define EADC_CMP0_CMPDAT_Pos (16) /!< EADC CMP0: CMPDAT Position /
sahilmgandhi	18:6a4db94011d3	10490	#define EADC_CMP0_CMPDAT_Msk (0xffful << EADC_CMP0_CMPDAT_Pos) /!< EADC CMP0: CMPDAT Mask /
sahilmgandhi	18:6a4db94011d3	10491
sahilmgandhi	18:6a4db94011d3	10492	#define EADC_CMP1_ADCMPEN_Pos (0) /!< EADC CMP1: ADCMPEN Position /
sahilmgandhi	18:6a4db94011d3	10493	#define EADC_CMP1_ADCMPEN_Msk (0x1ul << EADC_CMP1_ADCMPEN_Pos) /!< EADC CMP1: ADCMPEN Mask /
sahilmgandhi	18:6a4db94011d3	10494
sahilmgandhi	18:6a4db94011d3	10495	#define EADC_CMP1_ADCMPIE_Pos (1) /!< EADC CMP1: ADCMPIE Position /
sahilmgandhi	18:6a4db94011d3	10496	#define EADC_CMP1_ADCMPIE_Msk (0x1ul << EADC_CMP1_ADCMPIE_Pos) /!< EADC CMP1: ADCMPIE Mask /
sahilmgandhi	18:6a4db94011d3	10497
sahilmgandhi	18:6a4db94011d3	10498	#define EADC_CMP1_CMPCOND_Pos (2) /!< EADC CMP1: CMPCOND Position /
sahilmgandhi	18:6a4db94011d3	10499	#define EADC_CMP1_CMPCOND_Msk (0x1ul << EADC_CMP1_CMPCOND_Pos) /!< EADC CMP1: CMPCOND Mask /
sahilmgandhi	18:6a4db94011d3	10500
sahilmgandhi	18:6a4db94011d3	10501	#define EADC_CMP1_CMPSPL_Pos (3) /!< EADC CMP1: CMPSPL Position /
sahilmgandhi	18:6a4db94011d3	10502	#define EADC_CMP1_CMPSPL_Msk (0x7ul << EADC_CMP1_CMPSPL_Pos) /!< EADC CMP1: CMPSPL Mask /
sahilmgandhi	18:6a4db94011d3	10503
sahilmgandhi	18:6a4db94011d3	10504	#define EADC_CMP1_CMPMCNT_Pos (8) /!< EADC CMP1: CMPMCNT Position /
sahilmgandhi	18:6a4db94011d3	10505	#define EADC_CMP1_CMPMCNT_Msk (0xful << EADC_CMP1_CMPMCNT_Pos) /!< EADC CMP1: CMPMCNT Mask /
sahilmgandhi	18:6a4db94011d3	10506
sahilmgandhi	18:6a4db94011d3	10507	#define EADC_CMP1_CMPDAT_Pos (16) /!< EADC CMP1: CMPDAT Position /
sahilmgandhi	18:6a4db94011d3	10508	#define EADC_CMP1_CMPDAT_Msk (0xffful << EADC_CMP1_CMPDAT_Pos) /!< EADC CMP1: CMPDAT Mask /
sahilmgandhi	18:6a4db94011d3	10509
sahilmgandhi	18:6a4db94011d3	10510	#define EADC_STATUS0_VALID_Pos (0) /!< EADC STATUS0: VALID Position /
sahilmgandhi	18:6a4db94011d3	10511	#define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) /!< EADC STATUS0: VALID Mask /
sahilmgandhi	18:6a4db94011d3	10512
sahilmgandhi	18:6a4db94011d3	10513	#define EADC_STATUS0_OV_Pos (16) /!< EADC STATUS0: OV Position /
sahilmgandhi	18:6a4db94011d3	10514	#define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) /!< EADC STATUS0: OV Mask /
sahilmgandhi	18:6a4db94011d3	10515
sahilmgandhi	18:6a4db94011d3	10516	#define EADC_STATUS1_ADIF0_Pos (0) /!< EADC STATUS1: ADIF0 Position /
sahilmgandhi	18:6a4db94011d3	10517	#define EADC_STATUS1_ADIF0_Msk (0x1ul << EADC_STATUS1_ADIF0_Pos) /!< EADC STATUS1: ADIF0 Mask /
sahilmgandhi	18:6a4db94011d3	10518
sahilmgandhi	18:6a4db94011d3	10519	#define EADC_STATUS1_ADIF1_Pos (1) /!< EADC STATUS1: ADIF1 Position /
sahilmgandhi	18:6a4db94011d3	10520	#define EADC_STATUS1_ADIF1_Msk (0x1ul << EADC_STATUS1_ADIF1_Pos) /!< EADC STATUS1: ADIF1 Mask /
sahilmgandhi	18:6a4db94011d3	10521
sahilmgandhi	18:6a4db94011d3	10522	#define EADC_STATUS1_ADIF2_Pos (2) /!< EADC STATUS1: ADIF2 Position /
sahilmgandhi	18:6a4db94011d3	10523	#define EADC_STATUS1_ADIF2_Msk (0x1ul << EADC_STATUS1_ADIF2_Pos) /!< EADC STATUS1: ADIF2 Mask /
sahilmgandhi	18:6a4db94011d3	10524
sahilmgandhi	18:6a4db94011d3	10525	#define EADC_STATUS1_ADIF3_Pos (3) /!< EADC STATUS1: ADIF3 Position /
sahilmgandhi	18:6a4db94011d3	10526	#define EADC_STATUS1_ADIF3_Msk (0x1ul << EADC_STATUS1_ADIF3_Pos) /!< EADC STATUS1: ADIF3 Mask /
sahilmgandhi	18:6a4db94011d3	10527
sahilmgandhi	18:6a4db94011d3	10528	#define EADC_STATUS1_ADCMPO0_Pos (4) /!< EADC STATUS1: ADCMPO0 Position /
sahilmgandhi	18:6a4db94011d3	10529	#define EADC_STATUS1_ADCMPO0_Msk (0x1ul << EADC_STATUS1_ADCMPO0_Pos) /!< EADC STATUS1: ADCMPO0 Mask /
sahilmgandhi	18:6a4db94011d3	10530
sahilmgandhi	18:6a4db94011d3	10531	#define EADC_STATUS1_ADCMPO1_Pos (5) /!< EADC STATUS1: ADCMPO1 Position /
sahilmgandhi	18:6a4db94011d3	10532	#define EADC_STATUS1_ADCMPO1_Msk (0x1ul << EADC_STATUS1_ADCMPO1_Pos) /!< EADC STATUS1: ADCMPO1 Mask /
sahilmgandhi	18:6a4db94011d3	10533
sahilmgandhi	18:6a4db94011d3	10534	#define EADC_STATUS1_ADCMPF0_Pos (6) /!< EADC STATUS1: ADCMPF0 Position /
sahilmgandhi	18:6a4db94011d3	10535	#define EADC_STATUS1_ADCMPF0_Msk (0x1ul << EADC_STATUS1_ADCMPF0_Pos) /!< EADC STATUS1: ADCMPF0 Mask /
sahilmgandhi	18:6a4db94011d3	10536
sahilmgandhi	18:6a4db94011d3	10537	#define EADC_STATUS1_ADCMPF1_Pos (7) /!< EADC STATUS1: ADCMPF1 Position /
sahilmgandhi	18:6a4db94011d3	10538	#define EADC_STATUS1_ADCMPF1_Msk (0x1ul << EADC_STATUS1_ADCMPF1_Pos) /!< EADC STATUS1: ADCMPF1 Mask /
sahilmgandhi	18:6a4db94011d3	10539
sahilmgandhi	18:6a4db94011d3	10540	#define EADC_STATUS1_BUSY0_Pos (8) /!< EADC STATUS1: BUSY0 Position /
sahilmgandhi	18:6a4db94011d3	10541	#define EADC_STATUS1_BUSY0_Msk (0x1ul << EADC_STATUS1_BUSY0_Pos) /!< EADC STATUS1: BUSY0 Mask /
sahilmgandhi	18:6a4db94011d3	10542
sahilmgandhi	18:6a4db94011d3	10543	#define EADC_STATUS1_CHANNEL0_Pos (12) /!< EADC STATUS1: CHANNEL0 Position /
sahilmgandhi	18:6a4db94011d3	10544	#define EADC_STATUS1_CHANNEL0_Msk (0xful << EADC_STATUS1_CHANNEL0_Pos) /!< EADC STATUS1: CHANNEL0 Mask /
sahilmgandhi	18:6a4db94011d3	10545
sahilmgandhi	18:6a4db94011d3	10546	#define EADC_STATUS1_BUSY1_Pos (16) /!< EADC STATUS1: BUSY1 Position /
sahilmgandhi	18:6a4db94011d3	10547	#define EADC_STATUS1_BUSY1_Msk (0x1ul << EADC_STATUS1_BUSY1_Pos) /!< EADC STATUS1: BUSY1 Mask /
sahilmgandhi	18:6a4db94011d3	10548
sahilmgandhi	18:6a4db94011d3	10549	#define EADC_STATUS1_CHANNEL1_Pos (20) /!< EADC STATUS1: CHANNEL1 Position /
sahilmgandhi	18:6a4db94011d3	10550	#define EADC_STATUS1_CHANNEL1_Msk (0xful << EADC_STATUS1_CHANNEL1_Pos) /!< EADC STATUS1: CHANNEL1 Mask /
sahilmgandhi	18:6a4db94011d3	10551
sahilmgandhi	18:6a4db94011d3	10552	#define EADC_STATUS1_ADOVIF_Pos (24) /!< EADC STATUS1: ADOVIF Position /
sahilmgandhi	18:6a4db94011d3	10553	#define EADC_STATUS1_ADOVIF_Msk (0x1ul << EADC_STATUS1_ADOVIF_Pos) /!< EADC STATUS1: ADOVIF Mask /
sahilmgandhi	18:6a4db94011d3	10554
sahilmgandhi	18:6a4db94011d3	10555	#define EADC_STATUS1_STOVF_Pos (25) /!< EADC STATUS1: STOVF Position /
sahilmgandhi	18:6a4db94011d3	10556	#define EADC_STATUS1_STOVF_Msk (0x1ul << EADC_STATUS1_STOVF_Pos) /!< EADC STATUS1: STOVF Mask /
sahilmgandhi	18:6a4db94011d3	10557
sahilmgandhi	18:6a4db94011d3	10558	#define EADC_STATUS1_AVALID_Pos (26) /!< EADC STATUS1: AVALID Position /
sahilmgandhi	18:6a4db94011d3	10559	#define EADC_STATUS1_AVALID_Msk (0x1ul << EADC_STATUS1_AVALID_Pos) /!< EADC STATUS1: AVALID Mask /
sahilmgandhi	18:6a4db94011d3	10560
sahilmgandhi	18:6a4db94011d3	10561	#define EADC_STATUS1_AOV_Pos (27) /!< EADC STATUS1: AOV Position /
sahilmgandhi	18:6a4db94011d3	10562	#define EADC_STATUS1_AOV_Msk (0x1ul << EADC_STATUS1_AOV_Pos) /!< EADC STATUS1: AOV Mask /
sahilmgandhi	18:6a4db94011d3	10563
sahilmgandhi	18:6a4db94011d3	10564	#define EADC_EXTSMPT_EXTSMPT0_Pos (0) /!< EADC EXTSMPT: EXTSMPT0 Position /
sahilmgandhi	18:6a4db94011d3	10565	#define EADC_EXTSMPT_EXTSMPT0_Msk (0xfful << EADC_EXTSMPT_EXTSMPT0_Pos) /!< EADC EXTSMPT: EXTSMPT0 Mask /
sahilmgandhi	18:6a4db94011d3	10566
sahilmgandhi	18:6a4db94011d3	10567	#define EADC_EXTSMPT_EXTSMPT1_Pos (16) /!< EADC EXTSMPT: EXTSMPT1 Position /
sahilmgandhi	18:6a4db94011d3	10568	#define EADC_EXTSMPT_EXTSMPT1_Msk (0xfful << EADC_EXTSMPT_EXTSMPT1_Pos) /!< EADC EXTSMPT: EXTSMPT1 Mask /
sahilmgandhi	18:6a4db94011d3	10569
sahilmgandhi	18:6a4db94011d3	10570	#define EADC_AD0DDAT0_RESULT_Pos (0) /!< EADC AD0DDAT0: RESULT Position /
sahilmgandhi	18:6a4db94011d3	10571	#define EADC_AD0DDAT0_RESULT_Msk (0xffful << EADC_AD0DDAT0_RESULT_Pos) /!< EADC AD0DDAT0: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	10572
sahilmgandhi	18:6a4db94011d3	10573	#define EADC_AD0DDAT0_VALID_Pos (16) /!< EADC AD0DDAT0: VALID Position /
sahilmgandhi	18:6a4db94011d3	10574	#define EADC_AD0DDAT0_VALID_Msk (0x1ul << EADC_AD0DDAT0_VALID_Pos) /!< EADC AD0DDAT0: VALID Mask /
sahilmgandhi	18:6a4db94011d3	10575
sahilmgandhi	18:6a4db94011d3	10576	#define EADC_AD0DDAT1_RESULT_Pos (0) /!< EADC AD0DDAT1: RESULT Position /
sahilmgandhi	18:6a4db94011d3	10577	#define EADC_AD0DDAT1_RESULT_Msk (0xffful << EADC_AD0DDAT1_RESULT_Pos) /!< EADC AD0DDAT1: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	10578
sahilmgandhi	18:6a4db94011d3	10579	#define EADC_AD0DDAT1_VALID_Pos (16) /!< EADC AD0DDAT1: VALID Position /
sahilmgandhi	18:6a4db94011d3	10580	#define EADC_AD0DDAT1_VALID_Msk (0x1ul << EADC_AD0DDAT1_VALID_Pos) /!< EADC AD0DDAT1: VALID Mask /
sahilmgandhi	18:6a4db94011d3	10581
sahilmgandhi	18:6a4db94011d3	10582	#define EADC_AD0DDAT2_RESULT_Pos (0) /!< EADC AD0DDAT2: RESULT Position /
sahilmgandhi	18:6a4db94011d3	10583	#define EADC_AD0DDAT2_RESULT_Msk (0xffful << EADC_AD0DDAT2_RESULT_Pos) /!< EADC AD0DDAT2: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	10584
sahilmgandhi	18:6a4db94011d3	10585	#define EADC_AD0DDAT2_VALID_Pos (16) /!< EADC AD0DDAT2: VALID Position /
sahilmgandhi	18:6a4db94011d3	10586	#define EADC_AD0DDAT2_VALID_Msk (0x1ul << EADC_AD0DDAT2_VALID_Pos) /!< EADC AD0DDAT2: VALID Mask /
sahilmgandhi	18:6a4db94011d3	10587
sahilmgandhi	18:6a4db94011d3	10588	#define EADC_AD0DDAT3_RESULT_Pos (0) /!< EADC AD0DDAT3: RESULT Position /
sahilmgandhi	18:6a4db94011d3	10589	#define EADC_AD0DDAT3_RESULT_Msk (0xffful << EADC_AD0DDAT3_RESULT_Pos) /!< EADC AD0DDAT3: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	10590
sahilmgandhi	18:6a4db94011d3	10591	#define EADC_AD0DDAT3_VALID_Pos (16) /!< EADC AD0DDAT3: VALID Position /
sahilmgandhi	18:6a4db94011d3	10592	#define EADC_AD0DDAT3_VALID_Msk (0x1ul << EADC_AD0DDAT3_VALID_Pos) /!< EADC AD0DDAT3: VALID Mask /
sahilmgandhi	18:6a4db94011d3	10593
sahilmgandhi	18:6a4db94011d3	10594	#define EADC_AD1DDAT0_RESULT_Pos (0) /!< EADC AD1DDAT0: RESULT Position /
sahilmgandhi	18:6a4db94011d3	10595	#define EADC_AD1DDAT0_RESULT_Msk (0xffful << EADC_AD1DDAT0_RESULT_Pos) /!< EADC AD1DDAT0: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	10596
sahilmgandhi	18:6a4db94011d3	10597	#define EADC_AD1DDAT0_VALID_Pos (16) /!< EADC AD1DDAT0: VALID Position /
sahilmgandhi	18:6a4db94011d3	10598	#define EADC_AD1DDAT0_VALID_Msk (0x1ul << EADC_AD1DDAT0_VALID_Pos) /!< EADC AD1DDAT0: VALID Mask /
sahilmgandhi	18:6a4db94011d3	10599
sahilmgandhi	18:6a4db94011d3	10600	#define EADC_AD1DDAT1_RESULT_Pos (0) /!< EADC AD1DDAT1: RESULT Position /
sahilmgandhi	18:6a4db94011d3	10601	#define EADC_AD1DDAT1_RESULT_Msk (0xffful << EADC_AD1DDAT1_RESULT_Pos) /!< EADC AD1DDAT1: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	10602
sahilmgandhi	18:6a4db94011d3	10603	#define EADC_AD1DDAT1_VALID_Pos (16) /!< EADC AD1DDAT1: VALID Position /
sahilmgandhi	18:6a4db94011d3	10604	#define EADC_AD1DDAT1_VALID_Msk (0x1ul << EADC_AD1DDAT1_VALID_Pos) /!< EADC AD1DDAT1: VALID Mask /
sahilmgandhi	18:6a4db94011d3	10605
sahilmgandhi	18:6a4db94011d3	10606	#define EADC_AD1DDAT2_RESULT_Pos (0) /!< EADC AD1DDAT2: RESULT Position /
sahilmgandhi	18:6a4db94011d3	10607	#define EADC_AD1DDAT2_RESULT_Msk (0xffful << EADC_AD1DDAT2_RESULT_Pos) /!< EADC AD1DDAT2: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	10608
sahilmgandhi	18:6a4db94011d3	10609	#define EADC_AD1DDAT2_VALID_Pos (16) /!< EADC AD1DDAT2: VALID Position /
sahilmgandhi	18:6a4db94011d3	10610	#define EADC_AD1DDAT2_VALID_Msk (0x1ul << EADC_AD1DDAT2_VALID_Pos) /!< EADC AD1DDAT2: VALID Mask /
sahilmgandhi	18:6a4db94011d3	10611
sahilmgandhi	18:6a4db94011d3	10612	#define EADC_AD1DDAT3_RESULT_Pos (0) /!< EADC AD1DDAT3: RESULT Position /
sahilmgandhi	18:6a4db94011d3	10613	#define EADC_AD1DDAT3_RESULT_Msk (0xffful << EADC_AD1DDAT3_RESULT_Pos) /!< EADC AD1DDAT3: RESULT Mask /
sahilmgandhi	18:6a4db94011d3	10614
sahilmgandhi	18:6a4db94011d3	10615	#define EADC_AD1DDAT3_VALID_Pos (16) /!< EADC AD1DDAT3: VALID Position /
sahilmgandhi	18:6a4db94011d3	10616	#define EADC_AD1DDAT3_VALID_Msk (0x1ul << EADC_AD1DDAT3_VALID_Pos) /!< EADC AD1DDAT3: VALID Mask /
sahilmgandhi	18:6a4db94011d3	10617
sahilmgandhi	18:6a4db94011d3	10618	#define EADC_DBMEN_AD0DBM0_Pos (0) /!< EADC DBMEN: AD0DBM0 Position /
sahilmgandhi	18:6a4db94011d3	10619	#define EADC_DBMEN_AD0DBM0_Msk (0x1ul << EADC_DBMEN_AD0DBM0_Pos) /!< EADC DBMEN: AD0DBM0 Mask /
sahilmgandhi	18:6a4db94011d3	10620
sahilmgandhi	18:6a4db94011d3	10621	#define EADC_DBMEN_AD0DBM1_Pos (1) /!< EADC DBMEN: AD0DBM1 Position /
sahilmgandhi	18:6a4db94011d3	10622	#define EADC_DBMEN_AD0DBM1_Msk (0x1ul << EADC_DBMEN_AD0DBM1_Pos) /!< EADC DBMEN: AD0DBM1 Mask /
sahilmgandhi	18:6a4db94011d3	10623
sahilmgandhi	18:6a4db94011d3	10624	#define EADC_DBMEN_AD0DBM2_Pos (2) /!< EADC DBMEN: AD0DBM2 Position /
sahilmgandhi	18:6a4db94011d3	10625	#define EADC_DBMEN_AD0DBM2_Msk (0x1ul << EADC_DBMEN_AD0DBM2_Pos) /!< EADC DBMEN: AD0DBM2 Mask /
sahilmgandhi	18:6a4db94011d3	10626
sahilmgandhi	18:6a4db94011d3	10627	#define EADC_DBMEN_AD0DBM3_Pos (3) /!< EADC DBMEN: AD0DBM3 Position /
sahilmgandhi	18:6a4db94011d3	10628	#define EADC_DBMEN_AD0DBM3_Msk (0x1ul << EADC_DBMEN_AD0DBM3_Pos) /!< EADC DBMEN: AD0DBM3 Mask /
sahilmgandhi	18:6a4db94011d3	10629
sahilmgandhi	18:6a4db94011d3	10630	#define EADC_DBMEN_AD1DBM0_Pos (8) /!< EADC DBMEN: AD1DBM0 Position /
sahilmgandhi	18:6a4db94011d3	10631	#define EADC_DBMEN_AD1DBM0_Msk (0x1ul << EADC_DBMEN_AD1DBM0_Pos) /!< EADC DBMEN: AD1DBM0 Mask /
sahilmgandhi	18:6a4db94011d3	10632
sahilmgandhi	18:6a4db94011d3	10633	#define EADC_DBMEN_AD1DBM1_Pos (9) /!< EADC DBMEN: AD1DBM1 Position /
sahilmgandhi	18:6a4db94011d3	10634	#define EADC_DBMEN_AD1DBM1_Msk (0x1ul << EADC_DBMEN_AD1DBM1_Pos) /!< EADC DBMEN: AD1DBM1 Mask /
sahilmgandhi	18:6a4db94011d3	10635
sahilmgandhi	18:6a4db94011d3	10636	#define EADC_DBMEN_AD1DBM2_Pos (10) /!< EADC DBMEN: AD1DBM2 Position /
sahilmgandhi	18:6a4db94011d3	10637	#define EADC_DBMEN_AD1DBM2_Msk (0x1ul << EADC_DBMEN_AD1DBM2_Pos) /!< EADC DBMEN: AD1DBM2 Mask /
sahilmgandhi	18:6a4db94011d3	10638
sahilmgandhi	18:6a4db94011d3	10639	#define EADC_DBMEN_AD1DBM3_Pos (11) /!< EADC DBMEN: AD1DBM3 Position /
sahilmgandhi	18:6a4db94011d3	10640	#define EADC_DBMEN_AD1DBM3_Msk (0x1ul << EADC_DBMEN_AD1DBM3_Pos) /!< EADC DBMEN: AD1DBM3 Mask /
sahilmgandhi	18:6a4db94011d3	10641
sahilmgandhi	18:6a4db94011d3	10642	#define EADC_INTSRC0_AD0SPIE0_Pos (0) /!< EADC INTSRC0: AD0SPIE0 Position /
sahilmgandhi	18:6a4db94011d3	10643	#define EADC_INTSRC0_AD0SPIE0_Msk (0x1ul << EADC_INTSRC0_AD0SPIE0_Pos) /!< EADC INTSRC0: AD0SPIE0 Mask /
sahilmgandhi	18:6a4db94011d3	10644
sahilmgandhi	18:6a4db94011d3	10645	#define EADC_INTSRC0_AD0SPIE1_Pos (1) /!< EADC INTSRC0: AD0SPIE1 Position /
sahilmgandhi	18:6a4db94011d3	10646	#define EADC_INTSRC0_AD0SPIE1_Msk (0x1ul << EADC_INTSRC0_AD0SPIE1_Pos) /!< EADC INTSRC0: AD0SPIE1 Mask /
sahilmgandhi	18:6a4db94011d3	10647
sahilmgandhi	18:6a4db94011d3	10648	#define EADC_INTSRC0_AD0SPIE2_Pos (2) /!< EADC INTSRC0: AD0SPIE2 Position /
sahilmgandhi	18:6a4db94011d3	10649	#define EADC_INTSRC0_AD0SPIE2_Msk (0x1ul << EADC_INTSRC0_AD0SPIE2_Pos) /!< EADC INTSRC0: AD0SPIE2 Mask /
sahilmgandhi	18:6a4db94011d3	10650
sahilmgandhi	18:6a4db94011d3	10651	#define EADC_INTSRC0_AD0SPIE3_Pos (3) /!< EADC INTSRC0: AD0SPIE3 Position /
sahilmgandhi	18:6a4db94011d3	10652	#define EADC_INTSRC0_AD0SPIE3_Msk (0x1ul << EADC_INTSRC0_AD0SPIE3_Pos) /!< EADC INTSRC0: AD0SPIE3 Mask /
sahilmgandhi	18:6a4db94011d3	10653
sahilmgandhi	18:6a4db94011d3	10654	#define EADC_INTSRC0_AD0SPIE4_Pos (4) /!< EADC INTSRC0: AD0SPIE4 Position /
sahilmgandhi	18:6a4db94011d3	10655	#define EADC_INTSRC0_AD0SPIE4_Msk (0x1ul << EADC_INTSRC0_AD0SPIE4_Pos) /!< EADC INTSRC0: AD0SPIE4 Mask /
sahilmgandhi	18:6a4db94011d3	10656
sahilmgandhi	18:6a4db94011d3	10657	#define EADC_INTSRC0_AD0SPIE5_Pos (5) /!< EADC INTSRC0: AD0SPIE5 Position /
sahilmgandhi	18:6a4db94011d3	10658	#define EADC_INTSRC0_AD0SPIE5_Msk (0x1ul << EADC_INTSRC0_AD0SPIE5_Pos) /!< EADC INTSRC0: AD0SPIE5 Mask /
sahilmgandhi	18:6a4db94011d3	10659
sahilmgandhi	18:6a4db94011d3	10660	#define EADC_INTSRC0_AD0SPIE6_Pos (6) /!< EADC INTSRC0: AD0SPIE6 Position /
sahilmgandhi	18:6a4db94011d3	10661	#define EADC_INTSRC0_AD0SPIE6_Msk (0x1ul << EADC_INTSRC0_AD0SPIE6_Pos) /!< EADC INTSRC0: AD0SPIE6 Mask /
sahilmgandhi	18:6a4db94011d3	10662
sahilmgandhi	18:6a4db94011d3	10663	#define EADC_INTSRC0_AD0SPIE7_Pos (7) /!< EADC INTSRC0: AD0SPIE7 Position /
sahilmgandhi	18:6a4db94011d3	10664	#define EADC_INTSRC0_AD0SPIE7_Msk (0x1ul << EADC_INTSRC0_AD0SPIE7_Pos) /!< EADC INTSRC0: AD0SPIE7 Mask /
sahilmgandhi	18:6a4db94011d3	10665
sahilmgandhi	18:6a4db94011d3	10666	#define EADC_INTSRC0_AD1SPIE0_Pos (8) /!< EADC INTSRC0: AD1SPIE0 Position /
sahilmgandhi	18:6a4db94011d3	10667	#define EADC_INTSRC0_AD1SPIE0_Msk (0x1ul << EADC_INTSRC0_AD1SPIE0_Pos) /!< EADC INTSRC0: AD1SPIE0 Mask /
sahilmgandhi	18:6a4db94011d3	10668
sahilmgandhi	18:6a4db94011d3	10669	#define EADC_INTSRC0_AD1SPIE1_Pos (9) /!< EADC INTSRC0: AD1SPIE1 Position /
sahilmgandhi	18:6a4db94011d3	10670	#define EADC_INTSRC0_AD1SPIE1_Msk (0x1ul << EADC_INTSRC0_AD1SPIE1_Pos) /!< EADC INTSRC0: AD1SPIE1 Mask /
sahilmgandhi	18:6a4db94011d3	10671
sahilmgandhi	18:6a4db94011d3	10672	#define EADC_INTSRC0_AD1SPIE2_Pos (10) /!< EADC INTSRC0: AD1SPIE2 Position /
sahilmgandhi	18:6a4db94011d3	10673	#define EADC_INTSRC0_AD1SPIE2_Msk (0x1ul << EADC_INTSRC0_AD1SPIE2_Pos) /!< EADC INTSRC0: AD1SPIE2 Mask /
sahilmgandhi	18:6a4db94011d3	10674
sahilmgandhi	18:6a4db94011d3	10675	#define EADC_INTSRC0_AD1SPIE3_Pos (11) /!< EADC INTSRC0: AD1SPIE3 Position /
sahilmgandhi	18:6a4db94011d3	10676	#define EADC_INTSRC0_AD1SPIE3_Msk (0x1ul << EADC_INTSRC0_AD1SPIE3_Pos) /!< EADC INTSRC0: AD1SPIE3 Mask /
sahilmgandhi	18:6a4db94011d3	10677
sahilmgandhi	18:6a4db94011d3	10678	#define EADC_INTSRC0_AD1SPIE4_Pos (12) /!< EADC INTSRC0: AD1SPIE4 Position /
sahilmgandhi	18:6a4db94011d3	10679	#define EADC_INTSRC0_AD1SPIE4_Msk (0x1ul << EADC_INTSRC0_AD1SPIE4_Pos) /!< EADC INTSRC0: AD1SPIE4 Mask /
sahilmgandhi	18:6a4db94011d3	10680
sahilmgandhi	18:6a4db94011d3	10681	#define EADC_INTSRC0_AD1SPIE5_Pos (13) /!< EADC INTSRC0: AD1SPIE5 Position /
sahilmgandhi	18:6a4db94011d3	10682	#define EADC_INTSRC0_AD1SPIE5_Msk (0x1ul << EADC_INTSRC0_AD1SPIE5_Pos) /!< EADC INTSRC0: AD1SPIE5 Mask /
sahilmgandhi	18:6a4db94011d3	10683
sahilmgandhi	18:6a4db94011d3	10684	#define EADC_INTSRC0_AD1SPIE6_Pos (14) /!< EADC INTSRC0: AD1SPIE6 Position /
sahilmgandhi	18:6a4db94011d3	10685	#define EADC_INTSRC0_AD1SPIE6_Msk (0x1ul << EADC_INTSRC0_AD1SPIE6_Pos) /!< EADC INTSRC0: AD1SPIE6 Mask /
sahilmgandhi	18:6a4db94011d3	10686
sahilmgandhi	18:6a4db94011d3	10687	#define EADC_INTSRC0_AD1SPIE7_Pos (15) /!< EADC INTSRC0: AD1SPIE7 Position /
sahilmgandhi	18:6a4db94011d3	10688	#define EADC_INTSRC0_AD1SPIE7_Msk (0x1ul << EADC_INTSRC0_AD1SPIE7_Pos) /!< EADC INTSRC0: AD1SPIE7 Mask /
sahilmgandhi	18:6a4db94011d3	10689
sahilmgandhi	18:6a4db94011d3	10690	#define EADC_INTSRC1_AD0SPIE0_Pos (0) /!< EADC INTSRC1: AD0SPIE0 Position /
sahilmgandhi	18:6a4db94011d3	10691	#define EADC_INTSRC1_AD0SPIE0_Msk (0x1ul << EADC_INTSRC1_AD0SPIE0_Pos) /!< EADC INTSRC1: AD0SPIE0 Mask /
sahilmgandhi	18:6a4db94011d3	10692
sahilmgandhi	18:6a4db94011d3	10693	#define EADC_INTSRC1_AD0SPIE1_Pos (1) /!< EADC INTSRC1: AD0SPIE1 Position /
sahilmgandhi	18:6a4db94011d3	10694	#define EADC_INTSRC1_AD0SPIE1_Msk (0x1ul << EADC_INTSRC1_AD0SPIE1_Pos) /!< EADC INTSRC1: AD0SPIE1 Mask /
sahilmgandhi	18:6a4db94011d3	10695
sahilmgandhi	18:6a4db94011d3	10696	#define EADC_INTSRC1_AD0SPIE2_Pos (2) /!< EADC INTSRC1: AD0SPIE2 Position /
sahilmgandhi	18:6a4db94011d3	10697	#define EADC_INTSRC1_AD0SPIE2_Msk (0x1ul << EADC_INTSRC1_AD0SPIE2_Pos) /!< EADC INTSRC1: AD0SPIE2 Mask /
sahilmgandhi	18:6a4db94011d3	10698
sahilmgandhi	18:6a4db94011d3	10699	#define EADC_INTSRC1_AD0SPIE3_Pos (3) /!< EADC INTSRC1: AD0SPIE3 Position /
sahilmgandhi	18:6a4db94011d3	10700	#define EADC_INTSRC1_AD0SPIE3_Msk (0x1ul << EADC_INTSRC1_AD0SPIE3_Pos) /!< EADC INTSRC1: AD0SPIE3 Mask /
sahilmgandhi	18:6a4db94011d3	10701
sahilmgandhi	18:6a4db94011d3	10702	#define EADC_INTSRC1_AD0SPIE4_Pos (4) /!< EADC INTSRC1: AD0SPIE4 Position /
sahilmgandhi	18:6a4db94011d3	10703	#define EADC_INTSRC1_AD0SPIE4_Msk (0x1ul << EADC_INTSRC1_AD0SPIE4_Pos) /!< EADC INTSRC1: AD0SPIE4 Mask /
sahilmgandhi	18:6a4db94011d3	10704
sahilmgandhi	18:6a4db94011d3	10705	#define EADC_INTSRC1_AD0SPIE5_Pos (5) /!< EADC INTSRC1: AD0SPIE5 Position /
sahilmgandhi	18:6a4db94011d3	10706	#define EADC_INTSRC1_AD0SPIE5_Msk (0x1ul << EADC_INTSRC1_AD0SPIE5_Pos) /!< EADC INTSRC1: AD0SPIE5 Mask /
sahilmgandhi	18:6a4db94011d3	10707
sahilmgandhi	18:6a4db94011d3	10708	#define EADC_INTSRC1_AD0SPIE6_Pos (6) /!< EADC INTSRC1: AD0SPIE6 Position /
sahilmgandhi	18:6a4db94011d3	10709	#define EADC_INTSRC1_AD0SPIE6_Msk (0x1ul << EADC_INTSRC1_AD0SPIE6_Pos) /!< EADC INTSRC1: AD0SPIE6 Mask /
sahilmgandhi	18:6a4db94011d3	10710
sahilmgandhi	18:6a4db94011d3	10711	#define EADC_INTSRC1_AD0SPIE7_Pos (7) /!< EADC INTSRC1: AD0SPIE7 Position /
sahilmgandhi	18:6a4db94011d3	10712	#define EADC_INTSRC1_AD0SPIE7_Msk (0x1ul << EADC_INTSRC1_AD0SPIE7_Pos) /!< EADC INTSRC1: AD0SPIE7 Mask /
sahilmgandhi	18:6a4db94011d3	10713
sahilmgandhi	18:6a4db94011d3	10714	#define EADC_INTSRC1_AD1SPIE0_Pos (8) /!< EADC INTSRC1: AD1SPIE0 Position /
sahilmgandhi	18:6a4db94011d3	10715	#define EADC_INTSRC1_AD1SPIE0_Msk (0x1ul << EADC_INTSRC1_AD1SPIE0_Pos) /!< EADC INTSRC1: AD1SPIE0 Mask /
sahilmgandhi	18:6a4db94011d3	10716
sahilmgandhi	18:6a4db94011d3	10717	#define EADC_INTSRC1_AD1SPIE1_Pos (9) /!< EADC INTSRC1: AD1SPIE1 Position /
sahilmgandhi	18:6a4db94011d3	10718	#define EADC_INTSRC1_AD1SPIE1_Msk (0x1ul << EADC_INTSRC1_AD1SPIE1_Pos) /!< EADC INTSRC1: AD1SPIE1 Mask /
sahilmgandhi	18:6a4db94011d3	10719
sahilmgandhi	18:6a4db94011d3	10720	#define EADC_INTSRC1_AD1SPIE2_Pos (10) /!< EADC INTSRC1: AD1SPIE2 Position /
sahilmgandhi	18:6a4db94011d3	10721	#define EADC_INTSRC1_AD1SPIE2_Msk (0x1ul << EADC_INTSRC1_AD1SPIE2_Pos) /!< EADC INTSRC1: AD1SPIE2 Mask /
sahilmgandhi	18:6a4db94011d3	10722
sahilmgandhi	18:6a4db94011d3	10723	#define EADC_INTSRC1_AD1SPIE3_Pos (11) /!< EADC INTSRC1: AD1SPIE3 Position /
sahilmgandhi	18:6a4db94011d3	10724	#define EADC_INTSRC1_AD1SPIE3_Msk (0x1ul << EADC_INTSRC1_AD1SPIE3_Pos) /!< EADC INTSRC1: AD1SPIE3 Mask /
sahilmgandhi	18:6a4db94011d3	10725
sahilmgandhi	18:6a4db94011d3	10726	#define EADC_INTSRC1_AD1SPIE4_Pos (12) /!< EADC INTSRC1: AD1SPIE4 Position /
sahilmgandhi	18:6a4db94011d3	10727	#define EADC_INTSRC1_AD1SPIE4_Msk (0x1ul << EADC_INTSRC1_AD1SPIE4_Pos) /!< EADC INTSRC1: AD1SPIE4 Mask /
sahilmgandhi	18:6a4db94011d3	10728
sahilmgandhi	18:6a4db94011d3	10729	#define EADC_INTSRC1_AD1SPIE5_Pos (13) /!< EADC INTSRC1: AD1SPIE5 Position /
sahilmgandhi	18:6a4db94011d3	10730	#define EADC_INTSRC1_AD1SPIE5_Msk (0x1ul << EADC_INTSRC1_AD1SPIE5_Pos) /!< EADC INTSRC1: AD1SPIE5 Mask /
sahilmgandhi	18:6a4db94011d3	10731
sahilmgandhi	18:6a4db94011d3	10732	#define EADC_INTSRC1_AD1SPIE6_Pos (14) /!< EADC INTSRC1: AD1SPIE6 Position /
sahilmgandhi	18:6a4db94011d3	10733	#define EADC_INTSRC1_AD1SPIE6_Msk (0x1ul << EADC_INTSRC1_AD1SPIE6_Pos) /!< EADC INTSRC1: AD1SPIE6 Mask /
sahilmgandhi	18:6a4db94011d3	10734
sahilmgandhi	18:6a4db94011d3	10735	#define EADC_INTSRC1_AD1SPIE7_Pos (15) /!< EADC INTSRC1: AD1SPIE7 Position /
sahilmgandhi	18:6a4db94011d3	10736	#define EADC_INTSRC1_AD1SPIE7_Msk (0x1ul << EADC_INTSRC1_AD1SPIE7_Pos) /!< EADC INTSRC1: AD1SPIE7 Mask /
sahilmgandhi	18:6a4db94011d3	10737
sahilmgandhi	18:6a4db94011d3	10738	#define EADC_INTSRC2_AD0SPIE0_Pos (0) /!< EADC INTSRC2: AD0SPIE0 Position /
sahilmgandhi	18:6a4db94011d3	10739	#define EADC_INTSRC2_AD0SPIE0_Msk (0x1ul << EADC_INTSRC2_AD0SPIE0_Pos) /!< EADC INTSRC2: AD0SPIE0 Mask /
sahilmgandhi	18:6a4db94011d3	10740
sahilmgandhi	18:6a4db94011d3	10741	#define EADC_INTSRC2_AD0SPIE1_Pos (1) /!< EADC INTSRC2: AD0SPIE1 Position /
sahilmgandhi	18:6a4db94011d3	10742	#define EADC_INTSRC2_AD0SPIE1_Msk (0x1ul << EADC_INTSRC2_AD0SPIE1_Pos) /!< EADC INTSRC2: AD0SPIE1 Mask /
sahilmgandhi	18:6a4db94011d3	10743
sahilmgandhi	18:6a4db94011d3	10744	#define EADC_INTSRC2_AD0SPIE2_Pos (2) /!< EADC INTSRC2: AD0SPIE2 Position /
sahilmgandhi	18:6a4db94011d3	10745	#define EADC_INTSRC2_AD0SPIE2_Msk (0x1ul << EADC_INTSRC2_AD0SPIE2_Pos) /!< EADC INTSRC2: AD0SPIE2 Mask /
sahilmgandhi	18:6a4db94011d3	10746
sahilmgandhi	18:6a4db94011d3	10747	#define EADC_INTSRC2_AD0SPIE3_Pos (3) /!< EADC INTSRC2: AD0SPIE3 Position /
sahilmgandhi	18:6a4db94011d3	10748	#define EADC_INTSRC2_AD0SPIE3_Msk (0x1ul << EADC_INTSRC2_AD0SPIE3_Pos) /!< EADC INTSRC2: AD0SPIE3 Mask /
sahilmgandhi	18:6a4db94011d3	10749
sahilmgandhi	18:6a4db94011d3	10750	#define EADC_INTSRC2_AD0SPIE4_Pos (4) /!< EADC INTSRC2: AD0SPIE4 Position /
sahilmgandhi	18:6a4db94011d3	10751	#define EADC_INTSRC2_AD0SPIE4_Msk (0x1ul << EADC_INTSRC2_AD0SPIE4_Pos) /!< EADC INTSRC2: AD0SPIE4 Mask /
sahilmgandhi	18:6a4db94011d3	10752
sahilmgandhi	18:6a4db94011d3	10753	#define EADC_INTSRC2_AD0SPIE5_Pos (5) /!< EADC INTSRC2: AD0SPIE5 Position /
sahilmgandhi	18:6a4db94011d3	10754	#define EADC_INTSRC2_AD0SPIE5_Msk (0x1ul << EADC_INTSRC2_AD0SPIE5_Pos) /!< EADC INTSRC2: AD0SPIE5 Mask /
sahilmgandhi	18:6a4db94011d3	10755
sahilmgandhi	18:6a4db94011d3	10756	#define EADC_INTSRC2_AD0SPIE6_Pos (6) /!< EADC INTSRC2: AD0SPIE6 Position /
sahilmgandhi	18:6a4db94011d3	10757	#define EADC_INTSRC2_AD0SPIE6_Msk (0x1ul << EADC_INTSRC2_AD0SPIE6_Pos) /!< EADC INTSRC2: AD0SPIE6 Mask /
sahilmgandhi	18:6a4db94011d3	10758
sahilmgandhi	18:6a4db94011d3	10759	#define EADC_INTSRC2_AD0SPIE7_Pos (7) /!< EADC INTSRC2: AD0SPIE7 Position /
sahilmgandhi	18:6a4db94011d3	10760	#define EADC_INTSRC2_AD0SPIE7_Msk (0x1ul << EADC_INTSRC2_AD0SPIE7_Pos) /!< EADC INTSRC2: AD0SPIE7 Mask /
sahilmgandhi	18:6a4db94011d3	10761
sahilmgandhi	18:6a4db94011d3	10762	#define EADC_INTSRC2_AD1SPIE0_Pos (8) /!< EADC INTSRC2: AD1SPIE0 Position /
sahilmgandhi	18:6a4db94011d3	10763	#define EADC_INTSRC2_AD1SPIE0_Msk (0x1ul << EADC_INTSRC2_AD1SPIE0_Pos) /!< EADC INTSRC2: AD1SPIE0 Mask /
sahilmgandhi	18:6a4db94011d3	10764
sahilmgandhi	18:6a4db94011d3	10765	#define EADC_INTSRC2_AD1SPIE1_Pos (9) /!< EADC INTSRC2: AD1SPIE1 Position /
sahilmgandhi	18:6a4db94011d3	10766	#define EADC_INTSRC2_AD1SPIE1_Msk (0x1ul << EADC_INTSRC2_AD1SPIE1_Pos) /!< EADC INTSRC2: AD1SPIE1 Mask /
sahilmgandhi	18:6a4db94011d3	10767
sahilmgandhi	18:6a4db94011d3	10768	#define EADC_INTSRC2_AD1SPIE2_Pos (10) /!< EADC INTSRC2: AD1SPIE2 Position /
sahilmgandhi	18:6a4db94011d3	10769	#define EADC_INTSRC2_AD1SPIE2_Msk (0x1ul << EADC_INTSRC2_AD1SPIE2_Pos) /!< EADC INTSRC2: AD1SPIE2 Mask /
sahilmgandhi	18:6a4db94011d3	10770
sahilmgandhi	18:6a4db94011d3	10771	#define EADC_INTSRC2_AD1SPIE3_Pos (11) /!< EADC INTSRC2: AD1SPIE3 Position /
sahilmgandhi	18:6a4db94011d3	10772	#define EADC_INTSRC2_AD1SPIE3_Msk (0x1ul << EADC_INTSRC2_AD1SPIE3_Pos) /!< EADC INTSRC2: AD1SPIE3 Mask /
sahilmgandhi	18:6a4db94011d3	10773
sahilmgandhi	18:6a4db94011d3	10774	#define EADC_INTSRC2_AD1SPIE4_Pos (12) /!< EADC INTSRC2: AD1SPIE4 Position /
sahilmgandhi	18:6a4db94011d3	10775	#define EADC_INTSRC2_AD1SPIE4_Msk (0x1ul << EADC_INTSRC2_AD1SPIE4_Pos) /!< EADC INTSRC2: AD1SPIE4 Mask /
sahilmgandhi	18:6a4db94011d3	10776
sahilmgandhi	18:6a4db94011d3	10777	#define EADC_INTSRC2_AD1SPIE5_Pos (13) /!< EADC INTSRC2: AD1SPIE5 Position /
sahilmgandhi	18:6a4db94011d3	10778	#define EADC_INTSRC2_AD1SPIE5_Msk (0x1ul << EADC_INTSRC2_AD1SPIE5_Pos) /!< EADC INTSRC2: AD1SPIE5 Mask /
sahilmgandhi	18:6a4db94011d3	10779
sahilmgandhi	18:6a4db94011d3	10780	#define EADC_INTSRC2_AD1SPIE6_Pos (14) /!< EADC INTSRC2: AD1SPIE6 Position /
sahilmgandhi	18:6a4db94011d3	10781	#define EADC_INTSRC2_AD1SPIE6_Msk (0x1ul << EADC_INTSRC2_AD1SPIE6_Pos) /!< EADC INTSRC2: AD1SPIE6 Mask /
sahilmgandhi	18:6a4db94011d3	10782
sahilmgandhi	18:6a4db94011d3	10783	#define EADC_INTSRC2_AD1SPIE7_Pos (15) /!< EADC INTSRC2: AD1SPIE7 Position /
sahilmgandhi	18:6a4db94011d3	10784	#define EADC_INTSRC2_AD1SPIE7_Msk (0x1ul << EADC_INTSRC2_AD1SPIE7_Pos) /!< EADC INTSRC2: AD1SPIE7 Mask /
sahilmgandhi	18:6a4db94011d3	10785
sahilmgandhi	18:6a4db94011d3	10786	#define EADC_INTSRC3_AD0SPIE0_Pos (0) /!< EADC INTSRC3: AD0SPIE0 Position /
sahilmgandhi	18:6a4db94011d3	10787	#define EADC_INTSRC3_AD0SPIE0_Msk (0x1ul << EADC_INTSRC3_AD0SPIE0_Pos) /!< EADC INTSRC3: AD0SPIE0 Mask /
sahilmgandhi	18:6a4db94011d3	10788
sahilmgandhi	18:6a4db94011d3	10789	#define EADC_INTSRC3_AD0SPIE1_Pos (1) /!< EADC INTSRC3: AD0SPIE1 Position /
sahilmgandhi	18:6a4db94011d3	10790	#define EADC_INTSRC3_AD0SPIE1_Msk (0x1ul << EADC_INTSRC3_AD0SPIE1_Pos) /!< EADC INTSRC3: AD0SPIE1 Mask /
sahilmgandhi	18:6a4db94011d3	10791
sahilmgandhi	18:6a4db94011d3	10792	#define EADC_INTSRC3_AD0SPIE2_Pos (2) /!< EADC INTSRC3: AD0SPIE2 Position /
sahilmgandhi	18:6a4db94011d3	10793	#define EADC_INTSRC3_AD0SPIE2_Msk (0x1ul << EADC_INTSRC3_AD0SPIE2_Pos) /!< EADC INTSRC3: AD0SPIE2 Mask /
sahilmgandhi	18:6a4db94011d3	10794
sahilmgandhi	18:6a4db94011d3	10795	#define EADC_INTSRC3_AD0SPIE3_Pos (3) /!< EADC INTSRC3: AD0SPIE3 Position /
sahilmgandhi	18:6a4db94011d3	10796	#define EADC_INTSRC3_AD0SPIE3_Msk (0x1ul << EADC_INTSRC3_AD0SPIE3_Pos) /!< EADC INTSRC3: AD0SPIE3 Mask /
sahilmgandhi	18:6a4db94011d3	10797
sahilmgandhi	18:6a4db94011d3	10798	#define EADC_INTSRC3_AD0SPIE4_Pos (4) /!< EADC INTSRC3: AD0SPIE4 Position /
sahilmgandhi	18:6a4db94011d3	10799	#define EADC_INTSRC3_AD0SPIE4_Msk (0x1ul << EADC_INTSRC3_AD0SPIE4_Pos) /!< EADC INTSRC3: AD0SPIE4 Mask /
sahilmgandhi	18:6a4db94011d3	10800
sahilmgandhi	18:6a4db94011d3	10801	#define EADC_INTSRC3_AD0SPIE5_Pos (5) /!< EADC INTSRC3: AD0SPIE5 Position /
sahilmgandhi	18:6a4db94011d3	10802	#define EADC_INTSRC3_AD0SPIE5_Msk (0x1ul << EADC_INTSRC3_AD0SPIE5_Pos) /!< EADC INTSRC3: AD0SPIE5 Mask /
sahilmgandhi	18:6a4db94011d3	10803
sahilmgandhi	18:6a4db94011d3	10804	#define EADC_INTSRC3_AD0SPIE6_Pos (6) /!< EADC INTSRC3: AD0SPIE6 Position /
sahilmgandhi	18:6a4db94011d3	10805	#define EADC_INTSRC3_AD0SPIE6_Msk (0x1ul << EADC_INTSRC3_AD0SPIE6_Pos) /!< EADC INTSRC3: AD0SPIE6 Mask /
sahilmgandhi	18:6a4db94011d3	10806
sahilmgandhi	18:6a4db94011d3	10807	#define EADC_INTSRC3_AD0SPIE7_Pos (7) /!< EADC INTSRC3: AD0SPIE7 Position /
sahilmgandhi	18:6a4db94011d3	10808	#define EADC_INTSRC3_AD0SPIE7_Msk (0x1ul << EADC_INTSRC3_AD0SPIE7_Pos) /!< EADC INTSRC3: AD0SPIE7 Mask /
sahilmgandhi	18:6a4db94011d3	10809
sahilmgandhi	18:6a4db94011d3	10810	#define EADC_INTSRC3_AD1SPIE0_Pos (8) /!< EADC INTSRC3: AD1SPIE0 Position /
sahilmgandhi	18:6a4db94011d3	10811	#define EADC_INTSRC3_AD1SPIE0_Msk (0x1ul << EADC_INTSRC3_AD1SPIE0_Pos) /!< EADC INTSRC3: AD1SPIE0 Mask /
sahilmgandhi	18:6a4db94011d3	10812
sahilmgandhi	18:6a4db94011d3	10813	#define EADC_INTSRC3_AD1SPIE1_Pos (9) /!< EADC INTSRC3: AD1SPIE1 Position /
sahilmgandhi	18:6a4db94011d3	10814	#define EADC_INTSRC3_AD1SPIE1_Msk (0x1ul << EADC_INTSRC3_AD1SPIE1_Pos) /!< EADC INTSRC3: AD1SPIE1 Mask /
sahilmgandhi	18:6a4db94011d3	10815
sahilmgandhi	18:6a4db94011d3	10816	#define EADC_INTSRC3_AD1SPIE2_Pos (10) /!< EADC INTSRC3: AD1SPIE2 Position /
sahilmgandhi	18:6a4db94011d3	10817	#define EADC_INTSRC3_AD1SPIE2_Msk (0x1ul << EADC_INTSRC3_AD1SPIE2_Pos) /!< EADC INTSRC3: AD1SPIE2 Mask /
sahilmgandhi	18:6a4db94011d3	10818
sahilmgandhi	18:6a4db94011d3	10819	#define EADC_INTSRC3_AD1SPIE3_Pos (11) /!< EADC INTSRC3: AD1SPIE3 Position /
sahilmgandhi	18:6a4db94011d3	10820	#define EADC_INTSRC3_AD1SPIE3_Msk (0x1ul << EADC_INTSRC3_AD1SPIE3_Pos) /!< EADC INTSRC3: AD1SPIE3 Mask /
sahilmgandhi	18:6a4db94011d3	10821
sahilmgandhi	18:6a4db94011d3	10822	#define EADC_INTSRC3_AD1SPIE4_Pos (12) /!< EADC INTSRC3: AD1SPIE4 Position /
sahilmgandhi	18:6a4db94011d3	10823	#define EADC_INTSRC3_AD1SPIE4_Msk (0x1ul << EADC_INTSRC3_AD1SPIE4_Pos) /!< EADC INTSRC3: AD1SPIE4 Mask /
sahilmgandhi	18:6a4db94011d3	10824
sahilmgandhi	18:6a4db94011d3	10825	#define EADC_INTSRC3_AD1SPIE5_Pos (13) /!< EADC INTSRC3: AD1SPIE5 Position /
sahilmgandhi	18:6a4db94011d3	10826	#define EADC_INTSRC3_AD1SPIE5_Msk (0x1ul << EADC_INTSRC3_AD1SPIE5_Pos) /!< EADC INTSRC3: AD1SPIE5 Mask /
sahilmgandhi	18:6a4db94011d3	10827
sahilmgandhi	18:6a4db94011d3	10828	#define EADC_INTSRC3_AD1SPIE6_Pos (14) /!< EADC INTSRC3: AD1SPIE6 Position /
sahilmgandhi	18:6a4db94011d3	10829	#define EADC_INTSRC3_AD1SPIE6_Msk (0x1ul << EADC_INTSRC3_AD1SPIE6_Pos) /!< EADC INTSRC3: AD1SPIE6 Mask /
sahilmgandhi	18:6a4db94011d3	10830
sahilmgandhi	18:6a4db94011d3	10831	#define EADC_INTSRC3_AD1SPIE7_Pos (15) /!< EADC INTSRC3: AD1SPIE7 Position /
sahilmgandhi	18:6a4db94011d3	10832	#define EADC_INTSRC3_AD1SPIE7_Msk (0x1ul << EADC_INTSRC3_AD1SPIE7_Pos) /!< EADC INTSRC3: AD1SPIE7 Mask /
sahilmgandhi	18:6a4db94011d3	10833
sahilmgandhi	18:6a4db94011d3	10834	#define EADC_AD0TRGEN0_EPWM00REN_Pos (0) /!< EADC AD0TRGEN0: EPWM00REN Position /
sahilmgandhi	18:6a4db94011d3	10835	#define EADC_AD0TRGEN0_EPWM00REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM00REN_Pos) /!< EADC AD0TRGEN0: EPWM00REN Mask /
sahilmgandhi	18:6a4db94011d3	10836
sahilmgandhi	18:6a4db94011d3	10837	#define EADC_AD0TRGEN0_EPWM00FEN_Pos (1) /!< EADC AD0TRGEN0: EPWM00FEN Position /
sahilmgandhi	18:6a4db94011d3	10838	#define EADC_AD0TRGEN0_EPWM00FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM00FEN_Pos) /!< EADC AD0TRGEN0: EPWM00FEN Mask /
sahilmgandhi	18:6a4db94011d3	10839
sahilmgandhi	18:6a4db94011d3	10840	#define EADC_AD0TRGEN0_EPWM00PEN_Pos (2) /!< EADC AD0TRGEN0: EPWM00PEN Position /
sahilmgandhi	18:6a4db94011d3	10841	#define EADC_AD0TRGEN0_EPWM00PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM00PEN_Pos) /!< EADC AD0TRGEN0: EPWM00PEN Mask /
sahilmgandhi	18:6a4db94011d3	10842
sahilmgandhi	18:6a4db94011d3	10843	#define EADC_AD0TRGEN0_EPWM00CEN_Pos (3) /!< EADC AD0TRGEN0: EPWM00CEN Position /
sahilmgandhi	18:6a4db94011d3	10844	#define EADC_AD0TRGEN0_EPWM00CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM00CEN_Pos) /!< EADC AD0TRGEN0: EPWM00CEN Mask /
sahilmgandhi	18:6a4db94011d3	10845
sahilmgandhi	18:6a4db94011d3	10846	#define EADC_AD0TRGEN0_EPWM02REN_Pos (4) /!< EADC AD0TRGEN0: EPWM02REN Position /
sahilmgandhi	18:6a4db94011d3	10847	#define EADC_AD0TRGEN0_EPWM02REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM02REN_Pos) /!< EADC AD0TRGEN0: EPWM02REN Mask /
sahilmgandhi	18:6a4db94011d3	10848
sahilmgandhi	18:6a4db94011d3	10849	#define EADC_AD0TRGEN0_EPWM02FEN_Pos (5) /!< EADC AD0TRGEN0: EPWM02FEN Position /
sahilmgandhi	18:6a4db94011d3	10850	#define EADC_AD0TRGEN0_EPWM02FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM02FEN_Pos) /!< EADC AD0TRGEN0: EPWM02FEN Mask /
sahilmgandhi	18:6a4db94011d3	10851
sahilmgandhi	18:6a4db94011d3	10852	#define EADC_AD0TRGEN0_EPWM02PEN_Pos (6) /!< EADC AD0TRGEN0: EPWM02PEN Position /
sahilmgandhi	18:6a4db94011d3	10853	#define EADC_AD0TRGEN0_EPWM02PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM02PEN_Pos) /!< EADC AD0TRGEN0: EPWM02PEN Mask /
sahilmgandhi	18:6a4db94011d3	10854
sahilmgandhi	18:6a4db94011d3	10855	#define EADC_AD0TRGEN0_EPWM02CEN_Pos (7) /!< EADC AD0TRGEN0: EPWM02CEN Position /
sahilmgandhi	18:6a4db94011d3	10856	#define EADC_AD0TRGEN0_EPWM02CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM02CEN_Pos) /!< EADC AD0TRGEN0: EPWM02CEN Mask /
sahilmgandhi	18:6a4db94011d3	10857
sahilmgandhi	18:6a4db94011d3	10858	#define EADC_AD0TRGEN0_EPWM04REN_Pos (8) /!< EADC AD0TRGEN0: EPWM04REN Position /
sahilmgandhi	18:6a4db94011d3	10859	#define EADC_AD0TRGEN0_EPWM04REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM04REN_Pos) /!< EADC AD0TRGEN0: EPWM04REN Mask /
sahilmgandhi	18:6a4db94011d3	10860
sahilmgandhi	18:6a4db94011d3	10861	#define EADC_AD0TRGEN0_EPWM04FEN_Pos (9) /!< EADC AD0TRGEN0: EPWM04FEN Position /
sahilmgandhi	18:6a4db94011d3	10862	#define EADC_AD0TRGEN0_EPWM04FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM04FEN_Pos) /!< EADC AD0TRGEN0: EPWM04FEN Mask /
sahilmgandhi	18:6a4db94011d3	10863
sahilmgandhi	18:6a4db94011d3	10864	#define EADC_AD0TRGEN0_EPWM04PEN_Pos (10) /!< EADC AD0TRGEN0: EPWM04PEN Position /
sahilmgandhi	18:6a4db94011d3	10865	#define EADC_AD0TRGEN0_EPWM04PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM04PEN_Pos) /!< EADC AD0TRGEN0: EPWM04PEN Mask /
sahilmgandhi	18:6a4db94011d3	10866
sahilmgandhi	18:6a4db94011d3	10867	#define EADC_AD0TRGEN0_EPWM04CEN_Pos (11) /!< EADC AD0TRGEN0: EPWM04CEN Position /
sahilmgandhi	18:6a4db94011d3	10868	#define EADC_AD0TRGEN0_EPWM04CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM04CEN_Pos) /!< EADC AD0TRGEN0: EPWM04CEN Mask /
sahilmgandhi	18:6a4db94011d3	10869
sahilmgandhi	18:6a4db94011d3	10870	#define EADC_AD0TRGEN0_EPWM10REN_Pos (12) /!< EADC AD0TRGEN0: EPWM10REN Position /
sahilmgandhi	18:6a4db94011d3	10871	#define EADC_AD0TRGEN0_EPWM10REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM10REN_Pos) /!< EADC AD0TRGEN0: EPWM10REN Mask /
sahilmgandhi	18:6a4db94011d3	10872
sahilmgandhi	18:6a4db94011d3	10873	#define EADC_AD0TRGEN0_EPWM10FEN_Pos (13) /!< EADC AD0TRGEN0: EPWM10FEN Position /
sahilmgandhi	18:6a4db94011d3	10874	#define EADC_AD0TRGEN0_EPWM10FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM10FEN_Pos) /!< EADC AD0TRGEN0: EPWM10FEN Mask /
sahilmgandhi	18:6a4db94011d3	10875
sahilmgandhi	18:6a4db94011d3	10876	#define EADC_AD0TRGEN0_EPWM10PEN_Pos (14) /!< EADC AD0TRGEN0: EPWM10PEN Position /
sahilmgandhi	18:6a4db94011d3	10877	#define EADC_AD0TRGEN0_EPWM10PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM10PEN_Pos) /!< EADC AD0TRGEN0: EPWM10PEN Mask /
sahilmgandhi	18:6a4db94011d3	10878
sahilmgandhi	18:6a4db94011d3	10879	#define EADC_AD0TRGEN0_EPWM10CEN_Pos (15) /!< EADC AD0TRGEN0: EPWM10CEN Position /
sahilmgandhi	18:6a4db94011d3	10880	#define EADC_AD0TRGEN0_EPWM10CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM10CEN_Pos) /!< EADC AD0TRGEN0: EPWM10CEN Mask /
sahilmgandhi	18:6a4db94011d3	10881
sahilmgandhi	18:6a4db94011d3	10882	#define EADC_AD0TRGEN0_EPWM12REN_Pos (16) /!< EADC AD0TRGEN0: EPWM12REN Position /
sahilmgandhi	18:6a4db94011d3	10883	#define EADC_AD0TRGEN0_EPWM12REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM12REN_Pos) /!< EADC AD0TRGEN0: EPWM12REN Mask /
sahilmgandhi	18:6a4db94011d3	10884
sahilmgandhi	18:6a4db94011d3	10885	#define EADC_AD0TRGEN0_EPWM120FEN_Pos (17) /!< EADC AD0TRGEN0: EPWM120FEN Position /
sahilmgandhi	18:6a4db94011d3	10886	#define EADC_AD0TRGEN0_EPWM120FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM120FEN_Pos) /!< EADC AD0TRGEN0: EPWM120FEN Mask /
sahilmgandhi	18:6a4db94011d3	10887
sahilmgandhi	18:6a4db94011d3	10888	#define EADC_AD0TRGEN0_EPWM12PEN_Pos (18) /!< EADC AD0TRGEN0: EPWM12PEN Position /
sahilmgandhi	18:6a4db94011d3	10889	#define EADC_AD0TRGEN0_EPWM12PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM12PEN_Pos) /!< EADC AD0TRGEN0: EPWM12PEN Mask /
sahilmgandhi	18:6a4db94011d3	10890
sahilmgandhi	18:6a4db94011d3	10891	#define EADC_AD0TRGEN0_EPWM12CEN_Pos (19) /!< EADC AD0TRGEN0: EPWM12CEN Position /
sahilmgandhi	18:6a4db94011d3	10892	#define EADC_AD0TRGEN0_EPWM12CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM12CEN_Pos) /!< EADC AD0TRGEN0: EPWM12CEN Mask /
sahilmgandhi	18:6a4db94011d3	10893
sahilmgandhi	18:6a4db94011d3	10894	#define EADC_AD0TRGEN0_EPWM14REN_Pos (20) /!< EADC AD0TRGEN0: EPWM14REN Position /
sahilmgandhi	18:6a4db94011d3	10895	#define EADC_AD0TRGEN0_EPWM14REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM14REN_Pos) /!< EADC AD0TRGEN0: EPWM14REN Mask /
sahilmgandhi	18:6a4db94011d3	10896
sahilmgandhi	18:6a4db94011d3	10897	#define EADC_AD0TRGEN0_EPWM14FEN_Pos (21) /!< EADC AD0TRGEN0: EPWM14FEN Position /
sahilmgandhi	18:6a4db94011d3	10898	#define EADC_AD0TRGEN0_EPWM14FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM14FEN_Pos) /!< EADC AD0TRGEN0: EPWM14FEN Mask /
sahilmgandhi	18:6a4db94011d3	10899
sahilmgandhi	18:6a4db94011d3	10900	#define EADC_AD0TRGEN0_EPWM14PEN_Pos (22) /!< EADC AD0TRGEN0: EPWM14PEN Position /
sahilmgandhi	18:6a4db94011d3	10901	#define EADC_AD0TRGEN0_EPWM14PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM14PEN_Pos) /!< EADC AD0TRGEN0: EPWM14PEN Mask /
sahilmgandhi	18:6a4db94011d3	10902
sahilmgandhi	18:6a4db94011d3	10903	#define EADC_AD0TRGEN0_EPWM14CEN_Pos (23) /!< EADC AD0TRGEN0: EPWM14CEN Position /
sahilmgandhi	18:6a4db94011d3	10904	#define EADC_AD0TRGEN0_EPWM14CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM14CEN_Pos) /!< EADC AD0TRGEN0: EPWM14CEN Mask /
sahilmgandhi	18:6a4db94011d3	10905
sahilmgandhi	18:6a4db94011d3	10906	#define EADC_AD0TRGEN0_PWM00REN_Pos (24) /!< EADC AD0TRGEN0: PWM00REN Position /
sahilmgandhi	18:6a4db94011d3	10907	#define EADC_AD0TRGEN0_PWM00REN_Msk (0x1ul << EADC_AD0TRGEN0_PWM00REN_Pos) /!< EADC AD0TRGEN0: PWM00REN Mask /
sahilmgandhi	18:6a4db94011d3	10908
sahilmgandhi	18:6a4db94011d3	10909	#define EADC_AD0TRGEN0_PWM00FEN_Pos (25) /!< EADC AD0TRGEN0: PWM00FEN Position /
sahilmgandhi	18:6a4db94011d3	10910	#define EADC_AD0TRGEN0_PWM00FEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM00FEN_Pos) /!< EADC AD0TRGEN0: PWM00FEN Mask /
sahilmgandhi	18:6a4db94011d3	10911
sahilmgandhi	18:6a4db94011d3	10912	#define EADC_AD0TRGEN0_PWM00PEN_Pos (26) /!< EADC AD0TRGEN0: PWM00PEN Position /
sahilmgandhi	18:6a4db94011d3	10913	#define EADC_AD0TRGEN0_PWM00PEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM00PEN_Pos) /!< EADC AD0TRGEN0: PWM00PEN Mask /
sahilmgandhi	18:6a4db94011d3	10914
sahilmgandhi	18:6a4db94011d3	10915	#define EADC_AD0TRGEN0_PWM00CEN_Pos (27) /!< EADC AD0TRGEN0: PWM00CEN Position /
sahilmgandhi	18:6a4db94011d3	10916	#define EADC_AD0TRGEN0_PWM00CEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM00CEN_Pos) /!< EADC AD0TRGEN0: PWM00CEN Mask /
sahilmgandhi	18:6a4db94011d3	10917
sahilmgandhi	18:6a4db94011d3	10918	#define EADC_AD0TRGEN0_PWM01REN_Pos (28) /!< EADC AD0TRGEN0: PWM01REN Position /
sahilmgandhi	18:6a4db94011d3	10919	#define EADC_AD0TRGEN0_PWM01REN_Msk (0x1ul << EADC_AD0TRGEN0_PWM01REN_Pos) /!< EADC AD0TRGEN0: PWM01REN Mask /
sahilmgandhi	18:6a4db94011d3	10920
sahilmgandhi	18:6a4db94011d3	10921	#define EADC_AD0TRGEN0_PWM01FEN_Pos (29) /!< EADC AD0TRGEN0: PWM01FEN Position /
sahilmgandhi	18:6a4db94011d3	10922	#define EADC_AD0TRGEN0_PWM01FEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM01FEN_Pos) /!< EADC AD0TRGEN0: PWM01FEN Mask /
sahilmgandhi	18:6a4db94011d3	10923
sahilmgandhi	18:6a4db94011d3	10924	#define EADC_AD0TRGEN0_PWM01PEN_Pos (30) /!< EADC AD0TRGEN0: PWM01PEN Position /
sahilmgandhi	18:6a4db94011d3	10925	#define EADC_AD0TRGEN0_PWM01PEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM01PEN_Pos) /!< EADC AD0TRGEN0: PWM01PEN Mask /
sahilmgandhi	18:6a4db94011d3	10926
sahilmgandhi	18:6a4db94011d3	10927	#define EADC_AD0TRGEN0_PWM01CEN_Pos (31) /!< EADC AD0TRGEN0: PWM01CEN Position /
sahilmgandhi	18:6a4db94011d3	10928	#define EADC_AD0TRGEN0_PWM01CEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM01CEN_Pos) /!< EADC AD0TRGEN0: PWM01CEN Mask /
sahilmgandhi	18:6a4db94011d3	10929
sahilmgandhi	18:6a4db94011d3	10930	#define EADC_AD0TRGEN1_EPWM00REN_Pos (0) /!< EADC AD0TRGEN1: EPWM00REN Position /
sahilmgandhi	18:6a4db94011d3	10931	#define EADC_AD0TRGEN1_EPWM00REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM00REN_Pos) /!< EADC AD0TRGEN1: EPWM00REN Mask /
sahilmgandhi	18:6a4db94011d3	10932
sahilmgandhi	18:6a4db94011d3	10933	#define EADC_AD0TRGEN1_EPWM00FEN_Pos (1) /!< EADC AD0TRGEN1: EPWM00FEN Position /
sahilmgandhi	18:6a4db94011d3	10934	#define EADC_AD0TRGEN1_EPWM00FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM00FEN_Pos) /!< EADC AD0TRGEN1: EPWM00FEN Mask /
sahilmgandhi	18:6a4db94011d3	10935
sahilmgandhi	18:6a4db94011d3	10936	#define EADC_AD0TRGEN1_EPWM00PEN_Pos (2) /!< EADC AD0TRGEN1: EPWM00PEN Position /
sahilmgandhi	18:6a4db94011d3	10937	#define EADC_AD0TRGEN1_EPWM00PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM00PEN_Pos) /!< EADC AD0TRGEN1: EPWM00PEN Mask /
sahilmgandhi	18:6a4db94011d3	10938
sahilmgandhi	18:6a4db94011d3	10939	#define EADC_AD0TRGEN1_EPWM00CEN_Pos (3) /!< EADC AD0TRGEN1: EPWM00CEN Position /
sahilmgandhi	18:6a4db94011d3	10940	#define EADC_AD0TRGEN1_EPWM00CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM00CEN_Pos) /!< EADC AD0TRGEN1: EPWM00CEN Mask /
sahilmgandhi	18:6a4db94011d3	10941
sahilmgandhi	18:6a4db94011d3	10942	#define EADC_AD0TRGEN1_EPWM02REN_Pos (4) /!< EADC AD0TRGEN1: EPWM02REN Position /
sahilmgandhi	18:6a4db94011d3	10943	#define EADC_AD0TRGEN1_EPWM02REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM02REN_Pos) /!< EADC AD0TRGEN1: EPWM02REN Mask /
sahilmgandhi	18:6a4db94011d3	10944
sahilmgandhi	18:6a4db94011d3	10945	#define EADC_AD0TRGEN1_EPWM02FEN_Pos (5) /!< EADC AD0TRGEN1: EPWM02FEN Position /
sahilmgandhi	18:6a4db94011d3	10946	#define EADC_AD0TRGEN1_EPWM02FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM02FEN_Pos) /!< EADC AD0TRGEN1: EPWM02FEN Mask /
sahilmgandhi	18:6a4db94011d3	10947
sahilmgandhi	18:6a4db94011d3	10948	#define EADC_AD0TRGEN1_EPWM02PEN_Pos (6) /!< EADC AD0TRGEN1: EPWM02PEN Position /
sahilmgandhi	18:6a4db94011d3	10949	#define EADC_AD0TRGEN1_EPWM02PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM02PEN_Pos) /!< EADC AD0TRGEN1: EPWM02PEN Mask /
sahilmgandhi	18:6a4db94011d3	10950
sahilmgandhi	18:6a4db94011d3	10951	#define EADC_AD0TRGEN1_EPWM02CEN_Pos (7) /!< EADC AD0TRGEN1: EPWM02CEN Position /
sahilmgandhi	18:6a4db94011d3	10952	#define EADC_AD0TRGEN1_EPWM02CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM02CEN_Pos) /!< EADC AD0TRGEN1: EPWM02CEN Mask /
sahilmgandhi	18:6a4db94011d3	10953
sahilmgandhi	18:6a4db94011d3	10954	#define EADC_AD0TRGEN1_EPWM04REN_Pos (8) /!< EADC AD0TRGEN1: EPWM04REN Position /
sahilmgandhi	18:6a4db94011d3	10955	#define EADC_AD0TRGEN1_EPWM04REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM04REN_Pos) /!< EADC AD0TRGEN1: EPWM04REN Mask /
sahilmgandhi	18:6a4db94011d3	10956
sahilmgandhi	18:6a4db94011d3	10957	#define EADC_AD0TRGEN1_EPWM04FEN_Pos (9) /!< EADC AD0TRGEN1: EPWM04FEN Position /
sahilmgandhi	18:6a4db94011d3	10958	#define EADC_AD0TRGEN1_EPWM04FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM04FEN_Pos) /!< EADC AD0TRGEN1: EPWM04FEN Mask /
sahilmgandhi	18:6a4db94011d3	10959
sahilmgandhi	18:6a4db94011d3	10960	#define EADC_AD0TRGEN1_EPWM04PEN_Pos (10) /!< EADC AD0TRGEN1: EPWM04PEN Position /
sahilmgandhi	18:6a4db94011d3	10961	#define EADC_AD0TRGEN1_EPWM04PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM04PEN_Pos) /!< EADC AD0TRGEN1: EPWM04PEN Mask /
sahilmgandhi	18:6a4db94011d3	10962
sahilmgandhi	18:6a4db94011d3	10963	#define EADC_AD0TRGEN1_EPWM04CEN_Pos (11) /!< EADC AD0TRGEN1: EPWM04CEN Position /
sahilmgandhi	18:6a4db94011d3	10964	#define EADC_AD0TRGEN1_EPWM04CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM04CEN_Pos) /!< EADC AD0TRGEN1: EPWM04CEN Mask /
sahilmgandhi	18:6a4db94011d3	10965
sahilmgandhi	18:6a4db94011d3	10966	#define EADC_AD0TRGEN1_EPWM10REN_Pos (12) /!< EADC AD0TRGEN1: EPWM10REN Position /
sahilmgandhi	18:6a4db94011d3	10967	#define EADC_AD0TRGEN1_EPWM10REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM10REN_Pos) /!< EADC AD0TRGEN1: EPWM10REN Mask /
sahilmgandhi	18:6a4db94011d3	10968
sahilmgandhi	18:6a4db94011d3	10969	#define EADC_AD0TRGEN1_EPWM10FEN_Pos (13) /!< EADC AD0TRGEN1: EPWM10FEN Position /
sahilmgandhi	18:6a4db94011d3	10970	#define EADC_AD0TRGEN1_EPWM10FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM10FEN_Pos) /!< EADC AD0TRGEN1: EPWM10FEN Mask /
sahilmgandhi	18:6a4db94011d3	10971
sahilmgandhi	18:6a4db94011d3	10972	#define EADC_AD0TRGEN1_EPWM10PEN_Pos (14) /!< EADC AD0TRGEN1: EPWM10PEN Position /
sahilmgandhi	18:6a4db94011d3	10973	#define EADC_AD0TRGEN1_EPWM10PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM10PEN_Pos) /!< EADC AD0TRGEN1: EPWM10PEN Mask /
sahilmgandhi	18:6a4db94011d3	10974
sahilmgandhi	18:6a4db94011d3	10975	#define EADC_AD0TRGEN1_EPWM10CEN_Pos (15) /!< EADC AD0TRGEN1: EPWM10CEN Position /
sahilmgandhi	18:6a4db94011d3	10976	#define EADC_AD0TRGEN1_EPWM10CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM10CEN_Pos) /!< EADC AD0TRGEN1: EPWM10CEN Mask /
sahilmgandhi	18:6a4db94011d3	10977
sahilmgandhi	18:6a4db94011d3	10978	#define EADC_AD0TRGEN1_EPWM12REN_Pos (16) /!< EADC AD0TRGEN1: EPWM12REN Position /
sahilmgandhi	18:6a4db94011d3	10979	#define EADC_AD0TRGEN1_EPWM12REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM12REN_Pos) /!< EADC AD0TRGEN1: EPWM12REN Mask /
sahilmgandhi	18:6a4db94011d3	10980
sahilmgandhi	18:6a4db94011d3	10981	#define EADC_AD0TRGEN1_EPWM120FEN_Pos (17) /!< EADC AD0TRGEN1: EPWM120FEN Position /
sahilmgandhi	18:6a4db94011d3	10982	#define EADC_AD0TRGEN1_EPWM120FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM120FEN_Pos) /!< EADC AD0TRGEN1: EPWM120FEN Mask /
sahilmgandhi	18:6a4db94011d3	10983
sahilmgandhi	18:6a4db94011d3	10984	#define EADC_AD0TRGEN1_EPWM12PEN_Pos (18) /!< EADC AD0TRGEN1: EPWM12PEN Position /
sahilmgandhi	18:6a4db94011d3	10985	#define EADC_AD0TRGEN1_EPWM12PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM12PEN_Pos) /!< EADC AD0TRGEN1: EPWM12PEN Mask /
sahilmgandhi	18:6a4db94011d3	10986
sahilmgandhi	18:6a4db94011d3	10987	#define EADC_AD0TRGEN1_EPWM12CEN_Pos (19) /!< EADC AD0TRGEN1: EPWM12CEN Position /
sahilmgandhi	18:6a4db94011d3	10988	#define EADC_AD0TRGEN1_EPWM12CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM12CEN_Pos) /!< EADC AD0TRGEN1: EPWM12CEN Mask /
sahilmgandhi	18:6a4db94011d3	10989
sahilmgandhi	18:6a4db94011d3	10990	#define EADC_AD0TRGEN1_EPWM14REN_Pos (20) /!< EADC AD0TRGEN1: EPWM14REN Position /
sahilmgandhi	18:6a4db94011d3	10991	#define EADC_AD0TRGEN1_EPWM14REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM14REN_Pos) /!< EADC AD0TRGEN1: EPWM14REN Mask /
sahilmgandhi	18:6a4db94011d3	10992
sahilmgandhi	18:6a4db94011d3	10993	#define EADC_AD0TRGEN1_EPWM14FEN_Pos (21) /!< EADC AD0TRGEN1: EPWM14FEN Position /
sahilmgandhi	18:6a4db94011d3	10994	#define EADC_AD0TRGEN1_EPWM14FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM14FEN_Pos) /!< EADC AD0TRGEN1: EPWM14FEN Mask /
sahilmgandhi	18:6a4db94011d3	10995
sahilmgandhi	18:6a4db94011d3	10996	#define EADC_AD0TRGEN1_EPWM14PEN_Pos (22) /!< EADC AD0TRGEN1: EPWM14PEN Position /
sahilmgandhi	18:6a4db94011d3	10997	#define EADC_AD0TRGEN1_EPWM14PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM14PEN_Pos) /!< EADC AD0TRGEN1: EPWM14PEN Mask /
sahilmgandhi	18:6a4db94011d3	10998
sahilmgandhi	18:6a4db94011d3	10999	#define EADC_AD0TRGEN1_EPWM14CEN_Pos (23) /!< EADC AD0TRGEN1: EPWM14CEN Position /
sahilmgandhi	18:6a4db94011d3	11000	#define EADC_AD0TRGEN1_EPWM14CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM14CEN_Pos) /!< EADC AD0TRGEN1: EPWM14CEN Mask /
sahilmgandhi	18:6a4db94011d3	11001
sahilmgandhi	18:6a4db94011d3	11002	#define EADC_AD0TRGEN1_PWM00REN_Pos (24) /!< EADC AD0TRGEN1: PWM00REN Position /
sahilmgandhi	18:6a4db94011d3	11003	#define EADC_AD0TRGEN1_PWM00REN_Msk (0x1ul << EADC_AD0TRGEN1_PWM00REN_Pos) /!< EADC AD0TRGEN1: PWM00REN Mask /
sahilmgandhi	18:6a4db94011d3	11004
sahilmgandhi	18:6a4db94011d3	11005	#define EADC_AD0TRGEN1_PWM00FEN_Pos (25) /!< EADC AD0TRGEN1: PWM00FEN Position /
sahilmgandhi	18:6a4db94011d3	11006	#define EADC_AD0TRGEN1_PWM00FEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM00FEN_Pos) /!< EADC AD0TRGEN1: PWM00FEN Mask /
sahilmgandhi	18:6a4db94011d3	11007
sahilmgandhi	18:6a4db94011d3	11008	#define EADC_AD0TRGEN1_PWM00PEN_Pos (26) /!< EADC AD0TRGEN1: PWM00PEN Position /
sahilmgandhi	18:6a4db94011d3	11009	#define EADC_AD0TRGEN1_PWM00PEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM00PEN_Pos) /!< EADC AD0TRGEN1: PWM00PEN Mask /
sahilmgandhi	18:6a4db94011d3	11010
sahilmgandhi	18:6a4db94011d3	11011	#define EADC_AD0TRGEN1_PWM00CEN_Pos (27) /!< EADC AD0TRGEN1: PWM00CEN Position /
sahilmgandhi	18:6a4db94011d3	11012	#define EADC_AD0TRGEN1_PWM00CEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM00CEN_Pos) /!< EADC AD0TRGEN1: PWM00CEN Mask /
sahilmgandhi	18:6a4db94011d3	11013
sahilmgandhi	18:6a4db94011d3	11014	#define EADC_AD0TRGEN1_PWM01REN_Pos (28) /!< EADC AD0TRGEN1: PWM01REN Position /
sahilmgandhi	18:6a4db94011d3	11015	#define EADC_AD0TRGEN1_PWM01REN_Msk (0x1ul << EADC_AD0TRGEN1_PWM01REN_Pos) /!< EADC AD0TRGEN1: PWM01REN Mask /
sahilmgandhi	18:6a4db94011d3	11016
sahilmgandhi	18:6a4db94011d3	11017	#define EADC_AD0TRGEN1_PWM01FEN_Pos (29) /!< EADC AD0TRGEN1: PWM01FEN Position /
sahilmgandhi	18:6a4db94011d3	11018	#define EADC_AD0TRGEN1_PWM01FEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM01FEN_Pos) /!< EADC AD0TRGEN1: PWM01FEN Mask /
sahilmgandhi	18:6a4db94011d3	11019
sahilmgandhi	18:6a4db94011d3	11020	#define EADC_AD0TRGEN1_PWM01PEN_Pos (30) /!< EADC AD0TRGEN1: PWM01PEN Position /
sahilmgandhi	18:6a4db94011d3	11021	#define EADC_AD0TRGEN1_PWM01PEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM01PEN_Pos) /!< EADC AD0TRGEN1: PWM01PEN Mask /
sahilmgandhi	18:6a4db94011d3	11022
sahilmgandhi	18:6a4db94011d3	11023	#define EADC_AD0TRGEN1_PWM01CEN_Pos (31) /!< EADC AD0TRGEN1: PWM01CEN Position /
sahilmgandhi	18:6a4db94011d3	11024	#define EADC_AD0TRGEN1_PWM01CEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM01CEN_Pos) /!< EADC AD0TRGEN1: PWM01CEN Mask /
sahilmgandhi	18:6a4db94011d3	11025
sahilmgandhi	18:6a4db94011d3	11026	#define EADC_AD0TRGEN2_EPWM00REN_Pos (0) /!< EADC AD0TRGEN2: EPWM00REN Position /
sahilmgandhi	18:6a4db94011d3	11027	#define EADC_AD0TRGEN2_EPWM00REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM00REN_Pos) /!< EADC AD0TRGEN2: EPWM00REN Mask /
sahilmgandhi	18:6a4db94011d3	11028
sahilmgandhi	18:6a4db94011d3	11029	#define EADC_AD0TRGEN2_EPWM00FEN_Pos (1) /!< EADC AD0TRGEN2: EPWM00FEN Position /
sahilmgandhi	18:6a4db94011d3	11030	#define EADC_AD0TRGEN2_EPWM00FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM00FEN_Pos) /!< EADC AD0TRGEN2: EPWM00FEN Mask /
sahilmgandhi	18:6a4db94011d3	11031
sahilmgandhi	18:6a4db94011d3	11032	#define EADC_AD0TRGEN2_EPWM00PEN_Pos (2) /!< EADC AD0TRGEN2: EPWM00PEN Position /
sahilmgandhi	18:6a4db94011d3	11033	#define EADC_AD0TRGEN2_EPWM00PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM00PEN_Pos) /!< EADC AD0TRGEN2: EPWM00PEN Mask /
sahilmgandhi	18:6a4db94011d3	11034
sahilmgandhi	18:6a4db94011d3	11035	#define EADC_AD0TRGEN2_EPWM00CEN_Pos (3) /!< EADC AD0TRGEN2: EPWM00CEN Position /
sahilmgandhi	18:6a4db94011d3	11036	#define EADC_AD0TRGEN2_EPWM00CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM00CEN_Pos) /!< EADC AD0TRGEN2: EPWM00CEN Mask /
sahilmgandhi	18:6a4db94011d3	11037
sahilmgandhi	18:6a4db94011d3	11038	#define EADC_AD0TRGEN2_EPWM02REN_Pos (4) /!< EADC AD0TRGEN2: EPWM02REN Position /
sahilmgandhi	18:6a4db94011d3	11039	#define EADC_AD0TRGEN2_EPWM02REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM02REN_Pos) /!< EADC AD0TRGEN2: EPWM02REN Mask /
sahilmgandhi	18:6a4db94011d3	11040
sahilmgandhi	18:6a4db94011d3	11041	#define EADC_AD0TRGEN2_EPWM02FEN_Pos (5) /!< EADC AD0TRGEN2: EPWM02FEN Position /
sahilmgandhi	18:6a4db94011d3	11042	#define EADC_AD0TRGEN2_EPWM02FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM02FEN_Pos) /!< EADC AD0TRGEN2: EPWM02FEN Mask /
sahilmgandhi	18:6a4db94011d3	11043
sahilmgandhi	18:6a4db94011d3	11044	#define EADC_AD0TRGEN2_EPWM02PEN_Pos (6) /!< EADC AD0TRGEN2: EPWM02PEN Position /
sahilmgandhi	18:6a4db94011d3	11045	#define EADC_AD0TRGEN2_EPWM02PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM02PEN_Pos) /!< EADC AD0TRGEN2: EPWM02PEN Mask /
sahilmgandhi	18:6a4db94011d3	11046
sahilmgandhi	18:6a4db94011d3	11047	#define EADC_AD0TRGEN2_EPWM02CEN_Pos (7) /!< EADC AD0TRGEN2: EPWM02CEN Position /
sahilmgandhi	18:6a4db94011d3	11048	#define EADC_AD0TRGEN2_EPWM02CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM02CEN_Pos) /!< EADC AD0TRGEN2: EPWM02CEN Mask /
sahilmgandhi	18:6a4db94011d3	11049
sahilmgandhi	18:6a4db94011d3	11050	#define EADC_AD0TRGEN2_EPWM04REN_Pos (8) /!< EADC AD0TRGEN2: EPWM04REN Position /
sahilmgandhi	18:6a4db94011d3	11051	#define EADC_AD0TRGEN2_EPWM04REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM04REN_Pos) /!< EADC AD0TRGEN2: EPWM04REN Mask /
sahilmgandhi	18:6a4db94011d3	11052
sahilmgandhi	18:6a4db94011d3	11053	#define EADC_AD0TRGEN2_EPWM04FEN_Pos (9) /!< EADC AD0TRGEN2: EPWM04FEN Position /
sahilmgandhi	18:6a4db94011d3	11054	#define EADC_AD0TRGEN2_EPWM04FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM04FEN_Pos) /!< EADC AD0TRGEN2: EPWM04FEN Mask /
sahilmgandhi	18:6a4db94011d3	11055
sahilmgandhi	18:6a4db94011d3	11056	#define EADC_AD0TRGEN2_EPWM04PEN_Pos (10) /!< EADC AD0TRGEN2: EPWM04PEN Position /
sahilmgandhi	18:6a4db94011d3	11057	#define EADC_AD0TRGEN2_EPWM04PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM04PEN_Pos) /!< EADC AD0TRGEN2: EPWM04PEN Mask /
sahilmgandhi	18:6a4db94011d3	11058
sahilmgandhi	18:6a4db94011d3	11059	#define EADC_AD0TRGEN2_EPWM04CEN_Pos (11) /!< EADC AD0TRGEN2: EPWM04CEN Position /
sahilmgandhi	18:6a4db94011d3	11060	#define EADC_AD0TRGEN2_EPWM04CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM04CEN_Pos) /!< EADC AD0TRGEN2: EPWM04CEN Mask /
sahilmgandhi	18:6a4db94011d3	11061
sahilmgandhi	18:6a4db94011d3	11062	#define EADC_AD0TRGEN2_EPWM10REN_Pos (12) /!< EADC AD0TRGEN2: EPWM10REN Position /
sahilmgandhi	18:6a4db94011d3	11063	#define EADC_AD0TRGEN2_EPWM10REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM10REN_Pos) /!< EADC AD0TRGEN2: EPWM10REN Mask /
sahilmgandhi	18:6a4db94011d3	11064
sahilmgandhi	18:6a4db94011d3	11065	#define EADC_AD0TRGEN2_EPWM10FEN_Pos (13) /!< EADC AD0TRGEN2: EPWM10FEN Position /
sahilmgandhi	18:6a4db94011d3	11066	#define EADC_AD0TRGEN2_EPWM10FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM10FEN_Pos) /!< EADC AD0TRGEN2: EPWM10FEN Mask /
sahilmgandhi	18:6a4db94011d3	11067
sahilmgandhi	18:6a4db94011d3	11068	#define EADC_AD0TRGEN2_EPWM10PEN_Pos (14) /!< EADC AD0TRGEN2: EPWM10PEN Position /
sahilmgandhi	18:6a4db94011d3	11069	#define EADC_AD0TRGEN2_EPWM10PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM10PEN_Pos) /!< EADC AD0TRGEN2: EPWM10PEN Mask /
sahilmgandhi	18:6a4db94011d3	11070
sahilmgandhi	18:6a4db94011d3	11071	#define EADC_AD0TRGEN2_EPWM10CEN_Pos (15) /!< EADC AD0TRGEN2: EPWM10CEN Position /
sahilmgandhi	18:6a4db94011d3	11072	#define EADC_AD0TRGEN2_EPWM10CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM10CEN_Pos) /!< EADC AD0TRGEN2: EPWM10CEN Mask /
sahilmgandhi	18:6a4db94011d3	11073
sahilmgandhi	18:6a4db94011d3	11074	#define EADC_AD0TRGEN2_EPWM12REN_Pos (16) /!< EADC AD0TRGEN2: EPWM12REN Position /
sahilmgandhi	18:6a4db94011d3	11075	#define EADC_AD0TRGEN2_EPWM12REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM12REN_Pos) /!< EADC AD0TRGEN2: EPWM12REN Mask /
sahilmgandhi	18:6a4db94011d3	11076
sahilmgandhi	18:6a4db94011d3	11077	#define EADC_AD0TRGEN2_EPWM120FEN_Pos (17) /!< EADC AD0TRGEN2: EPWM120FEN Position /
sahilmgandhi	18:6a4db94011d3	11078	#define EADC_AD0TRGEN2_EPWM120FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM120FEN_Pos) /!< EADC AD0TRGEN2: EPWM120FEN Mask /
sahilmgandhi	18:6a4db94011d3	11079
sahilmgandhi	18:6a4db94011d3	11080	#define EADC_AD0TRGEN2_EPWM12PEN_Pos (18) /!< EADC AD0TRGEN2: EPWM12PEN Position /
sahilmgandhi	18:6a4db94011d3	11081	#define EADC_AD0TRGEN2_EPWM12PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM12PEN_Pos) /!< EADC AD0TRGEN2: EPWM12PEN Mask /
sahilmgandhi	18:6a4db94011d3	11082
sahilmgandhi	18:6a4db94011d3	11083	#define EADC_AD0TRGEN2_EPWM12CEN_Pos (19) /!< EADC AD0TRGEN2: EPWM12CEN Position /
sahilmgandhi	18:6a4db94011d3	11084	#define EADC_AD0TRGEN2_EPWM12CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM12CEN_Pos) /!< EADC AD0TRGEN2: EPWM12CEN Mask /
sahilmgandhi	18:6a4db94011d3	11085
sahilmgandhi	18:6a4db94011d3	11086	#define EADC_AD0TRGEN2_EPWM14REN_Pos (20) /!< EADC AD0TRGEN2: EPWM14REN Position /
sahilmgandhi	18:6a4db94011d3	11087	#define EADC_AD0TRGEN2_EPWM14REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM14REN_Pos) /!< EADC AD0TRGEN2: EPWM14REN Mask /
sahilmgandhi	18:6a4db94011d3	11088
sahilmgandhi	18:6a4db94011d3	11089	#define EADC_AD0TRGEN2_EPWM14FEN_Pos (21) /!< EADC AD0TRGEN2: EPWM14FEN Position /
sahilmgandhi	18:6a4db94011d3	11090	#define EADC_AD0TRGEN2_EPWM14FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM14FEN_Pos) /!< EADC AD0TRGEN2: EPWM14FEN Mask /
sahilmgandhi	18:6a4db94011d3	11091
sahilmgandhi	18:6a4db94011d3	11092	#define EADC_AD0TRGEN2_EPWM14PEN_Pos (22) /!< EADC AD0TRGEN2: EPWM14PEN Position /
sahilmgandhi	18:6a4db94011d3	11093	#define EADC_AD0TRGEN2_EPWM14PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM14PEN_Pos) /!< EADC AD0TRGEN2: EPWM14PEN Mask /
sahilmgandhi	18:6a4db94011d3	11094
sahilmgandhi	18:6a4db94011d3	11095	#define EADC_AD0TRGEN2_EPWM14CEN_Pos (23) /!< EADC AD0TRGEN2: EPWM14CEN Position /
sahilmgandhi	18:6a4db94011d3	11096	#define EADC_AD0TRGEN2_EPWM14CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM14CEN_Pos) /!< EADC AD0TRGEN2: EPWM14CEN Mask /
sahilmgandhi	18:6a4db94011d3	11097
sahilmgandhi	18:6a4db94011d3	11098	#define EADC_AD0TRGEN2_PWM00REN_Pos (24) /!< EADC AD0TRGEN2: PWM00REN Position /
sahilmgandhi	18:6a4db94011d3	11099	#define EADC_AD0TRGEN2_PWM00REN_Msk (0x1ul << EADC_AD0TRGEN2_PWM00REN_Pos) /!< EADC AD0TRGEN2: PWM00REN Mask /
sahilmgandhi	18:6a4db94011d3	11100
sahilmgandhi	18:6a4db94011d3	11101	#define EADC_AD0TRGEN2_PWM00FEN_Pos (25) /!< EADC AD0TRGEN2: PWM00FEN Position /
sahilmgandhi	18:6a4db94011d3	11102	#define EADC_AD0TRGEN2_PWM00FEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM00FEN_Pos) /!< EADC AD0TRGEN2: PWM00FEN Mask /
sahilmgandhi	18:6a4db94011d3	11103
sahilmgandhi	18:6a4db94011d3	11104	#define EADC_AD0TRGEN2_PWM00PEN_Pos (26) /!< EADC AD0TRGEN2: PWM00PEN Position /
sahilmgandhi	18:6a4db94011d3	11105	#define EADC_AD0TRGEN2_PWM00PEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM00PEN_Pos) /!< EADC AD0TRGEN2: PWM00PEN Mask /
sahilmgandhi	18:6a4db94011d3	11106
sahilmgandhi	18:6a4db94011d3	11107	#define EADC_AD0TRGEN2_PWM00CEN_Pos (27) /!< EADC AD0TRGEN2: PWM00CEN Position /
sahilmgandhi	18:6a4db94011d3	11108	#define EADC_AD0TRGEN2_PWM00CEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM00CEN_Pos) /!< EADC AD0TRGEN2: PWM00CEN Mask /
sahilmgandhi	18:6a4db94011d3	11109
sahilmgandhi	18:6a4db94011d3	11110	#define EADC_AD0TRGEN2_PWM01REN_Pos (28) /!< EADC AD0TRGEN2: PWM01REN Position /
sahilmgandhi	18:6a4db94011d3	11111	#define EADC_AD0TRGEN2_PWM01REN_Msk (0x1ul << EADC_AD0TRGEN2_PWM01REN_Pos) /!< EADC AD0TRGEN2: PWM01REN Mask /
sahilmgandhi	18:6a4db94011d3	11112
sahilmgandhi	18:6a4db94011d3	11113	#define EADC_AD0TRGEN2_PWM01FEN_Pos (29) /!< EADC AD0TRGEN2: PWM01FEN Position /
sahilmgandhi	18:6a4db94011d3	11114	#define EADC_AD0TRGEN2_PWM01FEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM01FEN_Pos) /!< EADC AD0TRGEN2: PWM01FEN Mask /
sahilmgandhi	18:6a4db94011d3	11115
sahilmgandhi	18:6a4db94011d3	11116	#define EADC_AD0TRGEN2_PWM01PEN_Pos (30) /!< EADC AD0TRGEN2: PWM01PEN Position /
sahilmgandhi	18:6a4db94011d3	11117	#define EADC_AD0TRGEN2_PWM01PEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM01PEN_Pos) /!< EADC AD0TRGEN2: PWM01PEN Mask /
sahilmgandhi	18:6a4db94011d3	11118
sahilmgandhi	18:6a4db94011d3	11119	#define EADC_AD0TRGEN2_PWM01CEN_Pos (31) /!< EADC AD0TRGEN2: PWM01CEN Position /
sahilmgandhi	18:6a4db94011d3	11120	#define EADC_AD0TRGEN2_PWM01CEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM01CEN_Pos) /!< EADC AD0TRGEN2: PWM01CEN Mask /
sahilmgandhi	18:6a4db94011d3	11121
sahilmgandhi	18:6a4db94011d3	11122	#define EADC_AD0TRGEN3_EPWM00REN_Pos (0) /!< EADC AD0TRGEN3: EPWM00REN Position /
sahilmgandhi	18:6a4db94011d3	11123	#define EADC_AD0TRGEN3_EPWM00REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM00REN_Pos) /!< EADC AD0TRGEN3: EPWM00REN Mask /
sahilmgandhi	18:6a4db94011d3	11124
sahilmgandhi	18:6a4db94011d3	11125	#define EADC_AD0TRGEN3_EPWM00FEN_Pos (1) /!< EADC AD0TRGEN3: EPWM00FEN Position /
sahilmgandhi	18:6a4db94011d3	11126	#define EADC_AD0TRGEN3_EPWM00FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM00FEN_Pos) /!< EADC AD0TRGEN3: EPWM00FEN Mask /
sahilmgandhi	18:6a4db94011d3	11127
sahilmgandhi	18:6a4db94011d3	11128	#define EADC_AD0TRGEN3_EPWM00PEN_Pos (2) /!< EADC AD0TRGEN3: EPWM00PEN Position /
sahilmgandhi	18:6a4db94011d3	11129	#define EADC_AD0TRGEN3_EPWM00PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM00PEN_Pos) /!< EADC AD0TRGEN3: EPWM00PEN Mask /
sahilmgandhi	18:6a4db94011d3	11130
sahilmgandhi	18:6a4db94011d3	11131	#define EADC_AD0TRGEN3_EPWM00CEN_Pos (3) /!< EADC AD0TRGEN3: EPWM00CEN Position /
sahilmgandhi	18:6a4db94011d3	11132	#define EADC_AD0TRGEN3_EPWM00CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM00CEN_Pos) /!< EADC AD0TRGEN3: EPWM00CEN Mask /
sahilmgandhi	18:6a4db94011d3	11133
sahilmgandhi	18:6a4db94011d3	11134	#define EADC_AD0TRGEN3_EPWM02REN_Pos (4) /!< EADC AD0TRGEN3: EPWM02REN Position /
sahilmgandhi	18:6a4db94011d3	11135	#define EADC_AD0TRGEN3_EPWM02REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM02REN_Pos) /!< EADC AD0TRGEN3: EPWM02REN Mask /
sahilmgandhi	18:6a4db94011d3	11136
sahilmgandhi	18:6a4db94011d3	11137	#define EADC_AD0TRGEN3_EPWM02FEN_Pos (5) /!< EADC AD0TRGEN3: EPWM02FEN Position /
sahilmgandhi	18:6a4db94011d3	11138	#define EADC_AD0TRGEN3_EPWM02FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM02FEN_Pos) /!< EADC AD0TRGEN3: EPWM02FEN Mask /
sahilmgandhi	18:6a4db94011d3	11139
sahilmgandhi	18:6a4db94011d3	11140	#define EADC_AD0TRGEN3_EPWM02PEN_Pos (6) /!< EADC AD0TRGEN3: EPWM02PEN Position /
sahilmgandhi	18:6a4db94011d3	11141	#define EADC_AD0TRGEN3_EPWM02PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM02PEN_Pos) /!< EADC AD0TRGEN3: EPWM02PEN Mask /
sahilmgandhi	18:6a4db94011d3	11142
sahilmgandhi	18:6a4db94011d3	11143	#define EADC_AD0TRGEN3_EPWM02CEN_Pos (7) /!< EADC AD0TRGEN3: EPWM02CEN Position /
sahilmgandhi	18:6a4db94011d3	11144	#define EADC_AD0TRGEN3_EPWM02CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM02CEN_Pos) /!< EADC AD0TRGEN3: EPWM02CEN Mask /
sahilmgandhi	18:6a4db94011d3	11145
sahilmgandhi	18:6a4db94011d3	11146	#define EADC_AD0TRGEN3_EPWM04REN_Pos (8) /!< EADC AD0TRGEN3: EPWM04REN Position /
sahilmgandhi	18:6a4db94011d3	11147	#define EADC_AD0TRGEN3_EPWM04REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM04REN_Pos) /!< EADC AD0TRGEN3: EPWM04REN Mask /
sahilmgandhi	18:6a4db94011d3	11148
sahilmgandhi	18:6a4db94011d3	11149	#define EADC_AD0TRGEN3_EPWM04FEN_Pos (9) /!< EADC AD0TRGEN3: EPWM04FEN Position /
sahilmgandhi	18:6a4db94011d3	11150	#define EADC_AD0TRGEN3_EPWM04FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM04FEN_Pos) /!< EADC AD0TRGEN3: EPWM04FEN Mask /
sahilmgandhi	18:6a4db94011d3	11151
sahilmgandhi	18:6a4db94011d3	11152	#define EADC_AD0TRGEN3_EPWM04PEN_Pos (10) /!< EADC AD0TRGEN3: EPWM04PEN Position /
sahilmgandhi	18:6a4db94011d3	11153	#define EADC_AD0TRGEN3_EPWM04PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM04PEN_Pos) /!< EADC AD0TRGEN3: EPWM04PEN Mask /
sahilmgandhi	18:6a4db94011d3	11154
sahilmgandhi	18:6a4db94011d3	11155	#define EADC_AD0TRGEN3_EPWM04CEN_Pos (11) /!< EADC AD0TRGEN3: EPWM04CEN Position /
sahilmgandhi	18:6a4db94011d3	11156	#define EADC_AD0TRGEN3_EPWM04CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM04CEN_Pos) /!< EADC AD0TRGEN3: EPWM04CEN Mask /
sahilmgandhi	18:6a4db94011d3	11157
sahilmgandhi	18:6a4db94011d3	11158	#define EADC_AD0TRGEN3_EPWM10REN_Pos (12) /!< EADC AD0TRGEN3: EPWM10REN Position /
sahilmgandhi	18:6a4db94011d3	11159	#define EADC_AD0TRGEN3_EPWM10REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM10REN_Pos) /!< EADC AD0TRGEN3: EPWM10REN Mask /
sahilmgandhi	18:6a4db94011d3	11160
sahilmgandhi	18:6a4db94011d3	11161	#define EADC_AD0TRGEN3_EPWM10FEN_Pos (13) /!< EADC AD0TRGEN3: EPWM10FEN Position /
sahilmgandhi	18:6a4db94011d3	11162	#define EADC_AD0TRGEN3_EPWM10FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM10FEN_Pos) /!< EADC AD0TRGEN3: EPWM10FEN Mask /
sahilmgandhi	18:6a4db94011d3	11163
sahilmgandhi	18:6a4db94011d3	11164	#define EADC_AD0TRGEN3_EPWM10PEN_Pos (14) /!< EADC AD0TRGEN3: EPWM10PEN Position /
sahilmgandhi	18:6a4db94011d3	11165	#define EADC_AD0TRGEN3_EPWM10PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM10PEN_Pos) /!< EADC AD0TRGEN3: EPWM10PEN Mask /
sahilmgandhi	18:6a4db94011d3	11166
sahilmgandhi	18:6a4db94011d3	11167	#define EADC_AD0TRGEN3_EPWM10CEN_Pos (15) /!< EADC AD0TRGEN3: EPWM10CEN Position /
sahilmgandhi	18:6a4db94011d3	11168	#define EADC_AD0TRGEN3_EPWM10CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM10CEN_Pos) /!< EADC AD0TRGEN3: EPWM10CEN Mask /
sahilmgandhi	18:6a4db94011d3	11169
sahilmgandhi	18:6a4db94011d3	11170	#define EADC_AD0TRGEN3_EPWM12REN_Pos (16) /!< EADC AD0TRGEN3: EPWM12REN Position /
sahilmgandhi	18:6a4db94011d3	11171	#define EADC_AD0TRGEN3_EPWM12REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM12REN_Pos) /!< EADC AD0TRGEN3: EPWM12REN Mask /
sahilmgandhi	18:6a4db94011d3	11172
sahilmgandhi	18:6a4db94011d3	11173	#define EADC_AD0TRGEN3_EPWM120FEN_Pos (17) /!< EADC AD0TRGEN3: EPWM120FEN Position /
sahilmgandhi	18:6a4db94011d3	11174	#define EADC_AD0TRGEN3_EPWM120FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM120FEN_Pos) /!< EADC AD0TRGEN3: EPWM120FEN Mask /
sahilmgandhi	18:6a4db94011d3	11175
sahilmgandhi	18:6a4db94011d3	11176	#define EADC_AD0TRGEN3_EPWM12PEN_Pos (18) /!< EADC AD0TRGEN3: EPWM12PEN Position /
sahilmgandhi	18:6a4db94011d3	11177	#define EADC_AD0TRGEN3_EPWM12PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM12PEN_Pos) /!< EADC AD0TRGEN3: EPWM12PEN Mask /
sahilmgandhi	18:6a4db94011d3	11178
sahilmgandhi	18:6a4db94011d3	11179	#define EADC_AD0TRGEN3_EPWM12CEN_Pos (19) /!< EADC AD0TRGEN3: EPWM12CEN Position /
sahilmgandhi	18:6a4db94011d3	11180	#define EADC_AD0TRGEN3_EPWM12CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM12CEN_Pos) /!< EADC AD0TRGEN3: EPWM12CEN Mask /
sahilmgandhi	18:6a4db94011d3	11181
sahilmgandhi	18:6a4db94011d3	11182	#define EADC_AD0TRGEN3_EPWM14REN_Pos (20) /!< EADC AD0TRGEN3: EPWM14REN Position /
sahilmgandhi	18:6a4db94011d3	11183	#define EADC_AD0TRGEN3_EPWM14REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM14REN_Pos) /!< EADC AD0TRGEN3: EPWM14REN Mask /
sahilmgandhi	18:6a4db94011d3	11184
sahilmgandhi	18:6a4db94011d3	11185	#define EADC_AD0TRGEN3_EPWM14FEN_Pos (21) /!< EADC AD0TRGEN3: EPWM14FEN Position /
sahilmgandhi	18:6a4db94011d3	11186	#define EADC_AD0TRGEN3_EPWM14FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM14FEN_Pos) /!< EADC AD0TRGEN3: EPWM14FEN Mask /
sahilmgandhi	18:6a4db94011d3	11187
sahilmgandhi	18:6a4db94011d3	11188	#define EADC_AD0TRGEN3_EPWM14PEN_Pos (22) /!< EADC AD0TRGEN3: EPWM14PEN Position /
sahilmgandhi	18:6a4db94011d3	11189	#define EADC_AD0TRGEN3_EPWM14PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM14PEN_Pos) /!< EADC AD0TRGEN3: EPWM14PEN Mask /
sahilmgandhi	18:6a4db94011d3	11190
sahilmgandhi	18:6a4db94011d3	11191	#define EADC_AD0TRGEN3_EPWM14CEN_Pos (23) /!< EADC AD0TRGEN3: EPWM14CEN Position /
sahilmgandhi	18:6a4db94011d3	11192	#define EADC_AD0TRGEN3_EPWM14CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM14CEN_Pos) /!< EADC AD0TRGEN3: EPWM14CEN Mask /
sahilmgandhi	18:6a4db94011d3	11193
sahilmgandhi	18:6a4db94011d3	11194	#define EADC_AD0TRGEN3_PWM00REN_Pos (24) /!< EADC AD0TRGEN3: PWM00REN Position /
sahilmgandhi	18:6a4db94011d3	11195	#define EADC_AD0TRGEN3_PWM00REN_Msk (0x1ul << EADC_AD0TRGEN3_PWM00REN_Pos) /!< EADC AD0TRGEN3: PWM00REN Mask /
sahilmgandhi	18:6a4db94011d3	11196
sahilmgandhi	18:6a4db94011d3	11197	#define EADC_AD0TRGEN3_PWM00FEN_Pos (25) /!< EADC AD0TRGEN3: PWM00FEN Position /
sahilmgandhi	18:6a4db94011d3	11198	#define EADC_AD0TRGEN3_PWM00FEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM00FEN_Pos) /!< EADC AD0TRGEN3: PWM00FEN Mask /
sahilmgandhi	18:6a4db94011d3	11199
sahilmgandhi	18:6a4db94011d3	11200	#define EADC_AD0TRGEN3_PWM00PEN_Pos (26) /!< EADC AD0TRGEN3: PWM00PEN Position /
sahilmgandhi	18:6a4db94011d3	11201	#define EADC_AD0TRGEN3_PWM00PEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM00PEN_Pos) /!< EADC AD0TRGEN3: PWM00PEN Mask /
sahilmgandhi	18:6a4db94011d3	11202
sahilmgandhi	18:6a4db94011d3	11203	#define EADC_AD0TRGEN3_PWM00CEN_Pos (27) /!< EADC AD0TRGEN3: PWM00CEN Position /
sahilmgandhi	18:6a4db94011d3	11204	#define EADC_AD0TRGEN3_PWM00CEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM00CEN_Pos) /!< EADC AD0TRGEN3: PWM00CEN Mask /
sahilmgandhi	18:6a4db94011d3	11205
sahilmgandhi	18:6a4db94011d3	11206	#define EADC_AD0TRGEN3_PWM01REN_Pos (28) /!< EADC AD0TRGEN3: PWM01REN Position /
sahilmgandhi	18:6a4db94011d3	11207	#define EADC_AD0TRGEN3_PWM01REN_Msk (0x1ul << EADC_AD0TRGEN3_PWM01REN_Pos) /!< EADC AD0TRGEN3: PWM01REN Mask /
sahilmgandhi	18:6a4db94011d3	11208
sahilmgandhi	18:6a4db94011d3	11209	#define EADC_AD0TRGEN3_PWM01FEN_Pos (29) /!< EADC AD0TRGEN3: PWM01FEN Position /
sahilmgandhi	18:6a4db94011d3	11210	#define EADC_AD0TRGEN3_PWM01FEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM01FEN_Pos) /!< EADC AD0TRGEN3: PWM01FEN Mask /
sahilmgandhi	18:6a4db94011d3	11211
sahilmgandhi	18:6a4db94011d3	11212	#define EADC_AD0TRGEN3_PWM01PEN_Pos (30) /!< EADC AD0TRGEN3: PWM01PEN Position /
sahilmgandhi	18:6a4db94011d3	11213	#define EADC_AD0TRGEN3_PWM01PEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM01PEN_Pos) /!< EADC AD0TRGEN3: PWM01PEN Mask /
sahilmgandhi	18:6a4db94011d3	11214
sahilmgandhi	18:6a4db94011d3	11215	#define EADC_AD0TRGEN3_PWM01CEN_Pos (31) /!< EADC AD0TRGEN3: PWM01CEN Position /
sahilmgandhi	18:6a4db94011d3	11216	#define EADC_AD0TRGEN3_PWM01CEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM01CEN_Pos) /!< EADC AD0TRGEN3: PWM01CEN Mask /
sahilmgandhi	18:6a4db94011d3	11217
sahilmgandhi	18:6a4db94011d3	11218	#define EADC_AD1TRGEN0_EPWM00REN_Pos (0) /!< EADC AD1TRGEN0: EPWM00REN Position /
sahilmgandhi	18:6a4db94011d3	11219	#define EADC_AD1TRGEN0_EPWM00REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM00REN_Pos) /!< EADC AD1TRGEN0: EPWM00REN Mask /
sahilmgandhi	18:6a4db94011d3	11220
sahilmgandhi	18:6a4db94011d3	11221	#define EADC_AD1TRGEN0_EPWM00FEN_Pos (1) /!< EADC AD1TRGEN0: EPWM00FEN Position /
sahilmgandhi	18:6a4db94011d3	11222	#define EADC_AD1TRGEN0_EPWM00FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM00FEN_Pos) /!< EADC AD1TRGEN0: EPWM00FEN Mask /
sahilmgandhi	18:6a4db94011d3	11223
sahilmgandhi	18:6a4db94011d3	11224	#define EADC_AD1TRGEN0_EPWM00PEN_Pos (2) /!< EADC AD1TRGEN0: EPWM00PEN Position /
sahilmgandhi	18:6a4db94011d3	11225	#define EADC_AD1TRGEN0_EPWM00PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM00PEN_Pos) /!< EADC AD1TRGEN0: EPWM00PEN Mask /
sahilmgandhi	18:6a4db94011d3	11226
sahilmgandhi	18:6a4db94011d3	11227	#define EADC_AD1TRGEN0_EPWM00CEN_Pos (3) /!< EADC AD1TRGEN0: EPWM00CEN Position /
sahilmgandhi	18:6a4db94011d3	11228	#define EADC_AD1TRGEN0_EPWM00CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM00CEN_Pos) /!< EADC AD1TRGEN0: EPWM00CEN Mask /
sahilmgandhi	18:6a4db94011d3	11229
sahilmgandhi	18:6a4db94011d3	11230	#define EADC_AD1TRGEN0_EPWM02REN_Pos (4) /!< EADC AD1TRGEN0: EPWM02REN Position /
sahilmgandhi	18:6a4db94011d3	11231	#define EADC_AD1TRGEN0_EPWM02REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM02REN_Pos) /!< EADC AD1TRGEN0: EPWM02REN Mask /
sahilmgandhi	18:6a4db94011d3	11232
sahilmgandhi	18:6a4db94011d3	11233	#define EADC_AD1TRGEN0_EPWM02FEN_Pos (5) /!< EADC AD1TRGEN0: EPWM02FEN Position /
sahilmgandhi	18:6a4db94011d3	11234	#define EADC_AD1TRGEN0_EPWM02FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM02FEN_Pos) /!< EADC AD1TRGEN0: EPWM02FEN Mask /
sahilmgandhi	18:6a4db94011d3	11235
sahilmgandhi	18:6a4db94011d3	11236	#define EADC_AD1TRGEN0_EPWM02PEN_Pos (6) /!< EADC AD1TRGEN0: EPWM02PEN Position /
sahilmgandhi	18:6a4db94011d3	11237	#define EADC_AD1TRGEN0_EPWM02PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM02PEN_Pos) /!< EADC AD1TRGEN0: EPWM02PEN Mask /
sahilmgandhi	18:6a4db94011d3	11238
sahilmgandhi	18:6a4db94011d3	11239	#define EADC_AD1TRGEN0_EPWM02CEN_Pos (7) /!< EADC AD1TRGEN0: EPWM02CEN Position /
sahilmgandhi	18:6a4db94011d3	11240	#define EADC_AD1TRGEN0_EPWM02CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM02CEN_Pos) /!< EADC AD1TRGEN0: EPWM02CEN Mask /
sahilmgandhi	18:6a4db94011d3	11241
sahilmgandhi	18:6a4db94011d3	11242	#define EADC_AD1TRGEN0_EPWM04REN_Pos (8) /!< EADC AD1TRGEN0: EPWM04REN Position /
sahilmgandhi	18:6a4db94011d3	11243	#define EADC_AD1TRGEN0_EPWM04REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM04REN_Pos) /!< EADC AD1TRGEN0: EPWM04REN Mask /
sahilmgandhi	18:6a4db94011d3	11244
sahilmgandhi	18:6a4db94011d3	11245	#define EADC_AD1TRGEN0_EPWM04FEN_Pos (9) /!< EADC AD1TRGEN0: EPWM04FEN Position /
sahilmgandhi	18:6a4db94011d3	11246	#define EADC_AD1TRGEN0_EPWM04FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM04FEN_Pos) /!< EADC AD1TRGEN0: EPWM04FEN Mask /
sahilmgandhi	18:6a4db94011d3	11247
sahilmgandhi	18:6a4db94011d3	11248	#define EADC_AD1TRGEN0_EPWM04PEN_Pos (10) /!< EADC AD1TRGEN0: EPWM04PEN Position /
sahilmgandhi	18:6a4db94011d3	11249	#define EADC_AD1TRGEN0_EPWM04PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM04PEN_Pos) /!< EADC AD1TRGEN0: EPWM04PEN Mask /
sahilmgandhi	18:6a4db94011d3	11250
sahilmgandhi	18:6a4db94011d3	11251	#define EADC_AD1TRGEN0_EPWM04CEN_Pos (11) /!< EADC AD1TRGEN0: EPWM04CEN Position /
sahilmgandhi	18:6a4db94011d3	11252	#define EADC_AD1TRGEN0_EPWM04CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM04CEN_Pos) /!< EADC AD1TRGEN0: EPWM04CEN Mask /
sahilmgandhi	18:6a4db94011d3	11253
sahilmgandhi	18:6a4db94011d3	11254	#define EADC_AD1TRGEN0_EPWM10REN_Pos (12) /!< EADC AD1TRGEN0: EPWM10REN Position /
sahilmgandhi	18:6a4db94011d3	11255	#define EADC_AD1TRGEN0_EPWM10REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM10REN_Pos) /!< EADC AD1TRGEN0: EPWM10REN Mask /
sahilmgandhi	18:6a4db94011d3	11256
sahilmgandhi	18:6a4db94011d3	11257	#define EADC_AD1TRGEN0_EPWM10FEN_Pos (13) /!< EADC AD1TRGEN0: EPWM10FEN Position /
sahilmgandhi	18:6a4db94011d3	11258	#define EADC_AD1TRGEN0_EPWM10FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM10FEN_Pos) /!< EADC AD1TRGEN0: EPWM10FEN Mask /
sahilmgandhi	18:6a4db94011d3	11259
sahilmgandhi	18:6a4db94011d3	11260	#define EADC_AD1TRGEN0_EPWM10PEN_Pos (14) /!< EADC AD1TRGEN0: EPWM10PEN Position /
sahilmgandhi	18:6a4db94011d3	11261	#define EADC_AD1TRGEN0_EPWM10PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM10PEN_Pos) /!< EADC AD1TRGEN0: EPWM10PEN Mask /
sahilmgandhi	18:6a4db94011d3	11262
sahilmgandhi	18:6a4db94011d3	11263	#define EADC_AD1TRGEN0_EPWM10CEN_Pos (15) /!< EADC AD1TRGEN0: EPWM10CEN Position /
sahilmgandhi	18:6a4db94011d3	11264	#define EADC_AD1TRGEN0_EPWM10CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM10CEN_Pos) /!< EADC AD1TRGEN0: EPWM10CEN Mask /
sahilmgandhi	18:6a4db94011d3	11265
sahilmgandhi	18:6a4db94011d3	11266	#define EADC_AD1TRGEN0_EPWM12REN_Pos (16) /!< EADC AD1TRGEN0: EPWM12REN Position /
sahilmgandhi	18:6a4db94011d3	11267	#define EADC_AD1TRGEN0_EPWM12REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM12REN_Pos) /!< EADC AD1TRGEN0: EPWM12REN Mask /
sahilmgandhi	18:6a4db94011d3	11268
sahilmgandhi	18:6a4db94011d3	11269	#define EADC_AD1TRGEN0_EPWM120FEN_Pos (17) /!< EADC AD1TRGEN0: EPWM120FEN Position /
sahilmgandhi	18:6a4db94011d3	11270	#define EADC_AD1TRGEN0_EPWM120FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM120FEN_Pos) /!< EADC AD1TRGEN0: EPWM120FEN Mask /
sahilmgandhi	18:6a4db94011d3	11271
sahilmgandhi	18:6a4db94011d3	11272	#define EADC_AD1TRGEN0_EPWM12PEN_Pos (18) /!< EADC AD1TRGEN0: EPWM12PEN Position /
sahilmgandhi	18:6a4db94011d3	11273	#define EADC_AD1TRGEN0_EPWM12PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM12PEN_Pos) /!< EADC AD1TRGEN0: EPWM12PEN Mask /
sahilmgandhi	18:6a4db94011d3	11274
sahilmgandhi	18:6a4db94011d3	11275	#define EADC_AD1TRGEN0_EPWM12CEN_Pos (19) /!< EADC AD1TRGEN0: EPWM12CEN Position /
sahilmgandhi	18:6a4db94011d3	11276	#define EADC_AD1TRGEN0_EPWM12CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM12CEN_Pos) /!< EADC AD1TRGEN0: EPWM12CEN Mask /
sahilmgandhi	18:6a4db94011d3	11277
sahilmgandhi	18:6a4db94011d3	11278	#define EADC_AD1TRGEN0_EPWM14REN_Pos (20) /!< EADC AD1TRGEN0: EPWM14REN Position /
sahilmgandhi	18:6a4db94011d3	11279	#define EADC_AD1TRGEN0_EPWM14REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM14REN_Pos) /!< EADC AD1TRGEN0: EPWM14REN Mask /
sahilmgandhi	18:6a4db94011d3	11280
sahilmgandhi	18:6a4db94011d3	11281	#define EADC_AD1TRGEN0_EPWM14FEN_Pos (21) /!< EADC AD1TRGEN0: EPWM14FEN Position /
sahilmgandhi	18:6a4db94011d3	11282	#define EADC_AD1TRGEN0_EPWM14FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM14FEN_Pos) /!< EADC AD1TRGEN0: EPWM14FEN Mask /
sahilmgandhi	18:6a4db94011d3	11283
sahilmgandhi	18:6a4db94011d3	11284	#define EADC_AD1TRGEN0_EPWM14PEN_Pos (22) /!< EADC AD1TRGEN0: EPWM14PEN Position /
sahilmgandhi	18:6a4db94011d3	11285	#define EADC_AD1TRGEN0_EPWM14PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM14PEN_Pos) /!< EADC AD1TRGEN0: EPWM14PEN Mask /
sahilmgandhi	18:6a4db94011d3	11286
sahilmgandhi	18:6a4db94011d3	11287	#define EADC_AD1TRGEN0_EPWM14CEN_Pos (23) /!< EADC AD1TRGEN0: EPWM14CEN Position /
sahilmgandhi	18:6a4db94011d3	11288	#define EADC_AD1TRGEN0_EPWM14CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM14CEN_Pos) /!< EADC AD1TRGEN0: EPWM14CEN Mask /
sahilmgandhi	18:6a4db94011d3	11289
sahilmgandhi	18:6a4db94011d3	11290	#define EADC_AD1TRGEN0_PWM00REN_Pos (24) /!< EADC AD1TRGEN0: PWM00REN Position /
sahilmgandhi	18:6a4db94011d3	11291	#define EADC_AD1TRGEN0_PWM00REN_Msk (0x1ul << EADC_AD1TRGEN0_PWM00REN_Pos) /!< EADC AD1TRGEN0: PWM00REN Mask /
sahilmgandhi	18:6a4db94011d3	11292
sahilmgandhi	18:6a4db94011d3	11293	#define EADC_AD1TRGEN0_PWM00FEN_Pos (25) /!< EADC AD1TRGEN0: PWM00FEN Position /
sahilmgandhi	18:6a4db94011d3	11294	#define EADC_AD1TRGEN0_PWM00FEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM00FEN_Pos) /!< EADC AD1TRGEN0: PWM00FEN Mask /
sahilmgandhi	18:6a4db94011d3	11295
sahilmgandhi	18:6a4db94011d3	11296	#define EADC_AD1TRGEN0_PWM00PEN_Pos (26) /!< EADC AD1TRGEN0: PWM00PEN Position /
sahilmgandhi	18:6a4db94011d3	11297	#define EADC_AD1TRGEN0_PWM00PEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM00PEN_Pos) /!< EADC AD1TRGEN0: PWM00PEN Mask /
sahilmgandhi	18:6a4db94011d3	11298
sahilmgandhi	18:6a4db94011d3	11299	#define EADC_AD1TRGEN0_PWM00CEN_Pos (27) /!< EADC AD1TRGEN0: PWM00CEN Position /
sahilmgandhi	18:6a4db94011d3	11300	#define EADC_AD1TRGEN0_PWM00CEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM00CEN_Pos) /!< EADC AD1TRGEN0: PWM00CEN Mask /
sahilmgandhi	18:6a4db94011d3	11301
sahilmgandhi	18:6a4db94011d3	11302	#define EADC_AD1TRGEN0_PWM01REN_Pos (28) /!< EADC AD1TRGEN0: PWM01REN Position /
sahilmgandhi	18:6a4db94011d3	11303	#define EADC_AD1TRGEN0_PWM01REN_Msk (0x1ul << EADC_AD1TRGEN0_PWM01REN_Pos) /!< EADC AD1TRGEN0: PWM01REN Mask /
sahilmgandhi	18:6a4db94011d3	11304
sahilmgandhi	18:6a4db94011d3	11305	#define EADC_AD1TRGEN0_PWM01FEN_Pos (29) /!< EADC AD1TRGEN0: PWM01FEN Position /
sahilmgandhi	18:6a4db94011d3	11306	#define EADC_AD1TRGEN0_PWM01FEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM01FEN_Pos) /!< EADC AD1TRGEN0: PWM01FEN Mask /
sahilmgandhi	18:6a4db94011d3	11307
sahilmgandhi	18:6a4db94011d3	11308	#define EADC_AD1TRGEN0_PWM01PEN_Pos (30) /!< EADC AD1TRGEN0: PWM01PEN Position /
sahilmgandhi	18:6a4db94011d3	11309	#define EADC_AD1TRGEN0_PWM01PEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM01PEN_Pos) /!< EADC AD1TRGEN0: PWM01PEN Mask /
sahilmgandhi	18:6a4db94011d3	11310
sahilmgandhi	18:6a4db94011d3	11311	#define EADC_AD1TRGEN0_PWM01CEN_Pos (31) /!< EADC AD1TRGEN0: PWM01CEN Position /
sahilmgandhi	18:6a4db94011d3	11312	#define EADC_AD1TRGEN0_PWM01CEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM01CEN_Pos) /!< EADC AD1TRGEN0: PWM01CEN Mask /
sahilmgandhi	18:6a4db94011d3	11313
sahilmgandhi	18:6a4db94011d3	11314	#define EADC_AD1TRGEN1_EPWM00REN_Pos (0) /!< EADC AD1TRGEN1: EPWM00REN Position /
sahilmgandhi	18:6a4db94011d3	11315	#define EADC_AD1TRGEN1_EPWM00REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM00REN_Pos) /!< EADC AD1TRGEN1: EPWM00REN Mask /
sahilmgandhi	18:6a4db94011d3	11316
sahilmgandhi	18:6a4db94011d3	11317	#define EADC_AD1TRGEN1_EPWM00FEN_Pos (1) /!< EADC AD1TRGEN1: EPWM00FEN Position /
sahilmgandhi	18:6a4db94011d3	11318	#define EADC_AD1TRGEN1_EPWM00FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM00FEN_Pos) /!< EADC AD1TRGEN1: EPWM00FEN Mask /
sahilmgandhi	18:6a4db94011d3	11319
sahilmgandhi	18:6a4db94011d3	11320	#define EADC_AD1TRGEN1_EPWM00PEN_Pos (2) /!< EADC AD1TRGEN1: EPWM00PEN Position /
sahilmgandhi	18:6a4db94011d3	11321	#define EADC_AD1TRGEN1_EPWM00PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM00PEN_Pos) /!< EADC AD1TRGEN1: EPWM00PEN Mask /
sahilmgandhi	18:6a4db94011d3	11322
sahilmgandhi	18:6a4db94011d3	11323	#define EADC_AD1TRGEN1_EPWM00CEN_Pos (3) /!< EADC AD1TRGEN1: EPWM00CEN Position /
sahilmgandhi	18:6a4db94011d3	11324	#define EADC_AD1TRGEN1_EPWM00CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM00CEN_Pos) /!< EADC AD1TRGEN1: EPWM00CEN Mask /
sahilmgandhi	18:6a4db94011d3	11325
sahilmgandhi	18:6a4db94011d3	11326	#define EADC_AD1TRGEN1_EPWM02REN_Pos (4) /!< EADC AD1TRGEN1: EPWM02REN Position /
sahilmgandhi	18:6a4db94011d3	11327	#define EADC_AD1TRGEN1_EPWM02REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM02REN_Pos) /!< EADC AD1TRGEN1: EPWM02REN Mask /
sahilmgandhi	18:6a4db94011d3	11328
sahilmgandhi	18:6a4db94011d3	11329	#define EADC_AD1TRGEN1_EPWM02FEN_Pos (5) /!< EADC AD1TRGEN1: EPWM02FEN Position /
sahilmgandhi	18:6a4db94011d3	11330	#define EADC_AD1TRGEN1_EPWM02FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM02FEN_Pos) /!< EADC AD1TRGEN1: EPWM02FEN Mask /
sahilmgandhi	18:6a4db94011d3	11331
sahilmgandhi	18:6a4db94011d3	11332	#define EADC_AD1TRGEN1_EPWM02PEN_Pos (6) /!< EADC AD1TRGEN1: EPWM02PEN Position /
sahilmgandhi	18:6a4db94011d3	11333	#define EADC_AD1TRGEN1_EPWM02PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM02PEN_Pos) /!< EADC AD1TRGEN1: EPWM02PEN Mask /
sahilmgandhi	18:6a4db94011d3	11334
sahilmgandhi	18:6a4db94011d3	11335	#define EADC_AD1TRGEN1_EPWM02CEN_Pos (7) /!< EADC AD1TRGEN1: EPWM02CEN Position /
sahilmgandhi	18:6a4db94011d3	11336	#define EADC_AD1TRGEN1_EPWM02CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM02CEN_Pos) /!< EADC AD1TRGEN1: EPWM02CEN Mask /
sahilmgandhi	18:6a4db94011d3	11337
sahilmgandhi	18:6a4db94011d3	11338	#define EADC_AD1TRGEN1_EPWM04REN_Pos (8) /!< EADC AD1TRGEN1: EPWM04REN Position /
sahilmgandhi	18:6a4db94011d3	11339	#define EADC_AD1TRGEN1_EPWM04REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM04REN_Pos) /!< EADC AD1TRGEN1: EPWM04REN Mask /
sahilmgandhi	18:6a4db94011d3	11340
sahilmgandhi	18:6a4db94011d3	11341	#define EADC_AD1TRGEN1_EPWM04FEN_Pos (9) /!< EADC AD1TRGEN1: EPWM04FEN Position /
sahilmgandhi	18:6a4db94011d3	11342	#define EADC_AD1TRGEN1_EPWM04FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM04FEN_Pos) /!< EADC AD1TRGEN1: EPWM04FEN Mask /
sahilmgandhi	18:6a4db94011d3	11343
sahilmgandhi	18:6a4db94011d3	11344	#define EADC_AD1TRGEN1_EPWM04PEN_Pos (10) /!< EADC AD1TRGEN1: EPWM04PEN Position /
sahilmgandhi	18:6a4db94011d3	11345	#define EADC_AD1TRGEN1_EPWM04PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM04PEN_Pos) /!< EADC AD1TRGEN1: EPWM04PEN Mask /
sahilmgandhi	18:6a4db94011d3	11346
sahilmgandhi	18:6a4db94011d3	11347	#define EADC_AD1TRGEN1_EPWM04CEN_Pos (11) /!< EADC AD1TRGEN1: EPWM04CEN Position /
sahilmgandhi	18:6a4db94011d3	11348	#define EADC_AD1TRGEN1_EPWM04CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM04CEN_Pos) /!< EADC AD1TRGEN1: EPWM04CEN Mask /
sahilmgandhi	18:6a4db94011d3	11349
sahilmgandhi	18:6a4db94011d3	11350	#define EADC_AD1TRGEN1_EPWM10REN_Pos (12) /!< EADC AD1TRGEN1: EPWM10REN Position /
sahilmgandhi	18:6a4db94011d3	11351	#define EADC_AD1TRGEN1_EPWM10REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM10REN_Pos) /!< EADC AD1TRGEN1: EPWM10REN Mask /
sahilmgandhi	18:6a4db94011d3	11352
sahilmgandhi	18:6a4db94011d3	11353	#define EADC_AD1TRGEN1_EPWM10FEN_Pos (13) /!< EADC AD1TRGEN1: EPWM10FEN Position /
sahilmgandhi	18:6a4db94011d3	11354	#define EADC_AD1TRGEN1_EPWM10FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM10FEN_Pos) /!< EADC AD1TRGEN1: EPWM10FEN Mask /
sahilmgandhi	18:6a4db94011d3	11355
sahilmgandhi	18:6a4db94011d3	11356	#define EADC_AD1TRGEN1_EPWM10PEN_Pos (14) /!< EADC AD1TRGEN1: EPWM10PEN Position /
sahilmgandhi	18:6a4db94011d3	11357	#define EADC_AD1TRGEN1_EPWM10PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM10PEN_Pos) /!< EADC AD1TRGEN1: EPWM10PEN Mask /
sahilmgandhi	18:6a4db94011d3	11358
sahilmgandhi	18:6a4db94011d3	11359	#define EADC_AD1TRGEN1_EPWM10CEN_Pos (15) /!< EADC AD1TRGEN1: EPWM10CEN Position /
sahilmgandhi	18:6a4db94011d3	11360	#define EADC_AD1TRGEN1_EPWM10CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM10CEN_Pos) /!< EADC AD1TRGEN1: EPWM10CEN Mask /
sahilmgandhi	18:6a4db94011d3	11361
sahilmgandhi	18:6a4db94011d3	11362	#define EADC_AD1TRGEN1_EPWM12REN_Pos (16) /!< EADC AD1TRGEN1: EPWM12REN Position /
sahilmgandhi	18:6a4db94011d3	11363	#define EADC_AD1TRGEN1_EPWM12REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM12REN_Pos) /!< EADC AD1TRGEN1: EPWM12REN Mask /
sahilmgandhi	18:6a4db94011d3	11364
sahilmgandhi	18:6a4db94011d3	11365	#define EADC_AD1TRGEN1_EPWM120FEN_Pos (17) /!< EADC AD1TRGEN1: EPWM120FEN Position /
sahilmgandhi	18:6a4db94011d3	11366	#define EADC_AD1TRGEN1_EPWM120FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM120FEN_Pos) /!< EADC AD1TRGEN1: EPWM120FEN Mask /
sahilmgandhi	18:6a4db94011d3	11367
sahilmgandhi	18:6a4db94011d3	11368	#define EADC_AD1TRGEN1_EPWM12PEN_Pos (18) /!< EADC AD1TRGEN1: EPWM12PEN Position /
sahilmgandhi	18:6a4db94011d3	11369	#define EADC_AD1TRGEN1_EPWM12PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM12PEN_Pos) /!< EADC AD1TRGEN1: EPWM12PEN Mask /
sahilmgandhi	18:6a4db94011d3	11370
sahilmgandhi	18:6a4db94011d3	11371	#define EADC_AD1TRGEN1_EPWM12CEN_Pos (19) /!< EADC AD1TRGEN1: EPWM12CEN Position /
sahilmgandhi	18:6a4db94011d3	11372	#define EADC_AD1TRGEN1_EPWM12CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM12CEN_Pos) /!< EADC AD1TRGEN1: EPWM12CEN Mask /
sahilmgandhi	18:6a4db94011d3	11373
sahilmgandhi	18:6a4db94011d3	11374	#define EADC_AD1TRGEN1_EPWM14REN_Pos (20) /!< EADC AD1TRGEN1: EPWM14REN Position /
sahilmgandhi	18:6a4db94011d3	11375	#define EADC_AD1TRGEN1_EPWM14REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM14REN_Pos) /!< EADC AD1TRGEN1: EPWM14REN Mask /
sahilmgandhi	18:6a4db94011d3	11376
sahilmgandhi	18:6a4db94011d3	11377	#define EADC_AD1TRGEN1_EPWM14FEN_Pos (21) /!< EADC AD1TRGEN1: EPWM14FEN Position /
sahilmgandhi	18:6a4db94011d3	11378	#define EADC_AD1TRGEN1_EPWM14FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM14FEN_Pos) /!< EADC AD1TRGEN1: EPWM14FEN Mask /
sahilmgandhi	18:6a4db94011d3	11379
sahilmgandhi	18:6a4db94011d3	11380	#define EADC_AD1TRGEN1_EPWM14PEN_Pos (22) /!< EADC AD1TRGEN1: EPWM14PEN Position /
sahilmgandhi	18:6a4db94011d3	11381	#define EADC_AD1TRGEN1_EPWM14PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM14PEN_Pos) /!< EADC AD1TRGEN1: EPWM14PEN Mask /
sahilmgandhi	18:6a4db94011d3	11382
sahilmgandhi	18:6a4db94011d3	11383	#define EADC_AD1TRGEN1_EPWM14CEN_Pos (23) /!< EADC AD1TRGEN1: EPWM14CEN Position /
sahilmgandhi	18:6a4db94011d3	11384	#define EADC_AD1TRGEN1_EPWM14CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM14CEN_Pos) /!< EADC AD1TRGEN1: EPWM14CEN Mask /
sahilmgandhi	18:6a4db94011d3	11385
sahilmgandhi	18:6a4db94011d3	11386	#define EADC_AD1TRGEN1_PWM00REN_Pos (24) /!< EADC AD1TRGEN1: PWM00REN Position /
sahilmgandhi	18:6a4db94011d3	11387	#define EADC_AD1TRGEN1_PWM00REN_Msk (0x1ul << EADC_AD1TRGEN1_PWM00REN_Pos) /!< EADC AD1TRGEN1: PWM00REN Mask /
sahilmgandhi	18:6a4db94011d3	11388
sahilmgandhi	18:6a4db94011d3	11389	#define EADC_AD1TRGEN1_PWM00FEN_Pos (25) /!< EADC AD1TRGEN1: PWM00FEN Position /
sahilmgandhi	18:6a4db94011d3	11390	#define EADC_AD1TRGEN1_PWM00FEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM00FEN_Pos) /!< EADC AD1TRGEN1: PWM00FEN Mask /
sahilmgandhi	18:6a4db94011d3	11391
sahilmgandhi	18:6a4db94011d3	11392	#define EADC_AD1TRGEN1_PWM00PEN_Pos (26) /!< EADC AD1TRGEN1: PWM00PEN Position /
sahilmgandhi	18:6a4db94011d3	11393	#define EADC_AD1TRGEN1_PWM00PEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM00PEN_Pos) /!< EADC AD1TRGEN1: PWM00PEN Mask /
sahilmgandhi	18:6a4db94011d3	11394
sahilmgandhi	18:6a4db94011d3	11395	#define EADC_AD1TRGEN1_PWM00CEN_Pos (27) /!< EADC AD1TRGEN1: PWM00CEN Position /
sahilmgandhi	18:6a4db94011d3	11396	#define EADC_AD1TRGEN1_PWM00CEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM00CEN_Pos) /!< EADC AD1TRGEN1: PWM00CEN Mask /
sahilmgandhi	18:6a4db94011d3	11397
sahilmgandhi	18:6a4db94011d3	11398	#define EADC_AD1TRGEN1_PWM01REN_Pos (28) /!< EADC AD1TRGEN1: PWM01REN Position /
sahilmgandhi	18:6a4db94011d3	11399	#define EADC_AD1TRGEN1_PWM01REN_Msk (0x1ul << EADC_AD1TRGEN1_PWM01REN_Pos) /!< EADC AD1TRGEN1: PWM01REN Mask /
sahilmgandhi	18:6a4db94011d3	11400
sahilmgandhi	18:6a4db94011d3	11401	#define EADC_AD1TRGEN1_PWM01FEN_Pos (29) /!< EADC AD1TRGEN1: PWM01FEN Position /
sahilmgandhi	18:6a4db94011d3	11402	#define EADC_AD1TRGEN1_PWM01FEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM01FEN_Pos) /!< EADC AD1TRGEN1: PWM01FEN Mask /
sahilmgandhi	18:6a4db94011d3	11403
sahilmgandhi	18:6a4db94011d3	11404	#define EADC_AD1TRGEN1_PWM01PEN_Pos (30) /!< EADC AD1TRGEN1: PWM01PEN Position /
sahilmgandhi	18:6a4db94011d3	11405	#define EADC_AD1TRGEN1_PWM01PEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM01PEN_Pos) /!< EADC AD1TRGEN1: PWM01PEN Mask /
sahilmgandhi	18:6a4db94011d3	11406
sahilmgandhi	18:6a4db94011d3	11407	#define EADC_AD1TRGEN1_PWM01CEN_Pos (31) /!< EADC AD1TRGEN1: PWM01CEN Position /
sahilmgandhi	18:6a4db94011d3	11408	#define EADC_AD1TRGEN1_PWM01CEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM01CEN_Pos) /!< EADC AD1TRGEN1: PWM01CEN Mask /
sahilmgandhi	18:6a4db94011d3	11409
sahilmgandhi	18:6a4db94011d3	11410	#define EADC_AD1TRGEN2_EPWM00REN_Pos (0) /!< EADC AD1TRGEN2: EPWM00REN Position /
sahilmgandhi	18:6a4db94011d3	11411	#define EADC_AD1TRGEN2_EPWM00REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM00REN_Pos) /!< EADC AD1TRGEN2: EPWM00REN Mask /
sahilmgandhi	18:6a4db94011d3	11412
sahilmgandhi	18:6a4db94011d3	11413	#define EADC_AD1TRGEN2_EPWM00FEN_Pos (1) /!< EADC AD1TRGEN2: EPWM00FEN Position /
sahilmgandhi	18:6a4db94011d3	11414	#define EADC_AD1TRGEN2_EPWM00FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM00FEN_Pos) /!< EADC AD1TRGEN2: EPWM00FEN Mask /
sahilmgandhi	18:6a4db94011d3	11415
sahilmgandhi	18:6a4db94011d3	11416	#define EADC_AD1TRGEN2_EPWM00PEN_Pos (2) /!< EADC AD1TRGEN2: EPWM00PEN Position /
sahilmgandhi	18:6a4db94011d3	11417	#define EADC_AD1TRGEN2_EPWM00PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM00PEN_Pos) /!< EADC AD1TRGEN2: EPWM00PEN Mask /
sahilmgandhi	18:6a4db94011d3	11418
sahilmgandhi	18:6a4db94011d3	11419	#define EADC_AD1TRGEN2_EPWM00CEN_Pos (3) /!< EADC AD1TRGEN2: EPWM00CEN Position /
sahilmgandhi	18:6a4db94011d3	11420	#define EADC_AD1TRGEN2_EPWM00CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM00CEN_Pos) /!< EADC AD1TRGEN2: EPWM00CEN Mask /
sahilmgandhi	18:6a4db94011d3	11421
sahilmgandhi	18:6a4db94011d3	11422	#define EADC_AD1TRGEN2_EPWM02REN_Pos (4) /!< EADC AD1TRGEN2: EPWM02REN Position /
sahilmgandhi	18:6a4db94011d3	11423	#define EADC_AD1TRGEN2_EPWM02REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM02REN_Pos) /!< EADC AD1TRGEN2: EPWM02REN Mask /
sahilmgandhi	18:6a4db94011d3	11424
sahilmgandhi	18:6a4db94011d3	11425	#define EADC_AD1TRGEN2_EPWM02FEN_Pos (5) /!< EADC AD1TRGEN2: EPWM02FEN Position /
sahilmgandhi	18:6a4db94011d3	11426	#define EADC_AD1TRGEN2_EPWM02FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM02FEN_Pos) /!< EADC AD1TRGEN2: EPWM02FEN Mask /
sahilmgandhi	18:6a4db94011d3	11427
sahilmgandhi	18:6a4db94011d3	11428	#define EADC_AD1TRGEN2_EPWM02PEN_Pos (6) /!< EADC AD1TRGEN2: EPWM02PEN Position /
sahilmgandhi	18:6a4db94011d3	11429	#define EADC_AD1TRGEN2_EPWM02PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM02PEN_Pos) /!< EADC AD1TRGEN2: EPWM02PEN Mask /
sahilmgandhi	18:6a4db94011d3	11430
sahilmgandhi	18:6a4db94011d3	11431	#define EADC_AD1TRGEN2_EPWM02CEN_Pos (7) /!< EADC AD1TRGEN2: EPWM02CEN Position /
sahilmgandhi	18:6a4db94011d3	11432	#define EADC_AD1TRGEN2_EPWM02CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM02CEN_Pos) /!< EADC AD1TRGEN2: EPWM02CEN Mask /
sahilmgandhi	18:6a4db94011d3	11433
sahilmgandhi	18:6a4db94011d3	11434	#define EADC_AD1TRGEN2_EPWM04REN_Pos (8) /!< EADC AD1TRGEN2: EPWM04REN Position /
sahilmgandhi	18:6a4db94011d3	11435	#define EADC_AD1TRGEN2_EPWM04REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM04REN_Pos) /!< EADC AD1TRGEN2: EPWM04REN Mask /
sahilmgandhi	18:6a4db94011d3	11436
sahilmgandhi	18:6a4db94011d3	11437	#define EADC_AD1TRGEN2_EPWM04FEN_Pos (9) /!< EADC AD1TRGEN2: EPWM04FEN Position /
sahilmgandhi	18:6a4db94011d3	11438	#define EADC_AD1TRGEN2_EPWM04FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM04FEN_Pos) /!< EADC AD1TRGEN2: EPWM04FEN Mask /
sahilmgandhi	18:6a4db94011d3	11439
sahilmgandhi	18:6a4db94011d3	11440	#define EADC_AD1TRGEN2_EPWM04PEN_Pos (10) /!< EADC AD1TRGEN2: EPWM04PEN Position /
sahilmgandhi	18:6a4db94011d3	11441	#define EADC_AD1TRGEN2_EPWM04PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM04PEN_Pos) /!< EADC AD1TRGEN2: EPWM04PEN Mask /
sahilmgandhi	18:6a4db94011d3	11442
sahilmgandhi	18:6a4db94011d3	11443	#define EADC_AD1TRGEN2_EPWM04CEN_Pos (11) /!< EADC AD1TRGEN2: EPWM04CEN Position /
sahilmgandhi	18:6a4db94011d3	11444	#define EADC_AD1TRGEN2_EPWM04CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM04CEN_Pos) /!< EADC AD1TRGEN2: EPWM04CEN Mask /
sahilmgandhi	18:6a4db94011d3	11445
sahilmgandhi	18:6a4db94011d3	11446	#define EADC_AD1TRGEN2_EPWM10REN_Pos (12) /!< EADC AD1TRGEN2: EPWM10REN Position /
sahilmgandhi	18:6a4db94011d3	11447	#define EADC_AD1TRGEN2_EPWM10REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM10REN_Pos) /!< EADC AD1TRGEN2: EPWM10REN Mask /
sahilmgandhi	18:6a4db94011d3	11448
sahilmgandhi	18:6a4db94011d3	11449	#define EADC_AD1TRGEN2_EPWM10FEN_Pos (13) /!< EADC AD1TRGEN2: EPWM10FEN Position /
sahilmgandhi	18:6a4db94011d3	11450	#define EADC_AD1TRGEN2_EPWM10FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM10FEN_Pos) /!< EADC AD1TRGEN2: EPWM10FEN Mask /
sahilmgandhi	18:6a4db94011d3	11451
sahilmgandhi	18:6a4db94011d3	11452	#define EADC_AD1TRGEN2_EPWM10PEN_Pos (14) /!< EADC AD1TRGEN2: EPWM10PEN Position /
sahilmgandhi	18:6a4db94011d3	11453	#define EADC_AD1TRGEN2_EPWM10PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM10PEN_Pos) /!< EADC AD1TRGEN2: EPWM10PEN Mask /
sahilmgandhi	18:6a4db94011d3	11454
sahilmgandhi	18:6a4db94011d3	11455	#define EADC_AD1TRGEN2_EPWM10CEN_Pos (15) /!< EADC AD1TRGEN2: EPWM10CEN Position /
sahilmgandhi	18:6a4db94011d3	11456	#define EADC_AD1TRGEN2_EPWM10CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM10CEN_Pos) /!< EADC AD1TRGEN2: EPWM10CEN Mask /
sahilmgandhi	18:6a4db94011d3	11457
sahilmgandhi	18:6a4db94011d3	11458	#define EADC_AD1TRGEN2_EPWM12REN_Pos (16) /!< EADC AD1TRGEN2: EPWM12REN Position /
sahilmgandhi	18:6a4db94011d3	11459	#define EADC_AD1TRGEN2_EPWM12REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM12REN_Pos) /!< EADC AD1TRGEN2: EPWM12REN Mask /
sahilmgandhi	18:6a4db94011d3	11460
sahilmgandhi	18:6a4db94011d3	11461	#define EADC_AD1TRGEN2_EPWM120FEN_Pos (17) /!< EADC AD1TRGEN2: EPWM120FEN Position /
sahilmgandhi	18:6a4db94011d3	11462	#define EADC_AD1TRGEN2_EPWM120FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM120FEN_Pos) /!< EADC AD1TRGEN2: EPWM120FEN Mask /
sahilmgandhi	18:6a4db94011d3	11463
sahilmgandhi	18:6a4db94011d3	11464	#define EADC_AD1TRGEN2_EPWM12PEN_Pos (18) /!< EADC AD1TRGEN2: EPWM12PEN Position /
sahilmgandhi	18:6a4db94011d3	11465	#define EADC_AD1TRGEN2_EPWM12PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM12PEN_Pos) /!< EADC AD1TRGEN2: EPWM12PEN Mask /
sahilmgandhi	18:6a4db94011d3	11466
sahilmgandhi	18:6a4db94011d3	11467	#define EADC_AD1TRGEN2_EPWM12CEN_Pos (19) /!< EADC AD1TRGEN2: EPWM12CEN Position /
sahilmgandhi	18:6a4db94011d3	11468	#define EADC_AD1TRGEN2_EPWM12CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM12CEN_Pos) /!< EADC AD1TRGEN2: EPWM12CEN Mask /
sahilmgandhi	18:6a4db94011d3	11469
sahilmgandhi	18:6a4db94011d3	11470	#define EADC_AD1TRGEN2_EPWM14REN_Pos (20) /!< EADC AD1TRGEN2: EPWM14REN Position /
sahilmgandhi	18:6a4db94011d3	11471	#define EADC_AD1TRGEN2_EPWM14REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM14REN_Pos) /!< EADC AD1TRGEN2: EPWM14REN Mask /
sahilmgandhi	18:6a4db94011d3	11472
sahilmgandhi	18:6a4db94011d3	11473	#define EADC_AD1TRGEN2_EPWM14FEN_Pos (21) /!< EADC AD1TRGEN2: EPWM14FEN Position /
sahilmgandhi	18:6a4db94011d3	11474	#define EADC_AD1TRGEN2_EPWM14FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM14FEN_Pos) /!< EADC AD1TRGEN2: EPWM14FEN Mask /
sahilmgandhi	18:6a4db94011d3	11475
sahilmgandhi	18:6a4db94011d3	11476	#define EADC_AD1TRGEN2_EPWM14PEN_Pos (22) /!< EADC AD1TRGEN2: EPWM14PEN Position /
sahilmgandhi	18:6a4db94011d3	11477	#define EADC_AD1TRGEN2_EPWM14PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM14PEN_Pos) /!< EADC AD1TRGEN2: EPWM14PEN Mask /
sahilmgandhi	18:6a4db94011d3	11478
sahilmgandhi	18:6a4db94011d3	11479	#define EADC_AD1TRGEN2_EPWM14CEN_Pos (23) /!< EADC AD1TRGEN2: EPWM14CEN Position /
sahilmgandhi	18:6a4db94011d3	11480	#define EADC_AD1TRGEN2_EPWM14CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM14CEN_Pos) /!< EADC AD1TRGEN2: EPWM14CEN Mask /
sahilmgandhi	18:6a4db94011d3	11481
sahilmgandhi	18:6a4db94011d3	11482	#define EADC_AD1TRGEN2_PWM00REN_Pos (24) /!< EADC AD1TRGEN2: PWM00REN Position /
sahilmgandhi	18:6a4db94011d3	11483	#define EADC_AD1TRGEN2_PWM00REN_Msk (0x1ul << EADC_AD1TRGEN2_PWM00REN_Pos) /!< EADC AD1TRGEN2: PWM00REN Mask /
sahilmgandhi	18:6a4db94011d3	11484
sahilmgandhi	18:6a4db94011d3	11485	#define EADC_AD1TRGEN2_PWM00FEN_Pos (25) /!< EADC AD1TRGEN2: PWM00FEN Position /
sahilmgandhi	18:6a4db94011d3	11486	#define EADC_AD1TRGEN2_PWM00FEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM00FEN_Pos) /!< EADC AD1TRGEN2: PWM00FEN Mask /
sahilmgandhi	18:6a4db94011d3	11487
sahilmgandhi	18:6a4db94011d3	11488	#define EADC_AD1TRGEN2_PWM00PEN_Pos (26) /!< EADC AD1TRGEN2: PWM00PEN Position /
sahilmgandhi	18:6a4db94011d3	11489	#define EADC_AD1TRGEN2_PWM00PEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM00PEN_Pos) /!< EADC AD1TRGEN2: PWM00PEN Mask /
sahilmgandhi	18:6a4db94011d3	11490
sahilmgandhi	18:6a4db94011d3	11491	#define EADC_AD1TRGEN2_PWM00CEN_Pos (27) /!< EADC AD1TRGEN2: PWM00CEN Position /
sahilmgandhi	18:6a4db94011d3	11492	#define EADC_AD1TRGEN2_PWM00CEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM00CEN_Pos) /!< EADC AD1TRGEN2: PWM00CEN Mask /
sahilmgandhi	18:6a4db94011d3	11493
sahilmgandhi	18:6a4db94011d3	11494	#define EADC_AD1TRGEN2_PWM01REN_Pos (28) /!< EADC AD1TRGEN2: PWM01REN Position /
sahilmgandhi	18:6a4db94011d3	11495	#define EADC_AD1TRGEN2_PWM01REN_Msk (0x1ul << EADC_AD1TRGEN2_PWM01REN_Pos) /!< EADC AD1TRGEN2: PWM01REN Mask /
sahilmgandhi	18:6a4db94011d3	11496
sahilmgandhi	18:6a4db94011d3	11497	#define EADC_AD1TRGEN2_PWM01FEN_Pos (29) /!< EADC AD1TRGEN2: PWM01FEN Position /
sahilmgandhi	18:6a4db94011d3	11498	#define EADC_AD1TRGEN2_PWM01FEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM01FEN_Pos) /!< EADC AD1TRGEN2: PWM01FEN Mask /
sahilmgandhi	18:6a4db94011d3	11499
sahilmgandhi	18:6a4db94011d3	11500	#define EADC_AD1TRGEN2_PWM01PEN_Pos (30) /!< EADC AD1TRGEN2: PWM01PEN Position /
sahilmgandhi	18:6a4db94011d3	11501	#define EADC_AD1TRGEN2_PWM01PEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM01PEN_Pos) /!< EADC AD1TRGEN2: PWM01PEN Mask /
sahilmgandhi	18:6a4db94011d3	11502
sahilmgandhi	18:6a4db94011d3	11503	#define EADC_AD1TRGEN2_PWM01CEN_Pos (31) /!< EADC AD1TRGEN2: PWM01CEN Position /
sahilmgandhi	18:6a4db94011d3	11504	#define EADC_AD1TRGEN2_PWM01CEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM01CEN_Pos) /!< EADC AD1TRGEN2: PWM01CEN Mask /
sahilmgandhi	18:6a4db94011d3	11505
sahilmgandhi	18:6a4db94011d3	11506	#define EADC_AD1TRGEN3_EPWM00REN_Pos (0) /!< EADC AD1TRGEN3: EPWM00REN Position /
sahilmgandhi	18:6a4db94011d3	11507	#define EADC_AD1TRGEN3_EPWM00REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM00REN_Pos) /!< EADC AD1TRGEN3: EPWM00REN Mask /
sahilmgandhi	18:6a4db94011d3	11508
sahilmgandhi	18:6a4db94011d3	11509	#define EADC_AD1TRGEN3_EPWM00FEN_Pos (1) /!< EADC AD1TRGEN3: EPWM00FEN Position /
sahilmgandhi	18:6a4db94011d3	11510	#define EADC_AD1TRGEN3_EPWM00FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM00FEN_Pos) /!< EADC AD1TRGEN3: EPWM00FEN Mask /
sahilmgandhi	18:6a4db94011d3	11511
sahilmgandhi	18:6a4db94011d3	11512	#define EADC_AD1TRGEN3_EPWM00PEN_Pos (2) /!< EADC AD1TRGEN3: EPWM00PEN Position /
sahilmgandhi	18:6a4db94011d3	11513	#define EADC_AD1TRGEN3_EPWM00PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM00PEN_Pos) /!< EADC AD1TRGEN3: EPWM00PEN Mask /
sahilmgandhi	18:6a4db94011d3	11514
sahilmgandhi	18:6a4db94011d3	11515	#define EADC_AD1TRGEN3_EPWM00CEN_Pos (3) /!< EADC AD1TRGEN3: EPWM00CEN Position /
sahilmgandhi	18:6a4db94011d3	11516	#define EADC_AD1TRGEN3_EPWM00CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM00CEN_Pos) /!< EADC AD1TRGEN3: EPWM00CEN Mask /
sahilmgandhi	18:6a4db94011d3	11517
sahilmgandhi	18:6a4db94011d3	11518	#define EADC_AD1TRGEN3_EPWM02REN_Pos (4) /!< EADC AD1TRGEN3: EPWM02REN Position /
sahilmgandhi	18:6a4db94011d3	11519	#define EADC_AD1TRGEN3_EPWM02REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM02REN_Pos) /!< EADC AD1TRGEN3: EPWM02REN Mask /
sahilmgandhi	18:6a4db94011d3	11520
sahilmgandhi	18:6a4db94011d3	11521	#define EADC_AD1TRGEN3_EPWM02FEN_Pos (5) /!< EADC AD1TRGEN3: EPWM02FEN Position /
sahilmgandhi	18:6a4db94011d3	11522	#define EADC_AD1TRGEN3_EPWM02FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM02FEN_Pos) /!< EADC AD1TRGEN3: EPWM02FEN Mask /
sahilmgandhi	18:6a4db94011d3	11523
sahilmgandhi	18:6a4db94011d3	11524	#define EADC_AD1TRGEN3_EPWM02PEN_Pos (6) /!< EADC AD1TRGEN3: EPWM02PEN Position /
sahilmgandhi	18:6a4db94011d3	11525	#define EADC_AD1TRGEN3_EPWM02PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM02PEN_Pos) /!< EADC AD1TRGEN3: EPWM02PEN Mask /
sahilmgandhi	18:6a4db94011d3	11526
sahilmgandhi	18:6a4db94011d3	11527	#define EADC_AD1TRGEN3_EPWM02CEN_Pos (7) /!< EADC AD1TRGEN3: EPWM02CEN Position /
sahilmgandhi	18:6a4db94011d3	11528	#define EADC_AD1TRGEN3_EPWM02CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM02CEN_Pos) /!< EADC AD1TRGEN3: EPWM02CEN Mask /
sahilmgandhi	18:6a4db94011d3	11529
sahilmgandhi	18:6a4db94011d3	11530	#define EADC_AD1TRGEN3_EPWM04REN_Pos (8) /!< EADC AD1TRGEN3: EPWM04REN Position /
sahilmgandhi	18:6a4db94011d3	11531	#define EADC_AD1TRGEN3_EPWM04REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM04REN_Pos) /!< EADC AD1TRGEN3: EPWM04REN Mask /
sahilmgandhi	18:6a4db94011d3	11532
sahilmgandhi	18:6a4db94011d3	11533	#define EADC_AD1TRGEN3_EPWM04FEN_Pos (9) /!< EADC AD1TRGEN3: EPWM04FEN Position /
sahilmgandhi	18:6a4db94011d3	11534	#define EADC_AD1TRGEN3_EPWM04FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM04FEN_Pos) /!< EADC AD1TRGEN3: EPWM04FEN Mask /
sahilmgandhi	18:6a4db94011d3	11535
sahilmgandhi	18:6a4db94011d3	11536	#define EADC_AD1TRGEN3_EPWM04PEN_Pos (10) /!< EADC AD1TRGEN3: EPWM04PEN Position /
sahilmgandhi	18:6a4db94011d3	11537	#define EADC_AD1TRGEN3_EPWM04PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM04PEN_Pos) /!< EADC AD1TRGEN3: EPWM04PEN Mask /
sahilmgandhi	18:6a4db94011d3	11538
sahilmgandhi	18:6a4db94011d3	11539	#define EADC_AD1TRGEN3_EPWM04CEN_Pos (11) /!< EADC AD1TRGEN3: EPWM04CEN Position /
sahilmgandhi	18:6a4db94011d3	11540	#define EADC_AD1TRGEN3_EPWM04CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM04CEN_Pos) /!< EADC AD1TRGEN3: EPWM04CEN Mask /
sahilmgandhi	18:6a4db94011d3	11541
sahilmgandhi	18:6a4db94011d3	11542	#define EADC_AD1TRGEN3_EPWM10REN_Pos (12) /!< EADC AD1TRGEN3: EPWM10REN Position /
sahilmgandhi	18:6a4db94011d3	11543	#define EADC_AD1TRGEN3_EPWM10REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM10REN_Pos) /!< EADC AD1TRGEN3: EPWM10REN Mask /
sahilmgandhi	18:6a4db94011d3	11544
sahilmgandhi	18:6a4db94011d3	11545	#define EADC_AD1TRGEN3_EPWM10FEN_Pos (13) /!< EADC AD1TRGEN3: EPWM10FEN Position /
sahilmgandhi	18:6a4db94011d3	11546	#define EADC_AD1TRGEN3_EPWM10FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM10FEN_Pos) /!< EADC AD1TRGEN3: EPWM10FEN Mask /
sahilmgandhi	18:6a4db94011d3	11547
sahilmgandhi	18:6a4db94011d3	11548	#define EADC_AD1TRGEN3_EPWM10PEN_Pos (14) /!< EADC AD1TRGEN3: EPWM10PEN Position /
sahilmgandhi	18:6a4db94011d3	11549	#define EADC_AD1TRGEN3_EPWM10PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM10PEN_Pos) /!< EADC AD1TRGEN3: EPWM10PEN Mask /
sahilmgandhi	18:6a4db94011d3	11550
sahilmgandhi	18:6a4db94011d3	11551	#define EADC_AD1TRGEN3_EPWM10CEN_Pos (15) /!< EADC AD1TRGEN3: EPWM10CEN Position /
sahilmgandhi	18:6a4db94011d3	11552	#define EADC_AD1TRGEN3_EPWM10CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM10CEN_Pos) /!< EADC AD1TRGEN3: EPWM10CEN Mask /
sahilmgandhi	18:6a4db94011d3	11553
sahilmgandhi	18:6a4db94011d3	11554	#define EADC_AD1TRGEN3_EPWM12REN_Pos (16) /!< EADC AD1TRGEN3: EPWM12REN Position /
sahilmgandhi	18:6a4db94011d3	11555	#define EADC_AD1TRGEN3_EPWM12REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM12REN_Pos) /!< EADC AD1TRGEN3: EPWM12REN Mask /
sahilmgandhi	18:6a4db94011d3	11556
sahilmgandhi	18:6a4db94011d3	11557	#define EADC_AD1TRGEN3_EPWM120FEN_Pos (17) /!< EADC AD1TRGEN3: EPWM120FEN Position /
sahilmgandhi	18:6a4db94011d3	11558	#define EADC_AD1TRGEN3_EPWM120FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM120FEN_Pos) /!< EADC AD1TRGEN3: EPWM120FEN Mask /
sahilmgandhi	18:6a4db94011d3	11559
sahilmgandhi	18:6a4db94011d3	11560	#define EADC_AD1TRGEN3_EPWM12PEN_Pos (18) /!< EADC AD1TRGEN3: EPWM12PEN Position /
sahilmgandhi	18:6a4db94011d3	11561	#define EADC_AD1TRGEN3_EPWM12PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM12PEN_Pos) /!< EADC AD1TRGEN3: EPWM12PEN Mask /
sahilmgandhi	18:6a4db94011d3	11562
sahilmgandhi	18:6a4db94011d3	11563	#define EADC_AD1TRGEN3_EPWM12CEN_Pos (19) /!< EADC AD1TRGEN3: EPWM12CEN Position /
sahilmgandhi	18:6a4db94011d3	11564	#define EADC_AD1TRGEN3_EPWM12CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM12CEN_Pos) /!< EADC AD1TRGEN3: EPWM12CEN Mask /
sahilmgandhi	18:6a4db94011d3	11565
sahilmgandhi	18:6a4db94011d3	11566	#define EADC_AD1TRGEN3_EPWM14REN_Pos (20) /!< EADC AD1TRGEN3: EPWM14REN Position /
sahilmgandhi	18:6a4db94011d3	11567	#define EADC_AD1TRGEN3_EPWM14REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM14REN_Pos) /!< EADC AD1TRGEN3: EPWM14REN Mask /
sahilmgandhi	18:6a4db94011d3	11568
sahilmgandhi	18:6a4db94011d3	11569	#define EADC_AD1TRGEN3_EPWM14FEN_Pos (21) /!< EADC AD1TRGEN3: EPWM14FEN Position /
sahilmgandhi	18:6a4db94011d3	11570	#define EADC_AD1TRGEN3_EPWM14FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM14FEN_Pos) /!< EADC AD1TRGEN3: EPWM14FEN Mask /
sahilmgandhi	18:6a4db94011d3	11571
sahilmgandhi	18:6a4db94011d3	11572	#define EADC_AD1TRGEN3_EPWM14PEN_Pos (22) /!< EADC AD1TRGEN3: EPWM14PEN Position /
sahilmgandhi	18:6a4db94011d3	11573	#define EADC_AD1TRGEN3_EPWM14PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM14PEN_Pos) /!< EADC AD1TRGEN3: EPWM14PEN Mask /
sahilmgandhi	18:6a4db94011d3	11574
sahilmgandhi	18:6a4db94011d3	11575	#define EADC_AD1TRGEN3_EPWM14CEN_Pos (23) /!< EADC AD1TRGEN3: EPWM14CEN Position /
sahilmgandhi	18:6a4db94011d3	11576	#define EADC_AD1TRGEN3_EPWM14CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM14CEN_Pos) /!< EADC AD1TRGEN3: EPWM14CEN Mask /
sahilmgandhi	18:6a4db94011d3	11577
sahilmgandhi	18:6a4db94011d3	11578	#define EADC_AD1TRGEN3_PWM00REN_Pos (24) /!< EADC AD1TRGEN3: PWM00REN Position /
sahilmgandhi	18:6a4db94011d3	11579	#define EADC_AD1TRGEN3_PWM00REN_Msk (0x1ul << EADC_AD1TRGEN3_PWM00REN_Pos) /!< EADC AD1TRGEN3: PWM00REN Mask /
sahilmgandhi	18:6a4db94011d3	11580
sahilmgandhi	18:6a4db94011d3	11581	#define EADC_AD1TRGEN3_PWM00FEN_Pos (25) /!< EADC AD1TRGEN3: PWM00FEN Position /
sahilmgandhi	18:6a4db94011d3	11582	#define EADC_AD1TRGEN3_PWM00FEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM00FEN_Pos) /!< EADC AD1TRGEN3: PWM00FEN Mask /
sahilmgandhi	18:6a4db94011d3	11583
sahilmgandhi	18:6a4db94011d3	11584	#define EADC_AD1TRGEN3_PWM00PEN_Pos (26) /!< EADC AD1TRGEN3: PWM00PEN Position /
sahilmgandhi	18:6a4db94011d3	11585	#define EADC_AD1TRGEN3_PWM00PEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM00PEN_Pos) /!< EADC AD1TRGEN3: PWM00PEN Mask /
sahilmgandhi	18:6a4db94011d3	11586
sahilmgandhi	18:6a4db94011d3	11587	#define EADC_AD1TRGEN3_PWM00CEN_Pos (27) /!< EADC AD1TRGEN3: PWM00CEN Position /
sahilmgandhi	18:6a4db94011d3	11588	#define EADC_AD1TRGEN3_PWM00CEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM00CEN_Pos) /!< EADC AD1TRGEN3: PWM00CEN Mask /
sahilmgandhi	18:6a4db94011d3	11589
sahilmgandhi	18:6a4db94011d3	11590	#define EADC_AD1TRGEN3_PWM01REN_Pos (28) /!< EADC AD1TRGEN3: PWM01REN Position /
sahilmgandhi	18:6a4db94011d3	11591	#define EADC_AD1TRGEN3_PWM01REN_Msk (0x1ul << EADC_AD1TRGEN3_PWM01REN_Pos) /!< EADC AD1TRGEN3: PWM01REN Mask /
sahilmgandhi	18:6a4db94011d3	11592
sahilmgandhi	18:6a4db94011d3	11593	#define EADC_AD1TRGEN3_PWM01FEN_Pos (29) /!< EADC AD1TRGEN3: PWM01FEN Position /
sahilmgandhi	18:6a4db94011d3	11594	#define EADC_AD1TRGEN3_PWM01FEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM01FEN_Pos) /!< EADC AD1TRGEN3: PWM01FEN Mask /
sahilmgandhi	18:6a4db94011d3	11595
sahilmgandhi	18:6a4db94011d3	11596	#define EADC_AD1TRGEN3_PWM01PEN_Pos (30) /!< EADC AD1TRGEN3: PWM01PEN Position /
sahilmgandhi	18:6a4db94011d3	11597	#define EADC_AD1TRGEN3_PWM01PEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM01PEN_Pos) /!< EADC AD1TRGEN3: PWM01PEN Mask /
sahilmgandhi	18:6a4db94011d3	11598
sahilmgandhi	18:6a4db94011d3	11599	#define EADC_AD1TRGEN3_PWM01CEN_Pos (31) /!< EADC AD1TRGEN3: PWM01CEN Position /
sahilmgandhi	18:6a4db94011d3	11600	#define EADC_AD1TRGEN3_PWM01CEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM01CEN_Pos) /!< EADC AD1TRGEN3: PWM01CEN Mask /
sahilmgandhi	18:6a4db94011d3	11601
sahilmgandhi	18:6a4db94011d3	11602	/*@}/ /* EADC_CONST */
sahilmgandhi	18:6a4db94011d3	11603	/*@}/ /* end of EADC register group */
sahilmgandhi	18:6a4db94011d3	11604
sahilmgandhi	18:6a4db94011d3	11605
sahilmgandhi	18:6a4db94011d3	11606	/---------------------- External Bus Interface Controller -------------------------/
sahilmgandhi	18:6a4db94011d3	11607	/**
sahilmgandhi	18:6a4db94011d3	11608	@addtogroup EBI External Bus Interface Controller(EBI)
sahilmgandhi	18:6a4db94011d3	11609	Memory Mapped Structure for EBI Controller
sahilmgandhi	18:6a4db94011d3	11610	@{ */
sahilmgandhi	18:6a4db94011d3	11611
sahilmgandhi	18:6a4db94011d3	11612	typedef struct {
sahilmgandhi	18:6a4db94011d3	11613
sahilmgandhi	18:6a4db94011d3	11614
sahilmgandhi	18:6a4db94011d3	11615	/**
sahilmgandhi	18:6a4db94011d3	11616	* CTL
sahilmgandhi	18:6a4db94011d3	11617	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	11618	* Offset: 0x00 External Bus Interface General Control Register
sahilmgandhi	18:6a4db94011d3	11619	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	11620	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	11621	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	11622	* \|[8:10] \|MCLKDIV \|External Output Clock Divider
sahilmgandhi	18:6a4db94011d3	11623	* \| \| \|The frequency of EBI output clock is controlled by MCLKDIV as below:
sahilmgandhi	18:6a4db94011d3	11624	* \| \| \|000 = HCLK/1.
sahilmgandhi	18:6a4db94011d3	11625	* \| \| \|001 = HCLK/2.
sahilmgandhi	18:6a4db94011d3	11626	* \| \| \|010 = HCLK/4.
sahilmgandhi	18:6a4db94011d3	11627	* \| \| \|011 = HCLK/8.
sahilmgandhi	18:6a4db94011d3	11628	* \| \| \|100 = HCLK/16.
sahilmgandhi	18:6a4db94011d3	11629	* \| \| \|101 = HCLK/32.
sahilmgandhi	18:6a4db94011d3	11630	* \| \| \|11x = Default.
sahilmgandhi	18:6a4db94011d3	11631	* \| \| \|Note: Default value of output clock is HCLK/1
sahilmgandhi	18:6a4db94011d3	11632	* \|[24:27] \|CRYPTOEN \|Encrypt/Decrypt Function Enable Control (For 4 Individual Chip Select)
sahilmgandhi	18:6a4db94011d3	11633	* \| \| \|0 = Encrypt/Decrypt function Disabled.
sahilmgandhi	18:6a4db94011d3	11634	* \| \| \|1 = Encrypt/Decrypt function Enabled.
sahilmgandhi	18:6a4db94011d3	11635	* \|[28:31] \|CSPOLINV \|Reverse Chip Select
sahilmgandhi	18:6a4db94011d3	11636	* \| \| \|The original design Chip Select is active low nCS.
sahilmgandhi	18:6a4db94011d3	11637	* \| \| \|"Chip Select Active High" can be specified by customers-Bit[28+n] is for nCS[n], where n=0~3.
sahilmgandhi	18:6a4db94011d3	11638	* \| \| \|0 = nCS (chip select active low).
sahilmgandhi	18:6a4db94011d3	11639	* \| \| \|1 = CS (chip select active high).
sahilmgandhi	18:6a4db94011d3	11640	*/
sahilmgandhi	18:6a4db94011d3	11641	__IO uint32_t CTL;
sahilmgandhi	18:6a4db94011d3	11642
sahilmgandhi	18:6a4db94011d3	11643	/**
sahilmgandhi	18:6a4db94011d3	11644	* TCTL
sahilmgandhi	18:6a4db94011d3	11645	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	11646	* Offset: 0x04 - 0x10 External Bus Interface Bank0~3 Timing Control Register
sahilmgandhi	18:6a4db94011d3	11647	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	11648	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	11649	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	11650	* \|[0:2] \|TALE \|Bank Expand Time Of ALE
sahilmgandhi	18:6a4db94011d3	11651	* \| \| \|The ALE width (tALE) to latch the address can be controlled by TALE.
sahilmgandhi	18:6a4db94011d3	11652	* \| \| \|tALE = (TALE+1)*MCLK.
sahilmgandhi	18:6a4db94011d3	11653	* \|[3:7] \|TACC \|EBI Bank Data Access Time
sahilmgandhi	18:6a4db94011d3	11654	* \| \| \|TACC define data access time (tACC).
sahilmgandhi	18:6a4db94011d3	11655	* \| \| \|tACC = (TACC +1) * MCLK.
sahilmgandhi	18:6a4db94011d3	11656	* \|[8:10] \|TAHD \|EBI Bank Data Access Hold Time
sahilmgandhi	18:6a4db94011d3	11657	* \| \| \|TAHD define data access hold time (tAHD).
sahilmgandhi	18:6a4db94011d3	11658	* \| \| \|tAHD = (TAHD +1) * MCLK.
sahilmgandhi	18:6a4db94011d3	11659	* \|[12:15] \|W2X \|Bank Idle State Cycle After Write
sahilmgandhi	18:6a4db94011d3	11660	* \| \| \|When write action is finish, idle state is inserted and nCS[0] return to high if W2X is not zero.
sahilmgandhi	18:6a4db94011d3	11661	* \| \| \|Idle state cycle = (W2X*MCLK).
sahilmgandhi	18:6a4db94011d3	11662	* \| \| \|0 = reserved.
sahilmgandhi	18:6a4db94011d3	11663	* \|[16:19] \|R2W \|Bank Idle State Cycle Between Read-Write
sahilmgandhi	18:6a4db94011d3	11664	* \| \| \|When read action is finish and next action is going to write, idle state is inserted and nCS[0] return to high if R2W is not zero.
sahilmgandhi	18:6a4db94011d3	11665	* \| \| \|Idle state cycle = (R2W*MCLK).
sahilmgandhi	18:6a4db94011d3	11666	* \| \| \|0 = reserved.
sahilmgandhi	18:6a4db94011d3	11667	* \|[24:27] \|R2R \|Bank Idle State Cycle Between Read-Read
sahilmgandhi	18:6a4db94011d3	11668	* \| \| \|When read action is finish and next action is going to read, idle state is inserted and nCS[0] return to high if R2R is not zero.
sahilmgandhi	18:6a4db94011d3	11669	* \| \| \|Idle state cycle = (R2R*MCLK).
sahilmgandhi	18:6a4db94011d3	11670	* \| \| \|0 = reserved.
sahilmgandhi	18:6a4db94011d3	11671	* \|[28] \|CSEN \|EBI Bank Enable Control
sahilmgandhi	18:6a4db94011d3	11672	* \| \| \|This bit is the functional enable bit for EBI.
sahilmgandhi	18:6a4db94011d3	11673	* \| \| \|0 = EBI function Disabled.
sahilmgandhi	18:6a4db94011d3	11674	* \| \| \|1 = EBI function Enabled.
sahilmgandhi	18:6a4db94011d3	11675	* \|[29] \|DW16 \|EBI Bank Data Width 16-Bit
sahilmgandhi	18:6a4db94011d3	11676	* \| \| \|This bit defines if the data bus is 8-bit or 16-bit.
sahilmgandhi	18:6a4db94011d3	11677	* \| \| \|0 = EBI data width is 8-bit.
sahilmgandhi	18:6a4db94011d3	11678	* \| \| \|1 = EBI data width is 16-bit.
sahilmgandhi	18:6a4db94011d3	11679	* \|[30] \|SEPEN \|EBI Bank Address/Data Bus Separating Enable Control
sahilmgandhi	18:6a4db94011d3	11680	* \| \| \|0 = Address/Data Bus Separating Disabled.
sahilmgandhi	18:6a4db94011d3	11681	* \| \| \|1 = Address/Data Bus Separating Enabled.
sahilmgandhi	18:6a4db94011d3	11682	*/
sahilmgandhi	18:6a4db94011d3	11683	__IO uint32_t TCTL[3];
sahilmgandhi	18:6a4db94011d3	11684
sahilmgandhi	18:6a4db94011d3	11685	/**
sahilmgandhi	18:6a4db94011d3	11686	* KEY0
sahilmgandhi	18:6a4db94011d3	11687	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	11688	* Offset: 0x14 External Bus Interface Crypto Key Word 0
sahilmgandhi	18:6a4db94011d3	11689	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	11690	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	11691	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	11692	* \|[0:31] \|KEY0 \|Crypto Key Word 0 (key[31:0]).
sahilmgandhi	18:6a4db94011d3	11693	*/
sahilmgandhi	18:6a4db94011d3	11694	__IO uint32_t KEY0;
sahilmgandhi	18:6a4db94011d3	11695
sahilmgandhi	18:6a4db94011d3	11696	/**
sahilmgandhi	18:6a4db94011d3	11697	* KEY1
sahilmgandhi	18:6a4db94011d3	11698	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	11699	* Offset: 0x18 External Bus Interface Crypto Key Word 1
sahilmgandhi	18:6a4db94011d3	11700	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	11701	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	11702	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	11703	* \|[0:31] \|KEY \|Crypto Key Word 1 (key[63:32]).
sahilmgandhi	18:6a4db94011d3	11704	*/
sahilmgandhi	18:6a4db94011d3	11705	__IO uint32_t KEY1;
sahilmgandhi	18:6a4db94011d3	11706
sahilmgandhi	18:6a4db94011d3	11707	/**
sahilmgandhi	18:6a4db94011d3	11708	* KEY2
sahilmgandhi	18:6a4db94011d3	11709	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	11710	* Offset: 0x1C External Bus Interface Crypto Key Word 2
sahilmgandhi	18:6a4db94011d3	11711	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	11712	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	11713	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	11714	* \|[0:31] \|KEY \|Crypto Key Word 2 (key[95:64]).
sahilmgandhi	18:6a4db94011d3	11715	*/
sahilmgandhi	18:6a4db94011d3	11716	__IO uint32_t KEY2;
sahilmgandhi	18:6a4db94011d3	11717
sahilmgandhi	18:6a4db94011d3	11718	/**
sahilmgandhi	18:6a4db94011d3	11719	* KEY3
sahilmgandhi	18:6a4db94011d3	11720	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	11721	* Offset: 0x20 External Bus Interface Crypto Key Word 3
sahilmgandhi	18:6a4db94011d3	11722	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	11723	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	11724	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	11725	* \|[0:31] \|KEY \|Crypto Key Word 3 (key[127:96]).
sahilmgandhi	18:6a4db94011d3	11726	*/
sahilmgandhi	18:6a4db94011d3	11727	__IO uint32_t KEY3;
sahilmgandhi	18:6a4db94011d3	11728
sahilmgandhi	18:6a4db94011d3	11729	} EBI_T;
sahilmgandhi	18:6a4db94011d3	11730
sahilmgandhi	18:6a4db94011d3	11731	/**
sahilmgandhi	18:6a4db94011d3	11732	@addtogroup EBI_CONST EBI Bit Field Definition
sahilmgandhi	18:6a4db94011d3	11733	Constant Definitions for EBI Controller
sahilmgandhi	18:6a4db94011d3	11734	@{ */
sahilmgandhi	18:6a4db94011d3	11735
sahilmgandhi	18:6a4db94011d3	11736	#define EBI_CTL_MCLKDIV_Pos (8) /!< EBI CTL: MCLKDIV Position /
sahilmgandhi	18:6a4db94011d3	11737	#define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /!< EBI CTL: MCLKDIV Mask /
sahilmgandhi	18:6a4db94011d3	11738
sahilmgandhi	18:6a4db94011d3	11739	#define EBI_CTL_CRYPTOEN_Pos (24) /!< EBI CTL: CRYPTOEN Position /
sahilmgandhi	18:6a4db94011d3	11740	#define EBI_CTL_CRYPTOEN_Msk (0xful << EBI_CTL_CRYPTOEN_Pos) /!< EBI CTL: CRYPTOEN Mask /
sahilmgandhi	18:6a4db94011d3	11741
sahilmgandhi	18:6a4db94011d3	11742	#define EBI_CTL_CSPOLINV_Pos (28) /!< EBI CTL: CSPOLINV Position /
sahilmgandhi	18:6a4db94011d3	11743	#define EBI_CTL_CSPOLINV_Msk (0xful << EBI_CTL_CSPOLINV_Pos) /!< EBI CTL: CSPOLINV Mask /
sahilmgandhi	18:6a4db94011d3	11744
sahilmgandhi	18:6a4db94011d3	11745	#define EBI_TCTL_TALE_Pos (0) /!< EBI TCTL: TALE Position /
sahilmgandhi	18:6a4db94011d3	11746	#define EBI_TCTL_TALE_Msk (0x7ul << EBI_TCTL_TALE_Pos) /!< EBI TCTL: TALE Mask /
sahilmgandhi	18:6a4db94011d3	11747
sahilmgandhi	18:6a4db94011d3	11748	#define EBI_TCTL_TACC_Pos (3) /!< EBI TCTL: TACC Position /
sahilmgandhi	18:6a4db94011d3	11749	#define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /!< EBI TCTL: TACC Mask /
sahilmgandhi	18:6a4db94011d3	11750
sahilmgandhi	18:6a4db94011d3	11751	#define EBI_TCTL_TAHD_Pos (8) /!< EBI TCTL: TAHD Position /
sahilmgandhi	18:6a4db94011d3	11752	#define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /!< EBI TCTL: TAHD Mask /
sahilmgandhi	18:6a4db94011d3	11753
sahilmgandhi	18:6a4db94011d3	11754	#define EBI_TCTL_W2X_Pos (12) /!< EBI TCTL: W2X Position /
sahilmgandhi	18:6a4db94011d3	11755	#define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /!< EBI TCTL: W2X Mask /
sahilmgandhi	18:6a4db94011d3	11756
sahilmgandhi	18:6a4db94011d3	11757	#define EBI_TCTL_R2W_Pos (16) /!< EBI TCTL: R2W Position /
sahilmgandhi	18:6a4db94011d3	11758	#define EBI_TCTL_R2W_Msk (0xful << EBI_TCTL_R2W_Pos) /!< EBI TCTL: R2W Mask /
sahilmgandhi	18:6a4db94011d3	11759
sahilmgandhi	18:6a4db94011d3	11760	#define EBI_TCTL_R2R_Pos (24) /!< EBI TCTL: R2R Position /
sahilmgandhi	18:6a4db94011d3	11761	#define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /!< EBI TCTL: R2R Mask /
sahilmgandhi	18:6a4db94011d3	11762
sahilmgandhi	18:6a4db94011d3	11763	#define EBI_TCTL_CSEN_Pos (28) /!< EBI TCTL: CSEN Position /
sahilmgandhi	18:6a4db94011d3	11764	#define EBI_TCTL_CSEN_Msk (0x1ul << EBI_TCTL_CSEN_Pos) /!< EBI TCTL: CSEN Mask /
sahilmgandhi	18:6a4db94011d3	11765
sahilmgandhi	18:6a4db94011d3	11766	#define EBI_TCTL_DW16_Pos (29) /!< EBI TCTL: DW16 Position /
sahilmgandhi	18:6a4db94011d3	11767	#define EBI_TCTL_DW16_Msk (0x1ul << EBI_TCTL_DW16_Pos) /!< EBI TCTL: DW16 Mask /
sahilmgandhi	18:6a4db94011d3	11768
sahilmgandhi	18:6a4db94011d3	11769	#define EBI_TCTL_SEPEN_Pos (30) /!< EBI TCTL: SEPEN Position /
sahilmgandhi	18:6a4db94011d3	11770	#define EBI_TCTL_SEPEN_Msk (0x1ul << EBI_TCTL_SEPEN_Pos) /!< EBI TCTL: SEPEN Mask /
sahilmgandhi	18:6a4db94011d3	11771
sahilmgandhi	18:6a4db94011d3	11772	#define EBI_KEY0_KEY_Pos (0) /!< EBI KEY0: KEY Position /
sahilmgandhi	18:6a4db94011d3	11773	#define EBI_KEY0_KEY_Msk (0xfffffffful << EBI_KEY0_KEY_Pos) /!< EBI KEY0: KEY Mask /
sahilmgandhi	18:6a4db94011d3	11774
sahilmgandhi	18:6a4db94011d3	11775	#define EBI_KEY1_KEY_Pos (0) /!< EBI KEY1: KEY Position /
sahilmgandhi	18:6a4db94011d3	11776	#define EBI_KEY1_KEY_Msk (0xfffffffful << EBI_KEY1_KEY_Pos) /!< EBI KEY1: KEY Mask /
sahilmgandhi	18:6a4db94011d3	11777
sahilmgandhi	18:6a4db94011d3	11778	#define EBI_KEY2_KEY_Pos (0) /!< EBI KEY2: KEY Position /
sahilmgandhi	18:6a4db94011d3	11779	#define EBI_KEY2_KEY_Msk (0xfffffffful << EBI_KEY2_KEY_Pos) /!< EBI KEY2: KEY Mask /
sahilmgandhi	18:6a4db94011d3	11780
sahilmgandhi	18:6a4db94011d3	11781	#define EBI_KEY3_KEY_Pos (0) /!< EBI KEY3: KEY Position /
sahilmgandhi	18:6a4db94011d3	11782	#define EBI_KEY3_KEY_Msk (0xfffffffful << EBI_KEY3_KEY_Pos) /!< EBI KEY3: KEY Mask /
sahilmgandhi	18:6a4db94011d3	11783
sahilmgandhi	18:6a4db94011d3	11784	/*@}/ /* EBI_CONST */
sahilmgandhi	18:6a4db94011d3	11785	/*@}/ /* end of EBI register group */
sahilmgandhi	18:6a4db94011d3	11786
sahilmgandhi	18:6a4db94011d3	11787
sahilmgandhi	18:6a4db94011d3	11788	/---------------------- Ethernet MAC Controller -------------------------/
sahilmgandhi	18:6a4db94011d3	11789	/**
sahilmgandhi	18:6a4db94011d3	11790	@addtogroup EMAC Ethernet MAC Controller(EMAC)
sahilmgandhi	18:6a4db94011d3	11791	Memory Mapped Structure for EMAC Controller
sahilmgandhi	18:6a4db94011d3	11792	@{ */
sahilmgandhi	18:6a4db94011d3	11793
sahilmgandhi	18:6a4db94011d3	11794	typedef struct {
sahilmgandhi	18:6a4db94011d3	11795
sahilmgandhi	18:6a4db94011d3	11796
sahilmgandhi	18:6a4db94011d3	11797	/**
sahilmgandhi	18:6a4db94011d3	11798	* CAMCTL
sahilmgandhi	18:6a4db94011d3	11799	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	11800	* Offset: 0x00 CAM Comparison Control Register
sahilmgandhi	18:6a4db94011d3	11801	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	11802	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	11803	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	11804	* \|[0] \|AUP \|Accept Unicast Packet
sahilmgandhi	18:6a4db94011d3	11805	* \| \| \|The AUP controls the unicast packet reception.
sahilmgandhi	18:6a4db94011d3	11806	* \| \| \|If AUP is enabled, EMAC receives all incoming packet its destination MAC address is a unicast address.
sahilmgandhi	18:6a4db94011d3	11807	* \| \| \|0 = EMAC receives packet depends on the CAM comparison result.
sahilmgandhi	18:6a4db94011d3	11808	* \| \| \|1 = EMAC receives all unicast packets.
sahilmgandhi	18:6a4db94011d3	11809	* \|[1] \|AMP \|Accept Multicast Packet
sahilmgandhi	18:6a4db94011d3	11810	* \| \| \|The AMP controls the multicast packet reception.
sahilmgandhi	18:6a4db94011d3	11811	* \| \| \|If AMP is enabled, EMAC receives all incoming packet its destination MAC address is a multicast address.
sahilmgandhi	18:6a4db94011d3	11812	* \| \| \|0 = EMAC receives packet depends on the CAM comparison result.
sahilmgandhi	18:6a4db94011d3	11813	* \| \| \|1 = EMAC receives all multicast packets.
sahilmgandhi	18:6a4db94011d3	11814	* \|[2] \|ABP \|Accept Broadcast Packet
sahilmgandhi	18:6a4db94011d3	11815	* \| \| \|The ABP controls the broadcast packet reception.
sahilmgandhi	18:6a4db94011d3	11816	* \| \| \|If ABP is enabled, EMAC receives all incoming packet its destination MAC address is a broadcast address.
sahilmgandhi	18:6a4db94011d3	11817	* \| \| \|0 = EMAC receives packet depends on the CAM comparison result.
sahilmgandhi	18:6a4db94011d3	11818	* \| \| \|1 = EMAC receives all broadcast packets.
sahilmgandhi	18:6a4db94011d3	11819	* \|[3] \|COMPEN \|Complement CAM Comparison Enable
sahilmgandhi	18:6a4db94011d3	11820	* \| \| \|The COMPEN controls the complement of the CAM comparison result.
sahilmgandhi	18:6a4db94011d3	11821	* \| \| \|If the CMPEN and COMPEN are both enabled, the incoming packet with specific destination MAC address configured in CAM entry will be dropped.
sahilmgandhi	18:6a4db94011d3	11822	* \| \| \|And the incoming packet with destination MAC address does not configured in any CAM entry will be received.
sahilmgandhi	18:6a4db94011d3	11823	* \| \| \|0 = The CAM comparison result does not complement.
sahilmgandhi	18:6a4db94011d3	11824	* \| \| \|1 = The CAM comparison result complemented.
sahilmgandhi	18:6a4db94011d3	11825	* \|[4] \|CMPEN \|CAM Compare Enable
sahilmgandhi	18:6a4db94011d3	11826	* \| \| \|The CMPEN controls the enable of CAM comparison function for destination MAC address recognition.
sahilmgandhi	18:6a4db94011d3	11827	* \| \| \|If software wants to receive a packet with specific destination MAC address, configures the MAC address into CAM 12~0, then enables that CAM entry and set CMPEN to 1.
sahilmgandhi	18:6a4db94011d3	11828	* \| \| \|0 = CAM comparison function for destination MAC address recognition disabled.
sahilmgandhi	18:6a4db94011d3	11829	* \| \| \|1 = CAM comparison function for destination MAC address recognition enabled.
sahilmgandhi	18:6a4db94011d3	11830	*/
sahilmgandhi	18:6a4db94011d3	11831	__IO uint32_t CAMCTL;
sahilmgandhi	18:6a4db94011d3	11832
sahilmgandhi	18:6a4db94011d3	11833	/**
sahilmgandhi	18:6a4db94011d3	11834	* CAMEN
sahilmgandhi	18:6a4db94011d3	11835	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	11836	* Offset: 0x04 CAM Enable Register
sahilmgandhi	18:6a4db94011d3	11837	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	11838	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	11839	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	11840	* \|[0] \|CAMxEN \|CAM Entry X Enable Control
sahilmgandhi	18:6a4db94011d3	11841	* \| \| \|The CAMxEN controls the validation of CAM entry x.
sahilmgandhi	18:6a4db94011d3	11842	* \| \| \|The CAM entry 13, 14 and 15 are for PAUSE control frame transmission.
sahilmgandhi	18:6a4db94011d3	11843	* \| \| \|If software wants to transmit a PAUSE control frame out to network, the enable bits of these three CAM entries all must be enabled first.
sahilmgandhi	18:6a4db94011d3	11844	* \| \| \|0 = CAM entry x Disabled.
sahilmgandhi	18:6a4db94011d3	11845	* \| \| \|1 = CAM entry x Enabled.
sahilmgandhi	18:6a4db94011d3	11846	*/
sahilmgandhi	18:6a4db94011d3	11847	__IO uint32_t CAMEN;
sahilmgandhi	18:6a4db94011d3	11848
sahilmgandhi	18:6a4db94011d3	11849	/**
sahilmgandhi	18:6a4db94011d3	11850	* CAM0M
sahilmgandhi	18:6a4db94011d3	11851	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	11852	* Offset: 0x08 CAM0 Most Significant Word Register
sahilmgandhi	18:6a4db94011d3	11853	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	11854	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	11855	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	11856	* \|[0:7] \|MACADDR2 \|MAC Address Byte 2
sahilmgandhi	18:6a4db94011d3	11857	* \|[8:15] \|MACADDR3 \|MAC Address Byte 3
sahilmgandhi	18:6a4db94011d3	11858	* \|[16:23] \|MACADDR4 \|MAC Address Byte 4
sahilmgandhi	18:6a4db94011d3	11859	* \|[24:31] \|MACADDR5 \|MAC Address Byte 5
sahilmgandhi	18:6a4db94011d3	11860	* \| \| \|The CAMxM keeps the bit 47~16 of MAC address.
sahilmgandhi	18:6a4db94011d3	11861	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	11862	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	11863	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	11864	*/
sahilmgandhi	18:6a4db94011d3	11865	__IO uint32_t CAM0M;
sahilmgandhi	18:6a4db94011d3	11866
sahilmgandhi	18:6a4db94011d3	11867	/**
sahilmgandhi	18:6a4db94011d3	11868	* CAM0L
sahilmgandhi	18:6a4db94011d3	11869	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	11870	* Offset: 0x0C CAM0 Least Significant Word Register
sahilmgandhi	18:6a4db94011d3	11871	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	11872	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	11873	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	11874	* \|[16:23] \|MACADDR0 \|MAC Address Byte 0
sahilmgandhi	18:6a4db94011d3	11875	* \|[24:31] \|MACADDR1 \|MAC Address Byte 1
sahilmgandhi	18:6a4db94011d3	11876	* \| \| \|The CAMxL keeps the bit 15~0 of MAC address.
sahilmgandhi	18:6a4db94011d3	11877	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	11878	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	11879	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	11880	*/
sahilmgandhi	18:6a4db94011d3	11881	__IO uint32_t CAM0L;
sahilmgandhi	18:6a4db94011d3	11882
sahilmgandhi	18:6a4db94011d3	11883	/**
sahilmgandhi	18:6a4db94011d3	11884	* CAM1M
sahilmgandhi	18:6a4db94011d3	11885	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	11886	* Offset: 0x10 CAM1 Most Significant Word Register
sahilmgandhi	18:6a4db94011d3	11887	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	11888	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	11889	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	11890	* \|[0:7] \|MACADDR2 \|MAC Address Byte 2
sahilmgandhi	18:6a4db94011d3	11891	* \|[8:15] \|MACADDR3 \|MAC Address Byte 3
sahilmgandhi	18:6a4db94011d3	11892	* \|[16:23] \|MACADDR4 \|MAC Address Byte 4
sahilmgandhi	18:6a4db94011d3	11893	* \|[24:31] \|MACADDR5 \|MAC Address Byte 5
sahilmgandhi	18:6a4db94011d3	11894	* \| \| \|The CAMxM keeps the bit 47~16 of MAC address.
sahilmgandhi	18:6a4db94011d3	11895	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	11896	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	11897	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	11898	*/
sahilmgandhi	18:6a4db94011d3	11899	__IO uint32_t CAM1M;
sahilmgandhi	18:6a4db94011d3	11900
sahilmgandhi	18:6a4db94011d3	11901	/**
sahilmgandhi	18:6a4db94011d3	11902	* CAM1L
sahilmgandhi	18:6a4db94011d3	11903	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	11904	* Offset: 0x14 CAM1 Least Significant Word Register
sahilmgandhi	18:6a4db94011d3	11905	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	11906	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	11907	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	11908	* \|[16:23] \|MACADDR0 \|MAC Address Byte 0
sahilmgandhi	18:6a4db94011d3	11909	* \|[24:31] \|MACADDR1 \|MAC Address Byte 1
sahilmgandhi	18:6a4db94011d3	11910	* \| \| \|The CAMxL keeps the bit 15~0 of MAC address.
sahilmgandhi	18:6a4db94011d3	11911	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	11912	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	11913	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	11914	*/
sahilmgandhi	18:6a4db94011d3	11915	__IO uint32_t CAM1L;
sahilmgandhi	18:6a4db94011d3	11916
sahilmgandhi	18:6a4db94011d3	11917	/**
sahilmgandhi	18:6a4db94011d3	11918	* CAM2M
sahilmgandhi	18:6a4db94011d3	11919	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	11920	* Offset: 0x18 CAM2 Most Significant Word Register
sahilmgandhi	18:6a4db94011d3	11921	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	11922	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	11923	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	11924	* \|[0:7] \|MACADDR2 \|MAC Address Byte 2
sahilmgandhi	18:6a4db94011d3	11925	* \|[8:15] \|MACADDR3 \|MAC Address Byte 3
sahilmgandhi	18:6a4db94011d3	11926	* \|[16:23] \|MACADDR4 \|MAC Address Byte 4
sahilmgandhi	18:6a4db94011d3	11927	* \|[24:31] \|MACADDR5 \|MAC Address Byte 5
sahilmgandhi	18:6a4db94011d3	11928	* \| \| \|The CAMxM keeps the bit 47~16 of MAC address.
sahilmgandhi	18:6a4db94011d3	11929	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	11930	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	11931	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	11932	*/
sahilmgandhi	18:6a4db94011d3	11933	__IO uint32_t CAM2M;
sahilmgandhi	18:6a4db94011d3	11934
sahilmgandhi	18:6a4db94011d3	11935	/**
sahilmgandhi	18:6a4db94011d3	11936	* CAM2L
sahilmgandhi	18:6a4db94011d3	11937	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	11938	* Offset: 0x1C CAM2 Least Significant Word Register
sahilmgandhi	18:6a4db94011d3	11939	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	11940	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	11941	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	11942	* \|[16:23] \|MACADDR0 \|MAC Address Byte 0
sahilmgandhi	18:6a4db94011d3	11943	* \|[24:31] \|MACADDR1 \|MAC Address Byte 1
sahilmgandhi	18:6a4db94011d3	11944	* \| \| \|The CAMxL keeps the bit 15~0 of MAC address.
sahilmgandhi	18:6a4db94011d3	11945	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	11946	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	11947	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	11948	*/
sahilmgandhi	18:6a4db94011d3	11949	__IO uint32_t CAM2L;
sahilmgandhi	18:6a4db94011d3	11950
sahilmgandhi	18:6a4db94011d3	11951	/**
sahilmgandhi	18:6a4db94011d3	11952	* CAM3M
sahilmgandhi	18:6a4db94011d3	11953	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	11954	* Offset: 0x20 CAM3 Most Significant Word Register
sahilmgandhi	18:6a4db94011d3	11955	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	11956	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	11957	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	11958	* \|[0:7] \|MACADDR2 \|MAC Address Byte 2
sahilmgandhi	18:6a4db94011d3	11959	* \|[8:15] \|MACADDR3 \|MAC Address Byte 3
sahilmgandhi	18:6a4db94011d3	11960	* \|[16:23] \|MACADDR4 \|MAC Address Byte 4
sahilmgandhi	18:6a4db94011d3	11961	* \|[24:31] \|MACADDR5 \|MAC Address Byte 5
sahilmgandhi	18:6a4db94011d3	11962	* \| \| \|The CAMxM keeps the bit 47~16 of MAC address.
sahilmgandhi	18:6a4db94011d3	11963	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	11964	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	11965	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	11966	*/
sahilmgandhi	18:6a4db94011d3	11967	__IO uint32_t CAM3M;
sahilmgandhi	18:6a4db94011d3	11968
sahilmgandhi	18:6a4db94011d3	11969	/**
sahilmgandhi	18:6a4db94011d3	11970	* CAM3L
sahilmgandhi	18:6a4db94011d3	11971	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	11972	* Offset: 0x24 CAM3 Least Significant Word Register
sahilmgandhi	18:6a4db94011d3	11973	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	11974	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	11975	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	11976	* \|[16:23] \|MACADDR0 \|MAC Address Byte 0
sahilmgandhi	18:6a4db94011d3	11977	* \|[24:31] \|MACADDR1 \|MAC Address Byte 1
sahilmgandhi	18:6a4db94011d3	11978	* \| \| \|The CAMxL keeps the bit 15~0 of MAC address.
sahilmgandhi	18:6a4db94011d3	11979	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	11980	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	11981	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	11982	*/
sahilmgandhi	18:6a4db94011d3	11983	__IO uint32_t CAM3L;
sahilmgandhi	18:6a4db94011d3	11984
sahilmgandhi	18:6a4db94011d3	11985	/**
sahilmgandhi	18:6a4db94011d3	11986	* CAM4M
sahilmgandhi	18:6a4db94011d3	11987	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	11988	* Offset: 0x28 CAM4 Most Significant Word Register
sahilmgandhi	18:6a4db94011d3	11989	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	11990	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	11991	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	11992	* \|[0:7] \|MACADDR2 \|MAC Address Byte 2
sahilmgandhi	18:6a4db94011d3	11993	* \|[8:15] \|MACADDR3 \|MAC Address Byte 3
sahilmgandhi	18:6a4db94011d3	11994	* \|[16:23] \|MACADDR4 \|MAC Address Byte 4
sahilmgandhi	18:6a4db94011d3	11995	* \|[24:31] \|MACADDR5 \|MAC Address Byte 5
sahilmgandhi	18:6a4db94011d3	11996	* \| \| \|The CAMxM keeps the bit 47~16 of MAC address.
sahilmgandhi	18:6a4db94011d3	11997	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	11998	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	11999	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	12000	*/
sahilmgandhi	18:6a4db94011d3	12001	__IO uint32_t CAM4M;
sahilmgandhi	18:6a4db94011d3	12002
sahilmgandhi	18:6a4db94011d3	12003	/**
sahilmgandhi	18:6a4db94011d3	12004	* CAM4L
sahilmgandhi	18:6a4db94011d3	12005	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12006	* Offset: 0x2C CAM4 Least Significant Word Register
sahilmgandhi	18:6a4db94011d3	12007	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12008	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12009	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12010	* \|[16:23] \|MACADDR0 \|MAC Address Byte 0
sahilmgandhi	18:6a4db94011d3	12011	* \|[24:31] \|MACADDR1 \|MAC Address Byte 1
sahilmgandhi	18:6a4db94011d3	12012	* \| \| \|The CAMxL keeps the bit 15~0 of MAC address.
sahilmgandhi	18:6a4db94011d3	12013	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	12014	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	12015	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	12016	*/
sahilmgandhi	18:6a4db94011d3	12017	__IO uint32_t CAM4L;
sahilmgandhi	18:6a4db94011d3	12018
sahilmgandhi	18:6a4db94011d3	12019	/**
sahilmgandhi	18:6a4db94011d3	12020	* CAM5M
sahilmgandhi	18:6a4db94011d3	12021	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12022	* Offset: 0x30 CAM5 Most Significant Word Register
sahilmgandhi	18:6a4db94011d3	12023	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12024	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12025	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12026	* \|[0:7] \|MACADDR2 \|MAC Address Byte 2
sahilmgandhi	18:6a4db94011d3	12027	* \|[8:15] \|MACADDR3 \|MAC Address Byte 3
sahilmgandhi	18:6a4db94011d3	12028	* \|[16:23] \|MACADDR4 \|MAC Address Byte 4
sahilmgandhi	18:6a4db94011d3	12029	* \|[24:31] \|MACADDR5 \|MAC Address Byte 5
sahilmgandhi	18:6a4db94011d3	12030	* \| \| \|The CAMxM keeps the bit 47~16 of MAC address.
sahilmgandhi	18:6a4db94011d3	12031	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	12032	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	12033	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	12034	*/
sahilmgandhi	18:6a4db94011d3	12035	__IO uint32_t CAM5M;
sahilmgandhi	18:6a4db94011d3	12036
sahilmgandhi	18:6a4db94011d3	12037	/**
sahilmgandhi	18:6a4db94011d3	12038	* CAM5L
sahilmgandhi	18:6a4db94011d3	12039	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12040	* Offset: 0x34 CAM5 Least Significant Word Register
sahilmgandhi	18:6a4db94011d3	12041	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12042	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12043	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12044	* \|[16:23] \|MACADDR0 \|MAC Address Byte 0
sahilmgandhi	18:6a4db94011d3	12045	* \|[24:31] \|MACADDR1 \|MAC Address Byte 1
sahilmgandhi	18:6a4db94011d3	12046	* \| \| \|The CAMxL keeps the bit 15~0 of MAC address.
sahilmgandhi	18:6a4db94011d3	12047	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	12048	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	12049	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	12050	*/
sahilmgandhi	18:6a4db94011d3	12051	__IO uint32_t CAM5L;
sahilmgandhi	18:6a4db94011d3	12052
sahilmgandhi	18:6a4db94011d3	12053	/**
sahilmgandhi	18:6a4db94011d3	12054	* CAM6M
sahilmgandhi	18:6a4db94011d3	12055	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12056	* Offset: 0x38 CAM6 Most Significant Word Register
sahilmgandhi	18:6a4db94011d3	12057	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12058	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12059	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12060	* \|[0:7] \|MACADDR2 \|MAC Address Byte 2
sahilmgandhi	18:6a4db94011d3	12061	* \|[8:15] \|MACADDR3 \|MAC Address Byte 3
sahilmgandhi	18:6a4db94011d3	12062	* \|[16:23] \|MACADDR4 \|MAC Address Byte 4
sahilmgandhi	18:6a4db94011d3	12063	* \|[24:31] \|MACADDR5 \|MAC Address Byte 5
sahilmgandhi	18:6a4db94011d3	12064	* \| \| \|The CAMxM keeps the bit 47~16 of MAC address.
sahilmgandhi	18:6a4db94011d3	12065	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	12066	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	12067	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	12068	*/
sahilmgandhi	18:6a4db94011d3	12069	__IO uint32_t CAM6M;
sahilmgandhi	18:6a4db94011d3	12070
sahilmgandhi	18:6a4db94011d3	12071	/**
sahilmgandhi	18:6a4db94011d3	12072	* CAM6L
sahilmgandhi	18:6a4db94011d3	12073	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12074	* Offset: 0x3C CAM6 Least Significant Word Register
sahilmgandhi	18:6a4db94011d3	12075	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12076	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12077	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12078	* \|[16:23] \|MACADDR0 \|MAC Address Byte 0
sahilmgandhi	18:6a4db94011d3	12079	* \|[24:31] \|MACADDR1 \|MAC Address Byte 1
sahilmgandhi	18:6a4db94011d3	12080	* \| \| \|The CAMxL keeps the bit 15~0 of MAC address.
sahilmgandhi	18:6a4db94011d3	12081	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	12082	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	12083	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	12084	*/
sahilmgandhi	18:6a4db94011d3	12085	__IO uint32_t CAM6L;
sahilmgandhi	18:6a4db94011d3	12086
sahilmgandhi	18:6a4db94011d3	12087	/**
sahilmgandhi	18:6a4db94011d3	12088	* CAM7M
sahilmgandhi	18:6a4db94011d3	12089	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12090	* Offset: 0x40 CAM7 Most Significant Word Register
sahilmgandhi	18:6a4db94011d3	12091	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12092	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12093	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12094	* \|[0:7] \|MACADDR2 \|MAC Address Byte 2
sahilmgandhi	18:6a4db94011d3	12095	* \|[8:15] \|MACADDR3 \|MAC Address Byte 3
sahilmgandhi	18:6a4db94011d3	12096	* \|[16:23] \|MACADDR4 \|MAC Address Byte 4
sahilmgandhi	18:6a4db94011d3	12097	* \|[24:31] \|MACADDR5 \|MAC Address Byte 5
sahilmgandhi	18:6a4db94011d3	12098	* \| \| \|The CAMxM keeps the bit 47~16 of MAC address.
sahilmgandhi	18:6a4db94011d3	12099	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	12100	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	12101	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	12102	*/
sahilmgandhi	18:6a4db94011d3	12103	__IO uint32_t CAM7M;
sahilmgandhi	18:6a4db94011d3	12104
sahilmgandhi	18:6a4db94011d3	12105	/**
sahilmgandhi	18:6a4db94011d3	12106	* CAM7L
sahilmgandhi	18:6a4db94011d3	12107	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12108	* Offset: 0x44 CAM7 Least Significant Word Register
sahilmgandhi	18:6a4db94011d3	12109	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12110	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12111	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12112	* \|[16:23] \|MACADDR0 \|MAC Address Byte 0
sahilmgandhi	18:6a4db94011d3	12113	* \|[24:31] \|MACADDR1 \|MAC Address Byte 1
sahilmgandhi	18:6a4db94011d3	12114	* \| \| \|The CAMxL keeps the bit 15~0 of MAC address.
sahilmgandhi	18:6a4db94011d3	12115	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	12116	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	12117	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	12118	*/
sahilmgandhi	18:6a4db94011d3	12119	__IO uint32_t CAM7L;
sahilmgandhi	18:6a4db94011d3	12120
sahilmgandhi	18:6a4db94011d3	12121	/**
sahilmgandhi	18:6a4db94011d3	12122	* CAM8M
sahilmgandhi	18:6a4db94011d3	12123	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12124	* Offset: 0x48 CAM8 Most Significant Word Register
sahilmgandhi	18:6a4db94011d3	12125	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12126	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12127	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12128	* \|[0:7] \|MACADDR2 \|MAC Address Byte 2
sahilmgandhi	18:6a4db94011d3	12129	* \|[8:15] \|MACADDR3 \|MAC Address Byte 3
sahilmgandhi	18:6a4db94011d3	12130	* \|[16:23] \|MACADDR4 \|MAC Address Byte 4
sahilmgandhi	18:6a4db94011d3	12131	* \|[24:31] \|MACADDR5 \|MAC Address Byte 5
sahilmgandhi	18:6a4db94011d3	12132	* \| \| \|The CAMxM keeps the bit 47~16 of MAC address.
sahilmgandhi	18:6a4db94011d3	12133	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	12134	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	12135	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	12136	*/
sahilmgandhi	18:6a4db94011d3	12137	__IO uint32_t CAM8M;
sahilmgandhi	18:6a4db94011d3	12138
sahilmgandhi	18:6a4db94011d3	12139	/**
sahilmgandhi	18:6a4db94011d3	12140	* CAM8L
sahilmgandhi	18:6a4db94011d3	12141	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12142	* Offset: 0x4C CAM8 Least Significant Word Register
sahilmgandhi	18:6a4db94011d3	12143	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12144	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12145	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12146	* \|[16:23] \|MACADDR0 \|MAC Address Byte 0
sahilmgandhi	18:6a4db94011d3	12147	* \|[24:31] \|MACADDR1 \|MAC Address Byte 1
sahilmgandhi	18:6a4db94011d3	12148	* \| \| \|The CAMxL keeps the bit 15~0 of MAC address.
sahilmgandhi	18:6a4db94011d3	12149	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	12150	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	12151	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	12152	*/
sahilmgandhi	18:6a4db94011d3	12153	__IO uint32_t CAM8L;
sahilmgandhi	18:6a4db94011d3	12154
sahilmgandhi	18:6a4db94011d3	12155	/**
sahilmgandhi	18:6a4db94011d3	12156	* CAM9M
sahilmgandhi	18:6a4db94011d3	12157	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12158	* Offset: 0x50 CAM9 Most Significant Word Register
sahilmgandhi	18:6a4db94011d3	12159	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12160	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12161	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12162	* \|[0:7] \|MACADDR2 \|MAC Address Byte 2
sahilmgandhi	18:6a4db94011d3	12163	* \|[8:15] \|MACADDR3 \|MAC Address Byte 3
sahilmgandhi	18:6a4db94011d3	12164	* \|[16:23] \|MACADDR4 \|MAC Address Byte 4
sahilmgandhi	18:6a4db94011d3	12165	* \|[24:31] \|MACADDR5 \|MAC Address Byte 5
sahilmgandhi	18:6a4db94011d3	12166	* \| \| \|The CAMxM keeps the bit 47~16 of MAC address.
sahilmgandhi	18:6a4db94011d3	12167	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	12168	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	12169	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	12170	*/
sahilmgandhi	18:6a4db94011d3	12171	__IO uint32_t CAM9M;
sahilmgandhi	18:6a4db94011d3	12172
sahilmgandhi	18:6a4db94011d3	12173	/**
sahilmgandhi	18:6a4db94011d3	12174	* CAM9L
sahilmgandhi	18:6a4db94011d3	12175	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12176	* Offset: 0x54 CAM9 Least Significant Word Register
sahilmgandhi	18:6a4db94011d3	12177	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12178	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12179	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12180	* \|[16:23] \|MACADDR0 \|MAC Address Byte 0
sahilmgandhi	18:6a4db94011d3	12181	* \|[24:31] \|MACADDR1 \|MAC Address Byte 1
sahilmgandhi	18:6a4db94011d3	12182	* \| \| \|The CAMxL keeps the bit 15~0 of MAC address.
sahilmgandhi	18:6a4db94011d3	12183	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	12184	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	12185	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	12186	*/
sahilmgandhi	18:6a4db94011d3	12187	__IO uint32_t CAM9L;
sahilmgandhi	18:6a4db94011d3	12188
sahilmgandhi	18:6a4db94011d3	12189	/**
sahilmgandhi	18:6a4db94011d3	12190	* CAM10M
sahilmgandhi	18:6a4db94011d3	12191	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12192	* Offset: 0x58 CAM10 Most Significant Word Register
sahilmgandhi	18:6a4db94011d3	12193	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12194	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12195	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12196	* \|[0:7] \|MACADDR2 \|MAC Address Byte 2
sahilmgandhi	18:6a4db94011d3	12197	* \|[8:15] \|MACADDR3 \|MAC Address Byte 3
sahilmgandhi	18:6a4db94011d3	12198	* \|[16:23] \|MACADDR4 \|MAC Address Byte 4
sahilmgandhi	18:6a4db94011d3	12199	* \|[24:31] \|MACADDR5 \|MAC Address Byte 5
sahilmgandhi	18:6a4db94011d3	12200	* \| \| \|The CAMxM keeps the bit 47~16 of MAC address.
sahilmgandhi	18:6a4db94011d3	12201	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	12202	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	12203	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	12204	*/
sahilmgandhi	18:6a4db94011d3	12205	__IO uint32_t CAM10M;
sahilmgandhi	18:6a4db94011d3	12206
sahilmgandhi	18:6a4db94011d3	12207	/**
sahilmgandhi	18:6a4db94011d3	12208	* CAM10L
sahilmgandhi	18:6a4db94011d3	12209	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12210	* Offset: 0x5C CAM10 Least Significant Word Register
sahilmgandhi	18:6a4db94011d3	12211	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12212	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12213	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12214	* \|[16:23] \|MACADDR0 \|MAC Address Byte 0
sahilmgandhi	18:6a4db94011d3	12215	* \|[24:31] \|MACADDR1 \|MAC Address Byte 1
sahilmgandhi	18:6a4db94011d3	12216	* \| \| \|The CAMxL keeps the bit 15~0 of MAC address.
sahilmgandhi	18:6a4db94011d3	12217	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	12218	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	12219	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	12220	*/
sahilmgandhi	18:6a4db94011d3	12221	__IO uint32_t CAM10L;
sahilmgandhi	18:6a4db94011d3	12222
sahilmgandhi	18:6a4db94011d3	12223	/**
sahilmgandhi	18:6a4db94011d3	12224	* CAM11M
sahilmgandhi	18:6a4db94011d3	12225	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12226	* Offset: 0x60 CAM11 Most Significant Word Register
sahilmgandhi	18:6a4db94011d3	12227	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12228	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12229	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12230	* \|[0:7] \|MACADDR2 \|MAC Address Byte 2
sahilmgandhi	18:6a4db94011d3	12231	* \|[8:15] \|MACADDR3 \|MAC Address Byte 3
sahilmgandhi	18:6a4db94011d3	12232	* \|[16:23] \|MACADDR4 \|MAC Address Byte 4
sahilmgandhi	18:6a4db94011d3	12233	* \|[24:31] \|MACADDR5 \|MAC Address Byte 5
sahilmgandhi	18:6a4db94011d3	12234	* \| \| \|The CAMxM keeps the bit 47~16 of MAC address.
sahilmgandhi	18:6a4db94011d3	12235	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	12236	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	12237	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	12238	*/
sahilmgandhi	18:6a4db94011d3	12239	__IO uint32_t CAM11M;
sahilmgandhi	18:6a4db94011d3	12240
sahilmgandhi	18:6a4db94011d3	12241	/**
sahilmgandhi	18:6a4db94011d3	12242	* CAM11L
sahilmgandhi	18:6a4db94011d3	12243	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12244	* Offset: 0x64 CAM11 Least Significant Word Register
sahilmgandhi	18:6a4db94011d3	12245	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12246	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12247	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12248	* \|[16:23] \|MACADDR0 \|MAC Address Byte 0
sahilmgandhi	18:6a4db94011d3	12249	* \|[24:31] \|MACADDR1 \|MAC Address Byte 1
sahilmgandhi	18:6a4db94011d3	12250	* \| \| \|The CAMxL keeps the bit 15~0 of MAC address.
sahilmgandhi	18:6a4db94011d3	12251	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	12252	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	12253	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	12254	*/
sahilmgandhi	18:6a4db94011d3	12255	__IO uint32_t CAM11L;
sahilmgandhi	18:6a4db94011d3	12256
sahilmgandhi	18:6a4db94011d3	12257	/**
sahilmgandhi	18:6a4db94011d3	12258	* CAM12M
sahilmgandhi	18:6a4db94011d3	12259	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12260	* Offset: 0x68 CAM12 Most Significant Word Register
sahilmgandhi	18:6a4db94011d3	12261	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12262	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12263	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12264	* \|[0:7] \|MACADDR2 \|MAC Address Byte 2
sahilmgandhi	18:6a4db94011d3	12265	* \|[8:15] \|MACADDR3 \|MAC Address Byte 3
sahilmgandhi	18:6a4db94011d3	12266	* \|[16:23] \|MACADDR4 \|MAC Address Byte 4
sahilmgandhi	18:6a4db94011d3	12267	* \|[24:31] \|MACADDR5 \|MAC Address Byte 5
sahilmgandhi	18:6a4db94011d3	12268	* \| \| \|The CAMxM keeps the bit 47~16 of MAC address.
sahilmgandhi	18:6a4db94011d3	12269	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	12270	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	12271	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	12272	*/
sahilmgandhi	18:6a4db94011d3	12273	__IO uint32_t CAM12M;
sahilmgandhi	18:6a4db94011d3	12274
sahilmgandhi	18:6a4db94011d3	12275	/**
sahilmgandhi	18:6a4db94011d3	12276	* CAM12L
sahilmgandhi	18:6a4db94011d3	12277	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12278	* Offset: 0x6C CAM12 Least Significant Word Register
sahilmgandhi	18:6a4db94011d3	12279	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12280	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12281	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12282	* \|[16:23] \|MACADDR0 \|MAC Address Byte 0
sahilmgandhi	18:6a4db94011d3	12283	* \|[24:31] \|MACADDR1 \|MAC Address Byte 1
sahilmgandhi	18:6a4db94011d3	12284	* \| \| \|The CAMxL keeps the bit 15~0 of MAC address.
sahilmgandhi	18:6a4db94011d3	12285	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	12286	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	12287	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	12288	*/
sahilmgandhi	18:6a4db94011d3	12289	__IO uint32_t CAM12L;
sahilmgandhi	18:6a4db94011d3	12290
sahilmgandhi	18:6a4db94011d3	12291	/**
sahilmgandhi	18:6a4db94011d3	12292	* CAM13M
sahilmgandhi	18:6a4db94011d3	12293	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12294	* Offset: 0x70 CAM13 Most Significant Word Register
sahilmgandhi	18:6a4db94011d3	12295	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12296	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12297	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12298	* \|[0:7] \|MACADDR2 \|MAC Address Byte 2
sahilmgandhi	18:6a4db94011d3	12299	* \|[8:15] \|MACADDR3 \|MAC Address Byte 3
sahilmgandhi	18:6a4db94011d3	12300	* \|[16:23] \|MACADDR4 \|MAC Address Byte 4
sahilmgandhi	18:6a4db94011d3	12301	* \|[24:31] \|MACADDR5 \|MAC Address Byte 5
sahilmgandhi	18:6a4db94011d3	12302	* \| \| \|The CAMxM keeps the bit 47~16 of MAC address.
sahilmgandhi	18:6a4db94011d3	12303	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	12304	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	12305	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	12306	*/
sahilmgandhi	18:6a4db94011d3	12307	__IO uint32_t CAM13M;
sahilmgandhi	18:6a4db94011d3	12308
sahilmgandhi	18:6a4db94011d3	12309	/**
sahilmgandhi	18:6a4db94011d3	12310	* CAM13L
sahilmgandhi	18:6a4db94011d3	12311	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12312	* Offset: 0x74 CAM13 Least Significant Word Register
sahilmgandhi	18:6a4db94011d3	12313	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12314	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12315	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12316	* \|[16:23] \|MACADDR0 \|MAC Address Byte 0
sahilmgandhi	18:6a4db94011d3	12317	* \|[24:31] \|MACADDR1 \|MAC Address Byte 1
sahilmgandhi	18:6a4db94011d3	12318	* \| \| \|The CAMxL keeps the bit 15~0 of MAC address.
sahilmgandhi	18:6a4db94011d3	12319	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	12320	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	12321	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	12322	*/
sahilmgandhi	18:6a4db94011d3	12323	__IO uint32_t CAM13L;
sahilmgandhi	18:6a4db94011d3	12324
sahilmgandhi	18:6a4db94011d3	12325	/**
sahilmgandhi	18:6a4db94011d3	12326	* CAM14M
sahilmgandhi	18:6a4db94011d3	12327	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12328	* Offset: 0x78 CAM14 Most Significant Word Register
sahilmgandhi	18:6a4db94011d3	12329	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12330	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12331	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12332	* \|[0:7] \|MACADDR2 \|MAC Address Byte 2
sahilmgandhi	18:6a4db94011d3	12333	* \|[8:15] \|MACADDR3 \|MAC Address Byte 3
sahilmgandhi	18:6a4db94011d3	12334	* \|[16:23] \|MACADDR4 \|MAC Address Byte 4
sahilmgandhi	18:6a4db94011d3	12335	* \|[24:31] \|MACADDR5 \|MAC Address Byte 5
sahilmgandhi	18:6a4db94011d3	12336	* \| \| \|The CAMxM keeps the bit 47~16 of MAC address.
sahilmgandhi	18:6a4db94011d3	12337	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	12338	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	12339	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	12340	*/
sahilmgandhi	18:6a4db94011d3	12341	__IO uint32_t CAM14M;
sahilmgandhi	18:6a4db94011d3	12342
sahilmgandhi	18:6a4db94011d3	12343	/**
sahilmgandhi	18:6a4db94011d3	12344	* CAM14L
sahilmgandhi	18:6a4db94011d3	12345	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12346	* Offset: 0x7C CAM14 Least Significant Word Register
sahilmgandhi	18:6a4db94011d3	12347	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12348	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12349	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12350	* \|[16:23] \|MACADDR0 \|MAC Address Byte 0
sahilmgandhi	18:6a4db94011d3	12351	* \|[24:31] \|MACADDR1 \|MAC Address Byte 1
sahilmgandhi	18:6a4db94011d3	12352	* \| \| \|The CAMxL keeps the bit 15~0 of MAC address.
sahilmgandhi	18:6a4db94011d3	12353	* \| \| \|The x can be the 0~14.
sahilmgandhi	18:6a4db94011d3	12354	* \| \| \|The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
sahilmgandhi	18:6a4db94011d3	12355	* \| \| \|For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
sahilmgandhi	18:6a4db94011d3	12356	*/
sahilmgandhi	18:6a4db94011d3	12357	__IO uint32_t CAM14L;
sahilmgandhi	18:6a4db94011d3	12358
sahilmgandhi	18:6a4db94011d3	12359	/**
sahilmgandhi	18:6a4db94011d3	12360	* CAM15MSB
sahilmgandhi	18:6a4db94011d3	12361	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12362	* Offset: 0x80 CAM15 Most Significant Word Register
sahilmgandhi	18:6a4db94011d3	12363	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12364	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12365	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12366	* \|[0:15] \|OPCODE \|OP Code Field of PAUSE Control Frame
sahilmgandhi	18:6a4db94011d3	12367	* \| \| \|In the PAUSE control frame, an op code field defined and is 0x0001.
sahilmgandhi	18:6a4db94011d3	12368	* \|[16:31] \|LENGTH \|LENGTH Field of PAUSE Control Frame
sahilmgandhi	18:6a4db94011d3	12369	* \| \| \|In the PAUSE control frame, a LENGTH field defined and is 0x8808.
sahilmgandhi	18:6a4db94011d3	12370	*/
sahilmgandhi	18:6a4db94011d3	12371	__IO uint32_t CAM15MSB;
sahilmgandhi	18:6a4db94011d3	12372
sahilmgandhi	18:6a4db94011d3	12373	/**
sahilmgandhi	18:6a4db94011d3	12374	* CAM15LSB
sahilmgandhi	18:6a4db94011d3	12375	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12376	* Offset: 0x84 CAM15 Least Significant Word Register
sahilmgandhi	18:6a4db94011d3	12377	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12378	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12379	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12380	* \|[24:31] \|OPERAND \|Pause Parameter
sahilmgandhi	18:6a4db94011d3	12381	* \| \| \|In the PAUSE control frame, an OPERAND field defined and controls how much time the destination Ethernet MAC Controller paused.
sahilmgandhi	18:6a4db94011d3	12382	* \| \| \|The unit of the OPERAND is a slot time, the 512 bits time.
sahilmgandhi	18:6a4db94011d3	12383	*/
sahilmgandhi	18:6a4db94011d3	12384	__IO uint32_t CAM15LSB;
sahilmgandhi	18:6a4db94011d3	12385
sahilmgandhi	18:6a4db94011d3	12386	/**
sahilmgandhi	18:6a4db94011d3	12387	* TXDSA
sahilmgandhi	18:6a4db94011d3	12388	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12389	* Offset: 0x88 Transmit Descriptor Link List Start Address Register
sahilmgandhi	18:6a4db94011d3	12390	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12391	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12392	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12393	* \|[0:31] \|TXDSA \|Transmit Descriptor Link-List Start Address
sahilmgandhi	18:6a4db94011d3	12394	* \| \| \|The TXDSA keeps the start address of transmit descriptor link-list.
sahilmgandhi	18:6a4db94011d3	12395	* \| \| \|If the software enables the bit TXON (EMAC_CTL[8]), the content of TXDSA will be loaded into the current transmit descriptor start address register (EMAC_CTXDSA).
sahilmgandhi	18:6a4db94011d3	12396	* \| \| \|The TXDSA does not be updated by EMAC.
sahilmgandhi	18:6a4db94011d3	12397	* \| \| \|During the operation, EMAC will ignore the bits [1:0] of TXDSA.
sahilmgandhi	18:6a4db94011d3	12398	* \| \| \|This means that each TX descriptor always must locate at word boundary memory address.
sahilmgandhi	18:6a4db94011d3	12399	*/
sahilmgandhi	18:6a4db94011d3	12400	__IO uint32_t TXDSA;
sahilmgandhi	18:6a4db94011d3	12401
sahilmgandhi	18:6a4db94011d3	12402	/**
sahilmgandhi	18:6a4db94011d3	12403	* RXDSA
sahilmgandhi	18:6a4db94011d3	12404	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12405	* Offset: 0x8C Receive Descriptor Link List Start Address Register
sahilmgandhi	18:6a4db94011d3	12406	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12407	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12408	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12409	* \|[0:31] \|RXDSA \|Receive Descriptor Link-List Start Address
sahilmgandhi	18:6a4db94011d3	12410	* \| \| \|The RXDSA keeps the start address of receive descriptor link-list.
sahilmgandhi	18:6a4db94011d3	12411	* \| \| \|If the S/W enables the bit RXON (EMAC_CTL[0]), the content of RXDSA will be loaded into the current receive descriptor start address register (EMAC_CRXDSA).
sahilmgandhi	18:6a4db94011d3	12412	* \| \| \|The RXDSA does not be updated by EMAC.
sahilmgandhi	18:6a4db94011d3	12413	* \| \| \|During the operation, EMAC will ignore the bits [1:0] of RXDSA.
sahilmgandhi	18:6a4db94011d3	12414	* \| \| \|This means that each RX descriptor always must locate at word boundary memory address.
sahilmgandhi	18:6a4db94011d3	12415	*/
sahilmgandhi	18:6a4db94011d3	12416	__IO uint32_t RXDSA;
sahilmgandhi	18:6a4db94011d3	12417
sahilmgandhi	18:6a4db94011d3	12418	/**
sahilmgandhi	18:6a4db94011d3	12419	* CTL
sahilmgandhi	18:6a4db94011d3	12420	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12421	* Offset: 0x90 MAC Control Register
sahilmgandhi	18:6a4db94011d3	12422	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12423	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12424	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12425	* \|[0] \|RXON \|Frame Reception ON
sahilmgandhi	18:6a4db94011d3	12426	* \| \| \|The RXON controls the normal packet reception of EMAC.
sahilmgandhi	18:6a4db94011d3	12427	* \| \| \|If the RXON is set to high, the EMAC starts the packet reception process, including the RX descriptor fetching, packet reception and RX descriptor modification.
sahilmgandhi	18:6a4db94011d3	12428	* \| \| \|It is necessary to finish EMAC initial sequence before enable RXON.
sahilmgandhi	18:6a4db94011d3	12429	* \| \| \|Otherwise, the EMAC operation is undefined.
sahilmgandhi	18:6a4db94011d3	12430	* \| \| \|If the RXON is disabled during EMAC is receiving an incoming packet, the EMAC stops the packet reception process after the current packet reception finished.
sahilmgandhi	18:6a4db94011d3	12431	* \| \| \|0 = Packet reception process stopped.
sahilmgandhi	18:6a4db94011d3	12432	* \| \| \|1 = Packet reception process started.
sahilmgandhi	18:6a4db94011d3	12433	* \|[1] \|ALP \|Accept Long Packet
sahilmgandhi	18:6a4db94011d3	12434	* \| \| \|The ALP controls the long packet, which packet length is greater than 1518 bytes, reception.
sahilmgandhi	18:6a4db94011d3	12435	* \| \| \|If the ALP is set to high, the EMAC will accept the long packet.
sahilmgandhi	18:6a4db94011d3	12436	* \| \| \|Otherwise, the long packet will be dropped.
sahilmgandhi	18:6a4db94011d3	12437	* \| \| \|0 = Ethernet MAC controller dropped the long packet.
sahilmgandhi	18:6a4db94011d3	12438	* \| \| \|1 = Ethernet MAC controller received the long packet.
sahilmgandhi	18:6a4db94011d3	12439	* \|[2] \|ARP \|Accept Runt Packet
sahilmgandhi	18:6a4db94011d3	12440	* \| \| \|The ARP controls the runt packet, which length is less than 64 bytes, reception.
sahilmgandhi	18:6a4db94011d3	12441	* \| \| \|If the ARP is set to high, the EMAC will accept the runt packet.
sahilmgandhi	18:6a4db94011d3	12442	* \| \| \|Otherwise, the runt packet will be dropped.
sahilmgandhi	18:6a4db94011d3	12443	* \| \| \|0 = Ethernet MAC controller dropped the runt packet.
sahilmgandhi	18:6a4db94011d3	12444	* \| \| \|1 = Ethernet MAC controller received the runt packet.
sahilmgandhi	18:6a4db94011d3	12445	* \|[3] \|ACP \|Accept Control Packet
sahilmgandhi	18:6a4db94011d3	12446	* \| \| \|The ACP controls the control frame reception.
sahilmgandhi	18:6a4db94011d3	12447	* \| \| \|If the ACP is set to high, the EMAC will accept the control frame.
sahilmgandhi	18:6a4db94011d3	12448	* \| \| \|Otherwise, the control frame will be dropped.
sahilmgandhi	18:6a4db94011d3	12449	* \| \| \|It is recommended that S/W only enable ACP while EMAC is operating on full duplex mode.
sahilmgandhi	18:6a4db94011d3	12450	* \| \| \|0 = Ethernet MAC controller dropped the control frame.
sahilmgandhi	18:6a4db94011d3	12451	* \| \| \|1 = Ethernet MAC controller received the control frame.
sahilmgandhi	18:6a4db94011d3	12452	* \|[4] \|AEP \|Accept CRC Error Packet
sahilmgandhi	18:6a4db94011d3	12453	* \| \| \|The AEP controls the EMAC accepts or drops the CRC error packet.
sahilmgandhi	18:6a4db94011d3	12454	* \| \| \|If the AEP is set to high, the incoming packet with CRC error will be received by EMAC as a good packet.
sahilmgandhi	18:6a4db94011d3	12455	* \| \| \|0 = Ethernet MAC controller dropped the CRC error packet.
sahilmgandhi	18:6a4db94011d3	12456	* \| \| \|1 = Ethernet MAC controller received the CRC error packet.
sahilmgandhi	18:6a4db94011d3	12457	* \|[5] \|STRIPCRC \|Strip CRC Checksum
sahilmgandhi	18:6a4db94011d3	12458	* \| \| \|The STRIPCRC controls if the length of incoming packet is calculated with 4 bytes CRC checksum.
sahilmgandhi	18:6a4db94011d3	12459	* \| \| \|If the STRIPCRC is set to high, 4 bytes CRC checksum is excluded from length calculation of incoming packet.
sahilmgandhi	18:6a4db94011d3	12460	* \| \| \|0 = The 4 bytes CRC checksum is included in packet length calculation.
sahilmgandhi	18:6a4db94011d3	12461	* \| \| \|1 = The 4 bytes CRC checksum is excluded in packet length calculation.
sahilmgandhi	18:6a4db94011d3	12462	* \|[6] \|WOLEN \|Wake On LAN Enable
sahilmgandhi	18:6a4db94011d3	12463	* \| \| \|The WOLEN high enables the functionality that Ethernet MAC controller checked if the incoming packet is Magic Packet and wakeup system from Power-down mode.
sahilmgandhi	18:6a4db94011d3	12464	* \| \| \|If incoming packet was a Magic Packet and the system was in Power-down, the Ethernet MAC controller would generate a wakeup event to wake system up from Power-down mode.
sahilmgandhi	18:6a4db94011d3	12465	* \| \| \|0 = Wake-up by Magic Packet function Disabled.
sahilmgandhi	18:6a4db94011d3	12466	* \| \| \|1 = Wake-up by Magic Packet function Enabled.
sahilmgandhi	18:6a4db94011d3	12467	* \|[8] \|TXON \|Frame Transmission ON
sahilmgandhi	18:6a4db94011d3	12468	* \| \| \|The TXON controls the normal packet transmission of EMAC.
sahilmgandhi	18:6a4db94011d3	12469	* \| \| \|If the TXON is set to high, the EMAC starts the packet transmission process, including the TX descriptor fetching, packet transmission and TX descriptor modification.
sahilmgandhi	18:6a4db94011d3	12470	* \| \| \|It is must to finish EMAC initial sequence before enable TXON.
sahilmgandhi	18:6a4db94011d3	12471	* \| \| \|Otherwise, the EMAC operation is undefined.
sahilmgandhi	18:6a4db94011d3	12472	* \| \| \|If the TXON is disabled during EMAC is transmitting a packet out, the EMAC stops the packet transmission process after the current packet transmission finished.
sahilmgandhi	18:6a4db94011d3	12473	* \| \| \|0 = Packet transmission process stopped.
sahilmgandhi	18:6a4db94011d3	12474	* \| \| \|1 = Packet transmission process started.
sahilmgandhi	18:6a4db94011d3	12475	* \|[9] \|NODEF \|No Deferral
sahilmgandhi	18:6a4db94011d3	12476	* \| \| \|The NODEF controls the enable of deferral exceed counter.
sahilmgandhi	18:6a4db94011d3	12477	* \| \| \|If NODEF is set to high, the deferral exceed counter is disabled.
sahilmgandhi	18:6a4db94011d3	12478	* \| \| \|The NODEF is only useful while EMAC is operating on half duplex mode.
sahilmgandhi	18:6a4db94011d3	12479	* \| \| \|0 = The deferral exceed counter Enabled.
sahilmgandhi	18:6a4db94011d3	12480	* \| \| \|1 = The deferral exceed counter Disabled.
sahilmgandhi	18:6a4db94011d3	12481	* \|[16] \|SDPZ \|Send PAUSE Frame
sahilmgandhi	18:6a4db94011d3	12482	* \| \| \|The SDPZ controls the PAUSE control frame transmission.
sahilmgandhi	18:6a4db94011d3	12483	* \| \| \|If S/W wants to send a PAUSE control frame out, the CAM entry 13, 14 and 15 must be configured first and the corresponding CAM enable bit of CAMEN register also must be set.
sahilmgandhi	18:6a4db94011d3	12484	* \| \| \|Then, set SDPZ to 1 enables the PAUSE control frame transmission.
sahilmgandhi	18:6a4db94011d3	12485	* \| \| \|The SDPZ is a self-clear bit.
sahilmgandhi	18:6a4db94011d3	12486	* \| \| \|This means after the PAUSE control frame transmission has completed, the SDPZ will be cleared automatically.
sahilmgandhi	18:6a4db94011d3	12487	* \| \| \|It is recommended that only enabling SNDPAUSE while EMAC is operating in Full Duplex mode.
sahilmgandhi	18:6a4db94011d3	12488	* \| \| \|0 = PAUSE control frame transmission completed.
sahilmgandhi	18:6a4db94011d3	12489	* \| \| \|1 = PAUSE control frame transmission Enabled.
sahilmgandhi	18:6a4db94011d3	12490	* \|[17] \|SQECHKEN \|SQE Checking Enable
sahilmgandhi	18:6a4db94011d3	12491	* \| \| \|The SQECHKEN controls the enable of SQE checking.
sahilmgandhi	18:6a4db94011d3	12492	* \| \| \|The SQE checking is only available while EMAC is operating on 10M bps and half duplex mode.
sahilmgandhi	18:6a4db94011d3	12493	* \| \| \|In other words, the SQECHKEN cannot affect EMAC operation, if the EMAC is operating on 100M bps or full duplex mode.
sahilmgandhi	18:6a4db94011d3	12494	* \| \| \|0 = SQE checking Disabled while EMAC is operating in 10Mbps and Half Duplex mode.
sahilmgandhi	18:6a4db94011d3	12495	* \| \| \|1 = SQE checking Enabled while EMAC is operating in 10Mbps and Half Duplex mode.
sahilmgandhi	18:6a4db94011d3	12496	* \|[18] \|FUDUP \|Full Duplex Mode Selection
sahilmgandhi	18:6a4db94011d3	12497	* \| \| \|The FUDUP controls that if EMAC is operating on full or half duplex mode.
sahilmgandhi	18:6a4db94011d3	12498	* \| \| \|0 = EMAC operates in half duplex mode.
sahilmgandhi	18:6a4db94011d3	12499	* \| \| \|1 = EMAC operates in full duplex mode.
sahilmgandhi	18:6a4db94011d3	12500	* \|[19] \|RMIIRXCTL \|RMII RX Control
sahilmgandhi	18:6a4db94011d3	12501	* \| \| \|The RMIIRXCTL control the receive data sample in RMII mode.
sahilmgandhi	18:6a4db94011d3	12502	* \| \| \|It's necessary to set this bit high when RMIIEN (EMAC_CTL[ [22]) is high.
sahilmgandhi	18:6a4db94011d3	12503	* \| \| \|0 = RMII RX control disabled.
sahilmgandhi	18:6a4db94011d3	12504	* \| \| \|1 = RMII RX control enabled.
sahilmgandhi	18:6a4db94011d3	12505	* \|[20] \|OPMODE \|Operation Mode Selection
sahilmgandhi	18:6a4db94011d3	12506	* \| \| \|The OPMODE defines that if the EMAC is operating on 10M or 100M bps mode.
sahilmgandhi	18:6a4db94011d3	12507	* \| \| \|The RST (EMAC_CTL[24]) would not affect OPMODE value.
sahilmgandhi	18:6a4db94011d3	12508	* \| \| \|0 = EMAC operates in 10Mbps mode.
sahilmgandhi	18:6a4db94011d3	12509	* \| \| \|1 = EMAC operates in 100Mbps mode.
sahilmgandhi	18:6a4db94011d3	12510	* \|[22] \|RMIIEN \|RMII Mode Enable
sahilmgandhi	18:6a4db94011d3	12511	* \| \| \|This bit controls if Ethernet MAC controller connected with off-chip Ethernet PHY by MII interface or RMII interface.
sahilmgandhi	18:6a4db94011d3	12512	* \| \| \|The RST (EMAC_CTL[24]) would not affect RMIIEN value.
sahilmgandhi	18:6a4db94011d3	12513	* \| \| \|0 = Ethernet MAC controller MII mode Enabled.
sahilmgandhi	18:6a4db94011d3	12514	* \| \| \|1 = Ethernet MAC controller RMII mode Enabled.
sahilmgandhi	18:6a4db94011d3	12515	* \|[24] \|RST \|Software Reset
sahilmgandhi	18:6a4db94011d3	12516	* \| \| \|The RST implements a reset function to make the EMAC return default state.
sahilmgandhi	18:6a4db94011d3	12517	* \| \| \|The RST is a self-clear bit.
sahilmgandhi	18:6a4db94011d3	12518	* \| \| \|This means after the software reset finished, the RST will be cleared automatically.
sahilmgandhi	18:6a4db94011d3	12519	* \| \| \|Enable RST can also reset all control and status registers, exclusive of the control bits RMIIEN (EMAC_CTL[22]), LOOPBK (EMAC_CTL[21]) and OPMODE (EMAC_CTL[20]).
sahilmgandhi	18:6a4db94011d3	12520	* \| \| \|The EMAC re-initial is necessary after the software reset completed.
sahilmgandhi	18:6a4db94011d3	12521	* \| \| \|0 = Software reset completed.
sahilmgandhi	18:6a4db94011d3	12522	* \| \| \|1 = Software reset Enabled.
sahilmgandhi	18:6a4db94011d3	12523	*/
sahilmgandhi	18:6a4db94011d3	12524	__IO uint32_t CTL;
sahilmgandhi	18:6a4db94011d3	12525
sahilmgandhi	18:6a4db94011d3	12526	/**
sahilmgandhi	18:6a4db94011d3	12527	* MIIMDAT
sahilmgandhi	18:6a4db94011d3	12528	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12529	* Offset: 0x94 MII Management Data Register
sahilmgandhi	18:6a4db94011d3	12530	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12531	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12532	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12533	* \|[0:15] \|DATA \|MII Management Data
sahilmgandhi	18:6a4db94011d3	12534	* \| \| \|The DATA is the 16 bits data that will be written into the registers of external PHY for MII Management write command or the data from the registers of external PHY for MII Management read command.
sahilmgandhi	18:6a4db94011d3	12535	*/
sahilmgandhi	18:6a4db94011d3	12536	__IO uint32_t MIIMDAT;
sahilmgandhi	18:6a4db94011d3	12537
sahilmgandhi	18:6a4db94011d3	12538	/**
sahilmgandhi	18:6a4db94011d3	12539	* MIIMCTL
sahilmgandhi	18:6a4db94011d3	12540	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12541	* Offset: 0x98 MII Management Control and Address Register
sahilmgandhi	18:6a4db94011d3	12542	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12543	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12544	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12545	* \|[0:4] \|PHYREG \|PHY Register Address
sahilmgandhi	18:6a4db94011d3	12546	* \| \| \|The PHYREG keeps the address to indicate which register of external PHY is the target of the MII management command.
sahilmgandhi	18:6a4db94011d3	12547	* \|[8:12] \|PHYADDR \|PHY Address
sahilmgandhi	18:6a4db94011d3	12548	* \| \| \|The PHYADDR keeps the address to differentiate which external PHY is the target of the MII management command.
sahilmgandhi	18:6a4db94011d3	12549	* \|[16] \|WRITE \|Write Command
sahilmgandhi	18:6a4db94011d3	12550	* \| \| \|The Write defines the MII management command is a read or write.
sahilmgandhi	18:6a4db94011d3	12551	* \| \| \|0 = MII management command is a read command.
sahilmgandhi	18:6a4db94011d3	12552	* \| \| \|1 = MII management command is a write command.
sahilmgandhi	18:6a4db94011d3	12553	* \|[17] \|BUSY \|Busy Bit
sahilmgandhi	18:6a4db94011d3	12554	* \| \| \|The BUSY controls the enable of the MII management frame generation.
sahilmgandhi	18:6a4db94011d3	12555	* \| \| \|If S/W wants to access registers of external PHY, it set BUSY to high and EMAC generates the MII management frame to external PHY through MII Management I/F.
sahilmgandhi	18:6a4db94011d3	12556	* \| \| \|The BUSY is a self-clear bit.
sahilmgandhi	18:6a4db94011d3	12557	* \| \| \|This means the BUSY will be cleared automatically after the MII management command finished.
sahilmgandhi	18:6a4db94011d3	12558	* \| \| \|0 = MII management command generation finished.
sahilmgandhi	18:6a4db94011d3	12559	* \| \| \|1 = MII management command generation Enabled.
sahilmgandhi	18:6a4db94011d3	12560	* \|[18] \|PREAMSP \|Preamble Suppress
sahilmgandhi	18:6a4db94011d3	12561	* \| \| \|The PREAMSP controls the preamble field generation of MII management frame.
sahilmgandhi	18:6a4db94011d3	12562	* \| \| \|If the PREAMSP is set to high, the preamble field generation of MII management frame is skipped.
sahilmgandhi	18:6a4db94011d3	12563	* \| \| \|0 = Preamble field generation of MII management frame not skipped.
sahilmgandhi	18:6a4db94011d3	12564	* \| \| \|1 = Preamble field generation of MII management frame skipped.
sahilmgandhi	18:6a4db94011d3	12565	* \|[19] \|MDCON \|MDC Clock ON Always
sahilmgandhi	18:6a4db94011d3	12566	* \| \| \|The MDC controls the MDC clock generation.
sahilmgandhi	18:6a4db94011d3	12567	* \| \| \|If the MDCON is set to high, the MDC clock actives always.
sahilmgandhi	18:6a4db94011d3	12568	* \| \| \|Otherwise, the MDC will only active while S/W issues a MII management command.
sahilmgandhi	18:6a4db94011d3	12569	* \| \| \|0 = MDC clock only actives while S/W issues a MII management command.
sahilmgandhi	18:6a4db94011d3	12570	* \| \| \|1 = MDC clock actives always.
sahilmgandhi	18:6a4db94011d3	12571	*/
sahilmgandhi	18:6a4db94011d3	12572	__IO uint32_t MIIMCTL;
sahilmgandhi	18:6a4db94011d3	12573
sahilmgandhi	18:6a4db94011d3	12574	/**
sahilmgandhi	18:6a4db94011d3	12575	* FIFOCTL
sahilmgandhi	18:6a4db94011d3	12576	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12577	* Offset: 0x9C FIFO Threshold Control Register
sahilmgandhi	18:6a4db94011d3	12578	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12579	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12580	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12581	* \|[0:1] \|RXFIFOTH \|RXFIFO Low Threshold
sahilmgandhi	18:6a4db94011d3	12582	* \| \| \|The RXFIFOTH controls when RXDMA requests internal arbiter for data transfer between RXFIFO and system memory.
sahilmgandhi	18:6a4db94011d3	12583	* \| \| \|The RXFIFOTH defines not only the high threshold of RXFIFO, but also the low threshold.
sahilmgandhi	18:6a4db94011d3	12584	* \| \| \|The low threshold is the half of high threshold always.
sahilmgandhi	18:6a4db94011d3	12585	* \| \| \|During the packet reception, if the RXFIFO reaches the high threshold, the RXDMA starts to transfer frame data from RXFIFO to system memory.
sahilmgandhi	18:6a4db94011d3	12586	* \| \| \|If the frame data in RXFIFO is less than low threshold, RXDMA stops to transfer the frame data to system memory.
sahilmgandhi	18:6a4db94011d3	12587	* \| \| \|00 = Depend on the burst length setting.
sahilmgandhi	18:6a4db94011d3	12588	* \| \| \|If the burst length is 8 words, high threshold is 8 words, too.
sahilmgandhi	18:6a4db94011d3	12589	* \| \| \|01 = RXFIFO high threshold is 64B and low threshold is 32B.
sahilmgandhi	18:6a4db94011d3	12590	* \| \| \|10 = RXFIFO high threshold is 128B and low threshold is 64B.
sahilmgandhi	18:6a4db94011d3	12591	* \| \| \|11 = RXFIFO high threshold is 192B and low threshold is 96B.
sahilmgandhi	18:6a4db94011d3	12592	* \|[8:9] \|TXFIFOTH \|TXFIFO Low Threshold
sahilmgandhi	18:6a4db94011d3	12593	* \| \| \|The TXFIFOTH controls when TXDMA requests internal arbiter for data transfer between system memory and TXFIFO.
sahilmgandhi	18:6a4db94011d3	12594	* \| \| \|The TXFIFOTH defines not only the low threshold of TXFIFO, but also the high threshold.
sahilmgandhi	18:6a4db94011d3	12595	* \| \| \|The high threshold is the twice of low threshold always.During the packet transmission, if the TXFIFO reaches the high threshold, the TXDMA stops generate request to transfer frame data from system memory to TXFIFO.
sahilmgandhi	18:6a4db94011d3	12596	* \| \| \|If the frame data in TXFIFO is less than low threshold, TXDMA starts to transfer frame data from system memory to TXFIFO.
sahilmgandhi	18:6a4db94011d3	12597	* \| \| \|The TXFIFOTH also defines when the TXMAC starts to transmit frame out to network.
sahilmgandhi	18:6a4db94011d3	12598	* \| \| \|The TXMAC starts to transmit the frame out while the TXFIFO first time reaches the high threshold during the transmission of the frame.
sahilmgandhi	18:6a4db94011d3	12599	* \| \| \|If the frame data length is less than TXFIFO high threshold, the TXMAC starts to transmit the frame out after the frame data are all inside the TXFIFO.
sahilmgandhi	18:6a4db94011d3	12600	* \| \| \|00 = Undefined.
sahilmgandhi	18:6a4db94011d3	12601	* \| \| \|01 = TXFIFO low threshold is 64B and high threshold is 128B.
sahilmgandhi	18:6a4db94011d3	12602	* \| \| \|10 = TXFIFO low threshold is 80B and high threshold is 160B.
sahilmgandhi	18:6a4db94011d3	12603	* \| \| \|11 = TXFIFO low threshold is 96B and high threshold is 192B.
sahilmgandhi	18:6a4db94011d3	12604	* \|[20:21] \|BURSTLEN \|DMA Burst Length
sahilmgandhi	18:6a4db94011d3	12605	* \| \| \|This defines the burst length of AHB bus cycle while EMAC accesses system memory.
sahilmgandhi	18:6a4db94011d3	12606	* \| \| \|00 = 16 words.
sahilmgandhi	18:6a4db94011d3	12607	* \| \| \|01 = 16 words.
sahilmgandhi	18:6a4db94011d3	12608	* \| \| \|10 = 8 words.
sahilmgandhi	18:6a4db94011d3	12609	* \| \| \|11 = 4 words.
sahilmgandhi	18:6a4db94011d3	12610	*/
sahilmgandhi	18:6a4db94011d3	12611	__IO uint32_t FIFOCTL;
sahilmgandhi	18:6a4db94011d3	12612
sahilmgandhi	18:6a4db94011d3	12613	/**
sahilmgandhi	18:6a4db94011d3	12614	* TXST
sahilmgandhi	18:6a4db94011d3	12615	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12616	* Offset: 0xA0 Transmit Start Demand Register
sahilmgandhi	18:6a4db94011d3	12617	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12618	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12619	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12620	* \|[0:31] \|TXST \|Transmit Start Demand
sahilmgandhi	18:6a4db94011d3	12621	* \| \| \|If the TX descriptor is not available for use of TXDMA after the TXON (EMAC_CTL[8]) is enabled, the FSM (Finite State Machine) of TXDMA enters the Halt state and the frame transmission is halted.
sahilmgandhi	18:6a4db94011d3	12622	* \| \| \|After the S/W has prepared the new TX descriptor for frame transmission, it must issue a write command to EMAC_TXST register to make TXDMA to leave Halt state and continue the frame transmission.
sahilmgandhi	18:6a4db94011d3	12623	* \| \| \|The EMAC_TXST is a write only register and read from this register is undefined.
sahilmgandhi	18:6a4db94011d3	12624	* \| \| \|The write to EMAC_TXST register takes effect only when TXDMA stayed at Halt state.
sahilmgandhi	18:6a4db94011d3	12625	*/
sahilmgandhi	18:6a4db94011d3	12626	__O uint32_t TXST;
sahilmgandhi	18:6a4db94011d3	12627
sahilmgandhi	18:6a4db94011d3	12628	/**
sahilmgandhi	18:6a4db94011d3	12629	* RXST
sahilmgandhi	18:6a4db94011d3	12630	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12631	* Offset: 0xA4 Receive Start Demand Register
sahilmgandhi	18:6a4db94011d3	12632	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12633	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12634	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12635	* \|[0:31] \|RXST \|Receive Start Demand
sahilmgandhi	18:6a4db94011d3	12636	* \| \| \|If the RX descriptor is not available for use of RXDMA after the RXON (EMAC_CTL[0]) is enabled, the FSM (Finite State Machine) of RXDMA enters the Halt state and the frame reception is halted.
sahilmgandhi	18:6a4db94011d3	12637	* \| \| \|After the S/W has prepared the new RX descriptor for frame reception, it must issue a write command to EMAC_RXST register to make RXDMA to leave Halt state and continue the frame reception.
sahilmgandhi	18:6a4db94011d3	12638	* \| \| \|The EMAC_RXST is a write only register and read from this register is undefined.
sahilmgandhi	18:6a4db94011d3	12639	* \| \| \|The write to EMAC_RXST register take effect only when RXDMA stayed at Halt state.
sahilmgandhi	18:6a4db94011d3	12640	*/
sahilmgandhi	18:6a4db94011d3	12641	__O uint32_t RXST;
sahilmgandhi	18:6a4db94011d3	12642
sahilmgandhi	18:6a4db94011d3	12643	/**
sahilmgandhi	18:6a4db94011d3	12644	* MRFL
sahilmgandhi	18:6a4db94011d3	12645	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12646	* Offset: 0xA8 Maximum Receive Frame Control Register
sahilmgandhi	18:6a4db94011d3	12647	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12648	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12649	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12650	* \|[0:15] \|MRFL \|Maximum Receive Frame Length
sahilmgandhi	18:6a4db94011d3	12651	* \| \| \|The MRFL defines the maximum frame length for received frame.
sahilmgandhi	18:6a4db94011d3	12652	* \| \| \|If the frame length of received frame is greater than MRFL, and bit MFLEIEN (EMAC_INTEN[8]) is also enabled, the bit MFLEIF (EMAC_INTSTS[8]) is set and the RX interrupt is triggered.
sahilmgandhi	18:6a4db94011d3	12653	* \| \| \|It is recommended that only use MRFL to qualify the length of received frame while S/W wants to receive a frame which length is greater than 1518 bytes.
sahilmgandhi	18:6a4db94011d3	12654	*/
sahilmgandhi	18:6a4db94011d3	12655	__IO uint32_t MRFL;
sahilmgandhi	18:6a4db94011d3	12656
sahilmgandhi	18:6a4db94011d3	12657	/**
sahilmgandhi	18:6a4db94011d3	12658	* INTEN
sahilmgandhi	18:6a4db94011d3	12659	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12660	* Offset: 0xAC MAC Interrupt Enable Register
sahilmgandhi	18:6a4db94011d3	12661	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12662	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12663	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12664	* \|[0] \|RXIEN \|Receive Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	12665	* \| \| \|The RXIEN controls the RX interrupt generation.
sahilmgandhi	18:6a4db94011d3	12666	* \| \| \|If RXIEN is enabled and RXIF (EMAC_INTSTS[0]) is high, EMAC generates the RX interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	12667	* \| \| \|If RXIEN is disabled, no RX interrupt is generated to CPU even any status bit EMAC_INTSTS[15:1] is set and the corresponding bit of EMAC_INTEN is enabled.
sahilmgandhi	18:6a4db94011d3	12668	* \| \| \|In other words, if S/W wants to receive RX interrupt from EMAC, this bit must be enabled.
sahilmgandhi	18:6a4db94011d3	12669	* \| \| \|And, if S/W doesn't want to receive any RX interrupt from EMAC, disables this bit.
sahilmgandhi	18:6a4db94011d3	12670	* \| \| \|0 = RXIF (EMAC_INTSTS[0]) is masked and RX interrupt generation Disabled.
sahilmgandhi	18:6a4db94011d3	12671	* \| \| \|1 = RXIF (EMAC_INTSTS[0]) is not masked and RX interrupt generation Enabled.
sahilmgandhi	18:6a4db94011d3	12672	* \|[1] \|CRCEIEN \|CRC Error Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	12673	* \| \| \|The CRCEIEN controls the CRCEIF (EMAC_INTSTS[1]) interrupt generation.
sahilmgandhi	18:6a4db94011d3	12674	* \| \| \|If CRCEIF (EMAC_INTSTS[1]) is set, and both CRCEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	12675	* \| \| \|If CRCEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the CRCEIF (EMAC_INTSTS[1]) is set.
sahilmgandhi	18:6a4db94011d3	12676	* \| \| \|0 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	12677	* \| \| \|1 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	12678	* \|[2] \|RXOVIEN \|Receive FIFO Overflow Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	12679	* \| \| \|The RXOVIEN controls the RXOVIF (EMAC_INTSTS[2]) interrupt generation.
sahilmgandhi	18:6a4db94011d3	12680	* \| \| \|If RXOVIF (EMAC_INTSTS[2]) is set, and both RXOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	12681	* \| \| \|If RXOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RXOVIF (EMAC_INTSTS[2]) is set.
sahilmgandhi	18:6a4db94011d3	12682	* \| \| \|0 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	12683	* \| \| \|1 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	12684	* \|[3] \|LPIEN \|Long Packet Interrupt Enable
sahilmgandhi	18:6a4db94011d3	12685	* \| \| \|The LPIEN controls the LPIF (EMAC_INTSTS[3]) interrupt generation.
sahilmgandhi	18:6a4db94011d3	12686	* \| \| \|If LPIF (EMAC_INTSTS[3]) is set, and both LPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	12687	* \| \| \|If LPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the LPIF (EMAC_INTSTS[3]) is set.
sahilmgandhi	18:6a4db94011d3	12688	* \| \| \|0 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	12689	* \| \| \|1 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	12690	* \|[4] \|RXGDIEN \|Receive Good Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	12691	* \| \| \|The RXGDIEN controls the RXGDIF (EMAC_INTSTS[4]) interrupt generation.
sahilmgandhi	18:6a4db94011d3	12692	* \| \| \|If RXGDIF (EMAC_INTSTS[4]) is set, and both RXGDIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	12693	* \| \| \|If RXGDIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RXGDIF (EMAC_INTSTS[4]) is set.
sahilmgandhi	18:6a4db94011d3	12694	* \| \| \|0 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	12695	* \| \| \|1 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	12696	* \|[5] \|ALIEIEN \|Alignment Error Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	12697	* \| \| \|The ALIEIEN controls the ALIEIF (EMAC_INTSTS[5]) interrupt generation.
sahilmgandhi	18:6a4db94011d3	12698	* \| \| \|If ALIEIF (EMAC_INTSTS[5]) is set, and both ALIEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	12699	* \| \| \|If ALIEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the ALIEIF (EMAC_INTSTS[5]) is set.
sahilmgandhi	18:6a4db94011d3	12700	* \| \| \|0 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	12701	* \| \| \|1 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	12702	* \|[6] \|RPIEN \|Runt Packet Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	12703	* \| \| \|The RPIEN controls the RPIF (EMAC_INTSTS[6]) interrupt generation.
sahilmgandhi	18:6a4db94011d3	12704	* \| \| \|If RPIF (EMAC_INTSTS[6]) is set, and both RPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	12705	* \| \| \|If RPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RPIF (EMAC_INTSTS[6]) is set.
sahilmgandhi	18:6a4db94011d3	12706	* \| \| \|0 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	12707	* \| \| \|1 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	12708	* \|[7] \|MPCOVIEN \|Miss Packet Counter Overrun Interrupt Enable
sahilmgandhi	18:6a4db94011d3	12709	* \| \| \|The MPCOVIEN controls the MPCOVIF (EMAC_INTSTS[7]) interrupt generation.
sahilmgandhi	18:6a4db94011d3	12710	* \| \| \|If MPCOVIF (EMAC_INTSTS[7]) is set, and both MPCOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	12711	* \| \| \|If MPCOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the MPCOVIF (EMAC_INTSTS[7]) is set.
sahilmgandhi	18:6a4db94011d3	12712	* \| \| \|0 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	12713	* \| \| \|1 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	12714	* \|[8] \|MFLEIEN \|Maximum Frame Length Exceed Interrupt Enable
sahilmgandhi	18:6a4db94011d3	12715	* \| \| \|The MFLEIEN controls the MFLEIF (EMAC_INTSTS[8]) interrupt generation.
sahilmgandhi	18:6a4db94011d3	12716	* \| \| \|If MFLEIF (EMAC_INTSTS[8]) is set, and both MFLEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	12717	* \| \| \|If MFLEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the MFLEIF (EMAC_INTSTS[8]) is set.
sahilmgandhi	18:6a4db94011d3	12718	* \| \| \|0 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	12719	* \| \| \|1 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	12720	* \|[9] \|DENIEN \|DMA Early Notification Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	12721	* \| \| \|The DENIEN controls the DENIF (EMAC_INTSTS[9]) interrupt generation.
sahilmgandhi	18:6a4db94011d3	12722	* \| \| \|If DENIF (EMAC_INTSTS[9]) is set, and both DENIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	12723	* \| \| \|If DENIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the DENIF (EMAC_INTSTS[9]) is set.
sahilmgandhi	18:6a4db94011d3	12724	* \| \| \|0 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	12725	* \| \| \|1 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	12726	* \|[10] \|RDUIEN \|Receive Descriptor Unavailable Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	12727	* \| \| \|The RDUIEN controls the RDUIF (EMAC_INTSTS[10]) interrupt generation.
sahilmgandhi	18:6a4db94011d3	12728	* \| \| \|If RDUIF (EMAC_INTSTS[10]) is set, and both RDUIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	12729	* \| \| \|If RDUIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RDUIF (EMAC_MIOSTA[10]) register is set.
sahilmgandhi	18:6a4db94011d3	12730	* \| \| \|0 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	12731	* \| \| \|1 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	12732	* \|[11] \|RXBEIEN \|Receive Bus Error Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	12733	* \| \| \|The RXBEIEN controls the RXBEIF (EMAC_INTSTS[11]) interrupt generation.
sahilmgandhi	18:6a4db94011d3	12734	* \| \| \|If RXBEIF (EMAC_INTSTS[11]) is set, and both RXBEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	12735	* \| \| \|If RXBEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RXBEIF (EMAC_INTSTS[11]) is set.
sahilmgandhi	18:6a4db94011d3	12736	* \| \| \|0 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	12737	* \| \| \|1 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	12738	* \|[14] \|CFRIEN \|Control Frame Receive Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	12739	* \| \| \|The CFRIEN controls the CFRIF (EMAC_INTSTS[14]) interrupt generation.
sahilmgandhi	18:6a4db94011d3	12740	* \| \| \|If CFRIF (EMAC_INTSTS[14]) is set, and both CFRIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	12741	* \| \| \|If CFRIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the CFRIF (EMAC_INTSTS[14]) register is set.
sahilmgandhi	18:6a4db94011d3	12742	* \| \| \|0 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	12743	* \| \| \|1 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	12744	* \|[15] \|WOLIEN \|Wake On LAN Interrupt Enable
sahilmgandhi	18:6a4db94011d3	12745	* \| \| \|The WOLIEN controls the WOLIF (EMAC_INTSTS[15]) interrupt generation.
sahilmgandhi	18:6a4db94011d3	12746	* \| \| \|If WOLIF (EMAC_INTSTS[15]) is set, and both WOLIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	12747	* \| \| \|If WOLIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the WOLIF (EMAC_INTSTS[15]) is set.
sahilmgandhi	18:6a4db94011d3	12748	* \| \| \|0 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	12749	* \| \| \|1 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	12750	* \|[16] \|TXIEN \|Transmit Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	12751	* \| \| \|The TXIEN controls the TX interrupt generation.
sahilmgandhi	18:6a4db94011d3	12752	* \| \| \|If TXIEN is enabled and TXIF (EMAC_INTSTS[16]) is high, EMAC generates the TX interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	12753	* \| \| \|If TXIEN is disabled, no TX interrupt is generated to CPU even any status bit of EMAC_INTSTS[24:17] set and the corresponding bit of EMAC_INTEN is enabled.
sahilmgandhi	18:6a4db94011d3	12754	* \| \| \|In other words, if S/W wants to receive TX interrupt from EMAC, this bit must be enabled.
sahilmgandhi	18:6a4db94011d3	12755	* \| \| \|And, if S/W doesn't want to receive any TX interrupt from EMAC, disables this bit.
sahilmgandhi	18:6a4db94011d3	12756	* \| \| \|0 = TXIF (EMAC_INTSTS[16]) is masked and TX interrupt generation Disabled.
sahilmgandhi	18:6a4db94011d3	12757	* \| \| \|1 = TXIF (EMAC_INTSTS[16]) is not masked and TX interrupt generation Enabled.
sahilmgandhi	18:6a4db94011d3	12758	* \|[17] \|TXUDIEN \|Transmit FIFO Underflow Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	12759	* \| \| \|The TXUDIEN controls the TXUDIF (EMAC_INTSTS[17]) interrupt generation.
sahilmgandhi	18:6a4db94011d3	12760	* \| \| \|If TXUDIF (EMAC_INTSTS[17]) is set, and both TXUDIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	12761	* \| \| \|If TXUDIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the TXUDIF (EMAC_INTSTS[17]) is set.
sahilmgandhi	18:6a4db94011d3	12762	* \| \| \|0 = TXUDIF (EMAC_INTSTS[17]) TX interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	12763	* \| \| \|1 = TXUDIF (EMAC_INTSTS[17]) TX interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	12764	* \|[18] \|TXCPIEN \|Transmit Completion Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	12765	* \| \| \|The TXCPIEN controls the TXCPIF (EMAC_INTSTS[18]) interrupt generation.
sahilmgandhi	18:6a4db94011d3	12766	* \| \| \|If TXCPIF (EMAC_INTSTS[18]) is set, and both TXCPIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	12767	* \| \| \|If TXCPIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the TXCPIF (EMAC_INTSTS[18]) is set.
sahilmgandhi	18:6a4db94011d3	12768	* \| \| \|0 = TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	12769	* \| \| \|1 = TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	12770	* \|[19] \|EXDEFIEN \|Defer Exceed Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	12771	* \| \| \|The EXDEFIEN controls the EXDEFIF (EMAC_INTSTS[19]) interrupt generation.
sahilmgandhi	18:6a4db94011d3	12772	* \| \| \|If EXDEFIF (EMAC_INTSTS[19]) is set, and both EXDEFIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	12773	* \| \| \|If EXDEFIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the EXDEFIF (EMAC_INTSTS[19]) is set.
sahilmgandhi	18:6a4db94011d3	12774	* \| \| \|0 = EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	12775	* \| \| \|1 = EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	12776	* \|[20] \|NCSIEN \|No Carrier Sense Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	12777	* \| \| \|The NCSIEN controls the NCSIF (EMAC_INTSTS[20]) interrupt generation.
sahilmgandhi	18:6a4db94011d3	12778	* \| \| \|If NCSIF (EMAC_INTSTS[20]) is set, and both NCSIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	12779	* \| \| \|If NCSIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the NCSIF (EMAC_INTSTS[20]) is set.
sahilmgandhi	18:6a4db94011d3	12780	* \| \| \|0 = NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	12781	* \| \| \|1 = NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	12782	* \|[21] \|TXABTIEN \|Transmit Abort Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	12783	* \| \| \|The TXABTIEN controls the TXABTIF (EMAC_INTSTS[21]) interrupt generation.
sahilmgandhi	18:6a4db94011d3	12784	* \| \| \|If TXABTIF (EMAC_INTSTS[21]) is set, and both TXABTIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	12785	* \| \| \|If TXABTIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the TXABTIF (EMAC_INTSTS[21]) is set.
sahilmgandhi	18:6a4db94011d3	12786	* \| \| \|0 = TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	12787	* \| \| \|1 = TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	12788	* \|[22] \|LCIEN \|Late Collision Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	12789	* \| \| \|The LCIEN controls the LCIF (EMAC_INTSTS[22]) interrupt generation.
sahilmgandhi	18:6a4db94011d3	12790	* \| \| \|If LCIF (EMAC_INTSTS[22]) is set, and both LCIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	12791	* \| \| \|If LCIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the LCIF (EMAC_INTSTS[22]) is set.
sahilmgandhi	18:6a4db94011d3	12792	* \| \| \|0 = LCIF (EMAC_INTSTS[22]) trigger TX interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	12793	* \| \| \|1 = LCIF (EMAC_INTSTS[22]) trigger TX interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	12794	* \|[23] \|TDUIEN \|Transmit Descriptor Unavailable Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	12795	* \| \| \|The TDUIEN controls the TDUIF (EMAC_INTSTS[23]) interrupt generation.
sahilmgandhi	18:6a4db94011d3	12796	* \| \| \|If TDUIF (EMAC_INTSTS[23]) is set, and both TDUIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	12797	* \| \| \|If TDUIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the TDUIF (EMAC_INTSTS[23]) is set.
sahilmgandhi	18:6a4db94011d3	12798	* \| \| \|0 = TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	12799	* \| \| \|1 = TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	12800	* \|[24] \|TXBEIEN \|Transmit Bus Error Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	12801	* \| \| \|The TXBEIEN controls the TXBEIF (EMAC_INTSTS[24]) interrupt generation.
sahilmgandhi	18:6a4db94011d3	12802	* \| \| \|If TXBEIF (EMAC_INTSTS[24]) is set, and both TXBEIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	12803	* \| \| \|If TXBEIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the TXBEIF (EMAC_INTSTS[24]) is set.
sahilmgandhi	18:6a4db94011d3	12804	* \| \| \|0 = TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	12805	* \| \| \|1 = TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	12806	* \|[28] \|TSALMIEN \|Time Stamp Alarm Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	12807	* \| \| \|The TSALMIEN controls the TSALMIF (EMAC_INTSTS[28]) interrupt generation.
sahilmgandhi	18:6a4db94011d3	12808	* \| \| \|If TSALMIF (EMAC_INTSTS[28]) is set, and both TSALMIEN and TXIEN (EMAC_INTEN[16]) enabled, the EMAC generates the TX interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	12809	* \| \| \|If TSALMIEN or TXIEN (EMAC_INTEN[16]) disabled, no TX interrupt generated to CPU even the TXTSALMIF (EMAC_INTEN[28]) is set.
sahilmgandhi	18:6a4db94011d3	12810	* \| \| \|0 = TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	12811	* \| \| \|1 = TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	12812	*/
sahilmgandhi	18:6a4db94011d3	12813	__IO uint32_t INTEN;
sahilmgandhi	18:6a4db94011d3	12814
sahilmgandhi	18:6a4db94011d3	12815	/**
sahilmgandhi	18:6a4db94011d3	12816	* INTSTS
sahilmgandhi	18:6a4db94011d3	12817	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12818	* Offset: 0xB0 MAC Interrupt Status Register
sahilmgandhi	18:6a4db94011d3	12819	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12820	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12821	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	12822	* \|[0] \|RXIF \|Receive Interrupt
sahilmgandhi	18:6a4db94011d3	12823	* \| \| \|The RXIF indicates the RX interrupt status.
sahilmgandhi	18:6a4db94011d3	12824	* \| \| \|If RXIF high and its corresponding enable bit, RXIEN (EMAC_INTEN[0]), is also high indicates the EMAC generates RX interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	12825	* \| \| \|If RXIF is high but RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated.
sahilmgandhi	18:6a4db94011d3	12826	* \| \| \|The RXIF is logic OR result of bit logic AND result of EMAC_INTSTS[15:1] and EMAC_INTEN[15:1].
sahilmgandhi	18:6a4db94011d3	12827	* \| \| \|In other words, if any bit of EMAC_INTSTS[15:1] is high and its corresponding enable bit in EMAC_INTEN[15:1] is also enabled, the RXIF will be high.
sahilmgandhi	18:6a4db94011d3	12828	* \| \| \|Because the RXIF is a logic OR result, clears EMAC_INTSTS[15:1] makes RXIF be cleared, too.
sahilmgandhi	18:6a4db94011d3	12829	* \| \| \|0 = No status bit in EMAC_INTSTS[15:1] is set or no enable bit in EMAC_INTEN[15:1] is enabled.
sahilmgandhi	18:6a4db94011d3	12830	* \| \| \|1 = At least one status in EMAC_INTSTS[15:1] is set and its corresponding enable bit in EMAC_INTEN[15:1] is enabled, too.
sahilmgandhi	18:6a4db94011d3	12831	* \|[1] \|CRCEIF \|CRC Error Interrupt
sahilmgandhi	18:6a4db94011d3	12832	* \| \| \|The CRCEIF high indicates the incoming packet incurred the CRC error and the packet is dropped.
sahilmgandhi	18:6a4db94011d3	12833	* \| \| \|If the AEP (EMAC_CTL[4]) is set, the CRC error packet will be regarded as a good packet and CRCEIF will not be set.
sahilmgandhi	18:6a4db94011d3	12834	* \| \| \|If the CRCEIF is high and CRCEIEN (EMAC_INTEN[1]) is enabled, the RXIF will be high.
sahilmgandhi	18:6a4db94011d3	12835	* \| \| \|Write 1 to this bit clears the CRCEIF status.
sahilmgandhi	18:6a4db94011d3	12836	* \| \| \|0 = The frame does not incur CRC error.
sahilmgandhi	18:6a4db94011d3	12837	* \| \| \|1 = The frame incurred CRC error.
sahilmgandhi	18:6a4db94011d3	12838	* \|[2] \|RXOVIF \|Receive FIFO Overflow Interrupt
sahilmgandhi	18:6a4db94011d3	12839	* \| \| \|The RXOVIF high indicates the RXFIFO overflow occurred during packet reception.
sahilmgandhi	18:6a4db94011d3	12840	* \| \| \|While the RXFIFO overflow occurred, the EMAC drops the current receiving packer.
sahilmgandhi	18:6a4db94011d3	12841	* \| \| \|If the RXFIFO overflow occurred often, it is recommended that modify RXFIFO threshold control, the RXFIFOTH of FFTCR register, to higher level.
sahilmgandhi	18:6a4db94011d3	12842	* \| \| \|If the RXOVIF is high and RXOVIEN (EMAC_INTEN[2]) is enabled, the RXIF will be high.
sahilmgandhi	18:6a4db94011d3	12843	* \| \| \|Write 1 to this bit clears the RXOVIF status.
sahilmgandhi	18:6a4db94011d3	12844	* \| \| \|0 = No RXFIFO overflow occurred during packet reception.
sahilmgandhi	18:6a4db94011d3	12845	* \| \| \|1 = RXFIFO overflow occurred during packet reception.
sahilmgandhi	18:6a4db94011d3	12846	* \|[3] \|LPIF \|Long Packet Interrupt Flag
sahilmgandhi	18:6a4db94011d3	12847	* \| \| \|The LPIF high indicates the length of the incoming packet is greater than 1518 bytes and the incoming packet is dropped.
sahilmgandhi	18:6a4db94011d3	12848	* \| \| \|If the ALP (EMAC_CTL[1]) is set, the long packet will be regarded as a good packet and LPIF will not be set.
sahilmgandhi	18:6a4db94011d3	12849	* \| \| \|If the LPIF is high and LPIEN (EMAC_INTEN[3]) is enabled, the RXIF will be high.
sahilmgandhi	18:6a4db94011d3	12850	* \| \| \|Write 1 to this bit clears the LPIF status.
sahilmgandhi	18:6a4db94011d3	12851	* \| \| \|0 = The incoming frame is not a long frame or S/W wants to receive a long frame.
sahilmgandhi	18:6a4db94011d3	12852	* \| \| \|1 = The incoming frame is a long frame and dropped.
sahilmgandhi	18:6a4db94011d3	12853	* \|[4] \|RXGDIF \|Receive Good Interrupt
sahilmgandhi	18:6a4db94011d3	12854	* \| \| \|The RXGDIF high indicates the frame reception has completed.
sahilmgandhi	18:6a4db94011d3	12855	* \| \| \|If the RXGDIF is high and RXGDIEN (EAMC_MIEN[4]) is enabled, the RXIF will be high.
sahilmgandhi	18:6a4db94011d3	12856	* \| \| \|Write 1 to this bit clears the RXGDIF status.
sahilmgandhi	18:6a4db94011d3	12857	* \| \| \|0 = The frame reception has not complete yet.
sahilmgandhi	18:6a4db94011d3	12858	* \| \| \|1 = The frame reception has completed.
sahilmgandhi	18:6a4db94011d3	12859	* \|[5] \|ALIEIF \|Alignment Error Interrupt
sahilmgandhi	18:6a4db94011d3	12860	* \| \| \|The ALIEIF high indicates the length of the incoming frame is not a multiple of byte.
sahilmgandhi	18:6a4db94011d3	12861	* \| \| \|If the ALIEIF is high and ALIEIEN (EMAC_INTEN[5]) is enabled, the RXIF will be high.
sahilmgandhi	18:6a4db94011d3	12862	* \| \| \|Write 1 to this bit clears the ALIEIF status.
sahilmgandhi	18:6a4db94011d3	12863	* \| \| \|0 = The frame length is a multiple of byte.
sahilmgandhi	18:6a4db94011d3	12864	* \| \| \|1 = The frame length is not a multiple of byte.
sahilmgandhi	18:6a4db94011d3	12865	* \|[6] \|RPIF \|Runt Packet Interrupt
sahilmgandhi	18:6a4db94011d3	12866	* \| \| \|The RPIF high indicates the length of the incoming packet is less than 64 bytes and the packet is dropped.
sahilmgandhi	18:6a4db94011d3	12867	* \| \| \|If the ARP (EMAC_CTL[2]) is set, the short packet is regarded as a good packet and RPIF will not be set.
sahilmgandhi	18:6a4db94011d3	12868	* \| \| \|If the RPIF is high and RPIEN (EMAC_INTEN[6]) is enabled, the RXIF will be high.
sahilmgandhi	18:6a4db94011d3	12869	* \| \| \|Write 1 to this bit clears the RPIF status.
sahilmgandhi	18:6a4db94011d3	12870	* \| \| \|0 = The incoming frame is not a short frame or S/W wants to receive a short frame.
sahilmgandhi	18:6a4db94011d3	12871	* \| \| \|1 = The incoming frame is a short frame and dropped.
sahilmgandhi	18:6a4db94011d3	12872	* \|[7] \|MPCOVIF \|Missed Packet Counter Overrun Interrupt Flag
sahilmgandhi	18:6a4db94011d3	12873	* \| \| \|The MPCOVIF high indicates the MPCNT, Missed Packet Count, has overflow.
sahilmgandhi	18:6a4db94011d3	12874	* \| \| \|If the MPCOVIF is high and MPCOVIEN (EMAC_INTEN[7]) is enabled, the RXIF will be high.
sahilmgandhi	18:6a4db94011d3	12875	* \| \| \|Write 1 to this bit clears the MPCOVIF status.
sahilmgandhi	18:6a4db94011d3	12876	* \| \| \|0 = The MPCNT has not rolled over yet.
sahilmgandhi	18:6a4db94011d3	12877	* \| \| \|1 = The MPCNT has rolled over yet.
sahilmgandhi	18:6a4db94011d3	12878	* \|[8] \|MFLEIF \|Maximum Frame Length Exceed Interrupt Flag
sahilmgandhi	18:6a4db94011d3	12879	* \| \| \|The MFLEIF high indicates the length of the incoming packet has exceeded the length limitation configured in DMARFC register and the incoming packet is dropped.
sahilmgandhi	18:6a4db94011d3	12880	* \| \| \|If the MFLEIF is high and MFLEIEN (EMAC_INTEN[8]) is enabled, the RXIF will be high.
sahilmgandhi	18:6a4db94011d3	12881	* \| \| \|Write 1 to this bit clears the MFLEIF status.
sahilmgandhi	18:6a4db94011d3	12882	* \| \| \|0 = The length of the incoming packet does not exceed the length limitation configured in DMARFC.
sahilmgandhi	18:6a4db94011d3	12883	* \| \| \|1 = The length of the incoming packet has exceeded the length limitation configured in DMARFC.
sahilmgandhi	18:6a4db94011d3	12884	* \|[9] \|DENIF \|DMA Early Notification Interrupt
sahilmgandhi	18:6a4db94011d3	12885	* \| \| \|The DENIF high indicates the EMAC has received the LENGTH field of the incoming packet.
sahilmgandhi	18:6a4db94011d3	12886	* \| \| \|If the DENIF is high and DENIENI (EMAC_INTEN[9]) is enabled, the RXIF will be high.
sahilmgandhi	18:6a4db94011d3	12887	* \| \| \|Write 1 to this bit clears the DENIF status.
sahilmgandhi	18:6a4db94011d3	12888	* \| \| \|0 = The LENGTH field of incoming packet has not received yet.
sahilmgandhi	18:6a4db94011d3	12889	* \| \| \|1 = The LENGTH field of incoming packet has received.
sahilmgandhi	18:6a4db94011d3	12890	* \|[10] \|RDUIF \|Receive Descriptor Unavailable Interrupt
sahilmgandhi	18:6a4db94011d3	12891	* \| \| \|The RDUIF high indicates that there is no available RX descriptor for packet reception and RXDMA will stay at Halt state.
sahilmgandhi	18:6a4db94011d3	12892	* \| \| \|Once, the RXDMA enters the Halt state, S/W must issues a write command to RSDR register to make RXDMA leave Halt state while new RX descriptor is available.
sahilmgandhi	18:6a4db94011d3	12893	* \| \| \|If the RDUIF is high and RDUIEN (EMAC_INTEN[10]) is enabled, the RXIF will be high.
sahilmgandhi	18:6a4db94011d3	12894	* \| \| \|Write 1 to this bit clears the RDUIF status.
sahilmgandhi	18:6a4db94011d3	12895	* \| \| \|0 = RX descriptor is available.
sahilmgandhi	18:6a4db94011d3	12896	* \| \| \|1 = RX descriptor is unavailable.
sahilmgandhi	18:6a4db94011d3	12897	* \|[11] \|RXBEIF \|Receive Bus Error Interrupt
sahilmgandhi	18:6a4db94011d3	12898	* \| \| \|The RXBEIF high indicates the memory controller replies ERROR response while EMAC access system memory through RXDMA during packet reception process.
sahilmgandhi	18:6a4db94011d3	12899	* \| \| \|Reset EMAC is recommended while RXBEIF status is high.
sahilmgandhi	18:6a4db94011d3	12900	* \| \| \|If the RXBEIF is high and RXBEIEN (EMAC_INTEN[11]) is enabled, the RXIF will be high.
sahilmgandhi	18:6a4db94011d3	12901	* \| \| \|Write 1 to this bit clears the RXBEIF status.
sahilmgandhi	18:6a4db94011d3	12902	* \| \| \|0 = No ERROR response is received.
sahilmgandhi	18:6a4db94011d3	12903	* \| \| \|1 = ERROR response is received.
sahilmgandhi	18:6a4db94011d3	12904	* \|[14] \|CFRIF \|Control Frame Receive Interrupt
sahilmgandhi	18:6a4db94011d3	12905	* \| \| \|The CFRIF high indicates EMAC receives a flow control frame.
sahilmgandhi	18:6a4db94011d3	12906	* \| \| \|The CFRIF only available while EMAC is operating on full duplex mode.
sahilmgandhi	18:6a4db94011d3	12907	* \| \| \|If the CFRIF is high and CFRIEN (EMAC_INTEN[14]) is enabled, the RXIF will be high.
sahilmgandhi	18:6a4db94011d3	12908	* \| \| \|Write 1 to this bit clears the CFRIF status.
sahilmgandhi	18:6a4db94011d3	12909	* \| \| \|0 = The EMAC does not receive the flow control frame.
sahilmgandhi	18:6a4db94011d3	12910	* \| \| \|1 = The EMAC receives a flow control frame.
sahilmgandhi	18:6a4db94011d3	12911	* \|[15] \|WOLIF \|Wake On LAN Interrupt Flag
sahilmgandhi	18:6a4db94011d3	12912	* \| \| \|The WOLIF high indicates EMAC receives a Magic Packet.
sahilmgandhi	18:6a4db94011d3	12913	* \| \| \|The CFRIF only available while system is in power down mode and WOLEN is set high.
sahilmgandhi	18:6a4db94011d3	12914	* \| \| \|If the WOLIF is high and WOLIEN (EMAC_INTEN[15]) is enabled, the RXIF will be high.
sahilmgandhi	18:6a4db94011d3	12915	* \| \| \|Write 1 to this bit clears the WOLIF status.
sahilmgandhi	18:6a4db94011d3	12916	* \| \| \|0 = The EMAC does not receive the Magic Packet.
sahilmgandhi	18:6a4db94011d3	12917	* \| \| \|1 = The EMAC receives a Magic Packet.
sahilmgandhi	18:6a4db94011d3	12918	* \|[16] \|TXIF \|Transmit Interrupt
sahilmgandhi	18:6a4db94011d3	12919	* \| \| \|The TXIF indicates the TX interrupt status.
sahilmgandhi	18:6a4db94011d3	12920	* \| \| \|If TXIF high and its corresponding enable bit, TXIEN (EMAC_INTEN[16]), is also high indicates the EMAC generates TX interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	12921	* \| \| \|If TXIF is high but TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated.
sahilmgandhi	18:6a4db94011d3	12922	* \| \| \|The TXIF is logic OR result of bit logic AND result of EMAC_INTSTS[28:17] and EMAC_INTEN[28:17].
sahilmgandhi	18:6a4db94011d3	12923	* \| \| \|In other words, if any bit of EMAC_INTSTS[28:17] is high and its corresponding enable bit in EMAC_INTEN[28:17] is also enabled, the TXIF will be high.
sahilmgandhi	18:6a4db94011d3	12924	* \| \| \|Because the TXIF is a logic OR result, clears EMAC_INTSTS[28:17] makes TXIF be cleared, too.
sahilmgandhi	18:6a4db94011d3	12925	* \| \| \|0 = No status bit in EMAC_INTSTS[28:17] is set or no enable bit in EMAC_INTEN[28:17] is enabled.
sahilmgandhi	18:6a4db94011d3	12926	* \| \| \|1 = At least one status in EMAC_INTSTS[28:17] is set and its corresponding enable bit in EMAC_INTEN[28:17] is enabled, too.
sahilmgandhi	18:6a4db94011d3	12927	* \|[17] \|TXUDIF \|Transmit FIFO Underflow Interrupt
sahilmgandhi	18:6a4db94011d3	12928	* \| \| \|The TXUDIF high indicates the TXFIFO underflow occurred during packet transmission.
sahilmgandhi	18:6a4db94011d3	12929	* \| \| \|While the TXFIFO underflow occurred, the EMAC will retransmit the packet automatically without S/W intervention.
sahilmgandhi	18:6a4db94011d3	12930	* \| \| \|If the TXFIFO underflow occurred often, it is recommended that modify TXFIFO threshold control, the TXFIFOTH of FFTCR register, to higher level.
sahilmgandhi	18:6a4db94011d3	12931	* \| \| \|If the TXUDIF is high and TXUDIEN (EMAC_INTEN[17]) is enabled, the TXIF will be high.
sahilmgandhi	18:6a4db94011d3	12932	* \| \| \|Write 1 to this bit clears the TXUDIF status.
sahilmgandhi	18:6a4db94011d3	12933	* \| \| \|0 = No TXFIFO underflow occurred during packet transmission.
sahilmgandhi	18:6a4db94011d3	12934	* \| \| \|1 = TXFIFO underflow occurred during packet transmission.
sahilmgandhi	18:6a4db94011d3	12935	* \|[18] \|TXCPIF \|Transmit Completion Interrupt
sahilmgandhi	18:6a4db94011d3	12936	* \| \| \|The TXCPIF indicates the packet transmission has completed correctly.
sahilmgandhi	18:6a4db94011d3	12937	* \| \| \|If the TXCPIF is high and TXCPIEN (EMAC_INTEN[18]) is enabled, the TXIF will be high.
sahilmgandhi	18:6a4db94011d3	12938	* \| \| \|Write 1 to this bit clears the TXCPIF status.
sahilmgandhi	18:6a4db94011d3	12939	* \| \| \|0 = The packet transmission not completed.
sahilmgandhi	18:6a4db94011d3	12940	* \| \| \|1 = The packet transmission has completed.
sahilmgandhi	18:6a4db94011d3	12941	* \|[19] \|EXDEFIF \|Defer Exceed Interrupt
sahilmgandhi	18:6a4db94011d3	12942	* \| \| \|The EXDEFIF high indicates the frame waiting for transmission has deferred over 0.32768ms on 100Mbps mode, or 3.2768ms on 10Mbps mode.
sahilmgandhi	18:6a4db94011d3	12943	* \| \| \|The deferral exceed check will only be done while bit NODEF of MCMDR is disabled, and EMAC is operating on half-duplex mode.
sahilmgandhi	18:6a4db94011d3	12944	* \| \| \|If the EXDEFIF is high and EXDEFIEN (EMAC_INTEN[19]) is enabled, the TXIF will be high.
sahilmgandhi	18:6a4db94011d3	12945	* \| \| \|Write 1 to this bit clears the EXDEFIF status.
sahilmgandhi	18:6a4db94011d3	12946	* \| \| \|0 = Frame waiting for transmission has not deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps).
sahilmgandhi	18:6a4db94011d3	12947	* \| \| \|1 = Frame waiting for transmission has deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps).
sahilmgandhi	18:6a4db94011d3	12948	* \|[20] \|NCSIF \|No Carrier Sense Interrupt
sahilmgandhi	18:6a4db94011d3	12949	* \| \| \|The NCSIF high indicates the MII I/F signal CRS does not active at the start of or during the packet transmission.
sahilmgandhi	18:6a4db94011d3	12950	* \| \| \|The NCSIF is only available while EMAC is operating on half-duplex mode.
sahilmgandhi	18:6a4db94011d3	12951	* \| \| \|If the NCSIF is high and NCSIEN (EMAC_INTEN[20]) is enabled, the TXIF will be high.
sahilmgandhi	18:6a4db94011d3	12952	* \| \| \|Write 1 to this bit clears the NCSIF status.
sahilmgandhi	18:6a4db94011d3	12953	* \| \| \|0 = CRS signal actives correctly.
sahilmgandhi	18:6a4db94011d3	12954	* \| \| \|1 = CRS signal does not active at the start of or during the packet transmission.
sahilmgandhi	18:6a4db94011d3	12955	* \|[21] \|TXABTIF \|Transmit Abort Interrupt
sahilmgandhi	18:6a4db94011d3	12956	* \| \| \|The TXABTIF high indicates the packet incurred 16 consecutive collisions during transmission, and then the transmission process for this packet is aborted.
sahilmgandhi	18:6a4db94011d3	12957	* \| \| \|The transmission abort is only available while EMAC is operating on half-duplex mode.
sahilmgandhi	18:6a4db94011d3	12958	* \| \| \|If the TXABTIF is high and TXABTIEN (EMAC_INTEN[21]) is enabled, the TXIF will be high.
sahilmgandhi	18:6a4db94011d3	12959	* \| \| \|Write 1 to this bit clears the TXABTIF status.
sahilmgandhi	18:6a4db94011d3	12960	* \| \| \|0 = Packet does not incur 16 consecutive collisions during transmission.
sahilmgandhi	18:6a4db94011d3	12961	* \| \| \|1 = Packet incurred 16 consecutive collisions during transmission.
sahilmgandhi	18:6a4db94011d3	12962	* \|[22] \|LCIF \|Late Collision Interrupt
sahilmgandhi	18:6a4db94011d3	12963	* \| \| \|The LCIF high indicates the collision occurred in the outside of 64 bytes collision window.
sahilmgandhi	18:6a4db94011d3	12964	* \| \| \|This means after the 64 bytes of a frame has been transmitted out to the network, the collision still occurred.
sahilmgandhi	18:6a4db94011d3	12965	* \| \| \|The late collision check will only be done while EMAC is operating on half-duplex mode.
sahilmgandhi	18:6a4db94011d3	12966	* \| \| \|If the LCIF is high and LCIEN (EMAC_INTEN[22]) is enabled, the TXIF will be high.
sahilmgandhi	18:6a4db94011d3	12967	* \| \| \|Write 1 to this bit clears the LCIF status.
sahilmgandhi	18:6a4db94011d3	12968	* \| \| \|0 = No collision occurred in the outside of 64 bytes collision window.
sahilmgandhi	18:6a4db94011d3	12969	* \| \| \|1 = Collision occurred in the outside of 64 bytes collision window.
sahilmgandhi	18:6a4db94011d3	12970	* \|[23] \|TDUIF \|Transmit Descriptor Unavailable Interrupt
sahilmgandhi	18:6a4db94011d3	12971	* \| \| \|The TDUIF high indicates that there is no available TX descriptor for packet transmission and TXDMA will stay at Halt state.
sahilmgandhi	18:6a4db94011d3	12972	* \| \| \|Once, the TXDMA enters the Halt state, S/W must issues a write command to TSDR register to make TXDMA leave Halt state while new TX descriptor is available.
sahilmgandhi	18:6a4db94011d3	12973	* \| \| \|If the TDUIF is high and TDUIEN (EMAC_INTEN[23]) is enabled, the TXIF will be high.
sahilmgandhi	18:6a4db94011d3	12974	* \| \| \|Write 1 to this bit clears the TDUIF status.
sahilmgandhi	18:6a4db94011d3	12975	* \| \| \|0 = TX descriptor is available.
sahilmgandhi	18:6a4db94011d3	12976	* \| \| \|1 = TX descriptor is unavailable.
sahilmgandhi	18:6a4db94011d3	12977	* \|[24] \|TXBEIF \|Transmit Bus Error Interrupt
sahilmgandhi	18:6a4db94011d3	12978	* \| \| \|The TXBEIF high indicates the memory controller replies ERROR response while EMAC access system memory through TXDMA during packet transmission process.
sahilmgandhi	18:6a4db94011d3	12979	* \| \| \|Reset EMAC is recommended while TXBEIF status is high.
sahilmgandhi	18:6a4db94011d3	12980	* \| \| \|If the TXBEIF is high and TXBEIEN (EMAC_INTEN[24]) is enabled, the TXIF will be high.
sahilmgandhi	18:6a4db94011d3	12981	* \| \| \|Write 1 to this bit clears the TXBEIF status.
sahilmgandhi	18:6a4db94011d3	12982	* \| \| \|0 = No ERROR response is received.
sahilmgandhi	18:6a4db94011d3	12983	* \| \| \|1 = ERROR response is received.
sahilmgandhi	18:6a4db94011d3	12984	* \|[28] \|TSALMIF \|Time Stamp Alarm Interrupt
sahilmgandhi	18:6a4db94011d3	12985	* \| \| \|The TSALMIF high indicates the EMAC_TSSEC register value equals to EMAC_ALMSEC register and EMAC_TSSUBSEC register value equals to register EMAC_TSMLSR.
sahilmgandhi	18:6a4db94011d3	12986	* \| \| \|If TSALMIF is high and TSALMIEN (EMAC_INTEN[28]) enabled, the TXIF will be high.
sahilmgandhi	18:6a4db94011d3	12987	* \| \| \|Write 1 to this bit clears the TSALMIF status.
sahilmgandhi	18:6a4db94011d3	12988	* \| \| \|0 = EMAC_TSSEC did not equal EMAC_ALMSEC or EMAC_TSSUBSEC did not equal EMAC_ALMSUBSEC.
sahilmgandhi	18:6a4db94011d3	12989	* \| \| \|1 = EMAC_TSSEC equals EMAC_ALMSEC and EMAC_TSSUBSEC equals EMAC_ALMSUBSEC.
sahilmgandhi	18:6a4db94011d3	12990	*/
sahilmgandhi	18:6a4db94011d3	12991	__IO uint32_t INTSTS;
sahilmgandhi	18:6a4db94011d3	12992
sahilmgandhi	18:6a4db94011d3	12993	/**
sahilmgandhi	18:6a4db94011d3	12994	* GENSTS
sahilmgandhi	18:6a4db94011d3	12995	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	12996	* Offset: 0xB4 MAC General Status Register
sahilmgandhi	18:6a4db94011d3	12997	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	12998	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	12999	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	13000	* \|[0] \|CFRIF \|Control Frame Received
sahilmgandhi	18:6a4db94011d3	13001	* \| \| \|The CFRIF high indicates EMAC receives a flow control frame.
sahilmgandhi	18:6a4db94011d3	13002	* \| \| \|The CFRIF only available while EMAC is operating on full duplex mode.
sahilmgandhi	18:6a4db94011d3	13003	* \| \| \|0 = The EMAC does not receive the flow control frame.
sahilmgandhi	18:6a4db94011d3	13004	* \| \| \|1 = The EMAC receives a flow control frame.
sahilmgandhi	18:6a4db94011d3	13005	* \|[1] \|RXHALT \|Receive Halted
sahilmgandhi	18:6a4db94011d3	13006	* \| \| \|The RXHALT high indicates the next normal packet reception process will be halted because the bit RXON of MCMDR is disabled be S/W.
sahilmgandhi	18:6a4db94011d3	13007	* \| \| \|0 = Next normal packet reception process will go on.
sahilmgandhi	18:6a4db94011d3	13008	* \| \| \|1 = Next normal packet reception process will be halted.
sahilmgandhi	18:6a4db94011d3	13009	* \|[2] \|RXFFULL \|RXFIFO Full
sahilmgandhi	18:6a4db94011d3	13010	* \| \| \|The RXFFULL indicates the RXFIFO is full due to four 64-byte packets are kept in RXFIFO and the following incoming packet will be dropped.
sahilmgandhi	18:6a4db94011d3	13011	* \| \| \|0 = The RXFIFO is not full.
sahilmgandhi	18:6a4db94011d3	13012	* \| \| \|1 = The RXFIFO is full and the following incoming packet will be dropped.
sahilmgandhi	18:6a4db94011d3	13013	* \|[4:7] \|COLCNT \|Collision Count
sahilmgandhi	18:6a4db94011d3	13014	* \| \| \|The COLCNT indicates that how many collisions occurred consecutively during a packet transmission.
sahilmgandhi	18:6a4db94011d3	13015	* \| \| \|If the packet incurred 16 consecutive collisions during transmission, the COLCNT will be 0 and bit TXABTIF will be set to 1.
sahilmgandhi	18:6a4db94011d3	13016	* \|[8] \|DEF \|Deferred Transmission
sahilmgandhi	18:6a4db94011d3	13017	* \| \| \|The DEF high indicates the packet transmission has deferred once.
sahilmgandhi	18:6a4db94011d3	13018	* \| \| \|The DEF is only available while EMAC is operating on half-duplex mode.
sahilmgandhi	18:6a4db94011d3	13019	* \| \| \|0 = Packet transmission does not defer.
sahilmgandhi	18:6a4db94011d3	13020	* \| \| \|1 = Packet transmission has deferred once.
sahilmgandhi	18:6a4db94011d3	13021	* \|[9] \|TXPAUSED \|Transmission Paused
sahilmgandhi	18:6a4db94011d3	13022	* \| \| \|The TXPAUSED high indicates the next normal packet transmission process will be paused temporally because EMAC received a PAUSE control frame.
sahilmgandhi	18:6a4db94011d3	13023	* \| \| \|0 = Next normal packet transmission process will go on.
sahilmgandhi	18:6a4db94011d3	13024	* \| \| \|1 = Next normal packet transmission process will be paused.
sahilmgandhi	18:6a4db94011d3	13025	* \|[10] \|SQE \|Signal Quality Error
sahilmgandhi	18:6a4db94011d3	13026	* \| \| \|The SQE high indicates the SQE error found at end of packet transmission on 10Mbps half-duplex mode.
sahilmgandhi	18:6a4db94011d3	13027	* \| \| \|The SQE error check will only be done while both bit SQECHKEN (EMAC_CTL[17]) is enabled and EMAC is operating on 10Mbps half-duplex mode.
sahilmgandhi	18:6a4db94011d3	13028	* \| \| \|0 = No SQE error found at end of packet transmission.
sahilmgandhi	18:6a4db94011d3	13029	* \| \| \|1 = SQE error found at end of packet transmission.
sahilmgandhi	18:6a4db94011d3	13030	* \|[11] \|TXHALT \|Transmission Halted
sahilmgandhi	18:6a4db94011d3	13031	* \| \| \|The TXHALT high indicates the next normal packet transmission process will be halted because the bit TXON (EMAC_CTL[8]) is disabled be S/W.
sahilmgandhi	18:6a4db94011d3	13032	* \| \| \|0 = Next normal packet transmission process will go on.
sahilmgandhi	18:6a4db94011d3	13033	* \| \| \|1 = Next normal packet transmission process will be halted.
sahilmgandhi	18:6a4db94011d3	13034	* \|[12] \|RPSTS \|Remote Pause Status
sahilmgandhi	18:6a4db94011d3	13035	* \| \| \|The RPSTS indicates that remote pause counter down counting actives.
sahilmgandhi	18:6a4db94011d3	13036	* \| \| \|After Ethernet MAC controller sent PAUSE frame out successfully, it starts the remote pause counter down counting.
sahilmgandhi	18:6a4db94011d3	13037	* \| \| \|When this bit high, it's predictable that remote Ethernet MAC controller wouldn't start the packet transmission until the down counting done.
sahilmgandhi	18:6a4db94011d3	13038	* \| \| \|0 = Remote pause counter down counting done.
sahilmgandhi	18:6a4db94011d3	13039	* \| \| \|1 = Remote pause counter down counting actives.
sahilmgandhi	18:6a4db94011d3	13040	*/
sahilmgandhi	18:6a4db94011d3	13041	__IO uint32_t GENSTS;
sahilmgandhi	18:6a4db94011d3	13042
sahilmgandhi	18:6a4db94011d3	13043	/**
sahilmgandhi	18:6a4db94011d3	13044	* MPCNT
sahilmgandhi	18:6a4db94011d3	13045	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	13046	* Offset: 0xB8 Missed Packet Count Register
sahilmgandhi	18:6a4db94011d3	13047	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	13048	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	13049	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	13050	* \|[0:15] \|MPCNT \|Miss Packet Count
sahilmgandhi	18:6a4db94011d3	13051	* \| \| \|The MPCNT indicates the number of packets that were dropped due to various types of receive errors.
sahilmgandhi	18:6a4db94011d3	13052	* \| \| \|The following type of receiving error makes missed packet counter increase:.
sahilmgandhi	18:6a4db94011d3	13053	* \| \| \|1. Incoming packet is incurred RXFIFO overflow.
sahilmgandhi	18:6a4db94011d3	13054	* \| \| \|2. Incoming packet is dropped due to RXON is disabled.
sahilmgandhi	18:6a4db94011d3	13055	* \| \| \|3. Incoming packet is incurred CRC error.
sahilmgandhi	18:6a4db94011d3	13056	*/
sahilmgandhi	18:6a4db94011d3	13057	__IO uint32_t MPCNT;
sahilmgandhi	18:6a4db94011d3	13058
sahilmgandhi	18:6a4db94011d3	13059	/**
sahilmgandhi	18:6a4db94011d3	13060	* RPCNT
sahilmgandhi	18:6a4db94011d3	13061	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	13062	* Offset: 0xBC MAC Receive Pause Count Register
sahilmgandhi	18:6a4db94011d3	13063	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	13064	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	13065	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	13066	* \|[0:15] \|RPCNT \|MAC Receive Pause Count
sahilmgandhi	18:6a4db94011d3	13067	* \| \| \|The RPCNT keeps the OPERAND field of the PAUSE control frame.
sahilmgandhi	18:6a4db94011d3	13068	* \| \| \|It indicates how many slot time (512 bit time) the TX of EMAC will be paused.
sahilmgandhi	18:6a4db94011d3	13069	*/
sahilmgandhi	18:6a4db94011d3	13070	__I uint32_t RPCNT;
sahilmgandhi	18:6a4db94011d3	13071	uint32_t RESERVE0[2];
sahilmgandhi	18:6a4db94011d3	13072
sahilmgandhi	18:6a4db94011d3	13073
sahilmgandhi	18:6a4db94011d3	13074	/**
sahilmgandhi	18:6a4db94011d3	13075	* FRSTS
sahilmgandhi	18:6a4db94011d3	13076	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	13077	* Offset: 0xC8 DMA Receive Frame Status Register
sahilmgandhi	18:6a4db94011d3	13078	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	13079	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	13080	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	13081	* \|[0:15] \|RXFLT \|Receive Frame LENGTH
sahilmgandhi	18:6a4db94011d3	13082	* \| \| \|The RXFLT keeps the LENGTH field of each incoming Ethernet packet.
sahilmgandhi	18:6a4db94011d3	13083	* \| \| \|If the bit DENIEN (EMAC_INTEN[9]) is enabled and the LENGTH field of incoming packet has received, the bit DENIF (EMAC_INTSTS[9]) will be set and trigger interrupt.
sahilmgandhi	18:6a4db94011d3	13084	* \| \| \|And, the content of LENGTH field will be stored in RXFLT.
sahilmgandhi	18:6a4db94011d3	13085	*/
sahilmgandhi	18:6a4db94011d3	13086	__IO uint32_t FRSTS;
sahilmgandhi	18:6a4db94011d3	13087
sahilmgandhi	18:6a4db94011d3	13088	/**
sahilmgandhi	18:6a4db94011d3	13089	* CTXDSA
sahilmgandhi	18:6a4db94011d3	13090	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	13091	* Offset: 0xCC Current Transmit Descriptor Start Address Register
sahilmgandhi	18:6a4db94011d3	13092	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	13093	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	13094	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	13095	* \|[0:31] \|CTXDSA \|Current Transmit Descriptor Start Address
sahilmgandhi	18:6a4db94011d3	13096	* \| \| \|The CTXDSA keeps the start address of TX descriptor that is used by TXDMA currently.
sahilmgandhi	18:6a4db94011d3	13097	* \| \| \|The CTXDSA is read only and write to this register has no effect.
sahilmgandhi	18:6a4db94011d3	13098	*/
sahilmgandhi	18:6a4db94011d3	13099	__I uint32_t CTXDSA;
sahilmgandhi	18:6a4db94011d3	13100
sahilmgandhi	18:6a4db94011d3	13101	/**
sahilmgandhi	18:6a4db94011d3	13102	* CTXBSA
sahilmgandhi	18:6a4db94011d3	13103	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	13104	* Offset: 0xD0 Current Transmit Buffer Start Address Register
sahilmgandhi	18:6a4db94011d3	13105	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	13106	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	13107	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	13108	* \|[0:31] \|CTXBSA \|Current Transmit Buffer Start Address
sahilmgandhi	18:6a4db94011d3	13109	* \| \| \|The CTXDSA keeps the start address of TX frame buffer that is used by TXDMA currently.
sahilmgandhi	18:6a4db94011d3	13110	* \| \| \|The CTXBSA is read only and write to this register has no effect.
sahilmgandhi	18:6a4db94011d3	13111	*/
sahilmgandhi	18:6a4db94011d3	13112	__I uint32_t CTXBSA;
sahilmgandhi	18:6a4db94011d3	13113
sahilmgandhi	18:6a4db94011d3	13114	/**
sahilmgandhi	18:6a4db94011d3	13115	* CRXDSA
sahilmgandhi	18:6a4db94011d3	13116	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	13117	* Offset: 0xD4 Current Receive Descriptor Start Address Register
sahilmgandhi	18:6a4db94011d3	13118	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	13119	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	13120	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	13121	* \|[0:31] \|CRXDSA \|Current Receive Descriptor Start Address
sahilmgandhi	18:6a4db94011d3	13122	* \| \| \|The CRXDSA keeps the start address of RX descriptor that is used by RXDMA currently.
sahilmgandhi	18:6a4db94011d3	13123	* \| \| \|The CRXDSA is read only and write to this register has no effect.
sahilmgandhi	18:6a4db94011d3	13124	*/
sahilmgandhi	18:6a4db94011d3	13125	__I uint32_t CRXDSA;
sahilmgandhi	18:6a4db94011d3	13126
sahilmgandhi	18:6a4db94011d3	13127	/**
sahilmgandhi	18:6a4db94011d3	13128	* CRXBSA
sahilmgandhi	18:6a4db94011d3	13129	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	13130	* Offset: 0xD8 Current Receive Buffer Start Address Register
sahilmgandhi	18:6a4db94011d3	13131	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	13132	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	13133	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	13134	* \|[0:31] \|CRXBSA \|Current Receive Buffer Start Address
sahilmgandhi	18:6a4db94011d3	13135	* \| \| \|The CRXBSA keeps the start address of RX frame buffer that is used by RXDMA currently.
sahilmgandhi	18:6a4db94011d3	13136	* \| \| \|The CRXBSA is read only and write to this register has no effect.
sahilmgandhi	18:6a4db94011d3	13137	*/
sahilmgandhi	18:6a4db94011d3	13138	__I uint32_t CRXBSA;
sahilmgandhi	18:6a4db94011d3	13139	uint32_t RESERVE1[9];
sahilmgandhi	18:6a4db94011d3	13140
sahilmgandhi	18:6a4db94011d3	13141
sahilmgandhi	18:6a4db94011d3	13142	/**
sahilmgandhi	18:6a4db94011d3	13143	* TSCTL
sahilmgandhi	18:6a4db94011d3	13144	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	13145	* Offset: 0x100 Time Stamp Control Register
sahilmgandhi	18:6a4db94011d3	13146	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	13147	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	13148	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	13149	* \|[0] \|TSEN \|Time Stamp Function Enable Control
sahilmgandhi	18:6a4db94011d3	13150	* \| \| \|This bit controls if the IEEE 1588 PTP time stamp function is enabled or not.
sahilmgandhi	18:6a4db94011d3	13151	* \| \| \|Set this bit high to enable IEEE 1588 PTP time stamp function while set this bit low to disable IEEE 1588 PTP time stamp function.
sahilmgandhi	18:6a4db94011d3	13152	* \| \| \|0 = I EEE 1588 PTP time stamp function Disabled.
sahilmgandhi	18:6a4db94011d3	13153	* \| \| \|1 = IEEE 1588 PTP time stamp function Enabled.
sahilmgandhi	18:6a4db94011d3	13154	* \|[1] \|TSIEN \|Time Stamp Counter Initialization Enable Control
sahilmgandhi	18:6a4db94011d3	13155	* \| \| \|Set this bit high enables Ethernet MAC controller to load value of register EMAC_UPDSEC and EMAC_UPDSUBSEC to PTP time stampe counter.
sahilmgandhi	18:6a4db94011d3	13156	* \| \| \|After the load operation finished, Ethernet MAC controller clear this bit to low automatically.
sahilmgandhi	18:6a4db94011d3	13157	* \| \| \|0 = Time stamp counter initialization done.
sahilmgandhi	18:6a4db94011d3	13158	* \| \| \|1 = Time stamp counter initialization Enabled.
sahilmgandhi	18:6a4db94011d3	13159	* \|[2] \|TSMODE \|Time Stamp Fine Update Enable Control
sahilmgandhi	18:6a4db94011d3	13160	* \| \| \|This bit chooses the time stamp counter update mode.
sahilmgandhi	18:6a4db94011d3	13161	* \| \| \|0 = Time stamp counter is in coarse update mode.
sahilmgandhi	18:6a4db94011d3	13162	* \| \| \|1 = Time stamp counter is in fine update mode.
sahilmgandhi	18:6a4db94011d3	13163	* \|[3] \|TSUPDATE \|Time Stamp Counter Time Update Enable Control
sahilmgandhi	18:6a4db94011d3	13164	* \| \| \|Set this bit high enables Ethernet MAC controller to add value of register EMAC_UPDSEC and EMAC_UPDSUBSEC to PTP time stamp counter.
sahilmgandhi	18:6a4db94011d3	13165	* \| \| \|After the add operation finished, Ethernet MAC controller clear this bit to low automatically.
sahilmgandhi	18:6a4db94011d3	13166	* \| \| \|0 = No action.
sahilmgandhi	18:6a4db94011d3	13167	* \| \| \|1 = EMAC_UPDSEC updated to EMAC_TSSEC and EMAC_UPDSUBSEC updated to EMAC_TSSUBSEC.
sahilmgandhi	18:6a4db94011d3	13168	* \|[5] \|TSALMEN \|Time Stamp Alarm Enable Control
sahilmgandhi	18:6a4db94011d3	13169	* \| \| \|Set this bit high enable Ethernet MAC controller to set TSALMIF (EMAC_INTSTS[28]) high when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
sahilmgandhi	18:6a4db94011d3	13170	* \| \| \|0 = Alarm disabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
sahilmgandhi	18:6a4db94011d3	13171	* \| \| \|1 = Alarm enabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
sahilmgandhi	18:6a4db94011d3	13172	*/
sahilmgandhi	18:6a4db94011d3	13173	__IO uint32_t TSCTL;
sahilmgandhi	18:6a4db94011d3	13174	uint32_t RESERVE2[3];
sahilmgandhi	18:6a4db94011d3	13175
sahilmgandhi	18:6a4db94011d3	13176
sahilmgandhi	18:6a4db94011d3	13177	/**
sahilmgandhi	18:6a4db94011d3	13178	* TSSEC
sahilmgandhi	18:6a4db94011d3	13179	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	13180	* Offset: 0x110 Time Stamp Most Significant Register
sahilmgandhi	18:6a4db94011d3	13181	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	13182	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	13183	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	13184	* \|[0:31] \|SEC \|Time Stamp Counter Second
sahilmgandhi	18:6a4db94011d3	13185	* \| \| \|This register reflects the bit [63:32] value of 64-bit reference timing counter.
sahilmgandhi	18:6a4db94011d3	13186	* \| \| \|This 32-bit value is used as the second part of time stamp when TSEN (EMAC_TSCTL[0]) is high.
sahilmgandhi	18:6a4db94011d3	13187	*/
sahilmgandhi	18:6a4db94011d3	13188	__I uint32_t TSSEC;
sahilmgandhi	18:6a4db94011d3	13189
sahilmgandhi	18:6a4db94011d3	13190	/**
sahilmgandhi	18:6a4db94011d3	13191	* TSSUBSEC
sahilmgandhi	18:6a4db94011d3	13192	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	13193	* Offset: 0x114 Time Stamp Least Significant Register
sahilmgandhi	18:6a4db94011d3	13194	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	13195	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	13196	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	13197	* \|[0:31] \|SUBSEC \|Time Stamp Counter Sub-Second
sahilmgandhi	18:6a4db94011d3	13198	* \| \| \|This register reflects the bit [31:0] value of 64-bit reference timing counter.
sahilmgandhi	18:6a4db94011d3	13199	* \| \| \|This 32-bit value is used as the sub-second part of time stamp when TSEN (EMAC_TSCTL[0]) is high.
sahilmgandhi	18:6a4db94011d3	13200	*/
sahilmgandhi	18:6a4db94011d3	13201	__I uint32_t TSSUBSEC;
sahilmgandhi	18:6a4db94011d3	13202
sahilmgandhi	18:6a4db94011d3	13203	/**
sahilmgandhi	18:6a4db94011d3	13204	* TSINC
sahilmgandhi	18:6a4db94011d3	13205	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	13206	* Offset: 0x118 Time Stamp Increment Register
sahilmgandhi	18:6a4db94011d3	13207	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	13208	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	13209	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	13210	* \|[0:7] \|CNTINC \|Time Stamp Counter Increment
sahilmgandhi	18:6a4db94011d3	13211	* \| \| \|Time stamp counter increment value.
sahilmgandhi	18:6a4db94011d3	13212	* \| \| \|If TSEN (EMAC_TSCTL[0]) is high, EMAC adds EMAC_TSSUBSEC with this 8-bit value every time when it wants to increase the EMAC_TSSUBSEC value.
sahilmgandhi	18:6a4db94011d3	13213	*/
sahilmgandhi	18:6a4db94011d3	13214	__IO uint32_t TSINC;
sahilmgandhi	18:6a4db94011d3	13215
sahilmgandhi	18:6a4db94011d3	13216	/**
sahilmgandhi	18:6a4db94011d3	13217	* TSADDEND
sahilmgandhi	18:6a4db94011d3	13218	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	13219	* Offset: 0x11C Time Stamp Addend Register
sahilmgandhi	18:6a4db94011d3	13220	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	13221	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	13222	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	13223	* \|[0:31] \|ADDEND \|Time Stamp Counter Addend
sahilmgandhi	18:6a4db94011d3	13224	* \| \| \|This register keeps a 32-bit value for accumulator to enable increment of EMAC_TSSUBSEC.
sahilmgandhi	18:6a4db94011d3	13225	* \| \| \|If TSEN (EMAC_TSCTL[0]) and TSMODE (EMAC_TSCTL[2]) are both high, EMAC increases accumulator with this 32-bit value in each HCLK.
sahilmgandhi	18:6a4db94011d3	13226	* \| \| \|Once the accumulator is overflow, it generates a enable to increase EMAC_TSSUBSEC with an 8-bit value kept in register EMAC_TSINC.
sahilmgandhi	18:6a4db94011d3	13227	*/
sahilmgandhi	18:6a4db94011d3	13228	__IO uint32_t TSADDEND;
sahilmgandhi	18:6a4db94011d3	13229
sahilmgandhi	18:6a4db94011d3	13230	/**
sahilmgandhi	18:6a4db94011d3	13231	* UPDSEC
sahilmgandhi	18:6a4db94011d3	13232	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	13233	* Offset: 0x120 Time Stamp Most Significant Update Register
sahilmgandhi	18:6a4db94011d3	13234	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	13235	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	13236	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	13237	* \|[0:31] \|SEC \|Time Stamp Counter Second Update
sahilmgandhi	18:6a4db94011d3	13238	* \| \| \|When TSIEN (EMAC_TSCTL[1]) is high.
sahilmgandhi	18:6a4db94011d3	13239	* \| \| \|EMAC loads this 32-bit value to EMAC_TSSEC directly.
sahilmgandhi	18:6a4db94011d3	13240	* \| \| \|When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSEC with this 32-bit value.
sahilmgandhi	18:6a4db94011d3	13241	*/
sahilmgandhi	18:6a4db94011d3	13242	__IO uint32_t UPDSEC;
sahilmgandhi	18:6a4db94011d3	13243
sahilmgandhi	18:6a4db94011d3	13244	/**
sahilmgandhi	18:6a4db94011d3	13245	* UPDSUBSEC
sahilmgandhi	18:6a4db94011d3	13246	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	13247	* Offset: 0x124 Time Stamp Least Significant Update Register
sahilmgandhi	18:6a4db94011d3	13248	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	13249	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	13250	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	13251	* \|[0:31] \|SUBSEC \|Time Stamp Counter Sub-Second Update
sahilmgandhi	18:6a4db94011d3	13252	* \| \| \|When TSIEN (EMAC_TSCTL[1]) is high.
sahilmgandhi	18:6a4db94011d3	13253	* \| \| \|EMAC loads this 32-bit value to EMAC_TSSUBSEC directly.
sahilmgandhi	18:6a4db94011d3	13254	* \| \| \|When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSUBSEC with this 32-bit value.
sahilmgandhi	18:6a4db94011d3	13255	*/
sahilmgandhi	18:6a4db94011d3	13256	__IO uint32_t UPDSUBSEC;
sahilmgandhi	18:6a4db94011d3	13257
sahilmgandhi	18:6a4db94011d3	13258	/**
sahilmgandhi	18:6a4db94011d3	13259	* ALMSEC
sahilmgandhi	18:6a4db94011d3	13260	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	13261	* Offset: 0x128 Time Stamp Most Significant Alarm Register
sahilmgandhi	18:6a4db94011d3	13262	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	13263	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	13264	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	13265	* \|[0:31] \|SEC \|Time Stamp Counter Second Alarm
sahilmgandhi	18:6a4db94011d3	13266	* \| \| \|Time stamp counter second part alarm value.
sahilmgandhi	18:6a4db94011d3	13267	* \| \| \|This value is only useful when ALMEN (EMAC_TSCTL[5]) high.
sahilmgandhi	18:6a4db94011d3	13268	* \| \| \|If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high.
sahilmgandhi	18:6a4db94011d3	13269	*/
sahilmgandhi	18:6a4db94011d3	13270	__IO uint32_t ALMSEC;
sahilmgandhi	18:6a4db94011d3	13271
sahilmgandhi	18:6a4db94011d3	13272	/**
sahilmgandhi	18:6a4db94011d3	13273	* ALMSUBSEC
sahilmgandhi	18:6a4db94011d3	13274	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	13275	* Offset: 0x12C Time Stamp Least Significant Alarm Register
sahilmgandhi	18:6a4db94011d3	13276	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	13277	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	13278	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	13279	* \|[0:31] \|SUBSEC \|Time Stamp Counter Sub-Second Alarm
sahilmgandhi	18:6a4db94011d3	13280	* \| \| \|Time stamp counter sub-second part alarm value.
sahilmgandhi	18:6a4db94011d3	13281	* \| \| \|This value is only useful when ALMEN (EMAC_TSCTL[5]) high.
sahilmgandhi	18:6a4db94011d3	13282	* \| \| \|If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high.
sahilmgandhi	18:6a4db94011d3	13283	*/
sahilmgandhi	18:6a4db94011d3	13284	__IO uint32_t ALMSUBSEC;
sahilmgandhi	18:6a4db94011d3	13285
sahilmgandhi	18:6a4db94011d3	13286	} EMAC_T;
sahilmgandhi	18:6a4db94011d3	13287
sahilmgandhi	18:6a4db94011d3	13288	/**
sahilmgandhi	18:6a4db94011d3	13289	@addtogroup EMAC_CONST EMAC Bit Field Definition
sahilmgandhi	18:6a4db94011d3	13290	Constant Definitions for EMAC Controller
sahilmgandhi	18:6a4db94011d3	13291	@{ */
sahilmgandhi	18:6a4db94011d3	13292
sahilmgandhi	18:6a4db94011d3	13293	#define EMAC_CAMCTL_AUP_Pos (0) /!< EMAC CAMCTL: AUP Position /
sahilmgandhi	18:6a4db94011d3	13294	#define EMAC_CAMCTL_AUP_Msk (0x1ul << EMAC_CAMCTL_AUP_Pos) /!< EMAC CAMCTL: AUP Mask /
sahilmgandhi	18:6a4db94011d3	13295
sahilmgandhi	18:6a4db94011d3	13296	#define EMAC_CAMCTL_AMP_Pos (1) /!< EMAC CAMCTL: AMP Position /
sahilmgandhi	18:6a4db94011d3	13297	#define EMAC_CAMCTL_AMP_Msk (0x1ul << EMAC_CAMCTL_AMP_Pos) /!< EMAC CAMCTL: AMP Mask /
sahilmgandhi	18:6a4db94011d3	13298
sahilmgandhi	18:6a4db94011d3	13299	#define EMAC_CAMCTL_ABP_Pos (2) /!< EMAC CAMCTL: ABP Position /
sahilmgandhi	18:6a4db94011d3	13300	#define EMAC_CAMCTL_ABP_Msk (0x1ul << EMAC_CAMCTL_ABP_Pos) /!< EMAC CAMCTL: ABP Mask /
sahilmgandhi	18:6a4db94011d3	13301
sahilmgandhi	18:6a4db94011d3	13302	#define EMAC_CAMCTL_COMPEN_Pos (3) /!< EMAC CAMCTL: COMPEN Position /
sahilmgandhi	18:6a4db94011d3	13303	#define EMAC_CAMCTL_COMPEN_Msk (0x1ul << EMAC_CAMCTL_COMPEN_Pos) /!< EMAC CAMCTL: COMPEN Mask /
sahilmgandhi	18:6a4db94011d3	13304
sahilmgandhi	18:6a4db94011d3	13305	#define EMAC_CAMCTL_CMPEN_Pos (4) /!< EMAC CAMCTL: CMPEN Position /
sahilmgandhi	18:6a4db94011d3	13306	#define EMAC_CAMCTL_CMPEN_Msk (0x1ul << EMAC_CAMCTL_CMPEN_Pos) /!< EMAC CAMCTL: CMPEN Mask /
sahilmgandhi	18:6a4db94011d3	13307
sahilmgandhi	18:6a4db94011d3	13308	#define EMAC_CAMEN_CAMxEN_Pos (0) /!< EMAC CAMEN: CAMxEN Position /
sahilmgandhi	18:6a4db94011d3	13309	#define EMAC_CAMEN_CAMxEN_Msk (0x1ul << EMAC_CAMEN_CAMxEN_Pos) /!< EMAC CAMEN: CAMxEN Mask /
sahilmgandhi	18:6a4db94011d3	13310
sahilmgandhi	18:6a4db94011d3	13311	#define EMAC_CAM0M_MACADDR2_Pos (0) /!< EMAC CAM0M: MACADDR2 Position /
sahilmgandhi	18:6a4db94011d3	13312	#define EMAC_CAM0M_MACADDR2_Msk (0xfful << EMAC_CAM0M_MACADDR2_Pos) /!< EMAC CAM0M: MACADDR2 Mask /
sahilmgandhi	18:6a4db94011d3	13313
sahilmgandhi	18:6a4db94011d3	13314	#define EMAC_CAM0M_MACADDR3_Pos (8) /!< EMAC CAM0M: MACADDR3 Position /
sahilmgandhi	18:6a4db94011d3	13315	#define EMAC_CAM0M_MACADDR3_Msk (0xfful << EMAC_CAM0M_MACADDR3_Pos) /!< EMAC CAM0M: MACADDR3 Mask /
sahilmgandhi	18:6a4db94011d3	13316
sahilmgandhi	18:6a4db94011d3	13317	#define EMAC_CAM0M_MACADDR4_Pos (16) /!< EMAC CAM0M: MACADDR4 Position /
sahilmgandhi	18:6a4db94011d3	13318	#define EMAC_CAM0M_MACADDR4_Msk (0xfful << EMAC_CAM0M_MACADDR4_Pos) /!< EMAC CAM0M: MACADDR4 Mask /
sahilmgandhi	18:6a4db94011d3	13319
sahilmgandhi	18:6a4db94011d3	13320	#define EMAC_CAM0M_MACADDR5_Pos (24) /!< EMAC CAM0M: MACADDR5 Position /
sahilmgandhi	18:6a4db94011d3	13321	#define EMAC_CAM0M_MACADDR5_Msk (0xfful << EMAC_CAM0M_MACADDR5_Pos) /!< EMAC CAM0M: MACADDR5 Mask /
sahilmgandhi	18:6a4db94011d3	13322
sahilmgandhi	18:6a4db94011d3	13323	#define EMAC_CAM0L_Rserved_Pos (0) /!< EMAC CAM0L: Rserved Position /
sahilmgandhi	18:6a4db94011d3	13324	#define EMAC_CAM0L_Rserved_Msk (0xfffful << EMAC_CAM0L_Rserved_Pos) /!< EMAC CAM0L: Rserved Mask /
sahilmgandhi	18:6a4db94011d3	13325
sahilmgandhi	18:6a4db94011d3	13326	#define EMAC_CAM0L_MACADDR0_Pos (16) /!< EMAC CAM0L: MACADDR0 Position /
sahilmgandhi	18:6a4db94011d3	13327	#define EMAC_CAM0L_MACADDR0_Msk (0xfful << EMAC_CAM0L_MACADDR0_Pos) /!< EMAC CAM0L: MACADDR0 Mask /
sahilmgandhi	18:6a4db94011d3	13328
sahilmgandhi	18:6a4db94011d3	13329	#define EMAC_CAM0L_MACADDR1_Pos (24) /!< EMAC CAM0L: MACADDR1 Position /
sahilmgandhi	18:6a4db94011d3	13330	#define EMAC_CAM0L_MACADDR1_Msk (0xfful << EMAC_CAM0L_MACADDR1_Pos) /!< EMAC CAM0L: MACADDR1 Mask /
sahilmgandhi	18:6a4db94011d3	13331
sahilmgandhi	18:6a4db94011d3	13332	#define EMAC_CAM1M_MACADDR2_Pos (0) /!< EMAC CAM1M: MACADDR2 Position /
sahilmgandhi	18:6a4db94011d3	13333	#define EMAC_CAM1M_MACADDR2_Msk (0xfful << EMAC_CAM1M_MACADDR2_Pos) /!< EMAC CAM1M: MACADDR2 Mask /
sahilmgandhi	18:6a4db94011d3	13334
sahilmgandhi	18:6a4db94011d3	13335	#define EMAC_CAM1M_MACADDR3_Pos (8) /!< EMAC CAM1M: MACADDR3 Position /
sahilmgandhi	18:6a4db94011d3	13336	#define EMAC_CAM1M_MACADDR3_Msk (0xfful << EMAC_CAM1M_MACADDR3_Pos) /!< EMAC CAM1M: MACADDR3 Mask /
sahilmgandhi	18:6a4db94011d3	13337
sahilmgandhi	18:6a4db94011d3	13338	#define EMAC_CAM1M_MACADDR4_Pos (16) /!< EMAC CAM1M: MACADDR4 Position /
sahilmgandhi	18:6a4db94011d3	13339	#define EMAC_CAM1M_MACADDR4_Msk (0xfful << EMAC_CAM1M_MACADDR4_Pos) /!< EMAC CAM1M: MACADDR4 Mask /
sahilmgandhi	18:6a4db94011d3	13340
sahilmgandhi	18:6a4db94011d3	13341	#define EMAC_CAM1M_MACADDR5_Pos (24) /!< EMAC CAM1M: MACADDR5 Position /
sahilmgandhi	18:6a4db94011d3	13342	#define EMAC_CAM1M_MACADDR5_Msk (0xfful << EMAC_CAM1M_MACADDR5_Pos) /!< EMAC CAM1M: MACADDR5 Mask /
sahilmgandhi	18:6a4db94011d3	13343
sahilmgandhi	18:6a4db94011d3	13344	#define EMAC_CAM1L_Rserved_Pos (0) /!< EMAC CAM1L: Rserved Position /
sahilmgandhi	18:6a4db94011d3	13345	#define EMAC_CAM1L_Rserved_Msk (0xfffful << EMAC_CAM1L_Rserved_Pos) /!< EMAC CAM1L: Rserved Mask /
sahilmgandhi	18:6a4db94011d3	13346
sahilmgandhi	18:6a4db94011d3	13347	#define EMAC_CAM1L_MACADDR0_Pos (16) /!< EMAC CAM1L: MACADDR0 Position /
sahilmgandhi	18:6a4db94011d3	13348	#define EMAC_CAM1L_MACADDR0_Msk (0xfful << EMAC_CAM1L_MACADDR0_Pos) /!< EMAC CAM1L: MACADDR0 Mask /
sahilmgandhi	18:6a4db94011d3	13349
sahilmgandhi	18:6a4db94011d3	13350	#define EMAC_CAM1L_MACADDR1_Pos (24) /!< EMAC CAM1L: MACADDR1 Position /
sahilmgandhi	18:6a4db94011d3	13351	#define EMAC_CAM1L_MACADDR1_Msk (0xfful << EMAC_CAM1L_MACADDR1_Pos) /!< EMAC CAM1L: MACADDR1 Mask /
sahilmgandhi	18:6a4db94011d3	13352
sahilmgandhi	18:6a4db94011d3	13353	#define EMAC_CAM2M_MACADDR2_Pos (0) /!< EMAC CAM2M: MACADDR2 Position /
sahilmgandhi	18:6a4db94011d3	13354	#define EMAC_CAM2M_MACADDR2_Msk (0xfful << EMAC_CAM2M_MACADDR2_Pos) /!< EMAC CAM2M: MACADDR2 Mask /
sahilmgandhi	18:6a4db94011d3	13355
sahilmgandhi	18:6a4db94011d3	13356	#define EMAC_CAM2M_MACADDR3_Pos (8) /!< EMAC CAM2M: MACADDR3 Position /
sahilmgandhi	18:6a4db94011d3	13357	#define EMAC_CAM2M_MACADDR3_Msk (0xfful << EMAC_CAM2M_MACADDR3_Pos) /!< EMAC CAM2M: MACADDR3 Mask /
sahilmgandhi	18:6a4db94011d3	13358
sahilmgandhi	18:6a4db94011d3	13359	#define EMAC_CAM2M_MACADDR4_Pos (16) /!< EMAC CAM2M: MACADDR4 Position /
sahilmgandhi	18:6a4db94011d3	13360	#define EMAC_CAM2M_MACADDR4_Msk (0xfful << EMAC_CAM2M_MACADDR4_Pos) /!< EMAC CAM2M: MACADDR4 Mask /
sahilmgandhi	18:6a4db94011d3	13361
sahilmgandhi	18:6a4db94011d3	13362	#define EMAC_CAM2M_MACADDR5_Pos (24) /!< EMAC CAM2M: MACADDR5 Position /
sahilmgandhi	18:6a4db94011d3	13363	#define EMAC_CAM2M_MACADDR5_Msk (0xfful << EMAC_CAM2M_MACADDR5_Pos) /!< EMAC CAM2M: MACADDR5 Mask /
sahilmgandhi	18:6a4db94011d3	13364
sahilmgandhi	18:6a4db94011d3	13365	#define EMAC_CAM2L_Rserved_Pos (0) /!< EMAC CAM2L: Rserved Position /
sahilmgandhi	18:6a4db94011d3	13366	#define EMAC_CAM2L_Rserved_Msk (0xfffful << EMAC_CAM2L_Rserved_Pos) /!< EMAC CAM2L: Rserved Mask /
sahilmgandhi	18:6a4db94011d3	13367
sahilmgandhi	18:6a4db94011d3	13368	#define EMAC_CAM2L_MACADDR0_Pos (16) /!< EMAC CAM2L: MACADDR0 Position /
sahilmgandhi	18:6a4db94011d3	13369	#define EMAC_CAM2L_MACADDR0_Msk (0xfful << EMAC_CAM2L_MACADDR0_Pos) /!< EMAC CAM2L: MACADDR0 Mask /
sahilmgandhi	18:6a4db94011d3	13370
sahilmgandhi	18:6a4db94011d3	13371	#define EMAC_CAM2L_MACADDR1_Pos (24) /!< EMAC CAM2L: MACADDR1 Position /
sahilmgandhi	18:6a4db94011d3	13372	#define EMAC_CAM2L_MACADDR1_Msk (0xfful << EMAC_CAM2L_MACADDR1_Pos) /!< EMAC CAM2L: MACADDR1 Mask /
sahilmgandhi	18:6a4db94011d3	13373
sahilmgandhi	18:6a4db94011d3	13374	#define EMAC_CAM3M_MACADDR2_Pos (0) /!< EMAC CAM3M: MACADDR2 Position /
sahilmgandhi	18:6a4db94011d3	13375	#define EMAC_CAM3M_MACADDR2_Msk (0xfful << EMAC_CAM3M_MACADDR2_Pos) /!< EMAC CAM3M: MACADDR2 Mask /
sahilmgandhi	18:6a4db94011d3	13376
sahilmgandhi	18:6a4db94011d3	13377	#define EMAC_CAM3M_MACADDR3_Pos (8) /!< EMAC CAM3M: MACADDR3 Position /
sahilmgandhi	18:6a4db94011d3	13378	#define EMAC_CAM3M_MACADDR3_Msk (0xfful << EMAC_CAM3M_MACADDR3_Pos) /!< EMAC CAM3M: MACADDR3 Mask /
sahilmgandhi	18:6a4db94011d3	13379
sahilmgandhi	18:6a4db94011d3	13380	#define EMAC_CAM3M_MACADDR4_Pos (16) /!< EMAC CAM3M: MACADDR4 Position /
sahilmgandhi	18:6a4db94011d3	13381	#define EMAC_CAM3M_MACADDR4_Msk (0xfful << EMAC_CAM3M_MACADDR4_Pos) /!< EMAC CAM3M: MACADDR4 Mask /
sahilmgandhi	18:6a4db94011d3	13382
sahilmgandhi	18:6a4db94011d3	13383	#define EMAC_CAM3M_MACADDR5_Pos (24) /!< EMAC CAM3M: MACADDR5 Position /
sahilmgandhi	18:6a4db94011d3	13384	#define EMAC_CAM3M_MACADDR5_Msk (0xfful << EMAC_CAM3M_MACADDR5_Pos) /!< EMAC CAM3M: MACADDR5 Mask /
sahilmgandhi	18:6a4db94011d3	13385
sahilmgandhi	18:6a4db94011d3	13386	#define EMAC_CAM3L_Rserved_Pos (0) /!< EMAC CAM3L: Rserved Position /
sahilmgandhi	18:6a4db94011d3	13387	#define EMAC_CAM3L_Rserved_Msk (0xfffful << EMAC_CAM3L_Rserved_Pos) /!< EMAC CAM3L: Rserved Mask /
sahilmgandhi	18:6a4db94011d3	13388
sahilmgandhi	18:6a4db94011d3	13389	#define EMAC_CAM3L_MACADDR0_Pos (16) /!< EMAC CAM3L: MACADDR0 Position /
sahilmgandhi	18:6a4db94011d3	13390	#define EMAC_CAM3L_MACADDR0_Msk (0xfful << EMAC_CAM3L_MACADDR0_Pos) /!< EMAC CAM3L: MACADDR0 Mask /
sahilmgandhi	18:6a4db94011d3	13391
sahilmgandhi	18:6a4db94011d3	13392	#define EMAC_CAM3L_MACADDR1_Pos (24) /!< EMAC CAM3L: MACADDR1 Position /
sahilmgandhi	18:6a4db94011d3	13393	#define EMAC_CAM3L_MACADDR1_Msk (0xfful << EMAC_CAM3L_MACADDR1_Pos) /!< EMAC CAM3L: MACADDR1 Mask /
sahilmgandhi	18:6a4db94011d3	13394
sahilmgandhi	18:6a4db94011d3	13395	#define EMAC_CAM4M_MACADDR2_Pos (0) /!< EMAC CAM4M: MACADDR2 Position /
sahilmgandhi	18:6a4db94011d3	13396	#define EMAC_CAM4M_MACADDR2_Msk (0xfful << EMAC_CAM4M_MACADDR2_Pos) /!< EMAC CAM4M: MACADDR2 Mask /
sahilmgandhi	18:6a4db94011d3	13397
sahilmgandhi	18:6a4db94011d3	13398	#define EMAC_CAM4M_MACADDR3_Pos (8) /!< EMAC CAM4M: MACADDR3 Position /
sahilmgandhi	18:6a4db94011d3	13399	#define EMAC_CAM4M_MACADDR3_Msk (0xfful << EMAC_CAM4M_MACADDR3_Pos) /!< EMAC CAM4M: MACADDR3 Mask /
sahilmgandhi	18:6a4db94011d3	13400
sahilmgandhi	18:6a4db94011d3	13401	#define EMAC_CAM4M_MACADDR4_Pos (16) /!< EMAC CAM4M: MACADDR4 Position /
sahilmgandhi	18:6a4db94011d3	13402	#define EMAC_CAM4M_MACADDR4_Msk (0xfful << EMAC_CAM4M_MACADDR4_Pos) /!< EMAC CAM4M: MACADDR4 Mask /
sahilmgandhi	18:6a4db94011d3	13403
sahilmgandhi	18:6a4db94011d3	13404	#define EMAC_CAM4M_MACADDR5_Pos (24) /!< EMAC CAM4M: MACADDR5 Position /
sahilmgandhi	18:6a4db94011d3	13405	#define EMAC_CAM4M_MACADDR5_Msk (0xfful << EMAC_CAM4M_MACADDR5_Pos) /!< EMAC CAM4M: MACADDR5 Mask /
sahilmgandhi	18:6a4db94011d3	13406
sahilmgandhi	18:6a4db94011d3	13407	#define EMAC_CAM4L_Rserved_Pos (0) /!< EMAC CAM4L: Rserved Position /
sahilmgandhi	18:6a4db94011d3	13408	#define EMAC_CAM4L_Rserved_Msk (0xfffful << EMAC_CAM4L_Rserved_Pos) /!< EMAC CAM4L: Rserved Mask /
sahilmgandhi	18:6a4db94011d3	13409
sahilmgandhi	18:6a4db94011d3	13410	#define EMAC_CAM4L_MACADDR0_Pos (16) /!< EMAC CAM4L: MACADDR0 Position /
sahilmgandhi	18:6a4db94011d3	13411	#define EMAC_CAM4L_MACADDR0_Msk (0xfful << EMAC_CAM4L_MACADDR0_Pos) /!< EMAC CAM4L: MACADDR0 Mask /
sahilmgandhi	18:6a4db94011d3	13412
sahilmgandhi	18:6a4db94011d3	13413	#define EMAC_CAM4L_MACADDR1_Pos (24) /!< EMAC CAM4L: MACADDR1 Position /
sahilmgandhi	18:6a4db94011d3	13414	#define EMAC_CAM4L_MACADDR1_Msk (0xfful << EMAC_CAM4L_MACADDR1_Pos) /!< EMAC CAM4L: MACADDR1 Mask /
sahilmgandhi	18:6a4db94011d3	13415
sahilmgandhi	18:6a4db94011d3	13416	#define EMAC_CAM5M_MACADDR2_Pos (0) /!< EMAC CAM5M: MACADDR2 Position /
sahilmgandhi	18:6a4db94011d3	13417	#define EMAC_CAM5M_MACADDR2_Msk (0xfful << EMAC_CAM5M_MACADDR2_Pos) /!< EMAC CAM5M: MACADDR2 Mask /
sahilmgandhi	18:6a4db94011d3	13418
sahilmgandhi	18:6a4db94011d3	13419	#define EMAC_CAM5M_MACADDR3_Pos (8) /!< EMAC CAM5M: MACADDR3 Position /
sahilmgandhi	18:6a4db94011d3	13420	#define EMAC_CAM5M_MACADDR3_Msk (0xfful << EMAC_CAM5M_MACADDR3_Pos) /!< EMAC CAM5M: MACADDR3 Mask /
sahilmgandhi	18:6a4db94011d3	13421
sahilmgandhi	18:6a4db94011d3	13422	#define EMAC_CAM5M_MACADDR4_Pos (16) /!< EMAC CAM5M: MACADDR4 Position /
sahilmgandhi	18:6a4db94011d3	13423	#define EMAC_CAM5M_MACADDR4_Msk (0xfful << EMAC_CAM5M_MACADDR4_Pos) /!< EMAC CAM5M: MACADDR4 Mask /
sahilmgandhi	18:6a4db94011d3	13424
sahilmgandhi	18:6a4db94011d3	13425	#define EMAC_CAM5M_MACADDR5_Pos (24) /!< EMAC CAM5M: MACADDR5 Position /
sahilmgandhi	18:6a4db94011d3	13426	#define EMAC_CAM5M_MACADDR5_Msk (0xfful << EMAC_CAM5M_MACADDR5_Pos) /!< EMAC CAM5M: MACADDR5 Mask /
sahilmgandhi	18:6a4db94011d3	13427
sahilmgandhi	18:6a4db94011d3	13428	#define EMAC_CAM5L_Rserved_Pos (0) /!< EMAC CAM5L: Rserved Position /
sahilmgandhi	18:6a4db94011d3	13429	#define EMAC_CAM5L_Rserved_Msk (0xfffful << EMAC_CAM5L_Rserved_Pos) /!< EMAC CAM5L: Rserved Mask /
sahilmgandhi	18:6a4db94011d3	13430
sahilmgandhi	18:6a4db94011d3	13431	#define EMAC_CAM5L_MACADDR0_Pos (16) /!< EMAC CAM5L: MACADDR0 Position /
sahilmgandhi	18:6a4db94011d3	13432	#define EMAC_CAM5L_MACADDR0_Msk (0xfful << EMAC_CAM5L_MACADDR0_Pos) /!< EMAC CAM5L: MACADDR0 Mask /
sahilmgandhi	18:6a4db94011d3	13433
sahilmgandhi	18:6a4db94011d3	13434	#define EMAC_CAM5L_MACADDR1_Pos (24) /!< EMAC CAM5L: MACADDR1 Position /
sahilmgandhi	18:6a4db94011d3	13435	#define EMAC_CAM5L_MACADDR1_Msk (0xfful << EMAC_CAM5L_MACADDR1_Pos) /!< EMAC CAM5L: MACADDR1 Mask /
sahilmgandhi	18:6a4db94011d3	13436
sahilmgandhi	18:6a4db94011d3	13437	#define EMAC_CAM6M_MACADDR2_Pos (0) /!< EMAC CAM6M: MACADDR2 Position /
sahilmgandhi	18:6a4db94011d3	13438	#define EMAC_CAM6M_MACADDR2_Msk (0xfful << EMAC_CAM6M_MACADDR2_Pos) /!< EMAC CAM6M: MACADDR2 Mask /
sahilmgandhi	18:6a4db94011d3	13439
sahilmgandhi	18:6a4db94011d3	13440	#define EMAC_CAM6M_MACADDR3_Pos (8) /!< EMAC CAM6M: MACADDR3 Position /
sahilmgandhi	18:6a4db94011d3	13441	#define EMAC_CAM6M_MACADDR3_Msk (0xfful << EMAC_CAM6M_MACADDR3_Pos) /!< EMAC CAM6M: MACADDR3 Mask /
sahilmgandhi	18:6a4db94011d3	13442
sahilmgandhi	18:6a4db94011d3	13443	#define EMAC_CAM6M_MACADDR4_Pos (16) /!< EMAC CAM6M: MACADDR4 Position /
sahilmgandhi	18:6a4db94011d3	13444	#define EMAC_CAM6M_MACADDR4_Msk (0xfful << EMAC_CAM6M_MACADDR4_Pos) /!< EMAC CAM6M: MACADDR4 Mask /
sahilmgandhi	18:6a4db94011d3	13445
sahilmgandhi	18:6a4db94011d3	13446	#define EMAC_CAM6M_MACADDR5_Pos (24) /!< EMAC CAM6M: MACADDR5 Position /
sahilmgandhi	18:6a4db94011d3	13447	#define EMAC_CAM6M_MACADDR5_Msk (0xfful << EMAC_CAM6M_MACADDR5_Pos) /!< EMAC CAM6M: MACADDR5 Mask /
sahilmgandhi	18:6a4db94011d3	13448
sahilmgandhi	18:6a4db94011d3	13449	#define EMAC_CAM6L_Rserved_Pos (0) /!< EMAC CAM6L: Rserved Position /
sahilmgandhi	18:6a4db94011d3	13450	#define EMAC_CAM6L_Rserved_Msk (0xfffful << EMAC_CAM6L_Rserved_Pos) /!< EMAC CAM6L: Rserved Mask /
sahilmgandhi	18:6a4db94011d3	13451
sahilmgandhi	18:6a4db94011d3	13452	#define EMAC_CAM6L_MACADDR0_Pos (16) /!< EMAC CAM6L: MACADDR0 Position /
sahilmgandhi	18:6a4db94011d3	13453	#define EMAC_CAM6L_MACADDR0_Msk (0xfful << EMAC_CAM6L_MACADDR0_Pos) /!< EMAC CAM6L: MACADDR0 Mask /
sahilmgandhi	18:6a4db94011d3	13454
sahilmgandhi	18:6a4db94011d3	13455	#define EMAC_CAM6L_MACADDR1_Pos (24) /!< EMAC CAM6L: MACADDR1 Position /
sahilmgandhi	18:6a4db94011d3	13456	#define EMAC_CAM6L_MACADDR1_Msk (0xfful << EMAC_CAM6L_MACADDR1_Pos) /!< EMAC CAM6L: MACADDR1 Mask /
sahilmgandhi	18:6a4db94011d3	13457
sahilmgandhi	18:6a4db94011d3	13458	#define EMAC_CAM7M_MACADDR2_Pos (0) /!< EMAC CAM7M: MACADDR2 Position /
sahilmgandhi	18:6a4db94011d3	13459	#define EMAC_CAM7M_MACADDR2_Msk (0xfful << EMAC_CAM7M_MACADDR2_Pos) /!< EMAC CAM7M: MACADDR2 Mask /
sahilmgandhi	18:6a4db94011d3	13460
sahilmgandhi	18:6a4db94011d3	13461	#define EMAC_CAM7M_MACADDR3_Pos (8) /!< EMAC CAM7M: MACADDR3 Position /
sahilmgandhi	18:6a4db94011d3	13462	#define EMAC_CAM7M_MACADDR3_Msk (0xfful << EMAC_CAM7M_MACADDR3_Pos) /!< EMAC CAM7M: MACADDR3 Mask /
sahilmgandhi	18:6a4db94011d3	13463
sahilmgandhi	18:6a4db94011d3	13464	#define EMAC_CAM7M_MACADDR4_Pos (16) /!< EMAC CAM7M: MACADDR4 Position /
sahilmgandhi	18:6a4db94011d3	13465	#define EMAC_CAM7M_MACADDR4_Msk (0xfful << EMAC_CAM7M_MACADDR4_Pos) /!< EMAC CAM7M: MACADDR4 Mask /
sahilmgandhi	18:6a4db94011d3	13466
sahilmgandhi	18:6a4db94011d3	13467	#define EMAC_CAM7M_MACADDR5_Pos (24) /!< EMAC CAM7M: MACADDR5 Position /
sahilmgandhi	18:6a4db94011d3	13468	#define EMAC_CAM7M_MACADDR5_Msk (0xfful << EMAC_CAM7M_MACADDR5_Pos) /!< EMAC CAM7M: MACADDR5 Mask /
sahilmgandhi	18:6a4db94011d3	13469
sahilmgandhi	18:6a4db94011d3	13470	#define EMAC_CAM7L_Rserved_Pos (0) /!< EMAC CAM7L: Rserved Position /
sahilmgandhi	18:6a4db94011d3	13471	#define EMAC_CAM7L_Rserved_Msk (0xfffful << EMAC_CAM7L_Rserved_Pos) /!< EMAC CAM7L: Rserved Mask /
sahilmgandhi	18:6a4db94011d3	13472
sahilmgandhi	18:6a4db94011d3	13473	#define EMAC_CAM7L_MACADDR0_Pos (16) /!< EMAC CAM7L: MACADDR0 Position /
sahilmgandhi	18:6a4db94011d3	13474	#define EMAC_CAM7L_MACADDR0_Msk (0xfful << EMAC_CAM7L_MACADDR0_Pos) /!< EMAC CAM7L: MACADDR0 Mask /
sahilmgandhi	18:6a4db94011d3	13475
sahilmgandhi	18:6a4db94011d3	13476	#define EMAC_CAM7L_MACADDR1_Pos (24) /!< EMAC CAM7L: MACADDR1 Position /
sahilmgandhi	18:6a4db94011d3	13477	#define EMAC_CAM7L_MACADDR1_Msk (0xfful << EMAC_CAM7L_MACADDR1_Pos) /!< EMAC CAM7L: MACADDR1 Mask /
sahilmgandhi	18:6a4db94011d3	13478
sahilmgandhi	18:6a4db94011d3	13479	#define EMAC_CAM8M_MACADDR2_Pos (0) /!< EMAC CAM8M: MACADDR2 Position /
sahilmgandhi	18:6a4db94011d3	13480	#define EMAC_CAM8M_MACADDR2_Msk (0xfful << EMAC_CAM8M_MACADDR2_Pos) /!< EMAC CAM8M: MACADDR2 Mask /
sahilmgandhi	18:6a4db94011d3	13481
sahilmgandhi	18:6a4db94011d3	13482	#define EMAC_CAM8M_MACADDR3_Pos (8) /!< EMAC CAM8M: MACADDR3 Position /
sahilmgandhi	18:6a4db94011d3	13483	#define EMAC_CAM8M_MACADDR3_Msk (0xfful << EMAC_CAM8M_MACADDR3_Pos) /!< EMAC CAM8M: MACADDR3 Mask /
sahilmgandhi	18:6a4db94011d3	13484
sahilmgandhi	18:6a4db94011d3	13485	#define EMAC_CAM8M_MACADDR4_Pos (16) /!< EMAC CAM8M: MACADDR4 Position /
sahilmgandhi	18:6a4db94011d3	13486	#define EMAC_CAM8M_MACADDR4_Msk (0xfful << EMAC_CAM8M_MACADDR4_Pos) /!< EMAC CAM8M: MACADDR4 Mask /
sahilmgandhi	18:6a4db94011d3	13487
sahilmgandhi	18:6a4db94011d3	13488	#define EMAC_CAM8M_MACADDR5_Pos (24) /!< EMAC CAM8M: MACADDR5 Position /
sahilmgandhi	18:6a4db94011d3	13489	#define EMAC_CAM8M_MACADDR5_Msk (0xfful << EMAC_CAM8M_MACADDR5_Pos) /!< EMAC CAM8M: MACADDR5 Mask /
sahilmgandhi	18:6a4db94011d3	13490
sahilmgandhi	18:6a4db94011d3	13491	#define EMAC_CAM8L_Rserved_Pos (0) /!< EMAC CAM8L: Rserved Position /
sahilmgandhi	18:6a4db94011d3	13492	#define EMAC_CAM8L_Rserved_Msk (0xfffful << EMAC_CAM8L_Rserved_Pos) /!< EMAC CAM8L: Rserved Mask /
sahilmgandhi	18:6a4db94011d3	13493
sahilmgandhi	18:6a4db94011d3	13494	#define EMAC_CAM8L_MACADDR0_Pos (16) /!< EMAC CAM8L: MACADDR0 Position /
sahilmgandhi	18:6a4db94011d3	13495	#define EMAC_CAM8L_MACADDR0_Msk (0xfful << EMAC_CAM8L_MACADDR0_Pos) /!< EMAC CAM8L: MACADDR0 Mask /
sahilmgandhi	18:6a4db94011d3	13496
sahilmgandhi	18:6a4db94011d3	13497	#define EMAC_CAM8L_MACADDR1_Pos (24) /!< EMAC CAM8L: MACADDR1 Position /
sahilmgandhi	18:6a4db94011d3	13498	#define EMAC_CAM8L_MACADDR1_Msk (0xfful << EMAC_CAM8L_MACADDR1_Pos) /!< EMAC CAM8L: MACADDR1 Mask /
sahilmgandhi	18:6a4db94011d3	13499
sahilmgandhi	18:6a4db94011d3	13500	#define EMAC_CAM9M_MACADDR2_Pos (0) /!< EMAC CAM9M: MACADDR2 Position /
sahilmgandhi	18:6a4db94011d3	13501	#define EMAC_CAM9M_MACADDR2_Msk (0xfful << EMAC_CAM9M_MACADDR2_Pos) /!< EMAC CAM9M: MACADDR2 Mask /
sahilmgandhi	18:6a4db94011d3	13502
sahilmgandhi	18:6a4db94011d3	13503	#define EMAC_CAM9M_MACADDR3_Pos (8) /!< EMAC CAM9M: MACADDR3 Position /
sahilmgandhi	18:6a4db94011d3	13504	#define EMAC_CAM9M_MACADDR3_Msk (0xfful << EMAC_CAM9M_MACADDR3_Pos) /!< EMAC CAM9M: MACADDR3 Mask /
sahilmgandhi	18:6a4db94011d3	13505
sahilmgandhi	18:6a4db94011d3	13506	#define EMAC_CAM9M_MACADDR4_Pos (16) /!< EMAC CAM9M: MACADDR4 Position /
sahilmgandhi	18:6a4db94011d3	13507	#define EMAC_CAM9M_MACADDR4_Msk (0xfful << EMAC_CAM9M_MACADDR4_Pos) /!< EMAC CAM9M: MACADDR4 Mask /
sahilmgandhi	18:6a4db94011d3	13508
sahilmgandhi	18:6a4db94011d3	13509	#define EMAC_CAM9M_MACADDR5_Pos (24) /!< EMAC CAM9M: MACADDR5 Position /
sahilmgandhi	18:6a4db94011d3	13510	#define EMAC_CAM9M_MACADDR5_Msk (0xfful << EMAC_CAM9M_MACADDR5_Pos) /!< EMAC CAM9M: MACADDR5 Mask /
sahilmgandhi	18:6a4db94011d3	13511
sahilmgandhi	18:6a4db94011d3	13512	#define EMAC_CAM9L_Rserved_Pos (0) /!< EMAC CAM9L: Rserved Position /
sahilmgandhi	18:6a4db94011d3	13513	#define EMAC_CAM9L_Rserved_Msk (0xfffful << EMAC_CAM9L_Rserved_Pos) /!< EMAC CAM9L: Rserved Mask /
sahilmgandhi	18:6a4db94011d3	13514
sahilmgandhi	18:6a4db94011d3	13515	#define EMAC_CAM9L_MACADDR0_Pos (16) /!< EMAC CAM9L: MACADDR0 Position /
sahilmgandhi	18:6a4db94011d3	13516	#define EMAC_CAM9L_MACADDR0_Msk (0xfful << EMAC_CAM9L_MACADDR0_Pos) /!< EMAC CAM9L: MACADDR0 Mask /
sahilmgandhi	18:6a4db94011d3	13517
sahilmgandhi	18:6a4db94011d3	13518	#define EMAC_CAM9L_MACADDR1_Pos (24) /!< EMAC CAM9L: MACADDR1 Position /
sahilmgandhi	18:6a4db94011d3	13519	#define EMAC_CAM9L_MACADDR1_Msk (0xfful << EMAC_CAM9L_MACADDR1_Pos) /!< EMAC CAM9L: MACADDR1 Mask /
sahilmgandhi	18:6a4db94011d3	13520
sahilmgandhi	18:6a4db94011d3	13521	#define EMAC_CAM10M_MACADDR2_Pos (0) /!< EMAC CAM10M: MACADDR2 Position /
sahilmgandhi	18:6a4db94011d3	13522	#define EMAC_CAM10M_MACADDR2_Msk (0xfful << EMAC_CAM10M_MACADDR2_Pos) /!< EMAC CAM10M: MACADDR2 Mask /
sahilmgandhi	18:6a4db94011d3	13523
sahilmgandhi	18:6a4db94011d3	13524	#define EMAC_CAM10M_MACADDR3_Pos (8) /!< EMAC CAM10M: MACADDR3 Position /
sahilmgandhi	18:6a4db94011d3	13525	#define EMAC_CAM10M_MACADDR3_Msk (0xfful << EMAC_CAM10M_MACADDR3_Pos) /!< EMAC CAM10M: MACADDR3 Mask /
sahilmgandhi	18:6a4db94011d3	13526
sahilmgandhi	18:6a4db94011d3	13527	#define EMAC_CAM10M_MACADDR4_Pos (16) /!< EMAC CAM10M: MACADDR4 Position /
sahilmgandhi	18:6a4db94011d3	13528	#define EMAC_CAM10M_MACADDR4_Msk (0xfful << EMAC_CAM10M_MACADDR4_Pos) /!< EMAC CAM10M: MACADDR4 Mask /
sahilmgandhi	18:6a4db94011d3	13529
sahilmgandhi	18:6a4db94011d3	13530	#define EMAC_CAM10M_MACADDR5_Pos (24) /!< EMAC CAM10M: MACADDR5 Position /
sahilmgandhi	18:6a4db94011d3	13531	#define EMAC_CAM10M_MACADDR5_Msk (0xfful << EMAC_CAM10M_MACADDR5_Pos) /!< EMAC CAM10M: MACADDR5 Mask /
sahilmgandhi	18:6a4db94011d3	13532
sahilmgandhi	18:6a4db94011d3	13533	#define EMAC_CAM10L_Rserved_Pos (0) /!< EMAC CAM10L: Rserved Position /
sahilmgandhi	18:6a4db94011d3	13534	#define EMAC_CAM10L_Rserved_Msk (0xfffful << EMAC_CAM10L_Rserved_Pos) /!< EMAC CAM10L: Rserved Mask /
sahilmgandhi	18:6a4db94011d3	13535
sahilmgandhi	18:6a4db94011d3	13536	#define EMAC_CAM10L_MACADDR0_Pos (16) /!< EMAC CAM10L: MACADDR0 Position /
sahilmgandhi	18:6a4db94011d3	13537	#define EMAC_CAM10L_MACADDR0_Msk (0xfful << EMAC_CAM10L_MACADDR0_Pos) /!< EMAC CAM10L: MACADDR0 Mask /
sahilmgandhi	18:6a4db94011d3	13538
sahilmgandhi	18:6a4db94011d3	13539	#define EMAC_CAM10L_MACADDR1_Pos (24) /!< EMAC CAM10L: MACADDR1 Position /
sahilmgandhi	18:6a4db94011d3	13540	#define EMAC_CAM10L_MACADDR1_Msk (0xfful << EMAC_CAM10L_MACADDR1_Pos) /!< EMAC CAM10L: MACADDR1 Mask /
sahilmgandhi	18:6a4db94011d3	13541
sahilmgandhi	18:6a4db94011d3	13542	#define EMAC_CAM11M_MACADDR2_Pos (0) /!< EMAC CAM11M: MACADDR2 Position /
sahilmgandhi	18:6a4db94011d3	13543	#define EMAC_CAM11M_MACADDR2_Msk (0xfful << EMAC_CAM11M_MACADDR2_Pos) /!< EMAC CAM11M: MACADDR2 Mask /
sahilmgandhi	18:6a4db94011d3	13544
sahilmgandhi	18:6a4db94011d3	13545	#define EMAC_CAM11M_MACADDR3_Pos (8) /!< EMAC CAM11M: MACADDR3 Position /
sahilmgandhi	18:6a4db94011d3	13546	#define EMAC_CAM11M_MACADDR3_Msk (0xfful << EMAC_CAM11M_MACADDR3_Pos) /!< EMAC CAM11M: MACADDR3 Mask /
sahilmgandhi	18:6a4db94011d3	13547
sahilmgandhi	18:6a4db94011d3	13548	#define EMAC_CAM11M_MACADDR4_Pos (16) /!< EMAC CAM11M: MACADDR4 Position /
sahilmgandhi	18:6a4db94011d3	13549	#define EMAC_CAM11M_MACADDR4_Msk (0xfful << EMAC_CAM11M_MACADDR4_Pos) /!< EMAC CAM11M: MACADDR4 Mask /
sahilmgandhi	18:6a4db94011d3	13550
sahilmgandhi	18:6a4db94011d3	13551	#define EMAC_CAM11M_MACADDR5_Pos (24) /!< EMAC CAM11M: MACADDR5 Position /
sahilmgandhi	18:6a4db94011d3	13552	#define EMAC_CAM11M_MACADDR5_Msk (0xfful << EMAC_CAM11M_MACADDR5_Pos) /!< EMAC CAM11M: MACADDR5 Mask /
sahilmgandhi	18:6a4db94011d3	13553
sahilmgandhi	18:6a4db94011d3	13554	#define EMAC_CAM11L_Rserved_Pos (0) /!< EMAC CAM11L: Rserved Position /
sahilmgandhi	18:6a4db94011d3	13555	#define EMAC_CAM11L_Rserved_Msk (0xfffful << EMAC_CAM11L_Rserved_Pos) /!< EMAC CAM11L: Rserved Mask /
sahilmgandhi	18:6a4db94011d3	13556
sahilmgandhi	18:6a4db94011d3	13557	#define EMAC_CAM11L_MACADDR0_Pos (16) /!< EMAC CAM11L: MACADDR0 Position /
sahilmgandhi	18:6a4db94011d3	13558	#define EMAC_CAM11L_MACADDR0_Msk (0xfful << EMAC_CAM11L_MACADDR0_Pos) /!< EMAC CAM11L: MACADDR0 Mask /
sahilmgandhi	18:6a4db94011d3	13559
sahilmgandhi	18:6a4db94011d3	13560	#define EMAC_CAM11L_MACADDR1_Pos (24) /!< EMAC CAM11L: MACADDR1 Position /
sahilmgandhi	18:6a4db94011d3	13561	#define EMAC_CAM11L_MACADDR1_Msk (0xfful << EMAC_CAM11L_MACADDR1_Pos) /!< EMAC CAM11L: MACADDR1 Mask /
sahilmgandhi	18:6a4db94011d3	13562
sahilmgandhi	18:6a4db94011d3	13563	#define EMAC_CAM12M_MACADDR2_Pos (0) /!< EMAC CAM12M: MACADDR2 Position /
sahilmgandhi	18:6a4db94011d3	13564	#define EMAC_CAM12M_MACADDR2_Msk (0xfful << EMAC_CAM12M_MACADDR2_Pos) /!< EMAC CAM12M: MACADDR2 Mask /
sahilmgandhi	18:6a4db94011d3	13565
sahilmgandhi	18:6a4db94011d3	13566	#define EMAC_CAM12M_MACADDR3_Pos (8) /!< EMAC CAM12M: MACADDR3 Position /
sahilmgandhi	18:6a4db94011d3	13567	#define EMAC_CAM12M_MACADDR3_Msk (0xfful << EMAC_CAM12M_MACADDR3_Pos) /!< EMAC CAM12M: MACADDR3 Mask /
sahilmgandhi	18:6a4db94011d3	13568
sahilmgandhi	18:6a4db94011d3	13569	#define EMAC_CAM12M_MACADDR4_Pos (16) /!< EMAC CAM12M: MACADDR4 Position /
sahilmgandhi	18:6a4db94011d3	13570	#define EMAC_CAM12M_MACADDR4_Msk (0xfful << EMAC_CAM12M_MACADDR4_Pos) /!< EMAC CAM12M: MACADDR4 Mask /
sahilmgandhi	18:6a4db94011d3	13571
sahilmgandhi	18:6a4db94011d3	13572	#define EMAC_CAM12M_MACADDR5_Pos (24) /!< EMAC CAM12M: MACADDR5 Position /
sahilmgandhi	18:6a4db94011d3	13573	#define EMAC_CAM12M_MACADDR5_Msk (0xfful << EMAC_CAM12M_MACADDR5_Pos) /!< EMAC CAM12M: MACADDR5 Mask /
sahilmgandhi	18:6a4db94011d3	13574
sahilmgandhi	18:6a4db94011d3	13575	#define EMAC_CAM12L_Rserved_Pos (0) /!< EMAC CAM12L: Rserved Position /
sahilmgandhi	18:6a4db94011d3	13576	#define EMAC_CAM12L_Rserved_Msk (0xfffful << EMAC_CAM12L_Rserved_Pos) /!< EMAC CAM12L: Rserved Mask /
sahilmgandhi	18:6a4db94011d3	13577
sahilmgandhi	18:6a4db94011d3	13578	#define EMAC_CAM12L_MACADDR0_Pos (16) /!< EMAC CAM12L: MACADDR0 Position /
sahilmgandhi	18:6a4db94011d3	13579	#define EMAC_CAM12L_MACADDR0_Msk (0xfful << EMAC_CAM12L_MACADDR0_Pos) /!< EMAC CAM12L: MACADDR0 Mask /
sahilmgandhi	18:6a4db94011d3	13580
sahilmgandhi	18:6a4db94011d3	13581	#define EMAC_CAM12L_MACADDR1_Pos (24) /!< EMAC CAM12L: MACADDR1 Position /
sahilmgandhi	18:6a4db94011d3	13582	#define EMAC_CAM12L_MACADDR1_Msk (0xfful << EMAC_CAM12L_MACADDR1_Pos) /!< EMAC CAM12L: MACADDR1 Mask /
sahilmgandhi	18:6a4db94011d3	13583
sahilmgandhi	18:6a4db94011d3	13584	#define EMAC_CAM13M_MACADDR2_Pos (0) /!< EMAC CAM13M: MACADDR2 Position /
sahilmgandhi	18:6a4db94011d3	13585	#define EMAC_CAM13M_MACADDR2_Msk (0xfful << EMAC_CAM13M_MACADDR2_Pos) /!< EMAC CAM13M: MACADDR2 Mask /
sahilmgandhi	18:6a4db94011d3	13586
sahilmgandhi	18:6a4db94011d3	13587	#define EMAC_CAM13M_MACADDR3_Pos (8) /!< EMAC CAM13M: MACADDR3 Position /
sahilmgandhi	18:6a4db94011d3	13588	#define EMAC_CAM13M_MACADDR3_Msk (0xfful << EMAC_CAM13M_MACADDR3_Pos) /!< EMAC CAM13M: MACADDR3 Mask /
sahilmgandhi	18:6a4db94011d3	13589
sahilmgandhi	18:6a4db94011d3	13590	#define EMAC_CAM13M_MACADDR4_Pos (16) /!< EMAC CAM13M: MACADDR4 Position /
sahilmgandhi	18:6a4db94011d3	13591	#define EMAC_CAM13M_MACADDR4_Msk (0xfful << EMAC_CAM13M_MACADDR4_Pos) /!< EMAC CAM13M: MACADDR4 Mask /
sahilmgandhi	18:6a4db94011d3	13592
sahilmgandhi	18:6a4db94011d3	13593	#define EMAC_CAM13M_MACADDR5_Pos (24) /!< EMAC CAM13M: MACADDR5 Position /
sahilmgandhi	18:6a4db94011d3	13594	#define EMAC_CAM13M_MACADDR5_Msk (0xfful << EMAC_CAM13M_MACADDR5_Pos) /!< EMAC CAM13M: MACADDR5 Mask /
sahilmgandhi	18:6a4db94011d3	13595
sahilmgandhi	18:6a4db94011d3	13596	#define EMAC_CAM13L_Rserved_Pos (0) /!< EMAC CAM13L: Rserved Position /
sahilmgandhi	18:6a4db94011d3	13597	#define EMAC_CAM13L_Rserved_Msk (0xfffful << EMAC_CAM13L_Rserved_Pos) /!< EMAC CAM13L: Rserved Mask /
sahilmgandhi	18:6a4db94011d3	13598
sahilmgandhi	18:6a4db94011d3	13599	#define EMAC_CAM13L_MACADDR0_Pos (16) /!< EMAC CAM13L: MACADDR0 Position /
sahilmgandhi	18:6a4db94011d3	13600	#define EMAC_CAM13L_MACADDR0_Msk (0xfful << EMAC_CAM13L_MACADDR0_Pos) /!< EMAC CAM13L: MACADDR0 Mask /
sahilmgandhi	18:6a4db94011d3	13601
sahilmgandhi	18:6a4db94011d3	13602	#define EMAC_CAM13L_MACADDR1_Pos (24) /!< EMAC CAM13L: MACADDR1 Position /
sahilmgandhi	18:6a4db94011d3	13603	#define EMAC_CAM13L_MACADDR1_Msk (0xfful << EMAC_CAM13L_MACADDR1_Pos) /!< EMAC CAM13L: MACADDR1 Mask /
sahilmgandhi	18:6a4db94011d3	13604
sahilmgandhi	18:6a4db94011d3	13605	#define EMAC_CAM14M_MACADDR2_Pos (0) /!< EMAC CAM14M: MACADDR2 Position /
sahilmgandhi	18:6a4db94011d3	13606	#define EMAC_CAM14M_MACADDR2_Msk (0xfful << EMAC_CAM14M_MACADDR2_Pos) /!< EMAC CAM14M: MACADDR2 Mask /
sahilmgandhi	18:6a4db94011d3	13607
sahilmgandhi	18:6a4db94011d3	13608	#define EMAC_CAM14M_MACADDR3_Pos (8) /!< EMAC CAM14M: MACADDR3 Position /
sahilmgandhi	18:6a4db94011d3	13609	#define EMAC_CAM14M_MACADDR3_Msk (0xfful << EMAC_CAM14M_MACADDR3_Pos) /!< EMAC CAM14M: MACADDR3 Mask /
sahilmgandhi	18:6a4db94011d3	13610
sahilmgandhi	18:6a4db94011d3	13611	#define EMAC_CAM14M_MACADDR4_Pos (16) /!< EMAC CAM14M: MACADDR4 Position /
sahilmgandhi	18:6a4db94011d3	13612	#define EMAC_CAM14M_MACADDR4_Msk (0xfful << EMAC_CAM14M_MACADDR4_Pos) /!< EMAC CAM14M: MACADDR4 Mask /
sahilmgandhi	18:6a4db94011d3	13613
sahilmgandhi	18:6a4db94011d3	13614	#define EMAC_CAM14M_MACADDR5_Pos (24) /!< EMAC CAM14M: MACADDR5 Position /
sahilmgandhi	18:6a4db94011d3	13615	#define EMAC_CAM14M_MACADDR5_Msk (0xfful << EMAC_CAM14M_MACADDR5_Pos) /!< EMAC CAM14M: MACADDR5 Mask /
sahilmgandhi	18:6a4db94011d3	13616
sahilmgandhi	18:6a4db94011d3	13617	#define EMAC_CAM14L_Rserved_Pos (0) /!< EMAC CAM14L: Rserved Position /
sahilmgandhi	18:6a4db94011d3	13618	#define EMAC_CAM14L_Rserved_Msk (0xfffful << EMAC_CAM14L_Rserved_Pos) /!< EMAC CAM14L: Rserved Mask /
sahilmgandhi	18:6a4db94011d3	13619
sahilmgandhi	18:6a4db94011d3	13620	#define EMAC_CAM14L_MACADDR0_Pos (16) /!< EMAC CAM14L: MACADDR0 Position /
sahilmgandhi	18:6a4db94011d3	13621	#define EMAC_CAM14L_MACADDR0_Msk (0xfful << EMAC_CAM14L_MACADDR0_Pos) /!< EMAC CAM14L: MACADDR0 Mask /
sahilmgandhi	18:6a4db94011d3	13622
sahilmgandhi	18:6a4db94011d3	13623	#define EMAC_CAM14L_MACADDR1_Pos (24) /!< EMAC CAM14L: MACADDR1 Position /
sahilmgandhi	18:6a4db94011d3	13624	#define EMAC_CAM14L_MACADDR1_Msk (0xfful << EMAC_CAM14L_MACADDR1_Pos) /!< EMAC CAM14L: MACADDR1 Mask /
sahilmgandhi	18:6a4db94011d3	13625
sahilmgandhi	18:6a4db94011d3	13626	#define EMAC_CAM15MSB_OPCODE_Pos (0) /!< EMAC CAM15MSB: OPCODE Position /
sahilmgandhi	18:6a4db94011d3	13627	#define EMAC_CAM15MSB_OPCODE_Msk (0xfffful << EMAC_CAM15MSB_OPCODE_Pos) /!< EMAC CAM15MSB: OPCODE Mask /
sahilmgandhi	18:6a4db94011d3	13628
sahilmgandhi	18:6a4db94011d3	13629	#define EMAC_CAM15MSB_LENGTH_Pos (16) /!< EMAC CAM15MSB: LENGTH Position /
sahilmgandhi	18:6a4db94011d3	13630	#define EMAC_CAM15MSB_LENGTH_Msk (0xfffful << EMAC_CAM15MSB_LENGTH_Pos) /!< EMAC CAM15MSB: LENGTH Mask /
sahilmgandhi	18:6a4db94011d3	13631
sahilmgandhi	18:6a4db94011d3	13632	#define EMAC_CAM15LSB_OPERAND_Pos (24) /!< EMAC CAM15LSB: OPERAND Position /
sahilmgandhi	18:6a4db94011d3	13633	#define EMAC_CAM15LSB_OPERAND_Msk (0xfful << EMAC_CAM15LSB_OPERAND_Pos) /!< EMAC CAM15LSB: OPERAND Mask /
sahilmgandhi	18:6a4db94011d3	13634
sahilmgandhi	18:6a4db94011d3	13635	#define EMAC_TXDSA_TXDSA_Pos (0) /!< EMAC TXDSA: TXDSA Position /
sahilmgandhi	18:6a4db94011d3	13636	#define EMAC_TXDSA_TXDSA_Msk (0xfffffffful << EMAC_TXDSA_TXDSA_Pos) /!< EMAC TXDSA: TXDSA Mask /
sahilmgandhi	18:6a4db94011d3	13637
sahilmgandhi	18:6a4db94011d3	13638	#define EMAC_RXDSA_RXDSA_Pos (0) /!< EMAC RXDSA: RXDSA Position /
sahilmgandhi	18:6a4db94011d3	13639	#define EMAC_RXDSA_RXDSA_Msk (0xfffffffful << EMAC_RXDSA_RXDSA_Pos) /!< EMAC RXDSA: RXDSA Mask /
sahilmgandhi	18:6a4db94011d3	13640
sahilmgandhi	18:6a4db94011d3	13641	#define EMAC_CTL_RXON_Pos (0) /!< EMAC CTL: RXON Position /
sahilmgandhi	18:6a4db94011d3	13642	#define EMAC_CTL_RXON_Msk (0x1ul << EMAC_CTL_RXON_Pos) /!< EMAC CTL: RXON Mask /
sahilmgandhi	18:6a4db94011d3	13643
sahilmgandhi	18:6a4db94011d3	13644	#define EMAC_CTL_ALP_Pos (1) /!< EMAC CTL: ALP Position /
sahilmgandhi	18:6a4db94011d3	13645	#define EMAC_CTL_ALP_Msk (0x1ul << EMAC_CTL_ALP_Pos) /!< EMAC CTL: ALP Mask /
sahilmgandhi	18:6a4db94011d3	13646
sahilmgandhi	18:6a4db94011d3	13647	#define EMAC_CTL_ARP_Pos (2) /!< EMAC CTL: ARP Position /
sahilmgandhi	18:6a4db94011d3	13648	#define EMAC_CTL_ARP_Msk (0x1ul << EMAC_CTL_ARP_Pos) /!< EMAC CTL: ARP Mask /
sahilmgandhi	18:6a4db94011d3	13649
sahilmgandhi	18:6a4db94011d3	13650	#define EMAC_CTL_ACP_Pos (3) /!< EMAC CTL: ACP Position /
sahilmgandhi	18:6a4db94011d3	13651	#define EMAC_CTL_ACP_Msk (0x1ul << EMAC_CTL_ACP_Pos) /!< EMAC CTL: ACP Mask /
sahilmgandhi	18:6a4db94011d3	13652
sahilmgandhi	18:6a4db94011d3	13653	#define EMAC_CTL_AEP_Pos (4) /!< EMAC CTL: AEP Position /
sahilmgandhi	18:6a4db94011d3	13654	#define EMAC_CTL_AEP_Msk (0x1ul << EMAC_CTL_AEP_Pos) /!< EMAC CTL: AEP Mask /
sahilmgandhi	18:6a4db94011d3	13655
sahilmgandhi	18:6a4db94011d3	13656	#define EMAC_CTL_STRIPCRC_Pos (5) /!< EMAC CTL: STRIPCRC Position /
sahilmgandhi	18:6a4db94011d3	13657	#define EMAC_CTL_STRIPCRC_Msk (0x1ul << EMAC_CTL_STRIPCRC_Pos) /!< EMAC CTL: STRIPCRC Mask /
sahilmgandhi	18:6a4db94011d3	13658
sahilmgandhi	18:6a4db94011d3	13659	#define EMAC_CTL_WOLEN_Pos (6) /!< EMAC CTL: WOLEN Position /
sahilmgandhi	18:6a4db94011d3	13660	#define EMAC_CTL_WOLEN_Msk (0x1ul << EMAC_CTL_WOLEN_Pos) /!< EMAC CTL: WOLEN Mask /
sahilmgandhi	18:6a4db94011d3	13661
sahilmgandhi	18:6a4db94011d3	13662	#define EMAC_CTL_TXON_Pos (8) /!< EMAC CTL: TXON Position /
sahilmgandhi	18:6a4db94011d3	13663	#define EMAC_CTL_TXON_Msk (0x1ul << EMAC_CTL_TXON_Pos) /!< EMAC CTL: TXON Mask /
sahilmgandhi	18:6a4db94011d3	13664
sahilmgandhi	18:6a4db94011d3	13665	#define EMAC_CTL_NODEF_Pos (9) /!< EMAC CTL: NODEF Position /
sahilmgandhi	18:6a4db94011d3	13666	#define EMAC_CTL_NODEF_Msk (0x1ul << EMAC_CTL_NODEF_Pos) /!< EMAC CTL: NODEF Mask /
sahilmgandhi	18:6a4db94011d3	13667
sahilmgandhi	18:6a4db94011d3	13668	#define EMAC_CTL_SDPZ_Pos (16) /!< EMAC CTL: SDPZ Position /
sahilmgandhi	18:6a4db94011d3	13669	#define EMAC_CTL_SDPZ_Msk (0x1ul << EMAC_CTL_SDPZ_Pos) /!< EMAC CTL: SDPZ Mask /
sahilmgandhi	18:6a4db94011d3	13670
sahilmgandhi	18:6a4db94011d3	13671	#define EMAC_CTL_SQECHKEN_Pos (17) /!< EMAC CTL: SQECHKEN Position /
sahilmgandhi	18:6a4db94011d3	13672	#define EMAC_CTL_SQECHKEN_Msk (0x1ul << EMAC_CTL_SQECHKEN_Pos) /!< EMAC CTL: SQECHKEN Mask /
sahilmgandhi	18:6a4db94011d3	13673
sahilmgandhi	18:6a4db94011d3	13674	#define EMAC_CTL_FUDUP_Pos (18) /!< EMAC CTL: FUDUP Position /
sahilmgandhi	18:6a4db94011d3	13675	#define EMAC_CTL_FUDUP_Msk (0x1ul << EMAC_CTL_FUDUP_Pos) /!< EMAC CTL: FUDUP Mask /
sahilmgandhi	18:6a4db94011d3	13676
sahilmgandhi	18:6a4db94011d3	13677	#define EMAC_CTL_RMIIRXCTL_Pos (19) /!< EMAC CTL: RMIIRXCTL Position /
sahilmgandhi	18:6a4db94011d3	13678	#define EMAC_CTL_RMIIRXCTL_Msk (0x1ul << EMAC_CTL_RMIIRXCTL_Pos) /!< EMAC CTL: RMIIRXCTL Mask /
sahilmgandhi	18:6a4db94011d3	13679
sahilmgandhi	18:6a4db94011d3	13680	#define EMAC_CTL_OPMODE_Pos (20) /!< EMAC CTL: OPMODE Position /
sahilmgandhi	18:6a4db94011d3	13681	#define EMAC_CTL_OPMODE_Msk (0x1ul << EMAC_CTL_OPMODE_Pos) /!< EMAC CTL: OPMODE Mask /
sahilmgandhi	18:6a4db94011d3	13682
sahilmgandhi	18:6a4db94011d3	13683	#define EMAC_CTL_RMIIEN_Pos (22) /!< EMAC CTL: RMIIEN Position /
sahilmgandhi	18:6a4db94011d3	13684	#define EMAC_CTL_RMIIEN_Msk (0x1ul << EMAC_CTL_RMIIEN_Pos) /!< EMAC CTL: RMIIEN Mask /
sahilmgandhi	18:6a4db94011d3	13685
sahilmgandhi	18:6a4db94011d3	13686	#define EMAC_CTL_RST_Pos (24) /!< EMAC CTL: RST Position /
sahilmgandhi	18:6a4db94011d3	13687	#define EMAC_CTL_RST_Msk (0x1ul << EMAC_CTL_RST_Pos) /!< EMAC CTL: RST Mask /
sahilmgandhi	18:6a4db94011d3	13688
sahilmgandhi	18:6a4db94011d3	13689	#define EMAC_MIIMDAT_DATA_Pos (0) /!< EMAC MIIMDAT: DATA Position /
sahilmgandhi	18:6a4db94011d3	13690	#define EMAC_MIIMDAT_DATA_Msk (0xfffful << EMAC_MIIMDAT_DATA_Pos) /!< EMAC MIIMDAT: DATA Mask /
sahilmgandhi	18:6a4db94011d3	13691
sahilmgandhi	18:6a4db94011d3	13692	#define EMAC_MIIMCTL_PHYREG_Pos (0) /!< EMAC MIIMCTL: PHYREG Position /
sahilmgandhi	18:6a4db94011d3	13693	#define EMAC_MIIMCTL_PHYREG_Msk (0x1ful << EMAC_MIIMCTL_PHYREG_Pos) /!< EMAC MIIMCTL: PHYREG Mask /
sahilmgandhi	18:6a4db94011d3	13694
sahilmgandhi	18:6a4db94011d3	13695	#define EMAC_MIIMCTL_PHYADDR_Pos (8) /!< EMAC MIIMCTL: PHYADDR Position /
sahilmgandhi	18:6a4db94011d3	13696	#define EMAC_MIIMCTL_PHYADDR_Msk (0x1ful << EMAC_MIIMCTL_PHYADDR_Pos) /!< EMAC MIIMCTL: PHYADDR Mask /
sahilmgandhi	18:6a4db94011d3	13697
sahilmgandhi	18:6a4db94011d3	13698	#define EMAC_MIIMCTL_WRITE_Pos (16) /!< EMAC MIIMCTL: WRITE Position /
sahilmgandhi	18:6a4db94011d3	13699	#define EMAC_MIIMCTL_WRITE_Msk (0x1ul << EMAC_MIIMCTL_WRITE_Pos) /!< EMAC MIIMCTL: WRITE Mask /
sahilmgandhi	18:6a4db94011d3	13700
sahilmgandhi	18:6a4db94011d3	13701	#define EMAC_MIIMCTL_BUSY_Pos (17) /!< EMAC MIIMCTL: BUSY Position /
sahilmgandhi	18:6a4db94011d3	13702	#define EMAC_MIIMCTL_BUSY_Msk (0x1ul << EMAC_MIIMCTL_BUSY_Pos) /!< EMAC MIIMCTL: BUSY Mask /
sahilmgandhi	18:6a4db94011d3	13703
sahilmgandhi	18:6a4db94011d3	13704	#define EMAC_MIIMCTL_PREAMSP_Pos (18) /!< EMAC MIIMCTL: PREAMSP Position /
sahilmgandhi	18:6a4db94011d3	13705	#define EMAC_MIIMCTL_PREAMSP_Msk (0x1ul << EMAC_MIIMCTL_PREAMSP_Pos) /!< EMAC MIIMCTL: PREAMSP Mask /
sahilmgandhi	18:6a4db94011d3	13706
sahilmgandhi	18:6a4db94011d3	13707	#define EMAC_MIIMCTL_MDCON_Pos (19) /!< EMAC MIIMCTL: MDCON Position /
sahilmgandhi	18:6a4db94011d3	13708	#define EMAC_MIIMCTL_MDCON_Msk (0x1ul << EMAC_MIIMCTL_MDCON_Pos) /!< EMAC MIIMCTL: MDCON Mask /
sahilmgandhi	18:6a4db94011d3	13709
sahilmgandhi	18:6a4db94011d3	13710	#define EMAC_FIFOCTL_RXFIFOTH_Pos (0) /!< EMAC FIFOCTL: RXFIFOTH Position /
sahilmgandhi	18:6a4db94011d3	13711	#define EMAC_FIFOCTL_RXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_RXFIFOTH_Pos) /!< EMAC FIFOCTL: RXFIFOTH Mask /
sahilmgandhi	18:6a4db94011d3	13712
sahilmgandhi	18:6a4db94011d3	13713	#define EMAC_FIFOCTL_TXFIFOTH_Pos (8) /!< EMAC FIFOCTL: TXFIFOTH Position /
sahilmgandhi	18:6a4db94011d3	13714	#define EMAC_FIFOCTL_TXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_TXFIFOTH_Pos) /!< EMAC FIFOCTL: TXFIFOTH Mask /
sahilmgandhi	18:6a4db94011d3	13715
sahilmgandhi	18:6a4db94011d3	13716	#define EMAC_FIFOCTL_BURSTLEN_Pos (20) /!< EMAC FIFOCTL: BURSTLEN Position /
sahilmgandhi	18:6a4db94011d3	13717	#define EMAC_FIFOCTL_BURSTLEN_Msk (0x3ul << EMAC_FIFOCTL_BURSTLEN_Pos) /!< EMAC FIFOCTL: BURSTLEN Mask /
sahilmgandhi	18:6a4db94011d3	13718
sahilmgandhi	18:6a4db94011d3	13719	#define EMAC_TXST_TXST_Pos (0) /!< EMAC TXST: TXST Position /
sahilmgandhi	18:6a4db94011d3	13720	#define EMAC_TXST_TXST_Msk (0xfffffffful << EMAC_TXST_TXST_Pos) /!< EMAC TXST: TXST Mask /
sahilmgandhi	18:6a4db94011d3	13721
sahilmgandhi	18:6a4db94011d3	13722	#define EMAC_RXST_RXST_Pos (0) /!< EMAC RXST: RXST Position /
sahilmgandhi	18:6a4db94011d3	13723	#define EMAC_RXST_RXST_Msk (0xfffffffful << EMAC_RXST_RXST_Pos) /!< EMAC RXST: RXST Mask /
sahilmgandhi	18:6a4db94011d3	13724
sahilmgandhi	18:6a4db94011d3	13725	#define EMAC_MRFL_MRFL_Pos (0) /!< EMAC MRFL: MRFL Position /
sahilmgandhi	18:6a4db94011d3	13726	#define EMAC_MRFL_MRFL_Msk (0xfffful << EMAC_MRFL_MRFL_Pos) /!< EMAC MRFL: MRFL Mask /
sahilmgandhi	18:6a4db94011d3	13727
sahilmgandhi	18:6a4db94011d3	13728	#define EMAC_INTEN_RXIEN_Pos (0) /!< EMAC INTEN: RXIEN Position /
sahilmgandhi	18:6a4db94011d3	13729	#define EMAC_INTEN_RXIEN_Msk (0x1ul << EMAC_INTEN_RXIEN_Pos) /!< EMAC INTEN: RXIEN Mask /
sahilmgandhi	18:6a4db94011d3	13730
sahilmgandhi	18:6a4db94011d3	13731	#define EMAC_INTEN_CRCEIEN_Pos (1) /!< EMAC INTEN: CRCEIEN Position /
sahilmgandhi	18:6a4db94011d3	13732	#define EMAC_INTEN_CRCEIEN_Msk (0x1ul << EMAC_INTEN_CRCEIEN_Pos) /!< EMAC INTEN: CRCEIEN Mask /
sahilmgandhi	18:6a4db94011d3	13733
sahilmgandhi	18:6a4db94011d3	13734	#define EMAC_INTEN_RXOVIEN_Pos (2) /!< EMAC INTEN: RXOVIEN Position /
sahilmgandhi	18:6a4db94011d3	13735	#define EMAC_INTEN_RXOVIEN_Msk (0x1ul << EMAC_INTEN_RXOVIEN_Pos) /!< EMAC INTEN: RXOVIEN Mask /
sahilmgandhi	18:6a4db94011d3	13736
sahilmgandhi	18:6a4db94011d3	13737	#define EMAC_INTEN_LPIEN_Pos (3) /!< EMAC INTEN: LPIEN Position /
sahilmgandhi	18:6a4db94011d3	13738	#define EMAC_INTEN_LPIEN_Msk (0x1ul << EMAC_INTEN_LPIEN_Pos) /!< EMAC INTEN: LPIEN Mask /
sahilmgandhi	18:6a4db94011d3	13739
sahilmgandhi	18:6a4db94011d3	13740	#define EMAC_INTEN_RXGDIEN_Pos (4) /!< EMAC INTEN: RXGDIEN Position /
sahilmgandhi	18:6a4db94011d3	13741	#define EMAC_INTEN_RXGDIEN_Msk (0x1ul << EMAC_INTEN_RXGDIEN_Pos) /!< EMAC INTEN: RXGDIEN Mask /
sahilmgandhi	18:6a4db94011d3	13742
sahilmgandhi	18:6a4db94011d3	13743	#define EMAC_INTEN_ALIEIEN_Pos (5) /!< EMAC INTEN: ALIEIEN Position /
sahilmgandhi	18:6a4db94011d3	13744	#define EMAC_INTEN_ALIEIEN_Msk (0x1ul << EMAC_INTEN_ALIEIEN_Pos) /!< EMAC INTEN: ALIEIEN Mask /
sahilmgandhi	18:6a4db94011d3	13745
sahilmgandhi	18:6a4db94011d3	13746	#define EMAC_INTEN_RPIEN_Pos (6) /!< EMAC INTEN: RPIEN Position /
sahilmgandhi	18:6a4db94011d3	13747	#define EMAC_INTEN_RPIEN_Msk (0x1ul << EMAC_INTEN_RPIEN_Pos) /!< EMAC INTEN: RPIEN Mask /
sahilmgandhi	18:6a4db94011d3	13748
sahilmgandhi	18:6a4db94011d3	13749	#define EMAC_INTEN_MPCOVIEN_Pos (7) /!< EMAC INTEN: MPCOVIEN Position /
sahilmgandhi	18:6a4db94011d3	13750	#define EMAC_INTEN_MPCOVIEN_Msk (0x1ul << EMAC_INTEN_MPCOVIEN_Pos) /!< EMAC INTEN: MPCOVIEN Mask /
sahilmgandhi	18:6a4db94011d3	13751
sahilmgandhi	18:6a4db94011d3	13752	#define EMAC_INTEN_MFLEIEN_Pos (8) /!< EMAC INTEN: MFLEIEN Position /
sahilmgandhi	18:6a4db94011d3	13753	#define EMAC_INTEN_MFLEIEN_Msk (0x1ul << EMAC_INTEN_MFLEIEN_Pos) /!< EMAC INTEN: MFLEIEN Mask /
sahilmgandhi	18:6a4db94011d3	13754
sahilmgandhi	18:6a4db94011d3	13755	#define EMAC_INTEN_DENIEN_Pos (9) /!< EMAC INTEN: DENIEN Position /
sahilmgandhi	18:6a4db94011d3	13756	#define EMAC_INTEN_DENIEN_Msk (0x1ul << EMAC_INTEN_DENIEN_Pos) /!< EMAC INTEN: DENIEN Mask /
sahilmgandhi	18:6a4db94011d3	13757
sahilmgandhi	18:6a4db94011d3	13758	#define EMAC_INTEN_RDUIEN_Pos (10) /!< EMAC INTEN: RDUIEN Position /
sahilmgandhi	18:6a4db94011d3	13759	#define EMAC_INTEN_RDUIEN_Msk (0x1ul << EMAC_INTEN_RDUIEN_Pos) /!< EMAC INTEN: RDUIEN Mask /
sahilmgandhi	18:6a4db94011d3	13760
sahilmgandhi	18:6a4db94011d3	13761	#define EMAC_INTEN_RXBEIEN_Pos (11) /!< EMAC INTEN: RXBEIEN Position /
sahilmgandhi	18:6a4db94011d3	13762	#define EMAC_INTEN_RXBEIEN_Msk (0x1ul << EMAC_INTEN_RXBEIEN_Pos) /!< EMAC INTEN: RXBEIEN Mask /
sahilmgandhi	18:6a4db94011d3	13763
sahilmgandhi	18:6a4db94011d3	13764	#define EMAC_INTEN_CFRIEN_Pos (14) /!< EMAC INTEN: CFRIEN Position /
sahilmgandhi	18:6a4db94011d3	13765	#define EMAC_INTEN_CFRIEN_Msk (0x1ul << EMAC_INTEN_CFRIEN_Pos) /!< EMAC INTEN: CFRIEN Mask /
sahilmgandhi	18:6a4db94011d3	13766
sahilmgandhi	18:6a4db94011d3	13767	#define EMAC_INTEN_WOLIEN_Pos (15) /!< EMAC INTEN: WOLIEN Position /
sahilmgandhi	18:6a4db94011d3	13768	#define EMAC_INTEN_WOLIEN_Msk (0x1ul << EMAC_INTEN_WOLIEN_Pos) /!< EMAC INTEN: WOLIEN Mask /
sahilmgandhi	18:6a4db94011d3	13769
sahilmgandhi	18:6a4db94011d3	13770	#define EMAC_INTEN_TXIEN_Pos (16) /!< EMAC INTEN: TXIEN Position /
sahilmgandhi	18:6a4db94011d3	13771	#define EMAC_INTEN_TXIEN_Msk (0x1ul << EMAC_INTEN_TXIEN_Pos) /!< EMAC INTEN: TXIEN Mask /
sahilmgandhi	18:6a4db94011d3	13772
sahilmgandhi	18:6a4db94011d3	13773	#define EMAC_INTEN_TXUDIEN_Pos (17) /!< EMAC INTEN: TXUDIEN Position /
sahilmgandhi	18:6a4db94011d3	13774	#define EMAC_INTEN_TXUDIEN_Msk (0x1ul << EMAC_INTEN_TXUDIEN_Pos) /!< EMAC INTEN: TXUDIEN Mask /
sahilmgandhi	18:6a4db94011d3	13775
sahilmgandhi	18:6a4db94011d3	13776	#define EMAC_INTEN_TXCPIEN_Pos (18) /!< EMAC INTEN: TXCPIEN Position /
sahilmgandhi	18:6a4db94011d3	13777	#define EMAC_INTEN_TXCPIEN_Msk (0x1ul << EMAC_INTEN_TXCPIEN_Pos) /!< EMAC INTEN: TXCPIEN Mask /
sahilmgandhi	18:6a4db94011d3	13778
sahilmgandhi	18:6a4db94011d3	13779	#define EMAC_INTEN_EXDEFIEN_Pos (19) /!< EMAC INTEN: EXDEFIEN Position /
sahilmgandhi	18:6a4db94011d3	13780	#define EMAC_INTEN_EXDEFIEN_Msk (0x1ul << EMAC_INTEN_EXDEFIEN_Pos) /!< EMAC INTEN: EXDEFIEN Mask /
sahilmgandhi	18:6a4db94011d3	13781
sahilmgandhi	18:6a4db94011d3	13782	#define EMAC_INTEN_NCSIEN_Pos (20) /!< EMAC INTEN: NCSIEN Position /
sahilmgandhi	18:6a4db94011d3	13783	#define EMAC_INTEN_NCSIEN_Msk (0x1ul << EMAC_INTEN_NCSIEN_Pos) /!< EMAC INTEN: NCSIEN Mask /
sahilmgandhi	18:6a4db94011d3	13784
sahilmgandhi	18:6a4db94011d3	13785	#define EMAC_INTEN_TXABTIEN_Pos (21) /!< EMAC INTEN: TXABTIEN Position /
sahilmgandhi	18:6a4db94011d3	13786	#define EMAC_INTEN_TXABTIEN_Msk (0x1ul << EMAC_INTEN_TXABTIEN_Pos) /!< EMAC INTEN: TXABTIEN Mask /
sahilmgandhi	18:6a4db94011d3	13787
sahilmgandhi	18:6a4db94011d3	13788	#define EMAC_INTEN_LCIEN_Pos (22) /!< EMAC INTEN: LCIEN Position /
sahilmgandhi	18:6a4db94011d3	13789	#define EMAC_INTEN_LCIEN_Msk (0x1ul << EMAC_INTEN_LCIEN_Pos) /!< EMAC INTEN: LCIEN Mask /
sahilmgandhi	18:6a4db94011d3	13790
sahilmgandhi	18:6a4db94011d3	13791	#define EMAC_INTEN_TDUIEN_Pos (23) /!< EMAC INTEN: TDUIEN Position /
sahilmgandhi	18:6a4db94011d3	13792	#define EMAC_INTEN_TDUIEN_Msk (0x1ul << EMAC_INTEN_TDUIEN_Pos) /!< EMAC INTEN: TDUIEN Mask /
sahilmgandhi	18:6a4db94011d3	13793
sahilmgandhi	18:6a4db94011d3	13794	#define EMAC_INTEN_TXBEIEN_Pos (24) /!< EMAC INTEN: TXBEIEN Position /
sahilmgandhi	18:6a4db94011d3	13795	#define EMAC_INTEN_TXBEIEN_Msk (0x1ul << EMAC_INTEN_TXBEIEN_Pos) /!< EMAC INTEN: TXBEIEN Mask /
sahilmgandhi	18:6a4db94011d3	13796
sahilmgandhi	18:6a4db94011d3	13797	#define EMAC_INTEN_TSALMIEN_Pos (28) /!< EMAC INTEN: TSALMIEN Position /
sahilmgandhi	18:6a4db94011d3	13798	#define EMAC_INTEN_TSALMIEN_Msk (0x1ul << EMAC_INTEN_TSALMIEN_Pos) /!< EMAC INTEN: TSALMIEN Mask /
sahilmgandhi	18:6a4db94011d3	13799
sahilmgandhi	18:6a4db94011d3	13800	#define EMAC_INTSTS_RXIF_Pos (0) /!< EMAC INTSTS: RXIF Position /
sahilmgandhi	18:6a4db94011d3	13801	#define EMAC_INTSTS_RXIF_Msk (0x1ul << EMAC_INTSTS_RXIF_Pos) /!< EMAC INTSTS: RXIF Mask /
sahilmgandhi	18:6a4db94011d3	13802
sahilmgandhi	18:6a4db94011d3	13803	#define EMAC_INTSTS_CRCEIF_Pos (1) /!< EMAC INTSTS: CRCEIF Position /
sahilmgandhi	18:6a4db94011d3	13804	#define EMAC_INTSTS_CRCEIF_Msk (0x1ul << EMAC_INTSTS_CRCEIF_Pos) /!< EMAC INTSTS: CRCEIF Mask /
sahilmgandhi	18:6a4db94011d3	13805
sahilmgandhi	18:6a4db94011d3	13806	#define EMAC_INTSTS_RXOVIF_Pos (2) /!< EMAC INTSTS: RXOVIF Position /
sahilmgandhi	18:6a4db94011d3	13807	#define EMAC_INTSTS_RXOVIF_Msk (0x1ul << EMAC_INTSTS_RXOVIF_Pos) /!< EMAC INTSTS: RXOVIF Mask /
sahilmgandhi	18:6a4db94011d3	13808
sahilmgandhi	18:6a4db94011d3	13809	#define EMAC_INTSTS_LPIF_Pos (3) /!< EMAC INTSTS: LPIF Position /
sahilmgandhi	18:6a4db94011d3	13810	#define EMAC_INTSTS_LPIF_Msk (0x1ul << EMAC_INTSTS_LPIF_Pos) /!< EMAC INTSTS: LPIF Mask /
sahilmgandhi	18:6a4db94011d3	13811
sahilmgandhi	18:6a4db94011d3	13812	#define EMAC_INTSTS_RXGDIF_Pos (4) /!< EMAC INTSTS: RXGDIF Position /
sahilmgandhi	18:6a4db94011d3	13813	#define EMAC_INTSTS_RXGDIF_Msk (0x1ul << EMAC_INTSTS_RXGDIF_Pos) /!< EMAC INTSTS: RXGDIF Mask /
sahilmgandhi	18:6a4db94011d3	13814
sahilmgandhi	18:6a4db94011d3	13815	#define EMAC_INTSTS_ALIEIF_Pos (5) /!< EMAC INTSTS: ALIEIF Position /
sahilmgandhi	18:6a4db94011d3	13816	#define EMAC_INTSTS_ALIEIF_Msk (0x1ul << EMAC_INTSTS_ALIEIF_Pos) /!< EMAC INTSTS: ALIEIF Mask /
sahilmgandhi	18:6a4db94011d3	13817
sahilmgandhi	18:6a4db94011d3	13818	#define EMAC_INTSTS_RPIF_Pos (6) /!< EMAC INTSTS: RPIF Position /
sahilmgandhi	18:6a4db94011d3	13819	#define EMAC_INTSTS_RPIF_Msk (0x1ul << EMAC_INTSTS_RPIF_Pos) /!< EMAC INTSTS: RPIF Mask /
sahilmgandhi	18:6a4db94011d3	13820
sahilmgandhi	18:6a4db94011d3	13821	#define EMAC_INTSTS_MPCOVIF_Pos (7) /!< EMAC INTSTS: MPCOVIF Position /
sahilmgandhi	18:6a4db94011d3	13822	#define EMAC_INTSTS_MPCOVIF_Msk (0x1ul << EMAC_INTSTS_MPCOVIF_Pos) /!< EMAC INTSTS: MPCOVIF Mask /
sahilmgandhi	18:6a4db94011d3	13823
sahilmgandhi	18:6a4db94011d3	13824	#define EMAC_INTSTS_MFLEIF_Pos (8) /!< EMAC INTSTS: MFLEIF Position /
sahilmgandhi	18:6a4db94011d3	13825	#define EMAC_INTSTS_MFLEIF_Msk (0x1ul << EMAC_INTSTS_MFLEIF_Pos) /!< EMAC INTSTS: MFLEIF Mask /
sahilmgandhi	18:6a4db94011d3	13826
sahilmgandhi	18:6a4db94011d3	13827	#define EMAC_INTSTS_DENIF_Pos (9) /!< EMAC INTSTS: DENIF Position /
sahilmgandhi	18:6a4db94011d3	13828	#define EMAC_INTSTS_DENIF_Msk (0x1ul << EMAC_INTSTS_DENIF_Pos) /!< EMAC INTSTS: DENIF Mask /
sahilmgandhi	18:6a4db94011d3	13829
sahilmgandhi	18:6a4db94011d3	13830	#define EMAC_INTSTS_RDUIF_Pos (10) /!< EMAC INTSTS: RDUIF Position /
sahilmgandhi	18:6a4db94011d3	13831	#define EMAC_INTSTS_RDUIF_Msk (0x1ul << EMAC_INTSTS_RDUIF_Pos) /!< EMAC INTSTS: RDUIF Mask /
sahilmgandhi	18:6a4db94011d3	13832
sahilmgandhi	18:6a4db94011d3	13833	#define EMAC_INTSTS_RXBEIF_Pos (11) /!< EMAC INTSTS: RXBEIF Position /
sahilmgandhi	18:6a4db94011d3	13834	#define EMAC_INTSTS_RXBEIF_Msk (0x1ul << EMAC_INTSTS_RXBEIF_Pos) /!< EMAC INTSTS: RXBEIF Mask /
sahilmgandhi	18:6a4db94011d3	13835
sahilmgandhi	18:6a4db94011d3	13836	#define EMAC_INTSTS_CFRIF_Pos (14) /!< EMAC INTSTS: CFRIF Position /
sahilmgandhi	18:6a4db94011d3	13837	#define EMAC_INTSTS_CFRIF_Msk (0x1ul << EMAC_INTSTS_CFRIF_Pos) /!< EMAC INTSTS: CFRIF Mask /
sahilmgandhi	18:6a4db94011d3	13838
sahilmgandhi	18:6a4db94011d3	13839	#define EMAC_INTSTS_WOLIF_Pos (15) /!< EMAC INTSTS: WOLIF Position /
sahilmgandhi	18:6a4db94011d3	13840	#define EMAC_INTSTS_WOLIF_Msk (0x1ul << EMAC_INTSTS_WOLIF_Pos) /!< EMAC INTSTS: WOLIF Mask /
sahilmgandhi	18:6a4db94011d3	13841
sahilmgandhi	18:6a4db94011d3	13842	#define EMAC_INTSTS_TXIF_Pos (16) /!< EMAC INTSTS: TXIF Position /
sahilmgandhi	18:6a4db94011d3	13843	#define EMAC_INTSTS_TXIF_Msk (0x1ul << EMAC_INTSTS_TXIF_Pos) /!< EMAC INTSTS: TXIF Mask /
sahilmgandhi	18:6a4db94011d3	13844
sahilmgandhi	18:6a4db94011d3	13845	#define EMAC_INTSTS_TXUDIF_Pos (17) /!< EMAC INTSTS: TXUDIF Position /
sahilmgandhi	18:6a4db94011d3	13846	#define EMAC_INTSTS_TXUDIF_Msk (0x1ul << EMAC_INTSTS_TXUDIF_Pos) /!< EMAC INTSTS: TXUDIF Mask /
sahilmgandhi	18:6a4db94011d3	13847
sahilmgandhi	18:6a4db94011d3	13848	#define EMAC_INTSTS_TXCPIF_Pos (18) /!< EMAC INTSTS: TXCPIF Position /
sahilmgandhi	18:6a4db94011d3	13849	#define EMAC_INTSTS_TXCPIF_Msk (0x1ul << EMAC_INTSTS_TXCPIF_Pos) /!< EMAC INTSTS: TXCPIF Mask /
sahilmgandhi	18:6a4db94011d3	13850
sahilmgandhi	18:6a4db94011d3	13851	#define EMAC_INTSTS_EXDEFIF_Pos (19) /!< EMAC INTSTS: EXDEFIF Position /
sahilmgandhi	18:6a4db94011d3	13852	#define EMAC_INTSTS_EXDEFIF_Msk (0x1ul << EMAC_INTSTS_EXDEFIF_Pos) /!< EMAC INTSTS: EXDEFIF Mask /
sahilmgandhi	18:6a4db94011d3	13853
sahilmgandhi	18:6a4db94011d3	13854	#define EMAC_INTSTS_NCSIF_Pos (20) /!< EMAC INTSTS: NCSIF Position /
sahilmgandhi	18:6a4db94011d3	13855	#define EMAC_INTSTS_NCSIF_Msk (0x1ul << EMAC_INTSTS_NCSIF_Pos) /!< EMAC INTSTS: NCSIF Mask /
sahilmgandhi	18:6a4db94011d3	13856
sahilmgandhi	18:6a4db94011d3	13857	#define EMAC_INTSTS_TXABTIF_Pos (21) /!< EMAC INTSTS: TXABTIF Position /
sahilmgandhi	18:6a4db94011d3	13858	#define EMAC_INTSTS_TXABTIF_Msk (0x1ul << EMAC_INTSTS_TXABTIF_Pos) /!< EMAC INTSTS: TXABTIF Mask /
sahilmgandhi	18:6a4db94011d3	13859
sahilmgandhi	18:6a4db94011d3	13860	#define EMAC_INTSTS_LCIF_Pos (22) /!< EMAC INTSTS: LCIF Position /
sahilmgandhi	18:6a4db94011d3	13861	#define EMAC_INTSTS_LCIF_Msk (0x1ul << EMAC_INTSTS_LCIF_Pos) /!< EMAC INTSTS: LCIF Mask /
sahilmgandhi	18:6a4db94011d3	13862
sahilmgandhi	18:6a4db94011d3	13863	#define EMAC_INTSTS_TDUIF_Pos (23) /!< EMAC INTSTS: TDUIF Position /
sahilmgandhi	18:6a4db94011d3	13864	#define EMAC_INTSTS_TDUIF_Msk (0x1ul << EMAC_INTSTS_TDUIF_Pos) /!< EMAC INTSTS: TDUIF Mask /
sahilmgandhi	18:6a4db94011d3	13865
sahilmgandhi	18:6a4db94011d3	13866	#define EMAC_INTSTS_TXBEIF_Pos (24) /!< EMAC INTSTS: TXBEIF Position /
sahilmgandhi	18:6a4db94011d3	13867	#define EMAC_INTSTS_TXBEIF_Msk (0x1ul << EMAC_INTSTS_TXBEIF_Pos) /!< EMAC INTSTS: TXBEIF Mask /
sahilmgandhi	18:6a4db94011d3	13868
sahilmgandhi	18:6a4db94011d3	13869	#define EMAC_INTSTS_TSALMIF_Pos (28) /!< EMAC INTSTS: TSALMIF Position /
sahilmgandhi	18:6a4db94011d3	13870	#define EMAC_INTSTS_TSALMIF_Msk (0x1ul << EMAC_INTSTS_TSALMIF_Pos) /!< EMAC INTSTS: TSALMIF Mask /
sahilmgandhi	18:6a4db94011d3	13871
sahilmgandhi	18:6a4db94011d3	13872	#define EMAC_GENSTS_CFRIF_Pos (0) /!< EMAC GENSTS: CFRIF Position /
sahilmgandhi	18:6a4db94011d3	13873	#define EMAC_GENSTS_CFRIF_Msk (0x1ul << EMAC_GENSTS_CFRIF_Pos) /!< EMAC GENSTS: CFRIF Mask /
sahilmgandhi	18:6a4db94011d3	13874
sahilmgandhi	18:6a4db94011d3	13875	#define EMAC_GENSTS_RXHALT_Pos (1) /!< EMAC GENSTS: RXHALT Position /
sahilmgandhi	18:6a4db94011d3	13876	#define EMAC_GENSTS_RXHALT_Msk (0x1ul << EMAC_GENSTS_RXHALT_Pos) /!< EMAC GENSTS: RXHALT Mask /
sahilmgandhi	18:6a4db94011d3	13877
sahilmgandhi	18:6a4db94011d3	13878	#define EMAC_GENSTS_RXFFULL_Pos (2) /!< EMAC GENSTS: RXFFULL Position /
sahilmgandhi	18:6a4db94011d3	13879	#define EMAC_GENSTS_RXFFULL_Msk (0x1ul << EMAC_GENSTS_RXFFULL_Pos) /!< EMAC GENSTS: RXFFULL Mask /
sahilmgandhi	18:6a4db94011d3	13880
sahilmgandhi	18:6a4db94011d3	13881	#define EMAC_GENSTS_COLCNT_Pos (4) /!< EMAC GENSTS: COLCNT Position /
sahilmgandhi	18:6a4db94011d3	13882	#define EMAC_GENSTS_COLCNT_Msk (0xful << EMAC_GENSTS_COLCNT_Pos) /!< EMAC GENSTS: COLCNT Mask /
sahilmgandhi	18:6a4db94011d3	13883
sahilmgandhi	18:6a4db94011d3	13884	#define EMAC_GENSTS_DEF_Pos (8) /!< EMAC GENSTS: DEF Position /
sahilmgandhi	18:6a4db94011d3	13885	#define EMAC_GENSTS_DEF_Msk (0x1ul << EMAC_GENSTS_DEF_Pos) /!< EMAC GENSTS: DEF Mask /
sahilmgandhi	18:6a4db94011d3	13886
sahilmgandhi	18:6a4db94011d3	13887	#define EMAC_GENSTS_TXPAUSED_Pos (9) /!< EMAC GENSTS: TXPAUSED Position /
sahilmgandhi	18:6a4db94011d3	13888	#define EMAC_GENSTS_TXPAUSED_Msk (0x1ul << EMAC_GENSTS_TXPAUSED_Pos) /!< EMAC GENSTS: TXPAUSED Mask /
sahilmgandhi	18:6a4db94011d3	13889
sahilmgandhi	18:6a4db94011d3	13890	#define EMAC_GENSTS_SQE_Pos (10) /!< EMAC GENSTS: SQE Position /
sahilmgandhi	18:6a4db94011d3	13891	#define EMAC_GENSTS_SQE_Msk (0x1ul << EMAC_GENSTS_SQE_Pos) /!< EMAC GENSTS: SQE Mask /
sahilmgandhi	18:6a4db94011d3	13892
sahilmgandhi	18:6a4db94011d3	13893	#define EMAC_GENSTS_TXHALT_Pos (11) /!< EMAC GENSTS: TXHALT Position /
sahilmgandhi	18:6a4db94011d3	13894	#define EMAC_GENSTS_TXHALT_Msk (0x1ul << EMAC_GENSTS_TXHALT_Pos) /!< EMAC GENSTS: TXHALT Mask /
sahilmgandhi	18:6a4db94011d3	13895
sahilmgandhi	18:6a4db94011d3	13896	#define EMAC_GENSTS_RPSTS_Pos (12) /!< EMAC GENSTS: RPSTS Position /
sahilmgandhi	18:6a4db94011d3	13897	#define EMAC_GENSTS_RPSTS_Msk (0x1ul << EMAC_GENSTS_RPSTS_Pos) /!< EMAC GENSTS: RPSTS Mask /
sahilmgandhi	18:6a4db94011d3	13898
sahilmgandhi	18:6a4db94011d3	13899	#define EMAC_MPCNT_MPCNT_Pos (0) /!< EMAC MPCNT: MPCNT Position /
sahilmgandhi	18:6a4db94011d3	13900	#define EMAC_MPCNT_MPCNT_Msk (0xfffful << EMAC_MPCNT_MPCNT_Pos) /!< EMAC MPCNT: MPCNT Mask /
sahilmgandhi	18:6a4db94011d3	13901
sahilmgandhi	18:6a4db94011d3	13902	#define EMAC_RPCNT_RPCNT_Pos (0) /!< EMAC RPCNT: RPCNT Position /
sahilmgandhi	18:6a4db94011d3	13903	#define EMAC_RPCNT_RPCNT_Msk (0xfffful << EMAC_RPCNT_RPCNT_Pos) /!< EMAC RPCNT: RPCNT Mask /
sahilmgandhi	18:6a4db94011d3	13904
sahilmgandhi	18:6a4db94011d3	13905	#define EMAC_FRSTS_RXFLT_Pos (0) /!< EMAC FRSTS: RXFLT Position /
sahilmgandhi	18:6a4db94011d3	13906	#define EMAC_FRSTS_RXFLT_Msk (0xfffful << EMAC_FRSTS_RXFLT_Pos) /!< EMAC FRSTS: RXFLT Mask /
sahilmgandhi	18:6a4db94011d3	13907
sahilmgandhi	18:6a4db94011d3	13908	#define EMAC_CTXDSA_CTXDSA_Pos (0) /!< EMAC CTXDSA: CTXDSA Position /
sahilmgandhi	18:6a4db94011d3	13909	#define EMAC_CTXDSA_CTXDSA_Msk (0xfffffffful << EMAC_CTXDSA_CTXDSA_Pos) /!< EMAC CTXDSA: CTXDSA Mask /
sahilmgandhi	18:6a4db94011d3	13910
sahilmgandhi	18:6a4db94011d3	13911	#define EMAC_CTXBSA_CTXBSA_Pos (0) /!< EMAC CTXBSA: CTXBSA Position /
sahilmgandhi	18:6a4db94011d3	13912	#define EMAC_CTXBSA_CTXBSA_Msk (0xfffffffful << EMAC_CTXBSA_CTXBSA_Pos) /!< EMAC CTXBSA: CTXBSA Mask /
sahilmgandhi	18:6a4db94011d3	13913
sahilmgandhi	18:6a4db94011d3	13914	#define EMAC_CRXDSA_CRXDSA_Pos (0) /!< EMAC CRXDSA: CRXDSA Position /
sahilmgandhi	18:6a4db94011d3	13915	#define EMAC_CRXDSA_CRXDSA_Msk (0xfffffffful << EMAC_CRXDSA_CRXDSA_Pos) /!< EMAC CRXDSA: CRXDSA Mask /
sahilmgandhi	18:6a4db94011d3	13916
sahilmgandhi	18:6a4db94011d3	13917	#define EMAC_CRXBSA_CRXBSA_Pos (0) /!< EMAC CRXBSA: CRXBSA Position /
sahilmgandhi	18:6a4db94011d3	13918	#define EMAC_CRXBSA_CRXBSA_Msk (0xfffffffful << EMAC_CRXBSA_CRXBSA_Pos) /!< EMAC CRXBSA: CRXBSA Mask /
sahilmgandhi	18:6a4db94011d3	13919
sahilmgandhi	18:6a4db94011d3	13920	#define EMAC_TSCTL_TSEN_Pos (0) /!< EMAC TSCTL: TSEN Position /
sahilmgandhi	18:6a4db94011d3	13921	#define EMAC_TSCTL_TSEN_Msk (0x1ul << EMAC_TSCTL_TSEN_Pos) /!< EMAC TSCTL: TSEN Mask /
sahilmgandhi	18:6a4db94011d3	13922
sahilmgandhi	18:6a4db94011d3	13923	#define EMAC_TSCTL_TSIEN_Pos (1) /!< EMAC TSCTL: TSIEN Position /
sahilmgandhi	18:6a4db94011d3	13924	#define EMAC_TSCTL_TSIEN_Msk (0x1ul << EMAC_TSCTL_TSIEN_Pos) /!< EMAC TSCTL: TSIEN Mask /
sahilmgandhi	18:6a4db94011d3	13925
sahilmgandhi	18:6a4db94011d3	13926	#define EMAC_TSCTL_TSMODE_Pos (2) /!< EMAC TSCTL: TSMODE Position /
sahilmgandhi	18:6a4db94011d3	13927	#define EMAC_TSCTL_TSMODE_Msk (0x1ul << EMAC_TSCTL_TSMODE_Pos) /!< EMAC TSCTL: TSMODE Mask /
sahilmgandhi	18:6a4db94011d3	13928
sahilmgandhi	18:6a4db94011d3	13929	#define EMAC_TSCTL_TSUPDATE_Pos (3) /!< EMAC TSCTL: TSUPDATE Position /
sahilmgandhi	18:6a4db94011d3	13930	#define EMAC_TSCTL_TSUPDATE_Msk (0x1ul << EMAC_TSCTL_TSUPDATE_Pos) /!< EMAC TSCTL: TSUPDATE Mask /
sahilmgandhi	18:6a4db94011d3	13931
sahilmgandhi	18:6a4db94011d3	13932	#define EMAC_TSCTL_TSALMEN_Pos (5) /!< EMAC TSCTL: TSALMEN Position /
sahilmgandhi	18:6a4db94011d3	13933	#define EMAC_TSCTL_TSALMEN_Msk (0x1ul << EMAC_TSCTL_TSALMEN_Pos) /!< EMAC TSCTL: TSALMEN Mask /
sahilmgandhi	18:6a4db94011d3	13934
sahilmgandhi	18:6a4db94011d3	13935	#define EMAC_TSSEC_SEC_Pos (0) /!< EMAC TSSEC: SEC Position /
sahilmgandhi	18:6a4db94011d3	13936	#define EMAC_TSSEC_SEC_Msk (0xfffffffful << EMAC_TSSEC_SEC_Pos) /!< EMAC TSSEC: SEC Mask /
sahilmgandhi	18:6a4db94011d3	13937
sahilmgandhi	18:6a4db94011d3	13938	#define EMAC_TSSUBSEC_SUBSEC_Pos (0) /!< EMAC TSSUBSEC: SUBSEC Position /
sahilmgandhi	18:6a4db94011d3	13939	#define EMAC_TSSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_TSSUBSEC_SUBSEC_Pos) /!< EMAC TSSUBSEC: SUBSEC Mask /
sahilmgandhi	18:6a4db94011d3	13940
sahilmgandhi	18:6a4db94011d3	13941	#define EMAC_TSINC_CNTINC_Pos (0) /!< EMAC TSINC: CNTINC Position /
sahilmgandhi	18:6a4db94011d3	13942	#define EMAC_TSINC_CNTINC_Msk (0xfful << EMAC_TSINC_CNTINC_Pos) /!< EMAC TSINC: CNTINC Mask /
sahilmgandhi	18:6a4db94011d3	13943
sahilmgandhi	18:6a4db94011d3	13944	#define EMAC_TSADDEND_ADDEND_Pos (0) /!< EMAC TSADDEND: ADDEND Position /
sahilmgandhi	18:6a4db94011d3	13945	#define EMAC_TSADDEND_ADDEND_Msk (0xfffffffful << EMAC_TSADDEND_ADDEND_Pos) /!< EMAC TSADDEND: ADDEND Mask /
sahilmgandhi	18:6a4db94011d3	13946
sahilmgandhi	18:6a4db94011d3	13947	#define EMAC_UPDSEC_SEC_Pos (0) /!< EMAC UPDSEC: SEC Position /
sahilmgandhi	18:6a4db94011d3	13948	#define EMAC_UPDSEC_SEC_Msk (0xfffffffful << EMAC_UPDSEC_SEC_Pos) /!< EMAC UPDSEC: SEC Mask /
sahilmgandhi	18:6a4db94011d3	13949
sahilmgandhi	18:6a4db94011d3	13950	#define EMAC_UPDSUBSEC_SUBSEC_Pos (0) /!< EMAC UPDSUBSEC: SUBSEC Position /
sahilmgandhi	18:6a4db94011d3	13951	#define EMAC_UPDSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_UPDSUBSEC_SUBSEC_Pos) /!< EMAC UPDSUBSEC: SUBSEC Mask /
sahilmgandhi	18:6a4db94011d3	13952
sahilmgandhi	18:6a4db94011d3	13953	#define EMAC_ALMSEC_SEC_Pos (0) /!< EMAC ALMSEC: SEC Position /
sahilmgandhi	18:6a4db94011d3	13954	#define EMAC_ALMSEC_SEC_Msk (0xfffffffful << EMAC_ALMSEC_SEC_Pos) /!< EMAC ALMSEC: SEC Mask /
sahilmgandhi	18:6a4db94011d3	13955
sahilmgandhi	18:6a4db94011d3	13956	#define EMAC_ALMSUBSEC_SUBSEC_Pos (0) /!< EMAC ALMSUBSEC: SUBSEC Position /
sahilmgandhi	18:6a4db94011d3	13957	#define EMAC_ALMSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_ALMSUBSEC_SUBSEC_Pos) /!< EMAC ALMSUBSEC: SUBSEC Mask /
sahilmgandhi	18:6a4db94011d3	13958
sahilmgandhi	18:6a4db94011d3	13959	/*@}/ /* EMAC_CONST */
sahilmgandhi	18:6a4db94011d3	13960	/*@}/ /* end of EMAC register group */
sahilmgandhi	18:6a4db94011d3	13961
sahilmgandhi	18:6a4db94011d3	13962
sahilmgandhi	18:6a4db94011d3	13963	/---------------------- Enhanced PWM Generator -------------------------/
sahilmgandhi	18:6a4db94011d3	13964	/**
sahilmgandhi	18:6a4db94011d3	13965	@addtogroup EPWM Enhanced PWM Generator(EPWM)
sahilmgandhi	18:6a4db94011d3	13966	Memory Mapped Structure for EPWM Controller
sahilmgandhi	18:6a4db94011d3	13967	@{ */
sahilmgandhi	18:6a4db94011d3	13968
sahilmgandhi	18:6a4db94011d3	13969	typedef struct {
sahilmgandhi	18:6a4db94011d3	13970
sahilmgandhi	18:6a4db94011d3	13971
sahilmgandhi	18:6a4db94011d3	13972	/**
sahilmgandhi	18:6a4db94011d3	13973	* CTL
sahilmgandhi	18:6a4db94011d3	13974	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	13975	* Offset: 0x00 PWM Control Register
sahilmgandhi	18:6a4db94011d3	13976	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	13977	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	13978	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	13979	* \|[0:1] \|MODE \|PWM Mode Selection
sahilmgandhi	18:6a4db94011d3	13980	* \| \| \|00 = Independent mode.
sahilmgandhi	18:6a4db94011d3	13981	* \| \| \|01 = Pair/Complementary mode.
sahilmgandhi	18:6a4db94011d3	13982	* \| \| \|10 = Synchronized mode.
sahilmgandhi	18:6a4db94011d3	13983	* \| \| \|11 = Reserved.
sahilmgandhi	18:6a4db94011d3	13984	* \|[2:3] \|CLKDIV \|PWM Clock Pre-Divider Selection
sahilmgandhi	18:6a4db94011d3	13985	* \| \| \|00 = PWM clock = EPWMx_CLK.
sahilmgandhi	18:6a4db94011d3	13986	* \| \| \|01 = PWM clock = EPWMx_CLK/2.
sahilmgandhi	18:6a4db94011d3	13987	* \| \| \|10 = PWM clock = EPWMx_CLK/4.
sahilmgandhi	18:6a4db94011d3	13988	* \| \| \|11 = PWM clock = EPWMx_CLK/16.
sahilmgandhi	18:6a4db94011d3	13989	* \|[4] \|PWMIEN \|PWM Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	13990	* \| \| \|0 = Disabling flag PIF to trigger PWM interrupt.
sahilmgandhi	18:6a4db94011d3	13991	* \| \| \|1 = Enabling flag PIF can trigger PWM interrupt.
sahilmgandhi	18:6a4db94011d3	13992	* \|[5] \|BRKIEN \|Brake0 And Brak1 Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	13993	* \| \| \|0 = Disabling flags BFK0 and BFK1 to trigger PWM interrupt.
sahilmgandhi	18:6a4db94011d3	13994	* \| \| \|1 = Enabling flags BRKIF0 and BRKIF1 can trigger PWM interrupt.
sahilmgandhi	18:6a4db94011d3	13995	* \|[6] \|LOAD \|Re-Load PWM Period Registers (EPWM_PERIOD) And PWM Duty Registers (PWM0~3) Control
sahilmgandhi	18:6a4db94011d3	13996	* \| \| \|0 = No action if written with 0.
sahilmgandhi	18:6a4db94011d3	13997	* \| \| \|The value of PWM period register (EPWM_PERIOD) and PWM duty registers (PWMn_CH0~PWMn_CH3) are not loaded to PWM counter and Comparator registers.
sahilmgandhi	18:6a4db94011d3	13998	* \| \| \|1 = Hardware will update the value of PWM period register (EPWM_PERIOD) and PWM duty registers (PWMn_CH0~PWMn_CH3) to PWM Counter and Comparator register at the time of PWM Counter matches PERIOD in edge and central aligned modes or at the time of PWM Counter down counts with underflow in central aligned mode.
sahilmgandhi	18:6a4db94011d3	13999	* \| \| \|Note1: n=0-1 for PWM unit0-1.
sahilmgandhi	18:6a4db94011d3	14000	* \| \| \|Note2: This bit is software write, hardware clear and always read zero.
sahilmgandhi	18:6a4db94011d3	14001	* \|[7] \|CNTEN \|Start CNTEN Control
sahilmgandhi	18:6a4db94011d3	14002	* \| \| \|0 = The PWM stops running.
sahilmgandhi	18:6a4db94011d3	14003	* \| \| \|1 = The PWM counter starts running.
sahilmgandhi	18:6a4db94011d3	14004	* \|[8] \|INTTYPE \|PWM Interrupt Type Selection
sahilmgandhi	18:6a4db94011d3	14005	* \| \| \|0 = PIF will be set if PWM counter underflow.
sahilmgandhi	18:6a4db94011d3	14006	* \| \| \|1 = PIF will be set if PWM counter matches EPWM_PERIOD register.
sahilmgandhi	18:6a4db94011d3	14007	* \| \| \|Note: This bit is effective when PWM in central align mode only.
sahilmgandhi	18:6a4db94011d3	14008	* \|[9] \|PINV \|Inverse PWM Comparator Output
sahilmgandhi	18:6a4db94011d3	14009	* \| \| \|When PINV is set to high the PWM comparator output signals will be inversed, therefore the PWM Duty (in percentage) is changed to (1-Duty) before PINV is set to high.
sahilmgandhi	18:6a4db94011d3	14010	* \| \| \|0 = Not inverse PWM comparator output.
sahilmgandhi	18:6a4db94011d3	14011	* \| \| \|1 = Inverse PWM comparator output.
sahilmgandhi	18:6a4db94011d3	14012	* \|[11] \|CNTCLR \|Clear PWM Counter Control
sahilmgandhi	18:6a4db94011d3	14013	* \| \| \|1 = Clear 16-bit PWM counter to 000H.
sahilmgandhi	18:6a4db94011d3	14014	* \| \| \|Note: It is automatically cleared by hardware.
sahilmgandhi	18:6a4db94011d3	14015	* \|[12] \|CNTTYPE \|PWM Aligned Type Selection
sahilmgandhi	18:6a4db94011d3	14016	* \| \| \|0 = Edge-aligned type.
sahilmgandhi	18:6a4db94011d3	14017	* \| \| \|1 = Centre-aligned type.
sahilmgandhi	18:6a4db94011d3	14018	* \|[13] \|GROUPEN \|Group Bit
sahilmgandhi	18:6a4db94011d3	14019	* \| \| \|0 = The signals timing of EPWM_CMPDAT0, EPWM_CMPDAT2 and EPWM_CMPDAT4 are independent.
sahilmgandhi	18:6a4db94011d3	14020	* \| \| \|1 = Unify the signals timing of EPWM_CMPDAT0, EPWM_CMPDAT2 and EPWM_CMPDAT4 in the same phase which is controlled by EPWM_CMPDAT0.
sahilmgandhi	18:6a4db94011d3	14021	* \|[14] \|BRKP0INV \|Inverse BKP0 State
sahilmgandhi	18:6a4db94011d3	14022	* \| \| \|0 = The state of pin BKPx0 is passed to the negative edge detector.
sahilmgandhi	18:6a4db94011d3	14023	* \| \| \|1 = The inversed state of pin BKPx0 is passed to the negative edge detector.
sahilmgandhi	18:6a4db94011d3	14024	* \|[15] \|BRKP1INV \|Inverse BKP1 State
sahilmgandhi	18:6a4db94011d3	14025	* \| \| \|0 = The state of pin BKPx1 is passed to the negative edge detector.
sahilmgandhi	18:6a4db94011d3	14026	* \| \| \|1 = The inversed state of pin BKPx1 is passed to the negative edge detector.
sahilmgandhi	18:6a4db94011d3	14027	* \|[16] \|BRKP0EN \|BKPx0 Pin Trigger Brake Function0 Enable Control
sahilmgandhi	18:6a4db94011d3	14028	* \| \| \|0 = PWMx Brake Function 0 Disabled.
sahilmgandhi	18:6a4db94011d3	14029	* \| \| \|1 = PWMx Brake Function 0 Enabled.
sahilmgandhi	18:6a4db94011d3	14030	* \| \| \|Note: x=0~1 for PWM unit0~1.
sahilmgandhi	18:6a4db94011d3	14031	* \|[17] \|BRKP1EN \|BKPx1 Pin Trigger Brake Function Enable Control
sahilmgandhi	18:6a4db94011d3	14032	* \| \| \|0 = PWMx Brake Function 1 Disabled.
sahilmgandhi	18:6a4db94011d3	14033	* \| \| \|1 = PWMx Brake Function 1 Enabled.
sahilmgandhi	18:6a4db94011d3	14034	* \| \| \|Note: x=0~1 for PWM unit0~1.
sahilmgandhi	18:6a4db94011d3	14035	* \|[18:19] \|BRK1SEL \|Brake Function 1 Source Selection
sahilmgandhi	18:6a4db94011d3	14036	* \| \| \|00 = From external pin BKPx1 (x=0~1 for unit0~1).
sahilmgandhi	18:6a4db94011d3	14037	* \| \| \|01 = From analog comparator 0 output (CPO0).
sahilmgandhi	18:6a4db94011d3	14038	* \| \| \|10 = From analog comparator 1 output (CPO1).
sahilmgandhi	18:6a4db94011d3	14039	* \| \| \|11 = From analog comparator 2 output (CPO2).
sahilmgandhi	18:6a4db94011d3	14040	* \|[20:21] \|BRK0NFSEL \|Brake 0 (BKPx0 Pin) Edge Detector Filter Clock Selection
sahilmgandhi	18:6a4db94011d3	14041	* \| \| \|00 = Filter clock = HCLK.
sahilmgandhi	18:6a4db94011d3	14042	* \| \| \|01 = Filter clock = HCLK/2.
sahilmgandhi	18:6a4db94011d3	14043	* \| \| \|10 = Filter clock = HCLK/4.
sahilmgandhi	18:6a4db94011d3	14044	* \| \| \|11 = Filter clock = HCLK/16.
sahilmgandhi	18:6a4db94011d3	14045	* \|[22:23] \|BRK1NFSEL \|Brake 1 (BKPx1 Pin) Edge Detector Filter Clock Selection
sahilmgandhi	18:6a4db94011d3	14046	* \| \| \|00 = Filter clock = HCLK.
sahilmgandhi	18:6a4db94011d3	14047	* \| \| \|01 =Filter clock = HCLK/2.
sahilmgandhi	18:6a4db94011d3	14048	* \| \| \|10 = Filter clock = HCLK/4.
sahilmgandhi	18:6a4db94011d3	14049	* \| \| \|11 = Filter clock = HCLK/16.
sahilmgandhi	18:6a4db94011d3	14050	* \|[24] \|CPO0BKEN \|CPO0 Digital Output As Brake0 Source Enable Control
sahilmgandhi	18:6a4db94011d3	14051	* \| \| \|1 = CPO0 as one brake source in Brake 0 Enabled.
sahilmgandhi	18:6a4db94011d3	14052	* \| \| \|0 = CPO0 as one brake source in Brake 0 Disabled.
sahilmgandhi	18:6a4db94011d3	14053	* \|[25] \|CPO1BKEN \|CPO1 Digital Output As Brake 0 Source Enable Control
sahilmgandhi	18:6a4db94011d3	14054	* \| \| \|0 = CPO1 as one brake source in Brake 0 Disabled.
sahilmgandhi	18:6a4db94011d3	14055	* \| \| \|1 = CPO1 as one brake source in Brake 0 Enabled.
sahilmgandhi	18:6a4db94011d3	14056	* \|[26] \|CPO2BKEN \|CPO2 Digital Output As Brake 0 Source Enable Control
sahilmgandhi	18:6a4db94011d3	14057	* \| \| \|0 = CPO2 as one brake source in Brake 0 Disabled.
sahilmgandhi	18:6a4db94011d3	14058	* \| \| \|1 = CPO2 as one brake source in Brake 0 Enabled.
sahilmgandhi	18:6a4db94011d3	14059	* \|[27] \|LVDBKEN \|Low-Level Detection Trigger PWM Brake Function 1 Enable Control
sahilmgandhi	18:6a4db94011d3	14060	* \| \| \|0 = Brake Function 1 triggered by Low-level detection Disabled.
sahilmgandhi	18:6a4db94011d3	14061	* \| \| \|1 = Brake Function 1 triggered by Low-level detection Enabled.
sahilmgandhi	18:6a4db94011d3	14062	* \|[28] \|BRK0NFDIS \|PWM Brake 0 Noise Filter Disable Control
sahilmgandhi	18:6a4db94011d3	14063	* \| \| \|0 = Noise filter of PWM Brake 0 Enabled.
sahilmgandhi	18:6a4db94011d3	14064	* \| \| \|1 = Noise filter of PWM Brake 0 Disabled.
sahilmgandhi	18:6a4db94011d3	14065	* \|[29] \|BRK1NFDIS \|PWM Brake 1 Noise Filter Disable Control
sahilmgandhi	18:6a4db94011d3	14066	* \| \| \|0 = Noise filter of PWM Brake 1 Enabled.
sahilmgandhi	18:6a4db94011d3	14067	* \| \| \|1 = Noise filter of PWM Brake 1 Disabled.
sahilmgandhi	18:6a4db94011d3	14068	* \|[31] \|CTRLD \|Center Reload Mode Enable Control
sahilmgandhi	18:6a4db94011d3	14069	* \| \| \|0 = EPWM reload duty register at the period point of PWM counter.
sahilmgandhi	18:6a4db94011d3	14070	* \| \| \|1 = EPWM reload duty register at the center point of PWM counter.
sahilmgandhi	18:6a4db94011d3	14071	* \| \| \|This bit only work when EPWM operation at center aligned mode.
sahilmgandhi	18:6a4db94011d3	14072	*/
sahilmgandhi	18:6a4db94011d3	14073	__IO uint32_t CTL;
sahilmgandhi	18:6a4db94011d3	14074
sahilmgandhi	18:6a4db94011d3	14075	/**
sahilmgandhi	18:6a4db94011d3	14076	* STATUS
sahilmgandhi	18:6a4db94011d3	14077	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14078	* Offset: 0x04 PWM Status Register
sahilmgandhi	18:6a4db94011d3	14079	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14080	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14081	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14082	* \|[0] \|BRKIF0 \|PWM Brake0 Flag
sahilmgandhi	18:6a4db94011d3	14083	* \| \| \|0 = PWM Brake 0 is able to poll falling signal at BKP0 and has not recognized any one.
sahilmgandhi	18:6a4db94011d3	14084	* \| \| \|1 = When PWM Brake 0 detects a falling signal at BKP0, this flag will be set to high.
sahilmgandhi	18:6a4db94011d3	14085	* \| \| \|Note: This bit must be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	14086	* \|[1] \|BRKIF1 \|PWM Brake1 Flag
sahilmgandhi	18:6a4db94011d3	14087	* \| \| \|0 = PWM Brake 1 is able to poll falling signal at BKP1 and has not recognized any one.
sahilmgandhi	18:6a4db94011d3	14088	* \| \| \|1 = When PWM Brake 1 detects a falling signal at pin BKP1, this flag will be set to high.
sahilmgandhi	18:6a4db94011d3	14089	* \| \| \|Note: This bit must be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	14090	* \|[2] \|PIF \|PWM Period Flag
sahilmgandhi	18:6a4db94011d3	14091	* \| \| \|0 = PWM Counter has not up counted to the value of PERIOD or down counted with underflow.
sahilmgandhi	18:6a4db94011d3	14092	* \| \| \|1 = Hardware will set this flag to high at the time of PWM Counter matches PERIOD in edge and Centre aligned modes or at the time of PWM Counter down counts with underflow in Centre aligned mode.
sahilmgandhi	18:6a4db94011d3	14093	* \| \| \|Note: This bit must be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	14094	* \|[4] \|EIF0 \|PWMx0 Edge Flag
sahilmgandhi	18:6a4db94011d3	14095	* \| \| \|0 = The PWMx0 doesn't toggle.
sahilmgandhi	18:6a4db94011d3	14096	* \| \| \|1 = Hardware will set this flag to high at the time of PWMx0 rising or falling.
sahilmgandhi	18:6a4db94011d3	14097	* \| \| \|If EINTTYPE0 = 0, this bit is set when PWMx0 falling is detected.
sahilmgandhi	18:6a4db94011d3	14098	* \| \| \|If EINTTYPE0 = 1, this bit is set when PWMx0 rising is detected.
sahilmgandhi	18:6a4db94011d3	14099	* \| \| \|Note: This bit must be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	14100	* \|[5] \|EIF2 \|PWMx2 Edge Flag
sahilmgandhi	18:6a4db94011d3	14101	* \| \| \|0 = The PWMx2 doesn't toggle.
sahilmgandhi	18:6a4db94011d3	14102	* \| \| \|1 = Hardware will set this flag to high at the time of PWMx2 rising or falling.
sahilmgandhi	18:6a4db94011d3	14103	* \| \| \|If EINTTYPE2 = 0, this bit is set when PWMx2 falling is detected.
sahilmgandhi	18:6a4db94011d3	14104	* \| \| \|If EINTTYPE2 = 1, this bit is set when PWMx2 rising is detected.
sahilmgandhi	18:6a4db94011d3	14105	* \| \| \|Note: This bit must be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	14106	* \|[6] \|EIF4 \|PWMx4 Edge Flag
sahilmgandhi	18:6a4db94011d3	14107	* \| \| \|0 = The PWMx4 doesn't toggle.
sahilmgandhi	18:6a4db94011d3	14108	* \| \| \|1 = Hardware will set this flag to high at the time of PWMx4 rising or falling.
sahilmgandhi	18:6a4db94011d3	14109	* \| \| \|If EINTTYPE4 = 0, this bit is set when PWMx4 falling is detected.
sahilmgandhi	18:6a4db94011d3	14110	* \| \| \|If EINTTYPE4 = 1, this bit is set when PWMx4 rising is detected.
sahilmgandhi	18:6a4db94011d3	14111	* \| \| \|Note: This bit must be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	14112	* \|[8] \|BRK0LOCK \|PWM Brake0 Locked
sahilmgandhi	18:6a4db94011d3	14113	* \| \| \|0 = Brake 0 state is released.
sahilmgandhi	18:6a4db94011d3	14114	* \| \| \|1 = When PWM Brake detects a falling signal at BKP0, this flag will be set to high to indicate the Brake0 state is locked.
sahilmgandhi	18:6a4db94011d3	14115	* \| \| \|Note: This bit must be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	14116	* \|[24] \|BRK0STS \|Brake 0 Status (Read Only)
sahilmgandhi	18:6a4db94011d3	14117	* \| \| \|0 = PWM had been out of Brake 0 state.
sahilmgandhi	18:6a4db94011d3	14118	* \| \| \|1 = PWM is in Brake 0 state.
sahilmgandhi	18:6a4db94011d3	14119	* \|[25] \|BRK1STS \|Brake 1 Status (Read Only)
sahilmgandhi	18:6a4db94011d3	14120	* \| \| \|0 = PWM had been out of Brake 1 state.
sahilmgandhi	18:6a4db94011d3	14121	* \| \| \|1 = PWM is in Brake 1 state.
sahilmgandhi	18:6a4db94011d3	14122	*/
sahilmgandhi	18:6a4db94011d3	14123	__IO uint32_t STATUS;
sahilmgandhi	18:6a4db94011d3	14124
sahilmgandhi	18:6a4db94011d3	14125	/**
sahilmgandhi	18:6a4db94011d3	14126	* PERIOD
sahilmgandhi	18:6a4db94011d3	14127	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14128	* Offset: 0x08 PWM Period Register
sahilmgandhi	18:6a4db94011d3	14129	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14130	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14131	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14132	* \|[0:15] \|PERIOD \|PWM Period Register
sahilmgandhi	18:6a4db94011d3	14133	* \| \| \|Edge aligned:
sahilmgandhi	18:6a4db94011d3	14134	* \| \| \|Period = (PERIOD + 1)* EPWMx_CLK period * pre-scalar.
sahilmgandhi	18:6a4db94011d3	14135	* \| \| \|Duty = (Duty +1 )* EPWMx_CLK period * pre-scalar.
sahilmgandhi	18:6a4db94011d3	14136	* \| \| \|Centre aligned:
sahilmgandhi	18:6a4db94011d3	14137	* \| \| \|Period = (PERIOD * 2)* EPWMx_CLK period * pre-scalar.
sahilmgandhi	18:6a4db94011d3	14138	* \| \| \|Duty = (Duty 2 + 1) EPWMx_CLK period * pre-scalar.
sahilmgandhi	18:6a4db94011d3	14139	*/
sahilmgandhi	18:6a4db94011d3	14140	__IO uint32_t PERIOD;
sahilmgandhi	18:6a4db94011d3	14141
sahilmgandhi	18:6a4db94011d3	14142	/**
sahilmgandhi	18:6a4db94011d3	14143	* CMPDAT0
sahilmgandhi	18:6a4db94011d3	14144	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14145	* Offset: 0x0C EPWM_CMPDAT0 Duty Register
sahilmgandhi	18:6a4db94011d3	14146	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14147	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14148	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14149	* \|[0:15] \|CMP \|PWM Duty Register
sahilmgandhi	18:6a4db94011d3	14150	* \| \| \|Edge aligned:
sahilmgandhi	18:6a4db94011d3	14151	* \| \| \|Period = (PERIOD + 1)* EPWMx_CLK period * pre-scalar.
sahilmgandhi	18:6a4db94011d3	14152	* \| \| \|Duty = (Duty +1 )* EPWMx_CLK period * pre-scalar.
sahilmgandhi	18:6a4db94011d3	14153	* \| \| \|Centre aligned:
sahilmgandhi	18:6a4db94011d3	14154	* \| \| \|Period = (PERIOD * 2)* EPWMx_CLK period * pre-scalar.
sahilmgandhi	18:6a4db94011d3	14155	* \| \| \|Duty = (Duty 2 + 1) EPWMx_CLK period * pre-scalar.
sahilmgandhi	18:6a4db94011d3	14156	*/
sahilmgandhi	18:6a4db94011d3	14157	__IO uint32_t CMPDAT0;
sahilmgandhi	18:6a4db94011d3	14158
sahilmgandhi	18:6a4db94011d3	14159	/**
sahilmgandhi	18:6a4db94011d3	14160	* CMPDAT2
sahilmgandhi	18:6a4db94011d3	14161	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14162	* Offset: 0x10 EPWM_CMPDAT2 Duty Register
sahilmgandhi	18:6a4db94011d3	14163	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14164	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14165	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14166	* \|[0:15] \|CMP \|PWM Duty Register
sahilmgandhi	18:6a4db94011d3	14167	* \| \| \|Edge aligned:
sahilmgandhi	18:6a4db94011d3	14168	* \| \| \|Period = (PERIOD + 1)* EPWMx_CLK period * pre-scalar.
sahilmgandhi	18:6a4db94011d3	14169	* \| \| \|Duty = (Duty +1 )* EPWMx_CLK period * pre-scalar.
sahilmgandhi	18:6a4db94011d3	14170	* \| \| \|Centre aligned:
sahilmgandhi	18:6a4db94011d3	14171	* \| \| \|Period = (PERIOD * 2)* EPWMx_CLK period * pre-scalar.
sahilmgandhi	18:6a4db94011d3	14172	* \| \| \|Duty = (Duty 2 + 1) EPWMx_CLK period * pre-scalar.
sahilmgandhi	18:6a4db94011d3	14173	*/
sahilmgandhi	18:6a4db94011d3	14174	__IO uint32_t CMPDAT2;
sahilmgandhi	18:6a4db94011d3	14175
sahilmgandhi	18:6a4db94011d3	14176	/**
sahilmgandhi	18:6a4db94011d3	14177	* CMPDAT4
sahilmgandhi	18:6a4db94011d3	14178	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14179	* Offset: 0x14 EPWM_CMPDAT4 Duty Register
sahilmgandhi	18:6a4db94011d3	14180	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14181	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14182	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14183	* \|[0:15] \|CMP \|PWM Duty Register
sahilmgandhi	18:6a4db94011d3	14184	* \| \| \|Edge aligned:
sahilmgandhi	18:6a4db94011d3	14185	* \| \| \|Period = (PERIOD + 1)* EPWMx_CLK period * pre-scalar.
sahilmgandhi	18:6a4db94011d3	14186	* \| \| \|Duty = (Duty +1 )* EPWMx_CLK period * pre-scalar.
sahilmgandhi	18:6a4db94011d3	14187	* \| \| \|Centre aligned:
sahilmgandhi	18:6a4db94011d3	14188	* \| \| \|Period = (PERIOD * 2)* EPWMx_CLK period * pre-scalar.
sahilmgandhi	18:6a4db94011d3	14189	* \| \| \|Duty = (Duty 2 + 1) EPWMx_CLK period * pre-scalar.
sahilmgandhi	18:6a4db94011d3	14190	*/
sahilmgandhi	18:6a4db94011d3	14191	__IO uint32_t CMPDAT4;
sahilmgandhi	18:6a4db94011d3	14192
sahilmgandhi	18:6a4db94011d3	14193	/**
sahilmgandhi	18:6a4db94011d3	14194	* MSKEN
sahilmgandhi	18:6a4db94011d3	14195	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14196	* Offset: 0x18 PWM Mask Mode Enable Control Register
sahilmgandhi	18:6a4db94011d3	14197	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14198	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14199	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14200	* \|[0:5] \|MSKEN \|PWM Mask Enable Control
sahilmgandhi	18:6a4db94011d3	14201	* \| \| \|The PWM generator signal will be masked when this bit is enabled.
sahilmgandhi	18:6a4db94011d3	14202	* \| \| \|The corresponding PWMn channel will be output with PMD.n data.
sahilmgandhi	18:6a4db94011d3	14203	* \| \| \|0 = PWM generator signal is output to next stage.
sahilmgandhi	18:6a4db94011d3	14204	* \| \| \|1 = PWM generator signal is masked and PMD.n is output to next stage.
sahilmgandhi	18:6a4db94011d3	14205	* \| \| \|Note: n = 0~5.
sahilmgandhi	18:6a4db94011d3	14206	*/
sahilmgandhi	18:6a4db94011d3	14207	__IO uint32_t MSKEN;
sahilmgandhi	18:6a4db94011d3	14208
sahilmgandhi	18:6a4db94011d3	14209	/**
sahilmgandhi	18:6a4db94011d3	14210	* MSK
sahilmgandhi	18:6a4db94011d3	14211	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14212	* Offset: 0x1C PWM Mask Mode Data Register
sahilmgandhi	18:6a4db94011d3	14213	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14214	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14215	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14216	* \|[0:5] \|MSKDAT \|PWM Mask Data Bit
sahilmgandhi	18:6a4db94011d3	14217	* \| \| \|This data bit control the state of PWMn output pin, if the corresponding PME.n = 1.
sahilmgandhi	18:6a4db94011d3	14218	* \| \| \|0 = Output logic low to PWMn.
sahilmgandhi	18:6a4db94011d3	14219	* \| \| \|1 = Output logic high to PWMn.
sahilmgandhi	18:6a4db94011d3	14220	* \| \| \|Note: n = 0~5.
sahilmgandhi	18:6a4db94011d3	14221	*/
sahilmgandhi	18:6a4db94011d3	14222	__IO uint32_t MSK;
sahilmgandhi	18:6a4db94011d3	14223
sahilmgandhi	18:6a4db94011d3	14224	/**
sahilmgandhi	18:6a4db94011d3	14225	* ASYMCMP0
sahilmgandhi	18:6a4db94011d3	14226	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14227	* Offset: 0x20 Asymmetric EPWM_CMPDAT0 Duty Register
sahilmgandhi	18:6a4db94011d3	14228	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14229	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14230	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14231	* \|[0:15] \|CMP \|Asymmetric PWM Duty Register
sahilmgandhi	18:6a4db94011d3	14232	* \| \| \|When the asymmetric PWM function is enabled, this 16-bit field determines the second time compared value after PWM counter has matched with PWM_Duty in the first half PWM cycle.
sahilmgandhi	18:6a4db94011d3	14233	*/
sahilmgandhi	18:6a4db94011d3	14234	__IO uint32_t ASYMCMP0;
sahilmgandhi	18:6a4db94011d3	14235
sahilmgandhi	18:6a4db94011d3	14236	/**
sahilmgandhi	18:6a4db94011d3	14237	* ASYMCMP2
sahilmgandhi	18:6a4db94011d3	14238	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14239	* Offset: 0x24 Asymmetric EPWM_CMPDAT2 Duty Register
sahilmgandhi	18:6a4db94011d3	14240	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14241	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14242	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14243	* \|[0:15] \|CMP \|Asymmetric PWM Duty Register
sahilmgandhi	18:6a4db94011d3	14244	* \| \| \|When the asymmetric PWM function is enabled, this 16-bit field determines the second time compared value after PWM counter has matched with PWM_Duty in the first half PWM cycle.
sahilmgandhi	18:6a4db94011d3	14245	*/
sahilmgandhi	18:6a4db94011d3	14246	__IO uint32_t ASYMCMP2;
sahilmgandhi	18:6a4db94011d3	14247
sahilmgandhi	18:6a4db94011d3	14248	/**
sahilmgandhi	18:6a4db94011d3	14249	* ASYMCMP4
sahilmgandhi	18:6a4db94011d3	14250	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14251	* Offset: 0x28 Asymmetric EPWM_CMPDAT4 Duty Register
sahilmgandhi	18:6a4db94011d3	14252	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14253	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14254	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14255	* \|[0:15] \|CMP \|Asymmetric PWM Duty Register
sahilmgandhi	18:6a4db94011d3	14256	* \| \| \|When the asymmetric PWM function is enabled, this 16-bit field determines the second time compared value after PWM counter has matched with PWM_Duty in the first half PWM cycle.
sahilmgandhi	18:6a4db94011d3	14257	*/
sahilmgandhi	18:6a4db94011d3	14258	__IO uint32_t ASYMCMP4;
sahilmgandhi	18:6a4db94011d3	14259
sahilmgandhi	18:6a4db94011d3	14260	/**
sahilmgandhi	18:6a4db94011d3	14261	* DTCTL
sahilmgandhi	18:6a4db94011d3	14262	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14263	* Offset: 0x2C PWM Dead-time Control Register
sahilmgandhi	18:6a4db94011d3	14264	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14265	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14266	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14267	* \|[0:10] \|DTCNT \|Dead-Time Counter
sahilmgandhi	18:6a4db94011d3	14268	* \| \| \|The dead-time can be calculated from the following formula:
sahilmgandhi	18:6a4db94011d3	14269	* \| \| \|Dead-time = EPWMx_CLK period * (DTCNT.[10:0]+1).
sahilmgandhi	18:6a4db94011d3	14270	* \|[16] \|DTEN0 \|Dead-Time Insertion Enable Control For PWMx Pair (PWM0, PWM1)
sahilmgandhi	18:6a4db94011d3	14271	* \| \| \|Dead-time insertion is only active when this pair of complementary PWM is enabled.
sahilmgandhi	18:6a4db94011d3	14272	* \| \| \|If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.
sahilmgandhi	18:6a4db94011d3	14273	* \| \| \|0 = Dead-time insertion Disabled on the pin pair (PWM0, PWM1).
sahilmgandhi	18:6a4db94011d3	14274	* \| \| \|1 = Dead-time insertion Enabled on the pin pair (PWM0, PWM1).
sahilmgandhi	18:6a4db94011d3	14275	* \| \| \|Note: x=0~1 for PWM unit0~1.
sahilmgandhi	18:6a4db94011d3	14276	* \|[17] \|DTEN2 \|Dead-Time Insertion Enable Control For PWMx Pair (PWM2, PWM3)
sahilmgandhi	18:6a4db94011d3	14277	* \| \| \|Dead-time insertion is only active when this pair of complementary PWM is enabled.
sahilmgandhi	18:6a4db94011d3	14278	* \| \| \|If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.
sahilmgandhi	18:6a4db94011d3	14279	* \| \| \|0 = Dead-time insertion Disabled on the pin pair (PWM2, PWM3).
sahilmgandhi	18:6a4db94011d3	14280	* \| \| \|1 = Dead-time insertion Enabled on the pin pair (PWM2, PWM3).
sahilmgandhi	18:6a4db94011d3	14281	* \| \| \|Note: x=0~1 for PWM unit0~1.
sahilmgandhi	18:6a4db94011d3	14282	* \|[18] \|DTEN4 \|Dead-Time Insertion Enable Control For PWMx Pair (PWM4, PWM5)
sahilmgandhi	18:6a4db94011d3	14283	* \| \| \|Dead-time insertion is only active when this pair of complementary PWM is enabled.
sahilmgandhi	18:6a4db94011d3	14284	* \| \| \|If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.
sahilmgandhi	18:6a4db94011d3	14285	* \| \| \|0 = Dead-time insertion Disabled on the pin pair (PWM4, PWM5).
sahilmgandhi	18:6a4db94011d3	14286	* \| \| \|1 = Dead-time insertion Enabled on the pin pair (PWM4, PWM5).
sahilmgandhi	18:6a4db94011d3	14287	* \| \| \|Note: x=0~1 for PWM unit0~1.
sahilmgandhi	18:6a4db94011d3	14288	*/
sahilmgandhi	18:6a4db94011d3	14289	__IO uint32_t DTCTL;
sahilmgandhi	18:6a4db94011d3	14290
sahilmgandhi	18:6a4db94011d3	14291	/**
sahilmgandhi	18:6a4db94011d3	14292	* BRKOUT
sahilmgandhi	18:6a4db94011d3	14293	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14294	* Offset: 0x30 PWM Brake Output
sahilmgandhi	18:6a4db94011d3	14295	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14296	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14297	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14298	* \|[0:5] \|BRKOUT \|PWM Brake Output
sahilmgandhi	18:6a4db94011d3	14299	* \| \| \|When PWM Brake is asserted, the PWM0~5 output state before polarity control will follow PWM1 bit0~5 setting, respectively.
sahilmgandhi	18:6a4db94011d3	14300	* \| \| \|0 = The PWMn output before polarity control is low when Brake is asserted.
sahilmgandhi	18:6a4db94011d3	14301	* \| \| \|1 = The PWMn output before polarity control is high when Brake is asserted.
sahilmgandhi	18:6a4db94011d3	14302	* \| \| \|Note: n = 0~5.
sahilmgandhi	18:6a4db94011d3	14303	*/
sahilmgandhi	18:6a4db94011d3	14304	__IO uint32_t BRKOUT;
sahilmgandhi	18:6a4db94011d3	14305
sahilmgandhi	18:6a4db94011d3	14306	/**
sahilmgandhi	18:6a4db94011d3	14307	* NPCTL
sahilmgandhi	18:6a4db94011d3	14308	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14309	* Offset: 0x34 PWM Negative Polarity Control
sahilmgandhi	18:6a4db94011d3	14310	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14311	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14312	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14313	* \|[0:5] \|NEGPOLAR \|PWM Negative Polarity Control
sahilmgandhi	18:6a4db94011d3	14314	* \| \| \|The register bit controls polarity/active state of real PWM output.
sahilmgandhi	18:6a4db94011d3	14315	* \| \| \|0 = PWMn output is active high.
sahilmgandhi	18:6a4db94011d3	14316	* \| \| \|1 = PWMn output is active low.
sahilmgandhi	18:6a4db94011d3	14317	* \| \| \|Note: n = 0~5.
sahilmgandhi	18:6a4db94011d3	14318	*/
sahilmgandhi	18:6a4db94011d3	14319	__IO uint32_t NPCTL;
sahilmgandhi	18:6a4db94011d3	14320
sahilmgandhi	18:6a4db94011d3	14321	/**
sahilmgandhi	18:6a4db94011d3	14322	* ASYMCTL
sahilmgandhi	18:6a4db94011d3	14323	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14324	* Offset: 0x38 Asymmetric PWM Control Register
sahilmgandhi	18:6a4db94011d3	14325	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14326	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14327	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14328	* \|[0] \|ASYMEN \|Asymmetric PWM Enable Control
sahilmgandhi	18:6a4db94011d3	14329	* \| \| \|0 = Asymmetric PWM function Disabled.
sahilmgandhi	18:6a4db94011d3	14330	* \| \| \|1 = Asymmetric PWM function Enabled.
sahilmgandhi	18:6a4db94011d3	14331	* \| \| \|Note: This control bit is only valid when PWM module is set in Centre-aligned mode.
sahilmgandhi	18:6a4db94011d3	14332	* \|[8:9] \|ASYMMODE0 \|Asymmetric PWMx0 Reload Mode Setting
sahilmgandhi	18:6a4db94011d3	14333	* \| \| \|00 = 1. PWM compare register 0 is reload PWM_Duty (PWMx0[15:0]) at PWM cycle start.
sahilmgandhi	18:6a4db94011d3	14334	* \| \| \| 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 0 in up-counting cycle
sahilmgandhi	18:6a4db94011d3	14335	* \| \| \|3.
sahilmgandhi	18:6a4db94011d3	14336	* \| \| \|PWM compare output toggles at compare match, in the meanwhile, PWM compare register 0 is reloaded with CMP (ASPWMx0[15:00]).
sahilmgandhi	18:6a4db94011d3	14337	* \| \| \| 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 0 in down-counting cycle.
sahilmgandhi	18:6a4db94011d3	14338	* \| \| \|01 = 1. PWM compare register 0 is reload PWM_Duty (PWMx0[15:0]) at PWM cycle start.
sahilmgandhi	18:6a4db94011d3	14339	* \| \| \| 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 0 in up-counting cycle
sahilmgandhi	18:6a4db94011d3	14340	* \| \| \|3.
sahilmgandhi	18:6a4db94011d3	14341	* \| \| \|PWM compare output toggles at compare match, in the meanwhile, PWM compare register 0 is reloaded with CMP (ASPWMx0[15:00]).
sahilmgandhi	18:6a4db94011d3	14342	* \| \| \| 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 0 in up-counting cycle.
sahilmgandhi	18:6a4db94011d3	14343	* \| \| \| 5. PWMx0 must be less than ASPWMx0
sahilmgandhi	18:6a4db94011d3	14344	* \| \| \|10 = 1. PWM compare register 0 is reload PWM_Duty (PWMx0[15:0]) at PWM cycle start.
sahilmgandhi	18:6a4db94011d3	14345	* \| \| \| 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 0 in down-counting cycle
sahilmgandhi	18:6a4db94011d3	14346	* \| \| \|3.
sahilmgandhi	18:6a4db94011d3	14347	* \| \| \|PWM compare output toggles at compare match, in the meanwhile, PWM compare register 0 is reloaded with CMP (ASPWMx0[15:00]).
sahilmgandhi	18:6a4db94011d3	14348	* \| \| \| 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 0 in down-counting cycle.
sahilmgandhi	18:6a4db94011d3	14349	* \| \| \| 5. PWMx0 must be greater than ASPWMx0.
sahilmgandhi	18:6a4db94011d3	14350	* \| \| \|11 = Reserved.
sahilmgandhi	18:6a4db94011d3	14351	* \| \| \|Note1: x=0~1 for PWM unit 0~1.
sahilmgandhi	18:6a4db94011d3	14352	* \| \| \|Note2: This bit field is available only when ASYMEN=1.
sahilmgandhi	18:6a4db94011d3	14353	* \| \| \|Note3: The setting will be effected at the condition of LOAD=1 and from the start of next PWM cycle.
sahilmgandhi	18:6a4db94011d3	14354	* \|[16:17] \|ASYMMODE2 \|Asymmetric PWMx2 Reload Mode Setting
sahilmgandhi	18:6a4db94011d3	14355	* \| \| \|00 = 1. PWM compare register 2 is reload PWM_Duty (PWMx2[15:0]) at PWM cycle start.
sahilmgandhi	18:6a4db94011d3	14356	* \| \| \| 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 2 in up-counting cycle
sahilmgandhi	18:6a4db94011d3	14357	* \| \| \|3.
sahilmgandhi	18:6a4db94011d3	14358	* \| \| \|PWM compare output toggles at compare match, in the meanwhile, PWM compare register 2 is reloaded with CMP (ASPWMx2[15:00]).
sahilmgandhi	18:6a4db94011d3	14359	* \| \| \| 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 2 in down-counting cycle.
sahilmgandhi	18:6a4db94011d3	14360	* \| \| \|01 = 1. PWM compare register 2 is reload PWM_Duty (PWMx2[15:0]) at PWM cycle start.
sahilmgandhi	18:6a4db94011d3	14361	* \| \| \| 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 2 in up-counting cycle
sahilmgandhi	18:6a4db94011d3	14362	* \| \| \|3.
sahilmgandhi	18:6a4db94011d3	14363	* \| \| \|PWM compare output toggles at compare match, in the meanwhile, PWM compare register2 is reloaded with CMP (ASPWMx2[15:00]).
sahilmgandhi	18:6a4db94011d3	14364	* \| \| \| 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 2 in up-counting cycle.
sahilmgandhi	18:6a4db94011d3	14365	* \| \| \| 5. PWMx2 must be less than ASPWMx2
sahilmgandhi	18:6a4db94011d3	14366	* \| \| \|10 = 1. PWM compare register 2 is reload PWM_Duty (PWMx2[15:0]) at PWM cycle start.
sahilmgandhi	18:6a4db94011d3	14367	* \| \| \| 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 2 in down-counting cycle
sahilmgandhi	18:6a4db94011d3	14368	* \| \| \|3.
sahilmgandhi	18:6a4db94011d3	14369	* \| \| \|PWM compare output toggles at compare match, in the meanwhile, PWM compare register 2 is reloaded with CMP (ASPWMx2[15:00]).
sahilmgandhi	18:6a4db94011d3	14370	* \| \| \| 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 2 in down-counting cycle.
sahilmgandhi	18:6a4db94011d3	14371	* \| \| \| 5. PWMx2 must be greater than ASPWMx2.
sahilmgandhi	18:6a4db94011d3	14372	* \| \| \|11 = Reserved.
sahilmgandhi	18:6a4db94011d3	14373	* \| \| \|Note1: x=0~1 for PWM unit 0~1.
sahilmgandhi	18:6a4db94011d3	14374	* \| \| \|Note2: This bit field is available only when ASYMEN=1.
sahilmgandhi	18:6a4db94011d3	14375	* \| \| \|Note3: The setting will be effected at the condition of LOAD=1 and from the start of next PWM cycle.
sahilmgandhi	18:6a4db94011d3	14376	* \|[24:25] \|ASYMMODE4 \|Asymmetric PWMx4 Reload Mode Setting
sahilmgandhi	18:6a4db94011d3	14377	* \| \| \|00 = 1. PWM compare register 4 is reload PWM_Duty (PWMx4[15:0]) at PWM cycle start.
sahilmgandhi	18:6a4db94011d3	14378	* \| \| \| 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 4 in up-counting cycle
sahilmgandhi	18:6a4db94011d3	14379	* \| \| \|3.
sahilmgandhi	18:6a4db94011d3	14380	* \| \| \|PWM compare output toggles at compare match, in the meanwhile, PWM compare register 4 is reloaded with CMP (ASPWMx4[15:00]).
sahilmgandhi	18:6a4db94011d3	14381	* \| \| \| 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 4 in down-counting cycle.
sahilmgandhi	18:6a4db94011d3	14382	* \| \| \|01 = 1. PWM compare register 4 is reload PWM_Duty (PWMx4[15:0]) at PWM cycle start.
sahilmgandhi	18:6a4db94011d3	14383	* \| \| \| 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 4 in up-counting cycle
sahilmgandhi	18:6a4db94011d3	14384	* \| \| \|3.
sahilmgandhi	18:6a4db94011d3	14385	* \| \| \|PWM compare output toggles at compare match, in the meanwhile, PWM compare register 0 is reloaded with CMP (ASPWMx4[15:00]).
sahilmgandhi	18:6a4db94011d3	14386	* \| \| \| 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 4 in up-counting cycle.
sahilmgandhi	18:6a4db94011d3	14387	* \| \| \| 5. PWMx4 must be less than ASPWMx4.
sahilmgandhi	18:6a4db94011d3	14388	* \| \| \|10 = 1. PWM compare register 4 is reload PWM_Duty (PWMx4[15:0]) at PWM cycle start.
sahilmgandhi	18:6a4db94011d3	14389	* \| \| \| 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 4 in down-counting cycle
sahilmgandhi	18:6a4db94011d3	14390	* \| \| \|3.
sahilmgandhi	18:6a4db94011d3	14391	* \| \| \|PWM compare output toggles at compare match, in the meanwhile, PWM compare register 4 is reloaded with CMP (ASPWMx4[15:00]).
sahilmgandhi	18:6a4db94011d3	14392	* \| \| \| 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 4 in down-counting cycle.
sahilmgandhi	18:6a4db94011d3	14393	* \| \| \| 5. PWMx4 must be greater than ASPWMx4.
sahilmgandhi	18:6a4db94011d3	14394	* \| \| \|11= Reserved.
sahilmgandhi	18:6a4db94011d3	14395	* \| \| \|Note1: x=0~1 for PWM unit 0~1.
sahilmgandhi	18:6a4db94011d3	14396	* \| \| \|Note2: This bit field is available only when ASYMEN=1.
sahilmgandhi	18:6a4db94011d3	14397	* \| \| \|Note3: The setting will be effected at the condition of LOAD=1 and from the start of next PWM cycle.
sahilmgandhi	18:6a4db94011d3	14398	*/
sahilmgandhi	18:6a4db94011d3	14399	__IO uint32_t ASYMCTL;
sahilmgandhi	18:6a4db94011d3	14400
sahilmgandhi	18:6a4db94011d3	14401	/**
sahilmgandhi	18:6a4db94011d3	14402	* PERIODCNT
sahilmgandhi	18:6a4db94011d3	14403	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14404	* Offset: 0x3C PIF Compared Counter
sahilmgandhi	18:6a4db94011d3	14405	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14406	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14407	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14408	* \|[0:3] \|PERIODCNT \|PIF Compared Counter
sahilmgandhi	18:6a4db94011d3	14409	* \| \| \|The register sets the count number which defines how many times of PWM period occurs to set bit PIF to request the PWM period interrupt.
sahilmgandhi	18:6a4db94011d3	14410	* \| \| \|PIF will be set in every (1 + PERIODCNT[3:0]) times of PWM period or center point defined by INTTYPE when EPWM_CTL [8] occurred.
sahilmgandhi	18:6a4db94011d3	14411	*/
sahilmgandhi	18:6a4db94011d3	14412	__IO uint32_t PERIODCNT;
sahilmgandhi	18:6a4db94011d3	14413
sahilmgandhi	18:6a4db94011d3	14414	/**
sahilmgandhi	18:6a4db94011d3	14415	* EINTCTL
sahilmgandhi	18:6a4db94011d3	14416	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14417	* Offset: 0x40 PWM Edge Interrupt Control Register
sahilmgandhi	18:6a4db94011d3	14418	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14419	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14420	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14421	* \|[0] \|EDGEIEN0 \|PWMx0 Edge Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	14422	* \| \| \|0 = Disabling flag EIF0 to trigger PWM interrupt.
sahilmgandhi	18:6a4db94011d3	14423	* \| \| \|1 = Enabling flag EIF0 can trigger PWM interrupt.
sahilmgandhi	18:6a4db94011d3	14424	* \|[1] \|EDGEIEN2 \|PWMx2 Edge Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	14425	* \| \| \|0 = Disabling flag EIF2 can trigger PWM interrupt.
sahilmgandhi	18:6a4db94011d3	14426	* \| \| \|1 = Enabling flag EIF2 can trigger PWM interrupt.
sahilmgandhi	18:6a4db94011d3	14427	* \|[2] \|EDGEIEN4 \|PWMx4 Edge Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	14428	* \| \| \|0 = Disable flag EIF4 to trigger PWM interrupt.
sahilmgandhi	18:6a4db94011d3	14429	* \| \| \|1 = Enabling flag EIF4 can trigger PWM interrupt.
sahilmgandhi	18:6a4db94011d3	14430	* \|[8] \|EINTTYPE0 \|PWMx0 Edge Interrupt Type
sahilmgandhi	18:6a4db94011d3	14431	* \| \| \|0 = EIF0 will be set if falling edge is detected at PWMx0.
sahilmgandhi	18:6a4db94011d3	14432	* \| \| \|1 = EIF0 will be set if rising edge is detected at PWMx0.
sahilmgandhi	18:6a4db94011d3	14433	* \|[9] \|EINTTYPE2 \|PWMx2 Edge Interrupt Type
sahilmgandhi	18:6a4db94011d3	14434	* \| \| \|0 = EIF2 will be set if falling edge is detected at PWMx2.
sahilmgandhi	18:6a4db94011d3	14435	* \| \| \|1 = EIF2 will be set if rising edge is detected at PWMx2.
sahilmgandhi	18:6a4db94011d3	14436	* \|[10] \|EINTTYPE4 \|PWMx4 Edge Interrupt Type
sahilmgandhi	18:6a4db94011d3	14437	* \| \| \|0 = EIF4 will be set if falling edge is detected at PWMx4.
sahilmgandhi	18:6a4db94011d3	14438	* \| \| \|1 = EIF4 will be set if rising edge is detected at PWMx4.
sahilmgandhi	18:6a4db94011d3	14439	*/
sahilmgandhi	18:6a4db94011d3	14440	__IO uint32_t EINTCTL;
sahilmgandhi	18:6a4db94011d3	14441
sahilmgandhi	18:6a4db94011d3	14442	/**
sahilmgandhi	18:6a4db94011d3	14443	* OUTEN0
sahilmgandhi	18:6a4db94011d3	14444	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14445	* Offset: 0x44 PWM Output Enable Control Register
sahilmgandhi	18:6a4db94011d3	14446	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14447	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14448	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14449	* \|[0] \|EVENOUTEN \|PWM Even Ports Output Enable Control
sahilmgandhi	18:6a4db94011d3	14450	* \| \| \|0 = PWM even ports output Disabled (PWM even ports at tri-state).
sahilmgandhi	18:6a4db94011d3	14451	* \| \| \|1 = PWM even ports output Enabled.
sahilmgandhi	18:6a4db94011d3	14452	* \|[1] \|ODDOUTEN \|PWM Odd Ports Output Enable Control
sahilmgandhi	18:6a4db94011d3	14453	* \| \| \|0 = PWM odd ports output Disabled (PWM even ports at tri-state).
sahilmgandhi	18:6a4db94011d3	14454	* \| \| \|1 = PWM odd ports output Enabled.
sahilmgandhi	18:6a4db94011d3	14455	*/
sahilmgandhi	18:6a4db94011d3	14456	__IO uint32_t OUTEN0;
sahilmgandhi	18:6a4db94011d3	14457
sahilmgandhi	18:6a4db94011d3	14458	} EPWM_T;
sahilmgandhi	18:6a4db94011d3	14459
sahilmgandhi	18:6a4db94011d3	14460	/**
sahilmgandhi	18:6a4db94011d3	14461	@addtogroup EPWM_CONST EPWM Bit Field Definition
sahilmgandhi	18:6a4db94011d3	14462	Constant Definitions for EPWM Controller
sahilmgandhi	18:6a4db94011d3	14463	@{ */
sahilmgandhi	18:6a4db94011d3	14464
sahilmgandhi	18:6a4db94011d3	14465	#define EPWM_CTL_MODE_Pos (0) /!< EPWM CTL: MODE Position /
sahilmgandhi	18:6a4db94011d3	14466	#define EPWM_CTL_MODE_Msk (0x3ul << EPWM_CTL_MODE_Pos) /!< EPWM CTL: MODE Mask /
sahilmgandhi	18:6a4db94011d3	14467
sahilmgandhi	18:6a4db94011d3	14468	#define EPWM_CTL_CLKDIV_Pos (2) /!< EPWM CTL: CLKDIV Position /
sahilmgandhi	18:6a4db94011d3	14469	#define EPWM_CTL_CLKDIV_Msk (0x3ul << EPWM_CTL_CLKDIV_Pos) /!< EPWM CTL: CLKDIV Mask /
sahilmgandhi	18:6a4db94011d3	14470
sahilmgandhi	18:6a4db94011d3	14471	#define EPWM_CTL_PWMIEN_Pos (4) /!< EPWM CTL: PWMIEN Position /
sahilmgandhi	18:6a4db94011d3	14472	#define EPWM_CTL_PWMIEN_Msk (0x1ul << EPWM_CTL_PWMIEN_Pos) /!< EPWM CTL: PWMIEN Mask /
sahilmgandhi	18:6a4db94011d3	14473
sahilmgandhi	18:6a4db94011d3	14474	#define EPWM_CTL_BRKIEN_Pos (5) /!< EPWM CTL: BRKIEN Position /
sahilmgandhi	18:6a4db94011d3	14475	#define EPWM_CTL_BRKIEN_Msk (0x1ul << EPWM_CTL_BRKIEN_Pos) /!< EPWM CTL: BRKIEN Mask /
sahilmgandhi	18:6a4db94011d3	14476
sahilmgandhi	18:6a4db94011d3	14477	#define EPWM_CTL_LOAD_Pos (6) /!< EPWM CTL: LOAD Position /
sahilmgandhi	18:6a4db94011d3	14478	#define EPWM_CTL_LOAD_Msk (0x1ul << EPWM_CTL_LOAD_Pos) /!< EPWM CTL: LOAD Mask /
sahilmgandhi	18:6a4db94011d3	14479
sahilmgandhi	18:6a4db94011d3	14480	#define EPWM_CTL_CNTEN_Pos (7) /!< EPWM CTL: CNTEN Position /
sahilmgandhi	18:6a4db94011d3	14481	#define EPWM_CTL_CNTEN_Msk (0x1ul << EPWM_CTL_CNTEN_Pos) /!< EPWM CTL: CNTEN Mask /
sahilmgandhi	18:6a4db94011d3	14482
sahilmgandhi	18:6a4db94011d3	14483	#define EPWM_CTL_INTTYPE_Pos (8) /!< EPWM CTL: INTTYPE Position /
sahilmgandhi	18:6a4db94011d3	14484	#define EPWM_CTL_INTTYPE_Msk (0x1ul << EPWM_CTL_INTTYPE_Pos) /!< EPWM CTL: INTTYPE Mask /
sahilmgandhi	18:6a4db94011d3	14485
sahilmgandhi	18:6a4db94011d3	14486	#define EPWM_CTL_PINV_Pos (9) /!< EPWM CTL: PINV Position /
sahilmgandhi	18:6a4db94011d3	14487	#define EPWM_CTL_PINV_Msk (0x1ul << EPWM_CTL_PINV_Pos) /!< EPWM CTL: PINV Mask /
sahilmgandhi	18:6a4db94011d3	14488
sahilmgandhi	18:6a4db94011d3	14489	#define EPWM_CTL_CNTCLR_Pos (11) /!< EPWM CTL: CNTCLR Position /
sahilmgandhi	18:6a4db94011d3	14490	#define EPWM_CTL_CNTCLR_Msk (0x1ul << EPWM_CTL_CNTCLR_Pos) /!< EPWM CTL: CNTCLR Mask /
sahilmgandhi	18:6a4db94011d3	14491
sahilmgandhi	18:6a4db94011d3	14492	#define EPWM_CTL_CNTTYPE_Pos (12) /!< EPWM CTL: CNTTYPE Position /
sahilmgandhi	18:6a4db94011d3	14493	#define EPWM_CTL_CNTTYPE_Msk (0x1ul << EPWM_CTL_CNTTYPE_Pos) /!< EPWM CTL: CNTTYPE Mask /
sahilmgandhi	18:6a4db94011d3	14494
sahilmgandhi	18:6a4db94011d3	14495	#define EPWM_CTL_GROUPEN_Pos (13) /!< EPWM CTL: GROUPEN Position /
sahilmgandhi	18:6a4db94011d3	14496	#define EPWM_CTL_GROUPEN_Msk (0x1ul << EPWM_CTL_GROUPEN_Pos) /!< EPWM CTL: GROUPEN Mask /
sahilmgandhi	18:6a4db94011d3	14497
sahilmgandhi	18:6a4db94011d3	14498	#define EPWM_CTL_BRKP0INV_Pos (14) /!< EPWM CTL: BRKP0INV Position /
sahilmgandhi	18:6a4db94011d3	14499	#define EPWM_CTL_BRKP0INV_Msk (0x1ul << EPWM_CTL_BRKP0INV_Pos) /!< EPWM CTL: BRKP0INV Mask /
sahilmgandhi	18:6a4db94011d3	14500
sahilmgandhi	18:6a4db94011d3	14501	#define EPWM_CTL_BRKP1INV_Pos (15) /!< EPWM CTL: BRKP1INV Position /
sahilmgandhi	18:6a4db94011d3	14502	#define EPWM_CTL_BRKP1INV_Msk (0x1ul << EPWM_CTL_BRKP1INV_Pos) /!< EPWM CTL: BRKP1INV Mask /
sahilmgandhi	18:6a4db94011d3	14503
sahilmgandhi	18:6a4db94011d3	14504	#define EPWM_CTL_BRKP0EN_Pos (16) /!< EPWM CTL: BRKP0EN Position /
sahilmgandhi	18:6a4db94011d3	14505	#define EPWM_CTL_BRKP0EN_Msk (0x1ul << EPWM_CTL_BRKP0EN_Pos) /!< EPWM CTL: BRKP0EN Mask /
sahilmgandhi	18:6a4db94011d3	14506
sahilmgandhi	18:6a4db94011d3	14507	#define EPWM_CTL_BRKP1EN_Pos (17) /!< EPWM CTL: BRKP1EN Position /
sahilmgandhi	18:6a4db94011d3	14508	#define EPWM_CTL_BRKP1EN_Msk (0x1ul << EPWM_CTL_BRKP1EN_Pos) /!< EPWM CTL: BRKP1EN Mask /
sahilmgandhi	18:6a4db94011d3	14509
sahilmgandhi	18:6a4db94011d3	14510	#define EPWM_CTL_BRK1SEL_Pos (18) /!< EPWM CTL: BRK1SEL Position /
sahilmgandhi	18:6a4db94011d3	14511	#define EPWM_CTL_BRK1SEL_Msk (0x3ul << EPWM_CTL_BRK1SEL_Pos) /!< EPWM CTL: BRK1SEL Mask /
sahilmgandhi	18:6a4db94011d3	14512
sahilmgandhi	18:6a4db94011d3	14513	#define EPWM_CTL_BRK0NFSEL_Pos (20) /!< EPWM CTL: BRK0NFSEL Position /
sahilmgandhi	18:6a4db94011d3	14514	#define EPWM_CTL_BRK0NFSEL_Msk (0x3ul << EPWM_CTL_BRK0NFSEL_Pos) /!< EPWM CTL: BRK0NFSEL Mask /
sahilmgandhi	18:6a4db94011d3	14515
sahilmgandhi	18:6a4db94011d3	14516	#define EPWM_CTL_BRK1NFSEL_Pos (22) /!< EPWM CTL: BRK1NFSEL Position /
sahilmgandhi	18:6a4db94011d3	14517	#define EPWM_CTL_BRK1NFSEL_Msk (0x3ul << EPWM_CTL_BRK1NFSEL_Pos) /!< EPWM CTL: BRK1NFSEL Mask /
sahilmgandhi	18:6a4db94011d3	14518
sahilmgandhi	18:6a4db94011d3	14519	#define EPWM_CTL_CPO0BKEN_Pos (24) /!< EPWM CTL: CPO0BKEN Position /
sahilmgandhi	18:6a4db94011d3	14520	#define EPWM_CTL_CPO0BKEN_Msk (0x1ul << EPWM_CTL_CPO0BKEN_Pos) /!< EPWM CTL: CPO0BKEN Mask /
sahilmgandhi	18:6a4db94011d3	14521
sahilmgandhi	18:6a4db94011d3	14522	#define EPWM_CTL_CPO1BKEN_Pos (25) /!< EPWM CTL: CPO1BKEN Position /
sahilmgandhi	18:6a4db94011d3	14523	#define EPWM_CTL_CPO1BKEN_Msk (0x1ul << EPWM_CTL_CPO1BKEN_Pos) /!< EPWM CTL: CPO1BKEN Mask /
sahilmgandhi	18:6a4db94011d3	14524
sahilmgandhi	18:6a4db94011d3	14525	#define EPWM_CTL_CPO2BKEN_Pos (26) /!< EPWM CTL: CPO2BKEN Position /
sahilmgandhi	18:6a4db94011d3	14526	#define EPWM_CTL_CPO2BKEN_Msk (0x1ul << EPWM_CTL_CPO2BKEN_Pos) /!< EPWM CTL: CPO2BKEN Mask /
sahilmgandhi	18:6a4db94011d3	14527
sahilmgandhi	18:6a4db94011d3	14528	#define EPWM_CTL_LVDBKEN_Pos (27) /!< EPWM CTL: LVDBKEN Position /
sahilmgandhi	18:6a4db94011d3	14529	#define EPWM_CTL_LVDBKEN_Msk (0x1ul << EPWM_CTL_LVDBKEN_Pos) /!< EPWM CTL: LVDBKEN Mask /
sahilmgandhi	18:6a4db94011d3	14530
sahilmgandhi	18:6a4db94011d3	14531	#define EPWM_CTL_BRK0NFDIS_Pos (28) /!< EPWM CTL: BRK0NFDIS Position /
sahilmgandhi	18:6a4db94011d3	14532	#define EPWM_CTL_BRK0NFDIS_Msk (0x1ul << EPWM_CTL_BRK0NFDIS_Pos) /!< EPWM CTL: BRK0NFDIS Mask /
sahilmgandhi	18:6a4db94011d3	14533
sahilmgandhi	18:6a4db94011d3	14534	#define EPWM_CTL_BRK1NFDIS_Pos (29) /!< EPWM CTL: BRK1NFDIS Position /
sahilmgandhi	18:6a4db94011d3	14535	#define EPWM_CTL_BRK1NFDIS_Msk (0x1ul << EPWM_CTL_BRK1NFDIS_Pos) /!< EPWM CTL: BRK1NFDIS Mask /
sahilmgandhi	18:6a4db94011d3	14536
sahilmgandhi	18:6a4db94011d3	14537	#define EPWM_CTL_CTRLD_Pos (31) /!< EPWM CTL: CTRLD Position /
sahilmgandhi	18:6a4db94011d3	14538	#define EPWM_CTL_CTRLD_Msk (0x1ul << EPWM_CTL_CTRLD_Pos) /!< EPWM CTL: CTRLD Mask /
sahilmgandhi	18:6a4db94011d3	14539
sahilmgandhi	18:6a4db94011d3	14540	#define EPWM_STATUS_BRKIF0_Pos (0) /!< EPWM STATUS: BRKIF0 Position /
sahilmgandhi	18:6a4db94011d3	14541	#define EPWM_STATUS_BRKIF0_Msk (0x1ul << EPWM_STATUS_BRKIF0_Pos) /!< EPWM STATUS: BRKIF0 Mask /
sahilmgandhi	18:6a4db94011d3	14542
sahilmgandhi	18:6a4db94011d3	14543	#define EPWM_STATUS_BRKIF1_Pos (1) /!< EPWM STATUS: BRKIF1 Position /
sahilmgandhi	18:6a4db94011d3	14544	#define EPWM_STATUS_BRKIF1_Msk (0x1ul << EPWM_STATUS_BRKIF1_Pos) /!< EPWM STATUS: BRKIF1 Mask /
sahilmgandhi	18:6a4db94011d3	14545
sahilmgandhi	18:6a4db94011d3	14546	#define EPWM_STATUS_PIF_Pos (2) /!< EPWM STATUS: PIF Position /
sahilmgandhi	18:6a4db94011d3	14547	#define EPWM_STATUS_PIF_Msk (0x1ul << EPWM_STATUS_PIF_Pos) /!< EPWM STATUS: PIF Mask /
sahilmgandhi	18:6a4db94011d3	14548
sahilmgandhi	18:6a4db94011d3	14549	#define EPWM_STATUS_EIF0_Pos (4) /!< EPWM STATUS: EIF0 Position /
sahilmgandhi	18:6a4db94011d3	14550	#define EPWM_STATUS_EIF0_Msk (0x1ul << EPWM_STATUS_EIF0_Pos) /!< EPWM STATUS: EIF0 Mask /
sahilmgandhi	18:6a4db94011d3	14551
sahilmgandhi	18:6a4db94011d3	14552	#define EPWM_STATUS_EIF2_Pos (5) /!< EPWM STATUS: EIF2 Position /
sahilmgandhi	18:6a4db94011d3	14553	#define EPWM_STATUS_EIF2_Msk (0x1ul << EPWM_STATUS_EIF2_Pos) /!< EPWM STATUS: EIF2 Mask /
sahilmgandhi	18:6a4db94011d3	14554
sahilmgandhi	18:6a4db94011d3	14555	#define EPWM_STATUS_EIF4_Pos (6) /!< EPWM STATUS: EIF4 Position /
sahilmgandhi	18:6a4db94011d3	14556	#define EPWM_STATUS_EIF4_Msk (0x1ul << EPWM_STATUS_EIF4_Pos) /!< EPWM STATUS: EIF4 Mask /
sahilmgandhi	18:6a4db94011d3	14557
sahilmgandhi	18:6a4db94011d3	14558	#define EPWM_STATUS_BRK0LOCK_Pos (8) /!< EPWM STATUS: BRK0LOCK Position /
sahilmgandhi	18:6a4db94011d3	14559	#define EPWM_STATUS_BRK0LOCK_Msk (0x1ul << EPWM_STATUS_BRK0LOCK_Pos) /!< EPWM STATUS: BRK0LOCK Mask /
sahilmgandhi	18:6a4db94011d3	14560
sahilmgandhi	18:6a4db94011d3	14561	#define EPWM_STATUS_BRK0STS_Pos (24) /!< EPWM STATUS: BRK0STS Position /
sahilmgandhi	18:6a4db94011d3	14562	#define EPWM_STATUS_BRK0STS_Msk (0x1ul << EPWM_STATUS_BRK0STS_Pos) /!< EPWM STATUS: BRK0STS Mask /
sahilmgandhi	18:6a4db94011d3	14563
sahilmgandhi	18:6a4db94011d3	14564	#define EPWM_STATUS_BRK1STS_Pos (25) /!< EPWM STATUS: BRK1STS Position /
sahilmgandhi	18:6a4db94011d3	14565	#define EPWM_STATUS_BRK1STS_Msk (0x1ul << EPWM_STATUS_BRK1STS_Pos) /!< EPWM STATUS: BRK1STS Mask /
sahilmgandhi	18:6a4db94011d3	14566
sahilmgandhi	18:6a4db94011d3	14567	#define EPWM_PERIOD_PERIOD_Pos (0) /!< EPWM PERIOD: PERIOD Position /
sahilmgandhi	18:6a4db94011d3	14568	#define EPWM_PERIOD_PERIOD_Msk (0xfffful << EPWM_PERIOD_PERIOD_Pos) /!< EPWM PERIOD: PERIOD Mask /
sahilmgandhi	18:6a4db94011d3	14569
sahilmgandhi	18:6a4db94011d3	14570	#define EPWM_CMPDAT0_CMP_Pos (0) /!< EPWM CMPDAT0: CMP Position /
sahilmgandhi	18:6a4db94011d3	14571	#define EPWM_CMPDAT0_CMP_Msk (0xfffful << EPWM_CMPDAT0_CMP_Pos) /!< EPWM CMPDAT0: CMP Mask /
sahilmgandhi	18:6a4db94011d3	14572
sahilmgandhi	18:6a4db94011d3	14573	#define EPWM_CMPDAT2_CMP_Pos (0) /!< EPWM CMPDAT2: CMP Position /
sahilmgandhi	18:6a4db94011d3	14574	#define EPWM_CMPDAT2_CMP_Msk (0xfffful << EPWM_CMPDAT2_CMP_Pos) /!< EPWM CMPDAT2: CMP Mask /
sahilmgandhi	18:6a4db94011d3	14575
sahilmgandhi	18:6a4db94011d3	14576	#define EPWM_CMPDAT4_CMP_Pos (0) /!< EPWM CMPDAT4: CMP Position /
sahilmgandhi	18:6a4db94011d3	14577	#define EPWM_CMPDAT4_CMP_Msk (0xfffful << EPWM_CMPDAT4_CMP_Pos) /!< EPWM CMPDAT4: CMP Mask /
sahilmgandhi	18:6a4db94011d3	14578
sahilmgandhi	18:6a4db94011d3	14579	#define EPWM_MSKEN_MSKEN_Pos (0) /!< EPWM MSKEN: MSKEN Position /
sahilmgandhi	18:6a4db94011d3	14580	#define EPWM_MSKEN_MSKEN_Msk (0x3ful << EPWM_MSKEN_MSKEN_Pos) /!< EPWM MSKEN: MSKEN Mask /
sahilmgandhi	18:6a4db94011d3	14581
sahilmgandhi	18:6a4db94011d3	14582	#define EPWM_MSK_MSKDAT_Pos (0) /!< EPWM MSK: MSKDAT Position /
sahilmgandhi	18:6a4db94011d3	14583	#define EPWM_MSK_MSKDAT_Msk (0x3ful << EPWM_MSK_MSKDAT_Pos) /!< EPWM MSK: MSKDAT Mask /
sahilmgandhi	18:6a4db94011d3	14584
sahilmgandhi	18:6a4db94011d3	14585	#define EPWM_ASYMCMP0_CMP_Pos (0) /!< EPWM ASYMCMP0: CMP Position /
sahilmgandhi	18:6a4db94011d3	14586	#define EPWM_ASYMCMP0_CMP_Msk (0xfffful << EPWM_ASYMCMP0_CMP_Pos) /!< EPWM ASYMCMP0: CMP Mask /
sahilmgandhi	18:6a4db94011d3	14587
sahilmgandhi	18:6a4db94011d3	14588	#define EPWM_ASYMCMP2_CMP_Pos (0) /!< EPWM ASYMCMP2: CMP Position /
sahilmgandhi	18:6a4db94011d3	14589	#define EPWM_ASYMCMP2_CMP_Msk (0xfffful << EPWM_ASYMCMP2_CMP_Pos) /!< EPWM ASYMCMP2: CMP Mask /
sahilmgandhi	18:6a4db94011d3	14590
sahilmgandhi	18:6a4db94011d3	14591	#define EPWM_ASYMCMP4_CMP_Pos (0) /!< EPWM ASYMCMP4: CMP Position /
sahilmgandhi	18:6a4db94011d3	14592	#define EPWM_ASYMCMP4_CMP_Msk (0xfffful << EPWM_ASYMCMP4_CMP_Pos) /!< EPWM ASYMCMP4: CMP Mask /
sahilmgandhi	18:6a4db94011d3	14593
sahilmgandhi	18:6a4db94011d3	14594	#define EPWM_DTCTL_DTCNT_Pos (0) /!< EPWM DTCTL: DTCNT Position /
sahilmgandhi	18:6a4db94011d3	14595	#define EPWM_DTCTL_DTCNT_Msk (0x7fful << EPWM_DTCTL_DTCNT_Pos) /!< EPWM DTCTL: DTCNT Mask /
sahilmgandhi	18:6a4db94011d3	14596
sahilmgandhi	18:6a4db94011d3	14597	#define EPWM_DTCTL_DTEN0_Pos (16) /!< EPWM DTCTL: DTEN0 Position /
sahilmgandhi	18:6a4db94011d3	14598	#define EPWM_DTCTL_DTEN0_Msk (0x1ul << EPWM_DTCTL_DTEN0_Pos) /!< EPWM DTCTL: DTEN0 Mask /
sahilmgandhi	18:6a4db94011d3	14599
sahilmgandhi	18:6a4db94011d3	14600	#define EPWM_DTCTL_DTEN2_Pos (17) /!< EPWM DTCTL: DTEN2 Position /
sahilmgandhi	18:6a4db94011d3	14601	#define EPWM_DTCTL_DTEN2_Msk (0x1ul << EPWM_DTCTL_DTEN2_Pos) /!< EPWM DTCTL: DTEN2 Mask /
sahilmgandhi	18:6a4db94011d3	14602
sahilmgandhi	18:6a4db94011d3	14603	#define EPWM_DTCTL_DTEN4_Pos (18) /!< EPWM DTCTL: DTEN4 Position /
sahilmgandhi	18:6a4db94011d3	14604	#define EPWM_DTCTL_DTEN4_Msk (0x1ul << EPWM_DTCTL_DTEN4_Pos) /!< EPWM DTCTL: DTEN4 Mask /
sahilmgandhi	18:6a4db94011d3	14605
sahilmgandhi	18:6a4db94011d3	14606	#define EPWM_BRKOUT_BRKOUT_Pos (0) /!< EPWM BRKOUT: BRKOUT Position /
sahilmgandhi	18:6a4db94011d3	14607	#define EPWM_BRKOUT_BRKOUT_Msk (0x3ful << EPWM_BRKOUT_BRKOUT_Pos) /!< EPWM BRKOUT: BRKOUT Mask /
sahilmgandhi	18:6a4db94011d3	14608
sahilmgandhi	18:6a4db94011d3	14609	#define EPWM_NPCTL_NEGPOLAR_Pos (0) /!< EPWM NPCTL: NEGPOLAR Position /
sahilmgandhi	18:6a4db94011d3	14610	#define EPWM_NPCTL_NEGPOLAR_Msk (0x3ful << EPWM_NPCTL_NEGPOLAR_Pos) /!< EPWM NPCTL: NEGPOLAR Mask /
sahilmgandhi	18:6a4db94011d3	14611
sahilmgandhi	18:6a4db94011d3	14612	#define EPWM_ASYMCTL_ASYMEN_Pos (0) /!< EPWM ASYMCTL: ASYMEN Position /
sahilmgandhi	18:6a4db94011d3	14613	#define EPWM_ASYMCTL_ASYMEN_Msk (0x1ul << EPWM_ASYMCTL_ASYMEN_Pos) /!< EPWM ASYMCTL: ASYMEN Mask /
sahilmgandhi	18:6a4db94011d3	14614
sahilmgandhi	18:6a4db94011d3	14615	#define EPWM_ASYMCTL_ASYMMODE0_Pos (8) /!< EPWM ASYMCTL: ASYMMODE0 Position /
sahilmgandhi	18:6a4db94011d3	14616	#define EPWM_ASYMCTL_ASYMMODE0_Msk (0x3ul << EPWM_ASYMCTL_ASYMMODE0_Pos) /!< EPWM ASYMCTL: ASYMMODE0 Mask /
sahilmgandhi	18:6a4db94011d3	14617
sahilmgandhi	18:6a4db94011d3	14618	#define EPWM_ASYMCTL_ASYMMODE2_Pos (16) /!< EPWM ASYMCTL: ASYMMODE2 Position /
sahilmgandhi	18:6a4db94011d3	14619	#define EPWM_ASYMCTL_ASYMMODE2_Msk (0x3ul << EPWM_ASYMCTL_ASYMMODE2_Pos) /!< EPWM ASYMCTL: ASYMMODE2 Mask /
sahilmgandhi	18:6a4db94011d3	14620
sahilmgandhi	18:6a4db94011d3	14621	#define EPWM_ASYMCTL_ASYMMODE4_Pos (24) /!< EPWM ASYMCTL: ASYMMODE4 Position /
sahilmgandhi	18:6a4db94011d3	14622	#define EPWM_ASYMCTL_ASYMMODE4_Msk (0x3ul << EPWM_ASYMCTL_ASYMMODE4_Pos) /!< EPWM ASYMCTL: ASYMMODE4 Mask /
sahilmgandhi	18:6a4db94011d3	14623
sahilmgandhi	18:6a4db94011d3	14624	#define EPWM_PERIODCNT_PERIODCNT_Pos (0) /!< EPWM PERIODCNT: PERIODCNT Position /
sahilmgandhi	18:6a4db94011d3	14625	#define EPWM_PERIODCNT_PERIODCNT_Msk (0xful << EPWM_PERIODCNT_PERIODCNT_Pos) /!< EPWM PERIODCNT: PERIODCNT Mask /
sahilmgandhi	18:6a4db94011d3	14626
sahilmgandhi	18:6a4db94011d3	14627	#define EPWM_EINTCTL_EDGEIEN0_Pos (0) /!< EPWM EINTCTL: EDGEIEN0 Position /
sahilmgandhi	18:6a4db94011d3	14628	#define EPWM_EINTCTL_EDGEIEN0_Msk (0x1ul << EPWM_EINTCTL_EDGEIEN0_Pos) /!< EPWM EINTCTL: EDGEIEN0 Mask /
sahilmgandhi	18:6a4db94011d3	14629
sahilmgandhi	18:6a4db94011d3	14630	#define EPWM_EINTCTL_EDGEIEN2_Pos (1) /!< EPWM EINTCTL: EDGEIEN2 Position /
sahilmgandhi	18:6a4db94011d3	14631	#define EPWM_EINTCTL_EDGEIEN2_Msk (0x1ul << EPWM_EINTCTL_EDGEIEN2_Pos) /!< EPWM EINTCTL: EDGEIEN2 Mask /
sahilmgandhi	18:6a4db94011d3	14632
sahilmgandhi	18:6a4db94011d3	14633	#define EPWM_EINTCTL_EDGEIEN4_Pos (2) /!< EPWM EINTCTL: EDGEIEN4 Position /
sahilmgandhi	18:6a4db94011d3	14634	#define EPWM_EINTCTL_EDGEIEN4_Msk (0x1ul << EPWM_EINTCTL_EDGEIEN4_Pos) /!< EPWM EINTCTL: EDGEIEN4 Mask /
sahilmgandhi	18:6a4db94011d3	14635
sahilmgandhi	18:6a4db94011d3	14636	#define EPWM_EINTCTL_EINTTYPE0_Pos (8) /!< EPWM EINTCTL: EINTTYPE0 Position /
sahilmgandhi	18:6a4db94011d3	14637	#define EPWM_EINTCTL_EINTTYPE0_Msk (0x1ul << EPWM_EINTCTL_EINTTYPE0_Pos) /!< EPWM EINTCTL: EINTTYPE0 Mask /
sahilmgandhi	18:6a4db94011d3	14638
sahilmgandhi	18:6a4db94011d3	14639	#define EPWM_EINTCTL_EINTTYPE2_Pos (9) /!< EPWM EINTCTL: EINTTYPE2 Position /
sahilmgandhi	18:6a4db94011d3	14640	#define EPWM_EINTCTL_EINTTYPE2_Msk (0x1ul << EPWM_EINTCTL_EINTTYPE2_Pos) /!< EPWM EINTCTL: EINTTYPE2 Mask /
sahilmgandhi	18:6a4db94011d3	14641
sahilmgandhi	18:6a4db94011d3	14642	#define EPWM_EINTCTL_EINTTYPE4_Pos (10) /!< EPWM EINTCTL: EINTTYPE4 Position /
sahilmgandhi	18:6a4db94011d3	14643	#define EPWM_EINTCTL_EINTTYPE4_Msk (0x1ul << EPWM_EINTCTL_EINTTYPE4_Pos) /!< EPWM EINTCTL: EINTTYPE4 Mask /
sahilmgandhi	18:6a4db94011d3	14644
sahilmgandhi	18:6a4db94011d3	14645	#define EPWM_OUTEN0_EVENOUTEN_Pos (0) /!< EPWM OUTEN0: EVENOUTEN Position /
sahilmgandhi	18:6a4db94011d3	14646	#define EPWM_OUTEN0_EVENOUTEN_Msk (0x1ul << EPWM_OUTEN0_EVENOUTEN_Pos) /!< EPWM OUTEN0: EVENOUTEN Mask /
sahilmgandhi	18:6a4db94011d3	14647
sahilmgandhi	18:6a4db94011d3	14648	#define EPWM_OUTEN0_ODDOUTEN_Pos (1) /!< EPWM OUTEN0: ODDOUTEN Position /
sahilmgandhi	18:6a4db94011d3	14649	#define EPWM_OUTEN0_ODDOUTEN_Msk (0x1ul << EPWM_OUTEN0_ODDOUTEN_Pos) /!< EPWM OUTEN0: ODDOUTEN Mask /
sahilmgandhi	18:6a4db94011d3	14650
sahilmgandhi	18:6a4db94011d3	14651	/*@}/ /* EPWM_CONST */
sahilmgandhi	18:6a4db94011d3	14652	/*@}/ /* end of EPWM register group */
sahilmgandhi	18:6a4db94011d3	14653
sahilmgandhi	18:6a4db94011d3	14654
sahilmgandhi	18:6a4db94011d3	14655	/---------------------- Flash Memory Controller -------------------------/
sahilmgandhi	18:6a4db94011d3	14656	/**
sahilmgandhi	18:6a4db94011d3	14657	@addtogroup FMC Flash Memory Controller(FMC)
sahilmgandhi	18:6a4db94011d3	14658	Memory Mapped Structure for FMC Controller
sahilmgandhi	18:6a4db94011d3	14659	@{ */
sahilmgandhi	18:6a4db94011d3	14660
sahilmgandhi	18:6a4db94011d3	14661	typedef struct {
sahilmgandhi	18:6a4db94011d3	14662	/**
sahilmgandhi	18:6a4db94011d3	14663	* ISPCTL
sahilmgandhi	18:6a4db94011d3	14664	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14665	* Offset: 0x00 ISP Control Register
sahilmgandhi	18:6a4db94011d3	14666	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14667	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14668	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14669	* \|[0] \|ISPEN \|ISP Enable Control (Write Protect)
sahilmgandhi	18:6a4db94011d3	14670	* \| \| \|ISP function enable bit. Set this bit to enable ISP function.
sahilmgandhi	18:6a4db94011d3	14671	* \| \| \|0 = ISP function Disabled.
sahilmgandhi	18:6a4db94011d3	14672	* \| \| \|1 = ISP function Enabled.
sahilmgandhi	18:6a4db94011d3	14673	* \|[1] \|BS \|Boot Select (Write Protect)
sahilmgandhi	18:6a4db94011d3	14674	* \| \| \|Set/clear this bit to select next booting from LDROM/APROM, respectively.
sahilmgandhi	18:6a4db94011d3	14675	* \| \| \|This bit also functions as chip booting status flag, which can be used to check where chip booted from.
sahilmgandhi	18:6a4db94011d3	14676	* \| \| \|This bit is initiated with the inversed value of CBS in Config0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened.
sahilmgandhi	18:6a4db94011d3	14677	* \| \| \|0 = Boot from APROM.
sahilmgandhi	18:6a4db94011d3	14678	* \| \| \|1 = Boot from LDROM.
sahilmgandhi	18:6a4db94011d3	14679	* \|[3] \|APUEN \|APROM Update Enable Control (Write Protect)
sahilmgandhi	18:6a4db94011d3	14680	* \| \| \|0 = APROM cannot be updated when the chip runs in APROM.
sahilmgandhi	18:6a4db94011d3	14681	* \| \| \|1 = APROM can be updated when the chip runs in APROM.
sahilmgandhi	18:6a4db94011d3	14682	* \|[4] \|CFGUEN \|Config-Bits Update By ISP (Write Protect) Enable Control
sahilmgandhi	18:6a4db94011d3	14683	* \| \| \|0 = ISP Disabled to update config-bits.
sahilmgandhi	18:6a4db94011d3	14684	* \| \| \|1 = ISP Enabled to update config-bits at KEYMATCH flag active (bit7 of ISPSTS).
sahilmgandhi	18:6a4db94011d3	14685	* \| \| \|Note: This bit is fixed to 0 in Secure mode.
sahilmgandhi	18:6a4db94011d3	14686	* \|[5] \|LDUEN \|LDROM Update Enable Control (Write Protect)
sahilmgandhi	18:6a4db94011d3	14687	* \| \| \|LDROM update enable bit.
sahilmgandhi	18:6a4db94011d3	14688	* \| \| \|0 = LDROM cannot be updated.
sahilmgandhi	18:6a4db94011d3	14689	* \| \| \|1 = LDROM can be updated at KEYMATCH flag active (bit7 of ISPSTS).
sahilmgandhi	18:6a4db94011d3	14690	* \| \| \|Note: This bit is fixed to 0 in Secure mode.
sahilmgandhi	18:6a4db94011d3	14691	* \|[6] \|ISPFF \|ISP Fail Flag (Write Protect)
sahilmgandhi	18:6a4db94011d3	14692	* \| \| \|This bit is set by hardware when a triggered ISP meets any of the following conditions:
sahilmgandhi	18:6a4db94011d3	14693	* \| \| \|(1) APROM writes to itself if APUEN is set to 0.
sahilmgandhi	18:6a4db94011d3	14694	* \| \| \|(2) LDROM writes to itself if LDUEN is set to 0.
sahilmgandhi	18:6a4db94011d3	14695	* \| \| \|(3) CONFIG is erased/programmed if CFGUEN is set to 0.
sahilmgandhi	18:6a4db94011d3	14696	* \| \| \|(4) Destination address is illegal, such as over an available range.
sahilmgandhi	18:6a4db94011d3	14697	* \| \| \|Note: This bit needs to be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	14698	*/
sahilmgandhi	18:6a4db94011d3	14699	__IO uint32_t ISPCTL;
sahilmgandhi	18:6a4db94011d3	14700
sahilmgandhi	18:6a4db94011d3	14701	/**
sahilmgandhi	18:6a4db94011d3	14702	* ISPADDR
sahilmgandhi	18:6a4db94011d3	14703	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14704	* Offset: 0x04 ISP Address Register
sahilmgandhi	18:6a4db94011d3	14705	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14706	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14707	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14708	* \|[0:31] \|ISPADR \|ISP Address
sahilmgandhi	18:6a4db94011d3	14709	* \| \| \|The NUC442/NUC472 series is equipped with an embedded flash and supports word program only.
sahilmgandhi	18:6a4db94011d3	14710	* \| \| \|ISPADR[1:0] must be kept 00b for ISP operation.
sahilmgandhi	18:6a4db94011d3	14711	*/
sahilmgandhi	18:6a4db94011d3	14712	__IO uint32_t ISPADDR;
sahilmgandhi	18:6a4db94011d3	14713
sahilmgandhi	18:6a4db94011d3	14714	/**
sahilmgandhi	18:6a4db94011d3	14715	* ISPDAT
sahilmgandhi	18:6a4db94011d3	14716	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14717	* Offset: 0x08 ISP Data Register
sahilmgandhi	18:6a4db94011d3	14718	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14719	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14720	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14721	* \|[0:31] \|ISPDAT \|ISP Data
sahilmgandhi	18:6a4db94011d3	14722	* \| \| \|Write data to this register before ISP program operation.
sahilmgandhi	18:6a4db94011d3	14723	* \| \| \|Read data from this register after ISP read operation.
sahilmgandhi	18:6a4db94011d3	14724	*/
sahilmgandhi	18:6a4db94011d3	14725	__IO uint32_t ISPDAT;
sahilmgandhi	18:6a4db94011d3	14726
sahilmgandhi	18:6a4db94011d3	14727	/**
sahilmgandhi	18:6a4db94011d3	14728	* ISPCMD
sahilmgandhi	18:6a4db94011d3	14729	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14730	* Offset: 0x0C ISP Command Register
sahilmgandhi	18:6a4db94011d3	14731	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14732	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14733	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14734	* \|[0:5] \|CMD \|ISP Command
sahilmgandhi	18:6a4db94011d3	14735	* \| \| \|Please check the table below for ISP commands.
sahilmgandhi	18:6a4db94011d3	14736	*/
sahilmgandhi	18:6a4db94011d3	14737	__IO uint32_t ISPCMD;
sahilmgandhi	18:6a4db94011d3	14738
sahilmgandhi	18:6a4db94011d3	14739	/**
sahilmgandhi	18:6a4db94011d3	14740	* ISPTRG
sahilmgandhi	18:6a4db94011d3	14741	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14742	* Offset: 0x10 ISP Trigger Register
sahilmgandhi	18:6a4db94011d3	14743	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14744	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14745	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14746	* \|[0] \|ISPGO \|ISP Start Trigger
sahilmgandhi	18:6a4db94011d3	14747	* \| \| \|Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
sahilmgandhi	18:6a4db94011d3	14748	* \| \| \|0 = ISP operation is finished.
sahilmgandhi	18:6a4db94011d3	14749	* \| \| \|1 = ISP is progressed.
sahilmgandhi	18:6a4db94011d3	14750	* \| \| \|This bit is the protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
sahilmgandhi	18:6a4db94011d3	14751	* \| \| \|Refer to the register REGWRPROT at address GCR_BA+0x100.
sahilmgandhi	18:6a4db94011d3	14752	*/
sahilmgandhi	18:6a4db94011d3	14753	__IO uint32_t ISPTRG;
sahilmgandhi	18:6a4db94011d3	14754
sahilmgandhi	18:6a4db94011d3	14755	/**
sahilmgandhi	18:6a4db94011d3	14756	* DFBA
sahilmgandhi	18:6a4db94011d3	14757	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14758	* Offset: 0x14 Data Flash Base Address
sahilmgandhi	18:6a4db94011d3	14759	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14760	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14761	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14762	* \|[0:31] \|DFBA \|Data Flash Base Address
sahilmgandhi	18:6a4db94011d3	14763	* \| \| \|This register indicates data flash start address. It is a read only register.
sahilmgandhi	18:6a4db94011d3	14764	* \| \| \|The data flash is shared with APROM and data flash size is defined by user configuration and the content of this register is loaded from Config1.
sahilmgandhi	18:6a4db94011d3	14765	*/
sahilmgandhi	18:6a4db94011d3	14766	__I uint32_t DFBA;
sahilmgandhi	18:6a4db94011d3	14767
sahilmgandhi	18:6a4db94011d3	14768	/**
sahilmgandhi	18:6a4db94011d3	14769	* FTCTL
sahilmgandhi	18:6a4db94011d3	14770	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14771	* Offset: 0x18 Flash Access Time Control Register
sahilmgandhi	18:6a4db94011d3	14772	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14773	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14774	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14775	* \|[4:6] \|FOM \|Frequency Optimization Mode (Write Protect)
sahilmgandhi	18:6a4db94011d3	14776	* \| \| \|When chip operation frequency is lower, chip can work more efficiently by setting FOM bits
sahilmgandhi	18:6a4db94011d3	14777	* \| \| \|FOM[2:0]
sahilmgandhi	18:6a4db94011d3	14778	* \| \| \|Optimized Frequency (OF)
sahilmgandhi	18:6a4db94011d3	14779	* \| \| \|001
sahilmgandhi	18:6a4db94011d3	14780	* \| \| \|0 MHz < OF <= 24 MHz
sahilmgandhi	18:6a4db94011d3	14781	* \| \| \|010
sahilmgandhi	18:6a4db94011d3	14782	* \| \| \|24 MHz < OF <= 48 MHz
sahilmgandhi	18:6a4db94011d3	14783	* \| \| \|011
sahilmgandhi	18:6a4db94011d3	14784	* \| \| \|48 MHz < OF <= 72 MHz
sahilmgandhi	18:6a4db94011d3	14785	* \| \| \|others
sahilmgandhi	18:6a4db94011d3	14786	* \| \| \|Reserved
sahilmgandhi	18:6a4db94011d3	14787	*/
sahilmgandhi	18:6a4db94011d3	14788	__IO uint32_t FTCTL;
sahilmgandhi	18:6a4db94011d3	14789	uint32_t RESERVE0[9];
sahilmgandhi	18:6a4db94011d3	14790
sahilmgandhi	18:6a4db94011d3	14791	/**
sahilmgandhi	18:6a4db94011d3	14792	* ISPSTS
sahilmgandhi	18:6a4db94011d3	14793	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14794	* Offset: 0x40 Flash Access Time Control Register
sahilmgandhi	18:6a4db94011d3	14795	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14796	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14797	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14798	* \|[0] \|ISPBUSY \|ISP busy flag
sahilmgandhi	18:6a4db94011d3	14799	* \| \| \|0 = ISP operation is finished.
sahilmgandhi	18:6a4db94011d3	14800	* \| \| \|1 = ISP is progressed.
sahilmgandhi	18:6a4db94011d3	14801	* \|[2:1] \|CBS \|Chip boot selection mode
sahilmgandhi	18:6a4db94011d3	14802	* \| \| \|This CBS field is just a copy of User-Configuration Config0 CBS[7:6].
sahilmgandhi	18:6a4db94011d3	14803	* \|[6] \|ISPFF \|ISP Fail Flag (Write Protect)
sahilmgandhi	18:6a4db94011d3	14804	* \| \| \|This bit is set by hardware when a triggered ISP meets any of the following conditions:
sahilmgandhi	18:6a4db94011d3	14805	* \| \| \|(1) APROM writes to itself if APUEN is set to 0.
sahilmgandhi	18:6a4db94011d3	14806	* \| \| \|(2) LDROM writes to itself if LDUEN is set to 0.
sahilmgandhi	18:6a4db94011d3	14807	* \| \| \|(3) CONFIG is erased/programmed if CFGUEN is set to 0.
sahilmgandhi	18:6a4db94011d3	14808	* \| \| \|(4) Destination address is illegal, such as over an available range.
sahilmgandhi	18:6a4db94011d3	14809	* \| \| \|Note: This bit needs to be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	14810	* \|[20:9] \|VECMAP \|Vector Page Mapping Address (Read Only)
sahilmgandhi	18:6a4db94011d3	14811	* \| \| \|The current flash address space 0x0000_0000~0x0000_07FF is mapping to
sahilmgandhi	18:6a4db94011d3	14812	* \| \| \|address {VECMAP[11:2], 11¡¦h000} ~ {VECMAP[11:2], 11¡¦h7FF}
sahilmgandhi	18:6a4db94011d3	14813	* \| \| \|VECMAP[1:0] is needed to set 0.
sahilmgandhi	18:6a4db94011d3	14814	* \|[26] \|CFGCRCF \|User-Configuration CRC Check Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	14815	* \| \| \|This bit is set by hardware when detecting CONFIG CRC checksum is error
sahilmgandhi	18:6a4db94011d3	14816	* \| \| \|0 = CONFIG CRC checksum is OK.
sahilmgandhi	18:6a4db94011d3	14817	* \| \| \|1 = CONFIG CRC checksum error and force chip into LOCK mode.
sahilmgandhi	18:6a4db94011d3	14818	*/
sahilmgandhi	18:6a4db94011d3	14819	__IO uint32_t ISPSTS;
sahilmgandhi	18:6a4db94011d3	14820
sahilmgandhi	18:6a4db94011d3	14821	/**
sahilmgandhi	18:6a4db94011d3	14822	* FBWP
sahilmgandhi	18:6a4db94011d3	14823	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14824	* Offset: 0x44 Flash Block Write Protect Control Register
sahilmgandhi	18:6a4db94011d3	14825	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14826	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14827	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14828	* \|[0:31] \|BWP \|Flash Block Write Protect Control
sahilmgandhi	18:6a4db94011d3	14829	* \| \| \|If BWP.N bit is set to 0, the APROM memory relative region cannot program and erase by ISP. (N=0~31).
sahilmgandhi	18:6a4db94011d3	14830	* \| \| \|Bit Block Protect Region
sahilmgandhi	18:6a4db94011d3	14831	* \| \| \|BWP0 0x00_0000 ~ 0x00_3FFF
sahilmgandhi	18:6a4db94011d3	14832	* \| \| \|BWP1 0x00_4000 ~ 0x00_7FFF
sahilmgandhi	18:6a4db94011d3	14833	* \| \| \|BWP2 0x00_8000 ~ 0x00_BFFF
sahilmgandhi	18:6a4db94011d3	14834	* \| \| \|BWP3 0x00_C000 ~ 0x00_FFFF
sahilmgandhi	18:6a4db94011d3	14835	* \| \| \|BWP4 0x01_0000 ~ 0x01_3FFF
sahilmgandhi	18:6a4db94011d3	14836	* \| \| \|BWP5 0x01_4000 ~ 0x01_7FFF
sahilmgandhi	18:6a4db94011d3	14837	* \| \| \|BWP6 0x01_8000 ~ 0x01_BFFF
sahilmgandhi	18:6a4db94011d3	14838	* \| \| \|BWP7 0x01_C000 ~ 0x01_FFFF
sahilmgandhi	18:6a4db94011d3	14839	* \| \| \|BWP8 0x02_0000 ~ 0x02_3FFF
sahilmgandhi	18:6a4db94011d3	14840	* \| \| \|BWP9 0x02_4000 ~ 0x02_7FFF
sahilmgandhi	18:6a4db94011d3	14841	* \| \| \|BWP10 0x02_8000 ~ 0x02_BFFF
sahilmgandhi	18:6a4db94011d3	14842	* \| \| \|BWP11 0x02_C000 ~ 0x02_FFFF
sahilmgandhi	18:6a4db94011d3	14843	* \| \| \|BWP12 0x03_0000 ~ 0x03_3FFF
sahilmgandhi	18:6a4db94011d3	14844	* \| \| \|BWP13 0x03_4000 ~ 0x03_7FFF
sahilmgandhi	18:6a4db94011d3	14845	* \| \| \|BWP14 0x03_8000 ~ 0x03_BFFF
sahilmgandhi	18:6a4db94011d3	14846	* \| \| \|BWP15 0x03_C000 ~ 0x03_FFFF
sahilmgandhi	18:6a4db94011d3	14847	* \| \| \|BWP16 0x04_0000 ~ 0x04_3FFF
sahilmgandhi	18:6a4db94011d3	14848	* \| \| \|BWP17 0x04_4000 ~ 0x04_7FFF
sahilmgandhi	18:6a4db94011d3	14849	* \| \| \|BWP18 0x04_8000 ~ 0x04_BFFF
sahilmgandhi	18:6a4db94011d3	14850	* \| \| \|BWP19 0x04_C000 ~ 0x04_FFFF
sahilmgandhi	18:6a4db94011d3	14851	* \| \| \|BWP20 0x05_0000 ~ 0x05_3FFF
sahilmgandhi	18:6a4db94011d3	14852	* \| \| \|BWP21 0x05_4000 ~ 0x05_7FFF
sahilmgandhi	18:6a4db94011d3	14853	* \| \| \|BWP22 0x05_8000 ~ 0x05_BFFF
sahilmgandhi	18:6a4db94011d3	14854	* \| \| \|BWP23 0x05_C000 ~ 0x05_FFFF
sahilmgandhi	18:6a4db94011d3	14855	* \| \| \|BWP24 0x06_0000 ~ 0x06_3FFF
sahilmgandhi	18:6a4db94011d3	14856	* \| \| \|BWP25 0x06_4000 ~ 0x06_7FFF
sahilmgandhi	18:6a4db94011d3	14857	* \| \| \|BWP26 0x06_8000 ~ 0x06_BFFF
sahilmgandhi	18:6a4db94011d3	14858	* \| \| \|BWP27 0x06_C000 ~ 0x06_FFFF
sahilmgandhi	18:6a4db94011d3	14859	* \| \| \|BWP28 0x07_0000 ~ 0x07_3FFF
sahilmgandhi	18:6a4db94011d3	14860	* \| \| \|BWP29 0x07_4000 ~ 0x07_7FFF
sahilmgandhi	18:6a4db94011d3	14861	* \| \| \|BWP30 0x07_8000 ~ 0x07_BFFF
sahilmgandhi	18:6a4db94011d3	14862	* \| \| \|BWP31 0x07_C000 ~ 0x07_FFFF
sahilmgandhi	18:6a4db94011d3	14863	* \| \| \|This register is loaded from Config2 when chip is power on.
sahilmgandhi	18:6a4db94011d3	14864	* \| \| \|It is read only, except the correct Super Key is matched.
sahilmgandhi	18:6a4db94011d3	14865	* \| \| \|This register is also a protected bit which means programming this bit needs to write "59h", "16h", "88h" to address GCR_BA+0x100 to disable register protection.
sahilmgandhi	18:6a4db94011d3	14866	* \| \| \|Refer to the register REGWRPROT at address GCR_BA+0x100.
sahilmgandhi	18:6a4db94011d3	14867	*/
sahilmgandhi	18:6a4db94011d3	14868	__IO uint32_t FBWP;
sahilmgandhi	18:6a4db94011d3	14869	uint32_t RESERVE1[14];
sahilmgandhi	18:6a4db94011d3	14870
sahilmgandhi	18:6a4db94011d3	14871	/**
sahilmgandhi	18:6a4db94011d3	14872	* MPDAT0
sahilmgandhi	18:6a4db94011d3	14873	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14874	* Offset: 0x80 ISP Data 0 Register
sahilmgandhi	18:6a4db94011d3	14875	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14876	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14877	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14878	* \|[0:31] \|ISPDAT0 \|ISP Data 0
sahilmgandhi	18:6a4db94011d3	14879	* \| \| \|This register is the first 32-bit data for 32b/64b/multi-word program,
sahilmgandhi	18:6a4db94011d3	14880	* \| \| \|and it is also the mirror of FMC_ISPDAT register, both registers keep the same data.
sahilmgandhi	18:6a4db94011d3	14881	*/
sahilmgandhi	18:6a4db94011d3	14882	__IO uint32_t MPDAT0;
sahilmgandhi	18:6a4db94011d3	14883
sahilmgandhi	18:6a4db94011d3	14884	/**
sahilmgandhi	18:6a4db94011d3	14885	* MPDAT1
sahilmgandhi	18:6a4db94011d3	14886	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14887	* Offset: 0x84 ISP Data 1 Register
sahilmgandhi	18:6a4db94011d3	14888	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14889	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14890	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14891	* \|[0:31] \|ISPDAT1 \|ISP Data 1
sahilmgandhi	18:6a4db94011d3	14892	* \| \| \|This register is the second 32-bit data for 32b/64b/multi-word program.
sahilmgandhi	18:6a4db94011d3	14893	*/
sahilmgandhi	18:6a4db94011d3	14894	__IO uint32_t MPDAT1;
sahilmgandhi	18:6a4db94011d3	14895
sahilmgandhi	18:6a4db94011d3	14896	/**
sahilmgandhi	18:6a4db94011d3	14897	* MPDAT2
sahilmgandhi	18:6a4db94011d3	14898	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14899	* Offset: 0x88 ISP Data 2 Register
sahilmgandhi	18:6a4db94011d3	14900	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14901	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14902	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14903	* \|[0:31] \|ISPDAT2 \|ISP Data 2
sahilmgandhi	18:6a4db94011d3	14904	* \| \| \|This register is the third 32-bit data for 32b/64b/multi-word program.
sahilmgandhi	18:6a4db94011d3	14905	*/
sahilmgandhi	18:6a4db94011d3	14906	__IO uint32_t MPDAT2;
sahilmgandhi	18:6a4db94011d3	14907
sahilmgandhi	18:6a4db94011d3	14908	/**
sahilmgandhi	18:6a4db94011d3	14909	* MPDAT3
sahilmgandhi	18:6a4db94011d3	14910	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14911	* Offset: 0x8C ISP Data 1 Register
sahilmgandhi	18:6a4db94011d3	14912	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14913	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14914	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14915	* \|[0:31] \|ISPDAT3 \|ISP Data 3
sahilmgandhi	18:6a4db94011d3	14916	* \| \| \|This register is the fourth 32-bit data for 32b/64b/multi-word program.
sahilmgandhi	18:6a4db94011d3	14917	*/
sahilmgandhi	18:6a4db94011d3	14918	__IO uint32_t MPDAT3;
sahilmgandhi	18:6a4db94011d3	14919
sahilmgandhi	18:6a4db94011d3	14920	uint32_t RESERVE2[12];
sahilmgandhi	18:6a4db94011d3	14921
sahilmgandhi	18:6a4db94011d3	14922	/**
sahilmgandhi	18:6a4db94011d3	14923	* MPSTS
sahilmgandhi	18:6a4db94011d3	14924	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14925	* Offset: 0xC0 ISP Multi-Word Program Status Register
sahilmgandhi	18:6a4db94011d3	14926	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14927	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14928	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14929	* \|[0] \|MPBUSY \|ISP Multi-Word Program Busy Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	14930	* \| \| \|0 = ISP Multi-Word Program operation is aborted or finished.
sahilmgandhi	18:6a4db94011d3	14931	* \| \| \|1 = ISP Multi-Word Program operation is progressed.
sahilmgandhi	18:6a4db94011d3	14932	* \|[2] \|ISPFF \|ISP Fail Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	14933	* \| \| \|This CBS field is just a copy of User-Configuration Config0 CBS[7:6].
sahilmgandhi	18:6a4db94011d3	14934	* \|[4] \|D0 \|ISP DATA 0 Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	14935	* \| \| \|This bit is set when FMC_MPDAT0 is written and auto-clear to 0
sahilmgandhi	18:6a4db94011d3	14936	* \| \| \|when the FMC_MPDAT0 is programmed to flash complete.
sahilmgandhi	18:6a4db94011d3	14937	* \| \| \|0 = FMC_MPDAT0 register is empty, or program to flash complete.
sahilmgandhi	18:6a4db94011d3	14938	* \| \| \|1 = FMC_MPDAT0 register has been written, and not programmed to flash yet.
sahilmgandhi	18:6a4db94011d3	14939	* \|[5] \|D1 \|ISP DATA 1 Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	14940	* \| \| \|This bit is set when FMC_MPDAT1 is written and auto-clear to 0
sahilmgandhi	18:6a4db94011d3	14941	* \| \| \|when the FMC_MPDAT1 is programmed to flash complete.
sahilmgandhi	18:6a4db94011d3	14942	* \| \| \|0 = FMC_MPDAT1 register is empty, or program to flash complete.
sahilmgandhi	18:6a4db94011d3	14943	* \| \| \|1 = FMC_MPDAT1 register has been written, and not programmed to flash yet.
sahilmgandhi	18:6a4db94011d3	14944	* \|[6] \|D2 \|ISP DATA 2 Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	14945	* \| \| \|This bit is set when FMC_MPDAT2 is written and auto-clear to 0
sahilmgandhi	18:6a4db94011d3	14946	* \| \| \|when the FMC_MPDAT2 is programmed to flash complete.
sahilmgandhi	18:6a4db94011d3	14947	* \| \| \|0 = FMC_MPDAT2 register is empty, or program to flash complete.
sahilmgandhi	18:6a4db94011d3	14948	* \| \| \|1 = FMC_MPDAT2 register has been written, and not programmed to flash yet.
sahilmgandhi	18:6a4db94011d3	14949	* \|[7] \|D3 \|ISP DATA 3 Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	14950	* \| \| \|This bit is set when FMC_MPDAT3 is written and auto-clear to 0
sahilmgandhi	18:6a4db94011d3	14951	* \| \| \|when the FMC_MPDAT3 is programmed to flash complete.
sahilmgandhi	18:6a4db94011d3	14952	* \| \| \|0 = FMC_MPDAT3 register is empty, or program to flash complete.
sahilmgandhi	18:6a4db94011d3	14953	* \| \| \|1 = FMC_MPDAT3 register has been written, and not programmed to flash yet.
sahilmgandhi	18:6a4db94011d3	14954	*/
sahilmgandhi	18:6a4db94011d3	14955	__IO uint32_t MPSTS;
sahilmgandhi	18:6a4db94011d3	14956
sahilmgandhi	18:6a4db94011d3	14957	/**
sahilmgandhi	18:6a4db94011d3	14958	* MPADDR
sahilmgandhi	18:6a4db94011d3	14959	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	14960	* Offset: 0xC4 ISP Multi-Word Program Address Status Register
sahilmgandhi	18:6a4db94011d3	14961	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	14962	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	14963	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	14964	* \|[0:31] \|MPADDR \|ISP Multi-Word Program Address Status
sahilmgandhi	18:6a4db94011d3	14965	* \| \| \|MPADDR is the address of ISP Multi-Word Program operation when
sahilmgandhi	18:6a4db94011d3	14966	* \| \| \|MPBUSY flag is 1. MPADDR will keep the final address when
sahilmgandhi	18:6a4db94011d3	14967	* \| \| \|Multi-Word Program is aborted or finished.
sahilmgandhi	18:6a4db94011d3	14968	*/
sahilmgandhi	18:6a4db94011d3	14969	__IO uint32_t MPADDR;
sahilmgandhi	18:6a4db94011d3	14970
sahilmgandhi	18:6a4db94011d3	14971	} FMC_T;
sahilmgandhi	18:6a4db94011d3	14972
sahilmgandhi	18:6a4db94011d3	14973
sahilmgandhi	18:6a4db94011d3	14974	/**
sahilmgandhi	18:6a4db94011d3	14975	@addtogroup FMC_CONST FMC Bit Field Definition
sahilmgandhi	18:6a4db94011d3	14976	Constant Definitions for FMC Controller
sahilmgandhi	18:6a4db94011d3	14977	@{ */
sahilmgandhi	18:6a4db94011d3	14978
sahilmgandhi	18:6a4db94011d3	14979	#define FMC_ISPCTL_ISPEN_Pos (0) /!< FMC ISPCTL: ISPEN Position /
sahilmgandhi	18:6a4db94011d3	14980	#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /!< FMC ISPCTL: ISPEN Mask /
sahilmgandhi	18:6a4db94011d3	14981
sahilmgandhi	18:6a4db94011d3	14982	#define FMC_ISPCTL_BS_Pos (1) /!< FMC ISPCTL: BS Position /
sahilmgandhi	18:6a4db94011d3	14983	#define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /!< FMC ISPCTL: BS Mask /
sahilmgandhi	18:6a4db94011d3	14984
sahilmgandhi	18:6a4db94011d3	14985	#define FMC_ISPCTL_APUEN_Pos (3) /!< FMC ISPCTL: APUEN Position /
sahilmgandhi	18:6a4db94011d3	14986	#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /!< FMC ISPCTL: APUEN Mask /
sahilmgandhi	18:6a4db94011d3	14987
sahilmgandhi	18:6a4db94011d3	14988	#define FMC_ISPCTL_CFGUEN_Pos (4) /!< FMC ISPCTL: CFGUEN Position /
sahilmgandhi	18:6a4db94011d3	14989	#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /!< FMC ISPCTL: CFGUEN Mask /
sahilmgandhi	18:6a4db94011d3	14990
sahilmgandhi	18:6a4db94011d3	14991	#define FMC_ISPCTL_LDUEN_Pos (5) /!< FMC ISPCTL: LDUEN Position /
sahilmgandhi	18:6a4db94011d3	14992	#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /!< FMC ISPCTL: LDUEN Mask /
sahilmgandhi	18:6a4db94011d3	14993
sahilmgandhi	18:6a4db94011d3	14994	#define FMC_ISPCTL_ISPFF_Pos (6) /!< FMC ISPCTL: ISPFF Position /
sahilmgandhi	18:6a4db94011d3	14995	#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /!< FMC ISPCTL: ISPFF Mask /
sahilmgandhi	18:6a4db94011d3	14996
sahilmgandhi	18:6a4db94011d3	14997	#define FMC_ISPADDR_ISPADDR_Pos (0) /!< FMC ISPADDR: ISPADDR Position /
sahilmgandhi	18:6a4db94011d3	14998	#define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /!< FMC ISPADDR: ISPADDR Mask /
sahilmgandhi	18:6a4db94011d3	14999
sahilmgandhi	18:6a4db94011d3	15000	#define FMC_ISPDAT_ISPDAT_Pos (0) /!< FMC ISPDAT: ISPDAT Position /
sahilmgandhi	18:6a4db94011d3	15001	#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /!< FMC ISPDAT: ISPDAT Mask /
sahilmgandhi	18:6a4db94011d3	15002
sahilmgandhi	18:6a4db94011d3	15003	#define FMC_ISPCMD_CMD_Pos (0) /!< FMC ISPCMD: CMD Position /
sahilmgandhi	18:6a4db94011d3	15004	#define FMC_ISPCMD_CMD_Msk (0x3ful << FMC_ISPCMD_CMD_Pos) /!< FMC ISPCMD: CMD Mask /
sahilmgandhi	18:6a4db94011d3	15005
sahilmgandhi	18:6a4db94011d3	15006	#define FMC_ISPTRG_ISPGO_Pos (0) /!< FMC ISPTRG: ISPGO Position /
sahilmgandhi	18:6a4db94011d3	15007	#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /!< FMC ISPTRG: ISPGO Mask /
sahilmgandhi	18:6a4db94011d3	15008
sahilmgandhi	18:6a4db94011d3	15009	#define FMC_DFBA_DFBA_Pos (0) /!< FMC DFBA: DFBA Position /
sahilmgandhi	18:6a4db94011d3	15010	#define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) /!< FMC DFBA: DFBA Mask /
sahilmgandhi	18:6a4db94011d3	15011
sahilmgandhi	18:6a4db94011d3	15012	#define FMC_FTCTL_FOM_Pos (4) /!< FMC FTCTL: FOM Position /
sahilmgandhi	18:6a4db94011d3	15013	#define FMC_FTCTL_FOM_Msk (0x7ul << FMC_FTCTL_FOM_Pos) /!< FMC FTCTL: FOM Mask /
sahilmgandhi	18:6a4db94011d3	15014
sahilmgandhi	18:6a4db94011d3	15015	#define FMC_ISPSTS_ISPBUSY_Pos (0) /!< FMC ISPSTS: ISPBUSY Position /
sahilmgandhi	18:6a4db94011d3	15016	#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /!< FMC ISPSTS: ISPBUSY Mask /
sahilmgandhi	18:6a4db94011d3	15017
sahilmgandhi	18:6a4db94011d3	15018	#define FMC_ISPSTS_CBS_Pos (1) /!< FMC ISPSTS: CBS Position /
sahilmgandhi	18:6a4db94011d3	15019	#define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) /!< FMC ISPSTS: CBS Mask /
sahilmgandhi	18:6a4db94011d3	15020
sahilmgandhi	18:6a4db94011d3	15021	#define FMC_ISPSTS_ISPFF_Pos (6) /!< FMC ISPSTS: ISPFF Position /
sahilmgandhi	18:6a4db94011d3	15022	#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /!< FMC ISPSTS: ISPFF Mask /
sahilmgandhi	18:6a4db94011d3	15023
sahilmgandhi	18:6a4db94011d3	15024	#define FMC_ISPSTS_VECMAP_Pos (9) /!< FMC ISPSTS: VECMAP Position /
sahilmgandhi	18:6a4db94011d3	15025	#define FMC_ISPSTS_VECMAP_Msk (0xffful << FMC_ISPSTS_VECMAP_Pos) /!< FMC ISPSTS: VECMAP Mask /
sahilmgandhi	18:6a4db94011d3	15026
sahilmgandhi	18:6a4db94011d3	15027	#define FMC_ISPSTS_CFGCRCF_Pos (26) /!< FMC ISPSTS: CFGCRCF Position /
sahilmgandhi	18:6a4db94011d3	15028	#define FMC_ISPSTS_CFGCRCF_Msk (0x1ul << FMC_ISPSTS_CFGCRCF_Pos) /!< FMC ISPSTS: CFGCRCF Mask /
sahilmgandhi	18:6a4db94011d3	15029
sahilmgandhi	18:6a4db94011d3	15030	#define FMC_FBWP_BWP_Pos (0) /!< FMC FBWP: BWP Position /
sahilmgandhi	18:6a4db94011d3	15031	#define FMC_FBWP_BWP_Msk (0xfffffffful << FMC_FBWP_BWP_Pos) /!< FMC FBWP: BWP Mask /
sahilmgandhi	18:6a4db94011d3	15032
sahilmgandhi	18:6a4db94011d3	15033	#define FMC_MPDAT0_ISPDAT0_Pos (0) /!< FMC MPDAT0: ISPDAT0 Position /
sahilmgandhi	18:6a4db94011d3	15034	#define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /!< FMC MPDAT0: ISPDAT0 Mask /
sahilmgandhi	18:6a4db94011d3	15035
sahilmgandhi	18:6a4db94011d3	15036	#define FMC_MPDAT1_ISPDAT1_Pos (0) /!< FMC MPDAT1: ISPDAT1 Position /
sahilmgandhi	18:6a4db94011d3	15037	#define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /!< FMC MPDAT1: ISPDAT1 Mask /
sahilmgandhi	18:6a4db94011d3	15038
sahilmgandhi	18:6a4db94011d3	15039	#define FMC_MPDAT2_ISPDAT2_Pos (0) /!< FMC MPDAT2: ISPDAT2 Position /
sahilmgandhi	18:6a4db94011d3	15040	#define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /!< FMC MPDAT2: ISPDAT2 Mask /
sahilmgandhi	18:6a4db94011d3	15041
sahilmgandhi	18:6a4db94011d3	15042	#define FMC_MPDAT3_ISPDAT3_Pos (0) /!< FMC MPDAT3: ISPDAT3 Position /
sahilmgandhi	18:6a4db94011d3	15043	#define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /!< FMC MPDAT3: ISPDAT3 Mask /
sahilmgandhi	18:6a4db94011d3	15044
sahilmgandhi	18:6a4db94011d3	15045	#define FMC_MPSTS_MPBUSY_Pos (0) /!< FMC MPSTS: WMPBUSY Position /
sahilmgandhi	18:6a4db94011d3	15046	#define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /!< FMC MPSTS: MPBUSY Mask /
sahilmgandhi	18:6a4db94011d3	15047
sahilmgandhi	18:6a4db94011d3	15048	#define FMC_MPSTS_ISPFF_Pos (2) /!< FMC MPSTS: ISPFF Position /
sahilmgandhi	18:6a4db94011d3	15049	#define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /!< FMC MPSTS: ISPFF Mask /
sahilmgandhi	18:6a4db94011d3	15050
sahilmgandhi	18:6a4db94011d3	15051	#define FMC_MPSTS_D0_Pos (4) /!< FMC MPSTS: D0 Position /
sahilmgandhi	18:6a4db94011d3	15052	#define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /!< FMC MPSTS: D0 Mask /
sahilmgandhi	18:6a4db94011d3	15053
sahilmgandhi	18:6a4db94011d3	15054	#define FMC_MPSTS_D1_Pos (5) /!< FMC MPSTS: D1 Position /
sahilmgandhi	18:6a4db94011d3	15055	#define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /!< FMC MPSTS: D1 Mask /
sahilmgandhi	18:6a4db94011d3	15056
sahilmgandhi	18:6a4db94011d3	15057	#define FMC_MPSTS_D2_Pos (6) /!< FMC MPSTS: D2 Position /
sahilmgandhi	18:6a4db94011d3	15058	#define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /!< FMC MPSTS: D2 Mask /
sahilmgandhi	18:6a4db94011d3	15059
sahilmgandhi	18:6a4db94011d3	15060	#define FMC_MPSTS_D3_Pos (7) /!< FMC MPSTS: D3 Position /
sahilmgandhi	18:6a4db94011d3	15061	#define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /!< FMC MPSTS: D3 Mask /
sahilmgandhi	18:6a4db94011d3	15062
sahilmgandhi	18:6a4db94011d3	15063	#define FMC_MPADDR_MPADDR_Pos (0) /!< FMC MPADDR: MPADDR Position /
sahilmgandhi	18:6a4db94011d3	15064	#define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /!< FMC MPADDR: MPADDR Mask /
sahilmgandhi	18:6a4db94011d3	15065
sahilmgandhi	18:6a4db94011d3	15066	/*@}/ /* FMC_CONST */
sahilmgandhi	18:6a4db94011d3	15067	/*@}/ /* end of FMC register group */
sahilmgandhi	18:6a4db94011d3	15068
sahilmgandhi	18:6a4db94011d3	15069
sahilmgandhi	18:6a4db94011d3	15070	/---------------------- General Purpose Input/Output Controller -------------------------/
sahilmgandhi	18:6a4db94011d3	15071	/**
sahilmgandhi	18:6a4db94011d3	15072	@addtogroup GPIO General Purpose Input/Output Controller(GPIO)
sahilmgandhi	18:6a4db94011d3	15073	Memory Mapped Structure for GPIO Controller
sahilmgandhi	18:6a4db94011d3	15074	@{ */
sahilmgandhi	18:6a4db94011d3	15075
sahilmgandhi	18:6a4db94011d3	15076	typedef struct {
sahilmgandhi	18:6a4db94011d3	15077
sahilmgandhi	18:6a4db94011d3	15078
sahilmgandhi	18:6a4db94011d3	15079	/**
sahilmgandhi	18:6a4db94011d3	15080	* Px_MODE
sahilmgandhi	18:6a4db94011d3	15081	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	15082	* Offset: 0x00 Px I/O Mode Control
sahilmgandhi	18:6a4db94011d3	15083	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	15084	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	15085	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	15086	* \|[0:1] \|MODE0 \|Port N Bit M I/O Mode Control
sahilmgandhi	18:6a4db94011d3	15087	* \| \| \|Determine the I/O mode of port n bit m.
sahilmgandhi	18:6a4db94011d3	15088	* \| \| \|00 = INPUT only mode.
sahilmgandhi	18:6a4db94011d3	15089	* \| \| \|01 = OUTPUT mode.
sahilmgandhi	18:6a4db94011d3	15090	* \| \| \|10 = Open-drain mode.
sahilmgandhi	18:6a4db94011d3	15091	* \| \| \|11 = Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15092	* \| \| \|Reset value:
sahilmgandhi	18:6a4db94011d3	15093	* \| \| \|0xFFFF_FFFF when ( cfg_io =1'b0).
sahilmgandhi	18:6a4db94011d3	15094	* \| \| \|0x0000_00000 when ( cfg_io =1'b1).
sahilmgandhi	18:6a4db94011d3	15095	* \|[2:3] \|MODE1 \|Port N Bit M I/O Mode Control
sahilmgandhi	18:6a4db94011d3	15096	* \| \| \|Determine the I/O mode of port n bit m.
sahilmgandhi	18:6a4db94011d3	15097	* \| \| \|00 = INPUT only mode.
sahilmgandhi	18:6a4db94011d3	15098	* \| \| \|01 = OUTPUT mode.
sahilmgandhi	18:6a4db94011d3	15099	* \| \| \|10 = Open-drain mode.
sahilmgandhi	18:6a4db94011d3	15100	* \| \| \|11 = Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15101	* \| \| \|Reset value:
sahilmgandhi	18:6a4db94011d3	15102	* \| \| \|0xFFFF_FFFF when ( cfg_io =1'b0).
sahilmgandhi	18:6a4db94011d3	15103	* \| \| \|0x0000_00000 when ( cfg_io =1'b1).
sahilmgandhi	18:6a4db94011d3	15104	* \|[4:5] \|MODE2 \|Port N Bit M I/O Mode Control
sahilmgandhi	18:6a4db94011d3	15105	* \| \| \|Determine the I/O mode of port n bit m.
sahilmgandhi	18:6a4db94011d3	15106	* \| \| \|00 = INPUT only mode.
sahilmgandhi	18:6a4db94011d3	15107	* \| \| \|01 = OUTPUT mode.
sahilmgandhi	18:6a4db94011d3	15108	* \| \| \|10 = Open-drain mode.
sahilmgandhi	18:6a4db94011d3	15109	* \| \| \|11 = Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15110	* \| \| \|Reset value:
sahilmgandhi	18:6a4db94011d3	15111	* \| \| \|0xFFFF_FFFF when ( cfg_io =1'b0).
sahilmgandhi	18:6a4db94011d3	15112	* \| \| \|0x0000_00000 when ( cfg_io =1'b1).
sahilmgandhi	18:6a4db94011d3	15113	* \|[6:7] \|MODE3 \|Port N Bit M I/O Mode Control
sahilmgandhi	18:6a4db94011d3	15114	* \| \| \|Determine the I/O mode of port n bit m.
sahilmgandhi	18:6a4db94011d3	15115	* \| \| \|00 = INPUT only mode.
sahilmgandhi	18:6a4db94011d3	15116	* \| \| \|01 = OUTPUT mode.
sahilmgandhi	18:6a4db94011d3	15117	* \| \| \|10 = Open-drain mode.
sahilmgandhi	18:6a4db94011d3	15118	* \| \| \|11 = Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15119	* \| \| \|Reset value:
sahilmgandhi	18:6a4db94011d3	15120	* \| \| \|0xFFFF_FFFF when ( cfg_io =1'b0).
sahilmgandhi	18:6a4db94011d3	15121	* \| \| \|0x0000_00000 when ( cfg_io =1'b1).
sahilmgandhi	18:6a4db94011d3	15122	* \|[8:9] \|MODE4 \|Port N Bit M I/O Mode Control
sahilmgandhi	18:6a4db94011d3	15123	* \| \| \|Determine the I/O mode of port n bit m.
sahilmgandhi	18:6a4db94011d3	15124	* \| \| \|00 = INPUT only mode.
sahilmgandhi	18:6a4db94011d3	15125	* \| \| \|01 = OUTPUT mode.
sahilmgandhi	18:6a4db94011d3	15126	* \| \| \|10 = Open-drain mode.
sahilmgandhi	18:6a4db94011d3	15127	* \| \| \|11 = Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15128	* \| \| \|Reset value:
sahilmgandhi	18:6a4db94011d3	15129	* \| \| \|0xFFFF_FFFF when ( cfg_io =1'b0).
sahilmgandhi	18:6a4db94011d3	15130	* \| \| \|0x0000_00000 when ( cfg_io =1'b1).
sahilmgandhi	18:6a4db94011d3	15131	* \|[10:11] \|MODE5 \|Port N Bit M I/O Mode Control
sahilmgandhi	18:6a4db94011d3	15132	* \| \| \|Determine the I/O mode of port n bit m.
sahilmgandhi	18:6a4db94011d3	15133	* \| \| \|00 = INPUT only mode.
sahilmgandhi	18:6a4db94011d3	15134	* \| \| \|01 = OUTPUT mode.
sahilmgandhi	18:6a4db94011d3	15135	* \| \| \|10 = Open-drain mode.
sahilmgandhi	18:6a4db94011d3	15136	* \| \| \|11 = Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15137	* \| \| \|Reset value:
sahilmgandhi	18:6a4db94011d3	15138	* \| \| \|0xFFFF_FFFF when ( cfg_io =1'b0).
sahilmgandhi	18:6a4db94011d3	15139	* \| \| \|0x0000_00000 when ( cfg_io =1'b1).
sahilmgandhi	18:6a4db94011d3	15140	* \|[12:13] \|MODE6 \|Port N Bit M I/O Mode Control
sahilmgandhi	18:6a4db94011d3	15141	* \| \| \|Determine the I/O mode of port n bit m.
sahilmgandhi	18:6a4db94011d3	15142	* \| \| \|00 = INPUT only mode.
sahilmgandhi	18:6a4db94011d3	15143	* \| \| \|01 = OUTPUT mode.
sahilmgandhi	18:6a4db94011d3	15144	* \| \| \|10 = Open-drain mode.
sahilmgandhi	18:6a4db94011d3	15145	* \| \| \|11 = Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15146	* \| \| \|Reset value:
sahilmgandhi	18:6a4db94011d3	15147	* \| \| \|0xFFFF_FFFF when ( cfg_io =1'b0).
sahilmgandhi	18:6a4db94011d3	15148	* \| \| \|0x0000_00000 when ( cfg_io =1'b1).
sahilmgandhi	18:6a4db94011d3	15149	* \|[14:15] \|MODE7 \|Port N Bit M I/O Mode Control
sahilmgandhi	18:6a4db94011d3	15150	* \| \| \|Determine the I/O mode of port n bit m.
sahilmgandhi	18:6a4db94011d3	15151	* \| \| \|00 = INPUT only mode.
sahilmgandhi	18:6a4db94011d3	15152	* \| \| \|01 = OUTPUT mode.
sahilmgandhi	18:6a4db94011d3	15153	* \| \| \|10 = Open-drain mode.
sahilmgandhi	18:6a4db94011d3	15154	* \| \| \|11 = Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15155	* \| \| \|Reset value:
sahilmgandhi	18:6a4db94011d3	15156	* \| \| \|0xFFFF_FFFF when ( cfg_io =1'b0).
sahilmgandhi	18:6a4db94011d3	15157	* \| \| \|0x0000_00000 when ( cfg_io =1'b1).
sahilmgandhi	18:6a4db94011d3	15158	* \|[16:17] \|MODE8 \|Port N Bit M I/O Mode Control
sahilmgandhi	18:6a4db94011d3	15159	* \| \| \|Determine the I/O mode of port n bit m.
sahilmgandhi	18:6a4db94011d3	15160	* \| \| \|00 = INPUT only mode.
sahilmgandhi	18:6a4db94011d3	15161	* \| \| \|01 = OUTPUT mode.
sahilmgandhi	18:6a4db94011d3	15162	* \| \| \|10 = Open-drain mode.
sahilmgandhi	18:6a4db94011d3	15163	* \| \| \|11 = Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15164	* \| \| \|Reset value:
sahilmgandhi	18:6a4db94011d3	15165	* \| \| \|0xFFFF_FFFF when ( cfg_io =1'b0).
sahilmgandhi	18:6a4db94011d3	15166	* \| \| \|0x0000_00000 when ( cfg_io =1'b1).
sahilmgandhi	18:6a4db94011d3	15167	* \|[18:19] \|MODE9 \|Port N Bit M I/O Mode Control
sahilmgandhi	18:6a4db94011d3	15168	* \| \| \|Determine the I/O mode of port n bit m.
sahilmgandhi	18:6a4db94011d3	15169	* \| \| \|00 = INPUT only mode.
sahilmgandhi	18:6a4db94011d3	15170	* \| \| \|01 = OUTPUT mode.
sahilmgandhi	18:6a4db94011d3	15171	* \| \| \|10 = Open-drain mode.
sahilmgandhi	18:6a4db94011d3	15172	* \| \| \|11 = Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15173	* \| \| \|Reset value:
sahilmgandhi	18:6a4db94011d3	15174	* \| \| \|0xFFFF_FFFF when ( cfg_io =1'b0).
sahilmgandhi	18:6a4db94011d3	15175	* \| \| \|0x0000_00000 when ( cfg_io =1'b1).
sahilmgandhi	18:6a4db94011d3	15176	* \|[20:21] \|MODE10 \|Port N Bit M I/O Mode Control
sahilmgandhi	18:6a4db94011d3	15177	* \| \| \|Determine the I/O mode of port n bit m.
sahilmgandhi	18:6a4db94011d3	15178	* \| \| \|00 = INPUT only mode.
sahilmgandhi	18:6a4db94011d3	15179	* \| \| \|01 = OUTPUT mode.
sahilmgandhi	18:6a4db94011d3	15180	* \| \| \|10 = Open-drain mode.
sahilmgandhi	18:6a4db94011d3	15181	* \| \| \|11 = Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15182	* \| \| \|Reset value:
sahilmgandhi	18:6a4db94011d3	15183	* \| \| \|0xFFFF_FFFF when ( cfg_io =1'b0).
sahilmgandhi	18:6a4db94011d3	15184	* \| \| \|0x0000_00000 when ( cfg_io =1'b1).
sahilmgandhi	18:6a4db94011d3	15185	* \|[22:23] \|MODE11 \|Port N Bit M I/O Mode Control
sahilmgandhi	18:6a4db94011d3	15186	* \| \| \|Determine the I/O mode of port n bit m.
sahilmgandhi	18:6a4db94011d3	15187	* \| \| \|00 = INPUT only mode.
sahilmgandhi	18:6a4db94011d3	15188	* \| \| \|01 = OUTPUT mode.
sahilmgandhi	18:6a4db94011d3	15189	* \| \| \|10 = Open-drain mode.
sahilmgandhi	18:6a4db94011d3	15190	* \| \| \|11 = Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15191	* \| \| \|Reset value:
sahilmgandhi	18:6a4db94011d3	15192	* \| \| \|0xFFFF_FFFF when ( cfg_io =1'b0).
sahilmgandhi	18:6a4db94011d3	15193	* \| \| \|0x0000_00000 when ( cfg_io =1'b1).
sahilmgandhi	18:6a4db94011d3	15194	* \|[24:25] \|MODE12 \|Port N Bit M I/O Mode Control
sahilmgandhi	18:6a4db94011d3	15195	* \| \| \|Determine the I/O mode of port n bit m.
sahilmgandhi	18:6a4db94011d3	15196	* \| \| \|00 = INPUT only mode.
sahilmgandhi	18:6a4db94011d3	15197	* \| \| \|01 = OUTPUT mode.
sahilmgandhi	18:6a4db94011d3	15198	* \| \| \|10 = Open-drain mode.
sahilmgandhi	18:6a4db94011d3	15199	* \| \| \|11 = Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15200	* \| \| \|Reset value:
sahilmgandhi	18:6a4db94011d3	15201	* \| \| \|0xFFFF_FFFF when ( cfg_io =1'b0).
sahilmgandhi	18:6a4db94011d3	15202	* \| \| \|0x0000_00000 when ( cfg_io =1'b1).
sahilmgandhi	18:6a4db94011d3	15203	* \|[26:27] \|MODE13 \|Port N Bit M I/O Mode Control
sahilmgandhi	18:6a4db94011d3	15204	* \| \| \|Determine the I/O mode of port n bit m.
sahilmgandhi	18:6a4db94011d3	15205	* \| \| \|00 = INPUT only mode.
sahilmgandhi	18:6a4db94011d3	15206	* \| \| \|01 = OUTPUT mode.
sahilmgandhi	18:6a4db94011d3	15207	* \| \| \|10 = Open-drain mode.
sahilmgandhi	18:6a4db94011d3	15208	* \| \| \|11 = Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15209	* \| \| \|Reset value:
sahilmgandhi	18:6a4db94011d3	15210	* \| \| \|0xFFFF_FFFF when ( cfg_io =1'b0).
sahilmgandhi	18:6a4db94011d3	15211	* \| \| \|0x0000_00000 when ( cfg_io =1'b1).
sahilmgandhi	18:6a4db94011d3	15212	* \|[28:29] \|MODE14 \|Port N Bit M I/O Mode Control
sahilmgandhi	18:6a4db94011d3	15213	* \| \| \|Determine the I/O mode of port n bit m.
sahilmgandhi	18:6a4db94011d3	15214	* \| \| \|00 = INPUT only mode.
sahilmgandhi	18:6a4db94011d3	15215	* \| \| \|01 = OUTPUT mode.
sahilmgandhi	18:6a4db94011d3	15216	* \| \| \|10 = Open-drain mode.
sahilmgandhi	18:6a4db94011d3	15217	* \| \| \|11 = Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15218	* \| \| \|Reset value:
sahilmgandhi	18:6a4db94011d3	15219	* \| \| \|0xFFFF_FFFF when ( cfg_io =1'b0).
sahilmgandhi	18:6a4db94011d3	15220	* \| \| \|0x0000_00000 when ( cfg_io =1'b1).
sahilmgandhi	18:6a4db94011d3	15221	* \|[30:31] \|MODE15 \|Port N Bit M I/O Mode Control
sahilmgandhi	18:6a4db94011d3	15222	* \| \| \|Determine the I/O mode of port n bit m.
sahilmgandhi	18:6a4db94011d3	15223	* \| \| \|00 = INPUT only mode.
sahilmgandhi	18:6a4db94011d3	15224	* \| \| \|01 = OUTPUT mode.
sahilmgandhi	18:6a4db94011d3	15225	* \| \| \|10 = Open-drain mode.
sahilmgandhi	18:6a4db94011d3	15226	* \| \| \|11 = Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15227	* \| \| \|Reset value:
sahilmgandhi	18:6a4db94011d3	15228	* \| \| \|0xFFFF_FFFF when ( cfg_io =1'b0).
sahilmgandhi	18:6a4db94011d3	15229	* \| \| \|0x0000_00000 when ( cfg_io =1'b1).
sahilmgandhi	18:6a4db94011d3	15230	*/
sahilmgandhi	18:6a4db94011d3	15231	__IO uint32_t MODE;
sahilmgandhi	18:6a4db94011d3	15232
sahilmgandhi	18:6a4db94011d3	15233	/**
sahilmgandhi	18:6a4db94011d3	15234	* Px_DINOFF
sahilmgandhi	18:6a4db94011d3	15235	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	15236	* Offset: 0x04 Px Digital Input Path Disable Control
sahilmgandhi	18:6a4db94011d3	15237	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	15238	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	15239	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	15240	* \|[16] \|DINOFF0 \|Port N Bit M Off Digital Input Path
sahilmgandhi	18:6a4db94011d3	15241	* \| \| \|Each of these bits is used to turn off the digital input path of port n bit m pin.
sahilmgandhi	18:6a4db94011d3	15242	* \| \| \|If input is analog signal, users can turn off digital input path to avoid input current leakage.
sahilmgandhi	18:6a4db94011d3	15243	* \| \| \|0 = Digital input path Enabled.
sahilmgandhi	18:6a4db94011d3	15244	* \| \| \|1 = Digital input path Disabled (Digital input is tied to low).
sahilmgandhi	18:6a4db94011d3	15245	* \|[17] \|DINOFF1 \|Port N Bit M Off Digital Input Path
sahilmgandhi	18:6a4db94011d3	15246	* \| \| \|Each of these bits is used to turn off the digital input path of port n bit m pin.
sahilmgandhi	18:6a4db94011d3	15247	* \| \| \|If input is analog signal, users can turn off digital input path to avoid input current leakage.
sahilmgandhi	18:6a4db94011d3	15248	* \| \| \|0 = Digital input path Enabled.
sahilmgandhi	18:6a4db94011d3	15249	* \| \| \|1 = Digital input path Disabled (Digital input is tied to low).
sahilmgandhi	18:6a4db94011d3	15250	* \|[18] \|DINOFF2 \|Port N Bit M Off Digital Input Path
sahilmgandhi	18:6a4db94011d3	15251	* \| \| \|Each of these bits is used to turn off the digital input path of port n bit m pin.
sahilmgandhi	18:6a4db94011d3	15252	* \| \| \|If input is analog signal, users can turn off digital input path to avoid input current leakage.
sahilmgandhi	18:6a4db94011d3	15253	* \| \| \|0 = Digital input path Enabled.
sahilmgandhi	18:6a4db94011d3	15254	* \| \| \|1 = Digital input path Disabled (Digital input is tied to low).
sahilmgandhi	18:6a4db94011d3	15255	* \|[19] \|DINOFF3 \|Port N Bit M Off Digital Input Path
sahilmgandhi	18:6a4db94011d3	15256	* \| \| \|Each of these bits is used to turn off the digital input path of port n bit m pin.
sahilmgandhi	18:6a4db94011d3	15257	* \| \| \|If input is analog signal, users can turn off digital input path to avoid input current leakage.
sahilmgandhi	18:6a4db94011d3	15258	* \| \| \|0 = Digital input path Enabled.
sahilmgandhi	18:6a4db94011d3	15259	* \| \| \|1 = Digital input path Disabled (Digital input is tied to low).
sahilmgandhi	18:6a4db94011d3	15260	* \|[20] \|DINOFF4 \|Port N Bit M Off Digital Input Path
sahilmgandhi	18:6a4db94011d3	15261	* \| \| \|Each of these bits is used to turn off the digital input path of port n bit m pin.
sahilmgandhi	18:6a4db94011d3	15262	* \| \| \|If input is analog signal, users can turn off digital input path to avoid input current leakage.
sahilmgandhi	18:6a4db94011d3	15263	* \| \| \|0 = Digital input path Enabled.
sahilmgandhi	18:6a4db94011d3	15264	* \| \| \|1 = Digital input path Disabled (Digital input is tied to low).
sahilmgandhi	18:6a4db94011d3	15265	* \|[21] \|DINOFF5 \|Port N Bit M Off Digital Input Path
sahilmgandhi	18:6a4db94011d3	15266	* \| \| \|Each of these bits is used to turn off the digital input path of port n bit m pin.
sahilmgandhi	18:6a4db94011d3	15267	* \| \| \|If input is analog signal, users can turn off digital input path to avoid input current leakage.
sahilmgandhi	18:6a4db94011d3	15268	* \| \| \|0 = Digital input path Enabled.
sahilmgandhi	18:6a4db94011d3	15269	* \| \| \|1 = Digital input path Disabled (Digital input is tied to low).
sahilmgandhi	18:6a4db94011d3	15270	* \|[22] \|DINOFF6 \|Port N Bit M Off Digital Input Path
sahilmgandhi	18:6a4db94011d3	15271	* \| \| \|Each of these bits is used to turn off the digital input path of port n bit m pin.
sahilmgandhi	18:6a4db94011d3	15272	* \| \| \|If input is analog signal, users can turn off digital input path to avoid input current leakage.
sahilmgandhi	18:6a4db94011d3	15273	* \| \| \|0 = Digital input path Enabled.
sahilmgandhi	18:6a4db94011d3	15274	* \| \| \|1 = Digital input path Disabled (Digital input is tied to low).
sahilmgandhi	18:6a4db94011d3	15275	* \|[23] \|DINOFF7 \|Port N Bit M Off Digital Input Path
sahilmgandhi	18:6a4db94011d3	15276	* \| \| \|Each of these bits is used to turn off the digital input path of port n bit m pin.
sahilmgandhi	18:6a4db94011d3	15277	* \| \| \|If input is analog signal, users can turn off digital input path to avoid input current leakage.
sahilmgandhi	18:6a4db94011d3	15278	* \| \| \|0 = Digital input path Enabled.
sahilmgandhi	18:6a4db94011d3	15279	* \| \| \|1 = Digital input path Disabled (Digital input is tied to low).
sahilmgandhi	18:6a4db94011d3	15280	* \|[24] \|DINOFF8 \|Port N Bit M Off Digital Input Path
sahilmgandhi	18:6a4db94011d3	15281	* \| \| \|Each of these bits is used to turn off the digital input path of port n bit m pin.
sahilmgandhi	18:6a4db94011d3	15282	* \| \| \|If input is analog signal, users can turn off digital input path to avoid input current leakage.
sahilmgandhi	18:6a4db94011d3	15283	* \| \| \|0 = Digital input path Enabled.
sahilmgandhi	18:6a4db94011d3	15284	* \| \| \|1 = Digital input path Disabled (Digital input is tied to low).
sahilmgandhi	18:6a4db94011d3	15285	* \|[25] \|DINOFF9 \|Port N Bit M Off Digital Input Path
sahilmgandhi	18:6a4db94011d3	15286	* \| \| \|Each of these bits is used to turn off the digital input path of port n bit m pin.
sahilmgandhi	18:6a4db94011d3	15287	* \| \| \|If input is analog signal, users can turn off digital input path to avoid input current leakage.
sahilmgandhi	18:6a4db94011d3	15288	* \| \| \|0 = Digital input path Enabled.
sahilmgandhi	18:6a4db94011d3	15289	* \| \| \|1 = Digital input path Disabled (Digital input is tied to low).
sahilmgandhi	18:6a4db94011d3	15290	* \|[26] \|DINOFF10 \|Port N Bit M Off Digital Input Path
sahilmgandhi	18:6a4db94011d3	15291	* \| \| \|Each of these bits is used to turn off the digital input path of port n bit m pin.
sahilmgandhi	18:6a4db94011d3	15292	* \| \| \|If input is analog signal, users can turn off digital input path to avoid input current leakage.
sahilmgandhi	18:6a4db94011d3	15293	* \| \| \|0 = Digital input path Enabled.
sahilmgandhi	18:6a4db94011d3	15294	* \| \| \|1 = Digital input path Disabled (Digital input is tied to low).
sahilmgandhi	18:6a4db94011d3	15295	* \|[27] \|DINOFF11 \|Port N Bit M Off Digital Input Path
sahilmgandhi	18:6a4db94011d3	15296	* \| \| \|Each of these bits is used to turn off the digital input path of port n bit m pin.
sahilmgandhi	18:6a4db94011d3	15297	* \| \| \|If input is analog signal, users can turn off digital input path to avoid input current leakage.
sahilmgandhi	18:6a4db94011d3	15298	* \| \| \|0 = Digital input path Enabled.
sahilmgandhi	18:6a4db94011d3	15299	* \| \| \|1 = Digital input path Disabled (Digital input is tied to low).
sahilmgandhi	18:6a4db94011d3	15300	* \|[28] \|DINOFF12 \|Port N Bit M Off Digital Input Path
sahilmgandhi	18:6a4db94011d3	15301	* \| \| \|Each of these bits is used to turn off the digital input path of port n bit m pin.
sahilmgandhi	18:6a4db94011d3	15302	* \| \| \|If input is analog signal, users can turn off digital input path to avoid input current leakage.
sahilmgandhi	18:6a4db94011d3	15303	* \| \| \|0 = Digital input path Enabled.
sahilmgandhi	18:6a4db94011d3	15304	* \| \| \|1 = Digital input path Disabled (Digital input is tied to low).
sahilmgandhi	18:6a4db94011d3	15305	* \|[29] \|DINOFF13 \|Port N Bit M Off Digital Input Path
sahilmgandhi	18:6a4db94011d3	15306	* \| \| \|Each of these bits is used to turn off the digital input path of port n bit m pin.
sahilmgandhi	18:6a4db94011d3	15307	* \| \| \|If input is analog signal, users can turn off digital input path to avoid input current leakage.
sahilmgandhi	18:6a4db94011d3	15308	* \| \| \|0 = Digital input path Enabled.
sahilmgandhi	18:6a4db94011d3	15309	* \| \| \|1 = Digital input path Disabled (Digital input is tied to low).
sahilmgandhi	18:6a4db94011d3	15310	* \|[30] \|DINOFF14 \|Port N Bit M Off Digital Input Path
sahilmgandhi	18:6a4db94011d3	15311	* \| \| \|Each of these bits is used to turn off the digital input path of port n bit m pin.
sahilmgandhi	18:6a4db94011d3	15312	* \| \| \|If input is analog signal, users can turn off digital input path to avoid input current leakage.
sahilmgandhi	18:6a4db94011d3	15313	* \| \| \|0 = Digital input path Enabled.
sahilmgandhi	18:6a4db94011d3	15314	* \| \| \|1 = Digital input path Disabled (Digital input is tied to low).
sahilmgandhi	18:6a4db94011d3	15315	* \|[31] \|DINOFF15 \|Port N Bit M Off Digital Input Path
sahilmgandhi	18:6a4db94011d3	15316	* \| \| \|Each of these bits is used to turn off the digital input path of port n bit m pin.
sahilmgandhi	18:6a4db94011d3	15317	* \| \| \|If input is analog signal, users can turn off digital input path to avoid input current leakage.
sahilmgandhi	18:6a4db94011d3	15318	* \| \| \|0 = Digital input path Enabled.
sahilmgandhi	18:6a4db94011d3	15319	* \| \| \|1 = Digital input path Disabled (Digital input is tied to low).
sahilmgandhi	18:6a4db94011d3	15320	*/
sahilmgandhi	18:6a4db94011d3	15321	__IO uint32_t DINOFF;
sahilmgandhi	18:6a4db94011d3	15322
sahilmgandhi	18:6a4db94011d3	15323	/**
sahilmgandhi	18:6a4db94011d3	15324	* Px_DOUT
sahilmgandhi	18:6a4db94011d3	15325	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	15326	* Offset: 0x08 Px Data Output Value
sahilmgandhi	18:6a4db94011d3	15327	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	15328	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	15329	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	15330	* \|[0] \|DOUT0 \|Port N Bit M Output
sahilmgandhi	18:6a4db94011d3	15331	* \| \| \|Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15332	* \| \| \|0 = Drive port n bit m high low.
sahilmgandhi	18:6a4db94011d3	15333	* \| \| \|1 = Drive port n bit m high level.
sahilmgandhi	18:6a4db94011d3	15334	* \|[1] \|DOUT1 \|Port N Bit M Output
sahilmgandhi	18:6a4db94011d3	15335	* \| \| \|Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15336	* \| \| \|0 = Drive port n bit m high low.
sahilmgandhi	18:6a4db94011d3	15337	* \| \| \|1 = Drive port n bit m high level.
sahilmgandhi	18:6a4db94011d3	15338	* \|[2] \|DOUT2 \|Port N Bit M Output
sahilmgandhi	18:6a4db94011d3	15339	* \| \| \|Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15340	* \| \| \|0 = Drive port n bit m high low.
sahilmgandhi	18:6a4db94011d3	15341	* \| \| \|1 = Drive port n bit m high level.
sahilmgandhi	18:6a4db94011d3	15342	* \|[3] \|DOUT3 \|Port N Bit M Output
sahilmgandhi	18:6a4db94011d3	15343	* \| \| \|Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15344	* \| \| \|0 = Drive port n bit m high low.
sahilmgandhi	18:6a4db94011d3	15345	* \| \| \|1 = Drive port n bit m high level.
sahilmgandhi	18:6a4db94011d3	15346	* \|[4] \|DOUT4 \|Port N Bit M Output
sahilmgandhi	18:6a4db94011d3	15347	* \| \| \|Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15348	* \| \| \|0 = Drive port n bit m high low.
sahilmgandhi	18:6a4db94011d3	15349	* \| \| \|1 = Drive port n bit m high level.
sahilmgandhi	18:6a4db94011d3	15350	* \|[5] \|DOUT5 \|Port N Bit M Output
sahilmgandhi	18:6a4db94011d3	15351	* \| \| \|Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15352	* \| \| \|0 = Drive port n bit m high low.
sahilmgandhi	18:6a4db94011d3	15353	* \| \| \|1 = Drive port n bit m high level.
sahilmgandhi	18:6a4db94011d3	15354	* \|[6] \|DOUT6 \|Port N Bit M Output
sahilmgandhi	18:6a4db94011d3	15355	* \| \| \|Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15356	* \| \| \|0 = Drive port n bit m high low.
sahilmgandhi	18:6a4db94011d3	15357	* \| \| \|1 = Drive port n bit m high level.
sahilmgandhi	18:6a4db94011d3	15358	* \|[7] \|DOUT7 \|Port N Bit M Output
sahilmgandhi	18:6a4db94011d3	15359	* \| \| \|Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15360	* \| \| \|0 = Drive port n bit m high low.
sahilmgandhi	18:6a4db94011d3	15361	* \| \| \|1 = Drive port n bit m high level.
sahilmgandhi	18:6a4db94011d3	15362	* \|[8] \|DOUT8 \|Port N Bit M Output
sahilmgandhi	18:6a4db94011d3	15363	* \| \| \|Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15364	* \| \| \|0 = Drive port n bit m high low.
sahilmgandhi	18:6a4db94011d3	15365	* \| \| \|1 = Drive port n bit m high level.
sahilmgandhi	18:6a4db94011d3	15366	* \|[9] \|DOUT9 \|Port N Bit M Output
sahilmgandhi	18:6a4db94011d3	15367	* \| \| \|Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15368	* \| \| \|0 = Drive port n bit m high low.
sahilmgandhi	18:6a4db94011d3	15369	* \| \| \|1 = Drive port n bit m high level.
sahilmgandhi	18:6a4db94011d3	15370	* \|[10] \|DOUT10 \|Port N Bit M Output
sahilmgandhi	18:6a4db94011d3	15371	* \| \| \|Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15372	* \| \| \|0 = Drive port n bit m high low.
sahilmgandhi	18:6a4db94011d3	15373	* \| \| \|1 = Drive port n bit m high level.
sahilmgandhi	18:6a4db94011d3	15374	* \|[11] \|DOUT11 \|Port N Bit M Output
sahilmgandhi	18:6a4db94011d3	15375	* \| \| \|Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15376	* \| \| \|0 = Drive port n bit m high low.
sahilmgandhi	18:6a4db94011d3	15377	* \| \| \|1 = Drive port n bit m high level.
sahilmgandhi	18:6a4db94011d3	15378	* \|[12] \|DOUT12 \|Port N Bit M Output
sahilmgandhi	18:6a4db94011d3	15379	* \| \| \|Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15380	* \| \| \|0 = Drive port n bit m high low.
sahilmgandhi	18:6a4db94011d3	15381	* \| \| \|1 = Drive port n bit m high level.
sahilmgandhi	18:6a4db94011d3	15382	* \|[13] \|DOUT13 \|Port N Bit M Output
sahilmgandhi	18:6a4db94011d3	15383	* \| \| \|Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15384	* \| \| \|0 = Drive port n bit m high low.
sahilmgandhi	18:6a4db94011d3	15385	* \| \| \|1 = Drive port n bit m high level.
sahilmgandhi	18:6a4db94011d3	15386	* \|[14] \|DOUT14 \|Port N Bit M Output
sahilmgandhi	18:6a4db94011d3	15387	* \| \| \|Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15388	* \| \| \|0 = Drive port n bit m high low.
sahilmgandhi	18:6a4db94011d3	15389	* \| \| \|1 = Drive port n bit m high level.
sahilmgandhi	18:6a4db94011d3	15390	* \|[15] \|DOUT15 \|Port N Bit M Output
sahilmgandhi	18:6a4db94011d3	15391	* \| \| \|Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
sahilmgandhi	18:6a4db94011d3	15392	* \| \| \|0 = Drive port n bit m high low.
sahilmgandhi	18:6a4db94011d3	15393	* \| \| \|1 = Drive port n bit m high level.
sahilmgandhi	18:6a4db94011d3	15394	*/
sahilmgandhi	18:6a4db94011d3	15395	__IO uint32_t DOUT;
sahilmgandhi	18:6a4db94011d3	15396
sahilmgandhi	18:6a4db94011d3	15397	/**
sahilmgandhi	18:6a4db94011d3	15398	* Px_DATMSK
sahilmgandhi	18:6a4db94011d3	15399	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	15400	* Offset: 0x0C Px Data Output Write Mask
sahilmgandhi	18:6a4db94011d3	15401	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	15402	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	15403	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	15404	* \|[0] \|DATMSK0 \|Port N Bit M Data Output Write Mask
sahilmgandhi	18:6a4db94011d3	15405	* \| \| \|These bits are used to protect the corresponding register of Px_DOUT[m].
sahilmgandhi	18:6a4db94011d3	15406	* \| \| \|When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
sahilmgandhi	18:6a4db94011d3	15407	* \| \| \|The write to port pin latch is masked.
sahilmgandhi	18:6a4db94011d3	15408	* \| \| \|0 = Px_DOUT[m] bit writing is valid.
sahilmgandhi	18:6a4db94011d3	15409	* \| \| \|1 = Px_DOUT[m] bit writing is ignored.
sahilmgandhi	18:6a4db94011d3	15410	* \|[1] \|DATMSK1 \|Port N Bit M Data Output Write Mask
sahilmgandhi	18:6a4db94011d3	15411	* \| \| \|These bits are used to protect the corresponding register of Px_DOUT[m].
sahilmgandhi	18:6a4db94011d3	15412	* \| \| \|When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
sahilmgandhi	18:6a4db94011d3	15413	* \| \| \|The write to port pin latch is masked.
sahilmgandhi	18:6a4db94011d3	15414	* \| \| \|0 = Px_DOUT[m] bit writing is valid.
sahilmgandhi	18:6a4db94011d3	15415	* \| \| \|1 = Px_DOUT[m] bit writing is ignored.
sahilmgandhi	18:6a4db94011d3	15416	* \|[2] \|DATMSK2 \|Port N Bit M Data Output Write Mask
sahilmgandhi	18:6a4db94011d3	15417	* \| \| \|These bits are used to protect the corresponding register of Px_DOUT[m].
sahilmgandhi	18:6a4db94011d3	15418	* \| \| \|When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
sahilmgandhi	18:6a4db94011d3	15419	* \| \| \|The write to port pin latch is masked.
sahilmgandhi	18:6a4db94011d3	15420	* \| \| \|0 = Px_DOUT[m] bit writing is valid.
sahilmgandhi	18:6a4db94011d3	15421	* \| \| \|1 = Px_DOUT[m] bit writing is ignored.
sahilmgandhi	18:6a4db94011d3	15422	* \|[3] \|DATMSK3 \|Port N Bit M Data Output Write Mask
sahilmgandhi	18:6a4db94011d3	15423	* \| \| \|These bits are used to protect the corresponding register of Px_DOUT[m].
sahilmgandhi	18:6a4db94011d3	15424	* \| \| \|When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
sahilmgandhi	18:6a4db94011d3	15425	* \| \| \|The write to port pin latch is masked.
sahilmgandhi	18:6a4db94011d3	15426	* \| \| \|0 = Px_DOUT[m] bit writing is valid.
sahilmgandhi	18:6a4db94011d3	15427	* \| \| \|1 = Px_DOUT[m] bit writing is ignored.
sahilmgandhi	18:6a4db94011d3	15428	* \|[4] \|DATMSK4 \|Port N Bit M Data Output Write Mask
sahilmgandhi	18:6a4db94011d3	15429	* \| \| \|These bits are used to protect the corresponding register of Px_DOUT[m].
sahilmgandhi	18:6a4db94011d3	15430	* \| \| \|When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
sahilmgandhi	18:6a4db94011d3	15431	* \| \| \|The write to port pin latch is masked.
sahilmgandhi	18:6a4db94011d3	15432	* \| \| \|0 = Px_DOUT[m] bit writing is valid.
sahilmgandhi	18:6a4db94011d3	15433	* \| \| \|1 = Px_DOUT[m] bit writing is ignored.
sahilmgandhi	18:6a4db94011d3	15434	* \|[5] \|DATMSK5 \|Port N Bit M Data Output Write Mask
sahilmgandhi	18:6a4db94011d3	15435	* \| \| \|These bits are used to protect the corresponding register of Px_DOUT[m].
sahilmgandhi	18:6a4db94011d3	15436	* \| \| \|When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
sahilmgandhi	18:6a4db94011d3	15437	* \| \| \|The write to port pin latch is masked.
sahilmgandhi	18:6a4db94011d3	15438	* \| \| \|0 = Px_DOUT[m] bit writing is valid.
sahilmgandhi	18:6a4db94011d3	15439	* \| \| \|1 = Px_DOUT[m] bit writing is ignored.
sahilmgandhi	18:6a4db94011d3	15440	* \|[6] \|DATMSK6 \|Port N Bit M Data Output Write Mask
sahilmgandhi	18:6a4db94011d3	15441	* \| \| \|These bits are used to protect the corresponding register of Px_DOUT[m].
sahilmgandhi	18:6a4db94011d3	15442	* \| \| \|When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
sahilmgandhi	18:6a4db94011d3	15443	* \| \| \|The write to port pin latch is masked.
sahilmgandhi	18:6a4db94011d3	15444	* \| \| \|0 = Px_DOUT[m] bit writing is valid.
sahilmgandhi	18:6a4db94011d3	15445	* \| \| \|1 = Px_DOUT[m] bit writing is ignored.
sahilmgandhi	18:6a4db94011d3	15446	* \|[7] \|DATMSK7 \|Port N Bit M Data Output Write Mask
sahilmgandhi	18:6a4db94011d3	15447	* \| \| \|These bits are used to protect the corresponding register of Px_DOUT[m].
sahilmgandhi	18:6a4db94011d3	15448	* \| \| \|When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
sahilmgandhi	18:6a4db94011d3	15449	* \| \| \|The write to port pin latch is masked.
sahilmgandhi	18:6a4db94011d3	15450	* \| \| \|0 = Px_DOUT[m] bit writing is valid.
sahilmgandhi	18:6a4db94011d3	15451	* \| \| \|1 = Px_DOUT[m] bit writing is ignored.
sahilmgandhi	18:6a4db94011d3	15452	* \|[8] \|DATMSK8 \|Port N Bit M Data Output Write Mask
sahilmgandhi	18:6a4db94011d3	15453	* \| \| \|These bits are used to protect the corresponding register of Px_DOUT[m].
sahilmgandhi	18:6a4db94011d3	15454	* \| \| \|When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
sahilmgandhi	18:6a4db94011d3	15455	* \| \| \|The write to port pin latch is masked.
sahilmgandhi	18:6a4db94011d3	15456	* \| \| \|0 = Px_DOUT[m] bit writing is valid.
sahilmgandhi	18:6a4db94011d3	15457	* \| \| \|1 = Px_DOUT[m] bit writing is ignored.
sahilmgandhi	18:6a4db94011d3	15458	* \|[9] \|DATMSK9 \|Port N Bit M Data Output Write Mask
sahilmgandhi	18:6a4db94011d3	15459	* \| \| \|These bits are used to protect the corresponding register of Px_DOUT[m].
sahilmgandhi	18:6a4db94011d3	15460	* \| \| \|When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
sahilmgandhi	18:6a4db94011d3	15461	* \| \| \|The write to port pin latch is masked.
sahilmgandhi	18:6a4db94011d3	15462	* \| \| \|0 = Px_DOUT[m] bit writing is valid.
sahilmgandhi	18:6a4db94011d3	15463	* \| \| \|1 = Px_DOUT[m] bit writing is ignored.
sahilmgandhi	18:6a4db94011d3	15464	* \|[10] \|DATMSK10 \|Port N Bit M Data Output Write Mask
sahilmgandhi	18:6a4db94011d3	15465	* \| \| \|These bits are used to protect the corresponding register of Px_DOUT[m].
sahilmgandhi	18:6a4db94011d3	15466	* \| \| \|When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
sahilmgandhi	18:6a4db94011d3	15467	* \| \| \|The write to port pin latch is masked.
sahilmgandhi	18:6a4db94011d3	15468	* \| \| \|0 = Px_DOUT[m] bit writing is valid.
sahilmgandhi	18:6a4db94011d3	15469	* \| \| \|1 = Px_DOUT[m] bit writing is ignored.
sahilmgandhi	18:6a4db94011d3	15470	* \|[11] \|DATMSK11 \|Port N Bit M Data Output Write Mask
sahilmgandhi	18:6a4db94011d3	15471	* \| \| \|These bits are used to protect the corresponding register of Px_DOUT[m].
sahilmgandhi	18:6a4db94011d3	15472	* \| \| \|When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
sahilmgandhi	18:6a4db94011d3	15473	* \| \| \|The write to port pin latch is masked.
sahilmgandhi	18:6a4db94011d3	15474	* \| \| \|0 = Px_DOUT[m] bit writing is valid.
sahilmgandhi	18:6a4db94011d3	15475	* \| \| \|1 = Px_DOUT[m] bit writing is ignored.
sahilmgandhi	18:6a4db94011d3	15476	* \|[12] \|DATMSK12 \|Port N Bit M Data Output Write Mask
sahilmgandhi	18:6a4db94011d3	15477	* \| \| \|These bits are used to protect the corresponding register of Px_DOUT[m].
sahilmgandhi	18:6a4db94011d3	15478	* \| \| \|When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
sahilmgandhi	18:6a4db94011d3	15479	* \| \| \|The write to port pin latch is masked.
sahilmgandhi	18:6a4db94011d3	15480	* \| \| \|0 = Px_DOUT[m] bit writing is valid.
sahilmgandhi	18:6a4db94011d3	15481	* \| \| \|1 = Px_DOUT[m] bit writing is ignored.
sahilmgandhi	18:6a4db94011d3	15482	* \|[13] \|DATMSK13 \|Port N Bit M Data Output Write Mask
sahilmgandhi	18:6a4db94011d3	15483	* \| \| \|These bits are used to protect the corresponding register of Px_DOUT[m].
sahilmgandhi	18:6a4db94011d3	15484	* \| \| \|When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
sahilmgandhi	18:6a4db94011d3	15485	* \| \| \|The write to port pin latch is masked.
sahilmgandhi	18:6a4db94011d3	15486	* \| \| \|0 = Px_DOUT[m] bit writing is valid.
sahilmgandhi	18:6a4db94011d3	15487	* \| \| \|1 = Px_DOUT[m] bit writing is ignored.
sahilmgandhi	18:6a4db94011d3	15488	* \|[14] \|DATMSK14 \|Port N Bit M Data Output Write Mask
sahilmgandhi	18:6a4db94011d3	15489	* \| \| \|These bits are used to protect the corresponding register of Px_DOUT[m].
sahilmgandhi	18:6a4db94011d3	15490	* \| \| \|When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
sahilmgandhi	18:6a4db94011d3	15491	* \| \| \|The write to port pin latch is masked.
sahilmgandhi	18:6a4db94011d3	15492	* \| \| \|0 = Px_DOUT[m] bit writing is valid.
sahilmgandhi	18:6a4db94011d3	15493	* \| \| \|1 = Px_DOUT[m] bit writing is ignored.
sahilmgandhi	18:6a4db94011d3	15494	* \|[15] \|DATMSK15 \|Port N Bit M Data Output Write Mask
sahilmgandhi	18:6a4db94011d3	15495	* \| \| \|These bits are used to protect the corresponding register of Px_DOUT[m].
sahilmgandhi	18:6a4db94011d3	15496	* \| \| \|When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
sahilmgandhi	18:6a4db94011d3	15497	* \| \| \|The write to port pin latch is masked.
sahilmgandhi	18:6a4db94011d3	15498	* \| \| \|0 = Px_DOUT[m] bit writing is valid.
sahilmgandhi	18:6a4db94011d3	15499	* \| \| \|1 = Px_DOUT[m] bit writing is ignored.
sahilmgandhi	18:6a4db94011d3	15500	*/
sahilmgandhi	18:6a4db94011d3	15501	__IO uint32_t DATMSK;
sahilmgandhi	18:6a4db94011d3	15502
sahilmgandhi	18:6a4db94011d3	15503	/**
sahilmgandhi	18:6a4db94011d3	15504	* Px_PIN
sahilmgandhi	18:6a4db94011d3	15505	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	15506	* Offset: 0x10 Px Pin Value
sahilmgandhi	18:6a4db94011d3	15507	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	15508	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	15509	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	15510	* \|[0] \|PIN0 \|Port N Bit M Pin Value
sahilmgandhi	18:6a4db94011d3	15511	* \| \| \|Each bit of the register reflects the actual status of the respective port pin.
sahilmgandhi	18:6a4db94011d3	15512	* \| \| \|If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
sahilmgandhi	18:6a4db94011d3	15513	* \|[1] \|PIN1 \|Port N Bit M Pin Value
sahilmgandhi	18:6a4db94011d3	15514	* \| \| \|Each bit of the register reflects the actual status of the respective port pin.
sahilmgandhi	18:6a4db94011d3	15515	* \| \| \|If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
sahilmgandhi	18:6a4db94011d3	15516	* \|[2] \|PIN2 \|Port N Bit M Pin Value
sahilmgandhi	18:6a4db94011d3	15517	* \| \| \|Each bit of the register reflects the actual status of the respective port pin.
sahilmgandhi	18:6a4db94011d3	15518	* \| \| \|If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
sahilmgandhi	18:6a4db94011d3	15519	* \|[3] \|PIN3 \|Port N Bit M Pin Value
sahilmgandhi	18:6a4db94011d3	15520	* \| \| \|Each bit of the register reflects the actual status of the respective port pin.
sahilmgandhi	18:6a4db94011d3	15521	* \| \| \|If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
sahilmgandhi	18:6a4db94011d3	15522	* \|[4] \|PIN4 \|Port N Bit M Pin Value
sahilmgandhi	18:6a4db94011d3	15523	* \| \| \|Each bit of the register reflects the actual status of the respective port pin.
sahilmgandhi	18:6a4db94011d3	15524	* \| \| \|If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
sahilmgandhi	18:6a4db94011d3	15525	* \|[5] \|PIN5 \|Port N Bit M Pin Value
sahilmgandhi	18:6a4db94011d3	15526	* \| \| \|Each bit of the register reflects the actual status of the respective port pin.
sahilmgandhi	18:6a4db94011d3	15527	* \| \| \|If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
sahilmgandhi	18:6a4db94011d3	15528	* \|[6] \|PIN6 \|Port N Bit M Pin Value
sahilmgandhi	18:6a4db94011d3	15529	* \| \| \|Each bit of the register reflects the actual status of the respective port pin.
sahilmgandhi	18:6a4db94011d3	15530	* \| \| \|If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
sahilmgandhi	18:6a4db94011d3	15531	* \|[7] \|PIN7 \|Port N Bit M Pin Value
sahilmgandhi	18:6a4db94011d3	15532	* \| \| \|Each bit of the register reflects the actual status of the respective port pin.
sahilmgandhi	18:6a4db94011d3	15533	* \| \| \|If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
sahilmgandhi	18:6a4db94011d3	15534	* \|[8] \|PIN8 \|Port N Bit M Pin Value
sahilmgandhi	18:6a4db94011d3	15535	* \| \| \|Each bit of the register reflects the actual status of the respective port pin.
sahilmgandhi	18:6a4db94011d3	15536	* \| \| \|If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
sahilmgandhi	18:6a4db94011d3	15537	* \|[9] \|PIN9 \|Port N Bit M Pin Value
sahilmgandhi	18:6a4db94011d3	15538	* \| \| \|Each bit of the register reflects the actual status of the respective port pin.
sahilmgandhi	18:6a4db94011d3	15539	* \| \| \|If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
sahilmgandhi	18:6a4db94011d3	15540	* \|[10] \|PIN10 \|Port N Bit M Pin Value
sahilmgandhi	18:6a4db94011d3	15541	* \| \| \|Each bit of the register reflects the actual status of the respective port pin.
sahilmgandhi	18:6a4db94011d3	15542	* \| \| \|If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
sahilmgandhi	18:6a4db94011d3	15543	* \|[11] \|PIN11 \|Port N Bit M Pin Value
sahilmgandhi	18:6a4db94011d3	15544	* \| \| \|Each bit of the register reflects the actual status of the respective port pin.
sahilmgandhi	18:6a4db94011d3	15545	* \| \| \|If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
sahilmgandhi	18:6a4db94011d3	15546	* \|[12] \|PIN12 \|Port N Bit M Pin Value
sahilmgandhi	18:6a4db94011d3	15547	* \| \| \|Each bit of the register reflects the actual status of the respective port pin.
sahilmgandhi	18:6a4db94011d3	15548	* \| \| \|If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
sahilmgandhi	18:6a4db94011d3	15549	* \|[13] \|PIN13 \|Port N Bit M Pin Value
sahilmgandhi	18:6a4db94011d3	15550	* \| \| \|Each bit of the register reflects the actual status of the respective port pin.
sahilmgandhi	18:6a4db94011d3	15551	* \| \| \|If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
sahilmgandhi	18:6a4db94011d3	15552	* \|[14] \|PIN14 \|Port N Bit M Pin Value
sahilmgandhi	18:6a4db94011d3	15553	* \| \| \|Each bit of the register reflects the actual status of the respective port pin.
sahilmgandhi	18:6a4db94011d3	15554	* \| \| \|If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
sahilmgandhi	18:6a4db94011d3	15555	* \|[15] \|PIN15 \|Port N Bit M Pin Value
sahilmgandhi	18:6a4db94011d3	15556	* \| \| \|Each bit of the register reflects the actual status of the respective port pin.
sahilmgandhi	18:6a4db94011d3	15557	* \| \| \|If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
sahilmgandhi	18:6a4db94011d3	15558	*/
sahilmgandhi	18:6a4db94011d3	15559	__I uint32_t PIN;
sahilmgandhi	18:6a4db94011d3	15560
sahilmgandhi	18:6a4db94011d3	15561	/**
sahilmgandhi	18:6a4db94011d3	15562	* Px_DBEN
sahilmgandhi	18:6a4db94011d3	15563	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	15564	* Offset: 0x14 Px De-Bounce Enable Control
sahilmgandhi	18:6a4db94011d3	15565	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	15566	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	15567	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	15568	* \|[0] \|DBEN0 \|Port N Bit M Input De-Bounce Enable
sahilmgandhi	18:6a4db94011d3	15569	* \| \| \|DBEN[m] is used to enable the de-bounce function for each corresponding bit.
sahilmgandhi	18:6a4db94011d3	15570	* \| \| \|DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
sahilmgandhi	18:6a4db94011d3	15571	* \| \| \|If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
sahilmgandhi	18:6a4db94011d3	15572	* \| \| \|The de-bounce clock is controlled by GPIO_DBCTL register.
sahilmgandhi	18:6a4db94011d3	15573	* \| \| \|0 = Port n bit m input de-bounce Disabled.
sahilmgandhi	18:6a4db94011d3	15574	* \| \| \|1 = Port n bit m input de-bounce Enabled.
sahilmgandhi	18:6a4db94011d3	15575	* \|[1] \|DBEN1 \|Port N Bit M Input De-Bounce Enable
sahilmgandhi	18:6a4db94011d3	15576	* \| \| \|DBEN[m] is used to enable the de-bounce function for each corresponding bit.
sahilmgandhi	18:6a4db94011d3	15577	* \| \| \|DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
sahilmgandhi	18:6a4db94011d3	15578	* \| \| \|If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
sahilmgandhi	18:6a4db94011d3	15579	* \| \| \|The de-bounce clock is controlled by GPIO_DBCTL register.
sahilmgandhi	18:6a4db94011d3	15580	* \| \| \|0 = Port n bit m input de-bounce Disabled.
sahilmgandhi	18:6a4db94011d3	15581	* \| \| \|1 = Port n bit m input de-bounce Enabled.
sahilmgandhi	18:6a4db94011d3	15582	* \|[2] \|DBEN2 \|Port N Bit M Input De-Bounce Enable
sahilmgandhi	18:6a4db94011d3	15583	* \| \| \|DBEN[m] is used to enable the de-bounce function for each corresponding bit.
sahilmgandhi	18:6a4db94011d3	15584	* \| \| \|DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
sahilmgandhi	18:6a4db94011d3	15585	* \| \| \|If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
sahilmgandhi	18:6a4db94011d3	15586	* \| \| \|The de-bounce clock is controlled by GPIO_DBCTL register.
sahilmgandhi	18:6a4db94011d3	15587	* \| \| \|0 = Port n bit m input de-bounce Disabled.
sahilmgandhi	18:6a4db94011d3	15588	* \| \| \|1 = Port n bit m input de-bounce Enabled.
sahilmgandhi	18:6a4db94011d3	15589	* \|[3] \|DBEN3 \|Port N Bit M Input De-Bounce Enable
sahilmgandhi	18:6a4db94011d3	15590	* \| \| \|DBEN[m] is used to enable the de-bounce function for each corresponding bit.
sahilmgandhi	18:6a4db94011d3	15591	* \| \| \|DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
sahilmgandhi	18:6a4db94011d3	15592	* \| \| \|If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
sahilmgandhi	18:6a4db94011d3	15593	* \| \| \|The de-bounce clock is controlled by GPIO_DBCTL register.
sahilmgandhi	18:6a4db94011d3	15594	* \| \| \|0 = Port n bit m input de-bounce Disabled.
sahilmgandhi	18:6a4db94011d3	15595	* \| \| \|1 = Port n bit m input de-bounce Enabled.
sahilmgandhi	18:6a4db94011d3	15596	* \|[4] \|DBEN4 \|Port N Bit M Input De-Bounce Enable
sahilmgandhi	18:6a4db94011d3	15597	* \| \| \|DBEN[m] is used to enable the de-bounce function for each corresponding bit.
sahilmgandhi	18:6a4db94011d3	15598	* \| \| \|DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
sahilmgandhi	18:6a4db94011d3	15599	* \| \| \|If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
sahilmgandhi	18:6a4db94011d3	15600	* \| \| \|The de-bounce clock is controlled by GPIO_DBCTL register.
sahilmgandhi	18:6a4db94011d3	15601	* \| \| \|0 = Port n bit m input de-bounce Disabled.
sahilmgandhi	18:6a4db94011d3	15602	* \| \| \|1 = Port n bit m input de-bounce Enabled.
sahilmgandhi	18:6a4db94011d3	15603	* \|[5] \|DBEN5 \|Port N Bit M Input De-Bounce Enable
sahilmgandhi	18:6a4db94011d3	15604	* \| \| \|DBEN[m] is used to enable the de-bounce function for each corresponding bit.
sahilmgandhi	18:6a4db94011d3	15605	* \| \| \|DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
sahilmgandhi	18:6a4db94011d3	15606	* \| \| \|If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
sahilmgandhi	18:6a4db94011d3	15607	* \| \| \|The de-bounce clock is controlled by GPIO_DBCTL register.
sahilmgandhi	18:6a4db94011d3	15608	* \| \| \|0 = Port n bit m input de-bounce Disabled.
sahilmgandhi	18:6a4db94011d3	15609	* \| \| \|1 = Port n bit m input de-bounce Enabled.
sahilmgandhi	18:6a4db94011d3	15610	* \|[6] \|DBEN6 \|Port N Bit M Input De-Bounce Enable
sahilmgandhi	18:6a4db94011d3	15611	* \| \| \|DBEN[m] is used to enable the de-bounce function for each corresponding bit.
sahilmgandhi	18:6a4db94011d3	15612	* \| \| \|DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
sahilmgandhi	18:6a4db94011d3	15613	* \| \| \|If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
sahilmgandhi	18:6a4db94011d3	15614	* \| \| \|The de-bounce clock is controlled by GPIO_DBCTL register.
sahilmgandhi	18:6a4db94011d3	15615	* \| \| \|0 = Port n bit m input de-bounce Disabled.
sahilmgandhi	18:6a4db94011d3	15616	* \| \| \|1 = Port n bit m input de-bounce Enabled.
sahilmgandhi	18:6a4db94011d3	15617	* \|[7] \|DBEN7 \|Port N Bit M Input De-Bounce Enable
sahilmgandhi	18:6a4db94011d3	15618	* \| \| \|DBEN[m] is used to enable the de-bounce function for each corresponding bit.
sahilmgandhi	18:6a4db94011d3	15619	* \| \| \|DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
sahilmgandhi	18:6a4db94011d3	15620	* \| \| \|If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
sahilmgandhi	18:6a4db94011d3	15621	* \| \| \|The de-bounce clock is controlled by GPIO_DBCTL register.
sahilmgandhi	18:6a4db94011d3	15622	* \| \| \|0 = Port n bit m input de-bounce Disabled.
sahilmgandhi	18:6a4db94011d3	15623	* \| \| \|1 = Port n bit m input de-bounce Enabled.
sahilmgandhi	18:6a4db94011d3	15624	* \|[8] \|DBEN8 \|Port N Bit M Input De-Bounce Enable
sahilmgandhi	18:6a4db94011d3	15625	* \| \| \|DBEN[m] is used to enable the de-bounce function for each corresponding bit.
sahilmgandhi	18:6a4db94011d3	15626	* \| \| \|DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
sahilmgandhi	18:6a4db94011d3	15627	* \| \| \|If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
sahilmgandhi	18:6a4db94011d3	15628	* \| \| \|The de-bounce clock is controlled by GPIO_DBCTL register.
sahilmgandhi	18:6a4db94011d3	15629	* \| \| \|0 = Port n bit m input de-bounce Disabled.
sahilmgandhi	18:6a4db94011d3	15630	* \| \| \|1 = Port n bit m input de-bounce Enabled.
sahilmgandhi	18:6a4db94011d3	15631	* \|[9] \|DBEN9 \|Port N Bit M Input De-Bounce Enable
sahilmgandhi	18:6a4db94011d3	15632	* \| \| \|DBEN[m] is used to enable the de-bounce function for each corresponding bit.
sahilmgandhi	18:6a4db94011d3	15633	* \| \| \|DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
sahilmgandhi	18:6a4db94011d3	15634	* \| \| \|If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
sahilmgandhi	18:6a4db94011d3	15635	* \| \| \|The de-bounce clock is controlled by GPIO_DBCTL register.
sahilmgandhi	18:6a4db94011d3	15636	* \| \| \|0 = Port n bit m input de-bounce Disabled.
sahilmgandhi	18:6a4db94011d3	15637	* \| \| \|1 = Port n bit m input de-bounce Enabled.
sahilmgandhi	18:6a4db94011d3	15638	* \|[10] \|DBEN10 \|Port N Bit M Input De-Bounce Enable
sahilmgandhi	18:6a4db94011d3	15639	* \| \| \|DBEN[m] is used to enable the de-bounce function for each corresponding bit.
sahilmgandhi	18:6a4db94011d3	15640	* \| \| \|DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
sahilmgandhi	18:6a4db94011d3	15641	* \| \| \|If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
sahilmgandhi	18:6a4db94011d3	15642	* \| \| \|The de-bounce clock is controlled by GPIO_DBCTL register.
sahilmgandhi	18:6a4db94011d3	15643	* \| \| \|0 = Port n bit m input de-bounce Disabled.
sahilmgandhi	18:6a4db94011d3	15644	* \| \| \|1 = Port n bit m input de-bounce Enabled.
sahilmgandhi	18:6a4db94011d3	15645	* \|[11] \|DBEN11 \|Port N Bit M Input De-Bounce Enable
sahilmgandhi	18:6a4db94011d3	15646	* \| \| \|DBEN[m] is used to enable the de-bounce function for each corresponding bit.
sahilmgandhi	18:6a4db94011d3	15647	* \| \| \|DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
sahilmgandhi	18:6a4db94011d3	15648	* \| \| \|If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
sahilmgandhi	18:6a4db94011d3	15649	* \| \| \|The de-bounce clock is controlled by GPIO_DBCTL register.
sahilmgandhi	18:6a4db94011d3	15650	* \| \| \|0 = Port n bit m input de-bounce Disabled.
sahilmgandhi	18:6a4db94011d3	15651	* \| \| \|1 = Port n bit m input de-bounce Enabled.
sahilmgandhi	18:6a4db94011d3	15652	* \|[12] \|DBEN12 \|Port N Bit M Input De-Bounce Enable
sahilmgandhi	18:6a4db94011d3	15653	* \| \| \|DBEN[m] is used to enable the de-bounce function for each corresponding bit.
sahilmgandhi	18:6a4db94011d3	15654	* \| \| \|DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
sahilmgandhi	18:6a4db94011d3	15655	* \| \| \|If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
sahilmgandhi	18:6a4db94011d3	15656	* \| \| \|The de-bounce clock is controlled by GPIO_DBCTL register.
sahilmgandhi	18:6a4db94011d3	15657	* \| \| \|0 = Port n bit m input de-bounce Disabled.
sahilmgandhi	18:6a4db94011d3	15658	* \| \| \|1 = Port n bit m input de-bounce Enabled.
sahilmgandhi	18:6a4db94011d3	15659	* \|[13] \|DBEN13 \|Port N Bit M Input De-Bounce Enable
sahilmgandhi	18:6a4db94011d3	15660	* \| \| \|DBEN[m] is used to enable the de-bounce function for each corresponding bit.
sahilmgandhi	18:6a4db94011d3	15661	* \| \| \|DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
sahilmgandhi	18:6a4db94011d3	15662	* \| \| \|If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
sahilmgandhi	18:6a4db94011d3	15663	* \| \| \|The de-bounce clock is controlled by GPIO_DBCTL register.
sahilmgandhi	18:6a4db94011d3	15664	* \| \| \|0 = Port n bit m input de-bounce Disabled.
sahilmgandhi	18:6a4db94011d3	15665	* \| \| \|1 = Port n bit m input de-bounce Enabled.
sahilmgandhi	18:6a4db94011d3	15666	* \|[14] \|DBEN14 \|Port N Bit M Input De-Bounce Enable
sahilmgandhi	18:6a4db94011d3	15667	* \| \| \|DBEN[m] is used to enable the de-bounce function for each corresponding bit.
sahilmgandhi	18:6a4db94011d3	15668	* \| \| \|DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
sahilmgandhi	18:6a4db94011d3	15669	* \| \| \|If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
sahilmgandhi	18:6a4db94011d3	15670	* \| \| \|The de-bounce clock is controlled by GPIO_DBCTL register.
sahilmgandhi	18:6a4db94011d3	15671	* \| \| \|0 = Port n bit m input de-bounce Disabled.
sahilmgandhi	18:6a4db94011d3	15672	* \| \| \|1 = Port n bit m input de-bounce Enabled.
sahilmgandhi	18:6a4db94011d3	15673	* \|[15] \|DBEN15 \|Port N Bit M Input De-Bounce Enable
sahilmgandhi	18:6a4db94011d3	15674	* \| \| \|DBEN[m] is used to enable the de-bounce function for each corresponding bit.
sahilmgandhi	18:6a4db94011d3	15675	* \| \| \|DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
sahilmgandhi	18:6a4db94011d3	15676	* \| \| \|If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
sahilmgandhi	18:6a4db94011d3	15677	* \| \| \|The de-bounce clock is controlled by GPIO_DBCTL register.
sahilmgandhi	18:6a4db94011d3	15678	* \| \| \|0 = Port n bit m input de-bounce Disabled.
sahilmgandhi	18:6a4db94011d3	15679	* \| \| \|1 = Port n bit m input de-bounce Enabled.
sahilmgandhi	18:6a4db94011d3	15680	*/
sahilmgandhi	18:6a4db94011d3	15681	__IO uint32_t DBEN;
sahilmgandhi	18:6a4db94011d3	15682
sahilmgandhi	18:6a4db94011d3	15683	/**
sahilmgandhi	18:6a4db94011d3	15684	* Px_INTTYPE
sahilmgandhi	18:6a4db94011d3	15685	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	15686	* Offset: 0x18 Px Interrupt Trigger Type Register
sahilmgandhi	18:6a4db94011d3	15687	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	15688	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	15689	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	15690	* \|[0] \|TYPE0 \|Port N Bit M Edge Or Level Triggered Interrupt Control
sahilmgandhi	18:6a4db94011d3	15691	* \| \| \|TYPE[m] decides the pin interrupt triggered by level or edge.
sahilmgandhi	18:6a4db94011d3	15692	* \| \| \|If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
sahilmgandhi	18:6a4db94011d3	15693	* \| \| \|If the interrupt is by level trigger, the input source is sampled by one HCLK.
sahilmgandhi	18:6a4db94011d3	15694	* \| \| \|clock and generates the interrupt.
sahilmgandhi	18:6a4db94011d3	15695	* \| \| \|0 = Edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15696	* \| \| \|1 = Level triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15697	* \| \| \|Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
sahilmgandhi	18:6a4db94011d3	15698	* \| \| \|If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
sahilmgandhi	18:6a4db94011d3	15699	* \| \| \|Note2: The de-bounce function is valid for edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15700	* \| \| \|If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
sahilmgandhi	18:6a4db94011d3	15701	* \|[1] \|TYPE1 \|Port N Bit M Edge Or Level Triggered Interrupt Control
sahilmgandhi	18:6a4db94011d3	15702	* \| \| \|TYPE[m] decides the pin interrupt triggered by level or edge.
sahilmgandhi	18:6a4db94011d3	15703	* \| \| \|If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
sahilmgandhi	18:6a4db94011d3	15704	* \| \| \|If the interrupt is by level trigger, the input source is sampled by one HCLK.
sahilmgandhi	18:6a4db94011d3	15705	* \| \| \|clock and generates the interrupt.
sahilmgandhi	18:6a4db94011d3	15706	* \| \| \|0 = Edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15707	* \| \| \|1 = Level triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15708	* \| \| \|Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
sahilmgandhi	18:6a4db94011d3	15709	* \| \| \|If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
sahilmgandhi	18:6a4db94011d3	15710	* \| \| \|Note2: The de-bounce function is valid for edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15711	* \| \| \|If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
sahilmgandhi	18:6a4db94011d3	15712	* \|[2] \|TYPE2 \|Port N Bit M Edge Or Level Triggered Interrupt Control
sahilmgandhi	18:6a4db94011d3	15713	* \| \| \|TYPE[m] decides the pin interrupt triggered by level or edge.
sahilmgandhi	18:6a4db94011d3	15714	* \| \| \|If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
sahilmgandhi	18:6a4db94011d3	15715	* \| \| \|If the interrupt is by level trigger, the input source is sampled by one HCLK.
sahilmgandhi	18:6a4db94011d3	15716	* \| \| \|clock and generates the interrupt.
sahilmgandhi	18:6a4db94011d3	15717	* \| \| \|0 = Edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15718	* \| \| \|1 = Level triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15719	* \| \| \|Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
sahilmgandhi	18:6a4db94011d3	15720	* \| \| \|If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
sahilmgandhi	18:6a4db94011d3	15721	* \| \| \|Note2: The de-bounce function is valid for edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15722	* \| \| \|If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
sahilmgandhi	18:6a4db94011d3	15723	* \|[3] \|TYPE3 \|Port N Bit M Edge Or Level Triggered Interrupt Control
sahilmgandhi	18:6a4db94011d3	15724	* \| \| \|TYPE[m] decides the pin interrupt triggered by level or edge.
sahilmgandhi	18:6a4db94011d3	15725	* \| \| \|If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
sahilmgandhi	18:6a4db94011d3	15726	* \| \| \|If the interrupt is by level trigger, the input source is sampled by one HCLK.
sahilmgandhi	18:6a4db94011d3	15727	* \| \| \|clock and generates the interrupt.
sahilmgandhi	18:6a4db94011d3	15728	* \| \| \|0 = Edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15729	* \| \| \|1 = Level triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15730	* \| \| \|Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
sahilmgandhi	18:6a4db94011d3	15731	* \| \| \|If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
sahilmgandhi	18:6a4db94011d3	15732	* \| \| \|Note2: The de-bounce function is valid for edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15733	* \| \| \|If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
sahilmgandhi	18:6a4db94011d3	15734	* \|[4] \|TYPE4 \|Port N Bit M Edge Or Level Triggered Interrupt Control
sahilmgandhi	18:6a4db94011d3	15735	* \| \| \|TYPE[m] decides the pin interrupt triggered by level or edge.
sahilmgandhi	18:6a4db94011d3	15736	* \| \| \|If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
sahilmgandhi	18:6a4db94011d3	15737	* \| \| \|If the interrupt is by level trigger, the input source is sampled by one HCLK.
sahilmgandhi	18:6a4db94011d3	15738	* \| \| \|clock and generates the interrupt.
sahilmgandhi	18:6a4db94011d3	15739	* \| \| \|0 = Edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15740	* \| \| \|1 = Level triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15741	* \| \| \|Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
sahilmgandhi	18:6a4db94011d3	15742	* \| \| \|If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
sahilmgandhi	18:6a4db94011d3	15743	* \| \| \|Note2: The de-bounce function is valid for edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15744	* \| \| \|If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
sahilmgandhi	18:6a4db94011d3	15745	* \|[5] \|TYPE5 \|Port N Bit M Edge Or Level Triggered Interrupt Control
sahilmgandhi	18:6a4db94011d3	15746	* \| \| \|TYPE[m] decides the pin interrupt triggered by level or edge.
sahilmgandhi	18:6a4db94011d3	15747	* \| \| \|If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
sahilmgandhi	18:6a4db94011d3	15748	* \| \| \|If the interrupt is by level trigger, the input source is sampled by one HCLK.
sahilmgandhi	18:6a4db94011d3	15749	* \| \| \|clock and generates the interrupt.
sahilmgandhi	18:6a4db94011d3	15750	* \| \| \|0 = Edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15751	* \| \| \|1 = Level triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15752	* \| \| \|Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
sahilmgandhi	18:6a4db94011d3	15753	* \| \| \|If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
sahilmgandhi	18:6a4db94011d3	15754	* \| \| \|Note2: The de-bounce function is valid for edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15755	* \| \| \|If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
sahilmgandhi	18:6a4db94011d3	15756	* \|[6] \|TYPE6 \|Port N Bit M Edge Or Level Triggered Interrupt Control
sahilmgandhi	18:6a4db94011d3	15757	* \| \| \|TYPE[m] decides the pin interrupt triggered by level or edge.
sahilmgandhi	18:6a4db94011d3	15758	* \| \| \|If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
sahilmgandhi	18:6a4db94011d3	15759	* \| \| \|If the interrupt is by level trigger, the input source is sampled by one HCLK.
sahilmgandhi	18:6a4db94011d3	15760	* \| \| \|clock and generates the interrupt.
sahilmgandhi	18:6a4db94011d3	15761	* \| \| \|0 = Edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15762	* \| \| \|1 = Level triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15763	* \| \| \|Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
sahilmgandhi	18:6a4db94011d3	15764	* \| \| \|If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
sahilmgandhi	18:6a4db94011d3	15765	* \| \| \|Note2: The de-bounce function is valid for edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15766	* \| \| \|If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
sahilmgandhi	18:6a4db94011d3	15767	* \|[7] \|TYPE7 \|Port N Bit M Edge Or Level Triggered Interrupt Control
sahilmgandhi	18:6a4db94011d3	15768	* \| \| \|TYPE[m] decides the pin interrupt triggered by level or edge.
sahilmgandhi	18:6a4db94011d3	15769	* \| \| \|If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
sahilmgandhi	18:6a4db94011d3	15770	* \| \| \|If the interrupt is by level trigger, the input source is sampled by one HCLK.
sahilmgandhi	18:6a4db94011d3	15771	* \| \| \|clock and generates the interrupt.
sahilmgandhi	18:6a4db94011d3	15772	* \| \| \|0 = Edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15773	* \| \| \|1 = Level triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15774	* \| \| \|Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
sahilmgandhi	18:6a4db94011d3	15775	* \| \| \|If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
sahilmgandhi	18:6a4db94011d3	15776	* \| \| \|Note2: The de-bounce function is valid for edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15777	* \| \| \|If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
sahilmgandhi	18:6a4db94011d3	15778	* \|[8] \|TYPE8 \|Port N Bit M Edge Or Level Triggered Interrupt Control
sahilmgandhi	18:6a4db94011d3	15779	* \| \| \|TYPE[m] decides the pin interrupt triggered by level or edge.
sahilmgandhi	18:6a4db94011d3	15780	* \| \| \|If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
sahilmgandhi	18:6a4db94011d3	15781	* \| \| \|If the interrupt is by level trigger, the input source is sampled by one HCLK.
sahilmgandhi	18:6a4db94011d3	15782	* \| \| \|clock and generates the interrupt.
sahilmgandhi	18:6a4db94011d3	15783	* \| \| \|0 = Edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15784	* \| \| \|1 = Level triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15785	* \| \| \|Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
sahilmgandhi	18:6a4db94011d3	15786	* \| \| \|If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
sahilmgandhi	18:6a4db94011d3	15787	* \| \| \|Note2: The de-bounce function is valid for edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15788	* \| \| \|If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
sahilmgandhi	18:6a4db94011d3	15789	* \|[9] \|TYPE9 \|Port N Bit M Edge Or Level Triggered Interrupt Control
sahilmgandhi	18:6a4db94011d3	15790	* \| \| \|TYPE[m] decides the pin interrupt triggered by level or edge.
sahilmgandhi	18:6a4db94011d3	15791	* \| \| \|If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
sahilmgandhi	18:6a4db94011d3	15792	* \| \| \|If the interrupt is by level trigger, the input source is sampled by one HCLK.
sahilmgandhi	18:6a4db94011d3	15793	* \| \| \|clock and generates the interrupt.
sahilmgandhi	18:6a4db94011d3	15794	* \| \| \|0 = Edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15795	* \| \| \|1 = Level triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15796	* \| \| \|Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
sahilmgandhi	18:6a4db94011d3	15797	* \| \| \|If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
sahilmgandhi	18:6a4db94011d3	15798	* \| \| \|Note2: The de-bounce function is valid for edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15799	* \| \| \|If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
sahilmgandhi	18:6a4db94011d3	15800	* \|[10] \|TYPE10 \|Port N Bit M Edge Or Level Triggered Interrupt Control
sahilmgandhi	18:6a4db94011d3	15801	* \| \| \|TYPE[m] decides the pin interrupt triggered by level or edge.
sahilmgandhi	18:6a4db94011d3	15802	* \| \| \|If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
sahilmgandhi	18:6a4db94011d3	15803	* \| \| \|If the interrupt is by level trigger, the input source is sampled by one HCLK.
sahilmgandhi	18:6a4db94011d3	15804	* \| \| \|clock and generates the interrupt.
sahilmgandhi	18:6a4db94011d3	15805	* \| \| \|0 = Edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15806	* \| \| \|1 = Level triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15807	* \| \| \|Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
sahilmgandhi	18:6a4db94011d3	15808	* \| \| \|If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
sahilmgandhi	18:6a4db94011d3	15809	* \| \| \|Note2: The de-bounce function is valid for edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15810	* \| \| \|If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
sahilmgandhi	18:6a4db94011d3	15811	* \|[11] \|TYPE11 \|Port N Bit M Edge Or Level Triggered Interrupt Control
sahilmgandhi	18:6a4db94011d3	15812	* \| \| \|TYPE[m] decides the pin interrupt triggered by level or edge.
sahilmgandhi	18:6a4db94011d3	15813	* \| \| \|If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
sahilmgandhi	18:6a4db94011d3	15814	* \| \| \|If the interrupt is by level trigger, the input source is sampled by one HCLK.
sahilmgandhi	18:6a4db94011d3	15815	* \| \| \|clock and generates the interrupt.
sahilmgandhi	18:6a4db94011d3	15816	* \| \| \|0 = Edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15817	* \| \| \|1 = Level triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15818	* \| \| \|Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
sahilmgandhi	18:6a4db94011d3	15819	* \| \| \|If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
sahilmgandhi	18:6a4db94011d3	15820	* \| \| \|Note2: The de-bounce function is valid for edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15821	* \| \| \|If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
sahilmgandhi	18:6a4db94011d3	15822	* \|[12] \|TYPE12 \|Port N Bit M Edge Or Level Triggered Interrupt Control
sahilmgandhi	18:6a4db94011d3	15823	* \| \| \|TYPE[m] decides the pin interrupt triggered by level or edge.
sahilmgandhi	18:6a4db94011d3	15824	* \| \| \|If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
sahilmgandhi	18:6a4db94011d3	15825	* \| \| \|If the interrupt is by level trigger, the input source is sampled by one HCLK.
sahilmgandhi	18:6a4db94011d3	15826	* \| \| \|clock and generates the interrupt.
sahilmgandhi	18:6a4db94011d3	15827	* \| \| \|0 = Edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15828	* \| \| \|1 = Level triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15829	* \| \| \|Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
sahilmgandhi	18:6a4db94011d3	15830	* \| \| \|If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
sahilmgandhi	18:6a4db94011d3	15831	* \| \| \|Note2: The de-bounce function is valid for edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15832	* \| \| \|If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
sahilmgandhi	18:6a4db94011d3	15833	* \|[13] \|TYPE13 \|Port N Bit M Edge Or Level Triggered Interrupt Control
sahilmgandhi	18:6a4db94011d3	15834	* \| \| \|TYPE[m] decides the pin interrupt triggered by level or edge.
sahilmgandhi	18:6a4db94011d3	15835	* \| \| \|If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
sahilmgandhi	18:6a4db94011d3	15836	* \| \| \|If the interrupt is by level trigger, the input source is sampled by one HCLK.
sahilmgandhi	18:6a4db94011d3	15837	* \| \| \|clock and generates the interrupt.
sahilmgandhi	18:6a4db94011d3	15838	* \| \| \|0 = Edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15839	* \| \| \|1 = Level triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15840	* \| \| \|Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
sahilmgandhi	18:6a4db94011d3	15841	* \| \| \|If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
sahilmgandhi	18:6a4db94011d3	15842	* \| \| \|Note2: The de-bounce function is valid for edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15843	* \| \| \|If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
sahilmgandhi	18:6a4db94011d3	15844	* \|[14] \|TYPE14 \|Port N Bit M Edge Or Level Triggered Interrupt Control
sahilmgandhi	18:6a4db94011d3	15845	* \| \| \|TYPE[m] decides the pin interrupt triggered by level or edge.
sahilmgandhi	18:6a4db94011d3	15846	* \| \| \|If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
sahilmgandhi	18:6a4db94011d3	15847	* \| \| \|If the interrupt is by level trigger, the input source is sampled by one HCLK.
sahilmgandhi	18:6a4db94011d3	15848	* \| \| \|clock and generates the interrupt.
sahilmgandhi	18:6a4db94011d3	15849	* \| \| \|0 = Edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15850	* \| \| \|1 = Level triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15851	* \| \| \|Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
sahilmgandhi	18:6a4db94011d3	15852	* \| \| \|If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
sahilmgandhi	18:6a4db94011d3	15853	* \| \| \|Note2: The de-bounce function is valid for edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15854	* \| \| \|If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
sahilmgandhi	18:6a4db94011d3	15855	* \|[15] \|TYPE15 \|Port N Bit M Edge Or Level Triggered Interrupt Control
sahilmgandhi	18:6a4db94011d3	15856	* \| \| \|TYPE[m] decides the pin interrupt triggered by level or edge.
sahilmgandhi	18:6a4db94011d3	15857	* \| \| \|If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
sahilmgandhi	18:6a4db94011d3	15858	* \| \| \|If the interrupt is by level trigger, the input source is sampled by one HCLK.
sahilmgandhi	18:6a4db94011d3	15859	* \| \| \|clock and generates the interrupt.
sahilmgandhi	18:6a4db94011d3	15860	* \| \| \|0 = Edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15861	* \| \| \|1 = Level triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15862	* \| \| \|Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
sahilmgandhi	18:6a4db94011d3	15863	* \| \| \|If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
sahilmgandhi	18:6a4db94011d3	15864	* \| \| \|Note2: The de-bounce function is valid for edge triggered interrupt.
sahilmgandhi	18:6a4db94011d3	15865	* \| \| \|If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
sahilmgandhi	18:6a4db94011d3	15866	*/
sahilmgandhi	18:6a4db94011d3	15867	__IO uint32_t INTTYPE;
sahilmgandhi	18:6a4db94011d3	15868
sahilmgandhi	18:6a4db94011d3	15869	/**
sahilmgandhi	18:6a4db94011d3	15870	* Px_INTEN
sahilmgandhi	18:6a4db94011d3	15871	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	15872	* Offset: 0x1C Px Interrupt Enable
sahilmgandhi	18:6a4db94011d3	15873	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	15874	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	15875	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	15876	* \|[0] \|FLIEN0 \|Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
sahilmgandhi	18:6a4db94011d3	15877	* \| \| \|FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	15878	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	15879	* \| \| \|0 = Port n bit m low-level or falling edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	15880	* \| \| \|1 = Port n bit m low-level or falling edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	15881	* \|[1] \|FLIEN1 \|Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
sahilmgandhi	18:6a4db94011d3	15882	* \| \| \|FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	15883	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	15884	* \| \| \|0 = Port n bit m low-level or falling edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	15885	* \| \| \|1 = Port n bit m low-level or falling edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	15886	* \|[2] \|FLIEN2 \|Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
sahilmgandhi	18:6a4db94011d3	15887	* \| \| \|FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	15888	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	15889	* \| \| \|0 = Port n bit m low-level or falling edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	15890	* \| \| \|1 = Port n bit m low-level or falling edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	15891	* \|[3] \|FLIEN3 \|Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
sahilmgandhi	18:6a4db94011d3	15892	* \| \| \|FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	15893	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	15894	* \| \| \|0 = Port n bit m low-level or falling edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	15895	* \| \| \|1 = Port n bit m low-level or falling edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	15896	* \|[4] \|FLIEN4 \|Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
sahilmgandhi	18:6a4db94011d3	15897	* \| \| \|FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	15898	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	15899	* \| \| \|0 = Port n bit m low-level or falling edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	15900	* \| \| \|1 = Port n bit m low-level or falling edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	15901	* \|[5] \|FLIEN5 \|Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
sahilmgandhi	18:6a4db94011d3	15902	* \| \| \|FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	15903	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	15904	* \| \| \|0 = Port n bit m low-level or falling edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	15905	* \| \| \|1 = Port n bit m low-level or falling edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	15906	* \|[6] \|FLIEN6 \|Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
sahilmgandhi	18:6a4db94011d3	15907	* \| \| \|FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	15908	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	15909	* \| \| \|0 = Port n bit m low-level or falling edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	15910	* \| \| \|1 = Port n bit m low-level or falling edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	15911	* \|[7] \|FLIEN7 \|Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
sahilmgandhi	18:6a4db94011d3	15912	* \| \| \|FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	15913	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	15914	* \| \| \|0 = Port n bit m low-level or falling edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	15915	* \| \| \|1 = Port n bit m low-level or falling edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	15916	* \|[8] \|FLIEN8 \|Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
sahilmgandhi	18:6a4db94011d3	15917	* \| \| \|FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	15918	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	15919	* \| \| \|0 = Port n bit m low-level or falling edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	15920	* \| \| \|1 = Port n bit m low-level or falling edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	15921	* \|[9] \|FLIEN9 \|Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
sahilmgandhi	18:6a4db94011d3	15922	* \| \| \|FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	15923	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	15924	* \| \| \|0 = Port n bit m low-level or falling edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	15925	* \| \| \|1 = Port n bit m low-level or falling edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	15926	* \|[10] \|FLIEN10 \|Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
sahilmgandhi	18:6a4db94011d3	15927	* \| \| \|FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	15928	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	15929	* \| \| \|0 = Port n bit m low-level or falling edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	15930	* \| \| \|1 = Port n bit m low-level or falling edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	15931	* \|[11] \|FLIEN11 \|Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
sahilmgandhi	18:6a4db94011d3	15932	* \| \| \|FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	15933	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	15934	* \| \| \|0 = Port n bit m low-level or falling edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	15935	* \| \| \|1 = Port n bit m low-level or falling edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	15936	* \|[12] \|FLIEN12 \|Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
sahilmgandhi	18:6a4db94011d3	15937	* \| \| \|FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	15938	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	15939	* \| \| \|0 = Port n bit m low-level or falling edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	15940	* \| \| \|1 = Port n bit m low-level or falling edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	15941	* \|[13] \|FLIEN13 \|Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
sahilmgandhi	18:6a4db94011d3	15942	* \| \| \|FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	15943	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	15944	* \| \| \|0 = Port n bit m low-level or falling edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	15945	* \| \| \|1 = Port n bit m low-level or falling edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	15946	* \|[14] \|FLIEN14 \|Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
sahilmgandhi	18:6a4db94011d3	15947	* \| \| \|FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	15948	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	15949	* \| \| \|0 = Port n bit m low-level or falling edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	15950	* \| \| \|1 = Port n bit m low-level or falling edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	15951	* \|[15] \|FLIEN15 \|Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
sahilmgandhi	18:6a4db94011d3	15952	* \| \| \|FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	15953	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	15954	* \| \| \|0 = Port n bit m low-level or falling edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	15955	* \| \| \|1 = Port n bit m low-level or falling edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	15956	* \|[16] \|RHIEN0 \|Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
sahilmgandhi	18:6a4db94011d3	15957	* \| \| \|RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	15958	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	15959	* \| \| \|0 = Port n bit m high-level or rising edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	15960	* \| \| \|1 = Port n bit m high-level or rising edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	15961	* \|[17] \|RHIEN1 \|Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
sahilmgandhi	18:6a4db94011d3	15962	* \| \| \|RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	15963	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	15964	* \| \| \|0 = Port n bit m high-level or rising edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	15965	* \| \| \|1 = Port n bit m high-level or rising edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	15966	* \|[18] \|RHIEN2 \|Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
sahilmgandhi	18:6a4db94011d3	15967	* \| \| \|RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	15968	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	15969	* \| \| \|0 = Port n bit m high-level or rising edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	15970	* \| \| \|1 = Port n bit m high-level or rising edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	15971	* \|[19] \|RHIEN3 \|Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
sahilmgandhi	18:6a4db94011d3	15972	* \| \| \|RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	15973	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	15974	* \| \| \|0 = Port n bit m high-level or rising edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	15975	* \| \| \|1 = Port n bit m high-level or rising edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	15976	* \|[20] \|RHIEN4 \|Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
sahilmgandhi	18:6a4db94011d3	15977	* \| \| \|RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	15978	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	15979	* \| \| \|0 = Port n bit m high-level or rising edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	15980	* \| \| \|1 = Port n bit m high-level or rising edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	15981	* \|[21] \|RHIEN5 \|Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
sahilmgandhi	18:6a4db94011d3	15982	* \| \| \|RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	15983	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	15984	* \| \| \|0 = Port n bit m high-level or rising edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	15985	* \| \| \|1 = Port n bit m high-level or rising edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	15986	* \|[22] \|RHIEN6 \|Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
sahilmgandhi	18:6a4db94011d3	15987	* \| \| \|RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	15988	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	15989	* \| \| \|0 = Port n bit m high-level or rising edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	15990	* \| \| \|1 = Port n bit m high-level or rising edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	15991	* \|[23] \|RHIEN7 \|Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
sahilmgandhi	18:6a4db94011d3	15992	* \| \| \|RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	15993	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	15994	* \| \| \|0 = Port n bit m high-level or rising edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	15995	* \| \| \|1 = Port n bit m high-level or rising edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	15996	* \|[24] \|RHIEN8 \|Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
sahilmgandhi	18:6a4db94011d3	15997	* \| \| \|RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	15998	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	15999	* \| \| \|0 = Port n bit m high-level or rising edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	16000	* \| \| \|1 = Port n bit m high-level or rising edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	16001	* \|[25] \|RHIEN9 \|Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
sahilmgandhi	18:6a4db94011d3	16002	* \| \| \|RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	16003	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	16004	* \| \| \|0 = Port n bit m high-level or rising edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	16005	* \| \| \|1 = Port n bit m high-level or rising edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	16006	* \|[26] \|RHIEN10 \|Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
sahilmgandhi	18:6a4db94011d3	16007	* \| \| \|RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	16008	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	16009	* \| \| \|0 = Port n bit m high-level or rising edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	16010	* \| \| \|1 = Port n bit m high-level or rising edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	16011	* \|[27] \|RHIEN11 \|Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
sahilmgandhi	18:6a4db94011d3	16012	* \| \| \|RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	16013	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	16014	* \| \| \|0 = Port n bit m high-level or rising edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	16015	* \| \| \|1 = Port n bit m high-level or rising edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	16016	* \|[28] \|RHIEN12 \|Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
sahilmgandhi	18:6a4db94011d3	16017	* \| \| \|RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	16018	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	16019	* \| \| \|0 = Port n bit m high-level or rising edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	16020	* \| \| \|1 = Port n bit m high-level or rising edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	16021	* \|[29] \|RHIEN13 \|Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
sahilmgandhi	18:6a4db94011d3	16022	* \| \| \|RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	16023	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	16024	* \| \| \|0 = Port n bit m high-level or rising edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	16025	* \| \| \|1 = Port n bit m high-level or rising edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	16026	* \|[30] \|RHIEN14 \|Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
sahilmgandhi	18:6a4db94011d3	16027	* \| \| \|RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	16028	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	16029	* \| \| \|0 = Port n bit m high-level or rising edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	16030	* \| \| \|1 = Port n bit m high-level or rising edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	16031	* \|[31] \|RHIEN15 \|Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
sahilmgandhi	18:6a4db94011d3	16032	* \| \| \|RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
sahilmgandhi	18:6a4db94011d3	16033	* \| \| \|Setting this bit to 1 also enables the pin wake-up function.
sahilmgandhi	18:6a4db94011d3	16034	* \| \| \|0 = Port n bit m high-level or rising edge interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	16035	* \| \| \|1 = Port n bit m high-level or rising edge interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	16036	*/
sahilmgandhi	18:6a4db94011d3	16037	__IO uint32_t INTEN;
sahilmgandhi	18:6a4db94011d3	16038
sahilmgandhi	18:6a4db94011d3	16039	/**
sahilmgandhi	18:6a4db94011d3	16040	* Px_INTSRC
sahilmgandhi	18:6a4db94011d3	16041	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	16042	* Offset: 0x20 Px Interrupt Source Flag
sahilmgandhi	18:6a4db94011d3	16043	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	16044	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	16045	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	16046	* \|[0] \|INTSRC0 \|Port N Bit M Interrupt Trigger Source Indicator
sahilmgandhi	18:6a4db94011d3	16047	* \| \| \|Read:
sahilmgandhi	18:6a4db94011d3	16048	* \| \| \|0 = No interrupt at Port n.
sahilmgandhi	18:6a4db94011d3	16049	* \| \| \|1 = Port n bit m generate an interrupt.
sahilmgandhi	18:6a4db94011d3	16050	* \| \| \|Write:
sahilmgandhi	18:6a4db94011d3	16051	* \| \| \|0= No effect.
sahilmgandhi	18:6a4db94011d3	16052	* \| \| \|1= Clear the correspond pending interrupt.
sahilmgandhi	18:6a4db94011d3	16053	* \|[1] \|INTSRC1 \|Port N Bit M Interrupt Trigger Source Indicator
sahilmgandhi	18:6a4db94011d3	16054	* \| \| \|Read:
sahilmgandhi	18:6a4db94011d3	16055	* \| \| \|0 = No interrupt at Port n.
sahilmgandhi	18:6a4db94011d3	16056	* \| \| \|1 = Port n bit m generate an interrupt.
sahilmgandhi	18:6a4db94011d3	16057	* \| \| \|Write:
sahilmgandhi	18:6a4db94011d3	16058	* \| \| \|0= No effect.
sahilmgandhi	18:6a4db94011d3	16059	* \| \| \|1= Clear the correspond pending interrupt.
sahilmgandhi	18:6a4db94011d3	16060	* \|[2] \|INTSRC2 \|Port N Bit M Interrupt Trigger Source Indicator
sahilmgandhi	18:6a4db94011d3	16061	* \| \| \|Read:
sahilmgandhi	18:6a4db94011d3	16062	* \| \| \|0 = No interrupt at Port n.
sahilmgandhi	18:6a4db94011d3	16063	* \| \| \|1 = Port n bit m generate an interrupt.
sahilmgandhi	18:6a4db94011d3	16064	* \| \| \|Write:
sahilmgandhi	18:6a4db94011d3	16065	* \| \| \|0= No effect.
sahilmgandhi	18:6a4db94011d3	16066	* \| \| \|1= Clear the correspond pending interrupt.
sahilmgandhi	18:6a4db94011d3	16067	* \|[3] \|INTSRC3 \|Port N Bit M Interrupt Trigger Source Indicator
sahilmgandhi	18:6a4db94011d3	16068	* \| \| \|Read:
sahilmgandhi	18:6a4db94011d3	16069	* \| \| \|0 = No interrupt at Port n.
sahilmgandhi	18:6a4db94011d3	16070	* \| \| \|1 = Port n bit m generate an interrupt.
sahilmgandhi	18:6a4db94011d3	16071	* \| \| \|Write:
sahilmgandhi	18:6a4db94011d3	16072	* \| \| \|0= No effect.
sahilmgandhi	18:6a4db94011d3	16073	* \| \| \|1= Clear the correspond pending interrupt.
sahilmgandhi	18:6a4db94011d3	16074	* \|[4] \|INTSRC4 \|Port N Bit M Interrupt Trigger Source Indicator
sahilmgandhi	18:6a4db94011d3	16075	* \| \| \|Read:
sahilmgandhi	18:6a4db94011d3	16076	* \| \| \|0 = No interrupt at Port n.
sahilmgandhi	18:6a4db94011d3	16077	* \| \| \|1 = Port n bit m generate an interrupt.
sahilmgandhi	18:6a4db94011d3	16078	* \| \| \|Write:
sahilmgandhi	18:6a4db94011d3	16079	* \| \| \|0= No effect.
sahilmgandhi	18:6a4db94011d3	16080	* \| \| \|1= Clear the correspond pending interrupt.
sahilmgandhi	18:6a4db94011d3	16081	* \|[5] \|INTSRC5 \|Port N Bit M Interrupt Trigger Source Indicator
sahilmgandhi	18:6a4db94011d3	16082	* \| \| \|Read:
sahilmgandhi	18:6a4db94011d3	16083	* \| \| \|0 = No interrupt at Port n.
sahilmgandhi	18:6a4db94011d3	16084	* \| \| \|1 = Port n bit m generate an interrupt.
sahilmgandhi	18:6a4db94011d3	16085	* \| \| \|Write:
sahilmgandhi	18:6a4db94011d3	16086	* \| \| \|0= No effect.
sahilmgandhi	18:6a4db94011d3	16087	* \| \| \|1= Clear the correspond pending interrupt.
sahilmgandhi	18:6a4db94011d3	16088	* \|[6] \|INTSRC6 \|Port N Bit M Interrupt Trigger Source Indicator
sahilmgandhi	18:6a4db94011d3	16089	* \| \| \|Read:
sahilmgandhi	18:6a4db94011d3	16090	* \| \| \|0 = No interrupt at Port n.
sahilmgandhi	18:6a4db94011d3	16091	* \| \| \|1 = Port n bit m generate an interrupt.
sahilmgandhi	18:6a4db94011d3	16092	* \| \| \|Write:
sahilmgandhi	18:6a4db94011d3	16093	* \| \| \|0= No effect.
sahilmgandhi	18:6a4db94011d3	16094	* \| \| \|1= Clear the correspond pending interrupt.
sahilmgandhi	18:6a4db94011d3	16095	* \|[7] \|INTSRC7 \|Port N Bit M Interrupt Trigger Source Indicator
sahilmgandhi	18:6a4db94011d3	16096	* \| \| \|Read:
sahilmgandhi	18:6a4db94011d3	16097	* \| \| \|0 = No interrupt at Port n.
sahilmgandhi	18:6a4db94011d3	16098	* \| \| \|1 = Port n bit m generate an interrupt.
sahilmgandhi	18:6a4db94011d3	16099	* \| \| \|Write:
sahilmgandhi	18:6a4db94011d3	16100	* \| \| \|0= No effect.
sahilmgandhi	18:6a4db94011d3	16101	* \| \| \|1= Clear the correspond pending interrupt.
sahilmgandhi	18:6a4db94011d3	16102	* \|[8] \|INTSRC8 \|Port N Bit M Interrupt Trigger Source Indicator
sahilmgandhi	18:6a4db94011d3	16103	* \| \| \|Read:
sahilmgandhi	18:6a4db94011d3	16104	* \| \| \|0 = No interrupt at Port n.
sahilmgandhi	18:6a4db94011d3	16105	* \| \| \|1 = Port n bit m generate an interrupt.
sahilmgandhi	18:6a4db94011d3	16106	* \| \| \|Write:
sahilmgandhi	18:6a4db94011d3	16107	* \| \| \|0= No effect.
sahilmgandhi	18:6a4db94011d3	16108	* \| \| \|1= Clear the correspond pending interrupt.
sahilmgandhi	18:6a4db94011d3	16109	* \|[9] \|INTSRC9 \|Port N Bit M Interrupt Trigger Source Indicator
sahilmgandhi	18:6a4db94011d3	16110	* \| \| \|Read:
sahilmgandhi	18:6a4db94011d3	16111	* \| \| \|0 = No interrupt at Port n.
sahilmgandhi	18:6a4db94011d3	16112	* \| \| \|1 = Port n bit m generate an interrupt.
sahilmgandhi	18:6a4db94011d3	16113	* \| \| \|Write:
sahilmgandhi	18:6a4db94011d3	16114	* \| \| \|0= No effect.
sahilmgandhi	18:6a4db94011d3	16115	* \| \| \|1= Clear the correspond pending interrupt.
sahilmgandhi	18:6a4db94011d3	16116	* \|[10] \|INTSRC10 \|Port N Bit M Interrupt Trigger Source Indicator
sahilmgandhi	18:6a4db94011d3	16117	* \| \| \|Read:
sahilmgandhi	18:6a4db94011d3	16118	* \| \| \|0 = No interrupt at Port n.
sahilmgandhi	18:6a4db94011d3	16119	* \| \| \|1 = Port n bit m generate an interrupt.
sahilmgandhi	18:6a4db94011d3	16120	* \| \| \|Write:
sahilmgandhi	18:6a4db94011d3	16121	* \| \| \|0= No effect.
sahilmgandhi	18:6a4db94011d3	16122	* \| \| \|1= Clear the correspond pending interrupt.
sahilmgandhi	18:6a4db94011d3	16123	* \|[11] \|INTSRC11 \|Port N Bit M Interrupt Trigger Source Indicator
sahilmgandhi	18:6a4db94011d3	16124	* \| \| \|Read:
sahilmgandhi	18:6a4db94011d3	16125	* \| \| \|0 = No interrupt at Port n.
sahilmgandhi	18:6a4db94011d3	16126	* \| \| \|1 = Port n bit m generate an interrupt.
sahilmgandhi	18:6a4db94011d3	16127	* \| \| \|Write:
sahilmgandhi	18:6a4db94011d3	16128	* \| \| \|0= No effect.
sahilmgandhi	18:6a4db94011d3	16129	* \| \| \|1= Clear the correspond pending interrupt.
sahilmgandhi	18:6a4db94011d3	16130	* \|[12] \|INTSRC12 \|Port N Bit M Interrupt Trigger Source Indicator
sahilmgandhi	18:6a4db94011d3	16131	* \| \| \|Read:
sahilmgandhi	18:6a4db94011d3	16132	* \| \| \|0 = No interrupt at Port n.
sahilmgandhi	18:6a4db94011d3	16133	* \| \| \|1 = Port n bit m generate an interrupt.
sahilmgandhi	18:6a4db94011d3	16134	* \| \| \|Write:
sahilmgandhi	18:6a4db94011d3	16135	* \| \| \|0= No effect.
sahilmgandhi	18:6a4db94011d3	16136	* \| \| \|1= Clear the correspond pending interrupt.
sahilmgandhi	18:6a4db94011d3	16137	* \|[13] \|INTSRC13 \|Port N Bit M Interrupt Trigger Source Indicator
sahilmgandhi	18:6a4db94011d3	16138	* \| \| \|Read:
sahilmgandhi	18:6a4db94011d3	16139	* \| \| \|0 = No interrupt at Port n.
sahilmgandhi	18:6a4db94011d3	16140	* \| \| \|1 = Port n bit m generate an interrupt.
sahilmgandhi	18:6a4db94011d3	16141	* \| \| \|Write:
sahilmgandhi	18:6a4db94011d3	16142	* \| \| \|0= No effect.
sahilmgandhi	18:6a4db94011d3	16143	* \| \| \|1= Clear the correspond pending interrupt.
sahilmgandhi	18:6a4db94011d3	16144	* \|[14] \|INTSRC14 \|Port N Bit M Interrupt Trigger Source Indicator
sahilmgandhi	18:6a4db94011d3	16145	* \| \| \|Read:
sahilmgandhi	18:6a4db94011d3	16146	* \| \| \|0 = No interrupt at Port n.
sahilmgandhi	18:6a4db94011d3	16147	* \| \| \|1 = Port n bit m generate an interrupt.
sahilmgandhi	18:6a4db94011d3	16148	* \| \| \|Write:
sahilmgandhi	18:6a4db94011d3	16149	* \| \| \|0= No effect.
sahilmgandhi	18:6a4db94011d3	16150	* \| \| \|1= Clear the correspond pending interrupt.
sahilmgandhi	18:6a4db94011d3	16151	* \|[15] \|INTSRC15 \|Port N Bit M Interrupt Trigger Source Indicator
sahilmgandhi	18:6a4db94011d3	16152	* \| \| \|Read:
sahilmgandhi	18:6a4db94011d3	16153	* \| \| \|0 = No interrupt at Port n.
sahilmgandhi	18:6a4db94011d3	16154	* \| \| \|1 = Port n bit m generate an interrupt.
sahilmgandhi	18:6a4db94011d3	16155	* \| \| \|Write:
sahilmgandhi	18:6a4db94011d3	16156	* \| \| \|0= No effect.
sahilmgandhi	18:6a4db94011d3	16157	* \| \| \|1= Clear the correspond pending interrupt.
sahilmgandhi	18:6a4db94011d3	16158	*/
sahilmgandhi	18:6a4db94011d3	16159	__IO uint32_t INTSRC;
sahilmgandhi	18:6a4db94011d3	16160
sahilmgandhi	18:6a4db94011d3	16161	/**
sahilmgandhi	18:6a4db94011d3	16162	* Px_SMTEN
sahilmgandhi	18:6a4db94011d3	16163	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	16164	* Offset: 0x24 Px Input Schmitt Trigger Enable
sahilmgandhi	18:6a4db94011d3	16165	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	16166	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	16167	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	16168	* \|[0] \|SMTEN0 \|0 = P I/O input Schmitt Trigger function Disabled.
sahilmgandhi	18:6a4db94011d3	16169	* \| \| \|1 = P I/O input Schmitt Trigger function Enabled.
sahilmgandhi	18:6a4db94011d3	16170	* \|[1] \|SMTEN1 \|0 = P I/O input Schmitt Trigger function Disabled.
sahilmgandhi	18:6a4db94011d3	16171	* \| \| \|1 = P I/O input Schmitt Trigger function Enabled.
sahilmgandhi	18:6a4db94011d3	16172	* \|[2] \|SMTEN2 \|0 = P I/O input Schmitt Trigger function Disabled.
sahilmgandhi	18:6a4db94011d3	16173	* \| \| \|1 = P I/O input Schmitt Trigger function Enabled.
sahilmgandhi	18:6a4db94011d3	16174	* \|[3] \|SMTEN3 \|0 = P I/O input Schmitt Trigger function Disabled.
sahilmgandhi	18:6a4db94011d3	16175	* \| \| \|1 = P I/O input Schmitt Trigger function Enabled.
sahilmgandhi	18:6a4db94011d3	16176	* \|[4] \|SMTEN4 \|0 = P I/O input Schmitt Trigger function Disabled.
sahilmgandhi	18:6a4db94011d3	16177	* \| \| \|1 = P I/O input Schmitt Trigger function Enabled.
sahilmgandhi	18:6a4db94011d3	16178	* \|[5] \|SMTEN5 \|0 = P I/O input Schmitt Trigger function Disabled.
sahilmgandhi	18:6a4db94011d3	16179	* \| \| \|1 = P I/O input Schmitt Trigger function Enabled.
sahilmgandhi	18:6a4db94011d3	16180	* \|[6] \|SMTEN6 \|0 = P I/O input Schmitt Trigger function Disabled.
sahilmgandhi	18:6a4db94011d3	16181	* \| \| \|1 = P I/O input Schmitt Trigger function Enabled.
sahilmgandhi	18:6a4db94011d3	16182	* \|[7] \|SMTEN7 \|0 = P I/O input Schmitt Trigger function Disabled.
sahilmgandhi	18:6a4db94011d3	16183	* \| \| \|1 = P I/O input Schmitt Trigger function Enabled.
sahilmgandhi	18:6a4db94011d3	16184	* \|[8] \|SMTEN8 \|0 = P I/O input Schmitt Trigger function Disabled.
sahilmgandhi	18:6a4db94011d3	16185	* \| \| \|1 = P I/O input Schmitt Trigger function Enabled.
sahilmgandhi	18:6a4db94011d3	16186	* \|[9] \|SMTEN9 \|0 = P I/O input Schmitt Trigger function Disabled.
sahilmgandhi	18:6a4db94011d3	16187	* \| \| \|1 = P I/O input Schmitt Trigger function Enabled.
sahilmgandhi	18:6a4db94011d3	16188	* \|[10] \|SMTEN10 \|0 = P I/O input Schmitt Trigger function Disabled.
sahilmgandhi	18:6a4db94011d3	16189	* \| \| \|1 = P I/O input Schmitt Trigger function Enabled.
sahilmgandhi	18:6a4db94011d3	16190	* \|[11] \|SMTEN11 \|0 = P I/O input Schmitt Trigger function Disabled.
sahilmgandhi	18:6a4db94011d3	16191	* \| \| \|1 = P I/O input Schmitt Trigger function Enabled.
sahilmgandhi	18:6a4db94011d3	16192	* \|[12] \|SMTEN12 \|0 = P I/O input Schmitt Trigger function Disabled.
sahilmgandhi	18:6a4db94011d3	16193	* \| \| \|1 = P I/O input Schmitt Trigger function Enabled.
sahilmgandhi	18:6a4db94011d3	16194	* \|[13] \|SMTEN13 \|0 = P I/O input Schmitt Trigger function Disabled.
sahilmgandhi	18:6a4db94011d3	16195	* \| \| \|1 = P I/O input Schmitt Trigger function Enabled.
sahilmgandhi	18:6a4db94011d3	16196	* \|[14] \|SMTEN14 \|0 = P I/O input Schmitt Trigger function Disabled.
sahilmgandhi	18:6a4db94011d3	16197	* \| \| \|1 = P I/O input Schmitt Trigger function Enabled.
sahilmgandhi	18:6a4db94011d3	16198	* \|[15] \|SMTEN15 \|0 = P I/O input Schmitt Trigger function Disabled.
sahilmgandhi	18:6a4db94011d3	16199	* \| \| \|1 = P I/O input Schmitt Trigger function Enabled.
sahilmgandhi	18:6a4db94011d3	16200	*/
sahilmgandhi	18:6a4db94011d3	16201	__IO uint32_t SMTEN;
sahilmgandhi	18:6a4db94011d3	16202
sahilmgandhi	18:6a4db94011d3	16203	/**
sahilmgandhi	18:6a4db94011d3	16204	* Px_SLEWCTL
sahilmgandhi	18:6a4db94011d3	16205	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	16206	* Offset: 0x28 Px High Slew Rate Control
sahilmgandhi	18:6a4db94011d3	16207	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	16208	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	16209	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	16210	* \|[0] \|HSREN0 \|0 = P I/O output with basic slew rate.
sahilmgandhi	18:6a4db94011d3	16211	* \| \| \|1 = P I/O output with higher slew rate.
sahilmgandhi	18:6a4db94011d3	16212	* \|[1] \|HSREN1 \|0 = P I/O output with basic slew rate.
sahilmgandhi	18:6a4db94011d3	16213	* \| \| \|1 = P I/O output with higher slew rate.
sahilmgandhi	18:6a4db94011d3	16214	* \|[2] \|HSREN2 \|0 = P I/O output with basic slew rate.
sahilmgandhi	18:6a4db94011d3	16215	* \| \| \|1 = P I/O output with higher slew rate.
sahilmgandhi	18:6a4db94011d3	16216	* \|[3] \|HSREN3 \|0 = P I/O output with basic slew rate.
sahilmgandhi	18:6a4db94011d3	16217	* \| \| \|1 = P I/O output with higher slew rate.
sahilmgandhi	18:6a4db94011d3	16218	* \|[4] \|HSREN4 \|0 = P I/O output with basic slew rate.
sahilmgandhi	18:6a4db94011d3	16219	* \| \| \|1 = P I/O output with higher slew rate.
sahilmgandhi	18:6a4db94011d3	16220	* \|[5] \|HSREN5 \|0 = P I/O output with basic slew rate.
sahilmgandhi	18:6a4db94011d3	16221	* \| \| \|1 = P I/O output with higher slew rate.
sahilmgandhi	18:6a4db94011d3	16222	* \|[6] \|HSREN6 \|0 = P I/O output with basic slew rate.
sahilmgandhi	18:6a4db94011d3	16223	* \| \| \|1 = P I/O output with higher slew rate.
sahilmgandhi	18:6a4db94011d3	16224	* \|[7] \|HSREN7 \|0 = P I/O output with basic slew rate.
sahilmgandhi	18:6a4db94011d3	16225	* \| \| \|1 = P I/O output with higher slew rate.
sahilmgandhi	18:6a4db94011d3	16226	* \|[8] \|HSREN8 \|0 = P I/O output with basic slew rate.
sahilmgandhi	18:6a4db94011d3	16227	* \| \| \|1 = P I/O output with higher slew rate.
sahilmgandhi	18:6a4db94011d3	16228	* \|[9] \|HSREN9 \|0 = P I/O output with basic slew rate.
sahilmgandhi	18:6a4db94011d3	16229	* \| \| \|1 = P I/O output with higher slew rate.
sahilmgandhi	18:6a4db94011d3	16230	* \|[10] \|HSREN10 \|0 = P I/O output with basic slew rate.
sahilmgandhi	18:6a4db94011d3	16231	* \| \| \|1 = P I/O output with higher slew rate.
sahilmgandhi	18:6a4db94011d3	16232	* \|[11] \|HSREN11 \|0 = P I/O output with basic slew rate.
sahilmgandhi	18:6a4db94011d3	16233	* \| \| \|1 = P I/O output with higher slew rate.
sahilmgandhi	18:6a4db94011d3	16234	* \|[12] \|HSREN12 \|0 = P I/O output with basic slew rate.
sahilmgandhi	18:6a4db94011d3	16235	* \| \| \|1 = P I/O output with higher slew rate.
sahilmgandhi	18:6a4db94011d3	16236	* \|[13] \|HSREN13 \|0 = P I/O output with basic slew rate.
sahilmgandhi	18:6a4db94011d3	16237	* \| \| \|1 = P I/O output with higher slew rate.
sahilmgandhi	18:6a4db94011d3	16238	* \|[14] \|HSREN14 \|0 = P I/O output with basic slew rate.
sahilmgandhi	18:6a4db94011d3	16239	* \| \| \|1 = P I/O output with higher slew rate.
sahilmgandhi	18:6a4db94011d3	16240	* \|[15] \|HSREN15 \|0 = P I/O output with basic slew rate.
sahilmgandhi	18:6a4db94011d3	16241	* \| \| \|1 = P I/O output with higher slew rate.
sahilmgandhi	18:6a4db94011d3	16242	*/
sahilmgandhi	18:6a4db94011d3	16243	__IO uint32_t SLEWCTL;
sahilmgandhi	18:6a4db94011d3	16244
sahilmgandhi	18:6a4db94011d3	16245	} GPIO_T;
sahilmgandhi	18:6a4db94011d3	16246
sahilmgandhi	18:6a4db94011d3	16247
sahilmgandhi	18:6a4db94011d3	16248	typedef struct {
sahilmgandhi	18:6a4db94011d3	16249
sahilmgandhi	18:6a4db94011d3	16250	/**
sahilmgandhi	18:6a4db94011d3	16251	* GPIO_DBCTL
sahilmgandhi	18:6a4db94011d3	16252	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	16253	* Offset: 0x000 Interrupt De-bounce Control
sahilmgandhi	18:6a4db94011d3	16254	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	16255	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	16256	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	16257	* \|[0:3] \|DBCLKSEL \|De-Bounce Sampling Cycle Selection
sahilmgandhi	18:6a4db94011d3	16258	* \| \| \|0000 = Sample interrupt input once per 1 clocks.
sahilmgandhi	18:6a4db94011d3	16259	* \| \| \|0001 = Sample interrupt input once per 2 clocks.
sahilmgandhi	18:6a4db94011d3	16260	* \| \| \|0010 = Sample interrupt input once per 4 clocks.
sahilmgandhi	18:6a4db94011d3	16261	* \| \| \|0011 = Sample interrupt input once per 8 clocks.
sahilmgandhi	18:6a4db94011d3	16262	* \| \| \|0100 = Sample interrupt input once per 16 clocks.
sahilmgandhi	18:6a4db94011d3	16263	* \| \| \|0101 = Sample interrupt input once per 32 clocks.
sahilmgandhi	18:6a4db94011d3	16264	* \| \| \|0110 = Sample interrupt input once per 64 clocks.
sahilmgandhi	18:6a4db94011d3	16265	* \| \| \|0111 = Sample interrupt input once per 128 clocks.
sahilmgandhi	18:6a4db94011d3	16266	* \| \| \|1000 = Sample interrupt input once per 256 clocks.
sahilmgandhi	18:6a4db94011d3	16267	* \| \| \|1001 = Sample interrupt input once per 2*256 clocks.
sahilmgandhi	18:6a4db94011d3	16268	* \| \| \|1010 = Sample interrupt input once per 4*256 clocks.
sahilmgandhi	18:6a4db94011d3	16269	* \| \| \|1011 = Sample interrupt input once per 8*256 clocks.
sahilmgandhi	18:6a4db94011d3	16270	* \| \| \|1100 = Sample interrupt input once per 16*256 clocks.
sahilmgandhi	18:6a4db94011d3	16271	* \| \| \|1101 = Sample interrupt input once per 32*256 clocks.
sahilmgandhi	18:6a4db94011d3	16272	* \| \| \|1110 = Sample interrupt input once per 64*256 clocks.
sahilmgandhi	18:6a4db94011d3	16273	* \| \| \|1111 = Sample interrupt input once per 128*256 clocks.
sahilmgandhi	18:6a4db94011d3	16274	* \|[4] \|DBCLKSRC \|De-Bounce Counter Clock Source Selection
sahilmgandhi	18:6a4db94011d3	16275	* \| \| \|0 = De-bounce counter clock source is the HCLK.
sahilmgandhi	18:6a4db94011d3	16276	* \| \| \|1 = De-bounce counter clock source is the internal 10 kHz clock.
sahilmgandhi	18:6a4db94011d3	16277	* \|[5] \|ICLKON \|Interrupt Clock On Mode
sahilmgandhi	18:6a4db94011d3	16278	* \| \| \|Setting this bit to 0 will disable the interrupt generate circuit clock if the pin[n] interrupt is disabled.
sahilmgandhi	18:6a4db94011d3	16279	* \| \| \|0 = Disable the clock if the all port interrupts are disabled.
sahilmgandhi	18:6a4db94011d3	16280	* \| \| \|1 = Interrupt generated circuit clock always Enabled.
sahilmgandhi	18:6a4db94011d3	16281	*/
sahilmgandhi	18:6a4db94011d3	16282	__IO uint32_t DBCTL;
sahilmgandhi	18:6a4db94011d3	16283
sahilmgandhi	18:6a4db94011d3	16284	} GPIO_DB_T;
sahilmgandhi	18:6a4db94011d3	16285
sahilmgandhi	18:6a4db94011d3	16286	/**
sahilmgandhi	18:6a4db94011d3	16287	@addtogroup GPIO_CONST GPIO Bit Field Definition
sahilmgandhi	18:6a4db94011d3	16288	Constant Definitions for GPIO Controller
sahilmgandhi	18:6a4db94011d3	16289	@{ */
sahilmgandhi	18:6a4db94011d3	16290
sahilmgandhi	18:6a4db94011d3	16291	#define GPIO_MODE_MODE0_Pos (0) /!< GPIO MODE: MODE0 Position /
sahilmgandhi	18:6a4db94011d3	16292	#define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) /!< GPIO MODE: MODE0 Mask /
sahilmgandhi	18:6a4db94011d3	16293
sahilmgandhi	18:6a4db94011d3	16294	#define GPIO_MODE_MODE1_Pos (2) /!< GPIO MODE: MODE1 Position /
sahilmgandhi	18:6a4db94011d3	16295	#define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) /!< GPIO MODE: MODE1 Mask /
sahilmgandhi	18:6a4db94011d3	16296
sahilmgandhi	18:6a4db94011d3	16297	#define GPIO_MODE_MODE2_Pos (4) /!< GPIO MODE: MODE2 Position /
sahilmgandhi	18:6a4db94011d3	16298	#define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) /!< GPIO MODE: MODE2 Mask /
sahilmgandhi	18:6a4db94011d3	16299
sahilmgandhi	18:6a4db94011d3	16300	#define GPIO_MODE_MODE3_Pos (6) /!< GPIO MODE: MODE3 Position /
sahilmgandhi	18:6a4db94011d3	16301	#define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) /!< GPIO MODE: MODE3 Mask /
sahilmgandhi	18:6a4db94011d3	16302
sahilmgandhi	18:6a4db94011d3	16303	#define GPIO_MODE_MODE4_Pos (8) /!< GPIO MODE: MODE4 Position /
sahilmgandhi	18:6a4db94011d3	16304	#define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) /!< GPIO MODE: MODE4 Mask /
sahilmgandhi	18:6a4db94011d3	16305
sahilmgandhi	18:6a4db94011d3	16306	#define GPIO_MODE_MODE5_Pos (10) /!< GPIO MODE: MODE5 Position /
sahilmgandhi	18:6a4db94011d3	16307	#define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) /!< GPIO MODE: MODE5 Mask /
sahilmgandhi	18:6a4db94011d3	16308
sahilmgandhi	18:6a4db94011d3	16309	#define GPIO_MODE_MODE6_Pos (12) /!< GPIO MODE: MODE6 Position /
sahilmgandhi	18:6a4db94011d3	16310	#define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) /!< GPIO MODE: MODE6 Mask /
sahilmgandhi	18:6a4db94011d3	16311
sahilmgandhi	18:6a4db94011d3	16312	#define GPIO_MODE_MODE7_Pos (14) /!< GPIO MODE: MODE7 Position /
sahilmgandhi	18:6a4db94011d3	16313	#define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) /!< GPIO MODE: MODE7 Mask /
sahilmgandhi	18:6a4db94011d3	16314
sahilmgandhi	18:6a4db94011d3	16315	#define GPIO_MODE_MODE8_Pos (16) /!< GPIO MODE: MODE8 Position /
sahilmgandhi	18:6a4db94011d3	16316	#define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) /!< GPIO MODE: MODE8 Mask /
sahilmgandhi	18:6a4db94011d3	16317
sahilmgandhi	18:6a4db94011d3	16318	#define GPIO_MODE_MODE9_Pos (18) /!< GPIO MODE: MODE9 Position /
sahilmgandhi	18:6a4db94011d3	16319	#define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) /!< GPIO MODE: MODE9 Mask /
sahilmgandhi	18:6a4db94011d3	16320
sahilmgandhi	18:6a4db94011d3	16321	#define GPIO_MODE_MODE10_Pos (20) /!< GPIO MODE: MODE10 Position /
sahilmgandhi	18:6a4db94011d3	16322	#define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) /!< GPIO MODE: MODE10 Mask /
sahilmgandhi	18:6a4db94011d3	16323
sahilmgandhi	18:6a4db94011d3	16324	#define GPIO_MODE_MODE11_Pos (22) /!< GPIO MODE: MODE11 Position /
sahilmgandhi	18:6a4db94011d3	16325	#define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) /!< GPIO MODE: MODE11 Mask /
sahilmgandhi	18:6a4db94011d3	16326
sahilmgandhi	18:6a4db94011d3	16327	#define GPIO_MODE_MODE12_Pos (24) /!< GPIO MODE: MODE12 Position /
sahilmgandhi	18:6a4db94011d3	16328	#define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) /!< GPIO MODE: MODE12 Mask /
sahilmgandhi	18:6a4db94011d3	16329
sahilmgandhi	18:6a4db94011d3	16330	#define GPIO_MODE_MODE13_Pos (26) /!< GPIO MODE: MODE13 Position /
sahilmgandhi	18:6a4db94011d3	16331	#define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) /!< GPIO MODE: MODE13 Mask /
sahilmgandhi	18:6a4db94011d3	16332
sahilmgandhi	18:6a4db94011d3	16333	#define GPIO_MODE_MODE14_Pos (28) /!< GPIO MODE: MODE14 Position /
sahilmgandhi	18:6a4db94011d3	16334	#define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) /!< GPIO MODE: MODE14 Mask /
sahilmgandhi	18:6a4db94011d3	16335
sahilmgandhi	18:6a4db94011d3	16336	#define GPIO_MODE_MODE15_Pos (30) /!< GPIO MODE: MODE15 Position /
sahilmgandhi	18:6a4db94011d3	16337	#define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) /!< GPIO MODE: MODE15 Mask /
sahilmgandhi	18:6a4db94011d3	16338
sahilmgandhi	18:6a4db94011d3	16339	#define GPIO_DINOFF_DINOFF0_Pos (16) /!< GPIO DINOFF: DINOFF0 Position /
sahilmgandhi	18:6a4db94011d3	16340	#define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) /!< GPIO DINOFF: DINOFF0 Mask /
sahilmgandhi	18:6a4db94011d3	16341
sahilmgandhi	18:6a4db94011d3	16342	#define GPIO_DINOFF_DINOFF1_Pos (17) /!< GPIO DINOFF: DINOFF1 Position /
sahilmgandhi	18:6a4db94011d3	16343	#define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) /!< GPIO DINOFF: DINOFF1 Mask /
sahilmgandhi	18:6a4db94011d3	16344
sahilmgandhi	18:6a4db94011d3	16345	#define GPIO_DINOFF_DINOFF2_Pos (18) /!< GPIO DINOFF: DINOFF2 Position /
sahilmgandhi	18:6a4db94011d3	16346	#define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) /!< GPIO DINOFF: DINOFF2 Mask /
sahilmgandhi	18:6a4db94011d3	16347
sahilmgandhi	18:6a4db94011d3	16348	#define GPIO_DINOFF_DINOFF3_Pos (19) /!< GPIO DINOFF: DINOFF3 Position /
sahilmgandhi	18:6a4db94011d3	16349	#define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) /!< GPIO DINOFF: DINOFF3 Mask /
sahilmgandhi	18:6a4db94011d3	16350
sahilmgandhi	18:6a4db94011d3	16351	#define GPIO_DINOFF_DINOFF4_Pos (20) /!< GPIO DINOFF: DINOFF4 Position /
sahilmgandhi	18:6a4db94011d3	16352	#define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) /!< GPIO DINOFF: DINOFF4 Mask /
sahilmgandhi	18:6a4db94011d3	16353
sahilmgandhi	18:6a4db94011d3	16354	#define GPIO_DINOFF_DINOFF5_Pos (21) /!< GPIO DINOFF: DINOFF5 Position /
sahilmgandhi	18:6a4db94011d3	16355	#define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) /!< GPIO DINOFF: DINOFF5 Mask /
sahilmgandhi	18:6a4db94011d3	16356
sahilmgandhi	18:6a4db94011d3	16357	#define GPIO_DINOFF_DINOFF6_Pos (22) /!< GPIO DINOFF: DINOFF6 Position /
sahilmgandhi	18:6a4db94011d3	16358	#define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) /!< GPIO DINOFF: DINOFF6 Mask /
sahilmgandhi	18:6a4db94011d3	16359
sahilmgandhi	18:6a4db94011d3	16360	#define GPIO_DINOFF_DINOFF7_Pos (23) /!< GPIO DINOFF: DINOFF7 Position /
sahilmgandhi	18:6a4db94011d3	16361	#define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) /!< GPIO DINOFF: DINOFF7 Mask /
sahilmgandhi	18:6a4db94011d3	16362
sahilmgandhi	18:6a4db94011d3	16363	#define GPIO_DINOFF_DINOFF8_Pos (24) /!< GPIO DINOFF: DINOFF8 Position /
sahilmgandhi	18:6a4db94011d3	16364	#define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) /!< GPIO DINOFF: DINOFF8 Mask /
sahilmgandhi	18:6a4db94011d3	16365
sahilmgandhi	18:6a4db94011d3	16366	#define GPIO_DINOFF_DINOFF9_Pos (25) /!< GPIO DINOFF: DINOFF9 Position /
sahilmgandhi	18:6a4db94011d3	16367	#define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) /!< GPIO DINOFF: DINOFF9 Mask /
sahilmgandhi	18:6a4db94011d3	16368
sahilmgandhi	18:6a4db94011d3	16369	#define GPIO_DINOFF_DINOFF10_Pos (26) /!< GPIO DINOFF: DINOFF10 Position /
sahilmgandhi	18:6a4db94011d3	16370	#define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) /!< GPIO DINOFF: DINOFF10 Mask /
sahilmgandhi	18:6a4db94011d3	16371
sahilmgandhi	18:6a4db94011d3	16372	#define GPIO_DINOFF_DINOFF11_Pos (27) /!< GPIO DINOFF: DINOFF11 Position /
sahilmgandhi	18:6a4db94011d3	16373	#define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) /!< GPIO DINOFF: DINOFF11 Mask /
sahilmgandhi	18:6a4db94011d3	16374
sahilmgandhi	18:6a4db94011d3	16375	#define GPIO_DINOFF_DINOFF12_Pos (28) /!< GPIO DINOFF: DINOFF12 Position /
sahilmgandhi	18:6a4db94011d3	16376	#define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) /!< GPIO DINOFF: DINOFF12 Mask /
sahilmgandhi	18:6a4db94011d3	16377
sahilmgandhi	18:6a4db94011d3	16378	#define GPIO_DINOFF_DINOFF13_Pos (29) /!< GPIO DINOFF: DINOFF13 Position /
sahilmgandhi	18:6a4db94011d3	16379	#define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) /!< GPIO DINOFF: DINOFF13 Mask /
sahilmgandhi	18:6a4db94011d3	16380
sahilmgandhi	18:6a4db94011d3	16381	#define GPIO_DINOFF_DINOFF14_Pos (30) /!< GPIO DINOFF: DINOFF14 Position /
sahilmgandhi	18:6a4db94011d3	16382	#define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) /!< GPIO DINOFF: DINOFF14 Mask /
sahilmgandhi	18:6a4db94011d3	16383
sahilmgandhi	18:6a4db94011d3	16384	#define GPIO_DINOFF_DINOFF15_Pos (31) /!< GPIO DINOFF: DINOFF15 Position /
sahilmgandhi	18:6a4db94011d3	16385	#define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) /!< GPIO DINOFF: DINOFF15 Mask /
sahilmgandhi	18:6a4db94011d3	16386
sahilmgandhi	18:6a4db94011d3	16387	#define GPIO_DOUT_DOUT0_Pos (0) /!< GPIO DOUT: DOUT0 Position /
sahilmgandhi	18:6a4db94011d3	16388	#define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) /!< GPIO DOUT: DOUT0 Mask /
sahilmgandhi	18:6a4db94011d3	16389
sahilmgandhi	18:6a4db94011d3	16390	#define GPIO_DOUT_DOUT1_Pos (1) /!< GPIO DOUT: DOUT1 Position /
sahilmgandhi	18:6a4db94011d3	16391	#define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) /!< GPIO DOUT: DOUT1 Mask /
sahilmgandhi	18:6a4db94011d3	16392
sahilmgandhi	18:6a4db94011d3	16393	#define GPIO_DOUT_DOUT2_Pos (2) /!< GPIO DOUT: DOUT2 Position /
sahilmgandhi	18:6a4db94011d3	16394	#define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) /!< GPIO DOUT: DOUT2 Mask /
sahilmgandhi	18:6a4db94011d3	16395
sahilmgandhi	18:6a4db94011d3	16396	#define GPIO_DOUT_DOUT3_Pos (3) /!< GPIO DOUT: DOUT3 Position /
sahilmgandhi	18:6a4db94011d3	16397	#define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) /!< GPIO DOUT: DOUT3 Mask /
sahilmgandhi	18:6a4db94011d3	16398
sahilmgandhi	18:6a4db94011d3	16399	#define GPIO_DOUT_DOUT4_Pos (4) /!< GPIO DOUT: DOUT4 Position /
sahilmgandhi	18:6a4db94011d3	16400	#define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) /!< GPIO DOUT: DOUT4 Mask /
sahilmgandhi	18:6a4db94011d3	16401
sahilmgandhi	18:6a4db94011d3	16402	#define GPIO_DOUT_DOUT5_Pos (5) /!< GPIO DOUT: DOUT5 Position /
sahilmgandhi	18:6a4db94011d3	16403	#define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) /!< GPIO DOUT: DOUT5 Mask /
sahilmgandhi	18:6a4db94011d3	16404
sahilmgandhi	18:6a4db94011d3	16405	#define GPIO_DOUT_DOUT6_Pos (6) /!< GPIO DOUT: DOUT6 Position /
sahilmgandhi	18:6a4db94011d3	16406	#define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) /!< GPIO DOUT: DOUT6 Mask /
sahilmgandhi	18:6a4db94011d3	16407
sahilmgandhi	18:6a4db94011d3	16408	#define GPIO_DOUT_DOUT7_Pos (7) /!< GPIO DOUT: DOUT7 Position /
sahilmgandhi	18:6a4db94011d3	16409	#define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) /!< GPIO DOUT: DOUT7 Mask /
sahilmgandhi	18:6a4db94011d3	16410
sahilmgandhi	18:6a4db94011d3	16411	#define GPIO_DOUT_DOUT8_Pos (8) /!< GPIO DOUT: DOUT8 Position /
sahilmgandhi	18:6a4db94011d3	16412	#define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) /!< GPIO DOUT: DOUT8 Mask /
sahilmgandhi	18:6a4db94011d3	16413
sahilmgandhi	18:6a4db94011d3	16414	#define GPIO_DOUT_DOUT9_Pos (9) /!< GPIO DOUT: DOUT9 Position /
sahilmgandhi	18:6a4db94011d3	16415	#define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) /!< GPIO DOUT: DOUT9 Mask /
sahilmgandhi	18:6a4db94011d3	16416
sahilmgandhi	18:6a4db94011d3	16417	#define GPIO_DOUT_DOUT10_Pos (10) /!< GPIO DOUT: DOUT10 Position /
sahilmgandhi	18:6a4db94011d3	16418	#define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) /!< GPIO DOUT: DOUT10 Mask /
sahilmgandhi	18:6a4db94011d3	16419
sahilmgandhi	18:6a4db94011d3	16420	#define GPIO_DOUT_DOUT11_Pos (11) /!< GPIO DOUT: DOUT11 Position /
sahilmgandhi	18:6a4db94011d3	16421	#define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) /!< GPIO DOUT: DOUT11 Mask /
sahilmgandhi	18:6a4db94011d3	16422
sahilmgandhi	18:6a4db94011d3	16423	#define GPIO_DOUT_DOUT12_Pos (12) /!< GPIO DOUT: DOUT12 Position /
sahilmgandhi	18:6a4db94011d3	16424	#define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) /!< GPIO DOUT: DOUT12 Mask /
sahilmgandhi	18:6a4db94011d3	16425
sahilmgandhi	18:6a4db94011d3	16426	#define GPIO_DOUT_DOUT13_Pos (13) /!< GPIO DOUT: DOUT13 Position /
sahilmgandhi	18:6a4db94011d3	16427	#define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) /!< GPIO DOUT: DOUT13 Mask /
sahilmgandhi	18:6a4db94011d3	16428
sahilmgandhi	18:6a4db94011d3	16429	#define GPIO_DOUT_DOUT14_Pos (14) /!< GPIO DOUT: DOUT14 Position /
sahilmgandhi	18:6a4db94011d3	16430	#define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) /!< GPIO DOUT: DOUT14 Mask /
sahilmgandhi	18:6a4db94011d3	16431
sahilmgandhi	18:6a4db94011d3	16432	#define GPIO_DOUT_DOUT15_Pos (15) /!< GPIO DOUT: DOUT15 Position /
sahilmgandhi	18:6a4db94011d3	16433	#define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) /!< GPIO DOUT: DOUT15 Mask /
sahilmgandhi	18:6a4db94011d3	16434
sahilmgandhi	18:6a4db94011d3	16435	#define GPIO_DATMSK_DATMSK0_Pos (0) /!< GPIO DATMSK: DATMSK0 Position /
sahilmgandhi	18:6a4db94011d3	16436	#define GPIO_DATMSK_DATMSK0_Msk (0x1ul << GPIO_DATMSK_DATMSK0_Pos) /!< GPIO DATMSK: DATMSK0 Mask /
sahilmgandhi	18:6a4db94011d3	16437
sahilmgandhi	18:6a4db94011d3	16438	#define GPIO_DATMSK_DATMSK1_Pos (1) /!< GPIO DATMSK: DATMSK1 Position /
sahilmgandhi	18:6a4db94011d3	16439	#define GPIO_DATMSK_DATMSK1_Msk (0x1ul << GPIO_DATMSK_DATMSK1_Pos) /!< GPIO DATMSK: DATMSK1 Mask /
sahilmgandhi	18:6a4db94011d3	16440
sahilmgandhi	18:6a4db94011d3	16441	#define GPIO_DATMSK_DATMSK2_Pos (2) /!< GPIO DATMSK: DATMSK2 Position /
sahilmgandhi	18:6a4db94011d3	16442	#define GPIO_DATMSK_DATMSK2_Msk (0x1ul << GPIO_DATMSK_DATMSK2_Pos) /!< GPIO DATMSK: DATMSK2 Mask /
sahilmgandhi	18:6a4db94011d3	16443
sahilmgandhi	18:6a4db94011d3	16444	#define GPIO_DATMSK_DATMSK3_Pos (3) /!< GPIO DATMSK: DATMSK3 Position /
sahilmgandhi	18:6a4db94011d3	16445	#define GPIO_DATMSK_DATMSK3_Msk (0x1ul << GPIO_DATMSK_DATMSK3_Pos) /!< GPIO DATMSK: DATMSK3 Mask /
sahilmgandhi	18:6a4db94011d3	16446
sahilmgandhi	18:6a4db94011d3	16447	#define GPIO_DATMSK_DATMSK4_Pos (4) /!< GPIO DATMSK: DATMSK4 Position /
sahilmgandhi	18:6a4db94011d3	16448	#define GPIO_DATMSK_DATMSK4_Msk (0x1ul << GPIO_DATMSK_DATMSK4_Pos) /!< GPIO DATMSK: DATMSK4 Mask /
sahilmgandhi	18:6a4db94011d3	16449
sahilmgandhi	18:6a4db94011d3	16450	#define GPIO_DATMSK_DATMSK5_Pos (5) /!< GPIO DATMSK: DATMSK5 Position /
sahilmgandhi	18:6a4db94011d3	16451	#define GPIO_DATMSK_DATMSK5_Msk (0x1ul << GPIO_DATMSK_DATMSK5_Pos) /!< GPIO DATMSK: DATMSK5 Mask /
sahilmgandhi	18:6a4db94011d3	16452
sahilmgandhi	18:6a4db94011d3	16453	#define GPIO_DATMSK_DATMSK6_Pos (6) /!< GPIO DATMSK: DATMSK6 Position /
sahilmgandhi	18:6a4db94011d3	16454	#define GPIO_DATMSK_DATMSK6_Msk (0x1ul << GPIO_DATMSK_DATMSK6_Pos) /!< GPIO DATMSK: DATMSK6 Mask /
sahilmgandhi	18:6a4db94011d3	16455
sahilmgandhi	18:6a4db94011d3	16456	#define GPIO_DATMSK_DATMSK7_Pos (7) /!< GPIO DATMSK: DATMSK7 Position /
sahilmgandhi	18:6a4db94011d3	16457	#define GPIO_DATMSK_DATMSK7_Msk (0x1ul << GPIO_DATMSK_DATMSK7_Pos) /!< GPIO DATMSK: DATMSK7 Mask /
sahilmgandhi	18:6a4db94011d3	16458
sahilmgandhi	18:6a4db94011d3	16459	#define GPIO_DATMSK_DATMSK8_Pos (8) /!< GPIO DATMSK: DATMSK8 Position /
sahilmgandhi	18:6a4db94011d3	16460	#define GPIO_DATMSK_DATMSK8_Msk (0x1ul << GPIO_DATMSK_DATMSK8_Pos) /!< GPIO DATMSK: DATMSK8 Mask /
sahilmgandhi	18:6a4db94011d3	16461
sahilmgandhi	18:6a4db94011d3	16462	#define GPIO_DATMSK_DATMSK9_Pos (9) /!< GPIO DATMSK: DATMSK9 Position /
sahilmgandhi	18:6a4db94011d3	16463	#define GPIO_DATMSK_DATMSK9_Msk (0x1ul << GPIO_DATMSK_DATMSK9_Pos) /!< GPIO DATMSK: DATMSK9 Mask /
sahilmgandhi	18:6a4db94011d3	16464
sahilmgandhi	18:6a4db94011d3	16465	#define GPIO_DATMSK_DATMSK10_Pos (10) /!< GPIO DATMSK: DATMSK10 Position /
sahilmgandhi	18:6a4db94011d3	16466	#define GPIO_DATMSK_DATMSK10_Msk (0x1ul << GPIO_DATMSK_DATMSK10_Pos) /!< GPIO DATMSK: DATMSK10 Mask /
sahilmgandhi	18:6a4db94011d3	16467
sahilmgandhi	18:6a4db94011d3	16468	#define GPIO_DATMSK_DATMSK11_Pos (11) /!< GPIO DATMSK: DATMSK11 Position /
sahilmgandhi	18:6a4db94011d3	16469	#define GPIO_DATMSK_DATMSK11_Msk (0x1ul << GPIO_DATMSK_DATMSK11_Pos) /!< GPIO DATMSK: DATMSK11 Mask /
sahilmgandhi	18:6a4db94011d3	16470
sahilmgandhi	18:6a4db94011d3	16471	#define GPIO_DATMSK_DATMSK12_Pos (12) /!< GPIO DATMSK: DATMSK12 Position /
sahilmgandhi	18:6a4db94011d3	16472	#define GPIO_DATMSK_DATMSK12_Msk (0x1ul << GPIO_DATMSK_DATMSK12_Pos) /!< GPIO DATMSK: DATMSK12 Mask /
sahilmgandhi	18:6a4db94011d3	16473
sahilmgandhi	18:6a4db94011d3	16474	#define GPIO_DATMSK_DATMSK13_Pos (13) /!< GPIO DATMSK: DATMSK13 Position /
sahilmgandhi	18:6a4db94011d3	16475	#define GPIO_DATMSK_DATMSK13_Msk (0x1ul << GPIO_DATMSK_DATMSK13_Pos) /!< GPIO DATMSK: DATMSK13 Mask /
sahilmgandhi	18:6a4db94011d3	16476
sahilmgandhi	18:6a4db94011d3	16477	#define GPIO_DATMSK_DATMSK14_Pos (14) /!< GPIO DATMSK: DATMSK14 Position /
sahilmgandhi	18:6a4db94011d3	16478	#define GPIO_DATMSK_DATMSK14_Msk (0x1ul << GPIO_DATMSK_DATMSK14_Pos) /!< GPIO DATMSK: DATMSK14 Mask /
sahilmgandhi	18:6a4db94011d3	16479
sahilmgandhi	18:6a4db94011d3	16480	#define GPIO_DATMSK_DATMSK15_Pos (15) /!< GPIO DATMSK: DATMSK15 Position /
sahilmgandhi	18:6a4db94011d3	16481	#define GPIO_DATMSK_DATMSK15_Msk (0x1ul << GPIO_DATMSK_DATMSK15_Pos) /!< GPIO DATMSK: DATMSK15 Mask /
sahilmgandhi	18:6a4db94011d3	16482
sahilmgandhi	18:6a4db94011d3	16483	#define GPIO_PIN_PIN0_Pos (0) /!< GPIO PIN: PIN0 Position /
sahilmgandhi	18:6a4db94011d3	16484	#define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) /!< GPIO PIN: PIN0 Mask /
sahilmgandhi	18:6a4db94011d3	16485
sahilmgandhi	18:6a4db94011d3	16486	#define GPIO_PIN_PIN1_Pos (1) /!< GPIO PIN: PIN1 Position /
sahilmgandhi	18:6a4db94011d3	16487	#define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) /!< GPIO PIN: PIN1 Mask /
sahilmgandhi	18:6a4db94011d3	16488
sahilmgandhi	18:6a4db94011d3	16489	#define GPIO_PIN_PIN2_Pos (2) /!< GPIO PIN: PIN2 Position /
sahilmgandhi	18:6a4db94011d3	16490	#define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) /!< GPIO PIN: PIN2 Mask /
sahilmgandhi	18:6a4db94011d3	16491
sahilmgandhi	18:6a4db94011d3	16492	#define GPIO_PIN_PIN3_Pos (3) /!< GPIO PIN: PIN3 Position /
sahilmgandhi	18:6a4db94011d3	16493	#define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) /!< GPIO PIN: PIN3 Mask /
sahilmgandhi	18:6a4db94011d3	16494
sahilmgandhi	18:6a4db94011d3	16495	#define GPIO_PIN_PIN4_Pos (4) /!< GPIO PIN: PIN4 Position /
sahilmgandhi	18:6a4db94011d3	16496	#define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) /!< GPIO PIN: PIN4 Mask /
sahilmgandhi	18:6a4db94011d3	16497
sahilmgandhi	18:6a4db94011d3	16498	#define GPIO_PIN_PIN5_Pos (5) /!< GPIO PIN: PIN5 Position /
sahilmgandhi	18:6a4db94011d3	16499	#define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) /!< GPIO PIN: PIN5 Mask /
sahilmgandhi	18:6a4db94011d3	16500
sahilmgandhi	18:6a4db94011d3	16501	#define GPIO_PIN_PIN6_Pos (6) /!< GPIO PIN: PIN6 Position /
sahilmgandhi	18:6a4db94011d3	16502	#define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) /!< GPIO PIN: PIN6 Mask /
sahilmgandhi	18:6a4db94011d3	16503
sahilmgandhi	18:6a4db94011d3	16504	#define GPIO_PIN_PIN7_Pos (7) /!< GPIO PIN: PIN7 Position /
sahilmgandhi	18:6a4db94011d3	16505	#define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) /!< GPIO PIN: PIN7 Mask /
sahilmgandhi	18:6a4db94011d3	16506
sahilmgandhi	18:6a4db94011d3	16507	#define GPIO_PIN_PIN8_Pos (8) /!< GPIO PIN: PIN8 Position /
sahilmgandhi	18:6a4db94011d3	16508	#define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) /!< GPIO PIN: PIN8 Mask /
sahilmgandhi	18:6a4db94011d3	16509
sahilmgandhi	18:6a4db94011d3	16510	#define GPIO_PIN_PIN9_Pos (9) /!< GPIO PIN: PIN9 Position /
sahilmgandhi	18:6a4db94011d3	16511	#define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) /!< GPIO PIN: PIN9 Mask /
sahilmgandhi	18:6a4db94011d3	16512
sahilmgandhi	18:6a4db94011d3	16513	#define GPIO_PIN_PIN10_Pos (10) /!< GPIO PIN: PIN10 Position /
sahilmgandhi	18:6a4db94011d3	16514	#define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) /!< GPIO PIN: PIN10 Mask /
sahilmgandhi	18:6a4db94011d3	16515
sahilmgandhi	18:6a4db94011d3	16516	#define GPIO_PIN_PIN11_Pos (11) /!< GPIO PIN: PIN11 Position /
sahilmgandhi	18:6a4db94011d3	16517	#define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) /!< GPIO PIN: PIN11 Mask /
sahilmgandhi	18:6a4db94011d3	16518
sahilmgandhi	18:6a4db94011d3	16519	#define GPIO_PIN_PIN12_Pos (12) /!< GPIO PIN: PIN12 Position /
sahilmgandhi	18:6a4db94011d3	16520	#define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) /!< GPIO PIN: PIN12 Mask /
sahilmgandhi	18:6a4db94011d3	16521
sahilmgandhi	18:6a4db94011d3	16522	#define GPIO_PIN_PIN13_Pos (13) /!< GPIO PIN: PIN13 Position /
sahilmgandhi	18:6a4db94011d3	16523	#define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) /!< GPIO PIN: PIN13 Mask /
sahilmgandhi	18:6a4db94011d3	16524
sahilmgandhi	18:6a4db94011d3	16525	#define GPIO_PIN_PIN14_Pos (14) /!< GPIO PIN: PIN14 Position /
sahilmgandhi	18:6a4db94011d3	16526	#define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) /!< GPIO PIN: PIN14 Mask /
sahilmgandhi	18:6a4db94011d3	16527
sahilmgandhi	18:6a4db94011d3	16528	#define GPIO_PIN_PIN15_Pos (15) /!< GPIO PIN: PIN15 Position /
sahilmgandhi	18:6a4db94011d3	16529	#define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) /!< GPIO PIN: PIN15 Mask /
sahilmgandhi	18:6a4db94011d3	16530
sahilmgandhi	18:6a4db94011d3	16531	#define GPIO_DBEN_DBEN0_Pos (0) /!< GPIO DBEN: DBEN0 Position /
sahilmgandhi	18:6a4db94011d3	16532	#define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) /!< GPIO DBEN: DBEN0 Mask /
sahilmgandhi	18:6a4db94011d3	16533
sahilmgandhi	18:6a4db94011d3	16534	#define GPIO_DBEN_DBEN1_Pos (1) /!< GPIO DBEN: DBEN1 Position /
sahilmgandhi	18:6a4db94011d3	16535	#define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) /!< GPIO DBEN: DBEN1 Mask /
sahilmgandhi	18:6a4db94011d3	16536
sahilmgandhi	18:6a4db94011d3	16537	#define GPIO_DBEN_DBEN2_Pos (2) /!< GPIO DBEN: DBEN2 Position /
sahilmgandhi	18:6a4db94011d3	16538	#define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) /!< GPIO DBEN: DBEN2 Mask /
sahilmgandhi	18:6a4db94011d3	16539
sahilmgandhi	18:6a4db94011d3	16540	#define GPIO_DBEN_DBEN3_Pos (3) /!< GPIO DBEN: DBEN3 Position /
sahilmgandhi	18:6a4db94011d3	16541	#define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) /!< GPIO DBEN: DBEN3 Mask /
sahilmgandhi	18:6a4db94011d3	16542
sahilmgandhi	18:6a4db94011d3	16543	#define GPIO_DBEN_DBEN4_Pos (4) /!< GPIO DBEN: DBEN4 Position /
sahilmgandhi	18:6a4db94011d3	16544	#define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) /!< GPIO DBEN: DBEN4 Mask /
sahilmgandhi	18:6a4db94011d3	16545
sahilmgandhi	18:6a4db94011d3	16546	#define GPIO_DBEN_DBEN5_Pos (5) /!< GPIO DBEN: DBEN5 Position /
sahilmgandhi	18:6a4db94011d3	16547	#define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) /!< GPIO DBEN: DBEN5 Mask /
sahilmgandhi	18:6a4db94011d3	16548
sahilmgandhi	18:6a4db94011d3	16549	#define GPIO_DBEN_DBEN6_Pos (6) /!< GPIO DBEN: DBEN6 Position /
sahilmgandhi	18:6a4db94011d3	16550	#define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) /!< GPIO DBEN: DBEN6 Mask /
sahilmgandhi	18:6a4db94011d3	16551
sahilmgandhi	18:6a4db94011d3	16552	#define GPIO_DBEN_DBEN7_Pos (7) /!< GPIO DBEN: DBEN7 Position /
sahilmgandhi	18:6a4db94011d3	16553	#define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) /!< GPIO DBEN: DBEN7 Mask /
sahilmgandhi	18:6a4db94011d3	16554
sahilmgandhi	18:6a4db94011d3	16555	#define GPIO_DBEN_DBEN8_Pos (8) /!< GPIO DBEN: DBEN8 Position /
sahilmgandhi	18:6a4db94011d3	16556	#define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) /!< GPIO DBEN: DBEN8 Mask /
sahilmgandhi	18:6a4db94011d3	16557
sahilmgandhi	18:6a4db94011d3	16558	#define GPIO_DBEN_DBEN9_Pos (9) /!< GPIO DBEN: DBEN9 Position /
sahilmgandhi	18:6a4db94011d3	16559	#define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) /!< GPIO DBEN: DBEN9 Mask /
sahilmgandhi	18:6a4db94011d3	16560
sahilmgandhi	18:6a4db94011d3	16561	#define GPIO_DBEN_DBEN10_Pos (10) /!< GPIO DBEN: DBEN10 Position /
sahilmgandhi	18:6a4db94011d3	16562	#define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) /!< GPIO DBEN: DBEN10 Mask /
sahilmgandhi	18:6a4db94011d3	16563
sahilmgandhi	18:6a4db94011d3	16564	#define GPIO_DBEN_DBEN11_Pos (11) /!< GPIO DBEN: DBEN11 Position /
sahilmgandhi	18:6a4db94011d3	16565	#define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) /!< GPIO DBEN: DBEN11 Mask /
sahilmgandhi	18:6a4db94011d3	16566
sahilmgandhi	18:6a4db94011d3	16567	#define GPIO_DBEN_DBEN12_Pos (12) /!< GPIO DBEN: DBEN12 Position /
sahilmgandhi	18:6a4db94011d3	16568	#define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) /!< GPIO DBEN: DBEN12 Mask /
sahilmgandhi	18:6a4db94011d3	16569
sahilmgandhi	18:6a4db94011d3	16570	#define GPIO_DBEN_DBEN13_Pos (13) /!< GPIO DBEN: DBEN13 Position /
sahilmgandhi	18:6a4db94011d3	16571	#define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) /!< GPIO DBEN: DBEN13 Mask /
sahilmgandhi	18:6a4db94011d3	16572
sahilmgandhi	18:6a4db94011d3	16573	#define GPIO_DBEN_DBEN14_Pos (14) /!< GPIO DBEN: DBEN14 Position /
sahilmgandhi	18:6a4db94011d3	16574	#define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) /!< GPIO DBEN: DBEN14 Mask /
sahilmgandhi	18:6a4db94011d3	16575
sahilmgandhi	18:6a4db94011d3	16576	#define GPIO_DBEN_DBEN15_Pos (15) /!< GPIO DBEN: DBEN15 Position /
sahilmgandhi	18:6a4db94011d3	16577	#define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) /!< GPIO DBEN: DBEN15 Mask /
sahilmgandhi	18:6a4db94011d3	16578
sahilmgandhi	18:6a4db94011d3	16579	#define GPIO_INTTYPE_TYPE0_Pos (0) /!< GPIO INTTYPE: TYPE0 Position /
sahilmgandhi	18:6a4db94011d3	16580	#define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) /!< GPIO INTTYPE: TYPE0 Mask /
sahilmgandhi	18:6a4db94011d3	16581
sahilmgandhi	18:6a4db94011d3	16582	#define GPIO_INTTYPE_TYPE1_Pos (1) /!< GPIO INTTYPE: TYPE1 Position /
sahilmgandhi	18:6a4db94011d3	16583	#define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) /!< GPIO INTTYPE: TYPE1 Mask /
sahilmgandhi	18:6a4db94011d3	16584
sahilmgandhi	18:6a4db94011d3	16585	#define GPIO_INTTYPE_TYPE2_Pos (2) /!< GPIO INTTYPE: TYPE2 Position /
sahilmgandhi	18:6a4db94011d3	16586	#define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) /!< GPIO INTTYPE: TYPE2 Mask /
sahilmgandhi	18:6a4db94011d3	16587
sahilmgandhi	18:6a4db94011d3	16588	#define GPIO_INTTYPE_TYPE3_Pos (3) /!< GPIO INTTYPE: TYPE3 Position /
sahilmgandhi	18:6a4db94011d3	16589	#define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) /!< GPIO INTTYPE: TYPE3 Mask /
sahilmgandhi	18:6a4db94011d3	16590
sahilmgandhi	18:6a4db94011d3	16591	#define GPIO_INTTYPE_TYPE4_Pos (4) /!< GPIO INTTYPE: TYPE4 Position /
sahilmgandhi	18:6a4db94011d3	16592	#define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) /!< GPIO INTTYPE: TYPE4 Mask /
sahilmgandhi	18:6a4db94011d3	16593
sahilmgandhi	18:6a4db94011d3	16594	#define GPIO_INTTYPE_TYPE5_Pos (5) /!< GPIO INTTYPE: TYPE5 Position /
sahilmgandhi	18:6a4db94011d3	16595	#define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) /!< GPIO INTTYPE: TYPE5 Mask /
sahilmgandhi	18:6a4db94011d3	16596
sahilmgandhi	18:6a4db94011d3	16597	#define GPIO_INTTYPE_TYPE6_Pos (6) /!< GPIO INTTYPE: TYPE6 Position /
sahilmgandhi	18:6a4db94011d3	16598	#define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) /!< GPIO INTTYPE: TYPE6 Mask /
sahilmgandhi	18:6a4db94011d3	16599
sahilmgandhi	18:6a4db94011d3	16600	#define GPIO_INTTYPE_TYPE7_Pos (7) /!< GPIO INTTYPE: TYPE7 Position /
sahilmgandhi	18:6a4db94011d3	16601	#define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) /!< GPIO INTTYPE: TYPE7 Mask /
sahilmgandhi	18:6a4db94011d3	16602
sahilmgandhi	18:6a4db94011d3	16603	#define GPIO_INTTYPE_TYPE8_Pos (8) /!< GPIO INTTYPE: TYPE8 Position /
sahilmgandhi	18:6a4db94011d3	16604	#define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) /!< GPIO INTTYPE: TYPE8 Mask /
sahilmgandhi	18:6a4db94011d3	16605
sahilmgandhi	18:6a4db94011d3	16606	#define GPIO_INTTYPE_TYPE9_Pos (9) /!< GPIO INTTYPE: TYPE9 Position /
sahilmgandhi	18:6a4db94011d3	16607	#define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) /!< GPIO INTTYPE: TYPE9 Mask /
sahilmgandhi	18:6a4db94011d3	16608
sahilmgandhi	18:6a4db94011d3	16609	#define GPIO_INTTYPE_TYPE10_Pos (10) /!< GPIO INTTYPE: TYPE10 Position /
sahilmgandhi	18:6a4db94011d3	16610	#define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) /!< GPIO INTTYPE: TYPE10 Mask /
sahilmgandhi	18:6a4db94011d3	16611
sahilmgandhi	18:6a4db94011d3	16612	#define GPIO_INTTYPE_TYPE11_Pos (11) /!< GPIO INTTYPE: TYPE11 Position /
sahilmgandhi	18:6a4db94011d3	16613	#define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) /!< GPIO INTTYPE: TYPE11 Mask /
sahilmgandhi	18:6a4db94011d3	16614
sahilmgandhi	18:6a4db94011d3	16615	#define GPIO_INTTYPE_TYPE12_Pos (12) /!< GPIO INTTYPE: TYPE12 Position /
sahilmgandhi	18:6a4db94011d3	16616	#define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) /!< GPIO INTTYPE: TYPE12 Mask /
sahilmgandhi	18:6a4db94011d3	16617
sahilmgandhi	18:6a4db94011d3	16618	#define GPIO_INTTYPE_TYPE13_Pos (13) /!< GPIO INTTYPE: TYPE13 Position /
sahilmgandhi	18:6a4db94011d3	16619	#define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) /!< GPIO INTTYPE: TYPE13 Mask /
sahilmgandhi	18:6a4db94011d3	16620
sahilmgandhi	18:6a4db94011d3	16621	#define GPIO_INTTYPE_TYPE14_Pos (14) /!< GPIO INTTYPE: TYPE14 Position /
sahilmgandhi	18:6a4db94011d3	16622	#define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) /!< GPIO INTTYPE: TYPE14 Mask /
sahilmgandhi	18:6a4db94011d3	16623
sahilmgandhi	18:6a4db94011d3	16624	#define GPIO_INTTYPE_TYPE15_Pos (15) /!< GPIO INTTYPE: TYPE15 Position /
sahilmgandhi	18:6a4db94011d3	16625	#define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) /!< GPIO INTTYPE: TYPE15 Mask /
sahilmgandhi	18:6a4db94011d3	16626
sahilmgandhi	18:6a4db94011d3	16627	#define GPIO_INTEN_FLIEN0_Pos (0) /!< GPIO INTEN: FLIEN0 Position /
sahilmgandhi	18:6a4db94011d3	16628	#define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) /!< GPIO INTEN: FLIEN0 Mask /
sahilmgandhi	18:6a4db94011d3	16629
sahilmgandhi	18:6a4db94011d3	16630	#define GPIO_INTEN_FLIEN1_Pos (1) /!< GPIO INTEN: FLIEN1 Position /
sahilmgandhi	18:6a4db94011d3	16631	#define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) /!< GPIO INTEN: FLIEN1 Mask /
sahilmgandhi	18:6a4db94011d3	16632
sahilmgandhi	18:6a4db94011d3	16633	#define GPIO_INTEN_FLIEN2_Pos (2) /!< GPIO INTEN: FLIEN2 Position /
sahilmgandhi	18:6a4db94011d3	16634	#define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) /!< GPIO INTEN: FLIEN2 Mask /
sahilmgandhi	18:6a4db94011d3	16635
sahilmgandhi	18:6a4db94011d3	16636	#define GPIO_INTEN_FLIEN3_Pos (3) /!< GPIO INTEN: FLIEN3 Position /
sahilmgandhi	18:6a4db94011d3	16637	#define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) /!< GPIO INTEN: FLIEN3 Mask /
sahilmgandhi	18:6a4db94011d3	16638
sahilmgandhi	18:6a4db94011d3	16639	#define GPIO_INTEN_FLIEN4_Pos (4) /!< GPIO INTEN: FLIEN4 Position /
sahilmgandhi	18:6a4db94011d3	16640	#define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) /!< GPIO INTEN: FLIEN4 Mask /
sahilmgandhi	18:6a4db94011d3	16641
sahilmgandhi	18:6a4db94011d3	16642	#define GPIO_INTEN_FLIEN5_Pos (5) /!< GPIO INTEN: FLIEN5 Position /
sahilmgandhi	18:6a4db94011d3	16643	#define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) /!< GPIO INTEN: FLIEN5 Mask /
sahilmgandhi	18:6a4db94011d3	16644
sahilmgandhi	18:6a4db94011d3	16645	#define GPIO_INTEN_FLIEN6_Pos (6) /!< GPIO INTEN: FLIEN6 Position /
sahilmgandhi	18:6a4db94011d3	16646	#define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) /!< GPIO INTEN: FLIEN6 Mask /
sahilmgandhi	18:6a4db94011d3	16647
sahilmgandhi	18:6a4db94011d3	16648	#define GPIO_INTEN_FLIEN7_Pos (7) /!< GPIO INTEN: FLIEN7 Position /
sahilmgandhi	18:6a4db94011d3	16649	#define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) /!< GPIO INTEN: FLIEN7 Mask /
sahilmgandhi	18:6a4db94011d3	16650
sahilmgandhi	18:6a4db94011d3	16651	#define GPIO_INTEN_FLIEN8_Pos (8) /!< GPIO INTEN: FLIEN8 Position /
sahilmgandhi	18:6a4db94011d3	16652	#define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) /!< GPIO INTEN: FLIEN8 Mask /
sahilmgandhi	18:6a4db94011d3	16653
sahilmgandhi	18:6a4db94011d3	16654	#define GPIO_INTEN_FLIEN9_Pos (9) /!< GPIO INTEN: FLIEN9 Position /
sahilmgandhi	18:6a4db94011d3	16655	#define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) /!< GPIO INTEN: FLIEN9 Mask /
sahilmgandhi	18:6a4db94011d3	16656
sahilmgandhi	18:6a4db94011d3	16657	#define GPIO_INTEN_FLIEN10_Pos (10) /!< GPIO INTEN: FLIEN10 Position /
sahilmgandhi	18:6a4db94011d3	16658	#define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) /!< GPIO INTEN: FLIEN10 Mask /
sahilmgandhi	18:6a4db94011d3	16659
sahilmgandhi	18:6a4db94011d3	16660	#define GPIO_INTEN_FLIEN11_Pos (11) /!< GPIO INTEN: FLIEN11 Position /
sahilmgandhi	18:6a4db94011d3	16661	#define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) /!< GPIO INTEN: FLIEN11 Mask /
sahilmgandhi	18:6a4db94011d3	16662
sahilmgandhi	18:6a4db94011d3	16663	#define GPIO_INTEN_FLIEN12_Pos (12) /!< GPIO INTEN: FLIEN12 Position /
sahilmgandhi	18:6a4db94011d3	16664	#define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) /!< GPIO INTEN: FLIEN12 Mask /
sahilmgandhi	18:6a4db94011d3	16665
sahilmgandhi	18:6a4db94011d3	16666	#define GPIO_INTEN_FLIEN13_Pos (13) /!< GPIO INTEN: FLIEN13 Position /
sahilmgandhi	18:6a4db94011d3	16667	#define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) /!< GPIO INTEN: FLIEN13 Mask /
sahilmgandhi	18:6a4db94011d3	16668
sahilmgandhi	18:6a4db94011d3	16669	#define GPIO_INTEN_FLIEN14_Pos (14) /!< GPIO INTEN: FLIEN14 Position /
sahilmgandhi	18:6a4db94011d3	16670	#define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) /!< GPIO INTEN: FLIEN14 Mask /
sahilmgandhi	18:6a4db94011d3	16671
sahilmgandhi	18:6a4db94011d3	16672	#define GPIO_INTEN_FLIEN15_Pos (15) /!< GPIO INTEN: FLIEN15 Position /
sahilmgandhi	18:6a4db94011d3	16673	#define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) /!< GPIO INTEN: FLIEN15 Mask /
sahilmgandhi	18:6a4db94011d3	16674
sahilmgandhi	18:6a4db94011d3	16675	#define GPIO_INTEN_RHIEN0_Pos (16) /!< GPIO INTEN: RHIEN0 Position /
sahilmgandhi	18:6a4db94011d3	16676	#define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) /!< GPIO INTEN: RHIEN0 Mask /
sahilmgandhi	18:6a4db94011d3	16677
sahilmgandhi	18:6a4db94011d3	16678	#define GPIO_INTEN_RHIEN1_Pos (17) /!< GPIO INTEN: RHIEN1 Position /
sahilmgandhi	18:6a4db94011d3	16679	#define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) /!< GPIO INTEN: RHIEN1 Mask /
sahilmgandhi	18:6a4db94011d3	16680
sahilmgandhi	18:6a4db94011d3	16681	#define GPIO_INTEN_RHIEN2_Pos (18) /!< GPIO INTEN: RHIEN2 Position /
sahilmgandhi	18:6a4db94011d3	16682	#define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) /!< GPIO INTEN: RHIEN2 Mask /
sahilmgandhi	18:6a4db94011d3	16683
sahilmgandhi	18:6a4db94011d3	16684	#define GPIO_INTEN_RHIEN3_Pos (19) /!< GPIO INTEN: RHIEN3 Position /
sahilmgandhi	18:6a4db94011d3	16685	#define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) /!< GPIO INTEN: RHIEN3 Mask /
sahilmgandhi	18:6a4db94011d3	16686
sahilmgandhi	18:6a4db94011d3	16687	#define GPIO_INTEN_RHIEN4_Pos (20) /!< GPIO INTEN: RHIEN4 Position /
sahilmgandhi	18:6a4db94011d3	16688	#define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) /!< GPIO INTEN: RHIEN4 Mask /
sahilmgandhi	18:6a4db94011d3	16689
sahilmgandhi	18:6a4db94011d3	16690	#define GPIO_INTEN_RHIEN5_Pos (21) /!< GPIO INTEN: RHIEN5 Position /
sahilmgandhi	18:6a4db94011d3	16691	#define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) /!< GPIO INTEN: RHIEN5 Mask /
sahilmgandhi	18:6a4db94011d3	16692
sahilmgandhi	18:6a4db94011d3	16693	#define GPIO_INTEN_RHIEN6_Pos (22) /!< GPIO INTEN: RHIEN6 Position /
sahilmgandhi	18:6a4db94011d3	16694	#define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) /!< GPIO INTEN: RHIEN6 Mask /
sahilmgandhi	18:6a4db94011d3	16695
sahilmgandhi	18:6a4db94011d3	16696	#define GPIO_INTEN_RHIEN7_Pos (23) /!< GPIO INTEN: RHIEN7 Position /
sahilmgandhi	18:6a4db94011d3	16697	#define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) /!< GPIO INTEN: RHIEN7 Mask /
sahilmgandhi	18:6a4db94011d3	16698
sahilmgandhi	18:6a4db94011d3	16699	#define GPIO_INTEN_RHIEN8_Pos (24) /!< GPIO INTEN: RHIEN8 Position /
sahilmgandhi	18:6a4db94011d3	16700	#define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) /!< GPIO INTEN: RHIEN8 Mask /
sahilmgandhi	18:6a4db94011d3	16701
sahilmgandhi	18:6a4db94011d3	16702	#define GPIO_INTEN_RHIEN9_Pos (25) /!< GPIO INTEN: RHIEN9 Position /
sahilmgandhi	18:6a4db94011d3	16703	#define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) /!< GPIO INTEN: RHIEN9 Mask /
sahilmgandhi	18:6a4db94011d3	16704
sahilmgandhi	18:6a4db94011d3	16705	#define GPIO_INTEN_RHIEN10_Pos (26) /!< GPIO INTEN: RHIEN10 Position /
sahilmgandhi	18:6a4db94011d3	16706	#define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) /!< GPIO INTEN: RHIEN10 Mask /
sahilmgandhi	18:6a4db94011d3	16707
sahilmgandhi	18:6a4db94011d3	16708	#define GPIO_INTEN_RHIEN11_Pos (27) /!< GPIO INTEN: RHIEN11 Position /
sahilmgandhi	18:6a4db94011d3	16709	#define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) /!< GPIO INTEN: RHIEN11 Mask /
sahilmgandhi	18:6a4db94011d3	16710
sahilmgandhi	18:6a4db94011d3	16711	#define GPIO_INTEN_RHIEN12_Pos (28) /!< GPIO INTEN: RHIEN12 Position /
sahilmgandhi	18:6a4db94011d3	16712	#define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) /!< GPIO INTEN: RHIEN12 Mask /
sahilmgandhi	18:6a4db94011d3	16713
sahilmgandhi	18:6a4db94011d3	16714	#define GPIO_INTEN_RHIEN13_Pos (29) /!< GPIO INTEN: RHIEN13 Position /
sahilmgandhi	18:6a4db94011d3	16715	#define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) /!< GPIO INTEN: RHIEN13 Mask /
sahilmgandhi	18:6a4db94011d3	16716
sahilmgandhi	18:6a4db94011d3	16717	#define GPIO_INTEN_RHIEN14_Pos (30) /!< GPIO INTEN: RHIEN14 Position /
sahilmgandhi	18:6a4db94011d3	16718	#define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) /!< GPIO INTEN: RHIEN14 Mask /
sahilmgandhi	18:6a4db94011d3	16719
sahilmgandhi	18:6a4db94011d3	16720	#define GPIO_INTEN_RHIEN15_Pos (31) /!< GPIO INTEN: RHIEN15 Position /
sahilmgandhi	18:6a4db94011d3	16721	#define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) /!< GPIO INTEN: RHIEN15 Mask /
sahilmgandhi	18:6a4db94011d3	16722
sahilmgandhi	18:6a4db94011d3	16723	#define GPIO_INTSRC_INTSRC0_Pos (0) /!< GPIO INTSRC: INTSRC0 Position /
sahilmgandhi	18:6a4db94011d3	16724	#define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) /!< GPIO INTSRC: INTSRC0 Mask /
sahilmgandhi	18:6a4db94011d3	16725
sahilmgandhi	18:6a4db94011d3	16726	#define GPIO_INTSRC_INTSRC1_Pos (1) /!< GPIO INTSRC: INTSRC1 Position /
sahilmgandhi	18:6a4db94011d3	16727	#define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) /!< GPIO INTSRC: INTSRC1 Mask /
sahilmgandhi	18:6a4db94011d3	16728
sahilmgandhi	18:6a4db94011d3	16729	#define GPIO_INTSRC_INTSRC2_Pos (2) /!< GPIO INTSRC: INTSRC2 Position /
sahilmgandhi	18:6a4db94011d3	16730	#define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) /!< GPIO INTSRC: INTSRC2 Mask /
sahilmgandhi	18:6a4db94011d3	16731
sahilmgandhi	18:6a4db94011d3	16732	#define GPIO_INTSRC_INTSRC3_Pos (3) /!< GPIO INTSRC: INTSRC3 Position /
sahilmgandhi	18:6a4db94011d3	16733	#define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) /!< GPIO INTSRC: INTSRC3 Mask /
sahilmgandhi	18:6a4db94011d3	16734
sahilmgandhi	18:6a4db94011d3	16735	#define GPIO_INTSRC_INTSRC4_Pos (4) /!< GPIO INTSRC: INTSRC4 Position /
sahilmgandhi	18:6a4db94011d3	16736	#define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) /!< GPIO INTSRC: INTSRC4 Mask /
sahilmgandhi	18:6a4db94011d3	16737
sahilmgandhi	18:6a4db94011d3	16738	#define GPIO_INTSRC_INTSRC5_Pos (5) /!< GPIO INTSRC: INTSRC5 Position /
sahilmgandhi	18:6a4db94011d3	16739	#define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) /!< GPIO INTSRC: INTSRC5 Mask /
sahilmgandhi	18:6a4db94011d3	16740
sahilmgandhi	18:6a4db94011d3	16741	#define GPIO_INTSRC_INTSRC6_Pos (6) /!< GPIO INTSRC: INTSRC6 Position /
sahilmgandhi	18:6a4db94011d3	16742	#define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) /!< GPIO INTSRC: INTSRC6 Mask /
sahilmgandhi	18:6a4db94011d3	16743
sahilmgandhi	18:6a4db94011d3	16744	#define GPIO_INTSRC_INTSRC7_Pos (7) /!< GPIO INTSRC: INTSRC7 Position /
sahilmgandhi	18:6a4db94011d3	16745	#define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) /!< GPIO INTSRC: INTSRC7 Mask /
sahilmgandhi	18:6a4db94011d3	16746
sahilmgandhi	18:6a4db94011d3	16747	#define GPIO_INTSRC_INTSRC8_Pos (8) /!< GPIO INTSRC: INTSRC8 Position /
sahilmgandhi	18:6a4db94011d3	16748	#define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) /!< GPIO INTSRC: INTSRC8 Mask /
sahilmgandhi	18:6a4db94011d3	16749
sahilmgandhi	18:6a4db94011d3	16750	#define GPIO_INTSRC_INTSRC9_Pos (9) /!< GPIO INTSRC: INTSRC9 Position /
sahilmgandhi	18:6a4db94011d3	16751	#define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) /!< GPIO INTSRC: INTSRC9 Mask /
sahilmgandhi	18:6a4db94011d3	16752
sahilmgandhi	18:6a4db94011d3	16753	#define GPIO_INTSRC_INTSRC10_Pos (10) /!< GPIO INTSRC: INTSRC10 Position /
sahilmgandhi	18:6a4db94011d3	16754	#define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) /!< GPIO INTSRC: INTSRC10 Mask /
sahilmgandhi	18:6a4db94011d3	16755
sahilmgandhi	18:6a4db94011d3	16756	#define GPIO_INTSRC_INTSRC11_Pos (11) /!< GPIO INTSRC: INTSRC11 Position /
sahilmgandhi	18:6a4db94011d3	16757	#define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) /!< GPIO INTSRC: INTSRC11 Mask /
sahilmgandhi	18:6a4db94011d3	16758
sahilmgandhi	18:6a4db94011d3	16759	#define GPIO_INTSRC_INTSRC12_Pos (12) /!< GPIO INTSRC: INTSRC12 Position /
sahilmgandhi	18:6a4db94011d3	16760	#define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) /!< GPIO INTSRC: INTSRC12 Mask /
sahilmgandhi	18:6a4db94011d3	16761
sahilmgandhi	18:6a4db94011d3	16762	#define GPIO_INTSRC_INTSRC13_Pos (13) /!< GPIO INTSRC: INTSRC13 Position /
sahilmgandhi	18:6a4db94011d3	16763	#define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) /!< GPIO INTSRC: INTSRC13 Mask /
sahilmgandhi	18:6a4db94011d3	16764
sahilmgandhi	18:6a4db94011d3	16765	#define GPIO_INTSRC_INTSRC14_Pos (14) /!< GPIO INTSRC: INTSRC14 Position /
sahilmgandhi	18:6a4db94011d3	16766	#define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) /!< GPIO INTSRC: INTSRC14 Mask /
sahilmgandhi	18:6a4db94011d3	16767
sahilmgandhi	18:6a4db94011d3	16768	#define GPIO_INTSRC_INTSRC15_Pos (15) /!< GPIO INTSRC: INTSRC15 Position /
sahilmgandhi	18:6a4db94011d3	16769	#define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) /!< GPIO INTSRC: INTSRC15 Mask /
sahilmgandhi	18:6a4db94011d3	16770
sahilmgandhi	18:6a4db94011d3	16771	#define GPIO_SMTEN_SMTEN0_Pos (0) /!< GPIO SMTEN: SMTEN0 Position /
sahilmgandhi	18:6a4db94011d3	16772	#define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) /!< GPIO SMTEN: SMTEN0 Mask /
sahilmgandhi	18:6a4db94011d3	16773
sahilmgandhi	18:6a4db94011d3	16774	#define GPIO_SMTEN_SMTEN1_Pos (1) /!< GPIO SMTEN: SMTEN1 Position /
sahilmgandhi	18:6a4db94011d3	16775	#define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) /!< GPIO SMTEN: SMTEN1 Mask /
sahilmgandhi	18:6a4db94011d3	16776
sahilmgandhi	18:6a4db94011d3	16777	#define GPIO_SMTEN_SMTEN2_Pos (2) /!< GPIO SMTEN: SMTEN2 Position /
sahilmgandhi	18:6a4db94011d3	16778	#define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) /!< GPIO SMTEN: SMTEN2 Mask /
sahilmgandhi	18:6a4db94011d3	16779
sahilmgandhi	18:6a4db94011d3	16780	#define GPIO_SMTEN_SMTEN3_Pos (3) /!< GPIO SMTEN: SMTEN3 Position /
sahilmgandhi	18:6a4db94011d3	16781	#define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) /!< GPIO SMTEN: SMTEN3 Mask /
sahilmgandhi	18:6a4db94011d3	16782
sahilmgandhi	18:6a4db94011d3	16783	#define GPIO_SMTEN_SMTEN4_Pos (4) /!< GPIO SMTEN: SMTEN4 Position /
sahilmgandhi	18:6a4db94011d3	16784	#define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) /!< GPIO SMTEN: SMTEN4 Mask /
sahilmgandhi	18:6a4db94011d3	16785
sahilmgandhi	18:6a4db94011d3	16786	#define GPIO_SMTEN_SMTEN5_Pos (5) /!< GPIO SMTEN: SMTEN5 Position /
sahilmgandhi	18:6a4db94011d3	16787	#define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) /!< GPIO SMTEN: SMTEN5 Mask /
sahilmgandhi	18:6a4db94011d3	16788
sahilmgandhi	18:6a4db94011d3	16789	#define GPIO_SMTEN_SMTEN6_Pos (6) /!< GPIO SMTEN: SMTEN6 Position /
sahilmgandhi	18:6a4db94011d3	16790	#define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) /!< GPIO SMTEN: SMTEN6 Mask /
sahilmgandhi	18:6a4db94011d3	16791
sahilmgandhi	18:6a4db94011d3	16792	#define GPIO_SMTEN_SMTEN7_Pos (7) /!< GPIO SMTEN: SMTEN7 Position /
sahilmgandhi	18:6a4db94011d3	16793	#define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) /!< GPIO SMTEN: SMTEN7 Mask /
sahilmgandhi	18:6a4db94011d3	16794
sahilmgandhi	18:6a4db94011d3	16795	#define GPIO_SMTEN_SMTEN8_Pos (8) /!< GPIO SMTEN: SMTEN8 Position /
sahilmgandhi	18:6a4db94011d3	16796	#define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) /!< GPIO SMTEN: SMTEN8 Mask /
sahilmgandhi	18:6a4db94011d3	16797
sahilmgandhi	18:6a4db94011d3	16798	#define GPIO_SMTEN_SMTEN9_Pos (9) /!< GPIO SMTEN: SMTEN9 Position /
sahilmgandhi	18:6a4db94011d3	16799	#define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) /!< GPIO SMTEN: SMTEN9 Mask /
sahilmgandhi	18:6a4db94011d3	16800
sahilmgandhi	18:6a4db94011d3	16801	#define GPIO_SMTEN_SMTEN10_Pos (10) /!< GPIO SMTEN: SMTEN10 Position /
sahilmgandhi	18:6a4db94011d3	16802	#define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) /!< GPIO SMTEN: SMTEN10 Mask /
sahilmgandhi	18:6a4db94011d3	16803
sahilmgandhi	18:6a4db94011d3	16804	#define GPIO_SMTEN_SMTEN11_Pos (11) /!< GPIO SMTEN: SMTEN11 Position /
sahilmgandhi	18:6a4db94011d3	16805	#define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) /!< GPIO SMTEN: SMTEN11 Mask /
sahilmgandhi	18:6a4db94011d3	16806
sahilmgandhi	18:6a4db94011d3	16807	#define GPIO_SMTEN_SMTEN12_Pos (12) /!< GPIO SMTEN: SMTEN12 Position /
sahilmgandhi	18:6a4db94011d3	16808	#define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) /!< GPIO SMTEN: SMTEN12 Mask /
sahilmgandhi	18:6a4db94011d3	16809
sahilmgandhi	18:6a4db94011d3	16810	#define GPIO_SMTEN_SMTEN13_Pos (13) /!< GPIO SMTEN: SMTEN13 Position /
sahilmgandhi	18:6a4db94011d3	16811	#define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) /!< GPIO SMTEN: SMTEN13 Mask /
sahilmgandhi	18:6a4db94011d3	16812
sahilmgandhi	18:6a4db94011d3	16813	#define GPIO_SMTEN_SMTEN14_Pos (14) /!< GPIO SMTEN: SMTEN14 Position /
sahilmgandhi	18:6a4db94011d3	16814	#define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) /!< GPIO SMTEN: SMTEN14 Mask /
sahilmgandhi	18:6a4db94011d3	16815
sahilmgandhi	18:6a4db94011d3	16816	#define GPIO_SMTEN_SMTEN15_Pos (15) /!< GPIO SMTEN: SMTEN15 Position /
sahilmgandhi	18:6a4db94011d3	16817	#define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) /!< GPIO SMTEN: SMTEN15 Mask /
sahilmgandhi	18:6a4db94011d3	16818
sahilmgandhi	18:6a4db94011d3	16819	#define GPIO_SLEWCTL_HSREN0_Pos (0) /!< GPIO SLEWCTL: HSREN0 Position /
sahilmgandhi	18:6a4db94011d3	16820	#define GPIO_SLEWCTL_HSREN0_Msk (0x1ul << GPIO_SLEWCTL_HSREN0_Pos) /!< GPIO SLEWCTL: HSREN0 Mask /
sahilmgandhi	18:6a4db94011d3	16821
sahilmgandhi	18:6a4db94011d3	16822	#define GPIO_SLEWCTL_HSREN1_Pos (1) /!< GPIO SLEWCTL: HSREN1 Position /
sahilmgandhi	18:6a4db94011d3	16823	#define GPIO_SLEWCTL_HSREN1_Msk (0x1ul << GPIO_SLEWCTL_HSREN1_Pos) /!< GPIO SLEWCTL: HSREN1 Mask /
sahilmgandhi	18:6a4db94011d3	16824
sahilmgandhi	18:6a4db94011d3	16825	#define GPIO_SLEWCTL_HSREN2_Pos (2) /!< GPIO SLEWCTL: HSREN2 Position /
sahilmgandhi	18:6a4db94011d3	16826	#define GPIO_SLEWCTL_HSREN2_Msk (0x1ul << GPIO_SLEWCTL_HSREN2_Pos) /!< GPIO SLEWCTL: HSREN2 Mask /
sahilmgandhi	18:6a4db94011d3	16827
sahilmgandhi	18:6a4db94011d3	16828	#define GPIO_SLEWCTL_HSREN3_Pos (3) /!< GPIO SLEWCTL: HSREN3 Position /
sahilmgandhi	18:6a4db94011d3	16829	#define GPIO_SLEWCTL_HSREN3_Msk (0x1ul << GPIO_SLEWCTL_HSREN3_Pos) /!< GPIO SLEWCTL: HSREN3 Mask /
sahilmgandhi	18:6a4db94011d3	16830
sahilmgandhi	18:6a4db94011d3	16831	#define GPIO_SLEWCTL_HSREN4_Pos (4) /!< GPIO SLEWCTL: HSREN4 Position /
sahilmgandhi	18:6a4db94011d3	16832	#define GPIO_SLEWCTL_HSREN4_Msk (0x1ul << GPIO_SLEWCTL_HSREN4_Pos) /!< GPIO SLEWCTL: HSREN4 Mask /
sahilmgandhi	18:6a4db94011d3	16833
sahilmgandhi	18:6a4db94011d3	16834	#define GPIO_SLEWCTL_HSREN5_Pos (5) /!< GPIO SLEWCTL: HSREN5 Position /
sahilmgandhi	18:6a4db94011d3	16835	#define GPIO_SLEWCTL_HSREN5_Msk (0x1ul << GPIO_SLEWCTL_HSREN5_Pos) /!< GPIO SLEWCTL: HSREN5 Mask /
sahilmgandhi	18:6a4db94011d3	16836
sahilmgandhi	18:6a4db94011d3	16837	#define GPIO_SLEWCTL_HSREN6_Pos (6) /!< GPIO SLEWCTL: HSREN6 Position /
sahilmgandhi	18:6a4db94011d3	16838	#define GPIO_SLEWCTL_HSREN6_Msk (0x1ul << GPIO_SLEWCTL_HSREN6_Pos) /!< GPIO SLEWCTL: HSREN6 Mask /
sahilmgandhi	18:6a4db94011d3	16839
sahilmgandhi	18:6a4db94011d3	16840	#define GPIO_SLEWCTL_HSREN7_Pos (7) /!< GPIO SLEWCTL: HSREN7 Position /
sahilmgandhi	18:6a4db94011d3	16841	#define GPIO_SLEWCTL_HSREN7_Msk (0x1ul << GPIO_SLEWCTL_HSREN7_Pos) /!< GPIO SLEWCTL: HSREN7 Mask /
sahilmgandhi	18:6a4db94011d3	16842
sahilmgandhi	18:6a4db94011d3	16843	#define GPIO_SLEWCTL_HSREN8_Pos (8) /!< GPIO SLEWCTL: HSREN8 Position /
sahilmgandhi	18:6a4db94011d3	16844	#define GPIO_SLEWCTL_HSREN8_Msk (0x1ul << GPIO_SLEWCTL_HSREN8_Pos) /!< GPIO SLEWCTL: HSREN8 Mask /
sahilmgandhi	18:6a4db94011d3	16845
sahilmgandhi	18:6a4db94011d3	16846	#define GPIO_SLEWCTL_HSREN9_Pos (9) /!< GPIO SLEWCTL: HSREN9 Position /
sahilmgandhi	18:6a4db94011d3	16847	#define GPIO_SLEWCTL_HSREN9_Msk (0x1ul << GPIO_SLEWCTL_HSREN9_Pos) /!< GPIO SLEWCTL: HSREN9 Mask /
sahilmgandhi	18:6a4db94011d3	16848
sahilmgandhi	18:6a4db94011d3	16849	#define GPIO_SLEWCTL_HSREN10_Pos (10) /!< GPIO SLEWCTL: HSREN10 Position /
sahilmgandhi	18:6a4db94011d3	16850	#define GPIO_SLEWCTL_HSREN10_Msk (0x1ul << GPIO_SLEWCTL_HSREN10_Pos) /!< GPIO SLEWCTL: HSREN10 Mask /
sahilmgandhi	18:6a4db94011d3	16851
sahilmgandhi	18:6a4db94011d3	16852	#define GPIO_SLEWCTL_HSREN11_Pos (11) /!< GPIO SLEWCTL: HSREN11 Position /
sahilmgandhi	18:6a4db94011d3	16853	#define GPIO_SLEWCTL_HSREN11_Msk (0x1ul << GPIO_SLEWCTL_HSREN11_Pos) /!< GPIO SLEWCTL: HSREN11 Mask /
sahilmgandhi	18:6a4db94011d3	16854
sahilmgandhi	18:6a4db94011d3	16855	#define GPIO_SLEWCTL_HSREN12_Pos (12) /!< GPIO SLEWCTL: HSREN12 Position /
sahilmgandhi	18:6a4db94011d3	16856	#define GPIO_SLEWCTL_HSREN12_Msk (0x1ul << GPIO_SLEWCTL_HSREN12_Pos) /!< GPIO SLEWCTL: HSREN12 Mask /
sahilmgandhi	18:6a4db94011d3	16857
sahilmgandhi	18:6a4db94011d3	16858	#define GPIO_SLEWCTL_HSREN13_Pos (13) /!< GPIO SLEWCTL: HSREN13 Position /
sahilmgandhi	18:6a4db94011d3	16859	#define GPIO_SLEWCTL_HSREN13_Msk (0x1ul << GPIO_SLEWCTL_HSREN13_Pos) /!< GPIO SLEWCTL: HSREN13 Mask /
sahilmgandhi	18:6a4db94011d3	16860
sahilmgandhi	18:6a4db94011d3	16861	#define GPIO_SLEWCTL_HSREN14_Pos (14) /!< GPIO SLEWCTL: HSREN14 Position /
sahilmgandhi	18:6a4db94011d3	16862	#define GPIO_SLEWCTL_HSREN14_Msk (0x1ul << GPIO_SLEWCTL_HSREN14_Pos) /!< GPIO SLEWCTL: HSREN14 Mask /
sahilmgandhi	18:6a4db94011d3	16863
sahilmgandhi	18:6a4db94011d3	16864	#define GPIO_SLEWCTL_HSREN15_Pos (15) /!< GPIO SLEWCTL: HSREN15 Position /
sahilmgandhi	18:6a4db94011d3	16865	#define GPIO_SLEWCTL_HSREN15_Msk (0x1ul << GPIO_SLEWCTL_HSREN15_Pos) /!< GPIO SLEWCTL: HSREN15 Mask /
sahilmgandhi	18:6a4db94011d3	16866
sahilmgandhi	18:6a4db94011d3	16867	#define GPIO_DBCTL_DBCLKSEL_Pos (0) /!< GPIO DBCTL: DBCLKSEL Position /
sahilmgandhi	18:6a4db94011d3	16868	#define GPIO_DBCTL_DBCLKSEL_Msk (0xful << GPIO_DBCTL_DBCLKSEL_Pos) /!< GPIO DBCTL: DBCLKSEL Mask /
sahilmgandhi	18:6a4db94011d3	16869
sahilmgandhi	18:6a4db94011d3	16870	#define GPIO_DBCTL_DBCLKSRC_Pos (4) /!< GPIO DBCTL: DBCLKSRC Position /
sahilmgandhi	18:6a4db94011d3	16871	#define GPIO_DBCTL_DBCLKSRC_Msk (0x1ul << GPIO_DBCTL_DBCLKSRC_Pos) /!< GPIO DBCTL: DBCLKSRC Mask /
sahilmgandhi	18:6a4db94011d3	16872
sahilmgandhi	18:6a4db94011d3	16873	#define GPIO_DBCTL_ICLKON_Pos (5) /!< GPIO DBCTL: ICLKON Position /
sahilmgandhi	18:6a4db94011d3	16874	#define GPIO_DBCTL_ICLKON_Msk (0x1ul << GPIO_DBCTL_ICLKON_Pos) /!< GPIO DBCTL: ICLKON Mask /
sahilmgandhi	18:6a4db94011d3	16875
sahilmgandhi	18:6a4db94011d3	16876	/*@}/ /* GPIO_CONST */
sahilmgandhi	18:6a4db94011d3	16877	/*@}/ /* end of GPIO register group */
sahilmgandhi	18:6a4db94011d3	16878
sahilmgandhi	18:6a4db94011d3	16879
sahilmgandhi	18:6a4db94011d3	16880	/---------------------- Inter-IC Bus Controller -------------------------/
sahilmgandhi	18:6a4db94011d3	16881	/**
sahilmgandhi	18:6a4db94011d3	16882	@addtogroup I2C Inter-IC Bus Controller(I2C)
sahilmgandhi	18:6a4db94011d3	16883	Memory Mapped Structure for I2C Controller
sahilmgandhi	18:6a4db94011d3	16884	@{ */
sahilmgandhi	18:6a4db94011d3	16885
sahilmgandhi	18:6a4db94011d3	16886	typedef struct {
sahilmgandhi	18:6a4db94011d3	16887
sahilmgandhi	18:6a4db94011d3	16888
sahilmgandhi	18:6a4db94011d3	16889	/**
sahilmgandhi	18:6a4db94011d3	16890	* CTL
sahilmgandhi	18:6a4db94011d3	16891	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	16892	* Offset: 0x00 I2C Control Register
sahilmgandhi	18:6a4db94011d3	16893	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	16894	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	16895	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	16896	* \|[2] \|AA \|Assert Acknowledge Control
sahilmgandhi	18:6a4db94011d3	16897	* \| \| \|When AA =1 prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter.
sahilmgandhi	18:6a4db94011d3	16898	* \| \| \|When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.
sahilmgandhi	18:6a4db94011d3	16899	* \|[3] \|SI \|I2C Interrupt Flag
sahilmgandhi	18:6a4db94011d3	16900	* \| \| \|When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested.
sahilmgandhi	18:6a4db94011d3	16901	* \| \| \|SI must be cleared by software.
sahilmgandhi	18:6a4db94011d3	16902	* \| \| \|Clear SI by writing 1 to this bit.
sahilmgandhi	18:6a4db94011d3	16903	* \|[4] \|STO \|I2C STOP Control
sahilmgandhi	18:6a4db94011d3	16904	* \| \| \|In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically.
sahilmgandhi	18:6a4db94011d3	16905	* \| \| \|In a slave mode, setting STO resets I2C hardware to the defined "not addressed" slave mode.
sahilmgandhi	18:6a4db94011d3	16906	* \| \| \|This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
sahilmgandhi	18:6a4db94011d3	16907	* \|[5] \|STA \|I2C START Control
sahilmgandhi	18:6a4db94011d3	16908	* \| \| \|Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
sahilmgandhi	18:6a4db94011d3	16909	* \|[6] \|I2CEN \|I2C Controller Enable Control
sahilmgandhi	18:6a4db94011d3	16910	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	16911	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	16912	* \| \| \|Set to enable I2C serial function controller.
sahilmgandhi	18:6a4db94011d3	16913	* \| \| \|When ENS1=1 the I2C serial function enables.
sahilmgandhi	18:6a4db94011d3	16914	* \| \| \|The multi-function pin function of SDA and SCL must set to I2C function first.
sahilmgandhi	18:6a4db94011d3	16915	* \|[7] \|INTEN \|I2C Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	16916	* \| \| \|0 = I2C interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	16917	* \| \| \|1 = I2C interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	16918	*/
sahilmgandhi	18:6a4db94011d3	16919	__IO uint32_t CTL;
sahilmgandhi	18:6a4db94011d3	16920
sahilmgandhi	18:6a4db94011d3	16921	/**
sahilmgandhi	18:6a4db94011d3	16922	* ADDR0
sahilmgandhi	18:6a4db94011d3	16923	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	16924	* Offset: 0x04 I2C Slave Address Register0
sahilmgandhi	18:6a4db94011d3	16925	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	16926	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	16927	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	16928	* \|[0] \|GC \|General Call Function
sahilmgandhi	18:6a4db94011d3	16929	* \| \| \|0 = General Call Function Disabled.
sahilmgandhi	18:6a4db94011d3	16930	* \| \| \|1 = General Call Function Enabled.
sahilmgandhi	18:6a4db94011d3	16931	* \|[1:7] \|ADDR \|I2C Address Bits
sahilmgandhi	18:6a4db94011d3	16932	* \| \| \|The content of this register is irrelevant when I2C is in Master mode.
sahilmgandhi	18:6a4db94011d3	16933	* \| \| \|In the slave mode, the seven most significant bits must be loaded with the chip's own address.
sahilmgandhi	18:6a4db94011d3	16934	* \| \| \|The I2C hardware will react if either of the address is matched.
sahilmgandhi	18:6a4db94011d3	16935	*/
sahilmgandhi	18:6a4db94011d3	16936	__IO uint32_t ADDR0;
sahilmgandhi	18:6a4db94011d3	16937
sahilmgandhi	18:6a4db94011d3	16938	/**
sahilmgandhi	18:6a4db94011d3	16939	* DAT
sahilmgandhi	18:6a4db94011d3	16940	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	16941	* Offset: 0x08 I2C Data Register
sahilmgandhi	18:6a4db94011d3	16942	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	16943	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	16944	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	16945	* \|[0:7] \|DAT \|I2C Data Bits
sahilmgandhi	18:6a4db94011d3	16946	* \| \| \|Bit [7:0] is located with the 8-bit transferred data of I2C serial port.
sahilmgandhi	18:6a4db94011d3	16947	*/
sahilmgandhi	18:6a4db94011d3	16948	__IO uint32_t DAT;
sahilmgandhi	18:6a4db94011d3	16949
sahilmgandhi	18:6a4db94011d3	16950	/**
sahilmgandhi	18:6a4db94011d3	16951	* STATUS
sahilmgandhi	18:6a4db94011d3	16952	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	16953	* Offset: 0x0C I2C Status Register
sahilmgandhi	18:6a4db94011d3	16954	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	16955	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	16956	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	16957	* \|[0:7] \|STATUS \|I2C Status Bits
sahilmgandhi	18:6a4db94011d3	16958	* \| \| \|The status register of I2C:
sahilmgandhi	18:6a4db94011d3	16959	* \| \| \|The three least significant bits are always 0.
sahilmgandhi	18:6a4db94011d3	16960	* \| \| \|The five most significant bits contain the status code.
sahilmgandhi	18:6a4db94011d3	16961	* \| \| \|Refer to section 6.15.5.4 for detail description.
sahilmgandhi	18:6a4db94011d3	16962	*/
sahilmgandhi	18:6a4db94011d3	16963	__I uint32_t STATUS;
sahilmgandhi	18:6a4db94011d3	16964
sahilmgandhi	18:6a4db94011d3	16965	/**
sahilmgandhi	18:6a4db94011d3	16966	* CLKDIV
sahilmgandhi	18:6a4db94011d3	16967	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	16968	* Offset: 0x10 I2C Clock Divided Register
sahilmgandhi	18:6a4db94011d3	16969	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	16970	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	16971	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	16972	* \|[0:7] \|DIVIDER \|I2C Clock Divided Bits
sahilmgandhi	18:6a4db94011d3	16973	* \| \| \|The I2C clock rate bits: Data Baud Rate of I2C = (system clock) / (4x (I2CLK+1)).
sahilmgandhi	18:6a4db94011d3	16974	* \| \| \|Note: The minimum value of I2CLK is 4.
sahilmgandhi	18:6a4db94011d3	16975	*/
sahilmgandhi	18:6a4db94011d3	16976	__IO uint32_t CLKDIV;
sahilmgandhi	18:6a4db94011d3	16977
sahilmgandhi	18:6a4db94011d3	16978	/**
sahilmgandhi	18:6a4db94011d3	16979	* TOCTL
sahilmgandhi	18:6a4db94011d3	16980	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	16981	* Offset: 0x14 I2C Time-out Control Register
sahilmgandhi	18:6a4db94011d3	16982	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	16983	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	16984	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	16985	* \|[0] \|TOIF \|Time-Out Flag
sahilmgandhi	18:6a4db94011d3	16986	* \| \| \|This bit is set by H/W when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (EI (I2CON[7])) is set to 1.
sahilmgandhi	18:6a4db94011d3	16987	* \| \| \|Note: Write 1 to clear this bit.
sahilmgandhi	18:6a4db94011d3	16988	* \|[1] \|TOCDIV4 \|Time-Out Counter Input Clock Divided By 4
sahilmgandhi	18:6a4db94011d3	16989	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	16990	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	16991	* \| \| \|When Enabled, The time-out period is extend 4 times.
sahilmgandhi	18:6a4db94011d3	16992	* \|[2] \|TOCEN \|Time-Out Counter Enable Control
sahilmgandhi	18:6a4db94011d3	16993	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	16994	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	16995	* \| \| \|When Enabled, the 14-bit time-out counter will start counting when SI (I2CON[3]) is clear.
sahilmgandhi	18:6a4db94011d3	16996	* \| \| \|Setting flag SI to high will reset counter and re-start up counting after SI is cleared.
sahilmgandhi	18:6a4db94011d3	16997	*/
sahilmgandhi	18:6a4db94011d3	16998	__IO uint32_t TOCTL;
sahilmgandhi	18:6a4db94011d3	16999
sahilmgandhi	18:6a4db94011d3	17000	/**
sahilmgandhi	18:6a4db94011d3	17001	* ADDR1
sahilmgandhi	18:6a4db94011d3	17002	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	17003	* Offset: 0x18 I2C Slave Address Register1
sahilmgandhi	18:6a4db94011d3	17004	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	17005	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	17006	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	17007	* \|[0] \|GC \|General Call Function
sahilmgandhi	18:6a4db94011d3	17008	* \| \| \|0 = General Call Function Disabled.
sahilmgandhi	18:6a4db94011d3	17009	* \| \| \|1 = General Call Function Enabled.
sahilmgandhi	18:6a4db94011d3	17010	* \|[1:7] \|ADDR \|I2C Address Bits
sahilmgandhi	18:6a4db94011d3	17011	* \| \| \|The content of this register is irrelevant when I2C is in Master mode.
sahilmgandhi	18:6a4db94011d3	17012	* \| \| \|In the slave mode, the seven most significant bits must be loaded with the chip's own address.
sahilmgandhi	18:6a4db94011d3	17013	* \| \| \|The I2C hardware will react if either of the address is matched.
sahilmgandhi	18:6a4db94011d3	17014	*/
sahilmgandhi	18:6a4db94011d3	17015	__IO uint32_t ADDR1;
sahilmgandhi	18:6a4db94011d3	17016
sahilmgandhi	18:6a4db94011d3	17017	/**
sahilmgandhi	18:6a4db94011d3	17018	* ADDR2
sahilmgandhi	18:6a4db94011d3	17019	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	17020	* Offset: 0x1C I2C Slave Address Register2
sahilmgandhi	18:6a4db94011d3	17021	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	17022	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	17023	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	17024	* \|[0] \|GC \|General Call Function
sahilmgandhi	18:6a4db94011d3	17025	* \| \| \|0 = General Call Function Disabled.
sahilmgandhi	18:6a4db94011d3	17026	* \| \| \|1 = General Call Function Enabled.
sahilmgandhi	18:6a4db94011d3	17027	* \|[1:7] \|ADDR \|I2C Address Bits
sahilmgandhi	18:6a4db94011d3	17028	* \| \| \|The content of this register is irrelevant when I2C is in Master mode.
sahilmgandhi	18:6a4db94011d3	17029	* \| \| \|In the slave mode, the seven most significant bits must be loaded with the chip's own address.
sahilmgandhi	18:6a4db94011d3	17030	* \| \| \|The I2C hardware will react if either of the address is matched.
sahilmgandhi	18:6a4db94011d3	17031	*/
sahilmgandhi	18:6a4db94011d3	17032	__IO uint32_t ADDR2;
sahilmgandhi	18:6a4db94011d3	17033
sahilmgandhi	18:6a4db94011d3	17034	/**
sahilmgandhi	18:6a4db94011d3	17035	* ADDR3
sahilmgandhi	18:6a4db94011d3	17036	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	17037	* Offset: 0x20 I2C Slave Address Register3
sahilmgandhi	18:6a4db94011d3	17038	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	17039	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	17040	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	17041	* \|[0] \|GC \|General Call Function
sahilmgandhi	18:6a4db94011d3	17042	* \| \| \|0 = General Call Function Disabled.
sahilmgandhi	18:6a4db94011d3	17043	* \| \| \|1 = General Call Function Enabled.
sahilmgandhi	18:6a4db94011d3	17044	* \|[1:7] \|ADDR \|I2C Address Bits
sahilmgandhi	18:6a4db94011d3	17045	* \| \| \|The content of this register is irrelevant when I2C is in Master mode.
sahilmgandhi	18:6a4db94011d3	17046	* \| \| \|In the slave mode, the seven most significant bits must be loaded with the chip's own address.
sahilmgandhi	18:6a4db94011d3	17047	* \| \| \|The I2C hardware will react if either of the address is matched.
sahilmgandhi	18:6a4db94011d3	17048	*/
sahilmgandhi	18:6a4db94011d3	17049	__IO uint32_t ADDR3;
sahilmgandhi	18:6a4db94011d3	17050
sahilmgandhi	18:6a4db94011d3	17051	/**
sahilmgandhi	18:6a4db94011d3	17052	* ADDRMSK0
sahilmgandhi	18:6a4db94011d3	17053	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	17054	* Offset: 0x24 I2C Slave Address Mask Register0
sahilmgandhi	18:6a4db94011d3	17055	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	17056	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	17057	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	17058	* \|[1:7] \|ADDRMSK \|I2C Address Mask Bits
sahilmgandhi	18:6a4db94011d3	17059	* \| \| \|0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
sahilmgandhi	18:6a4db94011d3	17060	* \| \| \|1 = Mask Enabled (the received corresponding address bit is don't care.).
sahilmgandhi	18:6a4db94011d3	17061	* \| \| \|I2C bus controllers support multiple address recognition with four address mask register.
sahilmgandhi	18:6a4db94011d3	17062	* \| \| \|When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
sahilmgandhi	18:6a4db94011d3	17063	* \| \| \|If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
sahilmgandhi	18:6a4db94011d3	17064	*/
sahilmgandhi	18:6a4db94011d3	17065	__IO uint32_t ADDRMSK0;
sahilmgandhi	18:6a4db94011d3	17066
sahilmgandhi	18:6a4db94011d3	17067	/**
sahilmgandhi	18:6a4db94011d3	17068	* ADDRMSK1
sahilmgandhi	18:6a4db94011d3	17069	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	17070	* Offset: 0x28 I2C Slave Address Mask Register1
sahilmgandhi	18:6a4db94011d3	17071	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	17072	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	17073	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	17074	* \|[1:7] \|ADDRMSK \|I2C Address Mask Bits
sahilmgandhi	18:6a4db94011d3	17075	* \| \| \|0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
sahilmgandhi	18:6a4db94011d3	17076	* \| \| \|1 = Mask Enabled (the received corresponding address bit is don't care.).
sahilmgandhi	18:6a4db94011d3	17077	* \| \| \|I2C bus controllers support multiple address recognition with four address mask register.
sahilmgandhi	18:6a4db94011d3	17078	* \| \| \|When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
sahilmgandhi	18:6a4db94011d3	17079	* \| \| \|If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
sahilmgandhi	18:6a4db94011d3	17080	*/
sahilmgandhi	18:6a4db94011d3	17081	__IO uint32_t ADDRMSK1;
sahilmgandhi	18:6a4db94011d3	17082
sahilmgandhi	18:6a4db94011d3	17083	/**
sahilmgandhi	18:6a4db94011d3	17084	* ADDRMSK2
sahilmgandhi	18:6a4db94011d3	17085	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	17086	* Offset: 0x2C I2C Slave Address Mask Register2
sahilmgandhi	18:6a4db94011d3	17087	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	17088	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	17089	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	17090	* \|[1:7] \|ADDRMSK \|I2C Address Mask Bits
sahilmgandhi	18:6a4db94011d3	17091	* \| \| \|0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
sahilmgandhi	18:6a4db94011d3	17092	* \| \| \|1 = Mask Enabled (the received corresponding address bit is don't care.).
sahilmgandhi	18:6a4db94011d3	17093	* \| \| \|I2C bus controllers support multiple address recognition with four address mask register.
sahilmgandhi	18:6a4db94011d3	17094	* \| \| \|When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
sahilmgandhi	18:6a4db94011d3	17095	* \| \| \|If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
sahilmgandhi	18:6a4db94011d3	17096	*/
sahilmgandhi	18:6a4db94011d3	17097	__IO uint32_t ADDRMSK2;
sahilmgandhi	18:6a4db94011d3	17098
sahilmgandhi	18:6a4db94011d3	17099	/**
sahilmgandhi	18:6a4db94011d3	17100	* ADDRMSK3
sahilmgandhi	18:6a4db94011d3	17101	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	17102	* Offset: 0x30 I2C Slave Address Mask Register3
sahilmgandhi	18:6a4db94011d3	17103	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	17104	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	17105	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	17106	* \|[1:7] \|ADDRMSK \|I2C Address Mask Bits
sahilmgandhi	18:6a4db94011d3	17107	* \| \| \|0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
sahilmgandhi	18:6a4db94011d3	17108	* \| \| \|1 = Mask Enabled (the received corresponding address bit is don't care.).
sahilmgandhi	18:6a4db94011d3	17109	* \| \| \|I2C bus controllers support multiple address recognition with four address mask register.
sahilmgandhi	18:6a4db94011d3	17110	* \| \| \|When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
sahilmgandhi	18:6a4db94011d3	17111	* \| \| \|If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
sahilmgandhi	18:6a4db94011d3	17112	*/
sahilmgandhi	18:6a4db94011d3	17113	__IO uint32_t ADDRMSK3;
sahilmgandhi	18:6a4db94011d3	17114	uint32_t RESERVE0[2];
sahilmgandhi	18:6a4db94011d3	17115
sahilmgandhi	18:6a4db94011d3	17116
sahilmgandhi	18:6a4db94011d3	17117	/**
sahilmgandhi	18:6a4db94011d3	17118	* WKCTL
sahilmgandhi	18:6a4db94011d3	17119	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	17120	* Offset: 0x3C I2C Wake-up Control Register
sahilmgandhi	18:6a4db94011d3	17121	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	17122	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	17123	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	17124	* \|[0] \|WKEN \|I2C Wake-Up Enable Control
sahilmgandhi	18:6a4db94011d3	17125	* \| \| \|0 = I2C wake-up function Disabled.
sahilmgandhi	18:6a4db94011d3	17126	* \| \| \|1 = I2C wake-up function Enabled.
sahilmgandhi	18:6a4db94011d3	17127	*/
sahilmgandhi	18:6a4db94011d3	17128	__IO uint32_t WKCTL;
sahilmgandhi	18:6a4db94011d3	17129
sahilmgandhi	18:6a4db94011d3	17130	/**
sahilmgandhi	18:6a4db94011d3	17131	* WKSTS
sahilmgandhi	18:6a4db94011d3	17132	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	17133	* Offset: 0x40 I2C Wake-up Status Register
sahilmgandhi	18:6a4db94011d3	17134	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	17135	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	17136	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	17137	* \|[0] \|WKIF \|I2C Wake-Up Flag
sahilmgandhi	18:6a4db94011d3	17138	* \| \| \|0 = No wake up occurred.
sahilmgandhi	18:6a4db94011d3	17139	* \| \| \|1 = Wake up from Power-down mode.
sahilmgandhi	18:6a4db94011d3	17140	* \| \| \|Note: Software can write 1 to clear this bit.
sahilmgandhi	18:6a4db94011d3	17141	*/
sahilmgandhi	18:6a4db94011d3	17142	__IO uint32_t WKSTS;
sahilmgandhi	18:6a4db94011d3	17143
sahilmgandhi	18:6a4db94011d3	17144	} I2C_T;
sahilmgandhi	18:6a4db94011d3	17145
sahilmgandhi	18:6a4db94011d3	17146	/**
sahilmgandhi	18:6a4db94011d3	17147	@addtogroup I2C_CONST I2C Bit Field Definition
sahilmgandhi	18:6a4db94011d3	17148	Constant Definitions for I2C Controller
sahilmgandhi	18:6a4db94011d3	17149	@{ */
sahilmgandhi	18:6a4db94011d3	17150
sahilmgandhi	18:6a4db94011d3	17151	#define I2C_CTL_AA_Pos (2) /!< I2C CTL: AA Position /
sahilmgandhi	18:6a4db94011d3	17152	#define I2C_CTL_AA_Msk (0x1ul << I2C_CTL_AA_Pos) /!< I2C CTL: AA Mask /
sahilmgandhi	18:6a4db94011d3	17153
sahilmgandhi	18:6a4db94011d3	17154	#define I2C_CTL_SI_Pos (3) /!< I2C CTL: SI Position /
sahilmgandhi	18:6a4db94011d3	17155	#define I2C_CTL_SI_Msk (0x1ul << I2C_CTL_SI_Pos) /!< I2C CTL: SI Mask /
sahilmgandhi	18:6a4db94011d3	17156
sahilmgandhi	18:6a4db94011d3	17157	#define I2C_CTL_STO_Pos (4) /!< I2C CTL: STO Position /
sahilmgandhi	18:6a4db94011d3	17158	#define I2C_CTL_STO_Msk (0x1ul << I2C_CTL_STO_Pos) /!< I2C CTL: STO Mask /
sahilmgandhi	18:6a4db94011d3	17159
sahilmgandhi	18:6a4db94011d3	17160	#define I2C_CTL_STA_Pos (5) /!< I2C CTL: STA Position /
sahilmgandhi	18:6a4db94011d3	17161	#define I2C_CTL_STA_Msk (0x1ul << I2C_CTL_STA_Pos) /!< I2C CTL: STA Mask /
sahilmgandhi	18:6a4db94011d3	17162
sahilmgandhi	18:6a4db94011d3	17163	#define I2C_CTL_I2CEN_Pos (6) /!< I2C CTL: I2CEN Position /
sahilmgandhi	18:6a4db94011d3	17164	#define I2C_CTL_I2CEN_Msk (0x1ul << I2C_CTL_I2CEN_Pos) /!< I2C CTL: I2CEN Mask /
sahilmgandhi	18:6a4db94011d3	17165
sahilmgandhi	18:6a4db94011d3	17166	#define I2C_CTL_INTEN_Pos (7) /!< I2C CTL: INTEN Position /
sahilmgandhi	18:6a4db94011d3	17167	#define I2C_CTL_INTEN_Msk (0x1ul << I2C_CTL_INTEN_Pos) /!< I2C CTL: INTEN Mask /
sahilmgandhi	18:6a4db94011d3	17168
sahilmgandhi	18:6a4db94011d3	17169	#define I2C_ADDR0_GC_Pos (0) /!< I2C ADDR0: GC Position /
sahilmgandhi	18:6a4db94011d3	17170	#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) /!< I2C ADDR0: GC Mask /
sahilmgandhi	18:6a4db94011d3	17171
sahilmgandhi	18:6a4db94011d3	17172	#define I2C_ADDR0_ADDR_Pos (1) /!< I2C ADDR0: ADDR Position /
sahilmgandhi	18:6a4db94011d3	17173	#define I2C_ADDR0_ADDR_Msk (0x7ful << I2C_ADDR0_ADDR_Pos) /!< I2C ADDR0: ADDR Mask /
sahilmgandhi	18:6a4db94011d3	17174
sahilmgandhi	18:6a4db94011d3	17175	#define I2C_DAT_DAT_Pos (0) /!< I2C DAT: DAT Position /
sahilmgandhi	18:6a4db94011d3	17176	#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) /!< I2C DAT: DAT Mask /
sahilmgandhi	18:6a4db94011d3	17177
sahilmgandhi	18:6a4db94011d3	17178	#define I2C_STATUS_STATUS_Pos (0) /!< I2C STATUS: STATUS Position /
sahilmgandhi	18:6a4db94011d3	17179	#define I2C_STATUS_STATUS_Msk (0xfful << I2C_STATUS_STATUS_Pos) /!< I2C STATUS: STATUS Mask /
sahilmgandhi	18:6a4db94011d3	17180
sahilmgandhi	18:6a4db94011d3	17181	#define I2C_CLKDIV_DIVIDER_Pos (0) /!< I2C CLKDIV: DIVIDER Position /
sahilmgandhi	18:6a4db94011d3	17182	#define I2C_CLKDIV_DIVIDER_Msk (0xfful << I2C_CLKDIV_DIVIDER_Pos) /!< I2C CLKDIV: DIVIDER Mask /
sahilmgandhi	18:6a4db94011d3	17183
sahilmgandhi	18:6a4db94011d3	17184	#define I2C_TOCTL_TOIF_Pos (0) /!< I2C TOCTL: TOIF Position /
sahilmgandhi	18:6a4db94011d3	17185	#define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) /!< I2C TOCTL: TOIF Mask /
sahilmgandhi	18:6a4db94011d3	17186
sahilmgandhi	18:6a4db94011d3	17187	#define I2C_TOCTL_TOCDIV4_Pos (1) /!< I2C TOCTL: TOCDIV4 Position /
sahilmgandhi	18:6a4db94011d3	17188	#define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) /!< I2C TOCTL: TOCDIV4 Mask /
sahilmgandhi	18:6a4db94011d3	17189
sahilmgandhi	18:6a4db94011d3	17190	#define I2C_TOCTL_TOCEN_Pos (2) /!< I2C TOCTL: TOCEN Position /
sahilmgandhi	18:6a4db94011d3	17191	#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) /!< I2C TOCTL: TOCEN Mask /
sahilmgandhi	18:6a4db94011d3	17192
sahilmgandhi	18:6a4db94011d3	17193	#define I2C_ADDR1_GC_Pos (0) /!< I2C ADDR1: GC Position /
sahilmgandhi	18:6a4db94011d3	17194	#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) /!< I2C ADDR1: GC Mask /
sahilmgandhi	18:6a4db94011d3	17195
sahilmgandhi	18:6a4db94011d3	17196	#define I2C_ADDR1_ADDR_Pos (1) /!< I2C ADDR1: ADDR Position /
sahilmgandhi	18:6a4db94011d3	17197	#define I2C_ADDR1_ADDR_Msk (0x7ful << I2C_ADDR1_ADDR_Pos) /!< I2C ADDR1: ADDR Mask /
sahilmgandhi	18:6a4db94011d3	17198
sahilmgandhi	18:6a4db94011d3	17199	#define I2C_ADDR2_GC_Pos (0) /!< I2C ADDR2: GC Position /
sahilmgandhi	18:6a4db94011d3	17200	#define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) /!< I2C ADDR2: GC Mask /
sahilmgandhi	18:6a4db94011d3	17201
sahilmgandhi	18:6a4db94011d3	17202	#define I2C_ADDR2_ADDR_Pos (1) /!< I2C ADDR2: ADDR Position /
sahilmgandhi	18:6a4db94011d3	17203	#define I2C_ADDR2_ADDR_Msk (0x7ful << I2C_ADDR2_ADDR_Pos) /!< I2C ADDR2: ADDR Mask /
sahilmgandhi	18:6a4db94011d3	17204
sahilmgandhi	18:6a4db94011d3	17205	#define I2C_ADDR3_GC_Pos (0) /!< I2C ADDR3: GC Position /
sahilmgandhi	18:6a4db94011d3	17206	#define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) /!< I2C ADDR3: GC Mask /
sahilmgandhi	18:6a4db94011d3	17207
sahilmgandhi	18:6a4db94011d3	17208	#define I2C_ADDR3_ADDR_Pos (1) /!< I2C ADDR3: ADDR Position /
sahilmgandhi	18:6a4db94011d3	17209	#define I2C_ADDR3_ADDR_Msk (0x7ful << I2C_ADDR3_ADDR_Pos) /!< I2C ADDR3: ADDR Mask /
sahilmgandhi	18:6a4db94011d3	17210
sahilmgandhi	18:6a4db94011d3	17211	#define I2C_ADDRMSK0_ADDRMSK_Pos (1) /!< I2C ADDRMSK0: ADDRMSK Position /
sahilmgandhi	18:6a4db94011d3	17212	#define I2C_ADDRMSK0_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK0_ADDRMSK_Pos) /!< I2C ADDRMSK0: ADDRMSK Mask /
sahilmgandhi	18:6a4db94011d3	17213
sahilmgandhi	18:6a4db94011d3	17214	#define I2C_ADDRMSK1_ADDRMSK_Pos (1) /!< I2C ADDRMSK1: ADDRMSK Position /
sahilmgandhi	18:6a4db94011d3	17215	#define I2C_ADDRMSK1_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK1_ADDRMSK_Pos) /!< I2C ADDRMSK1: ADDRMSK Mask /
sahilmgandhi	18:6a4db94011d3	17216
sahilmgandhi	18:6a4db94011d3	17217	#define I2C_ADDRMSK2_ADDRMSK_Pos (1) /!< I2C ADDRMSK2: ADDRMSK Position /
sahilmgandhi	18:6a4db94011d3	17218	#define I2C_ADDRMSK2_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK2_ADDRMSK_Pos) /!< I2C ADDRMSK2: ADDRMSK Mask /
sahilmgandhi	18:6a4db94011d3	17219
sahilmgandhi	18:6a4db94011d3	17220	#define I2C_ADDRMSK3_ADDRMSK_Pos (1) /!< I2C ADDRMSK3: ADDRMSK Position /
sahilmgandhi	18:6a4db94011d3	17221	#define I2C_ADDRMSK3_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK3_ADDRMSK_Pos) /!< I2C ADDRMSK3: ADDRMSK Mask /
sahilmgandhi	18:6a4db94011d3	17222
sahilmgandhi	18:6a4db94011d3	17223	#define I2C_WKCTL_WKEN_Pos (0) /!< I2C WKCTL: WKEN Position /
sahilmgandhi	18:6a4db94011d3	17224	#define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) /!< I2C WKCTL: WKEN Mask /
sahilmgandhi	18:6a4db94011d3	17225
sahilmgandhi	18:6a4db94011d3	17226	#define I2C_WKSTS_WKIF_Pos (0) /!< I2C WKSTS: WKIF Position /
sahilmgandhi	18:6a4db94011d3	17227	#define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /!< I2C WKSTS: WKIF Mask /
sahilmgandhi	18:6a4db94011d3	17228
sahilmgandhi	18:6a4db94011d3	17229	/*@}/ /* I2C_CONST */
sahilmgandhi	18:6a4db94011d3	17230	/*@}/ /* end of I2C register group */
sahilmgandhi	18:6a4db94011d3	17231
sahilmgandhi	18:6a4db94011d3	17232
sahilmgandhi	18:6a4db94011d3	17233	/---------------------- I2S Interface Controller -------------------------/
sahilmgandhi	18:6a4db94011d3	17234	/**
sahilmgandhi	18:6a4db94011d3	17235	@addtogroup I2S I2S Interface Controller(I2S)
sahilmgandhi	18:6a4db94011d3	17236	Memory Mapped Structure for I2S Controller
sahilmgandhi	18:6a4db94011d3	17237	@{ */
sahilmgandhi	18:6a4db94011d3	17238
sahilmgandhi	18:6a4db94011d3	17239	typedef struct {
sahilmgandhi	18:6a4db94011d3	17240
sahilmgandhi	18:6a4db94011d3	17241
sahilmgandhi	18:6a4db94011d3	17242	/**
sahilmgandhi	18:6a4db94011d3	17243	* CTL
sahilmgandhi	18:6a4db94011d3	17244	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	17245	* Offset: 0x00 I2S Control Register
sahilmgandhi	18:6a4db94011d3	17246	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	17247	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	17248	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	17249	* \|[0] \|I2SEN \|I2S Controller Enable Control
sahilmgandhi	18:6a4db94011d3	17250	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	17251	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	17252	* \|[1] \|TXEN \|Transmit Enable Control
sahilmgandhi	18:6a4db94011d3	17253	* \| \| \|0 = Data transmission Disabled.
sahilmgandhi	18:6a4db94011d3	17254	* \| \| \|1 = Data transmission Enabled.
sahilmgandhi	18:6a4db94011d3	17255	* \|[2] \|RXEN \|Receive Enable Control
sahilmgandhi	18:6a4db94011d3	17256	* \| \| \|0 = Data receiving Disabled.
sahilmgandhi	18:6a4db94011d3	17257	* \| \| \|1 = Data receiving Enabled.
sahilmgandhi	18:6a4db94011d3	17258	* \|[3] \|MUTE \|Transmit Mute Enable Control
sahilmgandhi	18:6a4db94011d3	17259	* \| \| \|0 = Transmit data is shifted from buffer.
sahilmgandhi	18:6a4db94011d3	17260	* \| \| \|1 = Transmit zero data.
sahilmgandhi	18:6a4db94011d3	17261	* \|[4:5] \|WDWIDTH \|Word Width
sahilmgandhi	18:6a4db94011d3	17262	* \| \| \|00 = data is 8-bit.
sahilmgandhi	18:6a4db94011d3	17263	* \| \| \|01 = data is 16-bit.
sahilmgandhi	18:6a4db94011d3	17264	* \| \| \|10 = data is 24-bit.
sahilmgandhi	18:6a4db94011d3	17265	* \| \| \|11 = data is 32-bit.
sahilmgandhi	18:6a4db94011d3	17266	* \|[6] \|MONO \|Monaural Data Control
sahilmgandhi	18:6a4db94011d3	17267	* \| \| \|0 = Data is stereo format.
sahilmgandhi	18:6a4db94011d3	17268	* \| \| \|1 = Data is monaural format.
sahilmgandhi	18:6a4db94011d3	17269	* \| \| \|Note: when chip records data, only right channel data will be saved if monaural format is select.
sahilmgandhi	18:6a4db94011d3	17270	* \|[7] \|FORMAT \|Data Format Selection
sahilmgandhi	18:6a4db94011d3	17271	* \| \| \|If PCM=0,
sahilmgandhi	18:6a4db94011d3	17272	* \| \| \|0 = I2S data format.
sahilmgandhi	18:6a4db94011d3	17273	* \| \| \|1 = MSB justified data format.
sahilmgandhi	18:6a4db94011d3	17274	* \| \| \|If PCM=1,
sahilmgandhi	18:6a4db94011d3	17275	* \| \| \|0 = PCM mode A.
sahilmgandhi	18:6a4db94011d3	17276	* \| \| \|1 = PCM mode B.
sahilmgandhi	18:6a4db94011d3	17277	* \|[8] \|SLAVE \|Slave Mode Enable Control
sahilmgandhi	18:6a4db94011d3	17278	* \| \| \|0 = Master mode.
sahilmgandhi	18:6a4db94011d3	17279	* \| \| \|1 = Slave mode.
sahilmgandhi	18:6a4db94011d3	17280	* \| \| \|Note: I2S can operate as master or slave.
sahilmgandhi	18:6a4db94011d3	17281	* \| \| \|For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send bit clock from NuMicro(TM)
sahilmgandhi	18:6a4db94011d3	17282	* \| \| \|NUC442/NUC472 series to Audio CODEC chip.
sahilmgandhi	18:6a4db94011d3	17283	* \| \| \|In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip.
sahilmgandhi	18:6a4db94011d3	17284	* \|[9:11] \|TXTH \|Transmit FIFO Threshold Level
sahilmgandhi	18:6a4db94011d3	17285	* \| \| \|000 = 0 word data in transmit FIFO.
sahilmgandhi	18:6a4db94011d3	17286	* \| \| \|001 = 1 word data in transmit FIFO.
sahilmgandhi	18:6a4db94011d3	17287	* \| \| \|010 = 2 words data in transmit FIFO.
sahilmgandhi	18:6a4db94011d3	17288	* \| \| \|011 = 3 words data in transmit FIFO.
sahilmgandhi	18:6a4db94011d3	17289	* \| \| \|100 = 4 words data in transmit FIFO.
sahilmgandhi	18:6a4db94011d3	17290	* \| \| \|101 = 5 words data in transmit FIFO.
sahilmgandhi	18:6a4db94011d3	17291	* \| \| \|110 = 6 words data in transmit FIFO.
sahilmgandhi	18:6a4db94011d3	17292	* \| \| \|111 = 7 words data in transmit FIFO.
sahilmgandhi	18:6a4db94011d3	17293	* \| \| \|Note: If remain data word(s) in transmit FIFO is the same or less than threshold level then TXTHF flag is set.
sahilmgandhi	18:6a4db94011d3	17294	* \|[12:14] \|RXTH \|Receive FIFO Threshold Level
sahilmgandhi	18:6a4db94011d3	17295	* \| \| \|000 = 1 word data in receive FIFO.
sahilmgandhi	18:6a4db94011d3	17296	* \| \| \|001 = 2 word data in receive FIFO.
sahilmgandhi	18:6a4db94011d3	17297	* \| \| \|010 = 3 word data in receive FIFO.
sahilmgandhi	18:6a4db94011d3	17298	* \| \| \|011 = 4 word data in receive FIFO.
sahilmgandhi	18:6a4db94011d3	17299	* \| \| \|100 = 5 word data in receive FIFO.
sahilmgandhi	18:6a4db94011d3	17300	* \| \| \|101 = 6 word data in receive FIFO.
sahilmgandhi	18:6a4db94011d3	17301	* \| \| \|110 = 7 word data in receive FIFO.
sahilmgandhi	18:6a4db94011d3	17302	* \| \| \|111 = 8 word data in receive FIFO.
sahilmgandhi	18:6a4db94011d3	17303	* \| \| \|Note: When received data word(s) in buffer is equal to or higher than threshold level then RXTHF flag is set.
sahilmgandhi	18:6a4db94011d3	17304	* \|[15] \|MCLKEN \|Master Clock Enable Control
sahilmgandhi	18:6a4db94011d3	17305	* \| \| \|0 = Master clock Disabled.
sahilmgandhi	18:6a4db94011d3	17306	* \| \| \|1 = Master clock Enabled.
sahilmgandhi	18:6a4db94011d3	17307	* \| \| \|Note: If the external crystal clock in NuMicro(TM) NUC442/NUC472 series is frequency 2N256fs, software can program MCLK_DIV(I2S_CLK[5:0]) to get 256fs clock to audio codec chip.
sahilmgandhi	18:6a4db94011d3	17308	* \|[16] \|RZCEN \|Right Channel Zero-Cross Detection Enable Control
sahilmgandhi	18:6a4db94011d3	17309	* \| \| \|0 = Right channel zero-cross detect Disabled.
sahilmgandhi	18:6a4db94011d3	17310	* \| \| \|1 = Right channel zero-cross detect Enabled.
sahilmgandhi	18:6a4db94011d3	17311	* \| \| \|Note1: If this bit is set to 1, when right channel data sign bit change or next shift data bits are all zero then RZCF(I2S_STATUS[22]) flag is set to 1.
sahilmgandhi	18:6a4db94011d3	17312	* \| \| \|Note2: If RZCF Flag is set to 1, the right channel will be mute.
sahilmgandhi	18:6a4db94011d3	17313	* \|[17] \|LZCEN \|Left Channel Zero-Cross Detect Enable Control
sahilmgandhi	18:6a4db94011d3	17314	* \| \| \|0 = Left channel zero-cross detect Disabled.
sahilmgandhi	18:6a4db94011d3	17315	* \| \| \|1 = Left channel zero-cross detect Enabled.
sahilmgandhi	18:6a4db94011d3	17316	* \| \| \|Note1: If this bit is set to 1, when left channel data sign bit change or next shift data bits are all zero then LZCF(I2S_STATUS[23]) flag is set to 1.
sahilmgandhi	18:6a4db94011d3	17317	* \| \| \|Note2: If LZCF Flag is set to 1, the left channel will be mute.
sahilmgandhi	18:6a4db94011d3	17318	* \|[18] \|TXCLR \|Clear Transmit FIFO
sahilmgandhi	18:6a4db94011d3	17319	* \| \| \|0 = No Effect.
sahilmgandhi	18:6a4db94011d3	17320	* \| \| \|1 = Clear TX FIFO.
sahilmgandhi	18:6a4db94011d3	17321	* \| \| \|Note1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT(I2S_STATUS[31:28]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed.
sahilmgandhi	18:6a4db94011d3	17322	* \| \| \|Note2: This bit is clear by hardware automatically, read it return zero.
sahilmgandhi	18:6a4db94011d3	17323	* \|[19] \|RXCLR \|Clear Receive FIFO
sahilmgandhi	18:6a4db94011d3	17324	* \| \| \|0 = No Effect.
sahilmgandhi	18:6a4db94011d3	17325	* \| \| \|1 = Clear RX FIFO.
sahilmgandhi	18:6a4db94011d3	17326	* \| \| \|Note1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS[27:24]) returns 0 and receive FIFO becomes empty.
sahilmgandhi	18:6a4db94011d3	17327	* \| \| \|Note2: This bit is cleared by hardware automatically, read it return zero.
sahilmgandhi	18:6a4db94011d3	17328	* \|[20] \|TXPDMAEN \|Transmit DMA Enable Control
sahilmgandhi	18:6a4db94011d3	17329	* \| \| \|0 = TX DMA Disabled.
sahilmgandhi	18:6a4db94011d3	17330	* \| \| \|1 = TX DMA Enabled.
sahilmgandhi	18:6a4db94011d3	17331	* \| \| \|Note: When TX DMA is enables, I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full.
sahilmgandhi	18:6a4db94011d3	17332	* \|[21] \|RXPDMAEN \|Receive DMA Enable Control
sahilmgandhi	18:6a4db94011d3	17333	* \| \| \|0 = RX DMA Disabled.
sahilmgandhi	18:6a4db94011d3	17334	* \| \| \|1 = RX DMA Enabled.
sahilmgandhi	18:6a4db94011d3	17335	* \| \| \|Note: When RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty.
sahilmgandhi	18:6a4db94011d3	17336	* \|[23] \|RXLCH \|Receive Left Channel Enable Control
sahilmgandhi	18:6a4db94011d3	17337	* \| \| \|0 = Receives right channel data when monaural format is selected.
sahilmgandhi	18:6a4db94011d3	17338	* \| \| \|1 = Receives left channel data when monaural format is selected.
sahilmgandhi	18:6a4db94011d3	17339	* \| \| \|Note: When monaural format is selected (MONO = 1), I2S will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1.
sahilmgandhi	18:6a4db94011d3	17340	* \|[24] \|PCMEN \|PCM Interface Enable Control
sahilmgandhi	18:6a4db94011d3	17341	* \| \| \|0 = I2S Interface.
sahilmgandhi	18:6a4db94011d3	17342	* \| \| \|1 = PCM Interface.
sahilmgandhi	18:6a4db94011d3	17343	*/
sahilmgandhi	18:6a4db94011d3	17344	__IO uint32_t CTL;
sahilmgandhi	18:6a4db94011d3	17345
sahilmgandhi	18:6a4db94011d3	17346	/**
sahilmgandhi	18:6a4db94011d3	17347	* CLKDIV
sahilmgandhi	18:6a4db94011d3	17348	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	17349	* Offset: 0x04 I2S Clock Divider Register
sahilmgandhi	18:6a4db94011d3	17350	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	17351	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	17352	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	17353	* \|[0:5] \|MCLKDIV \|Master Clock Divider
sahilmgandhi	18:6a4db94011d3	17354	* \| \| \|If chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip.
sahilmgandhi	18:6a4db94011d3	17355	* \| \| \|If MCLKDIV is set to 0, MCLK is the same as external clock input.
sahilmgandhi	18:6a4db94011d3	17356	* \| \| \|For example, sampling rate is 24 kHz and chip external crystal clock is 12.288 MHz, set MCLKDIV = 1.
sahilmgandhi	18:6a4db94011d3	17357	* \| \| \|F_MCLK = F_I2SCLK/(2x(MCLKDIV)) (When MCLKDIV is >= 1 ).
sahilmgandhi	18:6a4db94011d3	17358	* \| \| \|F_MCLK = F_I2SCLK (When MCLKDIV is set to 0 ).
sahilmgandhi	18:6a4db94011d3	17359	* \| \| \|Note: F_MCLK is the frequency of MCLK, and F_i2SCLK is the frequency of the I2S_CLK
sahilmgandhi	18:6a4db94011d3	17360	* \|[8:16] \|BCLKDIV \|Bit Clock Divider
sahilmgandhi	18:6a4db94011d3	17361	* \| \| \|If I2S operates in Master mode, bit clock is provided by the NuMicro(TM) NUC442/NUC472 series.
sahilmgandhi	18:6a4db94011d3	17362	* \| \| \|Software can program these bits to generate sampling rate clock frequency.
sahilmgandhi	18:6a4db94011d3	17363	* \| \| \|F_BCLK= F_I2SCLK / (2*(BCLKDIV + 1)).
sahilmgandhi	18:6a4db94011d3	17364	* \| \| \|Note: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK
sahilmgandhi	18:6a4db94011d3	17365	*/
sahilmgandhi	18:6a4db94011d3	17366	__IO uint32_t CLKDIV;
sahilmgandhi	18:6a4db94011d3	17367
sahilmgandhi	18:6a4db94011d3	17368	/**
sahilmgandhi	18:6a4db94011d3	17369	* IEN
sahilmgandhi	18:6a4db94011d3	17370	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	17371	* Offset: 0x08 I2S Interrupt Enable Register
sahilmgandhi	18:6a4db94011d3	17372	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	17373	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	17374	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	17375	* \|[0] \|RXUDIEN \|Receive FIFO Underflow Interrupt E Enable Control
sahilmgandhi	18:6a4db94011d3	17376	* \| \| \|0 = Interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	17377	* \| \| \|1 = Interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	17378	* \| \| \|Note: If software reads receive FIFO when it is empty then RXUDIF(I2S_STATUS[8]) flag is set to 1.
sahilmgandhi	18:6a4db94011d3	17379	* \|[1] \|RXOVIEN \|Receive FIFO Overflow Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	17380	* \| \| \|0 = Interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	17381	* \| \| \|1 = Interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	17382	* \| \| \|Note: Interrupt occurs if this bit is set to 1 and RXOVIEN(I2S_STATUS[9]) flag is set to 1
sahilmgandhi	18:6a4db94011d3	17383	* \|[2] \|RXTHIEN \|Receive FIFO Threshold Level Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	17384	* \| \| \|0 = Interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	17385	* \| \| \|1 = Interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	17386	* \| \| \|Note: When data word in receive FIFO is equal or higher than RXTH(I2S_CTL[14:12]) and the RXTHF bit is set to 1.
sahilmgandhi	18:6a4db94011d3	17387	* \| \| \|If RXTHIEN bit is enabled, interrupt occur.
sahilmgandhi	18:6a4db94011d3	17388	* \|[8] \|TXUDIEN \|Transmit FIFO Underflow Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	17389	* \| \| \|0 = Interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	17390	* \| \| \|1 = Interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	17391	* \| \| \|Note: Interrupt occur if this bit is set to 1 and TXUDIEN(I2S_STATUS[16]) flag is set to 1.
sahilmgandhi	18:6a4db94011d3	17392	* \|[9] \|TXOVIEN \|Transmit FIFO Overflow Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	17393	* \| \| \|0 = Interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	17394	* \| \| \|1 = Interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	17395	* \| \| \|Note: Interrupt occurs if this bit is set to 1 and TXOVIEN(I2S_STATUS[17]) flag is set to 1
sahilmgandhi	18:6a4db94011d3	17396	* \|[10] \|TXTHIEN \|Transmit FIFO Threshold Level Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	17397	* \| \| \|0 = Interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	17398	* \| \| \|1 = Interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	17399	* \| \| \|Note: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH(I2S_CTL[11:9]).
sahilmgandhi	18:6a4db94011d3	17400	* \|[11] \|RZCIEN \|Right Channel Zero-Cross Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	17401	* \| \| \|0 = Interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	17402	* \| \| \|1 = Interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	17403	* \| \| \|Note: Interrupt occurs if this bit is set to 1 and right channel zero-cross
sahilmgandhi	18:6a4db94011d3	17404	* \|[12] \|LZCIEN \|Left Channel Zero-Cross Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	17405	* \| \| \|0 = Interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	17406	* \| \| \|1 = Interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	17407	* \| \| \|Note: Interrupt occurs if this bit is set to 1 and left channel zero-cross
sahilmgandhi	18:6a4db94011d3	17408	*/
sahilmgandhi	18:6a4db94011d3	17409	__IO uint32_t IEN;
sahilmgandhi	18:6a4db94011d3	17410
sahilmgandhi	18:6a4db94011d3	17411	/**
sahilmgandhi	18:6a4db94011d3	17412	* STATUS
sahilmgandhi	18:6a4db94011d3	17413	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	17414	* Offset: 0x0C I2S Status Register
sahilmgandhi	18:6a4db94011d3	17415	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	17416	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	17417	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	17418	* \|[0] \|I2SIF \|I2S Interrupt Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	17419	* \| \| \|0 = No I2S interrupt.
sahilmgandhi	18:6a4db94011d3	17420	* \| \| \|1 = I2S interrupt.
sahilmgandhi	18:6a4db94011d3	17421	* \| \| \|Note: It is wire-OR of TXIF and RXIF bits.
sahilmgandhi	18:6a4db94011d3	17422	* \|[1] \|RXIF \|I2S Receive Interrupt (Read Only)
sahilmgandhi	18:6a4db94011d3	17423	* \| \| \|0 = No receive interrupt.
sahilmgandhi	18:6a4db94011d3	17424	* \| \| \|1 = Receive interrupt.
sahilmgandhi	18:6a4db94011d3	17425	* \|[2] \|TXIF \|I2S Transmit Interrupt (Read Only)
sahilmgandhi	18:6a4db94011d3	17426	* \| \| \|0 = No transmit interrupt.
sahilmgandhi	18:6a4db94011d3	17427	* \| \| \|1 = Transmit interrupt.
sahilmgandhi	18:6a4db94011d3	17428	* \|[3] \|RIGHT \|Right Channel (Read Only)
sahilmgandhi	18:6a4db94011d3	17429	* \| \| \|0 = Left channel.
sahilmgandhi	18:6a4db94011d3	17430	* \| \| \|1 = Right channel.
sahilmgandhi	18:6a4db94011d3	17431	* \| \| \|Note: This bit indicate current transmit data is belong to right channel
sahilmgandhi	18:6a4db94011d3	17432	* \|[8] \|RXUDIF \|Receive FIFO Underflow Flag
sahilmgandhi	18:6a4db94011d3	17433	* \| \| \|0 = No underflow occur.
sahilmgandhi	18:6a4db94011d3	17434	* \| \| \|1 = Underflow occur.
sahilmgandhi	18:6a4db94011d3	17435	* \| \| \|Note1: When receive FIFO is empty, and software reads the receive FIFO again.
sahilmgandhi	18:6a4db94011d3	17436	* \| \| \|This bit will be set to 1, and it indicates underflow situation occurs.
sahilmgandhi	18:6a4db94011d3	17437	* \| \| \|Note2: Write 1 to clear this bit to zero
sahilmgandhi	18:6a4db94011d3	17438	* \|[9] \|RXOVIF \|Receive FIFO Overflow Flag
sahilmgandhi	18:6a4db94011d3	17439	* \| \| \|0 = No overflow occur.
sahilmgandhi	18:6a4db94011d3	17440	* \| \| \|1 = Overflow occur.
sahilmgandhi	18:6a4db94011d3	17441	* \| \| \|Note1: When receive FIFO is full and receive hardware attempt write to data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote.
sahilmgandhi	18:6a4db94011d3	17442	* \| \| \|Note2: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	17443	* \|[10] \|RXTHIF \|Receive FIFO Threshold Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	17444	* \| \| \|0 = Data word(s) in FIFO is lower than threshold level.
sahilmgandhi	18:6a4db94011d3	17445	* \| \| \|1 = Data word(s) in FIFO is equal or higher than threshold level.
sahilmgandhi	18:6a4db94011d3	17446	* \| \| \|Note: When data word(s) in receive FIFO is equal or higher than threshold value set in RXTH(I2S_CTL[14:12]) the RXTHIF bit becomes to 1.
sahilmgandhi	18:6a4db94011d3	17447	* \| \| \|It keeps at 1 till RXCNT less than RXTH after software read RXFIFO register.
sahilmgandhi	18:6a4db94011d3	17448	* \|[11] \|RXFULL \|Receive FIFO Full (Read Only)
sahilmgandhi	18:6a4db94011d3	17449	* \| \| \|0 = Not full.
sahilmgandhi	18:6a4db94011d3	17450	* \| \| \|1 = Full.
sahilmgandhi	18:6a4db94011d3	17451	* \| \| \|Note: This bit reflects data words number in receive FIFO is 8.
sahilmgandhi	18:6a4db94011d3	17452	* \|[12] \|RXEMPTY \|Receive FIFO Empty (Read Only)
sahilmgandhi	18:6a4db94011d3	17453	* \| \| \|0 = Not empty.
sahilmgandhi	18:6a4db94011d3	17454	* \| \| \|1 = Empty.
sahilmgandhi	18:6a4db94011d3	17455	* \| \| \|Note: This bit reflects data words number in receive FIFO is zero
sahilmgandhi	18:6a4db94011d3	17456	* \|[16] \|TXUDIF \|Transmit FIFO Underflow Flag
sahilmgandhi	18:6a4db94011d3	17457	* \| \| \|0 = No underflow.
sahilmgandhi	18:6a4db94011d3	17458	* \| \| \|1 = Underflow.
sahilmgandhi	18:6a4db94011d3	17459	* \| \| \|Note1: When transmit FIFO is empty and shift logic hardware read data from data FIFO causes this set to 1.
sahilmgandhi	18:6a4db94011d3	17460	* \| \| \|Note2: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	17461	* \|[17] \|TXOVIF \|Transmit FIFO Overflow Flag
sahilmgandhi	18:6a4db94011d3	17462	* \| \| \|0 = No overflow.
sahilmgandhi	18:6a4db94011d3	17463	* \| \| \|1 = Overflow.
sahilmgandhi	18:6a4db94011d3	17464	* \| \| \|Note1: Write data to transmit FIFO when it is full and this bit set to 1
sahilmgandhi	18:6a4db94011d3	17465	* \| \| \|Note2: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	17466	* \|[18] \|TXTHIF \|Transmit FIFO Threshold Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	17467	* \| \| \|0 = Data word(s) in FIFO is higher than threshold level.
sahilmgandhi	18:6a4db94011d3	17468	* \| \| \|1 = Data word(s) in FIFO is equal or lower than threshold level.
sahilmgandhi	18:6a4db94011d3	17469	* \| \| \|Note: When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH(I2S_CTL[11:9]) the TXTHIF bit becomes to 1.
sahilmgandhi	18:6a4db94011d3	17470	* \| \| \|It keeps at 1 till TXCNT is higher than TXTH after software write TXFIFO register.
sahilmgandhi	18:6a4db94011d3	17471	* \|[19] \|TXFULL \|Transmit FIFO Full (Read Only)
sahilmgandhi	18:6a4db94011d3	17472	* \| \| \|This bit reflect data word number in transmit FIFO is 8
sahilmgandhi	18:6a4db94011d3	17473	* \| \| \|0 = Not full.
sahilmgandhi	18:6a4db94011d3	17474	* \| \| \|1 = Full.
sahilmgandhi	18:6a4db94011d3	17475	* \|[20] \|TXEMPTY \|Transmit FIFO Empty (Read Only)
sahilmgandhi	18:6a4db94011d3	17476	* \| \| \|This bit reflect data word number in transmit FIFO is zero
sahilmgandhi	18:6a4db94011d3	17477	* \| \| \|0 = Not empty.
sahilmgandhi	18:6a4db94011d3	17478	* \| \| \|1 = Empty.
sahilmgandhi	18:6a4db94011d3	17479	* \|[21] \|TXBUSY \|Transmit Busy (Read Only)
sahilmgandhi	18:6a4db94011d3	17480	* \| \| \|0 = Transmit shift buffer is empty.
sahilmgandhi	18:6a4db94011d3	17481	* \| \| \|1 = Transmit shift buffer is busy.
sahilmgandhi	18:6a4db94011d3	17482	* \| \| \|Note: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out.
sahilmgandhi	18:6a4db94011d3	17483	* \| \| \|And set to 1 when 1st data is load to shift buffer.
sahilmgandhi	18:6a4db94011d3	17484	* \|[22] \|RZCIF \|Right Channel Zero-Cross Flag
sahilmgandhi	18:6a4db94011d3	17485	* \| \| \|It indicates right channel next sample data sign bit is changed or all data bits are zero.
sahilmgandhi	18:6a4db94011d3	17486	* \| \| \|0 = No zero-cross.
sahilmgandhi	18:6a4db94011d3	17487	* \| \| \|1 = Right channel zero-cross is detected.
sahilmgandhi	18:6a4db94011d3	17488	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	17489	* \|[23] \|LZCIF \|Left Channel Zero-Cross Flag
sahilmgandhi	18:6a4db94011d3	17490	* \| \| \|It indicates left channel next sample data sign bit is changed or all data bits are zero.
sahilmgandhi	18:6a4db94011d3	17491	* \| \| \|0 = No zero-cross.
sahilmgandhi	18:6a4db94011d3	17492	* \| \| \|1 = Left channel zero-cross is detected.
sahilmgandhi	18:6a4db94011d3	17493	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	17494	* \|[24:27] \|RXCNT \|Receive FIFO Level (Read Only)
sahilmgandhi	18:6a4db94011d3	17495	* \| \| \|These bits indicate word number in receive FIFO
sahilmgandhi	18:6a4db94011d3	17496	* \| \| \|0000 = No data.
sahilmgandhi	18:6a4db94011d3	17497	* \| \| \|0001 = 1 word in receive FIFO.
sahilmgandhi	18:6a4db94011d3	17498	* \| \| \|....
sahilmgandhi	18:6a4db94011d3	17499	* \| \| \|1000 = 8 words in receive FIFO.
sahilmgandhi	18:6a4db94011d3	17500	* \|[28:31] \|TXCNT \|Transmit FIFO Level (Read Only)
sahilmgandhi	18:6a4db94011d3	17501	* \| \| \|These bits indicate word number in transmit FIFO
sahilmgandhi	18:6a4db94011d3	17502	* \| \| \|0000 = No data.
sahilmgandhi	18:6a4db94011d3	17503	* \| \| \|0001 = 1 word in transmit FIFO.
sahilmgandhi	18:6a4db94011d3	17504	* \| \| \|....
sahilmgandhi	18:6a4db94011d3	17505	* \| \| \|1000 = 8 words in transmit FIFO.
sahilmgandhi	18:6a4db94011d3	17506	*/
sahilmgandhi	18:6a4db94011d3	17507	__I uint32_t STATUS;
sahilmgandhi	18:6a4db94011d3	17508
sahilmgandhi	18:6a4db94011d3	17509	/**
sahilmgandhi	18:6a4db94011d3	17510	* TX
sahilmgandhi	18:6a4db94011d3	17511	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	17512	* Offset: 0x10 I2S Transmit FIFO Register
sahilmgandhi	18:6a4db94011d3	17513	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	17514	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	17515	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	17516	* \|[0:31] \|TX \|Transmit FIFO Bits
sahilmgandhi	18:6a4db94011d3	17517	* \| \| \|I2S contains 8 words (8x32 bit) data buffer for data transmit.
sahilmgandhi	18:6a4db94011d3	17518	* \| \| \|Write data to this register to prepare data for transmit.
sahilmgandhi	18:6a4db94011d3	17519	* \| \| \|The remaining word number is indicated by TXCNT(I2S_STATUS[31:28]).
sahilmgandhi	18:6a4db94011d3	17520	*/
sahilmgandhi	18:6a4db94011d3	17521	__O uint32_t TX;
sahilmgandhi	18:6a4db94011d3	17522
sahilmgandhi	18:6a4db94011d3	17523	/**
sahilmgandhi	18:6a4db94011d3	17524	* RX
sahilmgandhi	18:6a4db94011d3	17525	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	17526	* Offset: 0x14 I2S Receive FIFO Register
sahilmgandhi	18:6a4db94011d3	17527	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	17528	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	17529	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	17530	* \|[0:31] \|RX \|Receive FIFO Bits
sahilmgandhi	18:6a4db94011d3	17531	* \| \| \|I2S contains 8 words (8x32 bit) data buffer for data receive.
sahilmgandhi	18:6a4db94011d3	17532	* \| \| \|Read this register to get data in FIFO.
sahilmgandhi	18:6a4db94011d3	17533	* \| \| \|The remaining data word number is indicated by RXCNT(I2S_STATUS[27:24]).
sahilmgandhi	18:6a4db94011d3	17534	*/
sahilmgandhi	18:6a4db94011d3	17535	__I uint32_t RX;
sahilmgandhi	18:6a4db94011d3	17536
sahilmgandhi	18:6a4db94011d3	17537	} I2S_T;
sahilmgandhi	18:6a4db94011d3	17538
sahilmgandhi	18:6a4db94011d3	17539	/**
sahilmgandhi	18:6a4db94011d3	17540	@addtogroup I2S_CONST I2S Bit Field Definition
sahilmgandhi	18:6a4db94011d3	17541	Constant Definitions for I2S Controller
sahilmgandhi	18:6a4db94011d3	17542	@{ */
sahilmgandhi	18:6a4db94011d3	17543
sahilmgandhi	18:6a4db94011d3	17544	#define I2S_CTL_I2SEN_Pos (0) /!< I2S CTL: I2SEN Position /
sahilmgandhi	18:6a4db94011d3	17545	#define I2S_CTL_I2SEN_Msk (0x1ul << I2S_CTL_I2SEN_Pos) /!< I2S CTL: I2SEN Mask /
sahilmgandhi	18:6a4db94011d3	17546
sahilmgandhi	18:6a4db94011d3	17547	#define I2S_CTL_TXEN_Pos (1) /!< I2S CTL: TXEN Position /
sahilmgandhi	18:6a4db94011d3	17548	#define I2S_CTL_TXEN_Msk (0x1ul << I2S_CTL_TXEN_Pos) /!< I2S CTL: TXEN Mask /
sahilmgandhi	18:6a4db94011d3	17549
sahilmgandhi	18:6a4db94011d3	17550	#define I2S_CTL_RXEN_Pos (2) /!< I2S CTL: RXEN Position /
sahilmgandhi	18:6a4db94011d3	17551	#define I2S_CTL_RXEN_Msk (0x1ul << I2S_CTL_RXEN_Pos) /!< I2S CTL: RXEN Mask /
sahilmgandhi	18:6a4db94011d3	17552
sahilmgandhi	18:6a4db94011d3	17553	#define I2S_CTL_MUTE_Pos (3) /!< I2S CTL: MUTE Position /
sahilmgandhi	18:6a4db94011d3	17554	#define I2S_CTL_MUTE_Msk (0x1ul << I2S_CTL_MUTE_Pos) /!< I2S CTL: MUTE Mask /
sahilmgandhi	18:6a4db94011d3	17555
sahilmgandhi	18:6a4db94011d3	17556	#define I2S_CTL_WDWIDTH_Pos (4) /!< I2S CTL: WDWIDTH Position /
sahilmgandhi	18:6a4db94011d3	17557	#define I2S_CTL_WDWIDTH_Msk (0x3ul << I2S_CTL_WDWIDTH_Pos) /!< I2S CTL: WDWIDTH Mask /
sahilmgandhi	18:6a4db94011d3	17558
sahilmgandhi	18:6a4db94011d3	17559	#define I2S_CTL_MONO_Pos (6) /!< I2S CTL: MONO Position /
sahilmgandhi	18:6a4db94011d3	17560	#define I2S_CTL_MONO_Msk (0x1ul << I2S_CTL_MONO_Pos) /!< I2S CTL: MONO Mask /
sahilmgandhi	18:6a4db94011d3	17561
sahilmgandhi	18:6a4db94011d3	17562	#define I2S_CTL_FORMAT_Pos (7) /!< I2S CTL: FORMAT Position /
sahilmgandhi	18:6a4db94011d3	17563	#define I2S_CTL_FORMAT_Msk (0x1ul << I2S_CTL_FORMAT_Pos) /!< I2S CTL: FORMAT Mask /
sahilmgandhi	18:6a4db94011d3	17564
sahilmgandhi	18:6a4db94011d3	17565	#define I2S_CTL_SLAVE_Pos (8) /!< I2S CTL: SLAVE Position /
sahilmgandhi	18:6a4db94011d3	17566	#define I2S_CTL_SLAVE_Msk (0x1ul << I2S_CTL_SLAVE_Pos) /!< I2S CTL: SLAVE Mask /
sahilmgandhi	18:6a4db94011d3	17567
sahilmgandhi	18:6a4db94011d3	17568	#define I2S_CTL_TXTH_Pos (9) /!< I2S CTL: TXTH Position /
sahilmgandhi	18:6a4db94011d3	17569	#define I2S_CTL_TXTH_Msk (0x7ul << I2S_CTL_TXTH_Pos) /!< I2S CTL: TXTH Mask /
sahilmgandhi	18:6a4db94011d3	17570
sahilmgandhi	18:6a4db94011d3	17571	#define I2S_CTL_RXTH_Pos (12) /!< I2S CTL: RXTH Position /
sahilmgandhi	18:6a4db94011d3	17572	#define I2S_CTL_RXTH_Msk (0x7ul << I2S_CTL_RXTH_Pos) /!< I2S CTL: RXTH Mask /
sahilmgandhi	18:6a4db94011d3	17573
sahilmgandhi	18:6a4db94011d3	17574	#define I2S_CTL_MCLKEN_Pos (15) /!< I2S CTL: MCLKEN Position /
sahilmgandhi	18:6a4db94011d3	17575	#define I2S_CTL_MCLKEN_Msk (0x1ul << I2S_CTL_MCLKEN_Pos) /!< I2S CTL: MCLKEN Mask /
sahilmgandhi	18:6a4db94011d3	17576
sahilmgandhi	18:6a4db94011d3	17577	#define I2S_CTL_RZCEN_Pos (16) /!< I2S CTL: RZCEN Position /
sahilmgandhi	18:6a4db94011d3	17578	#define I2S_CTL_RZCEN_Msk (0x1ul << I2S_CTL_RZCEN_Pos) /!< I2S CTL: RZCEN Mask /
sahilmgandhi	18:6a4db94011d3	17579
sahilmgandhi	18:6a4db94011d3	17580	#define I2S_CTL_LZCEN_Pos (17) /!< I2S CTL: LZCEN Position /
sahilmgandhi	18:6a4db94011d3	17581	#define I2S_CTL_LZCEN_Msk (0x1ul << I2S_CTL_LZCEN_Pos) /!< I2S CTL: LZCEN Mask /
sahilmgandhi	18:6a4db94011d3	17582
sahilmgandhi	18:6a4db94011d3	17583	#define I2S_CTL_TXCLR_Pos (18) /!< I2S CTL: TXCLR Position /
sahilmgandhi	18:6a4db94011d3	17584	#define I2S_CTL_TXCLR_Msk (0x1ul << I2S_CTL_TXCLR_Pos) /!< I2S CTL: TXCLR Mask /
sahilmgandhi	18:6a4db94011d3	17585
sahilmgandhi	18:6a4db94011d3	17586	#define I2S_CTL_RXCLR_Pos (19) /!< I2S CTL: RXCLR Position /
sahilmgandhi	18:6a4db94011d3	17587	#define I2S_CTL_RXCLR_Msk (0x1ul << I2S_CTL_RXCLR_Pos) /!< I2S CTL: RXCLR Mask /
sahilmgandhi	18:6a4db94011d3	17588
sahilmgandhi	18:6a4db94011d3	17589	#define I2S_CTL_TXPDMAEN_Pos (20) /!< I2S CTL: TXPDMAEN Position /
sahilmgandhi	18:6a4db94011d3	17590	#define I2S_CTL_TXPDMAEN_Msk (0x1ul << I2S_CTL_TXPDMAEN_Pos) /!< I2S CTL: TXPDMAEN Mask /
sahilmgandhi	18:6a4db94011d3	17591
sahilmgandhi	18:6a4db94011d3	17592	#define I2S_CTL_RXPDMAEN_Pos (21) /!< I2S CTL: RXPDMAEN Position /
sahilmgandhi	18:6a4db94011d3	17593	#define I2S_CTL_RXPDMAEN_Msk (0x1ul << I2S_CTL_RXPDMAEN_Pos) /!< I2S CTL: RXPDMAEN Mask /
sahilmgandhi	18:6a4db94011d3	17594
sahilmgandhi	18:6a4db94011d3	17595	#define I2S_CTL_RXLCH_Pos (23) /!< I2S CTL: RXLCH Position /
sahilmgandhi	18:6a4db94011d3	17596	#define I2S_CTL_RXLCH_Msk (0x1ul << I2S_CTL_RXLCH_Pos) /!< I2S CTL: RXLCH Mask /
sahilmgandhi	18:6a4db94011d3	17597
sahilmgandhi	18:6a4db94011d3	17598	#define I2S_CTL_PCMEN_Pos (24) /!< I2S CTL: PCMEN Position /
sahilmgandhi	18:6a4db94011d3	17599	#define I2S_CTL_PCMEN_Msk (0x1ul << I2S_CTL_PCMEN_Pos) /!< I2S CTL: PCMEN Mask /
sahilmgandhi	18:6a4db94011d3	17600
sahilmgandhi	18:6a4db94011d3	17601	#define I2S_CLKDIV_MCLKDIV_Pos (0) /!< I2S CLKDIV: MCLKDIV Position /
sahilmgandhi	18:6a4db94011d3	17602	#define I2S_CLKDIV_MCLKDIV_Msk (0x3ful << I2S_CLKDIV_MCLKDIV_Pos) /!< I2S CLKDIV: MCLKDIV Mask /
sahilmgandhi	18:6a4db94011d3	17603
sahilmgandhi	18:6a4db94011d3	17604	#define I2S_CLKDIV_BCLKDIV_Pos (8) /!< I2S CLKDIV: BCLKDIV Position /
sahilmgandhi	18:6a4db94011d3	17605	#define I2S_CLKDIV_BCLKDIV_Msk (0x1fful << I2S_CLKDIV_BCLKDIV_Pos) /!< I2S CLKDIV: BCLKDIV Mask /
sahilmgandhi	18:6a4db94011d3	17606
sahilmgandhi	18:6a4db94011d3	17607	#define I2S_IEN_RXUDIEN_Pos (0) /!< I2S IEN: RXUDIEN Position /
sahilmgandhi	18:6a4db94011d3	17608	#define I2S_IEN_RXUDIEN_Msk (0x1ul << I2S_IEN_RXUDIEN_Pos) /!< I2S IEN: RXUDIEN Mask /
sahilmgandhi	18:6a4db94011d3	17609
sahilmgandhi	18:6a4db94011d3	17610	#define I2S_IEN_RXOVIEN_Pos (1) /!< I2S IEN: RXOVIEN Position /
sahilmgandhi	18:6a4db94011d3	17611	#define I2S_IEN_RXOVIEN_Msk (0x1ul << I2S_IEN_RXOVIEN_Pos) /!< I2S IEN: RXOVIEN Mask /
sahilmgandhi	18:6a4db94011d3	17612
sahilmgandhi	18:6a4db94011d3	17613	#define I2S_IEN_RXTHIEN_Pos (2) /!< I2S IEN: RXTHIEN Position /
sahilmgandhi	18:6a4db94011d3	17614	#define I2S_IEN_RXTHIEN_Msk (0x1ul << I2S_IEN_RXTHIEN_Pos) /!< I2S IEN: RXTHIEN Mask /
sahilmgandhi	18:6a4db94011d3	17615
sahilmgandhi	18:6a4db94011d3	17616	#define I2S_IEN_TXUDIEN_Pos (8) /!< I2S IEN: TXUDIEN Position /
sahilmgandhi	18:6a4db94011d3	17617	#define I2S_IEN_TXUDIEN_Msk (0x1ul << I2S_IEN_TXUDIEN_Pos) /!< I2S IEN: TXUDIEN Mask /
sahilmgandhi	18:6a4db94011d3	17618
sahilmgandhi	18:6a4db94011d3	17619	#define I2S_IEN_TXOVIEN_Pos (9) /!< I2S IEN: TXOVIEN Position /
sahilmgandhi	18:6a4db94011d3	17620	#define I2S_IEN_TXOVIEN_Msk (0x1ul << I2S_IEN_TXOVIEN_Pos) /!< I2S IEN: TXOVIEN Mask /
sahilmgandhi	18:6a4db94011d3	17621
sahilmgandhi	18:6a4db94011d3	17622	#define I2S_IEN_TXTHIEN_Pos (10) /!< I2S IEN: TXTHIEN Position /
sahilmgandhi	18:6a4db94011d3	17623	#define I2S_IEN_TXTHIEN_Msk (0x1ul << I2S_IEN_TXTHIEN_Pos) /!< I2S IEN: TXTHIEN Mask /
sahilmgandhi	18:6a4db94011d3	17624
sahilmgandhi	18:6a4db94011d3	17625	#define I2S_IEN_RZCIEN_Pos (11) /!< I2S IEN: RZCIEN Position /
sahilmgandhi	18:6a4db94011d3	17626	#define I2S_IEN_RZCIEN_Msk (0x1ul << I2S_IEN_RZCIEN_Pos) /!< I2S IEN: RZCIEN Mask /
sahilmgandhi	18:6a4db94011d3	17627
sahilmgandhi	18:6a4db94011d3	17628	#define I2S_IEN_LZCIEN_Pos (12) /!< I2S IEN: LZCIEN Position /
sahilmgandhi	18:6a4db94011d3	17629	#define I2S_IEN_LZCIEN_Msk (0x1ul << I2S_IEN_LZCIEN_Pos) /!< I2S IEN: LZCIEN Mask /
sahilmgandhi	18:6a4db94011d3	17630
sahilmgandhi	18:6a4db94011d3	17631	#define I2S_STATUS_I2SIF_Pos (0) /!< I2S STATUS: I2SIF Position /
sahilmgandhi	18:6a4db94011d3	17632	#define I2S_STATUS_I2SIF_Msk (0x1ul << I2S_STATUS_I2SIF_Pos) /!< I2S STATUS: I2SIF Mask /
sahilmgandhi	18:6a4db94011d3	17633
sahilmgandhi	18:6a4db94011d3	17634	#define I2S_STATUS_RXIF_Pos (1) /!< I2S STATUS: RXIF Position /
sahilmgandhi	18:6a4db94011d3	17635	#define I2S_STATUS_RXIF_Msk (0x1ul << I2S_STATUS_RXIF_Pos) /!< I2S STATUS: RXIF Mask /
sahilmgandhi	18:6a4db94011d3	17636
sahilmgandhi	18:6a4db94011d3	17637	#define I2S_STATUS_TXIF_Pos (2) /!< I2S STATUS: TXIF Position /
sahilmgandhi	18:6a4db94011d3	17638	#define I2S_STATUS_TXIF_Msk (0x1ul << I2S_STATUS_TXIF_Pos) /!< I2S STATUS: TXIF Mask /
sahilmgandhi	18:6a4db94011d3	17639
sahilmgandhi	18:6a4db94011d3	17640	#define I2S_STATUS_RIGHT_Pos (3) /!< I2S STATUS: RIGHT Position /
sahilmgandhi	18:6a4db94011d3	17641	#define I2S_STATUS_RIGHT_Msk (0x1ul << I2S_STATUS_RIGHT_Pos) /!< I2S STATUS: RIGHT Mask /
sahilmgandhi	18:6a4db94011d3	17642
sahilmgandhi	18:6a4db94011d3	17643	#define I2S_STATUS_RXUDIF_Pos (8) /!< I2S STATUS: RXUDIF Position /
sahilmgandhi	18:6a4db94011d3	17644	#define I2S_STATUS_RXUDIF_Msk (0x1ul << I2S_STATUS_RXUDIF_Pos) /!< I2S STATUS: RXUDIF Mask /
sahilmgandhi	18:6a4db94011d3	17645
sahilmgandhi	18:6a4db94011d3	17646	#define I2S_STATUS_RXOVIF_Pos (9) /!< I2S STATUS: RXOVIF Position /
sahilmgandhi	18:6a4db94011d3	17647	#define I2S_STATUS_RXOVIF_Msk (0x1ul << I2S_STATUS_RXOVIF_Pos) /!< I2S STATUS: RXOVIF Mask /
sahilmgandhi	18:6a4db94011d3	17648
sahilmgandhi	18:6a4db94011d3	17649	#define I2S_STATUS_RXTHIF_Pos (10) /!< I2S STATUS: RXTHIF Position /
sahilmgandhi	18:6a4db94011d3	17650	#define I2S_STATUS_RXTHIF_Msk (0x1ul << I2S_STATUS_RXTHIF_Pos) /!< I2S STATUS: RXTHIF Mask /
sahilmgandhi	18:6a4db94011d3	17651
sahilmgandhi	18:6a4db94011d3	17652	#define I2S_STATUS_RXFULL_Pos (11) /!< I2S STATUS: RXFULL Position /
sahilmgandhi	18:6a4db94011d3	17653	#define I2S_STATUS_RXFULL_Msk (0x1ul << I2S_STATUS_RXFULL_Pos) /!< I2S STATUS: RXFULL Mask /
sahilmgandhi	18:6a4db94011d3	17654
sahilmgandhi	18:6a4db94011d3	17655	#define I2S_STATUS_RXEMPTY_Pos (12) /!< I2S STATUS: RXEMPTY Position /
sahilmgandhi	18:6a4db94011d3	17656	#define I2S_STATUS_RXEMPTY_Msk (0x1ul << I2S_STATUS_RXEMPTY_Pos) /!< I2S STATUS: RXEMPTY Mask /
sahilmgandhi	18:6a4db94011d3	17657
sahilmgandhi	18:6a4db94011d3	17658	#define I2S_STATUS_TXUDIF_Pos (16) /!< I2S STATUS: TXUDIF Position /
sahilmgandhi	18:6a4db94011d3	17659	#define I2S_STATUS_TXUDIF_Msk (0x1ul << I2S_STATUS_TXUDIF_Pos) /!< I2S STATUS: TXUDIF Mask /
sahilmgandhi	18:6a4db94011d3	17660
sahilmgandhi	18:6a4db94011d3	17661	#define I2S_STATUS_TXOVIF_Pos (17) /!< I2S STATUS: TXOVIF Position /
sahilmgandhi	18:6a4db94011d3	17662	#define I2S_STATUS_TXOVIF_Msk (0x1ul << I2S_STATUS_TXOVIF_Pos) /!< I2S STATUS: TXOVIF Mask /
sahilmgandhi	18:6a4db94011d3	17663
sahilmgandhi	18:6a4db94011d3	17664	#define I2S_STATUS_TXTHIF_Pos (18) /!< I2S STATUS: TXTHIF Position /
sahilmgandhi	18:6a4db94011d3	17665	#define I2S_STATUS_TXTHIF_Msk (0x1ul << I2S_STATUS_TXTHIF_Pos) /!< I2S STATUS: TXTHIF Mask /
sahilmgandhi	18:6a4db94011d3	17666
sahilmgandhi	18:6a4db94011d3	17667	#define I2S_STATUS_TXFULL_Pos (19) /!< I2S STATUS: TXFULL Position /
sahilmgandhi	18:6a4db94011d3	17668	#define I2S_STATUS_TXFULL_Msk (0x1ul << I2S_STATUS_TXFULL_Pos) /!< I2S STATUS: TXFULL Mask /
sahilmgandhi	18:6a4db94011d3	17669
sahilmgandhi	18:6a4db94011d3	17670	#define I2S_STATUS_TXEMPTY_Pos (20) /!< I2S STATUS: TXEMPTY Position /
sahilmgandhi	18:6a4db94011d3	17671	#define I2S_STATUS_TXEMPTY_Msk (0x1ul << I2S_STATUS_TXEMPTY_Pos) /!< I2S STATUS: TXEMPTY Mask /
sahilmgandhi	18:6a4db94011d3	17672
sahilmgandhi	18:6a4db94011d3	17673	#define I2S_STATUS_TXBUSY_Pos (21) /!< I2S STATUS: TXBUSY Position /
sahilmgandhi	18:6a4db94011d3	17674	#define I2S_STATUS_TXBUSY_Msk (0x1ul << I2S_STATUS_TXBUSY_Pos) /!< I2S STATUS: TXBUSY Mask /
sahilmgandhi	18:6a4db94011d3	17675
sahilmgandhi	18:6a4db94011d3	17676	#define I2S_STATUS_RZCIF_Pos (22) /!< I2S STATUS: RZCIF Position /
sahilmgandhi	18:6a4db94011d3	17677	#define I2S_STATUS_RZCIF_Msk (0x1ul << I2S_STATUS_RZCIF_Pos) /!< I2S STATUS: RZCIF Mask /
sahilmgandhi	18:6a4db94011d3	17678
sahilmgandhi	18:6a4db94011d3	17679	#define I2S_STATUS_LZCIF_Pos (23) /!< I2S STATUS: LZCIF Position /
sahilmgandhi	18:6a4db94011d3	17680	#define I2S_STATUS_LZCIF_Msk (0x1ul << I2S_STATUS_LZCIF_Pos) /!< I2S STATUS: LZCIF Mask /
sahilmgandhi	18:6a4db94011d3	17681
sahilmgandhi	18:6a4db94011d3	17682	#define I2S_STATUS_RXCNT_Pos (24) /!< I2S STATUS: RXCNT Position /
sahilmgandhi	18:6a4db94011d3	17683	#define I2S_STATUS_RXCNT_Msk (0xful << I2S_STATUS_RXCNT_Pos) /!< I2S STATUS: RXCNT Mask /
sahilmgandhi	18:6a4db94011d3	17684
sahilmgandhi	18:6a4db94011d3	17685	#define I2S_STATUS_TXCNT_Pos (28) /!< I2S STATUS: TXCNT Position /
sahilmgandhi	18:6a4db94011d3	17686	#define I2S_STATUS_TXCNT_Msk (0xful << I2S_STATUS_TXCNT_Pos) /!< I2S STATUS: TXCNT Mask /
sahilmgandhi	18:6a4db94011d3	17687
sahilmgandhi	18:6a4db94011d3	17688	#define I2S_TX_TX_Pos (0) /!< I2S TX: TX Position /
sahilmgandhi	18:6a4db94011d3	17689	#define I2S_TX_TX_Msk (0xfffffffful << I2S_TX_TX_Pos) /!< I2S TX: TX Mask /
sahilmgandhi	18:6a4db94011d3	17690
sahilmgandhi	18:6a4db94011d3	17691	#define I2S_RX_RX_Pos (0) /!< I2S RX: RX Position /
sahilmgandhi	18:6a4db94011d3	17692	#define I2S_RX_RX_Msk (0xfffffffful << I2S_RX_RX_Pos) /!< I2S RX: RX Mask /
sahilmgandhi	18:6a4db94011d3	17693
sahilmgandhi	18:6a4db94011d3	17694	/*@}/ /* I2S_CONST */
sahilmgandhi	18:6a4db94011d3	17695	/*@}/ /* end of I2S register group */
sahilmgandhi	18:6a4db94011d3	17696
sahilmgandhi	18:6a4db94011d3	17697
sahilmgandhi	18:6a4db94011d3	17698	/---------------------- OP Amplifier -------------------------/
sahilmgandhi	18:6a4db94011d3	17699	/**
sahilmgandhi	18:6a4db94011d3	17700	@addtogroup OPA OP Amplifier(OPA)
sahilmgandhi	18:6a4db94011d3	17701	Memory Mapped Structure for OPA Controller
sahilmgandhi	18:6a4db94011d3	17702	@{ */
sahilmgandhi	18:6a4db94011d3	17703
sahilmgandhi	18:6a4db94011d3	17704	typedef struct {
sahilmgandhi	18:6a4db94011d3	17705
sahilmgandhi	18:6a4db94011d3	17706
sahilmgandhi	18:6a4db94011d3	17707	/**
sahilmgandhi	18:6a4db94011d3	17708	* CTL
sahilmgandhi	18:6a4db94011d3	17709	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	17710	* Offset: 0x00 OP Amplifier Control Register
sahilmgandhi	18:6a4db94011d3	17711	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	17712	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	17713	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	17714	* \|[0] \|OPEN0 \|OP Amplifier 0 Enable Control
sahilmgandhi	18:6a4db94011d3	17715	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	17716	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	17717	* \| \| \|Note: OP Amplifier 0 output needs wait stable 20us[MS1] after OPEN0 is first set.
sahilmgandhi	18:6a4db94011d3	17718	* \| \| \|[MS1]alpha test
sahilmgandhi	18:6a4db94011d3	17719	* \|[1] \|OPEN1 \|OP Amplifier 1 Enable Control
sahilmgandhi	18:6a4db94011d3	17720	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	17721	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	17722	* \| \| \|Note: OP Amplifier 1 output needs wait stable 20us[MS1] after OPEN1 is first set.
sahilmgandhi	18:6a4db94011d3	17723	* \| \| \|[MS1]alpha test
sahilmgandhi	18:6a4db94011d3	17724	* \|[4] \|OPSMTEN0 \|OP Amplifier 0 Schmitt Trigger Non-Inverting Buffer Enable Control
sahilmgandhi	18:6a4db94011d3	17725	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	17726	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	17727	* \|[5] \|OPSMTEN1 \|OP Amplifier 1 Schmitt Trigger Non-Inverting Buffer Enable Control
sahilmgandhi	18:6a4db94011d3	17728	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	17729	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	17730	* \|[8] \|OPAIE0 \|OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	17731	* \| \| \|0 = OP Amplifier 0 digital output interrupt function Disabled.
sahilmgandhi	18:6a4db94011d3	17732	* \| \| \|1 = OP Amplifier 0 digital output interrupt function Enabled.
sahilmgandhi	18:6a4db94011d3	17733	* \| \| \|The OPDF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPAIE0 is set to 1, a comparator interrupt request is generated.
sahilmgandhi	18:6a4db94011d3	17734	* \|[9] \|OPAIE1 \|OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	17735	* \| \| \|0 = OP Amplifier 1 digital output interrupt function Disabled.
sahilmgandhi	18:6a4db94011d3	17736	* \| \| \|1 = OP Amplifier 1 digital output interrupt function Enabled.
sahilmgandhi	18:6a4db94011d3	17737	* \| \| \|OPDF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPAIE1 is set to 1, a comparator interrupt request is generated.
sahilmgandhi	18:6a4db94011d3	17738	*/
sahilmgandhi	18:6a4db94011d3	17739	__IO uint32_t CTL;
sahilmgandhi	18:6a4db94011d3	17740
sahilmgandhi	18:6a4db94011d3	17741	/**
sahilmgandhi	18:6a4db94011d3	17742	* STATUS
sahilmgandhi	18:6a4db94011d3	17743	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	17744	* Offset: 0x04 OP Amplifier Status Register
sahilmgandhi	18:6a4db94011d3	17745	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	17746	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	17747	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	17748	* \|[0] \|OPDO0 \|OP Amplifier 0 Digital Output
sahilmgandhi	18:6a4db94011d3	17749	* \| \| \|Synchronized to the APB clock to allow reading by software.
sahilmgandhi	18:6a4db94011d3	17750	* \| \| \|Cleared when the Schmitt trigger buffer is disabled (OPSMTEN0 = 0).
sahilmgandhi	18:6a4db94011d3	17751	* \|[1] \|OPDO1 \|OP Amplifier 1 Digital Output
sahilmgandhi	18:6a4db94011d3	17752	* \| \| \|Synchronized to the APB clock to allow reading by software.
sahilmgandhi	18:6a4db94011d3	17753	* \| \| \|Cleared when the Schmitt trigger buffer is disabled (OPSMTEN1 = 0).
sahilmgandhi	18:6a4db94011d3	17754	* \|[4] \|OPDF0 \|OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Flag
sahilmgandhi	18:6a4db94011d3	17755	* \| \| \|OPDF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state.
sahilmgandhi	18:6a4db94011d3	17756	* \| \| \|This bit is cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	17757	* \|[5] \|OPDF1 \|OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Flag
sahilmgandhi	18:6a4db94011d3	17758	* \| \| \|OPDF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state.
sahilmgandhi	18:6a4db94011d3	17759	* \| \| \|This bit is cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	17760	*/
sahilmgandhi	18:6a4db94011d3	17761	__IO uint32_t STATUS;
sahilmgandhi	18:6a4db94011d3	17762
sahilmgandhi	18:6a4db94011d3	17763	} OPA_T;
sahilmgandhi	18:6a4db94011d3	17764
sahilmgandhi	18:6a4db94011d3	17765	/**
sahilmgandhi	18:6a4db94011d3	17766	@addtogroup OPA_CONST OPA Bit Field Definition
sahilmgandhi	18:6a4db94011d3	17767	Constant Definitions for OPA Controller
sahilmgandhi	18:6a4db94011d3	17768	@{ */
sahilmgandhi	18:6a4db94011d3	17769
sahilmgandhi	18:6a4db94011d3	17770	#define OPA_CTL_OPEN0_Pos (0) /!< OPA CTL: OPEN0 Position /
sahilmgandhi	18:6a4db94011d3	17771	#define OPA_CTL_OPEN0_Msk (0x1ul << OPA_CTL_OPEN0_Pos) /!< OPA CTL: OPEN0 Mask /
sahilmgandhi	18:6a4db94011d3	17772
sahilmgandhi	18:6a4db94011d3	17773	#define OPA_CTL_OPEN1_Pos (1) /!< OPA CTL: OPEN1 Position /
sahilmgandhi	18:6a4db94011d3	17774	#define OPA_CTL_OPEN1_Msk (0x1ul << OPA_CTL_OPEN1_Pos) /!< OPA CTL: OPEN1 Mask /
sahilmgandhi	18:6a4db94011d3	17775
sahilmgandhi	18:6a4db94011d3	17776	#define OPA_CTL_OPSMTEN0_Pos (4) /!< OPA CTL: OPSMTEN0 Position /
sahilmgandhi	18:6a4db94011d3	17777	#define OPA_CTL_OPSMTEN0_Msk (0x1ul << OPA_CTL_OPSMTEN0_Pos) /!< OPA CTL: OPSMTEN0 Mask /
sahilmgandhi	18:6a4db94011d3	17778
sahilmgandhi	18:6a4db94011d3	17779	#define OPA_CTL_OPSMTEN1_Pos (5) /!< OPA CTL: OPSMTEN1 Position /
sahilmgandhi	18:6a4db94011d3	17780	#define OPA_CTL_OPSMTEN1_Msk (0x1ul << OPA_CTL_OPSMTEN1_Pos) /!< OPA CTL: OPSMTEN1 Mask /
sahilmgandhi	18:6a4db94011d3	17781
sahilmgandhi	18:6a4db94011d3	17782	#define OPA_CTL_OPAIE0_Pos (8) /!< OPA CTL: OPAIE0 Position /
sahilmgandhi	18:6a4db94011d3	17783	#define OPA_CTL_OPAIE0_Msk (0x1ul << OPA_CTL_OPAIE0_Pos) /!< OPA CTL: OPAIE0 Mask /
sahilmgandhi	18:6a4db94011d3	17784
sahilmgandhi	18:6a4db94011d3	17785	#define OPA_CTL_OPAIE1_Pos (9) /!< OPA CTL: OPAIE1 Position /
sahilmgandhi	18:6a4db94011d3	17786	#define OPA_CTL_OPAIE1_Msk (0x1ul << OPA_CTL_OPAIE1_Pos) /!< OPA CTL: OPAIE1 Mask /
sahilmgandhi	18:6a4db94011d3	17787
sahilmgandhi	18:6a4db94011d3	17788	#define OPA_STATUS_OPDO0_Pos (0) /!< OPA STATUS: OPDO0 Position /
sahilmgandhi	18:6a4db94011d3	17789	#define OPA_STATUS_OPDO0_Msk (0x1ul << OPA_STATUS_OPDO0_Pos) /!< OPA STATUS: OPDO0 Mask /
sahilmgandhi	18:6a4db94011d3	17790
sahilmgandhi	18:6a4db94011d3	17791	#define OPA_STATUS_OPDO1_Pos (1) /!< OPA STATUS: OPDO1 Position /
sahilmgandhi	18:6a4db94011d3	17792	#define OPA_STATUS_OPDO1_Msk (0x1ul << OPA_STATUS_OPDO1_Pos) /!< OPA STATUS: OPDO1 Mask /
sahilmgandhi	18:6a4db94011d3	17793
sahilmgandhi	18:6a4db94011d3	17794	#define OPA_STATUS_OPDF0_Pos (4) /!< OPA STATUS: OPDF0 Position /
sahilmgandhi	18:6a4db94011d3	17795	#define OPA_STATUS_OPDF0_Msk (0x1ul << OPA_STATUS_OPDF0_Pos) /!< OPA STATUS: OPDF0 Mask /
sahilmgandhi	18:6a4db94011d3	17796
sahilmgandhi	18:6a4db94011d3	17797	#define OPA_STATUS_OPDF1_Pos (5) /!< OPA STATUS: OPDF1 Position /
sahilmgandhi	18:6a4db94011d3	17798	#define OPA_STATUS_OPDF1_Msk (0x1ul << OPA_STATUS_OPDF1_Pos) /!< OPA STATUS: OPDF1 Mask /
sahilmgandhi	18:6a4db94011d3	17799
sahilmgandhi	18:6a4db94011d3	17800	/*@}/ /* OPA_CONST */
sahilmgandhi	18:6a4db94011d3	17801	/*@}/ /* end of OPA register group */
sahilmgandhi	18:6a4db94011d3	17802
sahilmgandhi	18:6a4db94011d3	17803
sahilmgandhi	18:6a4db94011d3	17804	/---------------------- USB On-The-Go Controller -------------------------/
sahilmgandhi	18:6a4db94011d3	17805	/**
sahilmgandhi	18:6a4db94011d3	17806	@addtogroup OTG USB On-The-Go Controller(OTG)
sahilmgandhi	18:6a4db94011d3	17807	Memory Mapped Structure for OTG Controller
sahilmgandhi	18:6a4db94011d3	17808	@{ */
sahilmgandhi	18:6a4db94011d3	17809
sahilmgandhi	18:6a4db94011d3	17810	typedef struct {
sahilmgandhi	18:6a4db94011d3	17811
sahilmgandhi	18:6a4db94011d3	17812
sahilmgandhi	18:6a4db94011d3	17813	/**
sahilmgandhi	18:6a4db94011d3	17814	* CTL
sahilmgandhi	18:6a4db94011d3	17815	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	17816	* Offset: 0x00 OTG Control Register
sahilmgandhi	18:6a4db94011d3	17817	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	17818	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	17819	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	17820	* \|[0] \|VBUSDROP \|Drop The VUSB Bus
sahilmgandhi	18:6a4db94011d3	17821	* \| \| \|If user application running on this OTG A-device wants to conserve power consumption, set this bit to high When set this bit to TRUE, BUSREQ shall be cleared as well.
sahilmgandhi	18:6a4db94011d3	17822	* \| \| \|0 = Did Not drop the VBUS and keep going on USB data transfers.
sahilmgandhi	18:6a4db94011d3	17823	* \| \| \|1 = Drop the VBUS to conserve power consumption.
sahilmgandhi	18:6a4db94011d3	17824	* \|[1] \|BUSREQ \|OTG A-Device Bus Request
sahilmgandhi	18:6a4db94011d3	17825	* \| \| \|If user application of an OTG A-device wants to do data transfers via USB bus, set this bit to high Otherwise if user application won't use the bus any more, set this bit to low.
sahilmgandhi	18:6a4db94011d3	17826	* \| \| \|This bit will be automatically cleared if VBUSDROP bit is set to TRUE.
sahilmgandhi	18:6a4db94011d3	17827	* \|[2] \|HNPREQEN \|OTG B-Device HNP Enable/Request
sahilmgandhi	18:6a4db94011d3	17828	* \| \| \|Set this bit to TRUE after the OTG A-device successfully sends a SetFeature(b_hnp_enable) command to the OTG B-device This bit will be cleared automatically when a bus reset or SESS_VLD goes from TRUE to FALSE.
sahilmgandhi	18:6a4db94011d3	17829	* \|[4] \|OTGEN \|OTG Function Enable Control
sahilmgandhi	18:6a4db94011d3	17830	* \| \| \|If USB is configured as OTG device, this bit must set high.
sahilmgandhi	18:6a4db94011d3	17831	* \| \| \|0= OTG function Disabled.
sahilmgandhi	18:6a4db94011d3	17832	* \| \| \|1 = OTG function Enabled.
sahilmgandhi	18:6a4db94011d3	17833	* \|[7] \|PDEVCKON \|Force OTG PHY Output Clock To USB Device
sahilmgandhi	18:6a4db94011d3	17834	* \| \| \|If software configures OTG controller as OTG device and OTG device as A-device, OTG controller will output OTG PHY clock (30 MHz) to USB device only when OTG device as A-peripheral.
sahilmgandhi	18:6a4db94011d3	17835	* \| \| \|If software needs to configure USB device before role change (from A-Host to A-Peripheral), software can set this bit high to output OTG PHY clock to USB device.
sahilmgandhi	18:6a4db94011d3	17836	* \| \| \|0= USB device clock is available only when OTG device as a peripheral.
sahilmgandhi	18:6a4db94011d3	17837	* \| \| \|1 = Force output OTG PHY clock to USB device.
sahilmgandhi	18:6a4db94011d3	17838	* \|[8] \|WKEN \|OTG Wake-Up Enable Control
sahilmgandhi	18:6a4db94011d3	17839	* \| \| \|0= OTG ID pin status change wake-up Disabled.
sahilmgandhi	18:6a4db94011d3	17840	* \| \| \|1 = OTG ID pin status change wake-up Enabled.
sahilmgandhi	18:6a4db94011d3	17841	*/
sahilmgandhi	18:6a4db94011d3	17842	__IO uint32_t CTL;
sahilmgandhi	18:6a4db94011d3	17843
sahilmgandhi	18:6a4db94011d3	17844	/**
sahilmgandhi	18:6a4db94011d3	17845	* PHYCTL
sahilmgandhi	18:6a4db94011d3	17846	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	17847	* Offset: 0x04 OTG PHY Control Register
sahilmgandhi	18:6a4db94011d3	17848	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	17849	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	17850	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	17851	* \|[0] \|SWPDEN \|Software Control Pull-Down On Data Lines Enable Control
sahilmgandhi	18:6a4db94011d3	17852	* \| \| \|0 = Pull-down resistors on data lines is controlled by OTG control logic.
sahilmgandhi	18:6a4db94011d3	17853	* \| \| \|1 = Pull-down resistors on data lines is controlled by software.
sahilmgandhi	18:6a4db94011d3	17854	* \| \| \|Note: Software must set this bit high before controlling DPPDEN and DMPDEN.
sahilmgandhi	18:6a4db94011d3	17855	* \|[1] \|DPPDEN \|D+ Pull-Down Enable Control Set SWPDEN to TRUE before using this function
sahilmgandhi	18:6a4db94011d3	17856	* \| \| \|0 = 15 kOhm resistor pull-down on D+ pin Disabled.
sahilmgandhi	18:6a4db94011d3	17857	* \| \| \|1 = 15 kOhm resistor pull-down on D+ pin Enabled.
sahilmgandhi	18:6a4db94011d3	17858	* \|[2] \|DMPDEN \|D- Pull-Down Enable Control Set SWPDEN to TRUE before using this function
sahilmgandhi	18:6a4db94011d3	17859	* \| \| \|0 = 15 kOhm resistor pull-down on D- pin Disabled.
sahilmgandhi	18:6a4db94011d3	17860	* \| \| \|1 = 15 kOhm resistor pull-down on D- pin Enabled.
sahilmgandhi	18:6a4db94011d3	17861	* \|[5] \|VBSTSPOL \|Off-Chip USB VBUS Power Status Polarity
sahilmgandhi	18:6a4db94011d3	17862	* \| \| \|The polarity of off-chip USB VBUS LDO valid depends on the selected component.
sahilmgandhi	18:6a4db94011d3	17863	* \| \| \|This bit provides the inversed option of off-chip USB VBUS LDO valid.
sahilmgandhi	18:6a4db94011d3	17864	* \| \| \|0 = The polarity of off-chip USB VBUS LDO valid not inversed.
sahilmgandhi	18:6a4db94011d3	17865	* \| \| \|1 = The polarity of off-chip USB VBUS LDO valid inversed.
sahilmgandhi	18:6a4db94011d3	17866	* \|[6] \|VBENPOL \|Off-Chip USB VBUS Power Enable Polarity
sahilmgandhi	18:6a4db94011d3	17867	* \| \| \|The OTG controller will enable off-chip USB VBUS LDO to provide VBUS power when need.
sahilmgandhi	18:6a4db94011d3	17868	* \| \| \|The polarity of enabling off-chip BSU VBUS LDO (high active or low active) depends on the selected component.
sahilmgandhi	18:6a4db94011d3	17869	* \| \| \|This bit provides the inverse option of off-chip USB VBUS LDO enable.
sahilmgandhi	18:6a4db94011d3	17870	* \| \| \|0 = The polarity of enabling off-chip USB VBUS LDO from the OTG controller not inversed.
sahilmgandhi	18:6a4db94011d3	17871	* \| \| \|1 = The polarity of enabling off-chip USB VBUS LDO from the OTG controller inversed.
sahilmgandhi	18:6a4db94011d3	17872	* \|[7] \|IDDETEN \|ID Detection Enable
sahilmgandhi	18:6a4db94011d3	17873	* \| \| \|0 = Sampling on ID pin Enabled.
sahilmgandhi	18:6a4db94011d3	17874	* \| \| \|1 = Sampling on ID pin Disabled.
sahilmgandhi	18:6a4db94011d3	17875	* \|[8] \|PHYCLK \|PHY Input Clock Selection
sahilmgandhi	18:6a4db94011d3	17876	* \| \| \|0 = PHY input clock is12 MHz.
sahilmgandhi	18:6a4db94011d3	17877	* \| \| \|1 = PHY input clock is 24 MHz.
sahilmgandhi	18:6a4db94011d3	17878	* \|[9] \|OTGPHYEN \|OTG PHY Enable Control When Device Configured As OTG-Device
sahilmgandhi	18:6a4db94011d3	17879	* \| \| \|When device is configured as OTG-device, hardware will not enable OTG PHY automatically.
sahilmgandhi	18:6a4db94011d3	17880	* \| \| \|Software can set OTG_EN to enable OTG PHY.
sahilmgandhi	18:6a4db94011d3	17881	* \| \| \|0 = OTG PHY Disabled.
sahilmgandhi	18:6a4db94011d3	17882	* \| \| \|1 = OTG PHY Enabled.
sahilmgandhi	18:6a4db94011d3	17883	*/
sahilmgandhi	18:6a4db94011d3	17884	__IO uint32_t PHYCTL;
sahilmgandhi	18:6a4db94011d3	17885
sahilmgandhi	18:6a4db94011d3	17886	/**
sahilmgandhi	18:6a4db94011d3	17887	* INTEN
sahilmgandhi	18:6a4db94011d3	17888	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	17889	* Offset: 0x08 OTG Interrupt Enable Register
sahilmgandhi	18:6a4db94011d3	17890	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	17891	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	17892	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	17893	* \|[0] \|ROLECHGIEN\|Role(Host Or Peripheral) Changed Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	17894	* \| \| \|0 = Interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	17895	* \| \| \|1 = Interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	17896	* \|[1] \|VBEIEN \|VBUS Error Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	17897	* \| \| \|0 = Interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	17898	* \| \| \|1 = Interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	17899	* \| \| \|Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec.
sahilmgandhi	18:6a4db94011d3	17900	* \|[2] \|SRPFIEN \|SRP Fail Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	17901	* \| \| \|0 = Interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	17902	* \| \| \|1 = Interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	17903	* \|[3] \|HNPFIEN \|HNP Fail Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	17904	* \| \| \|0 = Interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	17905	* \| \| \|1 = Interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	17906	* \|[4] \|GOIDLEIEN \|OTG Device Goes IDLE State Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	17907	* \| \| \|0 = Interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	17908	* \| \| \|1 = Interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	17909	* \| \| \|Note: Going to idle state means going to a_idle or b_idle state.
sahilmgandhi	18:6a4db94011d3	17910	* \| \| \|Please refer to A-device state diagram and B-device state diagram in OTG spec.
sahilmgandhi	18:6a4db94011d3	17911	* \|[5] \|IDCHGIEN \|IDSTS Changed Interrupt Enable
sahilmgandhi	18:6a4db94011d3	17912	* \| \| \|0 = Interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	17913	* \| \| \|1 = Interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	17914	* \|[6] \|PDEVIEN \|Act As Peripheral Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	17915	* \| \| \|0 = This device as a peripheral interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	17916	* \| \| \|1 = This device as a peripheral interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	17917	* \|[7] \|HOSTIEN \|Act As Host Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	17918	* \| \| \|0= This device as a host interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	17919	* \| \| \|1 = This device as a host interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	17920	* \|[8] \|BVLDCHGIEN\|B-Device Session Valid Status Change (From High To Low Or From Low To High) Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	17921	* \| \| \|0 =Interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	17922	* \| \| \|1 = Interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	17923	* \|[9] \|AVLDCHGIEN\|A-Device Session Valid Status Change (From High To Low Or From Low To High) Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	17924	* \| \| \|0 = Interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	17925	* \| \| \|1 = Interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	17926	* \|[10] \|VBCHGIEN \|VBVALID Status Changed Interrupt Enable
sahilmgandhi	18:6a4db94011d3	17927	* \| \| \|0 = Interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	17928	* \| \| \|1 = Interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	17929	* \|[11] \|SECHGIEN \|SESSEND Status Changed Interrupt Enable Control 0 = Interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	17930	* \| \| \|1 = Interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	17931	* \|[13] \|SRPDETIEN \|SRP Detected Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	17932	* \| \| \|0 = Interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	17933	* \| \| \|1 = Interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	17934	*/
sahilmgandhi	18:6a4db94011d3	17935	__IO uint32_t INTEN;
sahilmgandhi	18:6a4db94011d3	17936
sahilmgandhi	18:6a4db94011d3	17937	/**
sahilmgandhi	18:6a4db94011d3	17938	* INTSTS
sahilmgandhi	18:6a4db94011d3	17939	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	17940	* Offset: 0x0C OTG Interrupt Status Register
sahilmgandhi	18:6a4db94011d3	17941	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	17942	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	17943	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	17944	* \|[0] \|ROLECHGIF \|OTG Role Change Interrupt Status
sahilmgandhi	18:6a4db94011d3	17945	* \| \| \|This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host
sahilmgandhi	18:6a4db94011d3	17946	* \| \| \|Note: Write 1 to clear this flag.
sahilmgandhi	18:6a4db94011d3	17947	* \|[1] \|VBEIF \|VBUS Error Interrupt Status
sahilmgandhi	18:6a4db94011d3	17948	* \| \| \|This flag will be set in one of two conditions
sahilmgandhi	18:6a4db94011d3	17949	* \| \| \|l One case is that voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A device starting to drive.
sahilmgandhi	18:6a4db94011d3	17950	* \| \| \|l The other case is that the supplied VBUS drops below a minimum valid threshold due to the overcurrent condition.
sahilmgandhi	18:6a4db94011d3	17951	* \| \| \|Note: Write 1 to clear this flag and recover from the VBUS error state.
sahilmgandhi	18:6a4db94011d3	17952	* \|[2] \|SRPFIF \|SRP Fail Interrupt Status
sahilmgandhi	18:6a4db94011d3	17953	* \| \| \|After initiating SRP, an OTG B-device will wait at least TB_SRP_FAIL min, defined in OTG specification, for the OTG A-device respond This flag is set when the OTG B-device didn't get the response from the remote A-device to turn VBUS on and generate a bus reset.
sahilmgandhi	18:6a4db94011d3	17954	* \| \| \|Note: Write 1 to clear this flag.
sahilmgandhi	18:6a4db94011d3	17955	* \|[3] \|HNPFIF \|HNP Fail Interrupt Status
sahilmgandhi	18:6a4db94011d3	17956	* \| \| \|When A-device has granted B-device to be host and USB bus in SE0 state, this bit will be set in specified interval (b_ase0_brst_tmr, defined in OTG spec.
sahilmgandhi	18:6a4db94011d3	17957	* \| \| \|specification), A-device does not signal connect signal.
sahilmgandhi	18:6a4db94011d3	17958	* \| \| \|Note: Write 1 to clear this flag.
sahilmgandhi	18:6a4db94011d3	17959	* \|[4] \|GOIDLEIF \|OTG Device Goes IDLE Interrupt Status
sahilmgandhi	18:6a4db94011d3	17960	* \| \| \|Flag is set if the OTG device transfers from non-idle state to idle state.
sahilmgandhi	18:6a4db94011d3	17961	* \| \| \|The OTG device will be neither a host nor a peripheral.
sahilmgandhi	18:6a4db94011d3	17962	* \| \| \|0 = OTG device does not go back to idle state(a_idle or b_idle).
sahilmgandhi	18:6a4db94011d3	17963	* \| \| \|1 = OTG device go back to idle state(a_idle or b_idle).
sahilmgandhi	18:6a4db94011d3	17964	* \| \| \|Note: Write 1 to clear this flag.
sahilmgandhi	18:6a4db94011d3	17965	* \|[5] \|IDCHGIF \|ID State Change Interrupt Status
sahilmgandhi	18:6a4db94011d3	17966	* \| \| \|0 = IDSTS not toggled.
sahilmgandhi	18:6a4db94011d3	17967	* \| \| \|1 = IDSTS from high to low or from low to high.
sahilmgandhi	18:6a4db94011d3	17968	* \| \| \|Note1: OTG_CTL[BUSREQ] will be cleared when IDDIG is high.
sahilmgandhi	18:6a4db94011d3	17969	* \| \| \|Note2: Write 1 to clear this flag.
sahilmgandhi	18:6a4db94011d3	17970	* \|[6] \|PDEVIF \|Act As Peripheral Interrupt Status
sahilmgandhi	18:6a4db94011d3	17971	* \| \| \|0= This device does not act as a peripheral.
sahilmgandhi	18:6a4db94011d3	17972	* \| \| \|1 = This device acts as a peripheral.
sahilmgandhi	18:6a4db94011d3	17973	* \| \| \|Note: Write 1 to clear this flag.
sahilmgandhi	18:6a4db94011d3	17974	* \|[7] \|HOSTIF \|Act As Host Interrupt Status
sahilmgandhi	18:6a4db94011d3	17975	* \| \| \|0= This device does not act as a host.
sahilmgandhi	18:6a4db94011d3	17976	* \| \| \|1 = This device acts as a host.
sahilmgandhi	18:6a4db94011d3	17977	* \| \| \|Note: Write 1 to clear this flag.
sahilmgandhi	18:6a4db94011d3	17978	* \|[8] \|BVLDCHGIF \|B-Device Session Valid State Change Interrupt Status
sahilmgandhi	18:6a4db94011d3	17979	* \| \| \|0 = BVLD not toggled.
sahilmgandhi	18:6a4db94011d3	17980	* \| \| \|1 = BVLD from high to low or low to high.
sahilmgandhi	18:6a4db94011d3	17981	* \| \| \|Note: Write 1 to clear this status.
sahilmgandhi	18:6a4db94011d3	17982	* \|[9] \|AVLDCHGIF \|A-Device Session Valid State Change Interrupt Status
sahilmgandhi	18:6a4db94011d3	17983	* \| \| \|0 = AVLD not toggled.
sahilmgandhi	18:6a4db94011d3	17984	* \| \| \|1 = AVLD from high to low or low to high.
sahilmgandhi	18:6a4db94011d3	17985	* \| \| \|Note: Write 1 to clear this flag.
sahilmgandhi	18:6a4db94011d3	17986	* \|[10] \|VBCHGIF \|VBVALID State Change Interrupt Status
sahilmgandhi	18:6a4db94011d3	17987	* \| \| \|0 = VBUS_VLD not toggled.
sahilmgandhi	18:6a4db94011d3	17988	* \| \| \|1 = VBUSVLD from high to low or from low to high.
sahilmgandhi	18:6a4db94011d3	17989	* \| \| \|Note: Write 1 to clear this flag.
sahilmgandhi	18:6a4db94011d3	17990	* \|[11] \|SECHGIF \|SESSEND State Change Interrupt Status
sahilmgandhi	18:6a4db94011d3	17991	* \| \| \|0 = Session end not toggled.
sahilmgandhi	18:6a4db94011d3	17992	* \| \| \|1 = SESSEND from high to low or from low to high.
sahilmgandhi	18:6a4db94011d3	17993	* \| \| \|Note: Write 1 to clear this flag.
sahilmgandhi	18:6a4db94011d3	17994	* \|[13] \|SRPDETIF \|SRP Detected Interrupt Status
sahilmgandhi	18:6a4db94011d3	17995	* \| \| \|0 = SRP not detected.
sahilmgandhi	18:6a4db94011d3	17996	* \| \| \|1 = SRP detected.
sahilmgandhi	18:6a4db94011d3	17997	* \| \| \|Note: Write 1 to clear this status.
sahilmgandhi	18:6a4db94011d3	17998	*/
sahilmgandhi	18:6a4db94011d3	17999	__IO uint32_t INTSTS;
sahilmgandhi	18:6a4db94011d3	18000
sahilmgandhi	18:6a4db94011d3	18001	/**
sahilmgandhi	18:6a4db94011d3	18002	* STATUS
sahilmgandhi	18:6a4db94011d3	18003	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18004	* Offset: 0x10 Functional Status Register
sahilmgandhi	18:6a4db94011d3	18005	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18006	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18007	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18008	* \|[0] \|OVERCUR \|Over current Condition
sahilmgandhi	18:6a4db94011d3	18009	* \| \| \|The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A device starting to drive
sahilmgandhi	18:6a4db94011d3	18010	* \| \| \|0 = OTG A-device drives VBUS successfully.
sahilmgandhi	18:6a4db94011d3	18011	* \| \| \|1 = Over current condition occurred.
sahilmgandhi	18:6a4db94011d3	18012	* \|[1] \|IDSTS \|ID Pin State Of Mini-B/Micro-Plug
sahilmgandhi	18:6a4db94011d3	18013	* \| \| \|0 = Mini-A/Micro-A plug is attached.
sahilmgandhi	18:6a4db94011d3	18014	* \| \| \|1 = Mini-B/Micro-B plug is attached.
sahilmgandhi	18:6a4db94011d3	18015	* \|[2] \|SESSEND \|Session End Status
sahilmgandhi	18:6a4db94011d3	18016	* \| \| \|0 = VBUS > 0.8V.
sahilmgandhi	18:6a4db94011d3	18017	* \| \| \|1 = VBUS < 0.2V.
sahilmgandhi	18:6a4db94011d3	18018	* \|[3] \|BVLID \|B-Device Session Valid Status
sahilmgandhi	18:6a4db94011d3	18019	* \| \| \|0 = VBUS < 0.8V.
sahilmgandhi	18:6a4db94011d3	18020	* \| \| \|1 = VBUS > 4V.
sahilmgandhi	18:6a4db94011d3	18021	* \|[4] \|AVLD \|A-Device Session Valid Status
sahilmgandhi	18:6a4db94011d3	18022	* \| \| \|0 = VBUS < 0.8V.
sahilmgandhi	18:6a4db94011d3	18023	* \| \| \|1 = VBUS > 2V.
sahilmgandhi	18:6a4db94011d3	18024	* \|[5] \|VBUSVLD \|VBUS Valid Status
sahilmgandhi	18:6a4db94011d3	18025	* \| \| \|0 = VBUS < 4.4V.
sahilmgandhi	18:6a4db94011d3	18026	* \| \| \|1 = VBUS > 4.75V.
sahilmgandhi	18:6a4db94011d3	18027	*/
sahilmgandhi	18:6a4db94011d3	18028	__I uint32_t STATUS;
sahilmgandhi	18:6a4db94011d3	18029
sahilmgandhi	18:6a4db94011d3	18030	} OTG_T;
sahilmgandhi	18:6a4db94011d3	18031
sahilmgandhi	18:6a4db94011d3	18032	/**
sahilmgandhi	18:6a4db94011d3	18033	@addtogroup OTG_CONST OTG Bit Field Definition
sahilmgandhi	18:6a4db94011d3	18034	Constant Definitions for OTG Controller
sahilmgandhi	18:6a4db94011d3	18035	@{ */
sahilmgandhi	18:6a4db94011d3	18036
sahilmgandhi	18:6a4db94011d3	18037	#define OTG_CTL_VBUSDROP_Pos (0) /!< OTG CTL: VBUSDROP Position /
sahilmgandhi	18:6a4db94011d3	18038	#define OTG_CTL_VBUSDROP_Msk (0x1ul << OTG_CTL_VBUSDROP_Pos) /!< OTG CTL: VBUSDROP Mask /
sahilmgandhi	18:6a4db94011d3	18039
sahilmgandhi	18:6a4db94011d3	18040	#define OTG_CTL_BUSREQ_Pos (1) /!< OTG CTL: BUSREQ Position /
sahilmgandhi	18:6a4db94011d3	18041	#define OTG_CTL_BUSREQ_Msk (0x1ul << OTG_CTL_BUSREQ_Pos) /!< OTG CTL: BUSREQ Mask /
sahilmgandhi	18:6a4db94011d3	18042
sahilmgandhi	18:6a4db94011d3	18043	#define OTG_CTL_HNPREQEN_Pos (2) /!< OTG CTL: HNPREQEN Position /
sahilmgandhi	18:6a4db94011d3	18044	#define OTG_CTL_HNPREQEN_Msk (0x1ul << OTG_CTL_HNPREQEN_Pos) /!< OTG CTL: HNPREQEN Mask /
sahilmgandhi	18:6a4db94011d3	18045
sahilmgandhi	18:6a4db94011d3	18046	#define OTG_CTL_OTGEN_Pos (4) /!< OTG CTL: OTGEN Position /
sahilmgandhi	18:6a4db94011d3	18047	#define OTG_CTL_OTGEN_Msk (0x1ul << OTG_CTL_OTGEN_Pos) /!< OTG CTL: OTGEN Mask /
sahilmgandhi	18:6a4db94011d3	18048
sahilmgandhi	18:6a4db94011d3	18049	#define OTG_CTL_PDEVCKON_Pos (7) /!< OTG CTL: PDEVCKON Position /
sahilmgandhi	18:6a4db94011d3	18050	#define OTG_CTL_PDEVCKON_Msk (0x1ul << OTG_CTL_PDEVCKON_Pos) /!< OTG CTL: PDEVCKON Mask /
sahilmgandhi	18:6a4db94011d3	18051
sahilmgandhi	18:6a4db94011d3	18052	#define OTG_CTL_WKEN_Pos (8) /!< OTG CTL: WKEN Position /
sahilmgandhi	18:6a4db94011d3	18053	#define OTG_CTL_WKEN_Msk (0x1ul << OTG_CTL_WKEN_Pos) /!< OTG CTL: WKEN Mask /
sahilmgandhi	18:6a4db94011d3	18054
sahilmgandhi	18:6a4db94011d3	18055	#define OTG_PHYCTL_SWPDEN_Pos (0) /!< OTG PHYCTL: SWPDEN Position /
sahilmgandhi	18:6a4db94011d3	18056	#define OTG_PHYCTL_SWPDEN_Msk (0x1ul << OTG_PHYCTL_SWPDEN_Pos) /!< OTG PHYCTL: SWPDEN Mask /
sahilmgandhi	18:6a4db94011d3	18057
sahilmgandhi	18:6a4db94011d3	18058	#define OTG_PHYCTL_DPPDEN_Pos (1) /!< OTG PHYCTL: DPPDEN Position /
sahilmgandhi	18:6a4db94011d3	18059	#define OTG_PHYCTL_DPPDEN_Msk (0x1ul << OTG_PHYCTL_DPPDEN_Pos) /!< OTG PHYCTL: DPPDEN Mask /
sahilmgandhi	18:6a4db94011d3	18060
sahilmgandhi	18:6a4db94011d3	18061	#define OTG_PHYCTL_DMPDEN_Pos (2) /!< OTG PHYCTL: DMPDEN Position /
sahilmgandhi	18:6a4db94011d3	18062	#define OTG_PHYCTL_DMPDEN_Msk (0x1ul << OTG_PHYCTL_DMPDEN_Pos) /!< OTG PHYCTL: DMPDEN Mask /
sahilmgandhi	18:6a4db94011d3	18063
sahilmgandhi	18:6a4db94011d3	18064	#define OTG_PHYCTL_VBSTSPOL_Pos (5) /!< OTG PHYCTL: VBSTSPOL Position /
sahilmgandhi	18:6a4db94011d3	18065	#define OTG_PHYCTL_VBSTSPOL_Msk (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos) /!< OTG PHYCTL: VBSTSPOL Mask /
sahilmgandhi	18:6a4db94011d3	18066
sahilmgandhi	18:6a4db94011d3	18067	#define OTG_PHYCTL_VBENPOL_Pos (6) /!< OTG PHYCTL: VBUSPOL Position /
sahilmgandhi	18:6a4db94011d3	18068	#define OTG_PHYCTL_VBENPOL_Msk (0x1ul << OTG_PHYCTL_VBENPOL_Pos) /!< OTG PHYCTL: VBUSPOL Mask /
sahilmgandhi	18:6a4db94011d3	18069
sahilmgandhi	18:6a4db94011d3	18070	#define OTG_PHYCTL_IDDETEN_Pos (7) /!< OTG PHYCTL: IDDETEN Position /
sahilmgandhi	18:6a4db94011d3	18071	#define OTG_PHYCTL_IDDETEN_Msk (0x1ul << OTG_PHYCTL_IDDETEN_Pos) /!< OTG PHYCTL: IDDETEN Mask /
sahilmgandhi	18:6a4db94011d3	18072
sahilmgandhi	18:6a4db94011d3	18073	#define OTG_PHYCTL_PHYCLK_Pos (8) /!< OTG PHYCTL: PHYCLK Position /
sahilmgandhi	18:6a4db94011d3	18074	#define OTG_PHYCTL_PHYCLK_Msk (0x1ul << OTG_PHYCTL_PHYCLK_Pos) /!< OTG PHYCTL: PHYCLK Mask /
sahilmgandhi	18:6a4db94011d3	18075
sahilmgandhi	18:6a4db94011d3	18076	#define OTG_PHYCTL_OTGPHYEN_Pos (9) /!< OTG PHYCTL: OTGPHYEN Position /
sahilmgandhi	18:6a4db94011d3	18077	#define OTG_PHYCTL_OTGPHYEN_Msk (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos) /!< OTG PHYCTL: OTGPHYEN Mask /
sahilmgandhi	18:6a4db94011d3	18078
sahilmgandhi	18:6a4db94011d3	18079	#define OTG_INTEN_ROLECHGIEN_Pos (0) /!< OTG INTEN: ROLECHGIEN Position /
sahilmgandhi	18:6a4db94011d3	18080	#define OTG_INTEN_ROLECHGIEN_Msk (0x1ul << OTG_INTEN_ROLECHGIEN_Pos) /!< OTG INTEN: ROLECHGIEN Mask /
sahilmgandhi	18:6a4db94011d3	18081
sahilmgandhi	18:6a4db94011d3	18082	#define OTG_INTEN_VBEIEN_Pos (1) /!< OTG INTEN: VBEIEN Position /
sahilmgandhi	18:6a4db94011d3	18083	#define OTG_INTEN_VBEIEN_Msk (0x1ul << OTG_INTEN_VBEIEN_Pos) /!< OTG INTEN: VBEIEN Mask /
sahilmgandhi	18:6a4db94011d3	18084
sahilmgandhi	18:6a4db94011d3	18085	#define OTG_INTEN_SRPFIEN_Pos (2) /!< OTG INTEN: SRPFIEN Position /
sahilmgandhi	18:6a4db94011d3	18086	#define OTG_INTEN_SRPFIEN_Msk (0x1ul << OTG_INTEN_SRPFIEN_Pos) /!< OTG INTEN: SRPFIEN Mask /
sahilmgandhi	18:6a4db94011d3	18087
sahilmgandhi	18:6a4db94011d3	18088	#define OTG_INTEN_HNPFIEN_Pos (3) /!< OTG INTEN: HNPFIEN Position /
sahilmgandhi	18:6a4db94011d3	18089	#define OTG_INTEN_HNPFIEN_Msk (0x1ul << OTG_INTEN_HNPFIEN_Pos) /!< OTG INTEN: HNPFIEN Mask /
sahilmgandhi	18:6a4db94011d3	18090
sahilmgandhi	18:6a4db94011d3	18091	#define OTG_INTEN_GOIDLEIEN_Pos (4) /!< OTG INTEN: GOIDLEIEN Position /
sahilmgandhi	18:6a4db94011d3	18092	#define OTG_INTEN_GOIDLEIEN_Msk (0x1ul << OTG_INTEN_GOIDLEIEN_Pos) /!< OTG INTEN: GOIDLEIEN Mask /
sahilmgandhi	18:6a4db94011d3	18093
sahilmgandhi	18:6a4db94011d3	18094	#define OTG_INTEN_IDCHGIEN_Pos (5) /!< OTG INTEN: IDCHGIEN Position /
sahilmgandhi	18:6a4db94011d3	18095	#define OTG_INTEN_IDCHGIEN_Msk (0x1ul << OTG_INTEN_IDCHGIEN_Pos) /!< OTG INTEN: IDCHGIEN Mask /
sahilmgandhi	18:6a4db94011d3	18096
sahilmgandhi	18:6a4db94011d3	18097	#define OTG_INTEN_PDEVIEN_Pos (6) /!< OTG INTEN: PDEVIEN Position /
sahilmgandhi	18:6a4db94011d3	18098	#define OTG_INTEN_PDEVIEN_Msk (0x1ul << OTG_INTEN_PDEVIEN_Pos) /!< OTG INTEN: PDEVIEN Mask /
sahilmgandhi	18:6a4db94011d3	18099
sahilmgandhi	18:6a4db94011d3	18100	#define OTG_INTEN_HOSTIEN_Pos (7) /!< OTG INTEN: HOSTIEN Position /
sahilmgandhi	18:6a4db94011d3	18101	#define OTG_INTEN_HOSTIEN_Msk (0x1ul << OTG_INTEN_HOSTIEN_Pos) /!< OTG INTEN: HOSTIEN Mask /
sahilmgandhi	18:6a4db94011d3	18102
sahilmgandhi	18:6a4db94011d3	18103	#define OTG_INTEN_BVLDCHGIEN_Pos (8) /!< OTG INTEN: BVLDCHGIEN Position /
sahilmgandhi	18:6a4db94011d3	18104	#define OTG_INTEN_BVLDCHGIEN_Msk (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos) /!< OTG INTEN: BVLDCHGIEN Mask /
sahilmgandhi	18:6a4db94011d3	18105
sahilmgandhi	18:6a4db94011d3	18106	#define OTG_INTEN_AVLDCHGIEN_Pos (9) /!< OTG INTEN: AVLDCHGIEN Position /
sahilmgandhi	18:6a4db94011d3	18107	#define OTG_INTEN_AVLDCHGIEN_Msk (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos) /!< OTG INTEN: AVLDCHGIEN Mask /
sahilmgandhi	18:6a4db94011d3	18108
sahilmgandhi	18:6a4db94011d3	18109	#define OTG_INTEN_VBCHGIEN_Pos (10) /!< OTG INTEN: VBCHGIEN Position /
sahilmgandhi	18:6a4db94011d3	18110	#define OTG_INTEN_VBCHGIEN_Msk (0x1ul << OTG_INTEN_VBCHGIEN_Pos) /!< OTG INTEN: VBCHGIEN Mask /
sahilmgandhi	18:6a4db94011d3	18111
sahilmgandhi	18:6a4db94011d3	18112	#define OTG_INTEN_SECHGIEN_Pos (11) /!< OTG INTEN: SECHGIEN Position /
sahilmgandhi	18:6a4db94011d3	18113	#define OTG_INTEN_SECHGIEN_Msk (0x1ul << OTG_INTEN_SECHGIEN_Pos) /!< OTG INTEN: SECHGIEN Mask /
sahilmgandhi	18:6a4db94011d3	18114
sahilmgandhi	18:6a4db94011d3	18115	#define OTG_INTEN_SRPDETIEN_Pos (13) /!< OTG INTEN: SRPDETIEN Position /
sahilmgandhi	18:6a4db94011d3	18116	#define OTG_INTEN_SRPDETIEN_Msk (0x1ul << OTG_INTEN_SRPDETIEN_Pos) /!< OTG INTEN: SRPDETIEN Mask /
sahilmgandhi	18:6a4db94011d3	18117
sahilmgandhi	18:6a4db94011d3	18118	#define OTG_INTSTS_ROLECHGIF_Pos (0) /!< OTG INTSTS: ROLECHGIF Position /
sahilmgandhi	18:6a4db94011d3	18119	#define OTG_INTSTS_ROLECHGIF_Msk (0x1ul << OTG_INTSTS_ROLECHGIF_Pos) /!< OTG INTSTS: ROLECHGIF Mask /
sahilmgandhi	18:6a4db94011d3	18120
sahilmgandhi	18:6a4db94011d3	18121	#define OTG_INTSTS_VBEIF_Pos (1) /!< OTG INTSTS: VBEIF Position /
sahilmgandhi	18:6a4db94011d3	18122	#define OTG_INTSTS_VBEIF_Msk (0x1ul << OTG_INTSTS_VBEIF_Pos) /!< OTG INTSTS: VBEIF Mask /
sahilmgandhi	18:6a4db94011d3	18123
sahilmgandhi	18:6a4db94011d3	18124	#define OTG_INTSTS_SRPFIF_Pos (2) /!< OTG INTSTS: SRPFIF Position /
sahilmgandhi	18:6a4db94011d3	18125	#define OTG_INTSTS_SRPFIF_Msk (0x1ul << OTG_INTSTS_SRPFIF_Pos) /!< OTG INTSTS: SRPFIF Mask /
sahilmgandhi	18:6a4db94011d3	18126
sahilmgandhi	18:6a4db94011d3	18127	#define OTG_INTSTS_HNPFIF_Pos (3) /!< OTG INTSTS: HNPFIF Position /
sahilmgandhi	18:6a4db94011d3	18128	#define OTG_INTSTS_HNPFIF_Msk (0x1ul << OTG_INTSTS_HNPFIF_Pos) /!< OTG INTSTS: HNPFIF Mask /
sahilmgandhi	18:6a4db94011d3	18129
sahilmgandhi	18:6a4db94011d3	18130	#define OTG_INTSTS_GOIDLEIF_Pos (4) /!< OTG INTSTS: GOIDLEIF Position /
sahilmgandhi	18:6a4db94011d3	18131	#define OTG_INTSTS_GOIDLEIF_Msk (0x1ul << OTG_INTSTS_GOIDLEIF_Pos) /!< OTG INTSTS: GOIDLEIF Mask /
sahilmgandhi	18:6a4db94011d3	18132
sahilmgandhi	18:6a4db94011d3	18133	#define OTG_INTSTS_IDCHGIF_Pos (5) /!< OTG INTSTS: IDCHGIF Position /
sahilmgandhi	18:6a4db94011d3	18134	#define OTG_INTSTS_IDCHGIF_Msk (0x1ul << OTG_INTSTS_IDCHGIF_Pos) /!< OTG INTSTS: IDCHGIF Mask /
sahilmgandhi	18:6a4db94011d3	18135
sahilmgandhi	18:6a4db94011d3	18136	#define OTG_INTSTS_PDEVIF_Pos (6) /!< OTG INTSTS: PDEVIF Position /
sahilmgandhi	18:6a4db94011d3	18137	#define OTG_INTSTS_PDEVIF_Msk (0x1ul << OTG_INTSTS_PDEVIF_Pos) /!< OTG INTSTS: PDEVIF Mask /
sahilmgandhi	18:6a4db94011d3	18138
sahilmgandhi	18:6a4db94011d3	18139	#define OTG_INTSTS_HOSTIF_Pos (7) /!< OTG INTSTS: HOSTIF Position /
sahilmgandhi	18:6a4db94011d3	18140	#define OTG_INTSTS_HOSTIF_Msk (0x1ul << OTG_INTSTS_HOSTIF_Pos) /!< OTG INTSTS: HOSTIF Mask /
sahilmgandhi	18:6a4db94011d3	18141
sahilmgandhi	18:6a4db94011d3	18142	#define OTG_INTSTS_BVLDCHGIF_Pos (8) /!< OTG INTSTS: BVLDCHGIF Position /
sahilmgandhi	18:6a4db94011d3	18143	#define OTG_INTSTS_BVLDCHGIF_Msk (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos) /!< OTG INTSTS: BVLDCHGIF Mask /
sahilmgandhi	18:6a4db94011d3	18144
sahilmgandhi	18:6a4db94011d3	18145	#define OTG_INTSTS_AVLDCHGIF_Pos (9) /!< OTG INTSTS: AVLDCHGIF Position /
sahilmgandhi	18:6a4db94011d3	18146	#define OTG_INTSTS_AVLDCHGIF_Msk (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos) /!< OTG INTSTS: AVLDCHGIF Mask /
sahilmgandhi	18:6a4db94011d3	18147
sahilmgandhi	18:6a4db94011d3	18148	#define OTG_INTSTS_VBCHGIF_Pos (10) /!< OTG INTSTS: VBCHGIF Position /
sahilmgandhi	18:6a4db94011d3	18149	#define OTG_INTSTS_VBCHGIF_Msk (0x1ul << OTG_INTSTS_VBCHGIF_Pos) /!< OTG INTSTS: VBCHGIF Mask /
sahilmgandhi	18:6a4db94011d3	18150
sahilmgandhi	18:6a4db94011d3	18151	#define OTG_INTSTS_SECHGIF_Pos (11) /!< OTG INTSTS: SECHGIF Position /
sahilmgandhi	18:6a4db94011d3	18152	#define OTG_INTSTS_SECHGIF_Msk (0x1ul << OTG_INTSTS_SECHGIF_Pos) /!< OTG INTSTS: SECHGIF Mask /
sahilmgandhi	18:6a4db94011d3	18153
sahilmgandhi	18:6a4db94011d3	18154	#define OTG_INTSTS_SRPDETIF_Pos (13) /!< OTG INTSTS: SRPDETIF Position /
sahilmgandhi	18:6a4db94011d3	18155	#define OTG_INTSTS_SRPDETIF_Msk (0x1ul << OTG_INTSTS_SRPDETIF_Pos) /!< OTG INTSTS: SRPDETIF Mask /
sahilmgandhi	18:6a4db94011d3	18156
sahilmgandhi	18:6a4db94011d3	18157	#define OTG_STATUS_OVERCUR_Pos (0) /!< OTG STATUS: OVERCUR Position /
sahilmgandhi	18:6a4db94011d3	18158	#define OTG_STATUS_OVERCUR_Msk (0x1ul << OTG_STATUS_OVERCUR_Pos) /!< OTG STATUS: OVERCUR Mask /
sahilmgandhi	18:6a4db94011d3	18159
sahilmgandhi	18:6a4db94011d3	18160	#define OTG_STATUS_IDSTS_Pos (1) /!< OTG STATUS: IDSTS Position /
sahilmgandhi	18:6a4db94011d3	18161	#define OTG_STATUS_IDSTS_Msk (0x1ul << OTG_STATUS_IDSTS_Pos) /!< OTG STATUS: IDSTS Mask /
sahilmgandhi	18:6a4db94011d3	18162
sahilmgandhi	18:6a4db94011d3	18163	#define OTG_STATUS_SESSEND_Pos (2) /!< OTG STATUS: SESSEND Position /
sahilmgandhi	18:6a4db94011d3	18164	#define OTG_STATUS_SESSEND_Msk (0x1ul << OTG_STATUS_SESSEND_Pos) /!< OTG STATUS: SESSEND Mask /
sahilmgandhi	18:6a4db94011d3	18165
sahilmgandhi	18:6a4db94011d3	18166	#define OTG_STATUS_BVLD_Pos (3) /!< OTG STATUS: BVLD Position /
sahilmgandhi	18:6a4db94011d3	18167	#define OTG_STATUS_BVLD_Msk (0x1ul << OTG_STATUS_BVLD_Pos) /!< OTG STATUS: BVLD Mask /
sahilmgandhi	18:6a4db94011d3	18168
sahilmgandhi	18:6a4db94011d3	18169	#define OTG_STATUS_AVLD_Pos (4) /!< OTG STATUS: AVLD Position /
sahilmgandhi	18:6a4db94011d3	18170	#define OTG_STATUS_AVLD_Msk (0x1ul << OTG_STATUS_AVLD_Pos) /!< OTG STATUS: AVLD Mask /
sahilmgandhi	18:6a4db94011d3	18171
sahilmgandhi	18:6a4db94011d3	18172	#define OTG_STATUS_VBUSVLD_Pos (5) /!< OTG STATUS: VBUSVLD Position /
sahilmgandhi	18:6a4db94011d3	18173	#define OTG_STATUS_VBUSVLD_Msk (0x1ul << OTG_STATUS_VBUSVLD_Pos) /!< OTG STATUS: VBUSVLD Mask /
sahilmgandhi	18:6a4db94011d3	18174
sahilmgandhi	18:6a4db94011d3	18175	/*@}/ /* OTG_CONST */
sahilmgandhi	18:6a4db94011d3	18176	/*@}/ /* end of OTG register group */
sahilmgandhi	18:6a4db94011d3	18177
sahilmgandhi	18:6a4db94011d3	18178
sahilmgandhi	18:6a4db94011d3	18179	/---------------------- Peripheral Direct Memory Access Controller -------------------------/
sahilmgandhi	18:6a4db94011d3	18180	/**
sahilmgandhi	18:6a4db94011d3	18181	@addtogroup PDMA Peripheral Direct Memory Access Controller(PDMA)
sahilmgandhi	18:6a4db94011d3	18182	Memory Mapped Structure for PDMA Controller
sahilmgandhi	18:6a4db94011d3	18183	@{ */
sahilmgandhi	18:6a4db94011d3	18184
sahilmgandhi	18:6a4db94011d3	18185	typedef struct {
sahilmgandhi	18:6a4db94011d3	18186
sahilmgandhi	18:6a4db94011d3	18187	/**
sahilmgandhi	18:6a4db94011d3	18188	* DSCTx_CTL
sahilmgandhi	18:6a4db94011d3	18189	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18190	* Offset: 0x00 Descriptor Table Control Register of PDMA Channel x
sahilmgandhi	18:6a4db94011d3	18191	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18192	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18193	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18194	* \|[0:1] \|OPMODE \|PDMA Operation Mode Selection
sahilmgandhi	18:6a4db94011d3	18195	* \| \| \|00 = Stop Mode.
sahilmgandhi	18:6a4db94011d3	18196	* \| \| \|Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to stop mode automatically.
sahilmgandhi	18:6a4db94011d3	18197	* \| \| \|01 = Basic Mode.
sahilmgandhi	18:6a4db94011d3	18198	* \| \| \|The descriptor table only has one task.
sahilmgandhi	18:6a4db94011d3	18199	* \| \| \|When this task is finished, the PDMA_INTSTS[x] will be asserted.
sahilmgandhi	18:6a4db94011d3	18200	* \| \| \|10 = Scatter-Gather Mode.
sahilmgandhi	18:6a4db94011d3	18201	* \| \| \|When operating in this mode, user must give the next descriptor table address in EMBTA_NTAAR register; PDMA will ignore this task, and then load the next task to execute.
sahilmgandhi	18:6a4db94011d3	18202	* \| \| \|Note: Before filling transfer task in the descriptor table, user must check if the descriptor table is complete.
sahilmgandhi	18:6a4db94011d3	18203	* \|[2] \|TXTYPE \|Request Type
sahilmgandhi	18:6a4db94011d3	18204	* \| \| \|0 = Burst request type.
sahilmgandhi	18:6a4db94011d3	18205	* \| \| \|1 = Single request type.
sahilmgandhi	18:6a4db94011d3	18206	* \|[4:6] \|BURSIZE \|Burst Size
sahilmgandhi	18:6a4db94011d3	18207	* \| \| \|This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.
sahilmgandhi	18:6a4db94011d3	18208	* \| \| \|But if in Single Request Type, this field is not useful and only 1 transfer item been transmitted for each transfer.
sahilmgandhi	18:6a4db94011d3	18209	* \| \| \|000 = 128 transfers.
sahilmgandhi	18:6a4db94011d3	18210	* \| \| \|001 = 64 transfers.
sahilmgandhi	18:6a4db94011d3	18211	* \| \| \|010 = 32 transfers.
sahilmgandhi	18:6a4db94011d3	18212	* \| \| \|011 = 16 transfers.
sahilmgandhi	18:6a4db94011d3	18213	* \| \| \|100 = 8 transfers.
sahilmgandhi	18:6a4db94011d3	18214	* \| \| \|101 = 4 transfers.
sahilmgandhi	18:6a4db94011d3	18215	* \| \| \|110 = 2 transfers.
sahilmgandhi	18:6a4db94011d3	18216	* \| \| \|111 = 1 transfers.
sahilmgandhi	18:6a4db94011d3	18217	* \|[7] \|TBINTDIS \|Table Interrupt Disable Control
sahilmgandhi	18:6a4db94011d3	18218	* \| \| \|This field can be used to decide whether to enable table interrupt or not.
sahilmgandhi	18:6a4db94011d3	18219	* \| \| \|When with transfer done flag, this bit is only used for scatter-gather mode.
sahilmgandhi	18:6a4db94011d3	18220	* \| \| \|If the TBINTDIS bit is enabled when PDMA finishes this task, there will no any interrupt generated.
sahilmgandhi	18:6a4db94011d3	18221	* \| \| \|However, with the table empty flag, this bit is also useful.
sahilmgandhi	18:6a4db94011d3	18222	* \| \| \|If it is set to '1', the TEMPTYF will not be set when this situation has happened.
sahilmgandhi	18:6a4db94011d3	18223	* \| \| \|0 = Table interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	18224	* \| \| \|1 = Table interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	18225	* \|[8:9] \|SAINC \|Source Address Increment
sahilmgandhi	18:6a4db94011d3	18226	* \| \| \|This field is used to set the source address increment size
sahilmgandhi	18:6a4db94011d3	18227	* \| \| \|11 = No Increment (Fixed Address.).
sahilmgandhi	18:6a4db94011d3	18228	* \| \| \|Other = Increment and size is depended on TXWIDTH selection.
sahilmgandhi	18:6a4db94011d3	18229	* \|[10:11] \|DAINC \|Destination Address Increment
sahilmgandhi	18:6a4db94011d3	18230	* \| \| \|This field is used to set the destination address increment size
sahilmgandhi	18:6a4db94011d3	18231	* \| \| \|11 = No Increment (Fixed Address.).
sahilmgandhi	18:6a4db94011d3	18232	* \| \| \|Other = Increment and size is depended on TXWIDTH selection.
sahilmgandhi	18:6a4db94011d3	18233	* \|[12:13] \|TXWIDTH \|Transfer Width Selection
sahilmgandhi	18:6a4db94011d3	18234	* \| \| \|This field is used for transfer width.
sahilmgandhi	18:6a4db94011d3	18235	* \| \| \|00 = 8 bits for every transfer item.
sahilmgandhi	18:6a4db94011d3	18236	* \| \| \|01 = 16 bits for every transfer item.
sahilmgandhi	18:6a4db94011d3	18237	* \| \| \|10 = 32 bits for every transfer item.
sahilmgandhi	18:6a4db94011d3	18238	* \| \| \|11 = Reserved.
sahilmgandhi	18:6a4db94011d3	18239	* \| \| \|Note: The PDMA transfer source address (EMBTA_ENDSAR) and PDMA transfer destination address (EMBTA_ENDDAR) should be alignment under the TXWIDTH selection
sahilmgandhi	18:6a4db94011d3	18240	* \|[16:29] \|TXCNT \|Transfer Count
sahilmgandhi	18:6a4db94011d3	18241	* \| \| \|The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field.
sahilmgandhi	18:6a4db94011d3	18242	* \| \| \|Note: When PDMA finish each transfer item, this field will be decrease imminently
sahilmgandhi	18:6a4db94011d3	18243	*/
sahilmgandhi	18:6a4db94011d3	18244	__IO uint32_t CTL;
sahilmgandhi	18:6a4db94011d3	18245
sahilmgandhi	18:6a4db94011d3	18246	/**
sahilmgandhi	18:6a4db94011d3	18247	* DSCTx_ENDSA
sahilmgandhi	18:6a4db94011d3	18248	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18249	* Offset: 0x04 End Source Address Register of PDMA Channel x
sahilmgandhi	18:6a4db94011d3	18250	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18251	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18252	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18253	* \|[0:31] \|ENDSA \|PDMA Transfer Ending Source Address Bits
sahilmgandhi	18:6a4db94011d3	18254	* \| \| \|This field indicates a 32-bit ending source address of PDMA.
sahilmgandhi	18:6a4db94011d3	18255	* \| \| \|Note: If the source start address is 0x2000_0000, the transfer count is 0x100 and the source address increment is word, this field must be filled 0x2000_0400.
sahilmgandhi	18:6a4db94011d3	18256	* \| \| \|The equation is "0x2000_0400 = 0x2000_0000 + 0x100*4(word)".
sahilmgandhi	18:6a4db94011d3	18257	*/
sahilmgandhi	18:6a4db94011d3	18258	__IO uint32_t ENDSA;
sahilmgandhi	18:6a4db94011d3	18259
sahilmgandhi	18:6a4db94011d3	18260	/**
sahilmgandhi	18:6a4db94011d3	18261	* DSCTx_ENDDA
sahilmgandhi	18:6a4db94011d3	18262	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18263	* Offset: 0x08 End Destination Address Register of PDMA Channel x
sahilmgandhi	18:6a4db94011d3	18264	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18265	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18266	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18267	* \|[0:31] \|ENDDA \|PDMA Transfer Ending Destination Address Bits
sahilmgandhi	18:6a4db94011d3	18268	* \| \| \|This field indicates a 32-bit ending destination address of PDMA.
sahilmgandhi	18:6a4db94011d3	18269	* \| \| \|Note: If the destination start address is 0x2000_0000, the transfer count is 0x100 and the destination address increment is word, this field must be filled 0x2000_0400.
sahilmgandhi	18:6a4db94011d3	18270	* \| \| \|The equation is "0x2000_0400 = 0x2000_0000 + 0x100*4(word)".
sahilmgandhi	18:6a4db94011d3	18271	*/
sahilmgandhi	18:6a4db94011d3	18272	__IO uint32_t ENDDA;
sahilmgandhi	18:6a4db94011d3	18273
sahilmgandhi	18:6a4db94011d3	18274	/**
sahilmgandhi	18:6a4db94011d3	18275	* DSCTx_NEXT
sahilmgandhi	18:6a4db94011d3	18276	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18277	* Offset: 0x0C Scatter-Gather Descriptor Table Offset Address of PDMA Channel x
sahilmgandhi	18:6a4db94011d3	18278	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18279	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18280	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18281	* \|[2:15] \|NEXT \|PDMA Next Description Table Offset Address Bits
sahilmgandhi	18:6a4db94011d3	18282	* \| \| \|This field indicates the offset of next descriptor table address in system memory.
sahilmgandhi	18:6a4db94011d3	18283	* \| \| \|Note1: The next descriptor table address must be word boundary.
sahilmgandhi	18:6a4db94011d3	18284	* \| \| \|Note2: The system memory based address is 0x2000_0000 (PDMA_ETADDR), if the next descriptor table is 0x2000_0100, that this field must fill 0x0100.
sahilmgandhi	18:6a4db94011d3	18285	* \| \| \|Note3: Before filled transfer task in the description table, user must check if the descriptor table is complete.
sahilmgandhi	18:6a4db94011d3	18286	*/
sahilmgandhi	18:6a4db94011d3	18287	__IO uint32_t NEXT;
sahilmgandhi	18:6a4db94011d3	18288
sahilmgandhi	18:6a4db94011d3	18289	} DSCT_T;
sahilmgandhi	18:6a4db94011d3	18290
sahilmgandhi	18:6a4db94011d3	18291	typedef struct {
sahilmgandhi	18:6a4db94011d3	18292	DSCT_T DSCT[16];
sahilmgandhi	18:6a4db94011d3	18293	uint32_t RESERVE0[192];
sahilmgandhi	18:6a4db94011d3	18294
sahilmgandhi	18:6a4db94011d3	18295	/**
sahilmgandhi	18:6a4db94011d3	18296	* CHCTL
sahilmgandhi	18:6a4db94011d3	18297	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18298	* Offset: 0x400 PDMA Channel Control Register
sahilmgandhi	18:6a4db94011d3	18299	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18300	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18301	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18302	* \|[0:15] \|CHEN \|PDMA Channel Enable Control Bit[X]
sahilmgandhi	18:6a4db94011d3	18303	* \| \| \|Set this bit to 1 to enable PDMA[x] operation.
sahilmgandhi	18:6a4db94011d3	18304	* \| \| \|0 = PDMA channel [x] Disabled.
sahilmgandhi	18:6a4db94011d3	18305	* \| \| \|1 = PDMA channel [x] Enabled.
sahilmgandhi	18:6a4db94011d3	18306	* \| \| \|Note1: If software stops each PDMA transfer by setting PDMA_STOP register, this bit will be cleared automatically after finishing current transfer.
sahilmgandhi	18:6a4db94011d3	18307	* \| \| \|Note2: Software reset (writing 0xFFFF_FFF to PDMA_STOP register) will clear this bit.
sahilmgandhi	18:6a4db94011d3	18308	* \| \| \|Note3: If each channel is not set as enabled, each channel cannot be active.
sahilmgandhi	18:6a4db94011d3	18309	*/
sahilmgandhi	18:6a4db94011d3	18310	__IO uint32_t CHCTL;
sahilmgandhi	18:6a4db94011d3	18311
sahilmgandhi	18:6a4db94011d3	18312	/**
sahilmgandhi	18:6a4db94011d3	18313	* STOP
sahilmgandhi	18:6a4db94011d3	18314	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18315	* Offset: 0x404 PDMA Stop Transfer Register
sahilmgandhi	18:6a4db94011d3	18316	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18317	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18318	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18319	* \|[0:15] \|STOP \|PDMA Stop Transfer Bit [X]
sahilmgandhi	18:6a4db94011d3	18320	* \| \| \|User can stop the PDMA transfer by software reset (writing all '1' to PDMA_STOP register) or by PDMA_STOP register.
sahilmgandhi	18:6a4db94011d3	18321	* \| \| \|The difference between software reset and PDMA_STOP register is when software set software reset, the operation will be stopped imminently that include the on-going transfer and the channel enable bit and request active flag will be cleared to '0'.
sahilmgandhi	18:6a4db94011d3	18322	* \| \| \|When software set PDMA_STOP bit, the operation will finish the on-going transfer channel and then clear the channel enable bit and request active flag.
sahilmgandhi	18:6a4db94011d3	18323	* \| \| \|Software can poll channel enable bit to know if the on-going transfer is finished.
sahilmgandhi	18:6a4db94011d3	18324	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	18325	* \| \| \|1 = Stop PDMA transfer[x].
sahilmgandhi	18:6a4db94011d3	18326	* \| \| \|Note1: This field is Write-Only
sahilmgandhi	18:6a4db94011d3	18327	* \| \| \|Note2: Setting all PDMA_STOP bit to "1" will generate software reset to reset internal state machine (the embedded table will not be reset).
sahilmgandhi	18:6a4db94011d3	18328	*/
sahilmgandhi	18:6a4db94011d3	18329	__O uint32_t STOP;
sahilmgandhi	18:6a4db94011d3	18330
sahilmgandhi	18:6a4db94011d3	18331	/**
sahilmgandhi	18:6a4db94011d3	18332	* SWREQ
sahilmgandhi	18:6a4db94011d3	18333	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18334	* Offset: 0x408 PDMA Software Request Register
sahilmgandhi	18:6a4db94011d3	18335	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18336	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18337	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18338	* \|[0:11] \|SWREQ \|PDMA Software Request Bit [X]
sahilmgandhi	18:6a4db94011d3	18339	* \| \| \|Set this bit to 1 to generate a software request to PDMA [x].
sahilmgandhi	18:6a4db94011d3	18340	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	18341	* \| \| \|1 = Generate a software request.
sahilmgandhi	18:6a4db94011d3	18342	* \| \| \|Note1: This field is Write-Only.
sahilmgandhi	18:6a4db94011d3	18343	* \| \| \|Software can indicate which channel is on active by reading PDMA_TRGSTS register.
sahilmgandhi	18:6a4db94011d3	18344	* \| \| \|Active flag may be triggered by software request or peripheral request.
sahilmgandhi	18:6a4db94011d3	18345	* \| \| \|Note2: If user does not enable each PDMA channel, the software request will be ignored.
sahilmgandhi	18:6a4db94011d3	18346	*/
sahilmgandhi	18:6a4db94011d3	18347	__O uint32_t SWREQ;
sahilmgandhi	18:6a4db94011d3	18348
sahilmgandhi	18:6a4db94011d3	18349	/**
sahilmgandhi	18:6a4db94011d3	18350	* TRGSTS
sahilmgandhi	18:6a4db94011d3	18351	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18352	* Offset: 0x40C PDMA Request Active Flag Register
sahilmgandhi	18:6a4db94011d3	18353	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18354	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18355	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18356	* \|[0:15] \|REQSTS \|PDMA Request Active Flag [X]
sahilmgandhi	18:6a4db94011d3	18357	* \| \| \|This flag indicates whether channel[x] have a request or not.
sahilmgandhi	18:6a4db94011d3	18358	* \| \| \|0 = Have no requests.
sahilmgandhi	18:6a4db94011d3	18359	* \| \| \|1 = Have a request.
sahilmgandhi	18:6a4db94011d3	18360	* \| \| \|Note1: The request may come from software request (SWREQ) or peripheral request.
sahilmgandhi	18:6a4db94011d3	18361	* \| \| \|Note2: When PDMA finishes channel transfer, this bit will be cleared automatically
sahilmgandhi	18:6a4db94011d3	18362	* \| \| \|Note3: Software reset (setting PDMA_STOP to 0xFFFF_FFFF) will clear this bit.
sahilmgandhi	18:6a4db94011d3	18363	*/
sahilmgandhi	18:6a4db94011d3	18364	__I uint32_t TRGSTS;
sahilmgandhi	18:6a4db94011d3	18365
sahilmgandhi	18:6a4db94011d3	18366	/**
sahilmgandhi	18:6a4db94011d3	18367	* PRISET
sahilmgandhi	18:6a4db94011d3	18368	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18369	* Offset: 0x410 PDMA Fixed Priority Setting Register
sahilmgandhi	18:6a4db94011d3	18370	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18371	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18372	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18373	* \|[0:15] \|FPRISET \|PDMA Fixed Priority Setting Bit[X]
sahilmgandhi	18:6a4db94011d3	18374	* \| \| \|Set this bit to 1 to enable fix priority level.
sahilmgandhi	18:6a4db94011d3	18375	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	18376	* \| \| \|1 = Set PDMA channel [x] be fixed priority channel.
sahilmgandhi	18:6a4db94011d3	18377	* \| \| \|The PDMA channel priority is shown in the following table.
sahilmgandhi	18:6a4db94011d3	18378	*/
sahilmgandhi	18:6a4db94011d3	18379	__IO uint32_t PRISET;
sahilmgandhi	18:6a4db94011d3	18380
sahilmgandhi	18:6a4db94011d3	18381	/**
sahilmgandhi	18:6a4db94011d3	18382	* PRICLR
sahilmgandhi	18:6a4db94011d3	18383	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18384	* Offset: 0x414 PDMA Fixed Priority Clear Register
sahilmgandhi	18:6a4db94011d3	18385	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18386	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18387	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18388	* \|[0:15] \|FPRICLR \|PDMA Fix Priority Clear Bit [X]
sahilmgandhi	18:6a4db94011d3	18389	* \| \| \|Set this bit to 1 to clear fixed priority level.
sahilmgandhi	18:6a4db94011d3	18390	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	18391	* \| \| \|1 = Set PDMA channel [x] to be round-robin priority channel.
sahilmgandhi	18:6a4db94011d3	18392	* \| \| \|Note: This field is Write-Only, and software can indicate the channel priority by reading PDMA_FPIOSEL register.
sahilmgandhi	18:6a4db94011d3	18393	*/
sahilmgandhi	18:6a4db94011d3	18394	__O uint32_t PRICLR;
sahilmgandhi	18:6a4db94011d3	18395
sahilmgandhi	18:6a4db94011d3	18396	/**
sahilmgandhi	18:6a4db94011d3	18397	* INTEN
sahilmgandhi	18:6a4db94011d3	18398	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18399	* Offset: 0x418 PDMA Interrupt Enable Control Register
sahilmgandhi	18:6a4db94011d3	18400	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18401	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18402	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18403	* \|[0:15] \|INTEN \|PDMA Interrupt Enable Control Register [X]
sahilmgandhi	18:6a4db94011d3	18404	* \| \| \|This field is used for enabling PDMA channel[x] interrupt.
sahilmgandhi	18:6a4db94011d3	18405	* \| \| \|0 = PDMA channel [x] interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	18406	* \| \| \|1 = PDMA channel [x] interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	18407	*/
sahilmgandhi	18:6a4db94011d3	18408	__IO uint32_t INTEN;
sahilmgandhi	18:6a4db94011d3	18409
sahilmgandhi	18:6a4db94011d3	18410	/**
sahilmgandhi	18:6a4db94011d3	18411	* INTSTS
sahilmgandhi	18:6a4db94011d3	18412	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18413	* Offset: 0x41C PDMA Interrupt Status Register
sahilmgandhi	18:6a4db94011d3	18414	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18415	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18416	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18417	* \|[0] \|ABTIF \|PDMA Read/Write Target Abort Interrupt Status Flag
sahilmgandhi	18:6a4db94011d3	18418	* \| \| \|This bit indicates that PDMA has target abort error; Software can read PDMA_TABORTF register to find which channel has target abort error.
sahilmgandhi	18:6a4db94011d3	18419	* \| \| \|0 = No bus ERROR response received.
sahilmgandhi	18:6a4db94011d3	18420	* \| \| \|1 = Bus ERROR response received.
sahilmgandhi	18:6a4db94011d3	18421	* \| \| \|Note: This field is read only.
sahilmgandhi	18:6a4db94011d3	18422	* \|[1] \|TDIF \|Transfer Done Interrupt Status Flag
sahilmgandhi	18:6a4db94011d3	18423	* \| \| \|This bit indicates that PDMA has finished transmission; Software can read PDMA_TDSTS register to indicate which channel finished transfer.
sahilmgandhi	18:6a4db94011d3	18424	* \| \| \|0 = Not finished yet.
sahilmgandhi	18:6a4db94011d3	18425	* \| \| \|1 = PDMA channel has finished transmission.
sahilmgandhi	18:6a4db94011d3	18426	* \| \| \|Note: This field is Read only.
sahilmgandhi	18:6a4db94011d3	18427	* \|[2] \|TEIF \|Table Empty Interrupt Status Flag
sahilmgandhi	18:6a4db94011d3	18428	* \| \| \|This bit indicates that PDMA has finished each table transmission and the operation is Stop mode.
sahilmgandhi	18:6a4db94011d3	18429	* \| \| \|Software can read TEIF register to indicate which channel finished transfer.
sahilmgandhi	18:6a4db94011d3	18430	* \| \| \|0 = Not finished yet.
sahilmgandhi	18:6a4db94011d3	18431	* \| \| \|1 = PDMA channel has finished and the operation is Stop mode.
sahilmgandhi	18:6a4db94011d3	18432	* \| \| \|Note: This field is Read only.
sahilmgandhi	18:6a4db94011d3	18433	* \|[8:23] \|REQTOFX \|Time-Out Status Flag For Each Channel
sahilmgandhi	18:6a4db94011d3	18434	* \| \| \|This flag indicates that PDMA has waited peripheral request for a period defined by TIMECNTX
sahilmgandhi	18:6a4db94011d3	18435	* \| \| \|0 = No time-out flag.
sahilmgandhi	18:6a4db94011d3	18436	* \| \| \|1 = Time-out flag.
sahilmgandhi	18:6a4db94011d3	18437	* \| \| \|Note: This field is Read only, but software can write 1 to clear it.
sahilmgandhi	18:6a4db94011d3	18438	*/
sahilmgandhi	18:6a4db94011d3	18439	__IO uint32_t INTSTS;
sahilmgandhi	18:6a4db94011d3	18440
sahilmgandhi	18:6a4db94011d3	18441	/**
sahilmgandhi	18:6a4db94011d3	18442	* ABTSTS
sahilmgandhi	18:6a4db94011d3	18443	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18444	* Offset: 0x420 PDMA Read/Write Target Abort Flag Register
sahilmgandhi	18:6a4db94011d3	18445	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18446	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18447	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18448	* \|[0:15] \|ABTIF \|PDMA Read/Write Target Abort Interrupt Status Flag
sahilmgandhi	18:6a4db94011d3	18449	* \| \| \|This bit indicates which PDMA has target abort error
sahilmgandhi	18:6a4db94011d3	18450	* \| \| \|0 = No bus ERROR response received.
sahilmgandhi	18:6a4db94011d3	18451	* \| \| \|1 = Bus ERROR response received.
sahilmgandhi	18:6a4db94011d3	18452	* \| \| \|Note: This field is read only, but software can write 1 to clear it.
sahilmgandhi	18:6a4db94011d3	18453	*/
sahilmgandhi	18:6a4db94011d3	18454	__IO uint32_t ABTSTS;
sahilmgandhi	18:6a4db94011d3	18455
sahilmgandhi	18:6a4db94011d3	18456	/**
sahilmgandhi	18:6a4db94011d3	18457	* TDSTS
sahilmgandhi	18:6a4db94011d3	18458	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18459	* Offset: 0x424 PDMA Transfer Done Flag Register
sahilmgandhi	18:6a4db94011d3	18460	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18461	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18462	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18463	* \|[0:15] \|TDIF \|Transfer Done Flag [X]
sahilmgandhi	18:6a4db94011d3	18464	* \| \| \|This bit indicates which PDMA channel has finished transmission.
sahilmgandhi	18:6a4db94011d3	18465	* \| \| \|0 = Not finished yet.
sahilmgandhi	18:6a4db94011d3	18466	* \| \| \|1 = PDMA channel has finished transmission.
sahilmgandhi	18:6a4db94011d3	18467	* \| \| \|Note: This field is read only, but software can write 1 to clear.
sahilmgandhi	18:6a4db94011d3	18468	*/
sahilmgandhi	18:6a4db94011d3	18469	__IO uint32_t TDSTS;
sahilmgandhi	18:6a4db94011d3	18470
sahilmgandhi	18:6a4db94011d3	18471	/**
sahilmgandhi	18:6a4db94011d3	18472	* SCATSTS
sahilmgandhi	18:6a4db94011d3	18473	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18474	* Offset: 0x428 PDMA Scatter-Gather Transfer Done Flag Register
sahilmgandhi	18:6a4db94011d3	18475	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18476	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18477	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18478	* \|[0:15] \|TEMPTYF \|Table Empty Flag Bit [X]
sahilmgandhi	18:6a4db94011d3	18479	* \| \| \|This bit indicates which PDMA channel table has finished transmission and the operation mode is Stop mode
sahilmgandhi	18:6a4db94011d3	18480	* \| \| \|0 = Not finished or not in Stop mode.
sahilmgandhi	18:6a4db94011d3	18481	* \| \| \|1 = PDMA channel has finished transmission and the operation is Stop mode.
sahilmgandhi	18:6a4db94011d3	18482	* \| \| \|Note: This field is read only, but software can write 1 to clear.
sahilmgandhi	18:6a4db94011d3	18483	*/
sahilmgandhi	18:6a4db94011d3	18484	__IO uint32_t SCATSTS;
sahilmgandhi	18:6a4db94011d3	18485
sahilmgandhi	18:6a4db94011d3	18486	/**
sahilmgandhi	18:6a4db94011d3	18487	* TACTSTS
sahilmgandhi	18:6a4db94011d3	18488	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18489	* Offset: 0x42C PDMA Transfer on Active Flag Register
sahilmgandhi	18:6a4db94011d3	18490	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18491	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18492	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18493	* \|[0:15] \|TXACTF \|Transfer On Active Flag Bit [X]
sahilmgandhi	18:6a4db94011d3	18494	* \| \| \|This bit indicates which PDMA channel is on active.
sahilmgandhi	18:6a4db94011d3	18495	* \| \| \|0 = PDMA channel is not finished.
sahilmgandhi	18:6a4db94011d3	18496	* \| \| \|1 = PDMA channel is on active.
sahilmgandhi	18:6a4db94011d3	18497	*/
sahilmgandhi	18:6a4db94011d3	18498	__I uint32_t TACTSTS;
sahilmgandhi	18:6a4db94011d3	18499	uint32_t RESERVE1[3];
sahilmgandhi	18:6a4db94011d3	18500
sahilmgandhi	18:6a4db94011d3	18501
sahilmgandhi	18:6a4db94011d3	18502	/**
sahilmgandhi	18:6a4db94011d3	18503	* SCATBA
sahilmgandhi	18:6a4db94011d3	18504	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18505	* Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register
sahilmgandhi	18:6a4db94011d3	18506	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18507	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18508	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18509	* \|[16:31] \|SCATBA \|PDMA Scatter-Gather Descriptor Table Base Address Bits
sahilmgandhi	18:6a4db94011d3	18510	* \| \| \|In Scatter-Gather mode, this is the base address for calculating the next link - list address.
sahilmgandhi	18:6a4db94011d3	18511	* \| \| \|The next link address equation is.
sahilmgandhi	18:6a4db94011d3	18512	* \| \| \|Next Link Address = { SCATBA[15:0], EMBTA_NTAAR[15:2], 2'b00}.
sahilmgandhi	18:6a4db94011d3	18513	* \| \| \|Note: Only useful in Scatter-Gather mode.
sahilmgandhi	18:6a4db94011d3	18514	*/
sahilmgandhi	18:6a4db94011d3	18515	__IO uint32_t SCATBA;
sahilmgandhi	18:6a4db94011d3	18516
sahilmgandhi	18:6a4db94011d3	18517	/**
sahilmgandhi	18:6a4db94011d3	18518	* TOC0_1
sahilmgandhi	18:6a4db94011d3	18519	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18520	* Offset: 0x440 PDMA Time-out Period Counter Ch1 and Ch0 Register
sahilmgandhi	18:6a4db94011d3	18521	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18522	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18523	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18524	* \|[0:15] \|TOC0 \|Time-Out Period Counter For Channel 0
sahilmgandhi	18:6a4db94011d3	18525	* \| \| \|This controls the period of time-out function for channel 0.
sahilmgandhi	18:6a4db94011d3	18526	* \| \| \|The calculation unit is based on 10 kHz clock.
sahilmgandhi	18:6a4db94011d3	18527	* \|[16:31] \|TOC1 \|Time-Out Period Counter For Channel 1
sahilmgandhi	18:6a4db94011d3	18528	* \| \| \|This controls the period of time-out function for channel 1.
sahilmgandhi	18:6a4db94011d3	18529	* \| \| \|The calculation unit is based on 10 kHz clock.
sahilmgandhi	18:6a4db94011d3	18530	*/
sahilmgandhi	18:6a4db94011d3	18531	__IO uint32_t TOC0_1;
sahilmgandhi	18:6a4db94011d3	18532
sahilmgandhi	18:6a4db94011d3	18533	/**
sahilmgandhi	18:6a4db94011d3	18534	* TOC2_3
sahilmgandhi	18:6a4db94011d3	18535	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18536	* Offset: 0x444 PDMA Time-out Period Counter Ch3 and Ch2 Register
sahilmgandhi	18:6a4db94011d3	18537	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18538	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18539	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18540	* \|[0:15] \|TOC2 \|Time-Out Period Counter For Channel 2
sahilmgandhi	18:6a4db94011d3	18541	* \| \| \|This controls the period of time-out function for channel 2.
sahilmgandhi	18:6a4db94011d3	18542	* \| \| \|The calculation unit is based on 10 kHz clock.
sahilmgandhi	18:6a4db94011d3	18543	* \|[16:31] \|TOC3 \|Time-Out Period Counter For Channel 3
sahilmgandhi	18:6a4db94011d3	18544	* \| \| \|This controls the period of time-out function for channel 3.
sahilmgandhi	18:6a4db94011d3	18545	* \| \| \|The calculation unit is based on 10 kHz clock.
sahilmgandhi	18:6a4db94011d3	18546	*/
sahilmgandhi	18:6a4db94011d3	18547	__IO uint32_t TOC2_3;
sahilmgandhi	18:6a4db94011d3	18548
sahilmgandhi	18:6a4db94011d3	18549	/**
sahilmgandhi	18:6a4db94011d3	18550	* TOC4_5
sahilmgandhi	18:6a4db94011d3	18551	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18552	* Offset: 0x448 PDMA Time-out Period Counter Ch5 and Ch4 Register
sahilmgandhi	18:6a4db94011d3	18553	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18554	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18555	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18556	* \|[0:15] \|TOC4 \|Time-Out Period Counter For Channel 4
sahilmgandhi	18:6a4db94011d3	18557	* \| \| \|This controls the period of time-out function for channel 4.
sahilmgandhi	18:6a4db94011d3	18558	* \| \| \|The calculation unit is based on 10 kHz clock.
sahilmgandhi	18:6a4db94011d3	18559	* \|[16:31] \|TOC5 \|Time-Out Period Counter For Channel 5
sahilmgandhi	18:6a4db94011d3	18560	* \| \| \|This controls the period of time-out function for channel 5.
sahilmgandhi	18:6a4db94011d3	18561	* \| \| \|The calculation unit is based on 10 kHz clock.
sahilmgandhi	18:6a4db94011d3	18562	*/
sahilmgandhi	18:6a4db94011d3	18563	__IO uint32_t TOC4_5;
sahilmgandhi	18:6a4db94011d3	18564
sahilmgandhi	18:6a4db94011d3	18565	/**
sahilmgandhi	18:6a4db94011d3	18566	* TOC6_7
sahilmgandhi	18:6a4db94011d3	18567	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18568	* Offset: 0x44C PDMA Time-out Period Counter Ch7 and Ch6 Register
sahilmgandhi	18:6a4db94011d3	18569	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18570	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18571	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18572	* \|[0:15] \|TOC6 \|Time-Out Period Counter For Channel 6
sahilmgandhi	18:6a4db94011d3	18573	* \| \| \|This controls the period of time-out function for channel 6.
sahilmgandhi	18:6a4db94011d3	18574	* \| \| \|The calculation unit is based on 10 kHz clock.
sahilmgandhi	18:6a4db94011d3	18575	* \|[16:31] \|TOC7 \|Time-Out Period Counter For Channel 7
sahilmgandhi	18:6a4db94011d3	18576	* \| \| \|This controls the period of time-out function for channel 7.
sahilmgandhi	18:6a4db94011d3	18577	* \| \| \|The calculation unit is based on 10 kHz clock.
sahilmgandhi	18:6a4db94011d3	18578	*/
sahilmgandhi	18:6a4db94011d3	18579	__IO uint32_t TOC6_7;
sahilmgandhi	18:6a4db94011d3	18580
sahilmgandhi	18:6a4db94011d3	18581	/**
sahilmgandhi	18:6a4db94011d3	18582	* TOC8_9
sahilmgandhi	18:6a4db94011d3	18583	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18584	* Offset: 0x450 PDMA Time-out Period Counter Ch9 and Ch8 Register
sahilmgandhi	18:6a4db94011d3	18585	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18586	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18587	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18588	* \|[0:15] \|TOC8 \|Time-Out Period Counter For Channel 8
sahilmgandhi	18:6a4db94011d3	18589	* \| \| \|This controls the period of time-out function for channel 8.
sahilmgandhi	18:6a4db94011d3	18590	* \| \| \|The calculation unit is based on 10 kHz clock.
sahilmgandhi	18:6a4db94011d3	18591	* \|[16:31] \|TOC9 \|Time-Out Period Counter For Channel 9
sahilmgandhi	18:6a4db94011d3	18592	* \| \| \|This controls the period of time-out function for channel 9.
sahilmgandhi	18:6a4db94011d3	18593	* \| \| \|The calculation unit is based on 10 kHz clock.
sahilmgandhi	18:6a4db94011d3	18594	*/
sahilmgandhi	18:6a4db94011d3	18595	__IO uint32_t TOC8_9;
sahilmgandhi	18:6a4db94011d3	18596
sahilmgandhi	18:6a4db94011d3	18597	/**
sahilmgandhi	18:6a4db94011d3	18598	* TOC10_11
sahilmgandhi	18:6a4db94011d3	18599	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18600	* Offset: 0x454 PDMA Time-out Period Counter Ch11 and Ch10 Register
sahilmgandhi	18:6a4db94011d3	18601	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18602	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18603	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18604	* \|[0:15] \|TOC10 \|Time-Out Period Counter For Channel 10
sahilmgandhi	18:6a4db94011d3	18605	* \| \| \|This controls the period of time-out function for channel 10.
sahilmgandhi	18:6a4db94011d3	18606	* \| \| \|The calculation unit is based on 10 kHz clock.
sahilmgandhi	18:6a4db94011d3	18607	* \|[16:31] \|TOC11 \|Time-Out Period Counter For Channel 11
sahilmgandhi	18:6a4db94011d3	18608	* \| \| \|This controls the period of time-out function for channel 11.
sahilmgandhi	18:6a4db94011d3	18609	* \| \| \|The calculation unit is based on 10 kHz clock.
sahilmgandhi	18:6a4db94011d3	18610	*/
sahilmgandhi	18:6a4db94011d3	18611	__IO uint32_t TOC10_11;
sahilmgandhi	18:6a4db94011d3	18612
sahilmgandhi	18:6a4db94011d3	18613	/**
sahilmgandhi	18:6a4db94011d3	18614	* TOC12_13
sahilmgandhi	18:6a4db94011d3	18615	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18616	* Offset: 0x458 PDMA Time-out Period Counter Ch13 and Ch12 Register
sahilmgandhi	18:6a4db94011d3	18617	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18618	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18619	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18620	* \|[0:15] \|TOC12 \|Time-Out Period Counter For Channel 12
sahilmgandhi	18:6a4db94011d3	18621	* \| \| \|This controls the period of time-out function for channel 12.
sahilmgandhi	18:6a4db94011d3	18622	* \| \| \|The calculation unit is based on 10 kHz clock.
sahilmgandhi	18:6a4db94011d3	18623	* \|[16:31] \|TOC13 \|Time-Out Period Counter For Channel 13
sahilmgandhi	18:6a4db94011d3	18624	* \| \| \|This controls the period of time-out function for channel 13.
sahilmgandhi	18:6a4db94011d3	18625	* \| \| \|The calculation unit is based on 10 kHz clock.
sahilmgandhi	18:6a4db94011d3	18626	*/
sahilmgandhi	18:6a4db94011d3	18627	__IO uint32_t TOC12_13;
sahilmgandhi	18:6a4db94011d3	18628
sahilmgandhi	18:6a4db94011d3	18629	/**
sahilmgandhi	18:6a4db94011d3	18630	* TOC14_15
sahilmgandhi	18:6a4db94011d3	18631	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18632	* Offset: 0x45C PDMA Time-out Period Counter Ch15 and Ch14 Register
sahilmgandhi	18:6a4db94011d3	18633	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18634	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18635	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18636	* \|[0:15] \|TOC14 \|Time-Out Period Counter For Channel 14
sahilmgandhi	18:6a4db94011d3	18637	* \| \| \|This control the period of time-out function for channel 14.
sahilmgandhi	18:6a4db94011d3	18638	* \| \| \|The calculation unit is based on 10 kHz clock.
sahilmgandhi	18:6a4db94011d3	18639	* \|[16:31] \|TOC15 \|Time-Out Period Counter For Channel 15
sahilmgandhi	18:6a4db94011d3	18640	* \| \| \|This control the period of time-out function for channel 15.
sahilmgandhi	18:6a4db94011d3	18641	* \| \| \|The calculation unit is based on 10 kHz clock.
sahilmgandhi	18:6a4db94011d3	18642	*/
sahilmgandhi	18:6a4db94011d3	18643	__IO uint32_t TOC14_15;
sahilmgandhi	18:6a4db94011d3	18644	uint32_t RESERVE2[8];
sahilmgandhi	18:6a4db94011d3	18645
sahilmgandhi	18:6a4db94011d3	18646
sahilmgandhi	18:6a4db94011d3	18647	/**
sahilmgandhi	18:6a4db94011d3	18648	* REQSEL0_3
sahilmgandhi	18:6a4db94011d3	18649	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18650	* Offset: 0x480 PDMA Source Module Select Register 0
sahilmgandhi	18:6a4db94011d3	18651	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18652	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18653	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18654	* \|[0:4] \|REQSRC0 \|Channel 0 Selection
sahilmgandhi	18:6a4db94011d3	18655	* \| \| \|This filed defines which peripheral is connected to PDMA channel 0.
sahilmgandhi	18:6a4db94011d3	18656	* \| \| \|Software can configure the peripheral by setting REQSRC0.
sahilmgandhi	18:6a4db94011d3	18657	* \| \| \|00000 = Connect to SPI0_TX.
sahilmgandhi	18:6a4db94011d3	18658	* \| \| \|00001 = Connect to SPI1_TX.
sahilmgandhi	18:6a4db94011d3	18659	* \| \| \|00010 = Connect to SPI2_TX.
sahilmgandhi	18:6a4db94011d3	18660	* \| \| \|00011 = Connect to SPI3_TX.
sahilmgandhi	18:6a4db94011d3	18661	* \| \| \|00100 = Connect to UART0_TX.
sahilmgandhi	18:6a4db94011d3	18662	* \| \| \|00101 = Connect to UART1_TX.
sahilmgandhi	18:6a4db94011d3	18663	* \| \| \|00110 = Connect to UART2_TX.
sahilmgandhi	18:6a4db94011d3	18664	* \| \| \|00111 = Connect to UART3_TX.
sahilmgandhi	18:6a4db94011d3	18665	* \| \| \|01000 = Connect to UART4_TX.
sahilmgandhi	18:6a4db94011d3	18666	* \| \| \|01001 = Connect to UART5_TX.
sahilmgandhi	18:6a4db94011d3	18667	* \| \| \|01010 = Reserved.
sahilmgandhi	18:6a4db94011d3	18668	* \| \| \|01011 = Connect to I2S_TX.
sahilmgandhi	18:6a4db94011d3	18669	* \| \| \|01100 = Connect to I2S1_TX.
sahilmgandhi	18:6a4db94011d3	18670	* \| \| \|01101 = Connect to SPI0_RX.
sahilmgandhi	18:6a4db94011d3	18671	* \| \| \|01110 = Connect to SPI1_RX.
sahilmgandhi	18:6a4db94011d3	18672	* \| \| \|01111 = Connect to SPI2_RX.
sahilmgandhi	18:6a4db94011d3	18673	* \| \| \|10000 = Connect to SPI3_RX.
sahilmgandhi	18:6a4db94011d3	18674	* \| \| \|10001 = Connect to UART0_RX.
sahilmgandhi	18:6a4db94011d3	18675	* \| \| \|10010 = Connect to UART1_RX.
sahilmgandhi	18:6a4db94011d3	18676	* \| \| \|10011 = Connect to UART2_RX.
sahilmgandhi	18:6a4db94011d3	18677	* \| \| \|10100 = Connect to UART3_RX.
sahilmgandhi	18:6a4db94011d3	18678	* \| \| \|10101 = Connect to UART4_RX.
sahilmgandhi	18:6a4db94011d3	18679	* \| \| \|10110 = Connect to UART5_RX.
sahilmgandhi	18:6a4db94011d3	18680	* \| \| \|10111 = Reserved.
sahilmgandhi	18:6a4db94011d3	18681	* \| \| \|11000 = Connect to ADC.
sahilmgandhi	18:6a4db94011d3	18682	* \| \| \|11001 = Connect to I2S_RX.
sahilmgandhi	18:6a4db94011d3	18683	* \| \| \|11010 = Connect to I2S1_RX.
sahilmgandhi	18:6a4db94011d3	18684	* \| \| \|Other = Reserved.
sahilmgandhi	18:6a4db94011d3	18685	* \|[8:12] \|REQSRC1 \|Channel 1 Selection
sahilmgandhi	18:6a4db94011d3	18686	* \| \| \|This filed defines which peripheral is connected to PDMA channel 1.
sahilmgandhi	18:6a4db94011d3	18687	* \| \| \|Software can configure the peripheral setting by REQSRC1.
sahilmgandhi	18:6a4db94011d3	18688	* \| \| \|The channel configuration is the same as REQSRC0 field.
sahilmgandhi	18:6a4db94011d3	18689	* \| \| \|Please refer to the explanation of REQSRC0.
sahilmgandhi	18:6a4db94011d3	18690	* \|[16:20] \|REQSRC2 \|Channel 2 Selection
sahilmgandhi	18:6a4db94011d3	18691	* \| \| \|This filed defines which peripheral is connected to PDMA channel 2.
sahilmgandhi	18:6a4db94011d3	18692	* \| \| \|Software can configure the peripheral setting by REQSRC2.
sahilmgandhi	18:6a4db94011d3	18693	* \| \| \|The channel configuration is the same as REQSRC0 field.
sahilmgandhi	18:6a4db94011d3	18694	* \| \| \|Please refer to the explanation of REQSRC0.
sahilmgandhi	18:6a4db94011d3	18695	* \|[24:28] \|REQSRC3 \|Channel 3 Selection
sahilmgandhi	18:6a4db94011d3	18696	* \| \| \|This filed defines which peripheral is connected to PDMA channel 3.
sahilmgandhi	18:6a4db94011d3	18697	* \| \| \|Software can configure the peripheral setting by REQSRC3.
sahilmgandhi	18:6a4db94011d3	18698	* \| \| \|The channel configuration is the same as REQSRC0 field.
sahilmgandhi	18:6a4db94011d3	18699	* \| \| \|Please refer to the explanation of REQSRC0.
sahilmgandhi	18:6a4db94011d3	18700	*/
sahilmgandhi	18:6a4db94011d3	18701	__IO uint32_t REQSEL0_3;
sahilmgandhi	18:6a4db94011d3	18702
sahilmgandhi	18:6a4db94011d3	18703	/**
sahilmgandhi	18:6a4db94011d3	18704	* REQSEL4_7
sahilmgandhi	18:6a4db94011d3	18705	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18706	* Offset: 0x484 PDMA Source Module Select Register 1
sahilmgandhi	18:6a4db94011d3	18707	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18708	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18709	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18710	* \|[0:4] \|REQSRC4 \|Channel 0 Selection
sahilmgandhi	18:6a4db94011d3	18711	* \| \| \|This filed defines which peripheral is connected to PDMA channel 4.
sahilmgandhi	18:6a4db94011d3	18712	* \| \| \|Software can configure the peripheral setting by REQSRC4.
sahilmgandhi	18:6a4db94011d3	18713	* \| \| \|The channel configuration is the same as REQSRC0 field.
sahilmgandhi	18:6a4db94011d3	18714	* \| \| \|Please refer to the explanation of REQSRC0.
sahilmgandhi	18:6a4db94011d3	18715	* \|[8:12] \|REQSRC5 \|Channel 1 Selection
sahilmgandhi	18:6a4db94011d3	18716	* \| \| \|This filed defines which peripheral is connected to PDMA channel 5.
sahilmgandhi	18:6a4db94011d3	18717	* \| \| \|Software can configure the peripheral setting by REQSRC5.
sahilmgandhi	18:6a4db94011d3	18718	* \| \| \|The channel configuration is the same as REQSRC0 field.
sahilmgandhi	18:6a4db94011d3	18719	* \| \| \|Please refer to the explanation of REQSRC0.
sahilmgandhi	18:6a4db94011d3	18720	* \|[16:20] \|REQSRC6 \|Channel 6 Selection
sahilmgandhi	18:6a4db94011d3	18721	* \| \| \|This filed defines which peripheral is connected to PDMA channel 6.
sahilmgandhi	18:6a4db94011d3	18722	* \| \| \|Software can configure the peripheral setting by REQSRC6.
sahilmgandhi	18:6a4db94011d3	18723	* \| \| \|The channel configuration is the same as REQSRC0 field.
sahilmgandhi	18:6a4db94011d3	18724	* \| \| \|Please refer to the explanation of REQSRC0.
sahilmgandhi	18:6a4db94011d3	18725	* \|[24:28] \|REQSRC7 \|Channel 7 Selection
sahilmgandhi	18:6a4db94011d3	18726	* \| \| \|This filed defines which peripheral is connected to PDMA channel 7.
sahilmgandhi	18:6a4db94011d3	18727	* \| \| \|Software can configure the peripheral setting by REQSRC7.
sahilmgandhi	18:6a4db94011d3	18728	* \| \| \|The channel configuration is the same as REQSRC0 field.
sahilmgandhi	18:6a4db94011d3	18729	* \| \| \|Please refer to the explanation of REQSRC0.
sahilmgandhi	18:6a4db94011d3	18730	*/
sahilmgandhi	18:6a4db94011d3	18731	__IO uint32_t REQSEL4_7;
sahilmgandhi	18:6a4db94011d3	18732
sahilmgandhi	18:6a4db94011d3	18733	/**
sahilmgandhi	18:6a4db94011d3	18734	* REQSEL8_11
sahilmgandhi	18:6a4db94011d3	18735	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18736	* Offset: 0x488 PDMA Source Module Select Register 2
sahilmgandhi	18:6a4db94011d3	18737	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18738	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18739	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18740	* \|[0:4] \|REQSRC8 \|Channel 8 Selection
sahilmgandhi	18:6a4db94011d3	18741	* \| \| \|This filed defines which peripheral is connected to PDMA channel 8.
sahilmgandhi	18:6a4db94011d3	18742	* \| \| \|Software can configure the peripheral setting by REQSRC8.
sahilmgandhi	18:6a4db94011d3	18743	* \| \| \|The channel configuration is the same as REQSRC0 field.
sahilmgandhi	18:6a4db94011d3	18744	* \| \| \|Please refer to the explanation of REQSRC0.
sahilmgandhi	18:6a4db94011d3	18745	* \|[8:12] \|REQSRC9 \|Channel 9 Selection
sahilmgandhi	18:6a4db94011d3	18746	* \| \| \|This filed defines which peripheral is connected to PDMA channel 9.
sahilmgandhi	18:6a4db94011d3	18747	* \| \| \|Software can configure the peripheral setting by REQSRC9.
sahilmgandhi	18:6a4db94011d3	18748	* \| \| \|The channel configuration is the same as REQSRC0 field.
sahilmgandhi	18:6a4db94011d3	18749	* \| \| \|Please refer to the explanation of REQSRC0.
sahilmgandhi	18:6a4db94011d3	18750	* \|[16:20] \|REQSRC10 \|Channel 10 Selection
sahilmgandhi	18:6a4db94011d3	18751	* \| \| \|This filed defines which peripheral is connected to PDMA channel 10.
sahilmgandhi	18:6a4db94011d3	18752	* \| \| \|Software can configure the peripheral setting by REQSRC10.
sahilmgandhi	18:6a4db94011d3	18753	* \| \| \|The channel configuration is the same as REQSRC0 field.
sahilmgandhi	18:6a4db94011d3	18754	* \| \| \|Please refer to the explanation of REQSRC0.
sahilmgandhi	18:6a4db94011d3	18755	* \|[24:28] \|REQSRC11 \|Channel 11 Selection
sahilmgandhi	18:6a4db94011d3	18756	* \| \| \|This filed defines which peripheral is connected to PDMA channel 11.
sahilmgandhi	18:6a4db94011d3	18757	* \| \| \|Software can configure the peripheral setting by REQSRC11.
sahilmgandhi	18:6a4db94011d3	18758	* \| \| \|The channel configuration is the same as REQSRC0 field.
sahilmgandhi	18:6a4db94011d3	18759	* \| \| \|Please refer to the explanation of REQSRC0.
sahilmgandhi	18:6a4db94011d3	18760	*/
sahilmgandhi	18:6a4db94011d3	18761	__IO uint32_t REQSEL8_11;
sahilmgandhi	18:6a4db94011d3	18762
sahilmgandhi	18:6a4db94011d3	18763	/**
sahilmgandhi	18:6a4db94011d3	18764	* REQSEL12_15
sahilmgandhi	18:6a4db94011d3	18765	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18766	* Offset: 0x48C PDMA Source Module Select Register 3
sahilmgandhi	18:6a4db94011d3	18767	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18768	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18769	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18770	* \|[0:4] \|REQSRC12 \|Channel 12 Selection
sahilmgandhi	18:6a4db94011d3	18771	* \| \| \|This filed defines which peripheral is connected to PDMA channel 12.
sahilmgandhi	18:6a4db94011d3	18772	* \| \| \|Software can configure the peripheral setting by REQSRC12.
sahilmgandhi	18:6a4db94011d3	18773	* \| \| \|The channel configuration is the same as REQSRC0 field.
sahilmgandhi	18:6a4db94011d3	18774	* \| \| \|Please refer to the explanation of REQSRC0.
sahilmgandhi	18:6a4db94011d3	18775	* \|[8:12] \|REQSRC13 \|Channel 13 Selection
sahilmgandhi	18:6a4db94011d3	18776	* \| \| \|This filed defines which peripheral is connected to PDMA channel 13.
sahilmgandhi	18:6a4db94011d3	18777	* \| \| \|Software can configure the peripheral setting by REQSRC13.
sahilmgandhi	18:6a4db94011d3	18778	* \| \| \|The channel configuration is the same as REQSRC0 field.
sahilmgandhi	18:6a4db94011d3	18779	* \| \| \|Please refer to the explanation of REQSRC0.
sahilmgandhi	18:6a4db94011d3	18780	* \|[16:20] \|REQSRC14 \|Channel 14 Selection
sahilmgandhi	18:6a4db94011d3	18781	* \| \| \|This filed defines which peripheral is connected to PDMA channel 14.
sahilmgandhi	18:6a4db94011d3	18782	* \| \| \|Software can configure the peripheral setting by REQSRC14.
sahilmgandhi	18:6a4db94011d3	18783	* \| \| \|The channel configuration is the same as REQSRC0 field.
sahilmgandhi	18:6a4db94011d3	18784	* \| \| \|Please refer to the explanation of REQSRC0.
sahilmgandhi	18:6a4db94011d3	18785	* \|[24:28] \|REQSRC15 \|Channel 15 Selection
sahilmgandhi	18:6a4db94011d3	18786	* \| \| \|This filed defines which peripheral is connected to PDMA channel 15.
sahilmgandhi	18:6a4db94011d3	18787	* \| \| \|Software can configure the peripheral setting by REQSRC15.
sahilmgandhi	18:6a4db94011d3	18788	* \| \| \|The channel configuration is the same as REQSRC0 field.
sahilmgandhi	18:6a4db94011d3	18789	* \| \| \|Please refer to the explanation of REQSRC0.
sahilmgandhi	18:6a4db94011d3	18790	*/
sahilmgandhi	18:6a4db94011d3	18791	__IO uint32_t REQSEL12_15;
sahilmgandhi	18:6a4db94011d3	18792
sahilmgandhi	18:6a4db94011d3	18793	} PDMA_T;
sahilmgandhi	18:6a4db94011d3	18794
sahilmgandhi	18:6a4db94011d3	18795	/**
sahilmgandhi	18:6a4db94011d3	18796	@addtogroup PDMA_CONST PDMA Bit Field Definition
sahilmgandhi	18:6a4db94011d3	18797	Constant Definitions for PDMA Controller
sahilmgandhi	18:6a4db94011d3	18798	@{ */
sahilmgandhi	18:6a4db94011d3	18799
sahilmgandhi	18:6a4db94011d3	18800	#define PDMA_DSCT_CTL_OPMODE_Pos (0) /!< PDMA DSCT_CTL: OPMODE Position /
sahilmgandhi	18:6a4db94011d3	18801	#define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) /!< PDMA DSCT_CTL: OPMODE Mask /
sahilmgandhi	18:6a4db94011d3	18802
sahilmgandhi	18:6a4db94011d3	18803	#define PDMA_DSCT_CTL_TXTYPE_Pos (2) /!< PDMA DSCT_CTL: TXTYPE Position /
sahilmgandhi	18:6a4db94011d3	18804	#define PDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos) /!< PDMA DSCT_CTL: TXTYPE Mask /
sahilmgandhi	18:6a4db94011d3	18805
sahilmgandhi	18:6a4db94011d3	18806	#define PDMA_DSCT_CTL_BURSIZE_Pos (4) /!< PDMA DSCT_CTL: BURSIZE Position /
sahilmgandhi	18:6a4db94011d3	18807	#define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) /!< PDMA DSCT_CTL: BURSIZE Mask /
sahilmgandhi	18:6a4db94011d3	18808
sahilmgandhi	18:6a4db94011d3	18809	#define PDMA_DSCT_CTL_TBINTDIS_Pos (7) /!< PDMA DSCT_CTL: TBINTDIS Position /
sahilmgandhi	18:6a4db94011d3	18810	#define PDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) /!< PDMA DSCT_CTL: TBINTDIS Mask /
sahilmgandhi	18:6a4db94011d3	18811
sahilmgandhi	18:6a4db94011d3	18812	#define PDMA_DSCT_CTL_SAINC_Pos (8) /!< PDMA DSCT_CTL: SAINC Position /
sahilmgandhi	18:6a4db94011d3	18813	#define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) /!< PDMA DSCT_CTL: SAINC Mask /
sahilmgandhi	18:6a4db94011d3	18814
sahilmgandhi	18:6a4db94011d3	18815	#define PDMA_DSCT_CTL_DAINC_Pos (10) /!< PDMA DSCT_CTL: DAINC Position /
sahilmgandhi	18:6a4db94011d3	18816	#define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) /!< PDMA DSCT_CTL: DAINC Mask /
sahilmgandhi	18:6a4db94011d3	18817
sahilmgandhi	18:6a4db94011d3	18818	#define PDMA_DSCT_CTL_TXWIDTH_Pos (12) /!< PDMA DSCT_CTL: TXWIDTH Position /
sahilmgandhi	18:6a4db94011d3	18819	#define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) /!< PDMA DSCT_CTL: TXWIDTH Mask /
sahilmgandhi	18:6a4db94011d3	18820
sahilmgandhi	18:6a4db94011d3	18821	#define PDMA_DSCT_CTL_TXCNT_Pos (16) /!< PDMA DSCT_CTL: TXCNT Position /
sahilmgandhi	18:6a4db94011d3	18822	#define PDMA_DSCT_CTL_TXCNT_Msk (0x3ffful << PDMA_DSCT_CTL_TXCNT_Pos) /!< PDMA DSCT_CTL: TXCNT Mask /
sahilmgandhi	18:6a4db94011d3	18823
sahilmgandhi	18:6a4db94011d3	18824	#define PDMA_DSCT_ENDSA_ENDSA_Pos (0) /!< PDMA DSCT_ENDSA: ENDSA Position /
sahilmgandhi	18:6a4db94011d3	18825	#define PDMA_DSCT_ENDSA_ENDSA_Msk (0xfffffffful << PDMA_DSCT_ENDSA_ENDSA_Pos) /!< PDMA DSCT_ENDSA: ENDSA Mask /
sahilmgandhi	18:6a4db94011d3	18826
sahilmgandhi	18:6a4db94011d3	18827	#define PDMA_DSCT_ENDDA_ENDDA_Pos (0) /!< PDMA DSCT_ENDDA: ENDDA Position /
sahilmgandhi	18:6a4db94011d3	18828	#define PDMA_DSCT_ENDDA_ENDDA_Msk (0xfffffffful << PDMA_DSCT_ENDDA_ENDDA_Pos) /!< PDMA DSCT_ENDDA: ENDDA Mask /
sahilmgandhi	18:6a4db94011d3	18829
sahilmgandhi	18:6a4db94011d3	18830	#define PDMA_DSCT_NEXT_NEXT_Pos (2) /!< PDMA DSCT_NEXT: NEXT Position /
sahilmgandhi	18:6a4db94011d3	18831	#define PDMA_DSCT_NEXT_NEXT_Msk (0x3ffful << PDMA_DSCT_NEXT_NEXT_Pos) /!< PDMA DSCT_NEXT: NEXT Mask /
sahilmgandhi	18:6a4db94011d3	18832
sahilmgandhi	18:6a4db94011d3	18833	#define PDMA_CHCTL_CHEN_Pos (0) /!< PDMA CHCTL: CHEN Position /
sahilmgandhi	18:6a4db94011d3	18834	#define PDMA_CHCTL_CHEN_Msk (0xfffful << PDMA_CHCTL_CHEN_Pos) /!< PDMA CHCTL: CHEN Mask /
sahilmgandhi	18:6a4db94011d3	18835
sahilmgandhi	18:6a4db94011d3	18836	#define PDMA_STOP_STOP_Pos (0) /!< PDMA STOP: STOP Position /
sahilmgandhi	18:6a4db94011d3	18837	#define PDMA_STOP_STOP_Msk (0xfffful << PDMA_STOP_STOP_Pos) /!< PDMA STOP: STOP Mask /
sahilmgandhi	18:6a4db94011d3	18838
sahilmgandhi	18:6a4db94011d3	18839	#define PDMA_SWREQ_SWREQ_Pos (0) /!< PDMA SWREQ: SWREQ Position /
sahilmgandhi	18:6a4db94011d3	18840	#define PDMA_SWREQ_SWREQ_Msk (0xffful << PDMA_SWREQ_SWREQ_Pos) /!< PDMA SWREQ: SWREQ Mask /
sahilmgandhi	18:6a4db94011d3	18841
sahilmgandhi	18:6a4db94011d3	18842	#define PDMA_TRGSTS_REQSTS_Pos (0) /!< PDMA TRGSTS: REQSTS Position /
sahilmgandhi	18:6a4db94011d3	18843	#define PDMA_TRGSTS_REQSTS_Msk (0xfffful << PDMA_TRGSTS_REQSTS_Pos) /!< PDMA TRGSTS: REQSTS Mask /
sahilmgandhi	18:6a4db94011d3	18844
sahilmgandhi	18:6a4db94011d3	18845	#define PDMA_PRISET_FPRISET_Pos (0) /!< PDMA PRISET: FPRISET Position /
sahilmgandhi	18:6a4db94011d3	18846	#define PDMA_PRISET_FPRISET_Msk (0xfffful << PDMA_PRISET_FPRISET_Pos) /!< PDMA PRISET: FPRISET Mask /
sahilmgandhi	18:6a4db94011d3	18847
sahilmgandhi	18:6a4db94011d3	18848	#define PDMA_PRICLR_FPRICLR_Pos (0) /!< PDMA PRICLR: FPRICLR Position /
sahilmgandhi	18:6a4db94011d3	18849	#define PDMA_PRICLR_FPRICLR_Msk (0xfffful << PDMA_PRICLR_FPRICLR_Pos) /!< PDMA PRICLR: FPRICLR Mask /
sahilmgandhi	18:6a4db94011d3	18850
sahilmgandhi	18:6a4db94011d3	18851	#define PDMA_INTEN_INTEN_Pos (0) /!< PDMA INTEN: INTEN Position /
sahilmgandhi	18:6a4db94011d3	18852	#define PDMA_INTEN_INTEN_Msk (0xfffful << PDMA_INTEN_INTEN_Pos) /!< PDMA INTEN: INTEN Mask /
sahilmgandhi	18:6a4db94011d3	18853
sahilmgandhi	18:6a4db94011d3	18854	#define PDMA_INTSTS_ABTIF_Pos (0) /!< PDMA INTSTS: ABTIF Position /
sahilmgandhi	18:6a4db94011d3	18855	#define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) /!< PDMA INTSTS: ABTIF Mask /
sahilmgandhi	18:6a4db94011d3	18856
sahilmgandhi	18:6a4db94011d3	18857	#define PDMA_INTSTS_TDIF_Pos (1) /!< PDMA INTSTS: TDIF Position /
sahilmgandhi	18:6a4db94011d3	18858	#define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) /!< PDMA INTSTS: TDIF Mask /
sahilmgandhi	18:6a4db94011d3	18859
sahilmgandhi	18:6a4db94011d3	18860	#define PDMA_INTSTS_TEIF_Pos (2) /!< PDMA INTSTS: TEIF Position /
sahilmgandhi	18:6a4db94011d3	18861	#define PDMA_INTSTS_TEIF_Msk (0x1ul << PDMA_INTSTS_TEIF_Pos) /!< PDMA INTSTS: TEIF Mask /
sahilmgandhi	18:6a4db94011d3	18862
sahilmgandhi	18:6a4db94011d3	18863	#define PDMA_INTSTS_REQTOFX_Pos (8) /!< PDMA INTSTS: REQTOFX Position /
sahilmgandhi	18:6a4db94011d3	18864	#define PDMA_INTSTS_REQTOFX_Msk (0xfffful << PDMA_INTSTS_REQTOFX_Pos) /!< PDMA INTSTS: REQTOFX Mask /
sahilmgandhi	18:6a4db94011d3	18865
sahilmgandhi	18:6a4db94011d3	18866	#define PDMA_ABTSTS_ABTIF_Pos (0) /!< PDMA ABTSTS: ABTIF Position /
sahilmgandhi	18:6a4db94011d3	18867	#define PDMA_ABTSTS_ABTIF_Msk (0xfffful << PDMA_ABTSTS_ABTIF_Pos) /!< PDMA ABTSTS: ABTIF Mask /
sahilmgandhi	18:6a4db94011d3	18868
sahilmgandhi	18:6a4db94011d3	18869	#define PDMA_TDSTS_TDIF_Pos (0) /!< PDMA TDSTS: TDIF Position /
sahilmgandhi	18:6a4db94011d3	18870	#define PDMA_TDSTS_TDIF_Msk (0xfffful << PDMA_TDSTS_TDIF_Pos) /!< PDMA TDSTS: TDIF Mask /
sahilmgandhi	18:6a4db94011d3	18871
sahilmgandhi	18:6a4db94011d3	18872	#define PDMA_SCATSTS_TEMPTYF_Pos (0) /!< PDMA SCATSTS: TEMPTYF Position /
sahilmgandhi	18:6a4db94011d3	18873	#define PDMA_SCATSTS_TEMPTYF_Msk (0xfffful << PDMA_SCATSTS_TEMPTYF_Pos) /!< PDMA SCATSTS: TEMPTYF Mask /
sahilmgandhi	18:6a4db94011d3	18874
sahilmgandhi	18:6a4db94011d3	18875	#define PDMA_TACTSTS_TXACTF_Pos (0) /!< PDMA TACTSTS: TXACTF Position /
sahilmgandhi	18:6a4db94011d3	18876	#define PDMA_TACTSTS_TXACTF_Msk (0xfffful << PDMA_TACTSTS_TXACTF_Pos) /!< PDMA TACTSTS: TXACTF Mask /
sahilmgandhi	18:6a4db94011d3	18877
sahilmgandhi	18:6a4db94011d3	18878	#define PDMA_SCATBA_SCATBA_Pos (16) /!< PDMA SCATBA: SCATBA Position /
sahilmgandhi	18:6a4db94011d3	18879	#define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) /!< PDMA SCATBA: SCATBA Mask /
sahilmgandhi	18:6a4db94011d3	18880
sahilmgandhi	18:6a4db94011d3	18881	#define PDMA_TOC0_1_TOC0_Pos (0) /!< PDMA TOC0_1: TOC0 Position /
sahilmgandhi	18:6a4db94011d3	18882	#define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) /!< PDMA TOC0_1: TOC0 Mask /
sahilmgandhi	18:6a4db94011d3	18883
sahilmgandhi	18:6a4db94011d3	18884	#define PDMA_TOC0_1_TOC1_Pos (16) /!< PDMA TOC0_1: TOC1 Position /
sahilmgandhi	18:6a4db94011d3	18885	#define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) /!< PDMA TOC0_1: TOC1 Mask /
sahilmgandhi	18:6a4db94011d3	18886
sahilmgandhi	18:6a4db94011d3	18887	#define PDMA_TOC2_3_TOC2_Pos (0) /!< PDMA TOC2_3: TOC2 Position /
sahilmgandhi	18:6a4db94011d3	18888	#define PDMA_TOC2_3_TOC2_Msk (0xfffful << PDMA_TOC2_3_TOC2_Pos) /!< PDMA TOC2_3: TOC2 Mask /
sahilmgandhi	18:6a4db94011d3	18889
sahilmgandhi	18:6a4db94011d3	18890	#define PDMA_TOC2_3_TOC3_Pos (16) /!< PDMA TOC2_3: TOC3 Position /
sahilmgandhi	18:6a4db94011d3	18891	#define PDMA_TOC2_3_TOC3_Msk (0xfffful << PDMA_TOC2_3_TOC3_Pos) /!< PDMA TOC2_3: TOC3 Mask /
sahilmgandhi	18:6a4db94011d3	18892
sahilmgandhi	18:6a4db94011d3	18893	#define PDMA_TOC4_5_TOC4_Pos (0) /!< PDMA TOC4_5: TOC4 Position /
sahilmgandhi	18:6a4db94011d3	18894	#define PDMA_TOC4_5_TOC4_Msk (0xfffful << PDMA_TOC4_5_TOC4_Pos) /!< PDMA TOC4_5: TOC4 Mask /
sahilmgandhi	18:6a4db94011d3	18895
sahilmgandhi	18:6a4db94011d3	18896	#define PDMA_TOC4_5_TOC5_Pos (16) /!< PDMA TOC4_5: TOC5 Position /
sahilmgandhi	18:6a4db94011d3	18897	#define PDMA_TOC4_5_TOC5_Msk (0xfffful << PDMA_TOC4_5_TOC5_Pos) /!< PDMA TOC4_5: TOC5 Mask /
sahilmgandhi	18:6a4db94011d3	18898
sahilmgandhi	18:6a4db94011d3	18899	#define PDMA_TOC6_7_TOC6_Pos (0) /!< PDMA TOC6_7: TOC6 Position /
sahilmgandhi	18:6a4db94011d3	18900	#define PDMA_TOC6_7_TOC6_Msk (0xfffful << PDMA_TOC6_7_TOC6_Pos) /!< PDMA TOC6_7: TOC6 Mask /
sahilmgandhi	18:6a4db94011d3	18901
sahilmgandhi	18:6a4db94011d3	18902	#define PDMA_TOC6_7_TOC7_Pos (16) /!< PDMA TOC6_7: TOC7 Position /
sahilmgandhi	18:6a4db94011d3	18903	#define PDMA_TOC6_7_TOC7_Msk (0xfffful << PDMA_TOC6_7_TOC7_Pos) /!< PDMA TOC6_7: TOC7 Mask /
sahilmgandhi	18:6a4db94011d3	18904
sahilmgandhi	18:6a4db94011d3	18905	#define PDMA_TOC8_9_TOC8_Pos (0) /!< PDMA TOC8_9: TOC8 Position /
sahilmgandhi	18:6a4db94011d3	18906	#define PDMA_TOC8_9_TOC8_Msk (0xfffful << PDMA_TOC8_9_TOC8_Pos) /!< PDMA TOC8_9: TOC8 Mask /
sahilmgandhi	18:6a4db94011d3	18907
sahilmgandhi	18:6a4db94011d3	18908	#define PDMA_TOC8_9_TOC9_Pos (16) /!< PDMA TOC8_9: TOC9 Position /
sahilmgandhi	18:6a4db94011d3	18909	#define PDMA_TOC8_9_TOC9_Msk (0xfffful << PDMA_TOC8_9_TOC9_Pos) /!< PDMA TOC8_9: TOC9 Mask /
sahilmgandhi	18:6a4db94011d3	18910
sahilmgandhi	18:6a4db94011d3	18911	#define PDMA_TOC10_11_TOC10_Pos (0) /!< PDMA TOC10_11: TOC10 Position /
sahilmgandhi	18:6a4db94011d3	18912	#define PDMA_TOC10_11_TOC10_Msk (0xfffful << PDMA_TOC10_11_TOC10_Pos) /!< PDMA TOC10_11: TOC10 Mask /
sahilmgandhi	18:6a4db94011d3	18913
sahilmgandhi	18:6a4db94011d3	18914	#define PDMA_TOC10_11_TOC11_Pos (16) /!< PDMA TOC10_11: TOC11 Position /
sahilmgandhi	18:6a4db94011d3	18915	#define PDMA_TOC10_11_TOC11_Msk (0xfffful << PDMA_TOC10_11_TOC11_Pos) /!< PDMA TOC10_11: TOC11 Mask /
sahilmgandhi	18:6a4db94011d3	18916
sahilmgandhi	18:6a4db94011d3	18917	#define PDMA_TOC12_13_TOC12_Pos (0) /!< PDMA TOC12_13: TOC12 Position /
sahilmgandhi	18:6a4db94011d3	18918	#define PDMA_TOC12_13_TOC12_Msk (0xfffful << PDMA_TOC12_13_TOC12_Pos) /!< PDMA TOC12_13: TOC12 Mask /
sahilmgandhi	18:6a4db94011d3	18919
sahilmgandhi	18:6a4db94011d3	18920	#define PDMA_TOC12_13_TOC13_Pos (16) /!< PDMA TOC12_13: TOC13 Position /
sahilmgandhi	18:6a4db94011d3	18921	#define PDMA_TOC12_13_TOC13_Msk (0xfffful << PDMA_TOC12_13_TOC13_Pos) /!< PDMA TOC12_13: TOC13 Mask /
sahilmgandhi	18:6a4db94011d3	18922
sahilmgandhi	18:6a4db94011d3	18923	#define PDMA_TOC14_15_TOC14_Pos (0) /!< PDMA TOC14_15: TOC14 Position /
sahilmgandhi	18:6a4db94011d3	18924	#define PDMA_TOC14_15_TOC14_Msk (0xfffful << PDMA_TOC14_15_TOC14_Pos) /!< PDMA TOC14_15: TOC14 Mask /
sahilmgandhi	18:6a4db94011d3	18925
sahilmgandhi	18:6a4db94011d3	18926	#define PDMA_TOC14_15_TOC15_Pos (16) /!< PDMA TOC14_15: TOC15 Position /
sahilmgandhi	18:6a4db94011d3	18927	#define PDMA_TOC14_15_TOC15_Msk (0xfffful << PDMA_TOC14_15_TOC15_Pos) /!< PDMA TOC14_15: TOC15 Mask /
sahilmgandhi	18:6a4db94011d3	18928
sahilmgandhi	18:6a4db94011d3	18929	#define PDMA_REQSEL0_3_REQSRC0_Pos (0) /!< PDMA REQSEL0_3: REQSRC0 Position /
sahilmgandhi	18:6a4db94011d3	18930	#define PDMA_REQSEL0_3_REQSRC0_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC0_Pos) /!< PDMA REQSEL0_3: REQSRC0 Mask /
sahilmgandhi	18:6a4db94011d3	18931
sahilmgandhi	18:6a4db94011d3	18932	#define PDMA_REQSEL0_3_REQSRC1_Pos (8) /!< PDMA REQSEL0_3: REQSRC1 Position /
sahilmgandhi	18:6a4db94011d3	18933	#define PDMA_REQSEL0_3_REQSRC1_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC1_Pos) /!< PDMA REQSEL0_3: REQSRC1 Mask /
sahilmgandhi	18:6a4db94011d3	18934
sahilmgandhi	18:6a4db94011d3	18935	#define PDMA_REQSEL0_3_REQSRC2_Pos (16) /!< PDMA REQSEL0_3: REQSRC2 Position /
sahilmgandhi	18:6a4db94011d3	18936	#define PDMA_REQSEL0_3_REQSRC2_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC2_Pos) /!< PDMA REQSEL0_3: REQSRC2 Mask /
sahilmgandhi	18:6a4db94011d3	18937
sahilmgandhi	18:6a4db94011d3	18938	#define PDMA_REQSEL0_3_REQSRC3_Pos (24) /!< PDMA REQSEL0_3: REQSRC3 Position /
sahilmgandhi	18:6a4db94011d3	18939	#define PDMA_REQSEL0_3_REQSRC3_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC3_Pos) /!< PDMA REQSEL0_3: REQSRC3 Mask /
sahilmgandhi	18:6a4db94011d3	18940
sahilmgandhi	18:6a4db94011d3	18941	#define PDMA_REQSEL4_7_REQSRC4_Pos (0) /!< PDMA REQSEL4_7: REQSRC4 Position /
sahilmgandhi	18:6a4db94011d3	18942	#define PDMA_REQSEL4_7_REQSRC4_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC4_Pos) /!< PDMA REQSEL4_7: REQSRC4 Mask /
sahilmgandhi	18:6a4db94011d3	18943
sahilmgandhi	18:6a4db94011d3	18944	#define PDMA_REQSEL4_7_REQSRC5_Pos (8) /!< PDMA REQSEL4_7: REQSRC5 Position /
sahilmgandhi	18:6a4db94011d3	18945	#define PDMA_REQSEL4_7_REQSRC5_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC5_Pos) /!< PDMA REQSEL4_7: REQSRC5 Mask /
sahilmgandhi	18:6a4db94011d3	18946
sahilmgandhi	18:6a4db94011d3	18947	#define PDMA_REQSEL4_7_REQSRC6_Pos (16) /!< PDMA REQSEL4_7: REQSRC6 Position /
sahilmgandhi	18:6a4db94011d3	18948	#define PDMA_REQSEL4_7_REQSRC6_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC6_Pos) /!< PDMA REQSEL4_7: REQSRC6 Mask /
sahilmgandhi	18:6a4db94011d3	18949
sahilmgandhi	18:6a4db94011d3	18950	#define PDMA_REQSEL4_7_REQSRC7_Pos (24) /!< PDMA REQSEL4_7: REQSRC7 Position /
sahilmgandhi	18:6a4db94011d3	18951	#define PDMA_REQSEL4_7_REQSRC7_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC7_Pos) /!< PDMA REQSEL4_7: REQSRC7 Mask /
sahilmgandhi	18:6a4db94011d3	18952
sahilmgandhi	18:6a4db94011d3	18953	#define PDMA_REQSEL8_11_REQSRC8_Pos (0) /!< PDMA REQSEL8_11: REQSRC8 Position /
sahilmgandhi	18:6a4db94011d3	18954	#define PDMA_REQSEL8_11_REQSRC8_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC8_Pos) /!< PDMA REQSEL8_11: REQSRC8 Mask /
sahilmgandhi	18:6a4db94011d3	18955
sahilmgandhi	18:6a4db94011d3	18956	#define PDMA_REQSEL8_11_REQSRC9_Pos (8) /!< PDMA REQSEL8_11: REQSRC9 Position /
sahilmgandhi	18:6a4db94011d3	18957	#define PDMA_REQSEL8_11_REQSRC9_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC9_Pos) /!< PDMA REQSEL8_11: REQSRC9 Mask /
sahilmgandhi	18:6a4db94011d3	18958
sahilmgandhi	18:6a4db94011d3	18959	#define PDMA_REQSEL8_11_REQSRC10_Pos (16) /!< PDMA REQSEL8_11: REQSRC10 Position /
sahilmgandhi	18:6a4db94011d3	18960	#define PDMA_REQSEL8_11_REQSRC10_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC10_Pos) /!< PDMA REQSEL8_11: REQSRC10 Mask /
sahilmgandhi	18:6a4db94011d3	18961
sahilmgandhi	18:6a4db94011d3	18962	#define PDMA_REQSEL8_11_REQSRC11_Pos (24) /!< PDMA REQSEL8_11: REQSRC11 Position /
sahilmgandhi	18:6a4db94011d3	18963	#define PDMA_REQSEL8_11_REQSRC11_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC11_Pos) /!< PDMA REQSEL8_11: REQSRC11 Mask /
sahilmgandhi	18:6a4db94011d3	18964
sahilmgandhi	18:6a4db94011d3	18965	#define PDMA_REQSEL12_15_REQSRC12_Pos (0) /!< PDMA REQSEL12_15: REQSRC12 Position /
sahilmgandhi	18:6a4db94011d3	18966	#define PDMA_REQSEL12_15_REQSRC12_Msk (0x1ful << PDMA_REQSEL12_15_REQSRC12_Pos) /!< PDMA REQSEL12_15: REQSRC12 Mask /
sahilmgandhi	18:6a4db94011d3	18967
sahilmgandhi	18:6a4db94011d3	18968	#define PDMA_REQSEL12_15_REQSRC13_Pos (8) /!< PDMA REQSEL12_15: REQSRC13 Position /
sahilmgandhi	18:6a4db94011d3	18969	#define PDMA_REQSEL12_15_REQSRC13_Msk (0x1ful << PDMA_REQSEL12_15_REQSRC13_Pos) /!< PDMA REQSEL12_15: REQSRC13 Mask /
sahilmgandhi	18:6a4db94011d3	18970
sahilmgandhi	18:6a4db94011d3	18971	#define PDMA_REQSEL12_15_REQSRC14_Pos (16) /!< PDMA REQSEL12_15: REQSRC14 Position /
sahilmgandhi	18:6a4db94011d3	18972	#define PDMA_REQSEL12_15_REQSRC14_Msk (0x1ful << PDMA_REQSEL12_15_REQSRC14_Pos) /!< PDMA REQSEL12_15: REQSRC14 Mask /
sahilmgandhi	18:6a4db94011d3	18973
sahilmgandhi	18:6a4db94011d3	18974	#define PDMA_REQSEL12_15_REQSRC15_Pos (24) /!< PDMA REQSEL12_15: REQSRC15 Position /
sahilmgandhi	18:6a4db94011d3	18975	#define PDMA_REQSEL12_15_REQSRC15_Msk (0x1ful << PDMA_REQSEL12_15_REQSRC15_Pos) /!< PDMA REQSEL12_15: REQSRC15 Mask /
sahilmgandhi	18:6a4db94011d3	18976
sahilmgandhi	18:6a4db94011d3	18977	/*@}/ /* PDMA_CONST */
sahilmgandhi	18:6a4db94011d3	18978	/*@}/ /* end of PDMA register group */
sahilmgandhi	18:6a4db94011d3	18979
sahilmgandhi	18:6a4db94011d3	18980
sahilmgandhi	18:6a4db94011d3	18981	/---------------------- PS/2 Device Controller -------------------------/
sahilmgandhi	18:6a4db94011d3	18982	/**
sahilmgandhi	18:6a4db94011d3	18983	@addtogroup PS2 PS/2 Device Controller(PS2)
sahilmgandhi	18:6a4db94011d3	18984	Memory Mapped Structure for PS2 Controller
sahilmgandhi	18:6a4db94011d3	18985	@{ */
sahilmgandhi	18:6a4db94011d3	18986
sahilmgandhi	18:6a4db94011d3	18987	typedef struct {
sahilmgandhi	18:6a4db94011d3	18988
sahilmgandhi	18:6a4db94011d3	18989
sahilmgandhi	18:6a4db94011d3	18990	/**
sahilmgandhi	18:6a4db94011d3	18991	* CTL
sahilmgandhi	18:6a4db94011d3	18992	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	18993	* Offset: 0x00 PS/2 Control Register
sahilmgandhi	18:6a4db94011d3	18994	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	18995	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	18996	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	18997	* \|[0] \|PS2EN \|PS/2 Device Enable Control
sahilmgandhi	18:6a4db94011d3	18998	* \| \| \|Enable PS/2 device controller.
sahilmgandhi	18:6a4db94011d3	18999	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	19000	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	19001	* \|[1] \|TXIEN \|Transmit Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	19002	* \| \| \|0 = Data transmit complete interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	19003	* \| \| \|1 = Data transmit complete interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	19004	* \|[2] \|RXIEN \|Receive Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	19005	* \| \| \|0 = Data receive complete interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	19006	* \| \| \|1 = Data receive complete interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	19007	* \|[3:6] \|TXFDEPTH \|Transmit Data FIFO Depth
sahilmgandhi	18:6a4db94011d3	19008	* \| \| \|There is 16-byte buffer for data transmit.
sahilmgandhi	18:6a4db94011d3	19009	* \| \| \|Software can define the FIFO depth from 1 to 16 bytes depending on the application.
sahilmgandhi	18:6a4db94011d3	19010	* \| \| \|0 = 1 byte.
sahilmgandhi	18:6a4db94011d3	19011	* \| \| \|1 = 2 bytes.
sahilmgandhi	18:6a4db94011d3	19012	* \| \| \|...
sahilmgandhi	18:6a4db94011d3	19013	* \| \| \|14 = 15 bytes.
sahilmgandhi	18:6a4db94011d3	19014	* \| \| \|15 = 16 bytes.
sahilmgandhi	18:6a4db94011d3	19015	* \|[7] \|ACK \|Acknowledge Enable Control
sahilmgandhi	18:6a4db94011d3	19016	* \| \| \|0 = Always sends acknowledge to host at 12th clock for host to device communication.
sahilmgandhi	18:6a4db94011d3	19017	* \| \| \|1 = If parity error or stop bit is not received correctly, acknowledge bit will not be sent to host at 12th clock.
sahilmgandhi	18:6a4db94011d3	19018	* \|[8] \|CLRFIFO \|Clear TX FIFO
sahilmgandhi	18:6a4db94011d3	19019	* \| \| \|Write 1 to this bit to terminate device to host transmission.
sahilmgandhi	18:6a4db94011d3	19020	* \| \| \|The TXEMPTY(PS2_STATUS[7]) bit will be set to 1 and pointer BYTEIDEX(PS2_STATUS[11:8]) is reset to 0 regardless there is residue data in buffer or not.
sahilmgandhi	18:6a4db94011d3	19021	* \| \| \|The buffer content is not been cleared.
sahilmgandhi	18:6a4db94011d3	19022	* \| \| \|0 = Not active.
sahilmgandhi	18:6a4db94011d3	19023	* \| \| \|1 = Clear FIFO.
sahilmgandhi	18:6a4db94011d3	19024	* \|[9] \|OVERRIDE \|Software Override PS/2 CLK/DATA Pin State
sahilmgandhi	18:6a4db94011d3	19025	* \| \| \|0 = CLKSTAT and DATSTAT pins are controlled by internal state machine.
sahilmgandhi	18:6a4db94011d3	19026	* \| \| \|1 = CLKSTAT and DATSTAT pins are controlled by software.
sahilmgandhi	18:6a4db94011d3	19027	* \|[10] \|FPS2CLK \|Force CLKSTAT Line
sahilmgandhi	18:6a4db94011d3	19028	* \| \| \|It forces CLKSTAT line high or low regardless of the internal state of the device controller if OVERRIDE is set to high.
sahilmgandhi	18:6a4db94011d3	19029	* \| \| \|0 = Force CLKSTAT line low.
sahilmgandhi	18:6a4db94011d3	19030	* \| \| \|1 = Force CLKSTAT line high.
sahilmgandhi	18:6a4db94011d3	19031	* \|[11] \|FPS2DAT \|Force DATSTAT Line
sahilmgandhi	18:6a4db94011d3	19032	* \| \| \|It forces DATSTAT high or low regardless of the internal state of the device controller if OVERRIDE is set to high.
sahilmgandhi	18:6a4db94011d3	19033	* \| \| \|0 = Force DATSTAT low.
sahilmgandhi	18:6a4db94011d3	19034	* \| \| \|1 = Force DATSTAT high.
sahilmgandhi	18:6a4db94011d3	19035	*/
sahilmgandhi	18:6a4db94011d3	19036	__IO uint32_t CTL;
sahilmgandhi	18:6a4db94011d3	19037
sahilmgandhi	18:6a4db94011d3	19038	/**
sahilmgandhi	18:6a4db94011d3	19039	* TXDAT0
sahilmgandhi	18:6a4db94011d3	19040	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19041	* Offset: 0x04 PS/2 Transmit DATA Register 0
sahilmgandhi	18:6a4db94011d3	19042	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19043	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19044	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19045	* \|[0:31] \|DAT \|Transmit Data
sahilmgandhi	18:6a4db94011d3	19046	* \| \| \|Write data to this register starts device to host communication if bus is in IDLE state.
sahilmgandhi	18:6a4db94011d3	19047	* \| \| \|Software must enable PS2EN(PS2_CTL[0]) before writing data to TX buffer.
sahilmgandhi	18:6a4db94011d3	19048	*/
sahilmgandhi	18:6a4db94011d3	19049	__IO uint32_t TXDAT0;
sahilmgandhi	18:6a4db94011d3	19050
sahilmgandhi	18:6a4db94011d3	19051	/**
sahilmgandhi	18:6a4db94011d3	19052	* TXDAT1
sahilmgandhi	18:6a4db94011d3	19053	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19054	* Offset: 0x08 PS/2 Transmit DATA Register 1
sahilmgandhi	18:6a4db94011d3	19055	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19056	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19057	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19058	* \|[0:31] \|DAT \|Transmit Data
sahilmgandhi	18:6a4db94011d3	19059	* \| \| \|Write data to this register starts device to host communication if bus is in IDLE state.
sahilmgandhi	18:6a4db94011d3	19060	* \| \| \|Software must enable PS2EN(PS2_CTL[0]) before writing data to TX buffer.
sahilmgandhi	18:6a4db94011d3	19061	*/
sahilmgandhi	18:6a4db94011d3	19062	__IO uint32_t TXDAT1;
sahilmgandhi	18:6a4db94011d3	19063
sahilmgandhi	18:6a4db94011d3	19064	/**
sahilmgandhi	18:6a4db94011d3	19065	* TXDAT2
sahilmgandhi	18:6a4db94011d3	19066	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19067	* Offset: 0x0C PS/2 Transmit DATA Register 2
sahilmgandhi	18:6a4db94011d3	19068	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19069	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19070	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19071	* \|[0:31] \|DAT \|Transmit Data
sahilmgandhi	18:6a4db94011d3	19072	* \| \| \|Write data to this register starts device to host communication if bus is in IDLE state.
sahilmgandhi	18:6a4db94011d3	19073	* \| \| \|Software must enable PS2EN(PS2_CTL[0]) before writing data to TX buffer.
sahilmgandhi	18:6a4db94011d3	19074	*/
sahilmgandhi	18:6a4db94011d3	19075	__IO uint32_t TXDAT2;
sahilmgandhi	18:6a4db94011d3	19076
sahilmgandhi	18:6a4db94011d3	19077	/**
sahilmgandhi	18:6a4db94011d3	19078	* TXDAT3
sahilmgandhi	18:6a4db94011d3	19079	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19080	* Offset: 0x10 PS/2 Transmit DATA Register 3
sahilmgandhi	18:6a4db94011d3	19081	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19082	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19083	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19084	* \|[0:31] \|DAT \|Transmit Data
sahilmgandhi	18:6a4db94011d3	19085	* \| \| \|Write data to this register starts device to host communication if bus is in IDLE state.
sahilmgandhi	18:6a4db94011d3	19086	* \| \| \|Software must enable PS2EN(PS2_CTL[0]) before writing data to TX buffer.
sahilmgandhi	18:6a4db94011d3	19087	*/
sahilmgandhi	18:6a4db94011d3	19088	__IO uint32_t TXDAT3;
sahilmgandhi	18:6a4db94011d3	19089
sahilmgandhi	18:6a4db94011d3	19090	/**
sahilmgandhi	18:6a4db94011d3	19091	* RXDAT
sahilmgandhi	18:6a4db94011d3	19092	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19093	* Offset: 0x14 PS/2 Receive DATA Register
sahilmgandhi	18:6a4db94011d3	19094	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19095	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19096	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19097	* \|[0:7] \|DAT \|Received Data
sahilmgandhi	18:6a4db94011d3	19098	* \| \| \|For host to device communication, after acknowledge bit is sent, the received data is copied from receive shift register to PS2_RXDAT register.
sahilmgandhi	18:6a4db94011d3	19099	* \| \| \|CPU must read this register before next byte reception complete; otherwise, the data will be overwritten and RXOV(PS2_STATUS[6]) bit will be set to 1.
sahilmgandhi	18:6a4db94011d3	19100	*/
sahilmgandhi	18:6a4db94011d3	19101	__I uint32_t RXDAT;
sahilmgandhi	18:6a4db94011d3	19102
sahilmgandhi	18:6a4db94011d3	19103	/**
sahilmgandhi	18:6a4db94011d3	19104	* STATUS
sahilmgandhi	18:6a4db94011d3	19105	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19106	* Offset: 0x18 PS/2 Status Register
sahilmgandhi	18:6a4db94011d3	19107	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19108	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19109	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19110	* \|[0] \|CLKSTAT \|CLK Pin State
sahilmgandhi	18:6a4db94011d3	19111	* \| \| \|This bit reflects the status of the CLKSTAT line after synchronizing.
sahilmgandhi	18:6a4db94011d3	19112	* \|[1] \|DATSTAT \|DATA Pin State
sahilmgandhi	18:6a4db94011d3	19113	* \| \| \|This bit reflects the status of the DATSTAT line after synchronizing and sampling.
sahilmgandhi	18:6a4db94011d3	19114	* \|[2] \|FRAMEERR \|Frame Error
sahilmgandhi	18:6a4db94011d3	19115	* \| \| \|For host to device communication, if STOP bit (logic 1) is not received it is a frame error.
sahilmgandhi	18:6a4db94011d3	19116	* \| \| \|If frame error occurs, DATA line may keep at low state after 12th clock.
sahilmgandhi	18:6a4db94011d3	19117	* \| \| \|At this moment, software overrides CLKSTAT to send clock till DATSTAT release to high state.
sahilmgandhi	18:6a4db94011d3	19118	* \| \| \|After that, device sends a "Resend" command to host.
sahilmgandhi	18:6a4db94011d3	19119	* \| \| \|0 = No frame error.
sahilmgandhi	18:6a4db94011d3	19120	* \| \| \|1 = Frame error occurred .
sahilmgandhi	18:6a4db94011d3	19121	* \| \| \|Note: Write 1 to clear this bit.
sahilmgandhi	18:6a4db94011d3	19122	* \|[3] \|RXPARITY \|Received Parity
sahilmgandhi	18:6a4db94011d3	19123	* \| \| \|This bit reflects the parity bit for the last received data byte (odd parity).
sahilmgandhi	18:6a4db94011d3	19124	* \| \| \|Note: This bit is read only.
sahilmgandhi	18:6a4db94011d3	19125	* \|[4] \|RXBUSY \|Receive Busy
sahilmgandhi	18:6a4db94011d3	19126	* \| \| \|This bit indicates that the PS/2 device is currently receiving data.
sahilmgandhi	18:6a4db94011d3	19127	* \| \| \|0 = Idle.
sahilmgandhi	18:6a4db94011d3	19128	* \| \| \|1 = Currently receiving data.
sahilmgandhi	18:6a4db94011d3	19129	* \| \| \|Note: This bit is read only.
sahilmgandhi	18:6a4db94011d3	19130	* \|[5] \|TXBUSY \|Transmit Busy
sahilmgandhi	18:6a4db94011d3	19131	* \| \| \|This bit indicates that the PS/2 device is currently sending data.
sahilmgandhi	18:6a4db94011d3	19132	* \| \| \|0 = Idle.
sahilmgandhi	18:6a4db94011d3	19133	* \| \| \|1 = Currently sending data.
sahilmgandhi	18:6a4db94011d3	19134	* \| \| \|Note: This bit is read only.
sahilmgandhi	18:6a4db94011d3	19135	* \|[6] \|RXOV \|RX Buffer Overwrite
sahilmgandhi	18:6a4db94011d3	19136	* \| \| \|0 = No overwrite.
sahilmgandhi	18:6a4db94011d3	19137	* \| \| \|1 = Data in PS2_RXDAT register is overwritten by new received data.
sahilmgandhi	18:6a4db94011d3	19138	* \| \| \|Note: Write 1 to clear this bit.
sahilmgandhi	18:6a4db94011d3	19139	* \|[7] \|TXEMPTY \|TX FIFO Empty
sahilmgandhi	18:6a4db94011d3	19140	* \| \| \|When software writes any data to PS2_TXDAT0-3 the TXEMPTY bit is cleared to 0 immediately if PS2EN is enabled.
sahilmgandhi	18:6a4db94011d3	19141	* \| \| \|When transmitted data byte number is equal to FIFODEPTH then TXEMPTY bit is set to 1.
sahilmgandhi	18:6a4db94011d3	19142	* \| \| \|0 = There is data to be transmitted.
sahilmgandhi	18:6a4db94011d3	19143	* \| \| \|1 = FIFO is empty.
sahilmgandhi	18:6a4db94011d3	19144	* \| \| \|Note: This bit is read only.
sahilmgandhi	18:6a4db94011d3	19145	* \|[8:11] \|BYTEIDX \|Byte Index
sahilmgandhi	18:6a4db94011d3	19146	* \| \| \|It indicates which data byte in transmit data shift register.
sahilmgandhi	18:6a4db94011d3	19147	* \| \| \|When all data in FIFO is transmitted and it will be cleared to 0.
sahilmgandhi	18:6a4db94011d3	19148	* \| \| \|Note: This bit is read only.
sahilmgandhi	18:6a4db94011d3	19149	* \| \| \|BYTEIDX DATA Transmit
sahilmgandhi	18:6a4db94011d3	19150	* \| \| \|0000 TXDATA0[7:0]
sahilmgandhi	18:6a4db94011d3	19151	* \| \| \|0001 TXDATA0[15:8]
sahilmgandhi	18:6a4db94011d3	19152	* \| \| \|0010 TXDATA0[23:16]
sahilmgandhi	18:6a4db94011d3	19153	* \| \| \|0011 TXDATA0[31:24]
sahilmgandhi	18:6a4db94011d3	19154	* \| \| \|0100 TXDATA1[7:0]
sahilmgandhi	18:6a4db94011d3	19155	* \| \| \|0101 TXDATA1[15:8]
sahilmgandhi	18:6a4db94011d3	19156	* \| \| \|0110 TXDATA1[23:16]
sahilmgandhi	18:6a4db94011d3	19157	* \| \| \|0111 TXDATA1[31:24]
sahilmgandhi	18:6a4db94011d3	19158	* \| \| \|1000 TXDATA2[7:0]
sahilmgandhi	18:6a4db94011d3	19159	* \| \| \|1001 TXDATA2[15:8]
sahilmgandhi	18:6a4db94011d3	19160	* \| \| \|1010 TXDATA2[23:16]
sahilmgandhi	18:6a4db94011d3	19161	* \| \| \|1011 TXDATA2[31:24]
sahilmgandhi	18:6a4db94011d3	19162	* \| \| \|1100 TXDATA3[7:0]
sahilmgandhi	18:6a4db94011d3	19163	* \| \| \|1101 TXDATA3[15:8]
sahilmgandhi	18:6a4db94011d3	19164	* \| \| \|1110 TXDATA3[23:16]
sahilmgandhi	18:6a4db94011d3	19165	* \| \| \|1111 TXDATA3[31:24]
sahilmgandhi	18:6a4db94011d3	19166	*/
sahilmgandhi	18:6a4db94011d3	19167	__IO uint32_t STATUS;
sahilmgandhi	18:6a4db94011d3	19168
sahilmgandhi	18:6a4db94011d3	19169	/**
sahilmgandhi	18:6a4db94011d3	19170	* INTSTS
sahilmgandhi	18:6a4db94011d3	19171	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19172	* Offset: 0x1C PS/2 Interrupt Status Register
sahilmgandhi	18:6a4db94011d3	19173	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19174	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19175	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19176	* \|[0] \|RXIF \|Receive Interrupt
sahilmgandhi	18:6a4db94011d3	19177	* \| \| \|This bit is set to 1 when acknowledge bit is sent for Host to device communication.
sahilmgandhi	18:6a4db94011d3	19178	* \| \| \|Interrupt occurs if RXIEN(PS2_CTL[2]) bit is set to 1.
sahilmgandhi	18:6a4db94011d3	19179	* \| \| \|0 = No interrupt.
sahilmgandhi	18:6a4db94011d3	19180	* \| \| \|1 = Receive interrupt occurred.
sahilmgandhi	18:6a4db94011d3	19181	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	19182	* \|[1] \|TXIF \|Transmit Interrupt
sahilmgandhi	18:6a4db94011d3	19183	* \| \| \|This bit is set to 1 after STOP bit is transmitted. Interrupt occurs if TXIEN(PS2_CTL[1]) bit is set
sahilmgandhi	18:6a4db94011d3	19184	* \| \| \|to 1.
sahilmgandhi	18:6a4db94011d3	19185	* \| \| \|0 = No interrupt.
sahilmgandhi	18:6a4db94011d3	19186	* \| \| \|1 = Transmit interrupt occurred.
sahilmgandhi	18:6a4db94011d3	19187	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	19188	*/
sahilmgandhi	18:6a4db94011d3	19189	__IO uint32_t INTSTS;
sahilmgandhi	18:6a4db94011d3	19190
sahilmgandhi	18:6a4db94011d3	19191	} PS2_T;
sahilmgandhi	18:6a4db94011d3	19192
sahilmgandhi	18:6a4db94011d3	19193	/**
sahilmgandhi	18:6a4db94011d3	19194	@addtogroup PS2_CONST PS2 Bit Field Definition
sahilmgandhi	18:6a4db94011d3	19195	Constant Definitions for PS2 Controller
sahilmgandhi	18:6a4db94011d3	19196	@{ */
sahilmgandhi	18:6a4db94011d3	19197
sahilmgandhi	18:6a4db94011d3	19198	#define PS2_CTL_PS2EN_Pos (0) /!< PS2 CTL: PS2EN Position /
sahilmgandhi	18:6a4db94011d3	19199	#define PS2_CTL_PS2EN_Msk (0x1ul << PS2_CTL_PS2EN_Pos) /!< PS2 CTL: PS2EN Mask /
sahilmgandhi	18:6a4db94011d3	19200
sahilmgandhi	18:6a4db94011d3	19201	#define PS2_CTL_TXIEN_Pos (1) /!< PS2 CTL: TXIEN Position /
sahilmgandhi	18:6a4db94011d3	19202	#define PS2_CTL_TXIEN_Msk (0x1ul << PS2_CTL_TXIEN_Pos) /!< PS2 CTL: TXIEN Mask /
sahilmgandhi	18:6a4db94011d3	19203
sahilmgandhi	18:6a4db94011d3	19204	#define PS2_CTL_RXIEN_Pos (2) /!< PS2 CTL: RXIEN Position /
sahilmgandhi	18:6a4db94011d3	19205	#define PS2_CTL_RXIEN_Msk (0x1ul << PS2_CTL_RXIEN_Pos) /!< PS2 CTL: RXIEN Mask /
sahilmgandhi	18:6a4db94011d3	19206
sahilmgandhi	18:6a4db94011d3	19207	#define PS2_CTL_TXFDEPTH_Pos (3) /!< PS2 CTL: TXFDEPTH Position /
sahilmgandhi	18:6a4db94011d3	19208	#define PS2_CTL_TXFDEPTH_Msk (0xful << PS2_CTL_TXFDEPTH_Pos) /!< PS2 CTL: TXFDEPTH Mask /
sahilmgandhi	18:6a4db94011d3	19209
sahilmgandhi	18:6a4db94011d3	19210	#define PS2_CTL_ACK_Pos (7) /!< PS2 CTL: ACK Position /
sahilmgandhi	18:6a4db94011d3	19211	#define PS2_CTL_ACK_Msk (0x1ul << PS2_CTL_ACK_Pos) /!< PS2 CTL: ACK Mask /
sahilmgandhi	18:6a4db94011d3	19212
sahilmgandhi	18:6a4db94011d3	19213	#define PS2_CTL_CLRFIFO_Pos (8) /!< PS2 CTL: CLRFIFO Position /
sahilmgandhi	18:6a4db94011d3	19214	#define PS2_CTL_CLRFIFO_Msk (0x1ul << PS2_CTL_CLRFIFO_Pos) /!< PS2 CTL: CLRFIFO Mask /
sahilmgandhi	18:6a4db94011d3	19215
sahilmgandhi	18:6a4db94011d3	19216	#define PS2_CTL_OVERRIDE_Pos (9) /!< PS2 CTL: OVERRIDE Position /
sahilmgandhi	18:6a4db94011d3	19217	#define PS2_CTL_OVERRIDE_Msk (0x1ul << PS2_CTL_OVERRIDE_Pos) /!< PS2 CTL: OVERRIDE Mask /
sahilmgandhi	18:6a4db94011d3	19218
sahilmgandhi	18:6a4db94011d3	19219	#define PS2_CTL_FPS2CLK_Pos (10) /!< PS2 CTL: FPS2CLK Position /
sahilmgandhi	18:6a4db94011d3	19220	#define PS2_CTL_FPS2CLK_Msk (0x1ul << PS2_CTL_FPS2CLK_Pos) /!< PS2 CTL: FPS2CLK Mask /
sahilmgandhi	18:6a4db94011d3	19221
sahilmgandhi	18:6a4db94011d3	19222	#define PS2_CTL_FPS2DAT_Pos (11) /!< PS2 CTL: FPS2DAT Position /
sahilmgandhi	18:6a4db94011d3	19223	#define PS2_CTL_FPS2DAT_Msk (0x1ul << PS2_CTL_FPS2DAT_Pos) /!< PS2 CTL: FPS2DAT Mask /
sahilmgandhi	18:6a4db94011d3	19224
sahilmgandhi	18:6a4db94011d3	19225	#define PS2_TXDAT0_DAT_Pos (0) /!< PS2 TXDAT0: DAT Position /
sahilmgandhi	18:6a4db94011d3	19226	#define PS2_TXDAT0_DAT_Msk (0xfffffffful << PS2_TXDAT0_DAT_Pos) /!< PS2 TXDAT0: DAT Mask /
sahilmgandhi	18:6a4db94011d3	19227
sahilmgandhi	18:6a4db94011d3	19228	#define PS2_TXDAT1_DAT_Pos (0) /!< PS2 TXDAT1: DAT Position /
sahilmgandhi	18:6a4db94011d3	19229	#define PS2_TXDAT1_DAT_Msk (0xfffffffful << PS2_TXDAT1_DAT_Pos) /!< PS2 TXDAT1: DAT Mask /
sahilmgandhi	18:6a4db94011d3	19230
sahilmgandhi	18:6a4db94011d3	19231	#define PS2_TXDAT2_DAT_Pos (0) /!< PS2 TXDAT2: DAT Position /
sahilmgandhi	18:6a4db94011d3	19232	#define PS2_TXDAT2_DAT_Msk (0xfffffffful << PS2_TXDAT2_DAT_Pos) /!< PS2 TXDAT2: DAT Mask /
sahilmgandhi	18:6a4db94011d3	19233
sahilmgandhi	18:6a4db94011d3	19234	#define PS2_TXDAT3_DAT_Pos (0) /!< PS2 TXDAT3: DAT Position /
sahilmgandhi	18:6a4db94011d3	19235	#define PS2_TXDAT3_DAT_Msk (0xfffffffful << PS2_TXDAT3_DAT_Pos) /!< PS2 TXDAT3: DAT Mask /
sahilmgandhi	18:6a4db94011d3	19236
sahilmgandhi	18:6a4db94011d3	19237	#define PS2_RXDAT_DAT_Pos (0) /!< PS2 RXDAT: DAT Position /
sahilmgandhi	18:6a4db94011d3	19238	#define PS2_RXDAT_DAT_Msk (0xfful << PS2_RXDAT_DAT_Pos) /!< PS2 RXDAT: DAT Mask /
sahilmgandhi	18:6a4db94011d3	19239
sahilmgandhi	18:6a4db94011d3	19240	#define PS2_STATUS_CLKSTAT_Pos (0) /!< PS2 STATUS: CLKSTAT Position /
sahilmgandhi	18:6a4db94011d3	19241	#define PS2_STATUS_CLKSTAT_Msk (0x1ul << PS2_STATUS_CLKSTAT_Pos) /!< PS2 STATUS: CLKSTAT Mask /
sahilmgandhi	18:6a4db94011d3	19242
sahilmgandhi	18:6a4db94011d3	19243	#define PS2_STATUS_DATSTAT_Pos (1) /!< PS2 STATUS: DATSTAT Position /
sahilmgandhi	18:6a4db94011d3	19244	#define PS2_STATUS_DATSTAT_Msk (0x1ul << PS2_STATUS_DATSTAT_Pos) /!< PS2 STATUS: DATSTAT Mask /
sahilmgandhi	18:6a4db94011d3	19245
sahilmgandhi	18:6a4db94011d3	19246	#define PS2_STATUS_FRAMEERR_Pos (2) /!< PS2 STATUS: FRAMEERR Position /
sahilmgandhi	18:6a4db94011d3	19247	#define PS2_STATUS_FRAMEERR_Msk (0x1ul << PS2_STATUS_FRAMEERR_Pos) /!< PS2 STATUS: FRAMEERR Mask /
sahilmgandhi	18:6a4db94011d3	19248
sahilmgandhi	18:6a4db94011d3	19249	#define PS2_STATUS_RXPARITY_Pos (3) /!< PS2 STATUS: RXPARITY Position /
sahilmgandhi	18:6a4db94011d3	19250	#define PS2_STATUS_RXPARITY_Msk (0x1ul << PS2_STATUS_RXPARITY_Pos) /!< PS2 STATUS: RXPARITY Mask /
sahilmgandhi	18:6a4db94011d3	19251
sahilmgandhi	18:6a4db94011d3	19252	#define PS2_STATUS_RXBUSY_Pos (4) /!< PS2 STATUS: RXBUSY Position /
sahilmgandhi	18:6a4db94011d3	19253	#define PS2_STATUS_RXBUSY_Msk (0x1ul << PS2_STATUS_RXBUSY_Pos) /!< PS2 STATUS: RXBUSY Mask /
sahilmgandhi	18:6a4db94011d3	19254
sahilmgandhi	18:6a4db94011d3	19255	#define PS2_STATUS_TXBUSY_Pos (5) /!< PS2 STATUS: TXBUSY Position /
sahilmgandhi	18:6a4db94011d3	19256	#define PS2_STATUS_TXBUSY_Msk (0x1ul << PS2_STATUS_TXBUSY_Pos) /!< PS2 STATUS: TXBUSY Mask /
sahilmgandhi	18:6a4db94011d3	19257
sahilmgandhi	18:6a4db94011d3	19258	#define PS2_STATUS_RXOV_Pos (6) /!< PS2 STATUS: RXOV Position /
sahilmgandhi	18:6a4db94011d3	19259	#define PS2_STATUS_RXOV_Msk (0x1ul << PS2_STATUS_RXOV_Pos) /!< PS2 STATUS: RXOV Mask /
sahilmgandhi	18:6a4db94011d3	19260
sahilmgandhi	18:6a4db94011d3	19261	#define PS2_STATUS_TXEMPTY_Pos (7) /!< PS2 STATUS: TXEMPTY Position /
sahilmgandhi	18:6a4db94011d3	19262	#define PS2_STATUS_TXEMPTY_Msk (0x1ul << PS2_STATUS_TXEMPTY_Pos) /!< PS2 STATUS: TXEMPTY Mask /
sahilmgandhi	18:6a4db94011d3	19263
sahilmgandhi	18:6a4db94011d3	19264	#define PS2_STATUS_BYTEIDX_Pos (8) /!< PS2 STATUS: BYTEIDX Position /
sahilmgandhi	18:6a4db94011d3	19265	#define PS2_STATUS_BYTEIDX_Msk (0xful << PS2_STATUS_BYTEIDX_Pos) /!< PS2 STATUS: BYTEIDX Mask /
sahilmgandhi	18:6a4db94011d3	19266
sahilmgandhi	18:6a4db94011d3	19267	#define PS2_INTSTS_RXIF_Pos (0) /!< PS2 INTSTS: RXIF Position /
sahilmgandhi	18:6a4db94011d3	19268	#define PS2_INTSTS_RXIF_Msk (0x1ul << PS2_INTSTS_RXIF_Pos) /!< PS2 INTSTS: RXIF Mask /
sahilmgandhi	18:6a4db94011d3	19269
sahilmgandhi	18:6a4db94011d3	19270	#define PS2_INTSTS_TXIF_Pos (1) /!< PS2 INTSTS: TXIF Position /
sahilmgandhi	18:6a4db94011d3	19271	#define PS2_INTSTS_TXIF_Msk (0x1ul << PS2_INTSTS_TXIF_Pos) /!< PS2 INTSTS: TXIF Mask /
sahilmgandhi	18:6a4db94011d3	19272
sahilmgandhi	18:6a4db94011d3	19273	/*@}/ /* PS2_CONST */
sahilmgandhi	18:6a4db94011d3	19274	/*@}/ /* end of PS2 register group */
sahilmgandhi	18:6a4db94011d3	19275
sahilmgandhi	18:6a4db94011d3	19276
sahilmgandhi	18:6a4db94011d3	19277	/---------------------- Pulse Width Modulation Controller -------------------------/
sahilmgandhi	18:6a4db94011d3	19278	/**
sahilmgandhi	18:6a4db94011d3	19279	@addtogroup PWM Pulse Width Modulation Controller(PWM)
sahilmgandhi	18:6a4db94011d3	19280	Memory Mapped Structure for PWM Controller
sahilmgandhi	18:6a4db94011d3	19281	@{ */
sahilmgandhi	18:6a4db94011d3	19282
sahilmgandhi	18:6a4db94011d3	19283	typedef struct {
sahilmgandhi	18:6a4db94011d3	19284
sahilmgandhi	18:6a4db94011d3	19285
sahilmgandhi	18:6a4db94011d3	19286	/**
sahilmgandhi	18:6a4db94011d3	19287	* CLKPSC
sahilmgandhi	18:6a4db94011d3	19288	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19289	* Offset: 0x00 PWM Clock Prescale Register
sahilmgandhi	18:6a4db94011d3	19290	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19291	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19292	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19293	* \|[0:7] \|CLKPSC01 \|PWM Counter Base-Clock Prescale For PWM Pair Of Channel 0 And Channel 1
sahilmgandhi	18:6a4db94011d3	19294	* \| \| \|The base-clock of PWM counter is decided by clock pre-scalar and clock divider.
sahilmgandhi	18:6a4db94011d3	19295	* \| \| \|Each PWM pair share one PWM counter base-clock prescaler.
sahilmgandhi	18:6a4db94011d3	19296	* \| \| \|The base-clock of PWM counter is divided by (CLKPSC01 + 1).
sahilmgandhi	18:6a4db94011d3	19297	* \| \| \|If the value of CLKPSC01 is zero, the base-clock prescaler will stop output clock and corresponding PWM counter will also stop.
sahilmgandhi	18:6a4db94011d3	19298	* \|[8:15] \|CLKPSC23 \|PWM Counter Base-Clock Prescale For PWM Pair Of Channel 2 And Channel 3
sahilmgandhi	18:6a4db94011d3	19299	* \| \| \|The base-clock of PWM counter is decided by clock pre-scalar and clock divider.
sahilmgandhi	18:6a4db94011d3	19300	* \| \| \|Each PWM pair share one PWM counter base-clock prescaler.
sahilmgandhi	18:6a4db94011d3	19301	* \| \| \|The base-clock of PWM counter is divided by (CLKPSC23 + 1).
sahilmgandhi	18:6a4db94011d3	19302	* \| \| \|If the value of CLKPSC23 is zero, the base-clock prescaler will stop output clock and corresponding PWM counter will also stop.
sahilmgandhi	18:6a4db94011d3	19303	* \|[16:23] \|CLKPSC45 \|PWM Counter Base-Clock Prescale For PWM Pair Of Channel 4 And Channel 5
sahilmgandhi	18:6a4db94011d3	19304	* \| \| \|The base-clock of PWM counter is decided by clock pre-scalar and clock divider.
sahilmgandhi	18:6a4db94011d3	19305	* \| \| \|Each PWM pair share one PWM counter base-clock prescaler.
sahilmgandhi	18:6a4db94011d3	19306	* \| \| \|The base-clock of PWM counter is divided by (CLKPSC45 + 1).
sahilmgandhi	18:6a4db94011d3	19307	* \| \| \|If the value of CLKPSC45 is zero, the base-clock prescaler will stop output clock and corresponding PWM counter will also stop.
sahilmgandhi	18:6a4db94011d3	19308	*/
sahilmgandhi	18:6a4db94011d3	19309	__IO uint32_t CLKPSC;
sahilmgandhi	18:6a4db94011d3	19310
sahilmgandhi	18:6a4db94011d3	19311	/**
sahilmgandhi	18:6a4db94011d3	19312	* CLKDIV
sahilmgandhi	18:6a4db94011d3	19313	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19314	* Offset: 0x04 PWM Clock Divide Register
sahilmgandhi	18:6a4db94011d3	19315	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19316	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19317	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19318	* \|[0:2] \|CLKDIV0 \|PWM Counter Base-Clock Divide For PWMx_CH0
sahilmgandhi	18:6a4db94011d3	19319	* \| \| \|(Table is the same as CLKDIV5)
sahilmgandhi	18:6a4db94011d3	19320	* \|[4:6] \|CLKDIV1 \|PWM Counter Base-Clock Divide For PWMx_CH1
sahilmgandhi	18:6a4db94011d3	19321	* \| \| \|(Table is the same as CLKDIV5)
sahilmgandhi	18:6a4db94011d3	19322	* \|[8:10] \|CLKDIV2 \|PWM Counter Base-Clock Divide For PWMx_CH2
sahilmgandhi	18:6a4db94011d3	19323	* \| \| \|(Table is the same as CLKDIV5)
sahilmgandhi	18:6a4db94011d3	19324	* \|[12:14] \|CLKDIV3 \|PWM Counter Base-Clock Divide For PWMx_CH3
sahilmgandhi	18:6a4db94011d3	19325	* \| \| \|(Table is the same as CLKDIV5)
sahilmgandhi	18:6a4db94011d3	19326	* \|[16:18] \|CLKDIV4 \|PWM Counter Base-Clock Divide For PWMx_CH4
sahilmgandhi	18:6a4db94011d3	19327	* \| \| \|(Table is the same as CLKDIV5)
sahilmgandhi	18:6a4db94011d3	19328	* \|[20:22] \|CLKDIV5 \|PWM Counter Base-Clock Divide For PWMx_CH5
sahilmgandhi	18:6a4db94011d3	19329	* \| \| \|The base-clock of PWM counter is decided by clock pre-scalar and clock divider.
sahilmgandhi	18:6a4db94011d3	19330	* \| \| \|Each PWM counter has independent clock divider control register and the divided value is listed in the table below:.
sahilmgandhi	18:6a4db94011d3	19331	* \| \| \|000 = 2.
sahilmgandhi	18:6a4db94011d3	19332	* \| \| \|001 = 4.
sahilmgandhi	18:6a4db94011d3	19333	* \| \| \|010 = 8.
sahilmgandhi	18:6a4db94011d3	19334	* \| \| \|011 = 16.
sahilmgandhi	18:6a4db94011d3	19335	* \| \| \|100 = 1.
sahilmgandhi	18:6a4db94011d3	19336	*/
sahilmgandhi	18:6a4db94011d3	19337	__IO uint32_t CLKDIV;
sahilmgandhi	18:6a4db94011d3	19338
sahilmgandhi	18:6a4db94011d3	19339	/**
sahilmgandhi	18:6a4db94011d3	19340	* CTL
sahilmgandhi	18:6a4db94011d3	19341	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19342	* Offset: 0x08 PWM Control Register
sahilmgandhi	18:6a4db94011d3	19343	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19344	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19345	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19346	* \|[0:5] \|CMPINV \|PWM Comparator Output Inverter Enable Control
sahilmgandhi	18:6a4db94011d3	19347	* \| \| \|When CMPINV is set to high, the PWM comparator output signals will be inversed,
sahilmgandhi	18:6a4db94011d3	19348	* \| \| \|0 = Comparator output inverter Disabled.
sahilmgandhi	18:6a4db94011d3	19349	* \| \| \|1 = Comparator output inverter Enabled.
sahilmgandhi	18:6a4db94011d3	19350	* \| \| \|Note: Each bit control corresponding PWM channel
sahilmgandhi	18:6a4db94011d3	19351	* \|[6] \|OUTMODE \|PWM Output Mode
sahilmgandhi	18:6a4db94011d3	19352	* \| \| \|The register controls the output mode of PWM
sahilmgandhi	18:6a4db94011d3	19353	* \| \| \|0 = PWM output at independent mode.
sahilmgandhi	18:6a4db94011d3	19354	* \| \| \|1 = PWM output at complementary mode.
sahilmgandhi	18:6a4db94011d3	19355	* \|[7] \|GROUPEN \|Group Mode Enable Control
sahilmgandhi	18:6a4db94011d3	19356	* \| \| \|0 = The signals timing of each PWM channel are independent.
sahilmgandhi	18:6a4db94011d3	19357	* \| \| \|1 = Unify the signals timing of PWM0, PWM2 and PWM4 in the same phase which is controlled by PWM0 and unify the signals timing of PWM1, PWM3 and PWM5 in the same phase which is controlled by PWM1.
sahilmgandhi	18:6a4db94011d3	19358	* \|[8:13] \|PINV \|PWM Output Polar Inverse Enable Control
sahilmgandhi	18:6a4db94011d3	19359	* \| \| \|The register controls polarity state of PWM output
sahilmgandhi	18:6a4db94011d3	19360	* \| \| \|0 = PWM output polar inverse Disabled.
sahilmgandhi	18:6a4db94011d3	19361	* \| \| \|1 = PWM output polar inverse Enabled.
sahilmgandhi	18:6a4db94011d3	19362	* \| \| \|Note: Each bit controls the corresponding PWM channel.
sahilmgandhi	18:6a4db94011d3	19363	* \|[15] \|SYNCEN \|Synchronous Mode Enable Control
sahilmgandhi	18:6a4db94011d3	19364	* \| \| \|0 = The signals timing of each PWM channel are independent.
sahilmgandhi	18:6a4db94011d3	19365	* \| \| \|1 = Unify the signals timing of PWM0 and PWM1 in the same phase which is controlled by PWM0 and so as another two PWM pair.
sahilmgandhi	18:6a4db94011d3	19366	* \| \| \|Note: If Group and Synchronous mode are enabled simultaneously, the Synchronous mode will be inactive.
sahilmgandhi	18:6a4db94011d3	19367	* \|[16:21] \|CNTMODE \|PWM Counter Operation Mode
sahilmgandhi	18:6a4db94011d3	19368	* \| \| \|0 = PWM counter working as One-shot mode.
sahilmgandhi	18:6a4db94011d3	19369	* \| \| \|1 = PWM counter working as Auto-reload mode.
sahilmgandhi	18:6a4db94011d3	19370	* \| \| \|Note: Each bit control corresponding PWM channel
sahilmgandhi	18:6a4db94011d3	19371	* \| \| \|Note: If there is a transition at this bit, it will cause PWM_PERIODn and PWM_CMPDATn be cleared.
sahilmgandhi	18:6a4db94011d3	19372	* \|[24:29] \|CNTTYPE \|PWM Counter Operation Aligned Type
sahilmgandhi	18:6a4db94011d3	19373	* \| \| \|0 = PWM counter operating as Edge-aligned type.
sahilmgandhi	18:6a4db94011d3	19374	* \| \| \|1 = PWM counter operating as Center-aligned type.
sahilmgandhi	18:6a4db94011d3	19375	* \| \| \|Note: Each bit control corresponding PWM channel
sahilmgandhi	18:6a4db94011d3	19376	* \|[31] \|DBGTRIOFF \|ICE Debug Mode Acknowledge Disable Control (Write Protect)
sahilmgandhi	18:6a4db94011d3	19377	* \| \| \|0 = ICE debug mode acknowledgement effects PWM output.
sahilmgandhi	18:6a4db94011d3	19378	* \| \| \|PWM pin will be forced as tri-state while ICE debug mode acknowledged.
sahilmgandhi	18:6a4db94011d3	19379	* \| \| \|1 = ICE debug mode acknowledgement disabled.
sahilmgandhi	18:6a4db94011d3	19380	* \| \| \|PWM pin will keep output no matter ICE debug mode acknowledged or not.
sahilmgandhi	18:6a4db94011d3	19381	*/
sahilmgandhi	18:6a4db94011d3	19382	__IO uint32_t CTL;
sahilmgandhi	18:6a4db94011d3	19383
sahilmgandhi	18:6a4db94011d3	19384	/**
sahilmgandhi	18:6a4db94011d3	19385	* CNTEN
sahilmgandhi	18:6a4db94011d3	19386	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19387	* Offset: 0x0C PWM Counter Enable Control Register
sahilmgandhi	18:6a4db94011d3	19388	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19389	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19390	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19391	* \|[0:5] \|CNTEN \|PWM Counter Enable Control
sahilmgandhi	18:6a4db94011d3	19392	* \| \| \|0 = PWM Counter Stop Running.
sahilmgandhi	18:6a4db94011d3	19393	* \| \| \|1 = PWM Counter Start Running.
sahilmgandhi	18:6a4db94011d3	19394	* \| \| \|Note: Each bit controls the corresponding PWM channel.
sahilmgandhi	18:6a4db94011d3	19395	*/
sahilmgandhi	18:6a4db94011d3	19396	__IO uint32_t CNTEN;
sahilmgandhi	18:6a4db94011d3	19397
sahilmgandhi	18:6a4db94011d3	19398	/**
sahilmgandhi	18:6a4db94011d3	19399	* PERIOD
sahilmgandhi	18:6a4db94011d3	19400	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19401	* Offset: 0x10 ~ 0x24 PWM Counter Register
sahilmgandhi	18:6a4db94011d3	19402	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19403	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19404	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19405	* \|[0:15] \|PERIOD \|PWM Period Register
sahilmgandhi	18:6a4db94011d3	19406	* \| \| \|PERIOD determines the PWM period.
sahilmgandhi	18:6a4db94011d3	19407	* \| \| \|PWM frequency = PWMxy_CLK/[(prescale+1)(clock divider)(PERIOD+1)]; where xy, could be 01, 23 or 45, depends on selected PWM channel.
sahilmgandhi	18:6a4db94011d3	19408	* \| \| \|For Edge-aligned mode:
sahilmgandhi	18:6a4db94011d3	19409	* \| \| \|l Duty ratio = (CMP+1)/(PERIOD+1).
sahilmgandhi	18:6a4db94011d3	19410	* \| \| \|l CMP >= PERIOD: PWM output is always high.
sahilmgandhi	18:6a4db94011d3	19411	* \| \| \|l CMP < PERIOD: PWM low width = (PERIOD-CMP) unit; PWM high width = (CMP+1) unit.
sahilmgandhi	18:6a4db94011d3	19412	* \| \| \|l CMP = 0: PWM low width = (PERIOD) unit; PWM high width = 1 unit.
sahilmgandhi	18:6a4db94011d3	19413	* \| \| \|For Center-aligned mode:
sahilmgandhi	18:6a4db94011d3	19414	* \| \| \|l Duty ratio = [(2 x CMP) + 1]/[2 x (PERIOD+1)].
sahilmgandhi	18:6a4db94011d3	19415	* \| \| \|l CMP > PERIOD: PWM output is always high.
sahilmgandhi	18:6a4db94011d3	19416	* \| \| \|l CMP <= PERIOD: PWM low width = 2 x (PERIOD-CMP) + 1 unit; PWM high width = (2 x CMP) + 1 unit.
sahilmgandhi	18:6a4db94011d3	19417	* \| \| \|l CMP = 0: PWM low width = 2 x PERIOD + 1 unit; PWM high width = 1 unit.
sahilmgandhi	18:6a4db94011d3	19418	* \| \| \|(Unit = one PWM clock cycle).
sahilmgandhi	18:6a4db94011d3	19419	* \| \| \|Note1: Any write to PERIOD will take effect in next PWM cycle.
sahilmgandhi	18:6a4db94011d3	19420	* \| \| \|Note2: When PWM operating at center-aligned type, PERIOD value should be set between 0x0000 to 0xFFFE.
sahilmgandhi	18:6a4db94011d3	19421	* \| \| \|If PERIOD equal to 0xFFFF, the PWM will work unpredictable.
sahilmgandhi	18:6a4db94011d3	19422	* \| \| \|Note3: When PERIOD value is set to 0, PWM output is always high.
sahilmgandhi	18:6a4db94011d3	19423	*/
sahilmgandhi	18:6a4db94011d3	19424	__IO uint32_t PERIOD[6];
sahilmgandhi	18:6a4db94011d3	19425
sahilmgandhi	18:6a4db94011d3	19426	/**
sahilmgandhi	18:6a4db94011d3	19427	* CMPDAT
sahilmgandhi	18:6a4db94011d3	19428	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19429	* Offset: 0x28 ~0x3C PWM Comparator Register
sahilmgandhi	18:6a4db94011d3	19430	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19431	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19432	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19433	* \|[0:15] \|CMP \|PWM Duty Register
sahilmgandhi	18:6a4db94011d3	19434	* \| \| \|CMP determines the PWM duty.
sahilmgandhi	18:6a4db94011d3	19435	* \| \| \|PWM frequency = PWMxy_CLK/[(prescale+1)(clock divider)(PERIOD+1)]; where xy, could be 01, 23 or, 45, depends on selected PWM channel.
sahilmgandhi	18:6a4db94011d3	19436	* \| \| \|For Edge-aligned mode:
sahilmgandhi	18:6a4db94011d3	19437	* \| \| \|l Duty ratio = (CMP+1)/(PERIOD+1).
sahilmgandhi	18:6a4db94011d3	19438	* \| \| \|l CMP >= PERIOD: PWM output is always high.
sahilmgandhi	18:6a4db94011d3	19439	* \| \| \|l CMP < PERIOD: PWM low width = (PERIOD-CMP) unit; PWM high width = (CMP+1) unit.
sahilmgandhi	18:6a4db94011d3	19440	* \| \| \|l CMP = 0: PWM low width = (PERIOD) unit; PWM high width = 1 unit.
sahilmgandhi	18:6a4db94011d3	19441	* \| \| \|For Center-aligned mode:
sahilmgandhi	18:6a4db94011d3	19442	* \| \| \|l Duty ratio = [(2 x CMP) + 1]/[2 x (PERIOD+1)].
sahilmgandhi	18:6a4db94011d3	19443	* \| \| \|l CMP > PERIOD: PWM output is always high.
sahilmgandhi	18:6a4db94011d3	19444	* \| \| \|l CMP <= PERIOD: PWM low width = 2 x (PERIOD-CMP) + 1 unit; PWM high width = (2 x CMP) + 1 unit.
sahilmgandhi	18:6a4db94011d3	19445	* \| \| \|l CMP = 0: PWM low width = 2 x PERIOD + 1 unit; PWM high width = 1 unit.
sahilmgandhi	18:6a4db94011d3	19446	* \| \| \|(Unit = one PWM clock cycle).
sahilmgandhi	18:6a4db94011d3	19447	* \| \| \|Note: Any write to CMP will take effect in next PWM cycle.
sahilmgandhi	18:6a4db94011d3	19448	*/
sahilmgandhi	18:6a4db94011d3	19449	__IO uint32_t CMPDAT[6];
sahilmgandhi	18:6a4db94011d3	19450
sahilmgandhi	18:6a4db94011d3	19451	/**
sahilmgandhi	18:6a4db94011d3	19452	* CNT
sahilmgandhi	18:6a4db94011d3	19453	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19454	* Offset: 0x40 ~ 0x54 PWM Data Register
sahilmgandhi	18:6a4db94011d3	19455	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19456	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19457	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19458	* \|[0:15] \|CNT \|PWM Data Register
sahilmgandhi	18:6a4db94011d3	19459	* \| \| \|User can monitor CNT to know the current value in 16-bit down counter.
sahilmgandhi	18:6a4db94011d3	19460	* \| \| \|Note: It is recommended that read this register when PWM engine clock is source from system clock, otherwise a transition value of PWM counter may be read.
sahilmgandhi	18:6a4db94011d3	19461	*/
sahilmgandhi	18:6a4db94011d3	19462	__I uint32_t CNT[6];
sahilmgandhi	18:6a4db94011d3	19463
sahilmgandhi	18:6a4db94011d3	19464	/**
sahilmgandhi	18:6a4db94011d3	19465	* MSKEN
sahilmgandhi	18:6a4db94011d3	19466	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19467	* Offset: 0x58 PWM Mask Control Register
sahilmgandhi	18:6a4db94011d3	19468	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19469	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19470	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19471	* \|[0:5] \|MSKEN \|PWM Mask Enable Control
sahilmgandhi	18:6a4db94011d3	19472	* \| \| \|The PWM output signal will be masked when this bit is enabled.
sahilmgandhi	18:6a4db94011d3	19473	* \| \| \|The corresponding PWMn channel will be output with MSKDAT data.
sahilmgandhi	18:6a4db94011d3	19474	* \| \| \|0 = PWM output signal is non-masked.
sahilmgandhi	18:6a4db94011d3	19475	* \| \| \|1 = PWM output signal is masked and output with MSKDAT data.
sahilmgandhi	18:6a4db94011d3	19476	* \| \| \|Note: Each bit controls the corresponding PWM channel.
sahilmgandhi	18:6a4db94011d3	19477	*/
sahilmgandhi	18:6a4db94011d3	19478	__IO uint32_t MSKEN;
sahilmgandhi	18:6a4db94011d3	19479
sahilmgandhi	18:6a4db94011d3	19480	/**
sahilmgandhi	18:6a4db94011d3	19481	* MSK
sahilmgandhi	18:6a4db94011d3	19482	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19483	* Offset: 0x5C PWM Mask Data Register
sahilmgandhi	18:6a4db94011d3	19484	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19485	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19486	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19487	* \|[0:5] \|MSKDAT \|PWM Mask Data Bit:
sahilmgandhi	18:6a4db94011d3	19488	* \| \| \|This data bit control the state of PWMn output pin, if corresponding mask function is enabled.
sahilmgandhi	18:6a4db94011d3	19489	* \| \| \|0 = Output logic low to PWMn.
sahilmgandhi	18:6a4db94011d3	19490	* \| \| \|1 = Output logic high to PWMn.
sahilmgandhi	18:6a4db94011d3	19491	* \| \| \|Note: Each bit controls the corresponding PWM channel.
sahilmgandhi	18:6a4db94011d3	19492	*/
sahilmgandhi	18:6a4db94011d3	19493	__IO uint32_t MSK;
sahilmgandhi	18:6a4db94011d3	19494
sahilmgandhi	18:6a4db94011d3	19495	/**
sahilmgandhi	18:6a4db94011d3	19496	* DTCTL
sahilmgandhi	18:6a4db94011d3	19497	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19498	* Offset: 0x60 PWM Dead-zone Control Register
sahilmgandhi	18:6a4db94011d3	19499	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19500	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19501	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19502	* \|[0:7] \|DTCNT01 \|Dead-Zone Interval For PWM Pair Of Channel 0 And Channel 1
sahilmgandhi	18:6a4db94011d3	19503	* \| \| \|These 8-bit determine the Dead-zone length.
sahilmgandhi	18:6a4db94011d3	19504	* \| \| \|The unit time of Dead-zone length is received from corresponding PWM_CLKDIV.
sahilmgandhi	18:6a4db94011d3	19505	* \|[8:15] \|DTCNT23 \|Dead-Zone Interval For PWM Pair Of Channel 2 And Channel 3
sahilmgandhi	18:6a4db94011d3	19506	* \| \| \|These 8-bit determine the Dead-zone length.
sahilmgandhi	18:6a4db94011d3	19507	* \| \| \|The unit time of Dead-zone length is received from corresponding PWM_CLKDIV.
sahilmgandhi	18:6a4db94011d3	19508	* \|[16:23] \|DTCNT45 \|Dead-Zone Interval For PWM Pair Of Channel 4 And Channel 5
sahilmgandhi	18:6a4db94011d3	19509	* \| \| \|These 8-bit determine the Dead-zone length.
sahilmgandhi	18:6a4db94011d3	19510	* \| \| \|The unit time of Dead-zone length is received from corresponding PWM_CLKDIV.
sahilmgandhi	18:6a4db94011d3	19511	* \|[24:25] \|DTDIV \|Dead-Zone Generator Divider
sahilmgandhi	18:6a4db94011d3	19512	* \| \| \|00 = Dead-zone clock equal to PWM base clock divide 1.
sahilmgandhi	18:6a4db94011d3	19513	* \| \| \|01 = Dead-zone clock equal to PWM base clock divide 2.
sahilmgandhi	18:6a4db94011d3	19514	* \| \| \|10 = Dead-zone clock equal to PWM base clock divide 4.
sahilmgandhi	18:6a4db94011d3	19515	* \| \| \|11 = Dead-zone clock equal to PWM base clock divide 8.
sahilmgandhi	18:6a4db94011d3	19516	* \|[28] \|DTEN01 \|Dead-Zone Enable Control For PWM Pair Of Channel 0 And Channel 1
sahilmgandhi	18:6a4db94011d3	19517	* \| \| \|Dead-zone insertion is only active when this pair of complementary PWM is enabled.
sahilmgandhi	18:6a4db94011d3	19518	* \| \| \|If Dead-zone insertion is inactive, the outputs of pin pair are complementary without any delay.
sahilmgandhi	18:6a4db94011d3	19519	* \| \| \|0 = Dead-zone insertion Disabled.
sahilmgandhi	18:6a4db94011d3	19520	* \| \| \|1 = Dead-zone insertion Enabled.
sahilmgandhi	18:6a4db94011d3	19521	* \|[29] \|DTEN23 \|Dead-Zone Enable Control For PWM Pair Of Channel 2 And Channel 3
sahilmgandhi	18:6a4db94011d3	19522	* \| \| \|Dead-zone insertion is only active when this pair of complementary PWM is enabled.
sahilmgandhi	18:6a4db94011d3	19523	* \| \| \|If Dead-zone insertion is inactive, the outputs of pin pair are complementary without any delay.
sahilmgandhi	18:6a4db94011d3	19524	* \| \| \|0 = Dead-zone insertion Disabled.
sahilmgandhi	18:6a4db94011d3	19525	* \| \| \|1 = Dead-zone insertion Enabled.
sahilmgandhi	18:6a4db94011d3	19526	* \|[30] \|DTEN45 \|Dead-Zone Enable Control For PWM Pair Of Channel 4 And Channel 5
sahilmgandhi	18:6a4db94011d3	19527	* \| \| \|Dead-zone insertion is only active when this pair of complementary PWM is enabled.
sahilmgandhi	18:6a4db94011d3	19528	* \| \| \|If Dead-zone insertion is inactive, the outputs of pin pair are complementary without any delay.
sahilmgandhi	18:6a4db94011d3	19529	* \| \| \|0 = Dead-zone insertion Disabled.
sahilmgandhi	18:6a4db94011d3	19530	* \| \| \|1 = Dead-zone insertion Enabled.
sahilmgandhi	18:6a4db94011d3	19531	*/
sahilmgandhi	18:6a4db94011d3	19532	__IO uint32_t DTCTL;
sahilmgandhi	18:6a4db94011d3	19533
sahilmgandhi	18:6a4db94011d3	19534	/**
sahilmgandhi	18:6a4db94011d3	19535	* TRGADCTL
sahilmgandhi	18:6a4db94011d3	19536	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19537	* Offset: 0x64 PWM Trigger Control Register
sahilmgandhi	18:6a4db94011d3	19538	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19539	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19540	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19541	* \|[0:5] \|PTRGEN \|PWM Period Point Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	19542	* \| \| \|0 = PWM period point trigger ADC function Disabled.
sahilmgandhi	18:6a4db94011d3	19543	* \| \| \|1 = PWM period point trigger ADC function Enabled.
sahilmgandhi	18:6a4db94011d3	19544	* \| \| \|PWM can trigger ADC to start conversion when PWM counter down count to zero if this bit is set to1.
sahilmgandhi	18:6a4db94011d3	19545	* \| \| \|Note: Each bit controls the corresponding PWM channel.
sahilmgandhi	18:6a4db94011d3	19546	* \|[8:13] \|CTRGEN \|PWM Center Point Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	19547	* \| \| \|0 = PWM center point trigger ADC function Disabled.
sahilmgandhi	18:6a4db94011d3	19548	* \| \| \|1 = PWM center point trigger ADC function Enabled.
sahilmgandhi	18:6a4db94011d3	19549	* \| \| \|PWM can trigger ADC to start conversion when PWM counter up count to (PERIODn+1) if this bit is set to1.
sahilmgandhi	18:6a4db94011d3	19550	* \| \| \|Note1: This bit should keep at 0 when PWM counter operating in Edge-aligned type.
sahilmgandhi	18:6a4db94011d3	19551	* \| \| \|Note2: Each bit controls the corresponding PWM channel.
sahilmgandhi	18:6a4db94011d3	19552	* \|[16:21] \|FTRGEN \|PWM Falling Edge Point Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	19553	* \| \| \|0 = PWM falling edge point trigger ADC function Disabled.
sahilmgandhi	18:6a4db94011d3	19554	* \| \| \|1 = PWM falling edge point trigger ADC function Enabled.
sahilmgandhi	18:6a4db94011d3	19555	* \| \| \|PWM can trigger ADC to start conversion when PWM output pin falling edge is detected if this bit is set to1.
sahilmgandhi	18:6a4db94011d3	19556	* \| \| \|Note: Each bit controls the corresponding PWM channel.
sahilmgandhi	18:6a4db94011d3	19557	* \|[24:29] \|RTRGEN \|PWM Rising Edge Point Trigger Enable Control
sahilmgandhi	18:6a4db94011d3	19558	* \| \| \|0 = PWM rising edge point trigger ADC function Disabled.
sahilmgandhi	18:6a4db94011d3	19559	* \| \| \|1 = PWM rising edge point trigger ADC function Enabled.
sahilmgandhi	18:6a4db94011d3	19560	* \| \| \|PWM can trigger ADC to start conversion when PWM output pin rising edge is detected if this bit is set to1.
sahilmgandhi	18:6a4db94011d3	19561	* \| \| \|Note: Each bit controls the corresponding PWM channel.
sahilmgandhi	18:6a4db94011d3	19562	*/
sahilmgandhi	18:6a4db94011d3	19563	__IO uint32_t TRGADCTL;
sahilmgandhi	18:6a4db94011d3	19564
sahilmgandhi	18:6a4db94011d3	19565	/**
sahilmgandhi	18:6a4db94011d3	19566	* TRGADCSTS
sahilmgandhi	18:6a4db94011d3	19567	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19568	* Offset: 0x68 PWM Trigger ADC Status Register
sahilmgandhi	18:6a4db94011d3	19569	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19570	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19571	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19572	* \|[0:5] \|PTRGF \|PWM Period Point Trigger Flag
sahilmgandhi	18:6a4db94011d3	19573	* \| \| \|This bit is set to 1 by hardware when PWM counter down count to zero if corresponding PTRGEN bit is 1.
sahilmgandhi	18:6a4db94011d3	19574	* \| \| \|After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.
sahilmgandhi	18:6a4db94011d3	19575	* \| \| \|Note1: Write 1 to clear this bit.
sahilmgandhi	18:6a4db94011d3	19576	* \| \| \|Note2: Each bit controls the corresponding PWM channel.
sahilmgandhi	18:6a4db94011d3	19577	* \|[8:13] \|CTRGF \|PWM Center Point Trigger Flag
sahilmgandhi	18:6a4db94011d3	19578	* \| \| \|This bit is set to 1 by hardware when PWM counter up counts to (PERIODn+1) if the corresponding CTRGEN bit is 1.
sahilmgandhi	18:6a4db94011d3	19579	* \| \| \|After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.
sahilmgandhi	18:6a4db94011d3	19580	* \| \| \|Note1: Write 1 to clear this bit.
sahilmgandhi	18:6a4db94011d3	19581	* \| \| \|Note2: Each bit controls the corresponding PWM channel.
sahilmgandhi	18:6a4db94011d3	19582	* \|[16:21] \|FTRGF \|PWM Falling Edge Point Trigger Indicator
sahilmgandhi	18:6a4db94011d3	19583	* \| \| \|This bit is set to 1 by hardware when PWM output pin falling edge is detected if corresponding FETRGEN bit is 1.
sahilmgandhi	18:6a4db94011d3	19584	* \| \| \|After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.
sahilmgandhi	18:6a4db94011d3	19585	* \| \| \|Note1: Write 1 to clear this bit.
sahilmgandhi	18:6a4db94011d3	19586	* \| \| \|Note2: Each bit controls the corresponding PWM channel.
sahilmgandhi	18:6a4db94011d3	19587	* \|[24:29] \|RTRGF \|PWM Rising Edge Point Trigger Indicator
sahilmgandhi	18:6a4db94011d3	19588	* \| \| \|This bit is set to 1 by hardware when PWM output pin rising edge is detected if corresponding RETRGEN bit is 1.
sahilmgandhi	18:6a4db94011d3	19589	* \| \| \|After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.
sahilmgandhi	18:6a4db94011d3	19590	* \| \| \|Note1: Write 1 to clear this bit.
sahilmgandhi	18:6a4db94011d3	19591	* \| \| \|Note2: Each bit controls the corresponding PWM channel.
sahilmgandhi	18:6a4db94011d3	19592	*/
sahilmgandhi	18:6a4db94011d3	19593	__IO uint32_t TRGADCSTS;
sahilmgandhi	18:6a4db94011d3	19594
sahilmgandhi	18:6a4db94011d3	19595	/**
sahilmgandhi	18:6a4db94011d3	19596	* BRKCTL
sahilmgandhi	18:6a4db94011d3	19597	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19598	* Offset: 0x6C PWM Brake Control Register
sahilmgandhi	18:6a4db94011d3	19599	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19600	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19601	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19602	* \|[0] \|BRKP0EN \|Brake0 Function Enable Control
sahilmgandhi	18:6a4db94011d3	19603	* \| \| \|0 = Brake0 detect function Disabled.
sahilmgandhi	18:6a4db94011d3	19604	* \| \| \|1 = Brake0 detect function Enabled.
sahilmgandhi	18:6a4db94011d3	19605	* \|[1] \|BRK0NFDIS \|PWM Brake 0 Noise Filter Disable Control
sahilmgandhi	18:6a4db94011d3	19606	* \| \| \|0 = Noise filter of PWM Brake 0 Enabled.
sahilmgandhi	18:6a4db94011d3	19607	* \| \| \|1 = Noise filter of PWM Brake 0 Disabled.
sahilmgandhi	18:6a4db94011d3	19608	* \|[2] \|BRK0INV \|Inverse BKP0 State
sahilmgandhi	18:6a4db94011d3	19609	* \| \| \|0 = The state of pin BKPx0 is passed to the negative edge detector.
sahilmgandhi	18:6a4db94011d3	19610	* \| \| \|1 = The inversed state of pin BKPx0 is passed to the negative edge detector.
sahilmgandhi	18:6a4db94011d3	19611	* \|[6:7] \|BRK0NFSEL \|Brake 0 (BKPx0 Pin) Edge Detector Filter Clock Selection
sahilmgandhi	18:6a4db94011d3	19612	* \| \| \|00 = Filter clock = HCLK.
sahilmgandhi	18:6a4db94011d3	19613	* \| \| \|01 = Filter clock = HCLK/2.
sahilmgandhi	18:6a4db94011d3	19614	* \| \| \|10 = Filter clock = HCLK/4.
sahilmgandhi	18:6a4db94011d3	19615	* \| \| \|11 = Filter clock = HCLK/16.
sahilmgandhi	18:6a4db94011d3	19616	* \|[8] \|BRKP1EN \|Brake1 Function Enable Control
sahilmgandhi	18:6a4db94011d3	19617	* \| \| \|0 = Brake1 function Disabled.
sahilmgandhi	18:6a4db94011d3	19618	* \| \| \|1 = Brake1 function Enabled.
sahilmgandhi	18:6a4db94011d3	19619	* \|[9] \|BRK1NFDIS \|PWM Brake 1 Noise Filter Disable Control
sahilmgandhi	18:6a4db94011d3	19620	* \| \| \|0 = Noise filter of PWM Brake 1 Enabled.
sahilmgandhi	18:6a4db94011d3	19621	* \| \| \|1 = Noise filter of PWM Brake 1 Disabled.
sahilmgandhi	18:6a4db94011d3	19622	* \|[10] \|BRK1INV \|Inverse BKP1 State
sahilmgandhi	18:6a4db94011d3	19623	* \| \| \|0 = The state of pin BKPx1 is passed to the negative edge detector.
sahilmgandhi	18:6a4db94011d3	19624	* \| \| \|1 = The inversed state of pin BKPx1 is passed to the negative edge detector.
sahilmgandhi	18:6a4db94011d3	19625	* \|[12:13] \|BK1SEL \|Brake Function 1 Source Selection
sahilmgandhi	18:6a4db94011d3	19626	* \| \| \|00 = From external pin BKP1.
sahilmgandhi	18:6a4db94011d3	19627	* \| \| \|01 = From analog comparator 0 output (CPO0).
sahilmgandhi	18:6a4db94011d3	19628	* \| \| \|10 = From analog comparator 1 output (CPO1).
sahilmgandhi	18:6a4db94011d3	19629	* \| \| \|11 = Reserved.
sahilmgandhi	18:6a4db94011d3	19630	* \|[14:15] \|BRK1NFSEL \|Brake 1 (BKPx1 Pin) Edge Detector Filter Clock Selection
sahilmgandhi	18:6a4db94011d3	19631	* \| \| \|00 = Filter clock = HCLK.
sahilmgandhi	18:6a4db94011d3	19632	* \| \| \|01 = Filter clock = HCLK/2.
sahilmgandhi	18:6a4db94011d3	19633	* \| \| \|10 = Filter clock = HCLK/4.
sahilmgandhi	18:6a4db94011d3	19634	* \| \| \|11 = Filter clock = HCLK/16.
sahilmgandhi	18:6a4db94011d3	19635	* \|[16] \|CPO0BKEN \|CPO0 Digital Output As Brake0 Source Enable Control
sahilmgandhi	18:6a4db94011d3	19636	* \| \| \|0 = CPO0 as one brake source in Brake 0 Disabled.
sahilmgandhi	18:6a4db94011d3	19637	* \| \| \|1 = CPO0 as one brake source in Brake 0 Enabled.
sahilmgandhi	18:6a4db94011d3	19638	* \|[17] \|CPO1BKEN \|CPO1 Digital Output As Brake 0 Source Enable Control
sahilmgandhi	18:6a4db94011d3	19639	* \| \| \|0 = CPO1 as one brake source in Brake 0 Disabled.
sahilmgandhi	18:6a4db94011d3	19640	* \| \| \|1 = CPO1 as one brake source in Brake 0 Enabled.
sahilmgandhi	18:6a4db94011d3	19641	* \|[18] \|CPO2BKEN \|CPO2 Digital Output As Brake 0 Source Enable Control
sahilmgandhi	18:6a4db94011d3	19642	* \| \| \|0 = CPO2 as one brake source in Brake 0 Disabled.
sahilmgandhi	18:6a4db94011d3	19643	* \| \| \|1 = CPO2 as one brake source in Brake 0 Enabled.
sahilmgandhi	18:6a4db94011d3	19644	* \|[19] \|LVDBKEN \|Low-Level Detection Trigger PWM Brake Function 1 Enable Control
sahilmgandhi	18:6a4db94011d3	19645	* \| \| \|0 = Brake Function 1 triggered by Low-level detection Disabled.
sahilmgandhi	18:6a4db94011d3	19646	* \| \| \|1 = Brake Function 1 triggered by Low-level detection Enabled.
sahilmgandhi	18:6a4db94011d3	19647	* \|[24:29] \|BKOD \|PWM Brake Output Data Register
sahilmgandhi	18:6a4db94011d3	19648	* \| \| \|0 = PWM output low when fault brake conditions asserted.
sahilmgandhi	18:6a4db94011d3	19649	* \| \| \|1 = PWM output high when fault brake conditions asserted.
sahilmgandhi	18:6a4db94011d3	19650	* \| \| \|Note: Each bit controls the corresponding PWM channel.
sahilmgandhi	18:6a4db94011d3	19651	*/
sahilmgandhi	18:6a4db94011d3	19652	__IO uint32_t BRKCTL;
sahilmgandhi	18:6a4db94011d3	19653
sahilmgandhi	18:6a4db94011d3	19654	/**
sahilmgandhi	18:6a4db94011d3	19655	* INTCTL
sahilmgandhi	18:6a4db94011d3	19656	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19657	* Offset: 0x70 PWM Interrupt Control Register
sahilmgandhi	18:6a4db94011d3	19658	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19659	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19660	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19661	* \|[0:5] \|PINTTYPE \|PWM Period Interrupt Type Selection
sahilmgandhi	18:6a4db94011d3	19662	* \| \| \|0 = PIF[n] will be set if PWM counter underflow.
sahilmgandhi	18:6a4db94011d3	19663	* \| \| \|1 = PIF[n] will be set if PWM counter matches PWM_PERIODn register.
sahilmgandhi	18:6a4db94011d3	19664	* \| \| \|Note1: This bit should keep at 0 when PWM counter operating in Edge-aligned type.
sahilmgandhi	18:6a4db94011d3	19665	* \| \| \|Note2: Each bit controls the corresponding PWM channel.
sahilmgandhi	18:6a4db94011d3	19666	* \|[8:13] \|DINTTYPE \|PWM Duty Interrupt Type Selection
sahilmgandhi	18:6a4db94011d3	19667	* \| \| \|0 = DIF[n] will be set if PWM counter matches PWM_CMPDATn register during down counting.
sahilmgandhi	18:6a4db94011d3	19668	* \| \| \|1 = DIF[n] will be set if PWM counter matches PWM_CMPDATn register during up counting.
sahilmgandhi	18:6a4db94011d3	19669	* \| \| \|Note1: This bit should keep at 0 when PWM counter operating in Edge-aligned type.
sahilmgandhi	18:6a4db94011d3	19670	* \| \| \|Note2: Each bit controls the corresponding PWM channel.
sahilmgandhi	18:6a4db94011d3	19671	*/
sahilmgandhi	18:6a4db94011d3	19672	__IO uint32_t INTCTL;
sahilmgandhi	18:6a4db94011d3	19673
sahilmgandhi	18:6a4db94011d3	19674	/**
sahilmgandhi	18:6a4db94011d3	19675	* INTEN
sahilmgandhi	18:6a4db94011d3	19676	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19677	* Offset: 0x74 PWM Interrupt Enable Control Register
sahilmgandhi	18:6a4db94011d3	19678	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19679	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19680	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19681	* \|[0:5] \|PIEN \|PWM Period Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	19682	* \| \| \|0 = Period interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	19683	* \| \| \|1 = Period interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	19684	* \| \| \|Note: Each bit controls the corresponding PWM channel.
sahilmgandhi	18:6a4db94011d3	19685	* \|[6] \|BRKIEN \|Brake0 And Brak1 Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	19686	* \| \| \|0 = Disabling flags BFK0 and BFK1 to trigger PWM interrupt.
sahilmgandhi	18:6a4db94011d3	19687	* \| \| \|1 = Enabling flags BRKIF0 and BRKIF1 can trigger PWM interrupt.
sahilmgandhi	18:6a4db94011d3	19688	* \|[8:13] \|DIEN \|PWM Duty Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	19689	* \| \| \|0 = Duty interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	19690	* \| \| \|1 = Duty interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	19691	* \| \| \|Note: Each bit controls the corresponding PWM channel.
sahilmgandhi	18:6a4db94011d3	19692	* \|[16:21] \|RLIEN \|Rising Latch Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	19693	* \| \| \|0 = Rising latch interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	19694	* \| \| \|1 = Rising latch interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	19695	* \| \| \|Note: Each bit controls the corresponding PWM channel.
sahilmgandhi	18:6a4db94011d3	19696	* \|[24:29] \|FLIEN \|Falling Latch Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	19697	* \| \| \|0 = Falling latch interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	19698	* \| \| \|1 = Falling latch interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	19699	* \| \| \|Note: Each bit controls the corresponding PWM channel.
sahilmgandhi	18:6a4db94011d3	19700	*/
sahilmgandhi	18:6a4db94011d3	19701	__IO uint32_t INTEN;
sahilmgandhi	18:6a4db94011d3	19702
sahilmgandhi	18:6a4db94011d3	19703	/**
sahilmgandhi	18:6a4db94011d3	19704	* INTSTS
sahilmgandhi	18:6a4db94011d3	19705	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19706	* Offset: 0x78 PWM Interrupt Flag Register
sahilmgandhi	18:6a4db94011d3	19707	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19708	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19709	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19710	* \|[0:5] \|PIF \|PWM Period Interrupt Flag
sahilmgandhi	18:6a4db94011d3	19711	* \| \| \|This bit is set by hardware when PWM counter reaches the requirement condition of interrupt (depending on PINTTYPE (PWM_INTCTL[n]) ).
sahilmgandhi	18:6a4db94011d3	19712	* \| \| \|Software can write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	19713	* \|[6] \|BRKIF0 \|PWM Brake0 Flag
sahilmgandhi	18:6a4db94011d3	19714	* \| \| \|0 = PWM Brake 0 is able to poll falling signal at BKP0 and has not recognized any one.
sahilmgandhi	18:6a4db94011d3	19715	* \| \| \|1 = When PWM Brake 0 detects a falling signal at BKP0, this flag will be set to high.
sahilmgandhi	18:6a4db94011d3	19716	* \| \| \|Note: This bit must be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	19717	* \|[7] \|BRKIF1 \|PWM Brake1 Flag
sahilmgandhi	18:6a4db94011d3	19718	* \| \| \|0 = PWM Brake 1 is able to poll falling signal at BKP1 and has not recognized any one.
sahilmgandhi	18:6a4db94011d3	19719	* \| \| \|1 = When PWM Brake 1 detects a falling signal at pin BKP1, this flag will be set to high.
sahilmgandhi	18:6a4db94011d3	19720	* \| \| \|Note: This bit must be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	19721	* \|[8:13] \|DIF \|PWM Duty Interrupt Flag
sahilmgandhi	18:6a4db94011d3	19722	* \| \| \|Flag is set by hardware when channel 0 PWM counter down count and reaches CMP0.
sahilmgandhi	18:6a4db94011d3	19723	* \| \| \|Software can clear this bit by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	19724	* \| \| \|Note: If CMP is equal to PERIOD, this flag is not working in edge-aligned type selection.
sahilmgandhi	18:6a4db94011d3	19725	* \|[14] \|BRKLK0 \|PWM Brake0 Locked
sahilmgandhi	18:6a4db94011d3	19726	* \| \| \|0 = Brake 0 state is released.
sahilmgandhi	18:6a4db94011d3	19727	* \| \| \|1 = When PWM Brake detects a falling signal at BKP0, this flag will be set to high to indicate the Brake0 state is locked.
sahilmgandhi	18:6a4db94011d3	19728	* \| \| \|Note: This bit must be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	19729	* \|[16:21] \|CRLIF \|Capture Rising Latch Interrupt Flag
sahilmgandhi	18:6a4db94011d3	19730	* \| \| \|0 = No capture rising latch condition happened.
sahilmgandhi	18:6a4db94011d3	19731	* \| \| \|1 = Capture rising latch condition happened, this flag will be set to high.
sahilmgandhi	18:6a4db94011d3	19732	* \| \| \|Note: This bit must be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	19733	* \|[22] \|BRKSTS0 \|Brake 0 Status (Read Only)
sahilmgandhi	18:6a4db94011d3	19734	* \| \| \|0 = PWM had been out of Brake 0 state.
sahilmgandhi	18:6a4db94011d3	19735	* \| \| \|1 = PWM is in Brake 0 state.
sahilmgandhi	18:6a4db94011d3	19736	* \|[23] \|BRKSTS1 \|Brake 1 Status (Read Only)
sahilmgandhi	18:6a4db94011d3	19737	* \| \| \|0 = PWM had been out of Brake 1 state.
sahilmgandhi	18:6a4db94011d3	19738	* \| \| \|1 = PWM is in Brake 1 state.
sahilmgandhi	18:6a4db94011d3	19739	* \|[24:29] \|CFLIF \|Capture Falling Latch Interrupt Flag
sahilmgandhi	18:6a4db94011d3	19740	* \| \| \|0 = No capture falling latch condition happened.
sahilmgandhi	18:6a4db94011d3	19741	* \| \| \|1 = Capture falling latch condition happened, this flag will be set to high.
sahilmgandhi	18:6a4db94011d3	19742	* \| \| \|Note: This bit must be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	19743	*/
sahilmgandhi	18:6a4db94011d3	19744	__IO uint32_t INTSTS;
sahilmgandhi	18:6a4db94011d3	19745
sahilmgandhi	18:6a4db94011d3	19746	/**
sahilmgandhi	18:6a4db94011d3	19747	* POEN
sahilmgandhi	18:6a4db94011d3	19748	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19749	* Offset: 0x7C PWM Output Enable Control Register
sahilmgandhi	18:6a4db94011d3	19750	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19751	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19752	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19753	* \|[0:5] \|POEN \|PWM Pin Output Enable Control
sahilmgandhi	18:6a4db94011d3	19754	* \| \| \|0 = PWM pin at tri-state.
sahilmgandhi	18:6a4db94011d3	19755	* \| \| \|1 = PWM pin in output mode.
sahilmgandhi	18:6a4db94011d3	19756	* \| \| \|Note: Each bit controls the corresponding PWM channel.
sahilmgandhi	18:6a4db94011d3	19757	*/
sahilmgandhi	18:6a4db94011d3	19758	__IO uint32_t POEN;
sahilmgandhi	18:6a4db94011d3	19759
sahilmgandhi	18:6a4db94011d3	19760	/**
sahilmgandhi	18:6a4db94011d3	19761	* CAPCTL
sahilmgandhi	18:6a4db94011d3	19762	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19763	* Offset: 0x80 PWM Capture Control Register
sahilmgandhi	18:6a4db94011d3	19764	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19765	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19766	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19767	* \|[0:5] \|CAPEN \|Capture Function Enable Control
sahilmgandhi	18:6a4db94011d3	19768	* \| \| \|0 = Capture function Disabled. RCAPDAT and FCAPDAT will not be updated.
sahilmgandhi	18:6a4db94011d3	19769	* \| \| \|1 = Capture function Enabled.
sahilmgandhi	18:6a4db94011d3	19770	* \| \| \|Capture latched the PWM counter value and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
sahilmgandhi	18:6a4db94011d3	19771	* \| \| \|Note: Each bit controls the corresponding PWM channel.
sahilmgandhi	18:6a4db94011d3	19772	* \|[8:13] \|CAPINV \|Capture Inverter Enable Control
sahilmgandhi	18:6a4db94011d3	19773	* \| \| \|0 = Capture source inverter Disabled.
sahilmgandhi	18:6a4db94011d3	19774	* \| \| \|1 = Capture source inverter Enabled. Reverse the input signal from GPIO
sahilmgandhi	18:6a4db94011d3	19775	* \| \| \|Note: Each bit controls the corresponding PWM channel.
sahilmgandhi	18:6a4db94011d3	19776	* \|[16:21] \|RCRLDEN \|Rising Latch Reload Enable Control
sahilmgandhi	18:6a4db94011d3	19777	* \| \| \|0 = Rising latch reload counter Enabled.
sahilmgandhi	18:6a4db94011d3	19778	* \| \| \|1 = Rising latch reload counter Enabled.
sahilmgandhi	18:6a4db94011d3	19779	* \|[24:29] \|FCRLDEN \|Falling Latch Reload Enable Control
sahilmgandhi	18:6a4db94011d3	19780	* \| \| \|0 = Falling latch reload counter Disabled.
sahilmgandhi	18:6a4db94011d3	19781	* \| \| \|1 = Falling latch
sahilmgandhi	18:6a4db94011d3	19782	* \| \| \|reload counter Enabled.
sahilmgandhi	18:6a4db94011d3	19783	*/
sahilmgandhi	18:6a4db94011d3	19784	__IO uint32_t CAPCTL;
sahilmgandhi	18:6a4db94011d3	19785
sahilmgandhi	18:6a4db94011d3	19786	/**
sahilmgandhi	18:6a4db94011d3	19787	* CAPINEN
sahilmgandhi	18:6a4db94011d3	19788	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19789	* Offset: 0x84 PWM Capture Input Enable Control Register
sahilmgandhi	18:6a4db94011d3	19790	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19791	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19792	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19793	* \|[0:5] \|CAPINEN \|Capture Input Enable Control
sahilmgandhi	18:6a4db94011d3	19794	* \| \| \|0 = PWM Channel capture input path Disabled.
sahilmgandhi	18:6a4db94011d3	19795	* \| \| \|The input of PWM channel capture function is always regarded as 0.
sahilmgandhi	18:6a4db94011d3	19796	* \| \| \|1 = PWM Channel capture input path Enabled.
sahilmgandhi	18:6a4db94011d3	19797	* \| \| \|The input of PWM channel capture function comes from correlative multifunction pin.
sahilmgandhi	18:6a4db94011d3	19798	* \| \| \|Note: Each bit controls the corresponding PWM channel.
sahilmgandhi	18:6a4db94011d3	19799	*/
sahilmgandhi	18:6a4db94011d3	19800	__IO uint32_t CAPINEN;
sahilmgandhi	18:6a4db94011d3	19801
sahilmgandhi	18:6a4db94011d3	19802	/**
sahilmgandhi	18:6a4db94011d3	19803	* CAPSTS
sahilmgandhi	18:6a4db94011d3	19804	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19805	* Offset: 0x88 PWM Capture Status Register
sahilmgandhi	18:6a4db94011d3	19806	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19807	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19808	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19809	* \|[0:5] \|CRIFOV \|Rising Latch Interrupt Flag Overrun Status
sahilmgandhi	18:6a4db94011d3	19810	* \| \| \|This flag indicates if rising latch happened when the corresponding CRLIF is 1
sahilmgandhi	18:6a4db94011d3	19811	* \| \| \|Note: This bit will be cleared automatically when user clear corresponding CRLIF.
sahilmgandhi	18:6a4db94011d3	19812	* \|[8:13] \|FLIFOV \|Falling Latch Interrupt Flag Overrun Status
sahilmgandhi	18:6a4db94011d3	19813	* \| \| \|This flag indicates if falling latch happened when the corresponding CFLIF is 1
sahilmgandhi	18:6a4db94011d3	19814	* \| \| \|Note: This bit will be cleared automatically when user clear corresponding CFLIF.
sahilmgandhi	18:6a4db94011d3	19815	*/
sahilmgandhi	18:6a4db94011d3	19816	__I uint32_t CAPSTS;
sahilmgandhi	18:6a4db94011d3	19817	uint32_t RESERVE0[1];
sahilmgandhi	18:6a4db94011d3	19818
sahilmgandhi	18:6a4db94011d3	19819
sahilmgandhi	18:6a4db94011d3	19820	/**
sahilmgandhi	18:6a4db94011d3	19821	* RCAPDAT0
sahilmgandhi	18:6a4db94011d3	19822	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19823	* Offset: 0x90 PWM Capture Rising Latch Register 0
sahilmgandhi	18:6a4db94011d3	19824	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19825	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19826	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19827	* \|[0:15] \|RCAPDAT \|Capture Rising Latch Register
sahilmgandhi	18:6a4db94011d3	19828	* \| \| \|Latch the PWM counter when Channel 0/1/2/3/4/5 has rising transition.
sahilmgandhi	18:6a4db94011d3	19829	*/
sahilmgandhi	18:6a4db94011d3	19830	__I uint32_t RCAPDAT0;
sahilmgandhi	18:6a4db94011d3	19831
sahilmgandhi	18:6a4db94011d3	19832	/**
sahilmgandhi	18:6a4db94011d3	19833	* FCAPDAT0
sahilmgandhi	18:6a4db94011d3	19834	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19835	* Offset: 0x94 PWM Capture Falling Latch Register 0
sahilmgandhi	18:6a4db94011d3	19836	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19837	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19838	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19839	* \|[0:15] \|FCAPDAT \|Capture Falling Latch Register
sahilmgandhi	18:6a4db94011d3	19840	* \| \| \|Latch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition.
sahilmgandhi	18:6a4db94011d3	19841	*/
sahilmgandhi	18:6a4db94011d3	19842	__I uint32_t FCAPDAT0;
sahilmgandhi	18:6a4db94011d3	19843
sahilmgandhi	18:6a4db94011d3	19844	/**
sahilmgandhi	18:6a4db94011d3	19845	* RCAPDAT1
sahilmgandhi	18:6a4db94011d3	19846	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19847	* Offset: 0x98 PWM Capture Rising Latch Register 1
sahilmgandhi	18:6a4db94011d3	19848	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19849	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19850	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19851	* \|[0:15] \|RCAPDAT \|Capture Rising Latch Register
sahilmgandhi	18:6a4db94011d3	19852	* \| \| \|Latch the PWM counter when Channel 0/1/2/3/4/5 has rising transition.
sahilmgandhi	18:6a4db94011d3	19853	*/
sahilmgandhi	18:6a4db94011d3	19854	__I uint32_t RCAPDAT1;
sahilmgandhi	18:6a4db94011d3	19855
sahilmgandhi	18:6a4db94011d3	19856	/**
sahilmgandhi	18:6a4db94011d3	19857	* FCAPDAT1
sahilmgandhi	18:6a4db94011d3	19858	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19859	* Offset: 0x9C PWM Capture Falling Latch Register 1
sahilmgandhi	18:6a4db94011d3	19860	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19861	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19862	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19863	* \|[0:15] \|FCAPDAT \|Capture Falling Latch Register
sahilmgandhi	18:6a4db94011d3	19864	* \| \| \|Latch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition.
sahilmgandhi	18:6a4db94011d3	19865	*/
sahilmgandhi	18:6a4db94011d3	19866	__I uint32_t FCAPDAT1;
sahilmgandhi	18:6a4db94011d3	19867
sahilmgandhi	18:6a4db94011d3	19868	/**
sahilmgandhi	18:6a4db94011d3	19869	* RCAPDAT2
sahilmgandhi	18:6a4db94011d3	19870	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19871	* Offset: 0xA0 PWM Capture Rising Latch Register 2
sahilmgandhi	18:6a4db94011d3	19872	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19873	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19874	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19875	* \|[0:15] \|RCAPDAT \|Capture Rising Latch Register
sahilmgandhi	18:6a4db94011d3	19876	* \| \| \|Latch the PWM counter when Channel 0/1/2/3/4/5 has rising transition.
sahilmgandhi	18:6a4db94011d3	19877	*/
sahilmgandhi	18:6a4db94011d3	19878	__I uint32_t RCAPDAT2;
sahilmgandhi	18:6a4db94011d3	19879
sahilmgandhi	18:6a4db94011d3	19880	/**
sahilmgandhi	18:6a4db94011d3	19881	* FCAPDAT2
sahilmgandhi	18:6a4db94011d3	19882	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19883	* Offset: 0xA4 PWM Capture Falling Latch Register 2
sahilmgandhi	18:6a4db94011d3	19884	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19885	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19886	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19887	* \|[0:15] \|FCAPDAT \|Capture Falling Latch Register
sahilmgandhi	18:6a4db94011d3	19888	* \| \| \|Latch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition.
sahilmgandhi	18:6a4db94011d3	19889	*/
sahilmgandhi	18:6a4db94011d3	19890	__I uint32_t FCAPDAT2;
sahilmgandhi	18:6a4db94011d3	19891
sahilmgandhi	18:6a4db94011d3	19892	/**
sahilmgandhi	18:6a4db94011d3	19893	* RCAPDAT3
sahilmgandhi	18:6a4db94011d3	19894	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19895	* Offset: 0xA8 PWM Capture Rising Latch Register 3
sahilmgandhi	18:6a4db94011d3	19896	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19897	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19898	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19899	* \|[0:15] \|RCAPDAT \|Capture Rising Latch Register
sahilmgandhi	18:6a4db94011d3	19900	* \| \| \|Latch the PWM counter when Channel 0/1/2/3/4/5 has rising transition.
sahilmgandhi	18:6a4db94011d3	19901	*/
sahilmgandhi	18:6a4db94011d3	19902	__I uint32_t RCAPDAT3;
sahilmgandhi	18:6a4db94011d3	19903
sahilmgandhi	18:6a4db94011d3	19904	/**
sahilmgandhi	18:6a4db94011d3	19905	* FCAPDAT3
sahilmgandhi	18:6a4db94011d3	19906	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19907	* Offset: 0xAC PWM Capture Falling Latch Register 3
sahilmgandhi	18:6a4db94011d3	19908	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19909	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19910	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19911	* \|[0:15] \|FCAPDAT \|Capture Falling Latch Register
sahilmgandhi	18:6a4db94011d3	19912	* \| \| \|Latch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition.
sahilmgandhi	18:6a4db94011d3	19913	*/
sahilmgandhi	18:6a4db94011d3	19914	__I uint32_t FCAPDAT3;
sahilmgandhi	18:6a4db94011d3	19915
sahilmgandhi	18:6a4db94011d3	19916	/**
sahilmgandhi	18:6a4db94011d3	19917	* RCAPDAT4
sahilmgandhi	18:6a4db94011d3	19918	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19919	* Offset: 0xB0 PWM Capture Rising Latch Register 4
sahilmgandhi	18:6a4db94011d3	19920	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19921	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19922	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19923	* \|[0:15] \|RCAPDAT \|Capture Rising Latch Register
sahilmgandhi	18:6a4db94011d3	19924	* \| \| \|Latch the PWM counter when Channel 0/1/2/3/4/5 has rising transition.
sahilmgandhi	18:6a4db94011d3	19925	*/
sahilmgandhi	18:6a4db94011d3	19926	__I uint32_t RCAPDAT4;
sahilmgandhi	18:6a4db94011d3	19927
sahilmgandhi	18:6a4db94011d3	19928	/**
sahilmgandhi	18:6a4db94011d3	19929	* FCAPDAT4
sahilmgandhi	18:6a4db94011d3	19930	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19931	* Offset: 0xB4 PWM Capture Falling Latch Register 4
sahilmgandhi	18:6a4db94011d3	19932	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19933	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19934	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19935	* \|[0:15] \|FCAPDAT \|Capture Falling Latch Register
sahilmgandhi	18:6a4db94011d3	19936	* \| \| \|Latch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition.
sahilmgandhi	18:6a4db94011d3	19937	*/
sahilmgandhi	18:6a4db94011d3	19938	__I uint32_t FCAPDAT4;
sahilmgandhi	18:6a4db94011d3	19939
sahilmgandhi	18:6a4db94011d3	19940	/**
sahilmgandhi	18:6a4db94011d3	19941	* RCAPDAT5
sahilmgandhi	18:6a4db94011d3	19942	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19943	* Offset: 0xB8 PWM Capture Rising Latch Register 5
sahilmgandhi	18:6a4db94011d3	19944	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19945	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19946	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19947	* \|[0:15] \|RCAPDAT \|Capture Rising Latch Register
sahilmgandhi	18:6a4db94011d3	19948	* \| \| \|Latch the PWM counter when Channel 0/1/2/3/4/5 has rising transition.
sahilmgandhi	18:6a4db94011d3	19949	*/
sahilmgandhi	18:6a4db94011d3	19950	__I uint32_t RCAPDAT5;
sahilmgandhi	18:6a4db94011d3	19951
sahilmgandhi	18:6a4db94011d3	19952	/**
sahilmgandhi	18:6a4db94011d3	19953	* FCAPDAT5
sahilmgandhi	18:6a4db94011d3	19954	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19955	* Offset: 0xBC PWM Capture Falling Latch Register 5
sahilmgandhi	18:6a4db94011d3	19956	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19957	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19958	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19959	* \|[0:15] \|FCAPDAT \|Capture Falling Latch Register
sahilmgandhi	18:6a4db94011d3	19960	* \| \| \|Latch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition.
sahilmgandhi	18:6a4db94011d3	19961	*/
sahilmgandhi	18:6a4db94011d3	19962	__I uint32_t FCAPDAT5;
sahilmgandhi	18:6a4db94011d3	19963	uint32_t RESERVE1[8];
sahilmgandhi	18:6a4db94011d3	19964
sahilmgandhi	18:6a4db94011d3	19965
sahilmgandhi	18:6a4db94011d3	19966	/**
sahilmgandhi	18:6a4db94011d3	19967	* SBS0
sahilmgandhi	18:6a4db94011d3	19968	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	19969	* Offset: 0xE0 PWM0 Synchronous Busy Status Register
sahilmgandhi	18:6a4db94011d3	19970	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	19971	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	19972	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	19973	* \|[0] \|SYNCBUSY \|PWM Synchronous Busy
sahilmgandhi	18:6a4db94011d3	19974	* \| \| \|When software writes PWM_PERIOD0/PWM_CMPDAT0/PWM_CLKPSC or switch PWM0 counter operation mode CNTMOD (CONR[16]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain.
sahilmgandhi	18:6a4db94011d3	19975	* \| \| \|Software needs to check this busy status before writes PWM_PERIOD0/PWM_CMPDAT0/ PWM_CLKPSC or switch PWM0 counter operation mode to make sure previous setting has been update completely.
sahilmgandhi	18:6a4db94011d3	19976	* \| \| \|This bit will be set when software writes PWM_PERIOD0/PWM_CMPDAT0/PWM_CLKPSC or switch PWM0 operation mode CNTMOD (CONR[16]) and will be cleared by hardware automatically when PWM update these value completely.
sahilmgandhi	18:6a4db94011d3	19977	*/
sahilmgandhi	18:6a4db94011d3	19978	__I uint32_t SBS[6];
sahilmgandhi	18:6a4db94011d3	19979
sahilmgandhi	18:6a4db94011d3	19980	} PWM_T;
sahilmgandhi	18:6a4db94011d3	19981
sahilmgandhi	18:6a4db94011d3	19982	/**
sahilmgandhi	18:6a4db94011d3	19983	@addtogroup PWM_CONST PWM Bit Field Definition
sahilmgandhi	18:6a4db94011d3	19984	Constant Definitions for PWM Controller
sahilmgandhi	18:6a4db94011d3	19985	@{ */
sahilmgandhi	18:6a4db94011d3	19986
sahilmgandhi	18:6a4db94011d3	19987	#define PWM_CLKPSC_CLKPSC01_Pos (0) /!< PWM CLKPSC: CLKPSC01 Position /
sahilmgandhi	18:6a4db94011d3	19988	#define PWM_CLKPSC_CLKPSC01_Msk (0xfful << PWM_CLKPSC_CLKPSC01_Pos) /!< PWM CLKPSC: CLKPSC01 Mask /
sahilmgandhi	18:6a4db94011d3	19989
sahilmgandhi	18:6a4db94011d3	19990	#define PWM_CLKPSC_CLKPSC23_Pos (8) /!< PWM CLKPSC: CLKPSC23 Position /
sahilmgandhi	18:6a4db94011d3	19991	#define PWM_CLKPSC_CLKPSC23_Msk (0xfful << PWM_CLKPSC_CLKPSC23_Pos) /!< PWM CLKPSC: CLKPSC23 Mask /
sahilmgandhi	18:6a4db94011d3	19992
sahilmgandhi	18:6a4db94011d3	19993	#define PWM_CLKPSC_CLKPSC45_Pos (16) /!< PWM CLKPSC: CLKPSC45 Position /
sahilmgandhi	18:6a4db94011d3	19994	#define PWM_CLKPSC_CLKPSC45_Msk (0xfful << PWM_CLKPSC_CLKPSC45_Pos) /!< PWM CLKPSC: CLKPSC45 Mask /
sahilmgandhi	18:6a4db94011d3	19995
sahilmgandhi	18:6a4db94011d3	19996	#define PWM_CLKDIV_CLKDIV0_Pos (0) /!< PWM CLKDIV: CLKDIV0 Position /
sahilmgandhi	18:6a4db94011d3	19997	#define PWM_CLKDIV_CLKDIV0_Msk (0x7ul << PWM_CLKDIV_CLKDIV0_Pos) /!< PWM CLKDIV: CLKDIV0 Mask /
sahilmgandhi	18:6a4db94011d3	19998
sahilmgandhi	18:6a4db94011d3	19999	#define PWM_CLKDIV_CLKDIV1_Pos (4) /!< PWM CLKDIV: CLKDIV1 Position /
sahilmgandhi	18:6a4db94011d3	20000	#define PWM_CLKDIV_CLKDIV1_Msk (0x7ul << PWM_CLKDIV_CLKDIV1_Pos) /!< PWM CLKDIV: CLKDIV1 Mask /
sahilmgandhi	18:6a4db94011d3	20001
sahilmgandhi	18:6a4db94011d3	20002	#define PWM_CLKDIV_CLKDIV2_Pos (8) /!< PWM CLKDIV: CLKDIV2 Position /
sahilmgandhi	18:6a4db94011d3	20003	#define PWM_CLKDIV_CLKDIV2_Msk (0x7ul << PWM_CLKDIV_CLKDIV2_Pos) /!< PWM CLKDIV: CLKDIV2 Mask /
sahilmgandhi	18:6a4db94011d3	20004
sahilmgandhi	18:6a4db94011d3	20005	#define PWM_CLKDIV_CLKDIV3_Pos (12) /!< PWM CLKDIV: CLKDIV3 Position /
sahilmgandhi	18:6a4db94011d3	20006	#define PWM_CLKDIV_CLKDIV3_Msk (0x7ul << PWM_CLKDIV_CLKDIV3_Pos) /!< PWM CLKDIV: CLKDIV3 Mask /
sahilmgandhi	18:6a4db94011d3	20007
sahilmgandhi	18:6a4db94011d3	20008	#define PWM_CLKDIV_CLKDIV4_Pos (16) /!< PWM CLKDIV: CLKDIV4 Position /
sahilmgandhi	18:6a4db94011d3	20009	#define PWM_CLKDIV_CLKDIV4_Msk (0x7ul << PWM_CLKDIV_CLKDIV4_Pos) /!< PWM CLKDIV: CLKDIV4 Mask /
sahilmgandhi	18:6a4db94011d3	20010
sahilmgandhi	18:6a4db94011d3	20011	#define PWM_CLKDIV_CLKDIV5_Pos (20) /!< PWM CLKDIV: CLKDIV5 Position /
sahilmgandhi	18:6a4db94011d3	20012	#define PWM_CLKDIV_CLKDIV5_Msk (0x7ul << PWM_CLKDIV_CLKDIV5_Pos) /!< PWM CLKDIV: CLKDIV5 Mask /
sahilmgandhi	18:6a4db94011d3	20013
sahilmgandhi	18:6a4db94011d3	20014	#define PWM_CTL_CMPINV_Pos (0) /!< PWM CTL: CMPINV Position /
sahilmgandhi	18:6a4db94011d3	20015	#define PWM_CTL_CMPINV_Msk (0x3ful << PWM_CTL_CMPINV_Pos) /!< PWM CTL: CMPINV Mask /
sahilmgandhi	18:6a4db94011d3	20016
sahilmgandhi	18:6a4db94011d3	20017	#define PWM_CTL_OUTMODE_Pos (6) /!< PWM CTL: OUTMODE Position /
sahilmgandhi	18:6a4db94011d3	20018	#define PWM_CTL_OUTMODE_Msk (0x1ul << PWM_CTL_OUTMODE_Pos) /!< PWM CTL: OUTMODE Mask /
sahilmgandhi	18:6a4db94011d3	20019
sahilmgandhi	18:6a4db94011d3	20020	#define PWM_CTL_GROUPEN_Pos (7) /!< PWM CTL: GROUPEN Position /
sahilmgandhi	18:6a4db94011d3	20021	#define PWM_CTL_GROUPEN_Msk (0x1ul << PWM_CTL_GROUPEN_Pos) /!< PWM CTL: GROUPEN Mask /
sahilmgandhi	18:6a4db94011d3	20022
sahilmgandhi	18:6a4db94011d3	20023	#define PWM_CTL_PINV_Pos (8) /!< PWM CTL: PINV Position /
sahilmgandhi	18:6a4db94011d3	20024	#define PWM_CTL_PINV_Msk (0x3ful << PWM_CTL_PINV_Pos) /!< PWM CTL: PINV Mask /
sahilmgandhi	18:6a4db94011d3	20025
sahilmgandhi	18:6a4db94011d3	20026	#define PWM_CTL_SYNCEN_Pos (15) /!< PWM CTL: SYNCEN Position /
sahilmgandhi	18:6a4db94011d3	20027	#define PWM_CTL_SYNCEN_Msk (0x1ul << PWM_CTL_SYNCEN_Pos) /!< PWM CTL: SYNCEN Mask /
sahilmgandhi	18:6a4db94011d3	20028
sahilmgandhi	18:6a4db94011d3	20029	#define PWM_CTL_CNTMODE_Pos (16) /!< PWM CTL: CNTMODE Position /
sahilmgandhi	18:6a4db94011d3	20030	#define PWM_CTL_CNTMODE_Msk (0x3ful << PWM_CTL_CNTMODE_Pos) /!< PWM CTL: CNTMODE Mask /
sahilmgandhi	18:6a4db94011d3	20031
sahilmgandhi	18:6a4db94011d3	20032	#define PWM_CTL_CNTTYPE_Pos (24) /!< PWM CTL: CNTTYPE Position /
sahilmgandhi	18:6a4db94011d3	20033	#define PWM_CTL_CNTTYPE_Msk (0x3ful << PWM_CTL_CNTTYPE_Pos) /!< PWM CTL: CNTTYPE Mask /
sahilmgandhi	18:6a4db94011d3	20034
sahilmgandhi	18:6a4db94011d3	20035	#define PWM_CTL_DBGTRIOFF_Pos (31) /!< PWM CTL: DBGTRIOFF Position /
sahilmgandhi	18:6a4db94011d3	20036	#define PWM_CTL_DBGTRIOFF_Msk (0x1ul << PWM_CTL_DBGTRIOFF_Pos) /!< PWM CTL: DBGTRIOFF Mask /
sahilmgandhi	18:6a4db94011d3	20037
sahilmgandhi	18:6a4db94011d3	20038	#define PWM_CNTEN_CNTEN_Pos (0) /!< PWM CNTEN: CNTEN Position /
sahilmgandhi	18:6a4db94011d3	20039	#define PWM_CNTEN_CNTEN_Msk (0x3ful << PWM_CNTEN_CNTEN_Pos) /!< PWM CNTEN: CNTEN Mask /
sahilmgandhi	18:6a4db94011d3	20040
sahilmgandhi	18:6a4db94011d3	20041	#define PWM_PERIOD0_PERIOD_Pos (0) /!< PWM PERIOD0: PERIOD Position /
sahilmgandhi	18:6a4db94011d3	20042	#define PWM_PERIOD0_PERIOD_Msk (0xfffful << PWM_PERIOD0_PERIOD_Pos) /!< PWM PERIOD0: PERIOD Mask /
sahilmgandhi	18:6a4db94011d3	20043
sahilmgandhi	18:6a4db94011d3	20044	#define PWM_PERIOD1_PERIOD_Pos (0) /!< PWM PERIOD1: PERIOD Position /
sahilmgandhi	18:6a4db94011d3	20045	#define PWM_PERIOD1_PERIOD_Msk (0xfffful << PWM_PERIOD1_PERIOD_Pos) /!< PWM PERIOD1: PERIOD Mask /
sahilmgandhi	18:6a4db94011d3	20046
sahilmgandhi	18:6a4db94011d3	20047	#define PWM_PERIOD2_PERIOD_Pos (0) /!< PWM PERIOD2: PERIOD Position /
sahilmgandhi	18:6a4db94011d3	20048	#define PWM_PERIOD2_PERIOD_Msk (0xfffful << PWM_PERIOD2_PERIOD_Pos) /!< PWM PERIOD2: PERIOD Mask /
sahilmgandhi	18:6a4db94011d3	20049
sahilmgandhi	18:6a4db94011d3	20050	#define PWM_PERIOD3_PERIOD_Pos (0) /!< PWM PERIOD3: PERIOD Position /
sahilmgandhi	18:6a4db94011d3	20051	#define PWM_PERIOD3_PERIOD_Msk (0xfffful << PWM_PERIOD3_PERIOD_Pos) /!< PWM PERIOD3: PERIOD Mask /
sahilmgandhi	18:6a4db94011d3	20052
sahilmgandhi	18:6a4db94011d3	20053	#define PWM_PERIOD4_PERIOD_Pos (0) /!< PWM PERIOD4: PERIOD Position /
sahilmgandhi	18:6a4db94011d3	20054	#define PWM_PERIOD4_PERIOD_Msk (0xfffful << PWM_PERIOD4_PERIOD_Pos) /!< PWM PERIOD4: PERIOD Mask /
sahilmgandhi	18:6a4db94011d3	20055
sahilmgandhi	18:6a4db94011d3	20056	#define PWM_PERIOD5_PERIOD_Pos (0) /!< PWM PERIOD5: PERIOD Position /
sahilmgandhi	18:6a4db94011d3	20057	#define PWM_PERIOD5_PERIOD_Msk (0xfffful << PWM_PERIOD5_PERIOD_Pos) /!< PWM PERIOD5: PERIOD Mask /
sahilmgandhi	18:6a4db94011d3	20058
sahilmgandhi	18:6a4db94011d3	20059	#define PWM_CMPDAT0_CMP_Pos (0) /!< PWM CMPDAT0: CMP Position /
sahilmgandhi	18:6a4db94011d3	20060	#define PWM_CMPDAT0_CMP_Msk (0xfffful << PWM_CMPDAT0_CMP_Pos) /!< PWM CMPDAT0: CMP Mask /
sahilmgandhi	18:6a4db94011d3	20061
sahilmgandhi	18:6a4db94011d3	20062	#define PWM_CMPDAT1_CMP_Pos (0) /!< PWM CMPDAT1: CMP Position /
sahilmgandhi	18:6a4db94011d3	20063	#define PWM_CMPDAT1_CMP_Msk (0xfffful << PWM_CMPDAT1_CMP_Pos) /!< PWM CMPDAT1: CMP Mask /
sahilmgandhi	18:6a4db94011d3	20064
sahilmgandhi	18:6a4db94011d3	20065	#define PWM_CMPDAT2_CMP_Pos (0) /!< PWM CMPDAT2: CMP Position /
sahilmgandhi	18:6a4db94011d3	20066	#define PWM_CMPDAT2_CMP_Msk (0xfffful << PWM_CMPDAT2_CMP_Pos) /!< PWM CMPDAT2: CMP Mask /
sahilmgandhi	18:6a4db94011d3	20067
sahilmgandhi	18:6a4db94011d3	20068	#define PWM_CMPDAT3_CMP_Pos (0) /!< PWM CMPDAT3: CMP Position /
sahilmgandhi	18:6a4db94011d3	20069	#define PWM_CMPDAT3_CMP_Msk (0xfffful << PWM_CMPDAT3_CMP_Pos) /!< PWM CMPDAT3: CMP Mask /
sahilmgandhi	18:6a4db94011d3	20070
sahilmgandhi	18:6a4db94011d3	20071	#define PWM_CMPDAT4_CMP_Pos (0) /!< PWM CMPDAT4: CMP Position /
sahilmgandhi	18:6a4db94011d3	20072	#define PWM_CMPDAT4_CMP_Msk (0xfffful << PWM_CMPDAT4_CMP_Pos) /!< PWM CMPDAT4: CMP Mask /
sahilmgandhi	18:6a4db94011d3	20073
sahilmgandhi	18:6a4db94011d3	20074	#define PWM_CMPDAT5_CMP_Pos (0) /!< PWM CMPDAT5: CMP Position /
sahilmgandhi	18:6a4db94011d3	20075	#define PWM_CMPDAT5_CMP_Msk (0xfffful << PWM_CMPDAT5_CMP_Pos) /!< PWM CMPDAT5: CMP Mask /
sahilmgandhi	18:6a4db94011d3	20076
sahilmgandhi	18:6a4db94011d3	20077	#define PWM_CNT0_CNT_Pos (0) /!< PWM CNT0: CNT Position /
sahilmgandhi	18:6a4db94011d3	20078	#define PWM_CNT0_CNT_Msk (0xfffful << PWM_CNT0_CNT_Pos) /!< PWM CNT0: CNT Mask /
sahilmgandhi	18:6a4db94011d3	20079
sahilmgandhi	18:6a4db94011d3	20080	#define PWM_CNT1_CNT_Pos (0) /!< PWM CNT1: CNT Position /
sahilmgandhi	18:6a4db94011d3	20081	#define PWM_CNT1_CNT_Msk (0xfffful << PWM_CNT1_CNT_Pos) /!< PWM CNT1: CNT Mask /
sahilmgandhi	18:6a4db94011d3	20082
sahilmgandhi	18:6a4db94011d3	20083	#define PWM_CNT2_CNT_Pos (0) /!< PWM CNT2: CNT Position /
sahilmgandhi	18:6a4db94011d3	20084	#define PWM_CNT2_CNT_Msk (0xfffful << PWM_CNT2_CNT_Pos) /!< PWM CNT2: CNT Mask /
sahilmgandhi	18:6a4db94011d3	20085
sahilmgandhi	18:6a4db94011d3	20086	#define PWM_CNT3_CNT_Pos (0) /!< PWM CNT3: CNT Position /
sahilmgandhi	18:6a4db94011d3	20087	#define PWM_CNT3_CNT_Msk (0xfffful << PWM_CNT3_CNT_Pos) /!< PWM CNT3: CNT Mask /
sahilmgandhi	18:6a4db94011d3	20088
sahilmgandhi	18:6a4db94011d3	20089	#define PWM_CNT4_CNT_Pos (0) /!< PWM CNT4: CNT Position /
sahilmgandhi	18:6a4db94011d3	20090	#define PWM_CNT4_CNT_Msk (0xfffful << PWM_CNT4_CNT_Pos) /!< PWM CNT4: CNT Mask /
sahilmgandhi	18:6a4db94011d3	20091
sahilmgandhi	18:6a4db94011d3	20092	#define PWM_CNT5_CNT_Pos (0) /!< PWM CNT5: CNT Position /
sahilmgandhi	18:6a4db94011d3	20093	#define PWM_CNT5_CNT_Msk (0xfffful << PWM_CNT5_CNT_Pos) /!< PWM CNT5: CNT Mask /
sahilmgandhi	18:6a4db94011d3	20094
sahilmgandhi	18:6a4db94011d3	20095	#define PWM_MSKEN_MSKEN_Pos (0) /!< PWM MSKEN: MSKEN Position /
sahilmgandhi	18:6a4db94011d3	20096	#define PWM_MSKEN_MSKEN_Msk (0x3ful << PWM_MSKEN_MSKEN_Pos) /!< PWM MSKEN: MSKEN Mask /
sahilmgandhi	18:6a4db94011d3	20097
sahilmgandhi	18:6a4db94011d3	20098	#define PWM_MSK_MSKDAT_Pos (0) /!< PWM MSK: MSKDAT Position /
sahilmgandhi	18:6a4db94011d3	20099	#define PWM_MSK_MSKDAT_Msk (0x3ful << PWM_MSK_MSKDAT_Pos) /!< PWM MSK: MSKDAT Mask /
sahilmgandhi	18:6a4db94011d3	20100
sahilmgandhi	18:6a4db94011d3	20101	#define PWM_DTCTL_DTCNT01_Pos (0) /!< PWM DTCTL: DTCNT01 Position /
sahilmgandhi	18:6a4db94011d3	20102	#define PWM_DTCTL_DTCNT01_Msk (0xfful << PWM_DTCTL_DTCNT01_Pos) /!< PWM DTCTL: DTCNT01 Mask /
sahilmgandhi	18:6a4db94011d3	20103
sahilmgandhi	18:6a4db94011d3	20104	#define PWM_DTCTL_DTCNT23_Pos (8) /!< PWM DTCTL: DTCNT23 Position /
sahilmgandhi	18:6a4db94011d3	20105	#define PWM_DTCTL_DTCNT23_Msk (0xfful << PWM_DTCTL_DTCNT23_Pos) /!< PWM DTCTL: DTCNT23 Mask /
sahilmgandhi	18:6a4db94011d3	20106
sahilmgandhi	18:6a4db94011d3	20107	#define PWM_DTCTL_DTCNT45_Pos (16) /!< PWM DTCTL: DTCNT45 Position /
sahilmgandhi	18:6a4db94011d3	20108	#define PWM_DTCTL_DTCNT45_Msk (0xfful << PWM_DTCTL_DTCNT45_Pos) /!< PWM DTCTL: DTCNT45 Mask /
sahilmgandhi	18:6a4db94011d3	20109
sahilmgandhi	18:6a4db94011d3	20110	#define PWM_DTCTL_DTDIV_Pos (24) /!< PWM DTCTL: DTDIV Position /
sahilmgandhi	18:6a4db94011d3	20111	#define PWM_DTCTL_DTDIV_Msk (0x3ul << PWM_DTCTL_DTDIV_Pos) /!< PWM DTCTL: DTDIV Mask /
sahilmgandhi	18:6a4db94011d3	20112
sahilmgandhi	18:6a4db94011d3	20113	#define PWM_DTCTL_DTEN01_Pos (28) /!< PWM DTCTL: DTEN01 Position /
sahilmgandhi	18:6a4db94011d3	20114	#define PWM_DTCTL_DTEN01_Msk (0x1ul << PWM_DTCTL_DTEN01_Pos) /!< PWM DTCTL: DTEN01 Mask /
sahilmgandhi	18:6a4db94011d3	20115
sahilmgandhi	18:6a4db94011d3	20116	#define PWM_DTCTL_DTEN23_Pos (29) /!< PWM DTCTL: DTEN23 Position /
sahilmgandhi	18:6a4db94011d3	20117	#define PWM_DTCTL_DTEN23_Msk (0x1ul << PWM_DTCTL_DTEN23_Pos) /!< PWM DTCTL: DTEN23 Mask /
sahilmgandhi	18:6a4db94011d3	20118
sahilmgandhi	18:6a4db94011d3	20119	#define PWM_DTCTL_DTEN45_Pos (30) /!< PWM DTCTL: DTEN45 Position /
sahilmgandhi	18:6a4db94011d3	20120	#define PWM_DTCTL_DTEN45_Msk (0x1ul << PWM_DTCTL_DTEN45_Pos) /!< PWM DTCTL: DTEN45 Mask /
sahilmgandhi	18:6a4db94011d3	20121
sahilmgandhi	18:6a4db94011d3	20122	#define PWM_TRGADCTL_PTRGEN_Pos (0) /!< PWM TRGADCTL: PTRGEN Position /
sahilmgandhi	18:6a4db94011d3	20123	#define PWM_TRGADCTL_PTRGEN_Msk (0x3ful << PWM_TRGADCTL_PTRGEN_Pos) /!< PWM TRGADCTL: PTRGEN Mask /
sahilmgandhi	18:6a4db94011d3	20124
sahilmgandhi	18:6a4db94011d3	20125	#define PWM_TRGADCTL_CTRGEN_Pos (8) /!< PWM TRGADCTL: CTRGEN Position /
sahilmgandhi	18:6a4db94011d3	20126	#define PWM_TRGADCTL_CTRGEN_Msk (0x3ful << PWM_TRGADCTL_CTRGEN_Pos) /!< PWM TRGADCTL: CTRGEN Mask /
sahilmgandhi	18:6a4db94011d3	20127
sahilmgandhi	18:6a4db94011d3	20128	#define PWM_TRGADCTL_FTRGEN_Pos (16) /!< PWM TRGADCTL: FTRGEN Position /
sahilmgandhi	18:6a4db94011d3	20129	#define PWM_TRGADCTL_FTRGEN_Msk (0x3ful << PWM_TRGADCTL_FTRGEN_Pos) /!< PWM TRGADCTL: FTRGEN Mask /
sahilmgandhi	18:6a4db94011d3	20130
sahilmgandhi	18:6a4db94011d3	20131	#define PWM_TRGADCTL_RTRGEN_Pos (24) /!< PWM TRGADCTL: RTRGEN Position /
sahilmgandhi	18:6a4db94011d3	20132	#define PWM_TRGADCTL_RTRGEN_Msk (0x3ful << PWM_TRGADCTL_RTRGEN_Pos) /!< PWM TRGADCTL: RTRGEN Mask /
sahilmgandhi	18:6a4db94011d3	20133
sahilmgandhi	18:6a4db94011d3	20134	#define PWM_TRGADCSTS_PTRGF_Pos (0) /!< PWM TRGADCSTS: PTRGF Position /
sahilmgandhi	18:6a4db94011d3	20135	#define PWM_TRGADCSTS_PTRGF_Msk (0x3ful << PWM_TRGADCSTS_PTRGF_Pos) /!< PWM TRGADCSTS: PTRGF Mask /
sahilmgandhi	18:6a4db94011d3	20136
sahilmgandhi	18:6a4db94011d3	20137	#define PWM_TRGADCSTS_CTRGF_Pos (8) /!< PWM TRGADCSTS: CTRGF Position /
sahilmgandhi	18:6a4db94011d3	20138	#define PWM_TRGADCSTS_CTRGF_Msk (0x3ful << PWM_TRGADCSTS_CTRGF_Pos) /!< PWM TRGADCSTS: CTRGF Mask /
sahilmgandhi	18:6a4db94011d3	20139
sahilmgandhi	18:6a4db94011d3	20140	#define PWM_TRGADCSTS_FTRGF_Pos (16) /!< PWM TRGADCSTS: FTRGF Position /
sahilmgandhi	18:6a4db94011d3	20141	#define PWM_TRGADCSTS_FTRGF_Msk (0x3ful << PWM_TRGADCSTS_FTRGF_Pos) /!< PWM TRGADCSTS: FTRGF Mask /
sahilmgandhi	18:6a4db94011d3	20142
sahilmgandhi	18:6a4db94011d3	20143	#define PWM_TRGADCSTS_RTRGF_Pos (24) /!< PWM TRGADCSTS: RTRGF Position /
sahilmgandhi	18:6a4db94011d3	20144	#define PWM_TRGADCSTS_RTRGF_Msk (0x3ful << PWM_TRGADCSTS_RTRGF_Pos) /!< PWM TRGADCSTS: RTRGF Mask /
sahilmgandhi	18:6a4db94011d3	20145
sahilmgandhi	18:6a4db94011d3	20146	#define PWM_BRKCTL_BRK0EN_Pos (0) /!< PWM BRKCTL: BRK0EN Position /
sahilmgandhi	18:6a4db94011d3	20147	#define PWM_BRKCTL_BRK0EN_Msk (0x1ul << PWM_BRKCTL_BRK0EN_Pos) /!< PWM BRKCTL: BRK0EN Mask /
sahilmgandhi	18:6a4db94011d3	20148
sahilmgandhi	18:6a4db94011d3	20149	#define PWM_BRKCTL_BRK0NFDIS_Pos (1) /!< PWM BRKCTL: BRK0NFDIS Position /
sahilmgandhi	18:6a4db94011d3	20150	#define PWM_BRKCTL_BRK0NFDIS_Msk (0x1ul << PWM_BRKCTL_BRK0NFDIS_Pos) /!< PWM BRKCTL: BRK0NFDIS Mask /
sahilmgandhi	18:6a4db94011d3	20151
sahilmgandhi	18:6a4db94011d3	20152	#define PWM_BRKCTL_BRK0INV_Pos (2) /!< PWM BRKCTL: BRK0INV Position /
sahilmgandhi	18:6a4db94011d3	20153	#define PWM_BRKCTL_BRK0INV_Msk (0x1ul << PWM_BRKCTL_BRK0INV_Pos) /!< PWM BRKCTL: BRK0INV Mask /
sahilmgandhi	18:6a4db94011d3	20154
sahilmgandhi	18:6a4db94011d3	20155	#define PWM_BRKCTL_BRK0NFSEL_Pos (6) /!< PWM BRKCTL: BRK0NFSEL Position /
sahilmgandhi	18:6a4db94011d3	20156	#define PWM_BRKCTL_BRK0NFSEL_Msk (0x3ul << PWM_BRKCTL_BRK0NFSEL_Pos) /!< PWM BRKCTL: BRK0NFSEL Mask /
sahilmgandhi	18:6a4db94011d3	20157
sahilmgandhi	18:6a4db94011d3	20158	#define PWM_BRKCTL_BRK1EN_Pos (8) /!< PWM BRKCTL: BRK1EN Position /
sahilmgandhi	18:6a4db94011d3	20159	#define PWM_BRKCTL_BRK1EN_Msk (0x1ul << PWM_BRKCTL_BRK1EN_Pos) /!< PWM BRKCTL: BRK1EN Mask /
sahilmgandhi	18:6a4db94011d3	20160
sahilmgandhi	18:6a4db94011d3	20161	#define PWM_BRKCTL_BRK1NFDIS_Pos (9) /!< PWM BRKCTL: BRK1NFDIS Position /
sahilmgandhi	18:6a4db94011d3	20162	#define PWM_BRKCTL_BRK1NFDIS_Msk (0x1ul << PWM_BRKCTL_BRK1NFDIS_Pos) /!< PWM BRKCTL: BRK1NFDIS Mask /
sahilmgandhi	18:6a4db94011d3	20163
sahilmgandhi	18:6a4db94011d3	20164	#define PWM_BRKCTL_BRK1INV_Pos (10) /!< PWM BRKCTL: BRK1INV Position /
sahilmgandhi	18:6a4db94011d3	20165	#define PWM_BRKCTL_BRK1INV_Msk (0x1ul << PWM_BRKCTL_BRK1INV_Pos) /!< PWM BRKCTL: BRK1INV Mask /
sahilmgandhi	18:6a4db94011d3	20166
sahilmgandhi	18:6a4db94011d3	20167	#define PWM_BRKCTL_BK1SEL_Pos (12) /!< PWM BRKCTL: BK1SEL Position /
sahilmgandhi	18:6a4db94011d3	20168	#define PWM_BRKCTL_BK1SEL_Msk (0x3ul << PWM_BRKCTL_BK1SEL_Pos) /!< PWM BRKCTL: BK1SEL Mask /
sahilmgandhi	18:6a4db94011d3	20169
sahilmgandhi	18:6a4db94011d3	20170	#define PWM_BRKCTL_BRK1NFSEL_Pos (14) /!< PWM BRKCTL: BRK1NFSEL Position /
sahilmgandhi	18:6a4db94011d3	20171	#define PWM_BRKCTL_BRK1NFSEL_Msk (0x3ul << PWM_BRKCTL_BRK1NFSEL_Pos) /!< PWM BRKCTL: BRK1NFSEL Mask /
sahilmgandhi	18:6a4db94011d3	20172
sahilmgandhi	18:6a4db94011d3	20173	#define PWM_BRKCTL_CPO0BKEN_Pos (16) /!< PWM BRKCTL: CPO0BKEN Position /
sahilmgandhi	18:6a4db94011d3	20174	#define PWM_BRKCTL_CPO0BKEN_Msk (0x1ul << PWM_BRKCTL_CPO0BKEN_Pos) /!< PWM BRKCTL: CPO0BKEN Mask /
sahilmgandhi	18:6a4db94011d3	20175
sahilmgandhi	18:6a4db94011d3	20176	#define PWM_BRKCTL_CPO1BKEN_Pos (17) /!< PWM BRKCTL: CPO1BKEN Position /
sahilmgandhi	18:6a4db94011d3	20177	#define PWM_BRKCTL_CPO1BKEN_Msk (0x1ul << PWM_BRKCTL_CPO1BKEN_Pos) /!< PWM BRKCTL: CPO1BKEN Mask /
sahilmgandhi	18:6a4db94011d3	20178
sahilmgandhi	18:6a4db94011d3	20179	#define PWM_BRKCTL_CPO2BKEN_Pos (18) /!< PWM BRKCTL: CPO2BKEN Position /
sahilmgandhi	18:6a4db94011d3	20180	#define PWM_BRKCTL_CPO2BKEN_Msk (0x1ul << PWM_BRKCTL_CPO2BKEN_Pos) /!< PWM BRKCTL: CPO2BKEN Mask /
sahilmgandhi	18:6a4db94011d3	20181
sahilmgandhi	18:6a4db94011d3	20182	#define PWM_BRKCTL_LVDBKEN_Pos (19) /!< PWM BRKCTL: LVDBKEN Position /
sahilmgandhi	18:6a4db94011d3	20183	#define PWM_BRKCTL_LVDBKEN_Msk (0x1ul << PWM_BRKCTL_LVDBKEN_Pos) /!< PWM BRKCTL: LVDBKEN Mask /
sahilmgandhi	18:6a4db94011d3	20184
sahilmgandhi	18:6a4db94011d3	20185	#define PWM_BRKCTL_BKOD_Pos (24) /!< PWM BRKCTL: BKOD Position /
sahilmgandhi	18:6a4db94011d3	20186	#define PWM_BRKCTL_BKOD_Msk (0x3ful << PWM_BRKCTL_BKOD_Pos) /!< PWM BRKCTL: BKOD Mask /
sahilmgandhi	18:6a4db94011d3	20187
sahilmgandhi	18:6a4db94011d3	20188	#define PWM_INTCTL_PINTTYPE_Pos (0) /!< PWM INTCTL: PINTTYPE Position /
sahilmgandhi	18:6a4db94011d3	20189	#define PWM_INTCTL_PINTTYPE_Msk (0x3ful << PWM_INTCTL_PINTTYPE_Pos) /!< PWM INTCTL: PINTTYPE Mask /
sahilmgandhi	18:6a4db94011d3	20190
sahilmgandhi	18:6a4db94011d3	20191	#define PWM_INTCTL_DINTTYPE_Pos (8) /!< PWM INTCTL: DINTTYPE Position /
sahilmgandhi	18:6a4db94011d3	20192	#define PWM_INTCTL_DINTTYPE_Msk (0x3ful << PWM_INTCTL_DINTTYPE_Pos) /!< PWM INTCTL: DINTTYPE Mask /
sahilmgandhi	18:6a4db94011d3	20193
sahilmgandhi	18:6a4db94011d3	20194	#define PWM_INTEN_PIEN_Pos (0) /!< PWM INTEN: PIEN Position /
sahilmgandhi	18:6a4db94011d3	20195	#define PWM_INTEN_PIEN_Msk (0x3ful << PWM_INTEN_PIEN_Pos) /!< PWM INTEN: PIEN Mask /
sahilmgandhi	18:6a4db94011d3	20196
sahilmgandhi	18:6a4db94011d3	20197	#define PWM_INTEN_BRKIEN_Pos (6) /!< PWM INTEN: BRKIEN Position /
sahilmgandhi	18:6a4db94011d3	20198	#define PWM_INTEN_BRKIEN_Msk (0x1ul << PWM_INTEN_BRKIEN_Pos) /!< PWM INTEN: BRKIEN Mask /
sahilmgandhi	18:6a4db94011d3	20199
sahilmgandhi	18:6a4db94011d3	20200	#define PWM_INTEN_DIEN_Pos (8) /!< PWM INTEN: DIEN Position /
sahilmgandhi	18:6a4db94011d3	20201	#define PWM_INTEN_DIEN_Msk (0x3ful << PWM_INTEN_DIEN_Pos) /!< PWM INTEN: DIEN Mask /
sahilmgandhi	18:6a4db94011d3	20202
sahilmgandhi	18:6a4db94011d3	20203	#define PWM_INTEN_RLIEN_Pos (16) /!< PWM INTEN: RLIEN Position /
sahilmgandhi	18:6a4db94011d3	20204	#define PWM_INTEN_RLIEN_Msk (0x3ful << PWM_INTEN_RLIEN_Pos) /!< PWM INTEN: RLIEN Mask /
sahilmgandhi	18:6a4db94011d3	20205
sahilmgandhi	18:6a4db94011d3	20206	#define PWM_INTEN_FLIEN_Pos (24) /!< PWM INTEN: FLIEN Position /
sahilmgandhi	18:6a4db94011d3	20207	#define PWM_INTEN_FLIEN_Msk (0x3ful << PWM_INTEN_FLIEN_Pos) /!< PWM INTEN: FLIEN Mask /
sahilmgandhi	18:6a4db94011d3	20208
sahilmgandhi	18:6a4db94011d3	20209	#define PWM_INTSTS_PIF_Pos (0) /!< PWM INTSTS: PIF Position /
sahilmgandhi	18:6a4db94011d3	20210	#define PWM_INTSTS_PIF_Msk (0x3ful << PWM_INTSTS_PIF_Pos) /!< PWM INTSTS: PIF Mask /
sahilmgandhi	18:6a4db94011d3	20211
sahilmgandhi	18:6a4db94011d3	20212	#define PWM_INTSTS_BRKIF0_Pos (6) /!< PWM INTSTS: BRKIF0 Position /
sahilmgandhi	18:6a4db94011d3	20213	#define PWM_INTSTS_BRKIF0_Msk (0x1ul << PWM_INTSTS_BRKIF0_Pos) /!< PWM INTSTS: BRKIF0 Mask /
sahilmgandhi	18:6a4db94011d3	20214
sahilmgandhi	18:6a4db94011d3	20215	#define PWM_INTSTS_BRKIF1_Pos (7) /!< PWM INTSTS: BRKIF1 Position /
sahilmgandhi	18:6a4db94011d3	20216	#define PWM_INTSTS_BRKIF1_Msk (0x1ul << PWM_INTSTS_BRKIF1_Pos) /!< PWM INTSTS: BRKIF1 Mask /
sahilmgandhi	18:6a4db94011d3	20217
sahilmgandhi	18:6a4db94011d3	20218	#define PWM_INTSTS_DIF_Pos (8) /!< PWM INTSTS: DIF Position /
sahilmgandhi	18:6a4db94011d3	20219	#define PWM_INTSTS_DIF_Msk (0x3ful << PWM_INTSTS_DIF_Pos) /!< PWM INTSTS: DIF Mask /
sahilmgandhi	18:6a4db94011d3	20220
sahilmgandhi	18:6a4db94011d3	20221	#define PWM_INTSTS_BRKLK0_Pos (14) /!< PWM INTSTS: BRKLK0 Position /
sahilmgandhi	18:6a4db94011d3	20222	#define PWM_INTSTS_BRKLK0_Msk (0x1ul << PWM_INTSTS_BRKLK0_Pos) /!< PWM INTSTS: BRKLK0 Mask /
sahilmgandhi	18:6a4db94011d3	20223
sahilmgandhi	18:6a4db94011d3	20224	#define PWM_INTSTS_CRLIF_Pos (16) /!< PWM INTSTS: CRLIF Position /
sahilmgandhi	18:6a4db94011d3	20225	#define PWM_INTSTS_CRLIF_Msk (0x3ful << PWM_INTSTS_CRLIF_Pos) /!< PWM INTSTS: CRLIF Mask /
sahilmgandhi	18:6a4db94011d3	20226
sahilmgandhi	18:6a4db94011d3	20227	#define PWM_INTSTS_BRKSTS0_Pos (22) /!< PWM INTSTS: BRKSTS0 Position /
sahilmgandhi	18:6a4db94011d3	20228	#define PWM_INTSTS_BRKSTS0_Msk (0x1ul << PWM_INTSTS_BRKSTS0_Pos) /!< PWM INTSTS: BRKSTS0 Mask /
sahilmgandhi	18:6a4db94011d3	20229
sahilmgandhi	18:6a4db94011d3	20230	#define PWM_INTSTS_BRKSTS1_Pos (23) /!< PWM INTSTS: BRKSTS1 Position /
sahilmgandhi	18:6a4db94011d3	20231	#define PWM_INTSTS_BRKSTS1_Msk (0x1ul << PWM_INTSTS_BRKSTS1_Pos) /!< PWM INTSTS: BRKSTS1 Mask /
sahilmgandhi	18:6a4db94011d3	20232
sahilmgandhi	18:6a4db94011d3	20233	#define PWM_INTSTS_CFLIF_Pos (24) /!< PWM INTSTS: CFLIF Position /
sahilmgandhi	18:6a4db94011d3	20234	#define PWM_INTSTS_CFLIF_Msk (0x3ful << PWM_INTSTS_CFLIF_Pos) /!< PWM INTSTS: CFLIF Mask /
sahilmgandhi	18:6a4db94011d3	20235
sahilmgandhi	18:6a4db94011d3	20236	#define PWM_POEN_POEN_Pos (0) /!< PWM POEN: POEN Position /
sahilmgandhi	18:6a4db94011d3	20237	#define PWM_POEN_POEN_Msk (0x3ful << PWM_POEN_POEN_Pos) /!< PWM POEN: POEN Mask /
sahilmgandhi	18:6a4db94011d3	20238
sahilmgandhi	18:6a4db94011d3	20239	#define PWM_CAPCTL_CAPEN_Pos (0) /!< PWM CAPCTL: CAPEN Position /
sahilmgandhi	18:6a4db94011d3	20240	#define PWM_CAPCTL_CAPEN_Msk (0x3ful << PWM_CAPCTL_CAPEN_Pos) /!< PWM CAPCTL: CAPEN Mask /
sahilmgandhi	18:6a4db94011d3	20241
sahilmgandhi	18:6a4db94011d3	20242	#define PWM_CAPCTL_CAPINV_Pos (8) /!< PWM CAPCTL: CAPINV Position /
sahilmgandhi	18:6a4db94011d3	20243	#define PWM_CAPCTL_CAPINV_Msk (0x3ful << PWM_CAPCTL_CAPINV_Pos) /!< PWM CAPCTL: CAPINV Mask /
sahilmgandhi	18:6a4db94011d3	20244
sahilmgandhi	18:6a4db94011d3	20245	#define PWM_CAPCTL_RCRLDEN_Pos (16) /!< PWM CAPCTL: RCRLDEN Position /
sahilmgandhi	18:6a4db94011d3	20246	#define PWM_CAPCTL_RCRLDEN_Msk (0x3ful << PWM_CAPCTL_RCRLDEN_Pos) /!< PWM CAPCTL: RCRLDEN Mask /
sahilmgandhi	18:6a4db94011d3	20247
sahilmgandhi	18:6a4db94011d3	20248	#define PWM_CAPCTL_FCRLDEN_Pos (24) /!< PWM CAPCTL: FCRLDEN Position /
sahilmgandhi	18:6a4db94011d3	20249	#define PWM_CAPCTL_FCRLDEN_Msk (0x3ful << PWM_CAPCTL_FCRLDEN_Pos) /!< PWM CAPCTL: FCRLDEN Mask /
sahilmgandhi	18:6a4db94011d3	20250
sahilmgandhi	18:6a4db94011d3	20251	#define PWM_CAPINEN_CAPINEN_Pos (0) /!< PWM CAPINEN: CAPINEN Position /
sahilmgandhi	18:6a4db94011d3	20252	#define PWM_CAPINEN_CAPINEN_Msk (0x3ful << PWM_CAPINEN_CAPINEN_Pos) /!< PWM CAPINEN: CAPINEN Mask /
sahilmgandhi	18:6a4db94011d3	20253
sahilmgandhi	18:6a4db94011d3	20254	#define PWM_CAPSTS_CRIFOV_Pos (0) /!< PWM CAPSTS: CRIFOV Position /
sahilmgandhi	18:6a4db94011d3	20255	#define PWM_CAPSTS_CRIFOV_Msk (0x3ful << PWM_CAPSTS_CRIFOV_Pos) /!< PWM CAPSTS: CRIFOV Mask /
sahilmgandhi	18:6a4db94011d3	20256
sahilmgandhi	18:6a4db94011d3	20257	#define PWM_CAPSTS_FLIFOV_Pos (8) /!< PWM CAPSTS: FLIFOV Position /
sahilmgandhi	18:6a4db94011d3	20258	#define PWM_CAPSTS_FLIFOV_Msk (0x3ful << PWM_CAPSTS_FLIFOV_Pos) /!< PWM CAPSTS: FLIFOV Mask /
sahilmgandhi	18:6a4db94011d3	20259
sahilmgandhi	18:6a4db94011d3	20260	#define PWM_RCAPDAT0_RCAPDAT_Pos (0) /!< PWM RCAPDAT0: RCAPDAT Position /
sahilmgandhi	18:6a4db94011d3	20261	#define PWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT0_RCAPDAT_Pos) /!< PWM RCAPDAT0: RCAPDAT Mask /
sahilmgandhi	18:6a4db94011d3	20262
sahilmgandhi	18:6a4db94011d3	20263	#define PWM_FCAPDAT0_FCAPDAT_Pos (0) /!< PWM FCAPDAT0: FCAPDAT Position /
sahilmgandhi	18:6a4db94011d3	20264	#define PWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT0_FCAPDAT_Pos) /!< PWM FCAPDAT0: FCAPDAT Mask /
sahilmgandhi	18:6a4db94011d3	20265
sahilmgandhi	18:6a4db94011d3	20266	#define PWM_RCAPDAT1_RCAPDAT_Pos (0) /!< PWM RCAPDAT1: RCAPDAT Position /
sahilmgandhi	18:6a4db94011d3	20267	#define PWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT1_RCAPDAT_Pos) /!< PWM RCAPDAT1: RCAPDAT Mask /
sahilmgandhi	18:6a4db94011d3	20268
sahilmgandhi	18:6a4db94011d3	20269	#define PWM_FCAPDAT1_FCAPDAT_Pos (0) /!< PWM FCAPDAT1: FCAPDAT Position /
sahilmgandhi	18:6a4db94011d3	20270	#define PWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT1_FCAPDAT_Pos) /!< PWM FCAPDAT1: FCAPDAT Mask /
sahilmgandhi	18:6a4db94011d3	20271
sahilmgandhi	18:6a4db94011d3	20272	#define PWM_RCAPDAT2_RCAPDAT_Pos (0) /!< PWM RCAPDAT2: RCAPDAT Position /
sahilmgandhi	18:6a4db94011d3	20273	#define PWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT2_RCAPDAT_Pos) /!< PWM RCAPDAT2: RCAPDAT Mask /
sahilmgandhi	18:6a4db94011d3	20274
sahilmgandhi	18:6a4db94011d3	20275	#define PWM_FCAPDAT2_FCAPDAT_Pos (0) /!< PWM FCAPDAT2: FCAPDAT Position /
sahilmgandhi	18:6a4db94011d3	20276	#define PWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT2_FCAPDAT_Pos) /!< PWM FCAPDAT2: FCAPDAT Mask /
sahilmgandhi	18:6a4db94011d3	20277
sahilmgandhi	18:6a4db94011d3	20278	#define PWM_RCAPDAT3_RCAPDAT_Pos (0) /!< PWM RCAPDAT3: RCAPDAT Position /
sahilmgandhi	18:6a4db94011d3	20279	#define PWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT3_RCAPDAT_Pos) /!< PWM RCAPDAT3: RCAPDAT Mask /
sahilmgandhi	18:6a4db94011d3	20280
sahilmgandhi	18:6a4db94011d3	20281	#define PWM_FCAPDAT3_FCAPDAT_Pos (0) /!< PWM FCAPDAT3: FCAPDAT Position /
sahilmgandhi	18:6a4db94011d3	20282	#define PWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT3_FCAPDAT_Pos) /!< PWM FCAPDAT3: FCAPDAT Mask /
sahilmgandhi	18:6a4db94011d3	20283
sahilmgandhi	18:6a4db94011d3	20284	#define PWM_RCAPDAT4_RCAPDAT_Pos (0) /!< PWM RCAPDAT4: RCAPDAT Position /
sahilmgandhi	18:6a4db94011d3	20285	#define PWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT4_RCAPDAT_Pos) /!< PWM RCAPDAT4: RCAPDAT Mask /
sahilmgandhi	18:6a4db94011d3	20286
sahilmgandhi	18:6a4db94011d3	20287	#define PWM_FCAPDAT4_FCAPDAT_Pos (0) /!< PWM FCAPDAT4: FCAPDAT Position /
sahilmgandhi	18:6a4db94011d3	20288	#define PWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT4_FCAPDAT_Pos) /!< PWM FCAPDAT4: FCAPDAT Mask /
sahilmgandhi	18:6a4db94011d3	20289
sahilmgandhi	18:6a4db94011d3	20290	#define PWM_RCAPDAT5_RCAPDAT_Pos (0) /!< PWM RCAPDAT5: RCAPDAT Position /
sahilmgandhi	18:6a4db94011d3	20291	#define PWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT5_RCAPDAT_Pos) /!< PWM RCAPDAT5: RCAPDAT Mask /
sahilmgandhi	18:6a4db94011d3	20292
sahilmgandhi	18:6a4db94011d3	20293	#define PWM_FCAPDAT5_FCAPDAT_Pos (0) /!< PWM FCAPDAT5: FCAPDAT Position /
sahilmgandhi	18:6a4db94011d3	20294	#define PWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT5_FCAPDAT_Pos) /!< PWM FCAPDAT5: FCAPDAT Mask /
sahilmgandhi	18:6a4db94011d3	20295
sahilmgandhi	18:6a4db94011d3	20296	#define PWM_SBS0_SYNCBUSY_Pos (0) /!< PWM SBS0: SYNCBUSY Position /
sahilmgandhi	18:6a4db94011d3	20297	#define PWM_SBS0_SYNCBUSY_Msk (0x1ul << PWM_SBS0_SYNCBUSY_Pos) /!< PWM SBS0: SYNCBUSY Mask /
sahilmgandhi	18:6a4db94011d3	20298
sahilmgandhi	18:6a4db94011d3	20299	#define PWM_SBS1_SYNCBUSY_Pos (0) /!< PWM SBS1: SYNCBUSY Position /
sahilmgandhi	18:6a4db94011d3	20300	#define PWM_SBS1_SYNCBUSY_Msk (0x1ul << PWM_SBS1_SYNCBUSY_Pos) /!< PWM SBS1: SYNCBUSY Mask /
sahilmgandhi	18:6a4db94011d3	20301
sahilmgandhi	18:6a4db94011d3	20302	#define PWM_SBS2_SYNCBUSY_Pos (0) /!< PWM SBS2: SYNCBUSY Position /
sahilmgandhi	18:6a4db94011d3	20303	#define PWM_SBS2_SYNCBUSY_Msk (0x1ul << PWM_SBS2_SYNCBUSY_Pos) /!< PWM SBS2: SYNCBUSY Mask /
sahilmgandhi	18:6a4db94011d3	20304
sahilmgandhi	18:6a4db94011d3	20305	#define PWM_SBS3_SYNCBUSY_Pos (0) /!< PWM SBS3: SYNCBUSY Position /
sahilmgandhi	18:6a4db94011d3	20306	#define PWM_SBS3_SYNCBUSY_Msk (0x1ul << PWM_SBS3_SYNCBUSY_Pos) /!< PWM SBS3: SYNCBUSY Mask /
sahilmgandhi	18:6a4db94011d3	20307
sahilmgandhi	18:6a4db94011d3	20308	#define PWM_SBS4_SYNCBUSY_Pos (0) /!< PWM SBS4: SYNCBUSY Position /
sahilmgandhi	18:6a4db94011d3	20309	#define PWM_SBS4_SYNCBUSY_Msk (0x1ul << PWM_SBS4_SYNCBUSY_Pos) /!< PWM SBS4: SYNCBUSY Mask /
sahilmgandhi	18:6a4db94011d3	20310
sahilmgandhi	18:6a4db94011d3	20311	#define PWM_SBS5_SYNCBUSY_Pos (0) /!< PWM SBS5: SYNCBUSY Position /
sahilmgandhi	18:6a4db94011d3	20312	#define PWM_SBS5_SYNCBUSY_Msk (0x1ul << PWM_SBS5_SYNCBUSY_Pos) /!< PWM SBS5: SYNCBUSY Mask /
sahilmgandhi	18:6a4db94011d3	20313
sahilmgandhi	18:6a4db94011d3	20314	/*@}/ /* PWM_CONST */
sahilmgandhi	18:6a4db94011d3	20315	/*@}/ /* end of PWM register group */
sahilmgandhi	18:6a4db94011d3	20316
sahilmgandhi	18:6a4db94011d3	20317
sahilmgandhi	18:6a4db94011d3	20318	/---------------------- Quadrature Encoder Interface -------------------------/
sahilmgandhi	18:6a4db94011d3	20319	/**
sahilmgandhi	18:6a4db94011d3	20320	@addtogroup QEI Quadrature Encoder Interface(QEI)
sahilmgandhi	18:6a4db94011d3	20321	Memory Mapped Structure for QEI Controller
sahilmgandhi	18:6a4db94011d3	20322	@{ */
sahilmgandhi	18:6a4db94011d3	20323
sahilmgandhi	18:6a4db94011d3	20324	typedef struct {
sahilmgandhi	18:6a4db94011d3	20325
sahilmgandhi	18:6a4db94011d3	20326
sahilmgandhi	18:6a4db94011d3	20327	/**
sahilmgandhi	18:6a4db94011d3	20328	* CNT
sahilmgandhi	18:6a4db94011d3	20329	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	20330	* Offset: 0x00 QEI Pulse Counter
sahilmgandhi	18:6a4db94011d3	20331	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	20332	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	20333	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	20334	* \|[0:31] \|VAL \|Quadrature Encoder Pulse Counter
sahilmgandhi	18:6a4db94011d3	20335	* \| \| \|A 32-bit up/down counter.
sahilmgandhi	18:6a4db94011d3	20336	* \| \| \|When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (QEI_STATUS[27]) is one or decreased by one if the bit DIRF is zero.
sahilmgandhi	18:6a4db94011d3	20337	* \| \| \|This register performs an integrator which count value is proportional to the encoder position.
sahilmgandhi	18:6a4db94011d3	20338	* \| \| \|The pulse counter may be initialized to a predetermined value by one of three events occurs:.
sahilmgandhi	18:6a4db94011d3	20339	* \| \| \|1. Software written if QEIEN (QEI_CTR[29]) = 0.
sahilmgandhi	18:6a4db94011d3	20340	* \| \| \|2. Compare-match event if QEIEN=1 and QEI is in compare-counting mode.
sahilmgandhi	18:6a4db94011d3	20341	* \| \| \|3. Index signal change if QEIEN=1 and IDXRLDEN (QEI_CTR[27])=1.
sahilmgandhi	18:6a4db94011d3	20342	*/
sahilmgandhi	18:6a4db94011d3	20343	__IO uint32_t CNT;
sahilmgandhi	18:6a4db94011d3	20344
sahilmgandhi	18:6a4db94011d3	20345	/**
sahilmgandhi	18:6a4db94011d3	20346	* CNTHOLD
sahilmgandhi	18:6a4db94011d3	20347	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	20348	* Offset: 0x04 QEI Pulse Counter Hold Register
sahilmgandhi	18:6a4db94011d3	20349	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	20350	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	20351	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	20352	* \|[0:31] \|VAL \|Quadrature Encoder Pulse Counter Hold Register
sahilmgandhi	18:6a4db94011d3	20353	* \| \| \|When bit HOLDCNT (QEIx_CTR[24]) goes from low to high, the QEI_CNT value is copied into QEI_CNTHOLD register.
sahilmgandhi	18:6a4db94011d3	20354	*/
sahilmgandhi	18:6a4db94011d3	20355	__IO uint32_t CNTHOLD;
sahilmgandhi	18:6a4db94011d3	20356
sahilmgandhi	18:6a4db94011d3	20357	/**
sahilmgandhi	18:6a4db94011d3	20358	* CNTLATCH
sahilmgandhi	18:6a4db94011d3	20359	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	20360	* Offset: 0x08 QEI Pulse Counter Index Latch Register
sahilmgandhi	18:6a4db94011d3	20361	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	20362	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	20363	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	20364	* \|[0:31] \|VAL \|Quadrature Encoder Pulse Counter Index Latch
sahilmgandhi	18:6a4db94011d3	20365	* \| \| \|When the IDXF (QEI_STATUS[18]) bit is set, the QEI_CNT value is copied into QEI_CNTLATCH register.
sahilmgandhi	18:6a4db94011d3	20366	*/
sahilmgandhi	18:6a4db94011d3	20367	__IO uint32_t CNTLATCH;
sahilmgandhi	18:6a4db94011d3	20368
sahilmgandhi	18:6a4db94011d3	20369	/**
sahilmgandhi	18:6a4db94011d3	20370	* CNTCMP
sahilmgandhi	18:6a4db94011d3	20371	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	20372	* Offset: 0x0C QEI Pulse Counter Compare Register
sahilmgandhi	18:6a4db94011d3	20373	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	20374	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	20375	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	20376	* \|[0:31] \|VAL \|Quadrature Encoder Pulse Counter Compare
sahilmgandhi	18:6a4db94011d3	20377	* \| \| \|if the QEI controller is in the compare-counting mode CMPENN (QEI_CTR[28]) =1, when the value of QEI_CNT matches the value of VAL the bit CMPF will be set.
sahilmgandhi	18:6a4db94011d3	20378	* \| \| \|This register is software writable.
sahilmgandhi	18:6a4db94011d3	20379	*/
sahilmgandhi	18:6a4db94011d3	20380	__IO uint32_t CNTCMP;
sahilmgandhi	18:6a4db94011d3	20381	uint32_t RESERVE0[1];
sahilmgandhi	18:6a4db94011d3	20382
sahilmgandhi	18:6a4db94011d3	20383
sahilmgandhi	18:6a4db94011d3	20384	/**
sahilmgandhi	18:6a4db94011d3	20385	* MAXCNT
sahilmgandhi	18:6a4db94011d3	20386	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	20387	* Offset: 0x14 QEI Pre-set Maximum Count Register
sahilmgandhi	18:6a4db94011d3	20388	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	20389	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	20390	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	20391	* \|[0:31] \|VAL \|Quadrature Encoder Preset Maximum Count
sahilmgandhi	18:6a4db94011d3	20392	* \| \| \|This register value determined by user stores the maximum value which may be the number of the quadrature encoder pulses in a revolution for the QEI controller compare-counting mode
sahilmgandhi	18:6a4db94011d3	20393	*/
sahilmgandhi	18:6a4db94011d3	20394	__IO uint32_t CNTMAX;
sahilmgandhi	18:6a4db94011d3	20395
sahilmgandhi	18:6a4db94011d3	20396	/**
sahilmgandhi	18:6a4db94011d3	20397	* CTR
sahilmgandhi	18:6a4db94011d3	20398	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	20399	* Offset: 0x18 QEI Controller Control Register
sahilmgandhi	18:6a4db94011d3	20400	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	20401	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	20402	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	20403	* \|[0:1] \|NFCLKSEL \|Noise Filter Clock Pre-Divide Selection
sahilmgandhi	18:6a4db94011d3	20404	* \| \| \|To determine the sampling frequency of the Noise Filter clock .
sahilmgandhi	18:6a4db94011d3	20405	* \| \| \|00 = QEI_CLK.
sahilmgandhi	18:6a4db94011d3	20406	* \| \| \|01 = QEI_CLK/2.
sahilmgandhi	18:6a4db94011d3	20407	* \| \| \|10 = QEI_CLK/4.
sahilmgandhi	18:6a4db94011d3	20408	* \| \| \|11 = QEI_CLK/16.
sahilmgandhi	18:6a4db94011d3	20409	* \|[3] \|NFDIS \|QEI Controller Input Noise Filter Disable Control
sahilmgandhi	18:6a4db94011d3	20410	* \| \| \|0 = The noise filter of QEI controller Enabled.
sahilmgandhi	18:6a4db94011d3	20411	* \| \| \|1 = The noise filter of QEI controller Disabled.
sahilmgandhi	18:6a4db94011d3	20412	* \|[4] \|CHAEN \|QEA Input To QEI Controller Enable Control
sahilmgandhi	18:6a4db94011d3	20413	* \| \| \|0 = QEA input to QEI Controller Disabled.
sahilmgandhi	18:6a4db94011d3	20414	* \| \| \|1 = QEA input to QEI Controller Enabled.
sahilmgandhi	18:6a4db94011d3	20415	* \|[5] \|CHBEN \|QEB Input To QEI Controller Enable Control
sahilmgandhi	18:6a4db94011d3	20416	* \| \| \|0 = QEB input to QEI Controller Disabled.
sahilmgandhi	18:6a4db94011d3	20417	* \| \| \|1 = QEB input to QEI Controller Enabled.
sahilmgandhi	18:6a4db94011d3	20418	* \|[6] \|IDXEN \|IDX Input To QEI Controller Enable Control
sahilmgandhi	18:6a4db94011d3	20419	* \| \| \|0 = IDX input to QEI Controller Disabled.
sahilmgandhi	18:6a4db94011d3	20420	* \| \| \|1 = IDX input to QEI Controller Enabled.
sahilmgandhi	18:6a4db94011d3	20421	* \|[8:9] \|MODE \|QEI Counting Mode Selection
sahilmgandhi	18:6a4db94011d3	20422	* \| \| \|There are four quadrature encoder pulse counter operation modes.
sahilmgandhi	18:6a4db94011d3	20423	* \| \| \|00 = X4 Free-counting Mode.
sahilmgandhi	18:6a4db94011d3	20424	* \| \| \|01 = X2 Free-counting Mode.
sahilmgandhi	18:6a4db94011d3	20425	* \| \| \|10 = X4 Compare-counting Mode.
sahilmgandhi	18:6a4db94011d3	20426	* \| \| \|11 = X2 Compare-counting Mode.
sahilmgandhi	18:6a4db94011d3	20427	* \|[12] \|CHAINV \|Inverse QEA Input Polarity
sahilmgandhi	18:6a4db94011d3	20428	* \| \| \|0 = Not inverse QEA input polarity.
sahilmgandhi	18:6a4db94011d3	20429	* \| \| \|1 = QEA input polarity is inversed to QEI controller.
sahilmgandhi	18:6a4db94011d3	20430	* \|[13] \|CHBINV \|Inverse QEB Input Polarity
sahilmgandhi	18:6a4db94011d3	20431	* \| \| \|0 = Not inverse QEB input polarity.
sahilmgandhi	18:6a4db94011d3	20432	* \| \| \|1 = QEB input polarity is inversed to QEI controller.
sahilmgandhi	18:6a4db94011d3	20433	* \|[14] \|IDXINV \|Inverse IDX Input Polarity
sahilmgandhi	18:6a4db94011d3	20434	* \| \| \|0 = Not inverse IDX input polarity.
sahilmgandhi	18:6a4db94011d3	20435	* \| \| \|1 = IDX input polarity is inversed to QEI controller.
sahilmgandhi	18:6a4db94011d3	20436	* \|[16] \|OVUNIEN \|OVUNF Trigger QEI Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	20437	* \| \| \|0 = OVUNF can trigger QEI controller interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	20438	* \| \| \|1 = OVUNF can trigger QEI controller interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	20439	* \|[17] \|DIRIEN \|DIRCHGF Trigger QEI Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	20440	* \| \| \|0 = DIRCHGF can trigger QEI controller interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	20441	* \| \| \|1 = DIRCHGF can trigger QEI controller interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	20442	* \|[18] \|CMPIEN \|CMPF Trigger QEI Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	20443	* \| \| \|0 = CMPF can trigger QEI controller interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	20444	* \| \| \|1 = CMPF can trigger QEI controller interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	20445	* \|[19] \|IDXIEN \|IDXF Trigger QEI Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	20446	* \| \| \|0 = The IDXF can trigger QEI interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	20447	* \| \| \|1 = The IDXF can trigger QEI interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	20448	* \|[20] \|HOLDTMR0 \|Hold QEI_CNT By Timer 0
sahilmgandhi	18:6a4db94011d3	20449	* \| \| \|0 = TIF (TISR0[0]) has no effect on HOLDCNT.
sahilmgandhi	18:6a4db94011d3	20450	* \| \| \|1 = A rising edge of bit TIF (TISR0[0]) in timer 0 sets HOLDCNT to 1.
sahilmgandhi	18:6a4db94011d3	20451	* \|[21] \|HOLDTMR1 \|Hold QEI_CNT By Timer 1
sahilmgandhi	18:6a4db94011d3	20452	* \| \| \|0 = TIF (TISR1[0]) has no effect on HOLDCNT.
sahilmgandhi	18:6a4db94011d3	20453	* \| \| \|1 = A rising edge of bit TIF (TISR1[0]) in timer 1 sets HOLDCNT to 1.
sahilmgandhi	18:6a4db94011d3	20454	* \|[22] \|HOLDTMR2 \|Hold QEI_CNT By Timer 2
sahilmgandhi	18:6a4db94011d3	20455	* \| \| \|0 = TIF (TISR2[0]) has no effect on HOLDCNT.
sahilmgandhi	18:6a4db94011d3	20456	* \| \| \|1 = A rising edge of bit TIF (TISR2[0]) in timer 2 sets HOLDCNT to 1.
sahilmgandhi	18:6a4db94011d3	20457	* \|[23] \|HOLDTMR3 \|Hold QEI_CNT By Timer 3
sahilmgandhi	18:6a4db94011d3	20458	* \| \| \|0 = TIF (TISR3[0]) has no effect on HOLDCNT.
sahilmgandhi	18:6a4db94011d3	20459	* \| \| \|1 = A rising edge of bit TIF (TISR3[0]) in timer 3 sets HOLDCNT to 1.
sahilmgandhi	18:6a4db94011d3	20460	* \|[24] \|HOLDCNT \|Hold QEI_CNT Control
sahilmgandhi	18:6a4db94011d3	20461	* \| \| \|When this bit is set from low to high, the QEI_CNT value is copied into QEI_CNTHOLD.
sahilmgandhi	18:6a4db94011d3	20462	* \| \| \|This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TISTRx[0]).
sahilmgandhi	18:6a4db94011d3	20463	* \| \| \|0 = No operation.
sahilmgandhi	18:6a4db94011d3	20464	* \| \| \|1 = QEI_CNT content is captured and stored in QEI_CNTHOLD.
sahilmgandhi	18:6a4db94011d3	20465	* \| \| \|Note: This bit is automatically cleared after QEI_CNTHOLD holds QEI_CNT value.
sahilmgandhi	18:6a4db94011d3	20466	* \|[25] \|IDXLATEN \|Index Latch QEI_CNT Enable Control
sahilmgandhi	18:6a4db94011d3	20467	* \| \| \|If this bit is set to high, the QEI_CNT content will be latched into QEI_CNTLATCH at every rising on signal CHX.
sahilmgandhi	18:6a4db94011d3	20468	* \| \| \|0 = The index signal latch QEI counter function Disabled.
sahilmgandhi	18:6a4db94011d3	20469	* \| \| \|1 = The index signal latch QEI counter function Enabled.
sahilmgandhi	18:6a4db94011d3	20470	* \|[27] \|IDXRLDEN \|Index Trigger QEI_CNT Reload Enable Control
sahilmgandhi	18:6a4db94011d3	20471	* \| \| \|When this bit is high and a rising edge comes on signal CHX, the QEI_CNT will be reset to zero if the counter is in up-counting type (DIRF = 1); while the QEI_CNT will be reloaded with QEI_MAXCNT content if the counter is in down-counting type (DIRF = 0).
sahilmgandhi	18:6a4db94011d3	20472	* \| \| \|0 = Reload function Disabled.
sahilmgandhi	18:6a4db94011d3	20473	* \| \| \|1 = QEI_CNT re-initialized by Index signal Enabled.
sahilmgandhi	18:6a4db94011d3	20474	* \|[28] \|CMPENN \|The Compare Function Enable Control
sahilmgandhi	18:6a4db94011d3	20475	* \| \| \|The compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register QEI_CNTCMP, if QEI_CNT value reaches QEI_CNTCMP, the flag CMPF will be set.
sahilmgandhi	18:6a4db94011d3	20476	* \| \| \|0 = Compare function Disabled.
sahilmgandhi	18:6a4db94011d3	20477	* \| \| \|1 = Compare function Enabled.
sahilmgandhi	18:6a4db94011d3	20478	* \|[29] \|QEIEN \|Quadrature Encoder Interface Controller Enable Control
sahilmgandhi	18:6a4db94011d3	20479	* \| \| \|0 = QEI controller function Disabled.
sahilmgandhi	18:6a4db94011d3	20480	* \| \| \|1 = QEI controller function Enabled.
sahilmgandhi	18:6a4db94011d3	20481	*/
sahilmgandhi	18:6a4db94011d3	20482	__IO uint32_t CTR;
sahilmgandhi	18:6a4db94011d3	20483	uint32_t RESERVE1[4];
sahilmgandhi	18:6a4db94011d3	20484
sahilmgandhi	18:6a4db94011d3	20485
sahilmgandhi	18:6a4db94011d3	20486	/**
sahilmgandhi	18:6a4db94011d3	20487	* STATUS
sahilmgandhi	18:6a4db94011d3	20488	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	20489	* Offset: 0x2C QEI Controller Status Register
sahilmgandhi	18:6a4db94011d3	20490	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	20491	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	20492	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	20493	* \|[0] \|IDXF \|IDX Detected Flag
sahilmgandhi	18:6a4db94011d3	20494	* \| \| \|When the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high.
sahilmgandhi	18:6a4db94011d3	20495	* \| \| \|0 = No rising edge detected on signal CHX.
sahilmgandhi	18:6a4db94011d3	20496	* \| \| \|1 = A rising edge occurs on signal CHX.
sahilmgandhi	18:6a4db94011d3	20497	* \| \| \|Note: This bit is only cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	20498	* \|[1] \|CMPF \|Compare-Match Flag
sahilmgandhi	18:6a4db94011d3	20499	* \| \| \|If the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the QEI_CNTCMP value.
sahilmgandhi	18:6a4db94011d3	20500	* \| \| \|0 = QEI counter does not match with QEI_CNTCMP value.
sahilmgandhi	18:6a4db94011d3	20501	* \| \| \|1 = QEI counter counts to the same as QEI_CNTCMP value.
sahilmgandhi	18:6a4db94011d3	20502	* \| \| \|Note: This bit is only cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	20503	* \|[2] \|OVUNF \|QEI Counter Overflow Or Underflow Flag
sahilmgandhi	18:6a4db94011d3	20504	* \| \| \|Flag is set by hardware while QEI_CNT overflows from 0xFFFF_FFFF to zero in free-counting mode or from the QEI_MAXCNT value to zero in compare-counting mode.
sahilmgandhi	18:6a4db94011d3	20505	* \| \| \|Similarly, the flag is set wile QEI counter underflows from zero to 0xFFFF_FFFF or QEI_MAXCNT.
sahilmgandhi	18:6a4db94011d3	20506	* \| \| \|0 = No overflow or underflow occurs in QEI counter.
sahilmgandhi	18:6a4db94011d3	20507	* \| \| \|1 = QEI counter occurs counting overflow or underflow.
sahilmgandhi	18:6a4db94011d3	20508	* \| \| \|Note: This bit is only cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	20509	* \|[3] \|DIRCHGF \|Direction Change Flag
sahilmgandhi	18:6a4db94011d3	20510	* \| \| \|Flag is set by hardware while QEI counter counting direction is changed.
sahilmgandhi	18:6a4db94011d3	20511	* \| \| \|Software can clear this bit by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	20512	* \| \| \|0 = No change in QEI counter counting direction.
sahilmgandhi	18:6a4db94011d3	20513	* \| \| \|1 = QEI counter counting direction is changed.
sahilmgandhi	18:6a4db94011d3	20514	* \| \| \|Note: This bit is only cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	20515	* \|[8] \|DIRF \|QEI Counter Counting Direction Indication
sahilmgandhi	18:6a4db94011d3	20516	* \| \| \|0 = QEI Counter is in down-counting.
sahilmgandhi	18:6a4db94011d3	20517	* \| \| \|1 = QEI Counter is in up-counting.
sahilmgandhi	18:6a4db94011d3	20518	* \| \| \|Note: This bit is set/reset by hardware according to the phase detection between CHA and CHB.
sahilmgandhi	18:6a4db94011d3	20519	*/
sahilmgandhi	18:6a4db94011d3	20520	__IO uint32_t STATUS;
sahilmgandhi	18:6a4db94011d3	20521
sahilmgandhi	18:6a4db94011d3	20522	} QEI_T;
sahilmgandhi	18:6a4db94011d3	20523
sahilmgandhi	18:6a4db94011d3	20524	/**
sahilmgandhi	18:6a4db94011d3	20525	@addtogroup QEI_CONST QEI Bit Field Definition
sahilmgandhi	18:6a4db94011d3	20526	Constant Definitions for QEI Controller
sahilmgandhi	18:6a4db94011d3	20527	@{ */
sahilmgandhi	18:6a4db94011d3	20528
sahilmgandhi	18:6a4db94011d3	20529	#define QEI_CNT_VAL_Pos (0) /!< QEI CNT: VAL Position /
sahilmgandhi	18:6a4db94011d3	20530	#define QEI_CNT_VAL_Msk (0xfffffffful << QEI_CNT_VAL_Pos) /!< QEI CNT: VAL Mask /
sahilmgandhi	18:6a4db94011d3	20531
sahilmgandhi	18:6a4db94011d3	20532	#define QEI_CNTHOLD_VAL_Pos (0) /!< QEI CNTHOLD: VAL Position /
sahilmgandhi	18:6a4db94011d3	20533	#define QEI_CNTHOLD_VAL_Msk (0xfffffffful << QEI_CNTHOLD_VAL_Pos) /!< QEI CNTHOLD: VAL Mask /
sahilmgandhi	18:6a4db94011d3	20534
sahilmgandhi	18:6a4db94011d3	20535	#define QEI_CNTLATCH_VAL_Pos (0) /!< QEI CNTLATCH: VAL Position /
sahilmgandhi	18:6a4db94011d3	20536	#define QEI_CNTLATCH_VAL_Msk (0xfffffffful << QEI_CNTLATCH_VAL_Pos) /!< QEI CNTLATCH: VAL Mask /
sahilmgandhi	18:6a4db94011d3	20537
sahilmgandhi	18:6a4db94011d3	20538	#define QEI_CNTCMP_VAL_Pos (0) /!< QEI CNTCMP: VAL Position /
sahilmgandhi	18:6a4db94011d3	20539	#define QEI_CNTCMP_VAL_Msk (0xfffffffful << QEI_CNTCMP_VAL_Pos) /!< QEI CNTCMP: VAL Mask /
sahilmgandhi	18:6a4db94011d3	20540
sahilmgandhi	18:6a4db94011d3	20541	#define QEI_CNTMAX_VAL_Pos (0) /!< QEI CNTMAX: VAL Position /
sahilmgandhi	18:6a4db94011d3	20542	#define QEI_CNTMAX_VAL_Msk (0xfffffffful << QEI_CNTMAX_VAL_Pos) /!< QEI CNTMAX: VAL Mask /
sahilmgandhi	18:6a4db94011d3	20543
sahilmgandhi	18:6a4db94011d3	20544	#define QEI_CTR_NFCLKSEL_Pos (0) /!< QEI CTR: NFCLKSEL Position /
sahilmgandhi	18:6a4db94011d3	20545	#define QEI_CTR_NFCLKSEL_Msk (0x3ul << QEI_CTR_NFCLKSEL_Pos) /!< QEI CTR: NFCLKSEL Mask /
sahilmgandhi	18:6a4db94011d3	20546
sahilmgandhi	18:6a4db94011d3	20547	#define QEI_CTR_NFDIS_Pos (3) /!< QEI CTR: NFDIS Position /
sahilmgandhi	18:6a4db94011d3	20548	#define QEI_CTR_NFDIS_Msk (0x1ul << QEI_CTR_NFDIS_Pos) /!< QEI CTR: NFDIS Mask /
sahilmgandhi	18:6a4db94011d3	20549
sahilmgandhi	18:6a4db94011d3	20550	#define QEI_CTR_CHAEN_Pos (4) /!< QEI CTR: CHAEN Position /
sahilmgandhi	18:6a4db94011d3	20551	#define QEI_CTR_CHAEN_Msk (0x1ul << QEI_CTR_CHAEN_Pos) /!< QEI CTR: CHAEN Mask /
sahilmgandhi	18:6a4db94011d3	20552
sahilmgandhi	18:6a4db94011d3	20553	#define QEI_CTR_CHBEN_Pos (5) /!< QEI CTR: CHBEN Position /
sahilmgandhi	18:6a4db94011d3	20554	#define QEI_CTR_CHBEN_Msk (0x1ul << QEI_CTR_CHBEN_Pos) /!< QEI CTR: CHBEN Mask /
sahilmgandhi	18:6a4db94011d3	20555
sahilmgandhi	18:6a4db94011d3	20556	#define QEI_CTR_IDXEN_Pos (6) /!< QEI CTR: IDXEN Position /
sahilmgandhi	18:6a4db94011d3	20557	#define QEI_CTR_IDXEN_Msk (0x1ul << QEI_CTR_IDXEN_Pos) /!< QEI CTR: IDXEN Mask /
sahilmgandhi	18:6a4db94011d3	20558
sahilmgandhi	18:6a4db94011d3	20559	#define QEI_CTR_MODE_Pos (8) /!< QEI CTR: MODE Position /
sahilmgandhi	18:6a4db94011d3	20560	#define QEI_CTR_MODE_Msk (0x3ul << QEI_CTR_MODE_Pos) /!< QEI CTR: MODE Mask /
sahilmgandhi	18:6a4db94011d3	20561
sahilmgandhi	18:6a4db94011d3	20562	#define QEI_CTR_CHAINV_Pos (12) /!< QEI CTR: CHAINV Position /
sahilmgandhi	18:6a4db94011d3	20563	#define QEI_CTR_CHAINV_Msk (0x1ul << QEI_CTR_CHAINV_Pos) /!< QEI CTR: CHAINV Mask /
sahilmgandhi	18:6a4db94011d3	20564
sahilmgandhi	18:6a4db94011d3	20565	#define QEI_CTR_CHBINV_Pos (13) /!< QEI CTR: CHBINV Position /
sahilmgandhi	18:6a4db94011d3	20566	#define QEI_CTR_CHBINV_Msk (0x1ul << QEI_CTR_CHBINV_Pos) /!< QEI CTR: CHBINV Mask /
sahilmgandhi	18:6a4db94011d3	20567
sahilmgandhi	18:6a4db94011d3	20568	#define QEI_CTR_IDXINV_Pos (14) /!< QEI CTR: IDXINV Position /
sahilmgandhi	18:6a4db94011d3	20569	#define QEI_CTR_IDXINV_Msk (0x1ul << QEI_CTR_IDXINV_Pos) /!< QEI CTR: IDXINV Mask /
sahilmgandhi	18:6a4db94011d3	20570
sahilmgandhi	18:6a4db94011d3	20571	#define QEI_CTR_OVUNIEN_Pos (16) /!< QEI CTR: OVUNIEN Position /
sahilmgandhi	18:6a4db94011d3	20572	#define QEI_CTR_OVUNIEN_Msk (0x1ul << QEI_CTR_OVUNIEN_Pos) /!< QEI CTR: OVUNIEN Mask /
sahilmgandhi	18:6a4db94011d3	20573
sahilmgandhi	18:6a4db94011d3	20574	#define QEI_CTR_DIRIEN_Pos (17) /!< QEI CTR: DIRIEN Position /
sahilmgandhi	18:6a4db94011d3	20575	#define QEI_CTR_DIRIEN_Msk (0x1ul << QEI_CTR_DIRIEN_Pos) /!< QEI CTR: DIRIEN Mask /
sahilmgandhi	18:6a4db94011d3	20576
sahilmgandhi	18:6a4db94011d3	20577	#define QEI_CTR_CMPIEN_Pos (18) /!< QEI CTR: CMPIEN Position /
sahilmgandhi	18:6a4db94011d3	20578	#define QEI_CTR_CMPIEN_Msk (0x1ul << QEI_CTR_CMPIEN_Pos) /!< QEI CTR: CMPIEN Mask /
sahilmgandhi	18:6a4db94011d3	20579
sahilmgandhi	18:6a4db94011d3	20580	#define QEI_CTR_IDXIEN_Pos (19) /!< QEI CTR: IDXIEN Position /
sahilmgandhi	18:6a4db94011d3	20581	#define QEI_CTR_IDXIEN_Msk (0x1ul << QEI_CTR_IDXIEN_Pos) /!< QEI CTR: IDXIEN Mask /
sahilmgandhi	18:6a4db94011d3	20582
sahilmgandhi	18:6a4db94011d3	20583	#define QEI_CTR_HOLDTMR0_Pos (20) /!< QEI CTR: HOLDTMR0 Position /
sahilmgandhi	18:6a4db94011d3	20584	#define QEI_CTR_HOLDTMR0_Msk (0x1ul << QEI_CTR_HOLDTMR0_Pos) /!< QEI CTR: HOLDTMR0 Mask /
sahilmgandhi	18:6a4db94011d3	20585
sahilmgandhi	18:6a4db94011d3	20586	#define QEI_CTR_HOLDTMR1_Pos (21) /!< QEI CTR: HOLDTMR1 Position /
sahilmgandhi	18:6a4db94011d3	20587	#define QEI_CTR_HOLDTMR1_Msk (0x1ul << QEI_CTR_HOLDTMR1_Pos) /!< QEI CTR: HOLDTMR1 Mask /
sahilmgandhi	18:6a4db94011d3	20588
sahilmgandhi	18:6a4db94011d3	20589	#define QEI_CTR_HOLDTMR2_Pos (22) /!< QEI CTR: HOLDTMR2 Position /
sahilmgandhi	18:6a4db94011d3	20590	#define QEI_CTR_HOLDTMR2_Msk (0x1ul << QEI_CTR_HOLDTMR2_Pos) /!< QEI CTR: HOLDTMR2 Mask /
sahilmgandhi	18:6a4db94011d3	20591
sahilmgandhi	18:6a4db94011d3	20592	#define QEI_CTR_HOLDTMR3_Pos (23) /!< QEI CTR: HOLDTMR3 Position /
sahilmgandhi	18:6a4db94011d3	20593	#define QEI_CTR_HOLDTMR3_Msk (0x1ul << QEI_CTR_HOLDTMR3_Pos) /!< QEI CTR: HOLDTMR3 Mask /
sahilmgandhi	18:6a4db94011d3	20594
sahilmgandhi	18:6a4db94011d3	20595	#define QEI_CTR_HOLDCNT_Pos (24) /!< QEI CTR: HOLDCNT Position /
sahilmgandhi	18:6a4db94011d3	20596	#define QEI_CTR_HOLDCNT_Msk (0x1ul << QEI_CTR_HOLDCNT_Pos) /!< QEI CTR: HOLDCNT Mask /
sahilmgandhi	18:6a4db94011d3	20597
sahilmgandhi	18:6a4db94011d3	20598	#define QEI_CTR_IDXLATEN_Pos (25) /!< QEI CTR: IDXLATEN Position /
sahilmgandhi	18:6a4db94011d3	20599	#define QEI_CTR_IDXLATEN_Msk (0x1ul << QEI_CTR_IDXLATEN_Pos) /!< QEI CTR: IDXLATEN Mask /
sahilmgandhi	18:6a4db94011d3	20600
sahilmgandhi	18:6a4db94011d3	20601	#define QEI_CTR_IDXRLDEN_Pos (27) /!< QEI CTR: IDXRLDEN Position /
sahilmgandhi	18:6a4db94011d3	20602	#define QEI_CTR_IDXRLDEN_Msk (0x1ul << QEI_CTR_IDXRLDEN_Pos) /!< QEI CTR: IDXRLDEN Mask /
sahilmgandhi	18:6a4db94011d3	20603
sahilmgandhi	18:6a4db94011d3	20604	#define QEI_CTR_CMPENN_Pos (28) /!< QEI CTR: CMPENN Position /
sahilmgandhi	18:6a4db94011d3	20605	#define QEI_CTR_CMPENN_Msk (0x1ul << QEI_CTR_CMPENN_Pos) /!< QEI CTR: CMPENN Mask /
sahilmgandhi	18:6a4db94011d3	20606
sahilmgandhi	18:6a4db94011d3	20607	#define QEI_CTR_QEIEN_Pos (29) /!< QEI CTR: QEIEN Position /
sahilmgandhi	18:6a4db94011d3	20608	#define QEI_CTR_QEIEN_Msk (0x1ul << QEI_CTR_QEIEN_Pos) /!< QEI CTR: QEIEN Mask /
sahilmgandhi	18:6a4db94011d3	20609
sahilmgandhi	18:6a4db94011d3	20610	#define QEI_STATUS_IDXF_Pos (0) /!< QEI STATUS: IDXF Position /
sahilmgandhi	18:6a4db94011d3	20611	#define QEI_STATUS_IDXF_Msk (0x1ul << QEI_STATUS_IDXF_Pos) /!< QEI STATUS: IDXF Mask /
sahilmgandhi	18:6a4db94011d3	20612
sahilmgandhi	18:6a4db94011d3	20613	#define QEI_STATUS_CMPF_Pos (1) /!< QEI STATUS: CMPF Position /
sahilmgandhi	18:6a4db94011d3	20614	#define QEI_STATUS_CMPF_Msk (0x1ul << QEI_STATUS_CMPF_Pos) /!< QEI STATUS: CMPF Mask /
sahilmgandhi	18:6a4db94011d3	20615
sahilmgandhi	18:6a4db94011d3	20616	#define QEI_STATUS_OVUNF_Pos (2) /!< QEI STATUS: OVUNF Position /
sahilmgandhi	18:6a4db94011d3	20617	#define QEI_STATUS_OVUNF_Msk (0x1ul << QEI_STATUS_OVUNF_Pos) /!< QEI STATUS: OVUNF Mask /
sahilmgandhi	18:6a4db94011d3	20618
sahilmgandhi	18:6a4db94011d3	20619	#define QEI_STATUS_DIRCHGF_Pos (3) /!< QEI STATUS: DIRCHGF Position /
sahilmgandhi	18:6a4db94011d3	20620	#define QEI_STATUS_DIRCHGF_Msk (0x1ul << QEI_STATUS_DIRCHGF_Pos) /!< QEI STATUS: DIRCHGF Mask /
sahilmgandhi	18:6a4db94011d3	20621
sahilmgandhi	18:6a4db94011d3	20622	#define QEI_STATUS_DIRF_Pos (8) /!< QEI STATUS: DIRF Position /
sahilmgandhi	18:6a4db94011d3	20623	#define QEI_STATUS_DIRF_Msk (0x1ul << QEI_STATUS_DIRF_Pos) /!< QEI STATUS: DIRF Mask /
sahilmgandhi	18:6a4db94011d3	20624
sahilmgandhi	18:6a4db94011d3	20625	/*@}/ /* QEI_CONST */
sahilmgandhi	18:6a4db94011d3	20626	/*@}/ /* end of QEI register group */
sahilmgandhi	18:6a4db94011d3	20627
sahilmgandhi	18:6a4db94011d3	20628
sahilmgandhi	18:6a4db94011d3	20629	/---------------------- Real Time Clock Controller -------------------------/
sahilmgandhi	18:6a4db94011d3	20630	/**
sahilmgandhi	18:6a4db94011d3	20631	@addtogroup RTC Real Time Clock Controller(RTC)
sahilmgandhi	18:6a4db94011d3	20632	Memory Mapped Structure for RTC Controller
sahilmgandhi	18:6a4db94011d3	20633	@{ */
sahilmgandhi	18:6a4db94011d3	20634
sahilmgandhi	18:6a4db94011d3	20635	typedef struct {
sahilmgandhi	18:6a4db94011d3	20636
sahilmgandhi	18:6a4db94011d3	20637	/**
sahilmgandhi	18:6a4db94011d3	20638	* INIT
sahilmgandhi	18:6a4db94011d3	20639	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	20640	* Offset: 0x00 RTC Initiation Register
sahilmgandhi	18:6a4db94011d3	20641	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	20642	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	20643	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	20644	* \|[0] \|INIT_Active\|RTC Active Status (Read Only)
sahilmgandhi	18:6a4db94011d3	20645	* \| \| \|0 = RTC is at reset state.
sahilmgandhi	18:6a4db94011d3	20646	* \| \| \|1 = RTC is at normal active state.
sahilmgandhi	18:6a4db94011d3	20647	* \|[1:31] \|INIT \|RTC Initiation
sahilmgandhi	18:6a4db94011d3	20648	* \| \| \|When RTC block is powered on, RTC is at reset state.
sahilmgandhi	18:6a4db94011d3	20649	* \| \| \|User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state.
sahilmgandhi	18:6a4db94011d3	20650	* \| \| \|Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
sahilmgandhi	18:6a4db94011d3	20651	* \| \| \|The INIT is a write-only field and read value will be always "0".
sahilmgandhi	18:6a4db94011d3	20652	*/
sahilmgandhi	18:6a4db94011d3	20653	__IO uint32_t INIT;
sahilmgandhi	18:6a4db94011d3	20654
sahilmgandhi	18:6a4db94011d3	20655	/**
sahilmgandhi	18:6a4db94011d3	20656	* RWEN
sahilmgandhi	18:6a4db94011d3	20657	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	20658	* Offset: 0x04 RTC Access Enable Register
sahilmgandhi	18:6a4db94011d3	20659	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	20660	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	20661	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	20662	* \|[0:15] \|RWEN \|RTC Register Access Enable Password (Write Only)
sahilmgandhi	18:6a4db94011d3	20663	* \| \| \|Writing 0xA965 to this register will enable RTC access and keep 1024 RTC clock.
sahilmgandhi	18:6a4db94011d3	20664	* \|[16] \|RWENF \|RTC Register Access Enable Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	20665	* \| \| \|0 = RTC register read/write Disabled.
sahilmgandhi	18:6a4db94011d3	20666	* \| \| \|1 = RTC register read/write Enabled.
sahilmgandhi	18:6a4db94011d3	20667	* \| \| \|This bit will be set after RTC_RWEN[15:0] register is load a 0xA965, and be cleared automatically after 1024 RTC clock.
sahilmgandhi	18:6a4db94011d3	20668	*/
sahilmgandhi	18:6a4db94011d3	20669	__O uint32_t RWEN;
sahilmgandhi	18:6a4db94011d3	20670
sahilmgandhi	18:6a4db94011d3	20671	/**
sahilmgandhi	18:6a4db94011d3	20672	* FREQADJ
sahilmgandhi	18:6a4db94011d3	20673	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	20674	* Offset: 0x08 RTC Frequency Compensation Register
sahilmgandhi	18:6a4db94011d3	20675	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	20676	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	20677	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	20678	* \|[0:5] \|FRACTION \|Fraction Part
sahilmgandhi	18:6a4db94011d3	20679	* \| \| \|Formula = (fraction part of detected value) x 60.
sahilmgandhi	18:6a4db94011d3	20680	* \| \| \|Note: Digit in RTC_FREQADJ must be expressed as hexadecimal number.
sahilmgandhi	18:6a4db94011d3	20681	* \|[8:11] \|INTEGER \|Integer Part
sahilmgandhi	18:6a4db94011d3	20682	*/
sahilmgandhi	18:6a4db94011d3	20683	__IO uint32_t FREQADJ;
sahilmgandhi	18:6a4db94011d3	20684
sahilmgandhi	18:6a4db94011d3	20685	/**
sahilmgandhi	18:6a4db94011d3	20686	* TIME
sahilmgandhi	18:6a4db94011d3	20687	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	20688	* Offset: 0x0C Time Loading Register
sahilmgandhi	18:6a4db94011d3	20689	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	20690	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	20691	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	20692	* \|[0:3] \|SEC \|1-Sec Time Digit (0~9)
sahilmgandhi	18:6a4db94011d3	20693	* \|[4:6] \|TENSEC \|10-Sec Time Digit (0~5)
sahilmgandhi	18:6a4db94011d3	20694	* \|[8:11] \|MIN \|1-Min Time Digit (0~9)
sahilmgandhi	18:6a4db94011d3	20695	* \|[12:14] \|TENMIN \|10-Min Time Digit (0~5)
sahilmgandhi	18:6a4db94011d3	20696	* \|[16:19] \|HR \|1-Hour Time Digit (0~9)
sahilmgandhi	18:6a4db94011d3	20697	* \|[20:21] \|TENHR \|10-Hour Time Digit (0~2)
sahilmgandhi	18:6a4db94011d3	20698	*/
sahilmgandhi	18:6a4db94011d3	20699	__IO uint32_t TIME;
sahilmgandhi	18:6a4db94011d3	20700
sahilmgandhi	18:6a4db94011d3	20701	/**
sahilmgandhi	18:6a4db94011d3	20702	* CAL
sahilmgandhi	18:6a4db94011d3	20703	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	20704	* Offset: 0x10 Calendar Loading Register
sahilmgandhi	18:6a4db94011d3	20705	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	20706	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	20707	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	20708	* \|[0:3] \|DAY \|1-Day Calendar Digit (0~9)
sahilmgandhi	18:6a4db94011d3	20709	* \|[4:5] \|TENDAY \|10-Day Calendar Digit (0~3)
sahilmgandhi	18:6a4db94011d3	20710	* \|[8:11] \|MON \|1-Month Calendar Digit (0~9)
sahilmgandhi	18:6a4db94011d3	20711	* \|[12] \|TENMON \|10-Month Calendar Digit (0~1)
sahilmgandhi	18:6a4db94011d3	20712	* \|[16:19] \|YEAR \|1-Year Calendar Digit (0~9)
sahilmgandhi	18:6a4db94011d3	20713	* \|[20:23] \|TENYEAR \|10-Year Calendar Digit (0~9)
sahilmgandhi	18:6a4db94011d3	20714	*/
sahilmgandhi	18:6a4db94011d3	20715	__IO uint32_t CAL;
sahilmgandhi	18:6a4db94011d3	20716
sahilmgandhi	18:6a4db94011d3	20717	/**
sahilmgandhi	18:6a4db94011d3	20718	* CLKFMT
sahilmgandhi	18:6a4db94011d3	20719	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	20720	* Offset: 0x14 Time Scale Selection Register
sahilmgandhi	18:6a4db94011d3	20721	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	20722	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	20723	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	20724	* \|[0] \|24HEN \|24-Hour / 12-Hour Time Scale Selection
sahilmgandhi	18:6a4db94011d3	20725	* \| \| \|Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale
sahilmgandhi	18:6a4db94011d3	20726	* \| \| \|0 = 12-hour time scale with AM and PM indication selected.
sahilmgandhi	18:6a4db94011d3	20727	* \| \| \|1 = 24-hour time scale selected.
sahilmgandhi	18:6a4db94011d3	20728	*/
sahilmgandhi	18:6a4db94011d3	20729	__IO uint32_t CLKFMT;
sahilmgandhi	18:6a4db94011d3	20730
sahilmgandhi	18:6a4db94011d3	20731	/**
sahilmgandhi	18:6a4db94011d3	20732	* WEEKDAY
sahilmgandhi	18:6a4db94011d3	20733	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	20734	* Offset: 0x18 Day of the Week Register
sahilmgandhi	18:6a4db94011d3	20735	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	20736	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	20737	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	20738	* \|[0:2] \|WEEKDAY \|Day Of The Week Bits
sahilmgandhi	18:6a4db94011d3	20739	* \| \| \|000 = Sunday.
sahilmgandhi	18:6a4db94011d3	20740	* \| \| \|001 = Monday.
sahilmgandhi	18:6a4db94011d3	20741	* \| \| \|010 = Tuesday.
sahilmgandhi	18:6a4db94011d3	20742	* \| \| \|011 = Wednesday.
sahilmgandhi	18:6a4db94011d3	20743	* \| \| \|100 = Thursday.
sahilmgandhi	18:6a4db94011d3	20744	* \| \| \|101 = Friday.
sahilmgandhi	18:6a4db94011d3	20745	* \| \| \|110 = Saturday.
sahilmgandhi	18:6a4db94011d3	20746	* \| \| \|111 = Reserved
sahilmgandhi	18:6a4db94011d3	20747	*/
sahilmgandhi	18:6a4db94011d3	20748	__IO uint32_t WEEKDAY;
sahilmgandhi	18:6a4db94011d3	20749
sahilmgandhi	18:6a4db94011d3	20750	/**
sahilmgandhi	18:6a4db94011d3	20751	* TALM
sahilmgandhi	18:6a4db94011d3	20752	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	20753	* Offset: 0x1C Time Alarm Register
sahilmgandhi	18:6a4db94011d3	20754	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	20755	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	20756	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	20757	* \|[0:3] \|SEC \|1-Sec Time Digit of Alarm Setting (0~9)
sahilmgandhi	18:6a4db94011d3	20758	* \|[4:6] \|TENSEC \|10-Sec Time Digit of Alarm Setting (0~5)
sahilmgandhi	18:6a4db94011d3	20759	* \|[8:11] \|MIN \|1-Min Time Digit of Alarm Setting (0~9)
sahilmgandhi	18:6a4db94011d3	20760	* \|[12:14] \|TENMIN \|10-Min Time Digit of Alarm Setting (0~5)
sahilmgandhi	18:6a4db94011d3	20761	* \|[16:19] \|HR \|1-Hour Time Digit of Alarm Setting (0~9)
sahilmgandhi	18:6a4db94011d3	20762	* \|[20:21] \|TENHR \|10-Hour Time Digit of Alarm Setting (0~2)
sahilmgandhi	18:6a4db94011d3	20763	*/
sahilmgandhi	18:6a4db94011d3	20764	__IO uint32_t TALM;
sahilmgandhi	18:6a4db94011d3	20765
sahilmgandhi	18:6a4db94011d3	20766	/**
sahilmgandhi	18:6a4db94011d3	20767	* CALM
sahilmgandhi	18:6a4db94011d3	20768	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	20769	* Offset: 0x20 Calendar Alarm Register
sahilmgandhi	18:6a4db94011d3	20770	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	20771	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	20772	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	20773	* \|[0:3] \|DAY \|1-Day Calendar Digit of Alarm Setting (0~9)
sahilmgandhi	18:6a4db94011d3	20774	* \|[4:5] \|TENDAY \|10-Day Calendar Digit of Alarm Setting (0~3)
sahilmgandhi	18:6a4db94011d3	20775	* \|[8:11] \|MON \|1-Month Calendar Digit of Alarm Setting (0~9)
sahilmgandhi	18:6a4db94011d3	20776	* \|[12] \|TENMON \|10-Month Calendar Digit of Alarm Setting (0~1)
sahilmgandhi	18:6a4db94011d3	20777	* \|[16:19] \|YEAR \|1-Year Calendar Digit of Alarm Setting (0~9)
sahilmgandhi	18:6a4db94011d3	20778	* \|[20:23] \|TENYEAR \|10-Year Calendar Digit of Alarm Setting (0~9)
sahilmgandhi	18:6a4db94011d3	20779	*/
sahilmgandhi	18:6a4db94011d3	20780	__IO uint32_t CALM;
sahilmgandhi	18:6a4db94011d3	20781
sahilmgandhi	18:6a4db94011d3	20782	/**
sahilmgandhi	18:6a4db94011d3	20783	* LEAPYEAR
sahilmgandhi	18:6a4db94011d3	20784	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	20785	* Offset: 0x24 Leap Year Indication Register
sahilmgandhi	18:6a4db94011d3	20786	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	20787	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	20788	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	20789	* \|[0] \|LEAPYEAR \|Leap Year Indicator (Read Only)
sahilmgandhi	18:6a4db94011d3	20790	* \| \| \|0 = This year is not a leap year.
sahilmgandhi	18:6a4db94011d3	20791	* \| \| \|1 = This year is leap year.
sahilmgandhi	18:6a4db94011d3	20792	*/
sahilmgandhi	18:6a4db94011d3	20793	__I uint32_t LEAPYEAR;
sahilmgandhi	18:6a4db94011d3	20794
sahilmgandhi	18:6a4db94011d3	20795	/**
sahilmgandhi	18:6a4db94011d3	20796	* INTEN
sahilmgandhi	18:6a4db94011d3	20797	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	20798	* Offset: 0x28 RTC Interrupt Enable Register
sahilmgandhi	18:6a4db94011d3	20799	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	20800	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	20801	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	20802	* \|[0] \|ALMIEN \|Alarm Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	20803	* \| \| \|0 = RTC Alarm Interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	20804	* \| \| \|1 = RTC Alarm Interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	20805	* \|[1] \|TICKIEN \|Time Tick Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	20806	* \| \| \|0 = RTC Time Tick Interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	20807	* \| \| \|1 = RTC Time Tick Interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	20808	*/
sahilmgandhi	18:6a4db94011d3	20809	__IO uint32_t INTEN;
sahilmgandhi	18:6a4db94011d3	20810
sahilmgandhi	18:6a4db94011d3	20811	/**
sahilmgandhi	18:6a4db94011d3	20812	* INTSTS
sahilmgandhi	18:6a4db94011d3	20813	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	20814	* Offset: 0x2C RTC Interrupt Indicator Register
sahilmgandhi	18:6a4db94011d3	20815	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	20816	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	20817	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	20818	* \|[0] \|ALMIF \|RTC Alarm Interrupt Flag
sahilmgandhi	18:6a4db94011d3	20819	* \| \| \|When RTC real time counters RTC_TIME and RTC_CAL reach the alarm setting time registers RTC_TALM and RTC_CALM, this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled (ALMIEN (RTC_INTEN(0)) is set to 1.
sahilmgandhi	18:6a4db94011d3	20820	* \| \| \|Chip will also be waken up if RTC Alarm Interrupt is enabled and this bit is set to 1 when chip is running at Power-down mode.
sahilmgandhi	18:6a4db94011d3	20821	* \| \| \|Note: This bit can be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	20822	* \|[1] \|TICKIF \|RTC Time Tick Interrupt Flag
sahilmgandhi	18:6a4db94011d3	20823	* \| \| \|When RTC Time Tick happened, this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled (TICKIEN (RTC_INTEN[1])) is set to 1.
sahilmgandhi	18:6a4db94011d3	20824	* \| \| \|Chip will also be waken up if RTC Tick Interrupt is enabled and this bit is set to 1 when chip is running at Power-down mode.
sahilmgandhi	18:6a4db94011d3	20825	* \| \| \|Note: This bit can be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	20826	*/
sahilmgandhi	18:6a4db94011d3	20827	__IO uint32_t INTSTS;
sahilmgandhi	18:6a4db94011d3	20828
sahilmgandhi	18:6a4db94011d3	20829	/**
sahilmgandhi	18:6a4db94011d3	20830	* TICK
sahilmgandhi	18:6a4db94011d3	20831	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	20832	* Offset: 0x30 RTC Time Tick Register
sahilmgandhi	18:6a4db94011d3	20833	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	20834	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	20835	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	20836	* \|[0:2] \|TICKSEL \|Time Tick Bits
sahilmgandhi	18:6a4db94011d3	20837	* \| \| \|The RTC time tick period for Periodic Time Tick Interrupt request.
sahilmgandhi	18:6a4db94011d3	20838	* \| \| \|000 = Time tick is 1 second.
sahilmgandhi	18:6a4db94011d3	20839	* \| \| \|001 = Time tick is 1/2 second.
sahilmgandhi	18:6a4db94011d3	20840	* \| \| \|010 = Time tick is 1/4 second.
sahilmgandhi	18:6a4db94011d3	20841	* \| \| \|011 = Time tick is 1/8 second.
sahilmgandhi	18:6a4db94011d3	20842	* \| \| \|100 = Time tick is 1/16 second.
sahilmgandhi	18:6a4db94011d3	20843	* \| \| \|101 = Time tick is 1/32 second.
sahilmgandhi	18:6a4db94011d3	20844	* \| \| \|110 = Time tick is 1/64 second.
sahilmgandhi	18:6a4db94011d3	20845	* \| \| \|111 = Time tick is 1/128 second.
sahilmgandhi	18:6a4db94011d3	20846	* \| \| \|Note: These bits can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active.
sahilmgandhi	18:6a4db94011d3	20847	*/
sahilmgandhi	18:6a4db94011d3	20848	__IO uint32_t TICK;
sahilmgandhi	18:6a4db94011d3	20849	uint32_t RESERVE0[2];
sahilmgandhi	18:6a4db94011d3	20850
sahilmgandhi	18:6a4db94011d3	20851
sahilmgandhi	18:6a4db94011d3	20852	/**
sahilmgandhi	18:6a4db94011d3	20853	* SPRCTL
sahilmgandhi	18:6a4db94011d3	20854	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	20855	* Offset: 0x3C RTC Spare Functional Control Register
sahilmgandhi	18:6a4db94011d3	20856	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	20857	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	20858	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	20859	* \|[2] \|SPRRWEN \|SPR Register Enable Control
sahilmgandhi	18:6a4db94011d3	20860	* \| \| \|This bit controls the spare register to be enabled or not.
sahilmgandhi	18:6a4db94011d3	20861	* \| \| \|0 = Spare register Disabled and RTC_SPR0 ~ RTC_SPR23 cannot be accessed.
sahilmgandhi	18:6a4db94011d3	20862	* \| \| \|1 = Spare register Enabled and RTC_SPR0 ~ RTC_SPR23 can be accessed.
sahilmgandhi	18:6a4db94011d3	20863	* \|[7] \|SPRRWRDY \|SPR Register Ready
sahilmgandhi	18:6a4db94011d3	20864	* \| \| \|This bit indicates if the registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR23 are ready to be accessed.
sahilmgandhi	18:6a4db94011d3	20865	* \| \| \|After CPU writing registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR23, polling this bit to check if these registers are updated done is necessary.
sahilmgandhi	18:6a4db94011d3	20866	* \| \| \|This bit is read only and any write to it won't take any effect.
sahilmgandhi	18:6a4db94011d3	20867	* \| \| \|0 = RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR23 updating is in progress.
sahilmgandhi	18:6a4db94011d3	20868	* \| \| \|1 = RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR23 are updated done and ready to be accessed.
sahilmgandhi	18:6a4db94011d3	20869	*/
sahilmgandhi	18:6a4db94011d3	20870	__IO uint32_t SPRCTL;
sahilmgandhi	18:6a4db94011d3	20871
sahilmgandhi	18:6a4db94011d3	20872	/**
sahilmgandhi	18:6a4db94011d3	20873	* SPRx
sahilmgandhi	18:6a4db94011d3	20874	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	20875	* Offset: 0x40 RTC Spare Register 0 ~ 23
sahilmgandhi	18:6a4db94011d3	20876	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	20877	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	20878	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	20879	* \|[0:31] \|SPARE \|SPARE Bits
sahilmgandhi	18:6a4db94011d3	20880	* \| \| \|This field is used to store back-up information defined by software.
sahilmgandhi	18:6a4db94011d3	20881	* \| \| \|This field will be cleared by hardware automatically once a snooper pin event is detected.
sahilmgandhi	18:6a4db94011d3	20882	* \| \| \|Before storing back-up information in to SPARE register, software should write 0xA965 to RTC_RWEN to make sure register read/write enabled.
sahilmgandhi	18:6a4db94011d3	20883	*/
sahilmgandhi	18:6a4db94011d3	20884	__IO uint32_t SPR[24];
sahilmgandhi	18:6a4db94011d3	20885	uint32_t RESERVE1[28];
sahilmgandhi	18:6a4db94011d3	20886
sahilmgandhi	18:6a4db94011d3	20887
sahilmgandhi	18:6a4db94011d3	20888	/**
sahilmgandhi	18:6a4db94011d3	20889	* TAMPCTL
sahilmgandhi	18:6a4db94011d3	20890	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	20891	* Offset: 0x110 Tamper Control Register
sahilmgandhi	18:6a4db94011d3	20892	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	20893	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	20894	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	20895	* \|[0] \|TIEN \|Tamper Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	20896	* \| \| \|0 = Tamper interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	20897	* \| \| \|1 = Tamper interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	20898	* \|[1] \|DESTROYEN \|Destroy Spare Register Enable Control
sahilmgandhi	18:6a4db94011d3	20899	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	20900	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	20901	* \|[2] \|TAMPEN0 \|Tamper0 Detect Enable Control
sahilmgandhi	18:6a4db94011d3	20902	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	20903	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	20904	* \|[3] \|TAMPEN1 \|Tamper1 Detect Enable Control
sahilmgandhi	18:6a4db94011d3	20905	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	20906	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	20907	* \|[4] \|TAMPDBEN0 \|Tamper0 De-Bounce Enable Control
sahilmgandhi	18:6a4db94011d3	20908	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	20909	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	20910	* \|[5] \|TAMPDBEN1 \|Tamper1 De-Bounce Enable Control
sahilmgandhi	18:6a4db94011d3	20911	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	20912	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	20913	* \|[6] \|TAMPLV0 \|Tamper0 Level
sahilmgandhi	18:6a4db94011d3	20914	* \| \| \|0 = Low.
sahilmgandhi	18:6a4db94011d3	20915	* \| \| \|1 = High.
sahilmgandhi	18:6a4db94011d3	20916	* \|[7] \|TAMPLV1 \|Tamper1 Level
sahilmgandhi	18:6a4db94011d3	20917	* \| \| \|0 = Low.
sahilmgandhi	18:6a4db94011d3	20918	* \| \| \|1 = High.
sahilmgandhi	18:6a4db94011d3	20919	*/
sahilmgandhi	18:6a4db94011d3	20920	__IO uint32_t TAMPCTL;
sahilmgandhi	18:6a4db94011d3	20921
sahilmgandhi	18:6a4db94011d3	20922	/**
sahilmgandhi	18:6a4db94011d3	20923	* TAMPSTS
sahilmgandhi	18:6a4db94011d3	20924	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	20925	* Offset: 0x114 Tamper Status Register
sahilmgandhi	18:6a4db94011d3	20926	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	20927	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	20928	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	20929	* \|[0] \|TAMPSTS0 \|Tamper0 Sense Flag
sahilmgandhi	18:6a4db94011d3	20930	* \| \| \|0 = No invasion.
sahilmgandhi	18:6a4db94011d3	20931	* \| \| \|1 = Tamper0 detect invasion.
sahilmgandhi	18:6a4db94011d3	20932	* \| \| \|Note: Write 1 to clear it
sahilmgandhi	18:6a4db94011d3	20933	* \|[1] \|TAMPSTS1 \|Tamper1 Sense Flag
sahilmgandhi	18:6a4db94011d3	20934	* \| \| \|0 = No invasion.
sahilmgandhi	18:6a4db94011d3	20935	* \| \| \|1 = Tamper1 detect invasion.
sahilmgandhi	18:6a4db94011d3	20936	* \| \| \|Note: Write 1 to clear it
sahilmgandhi	18:6a4db94011d3	20937	*/
sahilmgandhi	18:6a4db94011d3	20938	__IO uint32_t TAMPSTS;
sahilmgandhi	18:6a4db94011d3	20939	uint32_t RESERVE2[3];
sahilmgandhi	18:6a4db94011d3	20940
sahilmgandhi	18:6a4db94011d3	20941
sahilmgandhi	18:6a4db94011d3	20942	/**
sahilmgandhi	18:6a4db94011d3	20943	* TAMP0PCTL
sahilmgandhi	18:6a4db94011d3	20944	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	20945	* Offset: 0x124 TAMPER0 Pin I/O Mode Control
sahilmgandhi	18:6a4db94011d3	20946	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	20947	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	20948	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	20949	* \|[0] \|OUTLV \|Output Level
sahilmgandhi	18:6a4db94011d3	20950	* \| \| \|0 = Low.
sahilmgandhi	18:6a4db94011d3	20951	* \| \| \|1 = High.
sahilmgandhi	18:6a4db94011d3	20952	* \|[1] \|OUTEN \|Output Enable Control
sahilmgandhi	18:6a4db94011d3	20953	* \| \| \|0 = Output Enabled.
sahilmgandhi	18:6a4db94011d3	20954	* \| \| \|1 = Output Disabled.
sahilmgandhi	18:6a4db94011d3	20955	* \|[2] \|TRIEN \|Tri-State
sahilmgandhi	18:6a4db94011d3	20956	* \| \| \|0 = Tri-state Disabled.
sahilmgandhi	18:6a4db94011d3	20957	* \| \| \|1 = Tri-state Enabled.
sahilmgandhi	18:6a4db94011d3	20958	* \|[3] \|TYPE \|Type
sahilmgandhi	18:6a4db94011d3	20959	* \| \| \|0 = Input Schmitt Trigger function Disabled.
sahilmgandhi	18:6a4db94011d3	20960	* \| \| \|1 = Input Schmitt Trigger function Enabled.
sahilmgandhi	18:6a4db94011d3	20961	* \|[4] \|DINOFF \|Off Digital
sahilmgandhi	18:6a4db94011d3	20962	* \| \| \|0 = Off digital Disabled.
sahilmgandhi	18:6a4db94011d3	20963	* \| \| \|1 = Off digital Enabled.
sahilmgandhi	18:6a4db94011d3	20964	*/
sahilmgandhi	18:6a4db94011d3	20965	__IO uint32_t TAMP0PCTL;
sahilmgandhi	18:6a4db94011d3	20966
sahilmgandhi	18:6a4db94011d3	20967	/**
sahilmgandhi	18:6a4db94011d3	20968	* TAMP1PCTL
sahilmgandhi	18:6a4db94011d3	20969	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	20970	* Offset: 0x128 TAMPER1 Pin I/O Mode Control
sahilmgandhi	18:6a4db94011d3	20971	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	20972	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	20973	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	20974	* \|[0] \|OUTLV \|Output Level
sahilmgandhi	18:6a4db94011d3	20975	* \| \| \|0 = Low.
sahilmgandhi	18:6a4db94011d3	20976	* \| \| \|1 = High.
sahilmgandhi	18:6a4db94011d3	20977	* \|[1] \|OUTEN \|Output Enable Control
sahilmgandhi	18:6a4db94011d3	20978	* \| \| \|0 = Output Enabled.
sahilmgandhi	18:6a4db94011d3	20979	* \| \| \|1 = Output Disabled.
sahilmgandhi	18:6a4db94011d3	20980	* \|[2] \|TRIEN \|Tri-State
sahilmgandhi	18:6a4db94011d3	20981	* \| \| \|0 = Tri-state Disabled.
sahilmgandhi	18:6a4db94011d3	20982	* \| \| \|1 = Tri-state Enabled.
sahilmgandhi	18:6a4db94011d3	20983	* \|[3] \|TYPE \|Type
sahilmgandhi	18:6a4db94011d3	20984	* \| \| \|0 = Input Schmitt Trigger function Disabled.
sahilmgandhi	18:6a4db94011d3	20985	* \| \| \|1 = Input Schmitt Trigger function Enabled.
sahilmgandhi	18:6a4db94011d3	20986	* \|[4] \|DINOFF \|Off Digital
sahilmgandhi	18:6a4db94011d3	20987	* \| \| \|0 = Off digital Disabled.
sahilmgandhi	18:6a4db94011d3	20988	* \| \| \|1 = Off digital Enabled.
sahilmgandhi	18:6a4db94011d3	20989	*/
sahilmgandhi	18:6a4db94011d3	20990	__IO uint32_t TAMP1PCTL;
sahilmgandhi	18:6a4db94011d3	20991
sahilmgandhi	18:6a4db94011d3	20992	/**
sahilmgandhi	18:6a4db94011d3	20993	* LXTIPCTL
sahilmgandhi	18:6a4db94011d3	20994	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	20995	* Offset: 0x12C 32K Input Pin I/O Mode Control
sahilmgandhi	18:6a4db94011d3	20996	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	20997	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	20998	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	20999	* \|[0] \|OUTLV \|Output Level
sahilmgandhi	18:6a4db94011d3	21000	* \| \| \|0 = Low.
sahilmgandhi	18:6a4db94011d3	21001	* \| \| \|1 = High.
sahilmgandhi	18:6a4db94011d3	21002	* \|[1] \|OUTEN \|Output Enable Control
sahilmgandhi	18:6a4db94011d3	21003	* \| \| \|0 = Output Enabled.
sahilmgandhi	18:6a4db94011d3	21004	* \| \| \|1 = Output Disabled.
sahilmgandhi	18:6a4db94011d3	21005	* \|[2] \|TRIEN \|Tri-State
sahilmgandhi	18:6a4db94011d3	21006	* \| \| \|0 = Tri-state Disabled.
sahilmgandhi	18:6a4db94011d3	21007	* \| \| \|1 = Tri-state Enabled.
sahilmgandhi	18:6a4db94011d3	21008	* \|[3] \|TYPE \|Type
sahilmgandhi	18:6a4db94011d3	21009	* \| \| \|0 = Input Schmitt Trigger function Disabled.
sahilmgandhi	18:6a4db94011d3	21010	* \| \| \|1 = Input Schmitt Trigger function Enabled.
sahilmgandhi	18:6a4db94011d3	21011	* \|[4] \|DINOFF \|Off Digital
sahilmgandhi	18:6a4db94011d3	21012	* \| \| \|0 = Off digital Disabled.
sahilmgandhi	18:6a4db94011d3	21013	* \| \| \|1 = Off digital Enabled.
sahilmgandhi	18:6a4db94011d3	21014	*/
sahilmgandhi	18:6a4db94011d3	21015	__IO uint32_t LXTIPCTL;
sahilmgandhi	18:6a4db94011d3	21016
sahilmgandhi	18:6a4db94011d3	21017	/**
sahilmgandhi	18:6a4db94011d3	21018	* LXTOPCTL
sahilmgandhi	18:6a4db94011d3	21019	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	21020	* Offset: 0x130 32K Output Pin I/O Mode Control
sahilmgandhi	18:6a4db94011d3	21021	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	21022	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	21023	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	21024	* \|[0] \|OUTLV \|Output Level
sahilmgandhi	18:6a4db94011d3	21025	* \| \| \|0 = Low.
sahilmgandhi	18:6a4db94011d3	21026	* \| \| \|1 = High.
sahilmgandhi	18:6a4db94011d3	21027	* \|[1] \|OUTEN \|Output Enable Control
sahilmgandhi	18:6a4db94011d3	21028	* \| \| \|0 = Output Enabled.
sahilmgandhi	18:6a4db94011d3	21029	* \| \| \|1 = Output Disabled.
sahilmgandhi	18:6a4db94011d3	21030	* \|[2] \|TRIEN \|Tri-State
sahilmgandhi	18:6a4db94011d3	21031	* \| \| \|0 = Tri-state Disabled.
sahilmgandhi	18:6a4db94011d3	21032	* \| \| \|1 = Tri-state Enabled.
sahilmgandhi	18:6a4db94011d3	21033	* \|[3] \|TYPE \|Type
sahilmgandhi	18:6a4db94011d3	21034	* \| \| \|0 = Input Schmitt Trigger function Disabled.
sahilmgandhi	18:6a4db94011d3	21035	* \| \| \|1 = Input Schmitt Trigger function Enabled.
sahilmgandhi	18:6a4db94011d3	21036	* \|[4] \|DINOFF \|Off Digital
sahilmgandhi	18:6a4db94011d3	21037	* \| \| \|0 = Off digital Disabled.
sahilmgandhi	18:6a4db94011d3	21038	* \| \| \|1 = Off digital Enabled.
sahilmgandhi	18:6a4db94011d3	21039	*/
sahilmgandhi	18:6a4db94011d3	21040	__IO uint32_t LXTOPCTL;
sahilmgandhi	18:6a4db94011d3	21041	uint32_t RESERVE3[3];
sahilmgandhi	18:6a4db94011d3	21042
sahilmgandhi	18:6a4db94011d3	21043
sahilmgandhi	18:6a4db94011d3	21044	/**
sahilmgandhi	18:6a4db94011d3	21045	* TAMSK
sahilmgandhi	18:6a4db94011d3	21046	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	21047	* Offset: 0x140 Time Alarm MASK Register
sahilmgandhi	18:6a4db94011d3	21048	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	21049	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	21050	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	21051	* \|[0] \|MSEC \|Mask 1-Sec Time Digit of Alarm Setting (0~9)
sahilmgandhi	18:6a4db94011d3	21052	* \|[1] \|MTENSEC \|Mask 10-Sec Time Digit of Alarm Setting (0~5)
sahilmgandhi	18:6a4db94011d3	21053	* \|[2] \|MMIN \|Mask 1-Min Time Digit of Alarm Setting (0~9)
sahilmgandhi	18:6a4db94011d3	21054	* \|[3] \|MTENMIN \|Mask 10-Min Time Digit of Alarm Setting (0~5)
sahilmgandhi	18:6a4db94011d3	21055	* \|[4] \|MHR \|Mask 1-Hour Time Digit of Alarm Setting (0~9)
sahilmgandhi	18:6a4db94011d3	21056	* \|[5] \|MTENHR \|Mask 10-Hour Time Digit of Alarm Setting (0~2)
sahilmgandhi	18:6a4db94011d3	21057	*/
sahilmgandhi	18:6a4db94011d3	21058	__IO uint32_t TAMSK;
sahilmgandhi	18:6a4db94011d3	21059
sahilmgandhi	18:6a4db94011d3	21060	/**
sahilmgandhi	18:6a4db94011d3	21061	* CAMSK
sahilmgandhi	18:6a4db94011d3	21062	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	21063	* Offset: 0x144 Calendar Alarm MASK Register
sahilmgandhi	18:6a4db94011d3	21064	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	21065	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	21066	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	21067	* \|[0] \|MDAY \|Mask 1-Day Calendar Digit of Alarm Setting (0~9)
sahilmgandhi	18:6a4db94011d3	21068	* \|[1] \|MTENDAY \|Mask 10-Day Calendar Digit of Alarm Setting (0~3)
sahilmgandhi	18:6a4db94011d3	21069	* \|[2] \|MMON \|Mask 1-Month Calendar Digit of Alarm Setting (0~9)
sahilmgandhi	18:6a4db94011d3	21070	* \|[3] \|MTENMON \|Mask 10-Month Calendar Digit of Alarm Setting (0~1)
sahilmgandhi	18:6a4db94011d3	21071	* \|[4] \|MYEAR \|Mask 1-Year Calendar Digit of Alarm Setting (0~9)
sahilmgandhi	18:6a4db94011d3	21072	* \|[5] \|MTENYEAR \|Mask 10-Year Calendar Digit of Alarm Setting (0~9)
sahilmgandhi	18:6a4db94011d3	21073	*/
sahilmgandhi	18:6a4db94011d3	21074	__IO uint32_t CAMSK;
sahilmgandhi	18:6a4db94011d3	21075
sahilmgandhi	18:6a4db94011d3	21076	} RTC_T;
sahilmgandhi	18:6a4db94011d3	21077
sahilmgandhi	18:6a4db94011d3	21078	/**
sahilmgandhi	18:6a4db94011d3	21079	@addtogroup RTC_CONST RTC Bit Field Definition
sahilmgandhi	18:6a4db94011d3	21080	Constant Definitions for RTC Controller
sahilmgandhi	18:6a4db94011d3	21081	@{ */
sahilmgandhi	18:6a4db94011d3	21082
sahilmgandhi	18:6a4db94011d3	21083	#define RTC_INIT_INIT_Active_Pos (0) /!< RTC INIT: INIT_Active Position /
sahilmgandhi	18:6a4db94011d3	21084	#define RTC_INIT_INIT_Active_Msk (0x1ul << RTC_INIT_INIT_Active_Pos) /!< RTC INIT: INIT_Active Mask /
sahilmgandhi	18:6a4db94011d3	21085
sahilmgandhi	18:6a4db94011d3	21086	#define RTC_INIT_INIT_Pos (1) /!< RTC INIT: INIT Position /
sahilmgandhi	18:6a4db94011d3	21087	#define RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos) /!< RTC INIT: INIT Mask /
sahilmgandhi	18:6a4db94011d3	21088
sahilmgandhi	18:6a4db94011d3	21089	#define RTC_RWEN_RWEN_Pos (0) /!< RTC RWEN: RWEN Position /
sahilmgandhi	18:6a4db94011d3	21090	#define RTC_RWEN_RWEN_Msk (0xfffful << RTC_RWEN_RWEN_Pos) /!< RTC RWEN: RWEN Mask /
sahilmgandhi	18:6a4db94011d3	21091
sahilmgandhi	18:6a4db94011d3	21092	#define RTC_RWEN_RWENF_Pos (16) /!< RTC RWEN: RWENF Position /
sahilmgandhi	18:6a4db94011d3	21093	#define RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos) /!< RTC RWEN: RWENF Mask /
sahilmgandhi	18:6a4db94011d3	21094
sahilmgandhi	18:6a4db94011d3	21095	#define RTC_FREQADJ_FRACTION_Pos (0) /!< RTC FREQADJ: FRACTION Position /
sahilmgandhi	18:6a4db94011d3	21096	#define RTC_FREQADJ_FRACTION_Msk (0x3ful << RTC_FREQADJ_FRACTION_Pos) /!< RTC FREQADJ: FRACTION Mask /
sahilmgandhi	18:6a4db94011d3	21097
sahilmgandhi	18:6a4db94011d3	21098	#define RTC_FREQADJ_INTEGER_Pos (8) /!< RTC FREQADJ: INTEGER Position /
sahilmgandhi	18:6a4db94011d3	21099	#define RTC_FREQADJ_INTEGER_Msk (0xful << RTC_FREQADJ_INTEGER_Pos) /!< RTC FREQADJ: INTEGER Mask /
sahilmgandhi	18:6a4db94011d3	21100
sahilmgandhi	18:6a4db94011d3	21101	#define RTC_TIME_SEC_Pos (0) /!< RTC TIME: SEC Position /
sahilmgandhi	18:6a4db94011d3	21102	#define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /!< RTC TIME: SEC Mask /
sahilmgandhi	18:6a4db94011d3	21103
sahilmgandhi	18:6a4db94011d3	21104	#define RTC_TIME_TENSEC_Pos (4) /!< RTC TIME: TENSEC Position /
sahilmgandhi	18:6a4db94011d3	21105	#define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /!< RTC TIME: TENSEC Mask /
sahilmgandhi	18:6a4db94011d3	21106
sahilmgandhi	18:6a4db94011d3	21107	#define RTC_TIME_MIN_Pos (8) /!< RTC TIME: MIN Position /
sahilmgandhi	18:6a4db94011d3	21108	#define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /!< RTC TIME: MIN Mask /
sahilmgandhi	18:6a4db94011d3	21109
sahilmgandhi	18:6a4db94011d3	21110	#define RTC_TIME_TENMIN_Pos (12) /!< RTC TIME: TENMIN Position /
sahilmgandhi	18:6a4db94011d3	21111	#define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /!< RTC TIME: TENMIN Mask /
sahilmgandhi	18:6a4db94011d3	21112
sahilmgandhi	18:6a4db94011d3	21113	#define RTC_TIME_HR_Pos (16) /!< RTC TIME: HR Position /
sahilmgandhi	18:6a4db94011d3	21114	#define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /!< RTC TIME: HR Mask /
sahilmgandhi	18:6a4db94011d3	21115
sahilmgandhi	18:6a4db94011d3	21116	#define RTC_TIME_TENHR_Pos (20) /!< RTC TIME: TENHR Position /
sahilmgandhi	18:6a4db94011d3	21117	#define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /!< RTC TIME: TENHR Mask /
sahilmgandhi	18:6a4db94011d3	21118
sahilmgandhi	18:6a4db94011d3	21119	#define RTC_CAL_DAY_Pos (0) /!< RTC CAL: DAY Position /
sahilmgandhi	18:6a4db94011d3	21120	#define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /!< RTC CAL: DAY Mask /
sahilmgandhi	18:6a4db94011d3	21121
sahilmgandhi	18:6a4db94011d3	21122	#define RTC_CAL_TENDAY_Pos (4) /!< RTC CAL: TENDAY Position /
sahilmgandhi	18:6a4db94011d3	21123	#define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /!< RTC CAL: TENDAY Mask /
sahilmgandhi	18:6a4db94011d3	21124
sahilmgandhi	18:6a4db94011d3	21125	#define RTC_CAL_MON_Pos (8) /!< RTC CAL: MON Position /
sahilmgandhi	18:6a4db94011d3	21126	#define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /!< RTC CAL: MON Mask /
sahilmgandhi	18:6a4db94011d3	21127
sahilmgandhi	18:6a4db94011d3	21128	#define RTC_CAL_TENMON_Pos (12) /!< RTC CAL: TENMON Position /
sahilmgandhi	18:6a4db94011d3	21129	#define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /!< RTC CAL: TENMON Mask /
sahilmgandhi	18:6a4db94011d3	21130
sahilmgandhi	18:6a4db94011d3	21131	#define RTC_CAL_YEAR_Pos (16) /!< RTC CAL: YEAR Position /
sahilmgandhi	18:6a4db94011d3	21132	#define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /!< RTC CAL: YEAR Mask /
sahilmgandhi	18:6a4db94011d3	21133
sahilmgandhi	18:6a4db94011d3	21134	#define RTC_CAL_TENYEAR_Pos (20) /!< RTC CAL: TENYEAR Position /
sahilmgandhi	18:6a4db94011d3	21135	#define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /!< RTC CAL: TENYEAR Mask /
sahilmgandhi	18:6a4db94011d3	21136
sahilmgandhi	18:6a4db94011d3	21137	#define RTC_CLKFMT_24HEN_Pos (0) /!< RTC CLKFMT: 24HEN Position /
sahilmgandhi	18:6a4db94011d3	21138	#define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /!< RTC CLKFMT: 24HEN Mask /
sahilmgandhi	18:6a4db94011d3	21139
sahilmgandhi	18:6a4db94011d3	21140	#define RTC_WEEKDAY_WEEKDAY_Pos (0) /!< RTC WEEKDAY: WEEKDAY Position /
sahilmgandhi	18:6a4db94011d3	21141	#define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /!< RTC WEEKDAY: WEEKDAY Mask /
sahilmgandhi	18:6a4db94011d3	21142
sahilmgandhi	18:6a4db94011d3	21143	#define RTC_TALM_SEC_Pos (0) /!< RTC TALM: SEC Position /
sahilmgandhi	18:6a4db94011d3	21144	#define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /!< RTC TALM: SEC Mask /
sahilmgandhi	18:6a4db94011d3	21145
sahilmgandhi	18:6a4db94011d3	21146	#define RTC_TALM_TENSEC_Pos (4) /!< RTC TALM: TENSEC Position /
sahilmgandhi	18:6a4db94011d3	21147	#define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /!< RTC TALM: TENSEC Mask /
sahilmgandhi	18:6a4db94011d3	21148
sahilmgandhi	18:6a4db94011d3	21149	#define RTC_TALM_MIN_Pos (8) /!< RTC TALM: MIN Position /
sahilmgandhi	18:6a4db94011d3	21150	#define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /!< RTC TALM: MIN Mask /
sahilmgandhi	18:6a4db94011d3	21151
sahilmgandhi	18:6a4db94011d3	21152	#define RTC_TALM_TENMIN_Pos (12) /!< RTC TALM: TENMIN Position /
sahilmgandhi	18:6a4db94011d3	21153	#define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /!< RTC TALM: TENMIN Mask /
sahilmgandhi	18:6a4db94011d3	21154
sahilmgandhi	18:6a4db94011d3	21155	#define RTC_TALM_HR_Pos (16) /!< RTC TALM: HR Position /
sahilmgandhi	18:6a4db94011d3	21156	#define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /!< RTC TALM: HR Mask /
sahilmgandhi	18:6a4db94011d3	21157
sahilmgandhi	18:6a4db94011d3	21158	#define RTC_TALM_TENHR_Pos (20) /!< RTC TALM: TENHR Position /
sahilmgandhi	18:6a4db94011d3	21159	#define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /!< RTC TALM: TENHR Mask /
sahilmgandhi	18:6a4db94011d3	21160
sahilmgandhi	18:6a4db94011d3	21161	#define RTC_CALM_DAY_Pos (0) /!< RTC CALM: DAY Position /
sahilmgandhi	18:6a4db94011d3	21162	#define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /!< RTC CALM: DAY Mask /
sahilmgandhi	18:6a4db94011d3	21163
sahilmgandhi	18:6a4db94011d3	21164	#define RTC_CALM_TENDAY_Pos (4) /!< RTC CALM: TENDAY Position /
sahilmgandhi	18:6a4db94011d3	21165	#define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /!< RTC CALM: TENDAY Mask /
sahilmgandhi	18:6a4db94011d3	21166
sahilmgandhi	18:6a4db94011d3	21167	#define RTC_CALM_MON_Pos (8) /!< RTC CALM: MON Position /
sahilmgandhi	18:6a4db94011d3	21168	#define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /!< RTC CALM: MON Mask /
sahilmgandhi	18:6a4db94011d3	21169
sahilmgandhi	18:6a4db94011d3	21170	#define RTC_CALM_TENMON_Pos (12) /!< RTC CALM: TENMON Position /
sahilmgandhi	18:6a4db94011d3	21171	#define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /!< RTC CALM: TENMON Mask /
sahilmgandhi	18:6a4db94011d3	21172
sahilmgandhi	18:6a4db94011d3	21173	#define RTC_CALM_YEAR_Pos (16) /!< RTC CALM: YEAR Position /
sahilmgandhi	18:6a4db94011d3	21174	#define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /!< RTC CALM: YEAR Mask /
sahilmgandhi	18:6a4db94011d3	21175
sahilmgandhi	18:6a4db94011d3	21176	#define RTC_CALM_TENYEAR_Pos (20) /!< RTC CALM: TENYEAR Position /
sahilmgandhi	18:6a4db94011d3	21177	#define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /!< RTC CALM: TENYEAR Mask /
sahilmgandhi	18:6a4db94011d3	21178
sahilmgandhi	18:6a4db94011d3	21179	#define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /!< RTC LEAPYEAR: LEAPYEAR Position /
sahilmgandhi	18:6a4db94011d3	21180	#define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /!< RTC LEAPYEAR: LEAPYEAR Mask /
sahilmgandhi	18:6a4db94011d3	21181
sahilmgandhi	18:6a4db94011d3	21182	#define RTC_INTEN_ALMIEN_Pos (0) /!< RTC INTEN: ALMIEN Position /
sahilmgandhi	18:6a4db94011d3	21183	#define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /!< RTC INTEN: ALMIEN Mask /
sahilmgandhi	18:6a4db94011d3	21184
sahilmgandhi	18:6a4db94011d3	21185	#define RTC_INTEN_TICKIEN_Pos (1) /!< RTC INTEN: TICKIEN Position /
sahilmgandhi	18:6a4db94011d3	21186	#define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /!< RTC INTEN: TICKIEN Mask /
sahilmgandhi	18:6a4db94011d3	21187
sahilmgandhi	18:6a4db94011d3	21188	#define RTC_INTSTS_ALMIF_Pos (0) /!< RTC INTSTS: ALMIF Position /
sahilmgandhi	18:6a4db94011d3	21189	#define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /!< RTC INTSTS: ALMIF Mask /
sahilmgandhi	18:6a4db94011d3	21190
sahilmgandhi	18:6a4db94011d3	21191	#define RTC_INTSTS_TICKIF_Pos (1) /!< RTC INTSTS: TICKIF Position /
sahilmgandhi	18:6a4db94011d3	21192	#define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /!< RTC INTSTS: TICKIF Mask /
sahilmgandhi	18:6a4db94011d3	21193
sahilmgandhi	18:6a4db94011d3	21194	#define RTC_TICK_TICKSEL_Pos (0) /!< RTC TICK: TICKSEL Position /
sahilmgandhi	18:6a4db94011d3	21195	#define RTC_TICK_TICKSEL_Msk (0x7ul << RTC_TICK_TICKSEL_Pos) /!< RTC TICK: TICKSEL Mask /
sahilmgandhi	18:6a4db94011d3	21196
sahilmgandhi	18:6a4db94011d3	21197	#define RTC_SPRCTL_SPRRWEN_Pos (2) /!< RTC SPRCTL: SPRRWEN Position /
sahilmgandhi	18:6a4db94011d3	21198	#define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) /!< RTC SPRCTL: SPRRWEN Mask /
sahilmgandhi	18:6a4db94011d3	21199
sahilmgandhi	18:6a4db94011d3	21200	#define RTC_SPRCTL_SPRRWRDY_Pos (7) /!< RTC SPRCTL: SPRRWRDY Position /
sahilmgandhi	18:6a4db94011d3	21201	#define RTC_SPRCTL_SPRRWRDY_Msk (0x1ul << RTC_SPRCTL_SPRRWRDY_Pos) /!< RTC SPRCTL: SPRRWRDY Mask /
sahilmgandhi	18:6a4db94011d3	21202
sahilmgandhi	18:6a4db94011d3	21203	#define RTC_TAMPCTL_TIEN_Pos (0) /!< RTC TAMPCTL: TIEN Position /
sahilmgandhi	18:6a4db94011d3	21204	#define RTC_TAMPCTL_TIEN_Msk (0x1ul << RTC_TAMPCTL_TIEN_Pos) /!< RTC TAMPCTL: TIEN Mask /
sahilmgandhi	18:6a4db94011d3	21205
sahilmgandhi	18:6a4db94011d3	21206	#define RTC_TAMPCTL_DESTROYEN_Pos (1) /!< RTC TAMPCTL: DESTROYEN Position /
sahilmgandhi	18:6a4db94011d3	21207	#define RTC_TAMPCTL_DESTROYEN_Msk (0x1ul << RTC_TAMPCTL_DESTROYEN_Pos) /!< RTC TAMPCTL: DESTROYEN Mask /
sahilmgandhi	18:6a4db94011d3	21208
sahilmgandhi	18:6a4db94011d3	21209	#define RTC_TAMPCTL_TAMPEN0_Pos (2) /!< RTC TAMPCTL: TAMPEN0 Position /
sahilmgandhi	18:6a4db94011d3	21210	#define RTC_TAMPCTL_TAMPEN0_Msk (0x1ul << RTC_TAMPCTL_TAMPEN0_Pos) /!< RTC TAMPCTL: TAMPEN0 Mask /
sahilmgandhi	18:6a4db94011d3	21211
sahilmgandhi	18:6a4db94011d3	21212	#define RTC_TAMPCTL_TAMPEN1_Pos (3) /!< RTC TAMPCTL: TAMPEN1 Position /
sahilmgandhi	18:6a4db94011d3	21213	#define RTC_TAMPCTL_TAMPEN1_Msk (0x1ul << RTC_TAMPCTL_TAMPEN1_Pos) /!< RTC TAMPCTL: TAMPEN1 Mask /
sahilmgandhi	18:6a4db94011d3	21214
sahilmgandhi	18:6a4db94011d3	21215	#define RTC_TAMPCTL_TAMPDBEN0_Pos (4) /!< RTC TAMPCTL: TAMPDBEN0 Position /
sahilmgandhi	18:6a4db94011d3	21216	#define RTC_TAMPCTL_TAMPDBEN0_Msk (0x1ul << RTC_TAMPCTL_TAMPDBEN0_Pos) /!< RTC TAMPCTL: TAMPDBEN0 Mask /
sahilmgandhi	18:6a4db94011d3	21217
sahilmgandhi	18:6a4db94011d3	21218	#define RTC_TAMPCTL_TAMPDBEN1_Pos (5) /!< RTC TAMPCTL: TAMPDBEN1 Position /
sahilmgandhi	18:6a4db94011d3	21219	#define RTC_TAMPCTL_TAMPDBEN1_Msk (0x1ul << RTC_TAMPCTL_TAMPDBEN1_Pos) /!< RTC TAMPCTL: TAMPDBEN1 Mask /
sahilmgandhi	18:6a4db94011d3	21220
sahilmgandhi	18:6a4db94011d3	21221	#define RTC_TAMPCTL_TAMPLV0_Pos (6) /!< RTC TAMPCTL: TAMPLV0 Position /
sahilmgandhi	18:6a4db94011d3	21222	#define RTC_TAMPCTL_TAMPLV0_Msk (0x1ul << RTC_TAMPCTL_TAMPLV0_Pos) /!< RTC TAMPCTL: TAMPLV0 Mask /
sahilmgandhi	18:6a4db94011d3	21223
sahilmgandhi	18:6a4db94011d3	21224	#define RTC_TAMPCTL_TAMPLV1_Pos (7) /!< RTC TAMPCTL: TAMPLV1 Position /
sahilmgandhi	18:6a4db94011d3	21225	#define RTC_TAMPCTL_TAMPLV1_Msk (0x1ul << RTC_TAMPCTL_TAMPLV1_Pos) /!< RTC TAMPCTL: TAMPLV1 Mask /
sahilmgandhi	18:6a4db94011d3	21226
sahilmgandhi	18:6a4db94011d3	21227	#define RTC_TAMPSTS_TAMPSTS0_Pos (0) /!< RTC TAMPSTS: TAMPSTS0 Position /
sahilmgandhi	18:6a4db94011d3	21228	#define RTC_TAMPSTS_TAMPSTS0_Msk (0x1ul << RTC_TAMPSTS_TAMPSTS0_Pos) /!< RTC TAMPSTS: TAMPSTS0 Mask /
sahilmgandhi	18:6a4db94011d3	21229
sahilmgandhi	18:6a4db94011d3	21230	#define RTC_TAMPSTS_TAMPSTS1_Pos (1) /!< RTC TAMPSTS: TAMPSTS1 Position /
sahilmgandhi	18:6a4db94011d3	21231	#define RTC_TAMPSTS_TAMPSTS1_Msk (0x1ul << RTC_TAMPSTS_TAMPSTS1_Pos) /!< RTC TAMPSTS: TAMPSTS1 Mask /
sahilmgandhi	18:6a4db94011d3	21232
sahilmgandhi	18:6a4db94011d3	21233	#define RTC_TAMP0PCTL_OUTLV_Pos (0) /!< RTC TAMP0PCTL: OUTLV Position /
sahilmgandhi	18:6a4db94011d3	21234	#define RTC_TAMP0PCTL_OUTLV_Msk (0x1ul << RTC_TAMP0PCTL_OUTLV_Pos) /!< RTC TAMP0PCTL: OUTLV Mask /
sahilmgandhi	18:6a4db94011d3	21235
sahilmgandhi	18:6a4db94011d3	21236	#define RTC_TAMP0PCTL_OUTEN_Pos (1) /!< RTC TAMP0PCTL: OUTEN Position /
sahilmgandhi	18:6a4db94011d3	21237	#define RTC_TAMP0PCTL_OUTEN_Msk (0x1ul << RTC_TAMP0PCTL_OUTEN_Pos) /!< RTC TAMP0PCTL: OUTEN Mask /
sahilmgandhi	18:6a4db94011d3	21238
sahilmgandhi	18:6a4db94011d3	21239	#define RTC_TAMP0PCTL_TRIEN_Pos (2) /!< RTC TAMP0PCTL: TRIEN Position /
sahilmgandhi	18:6a4db94011d3	21240	#define RTC_TAMP0PCTL_TRIEN_Msk (0x1ul << RTC_TAMP0PCTL_TRIEN_Pos) /!< RTC TAMP0PCTL: TRIEN Mask /
sahilmgandhi	18:6a4db94011d3	21241
sahilmgandhi	18:6a4db94011d3	21242	#define RTC_TAMP0PCTL_TYPE_Pos (3) /!< RTC TAMP0PCTL: TYPE Position /
sahilmgandhi	18:6a4db94011d3	21243	#define RTC_TAMP0PCTL_TYPE_Msk (0x1ul << RTC_TAMP0PCTL_TYPE_Pos) /!< RTC TAMP0PCTL: TYPE Mask /
sahilmgandhi	18:6a4db94011d3	21244
sahilmgandhi	18:6a4db94011d3	21245	#define RTC_TAMP0PCTL_DINOFF_Pos (4) /!< RTC TAMP0PCTL: DINOFF Position /
sahilmgandhi	18:6a4db94011d3	21246	#define RTC_TAMP0PCTL_DINOFF_Msk (0x1ul << RTC_TAMP0PCTL_DINOFF_Pos) /!< RTC TAMP0PCTL: DINOFF Mask /
sahilmgandhi	18:6a4db94011d3	21247
sahilmgandhi	18:6a4db94011d3	21248	#define RTC_TAMP1PCTL_OUTLV_Pos (0) /!< RTC TAMP1PCTL: OUTLV Position /
sahilmgandhi	18:6a4db94011d3	21249	#define RTC_TAMP1PCTL_OUTLV_Msk (0x1ul << RTC_TAMP1PCTL_OUTLV_Pos) /!< RTC TAMP1PCTL: OUTLV Mask /
sahilmgandhi	18:6a4db94011d3	21250
sahilmgandhi	18:6a4db94011d3	21251	#define RTC_TAMP1PCTL_OUTEN_Pos (1) /!< RTC TAMP1PCTL: OUTEN Position /
sahilmgandhi	18:6a4db94011d3	21252	#define RTC_TAMP1PCTL_OUTEN_Msk (0x1ul << RTC_TAMP1PCTL_OUTEN_Pos) /!< RTC TAMP1PCTL: OUTEN Mask /
sahilmgandhi	18:6a4db94011d3	21253
sahilmgandhi	18:6a4db94011d3	21254	#define RTC_TAMP1PCTL_TRIEN_Pos (2) /!< RTC TAMP1PCTL: TRIEN Position /
sahilmgandhi	18:6a4db94011d3	21255	#define RTC_TAMP1PCTL_TRIEN_Msk (0x1ul << RTC_TAMP1PCTL_TRIEN_Pos) /!< RTC TAMP1PCTL: TRIEN Mask /
sahilmgandhi	18:6a4db94011d3	21256
sahilmgandhi	18:6a4db94011d3	21257	#define RTC_TAMP1PCTL_TYPE_Pos (3) /!< RTC TAMP1PCTL: TYPE Position /
sahilmgandhi	18:6a4db94011d3	21258	#define RTC_TAMP1PCTL_TYPE_Msk (0x1ul << RTC_TAMP1PCTL_TYPE_Pos) /!< RTC TAMP1PCTL: TYPE Mask /
sahilmgandhi	18:6a4db94011d3	21259
sahilmgandhi	18:6a4db94011d3	21260	#define RTC_TAMP1PCTL_DINOFF_Pos (4) /!< RTC TAMP1PCTL: DINOFF Position /
sahilmgandhi	18:6a4db94011d3	21261	#define RTC_TAMP1PCTL_DINOFF_Msk (0x1ul << RTC_TAMP1PCTL_DINOFF_Pos) /!< RTC TAMP1PCTL: DINOFF Mask /
sahilmgandhi	18:6a4db94011d3	21262
sahilmgandhi	18:6a4db94011d3	21263	#define RTC_LXTIPCTL_OUTLV_Pos (0) /!< RTC LXTIPCTL: OUTLV Position /
sahilmgandhi	18:6a4db94011d3	21264	#define RTC_LXTIPCTL_OUTLV_Msk (0x1ul << RTC_LXTIPCTL_OUTLV_Pos) /!< RTC LXTIPCTL: OUTLV Mask /
sahilmgandhi	18:6a4db94011d3	21265
sahilmgandhi	18:6a4db94011d3	21266	#define RTC_LXTIPCTL_OUTEN_Pos (1) /!< RTC LXTIPCTL: OUTEN Position /
sahilmgandhi	18:6a4db94011d3	21267	#define RTC_LXTIPCTL_OUTEN_Msk (0x1ul << RTC_LXTIPCTL_OUTEN_Pos) /!< RTC LXTIPCTL: OUTEN Mask /
sahilmgandhi	18:6a4db94011d3	21268
sahilmgandhi	18:6a4db94011d3	21269	#define RTC_LXTIPCTL_TRIEN_Pos (2) /!< RTC LXTIPCTL: TRIEN Position /
sahilmgandhi	18:6a4db94011d3	21270	#define RTC_LXTIPCTL_TRIEN_Msk (0x1ul << RTC_LXTIPCTL_TRIEN_Pos) /!< RTC LXTIPCTL: TRIEN Mask /
sahilmgandhi	18:6a4db94011d3	21271
sahilmgandhi	18:6a4db94011d3	21272	#define RTC_LXTIPCTL_TYPE_Pos (3) /!< RTC LXTIPCTL: TYPE Position /
sahilmgandhi	18:6a4db94011d3	21273	#define RTC_LXTIPCTL_TYPE_Msk (0x1ul << RTC_LXTIPCTL_TYPE_Pos) /!< RTC LXTIPCTL: TYPE Mask /
sahilmgandhi	18:6a4db94011d3	21274
sahilmgandhi	18:6a4db94011d3	21275	#define RTC_LXTIPCTL_DINOFF_Pos (4) /!< RTC LXTIPCTL: DINOFF Position /
sahilmgandhi	18:6a4db94011d3	21276	#define RTC_LXTIPCTL_DINOFF_Msk (0x1ul << RTC_LXTIPCTL_DINOFF_Pos) /!< RTC LXTIPCTL: DINOFF Mask /
sahilmgandhi	18:6a4db94011d3	21277
sahilmgandhi	18:6a4db94011d3	21278	#define RTC_LXTOPCTL_OUTLV_Pos (0) /!< RTC LXTOPCTL: OUTLV Position /
sahilmgandhi	18:6a4db94011d3	21279	#define RTC_LXTOPCTL_OUTLV_Msk (0x1ul << RTC_LXTOPCTL_OUTLV_Pos) /!< RTC LXTOPCTL: OUTLV Mask /
sahilmgandhi	18:6a4db94011d3	21280
sahilmgandhi	18:6a4db94011d3	21281	#define RTC_LXTOPCTL_OUTEN_Pos (1) /!< RTC LXTOPCTL: OUTEN Position /
sahilmgandhi	18:6a4db94011d3	21282	#define RTC_LXTOPCTL_OUTEN_Msk (0x1ul << RTC_LXTOPCTL_OUTEN_Pos) /!< RTC LXTOPCTL: OUTEN Mask /
sahilmgandhi	18:6a4db94011d3	21283
sahilmgandhi	18:6a4db94011d3	21284	#define RTC_LXTOPCTL_TRIEN_Pos (2) /!< RTC LXTOPCTL: TRIEN Position /
sahilmgandhi	18:6a4db94011d3	21285	#define RTC_LXTOPCTL_TRIEN_Msk (0x1ul << RTC_LXTOPCTL_TRIEN_Pos) /!< RTC LXTOPCTL: TRIEN Mask /
sahilmgandhi	18:6a4db94011d3	21286
sahilmgandhi	18:6a4db94011d3	21287	#define RTC_LXTOPCTL_TYPE_Pos (3) /!< RTC LXTOPCTL: TYPE Position /
sahilmgandhi	18:6a4db94011d3	21288	#define RTC_LXTOPCTL_TYPE_Msk (0x1ul << RTC_LXTOPCTL_TYPE_Pos) /!< RTC LXTOPCTL: TYPE Mask /
sahilmgandhi	18:6a4db94011d3	21289
sahilmgandhi	18:6a4db94011d3	21290	#define RTC_LXTOPCTL_DINOFF_Pos (4) /!< RTC LXTOPCTL: DINOFF Position /
sahilmgandhi	18:6a4db94011d3	21291	#define RTC_LXTOPCTL_DINOFF_Msk (0x1ul << RTC_LXTOPCTL_DINOFF_Pos) /!< RTC LXTOPCTL: DINOFF Mask /
sahilmgandhi	18:6a4db94011d3	21292
sahilmgandhi	18:6a4db94011d3	21293	#define RTC_TAMSK_MSEC_Pos (0) /!< RTC TAMSK: MSEC Position /
sahilmgandhi	18:6a4db94011d3	21294	#define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /!< RTC TAMSK: MSEC Mask /
sahilmgandhi	18:6a4db94011d3	21295
sahilmgandhi	18:6a4db94011d3	21296	#define RTC_TAMSK_MTENSEC_Pos (1) /!< RTC TAMSK: MTENSEC Position /
sahilmgandhi	18:6a4db94011d3	21297	#define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /!< RTC TAMSK: MTENSEC Mask /
sahilmgandhi	18:6a4db94011d3	21298
sahilmgandhi	18:6a4db94011d3	21299	#define RTC_TAMSK_MMIN_Pos (2) /!< RTC TAMSK: MMIN Position /
sahilmgandhi	18:6a4db94011d3	21300	#define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /!< RTC TAMSK: MMIN Mask /
sahilmgandhi	18:6a4db94011d3	21301
sahilmgandhi	18:6a4db94011d3	21302	#define RTC_TAMSK_MTENMIN_Pos (3) /!< RTC TAMSK: MTENMIN Position /
sahilmgandhi	18:6a4db94011d3	21303	#define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /!< RTC TAMSK: MTENMIN Mask /
sahilmgandhi	18:6a4db94011d3	21304
sahilmgandhi	18:6a4db94011d3	21305	#define RTC_TAMSK_MHR_Pos (4) /!< RTC TAMSK: MHR Position /
sahilmgandhi	18:6a4db94011d3	21306	#define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /!< RTC TAMSK: MHR Mask /
sahilmgandhi	18:6a4db94011d3	21307
sahilmgandhi	18:6a4db94011d3	21308	#define RTC_TAMSK_MTENHR_Pos (5) /!< RTC TAMSK: MTENHR Position /
sahilmgandhi	18:6a4db94011d3	21309	#define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /!< RTC TAMSK: MTENHR Mask /
sahilmgandhi	18:6a4db94011d3	21310
sahilmgandhi	18:6a4db94011d3	21311	#define RTC_CAMSK_MDAY_Pos (0) /!< RTC CAMSK: MDAY Position /
sahilmgandhi	18:6a4db94011d3	21312	#define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /!< RTC CAMSK: MDAY Mask /
sahilmgandhi	18:6a4db94011d3	21313
sahilmgandhi	18:6a4db94011d3	21314	#define RTC_CAMSK_MTENDAY_Pos (1) /!< RTC CAMSK: MTENDAY Position /
sahilmgandhi	18:6a4db94011d3	21315	#define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /!< RTC CAMSK: MTENDAY Mask /
sahilmgandhi	18:6a4db94011d3	21316
sahilmgandhi	18:6a4db94011d3	21317	#define RTC_CAMSK_MMON_Pos (2) /!< RTC CAMSK: MMON Position /
sahilmgandhi	18:6a4db94011d3	21318	#define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /!< RTC CAMSK: MMON Mask /
sahilmgandhi	18:6a4db94011d3	21319
sahilmgandhi	18:6a4db94011d3	21320	#define RTC_CAMSK_MTENMON_Pos (3) /!< RTC CAMSK: MTENMON Position /
sahilmgandhi	18:6a4db94011d3	21321	#define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /!< RTC CAMSK: MTENMON Mask /
sahilmgandhi	18:6a4db94011d3	21322
sahilmgandhi	18:6a4db94011d3	21323	#define RTC_CAMSK_MYEAR_Pos (4) /!< RTC CAMSK: MYEAR Position /
sahilmgandhi	18:6a4db94011d3	21324	#define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /!< RTC CAMSK: MYEAR Mask /
sahilmgandhi	18:6a4db94011d3	21325
sahilmgandhi	18:6a4db94011d3	21326	#define RTC_CAMSK_MTENYEAR_Pos (5) /!< RTC CAMSK: MTENYEAR Position /
sahilmgandhi	18:6a4db94011d3	21327	#define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /!< RTC CAMSK: MTENYEAR Mask /
sahilmgandhi	18:6a4db94011d3	21328
sahilmgandhi	18:6a4db94011d3	21329	/*@}/ /* RTC_CONST */
sahilmgandhi	18:6a4db94011d3	21330	/*@}/ /* end of RTC register group */
sahilmgandhi	18:6a4db94011d3	21331
sahilmgandhi	18:6a4db94011d3	21332
sahilmgandhi	18:6a4db94011d3	21333	/---------------------- Smart Card Host Interface Controller -------------------------/
sahilmgandhi	18:6a4db94011d3	21334	/**
sahilmgandhi	18:6a4db94011d3	21335	@addtogroup SC Smart Card Host Interface Controller(SC)
sahilmgandhi	18:6a4db94011d3	21336	Memory Mapped Structure for SC Controller
sahilmgandhi	18:6a4db94011d3	21337	@{ */
sahilmgandhi	18:6a4db94011d3	21338
sahilmgandhi	18:6a4db94011d3	21339	typedef struct {
sahilmgandhi	18:6a4db94011d3	21340
sahilmgandhi	18:6a4db94011d3	21341
sahilmgandhi	18:6a4db94011d3	21342	/**
sahilmgandhi	18:6a4db94011d3	21343	* DAT
sahilmgandhi	18:6a4db94011d3	21344	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	21345	* Offset: 0x00 SC Receive and Transmit Buffer Register
sahilmgandhi	18:6a4db94011d3	21346	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	21347	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	21348	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	21349	* \|[0:7] \|DAT \|Receiving/ Transmit Buffer
sahilmgandhi	18:6a4db94011d3	21350	* \| \| \|Write Operation:
sahilmgandhi	18:6a4db94011d3	21351	* \| \| \|By writing data to DAT, the SC will send out an 8-bit data.
sahilmgandhi	18:6a4db94011d3	21352	* \| \| \|Note: If SCEN(SC_CTL[0]) is not enabled, DAT cannot be programmed.
sahilmgandhi	18:6a4db94011d3	21353	* \| \| \|Read Operation:
sahilmgandhi	18:6a4db94011d3	21354	* \| \| \|By reading DAT, the SC will return an 8-bit received data.
sahilmgandhi	18:6a4db94011d3	21355	*/
sahilmgandhi	18:6a4db94011d3	21356	__IO uint32_t DAT;
sahilmgandhi	18:6a4db94011d3	21357
sahilmgandhi	18:6a4db94011d3	21358	/**
sahilmgandhi	18:6a4db94011d3	21359	* CTL
sahilmgandhi	18:6a4db94011d3	21360	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	21361	* Offset: 0x04 SC Control Register
sahilmgandhi	18:6a4db94011d3	21362	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	21363	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	21364	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	21365	* \|[0] \|SCEN \|SC Engine Enable Control
sahilmgandhi	18:6a4db94011d3	21366	* \| \| \|Set this bit to 1 to enable SC operation.
sahilmgandhi	18:6a4db94011d3	21367	* \| \| \|If this bit is cleared, SC will force all transition to IDLE state.
sahilmgandhi	18:6a4db94011d3	21368	* \|[1] \|RXOFF \|RX Transition Disable Control
sahilmgandhi	18:6a4db94011d3	21369	* \| \| \|0 = The receiver Enabled.
sahilmgandhi	18:6a4db94011d3	21370	* \| \| \|1 = The receiver Disabled.
sahilmgandhi	18:6a4db94011d3	21371	* \| \| \|Note: If AUTOCEN is enabled, this fields must be ignored.
sahilmgandhi	18:6a4db94011d3	21372	* \|[2] \|TXOFF \|TX Transition Disable Control
sahilmgandhi	18:6a4db94011d3	21373	* \| \| \|0 = The transceiver Enabled.
sahilmgandhi	18:6a4db94011d3	21374	* \| \| \|1 = The transceiver Disabled.
sahilmgandhi	18:6a4db94011d3	21375	* \|[3] \|AUTOCEN \|Auto Convention Enable Control
sahilmgandhi	18:6a4db94011d3	21376	* \| \| \|0 = Auto-convention Disabled.
sahilmgandhi	18:6a4db94011d3	21377	* \| \| \|1 = Auto-convention Enabled.
sahilmgandhi	18:6a4db94011d3	21378	* \| \| \|When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11.
sahilmgandhi	18:6a4db94011d3	21379	* \| \| \|If software enables auto convention function, the setting step must be done before Answer to Reset state and the first data must be 3B or 3F.
sahilmgandhi	18:6a4db94011d3	21380	* \| \| \|After hardware received first data and stored it at buffer, hardware will decided the convention and change the CONSEL (SC_CTL[5:4]) bits automatically.
sahilmgandhi	18:6a4db94011d3	21381	* \| \| \|If the first data is not 3B or 3F, hardware will generate an interrupt INT_ACON_ERR (if ACON_ERR IE (SC_INTEN[10]) = 1 to CPU.
sahilmgandhi	18:6a4db94011d3	21382	* \|[4:5] \|CONSEL \|Convention Selection
sahilmgandhi	18:6a4db94011d3	21383	* \| \| \|00 = Direct convention.
sahilmgandhi	18:6a4db94011d3	21384	* \| \| \|01 = Reserved.
sahilmgandhi	18:6a4db94011d3	21385	* \| \| \|10 = Reserved.
sahilmgandhi	18:6a4db94011d3	21386	* \| \| \|11 = Inverse convention.
sahilmgandhi	18:6a4db94011d3	21387	* \| \| \|Note: If AUTOCEN(SC_CTL[3]) enabled, this fields are ignored.
sahilmgandhi	18:6a4db94011d3	21388	* \|[6:7] \|RXTRGLV \|Rx Buffer Trigger Level
sahilmgandhi	18:6a4db94011d3	21389	* \| \| \|When the number of bytes in the receiving buffer equals the RXTRGLV, the RDA_IF will be set (if IER [RDAIENN] is enabled, an interrupt will be generated).
sahilmgandhi	18:6a4db94011d3	21390	* \| \| \|00 = INTR_RDA Trigger Level with 01 Bytes.
sahilmgandhi	18:6a4db94011d3	21391	* \| \| \|01 = INTR_RDA Trigger Level with 02 Bytes.
sahilmgandhi	18:6a4db94011d3	21392	* \| \| \|10 = INTR_RDA Trigger Level with 03 Bytees.
sahilmgandhi	18:6a4db94011d3	21393	* \| \| \|11 = Reserved.
sahilmgandhi	18:6a4db94011d3	21394	* \|[8:12] \|BGT \|Block Guard Time (BGT)
sahilmgandhi	18:6a4db94011d3	21395	* \| \| \|Block guard time means the minimum bit length between the leading edges of two consecutive characters between different transfer directions.
sahilmgandhi	18:6a4db94011d3	21396	* \| \| \|This field indicates the counter for the bit length of block guard time.
sahilmgandhi	18:6a4db94011d3	21397	* \| \| \|According to ISO7816-3, in T = 0 mode, software must fill 15 (real block guard time = 16.5) to this field; in T = 1 mode, software must fill 21 (real block guard time = 22.5) to it.
sahilmgandhi	18:6a4db94011d3	21398	* \| \| \|In RX mode, software can enable SC_ALTCTL [RXBGTEN] to detect the first coming character timing.
sahilmgandhi	18:6a4db94011d3	21399	* \| \| \|If the incoming data timing less than BGT, an interrupt will be generated.
sahilmgandhi	18:6a4db94011d3	21400	* \| \| \|Note: The real block guard time is BGT + 1.
sahilmgandhi	18:6a4db94011d3	21401	* \|[13:14] \|TMRSEL \|Timer Selection
sahilmgandhi	18:6a4db94011d3	21402	* \| \| \|00 = All internal timer function Disabled.
sahilmgandhi	18:6a4db94011d3	21403	* \| \| \|01 = Internal 24 bit timer Enabled.
sahilmgandhi	18:6a4db94011d3	21404	* \| \| \|Software can configure it by setting SC_TMRCTL0 [23:0].
sahilmgandhi	18:6a4db94011d3	21405	* \| \| \|SC_TMRCTL1 and SC_TMRCTL2 will be ignored in this mode.
sahilmgandhi	18:6a4db94011d3	21406	* \| \| \|10 = internal 24 bit timer and 8 bit internal timer Enabled.
sahilmgandhi	18:6a4db94011d3	21407	* \| \| \|Software can configure the 24 bit timer by setting SC_TMRCTL0 [23:0] and configure the 8 bit timer by setting SC_TMRCTL1[7:0].
sahilmgandhi	18:6a4db94011d3	21408	* \| \| \|SC_TMRCTL2 will be ignored in this mode.
sahilmgandhi	18:6a4db94011d3	21409	* \| \| \|11 = Internal 24 bit timer and two 8 bit timers Enabled.
sahilmgandhi	18:6a4db94011d3	21410	* \| \| \|Software can configure them by setting SC_TMRCTL0 [23:0], SC_TMRCTL1 [7:0] and SC_TMRCTL2 [7:0].
sahilmgandhi	18:6a4db94011d3	21411	* \|[15] \|NSB \|Stop Bit Length
sahilmgandhi	18:6a4db94011d3	21412	* \| \| \|This field indicates the length of stop bit.
sahilmgandhi	18:6a4db94011d3	21413	* \| \| \|0 = The stop bit length is 2 ETU.
sahilmgandhi	18:6a4db94011d3	21414	* \| \| \|1= The stop bit length is 1 ETU.
sahilmgandhi	18:6a4db94011d3	21415	* \| \| \|Note: The default stop bit length is 2. SMC and UART adopts NSB to program the stop bit length
sahilmgandhi	18:6a4db94011d3	21416	* \|[16:18] \|RXRTY \|RX Error Retry Count Number
sahilmgandhi	18:6a4db94011d3	21417	* \| \| \|This field indicates the maximum number of receiver retries that are allowed when parity error has occurred
sahilmgandhi	18:6a4db94011d3	21418	* \| \| \|Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.
sahilmgandhi	18:6a4db94011d3	21419	* \| \| \|Note2: This field cannot be changed when RXRTYEN enabled.
sahilmgandhi	18:6a4db94011d3	21420	* \| \| \|The change flow is to disable RX_ETRTRY_EN first and then fill in new retry value.
sahilmgandhi	18:6a4db94011d3	21421	* \|[19] \|RXRTYEN \|RX Error Retry Enable Control
sahilmgandhi	18:6a4db94011d3	21422	* \| \| \|This bit enables receiver retry function when parity error has occurred.
sahilmgandhi	18:6a4db94011d3	21423	* \| \| \|1 = RX error retry function Enabled.
sahilmgandhi	18:6a4db94011d3	21424	* \| \| \|0 = RX error retry function Disabled.
sahilmgandhi	18:6a4db94011d3	21425	* \| \| \|Note: Software must fill in the RXRTY value before enabling this bit.
sahilmgandhi	18:6a4db94011d3	21426	* \|[20:22] \|TXRTY \|TX Error Retry Count Number
sahilmgandhi	18:6a4db94011d3	21427	* \| \| \|This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.
sahilmgandhi	18:6a4db94011d3	21428	* \| \| \|Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.
sahilmgandhi	18:6a4db94011d3	21429	* \| \| \|Note2: This field cannot be changed when TXRTYEN enabled.
sahilmgandhi	18:6a4db94011d3	21430	* \| \| \|The change flow is to disable TX_ETRTRY_EN first and then fill in new retry value.
sahilmgandhi	18:6a4db94011d3	21431	* \|[23] \|TXRTYEN \|TX Error Retry Enable Control
sahilmgandhi	18:6a4db94011d3	21432	* \| \| \|This bit enables transmitter retry function when parity error has occurred.
sahilmgandhi	18:6a4db94011d3	21433	* \| \| \|0 = TX error retry function Disabled.
sahilmgandhi	18:6a4db94011d3	21434	* \| \| \|1 = TX error retry function Enabled.
sahilmgandhi	18:6a4db94011d3	21435	* \|[24:25] \|CDDBSEL \|Card Detect De-Bounce Selection
sahilmgandhi	18:6a4db94011d3	21436	* \| \| \|This field indicates the card detect de-bounce selection.
sahilmgandhi	18:6a4db94011d3	21437	* \| \| \|00 = De-bounce sample card insert once per 384 (128 * 3) engine clocks and de-bounce sample card removal once per 128 engine clocks.
sahilmgandhi	18:6a4db94011d3	21438	* \| \| \|01 = De-bounce sample card insert once per 192 (64 * 3) engine clocks and de-bounce sample card removal once per 64 engine clocks.
sahilmgandhi	18:6a4db94011d3	21439	* \| \| \|10 = De-bounce sample card insert once per 96 (32 * 3) engine clocks and de-bounce sample card removal once per 32 engine clocks.
sahilmgandhi	18:6a4db94011d3	21440	* \| \| \|11 = De-bounce sample card insert once per 48 (16 * 3) engine clocks and de-bounce sample card removal once per 16 engine clocks.
sahilmgandhi	18:6a4db94011d3	21441	* \|[26] \|CDLV \|Card Detect Level
sahilmgandhi	18:6a4db94011d3	21442	* \| \| \|0 = When hardware detects the card detect pin from high to low, it indicates a card is detected.
sahilmgandhi	18:6a4db94011d3	21443	* \| \| \|1 = When hardware detects the card detect pin from low to high, it indicates a card is detected.
sahilmgandhi	18:6a4db94011d3	21444	* \| \| \|Note: Software must select card detect level before Smart Card engine enabled.
sahilmgandhi	18:6a4db94011d3	21445	* \|[30] \|SYNC \|SYNC Flag Indicator
sahilmgandhi	18:6a4db94011d3	21446	* \| \| \|Due to synchronization, software should check this bit before writing a new value to RXRTY and TXRTY.
sahilmgandhi	18:6a4db94011d3	21447	* \| \| \|0 = synchronizing is completion, user can write new data to SC_PINCTL register.
sahilmgandhi	18:6a4db94011d3	21448	* \| \| \|1 = Last value is synchronizing.
sahilmgandhi	18:6a4db94011d3	21449	* \| \| \|Note: This bit is read only.
sahilmgandhi	18:6a4db94011d3	21450	*/
sahilmgandhi	18:6a4db94011d3	21451	__IO uint32_t CTL;
sahilmgandhi	18:6a4db94011d3	21452
sahilmgandhi	18:6a4db94011d3	21453	/**
sahilmgandhi	18:6a4db94011d3	21454	* ALTCTL
sahilmgandhi	18:6a4db94011d3	21455	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	21456	* Offset: 0x08 SC Alternate Control Register
sahilmgandhi	18:6a4db94011d3	21457	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	21458	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	21459	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	21460	* \|[0] \|TXRST \|TX Software Reset
sahilmgandhi	18:6a4db94011d3	21461	* \| \| \|When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.
sahilmgandhi	18:6a4db94011d3	21462	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	21463	* \| \| \|1 = Reset the TX internal state machine and pointers.
sahilmgandhi	18:6a4db94011d3	21464	* \| \| \|Note: This bit will be auto cleared after reset is complete.
sahilmgandhi	18:6a4db94011d3	21465	* \|[1] \|RXRST \|Rx Software Reset
sahilmgandhi	18:6a4db94011d3	21466	* \| \| \|When RXRST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.
sahilmgandhi	18:6a4db94011d3	21467	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	21468	* \| \| \|1 = Reset the Rx internal state machine and pointers.
sahilmgandhi	18:6a4db94011d3	21469	* \| \| \|Note: This bit will be auto cleared after reset is complete.
sahilmgandhi	18:6a4db94011d3	21470	* \|[2] \|DACTEN \|Deactivation Sequence Generator Enable Control
sahilmgandhi	18:6a4db94011d3	21471	* \| \| \|This bit enables SC controller to initiate the card by deactivation sequence
sahilmgandhi	18:6a4db94011d3	21472	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	21473	* \| \| \|1 = Deactivation sequence generator Enabled.
sahilmgandhi	18:6a4db94011d3	21474	* \| \| \|Note1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
sahilmgandhi	18:6a4db94011d3	21475	* \| \| \|Note2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
sahilmgandhi	18:6a4db94011d3	21476	* \| \| \|So don't fill this bit, TXRST, and RXRST at the same time.
sahilmgandhi	18:6a4db94011d3	21477	* \| \| \|Note3: If SC_CTL [SCEN] not enabled, this filed cannot be programmed.
sahilmgandhi	18:6a4db94011d3	21478	* \|[3] \|ACTEN \|Activation Sequence Generator Enable Control
sahilmgandhi	18:6a4db94011d3	21479	* \| \| \|This bit enables SC controller to initiate the card by activation sequence
sahilmgandhi	18:6a4db94011d3	21480	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	21481	* \| \| \|1 = Activation sequence generator Enabled.
sahilmgandhi	18:6a4db94011d3	21482	* \| \| \|Note1: When the activation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
sahilmgandhi	18:6a4db94011d3	21483	* \| \| \|Note2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
sahilmgandhi	18:6a4db94011d3	21484	* \| \| \|Note3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
sahilmgandhi	18:6a4db94011d3	21485	* \|[4] \|WARSTEN \|Warm Reset Sequence Generator Enable Control
sahilmgandhi	18:6a4db94011d3	21486	* \| \| \|This bit enables SC controller to initiate the card by warm reset sequence
sahilmgandhi	18:6a4db94011d3	21487	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	21488	* \| \| \|1 = Warm reset sequence generator Enabled.
sahilmgandhi	18:6a4db94011d3	21489	* \| \| \|Note1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
sahilmgandhi	18:6a4db94011d3	21490	* \| \| \|Note2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST, and RXRST at the same time.
sahilmgandhi	18:6a4db94011d3	21491	* \| \| \|Note3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
sahilmgandhi	18:6a4db94011d3	21492	* \|[5] \|CNTEN0 \|Internal Timer0 Start Enable Control
sahilmgandhi	18:6a4db94011d3	21493	* \| \| \|This bit enables Timer 0 to start counting.
sahilmgandhi	18:6a4db94011d3	21494	* \| \| \|Software can fill 0 to stop it and set 1 to reload and count.
sahilmgandhi	18:6a4db94011d3	21495	* \| \| \|0 = Stops counting.
sahilmgandhi	18:6a4db94011d3	21496	* \| \| \|1 = Start counting.
sahilmgandhi	18:6a4db94011d3	21497	* \| \| \|Note1: This field is used for internal 24 bit timer when TMRSEL (SC_CTL[14:13]) = 01.
sahilmgandhi	18:6a4db94011d3	21498	* \| \| \|Note2: If the operation mode is not in auto-reload mode (SC_TMRCTL0[26] = 0), this bit will be auto-cleared by hardware.
sahilmgandhi	18:6a4db94011d3	21499	* \| \| \|Note3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
sahilmgandhi	18:6a4db94011d3	21500	* \| \| \|So don't fill this bit, TXRST and RXRST at the same time.
sahilmgandhi	18:6a4db94011d3	21501	* \| \| \|Note4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
sahilmgandhi	18:6a4db94011d3	21502	* \|[6] \|CNTEN1 \|Internal Timer1 Start Enable Control
sahilmgandhi	18:6a4db94011d3	21503	* \| \| \|This bit enables Timer 1 to start counting.
sahilmgandhi	18:6a4db94011d3	21504	* \| \| \|Software can fill 0 to stop it and set 1 to reload and count.
sahilmgandhi	18:6a4db94011d3	21505	* \| \| \|0 = Stops counting.
sahilmgandhi	18:6a4db94011d3	21506	* \| \| \|1 = Start counting.
sahilmgandhi	18:6a4db94011d3	21507	* \| \| \|Note1: This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 10 or TMRSEL(SC_CTL[14:13]) = 11.
sahilmgandhi	18:6a4db94011d3	21508	* \| \| \|Don't filled CNTEN1 when SC_CTL([TMRSEL] = 00 or SC_CTL[TMRSEL] = 01.
sahilmgandhi	18:6a4db94011d3	21509	* \| \| \|Note2: If the operation mode is not in auto-reload mode (SC_TMRCTL1[26] = 0), this bit will be auto-cleared by hardware.
sahilmgandhi	18:6a4db94011d3	21510	* \| \| \|Note3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
sahilmgandhi	18:6a4db94011d3	21511	* \| \| \|Note4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
sahilmgandhi	18:6a4db94011d3	21512	* \|[7] \|CNTEN2 \|Internal Timer2 Start Enable Control
sahilmgandhi	18:6a4db94011d3	21513	* \| \| \|This bit enables Timer 2 to start counting.
sahilmgandhi	18:6a4db94011d3	21514	* \| \| \|Software can fill 0 to stop it and set 1 to reload and count.
sahilmgandhi	18:6a4db94011d3	21515	* \| \| \|0 = Stops counting.
sahilmgandhi	18:6a4db94011d3	21516	* \| \| \|1 = Start counting.
sahilmgandhi	18:6a4db94011d3	21517	* \| \| \|Note1: This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 11.
sahilmgandhi	18:6a4db94011d3	21518	* \| \| \|Don't filled CNTEN2 when TMRSEL(SC_CTL[14:13]) = 00 or TMRSEL(SC_CTL[14:13]) = 01 or TMRSEL(SC_CTL[14:13]) = 10.
sahilmgandhi	18:6a4db94011d3	21519	* \| \| \|Note2: If the operation mode is not in auto-reload mode (SC_TMRCTL2[26] = 0), this bit will be auto-cleared by hardware.
sahilmgandhi	18:6a4db94011d3	21520	* \| \| \|Note3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
sahilmgandhi	18:6a4db94011d3	21521	* \| \| \|So don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
sahilmgandhi	18:6a4db94011d3	21522	* \| \| \|Note4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
sahilmgandhi	18:6a4db94011d3	21523	* \|[8:9] \|INITSEL \|Initial Timing Selection
sahilmgandhi	18:6a4db94011d3	21524	* \| \| \|This fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).
sahilmgandhi	18:6a4db94011d3	21525	* \| \| \|Unit: SC clock
sahilmgandhi	18:6a4db94011d3	21526	* \| \| \|Activation: refer to SC Activation Sequence in Figure 5.19-4.
sahilmgandhi	18:6a4db94011d3	21527	* \| \| \|Warm-reset: refer to Warm-Reset Sequence in Figure 5.19-5
sahilmgandhi	18:6a4db94011d3	21528	* \| \| \|Deactivation: refer to Deactivation Sequence in Figure 5.19-6
sahilmgandhi	18:6a4db94011d3	21529	* \|[11] \|ADACEN \|Auto Deactivation When Card Removal
sahilmgandhi	18:6a4db94011d3	21530	* \| \| \|0 = Auto deactivation Disabled when hardware detected the card removal.
sahilmgandhi	18:6a4db94011d3	21531	* \| \| \|1 = Auto deactivation Enabled when hardware detected the card removal.
sahilmgandhi	18:6a4db94011d3	21532	* \| \| \|Note: When the card is removed, hardware will stop any process and then do deactivation sequence (if this bit is set).
sahilmgandhi	18:6a4db94011d3	21533	* \| \| \|If this process completes, hardware will generate an interrupt INT_INIT to CPU.
sahilmgandhi	18:6a4db94011d3	21534	* \|[12] \|RXBGTEN \|Receiver Block Guard Time Function Enable Control
sahilmgandhi	18:6a4db94011d3	21535	* \| \| \|0 = Receiver block guard time function Disabled.
sahilmgandhi	18:6a4db94011d3	21536	* \| \| \|1 = Receiver block guard time function Enabled.
sahilmgandhi	18:6a4db94011d3	21537	* \|[13] \|ACTSTS0 \|Internal Timer0 Active State (Read Only)
sahilmgandhi	18:6a4db94011d3	21538	* \| \| \|This bit indicates the timer counter status of timer0.
sahilmgandhi	18:6a4db94011d3	21539	* \| \| \|0 = Timer0 is not active.
sahilmgandhi	18:6a4db94011d3	21540	* \| \| \|1 = Timer0 is active.
sahilmgandhi	18:6a4db94011d3	21541	* \|[14] \|ACTSTS1 \|Internal Timer1 Active State (Read Only)
sahilmgandhi	18:6a4db94011d3	21542	* \| \| \|This bit indicates the timer counter status of timer1.
sahilmgandhi	18:6a4db94011d3	21543	* \| \| \|0 = Timer1 is not active.
sahilmgandhi	18:6a4db94011d3	21544	* \| \| \|1 = Timer1 is active.
sahilmgandhi	18:6a4db94011d3	21545	* \|[15] \|ACTSTS2 \|Internal Timer2 Active State (Read Only)
sahilmgandhi	18:6a4db94011d3	21546	* \| \| \|This bit indicates the timer counter status of timer2.
sahilmgandhi	18:6a4db94011d3	21547	* \| \| \|0 = Timer2 is not active.
sahilmgandhi	18:6a4db94011d3	21548	* \| \| \|1 = Timer2 is active.
sahilmgandhi	18:6a4db94011d3	21549	*/
sahilmgandhi	18:6a4db94011d3	21550	__IO uint32_t ALTCTL;
sahilmgandhi	18:6a4db94011d3	21551
sahilmgandhi	18:6a4db94011d3	21552	/**
sahilmgandhi	18:6a4db94011d3	21553	* EGT
sahilmgandhi	18:6a4db94011d3	21554	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	21555	* Offset: 0x0C SC Extend Guard Time Register
sahilmgandhi	18:6a4db94011d3	21556	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	21557	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	21558	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	21559	* \|[0:7] \|EGT \|Extended Guard Time
sahilmgandhi	18:6a4db94011d3	21560	* \| \| \|This field indicates the extended guard timer value.
sahilmgandhi	18:6a4db94011d3	21561	* \| \| \|Note: The counter is ETU base and the real extended guard time is EGT.
sahilmgandhi	18:6a4db94011d3	21562	*/
sahilmgandhi	18:6a4db94011d3	21563	__IO uint32_t EGT;
sahilmgandhi	18:6a4db94011d3	21564
sahilmgandhi	18:6a4db94011d3	21565	/**
sahilmgandhi	18:6a4db94011d3	21566	* RXTOUT
sahilmgandhi	18:6a4db94011d3	21567	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	21568	* Offset: 0x10 SC Receive Buffer Time-out Register
sahilmgandhi	18:6a4db94011d3	21569	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	21570	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	21571	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	21572	* \|[0:8] \|RFTM \|SC Receiver Buffer Time-Out (ETU Base)
sahilmgandhi	18:6a4db94011d3	21573	* \| \| \|The time-out counter resets and starts counting whenever the RX buffer received a new data word.
sahilmgandhi	18:6a4db94011d3	21574	* \| \| \|Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SC_DAT buffer, a receiver time-out interrupt INT_RTMR will be generated(if RXTOIF(SC_INTEN[9]) = 1 ).
sahilmgandhi	18:6a4db94011d3	21575	* \| \| \|Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5
sahilmgandhi	18:6a4db94011d3	21576	* \| \| \|Note2: Fill all 0 to this field indicates to disable this function.
sahilmgandhi	18:6a4db94011d3	21577	*/
sahilmgandhi	18:6a4db94011d3	21578	__IO uint32_t RXTOUT;
sahilmgandhi	18:6a4db94011d3	21579
sahilmgandhi	18:6a4db94011d3	21580	/**
sahilmgandhi	18:6a4db94011d3	21581	* ETUCTL
sahilmgandhi	18:6a4db94011d3	21582	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	21583	* Offset: 0x14 SC ETU Control Register
sahilmgandhi	18:6a4db94011d3	21584	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	21585	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	21586	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	21587	* \|[0:11] \|ETURDIV \|ETU Rate Divider
sahilmgandhi	18:6a4db94011d3	21588	* \| \| \|The field indicates the clock rate divider.
sahilmgandhi	18:6a4db94011d3	21589	* \| \| \|The real ETU is ETURDIV + 1.
sahilmgandhi	18:6a4db94011d3	21590	* \| \| \|Note: Software can configure this field, but this field must be greater than 0x004.
sahilmgandhi	18:6a4db94011d3	21591	* \|[15] \|CMPEN \|Compensation Mode Enable Control
sahilmgandhi	18:6a4db94011d3	21592	* \| \| \|This bit enables clock compensation function.
sahilmgandhi	18:6a4db94011d3	21593	* \| \| \|When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, where n is the value to be written into the ETURDIV .
sahilmgandhi	18:6a4db94011d3	21594	* \| \| \|0 = Compensation function Disabled.
sahilmgandhi	18:6a4db94011d3	21595	* \| \| \|1 = Compensation function Enabled.
sahilmgandhi	18:6a4db94011d3	21596	*/
sahilmgandhi	18:6a4db94011d3	21597	__IO uint32_t ETUCTL;
sahilmgandhi	18:6a4db94011d3	21598
sahilmgandhi	18:6a4db94011d3	21599	/**
sahilmgandhi	18:6a4db94011d3	21600	* INTEN
sahilmgandhi	18:6a4db94011d3	21601	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	21602	* Offset: 0x18 SC Interrupt Enable Control Register
sahilmgandhi	18:6a4db94011d3	21603	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	21604	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	21605	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	21606	* \|[0] \|RDAIEN \|Receive Data Reach Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	21607	* \| \| \|This field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt enable.
sahilmgandhi	18:6a4db94011d3	21608	* \| \| \|0 = Receive data reach trigger level interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	21609	* \| \| \|1 = Receive data reach trigger level interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	21610	* \|[1] \|TBEIEN \|Transmit Buffer Empty Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	21611	* \| \| \|This field is used for transmit buffer empty interrupt enable.
sahilmgandhi	18:6a4db94011d3	21612	* \| \| \|0 = Transmit buffer empty interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	21613	* \| \| \|1 = Transmit buffer empty interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	21614	* \|[2] \|TERRIEN \|Transfer Error Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	21615	* \| \| \|This field is used for transfer error interrupt enable.
sahilmgandhi	18:6a4db94011d3	21616	* \| \| \|The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]), receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOVER(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22] and transmitter retry over limit error TXOVERR(SC_STATUS[30].
sahilmgandhi	18:6a4db94011d3	21617	* \| \| \|0 = Transfer error interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	21618	* \| \| \|1 = Transfer error interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	21619	* \|[3] \|TMR0IEN \|Timer0 Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	21620	* \| \| \|This field is used to enable TMR0 interrupt enable.
sahilmgandhi	18:6a4db94011d3	21621	* \| \| \|0 = Timer0 interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	21622	* \| \| \|1 = Timer0 interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	21623	* \|[4] \|TMR1IEN \|Timer1 Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	21624	* \| \| \|This field is used to enable the TMR1 interrupt.
sahilmgandhi	18:6a4db94011d3	21625	* \| \| \|0 = Timer1 interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	21626	* \| \| \|1 = Timer1 interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	21627	* \|[5] \|TMR2IEN \|Timer2 Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	21628	* \| \| \|This field is used for TMR2 interrupt enable.
sahilmgandhi	18:6a4db94011d3	21629	* \| \| \|0 = Timer2 interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	21630	* \| \| \|1 = Timer2 interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	21631	* \|[6] \|BGTIEN \|Block Guard Time Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	21632	* \| \| \|This field is used for block guard time interrupt enable.
sahilmgandhi	18:6a4db94011d3	21633	* \| \| \|0 = Block guard time Disabled.
sahilmgandhi	18:6a4db94011d3	21634	* \| \| \|1 = Block guard time Enabled.
sahilmgandhi	18:6a4db94011d3	21635	* \|[7] \|CDIEN \|Card Detect Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	21636	* \| \| \|This field is used for card detect interrupt enable. The card detect status is CINSERT(SC_STATUS[12])
sahilmgandhi	18:6a4db94011d3	21637	* \| \| \|0 = Card detect interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	21638	* \| \| \|1 = Card detect interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	21639	* \|[8] \|INITIEN \|Initial End Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	21640	* \| \| \|This field is used for activation (ACTEN(SC_ALTCTL[3] = 1)), deactivation (DACTEN SC_ALTCTL[2] = 1) and warm reset (SC_ALTCTL [WARSTEN]) sequence interrupt enable.
sahilmgandhi	18:6a4db94011d3	21641	* \| \| \|0 = Initial end interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	21642	* \| \| \|1 = Initial end interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	21643	* \|[9] \|RXTOIF \|Receiver Buffer Time-Out Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	21644	* \| \| \|This field is used for receiver buffer time-out interrupt enable.
sahilmgandhi	18:6a4db94011d3	21645	* \| \| \|0 = Receiver buffer time-out interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	21646	* \| \| \|1 = Receiver buffer time-out interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	21647	* \|[10] \|ACERRIEN \|Auto Convention Error Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	21648	* \| \| \|This field is used for auto-convention error interrupt enable.
sahilmgandhi	18:6a4db94011d3	21649	* \| \| \|0 = Auto-convention error interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	21650	* \| \| \|1 = Auto-convention error interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	21651	*/
sahilmgandhi	18:6a4db94011d3	21652	__IO uint32_t INTEN;
sahilmgandhi	18:6a4db94011d3	21653
sahilmgandhi	18:6a4db94011d3	21654	/**
sahilmgandhi	18:6a4db94011d3	21655	* INTSTS
sahilmgandhi	18:6a4db94011d3	21656	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	21657	* Offset: 0x1C SC Interrupt Status Register
sahilmgandhi	18:6a4db94011d3	21658	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	21659	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	21660	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	21661	* \|[0] \|RDAIF \|Receive Data Reach Interrupt Status Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	21662	* \| \| \|This field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.
sahilmgandhi	18:6a4db94011d3	21663	* \| \| \|Note: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]).
sahilmgandhi	18:6a4db94011d3	21664	* \| \| \|If software reads data from SC_DAT and receiver buffer data byte number is less than RXTRGLV (SC_CTL[7:6]), this bit will be cleared automatically.
sahilmgandhi	18:6a4db94011d3	21665	* \|[1] \|TBEIF \|Transmit Buffer Empty Interrupt Status Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	21666	* \| \| \|This field is used for transmit buffer empty interrupt status flag.
sahilmgandhi	18:6a4db94011d3	21667	* \| \| \|Note: This field is the status flag of transmit buffer empty state.
sahilmgandhi	18:6a4db94011d3	21668	* \| \| \|If software wants to clear this bit, software must write data to SC_DAT bufferand then this bit will be cleared automatically.
sahilmgandhi	18:6a4db94011d3	21669	* \|[2] \|TERRIF \|Transfer Error Interrupt Status Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	21670	* \| \| \|This field is used for transfer error interrupt status flag.
sahilmgandhi	18:6a4db94011d3	21671	* \| \| \|The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5], parity error PEF(SC_STATUS[4] and receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOVER(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22] and transmitter retry over limit error TXOVERR(SC_SC[30]).
sahilmgandhi	18:6a4db94011d3	21672	* \| \| \|Note: This field is the status flag of BEF(SC_STATUS[6]), FEF(SC_STATUS[5], PEF(SC_STATUS[4], RXOV(SC_STATUS[0]), TXOVER(SC_STATUS[8]), RXOVERR(SC_STATUS[22] or TXOVERR(SC_SC[30]).
sahilmgandhi	18:6a4db94011d3	21673	* \| \| \|So, if software wants to clear this bit, software must write 1 to each field.
sahilmgandhi	18:6a4db94011d3	21674	* \|[3] \|TMR0IF \|Timer0 Interrupt Status Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	21675	* \| \| \|This field is used for TMR0 interrupt status flag.
sahilmgandhi	18:6a4db94011d3	21676	* \| \| \|Note: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	21677	* \|[4] \|TMR1IF \|Timer1 Interrupt Status Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	21678	* \| \| \|This field is used for TMR1 interrupt status flag.
sahilmgandhi	18:6a4db94011d3	21679	* \| \| \|Note: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	21680	* \|[5] \|TMR2IF \|Timer2 Interrupt Status Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	21681	* \| \| \|This field is used for TMR2 interrupt status flag.
sahilmgandhi	18:6a4db94011d3	21682	* \| \| \|Note: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	21683	* \|[6] \|BGTIF \|Block Guard Time Interrupt Status Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	21684	* \| \| \|This field is used for block guard time interrupt status flag.
sahilmgandhi	18:6a4db94011d3	21685	* \| \| \|Note1: This bit is valid when RXBGTEN (SC_ALTCTL[12]) is enabled.
sahilmgandhi	18:6a4db94011d3	21686	* \| \| \|Note2: This bit is read only, but it can be cleared by writing "1" to it.
sahilmgandhi	18:6a4db94011d3	21687	* \|[7] \|CDIF \|Card Detect Interrupt Status Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	21688	* \| \| \|This field is used for card detect interrupt status flag.
sahilmgandhi	18:6a4db94011d3	21689	* \| \| \|The card detect status is CINSERT (SC_STATUS[12])] and CREMOVE(SC_STATUS[11]).
sahilmgandhi	18:6a4db94011d3	21690	* \| \| \|Note: This field is the status flag of CINSERT SC_STATUS[12]) SC_PINCTL[CINSERT] or CREMOVE(SC_STATUS[11])].
sahilmgandhi	18:6a4db94011d3	21691	* \| \| \|So if software wants to clear this bit, software must write 1 to this field.
sahilmgandhi	18:6a4db94011d3	21692	* \|[8] \|INITIF \|Initial End Interrupt Status Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	21693	* \| \| \|This field is used for activation (ACTEN(SC_ALTCTL[3])), deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.
sahilmgandhi	18:6a4db94011d3	21694	* \| \| \|Note: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	21695	* \|[9] \|RBTOIF \|Receiver Buffer Time-Out Interrupt Status Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	21696	* \| \| \|This field is used for receiver buffer time-out interrupt status flag.
sahilmgandhi	18:6a4db94011d3	21697	* \| \| \|Note: This field is the status flag of receiver buffer time-out state.
sahilmgandhi	18:6a4db94011d3	21698	* \| \| \|If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_DAT buffer,.
sahilmgandhi	18:6a4db94011d3	21699	* \|[10] \|ACERRIF \|Auto Convention Error Interrupt Status Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	21700	* \| \| \|This field indicates auto convention sequence error.
sahilmgandhi	18:6a4db94011d3	21701	* \| \| \|If the received TS at ATR state is neither 3B nor 3F, this bit will be set.
sahilmgandhi	18:6a4db94011d3	21702	* \| \| \|Note: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	21703	*/
sahilmgandhi	18:6a4db94011d3	21704	__IO uint32_t INTSTS;
sahilmgandhi	18:6a4db94011d3	21705
sahilmgandhi	18:6a4db94011d3	21706	/**
sahilmgandhi	18:6a4db94011d3	21707	* STATUS
sahilmgandhi	18:6a4db94011d3	21708	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	21709	* Offset: 0x20 SC Status Register
sahilmgandhi	18:6a4db94011d3	21710	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	21711	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	21712	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	21713	* \|[0] \|RXOV \|RX Overflow Error Status Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	21714	* \| \| \|This bit is set when RX buffer overflow.
sahilmgandhi	18:6a4db94011d3	21715	* \| \| \|If the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.
sahilmgandhi	18:6a4db94011d3	21716	* \| \| \|Note: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	21717	* \|[1] \|RXEMPTY \|Receiver Buffer Empty Status Flag(Read Only)
sahilmgandhi	18:6a4db94011d3	21718	* \| \| \|This bit indicates RX buffer empty or not.
sahilmgandhi	18:6a4db94011d3	21719	* \| \| \|When the last byte of Rx buffer has been read by CPU, hardware sets this bit high.
sahilmgandhi	18:6a4db94011d3	21720	* \| \| \|It will be cleared when SC receives any new data.
sahilmgandhi	18:6a4db94011d3	21721	* \|[2] \|RXFULL \|Receiver Buffer Full Status Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	21722	* \| \| \|This bit indicates RX buffer full or not.
sahilmgandhi	18:6a4db94011d3	21723	* \| \| \|This bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
sahilmgandhi	18:6a4db94011d3	21724	* \|[4] \|PEF \|Receiver Parity Error Status Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	21725	* \| \| \|This bit is set to logic 1 whenever the received character does not have a valid
sahilmgandhi	18:6a4db94011d3	21726	* \| \| \|"parity bit".
sahilmgandhi	18:6a4db94011d3	21727	* \| \| \|Note1: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	21728	* \| \| \|Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
sahilmgandhi	18:6a4db94011d3	21729	* \|[5] \|FEF \|Receiver Frame Error Status Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	21730	* \| \| \|This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic 0).
sahilmgandhi	18:6a4db94011d3	21731	* \| \| \|Note1: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	21732	* \| \| \|Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
sahilmgandhi	18:6a4db94011d3	21733	* \|[6] \|BEF \|Receiver Break Error Status Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	21734	* \| \| \|This bit is set to a logic 1 whenever the received data input (RX) held in the "spacing state" (logic 0) is longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits).
sahilmgandhi	18:6a4db94011d3	21735	* \| \| \|.
sahilmgandhi	18:6a4db94011d3	21736	* \| \| \|Note1: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	21737	* \| \| \|Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
sahilmgandhi	18:6a4db94011d3	21738	* \|[8] \|TXOV \|TX Overflow Error Interrupt Status Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	21739	* \| \| \|If TX buffer is full, an additional write to SC_DAT will cause this bit be set to "1" by hardware.
sahilmgandhi	18:6a4db94011d3	21740	* \| \| \|Note: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	21741	* \|[9] \|TXEMPTY \|Transmit Buffer Empty Status Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	21742	* \| \| \|This bit indicates TX buffer empty or not.
sahilmgandhi	18:6a4db94011d3	21743	* \| \| \|When the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high.
sahilmgandhi	18:6a4db94011d3	21744	* \| \| \|It will be cleared when writing data into SC_DAT (TX buffer not empty).
sahilmgandhi	18:6a4db94011d3	21745	* \|[10] \|TXFULL \|Transmit Buffer Full Status Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	21746	* \| \| \|This bit indicates TX buffer full or not.
sahilmgandhi	18:6a4db94011d3	21747	* \| \| \|This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
sahilmgandhi	18:6a4db94011d3	21748	* \|[11] \|CREMOVE \|Card Detect Removal Status Of SC_CD Pin (Read Only)
sahilmgandhi	18:6a4db94011d3	21749	* \| \| \|This bit is set whenever card has been removal.
sahilmgandhi	18:6a4db94011d3	21750	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	21751	* \| \| \|1 = Card removed.
sahilmgandhi	18:6a4db94011d3	21752	* \| \| \|Note1: This bit is read only, but it can be cleared by writing "1" to it.
sahilmgandhi	18:6a4db94011d3	21753	* \| \| \|Note2: Card detect engine will start after SCEN (SC_CTL[0])set.
sahilmgandhi	18:6a4db94011d3	21754	* \|[12] \|CINSERT \|Card Detect Insert Status Of SC_CD Pin (Read Only)
sahilmgandhi	18:6a4db94011d3	21755	* \| \| \|This bit is set whenever card has been inserted.
sahilmgandhi	18:6a4db94011d3	21756	* \| \| \|0 = No effect.1 = Card insert.
sahilmgandhi	18:6a4db94011d3	21757	* \| \| \|Note1: This bit is read only, but it can be cleared by writing "1" to it.
sahilmgandhi	18:6a4db94011d3	21758	* \| \| \|Note2: The card detect engine will start after SCEN (SC_CTL[0]) set.
sahilmgandhi	18:6a4db94011d3	21759	* \|[13] \|CDPINSTS \|Card Detect Status Of SC_CD Pin Status (Read Only)
sahilmgandhi	18:6a4db94011d3	21760	* \| \| \|This bit is the pin status flag of SC_CD
sahilmgandhi	18:6a4db94011d3	21761	* \| \| \|0 = The SC_CD pin state at low.
sahilmgandhi	18:6a4db94011d3	21762	* \| \| \|1 = The SC_CD pin state at high.
sahilmgandhi	18:6a4db94011d3	21763	* \|[16:17] \|RXPOINT \|Receiver Buffer Pointer Status Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	21764	* \| \| \|This field indicates the RX buffer pointer status flag.
sahilmgandhi	18:6a4db94011d3	21765	* \| \| \|When SC receives one byte from external device, RXPOINT(SC_STATUS[17:16]) increases one.
sahilmgandhi	18:6a4db94011d3	21766	* \| \| \|When one byte of RX buffer is read by CPU, RXPOINT(SC_STATUS[17:16]) decreases one.
sahilmgandhi	18:6a4db94011d3	21767	* \|[21] \|RXRERR \|Receiver Retry Error (Read Only)
sahilmgandhi	18:6a4db94011d3	21768	* \| \| \|This bit is set by hardware when RX has any error and retries transfer.
sahilmgandhi	18:6a4db94011d3	21769	* \| \| \|Note1: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	21770	* \| \| \|Note2 This bit is a flag and cannot generate any interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	21771	* \| \| \|Note3: If CPU enables receiver retry function by setting RXRTYEN (SC_CTL[19]) , the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
sahilmgandhi	18:6a4db94011d3	21772	* \|[22] \|RXOVERR \|Receiver Over Retry Error (Read Only)
sahilmgandhi	18:6a4db94011d3	21773	* \| \| \|This bit is set by hardware when RX transfer error retry over retry number limit.
sahilmgandhi	18:6a4db94011d3	21774	* \| \| \|Note1: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	21775	* \| \| \|Note2: If CPU enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
sahilmgandhi	18:6a4db94011d3	21776	* \|[23] \|RXACT \|Receiver In Active Status Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	21777	* \| \| \|This bit is set by hardware when RX transfer is in active.
sahilmgandhi	18:6a4db94011d3	21778	* \| \| \|This bit is cleared automatically when RX transfer is finished.
sahilmgandhi	18:6a4db94011d3	21779	* \|[24:25] \|TXPOINT \|Transmit Buffer Pointer Status Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	21780	* \| \| \|This field indicates the TX buffer pointer status flag.
sahilmgandhi	18:6a4db94011d3	21781	* \| \| \|When CPU writes data into SC_DAT, TXPOINT increases one.
sahilmgandhi	18:6a4db94011d3	21782	* \| \| \|When one byte of TX Buffer is transferred to transmitter shift register, TXPOINT decreases one.
sahilmgandhi	18:6a4db94011d3	21783	* \|[29] \|TXRERR \|Transmitter Retry Error (Read Only)
sahilmgandhi	18:6a4db94011d3	21784	* \| \| \|This bit is set by hardware when transmitter re-transmits.
sahilmgandhi	18:6a4db94011d3	21785	* \| \| \|Note1: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	21786	* \| \| \|Note2 This bit is a flag and cannot generate any interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	21787	* \|[30] \|TXOVERR \|Transmitter Over Retry Error (Read Only)
sahilmgandhi	18:6a4db94011d3	21788	* \| \| \|This bit is set by hardware when transmitter re-transmits over retry number limitation.
sahilmgandhi	18:6a4db94011d3	21789	* \| \| \|Note: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	21790	* \|[31] \|TXACT \|Transmit In Active Status Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	21791	* \| \| \|0 = This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed.
sahilmgandhi	18:6a4db94011d3	21792	* \| \| \|1 = This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted.
sahilmgandhi	18:6a4db94011d3	21793	*/
sahilmgandhi	18:6a4db94011d3	21794	__IO uint32_t STATUS;
sahilmgandhi	18:6a4db94011d3	21795
sahilmgandhi	18:6a4db94011d3	21796	/**
sahilmgandhi	18:6a4db94011d3	21797	* PINCTL
sahilmgandhi	18:6a4db94011d3	21798	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	21799	* Offset: 0x24 SC Pin Control State Register
sahilmgandhi	18:6a4db94011d3	21800	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	21801	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	21802	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	21803	* \|[0] \|PWREN \|SC_PWREN Pin Signal
sahilmgandhi	18:6a4db94011d3	21804	* \| \| \|Software can set PWREN and PWRINV to decide SC_PWR pin is in high or low level.
sahilmgandhi	18:6a4db94011d3	21805	* \| \| \|Write this field to drive SC_PWR pin
sahilmgandhi	18:6a4db94011d3	21806	* \| \| \|Refer PWRINV description for programming SC_PWR pin voltage level.
sahilmgandhi	18:6a4db94011d3	21807	* \| \| \|Read this field to get SC_PWR pin status.
sahilmgandhi	18:6a4db94011d3	21808	* \| \| \|0 = SC_PWR pin status is low.
sahilmgandhi	18:6a4db94011d3	21809	* \| \| \|1 = SC_PWR pin status is high.
sahilmgandhi	18:6a4db94011d3	21810	* \| \| \|Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically.
sahilmgandhi	18:6a4db94011d3	21811	* \| \| \|So don't fill this field when operating in these modes.
sahilmgandhi	18:6a4db94011d3	21812	* \|[1] \|SCRST \|SCRST Pin Signal
sahilmgandhi	18:6a4db94011d3	21813	* \| \| \|This bit is the pin status of SCRST but user can drive SCRST pin to high or low by setting this bit.
sahilmgandhi	18:6a4db94011d3	21814	* \| \| \|Write this field to drive SCRST pin.
sahilmgandhi	18:6a4db94011d3	21815	* \| \| \|0 = Drive SCRST pin to low.
sahilmgandhi	18:6a4db94011d3	21816	* \| \| \|1 = Drive SCRST pin to high.
sahilmgandhi	18:6a4db94011d3	21817	* \| \| \|Read this
sahilmgandhi	18:6a4db94011d3	21818	* \| \| \|field to get SCRST pin status.
sahilmgandhi	18:6a4db94011d3	21819	* \| \| \|0 = SCRST pin status is low.
sahilmgandhi	18:6a4db94011d3	21820	* \| \| \|1 = SCRST pin status is high.
sahilmgandhi	18:6a4db94011d3	21821	* \| \| \|Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically.
sahilmgandhi	18:6a4db94011d3	21822	* \| \| \|So don't fill this field when operating in these modes.
sahilmgandhi	18:6a4db94011d3	21823	* \|[6] \|CLKKEEP \|SC Clock Enable Control
sahilmgandhi	18:6a4db94011d3	21824	* \| \| \|0 = SC clock generation Disabled.
sahilmgandhi	18:6a4db94011d3	21825	* \| \| \|1 = SC clock always keeps free running.
sahilmgandhi	18:6a4db94011d3	21826	* \| \| \|Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically.
sahilmgandhi	18:6a4db94011d3	21827	* \| \| \|So don't fill this field when operating in these modes.
sahilmgandhi	18:6a4db94011d3	21828	* \|[9] \|SCDOOUT \|SC Data Output Pin
sahilmgandhi	18:6a4db94011d3	21829	* \| \| \|This bit is the pin status of SCDOOUT but user can drive SCDOOUT pin to high or low by setting this bit.
sahilmgandhi	18:6a4db94011d3	21830	* \| \| \|0 = Drive SCDOOUT pin to low.
sahilmgandhi	18:6a4db94011d3	21831	* \| \| \|1 = Drive SCDOOUT pin to high.
sahilmgandhi	18:6a4db94011d3	21832	* \| \| \|Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically.
sahilmgandhi	18:6a4db94011d3	21833	* \| \| \|So don't fill this field when SC is in these modes.
sahilmgandhi	18:6a4db94011d3	21834	* \|[11] \|PWRINV \|SC_POW Pin Inverse
sahilmgandhi	18:6a4db94011d3	21835	* \| \| \|This bit is used for inverse the SC_POW pin.
sahilmgandhi	18:6a4db94011d3	21836	* \| \| \|There are four kinds of combination for SC_POW pin setting by PWRINV and PWREN(SC_PINCTL[0]).
sahilmgandhi	18:6a4db94011d3	21837	* \| \| \|PWRINV is bit 1 and PWREN is bit 0 for SC_POW_Pin as high or low voltage selection.
sahilmgandhi	18:6a4db94011d3	21838	* \| \| \|PWRINV is 0 and PWREN is 0, than SC_POW Pin output 0.
sahilmgandhi	18:6a4db94011d3	21839	* \| \| \|PWRINV is 0 and PWREN is 1, than SC_POW Pin output 1.
sahilmgandhi	18:6a4db94011d3	21840	* \| \| \|PWRINV is 1 and PWREN is 0, than SC_POW Pin output 1.
sahilmgandhi	18:6a4db94011d3	21841	* \| \| \|PWRINV is 1 and PWREN is 1, than SC_POW Pin output 0.
sahilmgandhi	18:6a4db94011d3	21842	* \| \| \|Note: Software must select PWRINV before Smart Card is enabled by SCEN (SC_CTL[0]).
sahilmgandhi	18:6a4db94011d3	21843	* \|[16] \|DATSTS \|This bit is the pin status of SC_DAT
sahilmgandhi	18:6a4db94011d3	21844	* \| \| \|0 = The SC_DAT pin is low.
sahilmgandhi	18:6a4db94011d3	21845	* \| \| \|1 = The SC_DAT pin is high.
sahilmgandhi	18:6a4db94011d3	21846	* \|[17] \|PWRSTS \|SC_PWR Pin Signal
sahilmgandhi	18:6a4db94011d3	21847	* \| \| \|This bit is the pin status of SC_PWR
sahilmgandhi	18:6a4db94011d3	21848	* \| \| \|0 = SC_PWR pin to low.
sahilmgandhi	18:6a4db94011d3	21849	* \| \| \|1 = SC_PWR pin to high.
sahilmgandhi	18:6a4db94011d3	21850	* \| \| \|Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
sahilmgandhi	18:6a4db94011d3	21851	* \| \| \|This bit is not allowed to program when SC is operated at these modes.
sahilmgandhi	18:6a4db94011d3	21852	* \|[18] \|RSTSTS \|SC_RST Pin Signals
sahilmgandhi	18:6a4db94011d3	21853	* \| \| \|This bit is the pin status of SC_RST
sahilmgandhi	18:6a4db94011d3	21854	* \| \| \|0 = SC_RST pin is low.
sahilmgandhi	18:6a4db94011d3	21855	* \| \| \|1 = SC_RST pin is high.
sahilmgandhi	18:6a4db94011d3	21856	* \| \| \|Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
sahilmgandhi	18:6a4db94011d3	21857	* \| \| \|This bit is not allowed to program when SC is operated at these modes.
sahilmgandhi	18:6a4db94011d3	21858	* \|[30] \|SYNC \|SYNC Flag Indicator
sahilmgandhi	18:6a4db94011d3	21859	* \| \| \|Due to synchronization, software should check this bit when writing a new value to SC_PINCTL register.
sahilmgandhi	18:6a4db94011d3	21860	* \| \| \|0 = Synchronizing is completion, user can write new data to SC_PINCTL register.
sahilmgandhi	18:6a4db94011d3	21861	* \| \| \|1 = Last value is synchronizing.
sahilmgandhi	18:6a4db94011d3	21862	* \| \| \|Note: This bit is read only.
sahilmgandhi	18:6a4db94011d3	21863	*/
sahilmgandhi	18:6a4db94011d3	21864	__IO uint32_t PINCTL;
sahilmgandhi	18:6a4db94011d3	21865
sahilmgandhi	18:6a4db94011d3	21866	/**
sahilmgandhi	18:6a4db94011d3	21867	* TMRCTL0
sahilmgandhi	18:6a4db94011d3	21868	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	21869	* Offset: 0x28 SC Internal Timer Control Register 0
sahilmgandhi	18:6a4db94011d3	21870	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	21871	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	21872	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	21873	* \|[0:23] \|CNT \|Timer 0 Counter Value (ETU Base)
sahilmgandhi	18:6a4db94011d3	21874	* \| \| \|This field indicates the internal timer operation values.
sahilmgandhi	18:6a4db94011d3	21875	* \|[24:27] \|OPMODE \|Timer 0 Operation Mode Selection
sahilmgandhi	18:6a4db94011d3	21876	* \| \| \|This field indicates the internal 24-bit timer operation selection.
sahilmgandhi	18:6a4db94011d3	21877	* \| \| \|Refer to 6.25.4.4 for programming Timer0.
sahilmgandhi	18:6a4db94011d3	21878	*/
sahilmgandhi	18:6a4db94011d3	21879	__IO uint32_t TMRCTL0;
sahilmgandhi	18:6a4db94011d3	21880
sahilmgandhi	18:6a4db94011d3	21881	/**
sahilmgandhi	18:6a4db94011d3	21882	* TMRCTL1
sahilmgandhi	18:6a4db94011d3	21883	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	21884	* Offset: 0x2C SC Internal Timer Control Register 1
sahilmgandhi	18:6a4db94011d3	21885	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	21886	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	21887	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	21888	* \|[0:7] \|CNT \|Timer 1 Counter Value (ETU Base)
sahilmgandhi	18:6a4db94011d3	21889	* \| \| \|This field indicates the internal timer operation values.
sahilmgandhi	18:6a4db94011d3	21890	* \|[24:27] \|OPMODE \|Timer 1 Operation Mode Selection
sahilmgandhi	18:6a4db94011d3	21891	* \| \| \|This field indicates the internal 8-bit timer operation selection.
sahilmgandhi	18:6a4db94011d3	21892	* \| \| \|Refer to 6.25.4.4 for programming Timer1.
sahilmgandhi	18:6a4db94011d3	21893	*/
sahilmgandhi	18:6a4db94011d3	21894	__IO uint32_t TMRCTL1;
sahilmgandhi	18:6a4db94011d3	21895
sahilmgandhi	18:6a4db94011d3	21896	/**
sahilmgandhi	18:6a4db94011d3	21897	* TMRCTL2
sahilmgandhi	18:6a4db94011d3	21898	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	21899	* Offset: 0x30 SC Internal Timer Control Register 2
sahilmgandhi	18:6a4db94011d3	21900	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	21901	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	21902	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	21903	* \|[0:7] \|CNT \|Timer 2 Counter Value (ETU Base)
sahilmgandhi	18:6a4db94011d3	21904	* \| \| \|This field indicates the internal timer operation values.
sahilmgandhi	18:6a4db94011d3	21905	* \|[24:27] \|OPMODE \|Timer 2 Operation Mode Selection
sahilmgandhi	18:6a4db94011d3	21906	* \| \| \|This field indicates the internal 8-bit timer operation selection
sahilmgandhi	18:6a4db94011d3	21907	* \| \| \|Refer to 6.25.4.4 for programming Timer2
sahilmgandhi	18:6a4db94011d3	21908	*/
sahilmgandhi	18:6a4db94011d3	21909	__IO uint32_t TMRCTL2;
sahilmgandhi	18:6a4db94011d3	21910
sahilmgandhi	18:6a4db94011d3	21911	/**
sahilmgandhi	18:6a4db94011d3	21912	* UARTCTL
sahilmgandhi	18:6a4db94011d3	21913	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	21914	* Offset: 0x34 SC UART Mode Control Register
sahilmgandhi	18:6a4db94011d3	21915	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	21916	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	21917	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	21918	* \|[0] \|UARTEN \|UART Mode Enable Control
sahilmgandhi	18:6a4db94011d3	21919	* \| \| \|0 = Smart Card mode.
sahilmgandhi	18:6a4db94011d3	21920	* \| \| \|1 = UART mode.
sahilmgandhi	18:6a4db94011d3	21921	* \| \| \|Note1: When operating in UART mode, user must set CONSEL (SC_CTL[5:4]) = 00 and AUTOCEN(SC_CTL[3]) = 0.
sahilmgandhi	18:6a4db94011d3	21922	* \| \| \|Note2: When operating in Smart Card mode, user must set SC_UARTCTL [7:0] = 00.
sahilmgandhi	18:6a4db94011d3	21923	* \| \| \|Note3: When UART is enabled, hardware will generate a reset to resetFIFO and internal state machine.
sahilmgandhi	18:6a4db94011d3	21924	* \|[4:5] \|WLS \|Data Length
sahilmgandhi	18:6a4db94011d3	21925	* \| \| \|00 = Character Data Length is 8 bits.
sahilmgandhi	18:6a4db94011d3	21926	* \| \| \|01 = Character Data Length is 7 bits.
sahilmgandhi	18:6a4db94011d3	21927	* \| \| \|10 = Character Data length is 6 bits.
sahilmgandhi	18:6a4db94011d3	21928	* \| \| \|11 = Character Data Length is 5 bits.
sahilmgandhi	18:6a4db94011d3	21929	* \| \| \|Note: In smart card mode, this WLS must be '00'
sahilmgandhi	18:6a4db94011d3	21930	* \|[6] \|PBOFF \|Parity Bit Disable Control
sahilmgandhi	18:6a4db94011d3	21931	* \| \| \|0 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data.
sahilmgandhi	18:6a4db94011d3	21932	* \| \| \|1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer.
sahilmgandhi	18:6a4db94011d3	21933	* \| \| \|Note: In smart card mode, this field must be '0' (default setting is with parity bit)
sahilmgandhi	18:6a4db94011d3	21934	* \|[7] \|OPE \|Odd Parity Enable Control
sahilmgandhi	18:6a4db94011d3	21935	* \| \| \|0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
sahilmgandhi	18:6a4db94011d3	21936	* \| \| \|1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
sahilmgandhi	18:6a4db94011d3	21937	* \| \| \|Note: This bit has effect only when PBOFF bit is '0'.
sahilmgandhi	18:6a4db94011d3	21938	*/
sahilmgandhi	18:6a4db94011d3	21939	__IO uint32_t UARTCTL;
sahilmgandhi	18:6a4db94011d3	21940
sahilmgandhi	18:6a4db94011d3	21941	/**
sahilmgandhi	18:6a4db94011d3	21942	* TMRDAT0
sahilmgandhi	18:6a4db94011d3	21943	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	21944	* Offset: 0x38 SC Timer 0 Current Data Register
sahilmgandhi	18:6a4db94011d3	21945	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	21946	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	21947	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	21948	* \|[0:23] \|CNT0 \|Timer0 Current Counter Value (Read Only)
sahilmgandhi	18:6a4db94011d3	21949	* \| \| \|This field indicates the current count values of timer0.
sahilmgandhi	18:6a4db94011d3	21950	*/
sahilmgandhi	18:6a4db94011d3	21951	__I uint32_t TMRDAT0;
sahilmgandhi	18:6a4db94011d3	21952
sahilmgandhi	18:6a4db94011d3	21953	/**
sahilmgandhi	18:6a4db94011d3	21954	* TMRDAT1_2
sahilmgandhi	18:6a4db94011d3	21955	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	21956	* Offset: 0x3C SC Timer 1 and 2 Current Data Register
sahilmgandhi	18:6a4db94011d3	21957	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	21958	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	21959	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	21960	* \|[0:7] \|CNT1 \|Timer1 Current Counter Value (Read Only)
sahilmgandhi	18:6a4db94011d3	21961	* \| \| \|This field indicates the current count values of timer1.
sahilmgandhi	18:6a4db94011d3	21962	* \|[8:15] \|CNT2 \|Timer2 Current Counter Value (Read Only)
sahilmgandhi	18:6a4db94011d3	21963	* \| \| \|This field indicates the current count values of timer2.
sahilmgandhi	18:6a4db94011d3	21964	*/
sahilmgandhi	18:6a4db94011d3	21965	__I uint32_t TMRDAT1_2;
sahilmgandhi	18:6a4db94011d3	21966
sahilmgandhi	18:6a4db94011d3	21967	} SC_T;
sahilmgandhi	18:6a4db94011d3	21968
sahilmgandhi	18:6a4db94011d3	21969	/**
sahilmgandhi	18:6a4db94011d3	21970	@addtogroup SC_CONST SC Bit Field Definition
sahilmgandhi	18:6a4db94011d3	21971	Constant Definitions for SC Controller
sahilmgandhi	18:6a4db94011d3	21972	@{ */
sahilmgandhi	18:6a4db94011d3	21973
sahilmgandhi	18:6a4db94011d3	21974	#define SC_DAT_DAT_Pos (0) /!< SC DAT: DAT Position /
sahilmgandhi	18:6a4db94011d3	21975	#define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) /!< SC DAT: DAT Mask /
sahilmgandhi	18:6a4db94011d3	21976
sahilmgandhi	18:6a4db94011d3	21977	#define SC_CTL_SCEN_Pos (0) /!< SC CTL: SCEN Position /
sahilmgandhi	18:6a4db94011d3	21978	#define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) /!< SC CTL: SCEN Mask /
sahilmgandhi	18:6a4db94011d3	21979
sahilmgandhi	18:6a4db94011d3	21980	#define SC_CTL_RXOFF_Pos (1) /!< SC CTL: RXOFF Position /
sahilmgandhi	18:6a4db94011d3	21981	#define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) /!< SC CTL: RXOFF Mask /
sahilmgandhi	18:6a4db94011d3	21982
sahilmgandhi	18:6a4db94011d3	21983	#define SC_CTL_TXOFF_Pos (2) /!< SC CTL: TXOFF Position /
sahilmgandhi	18:6a4db94011d3	21984	#define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) /!< SC CTL: TXOFF Mask /
sahilmgandhi	18:6a4db94011d3	21985
sahilmgandhi	18:6a4db94011d3	21986	#define SC_CTL_AUTOCEN_Pos (3) /!< SC CTL: AUTOCEN Position /
sahilmgandhi	18:6a4db94011d3	21987	#define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) /!< SC CTL: AUTOCEN Mask /
sahilmgandhi	18:6a4db94011d3	21988
sahilmgandhi	18:6a4db94011d3	21989	#define SC_CTL_CONSEL_Pos (4) /!< SC CTL: CONSEL Position /
sahilmgandhi	18:6a4db94011d3	21990	#define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) /!< SC CTL: CONSEL Mask /
sahilmgandhi	18:6a4db94011d3	21991
sahilmgandhi	18:6a4db94011d3	21992	#define SC_CTL_RXTRGLV_Pos (6) /!< SC CTL: RXTRGLV Position /
sahilmgandhi	18:6a4db94011d3	21993	#define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) /!< SC CTL: RXTRGLV Mask /
sahilmgandhi	18:6a4db94011d3	21994
sahilmgandhi	18:6a4db94011d3	21995	#define SC_CTL_BGT_Pos (8) /!< SC CTL: BGT Position /
sahilmgandhi	18:6a4db94011d3	21996	#define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) /!< SC CTL: BGT Mask /
sahilmgandhi	18:6a4db94011d3	21997
sahilmgandhi	18:6a4db94011d3	21998	#define SC_CTL_TMRSEL_Pos (13) /!< SC CTL: TMRSEL Position /
sahilmgandhi	18:6a4db94011d3	21999	#define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) /!< SC CTL: TMRSEL Mask /
sahilmgandhi	18:6a4db94011d3	22000
sahilmgandhi	18:6a4db94011d3	22001	#define SC_CTL_NSB_Pos (15) /!< SC CTL: NSB Position /
sahilmgandhi	18:6a4db94011d3	22002	#define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) /!< SC CTL: NSB Mask /
sahilmgandhi	18:6a4db94011d3	22003
sahilmgandhi	18:6a4db94011d3	22004	#define SC_CTL_RXRTY_Pos (16) /!< SC CTL: RXRTY Position /
sahilmgandhi	18:6a4db94011d3	22005	#define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) /!< SC CTL: RXRTY Mask /
sahilmgandhi	18:6a4db94011d3	22006
sahilmgandhi	18:6a4db94011d3	22007	#define SC_CTL_RXRTYEN_Pos (19) /!< SC CTL: RXRTYEN Position /
sahilmgandhi	18:6a4db94011d3	22008	#define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) /!< SC CTL: RXRTYEN Mask /
sahilmgandhi	18:6a4db94011d3	22009
sahilmgandhi	18:6a4db94011d3	22010	#define SC_CTL_TXRTY_Pos (20) /!< SC CTL: TXRTY Position /
sahilmgandhi	18:6a4db94011d3	22011	#define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) /!< SC CTL: TXRTY Mask /
sahilmgandhi	18:6a4db94011d3	22012
sahilmgandhi	18:6a4db94011d3	22013	#define SC_CTL_TXRTYEN_Pos (23) /!< SC CTL: TXRTYEN Position /
sahilmgandhi	18:6a4db94011d3	22014	#define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) /!< SC CTL: TXRTYEN Mask /
sahilmgandhi	18:6a4db94011d3	22015
sahilmgandhi	18:6a4db94011d3	22016	#define SC_CTL_CDDBSEL_Pos (24) /!< SC CTL: CDDBSEL Position /
sahilmgandhi	18:6a4db94011d3	22017	#define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) /!< SC CTL: CDDBSEL Mask /
sahilmgandhi	18:6a4db94011d3	22018
sahilmgandhi	18:6a4db94011d3	22019	#define SC_CTL_CDLV_Pos (26) /!< SC CTL: CDLV Position /
sahilmgandhi	18:6a4db94011d3	22020	#define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) /!< SC CTL: CDLV Mask /
sahilmgandhi	18:6a4db94011d3	22021
sahilmgandhi	18:6a4db94011d3	22022	#define SC_CTL_SYNC_Pos (30) /!< SC CTL: SYNC Position /
sahilmgandhi	18:6a4db94011d3	22023	#define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) /!< SC CTL: SYNC Mask /
sahilmgandhi	18:6a4db94011d3	22024
sahilmgandhi	18:6a4db94011d3	22025	#define SC_ALTCTL_TXRST_Pos (0) /!< SC ALTCTL: TXRST Position /
sahilmgandhi	18:6a4db94011d3	22026	#define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) /!< SC ALTCTL: TXRST Mask /
sahilmgandhi	18:6a4db94011d3	22027
sahilmgandhi	18:6a4db94011d3	22028	#define SC_ALTCTL_RXRST_Pos (1) /!< SC ALTCTL: RXRST Position /
sahilmgandhi	18:6a4db94011d3	22029	#define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) /!< SC ALTCTL: RXRST Mask /
sahilmgandhi	18:6a4db94011d3	22030
sahilmgandhi	18:6a4db94011d3	22031	#define SC_ALTCTL_DACTEN_Pos (2) /!< SC ALTCTL: DACTEN Position /
sahilmgandhi	18:6a4db94011d3	22032	#define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) /!< SC ALTCTL: DACTEN Mask /
sahilmgandhi	18:6a4db94011d3	22033
sahilmgandhi	18:6a4db94011d3	22034	#define SC_ALTCTL_ACTEN_Pos (3) /!< SC ALTCTL: ACTEN Position /
sahilmgandhi	18:6a4db94011d3	22035	#define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) /!< SC ALTCTL: ACTEN Mask /
sahilmgandhi	18:6a4db94011d3	22036
sahilmgandhi	18:6a4db94011d3	22037	#define SC_ALTCTL_WARSTEN_Pos (4) /!< SC ALTCTL: WARSTEN Position /
sahilmgandhi	18:6a4db94011d3	22038	#define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) /!< SC ALTCTL: WARSTEN Mask /
sahilmgandhi	18:6a4db94011d3	22039
sahilmgandhi	18:6a4db94011d3	22040	#define SC_ALTCTL_CNTEN0_Pos (5) /!< SC ALTCTL: CNTEN0 Position /
sahilmgandhi	18:6a4db94011d3	22041	#define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) /!< SC ALTCTL: CNTEN0 Mask /
sahilmgandhi	18:6a4db94011d3	22042
sahilmgandhi	18:6a4db94011d3	22043	#define SC_ALTCTL_CNTEN1_Pos (6) /!< SC ALTCTL: CNTEN1 Position /
sahilmgandhi	18:6a4db94011d3	22044	#define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) /!< SC ALTCTL: CNTEN1 Mask /
sahilmgandhi	18:6a4db94011d3	22045
sahilmgandhi	18:6a4db94011d3	22046	#define SC_ALTCTL_CNTEN2_Pos (7) /!< SC ALTCTL: CNTEN2 Position /
sahilmgandhi	18:6a4db94011d3	22047	#define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) /!< SC ALTCTL: CNTEN2 Mask /
sahilmgandhi	18:6a4db94011d3	22048
sahilmgandhi	18:6a4db94011d3	22049	#define SC_ALTCTL_INITSEL_Pos (8) /!< SC ALTCTL: INITSEL Position /
sahilmgandhi	18:6a4db94011d3	22050	#define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) /!< SC ALTCTL: INITSEL Mask /
sahilmgandhi	18:6a4db94011d3	22051
sahilmgandhi	18:6a4db94011d3	22052	#define SC_ALTCTL_ADACEN_Pos (11) /!< SC ALTCTL: ADACEN Position /
sahilmgandhi	18:6a4db94011d3	22053	#define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) /!< SC ALTCTL: ADACEN Mask /
sahilmgandhi	18:6a4db94011d3	22054
sahilmgandhi	18:6a4db94011d3	22055	#define SC_ALTCTL_RXBGTEN_Pos (12) /!< SC ALTCTL: RXBGTEN Position /
sahilmgandhi	18:6a4db94011d3	22056	#define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) /!< SC ALTCTL: RXBGTEN Mask /
sahilmgandhi	18:6a4db94011d3	22057
sahilmgandhi	18:6a4db94011d3	22058	#define SC_ALTCTL_ACTSTS0_Pos (13) /!< SC ALTCTL: ACTSTS0 Position /
sahilmgandhi	18:6a4db94011d3	22059	#define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) /!< SC ALTCTL: ACTSTS0 Mask /
sahilmgandhi	18:6a4db94011d3	22060
sahilmgandhi	18:6a4db94011d3	22061	#define SC_ALTCTL_ACTSTS1_Pos (14) /!< SC ALTCTL: ACTSTS1 Position /
sahilmgandhi	18:6a4db94011d3	22062	#define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) /!< SC ALTCTL: ACTSTS1 Mask /
sahilmgandhi	18:6a4db94011d3	22063
sahilmgandhi	18:6a4db94011d3	22064	#define SC_ALTCTL_ACTSTS2_Pos (15) /!< SC ALTCTL: ACTSTS2 Position /
sahilmgandhi	18:6a4db94011d3	22065	#define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) /!< SC ALTCTL: ACTSTS2 Mask /
sahilmgandhi	18:6a4db94011d3	22066
sahilmgandhi	18:6a4db94011d3	22067	#define SC_EGT_EGT_Pos (0) /!< SC EGT: EGT Position /
sahilmgandhi	18:6a4db94011d3	22068	#define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) /!< SC EGT: EGT Mask /
sahilmgandhi	18:6a4db94011d3	22069
sahilmgandhi	18:6a4db94011d3	22070	#define SC_RXTOUT_RFTM_Pos (0) /!< SC RXTOUT: RFTM Position /
sahilmgandhi	18:6a4db94011d3	22071	#define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) /!< SC RXTOUT: RFTM Mask /
sahilmgandhi	18:6a4db94011d3	22072
sahilmgandhi	18:6a4db94011d3	22073	#define SC_ETUCTL_ETURDIV_Pos (0) /!< SC ETUCTL: ETURDIV Position /
sahilmgandhi	18:6a4db94011d3	22074	#define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) /!< SC ETUCTL: ETURDIV Mask /
sahilmgandhi	18:6a4db94011d3	22075
sahilmgandhi	18:6a4db94011d3	22076	#define SC_ETUCTL_CMPEN_Pos (15) /!< SC ETUCTL: CMPEN Position /
sahilmgandhi	18:6a4db94011d3	22077	#define SC_ETUCTL_CMPEN_Msk (0x1ul << SC_ETUCTL_CMPEN_Pos) /!< SC ETUCTL: CMPEN Mask /
sahilmgandhi	18:6a4db94011d3	22078
sahilmgandhi	18:6a4db94011d3	22079	#define SC_INTEN_RDAIEN_Pos (0) /!< SC INTEN: RDAIEN Position /
sahilmgandhi	18:6a4db94011d3	22080	#define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) /!< SC INTEN: RDAIEN Mask /
sahilmgandhi	18:6a4db94011d3	22081
sahilmgandhi	18:6a4db94011d3	22082	#define SC_INTEN_TBEIEN_Pos (1) /!< SC INTEN: TBEIEN Position /
sahilmgandhi	18:6a4db94011d3	22083	#define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) /!< SC INTEN: TBEIEN Mask /
sahilmgandhi	18:6a4db94011d3	22084
sahilmgandhi	18:6a4db94011d3	22085	#define SC_INTEN_TERRIEN_Pos (2) /!< SC INTEN: TERRIEN Position /
sahilmgandhi	18:6a4db94011d3	22086	#define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) /!< SC INTEN: TERRIEN Mask /
sahilmgandhi	18:6a4db94011d3	22087
sahilmgandhi	18:6a4db94011d3	22088	#define SC_INTEN_TMR0IEN_Pos (3) /!< SC INTEN: TMR0IEN Position /
sahilmgandhi	18:6a4db94011d3	22089	#define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) /!< SC INTEN: TMR0IEN Mask /
sahilmgandhi	18:6a4db94011d3	22090
sahilmgandhi	18:6a4db94011d3	22091	#define SC_INTEN_TMR1IEN_Pos (4) /!< SC INTEN: TMR1IEN Position /
sahilmgandhi	18:6a4db94011d3	22092	#define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) /!< SC INTEN: TMR1IEN Mask /
sahilmgandhi	18:6a4db94011d3	22093
sahilmgandhi	18:6a4db94011d3	22094	#define SC_INTEN_TMR2IEN_Pos (5) /!< SC INTEN: TMR2IEN Position /
sahilmgandhi	18:6a4db94011d3	22095	#define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) /!< SC INTEN: TMR2IEN Mask /
sahilmgandhi	18:6a4db94011d3	22096
sahilmgandhi	18:6a4db94011d3	22097	#define SC_INTEN_BGTIEN_Pos (6) /!< SC INTEN: BGTIEN Position /
sahilmgandhi	18:6a4db94011d3	22098	#define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) /!< SC INTEN: BGTIEN Mask /
sahilmgandhi	18:6a4db94011d3	22099
sahilmgandhi	18:6a4db94011d3	22100	#define SC_INTEN_CDIEN_Pos (7) /!< SC INTEN: CDIEN Position /
sahilmgandhi	18:6a4db94011d3	22101	#define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) /!< SC INTEN: CDIEN Mask /
sahilmgandhi	18:6a4db94011d3	22102
sahilmgandhi	18:6a4db94011d3	22103	#define SC_INTEN_INITIEN_Pos (8) /!< SC INTEN: INITIEN Position /
sahilmgandhi	18:6a4db94011d3	22104	#define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) /!< SC INTEN: INITIEN Mask /
sahilmgandhi	18:6a4db94011d3	22105
sahilmgandhi	18:6a4db94011d3	22106	#define SC_INTEN_RXTOIF_Pos (9) /!< SC INTEN: RXTOIF Position /
sahilmgandhi	18:6a4db94011d3	22107	#define SC_INTEN_RXTOIF_Msk (0x1ul << SC_INTEN_RXTOIF_Pos) /!< SC INTEN: RXTOIF Mask /
sahilmgandhi	18:6a4db94011d3	22108
sahilmgandhi	18:6a4db94011d3	22109	#define SC_INTEN_ACERRIEN_Pos (10) /!< SC INTEN: ACERRIEN Position /
sahilmgandhi	18:6a4db94011d3	22110	#define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) /!< SC INTEN: ACERRIEN Mask /
sahilmgandhi	18:6a4db94011d3	22111
sahilmgandhi	18:6a4db94011d3	22112	#define SC_INTSTS_RDAIF_Pos (0) /!< SC INTSTS: RDAIF Position /
sahilmgandhi	18:6a4db94011d3	22113	#define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) /!< SC INTSTS: RDAIF Mask /
sahilmgandhi	18:6a4db94011d3	22114
sahilmgandhi	18:6a4db94011d3	22115	#define SC_INTSTS_TBEIF_Pos (1) /!< SC INTSTS: TBEIF Position /
sahilmgandhi	18:6a4db94011d3	22116	#define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) /!< SC INTSTS: TBEIF Mask /
sahilmgandhi	18:6a4db94011d3	22117
sahilmgandhi	18:6a4db94011d3	22118	#define SC_INTSTS_TERRIF_Pos (2) /!< SC INTSTS: TERRIF Position /
sahilmgandhi	18:6a4db94011d3	22119	#define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) /!< SC INTSTS: TERRIF Mask /
sahilmgandhi	18:6a4db94011d3	22120
sahilmgandhi	18:6a4db94011d3	22121	#define SC_INTSTS_TMR0IF_Pos (3) /!< SC INTSTS: TMR0IF Position /
sahilmgandhi	18:6a4db94011d3	22122	#define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) /!< SC INTSTS: TMR0IF Mask /
sahilmgandhi	18:6a4db94011d3	22123
sahilmgandhi	18:6a4db94011d3	22124	#define SC_INTSTS_TMR1IF_Pos (4) /!< SC INTSTS: TMR1IF Position /
sahilmgandhi	18:6a4db94011d3	22125	#define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) /!< SC INTSTS: TMR1IF Mask /
sahilmgandhi	18:6a4db94011d3	22126
sahilmgandhi	18:6a4db94011d3	22127	#define SC_INTSTS_TMR2IF_Pos (5) /!< SC INTSTS: TMR2IF Position /
sahilmgandhi	18:6a4db94011d3	22128	#define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) /!< SC INTSTS: TMR2IF Mask /
sahilmgandhi	18:6a4db94011d3	22129
sahilmgandhi	18:6a4db94011d3	22130	#define SC_INTSTS_BGTIF_Pos (6) /!< SC INTSTS: BGTIF Position /
sahilmgandhi	18:6a4db94011d3	22131	#define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) /!< SC INTSTS: BGTIF Mask /
sahilmgandhi	18:6a4db94011d3	22132
sahilmgandhi	18:6a4db94011d3	22133	#define SC_INTSTS_CDIF_Pos (7) /!< SC INTSTS: CDIF Position /
sahilmgandhi	18:6a4db94011d3	22134	#define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) /!< SC INTSTS: CDIF Mask /
sahilmgandhi	18:6a4db94011d3	22135
sahilmgandhi	18:6a4db94011d3	22136	#define SC_INTSTS_INITIF_Pos (8) /!< SC INTSTS: INITIF Position /
sahilmgandhi	18:6a4db94011d3	22137	#define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) /!< SC INTSTS: INITIF Mask /
sahilmgandhi	18:6a4db94011d3	22138
sahilmgandhi	18:6a4db94011d3	22139	#define SC_INTSTS_RBTOIF_Pos (9) /!< SC INTSTS: RBTOIF Position /
sahilmgandhi	18:6a4db94011d3	22140	#define SC_INTSTS_RBTOIF_Msk (0x1ul << SC_INTSTS_RBTOIF_Pos) /!< SC INTSTS: RBTOIF Mask /
sahilmgandhi	18:6a4db94011d3	22141
sahilmgandhi	18:6a4db94011d3	22142	#define SC_INTSTS_ACERRIF_Pos (10) /!< SC INTSTS: ACERRIF Position /
sahilmgandhi	18:6a4db94011d3	22143	#define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) /!< SC INTSTS: ACERRIF Mask /
sahilmgandhi	18:6a4db94011d3	22144
sahilmgandhi	18:6a4db94011d3	22145	#define SC_STATUS_RXOV_Pos (0) /!< SC STATUS: RXOV Position /
sahilmgandhi	18:6a4db94011d3	22146	#define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) /!< SC STATUS: RXOV Mask /
sahilmgandhi	18:6a4db94011d3	22147
sahilmgandhi	18:6a4db94011d3	22148	#define SC_STATUS_RXEMPTY_Pos (1) /!< SC STATUS: RXEMPTY Position /
sahilmgandhi	18:6a4db94011d3	22149	#define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) /!< SC STATUS: RXEMPTY Mask /
sahilmgandhi	18:6a4db94011d3	22150
sahilmgandhi	18:6a4db94011d3	22151	#define SC_STATUS_RXFULL_Pos (2) /!< SC STATUS: RXFULL Position /
sahilmgandhi	18:6a4db94011d3	22152	#define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) /!< SC STATUS: RXFULL Mask /
sahilmgandhi	18:6a4db94011d3	22153
sahilmgandhi	18:6a4db94011d3	22154	#define SC_STATUS_PEF_Pos (4) /!< SC STATUS: PEF Position /
sahilmgandhi	18:6a4db94011d3	22155	#define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) /!< SC STATUS: PEF Mask /
sahilmgandhi	18:6a4db94011d3	22156
sahilmgandhi	18:6a4db94011d3	22157	#define SC_STATUS_FEF_Pos (5) /!< SC STATUS: FEF Position /
sahilmgandhi	18:6a4db94011d3	22158	#define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) /!< SC STATUS: FEF Mask /
sahilmgandhi	18:6a4db94011d3	22159
sahilmgandhi	18:6a4db94011d3	22160	#define SC_STATUS_BEF_Pos (6) /!< SC STATUS: BEF Position /
sahilmgandhi	18:6a4db94011d3	22161	#define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) /!< SC STATUS: BEF Mask /
sahilmgandhi	18:6a4db94011d3	22162
sahilmgandhi	18:6a4db94011d3	22163	#define SC_STATUS_TXOV_Pos (8) /!< SC STATUS: TXOV Position /
sahilmgandhi	18:6a4db94011d3	22164	#define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) /!< SC STATUS: TXOV Mask /
sahilmgandhi	18:6a4db94011d3	22165
sahilmgandhi	18:6a4db94011d3	22166	#define SC_STATUS_TXEMPTY_Pos (9) /!< SC STATUS: TXEMPTY Position /
sahilmgandhi	18:6a4db94011d3	22167	#define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) /!< SC STATUS: TXEMPTY Mask /
sahilmgandhi	18:6a4db94011d3	22168
sahilmgandhi	18:6a4db94011d3	22169	#define SC_STATUS_TXFULL_Pos (10) /!< SC STATUS: TXFULL Position /
sahilmgandhi	18:6a4db94011d3	22170	#define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) /!< SC STATUS: TXFULL Mask /
sahilmgandhi	18:6a4db94011d3	22171
sahilmgandhi	18:6a4db94011d3	22172	#define SC_STATUS_CREMOVE_Pos (11) /!< SC STATUS: CREMOVE Position /
sahilmgandhi	18:6a4db94011d3	22173	#define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) /!< SC STATUS: CREMOVE Mask /
sahilmgandhi	18:6a4db94011d3	22174
sahilmgandhi	18:6a4db94011d3	22175	#define SC_STATUS_CINSERT_Pos (12) /!< SC STATUS: CINSERT Position /
sahilmgandhi	18:6a4db94011d3	22176	#define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) /!< SC STATUS: CINSERT Mask /
sahilmgandhi	18:6a4db94011d3	22177
sahilmgandhi	18:6a4db94011d3	22178	#define SC_STATUS_CDPINSTS_Pos (13) /!< SC STATUS: CDPINSTS Position /
sahilmgandhi	18:6a4db94011d3	22179	#define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) /!< SC STATUS: CDPINSTS Mask /
sahilmgandhi	18:6a4db94011d3	22180
sahilmgandhi	18:6a4db94011d3	22181	#define SC_STATUS_RXPOINT_Pos (16) /!< SC STATUS: RXPOINT Position /
sahilmgandhi	18:6a4db94011d3	22182	#define SC_STATUS_RXPOINT_Msk (0x3ul << SC_STATUS_RXPOINT_Pos) /!< SC STATUS: RXPOINT Mask /
sahilmgandhi	18:6a4db94011d3	22183
sahilmgandhi	18:6a4db94011d3	22184	#define SC_STATUS_RXRERR_Pos (21) /!< SC STATUS: RXRERR Position /
sahilmgandhi	18:6a4db94011d3	22185	#define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) /!< SC STATUS: RXRERR Mask /
sahilmgandhi	18:6a4db94011d3	22186
sahilmgandhi	18:6a4db94011d3	22187	#define SC_STATUS_RXOVERR_Pos (22) /!< SC STATUS: RXOVERR Position /
sahilmgandhi	18:6a4db94011d3	22188	#define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) /!< SC STATUS: RXOVERR Mask /
sahilmgandhi	18:6a4db94011d3	22189
sahilmgandhi	18:6a4db94011d3	22190	#define SC_STATUS_RXACT_Pos (23) /!< SC STATUS: RXACT Position /
sahilmgandhi	18:6a4db94011d3	22191	#define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) /!< SC STATUS: RXACT Mask /
sahilmgandhi	18:6a4db94011d3	22192
sahilmgandhi	18:6a4db94011d3	22193	#define SC_STATUS_TXPOINT_Pos (24) /!< SC STATUS: TXPOINT Position /
sahilmgandhi	18:6a4db94011d3	22194	#define SC_STATUS_TXPOINT_Msk (0x3ul << SC_STATUS_TXPOINT_Pos) /!< SC STATUS: TXPOINT Mask /
sahilmgandhi	18:6a4db94011d3	22195
sahilmgandhi	18:6a4db94011d3	22196	#define SC_STATUS_TXRERR_Pos (29) /!< SC STATUS: TXRERR Position /
sahilmgandhi	18:6a4db94011d3	22197	#define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) /!< SC STATUS: TXRERR Mask /
sahilmgandhi	18:6a4db94011d3	22198
sahilmgandhi	18:6a4db94011d3	22199	#define SC_STATUS_TXOVERR_Pos (30) /!< SC STATUS: TXOVERR Position /
sahilmgandhi	18:6a4db94011d3	22200	#define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) /!< SC STATUS: TXOVERR Mask /
sahilmgandhi	18:6a4db94011d3	22201
sahilmgandhi	18:6a4db94011d3	22202	#define SC_STATUS_TXACT_Pos (31) /!< SC STATUS: TXACT Position /
sahilmgandhi	18:6a4db94011d3	22203	#define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) /!< SC STATUS: TXACT Mask /
sahilmgandhi	18:6a4db94011d3	22204
sahilmgandhi	18:6a4db94011d3	22205	#define SC_PINCTL_PWREN_Pos (0) /!< SC PINCTL: PWREN Position /
sahilmgandhi	18:6a4db94011d3	22206	#define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) /!< SC PINCTL: PWREN Mask /
sahilmgandhi	18:6a4db94011d3	22207
sahilmgandhi	18:6a4db94011d3	22208	#define SC_PINCTL_SCRST_Pos (1) /!< SC PINCTL: SCRST Position /
sahilmgandhi	18:6a4db94011d3	22209	#define SC_PINCTL_SCRST_Msk (0x1ul << SC_PINCTL_SCRST_Pos) /!< SC PINCTL: SCRST Mask /
sahilmgandhi	18:6a4db94011d3	22210
sahilmgandhi	18:6a4db94011d3	22211	#define SC_PINCTL_CLKKEEP_Pos (6) /!< SC PINCTL: CLKKEEP Position /
sahilmgandhi	18:6a4db94011d3	22212	#define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) /!< SC PINCTL: CLKKEEP Mask /
sahilmgandhi	18:6a4db94011d3	22213
sahilmgandhi	18:6a4db94011d3	22214	#define SC_PINCTL_SCDOUT_Pos (9) /!< SC PINCTL: SCDOUT Position /
sahilmgandhi	18:6a4db94011d3	22215	#define SC_PINCTL_SCDOUT_Msk (0x1ul << SC_PINCTL_SCDOUT_Pos) /!< SC PINCTL: SCDOUT Mask /
sahilmgandhi	18:6a4db94011d3	22216
sahilmgandhi	18:6a4db94011d3	22217	#define SC_PINCTL_PWRINV_Pos (11) /!< SC PINCTL: PWRINV Position /
sahilmgandhi	18:6a4db94011d3	22218	#define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) /!< SC PINCTL: PWRINV Mask /
sahilmgandhi	18:6a4db94011d3	22219
sahilmgandhi	18:6a4db94011d3	22220	#define SC_PINCTL_DATSTS_Pos (16) /!< SC PINCTL: DATSTS Position /
sahilmgandhi	18:6a4db94011d3	22221	#define SC_PINCTL_DATSTS_Msk (0x1ul << SC_PINCTL_DATSTS_Pos) /!< SC PINCTL: DATSTS Mask /
sahilmgandhi	18:6a4db94011d3	22222
sahilmgandhi	18:6a4db94011d3	22223	#define SC_PINCTL_PWRSTS_Pos (17) /!< SC PINCTL: PWRSTS Position /
sahilmgandhi	18:6a4db94011d3	22224	#define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) /!< SC PINCTL: PWRSTS Mask /
sahilmgandhi	18:6a4db94011d3	22225
sahilmgandhi	18:6a4db94011d3	22226	#define SC_PINCTL_RSTSTS_Pos (18) /!< SC PINCTL: RSTSTS Position /
sahilmgandhi	18:6a4db94011d3	22227	#define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) /!< SC PINCTL: RSTSTS Mask /
sahilmgandhi	18:6a4db94011d3	22228
sahilmgandhi	18:6a4db94011d3	22229	#define SC_PINCTL_SYNC_Pos (30) /!< SC PINCTL: SYNC Position /
sahilmgandhi	18:6a4db94011d3	22230	#define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) /!< SC PINCTL: SYNC Mask /
sahilmgandhi	18:6a4db94011d3	22231
sahilmgandhi	18:6a4db94011d3	22232	#define SC_TMRCTL0_CNT_Pos (0) /!< SC TMRCTL0: CNT Position /
sahilmgandhi	18:6a4db94011d3	22233	#define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) /!< SC TMRCTL0: CNT Mask /
sahilmgandhi	18:6a4db94011d3	22234
sahilmgandhi	18:6a4db94011d3	22235	#define SC_TMRCTL0_OPMODE_Pos (24) /!< SC TMRCTL0: OPMODE Position /
sahilmgandhi	18:6a4db94011d3	22236	#define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) /!< SC TMRCTL0: OPMODE Mask /
sahilmgandhi	18:6a4db94011d3	22237
sahilmgandhi	18:6a4db94011d3	22238	#define SC_TMRCTL1_CNT_Pos (0) /!< SC TMRCTL1: CNT Position /
sahilmgandhi	18:6a4db94011d3	22239	#define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) /!< SC TMRCTL1: CNT Mask /
sahilmgandhi	18:6a4db94011d3	22240
sahilmgandhi	18:6a4db94011d3	22241	#define SC_TMRCTL1_OPMODE_Pos (24) /!< SC TMRCTL1: OPMODE Position /
sahilmgandhi	18:6a4db94011d3	22242	#define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) /!< SC TMRCTL1: OPMODE Mask /
sahilmgandhi	18:6a4db94011d3	22243
sahilmgandhi	18:6a4db94011d3	22244	#define SC_TMRCTL2_CNT_Pos (0) /!< SC TMRCTL2: CNT Position /
sahilmgandhi	18:6a4db94011d3	22245	#define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) /!< SC TMRCTL2: CNT Mask /
sahilmgandhi	18:6a4db94011d3	22246
sahilmgandhi	18:6a4db94011d3	22247	#define SC_TMRCTL2_OPMODE_Pos (24) /!< SC TMRCTL2: OPMODE Position /
sahilmgandhi	18:6a4db94011d3	22248	#define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) /!< SC TMRCTL2: OPMODE Mask /
sahilmgandhi	18:6a4db94011d3	22249
sahilmgandhi	18:6a4db94011d3	22250	#define SC_UARTCTL_UARTEN_Pos (0) /!< SC UARTCTL: UARTEN Position /
sahilmgandhi	18:6a4db94011d3	22251	#define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) /!< SC UARTCTL: UARTEN Mask /
sahilmgandhi	18:6a4db94011d3	22252
sahilmgandhi	18:6a4db94011d3	22253	#define SC_UARTCTL_WLS_Pos (4) /!< SC UARTCTL: WLS Position /
sahilmgandhi	18:6a4db94011d3	22254	#define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos) /!< SC UARTCTL: WLS Mask /
sahilmgandhi	18:6a4db94011d3	22255
sahilmgandhi	18:6a4db94011d3	22256	#define SC_UARTCTL_PBOFF_Pos (6) /!< SC UARTCTL: PBOFF Position /
sahilmgandhi	18:6a4db94011d3	22257	#define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) /!< SC UARTCTL: PBOFF Mask /
sahilmgandhi	18:6a4db94011d3	22258
sahilmgandhi	18:6a4db94011d3	22259	#define SC_UARTCTL_OPE_Pos (7) /!< SC UARTCTL: OPE Position /
sahilmgandhi	18:6a4db94011d3	22260	#define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) /!< SC UARTCTL: OPE Mask /
sahilmgandhi	18:6a4db94011d3	22261
sahilmgandhi	18:6a4db94011d3	22262	#define SC_TMRDAT0_TDR0_Pos (0) /!< SC TMRDAT0: TDR0 Position /
sahilmgandhi	18:6a4db94011d3	22263	#define SC_TMRDAT0_TDR0_Msk (0xfffffful << SC_TMRDAT0_TDR0_Pos) /!< SC TMRDAT0: TDR0 Mask /
sahilmgandhi	18:6a4db94011d3	22264
sahilmgandhi	18:6a4db94011d3	22265	#define SC_TMRDAT1_2_TDR1_Pos (0) /!< SC TMRDAT1_2: TDR1 Position /
sahilmgandhi	18:6a4db94011d3	22266	#define SC_TMRDAT1_2_TDR1_Msk (0xfful << SC_TMRDAT1_2_TDR1_Pos) /!< SC TMRDAT1_2: TDR1 Mask /
sahilmgandhi	18:6a4db94011d3	22267
sahilmgandhi	18:6a4db94011d3	22268	#define SC_TMRDAT1_2_TDR2_Pos (8) /!< SC TMRDAT1_2: TDR2 Position /
sahilmgandhi	18:6a4db94011d3	22269	#define SC_TMRDAT1_2_TDR2_Msk (0xfful << SC_TMRDAT1_2_TDR2_Pos) /!< SC TMRDAT1_2: TDR2 Mask /
sahilmgandhi	18:6a4db94011d3	22270
sahilmgandhi	18:6a4db94011d3	22271	/*@}/ /* SC_CONST */
sahilmgandhi	18:6a4db94011d3	22272	/*@}/ /* end of SC register group */
sahilmgandhi	18:6a4db94011d3	22273
sahilmgandhi	18:6a4db94011d3	22274
sahilmgandhi	18:6a4db94011d3	22275	/---------------------- SD Card Host Interface -------------------------/
sahilmgandhi	18:6a4db94011d3	22276	/**
sahilmgandhi	18:6a4db94011d3	22277	@addtogroup SDH SD Card Host Interface(SDH)
sahilmgandhi	18:6a4db94011d3	22278	Memory Mapped Structure for SDH Controller
sahilmgandhi	18:6a4db94011d3	22279	@{ */
sahilmgandhi	18:6a4db94011d3	22280
sahilmgandhi	18:6a4db94011d3	22281	typedef struct {
sahilmgandhi	18:6a4db94011d3	22282
sahilmgandhi	18:6a4db94011d3	22283	/**
sahilmgandhi	18:6a4db94011d3	22284	* FBx
sahilmgandhi	18:6a4db94011d3	22285	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	22286	* Offset: 0x00 ~ 0x7C Shared Buffer (FIFO) 0 ~ 31
sahilmgandhi	18:6a4db94011d3	22287	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	22288	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	22289	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	22290	* \|[0:31] \|BUF \|Shared Buffer
sahilmgandhi	18:6a4db94011d3	22291
sahilmgandhi	18:6a4db94011d3	22292	*/
sahilmgandhi	18:6a4db94011d3	22293	uint32_t FB[32];
sahilmgandhi	18:6a4db94011d3	22294	uint32_t RESERVE0[224];
sahilmgandhi	18:6a4db94011d3	22295
sahilmgandhi	18:6a4db94011d3	22296
sahilmgandhi	18:6a4db94011d3	22297	/**
sahilmgandhi	18:6a4db94011d3	22298	* DMACTL
sahilmgandhi	18:6a4db94011d3	22299	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	22300	* Offset: 0x400 DMA Control and Status Register
sahilmgandhi	18:6a4db94011d3	22301	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	22302	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	22303	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	22304	* \|[0] \|DMAEN \|DMA Engine Enable Control
sahilmgandhi	18:6a4db94011d3	22305	* \| \| \|0 = DMA Disabled.
sahilmgandhi	18:6a4db94011d3	22306	* \| \| \|1 = DMA Enabled.
sahilmgandhi	18:6a4db94011d3	22307	* \| \| \|If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state.
sahilmgandhi	18:6a4db94011d3	22308	* \| \| \|Note: If target abort is occurred, DMAEN will be cleared.
sahilmgandhi	18:6a4db94011d3	22309	* \|[1] \|DMARST \|Software Engine Reset
sahilmgandhi	18:6a4db94011d3	22310	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	22311	* \| \| \|1 = Reset internal state machine and pointers.
sahilmgandhi	18:6a4db94011d3	22312	* \| \| \|The contents of control register will not be cleared.
sahilmgandhi	18:6a4db94011d3	22313	* \| \| \|This bit will auto be cleared after few clock cycles.
sahilmgandhi	18:6a4db94011d3	22314	* \| \| \|Note: The software reset DMA related registers.
sahilmgandhi	18:6a4db94011d3	22315	* \|[3] \|SGEN \|Scatter-Gather Function Enable Control
sahilmgandhi	18:6a4db94011d3	22316	* \| \| \|0 = Scatter-gather function Disabled (DMA will treat the starting address in DMASAR as starting pointer of a single block memory).
sahilmgandhi	18:6a4db94011d3	22317	* \| \| \|1 = Scatter-gather function Enabled (DMA will treat the starting address in DMASAR as a starting address of Physical Address Descriptor (PAD) table.
sahilmgandhi	18:6a4db94011d3	22318	* \| \| \|The format of these Pads' will be described later).
sahilmgandhi	18:6a4db94011d3	22319	* \|[9] \|DMABUSY \|DMA Transfer Is In Progress
sahilmgandhi	18:6a4db94011d3	22320	* \| \| \|This bit indicates if SD Host is granted and doing DMA transfer or not.
sahilmgandhi	18:6a4db94011d3	22321	* \| \| \|0 = DMA transfer is not in progress.
sahilmgandhi	18:6a4db94011d3	22322	* \| \| \|1 = DMA transfer is in progress.
sahilmgandhi	18:6a4db94011d3	22323	*/
sahilmgandhi	18:6a4db94011d3	22324	__IO uint32_t DMACTL;
sahilmgandhi	18:6a4db94011d3	22325	uint32_t RESERVE1[1];
sahilmgandhi	18:6a4db94011d3	22326
sahilmgandhi	18:6a4db94011d3	22327
sahilmgandhi	18:6a4db94011d3	22328	/**
sahilmgandhi	18:6a4db94011d3	22329	* DMASA
sahilmgandhi	18:6a4db94011d3	22330	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	22331	* Offset: 0x408 DMA Transfer Starting Address Register
sahilmgandhi	18:6a4db94011d3	22332	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	22333	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	22334	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	22335	* \|[0] \|ORDER \|Determined To The PAD Table Fetching Is In Order Or Out Of Order
sahilmgandhi	18:6a4db94011d3	22336	* \| \| \|0 = PAD table is fetched in order.
sahilmgandhi	18:6a4db94011d3	22337	* \| \| \|1 = PAD table is fetched out of order.
sahilmgandhi	18:6a4db94011d3	22338	* \| \| \|Note: the bit0 is valid in scatter-gather mode when SGEN = 1.
sahilmgandhi	18:6a4db94011d3	22339	* \|[1:31] \|DMASA \|DMA Transfer Starting Address
sahilmgandhi	18:6a4db94011d3	22340	* \| \| \|This field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data.
sahilmgandhi	18:6a4db94011d3	22341	* \| \| \|If DMA is not in normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table.
sahilmgandhi	18:6a4db94011d3	22342	*/
sahilmgandhi	18:6a4db94011d3	22343	__IO uint32_t DMASA;
sahilmgandhi	18:6a4db94011d3	22344
sahilmgandhi	18:6a4db94011d3	22345	/**
sahilmgandhi	18:6a4db94011d3	22346	* DMABCNT
sahilmgandhi	18:6a4db94011d3	22347	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	22348	* Offset: 0x40C DMA Transfer Byte Count Register
sahilmgandhi	18:6a4db94011d3	22349	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	22350	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	22351	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	22352	* \|[0:25] \|BCNT \|DMA Transfer Byte Count (Read Only)
sahilmgandhi	18:6a4db94011d3	22353	* \| \| \|This field indicates the remained byte count of DMA transfer.
sahilmgandhi	18:6a4db94011d3	22354	* \| \| \|The value of this field is valid only when DMA is busy; otherwise, it is 0.
sahilmgandhi	18:6a4db94011d3	22355	*/
sahilmgandhi	18:6a4db94011d3	22356	__I uint32_t DMABCNT;
sahilmgandhi	18:6a4db94011d3	22357
sahilmgandhi	18:6a4db94011d3	22358	/**
sahilmgandhi	18:6a4db94011d3	22359	* DMAINTEN
sahilmgandhi	18:6a4db94011d3	22360	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	22361	* Offset: 0x410 DMA Interrupt Enable Control Register
sahilmgandhi	18:6a4db94011d3	22362	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	22363	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	22364	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	22365	* \|[0] \|ABORTIEN \|DMA Read/Write Target Abort Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	22366	* \| \| \|0 = Target abort interrupt generation Disabled during DMA transfer.
sahilmgandhi	18:6a4db94011d3	22367	* \| \| \|1 = Target abort interrupt generation Enabled during DMA transfer.
sahilmgandhi	18:6a4db94011d3	22368	* \|[1] \|WEOTIEN \|Wrong EOT Encountered Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	22369	* \| \| \|0 = Interrupt generation Disabled when wrong EOT is encountered.
sahilmgandhi	18:6a4db94011d3	22370	* \| \| \|1 = Interrupt generation Enabled when wrong EOT is encountered.
sahilmgandhi	18:6a4db94011d3	22371	*/
sahilmgandhi	18:6a4db94011d3	22372	__IO uint32_t DMAINTEN;
sahilmgandhi	18:6a4db94011d3	22373
sahilmgandhi	18:6a4db94011d3	22374	/**
sahilmgandhi	18:6a4db94011d3	22375	* DMAINTSTS
sahilmgandhi	18:6a4db94011d3	22376	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	22377	* Offset: 0x414 DMA Interrupt Status Register
sahilmgandhi	18:6a4db94011d3	22378	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	22379	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	22380	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	22381	* \|[0] \|ABORTIF \|DMA Read/Write Target Abort Interrupt Flag
sahilmgandhi	18:6a4db94011d3	22382	* \| \| \|0 = No bus ERROR response received.
sahilmgandhi	18:6a4db94011d3	22383	* \| \| \|1 = Bus ERROR response received.
sahilmgandhi	18:6a4db94011d3	22384	* \| \| \|Note: This bit is read only, but can be cleared by writing '1' to it.
sahilmgandhi	18:6a4db94011d3	22385	* \|[1] \|WEOTIF \|Wrong EOT Encountered Interrupt Flag
sahilmgandhi	18:6a4db94011d3	22386	* \| \| \|When DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD host), this bit will be set.
sahilmgandhi	18:6a4db94011d3	22387	* \| \| \|0 = No EOT encountered before DMA transfer finished.
sahilmgandhi	18:6a4db94011d3	22388	* \| \| \|1 = EOT encountered before DMA transfer finished.
sahilmgandhi	18:6a4db94011d3	22389	* \| \| \|Note: This bit is read only, but can be cleared by writing '1' to it.
sahilmgandhi	18:6a4db94011d3	22390	*/
sahilmgandhi	18:6a4db94011d3	22391	__IO uint32_t DMAINTSTS;
sahilmgandhi	18:6a4db94011d3	22392	uint32_t RESERVE2[250];
sahilmgandhi	18:6a4db94011d3	22393
sahilmgandhi	18:6a4db94011d3	22394
sahilmgandhi	18:6a4db94011d3	22395	/**
sahilmgandhi	18:6a4db94011d3	22396	* GCTL
sahilmgandhi	18:6a4db94011d3	22397	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	22398	* Offset: 0x800 Global Control and Status Register
sahilmgandhi	18:6a4db94011d3	22399	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	22400	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	22401	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	22402	* \|[0] \|GCTLRST \|Software Engine Reset
sahilmgandhi	18:6a4db94011d3	22403	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	22404	* \| \| \|1 = Reset SD host.
sahilmgandhi	18:6a4db94011d3	22405	* \| \| \|The contents of control register will not be cleared.
sahilmgandhi	18:6a4db94011d3	22406	* \| \| \|This bit will auto cleared after reset complete.
sahilmgandhi	18:6a4db94011d3	22407	* \|[1] \|SDEN \|Secure Digital Functionality Enable Control
sahilmgandhi	18:6a4db94011d3	22408	* \| \| \|0 = SD functionality disabled.
sahilmgandhi	18:6a4db94011d3	22409	* \| \| \|1 = SD functionality enabled.
sahilmgandhi	18:6a4db94011d3	22410	*/
sahilmgandhi	18:6a4db94011d3	22411	__IO uint32_t GCTL;
sahilmgandhi	18:6a4db94011d3	22412
sahilmgandhi	18:6a4db94011d3	22413	/**
sahilmgandhi	18:6a4db94011d3	22414	* GINTEN
sahilmgandhi	18:6a4db94011d3	22415	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	22416	* Offset: 0x804 Global Interrupt Control Register
sahilmgandhi	18:6a4db94011d3	22417	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	22418	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	22419	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	22420	* \|[0] \|DTAIEN \|DMA READ/WRITE Target Abort Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	22421	* \| \| \|0 = DMA READ/WRITE target abort interrupt generation disabled.
sahilmgandhi	18:6a4db94011d3	22422	* \| \| \|1 = DMA READ/WRITE target abort interrupt generation enabled.
sahilmgandhi	18:6a4db94011d3	22423	*/
sahilmgandhi	18:6a4db94011d3	22424	__IO uint32_t GINTEN;
sahilmgandhi	18:6a4db94011d3	22425
sahilmgandhi	18:6a4db94011d3	22426	/**
sahilmgandhi	18:6a4db94011d3	22427	* GINTSTS
sahilmgandhi	18:6a4db94011d3	22428	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	22429	* Offset: 0x808 Global Interrupt Status Register
sahilmgandhi	18:6a4db94011d3	22430	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	22431	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	22432	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	22433	* \|[0] \|DTAIF \|DMA READ/WRITE Target Abort Interrupt Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	22434	* \| \| \|This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation.
sahilmgandhi	18:6a4db94011d3	22435	* \| \| \|When Target Abort is occurred, please reset all engine.
sahilmgandhi	18:6a4db94011d3	22436	* \| \| \|0 = No bus ERROR response received.
sahilmgandhi	18:6a4db94011d3	22437	* \| \| \|1 = Bus ERROR response received.
sahilmgandhi	18:6a4db94011d3	22438	* \| \| \|Note: This bit is read only, but can be cleared by writing '1' to it.
sahilmgandhi	18:6a4db94011d3	22439	*/
sahilmgandhi	18:6a4db94011d3	22440	__I uint32_t GINTSTS;
sahilmgandhi	18:6a4db94011d3	22441	uint32_t RESERVE3[5];
sahilmgandhi	18:6a4db94011d3	22442
sahilmgandhi	18:6a4db94011d3	22443
sahilmgandhi	18:6a4db94011d3	22444	/**
sahilmgandhi	18:6a4db94011d3	22445	* CTL
sahilmgandhi	18:6a4db94011d3	22446	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	22447	* Offset: 0x820 SD Control and Status Register
sahilmgandhi	18:6a4db94011d3	22448	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	22449	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	22450	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	22451	* \|[0] \|COEN \|Command Output Enable Control
sahilmgandhi	18:6a4db94011d3	22452	* \| \| \|0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
sahilmgandhi	18:6a4db94011d3	22453	* \| \| \|1 = Enabled, SD host will output a command to SD card.
sahilmgandhi	18:6a4db94011d3	22454	* \| \| \|Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
sahilmgandhi	18:6a4db94011d3	22455	* \|[1] \|RIEN \|Response Input Enable Control
sahilmgandhi	18:6a4db94011d3	22456	* \| \| \|0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
sahilmgandhi	18:6a4db94011d3	22457	* \| \| \|1 = Enabled, SD host will wait to receive a response from SD card.
sahilmgandhi	18:6a4db94011d3	22458	* \| \| \|Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
sahilmgandhi	18:6a4db94011d3	22459	* \|[2] \|DIEN \|Data Input Enable Control
sahilmgandhi	18:6a4db94011d3	22460	* \| \| \|0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
sahilmgandhi	18:6a4db94011d3	22461	* \| \| \|1 = Enabled, SD host will wait to receive block data and the CRC16 value from SD card.
sahilmgandhi	18:6a4db94011d3	22462	* \| \| \|Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
sahilmgandhi	18:6a4db94011d3	22463	* \|[3] \|DOEN \|Data Output Enable Control
sahilmgandhi	18:6a4db94011d3	22464	* \| \| \|0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
sahilmgandhi	18:6a4db94011d3	22465	* \| \| \|1 = Enabled, SD host will transfer block data and the CRC16 value to SD card.
sahilmgandhi	18:6a4db94011d3	22466	* \| \| \|Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
sahilmgandhi	18:6a4db94011d3	22467	* \|[4] \|R2EN \|Response R2 Input Enable Control
sahilmgandhi	18:6a4db94011d3	22468	* \| \| \|0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
sahilmgandhi	18:6a4db94011d3	22469	* \| \| \|1 = Enabled, SD host will wait to receive a response R2 from SD card and store the response data into DMC's flash buffer (exclude CRC7).
sahilmgandhi	18:6a4db94011d3	22470	* \| \| \|Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
sahilmgandhi	18:6a4db94011d3	22471	* \|[5] \|CLK74OEN \|Initial 74 Clock Cycles Output Enable Control
sahilmgandhi	18:6a4db94011d3	22472	* \| \| \|0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
sahilmgandhi	18:6a4db94011d3	22473	* \| \| \|1 = Enabled, SD host will output 74 clock cycles to SD card.
sahilmgandhi	18:6a4db94011d3	22474	* \| \| \|Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
sahilmgandhi	18:6a4db94011d3	22475	* \|[6] \|CLK8OEN \|Generating 8 Clock Cycles Output Enable Control
sahilmgandhi	18:6a4db94011d3	22476	* \| \| \|0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
sahilmgandhi	18:6a4db94011d3	22477	* \| \| \|1 = Enabled, SD host will output 8 clock cycles.
sahilmgandhi	18:6a4db94011d3	22478	* \| \| \|Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
sahilmgandhi	18:6a4db94011d3	22479	* \|[7] \|CLKKEEP0 \|SD Clock Enable Control For Port 0
sahilmgandhi	18:6a4db94011d3	22480	* \| \| \|0 = SD host decided when to output clock and when to disable clock output automatically.
sahilmgandhi	18:6a4db94011d3	22481	* \| \| \|1 = SD clock always keeps free running.
sahilmgandhi	18:6a4db94011d3	22482	* \|[8:13] \|CMDCODE \|SD Command Code
sahilmgandhi	18:6a4db94011d3	22483	* \| \| \|This register contains the SD command code (0x00 - 0x3F).
sahilmgandhi	18:6a4db94011d3	22484	* \|[14] \|CTLRST \|Software Engine Reset
sahilmgandhi	18:6a4db94011d3	22485	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	22486	* \| \| \|1 = Reset the internal state machine and counters.
sahilmgandhi	18:6a4db94011d3	22487	* \| \| \|The contents of control register will not be cleared (but RIEN, DIEN, DOEN and R2_EN will be cleared).
sahilmgandhi	18:6a4db94011d3	22488	* \| \| \|This bit will be auto cleared after few clock cycles.
sahilmgandhi	18:6a4db94011d3	22489	* \|[15] \|DBW \|SD Data Bus Width (For 1-Bit / 4-Bit Selection)
sahilmgandhi	18:6a4db94011d3	22490	* \| \| \|0 = Data bus width is 1-bit.
sahilmgandhi	18:6a4db94011d3	22491	* \| \| \|1 = Data bus width is 4-bit.
sahilmgandhi	18:6a4db94011d3	22492	* \|[16:23] \|BLKCNT \|Block Counts To Be Transferred Or Received
sahilmgandhi	18:6a4db94011d3	22493	* \| \| \|This field contains the block counts for data-in and data-out transfer.
sahilmgandhi	18:6a4db94011d3	22494	* \| \| \|For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, software can use this function to accelerate data transfer and improve performance.
sahilmgandhi	18:6a4db94011d3	22495	* \| \| \|Don't fill 0x0 to this field.
sahilmgandhi	18:6a4db94011d3	22496	* \| \| \|Note: For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the actual total length is BLKCNT * (BLKLEN +1).
sahilmgandhi	18:6a4db94011d3	22497	* \|[24:27] \|SDNWR \|NWR Parameter For Block Write Operation
sahilmgandhi	18:6a4db94011d3	22498	* \| \| \|This value indicates the NWR parameter for data block write operation in SD clock counts.
sahilmgandhi	18:6a4db94011d3	22499	* \| \| \|The actual clock cycle will be SDNWR+1.
sahilmgandhi	18:6a4db94011d3	22500	* \|[29:30] \|SDPORT \|SD Port Selection
sahilmgandhi	18:6a4db94011d3	22501	* \| \| \|00 = Port 0 selected.
sahilmgandhi	18:6a4db94011d3	22502	* \| \| \|01 = Port 1 selected.
sahilmgandhi	18:6a4db94011d3	22503	* \| \| \|Other = Reserved.
sahilmgandhi	18:6a4db94011d3	22504	* \|[31] \|CLKKEEP1 \|SD Clock Enable Control For Port 1
sahilmgandhi	18:6a4db94011d3	22505	* \| \| \|0 = SD host decided when to output clock and when to disable clock output automatically.
sahilmgandhi	18:6a4db94011d3	22506	* \| \| \|1 = SD clock always keeps free running.
sahilmgandhi	18:6a4db94011d3	22507	*/
sahilmgandhi	18:6a4db94011d3	22508	__IO uint32_t CTL;
sahilmgandhi	18:6a4db94011d3	22509
sahilmgandhi	18:6a4db94011d3	22510	/**
sahilmgandhi	18:6a4db94011d3	22511	* CMDARG
sahilmgandhi	18:6a4db94011d3	22512	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	22513	* Offset: 0x824 SD Command Argument Register
sahilmgandhi	18:6a4db94011d3	22514	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	22515	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	22516	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	22517	* \|[0:31] \|ARGUMENT \|SD Command Argument
sahilmgandhi	18:6a4db94011d3	22518	* \| \| \|This register contains a 32-bit value specifies the argument of SD command from host controller to SD card.
sahilmgandhi	18:6a4db94011d3	22519	* \| \| \|Before trigger COEN (SDH_CTL [0]), software should fill argument in this field.
sahilmgandhi	18:6a4db94011d3	22520	*/
sahilmgandhi	18:6a4db94011d3	22521	__IO uint32_t CMDARG;
sahilmgandhi	18:6a4db94011d3	22522
sahilmgandhi	18:6a4db94011d3	22523	/**
sahilmgandhi	18:6a4db94011d3	22524	* INTEN
sahilmgandhi	18:6a4db94011d3	22525	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	22526	* Offset: 0x828 SD Interrupt Control Register
sahilmgandhi	18:6a4db94011d3	22527	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	22528	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	22529	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	22530	* \|[0] \|BLKDIEN \|Block Transfer Done Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	22531	* \| \| \|0 = SD host will not generate interrupt when data-in (out) transfer done.
sahilmgandhi	18:6a4db94011d3	22532	* \| \| \|1 = SD host will generate interrupt when data-in (out) transfer done.
sahilmgandhi	18:6a4db94011d3	22533	* \|[1] \|CRCIEN \|CRC7, CRC16 And CRC Status Error Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	22534	* \| \| \|0 = SD host will not generate interrupt when CRC7, CRC16 and CRC status is error.
sahilmgandhi	18:6a4db94011d3	22535	* \| \| \|1 = SD host will generate interrupt when CRC7, CRC16 and CRC status is error.
sahilmgandhi	18:6a4db94011d3	22536	* \|[8] \|CDIEN0 \|SD0 Card Detection Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	22537	* \| \| \|Enable/Disable interrupts generation of SD controller when card 0 is inserted or removed.
sahilmgandhi	18:6a4db94011d3	22538	* \| \| \|0 = Disable.
sahilmgandhi	18:6a4db94011d3	22539	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	22540	* \|[9] \|CDIEN1 \|SD1 Card Detection Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	22541	* \| \| \|Enable/Disable interrupts generation of SD controller when card 1 is inserted or removed.
sahilmgandhi	18:6a4db94011d3	22542	* \| \| \|0 = Disable.
sahilmgandhi	18:6a4db94011d3	22543	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	22544	* \|[12] \|RTOIEN \|Response Time-Out Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	22545	* \| \| \|Enable/Disable interrupts generation of SD controller when receiving response or R2 time-out.
sahilmgandhi	18:6a4db94011d3	22546	* \| \| \|Time-out value is specified at TOUT register.
sahilmgandhi	18:6a4db94011d3	22547	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	22548	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	22549	* \|[13] \|DITOIEN \|Data Input Time-Out Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	22550	* \| \| \|Enable/Disable interrupts generation of SD controller when data input time-out.
sahilmgandhi	18:6a4db94011d3	22551	* \| \| \|Time-out value is specified at TOUT register.
sahilmgandhi	18:6a4db94011d3	22552	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	22553	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	22554	* \|[14] \|WKIEN \|Wake-Up Signal Generating Enable Control
sahilmgandhi	18:6a4db94011d3	22555	* \| \| \|Enable/Disable wake-up signal generating of SD host when current using SD card issues an interrupt (wake-up) via DAT [1] to host.
sahilmgandhi	18:6a4db94011d3	22556	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	22557	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	22558	* \|[30] \|CDSRC0 \|SD0 Card Detect Source Selection
sahilmgandhi	18:6a4db94011d3	22559	* \| \| \|0 = From SD0 card's DAT3 pin.
sahilmgandhi	18:6a4db94011d3	22560	* \| \| \|Host need clock to got data on pin DAT3.
sahilmgandhi	18:6a4db94011d3	22561	* \| \| \|Please make sure CLKKEEP0 (SDH_CTL[7]) is 1 in order to generate free running clock for DAT3 pin.
sahilmgandhi	18:6a4db94011d3	22562	* \| \| \|1 = From GPIO pin.
sahilmgandhi	18:6a4db94011d3	22563	* \|[31] \|CDSRC1 \|SD1 Card Detect Source Selection
sahilmgandhi	18:6a4db94011d3	22564	* \| \| \|0 = From SD1 card's DAT3 pin.
sahilmgandhi	18:6a4db94011d3	22565	* \| \| \|Host need clock to got data on pin DAT3.
sahilmgandhi	18:6a4db94011d3	22566	* \| \| \|Please make sure CLKKEEP1 (SDH_CTL[31]) is 1 in order to generate free running clock for DAT3 pin.
sahilmgandhi	18:6a4db94011d3	22567	* \| \| \|1 = From GPIO pin.
sahilmgandhi	18:6a4db94011d3	22568	*/
sahilmgandhi	18:6a4db94011d3	22569	__IO uint32_t INTEN;
sahilmgandhi	18:6a4db94011d3	22570
sahilmgandhi	18:6a4db94011d3	22571	/**
sahilmgandhi	18:6a4db94011d3	22572	* INTSTS
sahilmgandhi	18:6a4db94011d3	22573	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	22574	* Offset: 0x82C SD Interrupt Status Register
sahilmgandhi	18:6a4db94011d3	22575	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	22576	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	22577	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	22578	* \|[0] \|BLKDIF \|Block Transfer Done Interrupt Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	22579	* \| \| \|This bit indicates that SD host has finished all data-in or data-out block transfer.
sahilmgandhi	18:6a4db94011d3	22580	* \| \| \|If there is a CRC16 error or incorrect CRC status during multiple block data transfer, the transfer will be broken and this bit will also be set.
sahilmgandhi	18:6a4db94011d3	22581	* \| \| \|0 = Not finished yet.
sahilmgandhi	18:6a4db94011d3	22582	* \| \| \|1 = Done.
sahilmgandhi	18:6a4db94011d3	22583	* \| \| \|Note: This bit is read only, but can be cleared by writing '1' to it.
sahilmgandhi	18:6a4db94011d3	22584	* \|[1] \|CRCIF \|CRC7, CRC16 And CRC Status Error Interrupt Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	22585	* \| \| \|This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer.
sahilmgandhi	18:6a4db94011d3	22586	* \| \| \|When CRC error is occurred, software should reset SD engine.
sahilmgandhi	18:6a4db94011d3	22587	* \| \| \|Some response (ex.
sahilmgandhi	18:6a4db94011d3	22588	* \| \| \|R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag.
sahilmgandhi	18:6a4db94011d3	22589	* \| \| \|In this condition, software should ignore CRC error and clears this bit manually.
sahilmgandhi	18:6a4db94011d3	22590	* \| \| \|0 = No CRC error is occurred.
sahilmgandhi	18:6a4db94011d3	22591	* \| \| \|1 = CRC error is occurred.
sahilmgandhi	18:6a4db94011d3	22592	* \| \| \|Note: This bit is read only, but can be cleared by writing '1' to it.
sahilmgandhi	18:6a4db94011d3	22593	* \|[2] \|CRC7 \|CRC7 Check Status (Read Only)
sahilmgandhi	18:6a4db94011d3	22594	* \| \| \|SD host will check CRC7 correctness during each response in.
sahilmgandhi	18:6a4db94011d3	22595	* \| \| \|If that response does not contain CRC7 information (ex.
sahilmgandhi	18:6a4db94011d3	22596	* \| \| \|R3), then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit.
sahilmgandhi	18:6a4db94011d3	22597	* \| \| \|0 = Fault.
sahilmgandhi	18:6a4db94011d3	22598	* \| \| \|1 = OK.
sahilmgandhi	18:6a4db94011d3	22599	* \|[3] \|CRC16 \|CRC16 Check Status Of Data-In Transfer (Read Only)
sahilmgandhi	18:6a4db94011d3	22600	* \| \| \|SD host will check CRC16 correctness after data-in transfer.
sahilmgandhi	18:6a4db94011d3	22601	* \| \| \|0 = Fault.
sahilmgandhi	18:6a4db94011d3	22602	* \| \| \|1 = OK.
sahilmgandhi	18:6a4db94011d3	22603	* \|[4:6] \|CRCSTS \|CRC Status Value Of Data-Out Transfer (Read Only)
sahilmgandhi	18:6a4db94011d3	22604	* \| \| \|SD host will record CRC status of data-out transfer.
sahilmgandhi	18:6a4db94011d3	22605	* \| \| \|Software could use this value to identify what type of error is during data-out transfer.
sahilmgandhi	18:6a4db94011d3	22606	* \| \| \|010 = Positive CRC status.
sahilmgandhi	18:6a4db94011d3	22607	* \| \| \|101 = Negative CRC status.
sahilmgandhi	18:6a4db94011d3	22608	* \| \| \|111 = SD card programming error occurs.
sahilmgandhi	18:6a4db94011d3	22609	* \|[7] \|DAT0STS \|DAT0 Pin Status Of Current Selected SD Port (Read Only)
sahilmgandhi	18:6a4db94011d3	22610	* \| \| \|This bit is the DAT0 pin status of current selected SD port.
sahilmgandhi	18:6a4db94011d3	22611	* \|[8] \|CDIF0 \|SD0 Card Detection Interrupt Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	22612	* \| \| \|This bit indicates that SD card 0 is inserted or removed.
sahilmgandhi	18:6a4db94011d3	22613	* \| \| \|Only when CDIEN0 (SDH_INTEN[8]) is set to 1, this bit is active.
sahilmgandhi	18:6a4db94011d3	22614	* \| \| \|0 = No card is inserted or removed.
sahilmgandhi	18:6a4db94011d3	22615	* \| \| \|1 = There is a card inserted in or removed from SD0.
sahilmgandhi	18:6a4db94011d3	22616	* \| \| \|Note: This bit is read only, but can be cleared by writing '1' to it.
sahilmgandhi	18:6a4db94011d3	22617	* \|[9] \|CDIF1 \|SD1 Card Detection Interrupt Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	22618	* \| \| \|This bit indicates that SD card 1 is inserted or removed.
sahilmgandhi	18:6a4db94011d3	22619	* \| \| \|Only when CDIEN1 (SDH_INTEN[9]) is set to 1, this bit is active.
sahilmgandhi	18:6a4db94011d3	22620	* \| \| \|0 = No card is inserted or removed.
sahilmgandhi	18:6a4db94011d3	22621	* \| \| \|1 = There is a card inserted in or removed from SD1.
sahilmgandhi	18:6a4db94011d3	22622	* \| \| \|Note: This bit is read only, but can be cleared by writing '1' to it.
sahilmgandhi	18:6a4db94011d3	22623	* \|[12] \|RTOIF \|Response Time-Out Interrupt Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	22624	* \| \| \|This bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit).
sahilmgandhi	18:6a4db94011d3	22625	* \| \| \|0 = Not time-out.
sahilmgandhi	18:6a4db94011d3	22626	* \| \| \|1 = Response time-out.
sahilmgandhi	18:6a4db94011d3	22627	* \| \| \|Note: This bit is read only, but can be cleared by writing '1' to it.
sahilmgandhi	18:6a4db94011d3	22628	* \|[13] \|DITOIF \|Data Input Time-Out Interrupt Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	22629	* \| \| \|This bit indicates that SD host counts to time-out value when receiving data (waiting start bit).
sahilmgandhi	18:6a4db94011d3	22630	* \| \| \|0 = Not time-out.
sahilmgandhi	18:6a4db94011d3	22631	* \| \| \|1 = Data input time-out.
sahilmgandhi	18:6a4db94011d3	22632	* \| \| \|Note: This bit is read only, but can be cleared by writing '1' to it.
sahilmgandhi	18:6a4db94011d3	22633	* \|[16] \|CDSTS0 \|Card Detect Status Of SD0 (Read Only)
sahilmgandhi	18:6a4db94011d3	22634	* \| \| \|This bit indicates the card detect pin status of SD0, and is used for card detection.
sahilmgandhi	18:6a4db94011d3	22635	* \| \| \|When there is a card inserted in or removed from SD0, software should check this bit to confirm if there is really a card insertion or removal.
sahilmgandhi	18:6a4db94011d3	22636	* \| \| \|If CDSRC0 (SDH_INTEN[30]) = 0, to select DAT3 for card detection:.
sahilmgandhi	18:6a4db94011d3	22637	* \| \| \|0 = Card removed.
sahilmgandhi	18:6a4db94011d3	22638	* \| \| \|1 = Card inserted.
sahilmgandhi	18:6a4db94011d3	22639	* \| \| \|If CDSRC0 (SDH_INTEN[30]) = 1, to select GPIO for card detection:.
sahilmgandhi	18:6a4db94011d3	22640	* \| \| \|0 = Card inserted.
sahilmgandhi	18:6a4db94011d3	22641	* \| \| \|1 = Card removed.
sahilmgandhi	18:6a4db94011d3	22642	* \|[17] \|CDSTS1 \|Card Detect Status Of SD1 (Read Only)
sahilmgandhi	18:6a4db94011d3	22643	* \| \| \|This bit indicates the card detect pin status of SD1, and is used for card detection.
sahilmgandhi	18:6a4db94011d3	22644	* \| \| \|When there is a card inserted in or removed from SD1, software should check this bit to confirm if there is really a card insertion or removal.
sahilmgandhi	18:6a4db94011d3	22645	* \| \| \|If CDSRC1 (SDH_INTEN[31]) = 0, to select DAT3 for card detection:.
sahilmgandhi	18:6a4db94011d3	22646	* \| \| \|0 = Card removed.
sahilmgandhi	18:6a4db94011d3	22647	* \| \| \|1 = Card inserted.
sahilmgandhi	18:6a4db94011d3	22648	* \| \| \|If CDSRC1 (SDH_INTEN[31]) = 1, to select GPIO for card detection:.
sahilmgandhi	18:6a4db94011d3	22649	* \| \| \|0 = Card inserted.
sahilmgandhi	18:6a4db94011d3	22650	* \| \| \|1 = Card removed.
sahilmgandhi	18:6a4db94011d3	22651	* \|[18] \|DAT1STS \|DAT1 Pin Status Of SD Port (Read Only)
sahilmgandhi	18:6a4db94011d3	22652	* \| \| \|This bit indicates the DAT1 pin status of SD port.
sahilmgandhi	18:6a4db94011d3	22653	*/
sahilmgandhi	18:6a4db94011d3	22654	__IO uint32_t INTSTS;
sahilmgandhi	18:6a4db94011d3	22655
sahilmgandhi	18:6a4db94011d3	22656	/**
sahilmgandhi	18:6a4db94011d3	22657	* RESP0
sahilmgandhi	18:6a4db94011d3	22658	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	22659	* Offset: 0x830 SD Receiving Response Token Register 0
sahilmgandhi	18:6a4db94011d3	22660	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	22661	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	22662	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	22663	* \|[0:31] \|RESPTK0 \|SD Receiving Response Token 0
sahilmgandhi	18:6a4db94011d3	22664	* \| \| \|SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set.
sahilmgandhi	18:6a4db94011d3	22665	* \| \| \|This field contains response bit 47-16 of the response token.
sahilmgandhi	18:6a4db94011d3	22666	*/
sahilmgandhi	18:6a4db94011d3	22667	__I uint32_t RESP0;
sahilmgandhi	18:6a4db94011d3	22668
sahilmgandhi	18:6a4db94011d3	22669	/**
sahilmgandhi	18:6a4db94011d3	22670	* RESP1
sahilmgandhi	18:6a4db94011d3	22671	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	22672	* Offset: 0x834 SD Receiving Response Token Register 1
sahilmgandhi	18:6a4db94011d3	22673	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	22674	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	22675	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	22676	* \|[0:7] \|RESPTK1 \|SD Receiving Response Token 1
sahilmgandhi	18:6a4db94011d3	22677	* \| \| \|SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set.
sahilmgandhi	18:6a4db94011d3	22678	* \| \| \|This register contains the bit 15-8 of the response token.
sahilmgandhi	18:6a4db94011d3	22679	*/
sahilmgandhi	18:6a4db94011d3	22680	__I uint32_t RESP1;
sahilmgandhi	18:6a4db94011d3	22681
sahilmgandhi	18:6a4db94011d3	22682	/**
sahilmgandhi	18:6a4db94011d3	22683	* BLEN
sahilmgandhi	18:6a4db94011d3	22684	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	22685	* Offset: 0x838 SD Block Length Register
sahilmgandhi	18:6a4db94011d3	22686	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	22687	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	22688	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	22689	* \|[0:10] \|BLKLEN \|SD BLOCK LENGTH In Byte Unit
sahilmgandhi	18:6a4db94011d3	22690	* \| \| \|An 11-bit value specifies the SD transfer byte count of a block.
sahilmgandhi	18:6a4db94011d3	22691	* \| \| \|The actual byte count is equal to BLKLEN+1.
sahilmgandhi	18:6a4db94011d3	22692	* \| \| \|Note: The default SD block length is 512 bytes
sahilmgandhi	18:6a4db94011d3	22693	*/
sahilmgandhi	18:6a4db94011d3	22694	__IO uint32_t BLEN;
sahilmgandhi	18:6a4db94011d3	22695
sahilmgandhi	18:6a4db94011d3	22696	/**
sahilmgandhi	18:6a4db94011d3	22697	* TOUT
sahilmgandhi	18:6a4db94011d3	22698	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	22699	* Offset: 0x83C SD Response/Data-in Time-out Register
sahilmgandhi	18:6a4db94011d3	22700	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	22701	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	22702	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	22703	* \|[0:23] \|TOUT \|SD Response/Data-In Time-Out Value
sahilmgandhi	18:6a4db94011d3	22704	* \| \| \|A 24-bit value specifies the time-out counts of response and data input.
sahilmgandhi	18:6a4db94011d3	22705	* \| \| \|SD host controller will wait start bit of response or data-in until this value reached.
sahilmgandhi	18:6a4db94011d3	22706	* \| \| \|The time period depends on SD engine clock frequency.
sahilmgandhi	18:6a4db94011d3	22707	* \| \| \|Do not write a small number into this field, or you may never get response or data due to time-out.
sahilmgandhi	18:6a4db94011d3	22708	* \| \| \|Note: Filling 0x0 into this field will disable hardware time-out function.
sahilmgandhi	18:6a4db94011d3	22709	*/
sahilmgandhi	18:6a4db94011d3	22710	__IO uint32_t TOUT;
sahilmgandhi	18:6a4db94011d3	22711
sahilmgandhi	18:6a4db94011d3	22712	} SDH_T;
sahilmgandhi	18:6a4db94011d3	22713
sahilmgandhi	18:6a4db94011d3	22714	/**
sahilmgandhi	18:6a4db94011d3	22715	@addtogroup SDH_CONST SDH Bit Field Definition
sahilmgandhi	18:6a4db94011d3	22716	Constant Definitions for SDH Controller
sahilmgandhi	18:6a4db94011d3	22717	@{ */
sahilmgandhi	18:6a4db94011d3	22718
sahilmgandhi	18:6a4db94011d3	22719	#define SDH_DMACTL_DMAEN_Pos (0) /!< SDH DMACTL: DMAEN Position /
sahilmgandhi	18:6a4db94011d3	22720	#define SDH_DMACTL_DMAEN_Msk (0x1ul << SDH_DMACTL_DMAEN_Pos) /!< SDH DMACTL: DMAEN Mask /
sahilmgandhi	18:6a4db94011d3	22721
sahilmgandhi	18:6a4db94011d3	22722	#define SDH_DMACTL_DMARST_Pos (1) /!< SDH DMACTL: DMARST Position /
sahilmgandhi	18:6a4db94011d3	22723	#define SDH_DMACTL_DMARST_Msk (0x1ul << SDH_DMACTL_DMARST_Pos) /!< SDH DMACTL: DMARST Mask /
sahilmgandhi	18:6a4db94011d3	22724
sahilmgandhi	18:6a4db94011d3	22725	#define SDH_DMACTL_SGEN_Pos (3) /!< SDH DMACTL: SGEN Position /
sahilmgandhi	18:6a4db94011d3	22726	#define SDH_DMACTL_SGEN_Msk (0x1ul << SDH_DMACTL_SGEN_Pos) /!< SDH DMACTL: SGEN Mask /
sahilmgandhi	18:6a4db94011d3	22727
sahilmgandhi	18:6a4db94011d3	22728	#define SDH_DMACTL_DMABUSY_Pos (9) /!< SDH DMACTL: DMABUSY Position /
sahilmgandhi	18:6a4db94011d3	22729	#define SDH_DMACTL_DMABUSY_Msk (0x1ul << SDH_DMACTL_DMABUSY_Pos) /!< SDH DMACTL: DMABUSY Mask /
sahilmgandhi	18:6a4db94011d3	22730
sahilmgandhi	18:6a4db94011d3	22731	#define SDH_DMASA_ORDER_Pos (0) /!< SDH DMASA: ORDER Position /
sahilmgandhi	18:6a4db94011d3	22732	#define SDH_DMASA_ORDER_Msk (0x1ul << SDH_DMASA_ORDER_Pos) /!< SDH DMASA: ORDER Mask /
sahilmgandhi	18:6a4db94011d3	22733
sahilmgandhi	18:6a4db94011d3	22734	#define SDH_DMASA_DMASA_Pos (1) /!< SDH DMASA: DMASA Position /
sahilmgandhi	18:6a4db94011d3	22735	#define SDH_DMASA_DMASA_Msk (0x7ffffffful << SDH_DMASA_DMASA_Pos) /!< SDH DMASA: DMASA Mask /
sahilmgandhi	18:6a4db94011d3	22736
sahilmgandhi	18:6a4db94011d3	22737	#define SDH_DMABCNT_BCNT_Pos (0) /!< SDH DMABCNT: BCNT Position /
sahilmgandhi	18:6a4db94011d3	22738	#define SDH_DMABCNT_BCNT_Msk (0x3fffffful << SDH_DMABCNT_BCNT_Pos) /!< SDH DMABCNT: BCNT Mask /
sahilmgandhi	18:6a4db94011d3	22739
sahilmgandhi	18:6a4db94011d3	22740	#define SDH_DMAINTEN_ABORTIEN_Pos (0) /!< SDH DMAINTEN: ABORTIEN Position /
sahilmgandhi	18:6a4db94011d3	22741	#define SDH_DMAINTEN_ABORTIEN_Msk (0x1ul << SDH_DMAINTEN_ABORTIEN_Pos) /!< SDH DMAINTEN: ABORTIEN Mask /
sahilmgandhi	18:6a4db94011d3	22742
sahilmgandhi	18:6a4db94011d3	22743	#define SDH_DMAINTEN_WEOTIEN_Pos (1) /!< SDH DMAINTEN: WEOTIEN Position /
sahilmgandhi	18:6a4db94011d3	22744	#define SDH_DMAINTEN_WEOTIEN_Msk (0x1ul << SDH_DMAINTEN_WEOTIEN_Pos) /!< SDH DMAINTEN: WEOTIEN Mask /
sahilmgandhi	18:6a4db94011d3	22745
sahilmgandhi	18:6a4db94011d3	22746	#define SDH_DMAINTSTS_ABORTIF_Pos (0) /!< SDH DMAINTSTS: ABORTIF Position /
sahilmgandhi	18:6a4db94011d3	22747	#define SDH_DMAINTSTS_ABORTIF_Msk (0x1ul << SDH_DMAINTSTS_ABORTIF_Pos) /!< SDH DMAINTSTS: ABORTIF Mask /
sahilmgandhi	18:6a4db94011d3	22748
sahilmgandhi	18:6a4db94011d3	22749	#define SDH_DMAINTSTS_WEOTIF_Pos (1) /!< SDH DMAINTSTS: WEOTIF Position /
sahilmgandhi	18:6a4db94011d3	22750	#define SDH_DMAINTSTS_WEOTIF_Msk (0x1ul << SDH_DMAINTSTS_WEOTIF_Pos) /!< SDH DMAINTSTS: WEOTIF Mask /
sahilmgandhi	18:6a4db94011d3	22751
sahilmgandhi	18:6a4db94011d3	22752	#define SDH_GCTL_GCTLRST_Pos (0) /!< SDH GCTL: GCTLRST Position /
sahilmgandhi	18:6a4db94011d3	22753	#define SDH_GCTL_GCTLRST_Msk (0x1ul << SDH_GCTL_GCTLRST_Pos) /!< SDH GCTL: GCTLRST Mask /
sahilmgandhi	18:6a4db94011d3	22754
sahilmgandhi	18:6a4db94011d3	22755	#define SDH_GCTL_SDEN_Pos (1) /!< SDH GCTL: SDEN Position /
sahilmgandhi	18:6a4db94011d3	22756	#define SDH_GCTL_SDEN_Msk (0x1ul << SDH_GCTL_SDEN_Pos) /!< SDH GCTL: SDEN Mask /
sahilmgandhi	18:6a4db94011d3	22757
sahilmgandhi	18:6a4db94011d3	22758	#define SDH_GINTEN_DTAIEN_Pos (0) /!< SDH GINTEN: DTAIEN Position /
sahilmgandhi	18:6a4db94011d3	22759	#define SDH_GINTEN_DTAIEN_Msk (0x1ul << SDH_GINTEN_DTAIEN_Pos) /!< SDH GINTEN: DTAIEN Mask /
sahilmgandhi	18:6a4db94011d3	22760
sahilmgandhi	18:6a4db94011d3	22761	#define SDH_GINTSTS_DTAIF_Pos (0) /!< SDH GINTSTS: DTAIF Position /
sahilmgandhi	18:6a4db94011d3	22762	#define SDH_GINTSTS_DTAIF_Msk (0x1ul << SDH_GINTSTS_DTAIF_Pos) /!< SDH GINTSTS: DTAIF Mask /
sahilmgandhi	18:6a4db94011d3	22763
sahilmgandhi	18:6a4db94011d3	22764	#define SDH_CTL_COEN_Pos (0) /!< SDH CTL: COEN Position /
sahilmgandhi	18:6a4db94011d3	22765	#define SDH_CTL_COEN_Msk (0x1ul << SDH_CTL_COEN_Pos) /!< SDH CTL: COEN Mask /
sahilmgandhi	18:6a4db94011d3	22766
sahilmgandhi	18:6a4db94011d3	22767	#define SDH_CTL_RIEN_Pos (1) /!< SDH CTL: RIEN Position /
sahilmgandhi	18:6a4db94011d3	22768	#define SDH_CTL_RIEN_Msk (0x1ul << SDH_CTL_RIEN_Pos) /!< SDH CTL: RIEN Mask /
sahilmgandhi	18:6a4db94011d3	22769
sahilmgandhi	18:6a4db94011d3	22770	#define SDH_CTL_DIEN_Pos (2) /!< SDH CTL: DIEN Position /
sahilmgandhi	18:6a4db94011d3	22771	#define SDH_CTL_DIEN_Msk (0x1ul << SDH_CTL_DIEN_Pos) /!< SDH CTL: DIEN Mask /
sahilmgandhi	18:6a4db94011d3	22772
sahilmgandhi	18:6a4db94011d3	22773	#define SDH_CTL_DOEN_Pos (3) /!< SDH CTL: DOEN Position /
sahilmgandhi	18:6a4db94011d3	22774	#define SDH_CTL_DOEN_Msk (0x1ul << SDH_CTL_DOEN_Pos) /!< SDH CTL: DOEN Mask /
sahilmgandhi	18:6a4db94011d3	22775
sahilmgandhi	18:6a4db94011d3	22776	#define SDH_CTL_R2EN_Pos (4) /!< SDH CTL: R2EN Position /
sahilmgandhi	18:6a4db94011d3	22777	#define SDH_CTL_R2EN_Msk (0x1ul << SDH_CTL_R2EN_Pos) /!< SDH CTL: R2EN Mask /
sahilmgandhi	18:6a4db94011d3	22778
sahilmgandhi	18:6a4db94011d3	22779	#define SDH_CTL_CLK74OEN_Pos (5) /!< SDH CTL: CLK74OEN Position /
sahilmgandhi	18:6a4db94011d3	22780	#define SDH_CTL_CLK74OEN_Msk (0x1ul << SDH_CTL_CLK74OEN_Pos) /!< SDH CTL: CLK74OEN Mask /
sahilmgandhi	18:6a4db94011d3	22781
sahilmgandhi	18:6a4db94011d3	22782	#define SDH_CTL_CLK8OEN_Pos (6) /!< SDH CTL: CLK8OEN Position /
sahilmgandhi	18:6a4db94011d3	22783	#define SDH_CTL_CLK8OEN_Msk (0x1ul << SDH_CTL_CLK8OEN_Pos) /!< SDH CTL: CLK8OEN Mask /
sahilmgandhi	18:6a4db94011d3	22784
sahilmgandhi	18:6a4db94011d3	22785	#define SDH_CTL_CLKKEEP0_Pos (7) /!< SDH CTL: CLKKEEP0 Position /
sahilmgandhi	18:6a4db94011d3	22786	#define SDH_CTL_CLKKEEP0_Msk (0x1ul << SDH_CTL_CLKKEEP0_Pos) /!< SDH CTL: CLKKEEP0 Mask /
sahilmgandhi	18:6a4db94011d3	22787
sahilmgandhi	18:6a4db94011d3	22788	#define SDH_CTL_CMDCODE_Pos (8) /!< SDH CTL: CMDCODE Position /
sahilmgandhi	18:6a4db94011d3	22789	#define SDH_CTL_CMDCODE_Msk (0x3ful << SDH_CTL_CMDCODE_Pos) /!< SDH CTL: CMDCODE Mask /
sahilmgandhi	18:6a4db94011d3	22790
sahilmgandhi	18:6a4db94011d3	22791	#define SDH_CTL_CTLRST_Pos (14) /!< SDH CTL: CTLRST Position /
sahilmgandhi	18:6a4db94011d3	22792	#define SDH_CTL_CTLRST_Msk (0x1ul << SDH_CTL_CTLRST_Pos) /!< SDH CTL: CTLRST Mask /
sahilmgandhi	18:6a4db94011d3	22793
sahilmgandhi	18:6a4db94011d3	22794	#define SDH_CTL_DBW_Pos (15) /!< SDH CTL: DBW Position /
sahilmgandhi	18:6a4db94011d3	22795	#define SDH_CTL_DBW_Msk (0x1ul << SDH_CTL_DBW_Pos) /!< SDH CTL: DBW Mask /
sahilmgandhi	18:6a4db94011d3	22796
sahilmgandhi	18:6a4db94011d3	22797	#define SDH_CTL_BLKCNT_Pos (16) /!< SDH CTL: BLKCNT Position /
sahilmgandhi	18:6a4db94011d3	22798	#define SDH_CTL_BLKCNT_Msk (0xfful << SDH_CTL_BLKCNT_Pos) /!< SDH CTL: BLKCNT Mask /
sahilmgandhi	18:6a4db94011d3	22799
sahilmgandhi	18:6a4db94011d3	22800	#define SDH_CTL_SDNWR_Pos (24) /!< SDH CTL: SDNWR Position /
sahilmgandhi	18:6a4db94011d3	22801	#define SDH_CTL_SDNWR_Msk (0xful << SDH_CTL_SDNWR_Pos) /!< SDH CTL: SDNWR Mask /
sahilmgandhi	18:6a4db94011d3	22802
sahilmgandhi	18:6a4db94011d3	22803	#define SDH_CTL_SDPORT_Pos (29) /!< SDH CTL: SDPORT Position /
sahilmgandhi	18:6a4db94011d3	22804	#define SDH_CTL_SDPORT_Msk (0x3ul << SDH_CTL_SDPORT_Pos) /!< SDH CTL: SDPORT Mask /
sahilmgandhi	18:6a4db94011d3	22805
sahilmgandhi	18:6a4db94011d3	22806	#define SDH_CTL_CLKKEEP1_Pos (31) /!< SDH CTL: CLKKEEP1 Position /
sahilmgandhi	18:6a4db94011d3	22807	#define SDH_CTL_CLKKEEP1_Msk (0x1ul << SDH_CTL_CLKKEEP1_Pos) /!< SDH CTL: CLKKEEP1 Mask /
sahilmgandhi	18:6a4db94011d3	22808
sahilmgandhi	18:6a4db94011d3	22809	#define SDH_CMDARG_ARGUMENT_Pos (0) /!< SDH CMDARG: ARGUMENT Position /
sahilmgandhi	18:6a4db94011d3	22810	#define SDH_CMDARG_ARGUMENT_Msk (0xfffffffful << SDH_CMDARG_ARGUMENT_Pos) /!< SDH CMDARG: ARGUMENT Mask /
sahilmgandhi	18:6a4db94011d3	22811
sahilmgandhi	18:6a4db94011d3	22812	#define SDH_INTEN_BLKDIEN_Pos (0) /!< SDH INTEN: BLKDIEN Position /
sahilmgandhi	18:6a4db94011d3	22813	#define SDH_INTEN_BLKDIEN_Msk (0x1ul << SDH_INTEN_BLKDIEN_Pos) /!< SDH INTEN: BLKDIEN Mask /
sahilmgandhi	18:6a4db94011d3	22814
sahilmgandhi	18:6a4db94011d3	22815	#define SDH_INTEN_CRCIEN_Pos (1) /!< SDH INTEN: CRCIEN Position /
sahilmgandhi	18:6a4db94011d3	22816	#define SDH_INTEN_CRCIEN_Msk (0x1ul << SDH_INTEN_CRCIEN_Pos) /!< SDH INTEN: CRCIEN Mask /
sahilmgandhi	18:6a4db94011d3	22817
sahilmgandhi	18:6a4db94011d3	22818	#define SDH_INTEN_CDIEN0_Pos (8) /!< SDH INTEN: CDIEN0 Position /
sahilmgandhi	18:6a4db94011d3	22819	#define SDH_INTEN_CDIEN0_Msk (0x1ul << SDH_INTEN_CDIEN0_Pos) /!< SDH INTEN: CDIEN0 Mask /
sahilmgandhi	18:6a4db94011d3	22820
sahilmgandhi	18:6a4db94011d3	22821	#define SDH_INTEN_CDIEN1_Pos (9) /!< SDH INTEN: CDIEN1 Position /
sahilmgandhi	18:6a4db94011d3	22822	#define SDH_INTEN_CDIEN1_Msk (0x1ul << SDH_INTEN_CDIEN1_Pos) /!< SDH INTEN: CDIEN1 Mask /
sahilmgandhi	18:6a4db94011d3	22823
sahilmgandhi	18:6a4db94011d3	22824	#define SDH_INTEN_SDHOST0IEN_Pos (10) /!< SDH INTSTS: SDHOST0IEN Position /
sahilmgandhi	18:6a4db94011d3	22825	#define SDH_INTEN_SDHOST0IEN_Msk (0x1ul << SDH_INTEN_SDHOST0IEN_Pos) /!< SDH INTSTS: SDHOST0IEN Mask /
sahilmgandhi	18:6a4db94011d3	22826
sahilmgandhi	18:6a4db94011d3	22827	#define SDH_INTEN_SDHOST1IEN_Pos (11) /!< SDH INTSTS: SDHOST1IEN Position /
sahilmgandhi	18:6a4db94011d3	22828	#define SDH_INTEN_SDHOST1IEN_Msk (0x1ul << SDH_INTEN_SDHOST1IEN_Pos) /!< SDH INTSTS: SDHOST1IEN Mask /
sahilmgandhi	18:6a4db94011d3	22829
sahilmgandhi	18:6a4db94011d3	22830	#define SDH_INTEN_RTOIEN_Pos (12) /!< SDH INTEN: RTOIEN Position /
sahilmgandhi	18:6a4db94011d3	22831	#define SDH_INTEN_RTOIEN_Msk (0x1ul << SDH_INTEN_RTOIEN_Pos) /!< SDH INTEN: RTOIEN Mask /
sahilmgandhi	18:6a4db94011d3	22832
sahilmgandhi	18:6a4db94011d3	22833	#define SDH_INTEN_DITOIEN_Pos (13) /!< SDH INTEN: DITOIEN Position /
sahilmgandhi	18:6a4db94011d3	22834	#define SDH_INTEN_DITOIEN_Msk (0x1ul << SDH_INTEN_DITOIEN_Pos) /!< SDH INTEN: DITOIEN Mask /
sahilmgandhi	18:6a4db94011d3	22835
sahilmgandhi	18:6a4db94011d3	22836	#define SDH_INTEN_WKIEN_Pos (14) /!< SDH INTEN: WKIEN Position /
sahilmgandhi	18:6a4db94011d3	22837	#define SDH_INTEN_WKIEN_Msk (0x1ul << SDH_INTEN_WKIEN_Pos) /!< SDH INTEN: WKIEN Mask /
sahilmgandhi	18:6a4db94011d3	22838
sahilmgandhi	18:6a4db94011d3	22839	#define SDH_INTEN_CDSRC0_Pos (30) /!< SDH INTEN: CDSRC0 Position /
sahilmgandhi	18:6a4db94011d3	22840	#define SDH_INTEN_CDSRC0_Msk (0x1ul << SDH_INTEN_CDSRC0_Pos) /!< SDH INTEN: CDSRC0 Mask /
sahilmgandhi	18:6a4db94011d3	22841
sahilmgandhi	18:6a4db94011d3	22842	#define SDH_INTEN_CDSRC1_Pos (31) /!< SDH INTEN: CDSRC1 Position /
sahilmgandhi	18:6a4db94011d3	22843	#define SDH_INTEN_CDSRC1_Msk (0x1ul << SDH_INTEN_CDSRC1_Pos) /!< SDH INTEN: CDSRC1 Mask /
sahilmgandhi	18:6a4db94011d3	22844
sahilmgandhi	18:6a4db94011d3	22845	#define SDH_INTSTS_BLKDIF_Pos (0) /!< SDH INTSTS: BLKDIF Position /
sahilmgandhi	18:6a4db94011d3	22846	#define SDH_INTSTS_BLKDIF_Msk (0x1ul << SDH_INTSTS_BLKDIF_Pos) /!< SDH INTSTS: BLKDIF Mask /
sahilmgandhi	18:6a4db94011d3	22847
sahilmgandhi	18:6a4db94011d3	22848	#define SDH_INTSTS_CRCIF_Pos (1) /!< SDH INTSTS: CRCIF Position /
sahilmgandhi	18:6a4db94011d3	22849	#define SDH_INTSTS_CRCIF_Msk (0x1ul << SDH_INTSTS_CRCIF_Pos) /!< SDH INTSTS: CRCIF Mask /
sahilmgandhi	18:6a4db94011d3	22850
sahilmgandhi	18:6a4db94011d3	22851	#define SDH_INTSTS_CRC7_Pos (2) /!< SDH INTSTS: CRC7 Position /
sahilmgandhi	18:6a4db94011d3	22852	#define SDH_INTSTS_CRC7_Msk (0x1ul << SDH_INTSTS_CRC7_Pos) /!< SDH INTSTS: CRC7 Mask /
sahilmgandhi	18:6a4db94011d3	22853
sahilmgandhi	18:6a4db94011d3	22854	#define SDH_INTSTS_CRC16_Pos (3) /!< SDH INTSTS: CRC16 Position /
sahilmgandhi	18:6a4db94011d3	22855	#define SDH_INTSTS_CRC16_Msk (0x1ul << SDH_INTSTS_CRC16_Pos) /!< SDH INTSTS: CRC16 Mask /
sahilmgandhi	18:6a4db94011d3	22856
sahilmgandhi	18:6a4db94011d3	22857	#define SDH_INTSTS_CRCSTS_Pos (4) /!< SDH INTSTS: CRCSTS Position /
sahilmgandhi	18:6a4db94011d3	22858	#define SDH_INTSTS_CRCSTS_Msk (0x7ul << SDH_INTSTS_CRCSTS_Pos) /!< SDH INTSTS: CRCSTS Mask /
sahilmgandhi	18:6a4db94011d3	22859
sahilmgandhi	18:6a4db94011d3	22860	#define SDH_INTSTS_DAT0STS_Pos (7) /!< SDH INTSTS: DAT0STS Position /
sahilmgandhi	18:6a4db94011d3	22861	#define SDH_INTSTS_DAT0STS_Msk (0x1ul << SDH_INTSTS_DAT0STS_Pos) /!< SDH INTSTS: DAT0STS Mask /
sahilmgandhi	18:6a4db94011d3	22862
sahilmgandhi	18:6a4db94011d3	22863	#define SDH_INTSTS_CDIF0_Pos (8) /!< SDH INTSTS: CDIF0 Position /
sahilmgandhi	18:6a4db94011d3	22864	#define SDH_INTSTS_CDIF0_Msk (0x1ul << SDH_INTSTS_CDIF0_Pos) /!< SDH INTSTS: CDIF0 Mask /
sahilmgandhi	18:6a4db94011d3	22865
sahilmgandhi	18:6a4db94011d3	22866	#define SDH_INTSTS_CDIF1_Pos (9) /!< SDH INTSTS: CDIF1 Position /
sahilmgandhi	18:6a4db94011d3	22867	#define SDH_INTSTS_CDIF1_Msk (0x1ul << SDH_INTSTS_CDIF1_Pos) /!< SDH INTSTS: CDIF1 Mask /
sahilmgandhi	18:6a4db94011d3	22868
sahilmgandhi	18:6a4db94011d3	22869	#define SDH_INTSTS_SDHOST0IF_Pos (10) /!< SDH INTSTS: SDHOST0IF Position /
sahilmgandhi	18:6a4db94011d3	22870	#define SDH_INTSTS_SDHOST0IF_Msk (0x1ul << SDH_INTSTS_SDHOST0IF_Pos) /!< SDH INTSTS: SDHOST0IF Mask /
sahilmgandhi	18:6a4db94011d3	22871
sahilmgandhi	18:6a4db94011d3	22872	#define SDH_INTSTS_SDHOST1IF_Pos (11) /!< SDH INTSTS: SDHOST1IF Position /
sahilmgandhi	18:6a4db94011d3	22873	#define SDH_INTSTS_SDHOST1IF_Msk (0x1ul << SDH_INTSTS_SDHOST1IF_Pos) /!< SDH INTSTS: SDHOST1IF Mask /
sahilmgandhi	18:6a4db94011d3	22874
sahilmgandhi	18:6a4db94011d3	22875	#define SDH_INTSTS_RTOIF_Pos (12) /!< SDH INTSTS: RTOIF Position /
sahilmgandhi	18:6a4db94011d3	22876	#define SDH_INTSTS_RTOIF_Msk (0x1ul << SDH_INTSTS_RTOIF_Pos) /!< SDH INTSTS: RTOIF Mask /
sahilmgandhi	18:6a4db94011d3	22877
sahilmgandhi	18:6a4db94011d3	22878	#define SDH_INTSTS_DINTOIF_Pos (13) /!< SDH INTSTS: DINTOIF Position /
sahilmgandhi	18:6a4db94011d3	22879	#define SDH_INTSTS_DINTOIF_Msk (0x1ul << SDH_INTSTS_DINTOIF_Pos) /!< SDH INTSTS: DINTOIF Mask /
sahilmgandhi	18:6a4db94011d3	22880
sahilmgandhi	18:6a4db94011d3	22881	#define SDH_INTSTS_CDSTS0_Pos (16) /!< SDH INTSTS: CDSTS0 Position /
sahilmgandhi	18:6a4db94011d3	22882	#define SDH_INTSTS_CDSTS0_Msk (0x1ul << SDH_INTSTS_CDSTS0_Pos) /!< SDH INTSTS: CDSTS0 Mask /
sahilmgandhi	18:6a4db94011d3	22883
sahilmgandhi	18:6a4db94011d3	22884	#define SDH_INTSTS_CDSTS1_Pos (17) /!< SDH INTSTS: CDSTS1 Position /
sahilmgandhi	18:6a4db94011d3	22885	#define SDH_INTSTS_CDSTS1_Msk (0x1ul << SDH_INTSTS_CDSTS1_Pos) /!< SDH INTSTS: CDSTS1 Mask /
sahilmgandhi	18:6a4db94011d3	22886
sahilmgandhi	18:6a4db94011d3	22887	#define SDH_INTSTS_DAT1STS_Pos (18) /!< SDH INTSTS: DAT1STS Position /
sahilmgandhi	18:6a4db94011d3	22888	#define SDH_INTSTS_DAT1STS_Msk (0x1ul << SDH_INTSTS_DAT1STS_Pos) /!< SDH INTSTS: DAT1STS Mask /
sahilmgandhi	18:6a4db94011d3	22889
sahilmgandhi	18:6a4db94011d3	22890	#define SDH_RESP0_RESPTK0_Pos (0) /!< SDH RESP0: RESPTK0 Position /
sahilmgandhi	18:6a4db94011d3	22891	#define SDH_RESP0_RESPTK0_Msk (0xfffffffful << SDH_RESP0_RESPTK0_Pos) /!< SDH RESP0: RESPTK0 Mask /
sahilmgandhi	18:6a4db94011d3	22892
sahilmgandhi	18:6a4db94011d3	22893	#define SDH_RESP1_RESPTK1_Pos (0) /!< SDH RESP1: RESPTK1 Position /
sahilmgandhi	18:6a4db94011d3	22894	#define SDH_RESP1_RESPTK1_Msk (0xfful << SDH_RESP1_RESPTK1_Pos) /!< SDH RESP1: RESPTK1 Mask /
sahilmgandhi	18:6a4db94011d3	22895
sahilmgandhi	18:6a4db94011d3	22896	#define SDH_BLEN_BLKLEN_Pos (0) /!< SDH BLEN: BLKLEN Position /
sahilmgandhi	18:6a4db94011d3	22897	#define SDH_BLEN_BLKLEN_Msk (0x7fful << SDH_BLEN_BLKLEN_Pos) /!< SDH BLEN: BLKLEN Mask /
sahilmgandhi	18:6a4db94011d3	22898
sahilmgandhi	18:6a4db94011d3	22899	#define SDH_TOUT_TOUT_Pos (0) /!< SDH TOUT: TOUT Position /
sahilmgandhi	18:6a4db94011d3	22900	#define SDH_TOUT_TOUT_Msk (0xfffffful << SDH_TOUT_TOUT_Pos) /!< SDH TOUT: TOUT Mask /
sahilmgandhi	18:6a4db94011d3	22901
sahilmgandhi	18:6a4db94011d3	22902	/*@}/ /* SDH_CONST */
sahilmgandhi	18:6a4db94011d3	22903	/*@}/ /* end of SDH register group */
sahilmgandhi	18:6a4db94011d3	22904
sahilmgandhi	18:6a4db94011d3	22905
sahilmgandhi	18:6a4db94011d3	22906	/---------------------- Serial Peripheral Interface Controller -------------------------/
sahilmgandhi	18:6a4db94011d3	22907	/**
sahilmgandhi	18:6a4db94011d3	22908	@addtogroup SPI Serial Peripheral Interface Controller(SPI)
sahilmgandhi	18:6a4db94011d3	22909	Memory Mapped Structure for SPI Controller
sahilmgandhi	18:6a4db94011d3	22910	@{ */
sahilmgandhi	18:6a4db94011d3	22911
sahilmgandhi	18:6a4db94011d3	22912	typedef struct {
sahilmgandhi	18:6a4db94011d3	22913
sahilmgandhi	18:6a4db94011d3	22914
sahilmgandhi	18:6a4db94011d3	22915	/**
sahilmgandhi	18:6a4db94011d3	22916	* CTL
sahilmgandhi	18:6a4db94011d3	22917	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	22918	* Offset: 0x00 SPI Control Register
sahilmgandhi	18:6a4db94011d3	22919	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	22920	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	22921	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	22922	* \|[0] \|SPIEN \|SPI Transfer Control Enable Control
sahilmgandhi	18:6a4db94011d3	22923	* \| \| \|0 = Transfer control Disabled.
sahilmgandhi	18:6a4db94011d3	22924	* \| \| \|1 = Transfer control Enabled.
sahilmgandhi	18:6a4db94011d3	22925	* \| \| \|Note1: In Master mode, the transfer will start when there is data in the FIFO buffer after this is set to 1.
sahilmgandhi	18:6a4db94011d3	22926	* \| \| \|In Slave mode, this device is ready to receive data when this bit is set to 1.
sahilmgandhi	18:6a4db94011d3	22927	* \| \| \|Note2: All configurations should be set before writing 1 to this SPIEN bit.
sahilmgandhi	18:6a4db94011d3	22928	* \| \| \|(eg: TXNEG, RXNEG, DWIDTH, LSB, CLKPOL, and so on).
sahilmgandhi	18:6a4db94011d3	22929	* \|[1] \|RXNEG \|Receive On Negative Edge
sahilmgandhi	18:6a4db94011d3	22930	* \| \| \|0 = Received data input signal is latched on the rising edge of SPICLK.
sahilmgandhi	18:6a4db94011d3	22931	* \| \| \|1 = Received data input signal is latched on the falling edge of SPICLK.
sahilmgandhi	18:6a4db94011d3	22932	* \|[2] \|TXNEG \|Transmit On Negative Edge
sahilmgandhi	18:6a4db94011d3	22933	* \| \| \|0 = Transmitted data output signal is changed on the rising edge of SPICLK.
sahilmgandhi	18:6a4db94011d3	22934	* \| \| \|1 = Transmitted data output signal is changed on the falling edge of SPICLK.
sahilmgandhi	18:6a4db94011d3	22935	* \|[3] \|CLKPOL \|Clock Polarity
sahilmgandhi	18:6a4db94011d3	22936	* \| \| \|0 = SPICLK is idle low.
sahilmgandhi	18:6a4db94011d3	22937	* \| \| \|1 = SPICLK is idle high.
sahilmgandhi	18:6a4db94011d3	22938	* \|[4:7] \|SUSPITV \|Suspend Interval (Master Only)
sahilmgandhi	18:6a4db94011d3	22939	* \| \| \|SUSPITV = 0x0 ... 0.5 SPICLK clock cycle.
sahilmgandhi	18:6a4db94011d3	22940	* \| \| \|SUSPITV = 0x1 ... 1.5 SPICLK clock cycle.
sahilmgandhi	18:6a4db94011d3	22941	* \| \| \|......
sahilmgandhi	18:6a4db94011d3	22942	* \| \| \|SUSPITV = 0xE ... 14.5 SPICLK clock cycle.
sahilmgandhi	18:6a4db94011d3	22943	* \| \| \|SUSPITV = 0xF ... 15.5 SPICLK clock cycle.
sahilmgandhi	18:6a4db94011d3	22944	* \| \| \|Note: The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer.
sahilmgandhi	18:6a4db94011d3	22945	* \| \| \|The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word.
sahilmgandhi	18:6a4db94011d3	22946	* \| \| \|The default value is 0x3.
sahilmgandhi	18:6a4db94011d3	22947	* \| \| \|The period of the suspend interval is obtained according to the following equation.
sahilmgandhi	18:6a4db94011d3	22948	* \| \| \|(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle
sahilmgandhi	18:6a4db94011d3	22949	* \|[8:12] \|DWIDTH \|Data Transmit Bit Width
sahilmgandhi	18:6a4db94011d3	22950	* \| \| \|This field specifies how many bits can be transmitted / received in one transaction.
sahilmgandhi	18:6a4db94011d3	22951	* \| \| \|The minimum bit length is 8 bits and can up to 32 bits.
sahilmgandhi	18:6a4db94011d3	22952	* \| \| \|DWIDTH = 0x08 ... 8 bits.
sahilmgandhi	18:6a4db94011d3	22953	* \| \| \|DWIDTH = 0x09 ... 9 bits.
sahilmgandhi	18:6a4db94011d3	22954	* \| \| \|......
sahilmgandhi	18:6a4db94011d3	22955	* \| \| \|DWIDTH = 0x1F ... 31 bits.
sahilmgandhi	18:6a4db94011d3	22956	* \| \| \|DWIDTH = 0x00 ... 32 bits.
sahilmgandhi	18:6a4db94011d3	22957	* \|[13] \|LSB \|Send LSB First
sahilmgandhi	18:6a4db94011d3	22958	* \| \| \|0 = MSB first.
sahilmgandhi	18:6a4db94011d3	22959	* \| \| \|1 = LSB first.
sahilmgandhi	18:6a4db94011d3	22960	* \| \| \|Note1: The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX).
sahilmgandhi	18:6a4db94011d3	22961	* \| \| \|Note2: The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
sahilmgandhi	18:6a4db94011d3	22962	* \|[16] \|TWOBIT \|2-Bit Mode Enable Control
sahilmgandhi	18:6a4db94011d3	22963	* \| \| \|0 = 2-bit mode Disabled.
sahilmgandhi	18:6a4db94011d3	22964	* \| \| \|1 = 2-bit mode Enabled.
sahilmgandhi	18:6a4db94011d3	22965	* \| \| \|Note: When 2-bit mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd
sahilmgandhi	18:6a4db94011d3	22966	* \| \| \|serial transmitted bit data is from the second FIFO buffer data.
sahilmgandhi	18:6a4db94011d3	22967	* \| \| \|As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
sahilmgandhi	18:6a4db94011d3	22968	* \|[17] \|UNITIEN \|Unit Transfer Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	22969	* \| \| \|0 = SPI unit transfer interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	22970	* \| \| \|1 = SPI unit transfer interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	22971	* \|[18] \|SLAVE \|Slave Mode Enable Control
sahilmgandhi	18:6a4db94011d3	22972	* \| \| \|0 = Master mode.
sahilmgandhi	18:6a4db94011d3	22973	* \| \| \|1 = Slave mode.
sahilmgandhi	18:6a4db94011d3	22974	* \|[19] \|REORDER \|Byte Reorder Function Enable Control
sahilmgandhi	18:6a4db94011d3	22975	* \| \| \|0 = Byte reorder function Disabled.
sahilmgandhi	18:6a4db94011d3	22976	* \| \| \|1 = Byte reorder function Enabled.
sahilmgandhi	18:6a4db94011d3	22977	* \| \| \|Note1: Byte reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
sahilmgandhi	18:6a4db94011d3	22978	* \| \| \|Note2: The byte reorder function is not supported when the Quad or Dual I/O mode is enabled.
sahilmgandhi	18:6a4db94011d3	22979	* \| \| \|Note3: A byte suspend interval will be inserted among each byte.
sahilmgandhi	18:6a4db94011d3	22980	* \| \| \|The period of the byte suspend interval depends on the setting of SUSPITV.
sahilmgandhi	18:6a4db94011d3	22981	* \|[20] \|QDIODIR \|Quad Or Dual I/O Mode Direction Control
sahilmgandhi	18:6a4db94011d3	22982	* \| \| \|0 = Quad or Dual Input mode.
sahilmgandhi	18:6a4db94011d3	22983	* \| \| \|1 = Quad or Dual Output mode.
sahilmgandhi	18:6a4db94011d3	22984	* \|[21] \|DUALIOEN \|Dual I/O Mode Enable Control
sahilmgandhi	18:6a4db94011d3	22985	* \| \| \|0 = Dual I/O mode Disabled.
sahilmgandhi	18:6a4db94011d3	22986	* \| \| \|1 = Dual I/O mode Enabled.
sahilmgandhi	18:6a4db94011d3	22987	* \|[22] \|QUADIOEN \|Quad I/O Mode Enable Control
sahilmgandhi	18:6a4db94011d3	22988	* \| \| \|0 = Quad I/O mode Disabled.
sahilmgandhi	18:6a4db94011d3	22989	* \| \| \|1 = Quad I/O mode Enabled.
sahilmgandhi	18:6a4db94011d3	22990	*/
sahilmgandhi	18:6a4db94011d3	22991	__IO uint32_t CTL;
sahilmgandhi	18:6a4db94011d3	22992
sahilmgandhi	18:6a4db94011d3	22993	/**
sahilmgandhi	18:6a4db94011d3	22994	* CLKDIV
sahilmgandhi	18:6a4db94011d3	22995	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	22996	* Offset: 0x04 SPI Clock Divider Register
sahilmgandhi	18:6a4db94011d3	22997	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	22998	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	22999	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	23000	* \|[0:7] \|DIVIDER \|Clock Divider Register
sahilmgandhi	18:6a4db94011d3	23001	* \| \| \|The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI master.
sahilmgandhi	18:6a4db94011d3	23002	* \| \| \|The frequency is obtained according to the following equation.
sahilmgandhi	18:6a4db94011d3	23003	* \| \| \|Note1: is the peripheral clock source, which is defined in the clock control, CLK_SEL1 register.
sahilmgandhi	18:6a4db94011d3	23004	* \| \| \|Note2: is the peripheral clock which is used to drive the SPI logic unit.
sahilmgandhi	18:6a4db94011d3	23005	*/
sahilmgandhi	18:6a4db94011d3	23006	__IO uint32_t CLKDIV;
sahilmgandhi	18:6a4db94011d3	23007
sahilmgandhi	18:6a4db94011d3	23008	/**
sahilmgandhi	18:6a4db94011d3	23009	* SSCTL
sahilmgandhi	18:6a4db94011d3	23010	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	23011	* Offset: 0x08 SPI Slave Select Control Register
sahilmgandhi	18:6a4db94011d3	23012	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	23013	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	23014	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	23015	* \|[0:1] \|SS \|Slave Select Control (Master Only)
sahilmgandhi	18:6a4db94011d3	23016	* \| \| \|If AUTOSS bit is cleared to 0,
sahilmgandhi	18:6a4db94011d3	23017	* \| \| \|0 = Set the SPI_SS line to inactive state.
sahilmgandhi	18:6a4db94011d3	23018	* \| \| \|1 = Set the proper SPI_SS line to active state.
sahilmgandhi	18:6a4db94011d3	23019	* \| \| \|If AUTOSS bit is set to 1,
sahilmgandhi	18:6a4db94011d3	23020	* \| \| \|0 = Keep the SPI_SS line at inactive state.
sahilmgandhi	18:6a4db94011d3	23021	* \| \| \|1 = Select the SPI_SS line to be automatically driven to active state for the duration of transmission/reception, and will be driven to inactive state for the rest of the time.
sahilmgandhi	18:6a4db94011d3	23022	* \| \| \|The active state of SPI_SS is specified in SSACTPOL bit.
sahilmgandhi	18:6a4db94011d3	23023	* \| \| \|Note: SPI_SS0 is defined as the slave select input in Slave mode.
sahilmgandhi	18:6a4db94011d3	23024	* \|[2] \|SSACTPOL \|Slave Select Active Level
sahilmgandhi	18:6a4db94011d3	23025	* \| \| \|0 = The slave select signal SPI_SS0/1 is active on low-level.
sahilmgandhi	18:6a4db94011d3	23026	* \| \| \|1 = The slave select signal SPI_SS0/1 is active on high-level.
sahilmgandhi	18:6a4db94011d3	23027	* \| \| \|Note: This bit defines the active status of slave select signal (SPI_SS0/1).
sahilmgandhi	18:6a4db94011d3	23028	* \|[3] \|AUTOSS \|Automatic Slave Select Function Enable Control (Master Only)
sahilmgandhi	18:6a4db94011d3	23029	* \| \| \|0 = Automatic slave select function Disabled.
sahilmgandhi	18:6a4db94011d3	23030	* \| \| \|1 = Automatic slave select function Enabled.
sahilmgandhi	18:6a4db94011d3	23031	* \| \| \|Note1: If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSCTL[1:0].
sahilmgandhi	18:6a4db94011d3	23032	* \| \| \|Note2: If this bit is set, SPI_SS0/1 signals will be generated automatically.
sahilmgandhi	18:6a4db94011d3	23033	* \| \| \|It means that device/slave select signal, which is set in SPI_SSCTL[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished.
sahilmgandhi	18:6a4db94011d3	23034	* \|[4] \|SLV3WIRE \|Slave 3-Wire Mode Enable Control
sahilmgandhi	18:6a4db94011d3	23035	* \| \| \|0 = 4-wire bi-direction interface.
sahilmgandhi	18:6a4db94011d3	23036	* \| \| \|1 = 3-wire bi-direction interface.
sahilmgandhi	18:6a4db94011d3	23037	* \| \| \|Note: This is used to ignore the slave select signal in Slave mode.
sahilmgandhi	18:6a4db94011d3	23038	* \| \| \|The SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI.
sahilmgandhi	18:6a4db94011d3	23039	* \|[5] \|SLVTOIEN \|Slave Mode Time-Out Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	23040	* \| \| \|0 = Slave mode time-out interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	23041	* \| \| \|1 = Slave mode time-out interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	23042	* \|[6] \|SLVTORST \|Slave Mode Time-Out FIFO Clear
sahilmgandhi	18:6a4db94011d3	23043	* \| \| \|0 = Time out FIFO clear Disabled.
sahilmgandhi	18:6a4db94011d3	23044	* \| \| \|1 = Time out FIFO clear Enabled.
sahilmgandhi	18:6a4db94011d3	23045	* \| \| \|Note: Both the FIFO clear function, TX_CLK and RXRST, active automatically when there is slave mode time-out event.
sahilmgandhi	18:6a4db94011d3	23046	* \|[8] \|SLVBEIEN \|Slave Mode Error 0 Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	23047	* \| \| \|0 = Slave mode error 0 interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	23048	* \| \| \|1 = Slave mode error 0 interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	23049	* \|[9] \|SLVURIEN \|Slave Mode Error 1 Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	23050	* \| \| \|0 = Slave mode error 1 interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	23051	* \| \| \|1 = Slave mode error 1 interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	23052	* \|[12] \|SSACTIEN \|Slave Select Active Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	23053	* \| \| \|0 = Slave select active interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	23054	* \| \| \|1 = Slave select active interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	23055	* \|[13] \|SSINAIEN \|Slave Select Inactive Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	23056	* \| \| \|0 = Slave select inactive interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	23057	* \| \| \|1 = Slave select inactive interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	23058	* \|[16:31] \|SLVTOCNT \|Slave Mode Time-Out Period
sahilmgandhi	18:6a4db94011d3	23059	* \| \| \|0 = Slave time out function disabled.
sahilmgandhi	18:6a4db94011d3	23060	* \| \| \|Others = Slave time out period.
sahilmgandhi	18:6a4db94011d3	23061	* \| \| \|Note: In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active.
sahilmgandhi	18:6a4db94011d3	23062	* \| \| \|The clock source of the time-out counter is Slave peripheral clock.
sahilmgandhi	18:6a4db94011d3	23063	* \| \| \|If the value is 0, it indicates the slave mode time-out function is disabled.
sahilmgandhi	18:6a4db94011d3	23064	*/
sahilmgandhi	18:6a4db94011d3	23065	__IO uint32_t SSCTL;
sahilmgandhi	18:6a4db94011d3	23066
sahilmgandhi	18:6a4db94011d3	23067	/**
sahilmgandhi	18:6a4db94011d3	23068	* PDMACTL
sahilmgandhi	18:6a4db94011d3	23069	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	23070	* Offset: 0x0C SPI PDMA Control Register
sahilmgandhi	18:6a4db94011d3	23071	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	23072	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	23073	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	23074	* \|[0] \|TXPDMAEN \|Transmit DMA Enable Control
sahilmgandhi	18:6a4db94011d3	23075	* \| \| \|0 = Transmit PDMA Disabled.
sahilmgandhi	18:6a4db94011d3	23076	* \| \| \|1 = Transmit PDMA Enabled.
sahilmgandhi	18:6a4db94011d3	23077	* \| \| \|Note: Setting this bit to 1 will start the transmit PDMA process.
sahilmgandhi	18:6a4db94011d3	23078	* \| \| \|SPI controller will issue request to PDMA controller automatically.
sahilmgandhi	18:6a4db94011d3	23079	* \| \| \|Hardware will clear this bit to 0 automatically after PDMA transfer done.
sahilmgandhi	18:6a4db94011d3	23080	* \|[1] \|RXPDMAEN \|Receive PDMA Enable Control
sahilmgandhi	18:6a4db94011d3	23081	* \| \| \|0 = Receive PDMA Disabled.
sahilmgandhi	18:6a4db94011d3	23082	* \| \| \|1 = Receive PDMA Enabled.
sahilmgandhi	18:6a4db94011d3	23083	* \| \| \|Note: Setting this bit to 1 will start the receive PDMA process.
sahilmgandhi	18:6a4db94011d3	23084	* \| \| \|The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty.
sahilmgandhi	18:6a4db94011d3	23085	* \| \| \|This bit will be cleared to 0 by hardware automatically after PDMA transfer is done.
sahilmgandhi	18:6a4db94011d3	23086	* \|[2] \|PDMARST \|PDMA Reset
sahilmgandhi	18:6a4db94011d3	23087	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	23088	* \| \| \|1 = Reset the PDMA control logic of the SPI controller. This bit will be cleared to 0 automatically.
sahilmgandhi	18:6a4db94011d3	23089	*/
sahilmgandhi	18:6a4db94011d3	23090	__IO uint32_t PDMACTL;
sahilmgandhi	18:6a4db94011d3	23091
sahilmgandhi	18:6a4db94011d3	23092	/**
sahilmgandhi	18:6a4db94011d3	23093	* FIFOCTL
sahilmgandhi	18:6a4db94011d3	23094	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	23095	* Offset: 0x10 SPI FIFO Control Register
sahilmgandhi	18:6a4db94011d3	23096	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	23097	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	23098	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	23099	* \|[0] \|RXRST \|Clear Receive FIFO Buffer
sahilmgandhi	18:6a4db94011d3	23100	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	23101	* \| \| \|1 = Clear receive FIFO buffer.
sahilmgandhi	18:6a4db94011d3	23102	* \| \| \|Note1: If there is slave receive time-out event, the RXRST will be set 1 when the SLVTORST, SPI_SSCTL[6], is enabled.
sahilmgandhi	18:6a4db94011d3	23103	* \| \| \|Note2: The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1.
sahilmgandhi	18:6a4db94011d3	23104	* \| \| \|This bit will be cleared to 0 by hardware about 3 system clocks + 3 peripheral clock after it is set to 1.
sahilmgandhi	18:6a4db94011d3	23105	* \|[1] \|TXRST \|Clear Transmit FIFO Buffer
sahilmgandhi	18:6a4db94011d3	23106	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	23107	* \| \| \|1 = Clear transmit FIFO buffer.
sahilmgandhi	18:6a4db94011d3	23108	* \| \| \|Note1: If there is slave receive time-out event, the TXRST will be set 1 when the SLVTORST, SPI_SSCTL[6], is enabled.
sahilmgandhi	18:6a4db94011d3	23109	* \| \| \|Note2: The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1.
sahilmgandhi	18:6a4db94011d3	23110	* \| \| \|This bit will be cleared to 0 by hardware about 3 system clocks + 3 peripheral clock after it is set to 1.
sahilmgandhi	18:6a4db94011d3	23111	* \|[2] \|RXTHIEN \|Receive FIFO Threshold Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	23112	* \| \| \|0 = RX FIFO threshold interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	23113	* \| \| \|1 = RX FIFO threshold interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	23114	* \|[3] \|TXTHIEN \|Transmit FIFO Threshold Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	23115	* \| \| \|0 = TX FIFO threshold interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	23116	* \| \| \|1 = TX FIFO threshold interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	23117	* \|[4] \|RXTOIEN \|Slave Receive Time-Out Interrupt Enable Control (Slave Only)
sahilmgandhi	18:6a4db94011d3	23118	* \| \| \|0 = Receive time-out interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	23119	* \| \| \|1 = Receive time-out interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	23120	* \|[5] \|RXOVIEN \|Receive FIFO Overrun Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	23121	* \| \| \|0 = Receive FIFO overrun interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	23122	* \| \| \|1 = Receive FIFO overrun interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	23123	* \|[6] \|TXUFPOL \|Transmit Under-Run Data Out (Slave Only)
sahilmgandhi	18:6a4db94011d3	23124	* \| \| \|0 = The SPI data bus is keep low if there is transmit under-run event.
sahilmgandhi	18:6a4db94011d3	23125	* \| \| \|1 = The SPI data bus is keep high if there is transmit under-run event.
sahilmgandhi	18:6a4db94011d3	23126	* \| \| \|Note1: The under run event is activated after the bus clock input and the hardware synchronous, so that the first 1~3 bit (depending on the relation between system clock and the peripheral clock) data out will be the last transaction data.
sahilmgandhi	18:6a4db94011d3	23127	* \| \| \|Note2: If the frequency of system clock approach to peripheral clock, they may need 3-bit time to report the transmit under-run event.
sahilmgandhi	18:6a4db94011d3	23128	* \|[7] \|TXUFIEN \|Transmit Under Run Interrupt Enable Control (Slave Only)
sahilmgandhi	18:6a4db94011d3	23129	* \| \| \|0 = Transmit FIFO under-run interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	23130	* \| \| \|1 = Transmit FIFO under-run interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	23131	* \|[24:26] \|RXTH \|Receive FIFO Threshold
sahilmgandhi	18:6a4db94011d3	23132	* \| \| \|If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
sahilmgandhi	18:6a4db94011d3	23133	* \|[28:30] \|TXTH \|Transmit FIFO Threshold
sahilmgandhi	18:6a4db94011d3	23134	* \| \| \|If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
sahilmgandhi	18:6a4db94011d3	23135	*/
sahilmgandhi	18:6a4db94011d3	23136	__IO uint32_t FIFOCTL;
sahilmgandhi	18:6a4db94011d3	23137
sahilmgandhi	18:6a4db94011d3	23138	/**
sahilmgandhi	18:6a4db94011d3	23139	* STATUS
sahilmgandhi	18:6a4db94011d3	23140	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	23141	* Offset: 0x14 SPI Status Register
sahilmgandhi	18:6a4db94011d3	23142	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	23143	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	23144	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	23145	* \|[0] \|BUSY \|Busy Status (Read Only)
sahilmgandhi	18:6a4db94011d3	23146	* \| \| \|0 = SPI controller is in Idle state.
sahilmgandhi	18:6a4db94011d3	23147	* \| \| \|1 = SPI controller is in busy state.
sahilmgandhi	18:6a4db94011d3	23148	* \| \| \|The following listing are the bus busy conditions:
sahilmgandhi	18:6a4db94011d3	23149	* \| \| \|*. SPIEN = 1 and the TXEMPTY = 0.
sahilmgandhi	18:6a4db94011d3	23150	* \| \| \|*. For SPI Master, the TXEMPTY = 1 but the current transaction is not finished yet.
sahilmgandhi	18:6a4db94011d3	23151	* \| \| \|*. For SPI Slave receive mode, the SPIEN = 1 and there is serial clock input into the SPI core logic when slave select is active.
sahilmgandhi	18:6a4db94011d3	23152	* \| \| \|*. For SPI Slave transmit mode, the SPIEN = 1 and the transmit buffer is not empty in SPI core logic even if the slave select is inactive.
sahilmgandhi	18:6a4db94011d3	23153	* \|[1] \|UNITIF \|Unit Transfer Interrupt Status
sahilmgandhi	18:6a4db94011d3	23154	* \| \| \|0 = No transaction has been finished since this bit was cleared to 0.
sahilmgandhi	18:6a4db94011d3	23155	* \| \| \|1 = SPI controller has finished one unit transfer.
sahilmgandhi	18:6a4db94011d3	23156	* \| \| \|Note: This bit will be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	23157	* \|[2] \|SSACTIF \|Slave Select Active Interrupt Status
sahilmgandhi	18:6a4db94011d3	23158	* \| \| \|0 = Slave select active interrupt is clear or not occur.
sahilmgandhi	18:6a4db94011d3	23159	* \| \| \|1 = Slave select active interrupt event occurred.
sahilmgandhi	18:6a4db94011d3	23160	* \| \| \|Note: This bit will be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	23161	* \|[3] \|SSINAIF \|Slave Select Inactive Interrupt Status
sahilmgandhi	18:6a4db94011d3	23162	* \| \| \|0 = Slave select inactive interrupt is clear or not occur.
sahilmgandhi	18:6a4db94011d3	23163	* \| \| \|1 = Slave select inactive interrupt event occurred.
sahilmgandhi	18:6a4db94011d3	23164	* \| \| \|Note: This bit will be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	23165	* \|[4] \|SSLINE \|Slave Select Line Bus Status (Read Only)
sahilmgandhi	18:6a4db94011d3	23166	* \| \| \|0 = Indicates the slave select line bus status is 0.
sahilmgandhi	18:6a4db94011d3	23167	* \| \| \|1 = Indicates the slave select line bus status is 1.
sahilmgandhi	18:6a4db94011d3	23168	* \| \| \|Note: If SSACTPOL, SPI_SSCTL[2], is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
sahilmgandhi	18:6a4db94011d3	23169	* \|[5] \|SLVTOIF \|Slave Time-Out Interrupt Status
sahilmgandhi	18:6a4db94011d3	23170	* \| \| \|0 = Slave time-out is not active.
sahilmgandhi	18:6a4db94011d3	23171	* \| \| \|1 = Slave time-out is active.
sahilmgandhi	18:6a4db94011d3	23172	* \| \| \|Note1: If the DWIDTH is set 16, one transaction is equal 16 bits bus clock period.
sahilmgandhi	18:6a4db94011d3	23173	* \| \| \|This bit will be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	23174	* \| \| \|Note2: When the Slave Select is active and the value of SLVTOCNT is not 0 and the busclock input, the slave time-out counter in SPI controller logic will be start.
sahilmgandhi	18:6a4db94011d3	23175	* \| \| \|When the value of time-out counter greater or equal than the value of SLVTOCNT, SPI_SSCTL[31:16], during before one transaction done, the slave time-out interrupt event will active.
sahilmgandhi	18:6a4db94011d3	23176	* \|[6] \|SLVBEIF \|Slave Mode Error 0 Interrupt Status
sahilmgandhi	18:6a4db94011d3	23177	* \| \| \|0 = No Slave mode error 0 event.
sahilmgandhi	18:6a4db94011d3	23178	* \| \| \|1 = Slave mode error 0 occurs.
sahilmgandhi	18:6a4db94011d3	23179	* \| \| \|Note1: If the slave select active but there is no any bus clock input, the SLVER0_INTSTS also active when the slave select goes to inactive state.
sahilmgandhi	18:6a4db94011d3	23180	* \| \| \|This bit will be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	23181	* \| \| \|Note2: In Slave mode, there is bit counter mismatch with DWIDTH when the slave select line goes to inactive state.
sahilmgandhi	18:6a4db94011d3	23182	* \|[7] \|SLVURIF \|Slave Mode Error 1 Interrupt Status
sahilmgandhi	18:6a4db94011d3	23183	* \| \| \|0 = No Slave mode error 1 event.
sahilmgandhi	18:6a4db94011d3	23184	* \| \| \|1 = Slave mode error 1 occurs.
sahilmgandhi	18:6a4db94011d3	23185	* \| \| \|Note: In Slave mode, transmit under-run occurs when the slave select line goes to inactive state.
sahilmgandhi	18:6a4db94011d3	23186	* \| \| \|This bit will be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	23187	* \|[8] \|RXEMPTY \|Receive FIFO Buffer Empty Indicator (Read Only)
sahilmgandhi	18:6a4db94011d3	23188	* \| \| \|0 = Receive FIFO buffer is not empty.
sahilmgandhi	18:6a4db94011d3	23189	* \| \| \|1 = Receive FIFO buffer is empty.
sahilmgandhi	18:6a4db94011d3	23190	* \|[9] \|RXFULL \|Receive FIFO Buffer Empty Indicator (Read Only)
sahilmgandhi	18:6a4db94011d3	23191	* \| \| \|0 = Receive FIFO buffer is not empty.
sahilmgandhi	18:6a4db94011d3	23192	* \| \| \|1 = Receive FIFO buffer is empty.
sahilmgandhi	18:6a4db94011d3	23193	* \|[10] \|RXTHIF \|Receive FIFO Threshold Interrupt Status (Read Only)
sahilmgandhi	18:6a4db94011d3	23194	* \| \| \|0 = The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RXTH.
sahilmgandhi	18:6a4db94011d3	23195	* \| \| \|1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
sahilmgandhi	18:6a4db94011d3	23196	* \| \| \|Note: If RX_INTEN = 1 and RX_INTSTS = 1, the SPI controller will generate a SPI interrupt request.
sahilmgandhi	18:6a4db94011d3	23197	* \|[11] \|RXOVIF \|Receive FIFO Overrun Status
sahilmgandhi	18:6a4db94011d3	23198	* \| \| \|0 = No FIFO over-run event.
sahilmgandhi	18:6a4db94011d3	23199	* \| \| \|1 = FIFO over-run event occurred.
sahilmgandhi	18:6a4db94011d3	23200	* \| \| \|Note: When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
sahilmgandhi	18:6a4db94011d3	23201	* \| \| \|This bit will be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	23202	* \|[12] \|RXTOIF \|Receive Time-Out Interrupt Status
sahilmgandhi	18:6a4db94011d3	23203	* \| \| \|0 = No receive FIFO time-out event.
sahilmgandhi	18:6a4db94011d3	23204	* \| \| \|1 = FIFO time-out event occurred.
sahilmgandhi	18:6a4db94011d3	23205	* \| \| \|Note: Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode.
sahilmgandhi	18:6a4db94011d3	23206	* \| \| \|When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
sahilmgandhi	18:6a4db94011d3	23207	* \| \| \|This bit will be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	23208	* \|[15] \|SPIENSTS \|SPI Enable Bit Status (Read Only)
sahilmgandhi	18:6a4db94011d3	23209	* \| \| \|0 = Indicates the transmit control bit is disabled.
sahilmgandhi	18:6a4db94011d3	23210	* \| \| \|1 = Indicates the transfer control bit is active.
sahilmgandhi	18:6a4db94011d3	23211	* \| \| \|Note: The clock source of SPI controller logic is peripheral clock, it is asynchronous with the system clock.
sahilmgandhi	18:6a4db94011d3	23212	* \| \| \|In order to make sure the function is disabled in SPI controller logic, this bit indicates the real status of SPIEN in SPI controller logic for user.
sahilmgandhi	18:6a4db94011d3	23213	* \|[16] \|TXEMPTY \|Transmit FIFO Buffer Empty Indicator (Read Only)
sahilmgandhi	18:6a4db94011d3	23214	* \| \| \|0 = Transmit FIFO buffer is not empty.
sahilmgandhi	18:6a4db94011d3	23215	* \| \| \|1 = Transmit FIFO buffer is empty.
sahilmgandhi	18:6a4db94011d3	23216	* \|[17] \|TXFULL \|Transmit FIFO Buffer Full Indicator (Read Only)
sahilmgandhi	18:6a4db94011d3	23217	* \| \| \|0 = Transmit FIFO buffer is not full.
sahilmgandhi	18:6a4db94011d3	23218	* \| \| \|1 = Transmit FIFO buffer is full.
sahilmgandhi	18:6a4db94011d3	23219	* \|[18] \|TXTHIF \|Transmit FIFO Threshold Interrupt Status (Read Only)
sahilmgandhi	18:6a4db94011d3	23220	* \| \| \|0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
sahilmgandhi	18:6a4db94011d3	23221	* \| \| \|1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
sahilmgandhi	18:6a4db94011d3	23222	* \| \| \|Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI controller will generate a SPI interrupt request.
sahilmgandhi	18:6a4db94011d3	23223	* \|[19] \|TXUFIF \|Transmit FIFO Under-Run Interrupt Status
sahilmgandhi	18:6a4db94011d3	23224	* \| \| \|0 =No under-run interrupt event.
sahilmgandhi	18:6a4db94011d3	23225	* \| \| \|1 = Under-run interrupt occurred.
sahilmgandhi	18:6a4db94011d3	23226	* \| \| \|Note: When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input , the output data depends on the setting of SLVUDFPOL and this bit will be set to 1 and this bit will be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	23227	* \|[23] \|TXRXRST \|FIFO CLR Status (Read Only)
sahilmgandhi	18:6a4db94011d3	23228	* \| \| \|0 = Done the FIFO buffer clear function of TXRST or RXRST.
sahilmgandhi	18:6a4db94011d3	23229	* \| \| \|1 = Doing the FIFO buffer clear function of TXRST or RXRST.
sahilmgandhi	18:6a4db94011d3	23230	* \| \| \|Note: Both the TXRST, RXRST, need 3 system clock + 3 peripheral clock , the status of this bit support the user to monitor the clear function is doing or done.
sahilmgandhi	18:6a4db94011d3	23231	* \|[24:27] \|RXCNT \|Receive FIFO Data Count (Read Only)
sahilmgandhi	18:6a4db94011d3	23232	* \| \| \|This bit field indicates the valid data count of receive FIFO buffer.
sahilmgandhi	18:6a4db94011d3	23233	* \|[28:31] \|TXCNT \|Transmit FIFO Data Count (Read Only)
sahilmgandhi	18:6a4db94011d3	23234	* \| \| \|This bit field indicates the valid data count of transmit FIFO buffer.
sahilmgandhi	18:6a4db94011d3	23235	*/
sahilmgandhi	18:6a4db94011d3	23236	__IO uint32_t STATUS;
sahilmgandhi	18:6a4db94011d3	23237	uint32_t RESERVE0[2];
sahilmgandhi	18:6a4db94011d3	23238
sahilmgandhi	18:6a4db94011d3	23239
sahilmgandhi	18:6a4db94011d3	23240	/**
sahilmgandhi	18:6a4db94011d3	23241	* TX
sahilmgandhi	18:6a4db94011d3	23242	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	23243	* Offset: 0x20 SPI Data Transmit Register
sahilmgandhi	18:6a4db94011d3	23244	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	23245	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	23246	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	23247	* \|[0:31] \|TX \|Data Transmit Bits
sahilmgandhi	18:6a4db94011d3	23248	* \| \| \|The data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffer.
sahilmgandhi	18:6a4db94011d3	23249	* \| \| \|The number of valid bits depends on the setting of transmit bit width field of the SPI_CTL register.
sahilmgandhi	18:6a4db94011d3	23250	* \| \| \|In Master mode, the serial data in SPI bus output need 5 module clock cycle when the data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffer.
sahilmgandhi	18:6a4db94011d3	23251	* \| \| \|For example, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted.
sahilmgandhi	18:6a4db94011d3	23252	* \| \| \|If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.
sahilmgandhi	18:6a4db94011d3	23253	*/
sahilmgandhi	18:6a4db94011d3	23254	__O uint32_t TX;
sahilmgandhi	18:6a4db94011d3	23255	uint32_t RESERVE1[3];
sahilmgandhi	18:6a4db94011d3	23256
sahilmgandhi	18:6a4db94011d3	23257
sahilmgandhi	18:6a4db94011d3	23258	/**
sahilmgandhi	18:6a4db94011d3	23259	* RX
sahilmgandhi	18:6a4db94011d3	23260	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	23261	* Offset: 0x30 SPI Data Receive Register
sahilmgandhi	18:6a4db94011d3	23262	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	23263	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	23264	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	23265	* \|[0:31] \|RX \|Data Receive Bits
sahilmgandhi	18:6a4db94011d3	23266	* \| \| \|There is 8-level FIFO buffer in this controller.
sahilmgandhi	18:6a4db94011d3	23267	* \| \| \|The data receive register holds the earliest datum received from SPI data input pin.
sahilmgandhi	18:6a4db94011d3	23268	* \| \| \|If the RXEMPTY bit, SPI_STATUS[8], is not set to 1, the receive FIFO buffer can be accessed through software by reading this register.
sahilmgandhi	18:6a4db94011d3	23269	* \| \| \|This is a read only register.
sahilmgandhi	18:6a4db94011d3	23270	*/
sahilmgandhi	18:6a4db94011d3	23271	__I uint32_t RX;
sahilmgandhi	18:6a4db94011d3	23272
sahilmgandhi	18:6a4db94011d3	23273	} SPI_T;
sahilmgandhi	18:6a4db94011d3	23274
sahilmgandhi	18:6a4db94011d3	23275	/**
sahilmgandhi	18:6a4db94011d3	23276	@addtogroup SPI_CONST SPI Bit Field Definition
sahilmgandhi	18:6a4db94011d3	23277	Constant Definitions for SPI Controller
sahilmgandhi	18:6a4db94011d3	23278	@{ */
sahilmgandhi	18:6a4db94011d3	23279
sahilmgandhi	18:6a4db94011d3	23280	#define SPI_CTL_SPIEN_Pos (0) /!< SPI CTL: SPIEN Position /
sahilmgandhi	18:6a4db94011d3	23281	#define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) /!< SPI CTL: SPIEN Mask /
sahilmgandhi	18:6a4db94011d3	23282
sahilmgandhi	18:6a4db94011d3	23283	#define SPI_CTL_RXNEG_Pos (1) /!< SPI CTL: RXNEG Position /
sahilmgandhi	18:6a4db94011d3	23284	#define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) /!< SPI CTL: RXNEG Mask /
sahilmgandhi	18:6a4db94011d3	23285
sahilmgandhi	18:6a4db94011d3	23286	#define SPI_CTL_TXNEG_Pos (2) /!< SPI CTL: TXNEG Position /
sahilmgandhi	18:6a4db94011d3	23287	#define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) /!< SPI CTL: TXNEG Mask /
sahilmgandhi	18:6a4db94011d3	23288
sahilmgandhi	18:6a4db94011d3	23289	#define SPI_CTL_CLKPOL_Pos (3) /!< SPI CTL: CLKPOL Position /
sahilmgandhi	18:6a4db94011d3	23290	#define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) /!< SPI CTL: CLKPOL Mask /
sahilmgandhi	18:6a4db94011d3	23291
sahilmgandhi	18:6a4db94011d3	23292	#define SPI_CTL_SUSPITV_Pos (4) /!< SPI CTL: SUSPITV Position /
sahilmgandhi	18:6a4db94011d3	23293	#define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) /!< SPI CTL: SUSPITV Mask /
sahilmgandhi	18:6a4db94011d3	23294
sahilmgandhi	18:6a4db94011d3	23295	#define SPI_CTL_DWIDTH_Pos (8) /!< SPI CTL: DWIDTH Position /
sahilmgandhi	18:6a4db94011d3	23296	#define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) /!< SPI CTL: DWIDTH Mask /
sahilmgandhi	18:6a4db94011d3	23297
sahilmgandhi	18:6a4db94011d3	23298	#define SPI_CTL_LSB_Pos (13) /!< SPI CTL: LSB Position /
sahilmgandhi	18:6a4db94011d3	23299	#define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /!< SPI CTL: LSB Mask /
sahilmgandhi	18:6a4db94011d3	23300
sahilmgandhi	18:6a4db94011d3	23301	#define SPI_CTL_TWOBIT_Pos (16) /!< SPI CTL: TWOBIT Position /
sahilmgandhi	18:6a4db94011d3	23302	#define SPI_CTL_TWOBIT_Msk (0x1ul << SPI_CTL_TWOBIT_Pos) /!< SPI CTL: TWOBIT Mask /
sahilmgandhi	18:6a4db94011d3	23303
sahilmgandhi	18:6a4db94011d3	23304	#define SPI_CTL_UNITIEN_Pos (17) /!< SPI CTL: UNITIEN Position /
sahilmgandhi	18:6a4db94011d3	23305	#define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) /!< SPI CTL: UNITIEN Mask /
sahilmgandhi	18:6a4db94011d3	23306
sahilmgandhi	18:6a4db94011d3	23307	#define SPI_CTL_SLAVE_Pos (18) /!< SPI CTL: SLAVE Position /
sahilmgandhi	18:6a4db94011d3	23308	#define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /!< SPI CTL: SLAVE Mask /
sahilmgandhi	18:6a4db94011d3	23309
sahilmgandhi	18:6a4db94011d3	23310	#define SPI_CTL_REORDER_Pos (19) /!< SPI CTL: REORDER Position /
sahilmgandhi	18:6a4db94011d3	23311	#define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /!< SPI CTL: REORDER Mask /
sahilmgandhi	18:6a4db94011d3	23312
sahilmgandhi	18:6a4db94011d3	23313	#define SPI_CTL_QDIODIR_Pos (20) /!< SPI CTL: QDIODIR Position /
sahilmgandhi	18:6a4db94011d3	23314	#define SPI_CTL_QDIODIR_Msk (0x1ul << SPI_CTL_QDIODIR_Pos) /!< SPI CTL: QDIODIR Mask /
sahilmgandhi	18:6a4db94011d3	23315
sahilmgandhi	18:6a4db94011d3	23316	#define SPI_CTL_DUALIOEN_Pos (21) /!< SPI CTL: DUALIOEN Position /
sahilmgandhi	18:6a4db94011d3	23317	#define SPI_CTL_DUALIOEN_Msk (0x1ul << SPI_CTL_DUALIOEN_Pos) /!< SPI CTL: DUALIOEN Mask /
sahilmgandhi	18:6a4db94011d3	23318
sahilmgandhi	18:6a4db94011d3	23319	#define SPI_CTL_QUADIOEN_Pos (22) /!< SPI CTL: QUADIOEN Position /
sahilmgandhi	18:6a4db94011d3	23320	#define SPI_CTL_QUADIOEN_Msk (0x1ul << SPI_CTL_QUADIOEN_Pos) /!< SPI CTL: QUADIOEN Mask /
sahilmgandhi	18:6a4db94011d3	23321
sahilmgandhi	18:6a4db94011d3	23322	#define SPI_CLKDIV_DIVIDER_Pos (0) /!< SPI CLKDIV: DIVIDER Position /
sahilmgandhi	18:6a4db94011d3	23323	#define SPI_CLKDIV_DIVIDER_Msk (0xfful << SPI_CLKDIV_DIVIDER_Pos) /!< SPI CLKDIV: DIVIDER Mask /
sahilmgandhi	18:6a4db94011d3	23324
sahilmgandhi	18:6a4db94011d3	23325	#define SPI_SSCTL_SS_Pos (0) /!< SPI SSCTL: SS Position /
sahilmgandhi	18:6a4db94011d3	23326	#define SPI_SSCTL_SS_Msk (0x3ul << SPI_SSCTL_SS_Pos) /!< SPI SSCTL: SS Mask /
sahilmgandhi	18:6a4db94011d3	23327
sahilmgandhi	18:6a4db94011d3	23328	#define SPI_SSCTL_SSACTPOL_Pos (2) /!< SPI SSCTL: SSACTPOL Position /
sahilmgandhi	18:6a4db94011d3	23329	#define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) /!< SPI SSCTL: SSACTPOL Mask /
sahilmgandhi	18:6a4db94011d3	23330
sahilmgandhi	18:6a4db94011d3	23331	#define SPI_SSCTL_AUTOSS_Pos (3) /!< SPI SSCTL: AUTOSS Position /
sahilmgandhi	18:6a4db94011d3	23332	#define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) /!< SPI SSCTL: AUTOSS Mask /
sahilmgandhi	18:6a4db94011d3	23333
sahilmgandhi	18:6a4db94011d3	23334	#define SPI_SSCTL_SLV3WIRE_Pos (4) /!< SPI SSCTL: SLV3WIRE Position /
sahilmgandhi	18:6a4db94011d3	23335	#define SPI_SSCTL_SLV3WIRE_Msk (0x1ul << SPI_SSCTL_SLV3WIRE_Pos) /!< SPI SSCTL: SLV3WIRE Mask /
sahilmgandhi	18:6a4db94011d3	23336
sahilmgandhi	18:6a4db94011d3	23337	#define SPI_SSCTL_SLVTOIEN_Pos (5) /!< SPI SSCTL: SLVTOIEN Position /
sahilmgandhi	18:6a4db94011d3	23338	#define SPI_SSCTL_SLVTOIEN_Msk (0x1ul << SPI_SSCTL_SLVTOIEN_Pos) /!< SPI SSCTL: SLVTOIEN Mask /
sahilmgandhi	18:6a4db94011d3	23339
sahilmgandhi	18:6a4db94011d3	23340	#define SPI_SSCTL_SLVTORST_Pos (6) /!< SPI SSCTL: SLVTORST Position /
sahilmgandhi	18:6a4db94011d3	23341	#define SPI_SSCTL_SLVTORST_Msk (0x1ul << SPI_SSCTL_SLVTORST_Pos) /!< SPI SSCTL: SLVTORST Mask /
sahilmgandhi	18:6a4db94011d3	23342
sahilmgandhi	18:6a4db94011d3	23343	#define SPI_SSCTL_SLVBEIEN_Pos (8) /!< SPI SSCTL: SLVBEIEN Position /
sahilmgandhi	18:6a4db94011d3	23344	#define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) /!< SPI SSCTL: SLVBEIEN Mask /
sahilmgandhi	18:6a4db94011d3	23345
sahilmgandhi	18:6a4db94011d3	23346	#define SPI_SSCTL_SLVURIEN_Pos (9) /!< SPI SSCTL: SLVURIEN Position /
sahilmgandhi	18:6a4db94011d3	23347	#define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) /!< SPI SSCTL: SLVURIEN Mask /
sahilmgandhi	18:6a4db94011d3	23348
sahilmgandhi	18:6a4db94011d3	23349	#define SPI_SSCTL_SSACTIEN_Pos (12) /!< SPI SSCTL: SSACTIEN Position /
sahilmgandhi	18:6a4db94011d3	23350	#define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) /!< SPI SSCTL: SSACTIEN Mask /
sahilmgandhi	18:6a4db94011d3	23351
sahilmgandhi	18:6a4db94011d3	23352	#define SPI_SSCTL_SSINAIEN_Pos (13) /!< SPI SSCTL: SSINAIEN Position /
sahilmgandhi	18:6a4db94011d3	23353	#define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) /!< SPI SSCTL: SSINAIEN Mask /
sahilmgandhi	18:6a4db94011d3	23354
sahilmgandhi	18:6a4db94011d3	23355	#define SPI_SSCTL_SLVTOCNT_Pos (16) /!< SPI SSCTL: SLVTOCNT Position /
sahilmgandhi	18:6a4db94011d3	23356	#define SPI_SSCTL_SLVTOCNT_Msk (0xfffful << SPI_SSCTL_SLVTOCNT_Pos) /!< SPI SSCTL: SLVTOCNT Mask /
sahilmgandhi	18:6a4db94011d3	23357
sahilmgandhi	18:6a4db94011d3	23358	#define SPI_PDMACTL_TXPDMAEN_Pos (0) /!< SPI PDMACTL: TXPDMAEN Position /
sahilmgandhi	18:6a4db94011d3	23359	#define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) /!< SPI PDMACTL: TXPDMAEN Mask /
sahilmgandhi	18:6a4db94011d3	23360
sahilmgandhi	18:6a4db94011d3	23361	#define SPI_PDMACTL_RXPDMAEN_Pos (1) /!< SPI PDMACTL: RXPDMAEN Position /
sahilmgandhi	18:6a4db94011d3	23362	#define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) /!< SPI PDMACTL: RXPDMAEN Mask /
sahilmgandhi	18:6a4db94011d3	23363
sahilmgandhi	18:6a4db94011d3	23364	#define SPI_PDMACTL_PDMARST_Pos (2) /!< SPI PDMACTL: PDMARST Position /
sahilmgandhi	18:6a4db94011d3	23365	#define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) /!< SPI PDMACTL: PDMARST Mask /
sahilmgandhi	18:6a4db94011d3	23366
sahilmgandhi	18:6a4db94011d3	23367	#define SPI_FIFOCTL_RXRST_Pos (0) /!< SPI FIFOCTL: RXRST Position /
sahilmgandhi	18:6a4db94011d3	23368	#define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) /!< SPI FIFOCTL: RXRST Mask /
sahilmgandhi	18:6a4db94011d3	23369
sahilmgandhi	18:6a4db94011d3	23370	#define SPI_FIFOCTL_TXRST_Pos (1) /!< SPI FIFOCTL: TXRST Position /
sahilmgandhi	18:6a4db94011d3	23371	#define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) /!< SPI FIFOCTL: TXRST Mask /
sahilmgandhi	18:6a4db94011d3	23372
sahilmgandhi	18:6a4db94011d3	23373	#define SPI_FIFOCTL_RXTHIEN_Pos (2) /!< SPI FIFOCTL: RXTHIEN Position /
sahilmgandhi	18:6a4db94011d3	23374	#define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) /!< SPI FIFOCTL: RXTHIEN Mask /
sahilmgandhi	18:6a4db94011d3	23375
sahilmgandhi	18:6a4db94011d3	23376	#define SPI_FIFOCTL_TXTHIEN_Pos (3) /!< SPI FIFOCTL: TXTHIEN Position /
sahilmgandhi	18:6a4db94011d3	23377	#define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) /!< SPI FIFOCTL: TXTHIEN Mask /
sahilmgandhi	18:6a4db94011d3	23378
sahilmgandhi	18:6a4db94011d3	23379	#define SPI_FIFOCTL_RXTOIEN_Pos (4) /!< SPI FIFOCTL: RXTOIEN Position /
sahilmgandhi	18:6a4db94011d3	23380	#define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) /!< SPI FIFOCTL: RXTOIEN Mask /
sahilmgandhi	18:6a4db94011d3	23381
sahilmgandhi	18:6a4db94011d3	23382	#define SPI_FIFOCTL_RXOVIEN_Pos (5) /!< SPI FIFOCTL: RXOVIEN Position /
sahilmgandhi	18:6a4db94011d3	23383	#define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) /!< SPI FIFOCTL: RXOVIEN Mask /
sahilmgandhi	18:6a4db94011d3	23384
sahilmgandhi	18:6a4db94011d3	23385	#define SPI_FIFOCTL_TXUFPOL_Pos (6) /!< SPI FIFOCTL: TXUFPOL Position /
sahilmgandhi	18:6a4db94011d3	23386	#define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) /!< SPI FIFOCTL: TXUFPOL Mask /
sahilmgandhi	18:6a4db94011d3	23387
sahilmgandhi	18:6a4db94011d3	23388	#define SPI_FIFOCTL_TXUFIEN_Pos (7) /!< SPI FIFOCTL: TXUFIEN Position /
sahilmgandhi	18:6a4db94011d3	23389	#define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) /!< SPI FIFOCTL: TXUFIEN Mask /
sahilmgandhi	18:6a4db94011d3	23390
sahilmgandhi	18:6a4db94011d3	23391	#define SPI_FIFOCTL_RXTH_Pos (24) /!< SPI FIFOCTL: RXTH Position /
sahilmgandhi	18:6a4db94011d3	23392	#define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) /!< SPI FIFOCTL: RXTH Mask /
sahilmgandhi	18:6a4db94011d3	23393
sahilmgandhi	18:6a4db94011d3	23394	#define SPI_FIFOCTL_TXTH_Pos (28) /!< SPI FIFOCTL: TXTH Position /
sahilmgandhi	18:6a4db94011d3	23395	#define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /!< SPI FIFOCTL: TXTH Mask /
sahilmgandhi	18:6a4db94011d3	23396
sahilmgandhi	18:6a4db94011d3	23397	#define SPI_STATUS_BUSY_Pos (0) /!< SPI STATUS: BUSY Position /
sahilmgandhi	18:6a4db94011d3	23398	#define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) /!< SPI STATUS: BUSY Mask /
sahilmgandhi	18:6a4db94011d3	23399
sahilmgandhi	18:6a4db94011d3	23400	#define SPI_STATUS_UNITIF_Pos (1) /!< SPI STATUS: UNITIF Position /
sahilmgandhi	18:6a4db94011d3	23401	#define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) /!< SPI STATUS: UNITIF Mask /
sahilmgandhi	18:6a4db94011d3	23402
sahilmgandhi	18:6a4db94011d3	23403	#define SPI_STATUS_SSACTIF_Pos (2) /!< SPI STATUS: SSACTIF Position /
sahilmgandhi	18:6a4db94011d3	23404	#define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) /!< SPI STATUS: SSACTIF Mask /
sahilmgandhi	18:6a4db94011d3	23405
sahilmgandhi	18:6a4db94011d3	23406	#define SPI_STATUS_SSINAIF_Pos (3) /!< SPI STATUS: SSINAIF Position /
sahilmgandhi	18:6a4db94011d3	23407	#define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) /!< SPI STATUS: SSINAIF Mask /
sahilmgandhi	18:6a4db94011d3	23408
sahilmgandhi	18:6a4db94011d3	23409	#define SPI_STATUS_SSLINE_Pos (4) /!< SPI STATUS: SSLINE Position /
sahilmgandhi	18:6a4db94011d3	23410	#define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) /!< SPI STATUS: SSLINE Mask /
sahilmgandhi	18:6a4db94011d3	23411
sahilmgandhi	18:6a4db94011d3	23412	#define SPI_STATUS_SLVTOIF_Pos (5) /!< SPI STATUS: SLVTOIF Position /
sahilmgandhi	18:6a4db94011d3	23413	#define SPI_STATUS_SLVTOIF_Msk (0x1ul << SPI_STATUS_SLVTOIF_Pos) /!< SPI STATUS: SLVTOIF Mask /
sahilmgandhi	18:6a4db94011d3	23414
sahilmgandhi	18:6a4db94011d3	23415	#define SPI_STATUS_SLVBEIF_Pos (6) /!< SPI STATUS: SLVBEIF Position /
sahilmgandhi	18:6a4db94011d3	23416	#define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) /!< SPI STATUS: SLVBEIF Mask /
sahilmgandhi	18:6a4db94011d3	23417
sahilmgandhi	18:6a4db94011d3	23418	#define SPI_STATUS_SLVUDRIF_Pos (7) /!< SPI STATUS: SLVUDRIF Position /
sahilmgandhi	18:6a4db94011d3	23419	#define SPI_STATUS_SLVUDRIF_Msk (0x1ul << SPI_STATUS_SLVUDRIF_Pos) /!< SPI STATUS: SLVUDRIF Mask /
sahilmgandhi	18:6a4db94011d3	23420
sahilmgandhi	18:6a4db94011d3	23421	#define SPI_STATUS_RXEMPTY_Pos (8) /!< SPI STATUS: RXEMPTY Position /
sahilmgandhi	18:6a4db94011d3	23422	#define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) /!< SPI STATUS: RXEMPTY Mask /
sahilmgandhi	18:6a4db94011d3	23423
sahilmgandhi	18:6a4db94011d3	23424	#define SPI_STATUS_RXFULL_Pos (9) /!< SPI STATUS: RXFULL Position /
sahilmgandhi	18:6a4db94011d3	23425	#define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) /!< SPI STATUS: RXFULL Mask /
sahilmgandhi	18:6a4db94011d3	23426
sahilmgandhi	18:6a4db94011d3	23427	#define SPI_STATUS_RXTHIF_Pos (10) /!< SPI STATUS: RXTHIF Position /
sahilmgandhi	18:6a4db94011d3	23428	#define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) /!< SPI STATUS: RXTHIF Mask /
sahilmgandhi	18:6a4db94011d3	23429
sahilmgandhi	18:6a4db94011d3	23430	#define SPI_STATUS_RXOVIF_Pos (11) /!< SPI STATUS: RXOVIF Position /
sahilmgandhi	18:6a4db94011d3	23431	#define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) /!< SPI STATUS: RXOVIF Mask /
sahilmgandhi	18:6a4db94011d3	23432
sahilmgandhi	18:6a4db94011d3	23433	#define SPI_STATUS_RXTOIF_Pos (12) /!< SPI STATUS: RXTOIF Position /
sahilmgandhi	18:6a4db94011d3	23434	#define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) /!< SPI STATUS: RXTOIF Mask /
sahilmgandhi	18:6a4db94011d3	23435
sahilmgandhi	18:6a4db94011d3	23436	#define SPI_STATUS_SPIENSTS_Pos (15) /!< SPI STATUS: SPIENSTS Position /
sahilmgandhi	18:6a4db94011d3	23437	#define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) /!< SPI STATUS: SPIENSTS Mask /
sahilmgandhi	18:6a4db94011d3	23438
sahilmgandhi	18:6a4db94011d3	23439	#define SPI_STATUS_TXEMPTY_Pos (16) /!< SPI STATUS: TXEMPTY Position /
sahilmgandhi	18:6a4db94011d3	23440	#define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) /!< SPI STATUS: TXEMPTY Mask /
sahilmgandhi	18:6a4db94011d3	23441
sahilmgandhi	18:6a4db94011d3	23442	#define SPI_STATUS_TXFULL_Pos (17) /!< SPI STATUS: TXFULL Position /
sahilmgandhi	18:6a4db94011d3	23443	#define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) /!< SPI STATUS: TXFULL Mask /
sahilmgandhi	18:6a4db94011d3	23444
sahilmgandhi	18:6a4db94011d3	23445	#define SPI_STATUS_TXTHIF_Pos (18) /!< SPI STATUS: TXTHIF Position /
sahilmgandhi	18:6a4db94011d3	23446	#define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) /!< SPI STATUS: TXTHIF Mask /
sahilmgandhi	18:6a4db94011d3	23447
sahilmgandhi	18:6a4db94011d3	23448	#define SPI_STATUS_TXUFIF_Pos (19) /!< SPI STATUS: TXUFIF Position /
sahilmgandhi	18:6a4db94011d3	23449	#define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) /!< SPI STATUS: TXUFIF Mask /
sahilmgandhi	18:6a4db94011d3	23450
sahilmgandhi	18:6a4db94011d3	23451	#define SPI_STATUS_TXRXRST_Pos (23) /!< SPI STATUS: TXRXRST Position /
sahilmgandhi	18:6a4db94011d3	23452	#define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) /!< SPI STATUS: TXRXRST Mask /
sahilmgandhi	18:6a4db94011d3	23453
sahilmgandhi	18:6a4db94011d3	23454	#define SPI_STATUS_RXCNT_Pos (24) /!< SPI STATUS: RXCNT Position /
sahilmgandhi	18:6a4db94011d3	23455	#define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) /!< SPI STATUS: RXCNT Mask /
sahilmgandhi	18:6a4db94011d3	23456
sahilmgandhi	18:6a4db94011d3	23457	#define SPI_STATUS_TXCNT_Pos (28) /!< SPI STATUS: TXCNT Position /
sahilmgandhi	18:6a4db94011d3	23458	#define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /!< SPI STATUS: TXCNT Mask /
sahilmgandhi	18:6a4db94011d3	23459
sahilmgandhi	18:6a4db94011d3	23460	#define SPI_TX_TX_Pos (0) /!< SPI TX: TX Position /
sahilmgandhi	18:6a4db94011d3	23461	#define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) /!< SPI TX: TX Mask /
sahilmgandhi	18:6a4db94011d3	23462
sahilmgandhi	18:6a4db94011d3	23463	#define SPI_RX_RX_Pos (0) /!< SPI RX: RX Position /
sahilmgandhi	18:6a4db94011d3	23464	#define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /!< SPI RX: RX Mask /
sahilmgandhi	18:6a4db94011d3	23465
sahilmgandhi	18:6a4db94011d3	23466	/*@}/ /* SPI_CONST */
sahilmgandhi	18:6a4db94011d3	23467	/*@}/ /* end of SPI register group */
sahilmgandhi	18:6a4db94011d3	23468
sahilmgandhi	18:6a4db94011d3	23469
sahilmgandhi	18:6a4db94011d3	23470	/---------------------- System Manger Controller -------------------------/
sahilmgandhi	18:6a4db94011d3	23471	/**
sahilmgandhi	18:6a4db94011d3	23472	@addtogroup SYS System Manger Controller(SYS)
sahilmgandhi	18:6a4db94011d3	23473	Memory Mapped Structure for SYS Controller
sahilmgandhi	18:6a4db94011d3	23474	@{ */
sahilmgandhi	18:6a4db94011d3	23475
sahilmgandhi	18:6a4db94011d3	23476	typedef struct {
sahilmgandhi	18:6a4db94011d3	23477
sahilmgandhi	18:6a4db94011d3	23478
sahilmgandhi	18:6a4db94011d3	23479	/**
sahilmgandhi	18:6a4db94011d3	23480	* PDID
sahilmgandhi	18:6a4db94011d3	23481	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	23482	* Offset: 0x00 Part Device Identification Number Register
sahilmgandhi	18:6a4db94011d3	23483	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	23484	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	23485	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	23486	* \|[0:31] \|SYS_PDID \|Part Device Identification Number
sahilmgandhi	18:6a4db94011d3	23487	* \| \| \|This register reflects device part number code.
sahilmgandhi	18:6a4db94011d3	23488	* \| \| \|S/W can read this register to identify which device is used.
sahilmgandhi	18:6a4db94011d3	23489	*/
sahilmgandhi	18:6a4db94011d3	23490	__I uint32_t PDID;
sahilmgandhi	18:6a4db94011d3	23491
sahilmgandhi	18:6a4db94011d3	23492	/**
sahilmgandhi	18:6a4db94011d3	23493	* RSTSTS
sahilmgandhi	18:6a4db94011d3	23494	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	23495	* Offset: 0x04 System Reset Source Register
sahilmgandhi	18:6a4db94011d3	23496	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	23497	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	23498	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	23499	* \|[0] \|PORF \|The PORF Flag Is Set By The "Reset Signal" From The Power-On Reset (POR) Controller Or Bit CHIPRST (SYS_IPRST0[0]) To Indicate The Previous Reset Source
sahilmgandhi	18:6a4db94011d3	23500	* \| \| \|0 = No reset from POR or CHIPRST.
sahilmgandhi	18:6a4db94011d3	23501	* \| \| \|1 = Power-On Reset (POR) or CHIPRST had issued the reset signal to reset the system.
sahilmgandhi	18:6a4db94011d3	23502	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	23503	* \|[1] \|PINRF \|The PINRF Flag Is Set By The "Reset Signal" From The /RESET Pin To Indicate The Previous Reset Source
sahilmgandhi	18:6a4db94011d3	23504	* \| \| \|0 = No reset from /RESET pin.
sahilmgandhi	18:6a4db94011d3	23505	* \| \| \|1 = The Pin /RESET had issued the reset signal to reset the system.
sahilmgandhi	18:6a4db94011d3	23506	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	23507	* \|[2] \|WDTRF \|The WDTRF Flag Is Set By The "Reset Signal" From The Watchdog Timer To Indicate The Previous Reset Source
sahilmgandhi	18:6a4db94011d3	23508	* \| \| \|0 = No reset from watchdog timer.
sahilmgandhi	18:6a4db94011d3	23509	* \| \| \|1 = The watchdog timer had issued the reset signal to reset the system.
sahilmgandhi	18:6a4db94011d3	23510	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	23511	* \|[3] \|LVRF \|The LVRF Flag Is Set By The "Reset Signal" From The Low-Voltage-Reset Controller To Indicate The Previous Reset Source
sahilmgandhi	18:6a4db94011d3	23512	* \| \| \|0 = No reset from LVR.
sahilmgandhi	18:6a4db94011d3	23513	* \| \| \|1 = The LVR controller had issued the reset signal to reset the system.
sahilmgandhi	18:6a4db94011d3	23514	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	23515	* \|[4] \|BODRF \|The BODRF Flag Is Set By The "Reset Signal" From The Brown-Out-Detector To Indicate The Previous Reset Source
sahilmgandhi	18:6a4db94011d3	23516	* \| \| \|0 = No reset from BOD.
sahilmgandhi	18:6a4db94011d3	23517	* \| \| \|1 = The BOD had issued the reset signal to reset the system.
sahilmgandhi	18:6a4db94011d3	23518	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	23519	* \|[5] \|SYSRF \|The SYSRF Flag Is Set By The "Reset Signal" From The Cortex(TM)-M4 Core To Indicate The Previous Reset Source
sahilmgandhi	18:6a4db94011d3	23520	* \| \| \|0 = No reset from Cortex(TM)-M4.
sahilmgandhi	18:6a4db94011d3	23521	* \| \| \|1 = The Cortex(TM)-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex(TM)-M4 core.
sahilmgandhi	18:6a4db94011d3	23522	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	23523	* \|[7] \|CPURF \|The CPURF Flag Is Set By Hardware If Software Writes CPURST (SYS_IPRST0[1]) 1 To Reset Cortex(TM)-M4 Core And Flash Memory Controller (FMC)
sahilmgandhi	18:6a4db94011d3	23524	* \| \| \|0 = No reset from CPU.
sahilmgandhi	18:6a4db94011d3	23525	* \| \| \|1 = The Cortex(TM)-M4 Core and FMC are reset by software setting CPURST to 1.
sahilmgandhi	18:6a4db94011d3	23526	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	23527	*/
sahilmgandhi	18:6a4db94011d3	23528	__IO uint32_t RSTSTS;
sahilmgandhi	18:6a4db94011d3	23529
sahilmgandhi	18:6a4db94011d3	23530	/**
sahilmgandhi	18:6a4db94011d3	23531	* IPRST0
sahilmgandhi	18:6a4db94011d3	23532	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	23533	* Offset: 0x08 Peripheral Controller Reset Control Register 1
sahilmgandhi	18:6a4db94011d3	23534	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	23535	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	23536	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	23537	* \|[0] \|CHIPRST \|Chip One-Shot Reset (Write Protect)
sahilmgandhi	18:6a4db94011d3	23538	* \| \| \|Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
sahilmgandhi	18:6a4db94011d3	23539	* \| \| \|The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.
sahilmgandhi	18:6a4db94011d3	23540	* \| \| \|This bit is a write protected bit, which means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
sahilmgandhi	18:6a4db94011d3	23541	* \| \| \|Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
sahilmgandhi	18:6a4db94011d3	23542	* \| \| \|0 = Chip normal operation.
sahilmgandhi	18:6a4db94011d3	23543	* \| \| \|1 = Chip one shot reset.
sahilmgandhi	18:6a4db94011d3	23544	* \|[1] \|CPURST \|Processor Core One-Shot Reset (Write Protect)
sahilmgandhi	18:6a4db94011d3	23545	* \| \| \|Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles
sahilmgandhi	18:6a4db94011d3	23546	* \| \| \|This bit is a write protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
sahilmgandhi	18:6a4db94011d3	23547	* \| \| \|Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
sahilmgandhi	18:6a4db94011d3	23548	* \| \| \|0 = Processor core normal operation.
sahilmgandhi	18:6a4db94011d3	23549	* \| \| \|1 = Processor core one-shot reset.
sahilmgandhi	18:6a4db94011d3	23550	* \|[2] \|PDMARST \|PDMA Controller Reset (Write Protect)
sahilmgandhi	18:6a4db94011d3	23551	* \| \| \|Setting this bit to 1 will generate a reset signal to the PDMA.
sahilmgandhi	18:6a4db94011d3	23552	* \| \| \|User needs to set this bit to 0 to release from reset state.
sahilmgandhi	18:6a4db94011d3	23553	* \| \| \|This bit is a write protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
sahilmgandhi	18:6a4db94011d3	23554	* \| \| \|Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
sahilmgandhi	18:6a4db94011d3	23555	* \| \| \|0 = PDMA controller normal operation.
sahilmgandhi	18:6a4db94011d3	23556	* \| \| \|1 = PDMA controller reset.
sahilmgandhi	18:6a4db94011d3	23557	* \|[3] \|EBIRST \|EBI Controller Reset (Write Protect)
sahilmgandhi	18:6a4db94011d3	23558	* \| \| \|Setting this bit to 1 will generate a reset signal to the EBI.
sahilmgandhi	18:6a4db94011d3	23559	* \| \| \|User needs to set this bit to 0 to release from the reset state.
sahilmgandhi	18:6a4db94011d3	23560	* \| \| \|This bit is a write protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
sahilmgandhi	18:6a4db94011d3	23561	* \| \| \|Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
sahilmgandhi	18:6a4db94011d3	23562	* \| \| \|0 = EBI controller normal operation.
sahilmgandhi	18:6a4db94011d3	23563	* \| \| \|1 = EBI controller reset.
sahilmgandhi	18:6a4db94011d3	23564	* \|[4] \|USBHRST \|UHC Controller Reset (Write Protect)
sahilmgandhi	18:6a4db94011d3	23565	* \| \| \|Setting this bit to 1 will generate a reset signal to the HSB HOST controller.
sahilmgandhi	18:6a4db94011d3	23566	* \| \| \|User needs to set this bit to 0 to release from the reset state.
sahilmgandhi	18:6a4db94011d3	23567	* \| \| \|This bit is a write protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
sahilmgandhi	18:6a4db94011d3	23568	* \| \| \|Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
sahilmgandhi	18:6a4db94011d3	23569	* \| \| \|0 = UHC controller normal operation.
sahilmgandhi	18:6a4db94011d3	23570	* \| \| \|1 = UHC controller reset.
sahilmgandhi	18:6a4db94011d3	23571	* \|[5] \|SDHRST \|EMAC Controller Reset (Write Protect)
sahilmgandhi	18:6a4db94011d3	23572	* \| \| \|Setting this bit to 1 will generate a reset signal to the EMAC controller.
sahilmgandhi	18:6a4db94011d3	23573	* \| \| \|User needs to set this bit to 0 to release from the reset state.
sahilmgandhi	18:6a4db94011d3	23574	* \| \| \|This bit is the protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
sahilmgandhi	18:6a4db94011d3	23575	* \| \| \|Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
sahilmgandhi	18:6a4db94011d3	23576	* \| \| \|0 = EMAC controller normal operation.
sahilmgandhi	18:6a4db94011d3	23577	* \| \| \|1 = EMAC controller reset.
sahilmgandhi	18:6a4db94011d3	23578	* \|[6] \|SDHOST_RST\|SD HOST Controller Reset (Write Protect)
sahilmgandhi	18:6a4db94011d3	23579	* \| \| \|Setting this bit to 1 will generate a reset signal to the SD HOST controller.
sahilmgandhi	18:6a4db94011d3	23580	* \| \| \|User needs to set this bit to 0 to release from the reset state.
sahilmgandhi	18:6a4db94011d3	23581	* \| \| \|This bit is a write protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
sahilmgandhi	18:6a4db94011d3	23582	* \| \| \|Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
sahilmgandhi	18:6a4db94011d3	23583	* \| \| \|0 = SD HOST controller normal operation.
sahilmgandhi	18:6a4db94011d3	23584	* \| \| \|1 = SD HOST controller reset.
sahilmgandhi	18:6a4db94011d3	23585	* \|[7] \|CRCRST \|CRC Controller Reset (Write Protect)
sahilmgandhi	18:6a4db94011d3	23586	* \| \| \|Setting this bit to 1 will generate a reset signal to the CRC controller.
sahilmgandhi	18:6a4db94011d3	23587	* \| \| \|User needs to set this bit to 0 to release from the reset state.
sahilmgandhi	18:6a4db94011d3	23588	* \| \| \|This bit is a write protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
sahilmgandhi	18:6a4db94011d3	23589	* \| \| \|Reference the register SYS_REGLCTL at address GCR_BA+0x100.
sahilmgandhi	18:6a4db94011d3	23590	* \| \| \|0 = CRC controller normal operation.
sahilmgandhi	18:6a4db94011d3	23591	* \| \| \|1 = CRC controller reset.
sahilmgandhi	18:6a4db94011d3	23592	* \|[8] \|CAPRST \|Image Capture Controller Reset (Write Protect)
sahilmgandhi	18:6a4db94011d3	23593	* \| \| \|Setting this bit to 1 will generate a reset signal to the CAP controller.
sahilmgandhi	18:6a4db94011d3	23594	* \| \| \|User needs to set this bit to 0 to release from the reset state.
sahilmgandhi	18:6a4db94011d3	23595	* \| \| \|This bit is a write protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
sahilmgandhi	18:6a4db94011d3	23596	* \| \| \|Reference the register SYS_REGLCTL at address GCR_BA+0x100.
sahilmgandhi	18:6a4db94011d3	23597	* \| \| \|0 = CAP controller normal operation.
sahilmgandhi	18:6a4db94011d3	23598	* \| \| \|1 = CAP controller reset.
sahilmgandhi	18:6a4db94011d3	23599	* \|[12] \|CRPT_RST \|CRYPTO Controller Reset (Write Protect)
sahilmgandhi	18:6a4db94011d3	23600	* \| \| \|Setting this bit to 1 will generate a reset signal to the CRYPTO controller.
sahilmgandhi	18:6a4db94011d3	23601	* \| \| \|User needs to set this bit to 0 to release from the reset state.
sahilmgandhi	18:6a4db94011d3	23602	* \| \| \|This bit is a write protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
sahilmgandhi	18:6a4db94011d3	23603	* \| \| \|Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
sahilmgandhi	18:6a4db94011d3	23604	* \| \| \|0 = CRYPTO controller normal operation.
sahilmgandhi	18:6a4db94011d3	23605	* \| \| \|1 = CRYPTO controller reset.
sahilmgandhi	18:6a4db94011d3	23606	*/
sahilmgandhi	18:6a4db94011d3	23607	__IO uint32_t IPRST0;
sahilmgandhi	18:6a4db94011d3	23608
sahilmgandhi	18:6a4db94011d3	23609	/**
sahilmgandhi	18:6a4db94011d3	23610	* IPRST1
sahilmgandhi	18:6a4db94011d3	23611	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	23612	* Offset: 0x0C Peripheral Controller Reset Control Register 2
sahilmgandhi	18:6a4db94011d3	23613	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	23614	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	23615	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	23616	* \|[1] \|GPIORST \|GPIO Controller Reset
sahilmgandhi	18:6a4db94011d3	23617	* \| \| \|0 = GPIO controller normal operation.
sahilmgandhi	18:6a4db94011d3	23618	* \| \| \|1 = GPIO controller reset.
sahilmgandhi	18:6a4db94011d3	23619	* \|[2] \|TMR0RST \|Timer0 Controller Reset
sahilmgandhi	18:6a4db94011d3	23620	* \| \| \|0 = Timer0 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23621	* \| \| \|1 = Timer0 controller reset.
sahilmgandhi	18:6a4db94011d3	23622	* \|[3] \|TMR1RST \|Timer1 Controller Reset
sahilmgandhi	18:6a4db94011d3	23623	* \| \| \|0 = Timer1 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23624	* \| \| \|1 = Timer1 controller reset.
sahilmgandhi	18:6a4db94011d3	23625	* \|[4] \|TMR2RST \|Timer2 Controller Reset
sahilmgandhi	18:6a4db94011d3	23626	* \| \| \|0 = Timer2 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23627	* \| \| \|1 = Timer2 controller reset.
sahilmgandhi	18:6a4db94011d3	23628	* \|[5] \|TMR3RST \|Timer3 Controller Reset
sahilmgandhi	18:6a4db94011d3	23629	* \| \| \|0 = Timer3 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23630	* \| \| \|1 = Timer3 controller reset.
sahilmgandhi	18:6a4db94011d3	23631	* \|[7] \|ACMPRST \|Analog Comparator Controller Reset
sahilmgandhi	18:6a4db94011d3	23632	* \| \| \|0 = Analog Comparator controller normal operation.
sahilmgandhi	18:6a4db94011d3	23633	* \| \| \|1 = Analog Comparator controller reset.
sahilmgandhi	18:6a4db94011d3	23634	* \|[8] \|I2C0RST \|I2C0 Controller Reset
sahilmgandhi	18:6a4db94011d3	23635	* \| \| \|0 = I2C0 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23636	* \| \| \|1 = I2C0 controller reset.
sahilmgandhi	18:6a4db94011d3	23637	* \|[9] \|I2C1RST \|I2C1 Controller Reset
sahilmgandhi	18:6a4db94011d3	23638	* \| \| \|0 = I2C1 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23639	* \| \| \|1 = I2C1 controller reset.
sahilmgandhi	18:6a4db94011d3	23640	* \|[12] \|SPI0RST \|SPI0 Controller Reset
sahilmgandhi	18:6a4db94011d3	23641	* \| \| \|0 = SPI0 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23642	* \| \| \|1 = SPI0 controller reset.
sahilmgandhi	18:6a4db94011d3	23643	* \|[13] \|SPI1RST \|SPI1 Controller Reset
sahilmgandhi	18:6a4db94011d3	23644	* \| \| \|0 = SPI1 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23645	* \| \| \|1 = SPI1 controller reset.
sahilmgandhi	18:6a4db94011d3	23646	* \|[14] \|SPI2RST \|SPI2 Controller Reset
sahilmgandhi	18:6a4db94011d3	23647	* \| \| \|0 = SPI2 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23648	* \| \| \|1 = SPI2 controller reset.
sahilmgandhi	18:6a4db94011d3	23649	* \|[15] \|SPI3RST \|SPI3 Controller Reset
sahilmgandhi	18:6a4db94011d3	23650	* \| \| \|0 = SPI3 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23651	* \| \| \|1 = SPI3 controller reset.
sahilmgandhi	18:6a4db94011d3	23652	* \|[16] \|UART0RST \|UART0 Controller Reset
sahilmgandhi	18:6a4db94011d3	23653	* \| \| \|0 = UART0 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23654	* \| \| \|1 = UART0 controller reset.
sahilmgandhi	18:6a4db94011d3	23655	* \|[17] \|UART1RST \|UART1 Controller Reset
sahilmgandhi	18:6a4db94011d3	23656	* \| \| \|0 = UART1 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23657	* \| \| \|1 = UART1 controller reset.
sahilmgandhi	18:6a4db94011d3	23658	* \|[18] \|UART2RST \|UART2 Controller Reset
sahilmgandhi	18:6a4db94011d3	23659	* \| \| \|0 = UART2 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23660	* \| \| \|1 = UART2 controller reset.
sahilmgandhi	18:6a4db94011d3	23661	* \|[19] \|UART3RST \|UART3 Controller Reset
sahilmgandhi	18:6a4db94011d3	23662	* \| \| \|0 = UART3 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23663	* \| \| \|1 = UART3 controller reset.
sahilmgandhi	18:6a4db94011d3	23664	* \|[20] \|UART4RST \|UART4 Controller Reset
sahilmgandhi	18:6a4db94011d3	23665	* \| \| \|0 = UART4 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23666	* \| \| \|1 = UART4 controller reset.
sahilmgandhi	18:6a4db94011d3	23667	* \|[21] \|UART5RST \|UART2 Controller Reset
sahilmgandhi	18:6a4db94011d3	23668	* \| \| \|0 = UART5 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23669	* \| \| \|1 = UART5 controller reset.
sahilmgandhi	18:6a4db94011d3	23670	* \|[24] \|CAN0RST \|CAN0 Controller Reset
sahilmgandhi	18:6a4db94011d3	23671	* \| \| \|0 = CAN0 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23672	* \| \| \|1 = CAN0 controller reset.
sahilmgandhi	18:6a4db94011d3	23673	* \|[25] \|CAN1RST \|CAN1 Controller Reset
sahilmgandhi	18:6a4db94011d3	23674	* \| \| \|0 = CAN1 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23675	* \| \| \|1 = CAN1 controller reset.
sahilmgandhi	18:6a4db94011d3	23676	* \|[27] \|USBDRST \|USB Device Controller Reset
sahilmgandhi	18:6a4db94011d3	23677	* \| \| \|0 = USB device controller normal operation.
sahilmgandhi	18:6a4db94011d3	23678	* \| \| \|1 = USB device controller reset.
sahilmgandhi	18:6a4db94011d3	23679	* \|[28] \|ADCRST \|ADC Controller Reset
sahilmgandhi	18:6a4db94011d3	23680	* \| \| \|0 = ADC controller normal operation.
sahilmgandhi	18:6a4db94011d3	23681	* \| \| \|1 = ADC controller reset.
sahilmgandhi	18:6a4db94011d3	23682	* \|[29] \|I2SRST \|I2S Controller Reset
sahilmgandhi	18:6a4db94011d3	23683	* \| \| \|0 = I2S controller normal operation.
sahilmgandhi	18:6a4db94011d3	23684	* \| \| \|1 = I2S controller reset.
sahilmgandhi	18:6a4db94011d3	23685	* \|[30] \|I2S1RST \|I2S1 Controller Reset
sahilmgandhi	18:6a4db94011d3	23686	* \| \| \|0 = I2S1 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23687	* \| \| \|1 = I2S1 controller reset.
sahilmgandhi	18:6a4db94011d3	23688	* \|[31] \|PS2RST \|PS/2 Controller Reset
sahilmgandhi	18:6a4db94011d3	23689	* \| \| \|0 = PS/2 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23690	* \| \| \|1 = PS/2 controller reset.
sahilmgandhi	18:6a4db94011d3	23691	*/
sahilmgandhi	18:6a4db94011d3	23692	__IO uint32_t IPRST1;
sahilmgandhi	18:6a4db94011d3	23693
sahilmgandhi	18:6a4db94011d3	23694	/**
sahilmgandhi	18:6a4db94011d3	23695	* IPRST2
sahilmgandhi	18:6a4db94011d3	23696	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	23697	* Offset: 0x10 Peripheral Controller Reset Control Register 3
sahilmgandhi	18:6a4db94011d3	23698	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	23699	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	23700	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	23701	* \|[0] \|SC0RST \|SC0 Controller Reset
sahilmgandhi	18:6a4db94011d3	23702	* \| \| \|0 = SC0 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23703	* \| \| \|1 = SC0 controller reset.
sahilmgandhi	18:6a4db94011d3	23704	* \|[1] \|SC1RST \|SC1 Controller Reset
sahilmgandhi	18:6a4db94011d3	23705	* \| \| \|0 = SC1 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23706	* \| \| \|1 = SC1 controller reset.
sahilmgandhi	18:6a4db94011d3	23707	* \|[2] \|SC2RST \|SC2 Controller Reset
sahilmgandhi	18:6a4db94011d3	23708	* \| \| \|0 = SC2 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23709	* \| \| \|1 = SC2 controller reset.
sahilmgandhi	18:6a4db94011d3	23710	* \|[3] \|SC3RST \|SC3 Controller Reset
sahilmgandhi	18:6a4db94011d3	23711	* \| \| \|0 = SC3 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23712	* \| \| \|1 = SC3 controller reset.
sahilmgandhi	18:6a4db94011d3	23713	* \|[4] \|SC4RST \|SC4 Controller Reset
sahilmgandhi	18:6a4db94011d3	23714	* \| \| \|0 = SC4 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23715	* \| \| \|1 = SC4 controller reset.
sahilmgandhi	18:6a4db94011d3	23716	* \|[5] \|SC5RST \|SC5 Controller Reset
sahilmgandhi	18:6a4db94011d3	23717	* \| \| \|0 = SC5 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23718	* \| \| \|1 = SC5 controller reset.
sahilmgandhi	18:6a4db94011d3	23719	* \|[8] \|I2C4RST \|I2C4 Controller Reset
sahilmgandhi	18:6a4db94011d3	23720	* \| \| \|0 = I2C4 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23721	* \| \| \|1 = I2C4 controller reset.
sahilmgandhi	18:6a4db94011d3	23722	* \|[16] \|PWM0RST \|PWM0 Controller Reset
sahilmgandhi	18:6a4db94011d3	23723	* \| \| \|0 = PWM0 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23724	* \| \| \|1 = PWM0 controller reset.
sahilmgandhi	18:6a4db94011d3	23725	* \|[17] \|PWM1RST \|PWM1 Controller Reset
sahilmgandhi	18:6a4db94011d3	23726	* \| \| \|0 = PWM1 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23727	* \| \| \|1 = PWM1 controller reset.
sahilmgandhi	18:6a4db94011d3	23728	* \|[22] \|QEI0RST \|QEI0 Controller Reset
sahilmgandhi	18:6a4db94011d3	23729	* \| \| \|0 = QEI0 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23730	* \| \| \|1 = QEI0 controller reset.
sahilmgandhi	18:6a4db94011d3	23731	* \|[23] \|QEI1RST \|QEI1 Controller Reset
sahilmgandhi	18:6a4db94011d3	23732	* \| \| \|0 = QEI1 controller normal operation.
sahilmgandhi	18:6a4db94011d3	23733	* \| \| \|1 = QEI1 controller reset.
sahilmgandhi	18:6a4db94011d3	23734	*/
sahilmgandhi	18:6a4db94011d3	23735	__IO uint32_t IPRST2;
sahilmgandhi	18:6a4db94011d3	23736	uint32_t RESERVE0[1];
sahilmgandhi	18:6a4db94011d3	23737
sahilmgandhi	18:6a4db94011d3	23738
sahilmgandhi	18:6a4db94011d3	23739	/**
sahilmgandhi	18:6a4db94011d3	23740	* BODCTL
sahilmgandhi	18:6a4db94011d3	23741	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	23742	* Offset: 0x18 Brown-out Detector Control Register
sahilmgandhi	18:6a4db94011d3	23743	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	23744	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	23745	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	23746	* \|[0] \|BODEN \|Brown-Out Detector Enable Control (Write Protect)
sahilmgandhi	18:6a4db94011d3	23747	* \| \| \|The default value is set by flash controller user configuration register config0 bit[23]
sahilmgandhi	18:6a4db94011d3	23748	* \| \| \|0 = Brown-out Detector function Disabled.
sahilmgandhi	18:6a4db94011d3	23749	* \| \| \|1 = Brown-out Detector function Enabled.
sahilmgandhi	18:6a4db94011d3	23750	* \| \| \|This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
sahilmgandhi	18:6a4db94011d3	23751	* \| \| \|Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
sahilmgandhi	18:6a4db94011d3	23752	* \|[1:2] \|BODVL \|Brown-Out Detector Threshold Voltage Selection (Write Protect)
sahilmgandhi	18:6a4db94011d3	23753	* \| \| \|The default value is set by flash controller user configuration register config0 bit[22:21]
sahilmgandhi	18:6a4db94011d3	23754	* \| \| \|Relationship between BODVL and Brown-out voltage listed below:
sahilmgandhi	18:6a4db94011d3	23755	* \| \| \|00 = 2.2V.
sahilmgandhi	18:6a4db94011d3	23756	* \| \| \|01 = 2.7V.
sahilmgandhi	18:6a4db94011d3	23757	* \| \| \|10 = 3.8V.
sahilmgandhi	18:6a4db94011d3	23758	* \| \| \|11 = 4.5V.
sahilmgandhi	18:6a4db94011d3	23759	* \| \| \|This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
sahilmgandhi	18:6a4db94011d3	23760	* \| \| \|Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
sahilmgandhi	18:6a4db94011d3	23761	* \|[3] \|BODRSTEN \|Brown-Out Reset Enable Control (Write Protect)
sahilmgandhi	18:6a4db94011d3	23762	* \| \| \|While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).
sahilmgandhi	18:6a4db94011d3	23763	* \| \| \|While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high.
sahilmgandhi	18:6a4db94011d3	23764	* \| \| \|BOD interrupt will keep till to the BODEN set to 0.
sahilmgandhi	18:6a4db94011d3	23765	* \| \| \|BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).
sahilmgandhi	18:6a4db94011d3	23766	* \| \| \|The default value is set by flash controller user configuration register config0 bit[20].
sahilmgandhi	18:6a4db94011d3	23767	* \| \| \|0 = Brown-out "INTERRUPT" function Enabled.
sahilmgandhi	18:6a4db94011d3	23768	* \| \| \|1 = Brown-out "RESET" function Enabled.
sahilmgandhi	18:6a4db94011d3	23769	* \| \| \|This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
sahilmgandhi	18:6a4db94011d3	23770	* \| \| \|Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
sahilmgandhi	18:6a4db94011d3	23771	* \|[4] \|BODINTF \|Brown-Out Detector Interrupt Flag
sahilmgandhi	18:6a4db94011d3	23772	* \| \| \|0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting.
sahilmgandhi	18:6a4db94011d3	23773	* \| \| \|1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled.
sahilmgandhi	18:6a4db94011d3	23774	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	23775	* \|[5] \|BODLPM \|Brown-Out Detector Low Power Mode (Write Protect)
sahilmgandhi	18:6a4db94011d3	23776	* \| \| \|The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
sahilmgandhi	18:6a4db94011d3	23777	* \| \| \|0 = BOD operate in normal mode (default).
sahilmgandhi	18:6a4db94011d3	23778	* \| \| \|1 = BOD Low Power mode Enabled.
sahilmgandhi	18:6a4db94011d3	23779	* \| \| \|This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
sahilmgandhi	18:6a4db94011d3	23780	* \| \| \|Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
sahilmgandhi	18:6a4db94011d3	23781	* \|[6] \|BODOUT \|Brown-Out Detector Output Status
sahilmgandhi	18:6a4db94011d3	23782	* \| \| \|0 = Brown-out Detector output status is 0.
sahilmgandhi	18:6a4db94011d3	23783	* \| \| \|It means the detected voltage is higher than BODVL setting or BODEN is 0.
sahilmgandhi	18:6a4db94011d3	23784	* \| \| \|1 = Brown-out Detector output status is 1.
sahilmgandhi	18:6a4db94011d3	23785	* \| \| \|It means the detected voltage is lower than BODVL setting.
sahilmgandhi	18:6a4db94011d3	23786	* \| \| \|If the BODEN is 0, BOD function disabled , this bit always responds 0000.
sahilmgandhi	18:6a4db94011d3	23787	* \|[7] \|LVREN \|Low Voltage Reset Enable Control (Write Protect)
sahilmgandhi	18:6a4db94011d3	23788	* \| \| \|The LVR function reset the chip when the input power voltage is lower than LVR circuit setting.
sahilmgandhi	18:6a4db94011d3	23789	* \| \| \|LVR function is enabled in default.
sahilmgandhi	18:6a4db94011d3	23790	* \| \| \|0 = Low Voltage Reset function Disabled.
sahilmgandhi	18:6a4db94011d3	23791	* \| \| \|1 = Low Voltage Reset function Enabled - After enabling the bit, the LVR function will be active with 100uS delay for LVR output stable (default).
sahilmgandhi	18:6a4db94011d3	23792	* \| \| \|This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
sahilmgandhi	18:6a4db94011d3	23793	* \| \| \|Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
sahilmgandhi	18:6a4db94011d3	23794	*/
sahilmgandhi	18:6a4db94011d3	23795	__IO uint32_t BODCTL;
sahilmgandhi	18:6a4db94011d3	23796
sahilmgandhi	18:6a4db94011d3	23797	/**
sahilmgandhi	18:6a4db94011d3	23798	* TEMPCTL
sahilmgandhi	18:6a4db94011d3	23799	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	23800	* Offset: 0x1C Temperature Sensor Control Register
sahilmgandhi	18:6a4db94011d3	23801	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	23802	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	23803	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	23804	* \|[0] \|VTEMPEN \|Temperature Sensor Enable Control
sahilmgandhi	18:6a4db94011d3	23805	* \| \| \|This bit is used to enable/disable temperature sensor function.
sahilmgandhi	18:6a4db94011d3	23806	* \| \| \|0 = Temperature sensor function Disabled (default).
sahilmgandhi	18:6a4db94011d3	23807	* \| \| \|1 = Temperature sensor function Enabled.
sahilmgandhi	18:6a4db94011d3	23808	* \| \| \|After this bit is set to 1, the value of temperature sensor output can be obtained from ADC conversion result.
sahilmgandhi	18:6a4db94011d3	23809	* \| \| \|Please refer to ADC function chapter for details.
sahilmgandhi	18:6a4db94011d3	23810	*/
sahilmgandhi	18:6a4db94011d3	23811	__IO uint32_t TEMPCTL;
sahilmgandhi	18:6a4db94011d3	23812
sahilmgandhi	18:6a4db94011d3	23813	/**
sahilmgandhi	18:6a4db94011d3	23814	* VCID
sahilmgandhi	18:6a4db94011d3	23815	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	23816	* Offset: 0x20 Hardware Version Control Register
sahilmgandhi	18:6a4db94011d3	23817	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	23818	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	23819	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	23820	* \|[0:15] \|VCID \|Hardware Version Control (Ready Only)
sahilmgandhi	18:6a4db94011d3	23821	* \| \| \|These registers repress hardware version.
sahilmgandhi	18:6a4db94011d3	23822	* \| \| \|These bits are the read protected bits.
sahilmgandhi	18:6a4db94011d3	23823	* \| \| \|It means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
sahilmgandhi	18:6a4db94011d3	23824	* \| \| \|Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
sahilmgandhi	18:6a4db94011d3	23825	*/
sahilmgandhi	18:6a4db94011d3	23826	__I uint32_t VCID;
sahilmgandhi	18:6a4db94011d3	23827
sahilmgandhi	18:6a4db94011d3	23828	/**
sahilmgandhi	18:6a4db94011d3	23829	* PORCTL
sahilmgandhi	18:6a4db94011d3	23830	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	23831	* Offset: 0x24 Power-On-Reset Controller Register
sahilmgandhi	18:6a4db94011d3	23832	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	23833	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	23834	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	23835	* \|[0:15] \|POROFF \|Power-On-Reset Enable Control (Write Protect)
sahilmgandhi	18:6a4db94011d3	23836	* \| \| \|When power on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again.
sahilmgandhi	18:6a4db94011d3	23837	* \| \| \|User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
sahilmgandhi	18:6a4db94011d3	23838	* \| \| \|The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
sahilmgandhi	18:6a4db94011d3	23839	* \| \| \|/RESET, Watch dog, LVR reset, BOD reset, ICE reset command and the software-chip reset function
sahilmgandhi	18:6a4db94011d3	23840	* \| \| \|This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
sahilmgandhi	18:6a4db94011d3	23841	* \| \| \|Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
sahilmgandhi	18:6a4db94011d3	23842	*/
sahilmgandhi	18:6a4db94011d3	23843	__IO uint32_t PORCTL;
sahilmgandhi	18:6a4db94011d3	23844
sahilmgandhi	18:6a4db94011d3	23845	/**
sahilmgandhi	18:6a4db94011d3	23846	* VREFCTL
sahilmgandhi	18:6a4db94011d3	23847	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	23848	* Offset: 0x28 ADC VREF Control Register
sahilmgandhi	18:6a4db94011d3	23849	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	23850	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	23851	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	23852	* \|[0:4] \|VREFCTL \|Vref control bits (Write Protect)
sahilmgandhi	18:6a4db94011d3	23853	* \| \| \|00011=Vref is internal 2.65V
sahilmgandhi	18:6a4db94011d3	23854	* \| \| \|00111=Vref is internal 2.048V
sahilmgandhi	18:6a4db94011d3	23855	* \| \| \|01011=Vref is internal 3.072V
sahilmgandhi	18:6a4db94011d3	23856	* \| \| \|01111=Vref is internal 4.096V
sahilmgandhi	18:6a4db94011d3	23857	* \| \| \|10000=Vref is from AVDD
sahilmgandhi	18:6a4db94011d3	23858	* \| \| \|Others=Reserved
sahilmgandhi	18:6a4db94011d3	23859	* \|[8] \|ADCMODESEL\|ADC IP Selection (Write Protect)
sahilmgandhi	18:6a4db94011d3	23860	* \| \| \|0 = ADC mode.
sahilmgandhi	18:6a4db94011d3	23861	* \| \| \|1 = E ADC mode.
sahilmgandhi	18:6a4db94011d3	23862	* \|[9] \|PWMSYNCMODE\|PWM SYNC MODE (Write Protect)
sahilmgandhi	18:6a4db94011d3	23863	* \| \| \|0 = PWM SYNC MODE Disabled; PWM engine clock can different with HCLK.
sahilmgandhi	18:6a4db94011d3	23864	* \| \| \|1 = PWM SYNC MODE Enabled; PWM engine clock is same as HCLK.
sahilmgandhi	18:6a4db94011d3	23865	*/
sahilmgandhi	18:6a4db94011d3	23866	__IO uint32_t VREFCTL;
sahilmgandhi	18:6a4db94011d3	23867
sahilmgandhi	18:6a4db94011d3	23868	/**
sahilmgandhi	18:6a4db94011d3	23869	* USBPHY
sahilmgandhi	18:6a4db94011d3	23870	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	23871	* Offset: 0x2C USB PHY Control Register
sahilmgandhi	18:6a4db94011d3	23872	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	23873	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	23874	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	23875	* \|[0:1] \|USBROLE \|USB Role Configuration (Write Protect)
sahilmgandhi	18:6a4db94011d3	23876	* \| \| \|USB role configuration can be from ROMMAP or software setting if software setting option, controlled by ROMMAP, is enabled.
sahilmgandhi	18:6a4db94011d3	23877	* \| \| \|00 = Standard USB device.
sahilmgandhi	18:6a4db94011d3	23878	* \| \| \|01 = Standard USB host.
sahilmgandhi	18:6a4db94011d3	23879	* \| \| \|10 = ID dependent device.
sahilmgandhi	18:6a4db94011d3	23880	* \| \| \|11 = On-The-Go device.
sahilmgandhi	18:6a4db94011d3	23881	* \|[8] \|LDO33EN \|LDO33 Enable Control (Write Protect)
sahilmgandhi	18:6a4db94011d3	23882	* \| \| \|0 = USB LDO33 Disabled.
sahilmgandhi	18:6a4db94011d3	23883	* \| \| \|1 = USB LDO33 Enabled.
sahilmgandhi	18:6a4db94011d3	23884	*/
sahilmgandhi	18:6a4db94011d3	23885	__IO uint32_t USBPHY;
sahilmgandhi	18:6a4db94011d3	23886
sahilmgandhi	18:6a4db94011d3	23887	/**
sahilmgandhi	18:6a4db94011d3	23888	* GPA_MFPL
sahilmgandhi	18:6a4db94011d3	23889	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	23890	* Offset: 0x30 Port A Low Byte Multi-function Control Register
sahilmgandhi	18:6a4db94011d3	23891	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	23892	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	23893	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	23894	* \|[0:3] \|PA0MFP \|PA.0 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23895	* \|[4:7] \|PA1MFP \|PA.1 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23896	* \|[8:11] \|PA2MFP \|PA.2 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23897	* \|[12:15] \|PA3MFP \|PA.3 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23898	* \|[16:19] \|PA4MFP \|PA.4 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23899	* \|[20:23] \|PA5MFP \|PA.5 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23900	* \|[24:27] \|PA6MFP \|PA.6 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23901	* \|[28:31] \|PA7MFP \|PA.7 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23902	*/
sahilmgandhi	18:6a4db94011d3	23903	__IO uint32_t GPA_MFPL;
sahilmgandhi	18:6a4db94011d3	23904
sahilmgandhi	18:6a4db94011d3	23905	/**
sahilmgandhi	18:6a4db94011d3	23906	* GPA_MFPH
sahilmgandhi	18:6a4db94011d3	23907	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	23908	* Offset: 0x34 Port A High Byte Multi-function Control Register
sahilmgandhi	18:6a4db94011d3	23909	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	23910	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	23911	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	23912	* \|[0:3] \|PA8MFP \|PA.8 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23913	* \|[4:7] \|PA9MFP \|PA.9 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23914	* \|[8:11] \|PA10MFP \|PA.10 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23915	* \|[12:15] \|PA11MFP \|PA.11 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23916	* \|[16:19] \|PA12MFP \|PA.12 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23917	* \|[20:23] \|PA13MFP \|PA.13 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23918	* \|[24:27] \|PA14MFP \|PA.14 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23919	* \|[28:31] \|PA15MFP \|PA.15 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23920	*/
sahilmgandhi	18:6a4db94011d3	23921	__IO uint32_t GPA_MFPH;
sahilmgandhi	18:6a4db94011d3	23922
sahilmgandhi	18:6a4db94011d3	23923	/**
sahilmgandhi	18:6a4db94011d3	23924	* GPB_MFPL
sahilmgandhi	18:6a4db94011d3	23925	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	23926	* Offset: 0x38 Port B Low Byte Multi-function Control Register
sahilmgandhi	18:6a4db94011d3	23927	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	23928	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	23929	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	23930	* \|[0:3] \|PB0MFP \|PB.0 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23931	* \|[4:7] \|PB1MFP \|PB.1 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23932	* \|[8:11] \|PB2MFP \|PB.2 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23933	* \|[12:15] \|PB3MFP \|PB.3 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23934	* \|[16:19] \|PB4MFP \|PB.4 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23935	* \|[20:23] \|PB5MFP \|PB.5 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23936	* \|[24:27] \|PB6MFP \|PB.6 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23937	* \|[28:31] \|PB7MFP \|PB.7 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23938	*/
sahilmgandhi	18:6a4db94011d3	23939	__IO uint32_t GPB_MFPL;
sahilmgandhi	18:6a4db94011d3	23940
sahilmgandhi	18:6a4db94011d3	23941	/**
sahilmgandhi	18:6a4db94011d3	23942	* GPB_MFPH
sahilmgandhi	18:6a4db94011d3	23943	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	23944	* Offset: 0x3C Port B High Byte Multi-function Control Register
sahilmgandhi	18:6a4db94011d3	23945	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	23946	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	23947	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	23948	* \|[0:3] \|PB8MFP \|PB.8 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23949	* \|[4:7] \|PB9MFP \|PB.9 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23950	* \|[8:11] \|PB10MFP \|PB.10 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23951	* \|[12:15] \|PB11MFP \|PB.11 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23952	* \|[16:19] \|PB12MFP \|PB.12 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23953	* \|[20:23] \|PB13MFP \|PB.13 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23954	* \|[24:27] \|PB14MFP \|PB.14 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23955	* \|[28:31] \|PB15MFP \|PB.15 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23956	*/
sahilmgandhi	18:6a4db94011d3	23957	__IO uint32_t GPB_MFPH;
sahilmgandhi	18:6a4db94011d3	23958
sahilmgandhi	18:6a4db94011d3	23959	/**
sahilmgandhi	18:6a4db94011d3	23960	* GPC_MFPL
sahilmgandhi	18:6a4db94011d3	23961	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	23962	* Offset: 0x40 Port C Low Byte Multi-function Control Register
sahilmgandhi	18:6a4db94011d3	23963	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	23964	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	23965	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	23966	* \|[0:3] \|PC0MFP \|PC.0 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23967	* \|[4:7] \|PC1MFP \|PC.1 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23968	* \|[8:11] \|PC2MFP \|PC.2 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23969	* \|[12:15] \|PC3MFP \|PC.3 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23970	* \|[16:19] \|PC4MFP \|PC.4 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23971	* \|[20:23] \|PC5MFP \|PC.5 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23972	* \|[24:27] \|PC6MFP \|PC.6 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23973	* \|[28:31] \|PC7MFP \|PC.7 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23974	*/
sahilmgandhi	18:6a4db94011d3	23975	__IO uint32_t GPC_MFPL;
sahilmgandhi	18:6a4db94011d3	23976
sahilmgandhi	18:6a4db94011d3	23977	/**
sahilmgandhi	18:6a4db94011d3	23978	* GPC_MFPH
sahilmgandhi	18:6a4db94011d3	23979	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	23980	* Offset: 0x44 Port C High Byte Multi-function Control Register
sahilmgandhi	18:6a4db94011d3	23981	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	23982	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	23983	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	23984	* \|[0:3] \|PC8MFP \|PC.8 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23985	* \|[4:7] \|PC9MFP \|PC.9 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23986	* \|[8:11] \|PC10MFP \|PC.10 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23987	* \|[12:15] \|PC11MFP \|PC.11 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23988	* \|[16:19] \|PC12MFP \|PC.12 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23989	* \|[20:23] \|PC13MFP \|PC.13 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23990	* \|[24:27] \|PC14MFP \|PC.14 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23991	* \|[28:31] \|PC15MFP \|PC.15 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	23992	*/
sahilmgandhi	18:6a4db94011d3	23993	__IO uint32_t GPC_MFPH;
sahilmgandhi	18:6a4db94011d3	23994
sahilmgandhi	18:6a4db94011d3	23995	/**
sahilmgandhi	18:6a4db94011d3	23996	* GPD_MFPL
sahilmgandhi	18:6a4db94011d3	23997	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	23998	* Offset: 0x48 Port D Low Byte Multi-function Control Register
sahilmgandhi	18:6a4db94011d3	23999	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	24000	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	24001	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	24002	* \|[0:3] \|PD0MFP \|PD.0 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24003	* \|[4:7] \|PD1MFP \|PD.1 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24004	* \|[8:11] \|PD2MFP \|PD.2 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24005	* \|[12:15] \|PD3MFP \|PD.3 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24006	* \|[16:19] \|PD4MFP \|PD.4 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24007	* \|[20:23] \|PD5MFP \|PD.5 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24008	* \|[24:27] \|PD6MFP \|PD.6 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24009	* \|[28:31] \|PD7MFP \|PD.7 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24010	*/
sahilmgandhi	18:6a4db94011d3	24011	__IO uint32_t GPD_MFPL;
sahilmgandhi	18:6a4db94011d3	24012
sahilmgandhi	18:6a4db94011d3	24013	/**
sahilmgandhi	18:6a4db94011d3	24014	* GPD_MFPH
sahilmgandhi	18:6a4db94011d3	24015	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	24016	* Offset: 0x4C Port D High Byte Multi-function Control Register
sahilmgandhi	18:6a4db94011d3	24017	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	24018	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	24019	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	24020	* \|[0:3] \|PD8MFP \|PD.8 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24021	* \|[4:7] \|PD9MFP \|PD.9 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24022	* \|[8:11] \|PD10MFP \|PD.10 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24023	* \|[12:15] \|PD11MFP \|PD.11 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24024	* \|[16:19] \|PD12MFP \|PD.12 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24025	* \|[20:23] \|PD13MFP \|PD.13 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24026	* \|[24:27] \|PD14MFP \|PD.14 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24027	* \|[28:31] \|PD15MFP \|PD.15 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24028	*/
sahilmgandhi	18:6a4db94011d3	24029	__IO uint32_t GPD_MFPH;
sahilmgandhi	18:6a4db94011d3	24030
sahilmgandhi	18:6a4db94011d3	24031	/**
sahilmgandhi	18:6a4db94011d3	24032	* GPE_MFPL
sahilmgandhi	18:6a4db94011d3	24033	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	24034	* Offset: 0x50 Port E Low Byte Multi-function Control Register
sahilmgandhi	18:6a4db94011d3	24035	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	24036	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	24037	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	24038	* \|[0:3] \|PE0MFP \|PE.0 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24039	* \|[4:7] \|PE1MFP \|PE.1 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24040	* \|[8:11] \|PE2MFP \|PE.2 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24041	* \|[12:15] \|PE3MFP \|PE.3 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24042	* \|[16:19] \|PE4MFP \|PE.4 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24043	* \|[20:23] \|PE5MFP \|PE.5 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24044	* \|[24:27] \|PE6MFP \|PE.6 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24045	* \|[28:31] \|PE7MFP \|PE.7 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24046	*/
sahilmgandhi	18:6a4db94011d3	24047	__IO uint32_t GPE_MFPL;
sahilmgandhi	18:6a4db94011d3	24048
sahilmgandhi	18:6a4db94011d3	24049	/**
sahilmgandhi	18:6a4db94011d3	24050	* GPE_MFPH
sahilmgandhi	18:6a4db94011d3	24051	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	24052	* Offset: 0x54 Port E High Byte Multi-function Control Register
sahilmgandhi	18:6a4db94011d3	24053	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	24054	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	24055	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	24056	* \|[0:3] \|PE8MFP \|PE.8 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24057	* \|[4:7] \|PE9MFP \|PE.9 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24058	* \|[8:11] \|PE10MFP \|PE.10 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24059	* \|[12:15] \|PE11MFP \|PE.11 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24060	* \|[16:19] \|PE12MFP \|PE.12 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24061	* \|[20:23] \|PE13MFP \|PE.13 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24062	* \|[24:27] \|PE14MFP \|PE.14 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24063	* \|[28:31] \|PE15MFP \|PE.15 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24064	*/
sahilmgandhi	18:6a4db94011d3	24065	__IO uint32_t GPE_MFPH;
sahilmgandhi	18:6a4db94011d3	24066
sahilmgandhi	18:6a4db94011d3	24067	/**
sahilmgandhi	18:6a4db94011d3	24068	* GPF_MFPL
sahilmgandhi	18:6a4db94011d3	24069	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	24070	* Offset: 0x58 Port F Low Byte Multi-function Control Register
sahilmgandhi	18:6a4db94011d3	24071	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	24072	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	24073	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	24074	* \|[0:3] \|PF0MFP \|PF.0 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24075	* \|[4:7] \|PF1MFP \|PF.1 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24076	* \|[8:11] \|PF2MFP \|PF.2 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24077	* \|[12:15] \|PF3MFP \|PF.3 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24078	* \|[16:19] \|PF4MFP \|PF.4 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24079	* \|[20:23] \|PF5MFP \|PF.5 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24080	* \|[24:27] \|PF6MFP \|PF.6 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24081	* \|[28:31] \|PF7MFP \|PF.7 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24082	*/
sahilmgandhi	18:6a4db94011d3	24083	__IO uint32_t GPF_MFPL;
sahilmgandhi	18:6a4db94011d3	24084
sahilmgandhi	18:6a4db94011d3	24085	/**
sahilmgandhi	18:6a4db94011d3	24086	* GPF_MFPH
sahilmgandhi	18:6a4db94011d3	24087	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	24088	* Offset: 0x5C Port F High Byte Multi-function Control Register
sahilmgandhi	18:6a4db94011d3	24089	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	24090	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	24091	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	24092	* \|[0:3] \|PF8MFP \|PF.8 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24093	* \|[4:7] \|PF9MFP \|PF.9 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24094	* \|[8:11] \|PF10MFP \|PF.10 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24095	* \|[12:15] \|PF11MFP \|PF.11 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24096	* \|[16:19] \|PF12MFP \|PF.12 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24097	* \|[20:23] \|PF13MFP \|PF.13 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24098	* \|[24:27] \|PF14MFP \|PF.14 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24099	* \|[28:31] \|PF15MFP \|PF.15 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24100	*/
sahilmgandhi	18:6a4db94011d3	24101	__IO uint32_t GPF_MFPH;
sahilmgandhi	18:6a4db94011d3	24102
sahilmgandhi	18:6a4db94011d3	24103	/**
sahilmgandhi	18:6a4db94011d3	24104	* GPG_MFPL
sahilmgandhi	18:6a4db94011d3	24105	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	24106	* Offset: 0x60 Port G Low Byte Multi-function Control Register
sahilmgandhi	18:6a4db94011d3	24107	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	24108	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	24109	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	24110	* \|[0:3] \|PG0MFP \|PG.0 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24111	* \|[4:7] \|PG1MFP \|PG.1 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24112	* \|[8:11] \|PG2MFP \|PG.2 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24113	* \|[12:15] \|PG3MFP \|PG.3 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24114	* \|[16:19] \|PG4MFP \|PG.4 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24115	* \|[20:23] \|PG5MFP \|PG.5 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24116	* \|[24:27] \|PG6MFP \|PG.6 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24117	* \|[28:31] \|PG7MFP \|PG.7 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24118	*/
sahilmgandhi	18:6a4db94011d3	24119	__IO uint32_t GPG_MFPL;
sahilmgandhi	18:6a4db94011d3	24120
sahilmgandhi	18:6a4db94011d3	24121	/**
sahilmgandhi	18:6a4db94011d3	24122	* GPG_MFPH
sahilmgandhi	18:6a4db94011d3	24123	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	24124	* Offset: 0x64 Port G High Byte Multi-function Control Register
sahilmgandhi	18:6a4db94011d3	24125	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	24126	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	24127	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	24128	* \|[0:3] \|PG8MFP \|PG.8 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24129	* \|[4:7] \|PG9MFP \|PG.9 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24130	* \|[8:11] \|PG10MFP \|PG.10 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24131	* \|[12:15] \|PG11MFP \|PG.11 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24132	* \|[16:19] \|PG12MFP \|PG.12 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24133	* \|[20:23] \|PG13MFP \|PG.13 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24134	* \|[24:27] \|PG14MFP \|PG.14 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24135	* \|[28:31] \|PG15MFP \|PG.15 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24136	*/
sahilmgandhi	18:6a4db94011d3	24137	__IO uint32_t GPG_MFPH;
sahilmgandhi	18:6a4db94011d3	24138
sahilmgandhi	18:6a4db94011d3	24139	/**
sahilmgandhi	18:6a4db94011d3	24140	* GPH_MFPL
sahilmgandhi	18:6a4db94011d3	24141	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	24142	* Offset: 0x68 Port H Low Byte Multi-function Control Register
sahilmgandhi	18:6a4db94011d3	24143	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	24144	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	24145	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	24146	* \|[0:3] \|PH0MFP \|PH.0 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24147	* \|[4:7] \|PH1MFP \|PH.1 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24148	* \|[8:11] \|PH2MFP \|PH.2 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24149	* \|[12:15] \|PH3MFP \|PH.3 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24150	* \|[16:19] \|PH4MFP \|PH.4 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24151	* \|[20:23] \|PH5MFP \|PH.5 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24152	* \|[24:27] \|PH6MFP \|PH.6 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24153	* \|[28:31] \|PH7MFP \|PH.7 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24154	*/
sahilmgandhi	18:6a4db94011d3	24155	__IO uint32_t GPH_MFPL;
sahilmgandhi	18:6a4db94011d3	24156
sahilmgandhi	18:6a4db94011d3	24157	/**
sahilmgandhi	18:6a4db94011d3	24158	* GPH_MFPH
sahilmgandhi	18:6a4db94011d3	24159	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	24160	* Offset: 0x6C Port H High Byte Multi-function Control Register
sahilmgandhi	18:6a4db94011d3	24161	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	24162	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	24163	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	24164	* \|[0:3] \|PH8MFP \|PH.8 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24165	* \|[4:7] \|PH9MFP \|PH.9 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24166	* \|[8:11] \|PH10MFP \|PH.10 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24167	* \|[12:15] \|PH11MFP \|PH.11 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24168	* \|[16:19] \|PH12MFP \|PH.12 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24169	* \|[20:23] \|PH13MFP \|PH.13 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24170	* \|[24:27] \|PH14MFP \|PH.14 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24171	* \|[28:31] \|PH15MFP \|PH.15 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24172	*/
sahilmgandhi	18:6a4db94011d3	24173	__IO uint32_t GPH_MFPH;
sahilmgandhi	18:6a4db94011d3	24174
sahilmgandhi	18:6a4db94011d3	24175	/**
sahilmgandhi	18:6a4db94011d3	24176	* GPI_MFPL
sahilmgandhi	18:6a4db94011d3	24177	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	24178	* Offset: 0x70 Port I Low Byte Multi-function Control Register
sahilmgandhi	18:6a4db94011d3	24179	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	24180	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	24181	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	24182	* \|[0:3] \|PI0MFP \|PI.0 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24183	* \|[4:7] \|PI1MFP \|PI.1 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24184	* \|[8:11] \|PI2MFP \|PI.2 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24185	* \|[12:15] \|PI3MFP \|PI.3 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24186	* \|[16:19] \|PI4MFP \|PI.4 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24187	* \|[20:23] \|PI5MFP \|PI.5 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24188	* \|[24:27] \|PI6MFP \|PI.6 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24189	* \|[28:31] \|PI7MFP \|PI.7 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24190	*/
sahilmgandhi	18:6a4db94011d3	24191	__IO uint32_t GPI_MFPL;
sahilmgandhi	18:6a4db94011d3	24192
sahilmgandhi	18:6a4db94011d3	24193	/**
sahilmgandhi	18:6a4db94011d3	24194	* GPI_MFPH
sahilmgandhi	18:6a4db94011d3	24195	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	24196	* Offset: 0x74 Port I High Byte Multi-function Control Register
sahilmgandhi	18:6a4db94011d3	24197	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	24198	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	24199	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	24200	* \|[0:3] \|PI8MFP \|PI.8 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24201	* \|[4:7] \|PI9MFP \|PI.9 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24202	* \|[8:11] \|PI10MFP \|PI.10 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24203	* \|[12:15] \|PI11MFP \|PI.11 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24204	* \|[16:19] \|PI12MFP \|PI.12 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24205	* \|[20:23] \|PI13MFP \|PI.13 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24206	* \|[24:27] \|PI14MFP \|PI.14 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24207	* \|[28:31] \|PI15MFP \|PI.15 Multi-function Pin Selection
sahilmgandhi	18:6a4db94011d3	24208	*/
sahilmgandhi	18:6a4db94011d3	24209	__IO uint32_t GPI_MFPH;
sahilmgandhi	18:6a4db94011d3	24210	uint32_t RESERVE1[18];
sahilmgandhi	18:6a4db94011d3	24211
sahilmgandhi	18:6a4db94011d3	24212
sahilmgandhi	18:6a4db94011d3	24213	/**
sahilmgandhi	18:6a4db94011d3	24214	* SRAM_INTCTL
sahilmgandhi	18:6a4db94011d3	24215	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	24216	* Offset: 0xC0 SRAM Failed Interrupt Enable Control Register
sahilmgandhi	18:6a4db94011d3	24217	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	24218	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	24219	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	24220	* \|[0] \|PERRIEN \|SRAM Parity Check Fail Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	24221	* \| \| \|0 = SRAMF INT Disabled.
sahilmgandhi	18:6a4db94011d3	24222	* \| \| \|1 = SRAMF INT Enabled when SRAM fail flag.
sahilmgandhi	18:6a4db94011d3	24223	*/
sahilmgandhi	18:6a4db94011d3	24224	__IO uint32_t SRAM_INTCTL;
sahilmgandhi	18:6a4db94011d3	24225
sahilmgandhi	18:6a4db94011d3	24226	/**
sahilmgandhi	18:6a4db94011d3	24227	* SRAM_STATUS
sahilmgandhi	18:6a4db94011d3	24228	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	24229	* Offset: 0xC4 SRAM Parity Check Error Flag
sahilmgandhi	18:6a4db94011d3	24230	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	24231	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	24232	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	24233	* \|[0] \|PERRIF0 \|SRAM Parity Check Fail Flag
sahilmgandhi	18:6a4db94011d3	24234	* \| \| \|0 = No first 1 SRAM fail.
sahilmgandhi	18:6a4db94011d3	24235	* \| \| \|1 = First SRAM Fail.
sahilmgandhi	18:6a4db94011d3	24236	* \|[1] \|PERRIF1 \|SRAM Parity Check Fail Flag
sahilmgandhi	18:6a4db94011d3	24237	* \| \| \|0 = 2nd SRAM fail.
sahilmgandhi	18:6a4db94011d3	24238	* \| \| \|1 = 2nd SRAM Fail.
sahilmgandhi	18:6a4db94011d3	24239	*/
sahilmgandhi	18:6a4db94011d3	24240	__IO uint32_t SRAM_STATUS;
sahilmgandhi	18:6a4db94011d3	24241
sahilmgandhi	18:6a4db94011d3	24242	/**
sahilmgandhi	18:6a4db94011d3	24243	* SRAM0_ERRADDR
sahilmgandhi	18:6a4db94011d3	24244	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	24245	* Offset: 0xC8 SRAM Parity Check Error First Address1
sahilmgandhi	18:6a4db94011d3	24246	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	24247	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	24248	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	24249	* \|[0:31] \|PERRADDR \|First SRAM parity check fail address
sahilmgandhi	18:6a4db94011d3	24250	*/
sahilmgandhi	18:6a4db94011d3	24251	__I uint32_t SRAM0_ERRADDR;
sahilmgandhi	18:6a4db94011d3	24252
sahilmgandhi	18:6a4db94011d3	24253	/**
sahilmgandhi	18:6a4db94011d3	24254	* SRAM1_ERRADDR
sahilmgandhi	18:6a4db94011d3	24255	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	24256	* Offset: 0xCC SRAM Parity Check Error First Address2
sahilmgandhi	18:6a4db94011d3	24257	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	24258	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	24259	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	24260	* \|[0:31] \|PERRADDR \|2nd
sahilmgandhi	18:6a4db94011d3	24261	* \| \| \|SRAM parity check fail address
sahilmgandhi	18:6a4db94011d3	24262	*/
sahilmgandhi	18:6a4db94011d3	24263	__I uint32_t SRAM1_ERRADDR;
sahilmgandhi	18:6a4db94011d3	24264	uint32_t RESERVE2[8];
sahilmgandhi	18:6a4db94011d3	24265
sahilmgandhi	18:6a4db94011d3	24266
sahilmgandhi	18:6a4db94011d3	24267	/**
sahilmgandhi	18:6a4db94011d3	24268	* IRCTCTL
sahilmgandhi	18:6a4db94011d3	24269	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	24270	* Offset: 0xF0 IRC Trim Control Register
sahilmgandhi	18:6a4db94011d3	24271	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	24272	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	24273	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	24274	* \|[0:1] \|FREQSEL \|Trim Frequency Selection
sahilmgandhi	18:6a4db94011d3	24275	* \| \| \|This field indicates the target frequency of HIRC auto trim.
sahilmgandhi	18:6a4db94011d3	24276	* \| \| \|If no any target frequency is selected (FREQSEL is 00), the HIRC auto trim function is disabled.
sahilmgandhi	18:6a4db94011d3	24277	* \| \| \|During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
sahilmgandhi	18:6a4db94011d3	24278	* \| \| \|00 = Disable HIRC auto trim function.
sahilmgandhi	18:6a4db94011d3	24279	* \| \| \|01 = Enable HIRC auto trim function and trim HIRC to 22.1184 MHz.
sahilmgandhi	18:6a4db94011d3	24280	* \| \| \|10 = Enable HIRC auto trim function and trim HIRC to 24 MHz.
sahilmgandhi	18:6a4db94011d3	24281	* \| \| \|11 = Reserved.
sahilmgandhi	18:6a4db94011d3	24282	* \|[4:5] \|LOOPSEL \|Trim Calculation Loop
sahilmgandhi	18:6a4db94011d3	24283	* \| \| \|This field defines that trim value calculation is based on how many 32.768 kHz clock.
sahilmgandhi	18:6a4db94011d3	24284	* \| \| \|For example, if CALCLOOP is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.
sahilmgandhi	18:6a4db94011d3	24285	* \| \| \|00 = Trim value calculation is based on average difference in 4 32.768 kHz clock.
sahilmgandhi	18:6a4db94011d3	24286	* \| \| \|01 = Trim value calculation is based on average difference in 8 32.768 kHz clock.
sahilmgandhi	18:6a4db94011d3	24287	* \| \| \|10 = Trim value calculation is based on average difference in 16 32.768 kHz clock.
sahilmgandhi	18:6a4db94011d3	24288	* \| \| \|11 = Trim value calculation is based on average difference in 32 32.768 kHz clock.
sahilmgandhi	18:6a4db94011d3	24289	* \|[6:7] \|RETRYCNT \|Trim Value Update Limitation Count
sahilmgandhi	18:6a4db94011d3	24290	* \| \| \|This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.
sahilmgandhi	18:6a4db94011d3	24291	* \| \| \|Once the HIRC locked, the internal trim value update counter will be reset.
sahilmgandhi	18:6a4db94011d3	24292	* \| \| \|If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
sahilmgandhi	18:6a4db94011d3	24293	* \| \| \|00 = Trim retry count limitation is 64.
sahilmgandhi	18:6a4db94011d3	24294	* \| \| \|01 = Trim retry count limitation is 128.
sahilmgandhi	18:6a4db94011d3	24295	* \| \| \|10 = Trim retry count limitation is 256.
sahilmgandhi	18:6a4db94011d3	24296	* \| \| \|11 = Trim retry count limitation is 512.
sahilmgandhi	18:6a4db94011d3	24297	* \|[8] \|CESTOPEN \|Clock Error Stop Enable Control
sahilmgandhi	18:6a4db94011d3	24298	* \| \| \|0 = The trim operation is keep going if clock is inaccuracy.
sahilmgandhi	18:6a4db94011d3	24299	* \| \| \|1 = The trim operation is stopped if clock is inaccuracy.
sahilmgandhi	18:6a4db94011d3	24300	*/
sahilmgandhi	18:6a4db94011d3	24301	__IO uint32_t IRCTCTL;
sahilmgandhi	18:6a4db94011d3	24302
sahilmgandhi	18:6a4db94011d3	24303	/**
sahilmgandhi	18:6a4db94011d3	24304	* IRCTIEN
sahilmgandhi	18:6a4db94011d3	24305	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	24306	* Offset: 0xF4 IRC Trim Interrupt Enable Control Register
sahilmgandhi	18:6a4db94011d3	24307	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	24308	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	24309	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	24310	* \|[1] \|TFAILIEN \|Trim Failure Interrupt Enable
sahilmgandhi	18:6a4db94011d3	24311	* \| \| \|This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL.
sahilmgandhi	18:6a4db94011d3	24312	* \| \| \|If this bit is high and TFAILIF is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
sahilmgandhi	18:6a4db94011d3	24313	* \| \| \|0 = Disable TFAILIF status to trigger an interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	24314	* \| \| \|1 = Enable TFAILIF status to trigger an interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	24315	* \|[2] \|CLKEIEN \|Clock Error Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	24316	* \| \| \|This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.
sahilmgandhi	18:6a4db94011d3	24317	* \| \| \|If this bit is set to1, and CLKERRIF is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
sahilmgandhi	18:6a4db94011d3	24318	* \| \| \|0 = Disable CLKERRIF status to trigger an interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	24319	* \| \| \|1 = Enable CLKERRIF status to trigger an interrupt to CPU.
sahilmgandhi	18:6a4db94011d3	24320	*/
sahilmgandhi	18:6a4db94011d3	24321	__IO uint32_t IRCTIEN;
sahilmgandhi	18:6a4db94011d3	24322
sahilmgandhi	18:6a4db94011d3	24323	/**
sahilmgandhi	18:6a4db94011d3	24324	* IRCTISTS
sahilmgandhi	18:6a4db94011d3	24325	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	24326	* Offset: 0xF8 IRC Trim Interrupt Status Register
sahilmgandhi	18:6a4db94011d3	24327	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	24328	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	24329	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	24330	* \|[0] \|FREQLOCK \|HIRC Frequency Lock Status
sahilmgandhi	18:6a4db94011d3	24331	* \| \| \|This bit indicates the HIRC frequency is locked.
sahilmgandhi	18:6a4db94011d3	24332	* \| \| \|This is a status bit and doesn't trigger any interrupt.
sahilmgandhi	18:6a4db94011d3	24333	* \|[1] \|TFAILIF \|Trim Failure Interrupt Status
sahilmgandhi	18:6a4db94011d3	24334	* \| \| \|This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked.
sahilmgandhi	18:6a4db94011d3	24335	* \| \| \|Once this bit is set, the auto trim operation stopped and FREQSEL will be cleared to 00 by hardware automatically.
sahilmgandhi	18:6a4db94011d3	24336	* \| \| \|If this bit is set and TFAILIEN is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
sahilmgandhi	18:6a4db94011d3	24337	* \| \| \|Write 1 to clear this to 0.
sahilmgandhi	18:6a4db94011d3	24338	* \| \| \|0 = Trim value update limitation count does not reach.
sahilmgandhi	18:6a4db94011d3	24339	* \| \| \|1 = Trim value update limitation count reached and HIRC frequency still not locked.
sahilmgandhi	18:6a4db94011d3	24340	* \|[2] \|CLKERRIF \|Clock Error Interrupt Status
sahilmgandhi	18:6a4db94011d3	24341	* \| \| \|When the frequency of external 32.768 kHz low-speed crystal or HIRC is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy
sahilmgandhi	18:6a4db94011d3	24342	* \| \| \|Once this bit is set to 1, the auto trim operation stopped and FREQSEL will be cleared to 00 by hardware automatically if CESTOPEN is set to 1.
sahilmgandhi	18:6a4db94011d3	24343	* \| \| \|If this bit is set and CLKEIEN is high, an interrupt will be triggered to notify the clock frequency is inaccuracy.
sahilmgandhi	18:6a4db94011d3	24344	* \| \| \|Write 1 to clear this to 0.
sahilmgandhi	18:6a4db94011d3	24345	* \| \| \|0 = Clock frequency is accuracy.
sahilmgandhi	18:6a4db94011d3	24346	* \| \| \|1 = Clock frequency is inaccuracy.
sahilmgandhi	18:6a4db94011d3	24347	*/
sahilmgandhi	18:6a4db94011d3	24348	__IO uint32_t IRCTISTS;
sahilmgandhi	18:6a4db94011d3	24349	uint32_t RESERVE3[1];
sahilmgandhi	18:6a4db94011d3	24350
sahilmgandhi	18:6a4db94011d3	24351
sahilmgandhi	18:6a4db94011d3	24352	/**
sahilmgandhi	18:6a4db94011d3	24353	* REGLCTL
sahilmgandhi	18:6a4db94011d3	24354	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	24355	* Offset: 0x100 Register Write-Protection Control Register
sahilmgandhi	18:6a4db94011d3	24356	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	24357	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	24358	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	24359	* \|[0] \|REGLCTL \|Register Write-Protection Disable Index (Read Only)
sahilmgandhi	18:6a4db94011d3	24360	* \| \| \|0 = Write-protection Enabled for writing protected registers.
sahilmgandhi	18:6a4db94011d3	24361	* \| \| \|Any write to the protected register is ignored.
sahilmgandhi	18:6a4db94011d3	24362	* \| \| \|1 = Write-protection Disabled for writing protected registers.
sahilmgandhi	18:6a4db94011d3	24363	* \| \| \|The Protected registers are:
sahilmgandhi	18:6a4db94011d3	24364	* \| \| \|SYS_IPRST0: address 0x4000_0008
sahilmgandhi	18:6a4db94011d3	24365	* \| \| \|SYS_BODCTL: address 0x4000_0018
sahilmgandhi	18:6a4db94011d3	24366	* \| \| \|SYS_PORCTL: address 0x4000_0024
sahilmgandhi	18:6a4db94011d3	24367	* \| \| \|PWRCON: address 0x4000_0200 (bit[6] is not protected for power wake-up interrupt clear)
sahilmgandhi	18:6a4db94011d3	24368	* \| \| \|APBCLK bit[0]: address 0x4000_0208 (bit[0] is watchdog clock enable)
sahilmgandhi	18:6a4db94011d3	24369	* \| \| \|CLKSEL0: address 0x4000_0210 (for HCLK and CPU STCLK clock source select)
sahilmgandhi	18:6a4db94011d3	24370	* \| \| \|CLKSEL1 bit[1:0]: address 0x4000_0214 (for watchdog clock source select)
sahilmgandhi	18:6a4db94011d3	24371	* \| \| \|NMI_SEL]: address 0x4000_0300 (for NMI source select)
sahilmgandhi	18:6a4db94011d3	24372	* \| \| \|ISPCON: address 0x4000_5000 (Flash ISP Control register)
sahilmgandhi	18:6a4db94011d3	24373	* \| \| \|ISPTRG: address 0x4000_5010 (ISP Trigger Control register)
sahilmgandhi	18:6a4db94011d3	24374	* \| \| \|WTCR: address 0x4004_0000
sahilmgandhi	18:6a4db94011d3	24375	* \| \| \|FATCON: address 0x4000_5018
sahilmgandhi	18:6a4db94011d3	24376	* \| \| \|TAMPER: address 0x400E_1000
sahilmgandhi	18:6a4db94011d3	24377	* \|[0:7] \|SYS_REGLCTL\|Register Write-Protection Code (Write Only)
sahilmgandhi	18:6a4db94011d3	24378	* \| \| \|Some registers have write-protection function.
sahilmgandhi	18:6a4db94011d3	24379	* \| \| \|Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field.
sahilmgandhi	18:6a4db94011d3	24380	* \| \| \|After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
sahilmgandhi	18:6a4db94011d3	24381	*/
sahilmgandhi	18:6a4db94011d3	24382	__IO uint32_t REGLCTL;
sahilmgandhi	18:6a4db94011d3	24383
sahilmgandhi	18:6a4db94011d3	24384	} SYS_T;
sahilmgandhi	18:6a4db94011d3	24385
sahilmgandhi	18:6a4db94011d3	24386	/**
sahilmgandhi	18:6a4db94011d3	24387	@addtogroup SYS_CONST SYS Bit Field Definition
sahilmgandhi	18:6a4db94011d3	24388	Constant Definitions for SYS Controller
sahilmgandhi	18:6a4db94011d3	24389	@{ */
sahilmgandhi	18:6a4db94011d3	24390
sahilmgandhi	18:6a4db94011d3	24391	#define SYS_PDID_SYS_PDID_Pos (0) /!< SYS PDID: SYS_PDID Position /
sahilmgandhi	18:6a4db94011d3	24392	#define SYS_PDID_SYS_PDID_Msk (0xfffffffful << SYS_PDID_SYS_PDID_Pos) /!< SYS PDID: SYS_PDID Mask /
sahilmgandhi	18:6a4db94011d3	24393
sahilmgandhi	18:6a4db94011d3	24394	#define SYS_RSTSTS_PORF_Pos (0) /!< SYS RSTSTS: PORF Position /
sahilmgandhi	18:6a4db94011d3	24395	#define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) /!< SYS RSTSTS: PORF Mask /
sahilmgandhi	18:6a4db94011d3	24396
sahilmgandhi	18:6a4db94011d3	24397	#define SYS_RSTSTS_PINRF_Pos (1) /!< SYS RSTSTS: PINRF Position /
sahilmgandhi	18:6a4db94011d3	24398	#define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) /!< SYS RSTSTS: PINRF Mask /
sahilmgandhi	18:6a4db94011d3	24399
sahilmgandhi	18:6a4db94011d3	24400	#define SYS_RSTSTS_WDTRF_Pos (2) /!< SYS RSTSTS: WDTRF Position /
sahilmgandhi	18:6a4db94011d3	24401	#define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) /!< SYS RSTSTS: WDTRF Mask /
sahilmgandhi	18:6a4db94011d3	24402
sahilmgandhi	18:6a4db94011d3	24403	#define SYS_RSTSTS_LVRF_Pos (3) /!< SYS RSTSTS: LVRF Position /
sahilmgandhi	18:6a4db94011d3	24404	#define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) /!< SYS RSTSTS: LVRF Mask /
sahilmgandhi	18:6a4db94011d3	24405
sahilmgandhi	18:6a4db94011d3	24406	#define SYS_RSTSTS_BODRF_Pos (4) /!< SYS RSTSTS: BODRF Position /
sahilmgandhi	18:6a4db94011d3	24407	#define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) /!< SYS RSTSTS: BODRF Mask /
sahilmgandhi	18:6a4db94011d3	24408
sahilmgandhi	18:6a4db94011d3	24409	#define SYS_RSTSTS_SYSRF_Pos (5) /!< SYS RSTSTS: SYSRF Position /
sahilmgandhi	18:6a4db94011d3	24410	#define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) /!< SYS RSTSTS: SYSRF Mask /
sahilmgandhi	18:6a4db94011d3	24411
sahilmgandhi	18:6a4db94011d3	24412	#define SYS_RSTSTS_CPURF_Pos (7) /!< SYS RSTSTS: CPURF Position /
sahilmgandhi	18:6a4db94011d3	24413	#define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) /!< SYS RSTSTS: CPURF Mask /
sahilmgandhi	18:6a4db94011d3	24414
sahilmgandhi	18:6a4db94011d3	24415	#define SYS_IPRST0_CHIPRST_Pos (0) /!< SYS IPRST0: CHIPRST Position /
sahilmgandhi	18:6a4db94011d3	24416	#define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) /!< SYS IPRST0: CHIPRST Mask /
sahilmgandhi	18:6a4db94011d3	24417
sahilmgandhi	18:6a4db94011d3	24418	#define SYS_IPRST0_CPURST_Pos (1) /!< SYS IPRST0: CPURST Position /
sahilmgandhi	18:6a4db94011d3	24419	#define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) /!< SYS IPRST0: CPURST Mask /
sahilmgandhi	18:6a4db94011d3	24420
sahilmgandhi	18:6a4db94011d3	24421	#define SYS_IPRST0_PDMARST_Pos (2) /!< SYS IPRST0: PDMARST Position /
sahilmgandhi	18:6a4db94011d3	24422	#define SYS_IPRST0_PDMARST_Msk (0x1ul << SYS_IPRST0_PDMARST_Pos) /!< SYS IPRST0: PDMARST Mask /
sahilmgandhi	18:6a4db94011d3	24423
sahilmgandhi	18:6a4db94011d3	24424	#define SYS_IPRST0_EBIRST_Pos (3) /!< SYS IPRST0: EBIRST Position /
sahilmgandhi	18:6a4db94011d3	24425	#define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) /!< SYS IPRST0: EBIRST Mask /
sahilmgandhi	18:6a4db94011d3	24426
sahilmgandhi	18:6a4db94011d3	24427	#define SYS_IPRST0_USBHRST_Pos (4) /!< SYS IPRST0: USBHRST Position /
sahilmgandhi	18:6a4db94011d3	24428	#define SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos) /!< SYS IPRST0: USBHRST Mask /
sahilmgandhi	18:6a4db94011d3	24429
sahilmgandhi	18:6a4db94011d3	24430	#define SYS_IPRST0_SDHRST_Pos (5) /!< SYS IPRST0: SDHRST Position /
sahilmgandhi	18:6a4db94011d3	24431	#define SYS_IPRST0_SDHRST_Msk (0x1ul << SYS_IPRST0_SDHRST_Pos) /!< SYS IPRST0: SDHRST Mask /
sahilmgandhi	18:6a4db94011d3	24432
sahilmgandhi	18:6a4db94011d3	24433	#define SYS_IPRST0_SDHOST_RST_Pos (6) /!< SYS IPRST0: SDHOST_RST Position /
sahilmgandhi	18:6a4db94011d3	24434	#define SYS_IPRST0_SDHOST_RST_Msk (0x1ul << SYS_IPRST0_SDHOST_RST_Pos) /!< SYS IPRST0: SDHOST_RST Mask /
sahilmgandhi	18:6a4db94011d3	24435
sahilmgandhi	18:6a4db94011d3	24436	#define SYS_IPRST0_CRCRST_Pos (7) /!< SYS IPRST0: CRCRST Position /
sahilmgandhi	18:6a4db94011d3	24437	#define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) /!< SYS IPRST0: CRCRST Mask /
sahilmgandhi	18:6a4db94011d3	24438
sahilmgandhi	18:6a4db94011d3	24439	#define SYS_IPRST0_CAPRST_Pos (8) /!< SYS IPRST0: CAPRST Position /
sahilmgandhi	18:6a4db94011d3	24440	#define SYS_IPRST0_CAPRST_Msk (0x1ul << SYS_IPRST0_CAPRST_Pos) /!< SYS IPRST0: CAPRST Mask /
sahilmgandhi	18:6a4db94011d3	24441
sahilmgandhi	18:6a4db94011d3	24442	#define SYS_IPRST0_CRPTRST_Pos (12) /!< SYS IPRST0: CRPTRST Position /
sahilmgandhi	18:6a4db94011d3	24443	#define SYS_IPRST0_CRPTRST_Msk (0x1ul << SYS_IPRST0_CRPTRST_Pos) /!< SYS IPRST0: CRPTRST Mask /
sahilmgandhi	18:6a4db94011d3	24444
sahilmgandhi	18:6a4db94011d3	24445	#define SYS_IPRST1_GPIORST_Pos (1) /!< SYS IPRST1: GPIORST Position /
sahilmgandhi	18:6a4db94011d3	24446	#define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) /!< SYS IPRST1: GPIORST Mask /
sahilmgandhi	18:6a4db94011d3	24447
sahilmgandhi	18:6a4db94011d3	24448	#define SYS_IPRST1_TMR0RST_Pos (2) /!< SYS IPRST1: TMR0RST Position /
sahilmgandhi	18:6a4db94011d3	24449	#define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) /!< SYS IPRST1: TMR0RST Mask /
sahilmgandhi	18:6a4db94011d3	24450
sahilmgandhi	18:6a4db94011d3	24451	#define SYS_IPRST1_TMR1RST_Pos (3) /!< SYS IPRST1: TMR1RST Position /
sahilmgandhi	18:6a4db94011d3	24452	#define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) /!< SYS IPRST1: TMR1RST Mask /
sahilmgandhi	18:6a4db94011d3	24453
sahilmgandhi	18:6a4db94011d3	24454	#define SYS_IPRST1_TMR2RST_Pos (4) /!< SYS IPRST1: TMR2RST Position /
sahilmgandhi	18:6a4db94011d3	24455	#define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) /!< SYS IPRST1: TMR2RST Mask /
sahilmgandhi	18:6a4db94011d3	24456
sahilmgandhi	18:6a4db94011d3	24457	#define SYS_IPRST1_TMR3RST_Pos (5) /!< SYS IPRST1: TMR3RST Position /
sahilmgandhi	18:6a4db94011d3	24458	#define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) /!< SYS IPRST1: TMR3RST Mask /
sahilmgandhi	18:6a4db94011d3	24459
sahilmgandhi	18:6a4db94011d3	24460	#define SYS_IPRST1_ACMPRST_Pos (7) /!< SYS IPRST1: ACMPRST Position /
sahilmgandhi	18:6a4db94011d3	24461	#define SYS_IPRST1_ACMPRST_Msk (0x1ul << SYS_IPRST1_ACMPRST_Pos) /!< SYS IPRST1: ACMPRST Mask /
sahilmgandhi	18:6a4db94011d3	24462
sahilmgandhi	18:6a4db94011d3	24463	#define SYS_IPRST1_I2C0RST_Pos (8) /!< SYS IPRST1: I2C0RST Position /
sahilmgandhi	18:6a4db94011d3	24464	#define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) /!< SYS IPRST1: I2C0RST Mask /
sahilmgandhi	18:6a4db94011d3	24465
sahilmgandhi	18:6a4db94011d3	24466	#define SYS_IPRST1_I2C1RST_Pos (9) /!< SYS IPRST1: I2C1RST Position /
sahilmgandhi	18:6a4db94011d3	24467	#define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) /!< SYS IPRST1: I2C1RST Mask /
sahilmgandhi	18:6a4db94011d3	24468
sahilmgandhi	18:6a4db94011d3	24469	#define SYS_IPRST1_I2C2RST_Pos (10) /!< SYS IPRST1: I2C2RST Position /
sahilmgandhi	18:6a4db94011d3	24470	#define SYS_IPRST1_I2C2RST_Msk (0x1ul << SYS_IPRST1_I2C2RST_Pos) /!< SYS IPRST1: I2C2RST Mask /
sahilmgandhi	18:6a4db94011d3	24471
sahilmgandhi	18:6a4db94011d3	24472	#define SYS_IPRST1_I2C3RST_Pos (11) /!< SYS IPRST1: I2C3RST Position /
sahilmgandhi	18:6a4db94011d3	24473	#define SYS_IPRST1_I2C3RST_Msk (0x1ul << SYS_IPRST1_I2C3RST_Pos) /!< SYS IPRST1: I2C3RST Mask /
sahilmgandhi	18:6a4db94011d3	24474
sahilmgandhi	18:6a4db94011d3	24475	#define SYS_IPRST1_SPI0RST_Pos (12) /!< SYS IPRST1: SPI0RST Position /
sahilmgandhi	18:6a4db94011d3	24476	#define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) /!< SYS IPRST1: SPI0RST Mask /
sahilmgandhi	18:6a4db94011d3	24477
sahilmgandhi	18:6a4db94011d3	24478	#define SYS_IPRST1_SPI1RST_Pos (13) /!< SYS IPRST1: SPI1RST Position /
sahilmgandhi	18:6a4db94011d3	24479	#define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) /!< SYS IPRST1: SPI1RST Mask /
sahilmgandhi	18:6a4db94011d3	24480
sahilmgandhi	18:6a4db94011d3	24481	#define SYS_IPRST1_SPI2RST_Pos (14) /!< SYS IPRST1: SPI2RST Position /
sahilmgandhi	18:6a4db94011d3	24482	#define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) /!< SYS IPRST1: SPI2RST Mask /
sahilmgandhi	18:6a4db94011d3	24483
sahilmgandhi	18:6a4db94011d3	24484	#define SYS_IPRST1_SPI3RST_Pos (15) /!< SYS IPRST1: SPI3RST Position /
sahilmgandhi	18:6a4db94011d3	24485	#define SYS_IPRST1_SPI3RST_Msk (0x1ul << SYS_IPRST1_SPI3RST_Pos) /!< SYS IPRST1: SPI3RST Mask /
sahilmgandhi	18:6a4db94011d3	24486
sahilmgandhi	18:6a4db94011d3	24487	#define SYS_IPRST1_UART0RST_Pos (16) /!< SYS IPRST1: UART0RST Position /
sahilmgandhi	18:6a4db94011d3	24488	#define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) /!< SYS IPRST1: UART0RST Mask /
sahilmgandhi	18:6a4db94011d3	24489
sahilmgandhi	18:6a4db94011d3	24490	#define SYS_IPRST1_UART1RST_Pos (17) /!< SYS IPRST1: UART1RST Position /
sahilmgandhi	18:6a4db94011d3	24491	#define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) /!< SYS IPRST1: UART1RST Mask /
sahilmgandhi	18:6a4db94011d3	24492
sahilmgandhi	18:6a4db94011d3	24493	#define SYS_IPRST1_UART2RST_Pos (18) /!< SYS IPRST1: UART2RST Position /
sahilmgandhi	18:6a4db94011d3	24494	#define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) /!< SYS IPRST1: UART2RST Mask /
sahilmgandhi	18:6a4db94011d3	24495
sahilmgandhi	18:6a4db94011d3	24496	#define SYS_IPRST1_UART3RST_Pos (19) /!< SYS IPRST1: UART3RST Position /
sahilmgandhi	18:6a4db94011d3	24497	#define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) /!< SYS IPRST1: UART3RST Mask /
sahilmgandhi	18:6a4db94011d3	24498
sahilmgandhi	18:6a4db94011d3	24499	#define SYS_IPRST1_UART4RST_Pos (20) /!< SYS IPRST1: UART4RST Position /
sahilmgandhi	18:6a4db94011d3	24500	#define SYS_IPRST1_UART4RST_Msk (0x1ul << SYS_IPRST1_UART4RST_Pos) /!< SYS IPRST1: UART4RST Mask /
sahilmgandhi	18:6a4db94011d3	24501
sahilmgandhi	18:6a4db94011d3	24502	#define SYS_IPRST1_UART5RST_Pos (21) /!< SYS IPRST1: UART5RST Position /
sahilmgandhi	18:6a4db94011d3	24503	#define SYS_IPRST1_UART5RST_Msk (0x1ul << SYS_IPRST1_UART5RST_Pos) /!< SYS IPRST1: UART5RST Mask /
sahilmgandhi	18:6a4db94011d3	24504
sahilmgandhi	18:6a4db94011d3	24505	#define SYS_IPRST1_CAN0RST_Pos (24) /!< SYS IPRST1: CAN0RST Position /
sahilmgandhi	18:6a4db94011d3	24506	#define SYS_IPRST1_CAN0RST_Msk (0x1ul << SYS_IPRST1_CAN0RST_Pos) /!< SYS IPRST1: CAN0RST Mask /
sahilmgandhi	18:6a4db94011d3	24507
sahilmgandhi	18:6a4db94011d3	24508	#define SYS_IPRST1_CAN1RST_Pos (25) /!< SYS IPRST1: CAN1RST Position /
sahilmgandhi	18:6a4db94011d3	24509	#define SYS_IPRST1_CAN1RST_Msk (0x1ul << SYS_IPRST1_CAN1RST_Pos) /!< SYS IPRST1: CAN1RST Mask /
sahilmgandhi	18:6a4db94011d3	24510
sahilmgandhi	18:6a4db94011d3	24511	#define SYS_IPRST1_USBDRST_Pos (27) /!< SYS IPRST1: USBDRST Position /
sahilmgandhi	18:6a4db94011d3	24512	#define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) /!< SYS IPRST1: USBDRST Mask /
sahilmgandhi	18:6a4db94011d3	24513
sahilmgandhi	18:6a4db94011d3	24514	#define SYS_IPRST1_ADCRST_Pos (28) /!< SYS IPRST1: ADCRST Position /
sahilmgandhi	18:6a4db94011d3	24515	#define SYS_IPRST1_ADCRST_Msk (0x1ul << SYS_IPRST1_ADCRST_Pos) /!< SYS IPRST1: ADCRST Mask /
sahilmgandhi	18:6a4db94011d3	24516
sahilmgandhi	18:6a4db94011d3	24517	#define SYS_IPRST1_I2S0RST_Pos (29) /!< SYS IPRST1: I2SRST Position /
sahilmgandhi	18:6a4db94011d3	24518	#define SYS_IPRST1_I2S0RST_Msk (0x1ul << SYS_IPRST1_I2S0RST_Pos) /!< SYS IPRST1: I2SRST Mask /
sahilmgandhi	18:6a4db94011d3	24519
sahilmgandhi	18:6a4db94011d3	24520	#define SYS_IPRST1_I2S1RST_Pos (30) /!< SYS IPRST1: I2S1RST Position /
sahilmgandhi	18:6a4db94011d3	24521	#define SYS_IPRST1_I2S1RST_Msk (0x1ul << SYS_IPRST1_I2S1RST_Pos) /!< SYS IPRST1: I2S1RST Mask /
sahilmgandhi	18:6a4db94011d3	24522
sahilmgandhi	18:6a4db94011d3	24523	#define SYS_IPRST1_PS2RST_Pos (31) /!< SYS IPRST1: PS2RST Position /
sahilmgandhi	18:6a4db94011d3	24524	#define SYS_IPRST1_PS2RST_Msk (0x1ul << SYS_IPRST1_PS2RST_Pos) /!< SYS IPRST1: PS2RST Mask /
sahilmgandhi	18:6a4db94011d3	24525
sahilmgandhi	18:6a4db94011d3	24526	#define SYS_IPRST2_SC0RST_Pos (0) /!< SYS IPRST2: SC0RST Position /
sahilmgandhi	18:6a4db94011d3	24527	#define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) /!< SYS IPRST2: SC0RST Mask /
sahilmgandhi	18:6a4db94011d3	24528
sahilmgandhi	18:6a4db94011d3	24529	#define SYS_IPRST2_SC1RST_Pos (1) /!< SYS IPRST2: SC1RST Position /
sahilmgandhi	18:6a4db94011d3	24530	#define SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos) /!< SYS IPRST2: SC1RST Mask /
sahilmgandhi	18:6a4db94011d3	24531
sahilmgandhi	18:6a4db94011d3	24532	#define SYS_IPRST2_SC2RST_Pos (2) /!< SYS IPRST2: SC2RST Position /
sahilmgandhi	18:6a4db94011d3	24533	#define SYS_IPRST2_SC2RST_Msk (0x1ul << SYS_IPRST2_SC2RST_Pos) /!< SYS IPRST2: SC2RST Mask /
sahilmgandhi	18:6a4db94011d3	24534
sahilmgandhi	18:6a4db94011d3	24535	#define SYS_IPRST2_SC3RST_Pos (3) /!< SYS IPRST2: SC3RST Position /
sahilmgandhi	18:6a4db94011d3	24536	#define SYS_IPRST2_SC3RST_Msk (0x1ul << SYS_IPRST2_SC3RST_Pos) /!< SYS IPRST2: SC3RST Mask /
sahilmgandhi	18:6a4db94011d3	24537
sahilmgandhi	18:6a4db94011d3	24538	#define SYS_IPRST2_SC4RST_Pos (4) /!< SYS IPRST2: SC4RST Position /
sahilmgandhi	18:6a4db94011d3	24539	#define SYS_IPRST2_SC4RST_Msk (0x1ul << SYS_IPRST2_SC4RST_Pos) /!< SYS IPRST2: SC4RST Mask /
sahilmgandhi	18:6a4db94011d3	24540
sahilmgandhi	18:6a4db94011d3	24541	#define SYS_IPRST2_SC5RST_Pos (5) /!< SYS IPRST2: SC5RST Position /
sahilmgandhi	18:6a4db94011d3	24542	#define SYS_IPRST2_SC5RST_Msk (0x1ul << SYS_IPRST2_SC5RST_Pos) /!< SYS IPRST2: SC5RST Mask /
sahilmgandhi	18:6a4db94011d3	24543
sahilmgandhi	18:6a4db94011d3	24544	#define SYS_IPRST2_I2C4RST_Pos (8) /!< SYS IPRST2: I2C4RST Position /
sahilmgandhi	18:6a4db94011d3	24545	#define SYS_IPRST2_I2C4RST_Msk (0x1ul << SYS_IPRST2_I2C4RST_Pos) /!< SYS IPRST2: I2C4RST Mask /
sahilmgandhi	18:6a4db94011d3	24546
sahilmgandhi	18:6a4db94011d3	24547	#define SYS_IPRST2_PWM0RST_Pos (16) /!< SYS IPRST2: PWM0RST Position /
sahilmgandhi	18:6a4db94011d3	24548	#define SYS_IPRST2_PWM0RST_Msk (0x1ul << SYS_IPRST2_PWM0RST_Pos) /!< SYS IPRST2: PWM0RST Mask /
sahilmgandhi	18:6a4db94011d3	24549
sahilmgandhi	18:6a4db94011d3	24550	#define SYS_IPRST2_PWM1RST_Pos (17) /!< SYS IPRST2: PWM1RST Position /
sahilmgandhi	18:6a4db94011d3	24551	#define SYS_IPRST2_PWM1RST_Msk (0x1ul << SYS_IPRST2_PWM1RST_Pos) /!< SYS IPRST2: PWM1RST Mask /
sahilmgandhi	18:6a4db94011d3	24552
sahilmgandhi	18:6a4db94011d3	24553	#define SYS_IPRST2_QEI0RST_Pos (22) /!< SYS IPRST2: QEI0RST Position /
sahilmgandhi	18:6a4db94011d3	24554	#define SYS_IPRST2_QEI0RST_Msk (0x1ul << SYS_IPRST2_QEI0RST_Pos) /!< SYS IPRST2: QEI0RST Mask /
sahilmgandhi	18:6a4db94011d3	24555
sahilmgandhi	18:6a4db94011d3	24556	#define SYS_IPRST2_QEI1RST_Pos (23) /!< SYS IPRST2: QEI1RST Position /
sahilmgandhi	18:6a4db94011d3	24557	#define SYS_IPRST2_QEI1RST_Msk (0x1ul << SYS_IPRST2_QEI1RST_Pos) /!< SYS IPRST2: QEI1RST Mask /
sahilmgandhi	18:6a4db94011d3	24558
sahilmgandhi	18:6a4db94011d3	24559	#define SYS_BODCTL_BODEN_Pos (0) /!< SYS BODCTL: BODEN Position /
sahilmgandhi	18:6a4db94011d3	24560	#define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) /!< SYS BODCTL: BODEN Mask /
sahilmgandhi	18:6a4db94011d3	24561
sahilmgandhi	18:6a4db94011d3	24562	#define SYS_BODCTL_BODVL_Pos (1) /!< SYS BODCTL: BODVL Position /
sahilmgandhi	18:6a4db94011d3	24563	#define SYS_BODCTL_BODVL_Msk (0x3ul << SYS_BODCTL_BODVL_Pos) /!< SYS BODCTL: BODVL Mask /
sahilmgandhi	18:6a4db94011d3	24564
sahilmgandhi	18:6a4db94011d3	24565	#define SYS_BODCTL_BODRSTEN_Pos (3) /!< SYS BODCTL: BODRSTEN Position /
sahilmgandhi	18:6a4db94011d3	24566	#define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) /!< SYS BODCTL: BODRSTEN Mask /
sahilmgandhi	18:6a4db94011d3	24567
sahilmgandhi	18:6a4db94011d3	24568	#define SYS_BODCTL_BODINTF_Pos (4) /!< SYS BODCTL: BODINTF Position /
sahilmgandhi	18:6a4db94011d3	24569	#define SYS_BODCTL_BODINTF_Msk (0x1ul << SYS_BODCTL_BODINTF_Pos) /!< SYS BODCTL: BODINTF Mask /
sahilmgandhi	18:6a4db94011d3	24570
sahilmgandhi	18:6a4db94011d3	24571	#define SYS_BODCTL_BODLPM_Pos (5) /!< SYS BODCTL: BODLPM Position /
sahilmgandhi	18:6a4db94011d3	24572	#define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos) /!< SYS BODCTL: BODLPM Mask /
sahilmgandhi	18:6a4db94011d3	24573
sahilmgandhi	18:6a4db94011d3	24574	#define SYS_BODCTL_BODOUT_Pos (6) /!< SYS BODCTL: BODOUT Position /
sahilmgandhi	18:6a4db94011d3	24575	#define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) /!< SYS BODCTL: BODOUT Mask /
sahilmgandhi	18:6a4db94011d3	24576
sahilmgandhi	18:6a4db94011d3	24577	#define SYS_BODCTL_LVREN_Pos (7) /!< SYS BODCTL: LVREN Position /
sahilmgandhi	18:6a4db94011d3	24578	#define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) /!< SYS BODCTL: LVREN Mask /
sahilmgandhi	18:6a4db94011d3	24579
sahilmgandhi	18:6a4db94011d3	24580	#define SYS_TEMPCTL_VTEMPEN_Pos (0) /!< SYS TEMPCTL: VTEMPEN Position /
sahilmgandhi	18:6a4db94011d3	24581	#define SYS_TEMPCTL_VTEMPEN_Msk (0x1ul << SYS_TEMPCTL_VTEMPEN_Pos) /!< SYS TEMPCTL: VTEMPEN Mask /
sahilmgandhi	18:6a4db94011d3	24582
sahilmgandhi	18:6a4db94011d3	24583	#define SYS_VCID_VCID_Pos (0) /!< SYS VCID: VCID Position /
sahilmgandhi	18:6a4db94011d3	24584	#define SYS_VCID_VCID_Msk (0xfffful << SYS_VCID_VCID_Pos) /!< SYS VCID: VCID Mask /
sahilmgandhi	18:6a4db94011d3	24585
sahilmgandhi	18:6a4db94011d3	24586	#define SYS_PORCTL_POROFF_Pos (0) /!< SYS PORCTL: POROFF Position /
sahilmgandhi	18:6a4db94011d3	24587	#define SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos) /!< SYS PORCTL: POROFF Mask /
sahilmgandhi	18:6a4db94011d3	24588
sahilmgandhi	18:6a4db94011d3	24589	#define SYS_VREFCTL_VREFCTL_Pos (0) /!< SYS VREFCTL: VREFCTL Position /
sahilmgandhi	18:6a4db94011d3	24590	#define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) /!< SYS VREFCTL: VREFCTL Mask /
sahilmgandhi	18:6a4db94011d3	24591
sahilmgandhi	18:6a4db94011d3	24592	#define SYS_VREFCTL_ADCMODESEL_Pos (8) /!< SYS VREFCTL: ADCMODESEL Position /
sahilmgandhi	18:6a4db94011d3	24593	#define SYS_VREFCTL_ADCMODESEL_Msk (0x1ul << SYS_VREFCTL_ADCMODESEL_Pos) /!< SYS VREFCTL: ADCMODESEL Mask /
sahilmgandhi	18:6a4db94011d3	24594
sahilmgandhi	18:6a4db94011d3	24595	#define SYS_VREFCTL_PWMSYNCMODE_Pos (9) /!< SYS VREFCTL: PWMSYNCMODE Position /
sahilmgandhi	18:6a4db94011d3	24596	#define SYS_VREFCTL_PWMSYNCMODE_Msk (0x1ul << SYS_VREFCTL_PWMSYNCMODE_Pos) /!< SYS VREFCTL: PWMSYNCMODE Mask /
sahilmgandhi	18:6a4db94011d3	24597
sahilmgandhi	18:6a4db94011d3	24598	#define SYS_USBPHY_USBROLE_Pos (0) /!< SYS USBPHY: USBROLE Position /
sahilmgandhi	18:6a4db94011d3	24599	#define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) /!< SYS USBPHY: USBROLE Mask /
sahilmgandhi	18:6a4db94011d3	24600
sahilmgandhi	18:6a4db94011d3	24601	#define SYS_USBPHY_LDO33EN_Pos (8) /!< SYS USBPHY: LDO33EN Position /
sahilmgandhi	18:6a4db94011d3	24602	#define SYS_USBPHY_LDO33EN_Msk (0x1ul << SYS_USBPHY_LDO33EN_Pos) /!< SYS USBPHY: LDO33EN Mask /
sahilmgandhi	18:6a4db94011d3	24603
sahilmgandhi	18:6a4db94011d3	24604	#define SYS_GPA_MFPL_PA0MFP_Pos (0) /!< SYS GPA_MFPL: PA0MFP Position /
sahilmgandhi	18:6a4db94011d3	24605	#define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) /!< SYS GPA_MFPL: PA0MFP Mask /
sahilmgandhi	18:6a4db94011d3	24606
sahilmgandhi	18:6a4db94011d3	24607	#define SYS_GPA_MFPL_PA1MFP_Pos (4) /!< SYS GPA_MFPL: PA1MFP Position /
sahilmgandhi	18:6a4db94011d3	24608	#define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) /!< SYS GPA_MFPL: PA1MFP Mask /
sahilmgandhi	18:6a4db94011d3	24609
sahilmgandhi	18:6a4db94011d3	24610	#define SYS_GPA_MFPL_PA2MFP_Pos (8) /!< SYS GPA_MFPL: PA2MFP Position /
sahilmgandhi	18:6a4db94011d3	24611	#define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) /!< SYS GPA_MFPL: PA2MFP Mask /
sahilmgandhi	18:6a4db94011d3	24612
sahilmgandhi	18:6a4db94011d3	24613	#define SYS_GPA_MFPL_PA3MFP_Pos (12) /!< SYS GPA_MFPL: PA3MFP Position /
sahilmgandhi	18:6a4db94011d3	24614	#define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) /!< SYS GPA_MFPL: PA3MFP Mask /
sahilmgandhi	18:6a4db94011d3	24615
sahilmgandhi	18:6a4db94011d3	24616	#define SYS_GPA_MFPL_PA4MFP_Pos (16) /!< SYS GPA_MFPL: PA4MFP Position /
sahilmgandhi	18:6a4db94011d3	24617	#define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) /!< SYS GPA_MFPL: PA4MFP Mask /
sahilmgandhi	18:6a4db94011d3	24618
sahilmgandhi	18:6a4db94011d3	24619	#define SYS_GPA_MFPL_PA5MFP_Pos (20) /!< SYS GPA_MFPL: PA5MFP Position /
sahilmgandhi	18:6a4db94011d3	24620	#define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) /!< SYS GPA_MFPL: PA5MFP Mask /
sahilmgandhi	18:6a4db94011d3	24621
sahilmgandhi	18:6a4db94011d3	24622	#define SYS_GPA_MFPL_PA6MFP_Pos (24) /!< SYS GPA_MFPL: PA6MFP Position /
sahilmgandhi	18:6a4db94011d3	24623	#define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) /!< SYS GPA_MFPL: PA6MFP Mask /
sahilmgandhi	18:6a4db94011d3	24624
sahilmgandhi	18:6a4db94011d3	24625	#define SYS_GPA_MFPL_PA7MFP_Pos (28) /!< SYS GPA_MFPL: PA7MFP Position /
sahilmgandhi	18:6a4db94011d3	24626	#define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos) /!< SYS GPA_MFPL: PA7MFP Mask /
sahilmgandhi	18:6a4db94011d3	24627
sahilmgandhi	18:6a4db94011d3	24628	#define SYS_GPA_MFPH_PA8MFP_Pos (0) /!< SYS GPA_MFPH: PA8MFP Position /
sahilmgandhi	18:6a4db94011d3	24629	#define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) /!< SYS GPA_MFPH: PA8MFP Mask /
sahilmgandhi	18:6a4db94011d3	24630
sahilmgandhi	18:6a4db94011d3	24631	#define SYS_GPA_MFPH_PA9MFP_Pos (4) /!< SYS GPA_MFPH: PA9MFP Position /
sahilmgandhi	18:6a4db94011d3	24632	#define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) /!< SYS GPA_MFPH: PA9MFP Mask /
sahilmgandhi	18:6a4db94011d3	24633
sahilmgandhi	18:6a4db94011d3	24634	#define SYS_GPA_MFPH_PA10MFP_Pos (8) /!< SYS GPA_MFPH: PA10MFP Position /
sahilmgandhi	18:6a4db94011d3	24635	#define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) /!< SYS GPA_MFPH: PA10MFP Mask /
sahilmgandhi	18:6a4db94011d3	24636
sahilmgandhi	18:6a4db94011d3	24637	#define SYS_GPA_MFPH_PA11MFP_Pos (12) /!< SYS GPA_MFPH: PA11MFP Position /
sahilmgandhi	18:6a4db94011d3	24638	#define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) /!< SYS GPA_MFPH: PA11MFP Mask /
sahilmgandhi	18:6a4db94011d3	24639
sahilmgandhi	18:6a4db94011d3	24640	#define SYS_GPA_MFPH_PA12MFP_Pos (16) /!< SYS GPA_MFPH: PA12MFP Position /
sahilmgandhi	18:6a4db94011d3	24641	#define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) /!< SYS GPA_MFPH: PA12MFP Mask /
sahilmgandhi	18:6a4db94011d3	24642
sahilmgandhi	18:6a4db94011d3	24643	#define SYS_GPA_MFPH_PA13MFP_Pos (20) /!< SYS GPA_MFPH: PA13MFP Position /
sahilmgandhi	18:6a4db94011d3	24644	#define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) /!< SYS GPA_MFPH: PA13MFP Mask /
sahilmgandhi	18:6a4db94011d3	24645
sahilmgandhi	18:6a4db94011d3	24646	#define SYS_GPA_MFPH_PA14MFP_Pos (24) /!< SYS GPA_MFPH: PA14MFP Position /
sahilmgandhi	18:6a4db94011d3	24647	#define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) /!< SYS GPA_MFPH: PA14MFP Mask /
sahilmgandhi	18:6a4db94011d3	24648
sahilmgandhi	18:6a4db94011d3	24649	#define SYS_GPA_MFPH_PA15MFP_Pos (28) /!< SYS GPA_MFPH: PA15MFP Position /
sahilmgandhi	18:6a4db94011d3	24650	#define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) /!< SYS GPA_MFPH: PA15MFP Mask /
sahilmgandhi	18:6a4db94011d3	24651
sahilmgandhi	18:6a4db94011d3	24652	#define SYS_GPB_MFPL_PB0MFP_Pos (0) /!< SYS GPB_MFPL: PB0MFP Position /
sahilmgandhi	18:6a4db94011d3	24653	#define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) /!< SYS GPB_MFPL: PB0MFP Mask /
sahilmgandhi	18:6a4db94011d3	24654
sahilmgandhi	18:6a4db94011d3	24655	#define SYS_GPB_MFPL_PB1MFP_Pos (4) /!< SYS GPB_MFPL: PB1MFP Position /
sahilmgandhi	18:6a4db94011d3	24656	#define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) /!< SYS GPB_MFPL: PB1MFP Mask /
sahilmgandhi	18:6a4db94011d3	24657
sahilmgandhi	18:6a4db94011d3	24658	#define SYS_GPB_MFPL_PB2MFP_Pos (8) /!< SYS GPB_MFPL: PB2MFP Position /
sahilmgandhi	18:6a4db94011d3	24659	#define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) /!< SYS GPB_MFPL: PB2MFP Mask /
sahilmgandhi	18:6a4db94011d3	24660
sahilmgandhi	18:6a4db94011d3	24661	#define SYS_GPB_MFPL_PB3MFP_Pos (12) /!< SYS GPB_MFPL: PB3MFP Position /
sahilmgandhi	18:6a4db94011d3	24662	#define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) /!< SYS GPB_MFPL: PB3MFP Mask /
sahilmgandhi	18:6a4db94011d3	24663
sahilmgandhi	18:6a4db94011d3	24664	#define SYS_GPB_MFPL_PB4MFP_Pos (16) /!< SYS GPB_MFPL: PB4MFP Position /
sahilmgandhi	18:6a4db94011d3	24665	#define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) /!< SYS GPB_MFPL: PB4MFP Mask /
sahilmgandhi	18:6a4db94011d3	24666
sahilmgandhi	18:6a4db94011d3	24667	#define SYS_GPB_MFPL_PB5MFP_Pos (20) /!< SYS GPB_MFPL: PB5MFP Position /
sahilmgandhi	18:6a4db94011d3	24668	#define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) /!< SYS GPB_MFPL: PB5MFP Mask /
sahilmgandhi	18:6a4db94011d3	24669
sahilmgandhi	18:6a4db94011d3	24670	#define SYS_GPB_MFPL_PB6MFP_Pos (24) /!< SYS GPB_MFPL: PB6MFP Position /
sahilmgandhi	18:6a4db94011d3	24671	#define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) /!< SYS GPB_MFPL: PB6MFP Mask /
sahilmgandhi	18:6a4db94011d3	24672
sahilmgandhi	18:6a4db94011d3	24673	#define SYS_GPB_MFPL_PB7MFP_Pos (28) /!< SYS GPB_MFPL: PB7MFP Position /
sahilmgandhi	18:6a4db94011d3	24674	#define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) /!< SYS GPB_MFPL: PB7MFP Mask /
sahilmgandhi	18:6a4db94011d3	24675
sahilmgandhi	18:6a4db94011d3	24676	#define SYS_GPB_MFPH_PB8MFP_Pos (0) /!< SYS GPB_MFPH: PB8MFP Position /
sahilmgandhi	18:6a4db94011d3	24677	#define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) /!< SYS GPB_MFPH: PB8MFP Mask /
sahilmgandhi	18:6a4db94011d3	24678
sahilmgandhi	18:6a4db94011d3	24679	#define SYS_GPB_MFPH_PB9MFP_Pos (4) /!< SYS GPB_MFPH: PB9MFP Position /
sahilmgandhi	18:6a4db94011d3	24680	#define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) /!< SYS GPB_MFPH: PB9MFP Mask /
sahilmgandhi	18:6a4db94011d3	24681
sahilmgandhi	18:6a4db94011d3	24682	#define SYS_GPB_MFPH_PB10MFP_Pos (8) /!< SYS GPB_MFPH: PB10MFP Position /
sahilmgandhi	18:6a4db94011d3	24683	#define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) /!< SYS GPB_MFPH: PB10MFP Mask /
sahilmgandhi	18:6a4db94011d3	24684
sahilmgandhi	18:6a4db94011d3	24685	#define SYS_GPB_MFPH_PB11MFP_Pos (12) /!< SYS GPB_MFPH: PB11MFP Position /
sahilmgandhi	18:6a4db94011d3	24686	#define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) /!< SYS GPB_MFPH: PB11MFP Mask /
sahilmgandhi	18:6a4db94011d3	24687
sahilmgandhi	18:6a4db94011d3	24688	#define SYS_GPB_MFPH_PB12MFP_Pos (16) /!< SYS GPB_MFPH: PB12MFP Position /
sahilmgandhi	18:6a4db94011d3	24689	#define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos) /!< SYS GPB_MFPH: PB12MFP Mask /
sahilmgandhi	18:6a4db94011d3	24690
sahilmgandhi	18:6a4db94011d3	24691	#define SYS_GPB_MFPH_PB13MFP_Pos (20) /!< SYS GPB_MFPH: PB13MFP Position /
sahilmgandhi	18:6a4db94011d3	24692	#define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) /!< SYS GPB_MFPH: PB13MFP Mask /
sahilmgandhi	18:6a4db94011d3	24693
sahilmgandhi	18:6a4db94011d3	24694	#define SYS_GPB_MFPH_PB14MFP_Pos (24) /!< SYS GPB_MFPH: PB14MFP Position /
sahilmgandhi	18:6a4db94011d3	24695	#define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) /!< SYS GPB_MFPH: PB14MFP Mask /
sahilmgandhi	18:6a4db94011d3	24696
sahilmgandhi	18:6a4db94011d3	24697	#define SYS_GPB_MFPH_PB15MFP_Pos (28) /!< SYS GPB_MFPH: PB15MFP Position /
sahilmgandhi	18:6a4db94011d3	24698	#define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) /!< SYS GPB_MFPH: PB15MFP Mask /
sahilmgandhi	18:6a4db94011d3	24699
sahilmgandhi	18:6a4db94011d3	24700	#define SYS_GPC_MFPL_PC0MFP_Pos (0) /!< SYS GPC_MFPL: PC0MFP Position /
sahilmgandhi	18:6a4db94011d3	24701	#define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) /!< SYS GPC_MFPL: PC0MFP Mask /
sahilmgandhi	18:6a4db94011d3	24702
sahilmgandhi	18:6a4db94011d3	24703	#define SYS_GPC_MFPL_PC1MFP_Pos (4) /!< SYS GPC_MFPL: PC1MFP Position /
sahilmgandhi	18:6a4db94011d3	24704	#define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) /!< SYS GPC_MFPL: PC1MFP Mask /
sahilmgandhi	18:6a4db94011d3	24705
sahilmgandhi	18:6a4db94011d3	24706	#define SYS_GPC_MFPL_PC2MFP_Pos (8) /!< SYS GPC_MFPL: PC2MFP Position /
sahilmgandhi	18:6a4db94011d3	24707	#define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) /!< SYS GPC_MFPL: PC2MFP Mask /
sahilmgandhi	18:6a4db94011d3	24708
sahilmgandhi	18:6a4db94011d3	24709	#define SYS_GPC_MFPL_PC3MFP_Pos (12) /!< SYS GPC_MFPL: PC3MFP Position /
sahilmgandhi	18:6a4db94011d3	24710	#define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) /!< SYS GPC_MFPL: PC3MFP Mask /
sahilmgandhi	18:6a4db94011d3	24711
sahilmgandhi	18:6a4db94011d3	24712	#define SYS_GPC_MFPL_PC4MFP_Pos (16) /!< SYS GPC_MFPL: PC4MFP Position /
sahilmgandhi	18:6a4db94011d3	24713	#define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos) /!< SYS GPC_MFPL: PC4MFP Mask /
sahilmgandhi	18:6a4db94011d3	24714
sahilmgandhi	18:6a4db94011d3	24715	#define SYS_GPC_MFPL_PC5MFP_Pos (20) /!< SYS GPC_MFPL: PC5MFP Position /
sahilmgandhi	18:6a4db94011d3	24716	#define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos) /!< SYS GPC_MFPL: PC5MFP Mask /
sahilmgandhi	18:6a4db94011d3	24717
sahilmgandhi	18:6a4db94011d3	24718	#define SYS_GPC_MFPL_PC6MFP_Pos (24) /!< SYS GPC_MFPL: PC6MFP Position /
sahilmgandhi	18:6a4db94011d3	24719	#define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) /!< SYS GPC_MFPL: PC6MFP Mask /
sahilmgandhi	18:6a4db94011d3	24720
sahilmgandhi	18:6a4db94011d3	24721	#define SYS_GPC_MFPL_PC7MFP_Pos (28) /!< SYS GPC_MFPL: PC7MFP Position /
sahilmgandhi	18:6a4db94011d3	24722	#define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) /!< SYS GPC_MFPL: PC7MFP Mask /
sahilmgandhi	18:6a4db94011d3	24723
sahilmgandhi	18:6a4db94011d3	24724	#define SYS_GPC_MFPH_PC8MFP_Pos (0) /!< SYS GPC_MFPH: PC8MFP Position /
sahilmgandhi	18:6a4db94011d3	24725	#define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) /!< SYS GPC_MFPH: PC8MFP Mask /
sahilmgandhi	18:6a4db94011d3	24726
sahilmgandhi	18:6a4db94011d3	24727	#define SYS_GPC_MFPH_PC9MFP_Pos (4) /!< SYS GPC_MFPH: PC9MFP Position /
sahilmgandhi	18:6a4db94011d3	24728	#define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) /!< SYS GPC_MFPH: PC9MFP Mask /
sahilmgandhi	18:6a4db94011d3	24729
sahilmgandhi	18:6a4db94011d3	24730	#define SYS_GPC_MFPH_PC10MFP_Pos (8) /!< SYS GPC_MFPH: PC10MFP Position /
sahilmgandhi	18:6a4db94011d3	24731	#define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) /!< SYS GPC_MFPH: PC10MFP Mask /
sahilmgandhi	18:6a4db94011d3	24732
sahilmgandhi	18:6a4db94011d3	24733	#define SYS_GPC_MFPH_PC11MFP_Pos (12) /!< SYS GPC_MFPH: PC11MFP Position /
sahilmgandhi	18:6a4db94011d3	24734	#define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) /!< SYS GPC_MFPH: PC11MFP Mask /
sahilmgandhi	18:6a4db94011d3	24735
sahilmgandhi	18:6a4db94011d3	24736	#define SYS_GPC_MFPH_PC12MFP_Pos (16) /!< SYS GPC_MFPH: PC12MFP Position /
sahilmgandhi	18:6a4db94011d3	24737	#define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos) /!< SYS GPC_MFPH: PC12MFP Mask /
sahilmgandhi	18:6a4db94011d3	24738
sahilmgandhi	18:6a4db94011d3	24739	#define SYS_GPC_MFPH_PC13MFP_Pos (20) /!< SYS GPC_MFPH: PC13MFP Position /
sahilmgandhi	18:6a4db94011d3	24740	#define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos) /!< SYS GPC_MFPH: PC13MFP Mask /
sahilmgandhi	18:6a4db94011d3	24741
sahilmgandhi	18:6a4db94011d3	24742	#define SYS_GPC_MFPH_PC14MFP_Pos (24) /!< SYS GPC_MFPH: PC14MFP Position /
sahilmgandhi	18:6a4db94011d3	24743	#define SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos) /!< SYS GPC_MFPH: PC14MFP Mask /
sahilmgandhi	18:6a4db94011d3	24744
sahilmgandhi	18:6a4db94011d3	24745	#define SYS_GPC_MFPH_PC15MFP_Pos (28) /!< SYS GPC_MFPH: PC15MFP Position /
sahilmgandhi	18:6a4db94011d3	24746	#define SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos) /!< SYS GPC_MFPH: PC15MFP Mask /
sahilmgandhi	18:6a4db94011d3	24747
sahilmgandhi	18:6a4db94011d3	24748	#define SYS_GPD_MFPL_PD0MFP_Pos (0) /!< SYS GPD_MFPL: PD0MFP Position /
sahilmgandhi	18:6a4db94011d3	24749	#define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos) /!< SYS GPD_MFPL: PD0MFP Mask /
sahilmgandhi	18:6a4db94011d3	24750
sahilmgandhi	18:6a4db94011d3	24751	#define SYS_GPD_MFPL_PD1MFP_Pos (4) /!< SYS GPD_MFPL: PD1MFP Position /
sahilmgandhi	18:6a4db94011d3	24752	#define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos) /!< SYS GPD_MFPL: PD1MFP Mask /
sahilmgandhi	18:6a4db94011d3	24753
sahilmgandhi	18:6a4db94011d3	24754	#define SYS_GPD_MFPL_PD2MFP_Pos (8) /!< SYS GPD_MFPL: PD2MFP Position /
sahilmgandhi	18:6a4db94011d3	24755	#define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos) /!< SYS GPD_MFPL: PD2MFP Mask /
sahilmgandhi	18:6a4db94011d3	24756
sahilmgandhi	18:6a4db94011d3	24757	#define SYS_GPD_MFPL_PD3MFP_Pos (12) /!< SYS GPD_MFPL: PD3MFP Position /
sahilmgandhi	18:6a4db94011d3	24758	#define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos) /!< SYS GPD_MFPL: PD3MFP Mask /
sahilmgandhi	18:6a4db94011d3	24759
sahilmgandhi	18:6a4db94011d3	24760	#define SYS_GPD_MFPL_PD4MFP_Pos (16) /!< SYS GPD_MFPL: PD4MFP Position /
sahilmgandhi	18:6a4db94011d3	24761	#define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos) /!< SYS GPD_MFPL: PD4MFP Mask /
sahilmgandhi	18:6a4db94011d3	24762
sahilmgandhi	18:6a4db94011d3	24763	#define SYS_GPD_MFPL_PD5MFP_Pos (20) /!< SYS GPD_MFPL: PD5MFP Position /
sahilmgandhi	18:6a4db94011d3	24764	#define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos) /!< SYS GPD_MFPL: PD5MFP Mask /
sahilmgandhi	18:6a4db94011d3	24765
sahilmgandhi	18:6a4db94011d3	24766	#define SYS_GPD_MFPL_PD6MFP_Pos (24) /!< SYS GPD_MFPL: PD6MFP Position /
sahilmgandhi	18:6a4db94011d3	24767	#define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) /!< SYS GPD_MFPL: PD6MFP Mask /
sahilmgandhi	18:6a4db94011d3	24768
sahilmgandhi	18:6a4db94011d3	24769	#define SYS_GPD_MFPL_PD7MFP_Pos (28) /!< SYS GPD_MFPL: PD7MFP Position /
sahilmgandhi	18:6a4db94011d3	24770	#define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) /!< SYS GPD_MFPL: PD7MFP Mask /
sahilmgandhi	18:6a4db94011d3	24771
sahilmgandhi	18:6a4db94011d3	24772	#define SYS_GPD_MFPH_PD8MFP_Pos (0) /!< SYS GPD_MFPH: PD8MFP Position /
sahilmgandhi	18:6a4db94011d3	24773	#define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos) /!< SYS GPD_MFPH: PD8MFP Mask /
sahilmgandhi	18:6a4db94011d3	24774
sahilmgandhi	18:6a4db94011d3	24775	#define SYS_GPD_MFPH_PD9MFP_Pos (4) /!< SYS GPD_MFPH: PD9MFP Position /
sahilmgandhi	18:6a4db94011d3	24776	#define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos) /!< SYS GPD_MFPH: PD9MFP Mask /
sahilmgandhi	18:6a4db94011d3	24777
sahilmgandhi	18:6a4db94011d3	24778	#define SYS_GPD_MFPH_PD10MFP_Pos (8) /!< SYS GPD_MFPH: PD10MFP Position /
sahilmgandhi	18:6a4db94011d3	24779	#define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos) /!< SYS GPD_MFPH: PD10MFP Mask /
sahilmgandhi	18:6a4db94011d3	24780
sahilmgandhi	18:6a4db94011d3	24781	#define SYS_GPD_MFPH_PD11MFP_Pos (12) /!< SYS GPD_MFPH: PD11MFP Position /
sahilmgandhi	18:6a4db94011d3	24782	#define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos) /!< SYS GPD_MFPH: PD11MFP Mask /
sahilmgandhi	18:6a4db94011d3	24783
sahilmgandhi	18:6a4db94011d3	24784	#define SYS_GPD_MFPH_PD12MFP_Pos (16) /!< SYS GPD_MFPH: PD12MFP Position /
sahilmgandhi	18:6a4db94011d3	24785	#define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos) /!< SYS GPD_MFPH: PD12MFP Mask /
sahilmgandhi	18:6a4db94011d3	24786
sahilmgandhi	18:6a4db94011d3	24787	#define SYS_GPD_MFPH_PD13MFP_Pos (20) /!< SYS GPD_MFPH: PD13MFP Position /
sahilmgandhi	18:6a4db94011d3	24788	#define SYS_GPD_MFPH_PD13MFP_Msk (0xful << SYS_GPD_MFPH_PD13MFP_Pos) /!< SYS GPD_MFPH: PD13MFP Mask /
sahilmgandhi	18:6a4db94011d3	24789
sahilmgandhi	18:6a4db94011d3	24790	#define SYS_GPD_MFPH_PD14MFP_Pos (24) /!< SYS GPD_MFPH: PD14MFP Position /
sahilmgandhi	18:6a4db94011d3	24791	#define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) /!< SYS GPD_MFPH: PD14MFP Mask /
sahilmgandhi	18:6a4db94011d3	24792
sahilmgandhi	18:6a4db94011d3	24793	#define SYS_GPD_MFPH_PD15MFP_Pos (28) /!< SYS GPD_MFPH: PD15MFP Position /
sahilmgandhi	18:6a4db94011d3	24794	#define SYS_GPD_MFPH_PD15MFP_Msk (0xful << SYS_GPD_MFPH_PD15MFP_Pos) /!< SYS GPD_MFPH: PD15MFP Mask /
sahilmgandhi	18:6a4db94011d3	24795
sahilmgandhi	18:6a4db94011d3	24796	#define SYS_GPE_MFPL_PE0MFP_Pos (0) /!< SYS GPE_MFPL: PE0MFP Position /
sahilmgandhi	18:6a4db94011d3	24797	#define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos) /!< SYS GPE_MFPL: PE0MFP Mask /
sahilmgandhi	18:6a4db94011d3	24798
sahilmgandhi	18:6a4db94011d3	24799	#define SYS_GPE_MFPL_PE1MFP_Pos (4) /!< SYS GPE_MFPL: PE1MFP Position /
sahilmgandhi	18:6a4db94011d3	24800	#define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos) /!< SYS GPE_MFPL: PE1MFP Mask /
sahilmgandhi	18:6a4db94011d3	24801
sahilmgandhi	18:6a4db94011d3	24802	#define SYS_GPE_MFPL_PE2MFP_Pos (8) /!< SYS GPE_MFPL: PE2MFP Position /
sahilmgandhi	18:6a4db94011d3	24803	#define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos) /!< SYS GPE_MFPL: PE2MFP Mask /
sahilmgandhi	18:6a4db94011d3	24804
sahilmgandhi	18:6a4db94011d3	24805	#define SYS_GPE_MFPL_PE3MFP_Pos (12) /!< SYS GPE_MFPL: PE3MFP Position /
sahilmgandhi	18:6a4db94011d3	24806	#define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos) /!< SYS GPE_MFPL: PE3MFP Mask /
sahilmgandhi	18:6a4db94011d3	24807
sahilmgandhi	18:6a4db94011d3	24808	#define SYS_GPE_MFPL_PE4MFP_Pos (16) /!< SYS GPE_MFPL: PE4MFP Position /
sahilmgandhi	18:6a4db94011d3	24809	#define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos) /!< SYS GPE_MFPL: PE4MFP Mask /
sahilmgandhi	18:6a4db94011d3	24810
sahilmgandhi	18:6a4db94011d3	24811	#define SYS_GPE_MFPL_PE5MFP_Pos (20) /!< SYS GPE_MFPL: PE5MFP Position /
sahilmgandhi	18:6a4db94011d3	24812	#define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) /!< SYS GPE_MFPL: PE5MFP Mask /
sahilmgandhi	18:6a4db94011d3	24813
sahilmgandhi	18:6a4db94011d3	24814	#define SYS_GPE_MFPL_PE6MFP_Pos (24) /!< SYS GPE_MFPL: PE6MFP Position /
sahilmgandhi	18:6a4db94011d3	24815	#define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos) /!< SYS GPE_MFPL: PE6MFP Mask /
sahilmgandhi	18:6a4db94011d3	24816
sahilmgandhi	18:6a4db94011d3	24817	#define SYS_GPE_MFPL_PE7MFP_Pos (28) /!< SYS GPE_MFPL: PE7MFP Position /
sahilmgandhi	18:6a4db94011d3	24818	#define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos) /!< SYS GPE_MFPL: PE7MFP Mask /
sahilmgandhi	18:6a4db94011d3	24819
sahilmgandhi	18:6a4db94011d3	24820	#define SYS_GPE_MFPH_PE8MFP_Pos (0) /!< SYS GPE_MFPH: PE8MFP Position /
sahilmgandhi	18:6a4db94011d3	24821	#define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos) /!< SYS GPE_MFPH: PE8MFP Mask /
sahilmgandhi	18:6a4db94011d3	24822
sahilmgandhi	18:6a4db94011d3	24823	#define SYS_GPE_MFPH_PE9MFP_Pos (4) /!< SYS GPE_MFPH: PE9MFP Position /
sahilmgandhi	18:6a4db94011d3	24824	#define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos) /!< SYS GPE_MFPH: PE9MFP Mask /
sahilmgandhi	18:6a4db94011d3	24825
sahilmgandhi	18:6a4db94011d3	24826	#define SYS_GPE_MFPH_PE10MFP_Pos (8) /!< SYS GPE_MFPH: PE10MFP Position /
sahilmgandhi	18:6a4db94011d3	24827	#define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos) /!< SYS GPE_MFPH: PE10MFP Mask /
sahilmgandhi	18:6a4db94011d3	24828
sahilmgandhi	18:6a4db94011d3	24829	#define SYS_GPE_MFPH_PE11MFP_Pos (12) /!< SYS GPE_MFPH: PE11MFP Position /
sahilmgandhi	18:6a4db94011d3	24830	#define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos) /!< SYS GPE_MFPH: PE11MFP Mask /
sahilmgandhi	18:6a4db94011d3	24831
sahilmgandhi	18:6a4db94011d3	24832	#define SYS_GPE_MFPH_PE12MFP_Pos (16) /!< SYS GPE_MFPH: PE12MFP Position /
sahilmgandhi	18:6a4db94011d3	24833	#define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos) /!< SYS GPE_MFPH: PE12MFP Mask /
sahilmgandhi	18:6a4db94011d3	24834
sahilmgandhi	18:6a4db94011d3	24835	#define SYS_GPE_MFPH_PE13MFP_Pos (20) /!< SYS GPE_MFPH: PE13MFP Position /
sahilmgandhi	18:6a4db94011d3	24836	#define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos) /!< SYS GPE_MFPH: PE13MFP Mask /
sahilmgandhi	18:6a4db94011d3	24837
sahilmgandhi	18:6a4db94011d3	24838	#define SYS_GPE_MFPH_PE14MFP_Pos (24) /!< SYS GPE_MFPH: PE14MFP Position /
sahilmgandhi	18:6a4db94011d3	24839	#define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos) /!< SYS GPE_MFPH: PE14MFP Mask /
sahilmgandhi	18:6a4db94011d3	24840
sahilmgandhi	18:6a4db94011d3	24841	#define SYS_GPE_MFPH_PE15MFP_Pos (28) /!< SYS GPE_MFPH: PE15MFP Position /
sahilmgandhi	18:6a4db94011d3	24842	#define SYS_GPE_MFPH_PE15MFP_Msk (0xful << SYS_GPE_MFPH_PE15MFP_Pos) /!< SYS GPE_MFPH: PE15MFP Mask /
sahilmgandhi	18:6a4db94011d3	24843
sahilmgandhi	18:6a4db94011d3	24844	#define SYS_GPF_MFPL_PF0MFP_Pos (0) /!< SYS GPF_MFPL: PF0MFP Position /
sahilmgandhi	18:6a4db94011d3	24845	#define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) /!< SYS GPF_MFPL: PF0MFP Mask /
sahilmgandhi	18:6a4db94011d3	24846
sahilmgandhi	18:6a4db94011d3	24847	#define SYS_GPF_MFPL_PF1MFP_Pos (4) /!< SYS GPF_MFPL: PF1MFP Position /
sahilmgandhi	18:6a4db94011d3	24848	#define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) /!< SYS GPF_MFPL: PF1MFP Mask /
sahilmgandhi	18:6a4db94011d3	24849
sahilmgandhi	18:6a4db94011d3	24850	#define SYS_GPF_MFPL_PF2MFP_Pos (8) /!< SYS GPF_MFPL: PF2MFP Position /
sahilmgandhi	18:6a4db94011d3	24851	#define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) /!< SYS GPF_MFPL: PF2MFP Mask /
sahilmgandhi	18:6a4db94011d3	24852
sahilmgandhi	18:6a4db94011d3	24853	#define SYS_GPF_MFPL_PF3MFP_Pos (12) /!< SYS GPF_MFPL: PF3MFP Position /
sahilmgandhi	18:6a4db94011d3	24854	#define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) /!< SYS GPF_MFPL: PF3MFP Mask /
sahilmgandhi	18:6a4db94011d3	24855
sahilmgandhi	18:6a4db94011d3	24856	#define SYS_GPF_MFPL_PF4MFP_Pos (16) /!< SYS GPF_MFPL: PF4MFP Position /
sahilmgandhi	18:6a4db94011d3	24857	#define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos) /!< SYS GPF_MFPL: PF4MFP Mask /
sahilmgandhi	18:6a4db94011d3	24858
sahilmgandhi	18:6a4db94011d3	24859	#define SYS_GPF_MFPL_PF5MFP_Pos (20) /!< SYS GPF_MFPL: PF5MFP Position /
sahilmgandhi	18:6a4db94011d3	24860	#define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos) /!< SYS GPF_MFPL: PF5MFP Mask /
sahilmgandhi	18:6a4db94011d3	24861
sahilmgandhi	18:6a4db94011d3	24862	#define SYS_GPF_MFPL_PF6MFP_Pos (24) /!< SYS GPF_MFPL: PF6MFP Position /
sahilmgandhi	18:6a4db94011d3	24863	#define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) /!< SYS GPF_MFPL: PF6MFP Mask /
sahilmgandhi	18:6a4db94011d3	24864
sahilmgandhi	18:6a4db94011d3	24865	#define SYS_GPF_MFPL_PF7MFP_Pos (28) /!< SYS GPF_MFPL: PF7MFP Position /
sahilmgandhi	18:6a4db94011d3	24866	#define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) /!< SYS GPF_MFPL: PF7MFP Mask /
sahilmgandhi	18:6a4db94011d3	24867
sahilmgandhi	18:6a4db94011d3	24868	#define SYS_GPF_MFPH_PF8MFP_Pos (0) /!< SYS GPF_MFPH: PF8MFP Position /
sahilmgandhi	18:6a4db94011d3	24869	#define SYS_GPF_MFPH_PF8MFP_Msk (0xful << SYS_GPF_MFPH_PF8MFP_Pos) /!< SYS GPF_MFPH: PF8MFP Mask /
sahilmgandhi	18:6a4db94011d3	24870
sahilmgandhi	18:6a4db94011d3	24871	#define SYS_GPF_MFPH_PF9MFP_Pos (4) /!< SYS GPF_MFPH: PF9MFP Position /
sahilmgandhi	18:6a4db94011d3	24872	#define SYS_GPF_MFPH_PF9MFP_Msk (0xful << SYS_GPF_MFPH_PF9MFP_Pos) /!< SYS GPF_MFPH: PF9MFP Mask /
sahilmgandhi	18:6a4db94011d3	24873
sahilmgandhi	18:6a4db94011d3	24874	#define SYS_GPF_MFPH_PF10MFP_Pos (8) /!< SYS GPF_MFPH: PF10MFP Position /
sahilmgandhi	18:6a4db94011d3	24875	#define SYS_GPF_MFPH_PF10MFP_Msk (0xful << SYS_GPF_MFPH_PF10MFP_Pos) /!< SYS GPF_MFPH: PF10MFP Mask /
sahilmgandhi	18:6a4db94011d3	24876
sahilmgandhi	18:6a4db94011d3	24877	#define SYS_GPF_MFPH_PF11MFP_Pos (12) /!< SYS GPF_MFPH: PF11MFP Position /
sahilmgandhi	18:6a4db94011d3	24878	#define SYS_GPF_MFPH_PF11MFP_Msk (0xful << SYS_GPF_MFPH_PF11MFP_Pos) /!< SYS GPF_MFPH: PF11MFP Mask /
sahilmgandhi	18:6a4db94011d3	24879
sahilmgandhi	18:6a4db94011d3	24880	#define SYS_GPF_MFPH_PF12MFP_Pos (16) /!< SYS GPF_MFPH: PF12MFP Position /
sahilmgandhi	18:6a4db94011d3	24881	#define SYS_GPF_MFPH_PF12MFP_Msk (0xful << SYS_GPF_MFPH_PF12MFP_Pos) /!< SYS GPF_MFPH: PF12MFP Mask /
sahilmgandhi	18:6a4db94011d3	24882
sahilmgandhi	18:6a4db94011d3	24883	#define SYS_GPF_MFPH_PF13MFP_Pos (20) /!< SYS GPF_MFPH: PF13MFP Position /
sahilmgandhi	18:6a4db94011d3	24884	#define SYS_GPF_MFPH_PF13MFP_Msk (0xful << SYS_GPF_MFPH_PF13MFP_Pos) /!< SYS GPF_MFPH: PF13MFP Mask /
sahilmgandhi	18:6a4db94011d3	24885
sahilmgandhi	18:6a4db94011d3	24886	#define SYS_GPF_MFPH_PF14MFP_Pos (24) /!< SYS GPF_MFPH: PF14MFP Position /
sahilmgandhi	18:6a4db94011d3	24887	#define SYS_GPF_MFPH_PF14MFP_Msk (0xful << SYS_GPF_MFPH_PF14MFP_Pos) /!< SYS GPF_MFPH: PF14MFP Mask /
sahilmgandhi	18:6a4db94011d3	24888
sahilmgandhi	18:6a4db94011d3	24889	#define SYS_GPF_MFPH_PF15MFP_Pos (28) /!< SYS GPF_MFPH: PF15MFP Position /
sahilmgandhi	18:6a4db94011d3	24890	#define SYS_GPF_MFPH_PF15MFP_Msk (0xful << SYS_GPF_MFPH_PF15MFP_Pos) /!< SYS GPF_MFPH: PF15MFP Mask /
sahilmgandhi	18:6a4db94011d3	24891
sahilmgandhi	18:6a4db94011d3	24892	#define SYS_GPG_MFPL_PG0MFP_Pos (0) /!< SYS GPG_MFPL: PG0MFP Position /
sahilmgandhi	18:6a4db94011d3	24893	#define SYS_GPG_MFPL_PG0MFP_Msk (0xful << SYS_GPG_MFPL_PG0MFP_Pos) /!< SYS GPG_MFPL: PG0MFP Mask /
sahilmgandhi	18:6a4db94011d3	24894
sahilmgandhi	18:6a4db94011d3	24895	#define SYS_GPG_MFPL_PG1MFP_Pos (4) /!< SYS GPG_MFPL: PG1MFP Position /
sahilmgandhi	18:6a4db94011d3	24896	#define SYS_GPG_MFPL_PG1MFP_Msk (0xful << SYS_GPG_MFPL_PG1MFP_Pos) /!< SYS GPG_MFPL: PG1MFP Mask /
sahilmgandhi	18:6a4db94011d3	24897
sahilmgandhi	18:6a4db94011d3	24898	#define SYS_GPG_MFPL_PG2MFP_Pos (8) /!< SYS GPG_MFPL: PG2MFP Position /
sahilmgandhi	18:6a4db94011d3	24899	#define SYS_GPG_MFPL_PG2MFP_Msk (0xful << SYS_GPG_MFPL_PG2MFP_Pos) /!< SYS GPG_MFPL: PG2MFP Mask /
sahilmgandhi	18:6a4db94011d3	24900
sahilmgandhi	18:6a4db94011d3	24901	#define SYS_GPG_MFPL_PG3MFP_Pos (12) /!< SYS GPG_MFPL: PG3MFP Position /
sahilmgandhi	18:6a4db94011d3	24902	#define SYS_GPG_MFPL_PG3MFP_Msk (0xful << SYS_GPG_MFPL_PG3MFP_Pos) /!< SYS GPG_MFPL: PG3MFP Mask /
sahilmgandhi	18:6a4db94011d3	24903
sahilmgandhi	18:6a4db94011d3	24904	#define SYS_GPG_MFPL_PG4MFP_Pos (16) /!< SYS GPG_MFPL: PG4MFP Position /
sahilmgandhi	18:6a4db94011d3	24905	#define SYS_GPG_MFPL_PG4MFP_Msk (0xful << SYS_GPG_MFPL_PG4MFP_Pos) /!< SYS GPG_MFPL: PG4MFP Mask /
sahilmgandhi	18:6a4db94011d3	24906
sahilmgandhi	18:6a4db94011d3	24907	#define SYS_GPG_MFPL_PG5MFP_Pos (20) /!< SYS GPG_MFPL: PG5MFP Position /
sahilmgandhi	18:6a4db94011d3	24908	#define SYS_GPG_MFPL_PG5MFP_Msk (0xful << SYS_GPG_MFPL_PG5MFP_Pos) /!< SYS GPG_MFPL: PG5MFP Mask /
sahilmgandhi	18:6a4db94011d3	24909
sahilmgandhi	18:6a4db94011d3	24910	#define SYS_GPG_MFPL_PG6MFP_Pos (24) /!< SYS GPG_MFPL: PG6MFP Position /
sahilmgandhi	18:6a4db94011d3	24911	#define SYS_GPG_MFPL_PG6MFP_Msk (0xful << SYS_GPG_MFPL_PG6MFP_Pos) /!< SYS GPG_MFPL: PG6MFP Mask /
sahilmgandhi	18:6a4db94011d3	24912
sahilmgandhi	18:6a4db94011d3	24913	#define SYS_GPG_MFPL_PG7MFP_Pos (28) /!< SYS GPG_MFPL: PG7MFP Position /
sahilmgandhi	18:6a4db94011d3	24914	#define SYS_GPG_MFPL_PG7MFP_Msk (0xful << SYS_GPG_MFPL_PG7MFP_Pos) /!< SYS GPG_MFPL: PG7MFP Mask /
sahilmgandhi	18:6a4db94011d3	24915
sahilmgandhi	18:6a4db94011d3	24916	#define SYS_GPG_MFPH_PG8MFP_Pos (0) /!< SYS GPG_MFPH: PG8MFP Position /
sahilmgandhi	18:6a4db94011d3	24917	#define SYS_GPG_MFPH_PG8MFP_Msk (0xful << SYS_GPG_MFPH_PG8MFP_Pos) /!< SYS GPG_MFPH: PG8MFP Mask /
sahilmgandhi	18:6a4db94011d3	24918
sahilmgandhi	18:6a4db94011d3	24919	#define SYS_GPG_MFPH_PG9MFP_Pos (4) /!< SYS GPG_MFPH: PG9MFP Position /
sahilmgandhi	18:6a4db94011d3	24920	#define SYS_GPG_MFPH_PG9MFP_Msk (0xful << SYS_GPG_MFPH_PG9MFP_Pos) /!< SYS GPG_MFPH: PG9MFP Mask /
sahilmgandhi	18:6a4db94011d3	24921
sahilmgandhi	18:6a4db94011d3	24922	#define SYS_GPG_MFPH_PG10MFP_Pos (8) /!< SYS GPG_MFPH: PG10MFP Position /
sahilmgandhi	18:6a4db94011d3	24923	#define SYS_GPG_MFPH_PG10MFP_Msk (0xful << SYS_GPG_MFPH_PG10MFP_Pos) /!< SYS GPG_MFPH: PG10MFP Mask /
sahilmgandhi	18:6a4db94011d3	24924
sahilmgandhi	18:6a4db94011d3	24925	#define SYS_GPG_MFPH_PG11MFP_Pos (12) /!< SYS GPG_MFPH: PG11MFP Position /
sahilmgandhi	18:6a4db94011d3	24926	#define SYS_GPG_MFPH_PG11MFP_Msk (0xful << SYS_GPG_MFPH_PG11MFP_Pos) /!< SYS GPG_MFPH: PG11MFP Mask /
sahilmgandhi	18:6a4db94011d3	24927
sahilmgandhi	18:6a4db94011d3	24928	#define SYS_GPG_MFPH_PG12MFP_Pos (16) /!< SYS GPG_MFPH: PG12MFP Position /
sahilmgandhi	18:6a4db94011d3	24929	#define SYS_GPG_MFPH_PG12MFP_Msk (0xful << SYS_GPG_MFPH_PG12MFP_Pos) /!< SYS GPG_MFPH: PG12MFP Mask /
sahilmgandhi	18:6a4db94011d3	24930
sahilmgandhi	18:6a4db94011d3	24931	#define SYS_GPG_MFPH_PG13MFP_Pos (20) /!< SYS GPG_MFPH: PG13MFP Position /
sahilmgandhi	18:6a4db94011d3	24932	#define SYS_GPG_MFPH_PG13MFP_Msk (0xful << SYS_GPG_MFPH_PG13MFP_Pos) /!< SYS GPG_MFPH: PG13MFP Mask /
sahilmgandhi	18:6a4db94011d3	24933
sahilmgandhi	18:6a4db94011d3	24934	#define SYS_GPG_MFPH_PG14MFP_Pos (24) /!< SYS GPG_MFPH: PG14MFP Position /
sahilmgandhi	18:6a4db94011d3	24935	#define SYS_GPG_MFPH_PG14MFP_Msk (0xful << SYS_GPG_MFPH_PG14MFP_Pos) /!< SYS GPG_MFPH: PG14MFP Mask /
sahilmgandhi	18:6a4db94011d3	24936
sahilmgandhi	18:6a4db94011d3	24937	#define SYS_GPG_MFPH_PG15MFP_Pos (28) /!< SYS GPG_MFPH: PG15MFP Position /
sahilmgandhi	18:6a4db94011d3	24938	#define SYS_GPG_MFPH_PG15MFP_Msk (0xful << SYS_GPG_MFPH_PG15MFP_Pos) /!< SYS GPG_MFPH: PG15MFP Mask /
sahilmgandhi	18:6a4db94011d3	24939
sahilmgandhi	18:6a4db94011d3	24940	#define SYS_GPH_MFPL_PH0MFP_Pos (0) /!< SYS GPH_MFPL: PH0MFP Position /
sahilmgandhi	18:6a4db94011d3	24941	#define SYS_GPH_MFPL_PH0MFP_Msk (0xful << SYS_GPH_MFPL_PH0MFP_Pos) /!< SYS GPH_MFPL: PH0MFP Mask /
sahilmgandhi	18:6a4db94011d3	24942
sahilmgandhi	18:6a4db94011d3	24943	#define SYS_GPH_MFPL_PH1MFP_Pos (4) /!< SYS GPH_MFPL: PH1MFP Position /
sahilmgandhi	18:6a4db94011d3	24944	#define SYS_GPH_MFPL_PH1MFP_Msk (0xful << SYS_GPH_MFPL_PH1MFP_Pos) /!< SYS GPH_MFPL: PH1MFP Mask /
sahilmgandhi	18:6a4db94011d3	24945
sahilmgandhi	18:6a4db94011d3	24946	#define SYS_GPH_MFPL_PH2MFP_Pos (8) /!< SYS GPH_MFPL: PH2MFP Position /
sahilmgandhi	18:6a4db94011d3	24947	#define SYS_GPH_MFPL_PH2MFP_Msk (0xful << SYS_GPH_MFPL_PH2MFP_Pos) /!< SYS GPH_MFPL: PH2MFP Mask /
sahilmgandhi	18:6a4db94011d3	24948
sahilmgandhi	18:6a4db94011d3	24949	#define SYS_GPH_MFPL_PH3MFP_Pos (12) /!< SYS GPH_MFPL: PH3MFP Position /
sahilmgandhi	18:6a4db94011d3	24950	#define SYS_GPH_MFPL_PH3MFP_Msk (0xful << SYS_GPH_MFPL_PH3MFP_Pos) /!< SYS GPH_MFPL: PH3MFP Mask /
sahilmgandhi	18:6a4db94011d3	24951
sahilmgandhi	18:6a4db94011d3	24952	#define SYS_GPH_MFPL_PH4MFP_Pos (16) /!< SYS GPH_MFPL: PH4MFP Position /
sahilmgandhi	18:6a4db94011d3	24953	#define SYS_GPH_MFPL_PH4MFP_Msk (0xful << SYS_GPH_MFPL_PH4MFP_Pos) /!< SYS GPH_MFPL: PH4MFP Mask /
sahilmgandhi	18:6a4db94011d3	24954
sahilmgandhi	18:6a4db94011d3	24955	#define SYS_GPH_MFPL_PH5MFP_Pos (20) /!< SYS GPH_MFPL: PH5MFP Position /
sahilmgandhi	18:6a4db94011d3	24956	#define SYS_GPH_MFPL_PH5MFP_Msk (0xful << SYS_GPH_MFPL_PH5MFP_Pos) /!< SYS GPH_MFPL: PH5MFP Mask /
sahilmgandhi	18:6a4db94011d3	24957
sahilmgandhi	18:6a4db94011d3	24958	#define SYS_GPH_MFPL_PH6MFP_Pos (24) /!< SYS GPH_MFPL: PH6MFP Position /
sahilmgandhi	18:6a4db94011d3	24959	#define SYS_GPH_MFPL_PH6MFP_Msk (0xful << SYS_GPH_MFPL_PH6MFP_Pos) /!< SYS GPH_MFPL: PH6MFP Mask /
sahilmgandhi	18:6a4db94011d3	24960
sahilmgandhi	18:6a4db94011d3	24961	#define SYS_GPH_MFPL_PH7MFP_Pos (28) /!< SYS GPH_MFPL: PH7MFP Position /
sahilmgandhi	18:6a4db94011d3	24962	#define SYS_GPH_MFPL_PH7MFP_Msk (0xful << SYS_GPH_MFPL_PH7MFP_Pos) /!< SYS GPH_MFPL: PH7MFP Mask /
sahilmgandhi	18:6a4db94011d3	24963
sahilmgandhi	18:6a4db94011d3	24964	#define SYS_GPH_MFPH_PH8MFP_Pos (0) /!< SYS GPH_MFPH: PH8MFP Position /
sahilmgandhi	18:6a4db94011d3	24965	#define SYS_GPH_MFPH_PH8MFP_Msk (0xful << SYS_GPH_MFPH_PH8MFP_Pos) /!< SYS GPH_MFPH: PH8MFP Mask /
sahilmgandhi	18:6a4db94011d3	24966
sahilmgandhi	18:6a4db94011d3	24967	#define SYS_GPH_MFPH_PH9MFP_Pos (4) /!< SYS GPH_MFPH: PH9MFP Position /
sahilmgandhi	18:6a4db94011d3	24968	#define SYS_GPH_MFPH_PH9MFP_Msk (0xful << SYS_GPH_MFPH_PH9MFP_Pos) /!< SYS GPH_MFPH: PH9MFP Mask /
sahilmgandhi	18:6a4db94011d3	24969
sahilmgandhi	18:6a4db94011d3	24970	#define SYS_GPH_MFPH_PH10MFP_Pos (8) /!< SYS GPH_MFPH: PH10MFP Position /
sahilmgandhi	18:6a4db94011d3	24971	#define SYS_GPH_MFPH_PH10MFP_Msk (0xful << SYS_GPH_MFPH_PH10MFP_Pos) /!< SYS GPH_MFPH: PH10MFP Mask /
sahilmgandhi	18:6a4db94011d3	24972
sahilmgandhi	18:6a4db94011d3	24973	#define SYS_GPH_MFPH_PH11MFP_Pos (12) /!< SYS GPH_MFPH: PH11MFP Position /
sahilmgandhi	18:6a4db94011d3	24974	#define SYS_GPH_MFPH_PH11MFP_Msk (0xful << SYS_GPH_MFPH_PH11MFP_Pos) /!< SYS GPH_MFPH: PH11MFP Mask /
sahilmgandhi	18:6a4db94011d3	24975
sahilmgandhi	18:6a4db94011d3	24976	#define SYS_GPH_MFPH_PH12MFP_Pos (16) /!< SYS GPH_MFPH: PH12MFP Position /
sahilmgandhi	18:6a4db94011d3	24977	#define SYS_GPH_MFPH_PH12MFP_Msk (0xful << SYS_GPH_MFPH_PH12MFP_Pos) /!< SYS GPH_MFPH: PH12MFP Mask /
sahilmgandhi	18:6a4db94011d3	24978
sahilmgandhi	18:6a4db94011d3	24979	#define SYS_GPH_MFPH_PH13MFP_Pos (20) /!< SYS GPH_MFPH: PH13MFP Position /
sahilmgandhi	18:6a4db94011d3	24980	#define SYS_GPH_MFPH_PH13MFP_Msk (0xful << SYS_GPH_MFPH_PH13MFP_Pos) /!< SYS GPH_MFPH: PH13MFP Mask /
sahilmgandhi	18:6a4db94011d3	24981
sahilmgandhi	18:6a4db94011d3	24982	#define SYS_GPH_MFPH_PH14MFP_Pos (24) /!< SYS GPH_MFPH: PH14MFP Position /
sahilmgandhi	18:6a4db94011d3	24983	#define SYS_GPH_MFPH_PH14MFP_Msk (0xful << SYS_GPH_MFPH_PH14MFP_Pos) /!< SYS GPH_MFPH: PH14MFP Mask /
sahilmgandhi	18:6a4db94011d3	24984
sahilmgandhi	18:6a4db94011d3	24985	#define SYS_GPH_MFPH_PH15MFP_Pos (28) /!< SYS GPH_MFPH: PH15MFP Position /
sahilmgandhi	18:6a4db94011d3	24986	#define SYS_GPH_MFPH_PH15MFP_Msk (0xful << SYS_GPH_MFPH_PH15MFP_Pos) /!< SYS GPH_MFPH: PH15MFP Mask /
sahilmgandhi	18:6a4db94011d3	24987
sahilmgandhi	18:6a4db94011d3	24988	#define SYS_GPI_MFPL_PI0MFP_Pos (0) /!< SYS GPI_MFPL: PI0MFP Position /
sahilmgandhi	18:6a4db94011d3	24989	#define SYS_GPI_MFPL_PI0MFP_Msk (0xful << SYS_GPI_MFPL_PI0MFP_Pos) /!< SYS GPI_MFPL: PI0MFP Mask /
sahilmgandhi	18:6a4db94011d3	24990
sahilmgandhi	18:6a4db94011d3	24991	#define SYS_GPI_MFPL_PI1MFP_Pos (4) /!< SYS GPI_MFPL: PI1MFP Position /
sahilmgandhi	18:6a4db94011d3	24992	#define SYS_GPI_MFPL_PI1MFP_Msk (0xful << SYS_GPI_MFPL_PI1MFP_Pos) /!< SYS GPI_MFPL: PI1MFP Mask /
sahilmgandhi	18:6a4db94011d3	24993
sahilmgandhi	18:6a4db94011d3	24994	#define SYS_GPI_MFPL_PI2MFP_Pos (8) /!< SYS GPI_MFPL: PI2MFP Position /
sahilmgandhi	18:6a4db94011d3	24995	#define SYS_GPI_MFPL_PI2MFP_Msk (0xful << SYS_GPI_MFPL_PI2MFP_Pos) /!< SYS GPI_MFPL: PI2MFP Mask /
sahilmgandhi	18:6a4db94011d3	24996
sahilmgandhi	18:6a4db94011d3	24997	#define SYS_GPI_MFPL_PI3MFP_Pos (12) /!< SYS GPI_MFPL: PI3MFP Position /
sahilmgandhi	18:6a4db94011d3	24998	#define SYS_GPI_MFPL_PI3MFP_Msk (0xful << SYS_GPI_MFPL_PI3MFP_Pos) /!< SYS GPI_MFPL: PI3MFP Mask /
sahilmgandhi	18:6a4db94011d3	24999
sahilmgandhi	18:6a4db94011d3	25000	#define SYS_GPI_MFPL_PI4MFP_Pos (16) /!< SYS GPI_MFPL: PI4MFP Position /
sahilmgandhi	18:6a4db94011d3	25001	#define SYS_GPI_MFPL_PI4MFP_Msk (0xful << SYS_GPI_MFPL_PI4MFP_Pos) /!< SYS GPI_MFPL: PI4MFP Mask /
sahilmgandhi	18:6a4db94011d3	25002
sahilmgandhi	18:6a4db94011d3	25003	#define SYS_GPI_MFPL_PI5MFP_Pos (20) /!< SYS GPI_MFPL: PI5MFP Position /
sahilmgandhi	18:6a4db94011d3	25004	#define SYS_GPI_MFPL_PI5MFP_Msk (0xful << SYS_GPI_MFPL_PI5MFP_Pos) /!< SYS GPI_MFPL: PI5MFP Mask /
sahilmgandhi	18:6a4db94011d3	25005
sahilmgandhi	18:6a4db94011d3	25006	#define SYS_GPI_MFPL_PI6MFP_Pos (24) /!< SYS GPI_MFPL: PI6MFP Position /
sahilmgandhi	18:6a4db94011d3	25007	#define SYS_GPI_MFPL_PI6MFP_Msk (0xful << SYS_GPI_MFPL_PI6MFP_Pos) /!< SYS GPI_MFPL: PI6MFP Mask /
sahilmgandhi	18:6a4db94011d3	25008
sahilmgandhi	18:6a4db94011d3	25009	#define SYS_GPI_MFPL_PI7MFP_Pos (28) /!< SYS GPI_MFPL: PI7MFP Position /
sahilmgandhi	18:6a4db94011d3	25010	#define SYS_GPI_MFPL_PI7MFP_Msk (0xful << SYS_GPI_MFPL_PI7MFP_Pos) /!< SYS GPI_MFPL: PI7MFP Mask /
sahilmgandhi	18:6a4db94011d3	25011
sahilmgandhi	18:6a4db94011d3	25012	#define SYS_GPI_MFPH_PI8MFP_Pos (0) /!< SYS GPI_MFPH: PI8MFP Position /
sahilmgandhi	18:6a4db94011d3	25013	#define SYS_GPI_MFPH_PI8MFP_Msk (0xful << SYS_GPI_MFPH_PI8MFP_Pos) /!< SYS GPI_MFPH: PI8MFP Mask /
sahilmgandhi	18:6a4db94011d3	25014
sahilmgandhi	18:6a4db94011d3	25015	#define SYS_GPI_MFPH_PI9MFP_Pos (4) /!< SYS GPI_MFPH: PI9MFP Position /
sahilmgandhi	18:6a4db94011d3	25016	#define SYS_GPI_MFPH_PI9MFP_Msk (0xful << SYS_GPI_MFPH_PI9MFP_Pos) /!< SYS GPI_MFPH: PI9MFP Mask /
sahilmgandhi	18:6a4db94011d3	25017
sahilmgandhi	18:6a4db94011d3	25018	#define SYS_GPI_MFPH_PI10MFP_Pos (8) /!< SYS GPI_MFPH: PI10MFP Position /
sahilmgandhi	18:6a4db94011d3	25019	#define SYS_GPI_MFPH_PI10MFP_Msk (0xful << SYS_GPI_MFPH_PI10MFP_Pos) /!< SYS GPI_MFPH: PI10MFP Mask /
sahilmgandhi	18:6a4db94011d3	25020
sahilmgandhi	18:6a4db94011d3	25021	#define SYS_GPI_MFPH_PI11MFP_Pos (12) /!< SYS GPI_MFPH: PI11MFP Position /
sahilmgandhi	18:6a4db94011d3	25022	#define SYS_GPI_MFPH_PI11MFP_Msk (0xful << SYS_GPI_MFPH_PI11MFP_Pos) /!< SYS GPI_MFPH: PI11MFP Mask /
sahilmgandhi	18:6a4db94011d3	25023
sahilmgandhi	18:6a4db94011d3	25024	#define SYS_GPI_MFPH_PI12MFP_Pos (16) /!< SYS GPI_MFPH: PI12MFP Position /
sahilmgandhi	18:6a4db94011d3	25025	#define SYS_GPI_MFPH_PI12MFP_Msk (0xful << SYS_GPI_MFPH_PI12MFP_Pos) /!< SYS GPI_MFPH: PI12MFP Mask /
sahilmgandhi	18:6a4db94011d3	25026
sahilmgandhi	18:6a4db94011d3	25027	#define SYS_GPI_MFPH_PI13MFP_Pos (20) /!< SYS GPI_MFPH: PI13MFP Position /
sahilmgandhi	18:6a4db94011d3	25028	#define SYS_GPI_MFPH_PI13MFP_Msk (0xful << SYS_GPI_MFPH_PI13MFP_Pos) /!< SYS GPI_MFPH: PI13MFP Mask /
sahilmgandhi	18:6a4db94011d3	25029
sahilmgandhi	18:6a4db94011d3	25030	#define SYS_GPI_MFPH_PI14MFP_Pos (24) /!< SYS GPI_MFPH: PI14MFP Position /
sahilmgandhi	18:6a4db94011d3	25031	#define SYS_GPI_MFPH_PI14MFP_Msk (0xful << SYS_GPI_MFPH_PI14MFP_Pos) /!< SYS GPI_MFPH: PI14MFP Mask /
sahilmgandhi	18:6a4db94011d3	25032
sahilmgandhi	18:6a4db94011d3	25033	#define SYS_GPI_MFPH_PI15MFP_Pos (28) /!< SYS GPI_MFPH: PI15MFP Position /
sahilmgandhi	18:6a4db94011d3	25034	#define SYS_GPI_MFPH_PI15MFP_Msk (0xful << SYS_GPI_MFPH_PI15MFP_Pos) /!< SYS GPI_MFPH: PI15MFP Mask /
sahilmgandhi	18:6a4db94011d3	25035
sahilmgandhi	18:6a4db94011d3	25036	#define SYS_SRAM_INTCTL_PERRIEN_Pos (0) /!< SYS SRAM_INTCTL: PERRIEN Position /
sahilmgandhi	18:6a4db94011d3	25037	#define SYS_SRAM_INTCTL_PERRIEN_Msk (0x1ul << SYS_SRAM_INTCTL_PERRIEN_Pos) /!< SYS SRAM_INTCTL: PERRIEN Mask /
sahilmgandhi	18:6a4db94011d3	25038
sahilmgandhi	18:6a4db94011d3	25039	#define SYS_SRAM_STATUS_PERRIF0_Pos (0) /!< SYS SRAM_STATUS: PERRIF0 Position /
sahilmgandhi	18:6a4db94011d3	25040	#define SYS_SRAM_STATUS_PERRIF0_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF0_Pos) /!< SYS SRAM_STATUS: PERRIF0 Mask /
sahilmgandhi	18:6a4db94011d3	25041
sahilmgandhi	18:6a4db94011d3	25042	#define SYS_SRAM_STATUS_PERRIF1_Pos (1) /!< SYS SRAM_STATUS: PERRIF1 Position /
sahilmgandhi	18:6a4db94011d3	25043	#define SYS_SRAM_STATUS_PERRIF1_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF1_Pos) /!< SYS SRAM_STATUS: PERRIF1 Mask /
sahilmgandhi	18:6a4db94011d3	25044
sahilmgandhi	18:6a4db94011d3	25045	#define SYS_SRAM0_ERRADDR_PERRADDR_Pos (0) /!< SYS SRAM0_ERRADDR: PERRADDR Position /
sahilmgandhi	18:6a4db94011d3	25046	#define SYS_SRAM0_ERRADDR_PERRADDR_Msk (0xfffffffful << SYS_SRAM0_ERRADDR_PERRADDR_Pos) /!< SYS SRAM0_ERRADDR: PERRADDR Mask /
sahilmgandhi	18:6a4db94011d3	25047
sahilmgandhi	18:6a4db94011d3	25048	#define SYS_SRAM1_ERRADDR_PERRADDR_Pos (0) /!< SYS SRAM1_ERRADDR: PERRADDR Position /
sahilmgandhi	18:6a4db94011d3	25049	#define SYS_SRAM1_ERRADDR_PERRADDR_Msk (0xfffffffful << SYS_SRAM1_ERRADDR_PERRADDR_Pos) /!< SYS SRAM1_ERRADDR: PERRADDR Mask /
sahilmgandhi	18:6a4db94011d3	25050
sahilmgandhi	18:6a4db94011d3	25051	#define SYS_IRCTCTL_FREQSEL_Pos (0) /!< SYS IRCTCTL: FREQSEL Position /
sahilmgandhi	18:6a4db94011d3	25052	#define SYS_IRCTCTL_FREQSEL_Msk (0x3ul << SYS_IRCTCTL_FREQSEL_Pos) /!< SYS IRCTCTL: FREQSEL Mask /
sahilmgandhi	18:6a4db94011d3	25053
sahilmgandhi	18:6a4db94011d3	25054	#define SYS_IRCTCTL_CALCLOOP_Pos (4) /!< SYS IRCTCTL: CALCLOOP Position /
sahilmgandhi	18:6a4db94011d3	25055	#define SYS_IRCTCTL_CALCLOOP_Msk (0x3ul << SYS_IRCTCTL_CALCLOOP_Pos) /!< SYS IRCTCTL: CALCLOOP Mask /
sahilmgandhi	18:6a4db94011d3	25056
sahilmgandhi	18:6a4db94011d3	25057	#define SYS_IRCTCTL_RETRYCNT_Pos (6) /!< SYS IRCTCTL: RETRYCNT Position /
sahilmgandhi	18:6a4db94011d3	25058	#define SYS_IRCTCTL_RETRYCNT_Msk (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos) /!< SYS IRCTCTL: RETRYCNT Mask /
sahilmgandhi	18:6a4db94011d3	25059
sahilmgandhi	18:6a4db94011d3	25060	#define SYS_IRCTCTL_CESTOPEN_Pos (8) /!< SYS IRCTCTL: CESTOPEN Position /
sahilmgandhi	18:6a4db94011d3	25061	#define SYS_IRCTCTL_CESTOPEN_Msk (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos) /!< SYS IRCTCTL: CESTOPEN Mask /
sahilmgandhi	18:6a4db94011d3	25062
sahilmgandhi	18:6a4db94011d3	25063	#define SYS_IRCTIEN_TFAILIEN_Pos (1) /!< SYS IRCTIEN: TFAILIEN Position /
sahilmgandhi	18:6a4db94011d3	25064	#define SYS_IRCTIEN_TFAILIEN_Msk (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos) /!< SYS IRCTIEN: TFAILIEN Mask /
sahilmgandhi	18:6a4db94011d3	25065
sahilmgandhi	18:6a4db94011d3	25066	#define SYS_IRCTIEN_CLKEIEN_Pos (2) /!< SYS IRCTIEN: CLKEIEN Position /
sahilmgandhi	18:6a4db94011d3	25067	#define SYS_IRCTIEN_CLKEIEN_Msk (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos) /!< SYS IRCTIEN: CLKEIEN Mask /
sahilmgandhi	18:6a4db94011d3	25068
sahilmgandhi	18:6a4db94011d3	25069	#define SYS_IRCTISTS_FREQLOCK_Pos (0) /!< SYS IRCTISTS: FREQLOCK Position /
sahilmgandhi	18:6a4db94011d3	25070	#define SYS_IRCTISTS_FREQLOCK_Msk (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos) /!< SYS IRCTISTS: FREQLOCK Mask /
sahilmgandhi	18:6a4db94011d3	25071
sahilmgandhi	18:6a4db94011d3	25072	#define SYS_IRCTISTS_TFAILIF_Pos (1) /!< SYS IRCTISTS: TFAILIF Position /
sahilmgandhi	18:6a4db94011d3	25073	#define SYS_IRCTISTS_TFAILIF_Msk (0x1ul << SYS_IRCTISTS_TFAILIF_Pos) /!< SYS IRCTISTS: TFAILIF Mask /
sahilmgandhi	18:6a4db94011d3	25074
sahilmgandhi	18:6a4db94011d3	25075	#define SYS_IRCTISTS_CLKERRIF_Pos (2) /!< SYS IRCTISTS: CLKERRIF Position /
sahilmgandhi	18:6a4db94011d3	25076	#define SYS_IRCTISTS_CLKERRIF_Msk (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos) /!< SYS IRCTISTS: CLKERRIF Mask /
sahilmgandhi	18:6a4db94011d3	25077
sahilmgandhi	18:6a4db94011d3	25078	#define SYS_REGLCTL_REGLCTL_Pos (0) /!< SYS REGLCTL: REGLCTL Position /
sahilmgandhi	18:6a4db94011d3	25079	#define SYS_REGLCTL_REGLCTL_Msk (0x1ul << SYS_REGLCTL_REGLCTL_Pos) /!< SYS REGLCTL: REGLCTL Mask /
sahilmgandhi	18:6a4db94011d3	25080
sahilmgandhi	18:6a4db94011d3	25081	#define SYS_REGLCTL_SYS_REGLCTL_Pos (0) /!< SYS REGLCTL: SYS_REGLCTL Position /
sahilmgandhi	18:6a4db94011d3	25082	#define SYS_REGLCTL_SYS_REGLCTL_Msk (0xfful << SYS_REGLCTL_SYS_REGLCTL_Pos) /!< SYS REGLCTL: SYS_REGLCTL Mask /
sahilmgandhi	18:6a4db94011d3	25083
sahilmgandhi	18:6a4db94011d3	25084	/*@}/ /* SYS_CONST */
sahilmgandhi	18:6a4db94011d3	25085	/*@}/ /* end of SYS register group */
sahilmgandhi	18:6a4db94011d3	25086
sahilmgandhi	18:6a4db94011d3	25087
sahilmgandhi	18:6a4db94011d3	25088	/---------------------- Timer Controller -------------------------/
sahilmgandhi	18:6a4db94011d3	25089	/**
sahilmgandhi	18:6a4db94011d3	25090	@addtogroup TIMER Timer Controller(TIMER)
sahilmgandhi	18:6a4db94011d3	25091	Memory Mapped Structure for TIMER Controller
sahilmgandhi	18:6a4db94011d3	25092	@{ */
sahilmgandhi	18:6a4db94011d3	25093
sahilmgandhi	18:6a4db94011d3	25094	typedef struct {
sahilmgandhi	18:6a4db94011d3	25095
sahilmgandhi	18:6a4db94011d3	25096
sahilmgandhi	18:6a4db94011d3	25097	/**
sahilmgandhi	18:6a4db94011d3	25098	* CTL
sahilmgandhi	18:6a4db94011d3	25099	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	25100	* Offset: 0x00 Timer Control and Status Register
sahilmgandhi	18:6a4db94011d3	25101	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	25102	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	25103	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	25104	* \|[0:7] \|PSC \|PSC Counter
sahilmgandhi	18:6a4db94011d3	25105	* \| \| \|Timer input clock source is divided by (PSC+1) before it is fed to the timer up counter.
sahilmgandhi	18:6a4db94011d3	25106	* \| \| \|If this field is 0 (PSC = 0), then there is no scaling.
sahilmgandhi	18:6a4db94011d3	25107	* \|[16] \|CNTDATEN \|Data Load Enable
sahilmgandhi	18:6a4db94011d3	25108	* \| \| \|When this bit is set, timer counter value (TIMER_CNT) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.
sahilmgandhi	18:6a4db94011d3	25109	* \| \| \|0 = Timer Data Register update Disabled.
sahilmgandhi	18:6a4db94011d3	25110	* \| \| \|1 = Timer Data Register update Enabled while timer counter is active.
sahilmgandhi	18:6a4db94011d3	25111	* \|[21] \|TOGDIS1 \|Toggle Output 1 Disable
sahilmgandhi	18:6a4db94011d3	25112	* \| \| \|Setting this bit will disable the Toggle output pins group 1.
sahilmgandhi	18:6a4db94011d3	25113	* \| \| \|0 = Toggle output pins group 1 Enabled.
sahilmgandhi	18:6a4db94011d3	25114	* \| \| \|1 = Toggle output pins group 1 Disabled.
sahilmgandhi	18:6a4db94011d3	25115	* \| \| \|Note: The group1 pins are PB4, PB1, PC6, and PC1.
sahilmgandhi	18:6a4db94011d3	25116	* \|[22] \|TOGDIS2 \|Toggle Output 2 Disable
sahilmgandhi	18:6a4db94011d3	25117	* \| \| \|Setting this bit will disable the Toggle output pins group 2.
sahilmgandhi	18:6a4db94011d3	25118	* \| \| \|0 = Toggle output pins group 2 Enabled.
sahilmgandhi	18:6a4db94011d3	25119	* \| \| \|1 = Toggle output pins group 2 Disabled.
sahilmgandhi	18:6a4db94011d3	25120	* \| \| \|Note1: If both TOUT1 (group 1 pins) and TOUT2 (group 2 pins) function are enabled, toggle output signal is generated only from TOUT1 pins.
sahilmgandhi	18:6a4db94011d3	25121	* \| \| \|Note2: The group2 pins are PD1, PE8, PE1, and PD11.
sahilmgandhi	18:6a4db94011d3	25122	* \|[23] \|WKEN \|Wake-Up Enable
sahilmgandhi	18:6a4db94011d3	25123	* \| \| \|If this bit is set to 1, while timer interrupt flag TIF (TIMER_INTSTS[0]) is 1 and INTEN (TIMERX_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
sahilmgandhi	18:6a4db94011d3	25124	* \| \| \|0 = Wake-up trigger event Disabled if timer interrupt signal generated.
sahilmgandhi	18:6a4db94011d3	25125	* \| \| \|1 = Wake-up trigger event Enabled if timer interrupt signal generated.
sahilmgandhi	18:6a4db94011d3	25126	* \|[24] \|EXTCNTEN \|Counter Mode Enable Bit
sahilmgandhi	18:6a4db94011d3	25127	* \| \| \|This bit is for external counting pin function enabled.
sahilmgandhi	18:6a4db94011d3	25128	* \| \| \|When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source.
sahilmgandhi	18:6a4db94011d3	25129	* \| \| \|0 = External counter mode Disabled.
sahilmgandhi	18:6a4db94011d3	25130	* \| \| \|1 = External counter mode Enabled.
sahilmgandhi	18:6a4db94011d3	25131	* \|[25] \|ACTSTS \|Timer Active Status Bit (Read Only)
sahilmgandhi	18:6a4db94011d3	25132	* \| \| \|This bit indicates the 24-bit up counter status.
sahilmgandhi	18:6a4db94011d3	25133	* \| \| \|0 = 24-bit up counter is not active.
sahilmgandhi	18:6a4db94011d3	25134	* \| \| \|1 = 24-bit up counter is active.
sahilmgandhi	18:6a4db94011d3	25135	* \|[26] \|RSTCNT \|Timer Reset Bit
sahilmgandhi	18:6a4db94011d3	25136	* \| \| \|Setting this bit will reset the 24-bit up counter value (TIMER_CNT) and also force CNTEN (TIMERX_CTL[30]) to 0 if ACTSTS (TIMERX_CTL[25]) is 1.
sahilmgandhi	18:6a4db94011d3	25137	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	25138	* \| \| \|1 = Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit.
sahilmgandhi	18:6a4db94011d3	25139	* \|[27:28] \|OPMODE \|Timer Operation Mode
sahilmgandhi	18:6a4db94011d3	25140	* \| \| \|00 = The Timer controller is operated in One-shot mode.
sahilmgandhi	18:6a4db94011d3	25141	* \| \| \|01 = The Timer controller is operated in Periodic mode.
sahilmgandhi	18:6a4db94011d3	25142	* \| \| \|10 = The Timer controller is operated in Toggle-output mode.
sahilmgandhi	18:6a4db94011d3	25143	* \| \| \|11 = The Timer controller is operated in Continuous Counting mode.
sahilmgandhi	18:6a4db94011d3	25144	* \|[29] \|INTEN \|Interrupt Enable Bit
sahilmgandhi	18:6a4db94011d3	25145	* \| \| \|0 = Timer Interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	25146	* \| \| \|1 = Timer Interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	25147	* \| \| \|If this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
sahilmgandhi	18:6a4db94011d3	25148	* \|[30] \|CNTEN \|Timer Enable
sahilmgandhi	18:6a4db94011d3	25149	* \| \| \|0 = Stops/Suspends counting.
sahilmgandhi	18:6a4db94011d3	25150	* \| \| \|1 = Starts counting.
sahilmgandhi	18:6a4db94011d3	25151	* \| \| \|Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value.
sahilmgandhi	18:6a4db94011d3	25152	* \| \| \|Note2: This bit is auto-cleared by hardware in one-shot mode (TIMERX_CTL[28:27] = 00) when the timer interrupt flag TIF (TIMER_INTSTS[0]) is generated.
sahilmgandhi	18:6a4db94011d3	25153	* \|[31] \|ICEDEBUG \|ICE Debug Mode Acknowledge Disable (Write Protect)
sahilmgandhi	18:6a4db94011d3	25154	* \| \| \|0 = ICE debug mode acknowledgement effects TIMER counting.
sahilmgandhi	18:6a4db94011d3	25155	* \| \| \|TIMER counter will be held while CPU is held by ICE.
sahilmgandhi	18:6a4db94011d3	25156	* \| \| \|1 = ICE debug mode acknowledgement Disabled.
sahilmgandhi	18:6a4db94011d3	25157	* \| \| \|TIMER counter will keep going no matter CPU is held by ICE or not.
sahilmgandhi	18:6a4db94011d3	25158	*/
sahilmgandhi	18:6a4db94011d3	25159	__IO uint32_t CTL;
sahilmgandhi	18:6a4db94011d3	25160
sahilmgandhi	18:6a4db94011d3	25161	/**
sahilmgandhi	18:6a4db94011d3	25162	* CMP
sahilmgandhi	18:6a4db94011d3	25163	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	25164	* Offset: 0x04 Timer Compare Register
sahilmgandhi	18:6a4db94011d3	25165	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	25166	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	25167	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	25168	* \|[0:23] \|CMPDAT \|Timer Compared Value
sahilmgandhi	18:6a4db94011d3	25169	* \| \| \|CMPDAT is a 24-bit compared value register.
sahilmgandhi	18:6a4db94011d3	25170	* \| \| \|When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMER_INTSTS[0] timer interrupt flag) will set to 1.
sahilmgandhi	18:6a4db94011d3	25171	* \| \| \|Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT).
sahilmgandhi	18:6a4db94011d3	25172	* \| \| \|Note1: Never write 0x0 or 0x1 in CMPDAT field, or the timer will run into unknown state.
sahilmgandhi	18:6a4db94011d3	25173	* \| \| \|Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if software writes a new value into CMPDAT field.
sahilmgandhi	18:6a4db94011d3	25174	* \| \| \|But if timer is operating at other modes, the 24-bit up counter will restart counting and using newest CMPDAT value to be the timer compared value if software writes a new value into CMPDAT field.
sahilmgandhi	18:6a4db94011d3	25175	*/
sahilmgandhi	18:6a4db94011d3	25176	__IO uint32_t CMP;
sahilmgandhi	18:6a4db94011d3	25177
sahilmgandhi	18:6a4db94011d3	25178	/**
sahilmgandhi	18:6a4db94011d3	25179	* INTSTS
sahilmgandhi	18:6a4db94011d3	25180	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	25181	* Offset: 0x08 Timer Interrupt Status Register
sahilmgandhi	18:6a4db94011d3	25182	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	25183	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	25184	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	25185	* \|[0] \|TIF \|Timer Interrupt Flag
sahilmgandhi	18:6a4db94011d3	25186	* \| \| \|This bit indicates the interrupt flag status of Timer while TIMER_CNT value reaches to CMPDAT value.
sahilmgandhi	18:6a4db94011d3	25187	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	25188	* \| \| \|1 = TIMER_CNT value matches the CMPDAT value.
sahilmgandhi	18:6a4db94011d3	25189	* \| \| \|Note: This bit is cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	25190	* \|[1] \|TWKF \|Timer Wake-Up Flag
sahilmgandhi	18:6a4db94011d3	25191	* \| \| \|This bit indicates the interrupt wake-up flag status of timer.
sahilmgandhi	18:6a4db94011d3	25192	* \| \| \|0 = Timer does not cause CPU wake-up.
sahilmgandhi	18:6a4db94011d3	25193	* \| \| \|1 = CPU wake-up from Idle or power-down mode if timer time-out interrupt signal generated.
sahilmgandhi	18:6a4db94011d3	25194	* \| \| \|Note: This bit is cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	25195	*/
sahilmgandhi	18:6a4db94011d3	25196	__IO uint32_t INTSTS;
sahilmgandhi	18:6a4db94011d3	25197
sahilmgandhi	18:6a4db94011d3	25198	/**
sahilmgandhi	18:6a4db94011d3	25199	* CNT
sahilmgandhi	18:6a4db94011d3	25200	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	25201	* Offset: 0x0C Timer Data Register
sahilmgandhi	18:6a4db94011d3	25202	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	25203	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	25204	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	25205	* \|[0:23] \|TIMER_CNT \|Timer Data Register
sahilmgandhi	18:6a4db94011d3	25206	* \| \| \|1. EXTCNTEN (TIMERX_CTL[24] ) = 0 : TIMER_CNT is 24- bit counter value.
sahilmgandhi	18:6a4db94011d3	25207	* \| \| \|User can read TIMER_CNT for getting current 24- bit counter value if TIMERX_CTL[24] is set to 0
sahilmgandhi	18:6a4db94011d3	25208	* \| \| \|2. EXTCNTEN (TIMERX_CTL[24] ) = 1 : TIMER_CNT is 24- bit event counter value.
sahilmgandhi	18:6a4db94011d3	25209	* \| \| \|User can read TIMER_CNT for getting current 24- bit event counter value if TIMERX_CTL[24] is 1
sahilmgandhi	18:6a4db94011d3	25210	*/
sahilmgandhi	18:6a4db94011d3	25211	__I uint32_t CNT;
sahilmgandhi	18:6a4db94011d3	25212
sahilmgandhi	18:6a4db94011d3	25213	/**
sahilmgandhi	18:6a4db94011d3	25214	* CAP
sahilmgandhi	18:6a4db94011d3	25215	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	25216	* Offset: 0x10 Timer Capture Data Register
sahilmgandhi	18:6a4db94011d3	25217	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	25218	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	25219	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	25220	* \|[0:23] \|CAPDAT \|Timer Capture Data Register
sahilmgandhi	18:6a4db94011d3	25221	* \| \| \|When CAPEN (TIMER_EXTCTL[3]) bit is set, CAPFUNCS (TIMER_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMER_EXTCTL[2:1]) setting, CAPIF (TIMER_EINTSTS[0]) will set to 1 and the current timer counter value (TIMER_CNT value) will be auto-loaded into this CAPDAT field.
sahilmgandhi	18:6a4db94011d3	25222	*/
sahilmgandhi	18:6a4db94011d3	25223	__I uint32_t CAP;
sahilmgandhi	18:6a4db94011d3	25224
sahilmgandhi	18:6a4db94011d3	25225	/**
sahilmgandhi	18:6a4db94011d3	25226	* EXTCTL
sahilmgandhi	18:6a4db94011d3	25227	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	25228	* Offset: 0x14 Timer External Control Register
sahilmgandhi	18:6a4db94011d3	25229	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	25230	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	25231	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	25232	* \|[0] \|CNTPHASE \|Timer External Count Phase
sahilmgandhi	18:6a4db94011d3	25233	* \| \| \|This bit indicates the detection phase of external counting pin.
sahilmgandhi	18:6a4db94011d3	25234	* \| \| \|0 = A falling edge of external counting pin will be counted.
sahilmgandhi	18:6a4db94011d3	25235	* \| \| \|1 = A rising edge of external counting pin will be counted.
sahilmgandhi	18:6a4db94011d3	25236	* \|[1:2] \|CAPEDGE \|Timer External Pin Edge Detect
sahilmgandhi	18:6a4db94011d3	25237	* \| \| \|00 = A 1 to 0 transition on TMx_EXT (x= 0~3) pin will be detected.
sahilmgandhi	18:6a4db94011d3	25238	* \| \| \|01 = A 0 to 1 transition on TMx_EXT (x= 0~3) pin will be detected.
sahilmgandhi	18:6a4db94011d3	25239	* \| \| \|10 = Either 1 to 0 or 0 to 1 transition on TMx_EXT (x= 0~3) pin will be detected.
sahilmgandhi	18:6a4db94011d3	25240	* \| \| \|11 = Reserved.
sahilmgandhi	18:6a4db94011d3	25241	* \|[3] \|CAPEN \|Timer External Pin Enable
sahilmgandhi	18:6a4db94011d3	25242	* \| \| \|This bit enables the CAPFUNCS (TIMER_EXTCTL[4]) function on the TMx_EXT pin.
sahilmgandhi	18:6a4db94011d3	25243	* \| \| \|0 = CAPFUNCS function of TMx_EXT (x= 0~3) pin will be ignored.
sahilmgandhi	18:6a4db94011d3	25244	* \| \| \|1 = CAPFUNCS function of TMx_EXT (x= 0~3) pin is active.
sahilmgandhi	18:6a4db94011d3	25245	* \|[4] \|CAPFUNCS \|Timer External Reset Counter / Capture Mode Select
sahilmgandhi	18:6a4db94011d3	25246	* \| \| \|0 = Transition on TMx_EXT (x= 0~3) pin is using to save the 24-bit timer counter value.
sahilmgandhi	18:6a4db94011d3	25247	* \| \| \|(TIMER_CNT value) to timer capture value (TIMER_CAP value) if CAPIF (TIMER_EINTSTS[0]) is set to 1
sahilmgandhi	18:6a4db94011d3	25248	* \| \| \|1 = Transition on TMx_EXT (x= 0~3) pin is using to reset the 24-bit timer counter value.
sahilmgandhi	18:6a4db94011d3	25249	* \|[5] \|CAPIEN \|Timer External Interrupt Enable
sahilmgandhi	18:6a4db94011d3	25250	* \| \| \|0 = TMx_EXT (x= 0~3) pin detection Interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	25251	* \| \| \|1 = TMx_EXT (x= 0~3) pin detection Interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	25252	* \| \| \|CAPIEN is used to enable timer external interrupt.
sahilmgandhi	18:6a4db94011d3	25253	* \| \| \|If CAPIEN enabled, timer will rise an interrupt when CAPIF = 1.
sahilmgandhi	18:6a4db94011d3	25254	* \| \| \|For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the TEX pin will cause the CAPIF(TIMER_EINTSTS[0]) interrupt flag to be set then the interrupt signal is generated and sent to NVIC to inform CPU.
sahilmgandhi	18:6a4db94011d3	25255	* \|[6] \|CAPDBEN \|Timer External Capture Pin De-Bounce Enable
sahilmgandhi	18:6a4db94011d3	25256	* \| \| \|0 = TMx_EXT (x= 0~3) pin de-bounce Disabled.
sahilmgandhi	18:6a4db94011d3	25257	* \| \| \|1 = TMx_EXT (x= 0~3) pin de-bounce Enabled.
sahilmgandhi	18:6a4db94011d3	25258	* \| \| \|If this bit is enabled, the edge detection of TMx_EXT pin is detected with de-bounce circuit.
sahilmgandhi	18:6a4db94011d3	25259	* \|[7] \|ECNTDBEN \|Timer Counter Pin De-Bounce Enable
sahilmgandhi	18:6a4db94011d3	25260	* \| \| \|0 = TMx (x= 0~3) pin de-bounce Disabled.
sahilmgandhi	18:6a4db94011d3	25261	* \| \| \|1 = TMx (x= 0~3) pin de-bounce Enabled.
sahilmgandhi	18:6a4db94011d3	25262	* \| \| \|If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
sahilmgandhi	18:6a4db94011d3	25263	*/
sahilmgandhi	18:6a4db94011d3	25264	__IO uint32_t EXTCTL;
sahilmgandhi	18:6a4db94011d3	25265
sahilmgandhi	18:6a4db94011d3	25266	/**
sahilmgandhi	18:6a4db94011d3	25267	* EINTSTS
sahilmgandhi	18:6a4db94011d3	25268	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	25269	* Offset: 0x18 Timer External Interrupt Status Register
sahilmgandhi	18:6a4db94011d3	25270	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	25271	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	25272	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	25273	* \|[0] \|CAPIF \|Timer External Interrupt Flag
sahilmgandhi	18:6a4db94011d3	25274	* \| \| \|This bit indicates the timer external interrupt flag status.
sahilmgandhi	18:6a4db94011d3	25275	* \| \| \|When CAPEN (TIMER_EXTCTL[3]) bit is set, CAPFUNCS (TIMER_EXTCTL[4]) bit is 0, and a transition on TMx_EXT (x= 0~3) pin matched the CAPEDGE (TIMER_EXTCTL[2:1]) setting, this bit will set to 1 by hardware.
sahilmgandhi	18:6a4db94011d3	25276	* \| \| \|0 = TMx_EXT (x= 0~3) pin interrupt did not occur.
sahilmgandhi	18:6a4db94011d3	25277	* \| \| \|1 = TMx_EXT (x= 0~3) pin interrupt occurred.
sahilmgandhi	18:6a4db94011d3	25278	* \| \| \|Note: This bit is cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	25279	*/
sahilmgandhi	18:6a4db94011d3	25280	__IO uint32_t EINTSTS;
sahilmgandhi	18:6a4db94011d3	25281
sahilmgandhi	18:6a4db94011d3	25282	} TIMER_T;
sahilmgandhi	18:6a4db94011d3	25283
sahilmgandhi	18:6a4db94011d3	25284	/**
sahilmgandhi	18:6a4db94011d3	25285	@addtogroup TIMER_CONST TIMER Bit Field Definition
sahilmgandhi	18:6a4db94011d3	25286	Constant Definitions for TIMER Controller
sahilmgandhi	18:6a4db94011d3	25287	@{ */
sahilmgandhi	18:6a4db94011d3	25288
sahilmgandhi	18:6a4db94011d3	25289	#define TIMER_CTL_PSC_Pos (0) /!< TIMER CTL: PSC Position /
sahilmgandhi	18:6a4db94011d3	25290	#define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) /!< TIMER CTL: PSC Mask /
sahilmgandhi	18:6a4db94011d3	25291
sahilmgandhi	18:6a4db94011d3	25292	#define TIMER_CTL_CNTDATEN_Pos (16) /!< TIMER CTL: CNTDATEN Position /
sahilmgandhi	18:6a4db94011d3	25293	#define TIMER_CTL_CNTDATEN_Msk (0x1ul << TIMER_CTL_CNTDATEN_Pos) /!< TIMER CTL: CNTDATEN Mask /
sahilmgandhi	18:6a4db94011d3	25294
sahilmgandhi	18:6a4db94011d3	25295	#define TIMER_CTL_TOGDIS1_Pos (21) /!< TIMER CTL: TOGDIS1 Position /
sahilmgandhi	18:6a4db94011d3	25296	#define TIMER_CTL_TOGDIS1_Msk (0x1ul << TIMER_CTL_TOGDIS1_Pos) /!< TIMER CTL: TOGDIS1 Mask /
sahilmgandhi	18:6a4db94011d3	25297
sahilmgandhi	18:6a4db94011d3	25298	#define TIMER_CTL_TOGDIS2_Pos (22) /!< TIMER CTL: TOGDIS2 Position /
sahilmgandhi	18:6a4db94011d3	25299	#define TIMER_CTL_TOGDIS2_Msk (0x1ul << TIMER_CTL_TOGDIS2_Pos) /!< TIMER CTL: TOGDIS2 Mask /
sahilmgandhi	18:6a4db94011d3	25300
sahilmgandhi	18:6a4db94011d3	25301	#define TIMER_CTL_WKEN_Pos (23) /!< TIMER CTL: WKEN Position /
sahilmgandhi	18:6a4db94011d3	25302	#define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) /!< TIMER CTL: WKEN Mask /
sahilmgandhi	18:6a4db94011d3	25303
sahilmgandhi	18:6a4db94011d3	25304	#define TIMER_CTL_EXTCNTEN_Pos (24) /!< TIMER CTL: EXTCNTEN Position /
sahilmgandhi	18:6a4db94011d3	25305	#define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) /!< TIMER CTL: EXTCNTEN Mask /
sahilmgandhi	18:6a4db94011d3	25306
sahilmgandhi	18:6a4db94011d3	25307	#define TIMER_CTL_ACTSTS_Pos (25) /!< TIMER CTL: ACTSTS Position /
sahilmgandhi	18:6a4db94011d3	25308	#define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) /!< TIMER CTL: ACTSTS Mask /
sahilmgandhi	18:6a4db94011d3	25309
sahilmgandhi	18:6a4db94011d3	25310	#define TIMER_CTL_RSTCNT_Pos (26) /!< TIMER CTL: RSTCNT Position /
sahilmgandhi	18:6a4db94011d3	25311	#define TIMER_CTL_RSTCNT_Msk (0x1ul << TIMER_CTL_RSTCNT_Pos) /!< TIMER CTL: RSTCNT Mask /
sahilmgandhi	18:6a4db94011d3	25312
sahilmgandhi	18:6a4db94011d3	25313	#define TIMER_CTL_OPMODE_Pos (27) /!< TIMER CTL: OPMODE Position /
sahilmgandhi	18:6a4db94011d3	25314	#define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) /!< TIMER CTL: OPMODE Mask /
sahilmgandhi	18:6a4db94011d3	25315
sahilmgandhi	18:6a4db94011d3	25316	#define TIMER_CTL_INTEN_Pos (29) /!< TIMER CTL: INTEN Position /
sahilmgandhi	18:6a4db94011d3	25317	#define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) /!< TIMER CTL: INTEN Mask /
sahilmgandhi	18:6a4db94011d3	25318
sahilmgandhi	18:6a4db94011d3	25319	#define TIMER_CTL_CNTEN_Pos (30) /!< TIMER CTL: CNTEN Position /
sahilmgandhi	18:6a4db94011d3	25320	#define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) /!< TIMER CTL: CNTEN Mask /
sahilmgandhi	18:6a4db94011d3	25321
sahilmgandhi	18:6a4db94011d3	25322	#define TIMER_CTL_ICEDEBUG_Pos (31) /!< TIMER CTL: ICEDEBUG Position /
sahilmgandhi	18:6a4db94011d3	25323	#define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) /!< TIMER CTL: ICEDEBUG Mask /
sahilmgandhi	18:6a4db94011d3	25324
sahilmgandhi	18:6a4db94011d3	25325	#define TIMER_CMP_CMPDAT_Pos (0) /!< TIMER CMP: CMPDAT Position /
sahilmgandhi	18:6a4db94011d3	25326	#define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) /!< TIMER CMP: CMPDAT Mask /
sahilmgandhi	18:6a4db94011d3	25327
sahilmgandhi	18:6a4db94011d3	25328	#define TIMER_INTSTS_TIF_Pos (0) /!< TIMER INTSTS: TIF Position /
sahilmgandhi	18:6a4db94011d3	25329	#define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) /!< TIMER INTSTS: TIF Mask /
sahilmgandhi	18:6a4db94011d3	25330
sahilmgandhi	18:6a4db94011d3	25331	#define TIMER_INTSTS_TWKF_Pos (1) /!< TIMER INTSTS: TWKF Position /
sahilmgandhi	18:6a4db94011d3	25332	#define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) /!< TIMER INTSTS: TWKF Mask /
sahilmgandhi	18:6a4db94011d3	25333
sahilmgandhi	18:6a4db94011d3	25334	#define TIMER_CNT_TIMER_CNT_Pos (0) /!< TIMER CNT: TIMER_CNT Position /
sahilmgandhi	18:6a4db94011d3	25335	#define TIMER_CNT_TIMER_CNT_Msk (0xfffffful << TIMER_CNT_TIMER_CNT_Pos) /!< TIMER CNT: TIMER_CNT Mask /
sahilmgandhi	18:6a4db94011d3	25336
sahilmgandhi	18:6a4db94011d3	25337	#define TIMER_CAP_CAPDAT_Pos (0) /!< TIMER CAP: CAPDAT Position /
sahilmgandhi	18:6a4db94011d3	25338	#define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) /!< TIMER CAP: CAPDAT Mask /
sahilmgandhi	18:6a4db94011d3	25339
sahilmgandhi	18:6a4db94011d3	25340	#define TIMER_EXTCTL_CNTPHASE_Pos (0) /!< TIMER EXTCTL: CNTPHASE Position /
sahilmgandhi	18:6a4db94011d3	25341	#define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) /!< TIMER EXTCTL: CNTPHASE Mask /
sahilmgandhi	18:6a4db94011d3	25342
sahilmgandhi	18:6a4db94011d3	25343	#define TIMER_EXTCTL_CAPEDGE_Pos (1) /!< TIMER EXTCTL: CAPEDGE Position /
sahilmgandhi	18:6a4db94011d3	25344	#define TIMER_EXTCTL_CAPEDGE_Msk (0x3ul << TIMER_EXTCTL_CAPEDGE_Pos) /!< TIMER EXTCTL: CAPEDGE Mask /
sahilmgandhi	18:6a4db94011d3	25345
sahilmgandhi	18:6a4db94011d3	25346	#define TIMER_EXTCTL_CAPEN_Pos (3) /!< TIMER EXTCTL: CAPEN Position /
sahilmgandhi	18:6a4db94011d3	25347	#define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) /!< TIMER EXTCTL: CAPEN Mask /
sahilmgandhi	18:6a4db94011d3	25348
sahilmgandhi	18:6a4db94011d3	25349	#define TIMER_EXTCTL_CAPFUNCS_Pos (4) /!< TIMER EXTCTL: CAPFUNCS Position /
sahilmgandhi	18:6a4db94011d3	25350	#define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) /!< TIMER EXTCTL: CAPFUNCS Mask /
sahilmgandhi	18:6a4db94011d3	25351
sahilmgandhi	18:6a4db94011d3	25352	#define TIMER_EXTCTL_CAPIEN_Pos (5) /!< TIMER EXTCTL: CAPIEN Position /
sahilmgandhi	18:6a4db94011d3	25353	#define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) /!< TIMER EXTCTL: CAPIEN Mask /
sahilmgandhi	18:6a4db94011d3	25354
sahilmgandhi	18:6a4db94011d3	25355	#define TIMER_EXTCTL_CAPDBEN_Pos (6) /!< TIMER EXTCTL: CAPDBEN Position /
sahilmgandhi	18:6a4db94011d3	25356	#define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) /!< TIMER EXTCTL: CAPDBEN Mask /
sahilmgandhi	18:6a4db94011d3	25357
sahilmgandhi	18:6a4db94011d3	25358	#define TIMER_EXTCTL_ECNTDBEN_Pos (7) /!< TIMER EXTCTL: ECNTDBEN Position /
sahilmgandhi	18:6a4db94011d3	25359	#define TIMER_EXTCTL_ECNTDBEN_Msk (0x1ul << TIMER_EXTCTL_ECNTDBEN_Pos) /!< TIMER EXTCTL: ECNTDBEN Mask /
sahilmgandhi	18:6a4db94011d3	25360
sahilmgandhi	18:6a4db94011d3	25361	#define TIMER_EINTSTS_CAPIF_Pos (0) /!< TIMER EINTSTS: CAPIF Position /
sahilmgandhi	18:6a4db94011d3	25362	#define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /!< TIMER EINTSTS: CAPIF Mask /
sahilmgandhi	18:6a4db94011d3	25363
sahilmgandhi	18:6a4db94011d3	25364
sahilmgandhi	18:6a4db94011d3	25365	/*@}/ /* TIMER_CONST */
sahilmgandhi	18:6a4db94011d3	25366	/*@}/ /* end of TMR register group */
sahilmgandhi	18:6a4db94011d3	25367
sahilmgandhi	18:6a4db94011d3	25368
sahilmgandhi	18:6a4db94011d3	25369	/---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------/
sahilmgandhi	18:6a4db94011d3	25370	/**
sahilmgandhi	18:6a4db94011d3	25371	@addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART)
sahilmgandhi	18:6a4db94011d3	25372	Memory Mapped Structure for UART Controller
sahilmgandhi	18:6a4db94011d3	25373	@{ */
sahilmgandhi	18:6a4db94011d3	25374
sahilmgandhi	18:6a4db94011d3	25375	typedef struct {
sahilmgandhi	18:6a4db94011d3	25376
sahilmgandhi	18:6a4db94011d3	25377
sahilmgandhi	18:6a4db94011d3	25378	/**
sahilmgandhi	18:6a4db94011d3	25379	* DAT
sahilmgandhi	18:6a4db94011d3	25380	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	25381	* Offset: 0x00 UARTx Receive / Transmit Buffer Register
sahilmgandhi	18:6a4db94011d3	25382	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	25383	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	25384	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	25385	* \|[0:7] \|DAT \|Receiving/Transmit Buffer
sahilmgandhi	18:6a4db94011d3	25386	* \| \| \|Write Operation:
sahilmgandhi	18:6a4db94011d3	25387	* \| \| \|By writing one byte to this register, the data byte will be stored in transmitter FIFO. The
sahilmgandhi	18:6a4db94011d3	25388	* \| \| \|UART Controller will send out the data stored in transmitter FIFO top location through the
sahilmgandhi	18:6a4db94011d3	25389	* \| \| \|UART_TXD.
sahilmgandhi	18:6a4db94011d3	25390	* \| \| \|Read Operation:
sahilmgandhi	18:6a4db94011d3	25391	* \| \| \|By reading this register, the UART will return an 8-bit data received from receiving FIFO
sahilmgandhi	18:6a4db94011d3	25392	*/
sahilmgandhi	18:6a4db94011d3	25393	__IO uint32_t DAT;
sahilmgandhi	18:6a4db94011d3	25394
sahilmgandhi	18:6a4db94011d3	25395	/**
sahilmgandhi	18:6a4db94011d3	25396	* INTEN
sahilmgandhi	18:6a4db94011d3	25397	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	25398	* Offset: 0x04 UARTx Interrupt Enable Register
sahilmgandhi	18:6a4db94011d3	25399	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	25400	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	25401	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	25402	* \|[0] \|RDAIEN \|Receive Data Available Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	25403	* \| \| \|0 = INT_RDA Disabled.
sahilmgandhi	18:6a4db94011d3	25404	* \| \| \|1 = INT_RDA Enabled.
sahilmgandhi	18:6a4db94011d3	25405	* \|[1] \|THREIEN \|Transmit Holding Register Empty Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	25406	* \| \| \|0 = INT_THRE Disabled.
sahilmgandhi	18:6a4db94011d3	25407	* \| \| \|1 = INT_THRE Enabled.
sahilmgandhi	18:6a4db94011d3	25408	* \|[2] \|RLSIEN \|Receive Line Status Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	25409	* \| \| \|0 = INT_RLS Disabled.
sahilmgandhi	18:6a4db94011d3	25410	* \| \| \|1 = INT_RLS Enabled.
sahilmgandhi	18:6a4db94011d3	25411	* \|[3] \|MODEMIEN \|Modem Status Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	25412	* \| \| \|0 = INT_MODEM Disabled.
sahilmgandhi	18:6a4db94011d3	25413	* \| \| \|1 = INT_MODEM Enabled.
sahilmgandhi	18:6a4db94011d3	25414	* \|[4] \|RXTOIEN \|RX Time-Out Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	25415	* \| \| \|0 = NT_TOUT Disabled.
sahilmgandhi	18:6a4db94011d3	25416	* \| \| \|1 = INT_TOUT Enabled.
sahilmgandhi	18:6a4db94011d3	25417	* \|[5] \|BUFERRIEN \|Buffer Error Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	25418	* \| \| \|0 = INT_BUF_ERR Disabled.
sahilmgandhi	18:6a4db94011d3	25419	* \| \| \|1 = INT_BUF_ERR Enabled.
sahilmgandhi	18:6a4db94011d3	25420	* \|[6] \|WKCTSIEN \|UART Wake-Up Function Enable Control
sahilmgandhi	18:6a4db94011d3	25421	* \| \| \|0 = UART wake-up function Disabled.
sahilmgandhi	18:6a4db94011d3	25422	* \| \| \|1 = UART wake-up function Enabled when the chip is in Power-down mode, an external CTS change will wake up chip from Power-down mode.
sahilmgandhi	18:6a4db94011d3	25423	* \|[8] \|LINIEN \|LIN RX Break Field Detected Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	25424	* \| \| \|0 = Lin bus RX break filed interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	25425	* \| \| \|1 = Lin bus RX break filed interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	25426	* \| \| \|Note: This field is used for LIN function mode.
sahilmgandhi	18:6a4db94011d3	25427	* \|[11] \|TOCNTEN \|Time-Out Counter Enable Control
sahilmgandhi	18:6a4db94011d3	25428	* \| \| \|0 = Time-out counter Disabled.
sahilmgandhi	18:6a4db94011d3	25429	* \| \| \|1 = Time-out counter Enabled.
sahilmgandhi	18:6a4db94011d3	25430	* \|[12] \|ATORTSEN \|RTS Auto Flow Control Enable Control
sahilmgandhi	18:6a4db94011d3	25431	* \| \| \|0 = RTS auto flow control Disabled.
sahilmgandhi	18:6a4db94011d3	25432	* \| \| \|1 = RTS auto flow control Enabled.
sahilmgandhi	18:6a4db94011d3	25433	* \| \| \|When RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert RTS signal.
sahilmgandhi	18:6a4db94011d3	25434	* \|[13] \|ATOCTSEN \|CTS Auto Flow Control Enable Control
sahilmgandhi	18:6a4db94011d3	25435	* \| \| \|0 = CTS auto flow control Disabled.
sahilmgandhi	18:6a4db94011d3	25436	* \| \| \|1 = CTS auto flow control Enabled.
sahilmgandhi	18:6a4db94011d3	25437	* \| \| \|When CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
sahilmgandhi	18:6a4db94011d3	25438	* \|[14] \|TXPDMAEN \|TX DMA Enable Control
sahilmgandhi	18:6a4db94011d3	25439	* \| \| \|This bit can enable or disable TX DMA service.
sahilmgandhi	18:6a4db94011d3	25440	* \| \| \|0 = TX DMA Disabled.
sahilmgandhi	18:6a4db94011d3	25441	* \| \| \|1 = TX DMA Enabled.
sahilmgandhi	18:6a4db94011d3	25442	* \|[15] \|RXPDMAEN \|RX DMA Enable Control
sahilmgandhi	18:6a4db94011d3	25443	* \| \| \|This bit can enable or disable RX DMA service.
sahilmgandhi	18:6a4db94011d3	25444	* \| \| \|0 = RX DMA Disabled.
sahilmgandhi	18:6a4db94011d3	25445	* \| \| \|1 = RX DMA Enabled.
sahilmgandhi	18:6a4db94011d3	25446	*/
sahilmgandhi	18:6a4db94011d3	25447	__IO uint32_t INTEN;
sahilmgandhi	18:6a4db94011d3	25448
sahilmgandhi	18:6a4db94011d3	25449	/**
sahilmgandhi	18:6a4db94011d3	25450	* FIFO
sahilmgandhi	18:6a4db94011d3	25451	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	25452	* Offset: 0x08 UARTx FIFO Control Register
sahilmgandhi	18:6a4db94011d3	25453	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	25454	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	25455	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	25456	* \|[1] \|RXRST \|RX Field Software Reset
sahilmgandhi	18:6a4db94011d3	25457	* \| \| \|When RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.
sahilmgandhi	18:6a4db94011d3	25458	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	25459	* \| \| \|1 = Reset the RX internal state machine and pointers.
sahilmgandhi	18:6a4db94011d3	25460	* \| \| \|Note: This bit will be automatically cleared for at least 3 UART engine clock cycles.
sahilmgandhi	18:6a4db94011d3	25461	* \|[2] \|TXRST \|TX Field Software Reset
sahilmgandhi	18:6a4db94011d3	25462	* \| \| \|When TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
sahilmgandhi	18:6a4db94011d3	25463	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	25464	* \| \| \|1 = Reset the TX internal state machine and pointers.
sahilmgandhi	18:6a4db94011d3	25465	* \| \| \|Note: This bit will auto clear needs at least 3 UART engine clock cycles.
sahilmgandhi	18:6a4db94011d3	25466	* \|[4:7] \|RFITL \|RX FIFO Interrupt (INT_RDA) Trigger Level
sahilmgandhi	18:6a4db94011d3	25467	* \| \| \|When the number of bytes in the receive FIFO equals the RFITL, the RDAIF will be set (if RDAIEN (UART_INTEN [0]) is enabled, an interrupt will generated).
sahilmgandhi	18:6a4db94011d3	25468	* \| \| \|0000 = 1 byte
sahilmgandhi	18:6a4db94011d3	25469	* \| \| \|0001 = 4 bytes
sahilmgandhi	18:6a4db94011d3	25470	* \| \| \|0010 = 8 bytes
sahilmgandhi	18:6a4db94011d3	25471	* \| \| \|0011 = 14 bytes
sahilmgandhi	18:6a4db94011d3	25472	* \| \| \|0100 = 30/14 bytes (High-speed/Normal Speed)
sahilmgandhi	18:6a4db94011d3	25473	* \| \| \|0101 = 46/14 bytes (High-speed/Normal Speed)
sahilmgandhi	18:6a4db94011d3	25474	* \| \| \|0110 = 62/14 bytes (High-speed/Normal Speed)
sahilmgandhi	18:6a4db94011d3	25475	* \| \| \|others = 62/14 bytes (High-speed/Normal Speed)
sahilmgandhi	18:6a4db94011d3	25476	* \|[8] \|RXOFF \|Receiver Disable
sahilmgandhi	18:6a4db94011d3	25477	* \| \| \|The receiver is disabled or not.
sahilmgandhi	18:6a4db94011d3	25478	* \| \| \|0 = Receiver Enabled.
sahilmgandhi	18:6a4db94011d3	25479	* \| \| \|1 = Receiver Disabled.
sahilmgandhi	18:6a4db94011d3	25480	* \| \| \|Note: This field is used for RS-485 Normal Multi-drop mode.
sahilmgandhi	18:6a4db94011d3	25481	* \| \| \|It should be programmed before RS-485_NMM (UART_ALTCTL [8]) is programmed.
sahilmgandhi	18:6a4db94011d3	25482	* \|[16:19] \|RTSTRGLV \|RTS Trigger Level For Auto-Flow Control Use
sahilmgandhi	18:6a4db94011d3	25483	* \| \| \|0000 = 01 byte
sahilmgandhi	18:6a4db94011d3	25484	* \| \| \|0001 = 04 bytes
sahilmgandhi	18:6a4db94011d3	25485	* \| \| \|0010 = 08 bytes
sahilmgandhi	18:6a4db94011d3	25486	* \| \| \|0011 = 14 bytes
sahilmgandhi	18:6a4db94011d3	25487	* \| \| \|0100 = 30/14 bytes (High-speed/Normal Speed)
sahilmgandhi	18:6a4db94011d3	25488	* \| \| \|0101 = 46/14 bytes (High-speed/Normal Speed)
sahilmgandhi	18:6a4db94011d3	25489	* \| \| \|0110 = 62/14 bytes (High-speed/Normal Speed)
sahilmgandhi	18:6a4db94011d3	25490	* \| \| \|others = 62/14 bytes (High-speed/Normal Speed)
sahilmgandhi	18:6a4db94011d3	25491	* \| \| \|Note: This field is used for auto RTS flow control.
sahilmgandhi	18:6a4db94011d3	25492	*/
sahilmgandhi	18:6a4db94011d3	25493	__IO uint32_t FIFO;
sahilmgandhi	18:6a4db94011d3	25494
sahilmgandhi	18:6a4db94011d3	25495	/**
sahilmgandhi	18:6a4db94011d3	25496	* LINE
sahilmgandhi	18:6a4db94011d3	25497	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	25498	* Offset: 0x0C UARTx Line Control Register
sahilmgandhi	18:6a4db94011d3	25499	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	25500	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	25501	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	25502	* \|[0:1] \|WLS \|Word Length Selection
sahilmgandhi	18:6a4db94011d3	25503	* \| \| \|00 = 5-bit
sahilmgandhi	18:6a4db94011d3	25504	* \| \| \|01 = 6-bit
sahilmgandhi	18:6a4db94011d3	25505	* \| \| \|10 = 7-bit
sahilmgandhi	18:6a4db94011d3	25506	* \| \| \|11 = 8-bit
sahilmgandhi	18:6a4db94011d3	25507	* \|[2] \|NSB \|Number Of "STOP Bit"
sahilmgandhi	18:6a4db94011d3	25508	* \| \| \|0= One " STOP bit" is generated in the transmitted data.
sahilmgandhi	18:6a4db94011d3	25509	* \| \| \|1= One and a half " STOP bit" is generated in the transmitted data when 5-bit word length is selected.
sahilmgandhi	18:6a4db94011d3	25510	* \| \| \|Two "STOP bit" is generated when 6-, 7- and 8-bit word length is selected.
sahilmgandhi	18:6a4db94011d3	25511	* \|[3] \|PBE \|Parity Bit Enable Control
sahilmgandhi	18:6a4db94011d3	25512	* \| \| \|0 = No parity bit.
sahilmgandhi	18:6a4db94011d3	25513	* \| \| \|1 = Parity bit is generated on each outgoing character and is checked on each incoming data.
sahilmgandhi	18:6a4db94011d3	25514	* \|[4] \|EPE \|Even Parity Enable Control
sahilmgandhi	18:6a4db94011d3	25515	* \| \| \|0 = Odd number of logic 1's is transmitted and checked in each word.
sahilmgandhi	18:6a4db94011d3	25516	* \| \| \|1 = Even number of logic 1's is transmitted and checked in each word.
sahilmgandhi	18:6a4db94011d3	25517	* \| \| \|This bit is effective only when bit 3 (parity bit enable) is set.
sahilmgandhi	18:6a4db94011d3	25518	* \|[5] \|SPE \|Stick Parity Enable Control
sahilmgandhi	18:6a4db94011d3	25519	* \| \| \|0 = Stick parity Disabled.
sahilmgandhi	18:6a4db94011d3	25520	* \| \| \|1 = If bit 3 and 4 are logic 1, the parity bit is transmitted and checked as logic 0.
sahilmgandhi	18:6a4db94011d3	25521	* \| \| \|If bit 3 is 1 and bit 4 is 0 then the parity bit is transmitted and checked as 1.
sahilmgandhi	18:6a4db94011d3	25522	* \|[6] \|BCB \|Break Control
sahilmgandhi	18:6a4db94011d3	25523	* \| \| \|When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0).
sahilmgandhi	18:6a4db94011d3	25524	* \| \| \|This bit acts only on TX and has no effect on the transmitter logic.
sahilmgandhi	18:6a4db94011d3	25525	*/
sahilmgandhi	18:6a4db94011d3	25526	__IO uint32_t LINE;
sahilmgandhi	18:6a4db94011d3	25527
sahilmgandhi	18:6a4db94011d3	25528	/**
sahilmgandhi	18:6a4db94011d3	25529	* MODEM
sahilmgandhi	18:6a4db94011d3	25530	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	25531	* Offset: 0x10 UARTx Modem Control Register
sahilmgandhi	18:6a4db94011d3	25532	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	25533	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	25534	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	25535	* \|[1] \|RTS \|RTS (Request-To-Send) Signal
sahilmgandhi	18:6a4db94011d3	25536	* \| \| \|0 = Drive RTS pin to logic 1 (If the RTSACTLV
sahilmgandhi	18:6a4db94011d3	25537	* \| \| \|set to low level triggered).
sahilmgandhi	18:6a4db94011d3	25538	* \| \| \|1 = Drive RTS pin to logic 0 (If the RTSACTLV set to low level triggered).
sahilmgandhi	18:6a4db94011d3	25539	* \| \| \|0 = Drive RTS pin to logic 0 (If the RTSACTLV
sahilmgandhi	18:6a4db94011d3	25540	* \| \| \|set to high level triggered).
sahilmgandhi	18:6a4db94011d3	25541	* \| \| \|1 = Drive RTS pin to logic 1 (If the RTSACTLV set to high level triggered).
sahilmgandhi	18:6a4db94011d3	25542	* \|[9] \|RTSACTLV \|RTS Trigger Level
sahilmgandhi	18:6a4db94011d3	25543	* \| \| \|This bit can change the RTS trigger level.
sahilmgandhi	18:6a4db94011d3	25544	* \| \| \|0= Low level triggered.
sahilmgandhi	18:6a4db94011d3	25545	* \| \| \|1= High level triggered.
sahilmgandhi	18:6a4db94011d3	25546	* \|[13] \|RTSSTS \|RTS Pin State (Read Only)
sahilmgandhi	18:6a4db94011d3	25547	* \| \| \|This bit is the output pin status of RTS.
sahilmgandhi	18:6a4db94011d3	25548	*/
sahilmgandhi	18:6a4db94011d3	25549	__IO uint32_t MODEM;
sahilmgandhi	18:6a4db94011d3	25550
sahilmgandhi	18:6a4db94011d3	25551	/**
sahilmgandhi	18:6a4db94011d3	25552	* MODEMSTS
sahilmgandhi	18:6a4db94011d3	25553	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	25554	* Offset: 0x14 UARTx Modem Status Register
sahilmgandhi	18:6a4db94011d3	25555	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	25556	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	25557	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	25558	* \|[0] \|CTSDETF \|Detect CTS State Change Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	25559	* \| \| \|This bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.
sahilmgandhi	18:6a4db94011d3	25560	* \| \| \|Software can write 1 to clear this bit to 0
sahilmgandhi	18:6a4db94011d3	25561	* \|[4] \|CTSSTS \|CTS Pin Status (Read Only)
sahilmgandhi	18:6a4db94011d3	25562	* \| \| \|This bit is the pin status of CTS.
sahilmgandhi	18:6a4db94011d3	25563	* \|[8] \|CTSACTLV \|CTS Trigger Level
sahilmgandhi	18:6a4db94011d3	25564	* \| \| \|This bit can change the CTS trigger level.
sahilmgandhi	18:6a4db94011d3	25565	* \| \| \|0= Low level triggered.
sahilmgandhi	18:6a4db94011d3	25566	* \| \| \|1= High level triggered.
sahilmgandhi	18:6a4db94011d3	25567	*/
sahilmgandhi	18:6a4db94011d3	25568	__IO uint32_t MODEMSTS;
sahilmgandhi	18:6a4db94011d3	25569
sahilmgandhi	18:6a4db94011d3	25570	/**
sahilmgandhi	18:6a4db94011d3	25571	* FIFOSTS
sahilmgandhi	18:6a4db94011d3	25572	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	25573	* Offset: 0x18 UARTx FIFO Status Register
sahilmgandhi	18:6a4db94011d3	25574	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	25575	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	25576	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	25577	* \|[0] \|RXOVIF \|RX Overflow Error IF (Read Only)
sahilmgandhi	18:6a4db94011d3	25578	* \| \| \|This bit is set when RX FIFO overflow.
sahilmgandhi	18:6a4db94011d3	25579	* \| \| \|If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 64/16 bytes of UART0/UART1, this bit will be set.
sahilmgandhi	18:6a4db94011d3	25580	* \| \| \|Note: This bit is read only, but it can be cleared by writing '1' to it.
sahilmgandhi	18:6a4db94011d3	25581	* \|[2] \|SCERR \|Smart Card Over Error Retry Flag
sahilmgandhi	18:6a4db94011d3	25582	* \| \| \|It is set to 1 when transmitter re-transmits over the retry number (TXRTY (UART_SCCTL[6:4])) or the receiver transfer error retry over retry number (RXRTY (UART_SCCTL[2:0]))
sahilmgandhi	18:6a4db94011d3	25583	* \| \| \|0 = No any transmitter re-transmits over or receiver transfer error retry over.
sahilmgandhi	18:6a4db94011d3	25584	* \| \| \|1 = one of the transmitter re-transmits over active or receiver transfer error retry over active.
sahilmgandhi	18:6a4db94011d3	25585	* \| \| \|Note1: This field is used for SC function mode.
sahilmgandhi	18:6a4db94011d3	25586	* \| \| \|Note2: This bit is read only, but it can be cleared by writing '1' to it.
sahilmgandhi	18:6a4db94011d3	25587	* \|[3] \|ADDRDETF \|RS-485 Address Byte Detection Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	25588	* \| \| \|This bit is set to logic 1 and set RS-485_ADD_EN (UART_ALTCTL[15]) whenever in RS-485 mode the receiver detect any address byte received address byte character (bit9 = '1') bit, and it is reset whenever the CPU writes 1 to this bit.
sahilmgandhi	18:6a4db94011d3	25589	* \| \| \|Note1: This field is used for RS-485 function mode.
sahilmgandhi	18:6a4db94011d3	25590	* \| \| \|Note2: This bit is read only, but it can be cleared by writing '1' to it.
sahilmgandhi	18:6a4db94011d3	25591	* \|[4] \|PEF \|Parity Error Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	25592	* \| \| \|This bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU writes 1 to this bit.
sahilmgandhi	18:6a4db94011d3	25593	* \| \| \|Note: This bit is read only, but it can be cleared by writing '1' to it.
sahilmgandhi	18:6a4db94011d3	25594	* \|[5] \|FEF \|Framing Error Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	25595	* \| \| \|This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.
sahilmgandhi	18:6a4db94011d3	25596	* \| \| \|Note: This bit is read only, but it can be cleared by writing '1' to it.
sahilmgandhi	18:6a4db94011d3	25597	* \|[6] \|BIF \|Break Interrupt Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	25598	* \| \| \|This bit is set to a logic 1 whenever the received data input(RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.
sahilmgandhi	18:6a4db94011d3	25599	* \| \| \|Note: This bit is read only, but it can be cleared by writing '1' to it.
sahilmgandhi	18:6a4db94011d3	25600	* \|[8:13] \|RXPTR \|RX FIFO Pointer (Read Only)
sahilmgandhi	18:6a4db94011d3	25601	* \| \| \|This field indicates the RX FIFO Buffer Pointer.
sahilmgandhi	18:6a4db94011d3	25602	* \| \| \|When UART receives one byte from external device, RXPTR increases one.
sahilmgandhi	18:6a4db94011d3	25603	* \| \| \|When one byte of RX FIFO is read by CPU, RXPTR decreases one.
sahilmgandhi	18:6a4db94011d3	25604	* \|[14] \|RXEMPTY \|Receiver FIFO Empty (Read Only)
sahilmgandhi	18:6a4db94011d3	25605	* \| \| \|This bit initiate RX FIFO empty or not.
sahilmgandhi	18:6a4db94011d3	25606	* \| \| \|When the last byte of RX FIFO has been read by CPU, hardware sets this bit high.
sahilmgandhi	18:6a4db94011d3	25607	* \| \| \|It will be cleared when UART receives any new data.
sahilmgandhi	18:6a4db94011d3	25608	* \|[15] \|RXFULL \|Receiver FIFO Full (Read Only)
sahilmgandhi	18:6a4db94011d3	25609	* \| \| \|This bit initiates RX FIFO full or not.
sahilmgandhi	18:6a4db94011d3	25610	* \| \| \|This bit is set when RXPTR is equal to 64/16(UART0/UART1~5), otherwise is cleared by hardware.
sahilmgandhi	18:6a4db94011d3	25611	* \|[16:21] \|TXPTR \|TX FIFO Pointer (Read Only)
sahilmgandhi	18:6a4db94011d3	25612	* \| \| \|This field indicates the TX FIFO Buffer Pointer.
sahilmgandhi	18:6a4db94011d3	25613	* \| \| \|When CPU writes one byte into UART_DAT, TXPTR increases one.
sahilmgandhi	18:6a4db94011d3	25614	* \| \| \|When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
sahilmgandhi	18:6a4db94011d3	25615	* \|[22] \|TXEMPTY \|Transmitter FIFO Empty (Read Only)
sahilmgandhi	18:6a4db94011d3	25616	* \| \| \|This bit indicates TX FIFO empty or not.
sahilmgandhi	18:6a4db94011d3	25617	* \| \| \|When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high.
sahilmgandhi	18:6a4db94011d3	25618	* \| \| \|It will be cleared when writing data into DAT (TX FIFO not empty).
sahilmgandhi	18:6a4db94011d3	25619	* \|[23] \|TX_FULL \|Transmitter FIFO Full (Read Only)
sahilmgandhi	18:6a4db94011d3	25620	* \| \| \|This bit indicates TX FIFO full or not.
sahilmgandhi	18:6a4db94011d3	25621	* \| \| \|This bit is set when TXPTR is equal to 64/16(UART0/UART1~5), otherwise is cleared by hardware.
sahilmgandhi	18:6a4db94011d3	25622	* \|[24] \|TXOVIF \|TX Overflow Error Interrupt Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	25623	* \| \| \|If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to
sahilmgandhi	18:6a4db94011d3	25624	* \| \| \|logic 1.
sahilmgandhi	18:6a4db94011d3	25625	* \| \| \|Note: This bit is read only, but it can be cleared by writing '1' to it.
sahilmgandhi	18:6a4db94011d3	25626	* \|[28] \|TXEMPTYF \|Transmitter Empty Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	25627	* \| \| \|Bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.
sahilmgandhi	18:6a4db94011d3	25628	* \| \| \|Bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
sahilmgandhi	18:6a4db94011d3	25629	*/
sahilmgandhi	18:6a4db94011d3	25630	__IO uint32_t FIFOSTS;
sahilmgandhi	18:6a4db94011d3	25631
sahilmgandhi	18:6a4db94011d3	25632	/**
sahilmgandhi	18:6a4db94011d3	25633	* INTSTS
sahilmgandhi	18:6a4db94011d3	25634	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	25635	* Offset: 0x1C UARTx Interrupt Status Register
sahilmgandhi	18:6a4db94011d3	25636	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	25637	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	25638	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	25639	* \|[0] \|RDAIF \|Receive Data Available Interrupt Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	25640	* \| \| \|When the number of bytes in the RX FIFO equals the RFITL then the RDAIF will be set.
sahilmgandhi	18:6a4db94011d3	25641	* \| \| \|If RDAIEN bit (UART_INTEN[0]) is enabled, the RDA interrupt will be generated.
sahilmgandhi	18:6a4db94011d3	25642	* \| \| \|Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
sahilmgandhi	18:6a4db94011d3	25643	* \|[1] \|THREIF \|Transmit Holding Register Empty Interrupt Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	25644	* \| \| \|This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register.
sahilmgandhi	18:6a4db94011d3	25645	* \| \| \|If THREIEN bit (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.
sahilmgandhi	18:6a4db94011d3	25646	* \| \| \|Note: This bit is read only and it will be cleared when writing data into DAT (TX FIFO not empty).
sahilmgandhi	18:6a4db94011d3	25647	* \|[2] \|RLSIF \|Receive Line Interrupt Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	25648	* \| \| \|This bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set).
sahilmgandhi	18:6a4db94011d3	25649	* \| \| \|If RLSIEN bit (UART_INTEN[2]) is enabled, the RLS interrupt will be generated.
sahilmgandhi	18:6a4db94011d3	25650	* \| \| \|Note1: In RS-485 function mode, this field include receiver detect any address byte received address byte character (bit9 = '1') bit.
sahilmgandhi	18:6a4db94011d3	25651	* \| \| \|Note2: In SC function mode, this field includes error retry over flag .
sahilmgandhi	18:6a4db94011d3	25652	* \| \| \|Note3: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
sahilmgandhi	18:6a4db94011d3	25653	* \|[3] \|MODENIF \|MODEM Interrupt Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	25654	* \| \| \|This bit is set when the CTS pin has state change (CTSDETF=1).
sahilmgandhi	18:6a4db94011d3	25655	* \| \| \|If MODEMIEN bit (UART_INTEN[3]) is enabled, the Modem interrupt will be generated.
sahilmgandhi	18:6a4db94011d3	25656	* \| \| \|Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF.
sahilmgandhi	18:6a4db94011d3	25657	* \|[4] \|RXTOIF \|Time-Out Interrupt Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	25658	* \| \| \|This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC.
sahilmgandhi	18:6a4db94011d3	25659	* \| \| \|If TIME_OUT_IEN bit (UART_INTEN[11]) is enabled, the Time-out interrupt will be generated.
sahilmgandhi	18:6a4db94011d3	25660	* \| \| \|Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
sahilmgandhi	18:6a4db94011d3	25661	* \|[5] \|BUFERRIF \|Buffer Error Interrupt Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	25662	* \| \| \|This bit is set when the TX or RX FIFO overflows (TXOVIF or RXOVIF is set).
sahilmgandhi	18:6a4db94011d3	25663	* \| \| \|When BERRIF is set, the transfer maybe is not correct.
sahilmgandhi	18:6a4db94011d3	25664	* \| \| \|If BUFERRIEN bit (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated.
sahilmgandhi	18:6a4db94011d3	25665	* \| \| \|Note: This bit is cleared when both TXOVIF and RXOVIF are cleared.
sahilmgandhi	18:6a4db94011d3	25666	* \|[7] \|LIN_IF \|LIN Bus Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	25667	* \| \| \|This bit is set when LIN slave header detect (SLVHDETF=1), LIN break detect (BRKDETF=1), bit error detect (BITEF=1), LIN slave ID parity error (SLVIDPEF) or LIN slave header error detect (SLVHEF) If LIN_RX_BRK_ IEN bit (UART_INTEN[8]) is enabled the LIN interrupt will be generated.
sahilmgandhi	18:6a4db94011d3	25668	* \| \| \|Note: This bit is cleared when both SLVHDETF and LIN_BRDER_F and BITEF and LINS_IDPENR_F and SLVHEF are cleared
sahilmgandhi	18:6a4db94011d3	25669	* \|[8] \|RDAINT \|Receive Data Available Interrupt Indicator (Read Only)
sahilmgandhi	18:6a4db94011d3	25670	* \| \| \|This bit is set if RDAIEN and RDAIF are both set to 1.
sahilmgandhi	18:6a4db94011d3	25671	* \| \| \|0 = No RDA interrupt is generated.
sahilmgandhi	18:6a4db94011d3	25672	* \| \| \|1 = RDA interrupt is generated.
sahilmgandhi	18:6a4db94011d3	25673	* \|[9] \|THREINT \|Transmit Holding Register Empty Interrupt
sahilmgandhi	18:6a4db94011d3	25674	* \| \| \|Indicator (Read Only)
sahilmgandhi	18:6a4db94011d3	25675	* \| \| \|This bit is set if THREIEN and THREIF are both set to 1.
sahilmgandhi	18:6a4db94011d3	25676	* \| \| \|0 = No THRE interrupt is generated.
sahilmgandhi	18:6a4db94011d3	25677	* \| \| \|1 = THRE interrupt is generated.
sahilmgandhi	18:6a4db94011d3	25678	* \|[10] \|RLSINT \|Receive Line Status Interrupt Indicator (Read Only)
sahilmgandhi	18:6a4db94011d3	25679	* \| \| \|This bit is set if RLSIEN and RLSIF are both set to 1.
sahilmgandhi	18:6a4db94011d3	25680	* \| \| \|0 = No RLS interrupt is generated.
sahilmgandhi	18:6a4db94011d3	25681	* \| \| \|1 = RLS interrupt is generated.
sahilmgandhi	18:6a4db94011d3	25682	* \|[11] \|MODEMINT \|MODEM Status Interrupt Indicator (Read Only)
sahilmgandhi	18:6a4db94011d3	25683	* \| \| \|This bit is set if MODEMIEN and MODENIF are both set to 1.
sahilmgandhi	18:6a4db94011d3	25684	* \| \| \|0 = No Modem interrupt is generated.
sahilmgandhi	18:6a4db94011d3	25685	* \| \| \|1 = Modem interrupt is generated.
sahilmgandhi	18:6a4db94011d3	25686	* \|[12] \|RXTOINT \|Time-Out Interrupt Indicator (Read Only)
sahilmgandhi	18:6a4db94011d3	25687	* \| \| \|This bit is set if TOUT_IEN and RXTOIF are both set to 1.
sahilmgandhi	18:6a4db94011d3	25688	* \| \| \|0 = No Tout interrupt is generated.
sahilmgandhi	18:6a4db94011d3	25689	* \| \| \|1 = Tout interrupt is generated.
sahilmgandhi	18:6a4db94011d3	25690	* \|[13] \|BUFERRINT \|Buffer Error Interrupt Indicator (Read Only)
sahilmgandhi	18:6a4db94011d3	25691	* \| \| \|This bit is set if BUFERRIEN and BERRIF are both set to 1.
sahilmgandhi	18:6a4db94011d3	25692	* \| \| \|0 = No buffer error interrupt is generated.
sahilmgandhi	18:6a4db94011d3	25693	* \| \| \|1 = The buffer error interrupt is generated.
sahilmgandhi	18:6a4db94011d3	25694	* \|[15] \|LININT \|LIN Bus Interrupt Indicator (Read Only)
sahilmgandhi	18:6a4db94011d3	25695	* \| \| \|This bit is set if LIN_IEN and LIN_RX_BREAK_IF are both set to 1.
sahilmgandhi	18:6a4db94011d3	25696	* \| \| \|0 = No LIN RX Break interrupt is generated.
sahilmgandhi	18:6a4db94011d3	25697	* \| \| \|1 = LIN RX Break interrupt is generated.
sahilmgandhi	18:6a4db94011d3	25698	* \|[18] \|HWRLSIF \|In DMA Mode, Receive Line Status Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	25699	* \| \| \|This bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set).
sahilmgandhi	18:6a4db94011d3	25700	* \| \| \|If RLSIEN bit (UART_INTEN[2]) is enabled, the RLS interrupt will be generated.
sahilmgandhi	18:6a4db94011d3	25701	* \| \| \|Note1: In RS-485 function mode, this field includes receiver detect any address byte received address byte character (bit9 = '1') bit.
sahilmgandhi	18:6a4db94011d3	25702	* \| \| \|Note2: In SC function mode, this field includes error retry over flag.
sahilmgandhi	18:6a4db94011d3	25703	* \| \| \|Note3: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
sahilmgandhi	18:6a4db94011d3	25704	* \|[19] \|HWMODIF \|In DMA Mode, MODEM Interrupt Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	25705	* \| \| \|This bit is set when the CTS pin has state change (CTSDETF = 1).
sahilmgandhi	18:6a4db94011d3	25706	* \| \| \|If MODEMIEN (UART_INTEN[3]) is enabled, the Modem interrupt will be generated.
sahilmgandhi	18:6a4db94011d3	25707	* \| \| \|Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF.
sahilmgandhi	18:6a4db94011d3	25708	* \|[20] \|HWTOIF \|In DMA Mode, Time-Out Interrupt Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	25709	* \| \| \|This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC.
sahilmgandhi	18:6a4db94011d3	25710	* \| \| \|If TIME_OUT_IEN (UART_INTEN[11]) is enabled, the Time-out interrupt will be generated.
sahilmgandhi	18:6a4db94011d3	25711	* \| \| \|Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
sahilmgandhi	18:6a4db94011d3	25712	* \|[21] \|HWBUFEIF \|In DMA Mode, Buffer Error Interrupt Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	25713	* \| \| \|This bit is set when the TX or RX FIFO overflows (TXOVIF or RXOVIF is set).
sahilmgandhi	18:6a4db94011d3	25714	* \| \| \|When BERRIF is set, the transfer maybe is not correct.
sahilmgandhi	18:6a4db94011d3	25715	* \| \| \|If BUFERRIEN bit (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
sahilmgandhi	18:6a4db94011d3	25716	* \| \| \|Note: This bit is cleared when both TXOVIF and RXOVIF are cleared.
sahilmgandhi	18:6a4db94011d3	25717	* \|[26] \|HWRLSINT \|In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)
sahilmgandhi	18:6a4db94011d3	25718	* \| \| \|This bit is set if RLSIEN and HWRLSIF are both set to 1.
sahilmgandhi	18:6a4db94011d3	25719	* \| \| \|0 = No RLS interrupt is generated in DMA mode.
sahilmgandhi	18:6a4db94011d3	25720	* \| \| \|1 = RLS interrupt is generated in DMA mode.
sahilmgandhi	18:6a4db94011d3	25721	* \|[27] \|HWMODINT \|In DMA Mode, MODEM Status Interrupt Indicator (Read Only)
sahilmgandhi	18:6a4db94011d3	25722	* \| \| \|This bit is set if MODEMIEN and HWMODIF are both set to 1.
sahilmgandhi	18:6a4db94011d3	25723	* \| \| \|0 = No Modem interrupt is generated in DMA mode.
sahilmgandhi	18:6a4db94011d3	25724	* \| \| \|1 = Modem interrupt is generated in DMA mode.
sahilmgandhi	18:6a4db94011d3	25725	* \|[28] \|HWTOINT \|In DMA Mode, Time-Out Interrupt Indicator (Read Only)
sahilmgandhi	18:6a4db94011d3	25726	* \| \| \|This bit is set if TOUT_IEN and HWTOIF are both set to 1.
sahilmgandhi	18:6a4db94011d3	25727	* \| \| \|0 = No Tout interrupt is generated in DMA mode.
sahilmgandhi	18:6a4db94011d3	25728	* \| \| \|1 = Tout interrupt is generated in DMA mode.
sahilmgandhi	18:6a4db94011d3	25729	* \|[29] \|HWBUFEINT \|In DMA Mode, Buffer Error Interrupt Indicator (Read Only)
sahilmgandhi	18:6a4db94011d3	25730	* \| \| \|This bit is set if BUFERRIEN and HWBFERIF are both set to 1.
sahilmgandhi	18:6a4db94011d3	25731	* \| \| \|0 = No buffer error interrupt is generated in DMA mode.
sahilmgandhi	18:6a4db94011d3	25732	* \| \| \|1 = The buffer error interrupt is generated in DMA mode.
sahilmgandhi	18:6a4db94011d3	25733	*/
sahilmgandhi	18:6a4db94011d3	25734	__IO uint32_t INTSTS;
sahilmgandhi	18:6a4db94011d3	25735
sahilmgandhi	18:6a4db94011d3	25736	/**
sahilmgandhi	18:6a4db94011d3	25737	* TOUT
sahilmgandhi	18:6a4db94011d3	25738	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	25739	* Offset: 0x20 UARTx Time-out Register
sahilmgandhi	18:6a4db94011d3	25740	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	25741	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	25742	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	25743	* \|[0:7] \|TOIC \|Time-Out Interrupt Comparator
sahilmgandhi	18:6a4db94011d3	25744	* \| \| \|The time-out counter resets and starts counting (the counting clock = baud rate clock) whenever the RX FIFO receives a new data word.
sahilmgandhi	18:6a4db94011d3	25745	* \| \| \|Once the content of time-out counter (TOUT_CNT) is equal to that of time-out interrupt comparator (TOIC), a receiver time-out interrupt (INT_TOUT) is generated if RXTOIEN (UART_INTEN[4]).
sahilmgandhi	18:6a4db94011d3	25746	* \| \| \|A new incoming data word or RX FIFO empty clears INT_TOUT.
sahilmgandhi	18:6a4db94011d3	25747	* \| \| \|In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255.
sahilmgandhi	18:6a4db94011d3	25748	* \| \| \|So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer.
sahilmgandhi	18:6a4db94011d3	25749	* \|[8:15] \|DLY \|TX Delay Time Value
sahilmgandhi	18:6a4db94011d3	25750	* \| \| \|This field is use to programming the transfer delay time between the last stop bit and next start bit.
sahilmgandhi	18:6a4db94011d3	25751	* \| \| \|Note: The counter clock is baud rate clock
sahilmgandhi	18:6a4db94011d3	25752	*/
sahilmgandhi	18:6a4db94011d3	25753	__IO uint32_t TOUT;
sahilmgandhi	18:6a4db94011d3	25754
sahilmgandhi	18:6a4db94011d3	25755	/**
sahilmgandhi	18:6a4db94011d3	25756	* BAUD
sahilmgandhi	18:6a4db94011d3	25757	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	25758	* Offset: 0x24 UARTx Baud Rate Divisor Register
sahilmgandhi	18:6a4db94011d3	25759	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	25760	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	25761	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	25762	* \|[0:15] \|BRD \|Baud Rate Divider
sahilmgandhi	18:6a4db94011d3	25763	* \| \| \|The field indicated the baud rate divider
sahilmgandhi	18:6a4db94011d3	25764	* \|[24:27] \|EDIVM1 \|Divider X
sahilmgandhi	18:6a4db94011d3	25765	* \| \| \|The baud rate divider M = X+1.
sahilmgandhi	18:6a4db94011d3	25766	* \|[28] \|BAUDM0 \|Divider X Equal To 1
sahilmgandhi	18:6a4db94011d3	25767	* \| \| \|0 = Divider M = X (the equation of M = X+1, but EDIVM1 (UART_BAUD[27:24]) must >= 8).
sahilmgandhi	18:6a4db94011d3	25768	* \| \| \|1 = Divider M = 1 (the equation of M = 1, but BRD (UART_BAUD[15:0]) must >= 3).
sahilmgandhi	18:6a4db94011d3	25769	* \| \| \|Refer to the table below for more information.
sahilmgandhi	18:6a4db94011d3	25770	* \|[29] \|BAUDM1 \|Divider X Enable Control
sahilmgandhi	18:6a4db94011d3	25771	* \| \| \|The BRD = Baud Rate Divider, and the baud rate equation is
sahilmgandhi	18:6a4db94011d3	25772	* \| \| \|Baud Rate = Clock / [M * (BRD + 2)]; The default value of M is 16.
sahilmgandhi	18:6a4db94011d3	25773	* \| \| \|0 = Divider X Disabled (the equation of M = 16).
sahilmgandhi	18:6a4db94011d3	25774	* \| \| \|1 = Divider X Enabled (the equation of M = X+1, but EDIVM1 (UART_BAUD[27:24]) must >= 8).
sahilmgandhi	18:6a4db94011d3	25775	* \| \| \|Refer to the table below for more information.
sahilmgandhi	18:6a4db94011d3	25776	* \| \| \|Note: In IrDA mode, this bit must disable.
sahilmgandhi	18:6a4db94011d3	25777	*/
sahilmgandhi	18:6a4db94011d3	25778	__IO uint32_t BAUD;
sahilmgandhi	18:6a4db94011d3	25779
sahilmgandhi	18:6a4db94011d3	25780	/**
sahilmgandhi	18:6a4db94011d3	25781	* IRDA
sahilmgandhi	18:6a4db94011d3	25782	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	25783	* Offset: 0x28 UARTx IrDA Control Register
sahilmgandhi	18:6a4db94011d3	25784	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	25785	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	25786	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	25787	* \|[1] \|TXEN \|IrDA Receiver/Transmitter Selection Enable Bit
sahilmgandhi	18:6a4db94011d3	25788	* \| \| \|0 = IrDA receiver Enabled.
sahilmgandhi	18:6a4db94011d3	25789	* \| \| \|1 = IrDA transmitter Enabled.
sahilmgandhi	18:6a4db94011d3	25790	* \|[5] \|TXINV \|IrDA Inverse Transmitting Output Signal
sahilmgandhi	18:6a4db94011d3	25791	* \| \| \|0 = No inversion.
sahilmgandhi	18:6a4db94011d3	25792	* \| \| \|1 = Inverse TX output signal.
sahilmgandhi	18:6a4db94011d3	25793	* \|[6] \|RXINV \|IrDA Inverse Receive Input Signal
sahilmgandhi	18:6a4db94011d3	25794	* \| \| \|0 = No inversion.
sahilmgandhi	18:6a4db94011d3	25795	* \| \| \|1 = Inverse RX input signal.
sahilmgandhi	18:6a4db94011d3	25796	* \|[7] \|FIXPULSE \|Pulse width of TX is fixed 1.6us.
sahilmgandhi	18:6a4db94011d3	25797	*/
sahilmgandhi	18:6a4db94011d3	25798	__IO uint32_t IRDA;
sahilmgandhi	18:6a4db94011d3	25799
sahilmgandhi	18:6a4db94011d3	25800	/**
sahilmgandhi	18:6a4db94011d3	25801	* ALTCTL
sahilmgandhi	18:6a4db94011d3	25802	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	25803	* Offset: 0x2C UARTx Alternate Control/Status Register
sahilmgandhi	18:6a4db94011d3	25804	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	25805	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	25806	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	25807	* \|[0:3] \|BKFL \|LIN Break Field Length
sahilmgandhi	18:6a4db94011d3	25808	* \| \| \|This field indicates a 4-bit LIN TX break field count.
sahilmgandhi	18:6a4db94011d3	25809	* \| \| \|Note1: This break field length is BRKFL + 1.
sahilmgandhi	18:6a4db94011d3	25810	* \| \| \|Note2: According to LIN spec, the reset value is 0xC (break field length = 13).
sahilmgandhi	18:6a4db94011d3	25811	* \|[6] \|LINRXEN \|LIN RX Enable Control
sahilmgandhi	18:6a4db94011d3	25812	* \| \| \|0 = LIN RX mode Disabled.
sahilmgandhi	18:6a4db94011d3	25813	* \| \| \|1 = LIN RX mode Enabled.
sahilmgandhi	18:6a4db94011d3	25814	* \|[7] \|LINTXEN \|LIN TX Break Mode Enable Control
sahilmgandhi	18:6a4db94011d3	25815	* \| \| \|The LIN TX header can be "break field" or "break and sync field" or "break, sync and frame ID field" depending on the setting HSEL register.
sahilmgandhi	18:6a4db94011d3	25816	* \| \| \|0 = Send LIN TX header Disabled.
sahilmgandhi	18:6a4db94011d3	25817	* \| \| \|1 = Send LIN TX header Enabled.
sahilmgandhi	18:6a4db94011d3	25818	* \| \| \|Note: When transmitter header field (it may be "break" or "break + sync" or "break + sync + frame ID" selected by HSEL field) transfer operation finished, this bit will be cleared automatically.
sahilmgandhi	18:6a4db94011d3	25819	* \|[8] \|RS485NMM \|RS-485 Normal Multi-Drop Operation Mode (NMM)
sahilmgandhi	18:6a4db94011d3	25820	* \| \| \|0 = RS-485 Normal Multi-drop Operation Mode (NMM) Disabled.
sahilmgandhi	18:6a4db94011d3	25821	* \| \| \|1 = RS-485 Normal Multi-drop Operation Mode (NMM) Enabled.
sahilmgandhi	18:6a4db94011d3	25822	* \| \| \|Note: It can't be active with RS-485_AAD operation mode.
sahilmgandhi	18:6a4db94011d3	25823	* \|[9] \|RS485AAD \|RS-485 Auto Address Detection Operation Mode (AAD)
sahilmgandhi	18:6a4db94011d3	25824	* \| \| \|0 = RS-485 Auto Address Detection (AAD) Operation mode Disabled.
sahilmgandhi	18:6a4db94011d3	25825	* \| \| \|1 = RS-485 Auto Address Detection (AAD) Operation mode Enabled.
sahilmgandhi	18:6a4db94011d3	25826	* \| \| \|Note: It can't be active with RS-485_NMM operation mode.
sahilmgandhi	18:6a4db94011d3	25827	* \|[10] \|RS485AUD \|RS-485 Auto Direction Mode (AUD)
sahilmgandhi	18:6a4db94011d3	25828	* \| \| \|0 = RS-485 Auto Direction Operation (AUO) mode Disabled.
sahilmgandhi	18:6a4db94011d3	25829	* \| \| \|1 = RS-485 Auto Direction Operation (AUO) mode Enabled.
sahilmgandhi	18:6a4db94011d3	25830	* \| \| \|Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
sahilmgandhi	18:6a4db94011d3	25831	* \|[15] \|ADDRDEN \|RS-485 Address Detection Enable Control
sahilmgandhi	18:6a4db94011d3	25832	* \| \| \|This bit is use to enable RS-485 address detection mode.
sahilmgandhi	18:6a4db94011d3	25833	* \| \| \|0 = address detection mode Disabled.
sahilmgandhi	18:6a4db94011d3	25834	* \| \| \|1 = Address detection mode Enabled.
sahilmgandhi	18:6a4db94011d3	25835	* \| \| \|Note: This field is used for RS-485 any operation mode.
sahilmgandhi	18:6a4db94011d3	25836	* \|[24:31] \|ADDRMV \|Address Match Value
sahilmgandhi	18:6a4db94011d3	25837	* \| \| \|This field contains the RS-485 address match values.
sahilmgandhi	18:6a4db94011d3	25838	* \| \| \|Note: This field is used for RS-485 auto address detection mode.
sahilmgandhi	18:6a4db94011d3	25839	*/
sahilmgandhi	18:6a4db94011d3	25840	__IO uint32_t ALTCTL;
sahilmgandhi	18:6a4db94011d3	25841
sahilmgandhi	18:6a4db94011d3	25842	/**
sahilmgandhi	18:6a4db94011d3	25843	* FUNCSEL
sahilmgandhi	18:6a4db94011d3	25844	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	25845	* Offset: 0x30 UARTx Function Select Register
sahilmgandhi	18:6a4db94011d3	25846	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	25847	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	25848	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	25849	* \|[0:2] \|FUNCSEL \|Function Select Enable Control
sahilmgandhi	18:6a4db94011d3	25850	* \| \| \|000 = UART function.
sahilmgandhi	18:6a4db94011d3	25851	* \| \| \|001 = LIN function Enabled.
sahilmgandhi	18:6a4db94011d3	25852	* \| \| \|010 = IrDA function Enabled.
sahilmgandhi	18:6a4db94011d3	25853	* \| \| \|011 = RS-485 function Enabled.
sahilmgandhi	18:6a4db94011d3	25854	* \| \| \|100 = Smart-Card function Enabled.
sahilmgandhi	18:6a4db94011d3	25855	*/
sahilmgandhi	18:6a4db94011d3	25856	__IO uint32_t FUNCSEL;
sahilmgandhi	18:6a4db94011d3	25857
sahilmgandhi	18:6a4db94011d3	25858	/**
sahilmgandhi	18:6a4db94011d3	25859	* LINCTL
sahilmgandhi	18:6a4db94011d3	25860	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	25861	* Offset: 0x34 UARTx LIN Control Register
sahilmgandhi	18:6a4db94011d3	25862	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	25863	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	25864	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	25865	* \|[0] \|SLVEN \|LIN Slave Mode Enable Control
sahilmgandhi	18:6a4db94011d3	25866	* \| \| \|0 = LIN slave mode Disabled.
sahilmgandhi	18:6a4db94011d3	25867	* \| \| \|1 = LIN slave mode Enabled.
sahilmgandhi	18:6a4db94011d3	25868	* \|[1] \|SLVHDEN \|LIN Slave Header Detection Enable Control
sahilmgandhi	18:6a4db94011d3	25869	* \| \| \|0 = LIN slave header detection Disabled.
sahilmgandhi	18:6a4db94011d3	25870	* \| \| \|1 = LIN slave header detection Enabled.
sahilmgandhi	18:6a4db94011d3	25871	* \| \| \|Note1: This bit only valid in LIN slave mode (SLVEN = 1).
sahilmgandhi	18:6a4db94011d3	25872	* \| \| \|Note2: In LIN function mode, when header field (break + sync + frame ID) is detected, hardware will generate an interrupt to CPU (INT_LIN) and the SLVHDETF flag (UART_LINSTS[0]) will be asserted.
sahilmgandhi	18:6a4db94011d3	25873	* \|[2] \|SLVAREN \|LIN Slave Automatic Resynchronization Mode Enable Control
sahilmgandhi	18:6a4db94011d3	25874	* \| \| \|0 = LIN automatic resynchronization Disabled.
sahilmgandhi	18:6a4db94011d3	25875	* \| \| \|1 = LIN automatic resynchronization Enabled.
sahilmgandhi	18:6a4db94011d3	25876	* \| \| \|Note1: This bit only valid in LIN slave mode (SLVEN = 1).
sahilmgandhi	18:6a4db94011d3	25877	* \| \| \|Note2: When operating in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1).
sahilmgandhi	18:6a4db94011d3	25878	* \| \| \|Note3: The control and interactions of this field are explained in 6.31.5.3.
sahilmgandhi	18:6a4db94011d3	25879	* \|[3] \|SLVDUEN \|LIN Slave Divider Update Method Enable Control
sahilmgandhi	18:6a4db94011d3	25880	* \| \| \|0 = UART_BAUD is updated as soon as UART_BAUD is writing by software (if no automatic resynchronization update occurs at the same time).
sahilmgandhi	18:6a4db94011d3	25881	* \| \| \|1 = UART_BAUD is updated at the next received character.
sahilmgandhi	18:6a4db94011d3	25882	* \| \| \|User must set the bit before checksum reception.
sahilmgandhi	18:6a4db94011d3	25883	* \| \| \|Note1: This bit only valid in LIN slave mode (SLVEN = 1).
sahilmgandhi	18:6a4db94011d3	25884	* \| \| \|Note2: This bit is used for LIN slave automatic resynchronization mode (for non-automatic resynchronization mode, this bit should be kept cleared).
sahilmgandhi	18:6a4db94011d3	25885	* \| \| \|Note3: The control and interactions of this field are explained in 6.31.5.3.
sahilmgandhi	18:6a4db94011d3	25886	* \|[4] \|MUTE \|LIN Mute Mode Enable Control
sahilmgandhi	18:6a4db94011d3	25887	* \| \| \|0 = LIN mute mode. Disabled
sahilmgandhi	18:6a4db94011d3	25888	* \| \| \|1 = LIN mute mode Enabled.
sahilmgandhi	18:6a4db94011d3	25889	* \| \| \|Note: The wake-up condition from mute mode and each control and interactions of this field are explained in 6.31.5.3.
sahilmgandhi	18:6a4db94011d3	25890	* \|[8] \|SENDH \|LIN TX Send Header Enable Control
sahilmgandhi	18:6a4db94011d3	25891	* \| \| \|The LIN TX header can be "break field" or "break and sync field" or "break, sync and frame ID field" depending on the setting HSEL register.
sahilmgandhi	18:6a4db94011d3	25892	* \| \| \|0 = Send LIN TX header Disabled.
sahilmgandhi	18:6a4db94011d3	25893	* \| \| \|1 = Send LIN TX header Enabled.
sahilmgandhi	18:6a4db94011d3	25894	* \| \| \|Note: When transmitter header field (it may be "break" or "break + sync" or "break + sync + frame ID" selected by HSEL field) transfer operation finished, this bit will be cleared automatically.
sahilmgandhi	18:6a4db94011d3	25895	* \|[9] \|IDPEN \|LIN ID Parity Enable Control
sahilmgandhi	18:6a4db94011d3	25896	* \| \| \|0 = LIN frame ID parity Disabled.
sahilmgandhi	18:6a4db94011d3	25897	* \| \| \|1 = LIN frame ID parity Enabled.
sahilmgandhi	18:6a4db94011d3	25898	* \| \| \|Note1: This bit can be used for LIN master to sending header field (SENDH = 1 and HSEL = 2'b10) or be used for enable LIN slave received frame ID parity checked.
sahilmgandhi	18:6a4db94011d3	25899	* \| \| \|Note2: This bit is only used when operation header transmitter is in HSEL = 2'b10.
sahilmgandhi	18:6a4db94011d3	25900	* \|[10] \|BRKDETEN \|LIN Break Detection Enable Control
sahilmgandhi	18:6a4db94011d3	25901	* \| \| \|When detect great than 11/10 bits are detected as 0, and are followed by a delimiter character, the BRKDETF flag (UART_LINSTS[8]) at the end of break field.
sahilmgandhi	18:6a4db94011d3	25902	* \| \| \|If the LINIEN bit (UART_INTEN[8]) = 1, an interrupt will be generated.
sahilmgandhi	18:6a4db94011d3	25903	* \| \| \|0 = LIN break detection Disabled.
sahilmgandhi	18:6a4db94011d3	25904	* \| \| \|1 = LIN break detection Enabled.
sahilmgandhi	18:6a4db94011d3	25905	* \|[11] \|RXOFF \|If the receiver is be enabled (RXOFF = 0), all received byte data will be accepted and stored in the RX-FIFO, and if the receiver is disabled (RXOFF = 1), all received byte data will be ignore.
sahilmgandhi	18:6a4db94011d3	25906	* \| \| \|0 = Bit error detection function Disabled.
sahilmgandhi	18:6a4db94011d3	25907	* \| \| \|1 = Bit error detection Enabled.
sahilmgandhi	18:6a4db94011d3	25908	* \| \| \|Note: This bit is only valid when operating in LIN function mode (UART_FUNCSEL = 2'b01).
sahilmgandhi	18:6a4db94011d3	25909	* \|[12] \|BITERREN \|Bit Error Detect Enable Control
sahilmgandhi	18:6a4db94011d3	25910	* \| \| \|0 = Bit error detection function Disabled.
sahilmgandhi	18:6a4db94011d3	25911	* \| \| \|1 = Bit error detection Enabled.
sahilmgandhi	18:6a4db94011d3	25912	* \| \| \|Note: In LIN function mode, when occur bit error, hardware will generate an interrupt to CPU (INT_LIN) and the BITEF (UART_LINSTS[9]) flag will be asserted.
sahilmgandhi	18:6a4db94011d3	25913	* \|[16:19] \|BRKFL \|LIN Break Field Length
sahilmgandhi	18:6a4db94011d3	25914	* \| \| \|This field indicates a 4-bit LIN TX break field count.
sahilmgandhi	18:6a4db94011d3	25915	* \| \| \|Note1: These registers are shadow registers of LIN_BKFL (UART_ALTCTL[3:0]), User can read/write it by setting LIN_BKFL (UART_ALTCTL[3:0]) or LIN_BKFL (UART_LINCTL[19:16]).
sahilmgandhi	18:6a4db94011d3	25916	* \| \| \|Note2: This break field length is BRKFL + 1.
sahilmgandhi	18:6a4db94011d3	25917	* \| \| \|Note3: According to LIN spec, the reset value is 0XC (break field length = 13).
sahilmgandhi	18:6a4db94011d3	25918	* \|[20:21] \|BSL \|LIN Break/Sync Delimiter Length
sahilmgandhi	18:6a4db94011d3	25919	* \| \| \|00 = LIN break/sync delimiter length is 1 bit time.
sahilmgandhi	18:6a4db94011d3	25920	* \| \| \|10 = The LIN break/sync delimiter length is 2 bit time.
sahilmgandhi	18:6a4db94011d3	25921	* \| \| \|10 = The LIN break/sync delimiter length is 3 bit time.
sahilmgandhi	18:6a4db94011d3	25922	* \| \| \|11 = The LIN break/sync delimiter length is 4 bit time.
sahilmgandhi	18:6a4db94011d3	25923	* \| \| \|Note: This bit used for LIN master to send header field.
sahilmgandhi	18:6a4db94011d3	25924	* \|[22:23] \|HSEL \|LIN Header Selection
sahilmgandhi	18:6a4db94011d3	25925	* \| \| \|00 = LIN header includes "break field".
sahilmgandhi	18:6a4db94011d3	25926	* \| \| \|01 = LIN header includes "break field" and "sync field".
sahilmgandhi	18:6a4db94011d3	25927	* \| \| \|10 = LIN header includes "break field", "sync field" and "frame ID field".
sahilmgandhi	18:6a4db94011d3	25928	* \| \| \|11 = LIN header includes "break field", "sync field" and "frame ID field", but this mode only supports Receiver mode, not support transmitter mode.
sahilmgandhi	18:6a4db94011d3	25929	* \| \| \|This mode difference with mode "10"; in this mode, the receiver will receive ID field (not check the PID (UART_LINCTL[31:24]) register) and when received ID field the SLVHDETF will be asserted (if SLVHDEN (UART_LINCTL[1]) be set).
sahilmgandhi	18:6a4db94011d3	25930	* \| \| \|Note: This bit is used to master mode for LIN to sending header field (SENDH = 1) or used to slave to indicates wake-up condition from mute mode (MUTE).
sahilmgandhi	18:6a4db94011d3	25931	* \|[24:31] \|PID \|This Field Contains The LIN Frame ID Value In LIN Function Mode, The Frame ID Parity Can Be Generated By Software Or Hardware Depending On UART_LINCTL [IDPEN]
sahilmgandhi	18:6a4db94011d3	25932	* \| \| \|If the parity generated by hardware (IDPEN (UART_LINCTL[9]) = 1), user fill ID0~ID5, hardware will calculi P0 and P1, otherwise user must filled frame ID and parity in this field.
sahilmgandhi	18:6a4db94011d3	25933	* \| \| \|Note1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first)
sahilmgandhi	18:6a4db94011d3	25934	* \| \| \|Note2: This field can be used for LIN Master mode or Slave mode.
sahilmgandhi	18:6a4db94011d3	25935	*/
sahilmgandhi	18:6a4db94011d3	25936	__IO uint32_t LINCTL;
sahilmgandhi	18:6a4db94011d3	25937
sahilmgandhi	18:6a4db94011d3	25938	/**
sahilmgandhi	18:6a4db94011d3	25939	* LINSTS
sahilmgandhi	18:6a4db94011d3	25940	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	25941	* Offset: 0x38 UARTx LIN Status Register
sahilmgandhi	18:6a4db94011d3	25942	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	25943	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	25944	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	25945	* \|[0] \|SLVHDETF \|LIN Slave Header Detection Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	25946	* \| \| \|This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	25947	* \| \| \|0 = LIN header not detected.
sahilmgandhi	18:6a4db94011d3	25948	* \| \| \|1 = LIN header detected (break + sync + frame ID).
sahilmgandhi	18:6a4db94011d3	25949	* \| \| \|Note1: This bit is read only, but can be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	25950	* \| \| \|Note2: This bit is only valid in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1) and LIN slave header detection function (SLVHDEN (UART_LINCTL[1])) is enabled.
sahilmgandhi	18:6a4db94011d3	25951	* \| \| \|Note3: When the ID parity check (IDPEN (UART_LINCTL[9]) = 1) is enabled, if hardware detect complete harder ("break + sync + frame ID"), the LINS_HEDT_F (UART_LINCTL[1]) will be set no matter the frame ID is corrected or not.
sahilmgandhi	18:6a4db94011d3	25952	* \|[1] \|SLVHEF \|LIN Slave Header Error Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	25953	* \| \| \|This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	25954	* \| \| \|The header include "break delimiter is too short", "frame error in sync field or Identifier field", "sync field data is not 0x55 without automatic resynchronization mode", "sync field deviation error with automatic resynchronization mode", "sync field measure time-out with automatic resynchronization mode" and "LIN header reception time-out".
sahilmgandhi	18:6a4db94011d3	25955	* \| \| \|0 = LIN header error not detected.
sahilmgandhi	18:6a4db94011d3	25956	* \| \| \|1 = LIN header error detected.
sahilmgandhi	18:6a4db94011d3	25957	* \| \| \|Note1: This bit is read only, but can be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	25958	* \| \| \|Note2: This bit is only valid in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1) and LIN slave header detection function (SLVHDEN (UART_LINCTL[1])) is enabled.
sahilmgandhi	18:6a4db94011d3	25959	* \|[2] \|SLVIDPEF \|LIN Slave ID Parity Error Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	25960	* \| \| \|This bit is set by hardware when receipted frame ID parity is not correct.
sahilmgandhi	18:6a4db94011d3	25961	* \| \| \|0 = no active.
sahilmgandhi	18:6a4db94011d3	25962	* \| \| \|1 = Receipted frame ID parity is not correct.
sahilmgandhi	18:6a4db94011d3	25963	* \| \| \|Note1: This bit is read only, but can be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	25964	* \| \| \|Note2: This bit is only valid in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1) and LIN frame ID parity check function (IDPEN (UART_LINCTL[9])) is enabled.
sahilmgandhi	18:6a4db94011d3	25965	* \|[3] \|SLVSYNCF \|LIN Slave Sync Field
sahilmgandhi	18:6a4db94011d3	25966	* \| \| \|This bit indicates that the LIN sync field is being analyzed.
sahilmgandhi	18:6a4db94011d3	25967	* \| \| \|When the receiver header have some error been detect, user must to reset the internal circuit to re-search new frame header by writing 1 to this bit.
sahilmgandhi	18:6a4db94011d3	25968	* \| \| \|0 = The current character is not at LIN sync state.
sahilmgandhi	18:6a4db94011d3	25969	* \| \| \|1 = The current character is at LIN sync state.
sahilmgandhi	18:6a4db94011d3	25970	* \| \| \|Note1: This bit only valid in LIN Slave mode (SLVEN = 1).
sahilmgandhi	18:6a4db94011d3	25971	* \| \| \|Note2: This bit is read only, but can be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	25972	* \| \| \|Note3: When user writing 1 to it, hardware will reload the initial baud-rate and re-search new frame header, the control and interactions of this field are explained in 6.31.5.3.
sahilmgandhi	18:6a4db94011d3	25973	* \|[8] \|BRKDETF \|LIN Break Detection Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	25974	* \| \| \|This bit is set by hardware when a break is detected and be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	25975	* \| \| \|0 = LIN break not detected.
sahilmgandhi	18:6a4db94011d3	25976	* \| \| \|1 = LIN break detected.
sahilmgandhi	18:6a4db94011d3	25977	* \| \| \|Note1: This bit is read only, but can be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	25978	* \| \| \|Note2: This bit is only valid when enable LIN break detection function (BRKDETEN (UART_LINCTL[10]))
sahilmgandhi	18:6a4db94011d3	25979	* \|[9] \|BITEF \|Bit Error Detect Status Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	25980	* \| \| \|At TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BITEF will be set.
sahilmgandhi	18:6a4db94011d3	25981	* \| \| \|When occur bit error, hardware will generate an interrupt to CPU (INT_LIN).
sahilmgandhi	18:6a4db94011d3	25982	* \| \| \|Note1: This bit is read only, but can be cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	25983	* \| \| \|Note2: This bit is only valid when enable bit error detection function (BRKL (UART_LINCTL[12]) == 1).
sahilmgandhi	18:6a4db94011d3	25984	*/
sahilmgandhi	18:6a4db94011d3	25985	__IO uint32_t LINSTS;
sahilmgandhi	18:6a4db94011d3	25986
sahilmgandhi	18:6a4db94011d3	25987	/**
sahilmgandhi	18:6a4db94011d3	25988	* LINDEBUG
sahilmgandhi	18:6a4db94011d3	25989	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	25990	* Offset: 0x3C UARTx LIN Debug Register
sahilmgandhi	18:6a4db94011d3	25991	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	25992	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	25993	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	25994	* \|[0] \|DEVERRF \|LIN Header Deviation Error (Read Only)
sahilmgandhi	18:6a4db94011d3	25995	* \| \| \|This bit indicates the header error cause by the sync field deviation error or sync field measure time-out with automatic resynchronization mode.
sahilmgandhi	18:6a4db94011d3	25996	* \|[1] \|TOF \|LIN Header Time-Out (Read Only)
sahilmgandhi	18:6a4db94011d3	25997	* \| \| \|This bit indicates the header error cause by the LIN header reception time-out.
sahilmgandhi	18:6a4db94011d3	25998	* \|[2] \|FRAMEERRF \|LIN Header Frame Error Flag (Read Only)
sahilmgandhi	18:6a4db94011d3	25999	* \| \| \|This bit indicates the header error cause by break delimiter is too short or frame error in sync field or Identifier field.
sahilmgandhi	18:6a4db94011d3	26000	* \|[3] \|SYNCERRF \|LIN Header Sync Data Error (Read Only)
sahilmgandhi	18:6a4db94011d3	26001	* \| \| \|This bit indicates the header error cause by the LIN received sync data is not 0x55.
sahilmgandhi	18:6a4db94011d3	26002	*/
sahilmgandhi	18:6a4db94011d3	26003	__IO uint32_t LINDEBUG;
sahilmgandhi	18:6a4db94011d3	26004
sahilmgandhi	18:6a4db94011d3	26005
sahilmgandhi	18:6a4db94011d3	26006	} UART_T;
sahilmgandhi	18:6a4db94011d3	26007
sahilmgandhi	18:6a4db94011d3	26008	/**
sahilmgandhi	18:6a4db94011d3	26009	@addtogroup UART_CONST UART Bit Field Definition
sahilmgandhi	18:6a4db94011d3	26010	Constant Definitions for UART Controller
sahilmgandhi	18:6a4db94011d3	26011	@{ */
sahilmgandhi	18:6a4db94011d3	26012
sahilmgandhi	18:6a4db94011d3	26013	#define UART_DAT_DAT_Pos (0) /!< UART DAT: DAT Position /
sahilmgandhi	18:6a4db94011d3	26014	#define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) /!< UART DAT: DAT Mask /
sahilmgandhi	18:6a4db94011d3	26015
sahilmgandhi	18:6a4db94011d3	26016	#define UART_INTEN_RDAIEN_Pos (0) /!< UART INTEN: RDAIEN Position /
sahilmgandhi	18:6a4db94011d3	26017	#define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) /!< UART INTEN: RDAIEN Mask /
sahilmgandhi	18:6a4db94011d3	26018
sahilmgandhi	18:6a4db94011d3	26019	#define UART_INTEN_THREIEN_Pos (1) /!< UART INTEN: THREIEN Position /
sahilmgandhi	18:6a4db94011d3	26020	#define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) /!< UART INTEN: THREIEN Mask /
sahilmgandhi	18:6a4db94011d3	26021
sahilmgandhi	18:6a4db94011d3	26022	#define UART_INTEN_RLSIEN_Pos (2) /!< UART INTEN: RLSIEN Position /
sahilmgandhi	18:6a4db94011d3	26023	#define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) /!< UART INTEN: RLSIEN Mask /
sahilmgandhi	18:6a4db94011d3	26024
sahilmgandhi	18:6a4db94011d3	26025	#define UART_INTEN_MODEMIEN_Pos (3) /!< UART INTEN: MODEMIEN Position /
sahilmgandhi	18:6a4db94011d3	26026	#define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) /!< UART INTEN: MODEMIEN Mask /
sahilmgandhi	18:6a4db94011d3	26027
sahilmgandhi	18:6a4db94011d3	26028	#define UART_INTEN_RXTOIEN_Pos (4) /!< UART INTEN: RXTOIEN Position /
sahilmgandhi	18:6a4db94011d3	26029	#define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) /!< UART INTEN: RXTOIEN Mask /
sahilmgandhi	18:6a4db94011d3	26030
sahilmgandhi	18:6a4db94011d3	26031	#define UART_INTEN_BUFERRIEN_Pos (5) /!< UART INTEN: BUFERRIEN Position /
sahilmgandhi	18:6a4db94011d3	26032	#define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos) /!< UART INTEN: BUFERRIEN Mask /
sahilmgandhi	18:6a4db94011d3	26033
sahilmgandhi	18:6a4db94011d3	26034	#define UART_INTEN_WKCTSIEN_Pos (6) /!< UART INTEN: WKCTSIEN Position /
sahilmgandhi	18:6a4db94011d3	26035	#define UART_INTEN_WKCTSIEN_Msk (0x1ul << UART_INTEN_WKCTSIEN_Pos) /!< UART INTEN: WKCTSIEN Mask /
sahilmgandhi	18:6a4db94011d3	26036
sahilmgandhi	18:6a4db94011d3	26037	#define UART_INTEN_LINIEN_Pos (8) /!< UART INTEN: LINIEN Position /
sahilmgandhi	18:6a4db94011d3	26038	#define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos) /!< UART INTEN: LINIEN Mask /
sahilmgandhi	18:6a4db94011d3	26039
sahilmgandhi	18:6a4db94011d3	26040	#define UART_INTEN_TOCNTEN_Pos (11) /!< UART INTEN: TOCNTEN Position /
sahilmgandhi	18:6a4db94011d3	26041	#define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos) /!< UART INTEN: TOCNTEN Mask /
sahilmgandhi	18:6a4db94011d3	26042
sahilmgandhi	18:6a4db94011d3	26043	#define UART_INTEN_ATORTSEN_Pos (12) /!< UART INTEN: ATORTSEN Position /
sahilmgandhi	18:6a4db94011d3	26044	#define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos) /!< UART INTEN: ATORTSEN Mask /
sahilmgandhi	18:6a4db94011d3	26045
sahilmgandhi	18:6a4db94011d3	26046	#define UART_INTEN_ATOCTSEN_Pos (13) /!< UART INTEN: ATOCTSEN Position /
sahilmgandhi	18:6a4db94011d3	26047	#define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos) /!< UART INTEN: ATOCTSEN Mask /
sahilmgandhi	18:6a4db94011d3	26048
sahilmgandhi	18:6a4db94011d3	26049	#define UART_INTEN_TXPDMAEN_Pos (14) /!< UART INTEN: TXPDMAEN Position /
sahilmgandhi	18:6a4db94011d3	26050	#define UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos) /!< UART INTEN: TXPDMAEN Mask /
sahilmgandhi	18:6a4db94011d3	26051
sahilmgandhi	18:6a4db94011d3	26052	#define UART_INTEN_RXPDMAEN_Pos (15) /!< UART INTEN: RXPDMAEN Position /
sahilmgandhi	18:6a4db94011d3	26053	#define UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos) /!< UART INTEN: RXPDMAEN Mask /
sahilmgandhi	18:6a4db94011d3	26054
sahilmgandhi	18:6a4db94011d3	26055	#define UART_FIFO_RXRST_Pos (1) /!< UART FIFO: RXRST Position /
sahilmgandhi	18:6a4db94011d3	26056	#define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos) /!< UART FIFO: RXRST Mask /
sahilmgandhi	18:6a4db94011d3	26057
sahilmgandhi	18:6a4db94011d3	26058	#define UART_FIFO_TXRST_Pos (2) /!< UART FIFO: TXRST Position /
sahilmgandhi	18:6a4db94011d3	26059	#define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos) /!< UART FIFO: TXRST Mask /
sahilmgandhi	18:6a4db94011d3	26060
sahilmgandhi	18:6a4db94011d3	26061	#define UART_FIFO_RFITL_Pos (4) /!< UART FIFO: RFITL Position /
sahilmgandhi	18:6a4db94011d3	26062	#define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos) /!< UART FIFO: RFITL Mask /
sahilmgandhi	18:6a4db94011d3	26063
sahilmgandhi	18:6a4db94011d3	26064	#define UART_FIFO_RXOFF_Pos (8) /!< UART FIFO: RXOFF Position /
sahilmgandhi	18:6a4db94011d3	26065	#define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos) /!< UART FIFO: RXOFF Mask /
sahilmgandhi	18:6a4db94011d3	26066
sahilmgandhi	18:6a4db94011d3	26067	#define UART_FIFO_RTSTRGLV_Pos (16) /!< UART FIFO: RTSTRGLV Position /
sahilmgandhi	18:6a4db94011d3	26068	#define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos) /!< UART FIFO: RTSTRGLV Mask /
sahilmgandhi	18:6a4db94011d3	26069
sahilmgandhi	18:6a4db94011d3	26070	#define UART_LINE_WLS_Pos (0) /!< UART LINE: WLS Position /
sahilmgandhi	18:6a4db94011d3	26071	#define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) /!< UART LINE: WLS Mask /
sahilmgandhi	18:6a4db94011d3	26072
sahilmgandhi	18:6a4db94011d3	26073	#define UART_LINE_NSB_Pos (2) /!< UART LINE: NSB Position /
sahilmgandhi	18:6a4db94011d3	26074	#define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) /!< UART LINE: NSB Mask /
sahilmgandhi	18:6a4db94011d3	26075
sahilmgandhi	18:6a4db94011d3	26076	#define UART_LINE_PBE_Pos (3) /!< UART LINE: PBE Position /
sahilmgandhi	18:6a4db94011d3	26077	#define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) /!< UART LINE: PBE Mask /
sahilmgandhi	18:6a4db94011d3	26078
sahilmgandhi	18:6a4db94011d3	26079	#define UART_LINE_EPE_Pos (4) /!< UART LINE: EPE Position /
sahilmgandhi	18:6a4db94011d3	26080	#define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) /!< UART LINE: EPE Mask /
sahilmgandhi	18:6a4db94011d3	26081
sahilmgandhi	18:6a4db94011d3	26082	#define UART_LINE_SPE_Pos (5) /!< UART LINE: SPE Position /
sahilmgandhi	18:6a4db94011d3	26083	#define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) /!< UART LINE: SPE Mask /
sahilmgandhi	18:6a4db94011d3	26084
sahilmgandhi	18:6a4db94011d3	26085	#define UART_LINE_BCB_Pos (6) /!< UART LINE: BCB Position /
sahilmgandhi	18:6a4db94011d3	26086	#define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) /!< UART LINE: BCB Mask /
sahilmgandhi	18:6a4db94011d3	26087
sahilmgandhi	18:6a4db94011d3	26088	#define UART_MODEM_RTS_Pos (1) /!< UART MODEM: RTS Position /
sahilmgandhi	18:6a4db94011d3	26089	#define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos) /!< UART MODEM: RTS Mask /
sahilmgandhi	18:6a4db94011d3	26090
sahilmgandhi	18:6a4db94011d3	26091	#define UART_MODEM_RTSACTLV_Pos (9) /!< UART MODEM: RTSACTLV Position /
sahilmgandhi	18:6a4db94011d3	26092	#define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) /!< UART MODEM: RTSACTLV Mask /
sahilmgandhi	18:6a4db94011d3	26093
sahilmgandhi	18:6a4db94011d3	26094	#define UART_MODEM_RTSSTS_Pos (13) /!< UART MODEM: RTSSTS Position /
sahilmgandhi	18:6a4db94011d3	26095	#define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) /!< UART MODEM: RTSSTS Mask /
sahilmgandhi	18:6a4db94011d3	26096
sahilmgandhi	18:6a4db94011d3	26097	#define UART_MODEMSTS_CTSDETF_Pos (0) /!< UART MODEMSTS: CTSDETF Position /
sahilmgandhi	18:6a4db94011d3	26098	#define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos) /!< UART MODEMSTS: CTSDETF Mask /
sahilmgandhi	18:6a4db94011d3	26099
sahilmgandhi	18:6a4db94011d3	26100	#define UART_MODEMSTS_CTSSTS_Pos (4) /!< UART MODEMSTS: CTSSTS Position /
sahilmgandhi	18:6a4db94011d3	26101	#define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos) /!< UART MODEMSTS: CTSSTS Mask /
sahilmgandhi	18:6a4db94011d3	26102
sahilmgandhi	18:6a4db94011d3	26103	#define UART_MODEMSTS_CTSACTLV_Pos (8) /!< UART MODEMSTS: CTSACTLV Position /
sahilmgandhi	18:6a4db94011d3	26104	#define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos) /!< UART MODEMSTS: CTSACTLV Mask /
sahilmgandhi	18:6a4db94011d3	26105
sahilmgandhi	18:6a4db94011d3	26106	#define UART_FIFOSTS_RXOVIF_Pos (0) /!< UART FIFOSTS: RXOVIF Position /
sahilmgandhi	18:6a4db94011d3	26107	#define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) /!< UART FIFOSTS: RXOVIF Mask /
sahilmgandhi	18:6a4db94011d3	26108
sahilmgandhi	18:6a4db94011d3	26109	#define UART_FIFOSTS_SCERR_Pos (2) /!< UART FIFOSTS: SCERR Position /
sahilmgandhi	18:6a4db94011d3	26110	#define UART_FIFOSTS_SCERR_Msk (0x1ul << UART_FIFOSTS_SCERR_Pos) /!< UART FIFOSTS: SCERR Mask /
sahilmgandhi	18:6a4db94011d3	26111
sahilmgandhi	18:6a4db94011d3	26112	#define UART_FIFOSTS_ADDRDETF_Pos (3) /!< UART FIFOSTS: ADDRDETF Position /
sahilmgandhi	18:6a4db94011d3	26113	#define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos) /!< UART FIFOSTS: ADDRDETF Mask /
sahilmgandhi	18:6a4db94011d3	26114
sahilmgandhi	18:6a4db94011d3	26115	#define UART_FIFOSTS_PEF_Pos (4) /!< UART FIFOSTS: PEF Position /
sahilmgandhi	18:6a4db94011d3	26116	#define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) /!< UART FIFOSTS: PEF Mask /
sahilmgandhi	18:6a4db94011d3	26117
sahilmgandhi	18:6a4db94011d3	26118	#define UART_FIFOSTS_FEF_Pos (5) /!< UART FIFOSTS: FEF Position /
sahilmgandhi	18:6a4db94011d3	26119	#define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) /!< UART FIFOSTS: FEF Mask /
sahilmgandhi	18:6a4db94011d3	26120
sahilmgandhi	18:6a4db94011d3	26121	#define UART_FIFOSTS_BIF_Pos (6) /!< UART FIFOSTS: BIF Position /
sahilmgandhi	18:6a4db94011d3	26122	#define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) /!< UART FIFOSTS: BIF Mask /
sahilmgandhi	18:6a4db94011d3	26123
sahilmgandhi	18:6a4db94011d3	26124	#define UART_FIFOSTS_RXPTR_Pos (8) /!< UART FIFOSTS: RXPTR Position /
sahilmgandhi	18:6a4db94011d3	26125	#define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos) /!< UART FIFOSTS: RXPTR Mask /
sahilmgandhi	18:6a4db94011d3	26126
sahilmgandhi	18:6a4db94011d3	26127	#define UART_FIFOSTS_RXEMPTY_Pos (14) /!< UART FIFOSTS: RXEMPTY Position /
sahilmgandhi	18:6a4db94011d3	26128	#define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) /!< UART FIFOSTS: RXEMPTY Mask /
sahilmgandhi	18:6a4db94011d3	26129
sahilmgandhi	18:6a4db94011d3	26130	#define UART_FIFOSTS_RXFULL_Pos (15) /!< UART FIFOSTS: RXFULL Position /
sahilmgandhi	18:6a4db94011d3	26131	#define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) /!< UART FIFOSTS: RXFULL Mask /
sahilmgandhi	18:6a4db94011d3	26132
sahilmgandhi	18:6a4db94011d3	26133	#define UART_FIFOSTS_TXPTR_Pos (16) /!< UART FIFOSTS: TXPTR Position /
sahilmgandhi	18:6a4db94011d3	26134	#define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos) /!< UART FIFOSTS: TXPTR Mask /
sahilmgandhi	18:6a4db94011d3	26135
sahilmgandhi	18:6a4db94011d3	26136	#define UART_FIFOSTS_TXEMPTY_Pos (22) /!< UART FIFOSTS: TXEMPTY Position /
sahilmgandhi	18:6a4db94011d3	26137	#define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) /!< UART FIFOSTS: TXEMPTY Mask /
sahilmgandhi	18:6a4db94011d3	26138
sahilmgandhi	18:6a4db94011d3	26139	#define UART_FIFOSTS_TXFULL_Pos (23) /!< UART FIFOSTS: TXFULL Position /
sahilmgandhi	18:6a4db94011d3	26140	#define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) /!< UART FIFOSTS: TXFULL Mask /
sahilmgandhi	18:6a4db94011d3	26141
sahilmgandhi	18:6a4db94011d3	26142	#define UART_FIFOSTS_TXOVIF_Pos (24) /!< UART FIFOSTS: TXOVIF Position /
sahilmgandhi	18:6a4db94011d3	26143	#define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) /!< UART FIFOSTS: TXOVIF Mask /
sahilmgandhi	18:6a4db94011d3	26144
sahilmgandhi	18:6a4db94011d3	26145	#define UART_FIFOSTS_TXEMPTYF_Pos (28) /!< UART FIFOSTS: TXEMPTYF Position /
sahilmgandhi	18:6a4db94011d3	26146	#define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos) /!< UART FIFOSTS: TXEMPTYF Mask /
sahilmgandhi	18:6a4db94011d3	26147
sahilmgandhi	18:6a4db94011d3	26148	#define UART_INTSTS_RDAIF_Pos (0) /!< UART INTSTS: RDAIF Position /
sahilmgandhi	18:6a4db94011d3	26149	#define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) /!< UART INTSTS: RDAIF Mask /
sahilmgandhi	18:6a4db94011d3	26150
sahilmgandhi	18:6a4db94011d3	26151	#define UART_INTSTS_THREIF_Pos (1) /!< UART INTSTS: THREIF Position /
sahilmgandhi	18:6a4db94011d3	26152	#define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) /!< UART INTSTS: THREIF Mask /
sahilmgandhi	18:6a4db94011d3	26153
sahilmgandhi	18:6a4db94011d3	26154	#define UART_INTSTS_RLSIF_Pos (2) /!< UART INTSTS: RLSIF Position /
sahilmgandhi	18:6a4db94011d3	26155	#define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) /!< UART INTSTS: RLSIF Mask /
sahilmgandhi	18:6a4db94011d3	26156
sahilmgandhi	18:6a4db94011d3	26157	#define UART_INTSTS_MODENIF_Pos (3) /!< UART INTSTS: MODENIF Position /
sahilmgandhi	18:6a4db94011d3	26158	#define UART_INTSTS_MODENIF_Msk (0x1ul << UART_INTSTS_MODENIF_Pos) /!< UART INTSTS: MODENIF Mask /
sahilmgandhi	18:6a4db94011d3	26159
sahilmgandhi	18:6a4db94011d3	26160	#define UART_INTSTS_RXTOIF_Pos (4) /!< UART INTSTS: RXTOIF Position /
sahilmgandhi	18:6a4db94011d3	26161	#define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) /!< UART INTSTS: RXTOIF Mask /
sahilmgandhi	18:6a4db94011d3	26162
sahilmgandhi	18:6a4db94011d3	26163	#define UART_INTSTS_BUFERRIF_Pos (5) /!< UART INTSTS: BUFERRIF Position /
sahilmgandhi	18:6a4db94011d3	26164	#define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos) /!< UART INTSTS: BUFERRIF Mask /
sahilmgandhi	18:6a4db94011d3	26165
sahilmgandhi	18:6a4db94011d3	26166	#define UART_INTSTS_LINIF_Pos (7) /!< UART INTSTS: LINIF Position /
sahilmgandhi	18:6a4db94011d3	26167	#define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos) /!< UART INTSTS: LINIF Mask /
sahilmgandhi	18:6a4db94011d3	26168
sahilmgandhi	18:6a4db94011d3	26169	#define UART_INTSTS_RDAINT_Pos (8) /!< UART INTSTS: RDAINT Position /
sahilmgandhi	18:6a4db94011d3	26170	#define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos) /!< UART INTSTS: RDAINT Mask /
sahilmgandhi	18:6a4db94011d3	26171
sahilmgandhi	18:6a4db94011d3	26172	#define UART_INTSTS_THREINT_Pos (9) /!< UART INTSTS: THERINT Position /
sahilmgandhi	18:6a4db94011d3	26173	#define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos) /!< UART INTSTS: THERINT Mask /
sahilmgandhi	18:6a4db94011d3	26174
sahilmgandhi	18:6a4db94011d3	26175	#define UART_INTSTS_RLSINT_Pos (10) /!< UART INTSTS: RLSINT Position /
sahilmgandhi	18:6a4db94011d3	26176	#define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos) /!< UART INTSTS: RLSINT Mask /
sahilmgandhi	18:6a4db94011d3	26177
sahilmgandhi	18:6a4db94011d3	26178	#define UART_INTSTS_MODEMINT_Pos (11) /!< UART INTSTS: MODEMINT Position /
sahilmgandhi	18:6a4db94011d3	26179	#define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos) /!< UART INTSTS: MODEMINT Mask /
sahilmgandhi	18:6a4db94011d3	26180
sahilmgandhi	18:6a4db94011d3	26181	#define UART_INTSTS_RXTOINT_Pos (12) /!< UART INTSTS: RXTOINT Position /
sahilmgandhi	18:6a4db94011d3	26182	#define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos) /!< UART INTSTS: RXTOINT Mask /
sahilmgandhi	18:6a4db94011d3	26183
sahilmgandhi	18:6a4db94011d3	26184	#define UART_INTSTS_BUFERRINT_Pos (13) /!< UART INTSTS: BUFERRINT Position /
sahilmgandhi	18:6a4db94011d3	26185	#define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos) /!< UART INTSTS: BUFERRINT Mask /
sahilmgandhi	18:6a4db94011d3	26186
sahilmgandhi	18:6a4db94011d3	26187	#define UART_INTSTS_LININT_Pos (15) /!< UART INTSTS: LININT Position /
sahilmgandhi	18:6a4db94011d3	26188	#define UART_INTSTS_LININT_Msk (0x1ul << UART_INTSTS_LININT_Pos) /!< UART INTSTS: LININT Mask /
sahilmgandhi	18:6a4db94011d3	26189
sahilmgandhi	18:6a4db94011d3	26190	#define UART_INTSTS_HWRLSIF_Pos (18) /!< UART INTSTS: HWRLSIF Position /
sahilmgandhi	18:6a4db94011d3	26191	#define UART_INTSTS_HWRLSIF_Msk (0x1ul << UART_INTSTS_HWRLSIF_Pos) /!< UART INTSTS: HWRLSIF Mask /
sahilmgandhi	18:6a4db94011d3	26192
sahilmgandhi	18:6a4db94011d3	26193	#define UART_INTSTS_HWMODIF_Pos (19) /!< UART INTSTS: HWMODIF Position /
sahilmgandhi	18:6a4db94011d3	26194	#define UART_INTSTS_HWMODIF_Msk (0x1ul << UART_INTSTS_HWMODIF_Pos) /!< UART INTSTS: HWMODIF Mask /
sahilmgandhi	18:6a4db94011d3	26195
sahilmgandhi	18:6a4db94011d3	26196	#define UART_INTSTS_HWTOIF_Pos (20) /!< UART INTSTS: HWTOIF Position /
sahilmgandhi	18:6a4db94011d3	26197	#define UART_INTSTS_HWTOIF_Msk (0x1ul << UART_INTSTS_HWTOIF_Pos) /!< UART INTSTS: HWTOIF Mask /
sahilmgandhi	18:6a4db94011d3	26198
sahilmgandhi	18:6a4db94011d3	26199	#define UART_INTSTS_HWBUFEIF_Pos (21) /!< UART INTSTS: HWBUFEIF Position /
sahilmgandhi	18:6a4db94011d3	26200	#define UART_INTSTS_HWBUFEIF_Msk (0x1ul << UART_INTSTS_HWBUFEIF_Pos) /!< UART INTSTS: HWBUFEIF Mask /
sahilmgandhi	18:6a4db94011d3	26201
sahilmgandhi	18:6a4db94011d3	26202	#define UART_INTSTS_HWRLSINT_Pos (26) /!< UART INTSTS: HWRLSINT Position /
sahilmgandhi	18:6a4db94011d3	26203	#define UART_INTSTS_HWRLSINT_Msk (0x1ul << UART_INTSTS_HWRLSINT_Pos) /!< UART INTSTS: HWRLSINT Mask /
sahilmgandhi	18:6a4db94011d3	26204
sahilmgandhi	18:6a4db94011d3	26205	#define UART_INTSTS_HWMODINT_Pos (27) /!< UART INTSTS: HWMODINT Position /
sahilmgandhi	18:6a4db94011d3	26206	#define UART_INTSTS_HWMODINT_Msk (0x1ul << UART_INTSTS_HWMODINT_Pos) /!< UART INTSTS: HWMODINT Mask /
sahilmgandhi	18:6a4db94011d3	26207
sahilmgandhi	18:6a4db94011d3	26208	#define UART_INTSTS_HWTOINT_Pos (28) /!< UART INTSTS: HWTOINT Position /
sahilmgandhi	18:6a4db94011d3	26209	#define UART_INTSTS_HWTOINT_Msk (0x1ul << UART_INTSTS_HWTOINT_Pos) /!< UART INTSTS: HWTOINT Mask /
sahilmgandhi	18:6a4db94011d3	26210
sahilmgandhi	18:6a4db94011d3	26211	#define UART_INTSTS_HWBUFEINT_Pos (29) /!< UART INTSTS: HWBUFEINT Position /
sahilmgandhi	18:6a4db94011d3	26212	#define UART_INTSTS_HWBUFEINT_Msk (0x1ul << UART_INTSTS_HWBUFEINT_Pos) /!< UART INTSTS: HWBUFEINT Mask /
sahilmgandhi	18:6a4db94011d3	26213
sahilmgandhi	18:6a4db94011d3	26214	#define UART_TOUT_TOIC_Pos (0) /!< UART TOUT: TOIC Position /
sahilmgandhi	18:6a4db94011d3	26215	#define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos) /!< UART TOUT: TOIC Mask /
sahilmgandhi	18:6a4db94011d3	26216
sahilmgandhi	18:6a4db94011d3	26217	#define UART_TOUT_DLY_Pos (8) /!< UART TOUT: DLY Position /
sahilmgandhi	18:6a4db94011d3	26218	#define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) /!< UART TOUT: DLY Mask /
sahilmgandhi	18:6a4db94011d3	26219
sahilmgandhi	18:6a4db94011d3	26220	#define UART_BAUD_BRD_Pos (0) /!< UART BAUD: BRD Position /
sahilmgandhi	18:6a4db94011d3	26221	#define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) /!< UART BAUD: BRD Mask /
sahilmgandhi	18:6a4db94011d3	26222
sahilmgandhi	18:6a4db94011d3	26223	#define UART_BAUD_EDIVM1_Pos (24) /!< UART BAUD: EDIVM1 Position /
sahilmgandhi	18:6a4db94011d3	26224	#define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos) /!< UART BAUD: EDIVM1 Mask /
sahilmgandhi	18:6a4db94011d3	26225
sahilmgandhi	18:6a4db94011d3	26226	#define UART_BAUD_BAUDM0_Pos (28) /!< UART BAUD: BAUDM0 Position /
sahilmgandhi	18:6a4db94011d3	26227	#define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos) /!< UART BAUD: BAUDM0 Mask /
sahilmgandhi	18:6a4db94011d3	26228
sahilmgandhi	18:6a4db94011d3	26229	#define UART_BAUD_BAUDM1_Pos (29) /!< UART BAUD: BAUDM1 Position /
sahilmgandhi	18:6a4db94011d3	26230	#define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos) /!< UART BAUD: BAUDM1 Mask /
sahilmgandhi	18:6a4db94011d3	26231
sahilmgandhi	18:6a4db94011d3	26232	#define UART_IRDA_TXEN_Pos (1) /!< UART IRDA: TXEN Position /
sahilmgandhi	18:6a4db94011d3	26233	#define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) /!< UART IRDA: TXEN Mask /
sahilmgandhi	18:6a4db94011d3	26234
sahilmgandhi	18:6a4db94011d3	26235	#define UART_IRDA_TXINV_Pos (5) /!< UART IRDA: TXINV Position /
sahilmgandhi	18:6a4db94011d3	26236	#define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) /!< UART IRDA: TXINV Mask /
sahilmgandhi	18:6a4db94011d3	26237
sahilmgandhi	18:6a4db94011d3	26238	#define UART_IRDA_RXINV_Pos (6) /!< UART IRDA: RXINV Position /
sahilmgandhi	18:6a4db94011d3	26239	#define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) /!< UART IRDA: RXINV Mask /
sahilmgandhi	18:6a4db94011d3	26240
sahilmgandhi	18:6a4db94011d3	26241	#define UART_IRDA_FIXPULSE_Pos (7) /!< UART IRDA: FIXPULSE Position /
sahilmgandhi	18:6a4db94011d3	26242	#define UART_IRDA_FIXPULSE_Msk (0x1ul << UART_IRDA_FIXPULSE_Pos) /!< UART IRDA: FIXPULSE Mask /
sahilmgandhi	18:6a4db94011d3	26243
sahilmgandhi	18:6a4db94011d3	26244	#define UART_ALTCTL_BKFL_Pos (0) /!< UART ALTCTL: BKFL Position /
sahilmgandhi	18:6a4db94011d3	26245	#define UART_ALTCTL_BKFL_Msk (0xful << UART_ALTCTL_BKFL_Pos) /!< UART ALTCTL: BKFL Mask /
sahilmgandhi	18:6a4db94011d3	26246
sahilmgandhi	18:6a4db94011d3	26247	#define UART_ALTCTL_LINRXEN_Pos (6) /!< UART ALTCTL: LINRXEN Position /
sahilmgandhi	18:6a4db94011d3	26248	#define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos) /!< UART ALTCTL: LINRXEN Mask /
sahilmgandhi	18:6a4db94011d3	26249
sahilmgandhi	18:6a4db94011d3	26250	#define UART_ALTCTL_LINTXEN_Pos (7) /!< UART ALTCTL: LINTXEN Position /
sahilmgandhi	18:6a4db94011d3	26251	#define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos) /!< UART ALTCTL: LINTXEN Mask /
sahilmgandhi	18:6a4db94011d3	26252
sahilmgandhi	18:6a4db94011d3	26253	#define UART_ALTCTL_RS485NMM_Pos (8) /!< UART ALTCTL: RS485NMM Position /
sahilmgandhi	18:6a4db94011d3	26254	#define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) /!< UART ALTCTL: RS485NMM Mask /
sahilmgandhi	18:6a4db94011d3	26255
sahilmgandhi	18:6a4db94011d3	26256	#define UART_ALTCTL_RS485AAD_Pos (9) /!< UART ALTCTL: RS485AAD Position /
sahilmgandhi	18:6a4db94011d3	26257	#define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) /!< UART ALTCTL: RS485AAD Mask /
sahilmgandhi	18:6a4db94011d3	26258
sahilmgandhi	18:6a4db94011d3	26259	#define UART_ALTCTL_RS485AUD_Pos (10) /!< UART ALTCTL: RS485AUD Position /
sahilmgandhi	18:6a4db94011d3	26260	#define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) /!< UART ALTCTL: RS485AUD Mask /
sahilmgandhi	18:6a4db94011d3	26261
sahilmgandhi	18:6a4db94011d3	26262	#define UART_ALTCTL_ADDRDEN_Pos (15) /!< UART ALTCTL: ADDRDEN Position /
sahilmgandhi	18:6a4db94011d3	26263	#define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) /!< UART ALTCTL: ADDRDEN Mask /
sahilmgandhi	18:6a4db94011d3	26264
sahilmgandhi	18:6a4db94011d3	26265	#define UART_ALTCTL_ADDRMV_Pos (24) /!< UART ALTCTL: ADDRMV Position /
sahilmgandhi	18:6a4db94011d3	26266	#define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos) /!< UART ALTCTL: ADDRMV Mask /
sahilmgandhi	18:6a4db94011d3	26267
sahilmgandhi	18:6a4db94011d3	26268	#define UART_FUNCSEL_FUNCSEL_Pos (0) /!< UART FUNCSEL: FUNCSEL Position /
sahilmgandhi	18:6a4db94011d3	26269	#define UART_FUNCSEL_FUNCSEL_Msk (0x7ul << UART_FUNCSEL_FUNCSEL_Pos) /!< UART FUNCSEL: FUNCSEL Mask /
sahilmgandhi	18:6a4db94011d3	26270
sahilmgandhi	18:6a4db94011d3	26271	#define UART_LINCTL_SLVEN_Pos (0) /!< UART LINCTL: SLVEN Position /
sahilmgandhi	18:6a4db94011d3	26272	#define UART_LINCTL_SLVEN_Msk (0x1ul << UART_LINCTL_SLVEN_Pos) /!< UART LINCTL: SLVEN Mask /
sahilmgandhi	18:6a4db94011d3	26273
sahilmgandhi	18:6a4db94011d3	26274	#define UART_LINCTL_SLVHDEN_Pos (1) /!< UART LINCTL: SLVHDEN Position /
sahilmgandhi	18:6a4db94011d3	26275	#define UART_LINCTL_SLVHDEN_Msk (0x1ul << UART_LINCTL_SLVHDEN_Pos) /!< UART LINCTL: SLVHDEN Mask /
sahilmgandhi	18:6a4db94011d3	26276
sahilmgandhi	18:6a4db94011d3	26277	#define UART_LINCTL_SLVAREN_Pos (2) /!< UART LINCTL: SLVAREN Position /
sahilmgandhi	18:6a4db94011d3	26278	#define UART_LINCTL_SLVAREN_Msk (0x1ul << UART_LINCTL_SLVAREN_Pos) /!< UART LINCTL: SLVAREN Mask /
sahilmgandhi	18:6a4db94011d3	26279
sahilmgandhi	18:6a4db94011d3	26280	#define UART_LINCTL_SLVDUEN_Pos (3) /!< UART LINCTL: SLVDUEN Position /
sahilmgandhi	18:6a4db94011d3	26281	#define UART_LINCTL_SLVDUEN_Msk (0x1ul << UART_LINCTL_SLVDUEN_Pos) /!< UART LINCTL: SLVDUEN Mask /
sahilmgandhi	18:6a4db94011d3	26282
sahilmgandhi	18:6a4db94011d3	26283	#define UART_LINCTL_MUTE_Pos (4) /!< UART LINCTL: MUTE Position /
sahilmgandhi	18:6a4db94011d3	26284	#define UART_LINCTL_MUTE_Msk (0x1ul << UART_LINCTL_MUTE_Pos) /!< UART LINCTL: MUTE Mask /
sahilmgandhi	18:6a4db94011d3	26285
sahilmgandhi	18:6a4db94011d3	26286	#define UART_LINCTL_SENDH_Pos (8) /!< UART LINCTL: SENDH Position /
sahilmgandhi	18:6a4db94011d3	26287	#define UART_LINCTL_SENDH_Msk (0x1ul << UART_LINCTL_SENDH_Pos) /!< UART LINCTL: SENDH Mask /
sahilmgandhi	18:6a4db94011d3	26288
sahilmgandhi	18:6a4db94011d3	26289	#define UART_LINCTL_IDPEN_Pos (9) /!< UART LINCTL: IDPEN Position /
sahilmgandhi	18:6a4db94011d3	26290	#define UART_LINCTL_IDPEN_Msk (0x1ul << UART_LINCTL_IDPEN_Pos) /!< UART LINCTL: IDPEN Mask /
sahilmgandhi	18:6a4db94011d3	26291
sahilmgandhi	18:6a4db94011d3	26292	#define UART_LINCTL_BRKDETEN_Pos (10) /!< UART LINCTL: BRKDETEN Position /
sahilmgandhi	18:6a4db94011d3	26293	#define UART_LINCTL_BRKDETEN_Msk (0x1ul << UART_LINCTL_BRKDETEN_Pos) /!< UART LINCTL: BRKDETEN Mask /
sahilmgandhi	18:6a4db94011d3	26294
sahilmgandhi	18:6a4db94011d3	26295	#define UART_LINCTL_RXOFF_Pos (11) /!< UART LINCTL: RXOFF Position /
sahilmgandhi	18:6a4db94011d3	26296	#define UART_LINCTL_RXOFF_Msk (0x1ul << UART_LINCTL_RXOFF_Pos) /!< UART LINCTL: RXOFF Mask /
sahilmgandhi	18:6a4db94011d3	26297
sahilmgandhi	18:6a4db94011d3	26298	#define UART_LINCTL_BITERREN_Pos (12) /!< UART LINCTL: BITERREN Position /
sahilmgandhi	18:6a4db94011d3	26299	#define UART_LINCTL_BITERREN_Msk (0x1ul << UART_LINCTL_BITERREN_Pos) /!< UART LINCTL: BITERREN Mask /
sahilmgandhi	18:6a4db94011d3	26300
sahilmgandhi	18:6a4db94011d3	26301	#define UART_LINCTL_BRKFL_Pos (16) /!< UART LINCTL: BRKFL Position /
sahilmgandhi	18:6a4db94011d3	26302	#define UART_LINCTL_BRKFL_Msk (0xful << UART_LINCTL_BRKFL_Pos) /!< UART LINCTL: BRKFL Mask /
sahilmgandhi	18:6a4db94011d3	26303
sahilmgandhi	18:6a4db94011d3	26304	#define UART_LINCTL_BSL_Pos (20) /!< UART LINCTL: BSL Position /
sahilmgandhi	18:6a4db94011d3	26305	#define UART_LINCTL_BSL_Msk (0x3ul << UART_LINCTL_BSL_Pos) /!< UART LINCTL: BSL Mask /
sahilmgandhi	18:6a4db94011d3	26306
sahilmgandhi	18:6a4db94011d3	26307	#define UART_LINCTL_HSEL_Pos (22) /!< UART LINCTL: HSEL Position /
sahilmgandhi	18:6a4db94011d3	26308	#define UART_LINCTL_HSEL_Msk (0x3ul << UART_LINCTL_HSEL_Pos) /!< UART LINCTL: HSEL Mask /
sahilmgandhi	18:6a4db94011d3	26309
sahilmgandhi	18:6a4db94011d3	26310	#define UART_LINCTL_PID_Pos (24) /!< UART LINCTL: PID Position /
sahilmgandhi	18:6a4db94011d3	26311	#define UART_LINCTL_PID_Msk (0xfful << UART_LINCTL_PID_Pos) /!< UART LINCTL: PID Mask /
sahilmgandhi	18:6a4db94011d3	26312
sahilmgandhi	18:6a4db94011d3	26313	#define UART_LINSTS_SLVHDETF_Pos (0) /!< UART LINSTS: SLVHDETF Position /
sahilmgandhi	18:6a4db94011d3	26314	#define UART_LINSTS_SLVHDETF_Msk (0x1ul << UART_LINSTS_SLVHDETF_Pos) /!< UART LINSTS: SLVHDETF Mask /
sahilmgandhi	18:6a4db94011d3	26315
sahilmgandhi	18:6a4db94011d3	26316	#define UART_LINSTS_SLVHEF_Pos (1) /!< UART LINSTS: SLVHEF Position /
sahilmgandhi	18:6a4db94011d3	26317	#define UART_LINSTS_SLVHEF_Msk (0x1ul << UART_LINSTS_SLVHEF_Pos) /!< UART LINSTS: SLVHEF Mask /
sahilmgandhi	18:6a4db94011d3	26318
sahilmgandhi	18:6a4db94011d3	26319	#define UART_LINSTS_SLVIDPEF_Pos (2) /!< UART LINSTS: SLVIDPEF Position /
sahilmgandhi	18:6a4db94011d3	26320	#define UART_LINSTS_SLVIDPEF_Msk (0x1ul << UART_LINSTS_SLVIDPEF_Pos) /!< UART LINSTS: SLVIDPEF Mask /
sahilmgandhi	18:6a4db94011d3	26321
sahilmgandhi	18:6a4db94011d3	26322	#define UART_LINSTS_SLVSYNCF_Pos (3) /!< UART LINSTS: SLVSYNCF Position /
sahilmgandhi	18:6a4db94011d3	26323	#define UART_LINSTS_SLVSYNCF_Msk (0x1ul << UART_LINSTS_SLVSYNCF_Pos) /!< UART LINSTS: SLVSYNCF Mask /
sahilmgandhi	18:6a4db94011d3	26324
sahilmgandhi	18:6a4db94011d3	26325	#define UART_LINSTS_BRKDETF_Pos (8) /!< UART LINSTS: BRKDETF Position /
sahilmgandhi	18:6a4db94011d3	26326	#define UART_LINSTS_BRKDETF_Msk (0x1ul << UART_LINSTS_BRKDETF_Pos) /!< UART LINSTS: BRKDETF Mask /
sahilmgandhi	18:6a4db94011d3	26327
sahilmgandhi	18:6a4db94011d3	26328	#define UART_LINSTS_BITEF_Pos (9) /!< UART LINSTS: BITEF Position /
sahilmgandhi	18:6a4db94011d3	26329	#define UART_LINSTS_BITEF_Msk (0x1ul << UART_LINSTS_BITEF_Pos) /!< UART LINSTS: BITEF Mask /
sahilmgandhi	18:6a4db94011d3	26330
sahilmgandhi	18:6a4db94011d3	26331	#define UART_LINDEBUG_DEVERRF_Pos (0) /!< UART LINDEBUG: DEVERRF Position /
sahilmgandhi	18:6a4db94011d3	26332	#define UART_LINDEBUG_DEVERRF_Msk (0x1ul << UART_LINDEBUG_DEVERRF_Pos) /!< UART LINDEBUG: DEVERRF Mask /
sahilmgandhi	18:6a4db94011d3	26333
sahilmgandhi	18:6a4db94011d3	26334	#define UART_LINDEBUG_TOF_Pos (1) /!< UART LINDEBUG: TOF Position /
sahilmgandhi	18:6a4db94011d3	26335	#define UART_LINDEBUG_TOF_Msk (0x1ul << UART_LINDEBUG_TOF_Pos) /!< UART LINDEBUG: TOF Mask /
sahilmgandhi	18:6a4db94011d3	26336
sahilmgandhi	18:6a4db94011d3	26337	#define UART_LINDEBUG_FRAMEERRF_Pos (2) /!< UART LINDEBUG: FRAMEERRF Position /
sahilmgandhi	18:6a4db94011d3	26338	#define UART_LINDEBUG_FRAMEERRF_Msk (0x1ul << UART_LINDEBUG_FRAMEERRF_Pos) /!< UART LINDEBUG: FRAMEERRF Mask /
sahilmgandhi	18:6a4db94011d3	26339
sahilmgandhi	18:6a4db94011d3	26340	#define UART_LINDEBUG_SYNCERRF_Pos (3) /!< UART LINDEBUG: SYNCERRF Position /
sahilmgandhi	18:6a4db94011d3	26341	#define UART_LINDEBUG_SYNCERRF_Msk (0x1ul << UART_LINDEBUG_SYNCERRF_Pos) /!< UART LINDEBUG: SYNCERRF Mask /
sahilmgandhi	18:6a4db94011d3	26342
sahilmgandhi	18:6a4db94011d3	26343	/*@}/ /* UART_CONST */
sahilmgandhi	18:6a4db94011d3	26344	/*@}/ /* end of UART register group */
sahilmgandhi	18:6a4db94011d3	26345
sahilmgandhi	18:6a4db94011d3	26346
sahilmgandhi	18:6a4db94011d3	26347	/---------------------- USB Host Controller -------------------------/
sahilmgandhi	18:6a4db94011d3	26348	/**
sahilmgandhi	18:6a4db94011d3	26349	@addtogroup USBH USB Host Controller(USBH)
sahilmgandhi	18:6a4db94011d3	26350	Memory Mapped Structure for USBH Controller
sahilmgandhi	18:6a4db94011d3	26351	@{ */
sahilmgandhi	18:6a4db94011d3	26352
sahilmgandhi	18:6a4db94011d3	26353	typedef struct {
sahilmgandhi	18:6a4db94011d3	26354	/**
sahilmgandhi	18:6a4db94011d3	26355	* HcRevision
sahilmgandhi	18:6a4db94011d3	26356	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	26357	* Offset: 0x00 Host Controller Revision Register
sahilmgandhi	18:6a4db94011d3	26358	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	26359	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	26360	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	26361	* \|[0:7] \|REV \|Revision
sahilmgandhi	18:6a4db94011d3	26362	* \| \| \|Indicates the Open HCI Specification revision number implemented by the Hardware.
sahilmgandhi	18:6a4db94011d3	26363	* \| \| \|Host Controller supports 1.1 specification.
sahilmgandhi	18:6a4db94011d3	26364	* \| \| \|(X.Y = XYh).
sahilmgandhi	18:6a4db94011d3	26365	*/
sahilmgandhi	18:6a4db94011d3	26366	__I uint32_t HcRevision;
sahilmgandhi	18:6a4db94011d3	26367
sahilmgandhi	18:6a4db94011d3	26368	/**
sahilmgandhi	18:6a4db94011d3	26369	* HcControl
sahilmgandhi	18:6a4db94011d3	26370	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	26371	* Offset: 0x04 Host Controller Control Register
sahilmgandhi	18:6a4db94011d3	26372	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	26373	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	26374	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	26375	* \|[0:1] \|CBSR \|Control Bulk Service Ratio
sahilmgandhi	18:6a4db94011d3	26376	* \| \| \|Specifies the number of Control Endpoints serviced for every Bulk Endpoint.
sahilmgandhi	18:6a4db94011d3	26377	* \| \| \|Encoding is N-1 where N is the number of Control Endpoints (i.e.
sahilmgandhi	18:6a4db94011d3	26378	* \| \| \|'00' = 1 Control Endpoint; '11' = 3 Control Endpoints).
sahilmgandhi	18:6a4db94011d3	26379	* \|[2] \|PLE \|Periodic List Enable Control
sahilmgandhi	18:6a4db94011d3	26380	* \| \| \|When set, this bit enables processing of the Periodic (interrupt and isochronous) list.
sahilmgandhi	18:6a4db94011d3	26381	* \| \| \|The Host Controller checks this bit prior to attempting any periodic transfers in a frame.
sahilmgandhi	18:6a4db94011d3	26382	* \|[3] \|IE \|Isochronous List Enable Control
sahilmgandhi	18:6a4db94011d3	26383	* \| \| \|When cleared, this bit disables the Isochronous List when the Periodic List is enabled (so Interrupt EDs may be serviced).
sahilmgandhi	18:6a4db94011d3	26384	* \| \| \|While processing the Periodic List, the Host Controller will check this bit when it finds an isochronous ED.
sahilmgandhi	18:6a4db94011d3	26385	* \|[4] \|CLE \|Control List Enable Control
sahilmgandhi	18:6a4db94011d3	26386	* \| \| \|When set, this bit enables processing of the Control list.
sahilmgandhi	18:6a4db94011d3	26387	* \|[5] \|BLE \|Bulk List Enable Control
sahilmgandhi	18:6a4db94011d3	26388	* \| \| \|When set, this bit enables processing of the Bulk list.
sahilmgandhi	18:6a4db94011d3	26389	* \|[6:7] \|HCFS \|Host Controller Functional State
sahilmgandhi	18:6a4db94011d3	26390	* \| \| \|This field sets the Host Controller state.
sahilmgandhi	18:6a4db94011d3	26391	* \| \| \|The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port.
sahilmgandhi	18:6a4db94011d3	26392	* \| \| \|States are:.
sahilmgandhi	18:6a4db94011d3	26393	* \| \| \|00 = USBSUSPEND.
sahilmgandhi	18:6a4db94011d3	26394	* \| \| \|01 = USBOPERATIONAL.
sahilmgandhi	18:6a4db94011d3	26395	* \| \| \|10 = USBRESUME.
sahilmgandhi	18:6a4db94011d3	26396	* \| \| \|11 = USBRESET.
sahilmgandhi	18:6a4db94011d3	26397	* \|[9] \|RWC \|Remote Wake-Up Connected
sahilmgandhi	18:6a4db94011d3	26398	* \| \| \|This bit indicated whether the HC supports a remote wake-up signal.
sahilmgandhi	18:6a4db94011d3	26399	* \| \| \|This implementation does not support any such signal.
sahilmgandhi	18:6a4db94011d3	26400	* \| \| \|The bit is hard-coded to '0.'.
sahilmgandhi	18:6a4db94011d3	26401	* \|[10] \|RWE \|Remote Wake-Up Connected Enable Control
sahilmgandhi	18:6a4db94011d3	26402	* \| \| \|If a remote wake-up signal is supported, this bit enables that operation.
sahilmgandhi	18:6a4db94011d3	26403	* \| \| \|Since there is no remote wake-up signal supported, this bit is ignored.
sahilmgandhi	18:6a4db94011d3	26404	*/
sahilmgandhi	18:6a4db94011d3	26405	__IO uint32_t HcControl;
sahilmgandhi	18:6a4db94011d3	26406
sahilmgandhi	18:6a4db94011d3	26407	/**
sahilmgandhi	18:6a4db94011d3	26408	* HcCommandStatus
sahilmgandhi	18:6a4db94011d3	26409	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	26410	* Offset: 0x08 Host Controller Command Status Register
sahilmgandhi	18:6a4db94011d3	26411	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	26412	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	26413	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	26414	* \|[0] \|HCR \|Host Controller Reset
sahilmgandhi	18:6a4db94011d3	26415	* \| \| \|This bit is set to initiate the software reset.
sahilmgandhi	18:6a4db94011d3	26416	* \| \| \|This bit is cleared by the Host Controller, upon completed of the reset operation.
sahilmgandhi	18:6a4db94011d3	26417	* \|[1] \|CLF \|Control List Filled
sahilmgandhi	18:6a4db94011d3	26418	* \| \| \|Set to indicate there is an active ED on the Control List.
sahilmgandhi	18:6a4db94011d3	26419	* \| \| \|It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List.
sahilmgandhi	18:6a4db94011d3	26420	* \|[2] \|BLF \|Bulk List Filled
sahilmgandhi	18:6a4db94011d3	26421	* \| \| \|Set to indicate there is an active ED on the Bulk List.
sahilmgandhi	18:6a4db94011d3	26422	* \| \| \|The bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk List.
sahilmgandhi	18:6a4db94011d3	26423	* \|[16:17] \|SOC \|Schedule Overrun Count
sahilmgandhi	18:6a4db94011d3	26424	* \| \| \|This field is incremented every time the SchedulingOverrun bit in HcInterruptStatus is set.
sahilmgandhi	18:6a4db94011d3	26425	* \| \| \|The count wraps from '11' to '00'.
sahilmgandhi	18:6a4db94011d3	26426	*/
sahilmgandhi	18:6a4db94011d3	26427	__IO uint32_t HcCommandStatus;
sahilmgandhi	18:6a4db94011d3	26428
sahilmgandhi	18:6a4db94011d3	26429	/**
sahilmgandhi	18:6a4db94011d3	26430	* HcInterruptStatus
sahilmgandhi	18:6a4db94011d3	26431	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	26432	* Offset: 0x0C Host Controller Interrupt Status Register
sahilmgandhi	18:6a4db94011d3	26433	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	26434	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	26435	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	26436	* \|[0] \|SO \|Scheduling Overrun
sahilmgandhi	18:6a4db94011d3	26437	* \| \| \|Set when the List Processor determines a Schedule Overrun has occurred.
sahilmgandhi	18:6a4db94011d3	26438	* \|[1] \|WDH \|Write Back Done Head
sahilmgandhi	18:6a4db94011d3	26439	* \| \| \|Set after the Host Controller has written HcDoneHead to HccaDoneHead.
sahilmgandhi	18:6a4db94011d3	26440	* \|[2] \|SF \|Start Of Frame
sahilmgandhi	18:6a4db94011d3	26441	* \| \| \|Set when the Frame Management block signals a 'Start of Frame' event.
sahilmgandhi	18:6a4db94011d3	26442	* \|[3] \|RD \|Resume Detected
sahilmgandhi	18:6a4db94011d3	26443	* \| \| \|Set when Host Controller detects resume signaling on a downstream port.
sahilmgandhi	18:6a4db94011d3	26444	* \|[4] \|UE \|Unrecoverable Error
sahilmgandhi	18:6a4db94011d3	26445	* \| \| \|This event is not implemented and is hard-coded to '0.' Writes are ignored.
sahilmgandhi	18:6a4db94011d3	26446	* \|[5] \|FNOF \|Frame Number Overflow
sahilmgandhi	18:6a4db94011d3	26447	* \| \| \|Set when bit 15 of Frame Number changes value.
sahilmgandhi	18:6a4db94011d3	26448	* \|[6] \|RHSC \|Root Hub Status Change
sahilmgandhi	18:6a4db94011d3	26449	* \| \| \|This bit is set when the content of HcRhStatus or the content of any HcRhPortStatus register has changed.
sahilmgandhi	18:6a4db94011d3	26450	*/
sahilmgandhi	18:6a4db94011d3	26451	__IO uint32_t HcInterruptStatus;
sahilmgandhi	18:6a4db94011d3	26452
sahilmgandhi	18:6a4db94011d3	26453	/**
sahilmgandhi	18:6a4db94011d3	26454	* HcInterruptEnable
sahilmgandhi	18:6a4db94011d3	26455	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	26456	* Offset: 0x10 Host Controller Interrupt Enable Control Register
sahilmgandhi	18:6a4db94011d3	26457	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	26458	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	26459	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	26460	* \|[0] \|SO \|Scheduling Overrun Enable Control
sahilmgandhi	18:6a4db94011d3	26461	* \| \| \|0 = The interrupt function Disabled.
sahilmgandhi	18:6a4db94011d3	26462	* \| \| \|1 = Interrupt generation Enabled due to Scheduling Overrun.
sahilmgandhi	18:6a4db94011d3	26463	* \|[1] \|WDH \|Write Back Done Head Enable Control
sahilmgandhi	18:6a4db94011d3	26464	* \| \| \|0 = The interrupt function Disabled.
sahilmgandhi	18:6a4db94011d3	26465	* \| \| \|1 = Interrupt generation Enabled due to Write-back Done Head.
sahilmgandhi	18:6a4db94011d3	26466	* \|[2] \|SF \|Start Of Frame Enable Control
sahilmgandhi	18:6a4db94011d3	26467	* \| \| \|0 = The interrupt function Disabled.
sahilmgandhi	18:6a4db94011d3	26468	* \| \| \|1 = interrupt generation Enabled due to Start of Frame.
sahilmgandhi	18:6a4db94011d3	26469	* \|[3] \|RD \|Resume Detected Enable Control
sahilmgandhi	18:6a4db94011d3	26470	* \| \| \|0 = The interrupt function Disabled.
sahilmgandhi	18:6a4db94011d3	26471	* \| \| \|1 = interrupt generation Enabled due to Resume Detected.
sahilmgandhi	18:6a4db94011d3	26472	* \|[4] \|UE \|Unrecoverable Error Enable Control
sahilmgandhi	18:6a4db94011d3	26473	* \| \| \|This event is not implemented. All writes to this bit are ignored.
sahilmgandhi	18:6a4db94011d3	26474	* \|[5] \|FNO \|Frame Number Overflow Enable Control
sahilmgandhi	18:6a4db94011d3	26475	* \| \| \|0 = The interrupt function Disabled.
sahilmgandhi	18:6a4db94011d3	26476	* \| \| \|1 = Interrupt generation Enabled due to Frame Number Overflow.
sahilmgandhi	18:6a4db94011d3	26477	* \|[6] \|RHSC \|Root Hub Status Change Enable Control
sahilmgandhi	18:6a4db94011d3	26478	* \| \| \|0 = The interrupt function Disabled.
sahilmgandhi	18:6a4db94011d3	26479	* \| \| \|1 = interrupt generation Enabled due to Root Hub Status Change.
sahilmgandhi	18:6a4db94011d3	26480	* \|[31] \|MIE \|Master Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	26481	* \| \| \|This bit is a global interrupt enable.
sahilmgandhi	18:6a4db94011d3	26482	* \| \| \|A write of '1' allows interrupts to be enabled via the specific enable bits listed above.
sahilmgandhi	18:6a4db94011d3	26483	*/
sahilmgandhi	18:6a4db94011d3	26484	__IO uint32_t HcInterruptEnable;
sahilmgandhi	18:6a4db94011d3	26485
sahilmgandhi	18:6a4db94011d3	26486	/**
sahilmgandhi	18:6a4db94011d3	26487	* HcInterruptDisable
sahilmgandhi	18:6a4db94011d3	26488	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	26489	* Offset: 0x14 Host Controller Interrupt Disable Control Register
sahilmgandhi	18:6a4db94011d3	26490	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	26491	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	26492	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	26493	* \|[0] \|SO \|Scheduling Overrun Disable Control
sahilmgandhi	18:6a4db94011d3	26494	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	26495	* \| \| \|1 = Interrupt generation Disabled due to Scheduling Overrun.
sahilmgandhi	18:6a4db94011d3	26496	* \|[1] \|WDH \|Write Back Done Head Disable Control
sahilmgandhi	18:6a4db94011d3	26497	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	26498	* \| \| \|1 = Interrupt generation Disabled due to Write-back Done Head.
sahilmgandhi	18:6a4db94011d3	26499	* \|[2] \|SF \|Start Of Frame Disable Control
sahilmgandhi	18:6a4db94011d3	26500	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	26501	* \| \| \|1 = Interrupt generation Disabled due to Start of Frame.
sahilmgandhi	18:6a4db94011d3	26502	* \|[3] \|RD \|Resume Detected Disable Control
sahilmgandhi	18:6a4db94011d3	26503	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	26504	* \| \| \|1 = Interrupt generation Disabled due to Resume Detected.
sahilmgandhi	18:6a4db94011d3	26505	* \|[4] \|UE \|Unrecoverable Error Disable Control
sahilmgandhi	18:6a4db94011d3	26506	* \| \| \|This event is not implemented. All writes to this bit are ignored.
sahilmgandhi	18:6a4db94011d3	26507	* \|[5] \|FNO \|Frame Number Overflow Disable Control
sahilmgandhi	18:6a4db94011d3	26508	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	26509	* \| \| \|1 = Interrupt generation Disabled due to Frame Number Overflow.
sahilmgandhi	18:6a4db94011d3	26510	* \|[6] \|RHSC \|Root Hub Status Change Disable Control
sahilmgandhi	18:6a4db94011d3	26511	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	26512	* \| \| \|1 = Interrupt generation Disabled due to Root Hub Status Change.
sahilmgandhi	18:6a4db94011d3	26513	* \|[31] \|MIE \|Master Interrupt Disable Control
sahilmgandhi	18:6a4db94011d3	26514	* \| \| \|Global interrupt disable. Writing '1' to disable all interrupts.
sahilmgandhi	18:6a4db94011d3	26515	*/
sahilmgandhi	18:6a4db94011d3	26516	__IO uint32_t HcInterruptDisable;
sahilmgandhi	18:6a4db94011d3	26517
sahilmgandhi	18:6a4db94011d3	26518	/**
sahilmgandhi	18:6a4db94011d3	26519	* HcHCCA
sahilmgandhi	18:6a4db94011d3	26520	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	26521	* Offset: 0x18 Host Controller Communication Area Register
sahilmgandhi	18:6a4db94011d3	26522	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	26523	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	26524	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	26525	* \|[8:31] \|HCCA \|Host Controller Communication Area
sahilmgandhi	18:6a4db94011d3	26526	* \| \| \|Pointer to HCCA base address.
sahilmgandhi	18:6a4db94011d3	26527	*/
sahilmgandhi	18:6a4db94011d3	26528	__IO uint32_t HcHCCA;
sahilmgandhi	18:6a4db94011d3	26529
sahilmgandhi	18:6a4db94011d3	26530	/**
sahilmgandhi	18:6a4db94011d3	26531	* HcPeriodCurrentED
sahilmgandhi	18:6a4db94011d3	26532	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	26533	* Offset: 0x1C Host Controller Period Current ED Register
sahilmgandhi	18:6a4db94011d3	26534	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	26535	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	26536	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	26537	* \|[4:31] \|PCED \|Periodic Current ED
sahilmgandhi	18:6a4db94011d3	26538	* \| \| \|Pointer to the current Periodic List ED.
sahilmgandhi	18:6a4db94011d3	26539	*/
sahilmgandhi	18:6a4db94011d3	26540	__IO uint32_t HcPeriodCurrentED;
sahilmgandhi	18:6a4db94011d3	26541
sahilmgandhi	18:6a4db94011d3	26542	/**
sahilmgandhi	18:6a4db94011d3	26543	* HcControlHeadED
sahilmgandhi	18:6a4db94011d3	26544	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	26545	* Offset: 0x20 Host Controller Control Head ED Register
sahilmgandhi	18:6a4db94011d3	26546	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	26547	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	26548	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	26549	* \|[4:31] \|CHED \|Control Head ED
sahilmgandhi	18:6a4db94011d3	26550	* \| \| \|Pointer to the Control List Head ED.
sahilmgandhi	18:6a4db94011d3	26551	*/
sahilmgandhi	18:6a4db94011d3	26552	__IO uint32_t HcControlHeadED;
sahilmgandhi	18:6a4db94011d3	26553
sahilmgandhi	18:6a4db94011d3	26554	/**
sahilmgandhi	18:6a4db94011d3	26555	* HcControlCurrentED
sahilmgandhi	18:6a4db94011d3	26556	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	26557	* Offset: 0x24 Host Controller Control Current ED Register
sahilmgandhi	18:6a4db94011d3	26558	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	26559	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	26560	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	26561	* \|[4:31] \|CCED \|Control Current Head ED
sahilmgandhi	18:6a4db94011d3	26562	* \| \| \|Pointer to the current Control List Head ED.
sahilmgandhi	18:6a4db94011d3	26563	*/
sahilmgandhi	18:6a4db94011d3	26564	__IO uint32_t HcControlCurrentED;
sahilmgandhi	18:6a4db94011d3	26565
sahilmgandhi	18:6a4db94011d3	26566	/**
sahilmgandhi	18:6a4db94011d3	26567	* HcBulkHeadED
sahilmgandhi	18:6a4db94011d3	26568	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	26569	* Offset: 0x28 Host Controller Bulk Head ED Register
sahilmgandhi	18:6a4db94011d3	26570	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	26571	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	26572	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	26573	* \|[4:31] \|BHED \|Bulk Head ED
sahilmgandhi	18:6a4db94011d3	26574	* \| \| \|Pointer to the Bulk List Head ED.
sahilmgandhi	18:6a4db94011d3	26575	*/
sahilmgandhi	18:6a4db94011d3	26576	__IO uint32_t HcBulkHeadED;
sahilmgandhi	18:6a4db94011d3	26577
sahilmgandhi	18:6a4db94011d3	26578	/**
sahilmgandhi	18:6a4db94011d3	26579	* HcBulkCurrentED
sahilmgandhi	18:6a4db94011d3	26580	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	26581	* Offset: 0x2C Host Controller Bulk Current ED Register
sahilmgandhi	18:6a4db94011d3	26582	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	26583	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	26584	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	26585	* \|[4:31] \|BCED \|Bulk Current Head ED
sahilmgandhi	18:6a4db94011d3	26586	* \| \| \|Pointer to the current Bulk List Head ED.
sahilmgandhi	18:6a4db94011d3	26587	*/
sahilmgandhi	18:6a4db94011d3	26588	__IO uint32_t HcBulkCurrentED;
sahilmgandhi	18:6a4db94011d3	26589
sahilmgandhi	18:6a4db94011d3	26590	/**
sahilmgandhi	18:6a4db94011d3	26591	* HcDoneHead
sahilmgandhi	18:6a4db94011d3	26592	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	26593	* Offset: 0x30 Host Controller Done Head Register
sahilmgandhi	18:6a4db94011d3	26594	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	26595	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	26596	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	26597	* \|[4:31] \|DH \|Done Head
sahilmgandhi	18:6a4db94011d3	26598	* \| \| \|Pointer to the current Done List Head ED.
sahilmgandhi	18:6a4db94011d3	26599	*/
sahilmgandhi	18:6a4db94011d3	26600	__IO uint32_t HcDoneHead;
sahilmgandhi	18:6a4db94011d3	26601
sahilmgandhi	18:6a4db94011d3	26602	/**
sahilmgandhi	18:6a4db94011d3	26603	* HcFmInterval
sahilmgandhi	18:6a4db94011d3	26604	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	26605	* Offset: 0x34 Host Controller Frame Interval Register
sahilmgandhi	18:6a4db94011d3	26606	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	26607	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	26608	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	26609	* \|[0:13] \|FI \|Frame Interval
sahilmgandhi	18:6a4db94011d3	26610	* \| \| \|This field specifies the length of a frame as (bit times - 1).
sahilmgandhi	18:6a4db94011d3	26611	* \| \| \|For 12,000 bit times in a frame, a value of 11,999 is stored here.
sahilmgandhi	18:6a4db94011d3	26612	* \|[16:30] \|FSMPS \|FS Largest Data Packet
sahilmgandhi	18:6a4db94011d3	26613	* \| \| \|This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame.
sahilmgandhi	18:6a4db94011d3	26614	* \|[31] \|FIT \|Frame Interval Toggle
sahilmgandhi	18:6a4db94011d3	26615	* \| \| \|This bit is toggled by HCD when it loads a new value into Frame Interval.
sahilmgandhi	18:6a4db94011d3	26616	*/
sahilmgandhi	18:6a4db94011d3	26617	__IO uint32_t HcFmInterval;
sahilmgandhi	18:6a4db94011d3	26618
sahilmgandhi	18:6a4db94011d3	26619	/**
sahilmgandhi	18:6a4db94011d3	26620	* HcFmRemaining
sahilmgandhi	18:6a4db94011d3	26621	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	26622	* Offset: 0x38 Host Controller Frame Remaining Register
sahilmgandhi	18:6a4db94011d3	26623	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	26624	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	26625	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	26626	* \|[0:13] \|FR \|Frame Remaining
sahilmgandhi	18:6a4db94011d3	26627	* \| \| \|When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period.
sahilmgandhi	18:6a4db94011d3	26628	* \| \| \|When the count reaches 0, (end of frame) the counter reloads with Frame Interval.
sahilmgandhi	18:6a4db94011d3	26629	* \| \| \|In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL.
sahilmgandhi	18:6a4db94011d3	26630	* \|[31] \|FRT \|Frame Remaining Toggle
sahilmgandhi	18:6a4db94011d3	26631	* \| \| \|Loaded with Frame Interval Toggle when FrameRemaining is loaded.
sahilmgandhi	18:6a4db94011d3	26632	*/
sahilmgandhi	18:6a4db94011d3	26633	__I uint32_t HcFmRemaining;
sahilmgandhi	18:6a4db94011d3	26634
sahilmgandhi	18:6a4db94011d3	26635	/**
sahilmgandhi	18:6a4db94011d3	26636	* HcFmNumber
sahilmgandhi	18:6a4db94011d3	26637	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	26638	* Offset: 0x3C Host Controller Frame Number Register
sahilmgandhi	18:6a4db94011d3	26639	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	26640	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	26641	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	26642	* \|[0:15] \|FN \|Frame Number
sahilmgandhi	18:6a4db94011d3	26643	* \| \| \|This 16-bit incrementing counter field is incremented coincident with the loading of FrameRemaining.
sahilmgandhi	18:6a4db94011d3	26644	* \| \| \|The count rolls over from 'FFFFh' to '0h.'.
sahilmgandhi	18:6a4db94011d3	26645	*/
sahilmgandhi	18:6a4db94011d3	26646	__I uint32_t HcFmNumber;
sahilmgandhi	18:6a4db94011d3	26647
sahilmgandhi	18:6a4db94011d3	26648	/**
sahilmgandhi	18:6a4db94011d3	26649	* HcPeriodicStart
sahilmgandhi	18:6a4db94011d3	26650	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	26651	* Offset: 0x40 Host Controller Periodic Start Register
sahilmgandhi	18:6a4db94011d3	26652	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	26653	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	26654	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	26655	* \|[0:13] \|PS \|Periodic Start
sahilmgandhi	18:6a4db94011d3	26656	* \| \| \|This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
sahilmgandhi	18:6a4db94011d3	26657	*/
sahilmgandhi	18:6a4db94011d3	26658	__IO uint32_t HcPeriodicStart;
sahilmgandhi	18:6a4db94011d3	26659
sahilmgandhi	18:6a4db94011d3	26660	/**
sahilmgandhi	18:6a4db94011d3	26661	* HcLSThreshold
sahilmgandhi	18:6a4db94011d3	26662	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	26663	* Offset: 0x44 Host Controller Low-speed Threshold Register
sahilmgandhi	18:6a4db94011d3	26664	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	26665	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	26666	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	26667	* \|[0:11] \|LST \|Low-Speed Threshold
sahilmgandhi	18:6a4db94011d3	26668	* \| \| \|This field contains a value which is compared to the FrameRemaining field prior to initiating a Low-speed transaction.
sahilmgandhi	18:6a4db94011d3	26669	* \| \| \|The transaction is started only if FrameRemaining >= this field.
sahilmgandhi	18:6a4db94011d3	26670	* \| \| \|The value is calculated by HCD with the consideration of transmission and setup overhead.
sahilmgandhi	18:6a4db94011d3	26671	*/
sahilmgandhi	18:6a4db94011d3	26672	__IO uint32_t HcLSThreshold;
sahilmgandhi	18:6a4db94011d3	26673
sahilmgandhi	18:6a4db94011d3	26674	/**
sahilmgandhi	18:6a4db94011d3	26675	* HcRhDescriptorA
sahilmgandhi	18:6a4db94011d3	26676	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	26677	* Offset: 0x48 Host Controller Root Hub Descriptor A Register
sahilmgandhi	18:6a4db94011d3	26678	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	26679	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	26680	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	26681	* \|[0:7] \|NDP \|Number Downstream Ports
sahilmgandhi	18:6a4db94011d3	26682	* \| \| \|Root Hub supports two downstream ports. It's 2 in this Root Hub.
sahilmgandhi	18:6a4db94011d3	26683	* \|[8] \|PSM \|Power Switching Mode
sahilmgandhi	18:6a4db94011d3	26684	* \| \| \|Global power switching mode implemented in Root Hub.
sahilmgandhi	18:6a4db94011d3	26685	* \| \| \|This bit is only valid when NPS bit is cleared.
sahilmgandhi	18:6a4db94011d3	26686	* \| \| \|This bit should be written '0'.
sahilmgandhi	18:6a4db94011d3	26687	* \| \| \|0 = Global Switching.
sahilmgandhi	18:6a4db94011d3	26688	* \| \| \|1 = Individual Switching.
sahilmgandhi	18:6a4db94011d3	26689	* \|[9] \|NPS \|No Power Switching
sahilmgandhi	18:6a4db94011d3	26690	* \| \| \|Global power switching implemented in Root Hub.
sahilmgandhi	18:6a4db94011d3	26691	* \| \| \|This bit should be written to support the external system port power switching implementation.
sahilmgandhi	18:6a4db94011d3	26692	* \| \| \|0 = Ports are power switched.
sahilmgandhi	18:6a4db94011d3	26693	* \| \| \|1 = Ports are always powered on.
sahilmgandhi	18:6a4db94011d3	26694	* \|[10] \|DT \|Device Type
sahilmgandhi	18:6a4db94011d3	26695	* \| \| \|The OHCI Root Hub is not a compound device.
sahilmgandhi	18:6a4db94011d3	26696	* \|[11] \|OCPM \|Overcurrent Protection Mode
sahilmgandhi	18:6a4db94011d3	26697	* \| \| \|Global overcurrent reporting implemented in Root Hub.
sahilmgandhi	18:6a4db94011d3	26698	* \| \| \|This bit should be written 0 and is only valid when NOCP bit is cleared.
sahilmgandhi	18:6a4db94011d3	26699	* \| \| \|0 = Global Overcurrent.
sahilmgandhi	18:6a4db94011d3	26700	* \| \| \|1 = Individual Overcurrent.
sahilmgandhi	18:6a4db94011d3	26701	* \|[12] \|NOCP \|No Overcurrent Protection
sahilmgandhi	18:6a4db94011d3	26702	* \| \| \|Global overcurrent reporting implemented in Root Hub.
sahilmgandhi	18:6a4db94011d3	26703	* \| \| \|This bit should be written to support the external system port overcurrent implementation.
sahilmgandhi	18:6a4db94011d3	26704	* \| \| \|0 = Overcurrent status is reported.
sahilmgandhi	18:6a4db94011d3	26705	* \| \| \|1 = Overcurrent status is not reported.
sahilmgandhi	18:6a4db94011d3	26706	* \|[24:31] \|POTGT \|Power On To Power Good Time
sahilmgandhi	18:6a4db94011d3	26707	* \| \| \|This field value is represented as the number of 2 ms intervals, which ensuring that the power switching is effective within 2 ms.
sahilmgandhi	18:6a4db94011d3	26708	* \| \| \|Only bits [25:24] are implemented as R/W.
sahilmgandhi	18:6a4db94011d3	26709	* \| \| \|The remaining bits are read only as '0'.
sahilmgandhi	18:6a4db94011d3	26710	* \| \| \|It is not expected that these bits be written to anything other than 1h, but limited adjustment is provided.
sahilmgandhi	18:6a4db94011d3	26711	* \| \| \|This field should be written to support system implementation.
sahilmgandhi	18:6a4db94011d3	26712	* \| \| \|This field should always be written to a non-zero value.
sahilmgandhi	18:6a4db94011d3	26713	*/
sahilmgandhi	18:6a4db94011d3	26714	__IO uint32_t HcRhDescriptorA;
sahilmgandhi	18:6a4db94011d3	26715
sahilmgandhi	18:6a4db94011d3	26716	/**
sahilmgandhi	18:6a4db94011d3	26717	* HcRhDescriptorB
sahilmgandhi	18:6a4db94011d3	26718	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	26719	* Offset: 0x4C Host Controller Root Hub Descriptor B Register
sahilmgandhi	18:6a4db94011d3	26720	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	26721	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	26722	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	26723	* \|[0:2] \|DR \|Device Removable
sahilmgandhi	18:6a4db94011d3	26724	* \| \| \|Root Hub ports default to removable devices.
sahilmgandhi	18:6a4db94011d3	26725	* \| \| \|0 = Device not removable.
sahilmgandhi	18:6a4db94011d3	26726	* \| \| \|1 = Device removable.
sahilmgandhi	18:6a4db94011d3	26727	* \| \| \|Port Bit relationship:
sahilmgandhi	18:6a4db94011d3	26728	* \| \| \|DevRemove[0] = Reserved.
sahilmgandhi	18:6a4db94011d3	26729	* \| \| \|DevRemove[1] = Port 1.
sahilmgandhi	18:6a4db94011d3	26730	* \| \| \|DevRemove[2] = Port 2.
sahilmgandhi	18:6a4db94011d3	26731	*/
sahilmgandhi	18:6a4db94011d3	26732	__IO uint32_t HcRhDescriptorB;
sahilmgandhi	18:6a4db94011d3	26733
sahilmgandhi	18:6a4db94011d3	26734	/**
sahilmgandhi	18:6a4db94011d3	26735	* HcRhStatus
sahilmgandhi	18:6a4db94011d3	26736	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	26737	* Offset: 0x50 Host Controller Root Hub Status Register
sahilmgandhi	18:6a4db94011d3	26738	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	26739	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	26740	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	26741	* \|[0] \|LPS \|LocalPowerStatus (Read)
sahilmgandhi	18:6a4db94011d3	26742	* \| \| \|Not Supported. Always read '0'.
sahilmgandhi	18:6a4db94011d3	26743	* \| \| \|ClearGlobalPower (Write)
sahilmgandhi	18:6a4db94011d3	26744	* \| \| \|Writing '1' issues a ClearGlobalPower command to the ports. Writing '0' has no effect.
sahilmgandhi	18:6a4db94011d3	26745	* \|[1] \|OCI \|Overcurrent Indicator
sahilmgandhi	18:6a4db94011d3	26746	* \| \| \|This bit reflects the state of the OVRCUR pin.
sahilmgandhi	18:6a4db94011d3	26747	* \| \| \|This field is only valid if NOCP (RHDESA[12]) and OCPM (RHDESA[11]) are cleared.
sahilmgandhi	18:6a4db94011d3	26748	* \| \| \|0 = No overcurrent condition.
sahilmgandhi	18:6a4db94011d3	26749	* \| \| \|1 = Overcurrent condition.
sahilmgandhi	18:6a4db94011d3	26750	* \|[15] \|DRWE \|Device Remote Wake-Up Enable Control (Read)
sahilmgandhi	18:6a4db94011d3	26751	* \| \| \|This bit enables ports' CC (HcRhPtr[0]) as a remote wake-up event.
sahilmgandhi	18:6a4db94011d3	26752	* \| \| \|0 = Disabled.
sahilmgandhi	18:6a4db94011d3	26753	* \| \| \|1 = Enabled.
sahilmgandhi	18:6a4db94011d3	26754	* \| \| \|Set Remote Wake-up Enable Control (Write)
sahilmgandhi	18:6a4db94011d3	26755	* \| \| \|Writing 1' sets DRWEn. Writing '0' has no effect.
sahilmgandhi	18:6a4db94011d3	26756	* \|[16] \|LPSC \|Local Power Status Change (Read)
sahilmgandhi	18:6a4db94011d3	26757	* \| \| \|Not supported. Always read '0'.
sahilmgandhi	18:6a4db94011d3	26758	* \| \| \|SetGlobalPower (Write)
sahilmgandhi	18:6a4db94011d3	26759	* \| \| \|Writing '1' issues a SetGlobalPower command to the ports. Writing '0' has no effect.
sahilmgandhi	18:6a4db94011d3	26760	* \|[17] \|OCIC \|Overcurrent Indicator Change
sahilmgandhi	18:6a4db94011d3	26761	* \| \| \|This bit is set when OC bit changes.
sahilmgandhi	18:6a4db94011d3	26762	* \| \| \|Writing '1' clears this bit. Writing '0' has no effect.
sahilmgandhi	18:6a4db94011d3	26763	* \|[31] \|CRWE \|Clear Remote Wake-Up Enable Control
sahilmgandhi	18:6a4db94011d3	26764	* \| \| \|Writing '1' to this bit clears DRWEn (HcRhStatus[15]). Writing '0' has no effect.
sahilmgandhi	18:6a4db94011d3	26765	*/
sahilmgandhi	18:6a4db94011d3	26766	__IO uint32_t HcRhStatus;
sahilmgandhi	18:6a4db94011d3	26767
sahilmgandhi	18:6a4db94011d3	26768	/**
sahilmgandhi	18:6a4db94011d3	26769	* HcRhPortStatus1/HcRhPortStatus2
sahilmgandhi	18:6a4db94011d3	26770	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	26771	* Offset: 0x54,0x58 Host Controller Root Hub Port Status [1/2]
sahilmgandhi	18:6a4db94011d3	26772	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	26773	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	26774	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	26775	* \|[0] \|CCS \|Current Connect Status (Read)
sahilmgandhi	18:6a4db94011d3	26776	* \| \| \|0 = No device connected.
sahilmgandhi	18:6a4db94011d3	26777	* \| \| \|1 = Device connected.
sahilmgandhi	18:6a4db94011d3	26778	* \| \| \|Clear Port Enable Control (Write)
sahilmgandhi	18:6a4db94011d3	26779	* \| \| \|Writing '1' a clears PE. Writing '0' has no effect.
sahilmgandhi	18:6a4db94011d3	26780	* \|[1] \|PES \|Port Enable Status (Read)
sahilmgandhi	18:6a4db94011d3	26781	* \| \| \|0 = Port Disabled.
sahilmgandhi	18:6a4db94011d3	26782	* \| \| \|1 = Port Enabled.
sahilmgandhi	18:6a4db94011d3	26783	* \| \| \|SetPortEnable (Write)
sahilmgandhi	18:6a4db94011d3	26784	* \| \| \|Writing '1' sets PE. Writing '0' has no effect.
sahilmgandhi	18:6a4db94011d3	26785	* \|[2] \|PSS \|PortSuspendStatus (Read)
sahilmgandhi	18:6a4db94011d3	26786	* \| \| \|0 = Port is not suspended.
sahilmgandhi	18:6a4db94011d3	26787	* \| \| \|1 = Port is selectively suspended.
sahilmgandhi	18:6a4db94011d3	26788	* \| \| \|SetPortSuspend (Write)
sahilmgandhi	18:6a4db94011d3	26789	* \| \| \|Writing '1' sets PortSuspendStatus. Writing '0' has no effect.
sahilmgandhi	18:6a4db94011d3	26790	* \|[3] \|POCI \|PortOverCurrentIndicator (Read)
sahilmgandhi	18:6a4db94011d3	26791	* \| \| \|Root Hub supports global overcurrent reporting.
sahilmgandhi	18:6a4db94011d3	26792	* \| \| \|This bit reflects the state of the OVRCUR pin dedicated to this port.
sahilmgandhi	18:6a4db94011d3	26793	* \| \| \|This field is only valid if NOCP (RHDESA[12]) is cleared and OCPM (RHDESA[11]) is set.
sahilmgandhi	18:6a4db94011d3	26794	* \| \| \|0 = No overcurrent condition.
sahilmgandhi	18:6a4db94011d3	26795	* \| \| \|1 = Overcurrent condition.
sahilmgandhi	18:6a4db94011d3	26796	* \| \| \|ClearPortSuspend (Write)
sahilmgandhi	18:6a4db94011d3	26797	* \| \| \|Writing '1' initiates the selective resume sequence for the port. Writing '0' has no effect.
sahilmgandhi	18:6a4db94011d3	26798	* \|[4] \|PRS \|PortResetStatus (Read)
sahilmgandhi	18:6a4db94011d3	26799	* \| \| \|This bit reflects the power state of the port regardless of the power switching mode.
sahilmgandhi	18:6a4db94011d3	26800	* \| \| \|0 = Port reset signal is not active.
sahilmgandhi	18:6a4db94011d3	26801	* \| \| \|1 = Port reset signal is active.
sahilmgandhi	18:6a4db94011d3	26802	* \| \| \|SetPortReset (Write)
sahilmgandhi	18:6a4db94011d3	26803	* \| \| \|Writing '1' sets PR. Writing '0' has no effect.
sahilmgandhi	18:6a4db94011d3	26804	* \|[8] \|PPS \|PortPowerStatus (Read)
sahilmgandhi	18:6a4db94011d3	26805	* \| \| \|This bit reflects the power state of the port regardless of the power switching mode.
sahilmgandhi	18:6a4db94011d3	26806	* \| \| \|0 = Port power is off.
sahilmgandhi	18:6a4db94011d3	26807	* \| \| \|1 = Port power is on.
sahilmgandhi	18:6a4db94011d3	26808	* \| \| \|Note: If NPS (RHDESA[9]) is set, this bit is always read as '1'.
sahilmgandhi	18:6a4db94011d3	26809	* \| \| \|SetPortPower (Write)
sahilmgandhi	18:6a4db94011d3	26810	* \| \| \|Writing '1' sets PPS. Writing '0' has no effect.
sahilmgandhi	18:6a4db94011d3	26811	* \|[9] \|LSDA \|LowSpeedDeviceAttached (Read)
sahilmgandhi	18:6a4db94011d3	26812	* \| \| \|This bit defines the speed (and bud idle) of the attached device. It is only valid when CC bit is set.
sahilmgandhi	18:6a4db94011d3	26813	* \| \| \|0 = Full Speed device.
sahilmgandhi	18:6a4db94011d3	26814	* \| \| \|1 = Low-speed device.
sahilmgandhi	18:6a4db94011d3	26815	* \| \| \|ClearPortPower (Write)
sahilmgandhi	18:6a4db94011d3	26816	* \| \| \|Writing '1' clears PPS bit. Writing '0' has no effect.
sahilmgandhi	18:6a4db94011d3	26817	* \|[16] \|CSC \|Connect Status Change
sahilmgandhi	18:6a4db94011d3	26818	* \| \| \|This bit indicates connect or disconnect event has been detected.
sahilmgandhi	18:6a4db94011d3	26819	* \| \| \|Writing '1' clears this bit.
sahilmgandhi	18:6a4db94011d3	26820	* \| \| \|Writing '0' has no effect.
sahilmgandhi	18:6a4db94011d3	26821	* \| \| \|0 = No connect/disconnect event.
sahilmgandhi	18:6a4db94011d3	26822	* \| \| \|1 = Hardware detection of connect/disconnect event.
sahilmgandhi	18:6a4db94011d3	26823	* \| \| \|Note: If DevRemove (HcRhDescriptorB[2:0]) is set, this bit resets to '1'.
sahilmgandhi	18:6a4db94011d3	26824	* \|[17] \|PESC \|Port Enable Status Change
sahilmgandhi	18:6a4db94011d3	26825	* \| \| \|This bit indicates that the port has been disabled due to a hardware event (cleared PE bit).
sahilmgandhi	18:6a4db94011d3	26826	* \| \| \|0 = No port enable change event.
sahilmgandhi	18:6a4db94011d3	26827	* \| \| \|1 = Port enable state has been changed.
sahilmgandhi	18:6a4db94011d3	26828	* \|[18] \|PSSC \|Port Reset Status Change
sahilmgandhi	18:6a4db94011d3	26829	* \| \| \|This bit indicates the completion of the selective resume sequence for the port.
sahilmgandhi	18:6a4db94011d3	26830	* \| \| \|0 = Port is not resumed.
sahilmgandhi	18:6a4db94011d3	26831	* \| \| \|1 = Port resume is complete.
sahilmgandhi	18:6a4db94011d3	26832	* \|[19] \|OCIC \|Port Overcurrent Indicator Change
sahilmgandhi	18:6a4db94011d3	26833	* \| \| \|This bit is set when OC (HcRhStatus[1]) changes. Writing '1' clears this bit. Writing '0' has no effect.
sahilmgandhi	18:6a4db94011d3	26834	* \|[20] \|PRSC \|Port Reset Status Change
sahilmgandhi	18:6a4db94011d3	26835	* \| \| \|This bit indicates that the port reset signal has completed.
sahilmgandhi	18:6a4db94011d3	26836	* \| \| \|0 = Port reset is not complete.
sahilmgandhi	18:6a4db94011d3	26837	* \| \| \|1 = Port reset is complete.
sahilmgandhi	18:6a4db94011d3	26838	*/
sahilmgandhi	18:6a4db94011d3	26839	__IO uint32_t HcRhPortStatus[2];
sahilmgandhi	18:6a4db94011d3	26840
sahilmgandhi	18:6a4db94011d3	26841	uint32_t RESERVE0[105];
sahilmgandhi	18:6a4db94011d3	26842
sahilmgandhi	18:6a4db94011d3	26843
sahilmgandhi	18:6a4db94011d3	26844	/**
sahilmgandhi	18:6a4db94011d3	26845	* HcPhyControl
sahilmgandhi	18:6a4db94011d3	26846	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	26847	* Offset: 0x200 USB PHY Control Register
sahilmgandhi	18:6a4db94011d3	26848	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	26849	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	26850	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	26851	* \|[27] \|STBYEN \|USB Transceiver Standby Enable Control
sahilmgandhi	18:6a4db94011d3	26852	* \| \| \|This bit controls if USB 1.1 transceiver could enter the standby mode to reduce power consumption.
sahilmgandhi	18:6a4db94011d3	26853	* \| \| \|If this bit is low, the USB 1.1 transceiver would never enter the standby mode.
sahilmgandhi	18:6a4db94011d3	26854	* \| \| \|If this bit is high, the USB 1.1 transceiver will enter standby mode while port is in power off state (port power is inactive).
sahilmgandhi	18:6a4db94011d3	26855	*/
sahilmgandhi	18:6a4db94011d3	26856	__IO uint32_t HcPhyControl;
sahilmgandhi	18:6a4db94011d3	26857
sahilmgandhi	18:6a4db94011d3	26858	/**
sahilmgandhi	18:6a4db94011d3	26859	* HcMiscControl
sahilmgandhi	18:6a4db94011d3	26860	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	26861	* Offset: 0x204 USB Operational Mode Enable Control Register
sahilmgandhi	18:6a4db94011d3	26862	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	26863	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	26864	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	26865	* \|[0] \|DBR16 \|Data Buffer Region 16
sahilmgandhi	18:6a4db94011d3	26866	* \| \| \|When set, the size of the data buffer region is 16 bytes. Otherwise, the size is 32 bytes.
sahilmgandhi	18:6a4db94011d3	26867	* \|[1] \|ABORT \|AHB Bus ERROR Response
sahilmgandhi	18:6a4db94011d3	26868	* \| \| \|This bit indicates there is an ERROR response received in AHB bus.
sahilmgandhi	18:6a4db94011d3	26869	* \| \| \|0 = No ERROR response received.
sahilmgandhi	18:6a4db94011d3	26870	* \| \| \|1 = ERROR response received.
sahilmgandhi	18:6a4db94011d3	26871	* \|[3] \|OCA \|Overcurrent Active Low
sahilmgandhi	18:6a4db94011d3	26872	* \| \| \|This bit controls the polarity of overcurrent flag from external power IC.
sahilmgandhi	18:6a4db94011d3	26873	* \| \| \|0 = Overcurrent flag is high active.
sahilmgandhi	18:6a4db94011d3	26874	* \| \| \|1 = Overcurrent flag is low active.
sahilmgandhi	18:6a4db94011d3	26875	* \|[4] \|PCAL \|Port Power Control Active Low
sahilmgandhi	18:6a4db94011d3	26876	* \| \| \|This bit controls the polarity of port power control to external power IC.
sahilmgandhi	18:6a4db94011d3	26877	* \| \| \|0 = Port power control is high active.
sahilmgandhi	18:6a4db94011d3	26878	* \| \| \|1 = Port power control is low active.
sahilmgandhi	18:6a4db94011d3	26879	* \|[8] \|SIEPD \|SIE Pipeline Disable Control
sahilmgandhi	18:6a4db94011d3	26880	* \| \| \|When set, waits for all USB bus activity to complete prior to returning completion status to the List Processor.
sahilmgandhi	18:6a4db94011d3	26881	* \| \| \|This is a fail safe mechanism to avoid potential problems with the clk_dr transition between 1.5 MHz and 12 MHz.
sahilmgandhi	18:6a4db94011d3	26882	* \|[16] \|DPRT1 \|Port 1 Disable Control
sahilmgandhi	18:6a4db94011d3	26883	* \| \| \|This bit controls if the connection between USB host controller and transceiver of port 1 is disabled.
sahilmgandhi	18:6a4db94011d3	26884	* \| \| \|If the connection is disabled, the USB host controller will not recognize any event of USB bus.
sahilmgandhi	18:6a4db94011d3	26885	* \| \| \|Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is.
sahilmgandhi	18:6a4db94011d3	26886	* \| \| \|0 = The connection between USB host controller and transceiver of port 1 is enabled.
sahilmgandhi	18:6a4db94011d3	26887	* \| \| \|1 = The connection between USB host controller and transceiver of port 1 is disabled and the transceiver of port 1 will also be forced into the standby mode.
sahilmgandhi	18:6a4db94011d3	26888	* \|[17] \|DPRT2 \|Port 2 Disable Control
sahilmgandhi	18:6a4db94011d3	26889	* \| \| \|This bit controls if the connection between USB host controller and transceiver of port 2 is disabled.
sahilmgandhi	18:6a4db94011d3	26890	* \| \| \|If the connection is disabled, the USB host controller will not recognize any event of USB bus.
sahilmgandhi	18:6a4db94011d3	26891	* \| \| \|Set this bit high, the transceiver of port 2 will also be forced into the standby mode no matter what USB host controller operation is.
sahilmgandhi	18:6a4db94011d3	26892	* \| \| \|0 = The connection between USB host controller and transceiver of port 2 is enabled.
sahilmgandhi	18:6a4db94011d3	26893	* \| \| \|1 = The connection between USB host controller and transceiver of port 2 is disabled and the transceiver of port 2 will also be forced into the standby mode.
sahilmgandhi	18:6a4db94011d3	26894	*/
sahilmgandhi	18:6a4db94011d3	26895	__IO uint32_t HcMiscControl;
sahilmgandhi	18:6a4db94011d3	26896
sahilmgandhi	18:6a4db94011d3	26897	} USBH_T;
sahilmgandhi	18:6a4db94011d3	26898
sahilmgandhi	18:6a4db94011d3	26899	/**
sahilmgandhi	18:6a4db94011d3	26900	@addtogroup USBH_CONST USBH Bit Field Definition
sahilmgandhi	18:6a4db94011d3	26901	Constant Definitions for USBH Controller
sahilmgandhi	18:6a4db94011d3	26902	@{ */
sahilmgandhi	18:6a4db94011d3	26903
sahilmgandhi	18:6a4db94011d3	26904	#define USBH_HcRevision_REV_Pos (0) /!< USBH HcRevision: REV Position /
sahilmgandhi	18:6a4db94011d3	26905	#define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) /!< USBH HcRevision: REV Mask /
sahilmgandhi	18:6a4db94011d3	26906
sahilmgandhi	18:6a4db94011d3	26907	#define USBH_HcControl_CBSR_Pos (0) /!< USBH HcControl: CBSR Position /
sahilmgandhi	18:6a4db94011d3	26908	#define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) /!< USBH HcControl: CBSR Mask /
sahilmgandhi	18:6a4db94011d3	26909
sahilmgandhi	18:6a4db94011d3	26910	#define USBH_HcControl_PLE_Pos (2) /!< USBH HcControl: CBSR Position /
sahilmgandhi	18:6a4db94011d3	26911	#define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) /!< USBH HcControl: CBSR Mask /
sahilmgandhi	18:6a4db94011d3	26912
sahilmgandhi	18:6a4db94011d3	26913	#define USBH_HcControl_IE_Pos (3) /!< USBH HcControl: IE Position /
sahilmgandhi	18:6a4db94011d3	26914	#define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) /!< USBH HcControl: IE Mask /
sahilmgandhi	18:6a4db94011d3	26915
sahilmgandhi	18:6a4db94011d3	26916	#define USBH_HcControl_CLE_Pos (4) /!< USBH HcControl: CLE Position /
sahilmgandhi	18:6a4db94011d3	26917	#define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) /!< USBH HcControl: CLE Mask /
sahilmgandhi	18:6a4db94011d3	26918
sahilmgandhi	18:6a4db94011d3	26919	#define USBH_HcControl_BLE_Pos (5) /!< USBH HcControl: BLE Position /
sahilmgandhi	18:6a4db94011d3	26920	#define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) /!< USBH HcControl: BLE Mask /
sahilmgandhi	18:6a4db94011d3	26921
sahilmgandhi	18:6a4db94011d3	26922	#define USBH_HcControl_HCFS_Pos (6) /!< USBH HcControl: HCFS Position /
sahilmgandhi	18:6a4db94011d3	26923	#define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) /!< USBH HcControl: HCFS Mask /
sahilmgandhi	18:6a4db94011d3	26924
sahilmgandhi	18:6a4db94011d3	26925	#define USBH_HcCommandStatus_HCR_Pos (0) /!< USBH HcCommandStatus: HCR Position /
sahilmgandhi	18:6a4db94011d3	26926	#define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) /!< USBH HcCommandStatus: HCR Mask /
sahilmgandhi	18:6a4db94011d3	26927
sahilmgandhi	18:6a4db94011d3	26928	#define USBH_HcCommandStatus_CLF_Pos (1) /!< USBH HcCommandStatus: CLF Position /
sahilmgandhi	18:6a4db94011d3	26929	#define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) /!< USBH HcCommandStatus: CLF Mask /
sahilmgandhi	18:6a4db94011d3	26930
sahilmgandhi	18:6a4db94011d3	26931	#define USBH_HcCommandStatus_BLF_Pos (2) /!< USBH HcCommandStatus: BLF Position /
sahilmgandhi	18:6a4db94011d3	26932	#define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) /!< USBH HcCommandStatus: BLF Mask /
sahilmgandhi	18:6a4db94011d3	26933
sahilmgandhi	18:6a4db94011d3	26934	#define USBH_HcCommandStatus_SOC_Pos (16) /!< USBH HcCommandStatus: SOC Position /
sahilmgandhi	18:6a4db94011d3	26935	#define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) /!< USBH HcCommandStatus: SOC Mask /
sahilmgandhi	18:6a4db94011d3	26936
sahilmgandhi	18:6a4db94011d3	26937	#define USBH_HcInterruptStatus_SO_Pos (0) /!< USBH HcInterruptStatus: SO Position /
sahilmgandhi	18:6a4db94011d3	26938	#define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) /!< USBH HcInterruptStatus: SO Mask /
sahilmgandhi	18:6a4db94011d3	26939
sahilmgandhi	18:6a4db94011d3	26940	#define USBH_HcInterruptStatus_WDH_Pos (1) /!< USBH HcInterruptStatus: WDH Position /
sahilmgandhi	18:6a4db94011d3	26941	#define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) /!< USBH HcInterruptStatus: WDH Mask /
sahilmgandhi	18:6a4db94011d3	26942
sahilmgandhi	18:6a4db94011d3	26943	#define USBH_HcInterruptStatus_SF_Pos (2) /!< USBH HcInterruptStatus: SF Position /
sahilmgandhi	18:6a4db94011d3	26944	#define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) /!< USBH HcInterruptStatus: SF Mask /
sahilmgandhi	18:6a4db94011d3	26945
sahilmgandhi	18:6a4db94011d3	26946	#define USBH_HcInterruptStatus_RD_Pos (3) /!< USBH HcInterruptStatus: RD Position /
sahilmgandhi	18:6a4db94011d3	26947	#define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) /!< USBH HcInterruptStatus: RD Mask /
sahilmgandhi	18:6a4db94011d3	26948
sahilmgandhi	18:6a4db94011d3	26949	#define USBH_HcInterruptStatus_FNO_Pos (5) /!< USBH HcInterruptStatus: FNO Position /
sahilmgandhi	18:6a4db94011d3	26950	#define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) /!< USBH HcInterruptStatus: FNO Mask /
sahilmgandhi	18:6a4db94011d3	26951
sahilmgandhi	18:6a4db94011d3	26952	#define USBH_HcInterruptStatus_RHSC_Pos (6) /!< USBH HcInterruptStatus: RHSC Position /
sahilmgandhi	18:6a4db94011d3	26953	#define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) /!< USBH HcInterruptStatus: RHSC Mask /
sahilmgandhi	18:6a4db94011d3	26954
sahilmgandhi	18:6a4db94011d3	26955	#define USBH_HcInterruptEnable_SO_Pos (0) /!< USBH HcInterruptEnable: SO Position /
sahilmgandhi	18:6a4db94011d3	26956	#define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) /!< USBH HcInterruptEnable: SO Mask /
sahilmgandhi	18:6a4db94011d3	26957
sahilmgandhi	18:6a4db94011d3	26958	#define USBH_HcInterruptEnable_WDH_Pos (1) /!< USBH HcInterruptEnable: WDH Position /
sahilmgandhi	18:6a4db94011d3	26959	#define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) /!< USBH HcInterruptEnable: WDH Mask /
sahilmgandhi	18:6a4db94011d3	26960
sahilmgandhi	18:6a4db94011d3	26961	#define USBH_HcInterruptEnable_SF_Pos (2) /!< USBH HcInterruptEnable: SF Position /
sahilmgandhi	18:6a4db94011d3	26962	#define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) /!< USBH HcInterruptEnable: SF Mask /
sahilmgandhi	18:6a4db94011d3	26963
sahilmgandhi	18:6a4db94011d3	26964	#define USBH_HcInterruptEnable_RD_Pos (3) /!< USBH HcInterruptEnable: RD Position /
sahilmgandhi	18:6a4db94011d3	26965	#define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) /!< USBH HcInterruptEnable: RD Mask /
sahilmgandhi	18:6a4db94011d3	26966
sahilmgandhi	18:6a4db94011d3	26967	#define USBH_HcInterruptEnable_FNO_Pos (5) /!< USBH HcInterruptEnable: FNO Position /
sahilmgandhi	18:6a4db94011d3	26968	#define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) /!< USBH HcInterruptEnable: FNO Mask /
sahilmgandhi	18:6a4db94011d3	26969
sahilmgandhi	18:6a4db94011d3	26970	#define USBH_HcInterruptEnable_RHSC_Pos (6) /!< USBH HcInterruptEnable: RHSC Position /
sahilmgandhi	18:6a4db94011d3	26971	#define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) /!< USBH HcInterruptEnable: RHSC Mask /
sahilmgandhi	18:6a4db94011d3	26972
sahilmgandhi	18:6a4db94011d3	26973	#define USBH_HcInterruptEnable_MIE_Pos (31) /!< USBH HcInterruptEnable: MIE Position /
sahilmgandhi	18:6a4db94011d3	26974	#define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) /!< USBH HcInterruptEnable: MIE Mask /
sahilmgandhi	18:6a4db94011d3	26975
sahilmgandhi	18:6a4db94011d3	26976	#define USBH_HcInterruptDisable_SO_Pos (0) /!< USBH HcInterruptDisable: SO Position /
sahilmgandhi	18:6a4db94011d3	26977	#define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) /!< USBH HcInterruptDisable: SO Mask /
sahilmgandhi	18:6a4db94011d3	26978
sahilmgandhi	18:6a4db94011d3	26979	#define USBH_HcInterruptDisable_WDH_Pos (1) /!< USBH HcInterruptDisable: WDH Position /
sahilmgandhi	18:6a4db94011d3	26980	#define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) /!< USBH HcInterruptDisable: WDH Mask /
sahilmgandhi	18:6a4db94011d3	26981
sahilmgandhi	18:6a4db94011d3	26982	#define USBH_HcInterruptDisable_SF_Pos (2) /!< USBH HcInterruptDisable: SF Position /
sahilmgandhi	18:6a4db94011d3	26983	#define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) /!< USBH HcInterruptDisable: SF Mask /
sahilmgandhi	18:6a4db94011d3	26984
sahilmgandhi	18:6a4db94011d3	26985	#define USBH_HcInterruptDisable_RD_Pos (3) /!< USBH HcInterruptDisable: RD Position /
sahilmgandhi	18:6a4db94011d3	26986	#define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) /!< USBH HcInterruptDisable: RD Mask /
sahilmgandhi	18:6a4db94011d3	26987
sahilmgandhi	18:6a4db94011d3	26988	#define USBH_HcInterruptDisable_FNO_Pos (5) /!< USBH HcInterruptDisable: FNO Position /
sahilmgandhi	18:6a4db94011d3	26989	#define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) /!< USBH HcInterruptDisable: FNO Mask /
sahilmgandhi	18:6a4db94011d3	26990
sahilmgandhi	18:6a4db94011d3	26991	#define USBH_HcInterruptDisable_RHSC_Pos (6) /!< USBH HcInterruptDisable: RHSC Position /
sahilmgandhi	18:6a4db94011d3	26992	#define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) /!< USBH HcInterruptDisable: RHSC Mask /
sahilmgandhi	18:6a4db94011d3	26993
sahilmgandhi	18:6a4db94011d3	26994	#define USBH_HcInterruptDisable_MIE_Pos (31) /!< USBH HcInterruptDisable: MIE Position /
sahilmgandhi	18:6a4db94011d3	26995	#define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) /!< USBH HcInterruptDisable: MIE Mask /
sahilmgandhi	18:6a4db94011d3	26996
sahilmgandhi	18:6a4db94011d3	26997	#define USBH_HcHCCA_HCCA_Pos (8) /!< USBH HcHCCA: HCCA Position /
sahilmgandhi	18:6a4db94011d3	26998	#define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) /!< USBH HcHCCA: HCCA Mask /
sahilmgandhi	18:6a4db94011d3	26999
sahilmgandhi	18:6a4db94011d3	27000	#define USBH_HcPeriodCurrentED_PCED_Pos (4) /!< USBH HcPeriodCurrentED: PCED Position /
sahilmgandhi	18:6a4db94011d3	27001	#define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) /!< USBH HcPeriodCurrentED: PCED Mask /
sahilmgandhi	18:6a4db94011d3	27002
sahilmgandhi	18:6a4db94011d3	27003	#define USBH_HcControlHeadED_CHED_Pos (4) /!< USBH HcControlHeadED: CHED Position /
sahilmgandhi	18:6a4db94011d3	27004	#define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) /!< USBH HcControlHeadED: CHED Mask /
sahilmgandhi	18:6a4db94011d3	27005
sahilmgandhi	18:6a4db94011d3	27006	#define USBH_HcControlCurrentED_CCED_Pos (4) /!< USBH HcControlCurrentED: CCED Position /
sahilmgandhi	18:6a4db94011d3	27007	#define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /!< USBH HcControlCurrentED: CCED Mask /
sahilmgandhi	18:6a4db94011d3	27008
sahilmgandhi	18:6a4db94011d3	27009	#define USBH_HcBulkHeadED_BHED_Pos (4) /!< USBH HcBulkHeadED: BHED Position /
sahilmgandhi	18:6a4db94011d3	27010	#define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) /!< USBH HcBulkHeadED: BHED Mask /
sahilmgandhi	18:6a4db94011d3	27011
sahilmgandhi	18:6a4db94011d3	27012	#define USBH_HcBulkCurrentED_BCED_Pos (4) /!< USBH HcBulkCurrentED: BCED Position /
sahilmgandhi	18:6a4db94011d3	27013	#define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) /!< USBH HcBulkCurrentED: BCED Mask /
sahilmgandhi	18:6a4db94011d3	27014
sahilmgandhi	18:6a4db94011d3	27015	#define USBH_HcDoneHead_DH_Pos (4) /!< USBH HcDoneHead: DH Position /
sahilmgandhi	18:6a4db94011d3	27016	#define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) /!< USBH HcDoneHead: DH Mask /
sahilmgandhi	18:6a4db94011d3	27017
sahilmgandhi	18:6a4db94011d3	27018	#define USBH_HcFmInterval_FI_Pos (0) /!< USBH HcFmInterval: FI Position /
sahilmgandhi	18:6a4db94011d3	27019	#define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) /!< USBH HcFmInterval: FI Mask /
sahilmgandhi	18:6a4db94011d3	27020
sahilmgandhi	18:6a4db94011d3	27021	#define USBH_HcFmInterval_FSMPS_Pos (16) /!< USBH HcFmInterval: FSMPS Position /
sahilmgandhi	18:6a4db94011d3	27022	#define USBH_HcFmInterval_FSMPS_Msk (0x7ffful << USBH_HcFmInterval_FSMPS_Pos) /!< USBH HcFmInterval: FSMPS Mask /
sahilmgandhi	18:6a4db94011d3	27023
sahilmgandhi	18:6a4db94011d3	27024	#define USBH_HcFmInterval_FIT_Pos (31) /!< USBH HcFmInterval: FIT Position /
sahilmgandhi	18:6a4db94011d3	27025	#define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) /!< USBH HcFmInterval: FIT Mask /
sahilmgandhi	18:6a4db94011d3	27026
sahilmgandhi	18:6a4db94011d3	27027	#define USBH_HcFmRemaining_FR_Pos (0) /!< USBH HcFmRemaining: FR Position /
sahilmgandhi	18:6a4db94011d3	27028	#define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) /!< USBH HcFmRemaining: FR Mask /
sahilmgandhi	18:6a4db94011d3	27029
sahilmgandhi	18:6a4db94011d3	27030	#define USBH_HcFmRemaining_FRT_Pos (31) /!< USBH HcFmRemaining: FRT Position /
sahilmgandhi	18:6a4db94011d3	27031	#define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) /!< USBH HcFmRemaining: FRT Mask /
sahilmgandhi	18:6a4db94011d3	27032
sahilmgandhi	18:6a4db94011d3	27033	#define USBH_HcFmNumber_FN_Pos (0) /!< USBH HcFmNumber: FN Position /
sahilmgandhi	18:6a4db94011d3	27034	#define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) /!< USBH HcFmNumber: FN Mask /
sahilmgandhi	18:6a4db94011d3	27035
sahilmgandhi	18:6a4db94011d3	27036	#define USBH_HcPeriodicStart_PS_Pos (0) /!< USBH HcPeriodicStart: PS Position /
sahilmgandhi	18:6a4db94011d3	27037	#define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) /!< USBH HcPeriodicStart: PS Mask /
sahilmgandhi	18:6a4db94011d3	27038
sahilmgandhi	18:6a4db94011d3	27039	#define USBH_HcLSThreshold_LST_Pos (0) /!< USBH HcLSThreshold: LST Position /
sahilmgandhi	18:6a4db94011d3	27040	#define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) /!< USBH HcLSThreshold: LST Mask /
sahilmgandhi	18:6a4db94011d3	27041
sahilmgandhi	18:6a4db94011d3	27042	#define USBH_HcRhDescriptorA_NDP_Pos (0) /!< USBH HcRhDescriptorA: NDP Position /
sahilmgandhi	18:6a4db94011d3	27043	#define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) /!< USBH HcRhDescriptorA: NDP Mask /
sahilmgandhi	18:6a4db94011d3	27044
sahilmgandhi	18:6a4db94011d3	27045	#define USBH_HcRhDescriptorA_PSM_Pos (8) /!< USBH HcRhDescriptorA: PSM Position /
sahilmgandhi	18:6a4db94011d3	27046	#define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) /!< USBH HcRhDescriptorA: PSM Mask /
sahilmgandhi	18:6a4db94011d3	27047
sahilmgandhi	18:6a4db94011d3	27048	#define USBH_HcRhDescriptorA_NPS_Pos (9) /!< USBH HcRhDescriptorA: NPS Position /
sahilmgandhi	18:6a4db94011d3	27049	#define USBH_HcRhDescriptorA_NPS_Msk (0x1ul << USBH_HcRhDescriptorA_NPS_Pos) /!< USBH HcRhDescriptorA: NPS Mask /
sahilmgandhi	18:6a4db94011d3	27050
sahilmgandhi	18:6a4db94011d3	27051	#define USBH_HcRhDescriptorA_DT_Pos (10) /!< USBH HcRhDescriptorA: DT Position /
sahilmgandhi	18:6a4db94011d3	27052	#define USBH_HcRhDescriptorA_DT_Msk (0x1ul << USBH_HcRhDescriptorA_DT_Pos) /!< USBH HcRhDescriptorA: DT Mask /
sahilmgandhi	18:6a4db94011d3	27053
sahilmgandhi	18:6a4db94011d3	27054	#define USBH_HcRhDescriptorA_OCPM_Pos (11) /!< USBH HcRhDescriptorA: OCPM Position /
sahilmgandhi	18:6a4db94011d3	27055	#define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) /!< USBH HcRhDescriptorA: OCPM Mask /
sahilmgandhi	18:6a4db94011d3	27056
sahilmgandhi	18:6a4db94011d3	27057	#define USBH_HcRhDescriptorA_NOCP_Pos (12) /!< USBH HcRhDescriptorA: NOCP Position /
sahilmgandhi	18:6a4db94011d3	27058	#define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) /!< USBH HcRhDescriptorA: NOCP Mask /
sahilmgandhi	18:6a4db94011d3	27059
sahilmgandhi	18:6a4db94011d3	27060	#define USBH_HcRhDescriptorA_POTPGT_Pos (24) /!< USBH HcRhDescriptorA: POTPGT Position /
sahilmgandhi	18:6a4db94011d3	27061	#define USBH_HcRhDescriptorA_POTPGT_Msk (0xfful << USBH_HcRhDescriptorA_POTPGT_Pos) /!< USBH HcRhDescriptorA: POTPGT Mask /
sahilmgandhi	18:6a4db94011d3	27062
sahilmgandhi	18:6a4db94011d3	27063	#define USBH_HcRhDescriptorB_PPCM_Pos (16) /!< USBH HcRhDescriptorB: PPCM Position /
sahilmgandhi	18:6a4db94011d3	27064	#define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) /!< USBH HcRhDescriptorB: PPCM Mask /
sahilmgandhi	18:6a4db94011d3	27065
sahilmgandhi	18:6a4db94011d3	27066	#define USBH_HcRhStatus_LPS_Pos (0) /!< USBH HcRhStatus: LPS Position /
sahilmgandhi	18:6a4db94011d3	27067	#define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) /!< USBH HcRhStatus: LPS Mask /
sahilmgandhi	18:6a4db94011d3	27068
sahilmgandhi	18:6a4db94011d3	27069	#define USBH_HcRhStatus_OCI_Pos (1) /!< USBH HcRhStatus: OCI Position /
sahilmgandhi	18:6a4db94011d3	27070	#define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) /!< USBH HcRhStatus: OCI Mask /
sahilmgandhi	18:6a4db94011d3	27071
sahilmgandhi	18:6a4db94011d3	27072	#define USBH_HcRhStatus_DRWE_Pos (15) /!< USBH HcRhStatus: DRWE Position /
sahilmgandhi	18:6a4db94011d3	27073	#define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) /!< USBH HcRhStatus: DRWE Mask /
sahilmgandhi	18:6a4db94011d3	27074
sahilmgandhi	18:6a4db94011d3	27075	#define USBH_HcRhStatus_LPSC_Pos (16) /!< USBH HcRhStatus: LPSC Position /
sahilmgandhi	18:6a4db94011d3	27076	#define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) /!< USBH HcRhStatus: LPSC Mask /
sahilmgandhi	18:6a4db94011d3	27077
sahilmgandhi	18:6a4db94011d3	27078	#define USBH_HcRhStatus_OCIC_Pos (17) /!< USBH HcRhStatus: OCIC Position /
sahilmgandhi	18:6a4db94011d3	27079	#define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) /!< USBH HcRhStatus: OCIC Mask /
sahilmgandhi	18:6a4db94011d3	27080
sahilmgandhi	18:6a4db94011d3	27081	#define USBH_HcRhStatus_CRWE_Pos (31) /!< USBH HcRhStatus: CRWE Position /
sahilmgandhi	18:6a4db94011d3	27082	#define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) /!< USBH HcRhStatus: CRWE Mask /
sahilmgandhi	18:6a4db94011d3	27083
sahilmgandhi	18:6a4db94011d3	27084	#define USBH_HcRhPortStatus_CCS_Pos (0) /!< USBH HcRhPortStatus: CCS Position /
sahilmgandhi	18:6a4db94011d3	27085	#define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos) /!< USBH HcRhPortStatus: CCS Mask /
sahilmgandhi	18:6a4db94011d3	27086
sahilmgandhi	18:6a4db94011d3	27087	#define USBH_HcRhPortStatus_PES_Pos (1) /!< USBH HcRhPortStatus: PES Position /
sahilmgandhi	18:6a4db94011d3	27088	#define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos) /!< USBH HcRhPortStatus: PES Mask /
sahilmgandhi	18:6a4db94011d3	27089
sahilmgandhi	18:6a4db94011d3	27090	#define USBH_HcRhPortStatus_PSS_Pos (2) /!< USBH HcRhPortStatus: PSS Position /
sahilmgandhi	18:6a4db94011d3	27091	#define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos) /!< USBH HcRhPortStatus: PSS Mask /
sahilmgandhi	18:6a4db94011d3	27092
sahilmgandhi	18:6a4db94011d3	27093	#define USBH_HcRhPortStatus_POCI_Pos (3) /!< USBH HcRhPortStatus: POCI Position /
sahilmgandhi	18:6a4db94011d3	27094	#define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos) /!< USBH HcRhPortStatus: POCI Mask /
sahilmgandhi	18:6a4db94011d3	27095
sahilmgandhi	18:6a4db94011d3	27096	#define USBH_HcRhPortStatus_PRS_Pos (4) /!< USBH HcRhPortStatus: PRS Position /
sahilmgandhi	18:6a4db94011d3	27097	#define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos) /!< USBH HcRhPortStatus: PRS Mask /
sahilmgandhi	18:6a4db94011d3	27098
sahilmgandhi	18:6a4db94011d3	27099	#define USBH_HcRhPortStatus_PPS_Pos (8) /!< USBH HcRhPortStatus: PPS Position /
sahilmgandhi	18:6a4db94011d3	27100	#define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos) /!< USBH HcRhPortStatus: PPS Mask /
sahilmgandhi	18:6a4db94011d3	27101
sahilmgandhi	18:6a4db94011d3	27102	#define USBH_HcRhPortStatus_LSDA_Pos (9) /!< USBH HcRhPortStatus: LSDA Position /
sahilmgandhi	18:6a4db94011d3	27103	#define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos) /!< USBH HcRhPortStatus: LSDA Mask /
sahilmgandhi	18:6a4db94011d3	27104
sahilmgandhi	18:6a4db94011d3	27105	#define USBH_HcRhPortStatus_CSC_Pos (16) /!< USBH HcRhPortStatus: CSC Position /
sahilmgandhi	18:6a4db94011d3	27106	#define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos) /!< USBH HcRhPortStatus: CSC Mask /
sahilmgandhi	18:6a4db94011d3	27107
sahilmgandhi	18:6a4db94011d3	27108	#define USBH_HcRhPortStatus_PESC_Pos (17) /!< USBH HcRhPortStatus: PESC Position /
sahilmgandhi	18:6a4db94011d3	27109	#define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos) /!< USBH HcRhPortStatus: PESC Mask /
sahilmgandhi	18:6a4db94011d3	27110
sahilmgandhi	18:6a4db94011d3	27111	#define USBH_HcRhPortStatus_PSSC_Pos (18) /!< USBH HcRhPortStatus: PSSC Position /
sahilmgandhi	18:6a4db94011d3	27112	#define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos) /!< USBH HcRhPortStatus: PSSC Mask /
sahilmgandhi	18:6a4db94011d3	27113
sahilmgandhi	18:6a4db94011d3	27114	#define USBH_HcRhPortStatus_OCIC_Pos (19) /!< USBH HcRhPortStatus: OCIC Position /
sahilmgandhi	18:6a4db94011d3	27115	#define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos) /!< USBH HcRhPortStatus: OCIC Mask /
sahilmgandhi	18:6a4db94011d3	27116
sahilmgandhi	18:6a4db94011d3	27117	#define USBH_HcRhPortStatus_PRSC_Pos (20) /!< USBH HcRhPortStatus: PRSC Position /
sahilmgandhi	18:6a4db94011d3	27118	#define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos) /!< USBH HcRhPortStatus: PRSC Mask /
sahilmgandhi	18:6a4db94011d3	27119
sahilmgandhi	18:6a4db94011d3	27120	#define USBH_HcPhyControl_STBYEN_Pos (27) /!< USBH HcPhyControl: STBYEN Position /
sahilmgandhi	18:6a4db94011d3	27121	#define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) /!< USBH HcPhyControl: STBYEN Mask /
sahilmgandhi	18:6a4db94011d3	27122
sahilmgandhi	18:6a4db94011d3	27123	#define USBH_HcMiscControl_DBR16_Pos (0) /!< USBH HcMiscControl: DBR16 Position /
sahilmgandhi	18:6a4db94011d3	27124	#define USBH_HcMiscControl_DBR16_Msk (0x1ul << USBH_HcMiscControl_DBR16_Pos) /!< USBH HcMiscControl: DBR16 Mask /
sahilmgandhi	18:6a4db94011d3	27125
sahilmgandhi	18:6a4db94011d3	27126	#define USBH_HcMiscControl_ABORT_Pos (1) /!< USBH HcMiscControl: ABORT Position /
sahilmgandhi	18:6a4db94011d3	27127	#define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos) /!< USBH HcMiscControl: ABORT Mask /
sahilmgandhi	18:6a4db94011d3	27128
sahilmgandhi	18:6a4db94011d3	27129	#define USBH_HcMiscControl_OCAL_Pos (3) /!< USBH HcMiscControl: OCAL Position /
sahilmgandhi	18:6a4db94011d3	27130	#define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos) /!< USBH HcMiscControl: OCAL Mask /
sahilmgandhi	18:6a4db94011d3	27131
sahilmgandhi	18:6a4db94011d3	27132	#define USBH_HcMiscControl_PCAL_Pos (4) /!< USBH HcMiscControl: PCAL Position /
sahilmgandhi	18:6a4db94011d3	27133	#define USBH_HcMiscControl_PCAL_Msk (0x1ul << USBH_HcMiscControl_PCAL_Pos) /!< USBH HcMiscControl: PCAL Mask /
sahilmgandhi	18:6a4db94011d3	27134
sahilmgandhi	18:6a4db94011d3	27135	#define USBH_HcMiscControl_SIEPD_Pos (8) /!< USBH HcMiscControl: SIEPD Position /
sahilmgandhi	18:6a4db94011d3	27136	#define USBH_HcMiscControl_SIEPD_Msk (0x1ul << USBH_HcMiscControl_SIEPD_Pos) /!< USBH HcMiscControl: SIEPD Mask /
sahilmgandhi	18:6a4db94011d3	27137
sahilmgandhi	18:6a4db94011d3	27138	#define USBH_HcMiscControl_DPRT1_Pos (16) /!< USBH HcMiscControl: DPRT1 Position /
sahilmgandhi	18:6a4db94011d3	27139	#define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos) /!< USBH HcMiscControl: DPRT1 Mask /
sahilmgandhi	18:6a4db94011d3	27140
sahilmgandhi	18:6a4db94011d3	27141	#define USBH_HcMiscControl_DPRT2_Pos (17) /!< USBH HcMiscControl: DPRT2 Position /
sahilmgandhi	18:6a4db94011d3	27142	#define USBH_HcMiscControl_DPRT2_Msk (0x1ul << USBH_HcMiscControl_DPRT2_Pos) /!< USBH HcMiscControl: DPRT2 Mask /
sahilmgandhi	18:6a4db94011d3	27143
sahilmgandhi	18:6a4db94011d3	27144	/*@}/ /* USBH_CONST */
sahilmgandhi	18:6a4db94011d3	27145	/*@}/ /* end of USBH register group */
sahilmgandhi	18:6a4db94011d3	27146
sahilmgandhi	18:6a4db94011d3	27147
sahilmgandhi	18:6a4db94011d3	27148	/---------------------- USB Device Controller -------------------------/
sahilmgandhi	18:6a4db94011d3	27149	/**
sahilmgandhi	18:6a4db94011d3	27150	@addtogroup USBD USB Device Controller(USBD)
sahilmgandhi	18:6a4db94011d3	27151	Memory Mapped Structure for USBD Controller
sahilmgandhi	18:6a4db94011d3	27152	@{ */
sahilmgandhi	18:6a4db94011d3	27153
sahilmgandhi	18:6a4db94011d3	27154	typedef struct {
sahilmgandhi	18:6a4db94011d3	27155
sahilmgandhi	18:6a4db94011d3	27156
sahilmgandhi	18:6a4db94011d3	27157	/**
sahilmgandhi	18:6a4db94011d3	27158	* GINTSTS
sahilmgandhi	18:6a4db94011d3	27159	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27160	* Offset: 0x00 Interrupt Status Low Register
sahilmgandhi	18:6a4db94011d3	27161	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27162	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27163	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27164	* \|[0] \|USBIF \|USB Interrupt
sahilmgandhi	18:6a4db94011d3	27165	* \| \| \|This bit conveys the interrupt status for USB specific events endpoint.
sahilmgandhi	18:6a4db94011d3	27166	* \| \| \|When set, USB interrupt status register should be read to determine the cause of the interrupt.
sahilmgandhi	18:6a4db94011d3	27167	* \| \| \|0 = No interrupt event occurred.
sahilmgandhi	18:6a4db94011d3	27168	* \| \| \|1 = The related interrupt event is occurred.
sahilmgandhi	18:6a4db94011d3	27169	* \|[1] \|CEPIF \|Control Endpoint Interrupt
sahilmgandhi	18:6a4db94011d3	27170	* \| \| \|This bit conveys the interrupt status for control endpoint.
sahilmgandhi	18:6a4db94011d3	27171	* \| \| \|When set, Control-ep's interrupt status register should be read to determine the cause of the interrupt.
sahilmgandhi	18:6a4db94011d3	27172	* \| \| \|0 = No interrupt event occurred.
sahilmgandhi	18:6a4db94011d3	27173	* \| \| \|1 = The related interrupt event is occurred.
sahilmgandhi	18:6a4db94011d3	27174	* \|[2] \|EPAIF \|Endpoints A Interrupt
sahilmgandhi	18:6a4db94011d3	27175	* \| \| \|When set, the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt.
sahilmgandhi	18:6a4db94011d3	27176	* \| \| \|0 = No interrupt event occurred.
sahilmgandhi	18:6a4db94011d3	27177	* \| \| \|1 = The related interrupt event is occurred.
sahilmgandhi	18:6a4db94011d3	27178	* \|[3] \|EPBIF \|Endpoints B Interrupt
sahilmgandhi	18:6a4db94011d3	27179	* \| \| \|When set, the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt.
sahilmgandhi	18:6a4db94011d3	27180	* \| \| \|0 = No interrupt event occurred.
sahilmgandhi	18:6a4db94011d3	27181	* \| \| \|1 = The related interrupt event is occurred.
sahilmgandhi	18:6a4db94011d3	27182	* \|[4] \|EPCIF \|Endpoints C Interrupt
sahilmgandhi	18:6a4db94011d3	27183	* \| \| \|When set, the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt.
sahilmgandhi	18:6a4db94011d3	27184	* \| \| \|0 = No interrupt event occurred.
sahilmgandhi	18:6a4db94011d3	27185	* \| \| \|1 = The related interrupt event is occurred.
sahilmgandhi	18:6a4db94011d3	27186	* \|[5] \|EPDIF \|Endpoints D Interrupt
sahilmgandhi	18:6a4db94011d3	27187	* \| \| \|When set, the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt.
sahilmgandhi	18:6a4db94011d3	27188	* \| \| \|0 = No interrupt event occurred.
sahilmgandhi	18:6a4db94011d3	27189	* \| \| \|1 = The related interrupt event is occurred.
sahilmgandhi	18:6a4db94011d3	27190	* \|[6] \|EPEIF \|Endpoints E Interrupt
sahilmgandhi	18:6a4db94011d3	27191	* \| \| \|When set, the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt.
sahilmgandhi	18:6a4db94011d3	27192	* \| \| \|0 = No interrupt event occurred.
sahilmgandhi	18:6a4db94011d3	27193	* \| \| \|1 = The related interrupt event is occurred.
sahilmgandhi	18:6a4db94011d3	27194	* \|[7] \|EPFIF \|Endpoints F Interrupt
sahilmgandhi	18:6a4db94011d3	27195	* \| \| \|When set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt.
sahilmgandhi	18:6a4db94011d3	27196	* \| \| \|0 = No interrupt event occurred.
sahilmgandhi	18:6a4db94011d3	27197	* \| \| \|1 = The related interrupt event is occurred.
sahilmgandhi	18:6a4db94011d3	27198	* \|[8] \|EPGIF \|Endpoints G Interrupt
sahilmgandhi	18:6a4db94011d3	27199	* \| \| \|When set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt.
sahilmgandhi	18:6a4db94011d3	27200	* \| \| \|0 = No interrupt event occurred.
sahilmgandhi	18:6a4db94011d3	27201	* \| \| \|1 = The related interrupt event is occurred.
sahilmgandhi	18:6a4db94011d3	27202	* \|[9] \|EPHIF \|Endpoints H Interrupt
sahilmgandhi	18:6a4db94011d3	27203	* \| \| \|When set, the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt.
sahilmgandhi	18:6a4db94011d3	27204	* \| \| \|0 = No interrupt event occurred.
sahilmgandhi	18:6a4db94011d3	27205	* \| \| \|1 = The related interrupt event is occurred.
sahilmgandhi	18:6a4db94011d3	27206	* \|[10] \|EPIIF \|Endpoints I Interrupt
sahilmgandhi	18:6a4db94011d3	27207	* \| \| \|When set, the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt.
sahilmgandhi	18:6a4db94011d3	27208	* \| \| \|0 = No interrupt event occurred.
sahilmgandhi	18:6a4db94011d3	27209	* \| \| \|1 = The related interrupt event is occurred.
sahilmgandhi	18:6a4db94011d3	27210	* \|[11] \|EPJIF \|Endpoints J Interrupt
sahilmgandhi	18:6a4db94011d3	27211	* \| \| \|When set, the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt.
sahilmgandhi	18:6a4db94011d3	27212	* \| \| \|0 = No interrupt event occurred.
sahilmgandhi	18:6a4db94011d3	27213	* \| \| \|1 = The related interrupt event is occurred.
sahilmgandhi	18:6a4db94011d3	27214	* \|[12] \|EPKIF \|Endpoints K Interrupt
sahilmgandhi	18:6a4db94011d3	27215	* \| \| \|When set, the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt.
sahilmgandhi	18:6a4db94011d3	27216	* \| \| \|0 = No interrupt event occurred.
sahilmgandhi	18:6a4db94011d3	27217	* \| \| \|1 = The related interrupt event is occurred.
sahilmgandhi	18:6a4db94011d3	27218	* \|[13] \|EPLIF \|Endpoints L Interrupt
sahilmgandhi	18:6a4db94011d3	27219	* \| \| \|When set, the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt.
sahilmgandhi	18:6a4db94011d3	27220	* \| \| \|0 = No interrupt event occurred.
sahilmgandhi	18:6a4db94011d3	27221	* \| \| \|1 = The related interrupt event is occurred.
sahilmgandhi	18:6a4db94011d3	27222	*/
sahilmgandhi	18:6a4db94011d3	27223	__I uint32_t GINTSTS;
sahilmgandhi	18:6a4db94011d3	27224	uint32_t RESERVE0[1];
sahilmgandhi	18:6a4db94011d3	27225
sahilmgandhi	18:6a4db94011d3	27226
sahilmgandhi	18:6a4db94011d3	27227	/**
sahilmgandhi	18:6a4db94011d3	27228	* GINTEN
sahilmgandhi	18:6a4db94011d3	27229	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27230	* Offset: 0x08 Interrupt Enable Low Register
sahilmgandhi	18:6a4db94011d3	27231	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27232	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27233	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27234	* \|[0] \|USBIE \|USB Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	27235	* \| \| \|When set, this bit enables a local interrupt to be generated when a USB event occurs on the bus.
sahilmgandhi	18:6a4db94011d3	27236	* \| \| \|0 = The related interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27237	* \| \| \|1 = The related interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27238	* \|[1] \|CEPIE \|Control Endpoint Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	27239	* \| \| \|When set, this bit enables a local interrupt to be generated when an interrupt is pending for the control endpoint.
sahilmgandhi	18:6a4db94011d3	27240	* \| \| \|0 = The related interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27241	* \| \| \|1 = The related interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27242	* \|[2] \|EPAIE \|Interrupt Enable Control For Endpoint A
sahilmgandhi	18:6a4db94011d3	27243	* \| \| \|When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint A.
sahilmgandhi	18:6a4db94011d3	27244	* \| \| \|0 = The related interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27245	* \| \| \|1 = The related interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27246	* \|[3] \|EPBIE \|Interrupt Enable Control For Endpoint B
sahilmgandhi	18:6a4db94011d3	27247	* \| \| \|When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint B
sahilmgandhi	18:6a4db94011d3	27248	* \| \| \|0 = The related interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27249	* \| \| \|1 = The related interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27250	* \|[4] \|EPCIE \|Interrupt Enable Control For Endpoint C
sahilmgandhi	18:6a4db94011d3	27251	* \| \| \|When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint C
sahilmgandhi	18:6a4db94011d3	27252	* \| \| \|0 = The related interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27253	* \| \| \|1 = The related interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27254	* \|[5] \|EPDIE \|Interrupt Enable Control For Endpoint D
sahilmgandhi	18:6a4db94011d3	27255	* \| \| \|When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint D
sahilmgandhi	18:6a4db94011d3	27256	* \| \| \|0 = The related interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27257	* \| \| \|1 = The related interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27258	* \|[6] \|EPEIE \|Interrupt Enable Control For Endpoint E
sahilmgandhi	18:6a4db94011d3	27259	* \| \| \|When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint E
sahilmgandhi	18:6a4db94011d3	27260	* \| \| \|0 = The related interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27261	* \| \| \|1 = The related interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27262	* \|[7] \|EPFIE \|Interrupt Enable Control For Endpoint F
sahilmgandhi	18:6a4db94011d3	27263	* \| \| \|When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint F
sahilmgandhi	18:6a4db94011d3	27264	* \| \| \|0 = The related interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27265	* \| \| \|1 = The related interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27266	* \|[8] \|EPGIE \|Interrupt Enable Control For Endpoint G
sahilmgandhi	18:6a4db94011d3	27267	* \| \| \|When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint G
sahilmgandhi	18:6a4db94011d3	27268	* \| \| \|0 = The related interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27269	* \| \| \|1 = The related interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27270	* \|[9] \|EPHIE \|Interrupt Enable Control For Endpoint H
sahilmgandhi	18:6a4db94011d3	27271	* \| \| \|When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint H
sahilmgandhi	18:6a4db94011d3	27272	* \| \| \|0 = The related interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27273	* \| \| \|1 = The related interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27274	* \|[10] \|EPIIE \|Interrupt Enable Control For Endpoint I
sahilmgandhi	18:6a4db94011d3	27275	* \| \| \|When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint I
sahilmgandhi	18:6a4db94011d3	27276	* \| \| \|0 = The related interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27277	* \| \| \|1 = The related interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27278	* \|[11] \|EPJIE \|Interrupt Enable Control For Endpoint J
sahilmgandhi	18:6a4db94011d3	27279	* \| \| \|When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint J
sahilmgandhi	18:6a4db94011d3	27280	* \| \| \|0 = The related interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27281	* \| \| \|1 = The related interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27282	* \|[12] \|EPKIE \|Interrupt Enable Control For Endpoint K
sahilmgandhi	18:6a4db94011d3	27283	* \| \| \|When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint K
sahilmgandhi	18:6a4db94011d3	27284	* \| \| \|0 = The related interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27285	* \| \| \|1 = The related interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27286	* \|[13] \|EPLIE \|Interrupt Enable Control For Endpoint L
sahilmgandhi	18:6a4db94011d3	27287	* \| \| \|When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint L
sahilmgandhi	18:6a4db94011d3	27288	* \| \| \|0 = The related interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27289	* \| \| \|1 = The related interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27290	*/
sahilmgandhi	18:6a4db94011d3	27291	__IO uint32_t GINTEN;
sahilmgandhi	18:6a4db94011d3	27292	uint32_t RESERVE1[1];
sahilmgandhi	18:6a4db94011d3	27293
sahilmgandhi	18:6a4db94011d3	27294
sahilmgandhi	18:6a4db94011d3	27295	/**
sahilmgandhi	18:6a4db94011d3	27296	* BUSINTSTS
sahilmgandhi	18:6a4db94011d3	27297	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27298	* Offset: 0x10 USB Bus Interrupt Status Register
sahilmgandhi	18:6a4db94011d3	27299	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27300	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27301	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27302	* \|[0] \|SOFIF \|SOF Receive Control
sahilmgandhi	18:6a4db94011d3	27303	* \| \| \|This bit indicates when a start-of-frame packet has been received.
sahilmgandhi	18:6a4db94011d3	27304	* \| \| \|0 = No start-of-frame packet has been received.
sahilmgandhi	18:6a4db94011d3	27305	* \| \| \|1 = Start-of-frame packet has been received.
sahilmgandhi	18:6a4db94011d3	27306	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27307	* \|[1] \|RSTIF \|Reset Status
sahilmgandhi	18:6a4db94011d3	27308	* \| \| \|When set, this bit indicates that either the USB root port reset is end.
sahilmgandhi	18:6a4db94011d3	27309	* \| \| \|0 = No USB root port reset is end.
sahilmgandhi	18:6a4db94011d3	27310	* \| \| \|1 = USB root port reset is end.
sahilmgandhi	18:6a4db94011d3	27311	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27312	* \|[2] \|RESUMEIF \|Resume
sahilmgandhi	18:6a4db94011d3	27313	* \| \| \|When set, this bit indicates that a device resume has occurred.
sahilmgandhi	18:6a4db94011d3	27314	* \| \| \|0 = No device resume has occurred.
sahilmgandhi	18:6a4db94011d3	27315	* \| \| \|1 = Device resume has occurred.
sahilmgandhi	18:6a4db94011d3	27316	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27317	* \|[3] \|SUSPENDIF \|Suspend Request
sahilmgandhi	18:6a4db94011d3	27318	* \| \| \|This bit is set as default and it has to be cleared by writing '1' before the USB reset.
sahilmgandhi	18:6a4db94011d3	27319	* \| \| \|This bit is also set when a USB Suspend request is detected from the host.
sahilmgandhi	18:6a4db94011d3	27320	* \| \| \|0 = No USB Suspend request is detected from the host.
sahilmgandhi	18:6a4db94011d3	27321	* \| \| \|1= USB Suspend request is detected from the host.
sahilmgandhi	18:6a4db94011d3	27322	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27323	* \|[4] \|HISPDIF \|High-Speed Settle
sahilmgandhi	18:6a4db94011d3	27324	* \| \| \|0 = No valid high-speed reset protocol is detected.
sahilmgandhi	18:6a4db94011d3	27325	* \| \| \|1 = Valid high-speed reset protocol is over and the device has settled in high-speed.
sahilmgandhi	18:6a4db94011d3	27326	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27327	* \|[5] \|DMADONEIF \|DMA Completion Interrupt
sahilmgandhi	18:6a4db94011d3	27328	* \| \| \|0 = No DMA transfer over.
sahilmgandhi	18:6a4db94011d3	27329	* \| \| \|1 = DMA transfer is over.
sahilmgandhi	18:6a4db94011d3	27330	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27331	* \|[6] \|PHYCLKVLDIF\|Usable Clock Interrupt
sahilmgandhi	18:6a4db94011d3	27332	* \| \| \|0 = Usable clock is not available.
sahilmgandhi	18:6a4db94011d3	27333	* \| \| \|1 = Usable clock is available from the transceiver.
sahilmgandhi	18:6a4db94011d3	27334	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27335	* \|[8] \|VBUSDETIF \|VBUS Detection Interrupt Status
sahilmgandhi	18:6a4db94011d3	27336	* \| \| \|0 = No VBUS is plug-in.
sahilmgandhi	18:6a4db94011d3	27337	* \| \| \|1 = VBUS is plug-in.
sahilmgandhi	18:6a4db94011d3	27338	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27339	*/
sahilmgandhi	18:6a4db94011d3	27340	__IO uint32_t BUSINTSTS;
sahilmgandhi	18:6a4db94011d3	27341
sahilmgandhi	18:6a4db94011d3	27342	/**
sahilmgandhi	18:6a4db94011d3	27343	* BUSINTEN
sahilmgandhi	18:6a4db94011d3	27344	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27345	* Offset: 0x14 USB Bus Interrupt Enable Register
sahilmgandhi	18:6a4db94011d3	27346	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27347	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27348	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27349	* \|[0] \|SOFIEN \|SOF Interrupt
sahilmgandhi	18:6a4db94011d3	27350	* \| \| \|This bit enables the SOF interrupt.
sahilmgandhi	18:6a4db94011d3	27351	* \| \| \|0 = SOF interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27352	* \| \| \|1 = SOF interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27353	* \|[1] \|RSTIEN \|Reset Status
sahilmgandhi	18:6a4db94011d3	27354	* \| \| \|This bit enables the USB-Reset interrupt.
sahilmgandhi	18:6a4db94011d3	27355	* \| \| \|0 = USB-Reset interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27356	* \| \| \|1 = USB-Reset interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27357	* \|[2] \|RESUMEIEN \|Resume
sahilmgandhi	18:6a4db94011d3	27358	* \| \| \|This bit enables the Resume interrupt.
sahilmgandhi	18:6a4db94011d3	27359	* \| \| \|0 = Resume interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27360	* \| \| \|1 = Resume interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27361	* \|[3] \|SUSPENDIEN\|Suspend Request
sahilmgandhi	18:6a4db94011d3	27362	* \| \| \|This bit enables the Suspend interrupt.
sahilmgandhi	18:6a4db94011d3	27363	* \| \| \|0 = Suspend interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27364	* \| \| \|1 = Suspend interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27365	* \|[4] \|HISPDIEN \|High-Speed Settle
sahilmgandhi	18:6a4db94011d3	27366	* \| \| \|This bit enables the high-speed settle interrupt.
sahilmgandhi	18:6a4db94011d3	27367	* \| \| \|0 = High-speed settle interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27368	* \| \| \|1 = High-speed settle interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27369	* \|[5] \|DMADONEIEN\|DMA Completion Interrupt
sahilmgandhi	18:6a4db94011d3	27370	* \| \| \|This bit enables the DMA completion interrupt
sahilmgandhi	18:6a4db94011d3	27371	* \| \| \|0 = DMA completion interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27372	* \| \| \|1 = DMA completion interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27373	* \|[6] \|PHYCLKVLDIEN\|Usable Clock Interrupt
sahilmgandhi	18:6a4db94011d3	27374	* \| \| \|This bit enables the usable clock interrupt.
sahilmgandhi	18:6a4db94011d3	27375	* \| \| \|0 = Usable clock interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27376	* \| \| \|1 = Usable clock interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27377	* \|[8] \|VBUSDETIEN\|VBUS Detection Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	27378	* \| \| \|This bit enables the VBUS floating detection interrupt.
sahilmgandhi	18:6a4db94011d3	27379	* \| \| \|0 = VBUS floating detection interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27380	* \| \| \|1 = VBUS floating detection interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27381	*/
sahilmgandhi	18:6a4db94011d3	27382	__IO uint32_t BUSINTEN;
sahilmgandhi	18:6a4db94011d3	27383
sahilmgandhi	18:6a4db94011d3	27384	/**
sahilmgandhi	18:6a4db94011d3	27385	* OPER
sahilmgandhi	18:6a4db94011d3	27386	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27387	* Offset: 0x18 USB Operational Register
sahilmgandhi	18:6a4db94011d3	27388	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27389	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27390	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27391	* \|[0] \|RESUMEEN \|Generate Resume
sahilmgandhi	18:6a4db94011d3	27392	* \| \| \|0 = No Resume sequence to be initiated to the host.
sahilmgandhi	18:6a4db94011d3	27393	* \| \| \|1 = A Resume sequence to be initiated to the host if device remote wakeup is enabled.
sahilmgandhi	18:6a4db94011d3	27394	* \| \| \|This bit is self-clearing.
sahilmgandhi	18:6a4db94011d3	27395	* \|[1] \|HISPDEN \|USB High-Speed
sahilmgandhi	18:6a4db94011d3	27396	* \| \| \|0 = The USB device controller to suppress the chirp-sequence during reset protocol, thereby allowing the USB device controller to settle in full-speed, even though it is connected to a USB2.0 Host.
sahilmgandhi	18:6a4db94011d3	27397	* \| \| \|1 = The USB device controller to initiate a chirp-sequence during reset protocol.
sahilmgandhi	18:6a4db94011d3	27398	* \|[2] \|CURSPD \|USB Current Speed
sahilmgandhi	18:6a4db94011d3	27399	* \| \| \|0 = The device has settled in Full Speed.
sahilmgandhi	18:6a4db94011d3	27400	* \| \| \|1 = The USB device controller has settled in High-speed.
sahilmgandhi	18:6a4db94011d3	27401	*/
sahilmgandhi	18:6a4db94011d3	27402	__IO uint32_t OPER;
sahilmgandhi	18:6a4db94011d3	27403
sahilmgandhi	18:6a4db94011d3	27404	/**
sahilmgandhi	18:6a4db94011d3	27405	* FRAMECNT
sahilmgandhi	18:6a4db94011d3	27406	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27407	* Offset: 0x1C USB Frame Count Register
sahilmgandhi	18:6a4db94011d3	27408	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27409	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27410	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27411	* \|[0:2] \|MFRAMECNT \|Micro-Frame Counter
sahilmgandhi	18:6a4db94011d3	27412	* \| \| \|This field contains the micro-frame number for the frame number in the frame counter field.
sahilmgandhi	18:6a4db94011d3	27413	* \|[3:13] \|FRAMECNT \|Frame Counter
sahilmgandhi	18:6a4db94011d3	27414	* \| \| \|This field contains the frame count from the most recent start-of-frame packet.
sahilmgandhi	18:6a4db94011d3	27415	*/
sahilmgandhi	18:6a4db94011d3	27416	__I uint32_t FRAMECNT;
sahilmgandhi	18:6a4db94011d3	27417
sahilmgandhi	18:6a4db94011d3	27418	/**
sahilmgandhi	18:6a4db94011d3	27419	* FADDR
sahilmgandhi	18:6a4db94011d3	27420	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27421	* Offset: 0x20 USB Function Address Register
sahilmgandhi	18:6a4db94011d3	27422	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27423	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27424	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27425	* \|[0:6] \|FADDR \|USB Function Address
sahilmgandhi	18:6a4db94011d3	27426	* \| \| \|This field contains the current USB address of the device.
sahilmgandhi	18:6a4db94011d3	27427	* \| \| \|This field is cleared when a root port reset is detected.
sahilmgandhi	18:6a4db94011d3	27428	*/
sahilmgandhi	18:6a4db94011d3	27429	__IO uint32_t FADDR;
sahilmgandhi	18:6a4db94011d3	27430
sahilmgandhi	18:6a4db94011d3	27431	/**
sahilmgandhi	18:6a4db94011d3	27432	* TEST
sahilmgandhi	18:6a4db94011d3	27433	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27434	* Offset: 0x24 USB Test Mode Register
sahilmgandhi	18:6a4db94011d3	27435	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27436	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27437	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27438	* \|[0:2] \|TESTMODE \|Test Mode Selection
sahilmgandhi	18:6a4db94011d3	27439	* \| \| \|000 = Normal Operation.
sahilmgandhi	18:6a4db94011d3	27440	* \| \| \|001 = Test_J.
sahilmgandhi	18:6a4db94011d3	27441	* \| \| \|010 = Test_K.
sahilmgandhi	18:6a4db94011d3	27442	* \| \| \|011 = Test_SE0_NAK.
sahilmgandhi	18:6a4db94011d3	27443	* \| \| \|100 = Test_Packet.
sahilmgandhi	18:6a4db94011d3	27444	* \| \| \|101 = Test_Force_Enable.
sahilmgandhi	18:6a4db94011d3	27445	* \| \| \|110 = Reserved.
sahilmgandhi	18:6a4db94011d3	27446	* \| \| \|111 = Reserved.
sahilmgandhi	18:6a4db94011d3	27447	* \| \| \|Note: This field is cleared when root port reset is detected.
sahilmgandhi	18:6a4db94011d3	27448	*/
sahilmgandhi	18:6a4db94011d3	27449	__IO uint32_t TEST;
sahilmgandhi	18:6a4db94011d3	27450
sahilmgandhi	18:6a4db94011d3	27451	union {
sahilmgandhi	18:6a4db94011d3	27452
sahilmgandhi	18:6a4db94011d3	27453	/**
sahilmgandhi	18:6a4db94011d3	27454	* CEPDAT
sahilmgandhi	18:6a4db94011d3	27455	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27456	* Offset: 0x28 Control-Endpoint Data Buffer
sahilmgandhi	18:6a4db94011d3	27457	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27458	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27459	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27460	* \|[0:31] \|DAT \|Control-Endpoint Data Buffer
sahilmgandhi	18:6a4db94011d3	27461	* \| \| \|Control endpoint data buffer for the buffer transaction (read or write).
sahilmgandhi	18:6a4db94011d3	27462	* \| \| \|Note: Only word or byte access are supported.
sahilmgandhi	18:6a4db94011d3	27463	*/
sahilmgandhi	18:6a4db94011d3	27464	__IO uint32_t CEPDAT;
sahilmgandhi	18:6a4db94011d3	27465	/**
sahilmgandhi	18:6a4db94011d3	27466	* CEPDAT_BYTE
sahilmgandhi	18:6a4db94011d3	27467	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27468	* Offset: 0x28 Control-Endpoint Data Buffer for Byte Access
sahilmgandhi	18:6a4db94011d3	27469	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27470	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27471	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27472	* \|[0:7] \|DAT \|Control-Endpoint Data Buffer
sahilmgandhi	18:6a4db94011d3	27473	* \| \| \|Control endpoint data buffer for the buffer transaction (read or write).
sahilmgandhi	18:6a4db94011d3	27474	* \| \| \|Note: Only word or byte access are supported.
sahilmgandhi	18:6a4db94011d3	27475	*/
sahilmgandhi	18:6a4db94011d3	27476	__IO uint8_t CEPDAT_BYTE;
sahilmgandhi	18:6a4db94011d3	27477
sahilmgandhi	18:6a4db94011d3	27478	};///< Define Control-Endpoint Data Register 32-bit or 8-bit access
sahilmgandhi	18:6a4db94011d3	27479
sahilmgandhi	18:6a4db94011d3	27480	/**
sahilmgandhi	18:6a4db94011d3	27481	* CEPCTL
sahilmgandhi	18:6a4db94011d3	27482	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27483	* Offset: 0x2C Control-Endpoint Control and Status
sahilmgandhi	18:6a4db94011d3	27484	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27485	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27486	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27487	* \|[0] \|NAKCLR \|No Acknowledge Control
sahilmgandhi	18:6a4db94011d3	27488	* \| \| \|This bit plays a crucial role in any control transfer.
sahilmgandhi	18:6a4db94011d3	27489	* \| \| \|0 = The bit is being cleared by the local CPU by writing zero, the USB device controller will be responding with NAKs for the subsequent status phase.
sahilmgandhi	18:6a4db94011d3	27490	* \| \| \|This mechanism holds the host from moving to the next request, until the local CPU is also ready to process the next request.
sahilmgandhi	18:6a4db94011d3	27491	* \| \| \|1 = This bit is set to one by the USB device controller, whenever a setup token is received.
sahilmgandhi	18:6a4db94011d3	27492	* \| \| \|The local CPU can take its own time to finish off any house-keeping work based on the request and then clear this bit.
sahilmgandhi	18:6a4db94011d3	27493	* \| \| \|Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated.
sahilmgandhi	18:6a4db94011d3	27494	* \|[1] \|STALLEN \|Stall Enable Control
sahilmgandhi	18:6a4db94011d3	27495	* \| \| \|When this stall bit is set, the control endpoint sends a stall handshake in response to any in or out token thereafter.
sahilmgandhi	18:6a4db94011d3	27496	* \| \| \|This is typically used for response to invalid/unsupported requests.
sahilmgandhi	18:6a4db94011d3	27497	* \| \| \|When this bit is being set the NAK clear bit has to be cleared at the same time since the NAK clear bit has highest priority than STALL.
sahilmgandhi	18:6a4db94011d3	27498	* \| \| \|It is automatically cleared on receipt of a next setup-token.
sahilmgandhi	18:6a4db94011d3	27499	* \| \| \|So, the local CPU need not write again to clear this bit.
sahilmgandhi	18:6a4db94011d3	27500	* \| \| \|0 = No sends a stall handshake in response to any in or out token thereafter.
sahilmgandhi	18:6a4db94011d3	27501	* \| \| \|1 = The control endpoint sends a stall handshake in response to any in or out token thereafter.
sahilmgandhi	18:6a4db94011d3	27502	* \| \| \|Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated.
sahilmgandhi	18:6a4db94011d3	27503	* \|[2] \|ZEROLEN \|Zero Packet Length
sahilmgandhi	18:6a4db94011d3	27504	* \| \| \|This bit is valid for Auto Validation mode only.
sahilmgandhi	18:6a4db94011d3	27505	* \| \| \|0 = No zero length packet to the host during Data stage to an IN token.
sahilmgandhi	18:6a4db94011d3	27506	* \| \| \|1 = USB device controller can send a zero length packet to the host during Data stage to an IN token.
sahilmgandhi	18:6a4db94011d3	27507	* \| \| \|This bit gets cleared once the zero length data packet is sent.
sahilmgandhi	18:6a4db94011d3	27508	* \| \| \|So, the local CPU need not write again to clear this bit.
sahilmgandhi	18:6a4db94011d3	27509	* \|[3] \|FLUSH \|CEP-FLUSH Bit
sahilmgandhi	18:6a4db94011d3	27510	* \| \| \|0 = No the packet buffer and its corresponding USBD_CEPDATCNT register to be cleared.
sahilmgandhi	18:6a4db94011d3	27511	* \| \| \|1 = The packet buffer and its corresponding USBD_CEPDATCNT register to be cleared.
sahilmgandhi	18:6a4db94011d3	27512	* \| \| \|This bit is self-cleaning.
sahilmgandhi	18:6a4db94011d3	27513	*/
sahilmgandhi	18:6a4db94011d3	27514	__IO uint32_t CEPCTL;
sahilmgandhi	18:6a4db94011d3	27515
sahilmgandhi	18:6a4db94011d3	27516	/**
sahilmgandhi	18:6a4db94011d3	27517	* CEPINTEN
sahilmgandhi	18:6a4db94011d3	27518	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27519	* Offset: 0x30 Control-Endpoint Interrupt Enable
sahilmgandhi	18:6a4db94011d3	27520	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27521	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27522	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27523	* \|[0] \|SETUPTKIEN\|Setup Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	27524	* \| \| \|0 = The SETUP token interrupt in Control Endpoint Disabled.
sahilmgandhi	18:6a4db94011d3	27525	* \| \| \|1 = The SETUP token interrupt in Control Endpoint Enabled.
sahilmgandhi	18:6a4db94011d3	27526	* \|[1] \|SETUPPKIEN\|Setup Packet Interrupt
sahilmgandhi	18:6a4db94011d3	27527	* \| \| \|0 = The SETUP packet interrupt in Control Endpoint Disabled.
sahilmgandhi	18:6a4db94011d3	27528	* \| \| \|1 = The SETUP packet interrupt in Control Endpoint Enabled.
sahilmgandhi	18:6a4db94011d3	27529	* \|[2] \|OUTTKIEN \|Out Token Interrupt
sahilmgandhi	18:6a4db94011d3	27530	* \| \| \|0 = The OUT token interrupt in Control Endpoint Disabled.
sahilmgandhi	18:6a4db94011d3	27531	* \| \| \|1 = The OUT token interrupt in Control Endpoint Enabled.
sahilmgandhi	18:6a4db94011d3	27532	* \|[3] \|INTKIEN \|In Token Interrupt
sahilmgandhi	18:6a4db94011d3	27533	* \| \| \|0 = The IN token interrupt in Control Endpoint Disabled.
sahilmgandhi	18:6a4db94011d3	27534	* \| \| \|1 = The IN token interrupt in Control Endpoint Enabled.
sahilmgandhi	18:6a4db94011d3	27535	* \|[4] \|PINGIEN \|Ping Token Interrupt
sahilmgandhi	18:6a4db94011d3	27536	* \| \| \|0 = The ping token interrupt in Control Endpoint Disabled.
sahilmgandhi	18:6a4db94011d3	27537	* \| \| \|1 = The ping token interrupt Control Endpoint Enabled.
sahilmgandhi	18:6a4db94011d3	27538	* \|[5] \|TXPKIEN \|Data Packet Transmitted Interrupt
sahilmgandhi	18:6a4db94011d3	27539	* \| \| \|0 = The data packet transmitted interrupt in Control Endpoint Disabled.
sahilmgandhi	18:6a4db94011d3	27540	* \| \| \|1 = The data packet transmitted interrupt in Control Endpoint Enabled.
sahilmgandhi	18:6a4db94011d3	27541	* \|[6] \|RXPKIEN \|Data Packet Received Interrupt
sahilmgandhi	18:6a4db94011d3	27542	* \| \| \|0 = The data received interrupt in Control Endpoint Disabled.
sahilmgandhi	18:6a4db94011d3	27543	* \| \| \|1 = The data received interrupt in Control Endpoint Enabled.
sahilmgandhi	18:6a4db94011d3	27544	* \|[7] \|NAKIEN \|NAK Sent Interrupt
sahilmgandhi	18:6a4db94011d3	27545	* \| \| \|0 = The NAK sent interrupt in Control Endpoint Disabled.
sahilmgandhi	18:6a4db94011d3	27546	* \| \| \|1 = The NAK sent interrupt in Control Endpoint Enabled.
sahilmgandhi	18:6a4db94011d3	27547	* \|[8] \|STALLIEN \|STALL Sent Interrupt
sahilmgandhi	18:6a4db94011d3	27548	* \| \| \|0 = The STALL sent interrupt in Control Endpoint Disabled.
sahilmgandhi	18:6a4db94011d3	27549	* \| \| \|1 = The STALL sent interrupt in Control Endpoint Enabled.
sahilmgandhi	18:6a4db94011d3	27550	* \|[9] \|ERRIEN \|USB Error Interrupt
sahilmgandhi	18:6a4db94011d3	27551	* \| \| \|0 = The USB Error interrupt in Control Endpoint Disabled.
sahilmgandhi	18:6a4db94011d3	27552	* \| \| \|1 = The USB Error interrupt in Control Endpoint Enabled.
sahilmgandhi	18:6a4db94011d3	27553	* \|[10] \|STSDONEIEN\|Status Completion Interrupt
sahilmgandhi	18:6a4db94011d3	27554	* \| \| \|0 = The Status Completion interrupt in Control Endpoint Disabled.
sahilmgandhi	18:6a4db94011d3	27555	* \| \| \|1 = The Status Completion interrupt in Control Endpoint Enabled.
sahilmgandhi	18:6a4db94011d3	27556	* \|[11] \|BUFFULLIEN\|Buffer Full Interrupt
sahilmgandhi	18:6a4db94011d3	27557	* \| \| \|0 = The buffer full interrupt in Control Endpoint Disabled.
sahilmgandhi	18:6a4db94011d3	27558	* \| \| \|1 = The buffer full interrupt in Control Endpoint Enabled.
sahilmgandhi	18:6a4db94011d3	27559	* \|[12] \|BUFEMPTYIEN\|Buffer Empty Interrupt
sahilmgandhi	18:6a4db94011d3	27560	* \| \| \|0 = The buffer empty interrupt in Control Endpoint Disabled.
sahilmgandhi	18:6a4db94011d3	27561	* \| \| \|1= The buffer empty interrupt in Control Endpoint Enabled.
sahilmgandhi	18:6a4db94011d3	27562	*/
sahilmgandhi	18:6a4db94011d3	27563	__IO uint32_t CEPINTEN;
sahilmgandhi	18:6a4db94011d3	27564
sahilmgandhi	18:6a4db94011d3	27565	/**
sahilmgandhi	18:6a4db94011d3	27566	* CEPINTSTS
sahilmgandhi	18:6a4db94011d3	27567	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27568	* Offset: 0x34 Control-Endpoint Interrupt Status
sahilmgandhi	18:6a4db94011d3	27569	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27570	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27571	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27572	* \|[0] \|SETUPTKIF \|Setup Token Interrupt
sahilmgandhi	18:6a4db94011d3	27573	* \| \| \|0 = Not a Setup token is received.
sahilmgandhi	18:6a4db94011d3	27574	* \| \| \|1 = A Setup token is received. Writing 1 clears this status bit
sahilmgandhi	18:6a4db94011d3	27575	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27576	* \|[1] \|SETUPPKIF \|Setup Packet Interrupt
sahilmgandhi	18:6a4db94011d3	27577	* \| \| \|This bit must be cleared (by writing 1) before the next setup packet can be received.
sahilmgandhi	18:6a4db94011d3	27578	* \| \| \|If the bit is not cleared, then the successive setup packets will be overwritten in the setup packet buffer.
sahilmgandhi	18:6a4db94011d3	27579	* \| \| \|0 = Not a Setup packet has been received from the host.
sahilmgandhi	18:6a4db94011d3	27580	* \| \| \|1 = A Setup packet has been received from the host.
sahilmgandhi	18:6a4db94011d3	27581	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27582	* \|[2] \|OUTTKIF \|Out Token Interrupt
sahilmgandhi	18:6a4db94011d3	27583	* \| \| \|0 = The control-endpoint does not received an OUT token from the host.
sahilmgandhi	18:6a4db94011d3	27584	* \| \| \|1 = The control-endpoint receives an OUT token from the host.
sahilmgandhi	18:6a4db94011d3	27585	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27586	* \|[3] \|INTKIF \|In Token Interrupt
sahilmgandhi	18:6a4db94011d3	27587	* \| \| \|0 = The control-endpoint does not received an IN token from the host.
sahilmgandhi	18:6a4db94011d3	27588	* \| \| \|1 = The control-endpoint receives an IN token from the host.
sahilmgandhi	18:6a4db94011d3	27589	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27590	* \|[4] \|PINGIF \|Ping Token Interrupt
sahilmgandhi	18:6a4db94011d3	27591	* \| \| \|0 = The control-endpoint does not received a ping token from the host.
sahilmgandhi	18:6a4db94011d3	27592	* \| \| \|1 = The control-endpoint receives a ping token from the host.
sahilmgandhi	18:6a4db94011d3	27593	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27594	* \|[5] \|TXPKIF \|Data Packet Transmitted Interrupt
sahilmgandhi	18:6a4db94011d3	27595	* \| \| \|0 = Not a data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same.
sahilmgandhi	18:6a4db94011d3	27596	* \| \| \|1 = A data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same.
sahilmgandhi	18:6a4db94011d3	27597	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27598	* \|[6] \|RXPKIF \|Data Packet Received Interrupt
sahilmgandhi	18:6a4db94011d3	27599	* \| \| \|0 = Not a data packet is successfully received from the host for an OUT-token and an ACK is sent to the host.
sahilmgandhi	18:6a4db94011d3	27600	* \| \| \|1 = A data packet is successfully received from the host for an OUT-token and an ACK is sent to the host.
sahilmgandhi	18:6a4db94011d3	27601	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27602	* \|[7] \|NAKIF \|NAK Sent Interrupt
sahilmgandhi	18:6a4db94011d3	27603	* \| \| \|0 = Not a NAK-token is sent in response to an IN/OUT token.
sahilmgandhi	18:6a4db94011d3	27604	* \| \| \|1 = A NAK-token is sent in response to an IN/OUT token.
sahilmgandhi	18:6a4db94011d3	27605	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27606	* \|[8] \|STALLIF \|STALL Sent Interrupt
sahilmgandhi	18:6a4db94011d3	27607	* \| \| \|0 = Not a stall-token is sent in response to an IN/OUT token.
sahilmgandhi	18:6a4db94011d3	27608	* \| \| \|1 = A stall-token is sent in response to an IN/OUT token.
sahilmgandhi	18:6a4db94011d3	27609	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27610	* \|[9] \|ERRIF \|USB Error Interrupt
sahilmgandhi	18:6a4db94011d3	27611	* \| \| \|0 = No error had occurred during the transaction.
sahilmgandhi	18:6a4db94011d3	27612	* \| \| \|1 = An error had occurred during the transaction.
sahilmgandhi	18:6a4db94011d3	27613	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27614	* \|[10] \|STSDONEIF \|Status Completion Interrupt
sahilmgandhi	18:6a4db94011d3	27615	* \| \| \|0 = Not a USB transaction has completed successfully.
sahilmgandhi	18:6a4db94011d3	27616	* \| \| \|1 = The status stage of a USB transaction has completed successfully.
sahilmgandhi	18:6a4db94011d3	27617	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27618	* \|[11] \|BUFFULLIF \|Buffer Full Interrupt
sahilmgandhi	18:6a4db94011d3	27619	* \| \| \|0 = The control-endpoint buffer is not full.
sahilmgandhi	18:6a4db94011d3	27620	* \| \| \|1 = The control-endpoint buffer is full.
sahilmgandhi	18:6a4db94011d3	27621	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27622	* \|[12] \|BUFEMPTYIF\|Buffer Empty Interrupt
sahilmgandhi	18:6a4db94011d3	27623	* \| \| \|0 = The control-endpoint buffer is not empty.
sahilmgandhi	18:6a4db94011d3	27624	* \| \| \|1 = The control-endpoint buffer is empty.
sahilmgandhi	18:6a4db94011d3	27625	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27626	*/
sahilmgandhi	18:6a4db94011d3	27627	__IO uint32_t CEPINTSTS;
sahilmgandhi	18:6a4db94011d3	27628
sahilmgandhi	18:6a4db94011d3	27629	/**
sahilmgandhi	18:6a4db94011d3	27630	* CEPTXCNT
sahilmgandhi	18:6a4db94011d3	27631	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27632	* Offset: 0x38 Control-Endpoint In-transfer Data Count
sahilmgandhi	18:6a4db94011d3	27633	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27634	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27635	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27636	* \|[0:7] \|TXCNT \|In-Transfer Data Count
sahilmgandhi	18:6a4db94011d3	27637	* \| \| \|There is no mode selection for the control endpoint (but it operates like manual mode).The local-CPU has to fill the control-endpoint buffer with the data to be sent for an in-token and to write the count of bytes in this register.
sahilmgandhi	18:6a4db94011d3	27638	* \| \| \|When zero is written into this field, a zero length packet is sent to the host.
sahilmgandhi	18:6a4db94011d3	27639	* \| \| \|When the count written in the register is more than the MPS, the data sent will be of only MPS.
sahilmgandhi	18:6a4db94011d3	27640	*/
sahilmgandhi	18:6a4db94011d3	27641	__IO uint32_t CEPTXCNT;
sahilmgandhi	18:6a4db94011d3	27642
sahilmgandhi	18:6a4db94011d3	27643	/**
sahilmgandhi	18:6a4db94011d3	27644	* CEPRXCNT
sahilmgandhi	18:6a4db94011d3	27645	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27646	* Offset: 0x3C Control-Endpoint Out-transfer Data Count
sahilmgandhi	18:6a4db94011d3	27647	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27648	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27649	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27650	* \|[0:7] \|RXCNT \|Out-Transfer Data Count
sahilmgandhi	18:6a4db94011d3	27651	* \| \| \|The USB device controller maintains the count of the data received in case of an out transfer, during the control transfer.
sahilmgandhi	18:6a4db94011d3	27652	*/
sahilmgandhi	18:6a4db94011d3	27653	__I uint32_t CEPRXCNT;
sahilmgandhi	18:6a4db94011d3	27654
sahilmgandhi	18:6a4db94011d3	27655	/**
sahilmgandhi	18:6a4db94011d3	27656	* CEPDATCNT
sahilmgandhi	18:6a4db94011d3	27657	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27658	* Offset: 0x40 Control-Endpoint data count
sahilmgandhi	18:6a4db94011d3	27659	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27660	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27661	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27662	* \|[0:15] \|DATCNT \|Control-Endpoint Data Count
sahilmgandhi	18:6a4db94011d3	27663	* \| \| \|The USB device controller maintains the count of the data of control-endpoint.
sahilmgandhi	18:6a4db94011d3	27664	*/
sahilmgandhi	18:6a4db94011d3	27665	__I uint32_t CEPDATCNT;
sahilmgandhi	18:6a4db94011d3	27666
sahilmgandhi	18:6a4db94011d3	27667	/**
sahilmgandhi	18:6a4db94011d3	27668	* SETUP1_0
sahilmgandhi	18:6a4db94011d3	27669	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27670	* Offset: 0x44 Setup1 & Setup0 bytes
sahilmgandhi	18:6a4db94011d3	27671	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27672	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27673	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27674	* \|[0:7] \|SETUP0 \|Setup Byte 0[7:0]
sahilmgandhi	18:6a4db94011d3	27675	* \| \| \|This register provides byte 0 of the last setup packet received.
sahilmgandhi	18:6a4db94011d3	27676	* \| \| \|For a Standard Device Request, the following bmRequestType information is returned.
sahilmgandhi	18:6a4db94011d3	27677	* \| \| \|Bit 7(Direction):
sahilmgandhi	18:6a4db94011d3	27678	* \| \| \| 0: Host to device
sahilmgandhi	18:6a4db94011d3	27679	* \| \| \| 1: Device to host
sahilmgandhi	18:6a4db94011d3	27680	* \| \| \|Bit 6-5 (Type):
sahilmgandhi	18:6a4db94011d3	27681	* \| \| \| 00: Standard
sahilmgandhi	18:6a4db94011d3	27682	* \| \| \| 01: Class
sahilmgandhi	18:6a4db94011d3	27683	* \| \| \| 10: Vendor
sahilmgandhi	18:6a4db94011d3	27684	* \| \| \| 11: Reserved
sahilmgandhi	18:6a4db94011d3	27685	* \| \| \|Bit 4-0 (Recipient)
sahilmgandhi	18:6a4db94011d3	27686	* \| \| \| 00000: Device
sahilmgandhi	18:6a4db94011d3	27687	* \| \| \| 00001: Interface
sahilmgandhi	18:6a4db94011d3	27688	* \| \| \| 00010: Endpoint
sahilmgandhi	18:6a4db94011d3	27689	* \| \| \| 00011: Other
sahilmgandhi	18:6a4db94011d3	27690	* \| \| \| Others: Reserved
sahilmgandhi	18:6a4db94011d3	27691	* \|[8:15] \|SETUP1 \|Setup Byte 1[15:8]
sahilmgandhi	18:6a4db94011d3	27692	* \| \| \|This register provides byte 1 of the last setup packet received.
sahilmgandhi	18:6a4db94011d3	27693	* \| \| \|For a Standard Device Request, the following bRequest Code information is returned.
sahilmgandhi	18:6a4db94011d3	27694	* \| \| \|00000000 = Get Status.
sahilmgandhi	18:6a4db94011d3	27695	* \| \| \|00000001 = Clear Feature.
sahilmgandhi	18:6a4db94011d3	27696	* \| \| \|00000010 = Reserved.
sahilmgandhi	18:6a4db94011d3	27697	* \| \| \|00000011 = Set Feature.
sahilmgandhi	18:6a4db94011d3	27698	* \| \| \|00000100 = Reserved.
sahilmgandhi	18:6a4db94011d3	27699	* \| \| \|00000101 = Set Address.
sahilmgandhi	18:6a4db94011d3	27700	* \| \| \|00000110 = Get Descriptor.
sahilmgandhi	18:6a4db94011d3	27701	* \| \| \|00000111 = Set Descriptor.
sahilmgandhi	18:6a4db94011d3	27702	* \| \| \|00001000 = Get Configuration.
sahilmgandhi	18:6a4db94011d3	27703	* \| \| \|00001001 = Set Configuration.
sahilmgandhi	18:6a4db94011d3	27704	* \| \| \|00001010 = Get Interface.
sahilmgandhi	18:6a4db94011d3	27705	* \| \| \|00001011 = Set Interface.
sahilmgandhi	18:6a4db94011d3	27706	* \| \| \|00001100 = Synch Frame.
sahilmgandhi	18:6a4db94011d3	27707	*/
sahilmgandhi	18:6a4db94011d3	27708	__I uint32_t SETUP1_0;
sahilmgandhi	18:6a4db94011d3	27709
sahilmgandhi	18:6a4db94011d3	27710	/**
sahilmgandhi	18:6a4db94011d3	27711	* SETUP3_2
sahilmgandhi	18:6a4db94011d3	27712	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27713	* Offset: 0x48 Setup3 & Setup2 Bytes
sahilmgandhi	18:6a4db94011d3	27714	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27715	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27716	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27717	* \|[0:7] \|SETUP2 \|Setup Byte 2 [7:0]
sahilmgandhi	18:6a4db94011d3	27718	* \| \| \|This register provides byte 2 of the last setup packet received.
sahilmgandhi	18:6a4db94011d3	27719	* \| \| \|For a Standard Device Request, the least significant byte of the wValue field is returned.
sahilmgandhi	18:6a4db94011d3	27720	* \|[8:15] \|SETUP3 \|Setup Byte 3 [15:8]
sahilmgandhi	18:6a4db94011d3	27721	* \| \| \|This register provides byte 3 of the last setup packet received.
sahilmgandhi	18:6a4db94011d3	27722	* \| \| \|For a Standard Device Request, the most significant byte of the wValue field is returned.
sahilmgandhi	18:6a4db94011d3	27723	*/
sahilmgandhi	18:6a4db94011d3	27724	__I uint32_t SETUP3_2;
sahilmgandhi	18:6a4db94011d3	27725
sahilmgandhi	18:6a4db94011d3	27726	/**
sahilmgandhi	18:6a4db94011d3	27727	* SETUP5_4
sahilmgandhi	18:6a4db94011d3	27728	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27729	* Offset: 0x4C Setup5 & Setup4 Bytes
sahilmgandhi	18:6a4db94011d3	27730	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27731	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27732	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27733	* \|[0:7] \|SETUP4 \|Setup Byte 4[7:0]
sahilmgandhi	18:6a4db94011d3	27734	* \| \| \|This register provides byte 4 of the last setup packet received.
sahilmgandhi	18:6a4db94011d3	27735	* \| \| \|For a Standard Device Request, the least significant byte of the wIndex is returned.
sahilmgandhi	18:6a4db94011d3	27736	* \|[8:15] \|SETUP5 \|Setup Byte 5[15:8]
sahilmgandhi	18:6a4db94011d3	27737	* \| \| \|This register provides byte 5 of the last setup packet received.
sahilmgandhi	18:6a4db94011d3	27738	* \| \| \|For a Standard Device Request, the most significant byte of the wIndex field is returned.
sahilmgandhi	18:6a4db94011d3	27739	*/
sahilmgandhi	18:6a4db94011d3	27740	__I uint32_t SETUP5_4;
sahilmgandhi	18:6a4db94011d3	27741
sahilmgandhi	18:6a4db94011d3	27742	/**
sahilmgandhi	18:6a4db94011d3	27743	* SETUP7_6
sahilmgandhi	18:6a4db94011d3	27744	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27745	* Offset: 0x50 Setup7 & Setup6 Bytes
sahilmgandhi	18:6a4db94011d3	27746	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27747	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27748	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27749	* \|[0:7] \|SETUP6 \|Setup Byte 6[7:0]
sahilmgandhi	18:6a4db94011d3	27750	* \| \| \|This register provides byte 6 of the last setup packet received.
sahilmgandhi	18:6a4db94011d3	27751	* \| \| \|For a Standard Device Request, the least significant byte of the wLength field is returned.
sahilmgandhi	18:6a4db94011d3	27752	* \|[8:15] \|SETUP7 \|Setup Byte 7[15:8]
sahilmgandhi	18:6a4db94011d3	27753	* \| \| \|This register provides byte 7 of the last setup packet received.
sahilmgandhi	18:6a4db94011d3	27754	* \| \| \|For a Standard Device Request, the most significant byte of the wLength field is returned.
sahilmgandhi	18:6a4db94011d3	27755	*/
sahilmgandhi	18:6a4db94011d3	27756	__I uint32_t SETUP7_6;
sahilmgandhi	18:6a4db94011d3	27757
sahilmgandhi	18:6a4db94011d3	27758	/**
sahilmgandhi	18:6a4db94011d3	27759	* CEPBUFSTART
sahilmgandhi	18:6a4db94011d3	27760	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27761	* Offset: 0x54 Control Endpoint RAM Start Address Register
sahilmgandhi	18:6a4db94011d3	27762	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27763	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27764	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27765	* \|[0:11] \|SADDR \|Control-Endpoint Start Address
sahilmgandhi	18:6a4db94011d3	27766	* \| \| \|This is the start-address of the RAM space allocated for the control-endpoint.
sahilmgandhi	18:6a4db94011d3	27767	*/
sahilmgandhi	18:6a4db94011d3	27768	__IO uint32_t CEPBUFSTART;
sahilmgandhi	18:6a4db94011d3	27769
sahilmgandhi	18:6a4db94011d3	27770	/**
sahilmgandhi	18:6a4db94011d3	27771	* CEPBUFEND
sahilmgandhi	18:6a4db94011d3	27772	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27773	* Offset: 0x58 Control Endpoint RAM End Address Register
sahilmgandhi	18:6a4db94011d3	27774	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27775	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27776	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27777	* \|[0:11] \|EADDR \|Control-Endpoint End Address
sahilmgandhi	18:6a4db94011d3	27778	* \| \| \|This is the end-address of the RAM space allocated for the control-endpoint.
sahilmgandhi	18:6a4db94011d3	27779	*/
sahilmgandhi	18:6a4db94011d3	27780	__IO uint32_t CEPBUFEND;
sahilmgandhi	18:6a4db94011d3	27781
sahilmgandhi	18:6a4db94011d3	27782	/**
sahilmgandhi	18:6a4db94011d3	27783	* DMACTL
sahilmgandhi	18:6a4db94011d3	27784	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27785	* Offset: 0x5C DMA Control Status Register
sahilmgandhi	18:6a4db94011d3	27786	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27787	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27788	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27789	* \|[0:3] \|EPNUM \|DMA Endpoint Address Bits
sahilmgandhi	18:6a4db94011d3	27790	* \| \| \|Used to define the Endpoint Address
sahilmgandhi	18:6a4db94011d3	27791	* \|[4] \|DMARD \|DMA Operation
sahilmgandhi	18:6a4db94011d3	27792	* \| \| \|0 = the operation is a DMA write.
sahilmgandhi	18:6a4db94011d3	27793	* \| \| \|1 = the operation is a DMA read.
sahilmgandhi	18:6a4db94011d3	27794	* \|[5] \|DMAEN \|DMA Enable Control
sahilmgandhi	18:6a4db94011d3	27795	* \| \| \|0 = DMA function Disabled.
sahilmgandhi	18:6a4db94011d3	27796	* \| \| \|1 = DMA function Enabled.
sahilmgandhi	18:6a4db94011d3	27797	* \|[6] \|SGEN \|Scatter Gather Function Enable Control
sahilmgandhi	18:6a4db94011d3	27798	* \| \| \|0 = Scatter gather function Disabled.
sahilmgandhi	18:6a4db94011d3	27799	* \| \| \|1 = Scatter gather function Enabled.
sahilmgandhi	18:6a4db94011d3	27800	* \|[7] \|DMARST \|Reset DMA State Machine
sahilmgandhi	18:6a4db94011d3	27801	* \| \| \|0 = No reset the DMA state machine.
sahilmgandhi	18:6a4db94011d3	27802	* \| \| \|1 = Reset the DMA state machine.
sahilmgandhi	18:6a4db94011d3	27803	*/
sahilmgandhi	18:6a4db94011d3	27804	__IO uint32_t DMACTL;
sahilmgandhi	18:6a4db94011d3	27805
sahilmgandhi	18:6a4db94011d3	27806	/**
sahilmgandhi	18:6a4db94011d3	27807	* DMACNT
sahilmgandhi	18:6a4db94011d3	27808	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27809	* Offset: 0x60 DMA Count Register
sahilmgandhi	18:6a4db94011d3	27810	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27811	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27812	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27813	* \|[0:19] \|DMACNT \|DMA Transfer Count
sahilmgandhi	18:6a4db94011d3	27814	* \| \| \|The transfer count of the DMA operation to be performed is written to this register.
sahilmgandhi	18:6a4db94011d3	27815	*/
sahilmgandhi	18:6a4db94011d3	27816	__IO uint32_t DMACNT;
sahilmgandhi	18:6a4db94011d3	27817
sahilmgandhi	18:6a4db94011d3	27818	union {
sahilmgandhi	18:6a4db94011d3	27819
sahilmgandhi	18:6a4db94011d3	27820	/**
sahilmgandhi	18:6a4db94011d3	27821	* EPADAT
sahilmgandhi	18:6a4db94011d3	27822	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27823	* Offset: 0x64 Endpoint A Data Register
sahilmgandhi	18:6a4db94011d3	27824	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27825	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27826	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27827	* \|[0:31] \|EPDAT \|Endpoint A~L Data Register
sahilmgandhi	18:6a4db94011d3	27828	* \| \| \|Endpoint A~L data buffer for the buffer transaction (read or write).
sahilmgandhi	18:6a4db94011d3	27829	* \| \| \|Note: Only word or byte access are supported.
sahilmgandhi	18:6a4db94011d3	27830	*/
sahilmgandhi	18:6a4db94011d3	27831	__IO uint32_t EPADAT;
sahilmgandhi	18:6a4db94011d3	27832	/**
sahilmgandhi	18:6a4db94011d3	27833	* EPADAT_BYTE
sahilmgandhi	18:6a4db94011d3	27834	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27835	* Offset: 0x64 Endpoint A Data Register for Byte Access
sahilmgandhi	18:6a4db94011d3	27836	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27837	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27838	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27839	* \|[0:7] \|EPDAT \|Endpoint A~L Data Register
sahilmgandhi	18:6a4db94011d3	27840	* \| \| \|Endpoint A~L data buffer for the buffer transaction (read or write).
sahilmgandhi	18:6a4db94011d3	27841	* \| \| \|Note: Only word or byte access are supported.
sahilmgandhi	18:6a4db94011d3	27842	*/
sahilmgandhi	18:6a4db94011d3	27843	__IO uint8_t EPADAT_BYTE;
sahilmgandhi	18:6a4db94011d3	27844
sahilmgandhi	18:6a4db94011d3	27845	}; ///< Define EPA Data Register 32-bit or 8-bit access
sahilmgandhi	18:6a4db94011d3	27846
sahilmgandhi	18:6a4db94011d3	27847	/**
sahilmgandhi	18:6a4db94011d3	27848	* EPAINTSTS
sahilmgandhi	18:6a4db94011d3	27849	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27850	* Offset: 0x68 Endpoint A Interrupt Status Register
sahilmgandhi	18:6a4db94011d3	27851	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27852	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27853	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27854	* \|[0] \|BUFFULLIF \|Buffer Full
sahilmgandhi	18:6a4db94011d3	27855	* \| \| \|For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
sahilmgandhi	18:6a4db94011d3	27856	* \| \| \|For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
sahilmgandhi	18:6a4db94011d3	27857	* \| \| \|0 = The endpoint packet buffer is not full.
sahilmgandhi	18:6a4db94011d3	27858	* \| \| \|1 = The endpoint packet buffer is full.
sahilmgandhi	18:6a4db94011d3	27859	* \| \| \|Note: This bit is read-only.
sahilmgandhi	18:6a4db94011d3	27860	* \|[1] \|BUFEMPTYIF\|Buffer Empty
sahilmgandhi	18:6a4db94011d3	27861	* \| \| \|For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
sahilmgandhi	18:6a4db94011d3	27862	* \| \| \|0 = The endpoint buffer is not empty.
sahilmgandhi	18:6a4db94011d3	27863	* \| \| \|1 = The endpoint buffer is empty.
sahilmgandhi	18:6a4db94011d3	27864	* \| \| \|For an OUT endpoint:
sahilmgandhi	18:6a4db94011d3	27865	* \| \| \|0 = The currently selected buffer has not a count of 0.
sahilmgandhi	18:6a4db94011d3	27866	* \| \| \|1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
sahilmgandhi	18:6a4db94011d3	27867	* \| \| \|Note: This bit is read-only.
sahilmgandhi	18:6a4db94011d3	27868	* \|[2] \|SHORTTXIF \|Short Packet Transferred Interrupt
sahilmgandhi	18:6a4db94011d3	27869	* \| \| \|0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
sahilmgandhi	18:6a4db94011d3	27870	* \| \| \|1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
sahilmgandhi	18:6a4db94011d3	27871	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27872	* \|[3] \|TXPKIF \|Data Packet Transmitted Interrupt
sahilmgandhi	18:6a4db94011d3	27873	* \| \| \|0 = Not a data packet is transmitted from the endpoint to the host.
sahilmgandhi	18:6a4db94011d3	27874	* \| \| \|1 = A data packet is transmitted from the endpoint to the host.
sahilmgandhi	18:6a4db94011d3	27875	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27876	* \|[4] \|RXPKIF \|Data Packet Received Interrupt
sahilmgandhi	18:6a4db94011d3	27877	* \| \| \|0 = No data packet is received from the host by the endpoint.
sahilmgandhi	18:6a4db94011d3	27878	* \| \| \|1 = A data packet is received from the host by the endpoint.
sahilmgandhi	18:6a4db94011d3	27879	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27880	* \|[5] \|OUTTKIF \|Data OUT Token Interrupt
sahilmgandhi	18:6a4db94011d3	27881	* \| \| \|0 = A Data OUT token has not been received from the host.
sahilmgandhi	18:6a4db94011d3	27882	* \| \| \|1 = A Data OUT token has been received from the host.
sahilmgandhi	18:6a4db94011d3	27883	* \| \| \|This bit also set by PING tokens(in high-speed only).
sahilmgandhi	18:6a4db94011d3	27884	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27885	* \|[6] \|INTKIF \|Data IN Token Interrupt
sahilmgandhi	18:6a4db94011d3	27886	* \| \| \|0 = Not Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	27887	* \| \| \|1 = A Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	27888	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27889	* \|[7] \|PINGIF \|PING Token Interrupt
sahilmgandhi	18:6a4db94011d3	27890	* \| \| \|0 = A Data PING token has not been received from the host.
sahilmgandhi	18:6a4db94011d3	27891	* \| \| \|1 = A Data PING token has been received from the host.
sahilmgandhi	18:6a4db94011d3	27892	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27893	* \|[8] \|NAKIF \|USB NAK Sent
sahilmgandhi	18:6a4db94011d3	27894	* \| \| \|0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
sahilmgandhi	18:6a4db94011d3	27895	* \| \| \|1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
sahilmgandhi	18:6a4db94011d3	27896	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27897	* \|[9] \|STALLIF \|USB STALL Sent
sahilmgandhi	18:6a4db94011d3	27898	* \| \| \|0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
sahilmgandhi	18:6a4db94011d3	27899	* \| \| \|1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
sahilmgandhi	18:6a4db94011d3	27900	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27901	* \|[10] \|NYETIF \|NYET Sent
sahilmgandhi	18:6a4db94011d3	27902	* \| \| \|0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
sahilmgandhi	18:6a4db94011d3	27903	* \| \| \|1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
sahilmgandhi	18:6a4db94011d3	27904	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27905	* \|[11] \|ERRIF \|ERR Sent
sahilmgandhi	18:6a4db94011d3	27906	* \| \| \|0 = No any error in the transaction.
sahilmgandhi	18:6a4db94011d3	27907	* \| \| \|1 = There occurs any error in the transaction.
sahilmgandhi	18:6a4db94011d3	27908	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27909	* \|[12] \|SHORTRXIF \|Bulk Out Short Packet Received
sahilmgandhi	18:6a4db94011d3	27910	* \| \| \|0 = No bulk out short packet is received.
sahilmgandhi	18:6a4db94011d3	27911	* \| \| \|1 = Received bulk out short packet (including zero length packet ).
sahilmgandhi	18:6a4db94011d3	27912	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	27913	*/
sahilmgandhi	18:6a4db94011d3	27914	__IO uint32_t EPAINTSTS;
sahilmgandhi	18:6a4db94011d3	27915
sahilmgandhi	18:6a4db94011d3	27916	/**
sahilmgandhi	18:6a4db94011d3	27917	* EPAINTEN
sahilmgandhi	18:6a4db94011d3	27918	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27919	* Offset: 0x6C Endpoint A Interrupt Enable Register
sahilmgandhi	18:6a4db94011d3	27920	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27921	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27922	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27923	* \|[0] \|BUFFULLIEN\|Buffer Full Interrupt
sahilmgandhi	18:6a4db94011d3	27924	* \| \| \|When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
sahilmgandhi	18:6a4db94011d3	27925	* \| \| \|0 = Buffer full interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27926	* \| \| \|1 = Buffer full interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27927	* \|[1] \|BUFEMPTYIEN\|Buffer Empty Interrupt
sahilmgandhi	18:6a4db94011d3	27928	* \| \| \|When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
sahilmgandhi	18:6a4db94011d3	27929	* \| \| \|0 = Buffer empty interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27930	* \| \| \|1 = Buffer empty interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27931	* \|[2] \|SHORTTXIEN\|Short Packet Transferred Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	27932	* \| \| \|When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
sahilmgandhi	18:6a4db94011d3	27933	* \| \| \|0 = Short data packet interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27934	* \| \| \|1 = Short data packet interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27935	* \|[3] \|TXPKIEN \|Data Packet Transmitted Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	27936	* \| \| \|When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
sahilmgandhi	18:6a4db94011d3	27937	* \| \| \|0 = Data packet has been received from the host interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27938	* \| \| \|1 = Data packet has been received from the host interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27939	* \|[4] \|RXPKIEN \|Data Packet Received Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	27940	* \| \| \|When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
sahilmgandhi	18:6a4db94011d3	27941	* \| \| \|0 = Data packet has been transmitted to the host interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27942	* \| \| \|1 = Data packet has been transmitted to the host interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27943	* \|[5] \|OUTTKIEN \|Data OUT Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	27944	* \| \| \|When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
sahilmgandhi	18:6a4db94011d3	27945	* \| \| \|0 = Data OUT token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27946	* \| \| \|1 = Data OUT token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27947	* \|[6] \|INTKIEN \|Data IN Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	27948	* \| \| \|When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	27949	* \| \| \|0 = Data IN token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27950	* \| \| \|1 = Data IN token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27951	* \|[7] \|PINGIEN \|PING Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	27952	* \| \| \|When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
sahilmgandhi	18:6a4db94011d3	27953	* \| \| \|0 = PING token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27954	* \| \| \|1 = PING token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27955	* \|[8] \|NAKIEN \|USB NAK Sent Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	27956	* \| \| \|When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
sahilmgandhi	18:6a4db94011d3	27957	* \| \| \|0 = NAK token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27958	* \| \| \|1 = NAK token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27959	* \|[9] \|STALLIEN \|USB STALL Sent Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	27960	* \| \| \|When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
sahilmgandhi	18:6a4db94011d3	27961	* \| \| \|0 = STALL token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27962	* \| \| \|1 = STALL token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27963	* \|[10] \|NYETIEN \|NYET Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	27964	* \| \| \|When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	27965	* \| \| \|0 = NYET condition interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27966	* \| \| \|1 = NYET condition interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27967	* \|[11] \|ERRIEN \|ERR Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	27968	* \| \| \|When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	27969	* \| \| \|0 = Error event interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27970	* \| \| \|1 = Error event interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27971	* \|[12] \|SHORTRXIEN\|Bulk Out Short Packet Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	27972	* \| \| \|When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	27973	* \| \| \|0 = Bulk out interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	27974	* \| \| \|1 = Bulk out interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	27975	*/
sahilmgandhi	18:6a4db94011d3	27976	__IO uint32_t EPAINTEN;
sahilmgandhi	18:6a4db94011d3	27977
sahilmgandhi	18:6a4db94011d3	27978	/**
sahilmgandhi	18:6a4db94011d3	27979	* EPADATCNT
sahilmgandhi	18:6a4db94011d3	27980	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27981	* Offset: 0x70 Endpoint A Data Available Count Register
sahilmgandhi	18:6a4db94011d3	27982	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27983	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27984	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27985	* \|[0:15] \|DATCNT \|Data Count
sahilmgandhi	18:6a4db94011d3	27986	* \| \| \|For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
sahilmgandhi	18:6a4db94011d3	27987	* \|[16:30] \|DMALOOP \|DMA Loop
sahilmgandhi	18:6a4db94011d3	27988	* \| \| \|This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
sahilmgandhi	18:6a4db94011d3	27989	*/
sahilmgandhi	18:6a4db94011d3	27990	__I uint32_t EPADATCNT;
sahilmgandhi	18:6a4db94011d3	27991
sahilmgandhi	18:6a4db94011d3	27992	/**
sahilmgandhi	18:6a4db94011d3	27993	* EPARSPCTL
sahilmgandhi	18:6a4db94011d3	27994	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	27995	* Offset: 0x74 Endpoint A Response Control Register
sahilmgandhi	18:6a4db94011d3	27996	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	27997	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	27998	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	27999	* \|[0] \|FLUSH \|Buffer Flush
sahilmgandhi	18:6a4db94011d3	28000	* \| \| \|Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
sahilmgandhi	18:6a4db94011d3	28001	* \| \| \|This bit is self-clearing.
sahilmgandhi	18:6a4db94011d3	28002	* \| \| \|This bit should always be written after an configuration event.
sahilmgandhi	18:6a4db94011d3	28003	* \| \| \|0 = The packet buffer is not flushed.
sahilmgandhi	18:6a4db94011d3	28004	* \| \| \|1 = The packet buffer is flushed by user.
sahilmgandhi	18:6a4db94011d3	28005	* \|[1:2] \|MODE \|Mode Control
sahilmgandhi	18:6a4db94011d3	28006	* \| \| \|The two bits decide the operation mode of the in-endpoint.
sahilmgandhi	18:6a4db94011d3	28007	* \| \| \|00: Auto-Validate Mode
sahilmgandhi	18:6a4db94011d3	28008	* \| \| \|01: Manual-Validate Mode
sahilmgandhi	18:6a4db94011d3	28009	* \| \| \|10: Fly Mode
sahilmgandhi	18:6a4db94011d3	28010	* \| \| \|11: Reserved
sahilmgandhi	18:6a4db94011d3	28011	* \| \| \|These bits are not valid for an out-endpoint.
sahilmgandhi	18:6a4db94011d3	28012	* \| \| \|The auto validate mode will be activated when the reserved mode is selected.
sahilmgandhi	18:6a4db94011d3	28013	* \|[3] \|TOGGLE \|Endpoint Toggle
sahilmgandhi	18:6a4db94011d3	28014	* \| \| \|This bit is used to clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	28015	* \| \| \|Reading this bit returns the current state of the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	28016	* \| \| \|The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
sahilmgandhi	18:6a4db94011d3	28017	* \| \| \|Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
sahilmgandhi	18:6a4db94011d3	28018	* \| \| \|0 = Not clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	28019	* \| \| \|1 = Clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	28020	* \|[4] \|HALT \|Endpoint Halt
sahilmgandhi	18:6a4db94011d3	28021	* \| \| \|This bit is used to send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	28022	* \| \| \|When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
sahilmgandhi	18:6a4db94011d3	28023	* \| \| \|0 = Not send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	28024	* \| \| \|1 = Send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	28025	* \|[5] \|ZEROLEN \|Zero Length
sahilmgandhi	18:6a4db94011d3	28026	* \| \| \|This bit is used to send a zero-length packet n response to an IN-token.
sahilmgandhi	18:6a4db94011d3	28027	* \| \| \|When this bit is set, a zero packet is sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	28028	* \| \| \|0 = A zero packet is not sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	28029	* \| \| \|1 = A zero packet is sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	28030	* \|[6] \|SHORTTXEN \|Short Packet Transfer Enable
sahilmgandhi	18:6a4db94011d3	28031	* \| \| \|This bit is applicable only in case of Auto-Validate Method.
sahilmgandhi	18:6a4db94011d3	28032	* \| \| \|This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
sahilmgandhi	18:6a4db94011d3	28033	* \| \| \|0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
sahilmgandhi	18:6a4db94011d3	28034	* \| \| \|1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
sahilmgandhi	18:6a4db94011d3	28035	* \|[7] \|DISBUF \|Buffer Disable Control
sahilmgandhi	18:6a4db94011d3	28036	* \| \| \|This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	28037	* \| \| \|0 = Buffer Not Disabled when Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	28038	* \| \| \|1 = Buffer Disabled when Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	28039	*/
sahilmgandhi	18:6a4db94011d3	28040	__IO uint32_t EPARSPCTL;
sahilmgandhi	18:6a4db94011d3	28041
sahilmgandhi	18:6a4db94011d3	28042	/**
sahilmgandhi	18:6a4db94011d3	28043	* EPAMPS
sahilmgandhi	18:6a4db94011d3	28044	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28045	* Offset: 0x78 Endpoint A Maximum Packet Size Register
sahilmgandhi	18:6a4db94011d3	28046	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28047	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28048	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28049	* \|[0:10] \|EPMPS \|Endpoint Maximum Packet Size
sahilmgandhi	18:6a4db94011d3	28050	* \| \| \|This field determines the Maximum Packet Size of the Endpoint.
sahilmgandhi	18:6a4db94011d3	28051	*/
sahilmgandhi	18:6a4db94011d3	28052	__IO uint32_t EPAMPS;
sahilmgandhi	18:6a4db94011d3	28053
sahilmgandhi	18:6a4db94011d3	28054	/**
sahilmgandhi	18:6a4db94011d3	28055	* EPATXCNT
sahilmgandhi	18:6a4db94011d3	28056	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28057	* Offset: 0x7C Endpoint A Transfer Count Register
sahilmgandhi	18:6a4db94011d3	28058	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28059	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28060	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28061	* \|[0:10] \|TXCNT \|Endpoint Transfer Count
sahilmgandhi	18:6a4db94011d3	28062	* \| \| \|For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
sahilmgandhi	18:6a4db94011d3	28063	* \| \| \|For OUT endpoints, this field has no effect.
sahilmgandhi	18:6a4db94011d3	28064	*/
sahilmgandhi	18:6a4db94011d3	28065	__IO uint32_t EPATXCNT;
sahilmgandhi	18:6a4db94011d3	28066
sahilmgandhi	18:6a4db94011d3	28067	/**
sahilmgandhi	18:6a4db94011d3	28068	* EPACFG
sahilmgandhi	18:6a4db94011d3	28069	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28070	* Offset: 0x80 Endpoint A Configuration Register
sahilmgandhi	18:6a4db94011d3	28071	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28072	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28073	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28074	* \|[0] \|EPEN \|Endpoint Valid
sahilmgandhi	18:6a4db94011d3	28075	* \| \| \|When set, this bit enables this endpoint.
sahilmgandhi	18:6a4db94011d3	28076	* \| \| \|This bit has no effect on Endpoint 0, which is always enabled.
sahilmgandhi	18:6a4db94011d3	28077	* \| \| \|0 = The endpoint Disabled.
sahilmgandhi	18:6a4db94011d3	28078	* \| \| \|1 = The endpoint Enabled.
sahilmgandhi	18:6a4db94011d3	28079	* \|[1:2] \|EPTYPE \|Endpoint Type
sahilmgandhi	18:6a4db94011d3	28080	* \| \| \|This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
sahilmgandhi	18:6a4db94011d3	28081	* \| \| \|00 = Reserved.
sahilmgandhi	18:6a4db94011d3	28082	* \| \| \|01 = Bulk.
sahilmgandhi	18:6a4db94011d3	28083	* \| \| \|10 = Interrupt.
sahilmgandhi	18:6a4db94011d3	28084	* \| \| \|11 = Isochronous.
sahilmgandhi	18:6a4db94011d3	28085	* \|[3] \|EPDIR \|Endpoint Direction
sahilmgandhi	18:6a4db94011d3	28086	* \| \| \|0 = out-endpoint (Host OUT to Device).
sahilmgandhi	18:6a4db94011d3	28087	* \| \| \|1 = in-endpoint (Host IN to Device).
sahilmgandhi	18:6a4db94011d3	28088	* \| \| \|Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
sahilmgandhi	18:6a4db94011d3	28089	* \|[4:7] \|EPNUM \|Endpoint Number
sahilmgandhi	18:6a4db94011d3	28090	* \| \| \|This field selects the number of the endpoint. Valid numbers 1 to 15.
sahilmgandhi	18:6a4db94011d3	28091	*/
sahilmgandhi	18:6a4db94011d3	28092	__IO uint32_t EPACFG;
sahilmgandhi	18:6a4db94011d3	28093
sahilmgandhi	18:6a4db94011d3	28094	/**
sahilmgandhi	18:6a4db94011d3	28095	* EPABUFSTART
sahilmgandhi	18:6a4db94011d3	28096	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28097	* Offset: 0x84 Endpoint A RAM Start Address Register
sahilmgandhi	18:6a4db94011d3	28098	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28099	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28100	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28101	* \|[0:11] \|SADDR \|Endpoint Start Address
sahilmgandhi	18:6a4db94011d3	28102	* \| \| \|This is the start-address of the RAM space allocated for the endpoint A~L.
sahilmgandhi	18:6a4db94011d3	28103	*/
sahilmgandhi	18:6a4db94011d3	28104	__IO uint32_t EPABUFSTART;
sahilmgandhi	18:6a4db94011d3	28105
sahilmgandhi	18:6a4db94011d3	28106	/**
sahilmgandhi	18:6a4db94011d3	28107	* EPABUFEND
sahilmgandhi	18:6a4db94011d3	28108	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28109	* Offset: 0x88 Endpoint A RAM End Address Register
sahilmgandhi	18:6a4db94011d3	28110	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28111	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28112	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28113	* \|[0:11] \|EADDR \|Endpoint End Address
sahilmgandhi	18:6a4db94011d3	28114	* \| \| \|This is the end-address of the RAM space allocated for the endpoint A~L.
sahilmgandhi	18:6a4db94011d3	28115	*/
sahilmgandhi	18:6a4db94011d3	28116	__IO uint32_t EPABUFEND;
sahilmgandhi	18:6a4db94011d3	28117
sahilmgandhi	18:6a4db94011d3	28118	union {
sahilmgandhi	18:6a4db94011d3	28119
sahilmgandhi	18:6a4db94011d3	28120	/**
sahilmgandhi	18:6a4db94011d3	28121	* EPBDAT
sahilmgandhi	18:6a4db94011d3	28122	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28123	* Offset: 0x8C Endpoint B Data Register
sahilmgandhi	18:6a4db94011d3	28124	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28125	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28126	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28127	* \|[0:31] \|EPDAT \|Endpoint A~L Data Register
sahilmgandhi	18:6a4db94011d3	28128	* \| \| \|Endpoint A~L data buffer for the buffer transaction (read or write).
sahilmgandhi	18:6a4db94011d3	28129	* \| \| \|Note: Only word or byte access are supported.
sahilmgandhi	18:6a4db94011d3	28130	*/
sahilmgandhi	18:6a4db94011d3	28131	__IO uint32_t EPBDAT;
sahilmgandhi	18:6a4db94011d3	28132	/**
sahilmgandhi	18:6a4db94011d3	28133	* EPBDAT_BYTE
sahilmgandhi	18:6a4db94011d3	28134	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28135	* Offset: 0x8C Endpoint B Data Register or Byte Access
sahilmgandhi	18:6a4db94011d3	28136	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28137	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28138	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28139	* \|[0:7] \|EPDAT \|Endpoint A~L Data Register
sahilmgandhi	18:6a4db94011d3	28140	* \| \| \|Endpoint A~L data buffer for the buffer transaction (read or write).
sahilmgandhi	18:6a4db94011d3	28141	* \| \| \|Note: Only word or byte access are supported.
sahilmgandhi	18:6a4db94011d3	28142	*/
sahilmgandhi	18:6a4db94011d3	28143	__IO uint8_t EPBDAT_BYTE;
sahilmgandhi	18:6a4db94011d3	28144
sahilmgandhi	18:6a4db94011d3	28145	}; ///< Define EPB Data Register 32-bit or 8-bit access
sahilmgandhi	18:6a4db94011d3	28146
sahilmgandhi	18:6a4db94011d3	28147	/**
sahilmgandhi	18:6a4db94011d3	28148	* EPBINTSTS
sahilmgandhi	18:6a4db94011d3	28149	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28150	* Offset: 0x90 Endpoint B Interrupt Status Register
sahilmgandhi	18:6a4db94011d3	28151	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28152	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28153	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28154	* \|[0] \|BUFFULLIF \|Buffer Full
sahilmgandhi	18:6a4db94011d3	28155	* \| \| \|For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
sahilmgandhi	18:6a4db94011d3	28156	* \| \| \|For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
sahilmgandhi	18:6a4db94011d3	28157	* \| \| \|0 = The endpoint packet buffer is not full.
sahilmgandhi	18:6a4db94011d3	28158	* \| \| \|1 = The endpoint packet buffer is full.
sahilmgandhi	18:6a4db94011d3	28159	* \| \| \|Note: This bit is read-only.
sahilmgandhi	18:6a4db94011d3	28160	* \|[1] \|BUFEMPTYIF\|Buffer Empty
sahilmgandhi	18:6a4db94011d3	28161	* \| \| \|For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
sahilmgandhi	18:6a4db94011d3	28162	* \| \| \|0 = The endpoint buffer is not empty.
sahilmgandhi	18:6a4db94011d3	28163	* \| \| \|1 = The endpoint buffer is empty.
sahilmgandhi	18:6a4db94011d3	28164	* \| \| \|For an OUT endpoint:
sahilmgandhi	18:6a4db94011d3	28165	* \| \| \|0 = The currently selected buffer has not a count of 0.
sahilmgandhi	18:6a4db94011d3	28166	* \| \| \|1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
sahilmgandhi	18:6a4db94011d3	28167	* \| \| \|Note: This bit is read-only.
sahilmgandhi	18:6a4db94011d3	28168	* \|[2] \|SHORTTXIF \|Short Packet Transferred Interrupt
sahilmgandhi	18:6a4db94011d3	28169	* \| \| \|0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
sahilmgandhi	18:6a4db94011d3	28170	* \| \| \|1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
sahilmgandhi	18:6a4db94011d3	28171	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28172	* \|[3] \|TXPKIF \|Data Packet Transmitted Interrupt
sahilmgandhi	18:6a4db94011d3	28173	* \| \| \|0 = Not a data packet is transmitted from the endpoint to the host.
sahilmgandhi	18:6a4db94011d3	28174	* \| \| \|1 = A data packet is transmitted from the endpoint to the host.
sahilmgandhi	18:6a4db94011d3	28175	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28176	* \|[4] \|RXPKIF \|Data Packet Received Interrupt
sahilmgandhi	18:6a4db94011d3	28177	* \| \| \|0 = No data packet is received from the host by the endpoint.
sahilmgandhi	18:6a4db94011d3	28178	* \| \| \|1 = A data packet is received from the host by the endpoint.
sahilmgandhi	18:6a4db94011d3	28179	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28180	* \|[5] \|OUTTKIF \|Data OUT Token Interrupt
sahilmgandhi	18:6a4db94011d3	28181	* \| \| \|0 = A Data OUT token has not been received from the host.
sahilmgandhi	18:6a4db94011d3	28182	* \| \| \|1 = A Data OUT token has been received from the host.
sahilmgandhi	18:6a4db94011d3	28183	* \| \| \|This bit also set by PING tokens(in high-speed only).
sahilmgandhi	18:6a4db94011d3	28184	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28185	* \|[6] \|INTKIF \|Data IN Token Interrupt
sahilmgandhi	18:6a4db94011d3	28186	* \| \| \|0 = Not Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	28187	* \| \| \|1 = A Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	28188	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28189	* \|[7] \|PINGIF \|PING Token Interrupt
sahilmgandhi	18:6a4db94011d3	28190	* \| \| \|0 = A Data PING token has not been received from the host.
sahilmgandhi	18:6a4db94011d3	28191	* \| \| \|1 = A Data PING token has been received from the host.
sahilmgandhi	18:6a4db94011d3	28192	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28193	* \|[8] \|NAKIF \|USB NAK Sent
sahilmgandhi	18:6a4db94011d3	28194	* \| \| \|0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
sahilmgandhi	18:6a4db94011d3	28195	* \| \| \|1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
sahilmgandhi	18:6a4db94011d3	28196	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28197	* \|[9] \|STALLIF \|USB STALL Sent
sahilmgandhi	18:6a4db94011d3	28198	* \| \| \|0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
sahilmgandhi	18:6a4db94011d3	28199	* \| \| \|1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
sahilmgandhi	18:6a4db94011d3	28200	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28201	* \|[10] \|NYETIF \|NYET Sent
sahilmgandhi	18:6a4db94011d3	28202	* \| \| \|0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
sahilmgandhi	18:6a4db94011d3	28203	* \| \| \|1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
sahilmgandhi	18:6a4db94011d3	28204	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28205	* \|[11] \|ERRIF \|ERR Sent
sahilmgandhi	18:6a4db94011d3	28206	* \| \| \|0 = No any error in the transaction.
sahilmgandhi	18:6a4db94011d3	28207	* \| \| \|1 = There occurs any error in the transaction.
sahilmgandhi	18:6a4db94011d3	28208	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28209	* \|[12] \|SHORTRXIF \|Bulk Out Short Packet Received
sahilmgandhi	18:6a4db94011d3	28210	* \| \| \|0 = No bulk out short packet is received.
sahilmgandhi	18:6a4db94011d3	28211	* \| \| \|1 = Received bulk out short packet (including zero length packet ).
sahilmgandhi	18:6a4db94011d3	28212	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28213	*/
sahilmgandhi	18:6a4db94011d3	28214	__IO uint32_t EPBINTSTS;
sahilmgandhi	18:6a4db94011d3	28215
sahilmgandhi	18:6a4db94011d3	28216	/**
sahilmgandhi	18:6a4db94011d3	28217	* EPBINTEN
sahilmgandhi	18:6a4db94011d3	28218	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28219	* Offset: 0x94 Endpoint B Interrupt Enable Register
sahilmgandhi	18:6a4db94011d3	28220	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28221	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28222	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28223	* \|[0] \|BUFFULLIEN\|Buffer Full Interrupt
sahilmgandhi	18:6a4db94011d3	28224	* \| \| \|When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
sahilmgandhi	18:6a4db94011d3	28225	* \| \| \|0 = Buffer full interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28226	* \| \| \|1 = Buffer full interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28227	* \|[1] \|BUFEMPTYIEN\|Buffer Empty Interrupt
sahilmgandhi	18:6a4db94011d3	28228	* \| \| \|When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
sahilmgandhi	18:6a4db94011d3	28229	* \| \| \|0 = Buffer empty interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28230	* \| \| \|1 = Buffer empty interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28231	* \|[2] \|SHORTTXIEN\|Short Packet Transferred Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28232	* \| \| \|When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
sahilmgandhi	18:6a4db94011d3	28233	* \| \| \|0 = Short data packet interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28234	* \| \| \|1 = Short data packet interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28235	* \|[3] \|TXPKIEN \|Data Packet Transmitted Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28236	* \| \| \|When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
sahilmgandhi	18:6a4db94011d3	28237	* \| \| \|0 = Data packet has been received from the host interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28238	* \| \| \|1 = Data packet has been received from the host interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28239	* \|[4] \|RXPKIEN \|Data Packet Received Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28240	* \| \| \|When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
sahilmgandhi	18:6a4db94011d3	28241	* \| \| \|0 = Data packet has been transmitted to the host interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28242	* \| \| \|1 = Data packet has been transmitted to the host interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28243	* \|[5] \|OUTTKIEN \|Data OUT Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28244	* \| \| \|When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
sahilmgandhi	18:6a4db94011d3	28245	* \| \| \|0 = Data OUT token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28246	* \| \| \|1 = Data OUT token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28247	* \|[6] \|INTKIEN \|Data IN Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28248	* \| \| \|When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	28249	* \| \| \|0 = Data IN token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28250	* \| \| \|1 = Data IN token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28251	* \|[7] \|PINGIEN \|PING Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28252	* \| \| \|When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
sahilmgandhi	18:6a4db94011d3	28253	* \| \| \|0 = PING token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28254	* \| \| \|1 = PING token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28255	* \|[8] \|NAKIEN \|USB NAK Sent Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28256	* \| \| \|When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
sahilmgandhi	18:6a4db94011d3	28257	* \| \| \|0 = NAK token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28258	* \| \| \|1 = NAK token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28259	* \|[9] \|STALLIEN \|USB STALL Sent Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28260	* \| \| \|When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
sahilmgandhi	18:6a4db94011d3	28261	* \| \| \|0 = STALL token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28262	* \| \| \|1 = STALL token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28263	* \|[10] \|NYETIEN \|NYET Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28264	* \| \| \|When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	28265	* \| \| \|0 = NYET condition interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28266	* \| \| \|1 = NYET condition interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28267	* \|[11] \|ERRIEN \|ERR Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28268	* \| \| \|When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	28269	* \| \| \|0 = Error event interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28270	* \| \| \|1 = Error event interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28271	* \|[12] \|SHORTRXIEN\|Bulk Out Short Packet Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28272	* \| \| \|When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	28273	* \| \| \|0 = Bulk out interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28274	* \| \| \|1 = Bulk out interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28275	*/
sahilmgandhi	18:6a4db94011d3	28276	__IO uint32_t EPBINTEN;
sahilmgandhi	18:6a4db94011d3	28277
sahilmgandhi	18:6a4db94011d3	28278	/**
sahilmgandhi	18:6a4db94011d3	28279	* EPBDATCNT
sahilmgandhi	18:6a4db94011d3	28280	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28281	* Offset: 0x98 Endpoint B Data Available Count Register
sahilmgandhi	18:6a4db94011d3	28282	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28283	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28284	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28285	* \|[0:15] \|DATCNT \|Data Count
sahilmgandhi	18:6a4db94011d3	28286	* \| \| \|For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
sahilmgandhi	18:6a4db94011d3	28287	* \|[16:30] \|DMALOOP \|DMA Loop
sahilmgandhi	18:6a4db94011d3	28288	* \| \| \|This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
sahilmgandhi	18:6a4db94011d3	28289	*/
sahilmgandhi	18:6a4db94011d3	28290	__I uint32_t EPBDATCNT;
sahilmgandhi	18:6a4db94011d3	28291
sahilmgandhi	18:6a4db94011d3	28292	/**
sahilmgandhi	18:6a4db94011d3	28293	* EPBRSPCTL
sahilmgandhi	18:6a4db94011d3	28294	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28295	* Offset: 0x9C Endpoint B Response Control Register
sahilmgandhi	18:6a4db94011d3	28296	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28297	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28298	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28299	* \|[0] \|FLUSH \|Buffer Flush
sahilmgandhi	18:6a4db94011d3	28300	* \| \| \|Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
sahilmgandhi	18:6a4db94011d3	28301	* \| \| \|This bit is self-clearing.
sahilmgandhi	18:6a4db94011d3	28302	* \| \| \|This bit should always be written after an configuration event.
sahilmgandhi	18:6a4db94011d3	28303	* \| \| \|0 = The packet buffer is not flushed.
sahilmgandhi	18:6a4db94011d3	28304	* \| \| \|1 = The packet buffer is flushed by user.
sahilmgandhi	18:6a4db94011d3	28305	* \|[1:2] \|MODE \|Mode Control
sahilmgandhi	18:6a4db94011d3	28306	* \| \| \|The two bits decide the operation mode of the in-endpoint.
sahilmgandhi	18:6a4db94011d3	28307	* \| \| \|00: Auto-Validate Mode
sahilmgandhi	18:6a4db94011d3	28308	* \| \| \|01: Manual-Validate Mode
sahilmgandhi	18:6a4db94011d3	28309	* \| \| \|10: Fly Mode
sahilmgandhi	18:6a4db94011d3	28310	* \| \| \|11: Reserved
sahilmgandhi	18:6a4db94011d3	28311	* \| \| \|These bits are not valid for an out-endpoint.
sahilmgandhi	18:6a4db94011d3	28312	* \| \| \|The auto validate mode will be activated when the reserved mode is selected.
sahilmgandhi	18:6a4db94011d3	28313	* \|[3] \|TOGGLE \|Endpoint Toggle
sahilmgandhi	18:6a4db94011d3	28314	* \| \| \|This bit is used to clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	28315	* \| \| \|Reading this bit returns the current state of the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	28316	* \| \| \|The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
sahilmgandhi	18:6a4db94011d3	28317	* \| \| \|Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
sahilmgandhi	18:6a4db94011d3	28318	* \| \| \|0 = Not clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	28319	* \| \| \|1 = Clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	28320	* \|[4] \|HALT \|Endpoint Halt
sahilmgandhi	18:6a4db94011d3	28321	* \| \| \|This bit is used to send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	28322	* \| \| \|When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
sahilmgandhi	18:6a4db94011d3	28323	* \| \| \|0 = Not send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	28324	* \| \| \|1 = Send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	28325	* \|[5] \|ZEROLEN \|Zero Length
sahilmgandhi	18:6a4db94011d3	28326	* \| \| \|This bit is used to send a zero-length packet n response to an IN-token.
sahilmgandhi	18:6a4db94011d3	28327	* \| \| \|When this bit is set, a zero packet is sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	28328	* \| \| \|0 = A zero packet is not sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	28329	* \| \| \|1 = A zero packet is sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	28330	* \|[6] \|SHORTTXEN \|Short Packet Transfer Enable
sahilmgandhi	18:6a4db94011d3	28331	* \| \| \|This bit is applicable only in case of Auto-Validate Method.
sahilmgandhi	18:6a4db94011d3	28332	* \| \| \|This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
sahilmgandhi	18:6a4db94011d3	28333	* \| \| \|0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
sahilmgandhi	18:6a4db94011d3	28334	* \| \| \|1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
sahilmgandhi	18:6a4db94011d3	28335	* \|[7] \|DISBUF \|Buffer Disable Control
sahilmgandhi	18:6a4db94011d3	28336	* \| \| \|This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	28337	* \| \| \|0 = Buffer Not Disabled when Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	28338	* \| \| \|1 = Buffer Disabled when Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	28339	*/
sahilmgandhi	18:6a4db94011d3	28340	__IO uint32_t EPBRSPCTL;
sahilmgandhi	18:6a4db94011d3	28341
sahilmgandhi	18:6a4db94011d3	28342	/**
sahilmgandhi	18:6a4db94011d3	28343	* EPBMPS
sahilmgandhi	18:6a4db94011d3	28344	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28345	* Offset: 0xA0 Endpoint B Maximum Packet Size Register
sahilmgandhi	18:6a4db94011d3	28346	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28347	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28348	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28349	* \|[0:10] \|EPMPS \|Endpoint Maximum Packet Size
sahilmgandhi	18:6a4db94011d3	28350	* \| \| \|This field determines the Maximum Packet Size of the Endpoint.
sahilmgandhi	18:6a4db94011d3	28351	*/
sahilmgandhi	18:6a4db94011d3	28352	__IO uint32_t EPBMPS;
sahilmgandhi	18:6a4db94011d3	28353
sahilmgandhi	18:6a4db94011d3	28354	/**
sahilmgandhi	18:6a4db94011d3	28355	* EPBTXCNT
sahilmgandhi	18:6a4db94011d3	28356	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28357	* Offset: 0xA4 Endpoint B Transfer Count Register
sahilmgandhi	18:6a4db94011d3	28358	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28359	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28360	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28361	* \|[0:10] \|TXCNT \|Endpoint Transfer Count
sahilmgandhi	18:6a4db94011d3	28362	* \| \| \|For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
sahilmgandhi	18:6a4db94011d3	28363	* \| \| \|For OUT endpoints, this field has no effect.
sahilmgandhi	18:6a4db94011d3	28364	*/
sahilmgandhi	18:6a4db94011d3	28365	__IO uint32_t EPBTXCNT;
sahilmgandhi	18:6a4db94011d3	28366
sahilmgandhi	18:6a4db94011d3	28367	/**
sahilmgandhi	18:6a4db94011d3	28368	* EPBCFG
sahilmgandhi	18:6a4db94011d3	28369	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28370	* Offset: 0xA8 Endpoint B Configuration Register
sahilmgandhi	18:6a4db94011d3	28371	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28372	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28373	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28374	* \|[0] \|EPEN \|Endpoint Valid
sahilmgandhi	18:6a4db94011d3	28375	* \| \| \|When set, this bit enables this endpoint.
sahilmgandhi	18:6a4db94011d3	28376	* \| \| \|This bit has no effect on Endpoint 0, which is always enabled.
sahilmgandhi	18:6a4db94011d3	28377	* \| \| \|0 = The endpoint Disabled.
sahilmgandhi	18:6a4db94011d3	28378	* \| \| \|1 = The endpoint Enabled.
sahilmgandhi	18:6a4db94011d3	28379	* \|[1:2] \|EPTYPE \|Endpoint Type
sahilmgandhi	18:6a4db94011d3	28380	* \| \| \|This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
sahilmgandhi	18:6a4db94011d3	28381	* \| \| \|00 = Reserved.
sahilmgandhi	18:6a4db94011d3	28382	* \| \| \|01 = Bulk.
sahilmgandhi	18:6a4db94011d3	28383	* \| \| \|10 = Interrupt.
sahilmgandhi	18:6a4db94011d3	28384	* \| \| \|11 = Isochronous.
sahilmgandhi	18:6a4db94011d3	28385	* \|[3] \|EPDIR \|Endpoint Direction
sahilmgandhi	18:6a4db94011d3	28386	* \| \| \|0 = out-endpoint (Host OUT to Device).
sahilmgandhi	18:6a4db94011d3	28387	* \| \| \|1 = in-endpoint (Host IN to Device).
sahilmgandhi	18:6a4db94011d3	28388	* \| \| \|Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
sahilmgandhi	18:6a4db94011d3	28389	* \|[4:7] \|EPNUM \|Endpoint Number
sahilmgandhi	18:6a4db94011d3	28390	* \| \| \|This field selects the number of the endpoint. Valid numbers 1 to 15.
sahilmgandhi	18:6a4db94011d3	28391	*/
sahilmgandhi	18:6a4db94011d3	28392	__IO uint32_t EPBCFG;
sahilmgandhi	18:6a4db94011d3	28393
sahilmgandhi	18:6a4db94011d3	28394	/**
sahilmgandhi	18:6a4db94011d3	28395	* EPBBUFSTART
sahilmgandhi	18:6a4db94011d3	28396	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28397	* Offset: 0xAC Endpoint B RAM Start Address Register
sahilmgandhi	18:6a4db94011d3	28398	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28399	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28400	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28401	* \|[0:11] \|SADDR \|Endpoint Start Address
sahilmgandhi	18:6a4db94011d3	28402	* \| \| \|This is the start-address of the RAM space allocated for the endpoint A~L.
sahilmgandhi	18:6a4db94011d3	28403	*/
sahilmgandhi	18:6a4db94011d3	28404	__IO uint32_t EPBBUFSTART;
sahilmgandhi	18:6a4db94011d3	28405
sahilmgandhi	18:6a4db94011d3	28406	/**
sahilmgandhi	18:6a4db94011d3	28407	* EPBBUFEND
sahilmgandhi	18:6a4db94011d3	28408	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28409	* Offset: 0xB0 Endpoint B RAM End Address Register
sahilmgandhi	18:6a4db94011d3	28410	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28411	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28412	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28413	* \|[0:11] \|EADDR \|Endpoint End Address
sahilmgandhi	18:6a4db94011d3	28414	* \| \| \|This is the end-address of the RAM space allocated for the endpoint A~L.
sahilmgandhi	18:6a4db94011d3	28415	*/
sahilmgandhi	18:6a4db94011d3	28416	__IO uint32_t EPBBUFEND;
sahilmgandhi	18:6a4db94011d3	28417
sahilmgandhi	18:6a4db94011d3	28418	union {
sahilmgandhi	18:6a4db94011d3	28419
sahilmgandhi	18:6a4db94011d3	28420	/**
sahilmgandhi	18:6a4db94011d3	28421	* EPCDAT
sahilmgandhi	18:6a4db94011d3	28422	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28423	* Offset: 0xB4 Endpoint C Data Register
sahilmgandhi	18:6a4db94011d3	28424	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28425	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28426	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28427	* \|[0:31] \|EPDAT \|Endpoint A~L Data Register
sahilmgandhi	18:6a4db94011d3	28428	* \| \| \|Endpoint A~L data buffer for the buffer transaction (read or write).
sahilmgandhi	18:6a4db94011d3	28429	* \| \| \|Note: Only word or byte access are supported.
sahilmgandhi	18:6a4db94011d3	28430	*/
sahilmgandhi	18:6a4db94011d3	28431	__IO uint32_t EPCDAT;
sahilmgandhi	18:6a4db94011d3	28432	/**
sahilmgandhi	18:6a4db94011d3	28433	* EPCDAT_BYTE
sahilmgandhi	18:6a4db94011d3	28434	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28435	* Offset: 0xB4 Endpoint C Data Register for Byte Access
sahilmgandhi	18:6a4db94011d3	28436	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28437	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28438	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28439	* \|[0:7] \|EPDAT \|Endpoint A~L Data Register
sahilmgandhi	18:6a4db94011d3	28440	* \| \| \|Endpoint A~L data buffer for the buffer transaction (read or write).
sahilmgandhi	18:6a4db94011d3	28441	* \| \| \|Note: Only word or byte access are supported.
sahilmgandhi	18:6a4db94011d3	28442	*/
sahilmgandhi	18:6a4db94011d3	28443	__IO uint8_t EPCDAT_BYTE;
sahilmgandhi	18:6a4db94011d3	28444
sahilmgandhi	18:6a4db94011d3	28445	}; ///< Define EPC Data Register 32-bit or 8-bit access
sahilmgandhi	18:6a4db94011d3	28446
sahilmgandhi	18:6a4db94011d3	28447	/**
sahilmgandhi	18:6a4db94011d3	28448	* EPCINTSTS
sahilmgandhi	18:6a4db94011d3	28449	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28450	* Offset: 0xB8 Endpoint C Interrupt Status Register
sahilmgandhi	18:6a4db94011d3	28451	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28452	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28453	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28454	* \|[0] \|BUFFULLIF \|Buffer Full
sahilmgandhi	18:6a4db94011d3	28455	* \| \| \|For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
sahilmgandhi	18:6a4db94011d3	28456	* \| \| \|For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
sahilmgandhi	18:6a4db94011d3	28457	* \| \| \|0 = The endpoint packet buffer is not full.
sahilmgandhi	18:6a4db94011d3	28458	* \| \| \|1 = The endpoint packet buffer is full.
sahilmgandhi	18:6a4db94011d3	28459	* \| \| \|Note: This bit is read-only.
sahilmgandhi	18:6a4db94011d3	28460	* \|[1] \|BUFEMPTYIF\|Buffer Empty
sahilmgandhi	18:6a4db94011d3	28461	* \| \| \|For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
sahilmgandhi	18:6a4db94011d3	28462	* \| \| \|0 = The endpoint buffer is not empty.
sahilmgandhi	18:6a4db94011d3	28463	* \| \| \|1 = The endpoint buffer is empty.
sahilmgandhi	18:6a4db94011d3	28464	* \| \| \|For an OUT endpoint:
sahilmgandhi	18:6a4db94011d3	28465	* \| \| \|0 = The currently selected buffer has not a count of 0.
sahilmgandhi	18:6a4db94011d3	28466	* \| \| \|1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
sahilmgandhi	18:6a4db94011d3	28467	* \| \| \|Note: This bit is read-only.
sahilmgandhi	18:6a4db94011d3	28468	* \|[2] \|SHORTTXIF \|Short Packet Transferred Interrupt
sahilmgandhi	18:6a4db94011d3	28469	* \| \| \|0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
sahilmgandhi	18:6a4db94011d3	28470	* \| \| \|1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
sahilmgandhi	18:6a4db94011d3	28471	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28472	* \|[3] \|TXPKIF \|Data Packet Transmitted Interrupt
sahilmgandhi	18:6a4db94011d3	28473	* \| \| \|0 = Not a data packet is transmitted from the endpoint to the host.
sahilmgandhi	18:6a4db94011d3	28474	* \| \| \|1 = A data packet is transmitted from the endpoint to the host.
sahilmgandhi	18:6a4db94011d3	28475	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28476	* \|[4] \|RXPKIF \|Data Packet Received Interrupt
sahilmgandhi	18:6a4db94011d3	28477	* \| \| \|0 = No data packet is received from the host by the endpoint.
sahilmgandhi	18:6a4db94011d3	28478	* \| \| \|1 = A data packet is received from the host by the endpoint.
sahilmgandhi	18:6a4db94011d3	28479	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28480	* \|[5] \|OUTTKIF \|Data OUT Token Interrupt
sahilmgandhi	18:6a4db94011d3	28481	* \| \| \|0 = A Data OUT token has not been received from the host.
sahilmgandhi	18:6a4db94011d3	28482	* \| \| \|1 = A Data OUT token has been received from the host.
sahilmgandhi	18:6a4db94011d3	28483	* \| \| \|This bit also set by PING tokens(in high-speed only).
sahilmgandhi	18:6a4db94011d3	28484	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28485	* \|[6] \|INTKIF \|Data IN Token Interrupt
sahilmgandhi	18:6a4db94011d3	28486	* \| \| \|0 = Not Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	28487	* \| \| \|1 = A Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	28488	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28489	* \|[7] \|PINGIF \|PING Token Interrupt
sahilmgandhi	18:6a4db94011d3	28490	* \| \| \|0 = A Data PING token has not been received from the host.
sahilmgandhi	18:6a4db94011d3	28491	* \| \| \|1 = A Data PING token has been received from the host.
sahilmgandhi	18:6a4db94011d3	28492	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28493	* \|[8] \|NAKIF \|USB NAK Sent
sahilmgandhi	18:6a4db94011d3	28494	* \| \| \|0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
sahilmgandhi	18:6a4db94011d3	28495	* \| \| \|1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
sahilmgandhi	18:6a4db94011d3	28496	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28497	* \|[9] \|STALLIF \|USB STALL Sent
sahilmgandhi	18:6a4db94011d3	28498	* \| \| \|0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
sahilmgandhi	18:6a4db94011d3	28499	* \| \| \|1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
sahilmgandhi	18:6a4db94011d3	28500	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28501	* \|[10] \|NYETIF \|NYET Sent
sahilmgandhi	18:6a4db94011d3	28502	* \| \| \|0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
sahilmgandhi	18:6a4db94011d3	28503	* \| \| \|1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
sahilmgandhi	18:6a4db94011d3	28504	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28505	* \|[11] \|ERRIF \|ERR Sent
sahilmgandhi	18:6a4db94011d3	28506	* \| \| \|0 = No any error in the transaction.
sahilmgandhi	18:6a4db94011d3	28507	* \| \| \|1 = There occurs any error in the transaction.
sahilmgandhi	18:6a4db94011d3	28508	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28509	* \|[12] \|SHORTRXIF \|Bulk Out Short Packet Received
sahilmgandhi	18:6a4db94011d3	28510	* \| \| \|0 = No bulk out short packet is received.
sahilmgandhi	18:6a4db94011d3	28511	* \| \| \|1 = Received bulk out short packet (including zero length packet ).
sahilmgandhi	18:6a4db94011d3	28512	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28513	*/
sahilmgandhi	18:6a4db94011d3	28514	__IO uint32_t EPCINTSTS;
sahilmgandhi	18:6a4db94011d3	28515
sahilmgandhi	18:6a4db94011d3	28516	/**
sahilmgandhi	18:6a4db94011d3	28517	* EPCINTEN
sahilmgandhi	18:6a4db94011d3	28518	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28519	* Offset: 0xBC Endpoint C Interrupt Enable Register
sahilmgandhi	18:6a4db94011d3	28520	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28521	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28522	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28523	* \|[0] \|BUFFULLIEN\|Buffer Full Interrupt
sahilmgandhi	18:6a4db94011d3	28524	* \| \| \|When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
sahilmgandhi	18:6a4db94011d3	28525	* \| \| \|0 = Buffer full interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28526	* \| \| \|1 = Buffer full interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28527	* \|[1] \|BUFEMPTYIEN\|Buffer Empty Interrupt
sahilmgandhi	18:6a4db94011d3	28528	* \| \| \|When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
sahilmgandhi	18:6a4db94011d3	28529	* \| \| \|0 = Buffer empty interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28530	* \| \| \|1 = Buffer empty interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28531	* \|[2] \|SHORTTXIEN\|Short Packet Transferred Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28532	* \| \| \|When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
sahilmgandhi	18:6a4db94011d3	28533	* \| \| \|0 = Short data packet interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28534	* \| \| \|1 = Short data packet interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28535	* \|[3] \|TXPKIEN \|Data Packet Transmitted Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28536	* \| \| \|When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
sahilmgandhi	18:6a4db94011d3	28537	* \| \| \|0 = Data packet has been received from the host interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28538	* \| \| \|1 = Data packet has been received from the host interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28539	* \|[4] \|RXPKIEN \|Data Packet Received Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28540	* \| \| \|When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
sahilmgandhi	18:6a4db94011d3	28541	* \| \| \|0 = Data packet has been transmitted to the host interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28542	* \| \| \|1 = Data packet has been transmitted to the host interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28543	* \|[5] \|OUTTKIEN \|Data OUT Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28544	* \| \| \|When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
sahilmgandhi	18:6a4db94011d3	28545	* \| \| \|0 = Data OUT token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28546	* \| \| \|1 = Data OUT token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28547	* \|[6] \|INTKIEN \|Data IN Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28548	* \| \| \|When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	28549	* \| \| \|0 = Data IN token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28550	* \| \| \|1 = Data IN token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28551	* \|[7] \|PINGIEN \|PING Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28552	* \| \| \|When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
sahilmgandhi	18:6a4db94011d3	28553	* \| \| \|0 = PING token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28554	* \| \| \|1 = PING token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28555	* \|[8] \|NAKIEN \|USB NAK Sent Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28556	* \| \| \|When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
sahilmgandhi	18:6a4db94011d3	28557	* \| \| \|0 = NAK token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28558	* \| \| \|1 = NAK token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28559	* \|[9] \|STALLIEN \|USB STALL Sent Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28560	* \| \| \|When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
sahilmgandhi	18:6a4db94011d3	28561	* \| \| \|0 = STALL token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28562	* \| \| \|1 = STALL token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28563	* \|[10] \|NYETIEN \|NYET Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28564	* \| \| \|When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	28565	* \| \| \|0 = NYET condition interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28566	* \| \| \|1 = NYET condition interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28567	* \|[11] \|ERRIEN \|ERR Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28568	* \| \| \|When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	28569	* \| \| \|0 = Error event interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28570	* \| \| \|1 = Error event interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28571	* \|[12] \|SHORTRXIEN\|Bulk Out Short Packet Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28572	* \| \| \|When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	28573	* \| \| \|0 = Bulk out interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28574	* \| \| \|1 = Bulk out interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28575	*/
sahilmgandhi	18:6a4db94011d3	28576	__IO uint32_t EPCINTEN;
sahilmgandhi	18:6a4db94011d3	28577
sahilmgandhi	18:6a4db94011d3	28578	/**
sahilmgandhi	18:6a4db94011d3	28579	* EPCDATCNT
sahilmgandhi	18:6a4db94011d3	28580	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28581	* Offset: 0xC0 Endpoint C Data Available Count Register
sahilmgandhi	18:6a4db94011d3	28582	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28583	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28584	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28585	* \|[0:15] \|DATCNT \|Data Count
sahilmgandhi	18:6a4db94011d3	28586	* \| \| \|For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
sahilmgandhi	18:6a4db94011d3	28587	* \|[16:30] \|DMALOOP \|DMA Loop
sahilmgandhi	18:6a4db94011d3	28588	* \| \| \|This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
sahilmgandhi	18:6a4db94011d3	28589	*/
sahilmgandhi	18:6a4db94011d3	28590	__I uint32_t EPCDATCNT;
sahilmgandhi	18:6a4db94011d3	28591
sahilmgandhi	18:6a4db94011d3	28592	/**
sahilmgandhi	18:6a4db94011d3	28593	* EPCRSPCTL
sahilmgandhi	18:6a4db94011d3	28594	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28595	* Offset: 0xC4 Endpoint C Response Control Register
sahilmgandhi	18:6a4db94011d3	28596	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28597	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28598	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28599	* \|[0] \|FLUSH \|Buffer Flush
sahilmgandhi	18:6a4db94011d3	28600	* \| \| \|Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
sahilmgandhi	18:6a4db94011d3	28601	* \| \| \|This bit is self-clearing.
sahilmgandhi	18:6a4db94011d3	28602	* \| \| \|This bit should always be written after an configuration event.
sahilmgandhi	18:6a4db94011d3	28603	* \| \| \|0 = The packet buffer is not flushed.
sahilmgandhi	18:6a4db94011d3	28604	* \| \| \|1 = The packet buffer is flushed by user.
sahilmgandhi	18:6a4db94011d3	28605	* \|[1:2] \|MODE \|Mode Control
sahilmgandhi	18:6a4db94011d3	28606	* \| \| \|The two bits decide the operation mode of the in-endpoint.
sahilmgandhi	18:6a4db94011d3	28607	* \| \| \|00: Auto-Validate Mode
sahilmgandhi	18:6a4db94011d3	28608	* \| \| \|01: Manual-Validate Mode
sahilmgandhi	18:6a4db94011d3	28609	* \| \| \|10: Fly Mode
sahilmgandhi	18:6a4db94011d3	28610	* \| \| \|11: Reserved
sahilmgandhi	18:6a4db94011d3	28611	* \| \| \|These bits are not valid for an out-endpoint.
sahilmgandhi	18:6a4db94011d3	28612	* \| \| \|The auto validate mode will be activated when the reserved mode is selected.
sahilmgandhi	18:6a4db94011d3	28613	* \|[3] \|TOGGLE \|Endpoint Toggle
sahilmgandhi	18:6a4db94011d3	28614	* \| \| \|This bit is used to clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	28615	* \| \| \|Reading this bit returns the current state of the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	28616	* \| \| \|The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
sahilmgandhi	18:6a4db94011d3	28617	* \| \| \|Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
sahilmgandhi	18:6a4db94011d3	28618	* \| \| \|0 = Not clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	28619	* \| \| \|1 = Clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	28620	* \|[4] \|HALT \|Endpoint Halt
sahilmgandhi	18:6a4db94011d3	28621	* \| \| \|This bit is used to send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	28622	* \| \| \|When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
sahilmgandhi	18:6a4db94011d3	28623	* \| \| \|0 = Not send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	28624	* \| \| \|1 = Send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	28625	* \|[5] \|ZEROLEN \|Zero Length
sahilmgandhi	18:6a4db94011d3	28626	* \| \| \|This bit is used to send a zero-length packet n response to an IN-token.
sahilmgandhi	18:6a4db94011d3	28627	* \| \| \|When this bit is set, a zero packet is sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	28628	* \| \| \|0 = A zero packet is not sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	28629	* \| \| \|1 = A zero packet is sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	28630	* \|[6] \|SHORTTXEN \|Short Packet Transfer Enable
sahilmgandhi	18:6a4db94011d3	28631	* \| \| \|This bit is applicable only in case of Auto-Validate Method.
sahilmgandhi	18:6a4db94011d3	28632	* \| \| \|This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
sahilmgandhi	18:6a4db94011d3	28633	* \| \| \|0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
sahilmgandhi	18:6a4db94011d3	28634	* \| \| \|1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
sahilmgandhi	18:6a4db94011d3	28635	* \|[7] \|DISBUF \|Buffer Disable Control
sahilmgandhi	18:6a4db94011d3	28636	* \| \| \|This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	28637	* \| \| \|0 = Buffer Not Disabled when Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	28638	* \| \| \|1 = Buffer Disabled when Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	28639	*/
sahilmgandhi	18:6a4db94011d3	28640	__IO uint32_t EPCRSPCTL;
sahilmgandhi	18:6a4db94011d3	28641
sahilmgandhi	18:6a4db94011d3	28642	/**
sahilmgandhi	18:6a4db94011d3	28643	* EPCMPS
sahilmgandhi	18:6a4db94011d3	28644	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28645	* Offset: 0xC8 Endpoint C Maximum Packet Size Register
sahilmgandhi	18:6a4db94011d3	28646	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28647	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28648	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28649	* \|[0:10] \|EPMPS \|Endpoint Maximum Packet Size
sahilmgandhi	18:6a4db94011d3	28650	* \| \| \|This field determines the Maximum Packet Size of the Endpoint.
sahilmgandhi	18:6a4db94011d3	28651	*/
sahilmgandhi	18:6a4db94011d3	28652	__IO uint32_t EPCMPS;
sahilmgandhi	18:6a4db94011d3	28653
sahilmgandhi	18:6a4db94011d3	28654	/**
sahilmgandhi	18:6a4db94011d3	28655	* EPCTXCNT
sahilmgandhi	18:6a4db94011d3	28656	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28657	* Offset: 0xCC Endpoint C Transfer Count Register
sahilmgandhi	18:6a4db94011d3	28658	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28659	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28660	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28661	* \|[0:10] \|TXCNT \|Endpoint Transfer Count
sahilmgandhi	18:6a4db94011d3	28662	* \| \| \|For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
sahilmgandhi	18:6a4db94011d3	28663	* \| \| \|For OUT endpoints, this field has no effect.
sahilmgandhi	18:6a4db94011d3	28664	*/
sahilmgandhi	18:6a4db94011d3	28665	__IO uint32_t EPCTXCNT;
sahilmgandhi	18:6a4db94011d3	28666
sahilmgandhi	18:6a4db94011d3	28667	/**
sahilmgandhi	18:6a4db94011d3	28668	* EPCCFG
sahilmgandhi	18:6a4db94011d3	28669	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28670	* Offset: 0xD0 Endpoint C Configuration Register
sahilmgandhi	18:6a4db94011d3	28671	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28672	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28673	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28674	* \|[0] \|EPEN \|Endpoint Valid
sahilmgandhi	18:6a4db94011d3	28675	* \| \| \|When set, this bit enables this endpoint.
sahilmgandhi	18:6a4db94011d3	28676	* \| \| \|This bit has no effect on Endpoint 0, which is always enabled.
sahilmgandhi	18:6a4db94011d3	28677	* \| \| \|0 = The endpoint Disabled.
sahilmgandhi	18:6a4db94011d3	28678	* \| \| \|1 = The endpoint Enabled.
sahilmgandhi	18:6a4db94011d3	28679	* \|[1:2] \|EPTYPE \|Endpoint Type
sahilmgandhi	18:6a4db94011d3	28680	* \| \| \|This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
sahilmgandhi	18:6a4db94011d3	28681	* \| \| \|00 = Reserved.
sahilmgandhi	18:6a4db94011d3	28682	* \| \| \|01 = Bulk.
sahilmgandhi	18:6a4db94011d3	28683	* \| \| \|10 = Interrupt.
sahilmgandhi	18:6a4db94011d3	28684	* \| \| \|11 = Isochronous.
sahilmgandhi	18:6a4db94011d3	28685	* \|[3] \|EPDIR \|Endpoint Direction
sahilmgandhi	18:6a4db94011d3	28686	* \| \| \|0 = out-endpoint (Host OUT to Device).
sahilmgandhi	18:6a4db94011d3	28687	* \| \| \|1 = in-endpoint (Host IN to Device).
sahilmgandhi	18:6a4db94011d3	28688	* \| \| \|Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
sahilmgandhi	18:6a4db94011d3	28689	* \|[4:7] \|EPNUM \|Endpoint Number
sahilmgandhi	18:6a4db94011d3	28690	* \| \| \|This field selects the number of the endpoint. Valid numbers 1 to 15.
sahilmgandhi	18:6a4db94011d3	28691	*/
sahilmgandhi	18:6a4db94011d3	28692	__IO uint32_t EPCCFG;
sahilmgandhi	18:6a4db94011d3	28693
sahilmgandhi	18:6a4db94011d3	28694	/**
sahilmgandhi	18:6a4db94011d3	28695	* EPCBUFSTART
sahilmgandhi	18:6a4db94011d3	28696	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28697	* Offset: 0xD4 Endpoint C RAM Start Address Register
sahilmgandhi	18:6a4db94011d3	28698	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28699	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28700	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28701	* \|[0:11] \|SADDR \|Endpoint Start Address
sahilmgandhi	18:6a4db94011d3	28702	* \| \| \|This is the start-address of the RAM space allocated for the endpoint A~L.
sahilmgandhi	18:6a4db94011d3	28703	*/
sahilmgandhi	18:6a4db94011d3	28704	__IO uint32_t EPCBUFSTART;
sahilmgandhi	18:6a4db94011d3	28705
sahilmgandhi	18:6a4db94011d3	28706	/**
sahilmgandhi	18:6a4db94011d3	28707	* EPCBUFEND
sahilmgandhi	18:6a4db94011d3	28708	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28709	* Offset: 0xD8 Endpoint C RAM End Address Register
sahilmgandhi	18:6a4db94011d3	28710	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28711	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28712	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28713	* \|[0:11] \|EADDR \|Endpoint End Address
sahilmgandhi	18:6a4db94011d3	28714	* \| \| \|This is the end-address of the RAM space allocated for the endpoint A~L.
sahilmgandhi	18:6a4db94011d3	28715	*/
sahilmgandhi	18:6a4db94011d3	28716	__IO uint32_t EPCBUFEND;
sahilmgandhi	18:6a4db94011d3	28717
sahilmgandhi	18:6a4db94011d3	28718	union {
sahilmgandhi	18:6a4db94011d3	28719
sahilmgandhi	18:6a4db94011d3	28720	/**
sahilmgandhi	18:6a4db94011d3	28721	* EPDDAT
sahilmgandhi	18:6a4db94011d3	28722	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28723	* Offset: 0xDC Endpoint D Data Register
sahilmgandhi	18:6a4db94011d3	28724	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28725	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28726	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28727	* \|[0:31] \|EPDAT \|Endpoint A~L Data Register
sahilmgandhi	18:6a4db94011d3	28728	* \| \| \|Endpoint A~L data buffer for the buffer transaction (read or write).
sahilmgandhi	18:6a4db94011d3	28729	* \| \| \|Note: Only word or byte access are supported.
sahilmgandhi	18:6a4db94011d3	28730	*/
sahilmgandhi	18:6a4db94011d3	28731	__IO uint32_t EPDDAT;
sahilmgandhi	18:6a4db94011d3	28732	/**
sahilmgandhi	18:6a4db94011d3	28733	* EPDDAT_BYTE
sahilmgandhi	18:6a4db94011d3	28734	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28735	* Offset: 0xDC Endpoint D Data Register for Byte Access
sahilmgandhi	18:6a4db94011d3	28736	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28737	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28738	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28739	* \|[0:7] \|EPDAT \|Endpoint A~L Data Register
sahilmgandhi	18:6a4db94011d3	28740	* \| \| \|Endpoint A~L data buffer for the buffer transaction (read or write).
sahilmgandhi	18:6a4db94011d3	28741	* \| \| \|Note: Only word or byte access are supported.
sahilmgandhi	18:6a4db94011d3	28742	*/
sahilmgandhi	18:6a4db94011d3	28743	__IO uint8_t EPDDAT_BYTE;
sahilmgandhi	18:6a4db94011d3	28744
sahilmgandhi	18:6a4db94011d3	28745	}; ///< Define EPD Data Register 32-bit or 8-bit access
sahilmgandhi	18:6a4db94011d3	28746
sahilmgandhi	18:6a4db94011d3	28747	/**
sahilmgandhi	18:6a4db94011d3	28748	* EPDINTSTS
sahilmgandhi	18:6a4db94011d3	28749	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28750	* Offset: 0xE0 Endpoint D Interrupt Status Register
sahilmgandhi	18:6a4db94011d3	28751	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28752	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28753	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28754	* \|[0] \|BUFFULLIF \|Buffer Full
sahilmgandhi	18:6a4db94011d3	28755	* \| \| \|For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
sahilmgandhi	18:6a4db94011d3	28756	* \| \| \|For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
sahilmgandhi	18:6a4db94011d3	28757	* \| \| \|0 = The endpoint packet buffer is not full.
sahilmgandhi	18:6a4db94011d3	28758	* \| \| \|1 = The endpoint packet buffer is full.
sahilmgandhi	18:6a4db94011d3	28759	* \| \| \|Note: This bit is read-only.
sahilmgandhi	18:6a4db94011d3	28760	* \|[1] \|BUFEMPTYIF\|Buffer Empty
sahilmgandhi	18:6a4db94011d3	28761	* \| \| \|For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
sahilmgandhi	18:6a4db94011d3	28762	* \| \| \|0 = The endpoint buffer is not empty.
sahilmgandhi	18:6a4db94011d3	28763	* \| \| \|1 = The endpoint buffer is empty.
sahilmgandhi	18:6a4db94011d3	28764	* \| \| \|For an OUT endpoint:
sahilmgandhi	18:6a4db94011d3	28765	* \| \| \|0 = The currently selected buffer has not a count of 0.
sahilmgandhi	18:6a4db94011d3	28766	* \| \| \|1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
sahilmgandhi	18:6a4db94011d3	28767	* \| \| \|Note: This bit is read-only.
sahilmgandhi	18:6a4db94011d3	28768	* \|[2] \|SHORTTXIF \|Short Packet Transferred Interrupt
sahilmgandhi	18:6a4db94011d3	28769	* \| \| \|0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
sahilmgandhi	18:6a4db94011d3	28770	* \| \| \|1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
sahilmgandhi	18:6a4db94011d3	28771	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28772	* \|[3] \|TXPKIF \|Data Packet Transmitted Interrupt
sahilmgandhi	18:6a4db94011d3	28773	* \| \| \|0 = Not a data packet is transmitted from the endpoint to the host.
sahilmgandhi	18:6a4db94011d3	28774	* \| \| \|1 = A data packet is transmitted from the endpoint to the host.
sahilmgandhi	18:6a4db94011d3	28775	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28776	* \|[4] \|RXPKIF \|Data Packet Received Interrupt
sahilmgandhi	18:6a4db94011d3	28777	* \| \| \|0 = No data packet is received from the host by the endpoint.
sahilmgandhi	18:6a4db94011d3	28778	* \| \| \|1 = A data packet is received from the host by the endpoint.
sahilmgandhi	18:6a4db94011d3	28779	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28780	* \|[5] \|OUTTKIF \|Data OUT Token Interrupt
sahilmgandhi	18:6a4db94011d3	28781	* \| \| \|0 = A Data OUT token has not been received from the host.
sahilmgandhi	18:6a4db94011d3	28782	* \| \| \|1 = A Data OUT token has been received from the host.
sahilmgandhi	18:6a4db94011d3	28783	* \| \| \|This bit also set by PING tokens(in high-speed only).
sahilmgandhi	18:6a4db94011d3	28784	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28785	* \|[6] \|INTKIF \|Data IN Token Interrupt
sahilmgandhi	18:6a4db94011d3	28786	* \| \| \|0 = Not Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	28787	* \| \| \|1 = A Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	28788	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28789	* \|[7] \|PINGIF \|PING Token Interrupt
sahilmgandhi	18:6a4db94011d3	28790	* \| \| \|0 = A Data PING token has not been received from the host.
sahilmgandhi	18:6a4db94011d3	28791	* \| \| \|1 = A Data PING token has been received from the host.
sahilmgandhi	18:6a4db94011d3	28792	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28793	* \|[8] \|NAKIF \|USB NAK Sent
sahilmgandhi	18:6a4db94011d3	28794	* \| \| \|0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
sahilmgandhi	18:6a4db94011d3	28795	* \| \| \|1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
sahilmgandhi	18:6a4db94011d3	28796	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28797	* \|[9] \|STALLIF \|USB STALL Sent
sahilmgandhi	18:6a4db94011d3	28798	* \| \| \|0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
sahilmgandhi	18:6a4db94011d3	28799	* \| \| \|1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
sahilmgandhi	18:6a4db94011d3	28800	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28801	* \|[10] \|NYETIF \|NYET Sent
sahilmgandhi	18:6a4db94011d3	28802	* \| \| \|0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
sahilmgandhi	18:6a4db94011d3	28803	* \| \| \|1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
sahilmgandhi	18:6a4db94011d3	28804	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28805	* \|[11] \|ERRIF \|ERR Sent
sahilmgandhi	18:6a4db94011d3	28806	* \| \| \|0 = No any error in the transaction.
sahilmgandhi	18:6a4db94011d3	28807	* \| \| \|1 = There occurs any error in the transaction.
sahilmgandhi	18:6a4db94011d3	28808	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28809	* \|[12] \|SHORTRXIF \|Bulk Out Short Packet Received
sahilmgandhi	18:6a4db94011d3	28810	* \| \| \|0 = No bulk out short packet is received.
sahilmgandhi	18:6a4db94011d3	28811	* \| \| \|1 = Received bulk out short packet (including zero length packet ).
sahilmgandhi	18:6a4db94011d3	28812	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	28813	*/
sahilmgandhi	18:6a4db94011d3	28814	__IO uint32_t EPDINTSTS;
sahilmgandhi	18:6a4db94011d3	28815
sahilmgandhi	18:6a4db94011d3	28816	/**
sahilmgandhi	18:6a4db94011d3	28817	* EPDINTEN
sahilmgandhi	18:6a4db94011d3	28818	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28819	* Offset: 0xE4 Endpoint D Interrupt Enable Register
sahilmgandhi	18:6a4db94011d3	28820	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28821	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28822	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28823	* \|[0] \|BUFFULLIEN\|Buffer Full Interrupt
sahilmgandhi	18:6a4db94011d3	28824	* \| \| \|When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
sahilmgandhi	18:6a4db94011d3	28825	* \| \| \|0 = Buffer full interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28826	* \| \| \|1 = Buffer full interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28827	* \|[1] \|BUFEMPTYIEN\|Buffer Empty Interrupt
sahilmgandhi	18:6a4db94011d3	28828	* \| \| \|When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
sahilmgandhi	18:6a4db94011d3	28829	* \| \| \|0 = Buffer empty interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28830	* \| \| \|1 = Buffer empty interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28831	* \|[2] \|SHORTTXIEN\|Short Packet Transferred Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28832	* \| \| \|When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
sahilmgandhi	18:6a4db94011d3	28833	* \| \| \|0 = Short data packet interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28834	* \| \| \|1 = Short data packet interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28835	* \|[3] \|TXPKIEN \|Data Packet Transmitted Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28836	* \| \| \|When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
sahilmgandhi	18:6a4db94011d3	28837	* \| \| \|0 = Data packet has been received from the host interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28838	* \| \| \|1 = Data packet has been received from the host interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28839	* \|[4] \|RXPKIEN \|Data Packet Received Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28840	* \| \| \|When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
sahilmgandhi	18:6a4db94011d3	28841	* \| \| \|0 = Data packet has been transmitted to the host interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28842	* \| \| \|1 = Data packet has been transmitted to the host interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28843	* \|[5] \|OUTTKIEN \|Data OUT Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28844	* \| \| \|When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
sahilmgandhi	18:6a4db94011d3	28845	* \| \| \|0 = Data OUT token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28846	* \| \| \|1 = Data OUT token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28847	* \|[6] \|INTKIEN \|Data IN Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28848	* \| \| \|When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	28849	* \| \| \|0 = Data IN token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28850	* \| \| \|1 = Data IN token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28851	* \|[7] \|PINGIEN \|PING Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28852	* \| \| \|When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
sahilmgandhi	18:6a4db94011d3	28853	* \| \| \|0 = PING token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28854	* \| \| \|1 = PING token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28855	* \|[8] \|NAKIEN \|USB NAK Sent Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28856	* \| \| \|When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
sahilmgandhi	18:6a4db94011d3	28857	* \| \| \|0 = NAK token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28858	* \| \| \|1 = NAK token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28859	* \|[9] \|STALLIEN \|USB STALL Sent Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28860	* \| \| \|When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
sahilmgandhi	18:6a4db94011d3	28861	* \| \| \|0 = STALL token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28862	* \| \| \|1 = STALL token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28863	* \|[10] \|NYETIEN \|NYET Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28864	* \| \| \|When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	28865	* \| \| \|0 = NYET condition interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28866	* \| \| \|1 = NYET condition interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28867	* \|[11] \|ERRIEN \|ERR Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28868	* \| \| \|When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	28869	* \| \| \|0 = Error event interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28870	* \| \| \|1 = Error event interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28871	* \|[12] \|SHORTRXIEN\|Bulk Out Short Packet Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	28872	* \| \| \|When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	28873	* \| \| \|0 = Bulk out interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	28874	* \| \| \|1 = Bulk out interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	28875	*/
sahilmgandhi	18:6a4db94011d3	28876	__IO uint32_t EPDINTEN;
sahilmgandhi	18:6a4db94011d3	28877
sahilmgandhi	18:6a4db94011d3	28878	/**
sahilmgandhi	18:6a4db94011d3	28879	* EPDDATCNT
sahilmgandhi	18:6a4db94011d3	28880	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28881	* Offset: 0xE8 Endpoint D Data Available Count Register
sahilmgandhi	18:6a4db94011d3	28882	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28883	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28884	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28885	* \|[0:15] \|DATCNT \|Data Count
sahilmgandhi	18:6a4db94011d3	28886	* \| \| \|For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
sahilmgandhi	18:6a4db94011d3	28887	* \|[16:30] \|DMALOOP \|DMA Loop
sahilmgandhi	18:6a4db94011d3	28888	* \| \| \|This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
sahilmgandhi	18:6a4db94011d3	28889	*/
sahilmgandhi	18:6a4db94011d3	28890	__I uint32_t EPDDATCNT;
sahilmgandhi	18:6a4db94011d3	28891
sahilmgandhi	18:6a4db94011d3	28892	/**
sahilmgandhi	18:6a4db94011d3	28893	* EPDRSPCTL
sahilmgandhi	18:6a4db94011d3	28894	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28895	* Offset: 0xEC Endpoint D Response Control Register
sahilmgandhi	18:6a4db94011d3	28896	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28897	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28898	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28899	* \|[0] \|FLUSH \|Buffer Flush
sahilmgandhi	18:6a4db94011d3	28900	* \| \| \|Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
sahilmgandhi	18:6a4db94011d3	28901	* \| \| \|This bit is self-clearing.
sahilmgandhi	18:6a4db94011d3	28902	* \| \| \|This bit should always be written after an configuration event.
sahilmgandhi	18:6a4db94011d3	28903	* \| \| \|0 = The packet buffer is not flushed.
sahilmgandhi	18:6a4db94011d3	28904	* \| \| \|1 = The packet buffer is flushed by user.
sahilmgandhi	18:6a4db94011d3	28905	* \|[1:2] \|MODE \|Mode Control
sahilmgandhi	18:6a4db94011d3	28906	* \| \| \|The two bits decide the operation mode of the in-endpoint.
sahilmgandhi	18:6a4db94011d3	28907	* \| \| \|00: Auto-Validate Mode
sahilmgandhi	18:6a4db94011d3	28908	* \| \| \|01: Manual-Validate Mode
sahilmgandhi	18:6a4db94011d3	28909	* \| \| \|10: Fly Mode
sahilmgandhi	18:6a4db94011d3	28910	* \| \| \|11: Reserved
sahilmgandhi	18:6a4db94011d3	28911	* \| \| \|These bits are not valid for an out-endpoint.
sahilmgandhi	18:6a4db94011d3	28912	* \| \| \|The auto validate mode will be activated when the reserved mode is selected.
sahilmgandhi	18:6a4db94011d3	28913	* \|[3] \|TOGGLE \|Endpoint Toggle
sahilmgandhi	18:6a4db94011d3	28914	* \| \| \|This bit is used to clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	28915	* \| \| \|Reading this bit returns the current state of the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	28916	* \| \| \|The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
sahilmgandhi	18:6a4db94011d3	28917	* \| \| \|Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
sahilmgandhi	18:6a4db94011d3	28918	* \| \| \|0 = Not clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	28919	* \| \| \|1 = Clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	28920	* \|[4] \|HALT \|Endpoint Halt
sahilmgandhi	18:6a4db94011d3	28921	* \| \| \|This bit is used to send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	28922	* \| \| \|When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
sahilmgandhi	18:6a4db94011d3	28923	* \| \| \|0 = Not send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	28924	* \| \| \|1 = Send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	28925	* \|[5] \|ZEROLEN \|Zero Length
sahilmgandhi	18:6a4db94011d3	28926	* \| \| \|This bit is used to send a zero-length packet n response to an IN-token.
sahilmgandhi	18:6a4db94011d3	28927	* \| \| \|When this bit is set, a zero packet is sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	28928	* \| \| \|0 = A zero packet is not sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	28929	* \| \| \|1 = A zero packet is sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	28930	* \|[6] \|SHORTTXEN \|Short Packet Transfer Enable
sahilmgandhi	18:6a4db94011d3	28931	* \| \| \|This bit is applicable only in case of Auto-Validate Method.
sahilmgandhi	18:6a4db94011d3	28932	* \| \| \|This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
sahilmgandhi	18:6a4db94011d3	28933	* \| \| \|0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
sahilmgandhi	18:6a4db94011d3	28934	* \| \| \|1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
sahilmgandhi	18:6a4db94011d3	28935	* \|[7] \|DISBUF \|Buffer Disable Control
sahilmgandhi	18:6a4db94011d3	28936	* \| \| \|This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	28937	* \| \| \|0 = Buffer Not Disabled when Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	28938	* \| \| \|1 = Buffer Disabled when Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	28939	*/
sahilmgandhi	18:6a4db94011d3	28940	__IO uint32_t EPDRSPCTL;
sahilmgandhi	18:6a4db94011d3	28941
sahilmgandhi	18:6a4db94011d3	28942	/**
sahilmgandhi	18:6a4db94011d3	28943	* EPDMPS
sahilmgandhi	18:6a4db94011d3	28944	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28945	* Offset: 0xF0 Endpoint D Maximum Packet Size Register
sahilmgandhi	18:6a4db94011d3	28946	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28947	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28948	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28949	* \|[0:10] \|EPMPS \|Endpoint Maximum Packet Size
sahilmgandhi	18:6a4db94011d3	28950	* \| \| \|This field determines the Maximum Packet Size of the Endpoint.
sahilmgandhi	18:6a4db94011d3	28951	*/
sahilmgandhi	18:6a4db94011d3	28952	__IO uint32_t EPDMPS;
sahilmgandhi	18:6a4db94011d3	28953
sahilmgandhi	18:6a4db94011d3	28954	/**
sahilmgandhi	18:6a4db94011d3	28955	* EPDTXCNT
sahilmgandhi	18:6a4db94011d3	28956	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28957	* Offset: 0xF4 Endpoint D Transfer Count Register
sahilmgandhi	18:6a4db94011d3	28958	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28959	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28960	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28961	* \|[0:10] \|TXCNT \|Endpoint Transfer Count
sahilmgandhi	18:6a4db94011d3	28962	* \| \| \|For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
sahilmgandhi	18:6a4db94011d3	28963	* \| \| \|For OUT endpoints, this field has no effect.
sahilmgandhi	18:6a4db94011d3	28964	*/
sahilmgandhi	18:6a4db94011d3	28965	__IO uint32_t EPDTXCNT;
sahilmgandhi	18:6a4db94011d3	28966
sahilmgandhi	18:6a4db94011d3	28967	/**
sahilmgandhi	18:6a4db94011d3	28968	* EPDCFG
sahilmgandhi	18:6a4db94011d3	28969	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28970	* Offset: 0xF8 Endpoint D Configuration Register
sahilmgandhi	18:6a4db94011d3	28971	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28972	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	28973	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	28974	* \|[0] \|EPEN \|Endpoint Valid
sahilmgandhi	18:6a4db94011d3	28975	* \| \| \|When set, this bit enables this endpoint.
sahilmgandhi	18:6a4db94011d3	28976	* \| \| \|This bit has no effect on Endpoint 0, which is always enabled.
sahilmgandhi	18:6a4db94011d3	28977	* \| \| \|0 = The endpoint Disabled.
sahilmgandhi	18:6a4db94011d3	28978	* \| \| \|1 = The endpoint Enabled.
sahilmgandhi	18:6a4db94011d3	28979	* \|[1:2] \|EPTYPE \|Endpoint Type
sahilmgandhi	18:6a4db94011d3	28980	* \| \| \|This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
sahilmgandhi	18:6a4db94011d3	28981	* \| \| \|00 = Reserved.
sahilmgandhi	18:6a4db94011d3	28982	* \| \| \|01 = Bulk.
sahilmgandhi	18:6a4db94011d3	28983	* \| \| \|10 = Interrupt.
sahilmgandhi	18:6a4db94011d3	28984	* \| \| \|11 = Isochronous.
sahilmgandhi	18:6a4db94011d3	28985	* \|[3] \|EPDIR \|Endpoint Direction
sahilmgandhi	18:6a4db94011d3	28986	* \| \| \|0 = out-endpoint (Host OUT to Device).
sahilmgandhi	18:6a4db94011d3	28987	* \| \| \|1 = in-endpoint (Host IN to Device).
sahilmgandhi	18:6a4db94011d3	28988	* \| \| \|Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
sahilmgandhi	18:6a4db94011d3	28989	* \|[4:7] \|EPNUM \|Endpoint Number
sahilmgandhi	18:6a4db94011d3	28990	* \| \| \|This field selects the number of the endpoint. Valid numbers 1 to 15.
sahilmgandhi	18:6a4db94011d3	28991	*/
sahilmgandhi	18:6a4db94011d3	28992	__IO uint32_t EPDCFG;
sahilmgandhi	18:6a4db94011d3	28993
sahilmgandhi	18:6a4db94011d3	28994	/**
sahilmgandhi	18:6a4db94011d3	28995	* EPDBUFSTART
sahilmgandhi	18:6a4db94011d3	28996	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	28997	* Offset: 0xFC Endpoint D RAM Start Address Register
sahilmgandhi	18:6a4db94011d3	28998	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	28999	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29000	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29001	* \|[0:11] \|SADDR \|Endpoint Start Address
sahilmgandhi	18:6a4db94011d3	29002	* \| \| \|This is the start-address of the RAM space allocated for the endpoint A~L.
sahilmgandhi	18:6a4db94011d3	29003	*/
sahilmgandhi	18:6a4db94011d3	29004	__IO uint32_t EPDBUFSTART;
sahilmgandhi	18:6a4db94011d3	29005
sahilmgandhi	18:6a4db94011d3	29006	/**
sahilmgandhi	18:6a4db94011d3	29007	* EPDBUFEND
sahilmgandhi	18:6a4db94011d3	29008	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29009	* Offset: 0x100 Endpoint D RAM End Address Register
sahilmgandhi	18:6a4db94011d3	29010	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29011	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29012	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29013	* \|[0:11] \|EADDR \|Endpoint End Address
sahilmgandhi	18:6a4db94011d3	29014	* \| \| \|This is the end-address of the RAM space allocated for the endpoint A~L.
sahilmgandhi	18:6a4db94011d3	29015	*/
sahilmgandhi	18:6a4db94011d3	29016	__IO uint32_t EPDBUFEND;
sahilmgandhi	18:6a4db94011d3	29017
sahilmgandhi	18:6a4db94011d3	29018	union {
sahilmgandhi	18:6a4db94011d3	29019
sahilmgandhi	18:6a4db94011d3	29020	/**
sahilmgandhi	18:6a4db94011d3	29021	* EPEDAT
sahilmgandhi	18:6a4db94011d3	29022	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29023	* Offset: 0x104 Endpoint E Data Register
sahilmgandhi	18:6a4db94011d3	29024	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29025	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29026	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29027	* \|[0:31] \|EPDAT \|Endpoint A~L Data Register
sahilmgandhi	18:6a4db94011d3	29028	* \| \| \|Endpoint A~L data buffer for the buffer transaction (read or write).
sahilmgandhi	18:6a4db94011d3	29029	* \| \| \|Note: Only word or byte access are supported.
sahilmgandhi	18:6a4db94011d3	29030	*/
sahilmgandhi	18:6a4db94011d3	29031	__IO uint32_t EPEDAT;
sahilmgandhi	18:6a4db94011d3	29032	/**
sahilmgandhi	18:6a4db94011d3	29033	* EPEDAT_BYTE
sahilmgandhi	18:6a4db94011d3	29034	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29035	* Offset: 0x104 Endpoint E Data Register for Byte Access
sahilmgandhi	18:6a4db94011d3	29036	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29037	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29038	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29039	* \|[0:7] \|EPDAT \|Endpoint A~L Data Register
sahilmgandhi	18:6a4db94011d3	29040	* \| \| \|Endpoint A~L data buffer for the buffer transaction (read or write).
sahilmgandhi	18:6a4db94011d3	29041	* \| \| \|Note: Only word or byte access are supported.
sahilmgandhi	18:6a4db94011d3	29042	*/
sahilmgandhi	18:6a4db94011d3	29043	__IO uint8_t EPEDAT_BYTE;
sahilmgandhi	18:6a4db94011d3	29044
sahilmgandhi	18:6a4db94011d3	29045	}; ///< Define EPE Data Register 32-bit or 8-bit access
sahilmgandhi	18:6a4db94011d3	29046
sahilmgandhi	18:6a4db94011d3	29047	/**
sahilmgandhi	18:6a4db94011d3	29048	* EPEINTSTS
sahilmgandhi	18:6a4db94011d3	29049	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29050	* Offset: 0x108 Endpoint E Interrupt Status Register
sahilmgandhi	18:6a4db94011d3	29051	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29052	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29053	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29054	* \|[0] \|BUFFULLIF \|Buffer Full
sahilmgandhi	18:6a4db94011d3	29055	* \| \| \|For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
sahilmgandhi	18:6a4db94011d3	29056	* \| \| \|For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
sahilmgandhi	18:6a4db94011d3	29057	* \| \| \|0 = The endpoint packet buffer is not full.
sahilmgandhi	18:6a4db94011d3	29058	* \| \| \|1 = The endpoint packet buffer is full.
sahilmgandhi	18:6a4db94011d3	29059	* \| \| \|Note: This bit is read-only.
sahilmgandhi	18:6a4db94011d3	29060	* \|[1] \|BUFEMPTYIF\|Buffer Empty
sahilmgandhi	18:6a4db94011d3	29061	* \| \| \|For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
sahilmgandhi	18:6a4db94011d3	29062	* \| \| \|0 = The endpoint buffer is not empty.
sahilmgandhi	18:6a4db94011d3	29063	* \| \| \|1 = The endpoint buffer is empty.
sahilmgandhi	18:6a4db94011d3	29064	* \| \| \|For an OUT endpoint:
sahilmgandhi	18:6a4db94011d3	29065	* \| \| \|0 = The currently selected buffer has not a count of 0.
sahilmgandhi	18:6a4db94011d3	29066	* \| \| \|1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
sahilmgandhi	18:6a4db94011d3	29067	* \| \| \|Note: This bit is read-only.
sahilmgandhi	18:6a4db94011d3	29068	* \|[2] \|SHORTTXIF \|Short Packet Transferred Interrupt
sahilmgandhi	18:6a4db94011d3	29069	* \| \| \|0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
sahilmgandhi	18:6a4db94011d3	29070	* \| \| \|1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
sahilmgandhi	18:6a4db94011d3	29071	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29072	* \|[3] \|TXPKIF \|Data Packet Transmitted Interrupt
sahilmgandhi	18:6a4db94011d3	29073	* \| \| \|0 = Not a data packet is transmitted from the endpoint to the host.
sahilmgandhi	18:6a4db94011d3	29074	* \| \| \|1 = A data packet is transmitted from the endpoint to the host.
sahilmgandhi	18:6a4db94011d3	29075	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29076	* \|[4] \|RXPKIF \|Data Packet Received Interrupt
sahilmgandhi	18:6a4db94011d3	29077	* \| \| \|0 = No data packet is received from the host by the endpoint.
sahilmgandhi	18:6a4db94011d3	29078	* \| \| \|1 = A data packet is received from the host by the endpoint.
sahilmgandhi	18:6a4db94011d3	29079	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29080	* \|[5] \|OUTTKIF \|Data OUT Token Interrupt
sahilmgandhi	18:6a4db94011d3	29081	* \| \| \|0 = A Data OUT token has not been received from the host.
sahilmgandhi	18:6a4db94011d3	29082	* \| \| \|1 = A Data OUT token has been received from the host.
sahilmgandhi	18:6a4db94011d3	29083	* \| \| \|This bit also set by PING tokens(in high-speed only).
sahilmgandhi	18:6a4db94011d3	29084	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29085	* \|[6] \|INTKIF \|Data IN Token Interrupt
sahilmgandhi	18:6a4db94011d3	29086	* \| \| \|0 = Not Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	29087	* \| \| \|1 = A Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	29088	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29089	* \|[7] \|PINGIF \|PING Token Interrupt
sahilmgandhi	18:6a4db94011d3	29090	* \| \| \|0 = A Data PING token has not been received from the host.
sahilmgandhi	18:6a4db94011d3	29091	* \| \| \|1 = A Data PING token has been received from the host.
sahilmgandhi	18:6a4db94011d3	29092	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29093	* \|[8] \|NAKIF \|USB NAK Sent
sahilmgandhi	18:6a4db94011d3	29094	* \| \| \|0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
sahilmgandhi	18:6a4db94011d3	29095	* \| \| \|1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
sahilmgandhi	18:6a4db94011d3	29096	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29097	* \|[9] \|STALLIF \|USB STALL Sent
sahilmgandhi	18:6a4db94011d3	29098	* \| \| \|0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
sahilmgandhi	18:6a4db94011d3	29099	* \| \| \|1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
sahilmgandhi	18:6a4db94011d3	29100	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29101	* \|[10] \|NYETIF \|NYET Sent
sahilmgandhi	18:6a4db94011d3	29102	* \| \| \|0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
sahilmgandhi	18:6a4db94011d3	29103	* \| \| \|1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
sahilmgandhi	18:6a4db94011d3	29104	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29105	* \|[11] \|ERRIF \|ERR Sent
sahilmgandhi	18:6a4db94011d3	29106	* \| \| \|0 = No any error in the transaction.
sahilmgandhi	18:6a4db94011d3	29107	* \| \| \|1 = There occurs any error in the transaction.
sahilmgandhi	18:6a4db94011d3	29108	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29109	* \|[12] \|SHORTRXIF \|Bulk Out Short Packet Received
sahilmgandhi	18:6a4db94011d3	29110	* \| \| \|0 = No bulk out short packet is received.
sahilmgandhi	18:6a4db94011d3	29111	* \| \| \|1 = Received bulk out short packet (including zero length packet ).
sahilmgandhi	18:6a4db94011d3	29112	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29113	*/
sahilmgandhi	18:6a4db94011d3	29114	__IO uint32_t EPEINTSTS;
sahilmgandhi	18:6a4db94011d3	29115
sahilmgandhi	18:6a4db94011d3	29116	/**
sahilmgandhi	18:6a4db94011d3	29117	* EPEINTEN
sahilmgandhi	18:6a4db94011d3	29118	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29119	* Offset: 0x10C Endpoint E Interrupt Enable Register
sahilmgandhi	18:6a4db94011d3	29120	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29121	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29122	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29123	* \|[0] \|BUFFULLIEN\|Buffer Full Interrupt
sahilmgandhi	18:6a4db94011d3	29124	* \| \| \|When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
sahilmgandhi	18:6a4db94011d3	29125	* \| \| \|0 = Buffer full interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29126	* \| \| \|1 = Buffer full interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29127	* \|[1] \|BUFEMPTYIEN\|Buffer Empty Interrupt
sahilmgandhi	18:6a4db94011d3	29128	* \| \| \|When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
sahilmgandhi	18:6a4db94011d3	29129	* \| \| \|0 = Buffer empty interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29130	* \| \| \|1 = Buffer empty interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29131	* \|[2] \|SHORTTXIEN\|Short Packet Transferred Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29132	* \| \| \|When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
sahilmgandhi	18:6a4db94011d3	29133	* \| \| \|0 = Short data packet interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29134	* \| \| \|1 = Short data packet interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29135	* \|[3] \|TXPKIEN \|Data Packet Transmitted Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29136	* \| \| \|When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
sahilmgandhi	18:6a4db94011d3	29137	* \| \| \|0 = Data packet has been received from the host interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29138	* \| \| \|1 = Data packet has been received from the host interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29139	* \|[4] \|RXPKIEN \|Data Packet Received Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29140	* \| \| \|When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
sahilmgandhi	18:6a4db94011d3	29141	* \| \| \|0 = Data packet has been transmitted to the host interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29142	* \| \| \|1 = Data packet has been transmitted to the host interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29143	* \|[5] \|OUTTKIEN \|Data OUT Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29144	* \| \| \|When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
sahilmgandhi	18:6a4db94011d3	29145	* \| \| \|0 = Data OUT token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29146	* \| \| \|1 = Data OUT token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29147	* \|[6] \|INTKIEN \|Data IN Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29148	* \| \| \|When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	29149	* \| \| \|0 = Data IN token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29150	* \| \| \|1 = Data IN token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29151	* \|[7] \|PINGIEN \|PING Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29152	* \| \| \|When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
sahilmgandhi	18:6a4db94011d3	29153	* \| \| \|0 = PING token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29154	* \| \| \|1 = PING token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29155	* \|[8] \|NAKIEN \|USB NAK Sent Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29156	* \| \| \|When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
sahilmgandhi	18:6a4db94011d3	29157	* \| \| \|0 = NAK token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29158	* \| \| \|1 = NAK token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29159	* \|[9] \|STALLIEN \|USB STALL Sent Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29160	* \| \| \|When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
sahilmgandhi	18:6a4db94011d3	29161	* \| \| \|0 = STALL token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29162	* \| \| \|1 = STALL token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29163	* \|[10] \|NYETIEN \|NYET Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29164	* \| \| \|When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	29165	* \| \| \|0 = NYET condition interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29166	* \| \| \|1 = NYET condition interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29167	* \|[11] \|ERRIEN \|ERR Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29168	* \| \| \|When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	29169	* \| \| \|0 = Error event interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29170	* \| \| \|1 = Error event interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29171	* \|[12] \|SHORTRXIEN\|Bulk Out Short Packet Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29172	* \| \| \|When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	29173	* \| \| \|0 = Bulk out interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29174	* \| \| \|1 = Bulk out interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29175	*/
sahilmgandhi	18:6a4db94011d3	29176	__IO uint32_t EPEINTEN;
sahilmgandhi	18:6a4db94011d3	29177
sahilmgandhi	18:6a4db94011d3	29178	/**
sahilmgandhi	18:6a4db94011d3	29179	* EPEDATCNT
sahilmgandhi	18:6a4db94011d3	29180	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29181	* Offset: 0x110 Endpoint E Data Available Count Register
sahilmgandhi	18:6a4db94011d3	29182	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29183	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29184	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29185	* \|[0:15] \|DATCNT \|Data Count
sahilmgandhi	18:6a4db94011d3	29186	* \| \| \|For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
sahilmgandhi	18:6a4db94011d3	29187	* \|[16:30] \|DMALOOP \|DMA Loop
sahilmgandhi	18:6a4db94011d3	29188	* \| \| \|This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
sahilmgandhi	18:6a4db94011d3	29189	*/
sahilmgandhi	18:6a4db94011d3	29190	__I uint32_t EPEDATCNT;
sahilmgandhi	18:6a4db94011d3	29191
sahilmgandhi	18:6a4db94011d3	29192	/**
sahilmgandhi	18:6a4db94011d3	29193	* EPERSPCTL
sahilmgandhi	18:6a4db94011d3	29194	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29195	* Offset: 0x114 Endpoint E Response Control Register
sahilmgandhi	18:6a4db94011d3	29196	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29197	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29198	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29199	* \|[0] \|FLUSH \|Buffer Flush
sahilmgandhi	18:6a4db94011d3	29200	* \| \| \|Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
sahilmgandhi	18:6a4db94011d3	29201	* \| \| \|This bit is self-clearing.
sahilmgandhi	18:6a4db94011d3	29202	* \| \| \|This bit should always be written after an configuration event.
sahilmgandhi	18:6a4db94011d3	29203	* \| \| \|0 = The packet buffer is not flushed.
sahilmgandhi	18:6a4db94011d3	29204	* \| \| \|1 = The packet buffer is flushed by user.
sahilmgandhi	18:6a4db94011d3	29205	* \|[1:2] \|MODE \|Mode Control
sahilmgandhi	18:6a4db94011d3	29206	* \| \| \|The two bits decide the operation mode of the in-endpoint.
sahilmgandhi	18:6a4db94011d3	29207	* \| \| \|00: Auto-Validate Mode
sahilmgandhi	18:6a4db94011d3	29208	* \| \| \|01: Manual-Validate Mode
sahilmgandhi	18:6a4db94011d3	29209	* \| \| \|10: Fly Mode
sahilmgandhi	18:6a4db94011d3	29210	* \| \| \|11: Reserved
sahilmgandhi	18:6a4db94011d3	29211	* \| \| \|These bits are not valid for an out-endpoint.
sahilmgandhi	18:6a4db94011d3	29212	* \| \| \|The auto validate mode will be activated when the reserved mode is selected.
sahilmgandhi	18:6a4db94011d3	29213	* \|[3] \|TOGGLE \|Endpoint Toggle
sahilmgandhi	18:6a4db94011d3	29214	* \| \| \|This bit is used to clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	29215	* \| \| \|Reading this bit returns the current state of the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	29216	* \| \| \|The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
sahilmgandhi	18:6a4db94011d3	29217	* \| \| \|Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
sahilmgandhi	18:6a4db94011d3	29218	* \| \| \|0 = Not clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	29219	* \| \| \|1 = Clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	29220	* \|[4] \|HALT \|Endpoint Halt
sahilmgandhi	18:6a4db94011d3	29221	* \| \| \|This bit is used to send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	29222	* \| \| \|When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
sahilmgandhi	18:6a4db94011d3	29223	* \| \| \|0 = Not send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	29224	* \| \| \|1 = Send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	29225	* \|[5] \|ZEROLEN \|Zero Length
sahilmgandhi	18:6a4db94011d3	29226	* \| \| \|This bit is used to send a zero-length packet n response to an IN-token.
sahilmgandhi	18:6a4db94011d3	29227	* \| \| \|When this bit is set, a zero packet is sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	29228	* \| \| \|0 = A zero packet is not sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	29229	* \| \| \|1 = A zero packet is sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	29230	* \|[6] \|SHORTTXEN \|Short Packet Transfer Enable
sahilmgandhi	18:6a4db94011d3	29231	* \| \| \|This bit is applicable only in case of Auto-Validate Method.
sahilmgandhi	18:6a4db94011d3	29232	* \| \| \|This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
sahilmgandhi	18:6a4db94011d3	29233	* \| \| \|0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
sahilmgandhi	18:6a4db94011d3	29234	* \| \| \|1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
sahilmgandhi	18:6a4db94011d3	29235	* \|[7] \|DISBUF \|Buffer Disable Control
sahilmgandhi	18:6a4db94011d3	29236	* \| \| \|This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	29237	* \| \| \|0 = Buffer Not Disabled when Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	29238	* \| \| \|1 = Buffer Disabled when Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	29239	*/
sahilmgandhi	18:6a4db94011d3	29240	__IO uint32_t EPERSPCTL;
sahilmgandhi	18:6a4db94011d3	29241
sahilmgandhi	18:6a4db94011d3	29242	/**
sahilmgandhi	18:6a4db94011d3	29243	* EPEMPS
sahilmgandhi	18:6a4db94011d3	29244	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29245	* Offset: 0x118 Endpoint E Maximum Packet Size Register
sahilmgandhi	18:6a4db94011d3	29246	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29247	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29248	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29249	* \|[0:10] \|EPMPS \|Endpoint Maximum Packet Size
sahilmgandhi	18:6a4db94011d3	29250	* \| \| \|This field determines the Maximum Packet Size of the Endpoint.
sahilmgandhi	18:6a4db94011d3	29251	*/
sahilmgandhi	18:6a4db94011d3	29252	__IO uint32_t EPEMPS;
sahilmgandhi	18:6a4db94011d3	29253
sahilmgandhi	18:6a4db94011d3	29254	/**
sahilmgandhi	18:6a4db94011d3	29255	* EPETXCNT
sahilmgandhi	18:6a4db94011d3	29256	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29257	* Offset: 0x11C Endpoint E Transfer Count Register
sahilmgandhi	18:6a4db94011d3	29258	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29259	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29260	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29261	* \|[0:10] \|TXCNT \|Endpoint Transfer Count
sahilmgandhi	18:6a4db94011d3	29262	* \| \| \|For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
sahilmgandhi	18:6a4db94011d3	29263	* \| \| \|For OUT endpoints, this field has no effect.
sahilmgandhi	18:6a4db94011d3	29264	*/
sahilmgandhi	18:6a4db94011d3	29265	__IO uint32_t EPETXCNT;
sahilmgandhi	18:6a4db94011d3	29266
sahilmgandhi	18:6a4db94011d3	29267	/**
sahilmgandhi	18:6a4db94011d3	29268	* EPECFG
sahilmgandhi	18:6a4db94011d3	29269	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29270	* Offset: 0x120 Endpoint E Configuration Register
sahilmgandhi	18:6a4db94011d3	29271	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29272	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29273	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29274	* \|[0] \|EPEN \|Endpoint Valid
sahilmgandhi	18:6a4db94011d3	29275	* \| \| \|When set, this bit enables this endpoint.
sahilmgandhi	18:6a4db94011d3	29276	* \| \| \|This bit has no effect on Endpoint 0, which is always enabled.
sahilmgandhi	18:6a4db94011d3	29277	* \| \| \|0 = The endpoint Disabled.
sahilmgandhi	18:6a4db94011d3	29278	* \| \| \|1 = The endpoint Enabled.
sahilmgandhi	18:6a4db94011d3	29279	* \|[1:2] \|EPTYPE \|Endpoint Type
sahilmgandhi	18:6a4db94011d3	29280	* \| \| \|This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
sahilmgandhi	18:6a4db94011d3	29281	* \| \| \|00 = Reserved.
sahilmgandhi	18:6a4db94011d3	29282	* \| \| \|01 = Bulk.
sahilmgandhi	18:6a4db94011d3	29283	* \| \| \|10 = Interrupt.
sahilmgandhi	18:6a4db94011d3	29284	* \| \| \|11 = Isochronous.
sahilmgandhi	18:6a4db94011d3	29285	* \|[3] \|EPDIR \|Endpoint Direction
sahilmgandhi	18:6a4db94011d3	29286	* \| \| \|0 = out-endpoint (Host OUT to Device).
sahilmgandhi	18:6a4db94011d3	29287	* \| \| \|1 = in-endpoint (Host IN to Device).
sahilmgandhi	18:6a4db94011d3	29288	* \| \| \|Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
sahilmgandhi	18:6a4db94011d3	29289	* \|[4:7] \|EPNUM \|Endpoint Number
sahilmgandhi	18:6a4db94011d3	29290	* \| \| \|This field selects the number of the endpoint. Valid numbers 1 to 15.
sahilmgandhi	18:6a4db94011d3	29291	*/
sahilmgandhi	18:6a4db94011d3	29292	__IO uint32_t EPECFG;
sahilmgandhi	18:6a4db94011d3	29293
sahilmgandhi	18:6a4db94011d3	29294	/**
sahilmgandhi	18:6a4db94011d3	29295	* EPEBUFSTART
sahilmgandhi	18:6a4db94011d3	29296	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29297	* Offset: 0x124 Endpoint E RAM Start Address Register
sahilmgandhi	18:6a4db94011d3	29298	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29299	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29300	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29301	* \|[0:11] \|SADDR \|Endpoint Start Address
sahilmgandhi	18:6a4db94011d3	29302	* \| \| \|This is the start-address of the RAM space allocated for the endpoint A~L.
sahilmgandhi	18:6a4db94011d3	29303	*/
sahilmgandhi	18:6a4db94011d3	29304	__IO uint32_t EPEBUFSTART;
sahilmgandhi	18:6a4db94011d3	29305
sahilmgandhi	18:6a4db94011d3	29306	/**
sahilmgandhi	18:6a4db94011d3	29307	* EPEBUFEND
sahilmgandhi	18:6a4db94011d3	29308	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29309	* Offset: 0x128 Endpoint E RAM End Address Register
sahilmgandhi	18:6a4db94011d3	29310	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29311	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29312	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29313	* \|[0:11] \|EADDR \|Endpoint End Address
sahilmgandhi	18:6a4db94011d3	29314	* \| \| \|This is the end-address of the RAM space allocated for the endpoint A~L.
sahilmgandhi	18:6a4db94011d3	29315	*/
sahilmgandhi	18:6a4db94011d3	29316	__IO uint32_t EPEBUFEND;
sahilmgandhi	18:6a4db94011d3	29317
sahilmgandhi	18:6a4db94011d3	29318	union {
sahilmgandhi	18:6a4db94011d3	29319
sahilmgandhi	18:6a4db94011d3	29320	/**
sahilmgandhi	18:6a4db94011d3	29321	* EPFDAT
sahilmgandhi	18:6a4db94011d3	29322	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29323	* Offset: 0x12C Endpoint F Data Register
sahilmgandhi	18:6a4db94011d3	29324	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29325	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29326	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29327	* \|[0:31] \|EPDAT \|Endpoint A~L Data Register
sahilmgandhi	18:6a4db94011d3	29328	* \| \| \|Endpoint A~L data buffer for the buffer transaction (read or write).
sahilmgandhi	18:6a4db94011d3	29329	* \| \| \|Note: Only word or byte access are supported.
sahilmgandhi	18:6a4db94011d3	29330	*/
sahilmgandhi	18:6a4db94011d3	29331	__IO uint32_t EPFDAT;
sahilmgandhi	18:6a4db94011d3	29332	/**
sahilmgandhi	18:6a4db94011d3	29333	* EPFDAT_BYTE
sahilmgandhi	18:6a4db94011d3	29334	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29335	* Offset: 0x12C Endpoint F Data Register for Byte Access
sahilmgandhi	18:6a4db94011d3	29336	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29337	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29338	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29339	* \|[0:7] \|EPDAT \|Endpoint A~L Data Register
sahilmgandhi	18:6a4db94011d3	29340	* \| \| \|Endpoint A~L data buffer for the buffer transaction (read or write).
sahilmgandhi	18:6a4db94011d3	29341	* \| \| \|Note: Only word or byte access are supported.
sahilmgandhi	18:6a4db94011d3	29342	*/
sahilmgandhi	18:6a4db94011d3	29343	__IO uint8_t EPFDAT_BYTE;
sahilmgandhi	18:6a4db94011d3	29344
sahilmgandhi	18:6a4db94011d3	29345	}; ///< Define EPF Data Register 32-bit or 8-bit access
sahilmgandhi	18:6a4db94011d3	29346
sahilmgandhi	18:6a4db94011d3	29347	/**
sahilmgandhi	18:6a4db94011d3	29348	* EPFINTSTS
sahilmgandhi	18:6a4db94011d3	29349	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29350	* Offset: 0x130 Endpoint F Interrupt Status Register
sahilmgandhi	18:6a4db94011d3	29351	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29352	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29353	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29354	* \|[0] \|BUFFULLIF \|Buffer Full
sahilmgandhi	18:6a4db94011d3	29355	* \| \| \|For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
sahilmgandhi	18:6a4db94011d3	29356	* \| \| \|For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
sahilmgandhi	18:6a4db94011d3	29357	* \| \| \|0 = The endpoint packet buffer is not full.
sahilmgandhi	18:6a4db94011d3	29358	* \| \| \|1 = The endpoint packet buffer is full.
sahilmgandhi	18:6a4db94011d3	29359	* \| \| \|Note: This bit is read-only.
sahilmgandhi	18:6a4db94011d3	29360	* \|[1] \|BUFEMPTYIF\|Buffer Empty
sahilmgandhi	18:6a4db94011d3	29361	* \| \| \|For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
sahilmgandhi	18:6a4db94011d3	29362	* \| \| \|0 = The endpoint buffer is not empty.
sahilmgandhi	18:6a4db94011d3	29363	* \| \| \|1 = The endpoint buffer is empty.
sahilmgandhi	18:6a4db94011d3	29364	* \| \| \|For an OUT endpoint:
sahilmgandhi	18:6a4db94011d3	29365	* \| \| \|0 = The currently selected buffer has not a count of 0.
sahilmgandhi	18:6a4db94011d3	29366	* \| \| \|1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
sahilmgandhi	18:6a4db94011d3	29367	* \| \| \|Note: This bit is read-only.
sahilmgandhi	18:6a4db94011d3	29368	* \|[2] \|SHORTTXIF \|Short Packet Transferred Interrupt
sahilmgandhi	18:6a4db94011d3	29369	* \| \| \|0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
sahilmgandhi	18:6a4db94011d3	29370	* \| \| \|1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
sahilmgandhi	18:6a4db94011d3	29371	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29372	* \|[3] \|TXPKIF \|Data Packet Transmitted Interrupt
sahilmgandhi	18:6a4db94011d3	29373	* \| \| \|0 = Not a data packet is transmitted from the endpoint to the host.
sahilmgandhi	18:6a4db94011d3	29374	* \| \| \|1 = A data packet is transmitted from the endpoint to the host.
sahilmgandhi	18:6a4db94011d3	29375	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29376	* \|[4] \|RXPKIF \|Data Packet Received Interrupt
sahilmgandhi	18:6a4db94011d3	29377	* \| \| \|0 = No data packet is received from the host by the endpoint.
sahilmgandhi	18:6a4db94011d3	29378	* \| \| \|1 = A data packet is received from the host by the endpoint.
sahilmgandhi	18:6a4db94011d3	29379	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29380	* \|[5] \|OUTTKIF \|Data OUT Token Interrupt
sahilmgandhi	18:6a4db94011d3	29381	* \| \| \|0 = A Data OUT token has not been received from the host.
sahilmgandhi	18:6a4db94011d3	29382	* \| \| \|1 = A Data OUT token has been received from the host.
sahilmgandhi	18:6a4db94011d3	29383	* \| \| \|This bit also set by PING tokens(in high-speed only).
sahilmgandhi	18:6a4db94011d3	29384	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29385	* \|[6] \|INTKIF \|Data IN Token Interrupt
sahilmgandhi	18:6a4db94011d3	29386	* \| \| \|0 = Not Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	29387	* \| \| \|1 = A Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	29388	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29389	* \|[7] \|PINGIF \|PING Token Interrupt
sahilmgandhi	18:6a4db94011d3	29390	* \| \| \|0 = A Data PING token has not been received from the host.
sahilmgandhi	18:6a4db94011d3	29391	* \| \| \|1 = A Data PING token has been received from the host.
sahilmgandhi	18:6a4db94011d3	29392	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29393	* \|[8] \|NAKIF \|USB NAK Sent
sahilmgandhi	18:6a4db94011d3	29394	* \| \| \|0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
sahilmgandhi	18:6a4db94011d3	29395	* \| \| \|1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
sahilmgandhi	18:6a4db94011d3	29396	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29397	* \|[9] \|STALLIF \|USB STALL Sent
sahilmgandhi	18:6a4db94011d3	29398	* \| \| \|0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
sahilmgandhi	18:6a4db94011d3	29399	* \| \| \|1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
sahilmgandhi	18:6a4db94011d3	29400	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29401	* \|[10] \|NYETIF \|NYET Sent
sahilmgandhi	18:6a4db94011d3	29402	* \| \| \|0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
sahilmgandhi	18:6a4db94011d3	29403	* \| \| \|1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
sahilmgandhi	18:6a4db94011d3	29404	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29405	* \|[11] \|ERRIF \|ERR Sent
sahilmgandhi	18:6a4db94011d3	29406	* \| \| \|0 = No any error in the transaction.
sahilmgandhi	18:6a4db94011d3	29407	* \| \| \|1 = There occurs any error in the transaction.
sahilmgandhi	18:6a4db94011d3	29408	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29409	* \|[12] \|SHORTRXIF \|Bulk Out Short Packet Received
sahilmgandhi	18:6a4db94011d3	29410	* \| \| \|0 = No bulk out short packet is received.
sahilmgandhi	18:6a4db94011d3	29411	* \| \| \|1 = Received bulk out short packet (including zero length packet ).
sahilmgandhi	18:6a4db94011d3	29412	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29413	*/
sahilmgandhi	18:6a4db94011d3	29414	__IO uint32_t EPFINTSTS;
sahilmgandhi	18:6a4db94011d3	29415
sahilmgandhi	18:6a4db94011d3	29416	/**
sahilmgandhi	18:6a4db94011d3	29417	* EPFINTEN
sahilmgandhi	18:6a4db94011d3	29418	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29419	* Offset: 0x134 Endpoint F Interrupt Enable Register
sahilmgandhi	18:6a4db94011d3	29420	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29421	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29422	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29423	* \|[0] \|BUFFULLIEN\|Buffer Full Interrupt
sahilmgandhi	18:6a4db94011d3	29424	* \| \| \|When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
sahilmgandhi	18:6a4db94011d3	29425	* \| \| \|0 = Buffer full interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29426	* \| \| \|1 = Buffer full interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29427	* \|[1] \|BUFEMPTYIEN\|Buffer Empty Interrupt
sahilmgandhi	18:6a4db94011d3	29428	* \| \| \|When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
sahilmgandhi	18:6a4db94011d3	29429	* \| \| \|0 = Buffer empty interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29430	* \| \| \|1 = Buffer empty interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29431	* \|[2] \|SHORTTXIEN\|Short Packet Transferred Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29432	* \| \| \|When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
sahilmgandhi	18:6a4db94011d3	29433	* \| \| \|0 = Short data packet interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29434	* \| \| \|1 = Short data packet interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29435	* \|[3] \|TXPKIEN \|Data Packet Transmitted Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29436	* \| \| \|When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
sahilmgandhi	18:6a4db94011d3	29437	* \| \| \|0 = Data packet has been received from the host interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29438	* \| \| \|1 = Data packet has been received from the host interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29439	* \|[4] \|RXPKIEN \|Data Packet Received Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29440	* \| \| \|When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
sahilmgandhi	18:6a4db94011d3	29441	* \| \| \|0 = Data packet has been transmitted to the host interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29442	* \| \| \|1 = Data packet has been transmitted to the host interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29443	* \|[5] \|OUTTKIEN \|Data OUT Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29444	* \| \| \|When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
sahilmgandhi	18:6a4db94011d3	29445	* \| \| \|0 = Data OUT token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29446	* \| \| \|1 = Data OUT token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29447	* \|[6] \|INTKIEN \|Data IN Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29448	* \| \| \|When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	29449	* \| \| \|0 = Data IN token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29450	* \| \| \|1 = Data IN token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29451	* \|[7] \|PINGIEN \|PING Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29452	* \| \| \|When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
sahilmgandhi	18:6a4db94011d3	29453	* \| \| \|0 = PING token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29454	* \| \| \|1 = PING token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29455	* \|[8] \|NAKIEN \|USB NAK Sent Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29456	* \| \| \|When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
sahilmgandhi	18:6a4db94011d3	29457	* \| \| \|0 = NAK token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29458	* \| \| \|1 = NAK token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29459	* \|[9] \|STALLIEN \|USB STALL Sent Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29460	* \| \| \|When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
sahilmgandhi	18:6a4db94011d3	29461	* \| \| \|0 = STALL token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29462	* \| \| \|1 = STALL token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29463	* \|[10] \|NYETIEN \|NYET Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29464	* \| \| \|When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	29465	* \| \| \|0 = NYET condition interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29466	* \| \| \|1 = NYET condition interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29467	* \|[11] \|ERRIEN \|ERR Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29468	* \| \| \|When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	29469	* \| \| \|0 = Error event interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29470	* \| \| \|1 = Error event interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29471	* \|[12] \|SHORTRXIEN\|Bulk Out Short Packet Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29472	* \| \| \|When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	29473	* \| \| \|0 = Bulk out interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29474	* \| \| \|1 = Bulk out interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29475	*/
sahilmgandhi	18:6a4db94011d3	29476	__IO uint32_t EPFINTEN;
sahilmgandhi	18:6a4db94011d3	29477
sahilmgandhi	18:6a4db94011d3	29478	/**
sahilmgandhi	18:6a4db94011d3	29479	* EPFDATCNT
sahilmgandhi	18:6a4db94011d3	29480	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29481	* Offset: 0x138 Endpoint F Data Available Count Register
sahilmgandhi	18:6a4db94011d3	29482	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29483	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29484	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29485	* \|[0:15] \|DATCNT \|Data Count
sahilmgandhi	18:6a4db94011d3	29486	* \| \| \|For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
sahilmgandhi	18:6a4db94011d3	29487	* \|[16:30] \|DMALOOP \|DMA Loop
sahilmgandhi	18:6a4db94011d3	29488	* \| \| \|This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
sahilmgandhi	18:6a4db94011d3	29489	*/
sahilmgandhi	18:6a4db94011d3	29490	__I uint32_t EPFDATCNT;
sahilmgandhi	18:6a4db94011d3	29491
sahilmgandhi	18:6a4db94011d3	29492	/**
sahilmgandhi	18:6a4db94011d3	29493	* EPFRSPCTL
sahilmgandhi	18:6a4db94011d3	29494	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29495	* Offset: 0x13C Endpoint F Response Control Register
sahilmgandhi	18:6a4db94011d3	29496	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29497	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29498	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29499	* \|[0] \|FLUSH \|Buffer Flush
sahilmgandhi	18:6a4db94011d3	29500	* \| \| \|Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
sahilmgandhi	18:6a4db94011d3	29501	* \| \| \|This bit is self-clearing.
sahilmgandhi	18:6a4db94011d3	29502	* \| \| \|This bit should always be written after an configuration event.
sahilmgandhi	18:6a4db94011d3	29503	* \| \| \|0 = The packet buffer is not flushed.
sahilmgandhi	18:6a4db94011d3	29504	* \| \| \|1 = The packet buffer is flushed by user.
sahilmgandhi	18:6a4db94011d3	29505	* \|[1:2] \|MODE \|Mode Control
sahilmgandhi	18:6a4db94011d3	29506	* \| \| \|The two bits decide the operation mode of the in-endpoint.
sahilmgandhi	18:6a4db94011d3	29507	* \| \| \|00: Auto-Validate Mode
sahilmgandhi	18:6a4db94011d3	29508	* \| \| \|01: Manual-Validate Mode
sahilmgandhi	18:6a4db94011d3	29509	* \| \| \|10: Fly Mode
sahilmgandhi	18:6a4db94011d3	29510	* \| \| \|11: Reserved
sahilmgandhi	18:6a4db94011d3	29511	* \| \| \|These bits are not valid for an out-endpoint.
sahilmgandhi	18:6a4db94011d3	29512	* \| \| \|The auto validate mode will be activated when the reserved mode is selected.
sahilmgandhi	18:6a4db94011d3	29513	* \|[3] \|TOGGLE \|Endpoint Toggle
sahilmgandhi	18:6a4db94011d3	29514	* \| \| \|This bit is used to clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	29515	* \| \| \|Reading this bit returns the current state of the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	29516	* \| \| \|The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
sahilmgandhi	18:6a4db94011d3	29517	* \| \| \|Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
sahilmgandhi	18:6a4db94011d3	29518	* \| \| \|0 = Not clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	29519	* \| \| \|1 = Clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	29520	* \|[4] \|HALT \|Endpoint Halt
sahilmgandhi	18:6a4db94011d3	29521	* \| \| \|This bit is used to send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	29522	* \| \| \|When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
sahilmgandhi	18:6a4db94011d3	29523	* \| \| \|0 = Not send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	29524	* \| \| \|1 = Send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	29525	* \|[5] \|ZEROLEN \|Zero Length
sahilmgandhi	18:6a4db94011d3	29526	* \| \| \|This bit is used to send a zero-length packet n response to an IN-token.
sahilmgandhi	18:6a4db94011d3	29527	* \| \| \|When this bit is set, a zero packet is sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	29528	* \| \| \|0 = A zero packet is not sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	29529	* \| \| \|1 = A zero packet is sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	29530	* \|[6] \|SHORTTXEN \|Short Packet Transfer Enable
sahilmgandhi	18:6a4db94011d3	29531	* \| \| \|This bit is applicable only in case of Auto-Validate Method.
sahilmgandhi	18:6a4db94011d3	29532	* \| \| \|This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
sahilmgandhi	18:6a4db94011d3	29533	* \| \| \|0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
sahilmgandhi	18:6a4db94011d3	29534	* \| \| \|1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
sahilmgandhi	18:6a4db94011d3	29535	* \|[7] \|DISBUF \|Buffer Disable Control
sahilmgandhi	18:6a4db94011d3	29536	* \| \| \|This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	29537	* \| \| \|0 = Buffer Not Disabled when Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	29538	* \| \| \|1 = Buffer Disabled when Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	29539	*/
sahilmgandhi	18:6a4db94011d3	29540	__IO uint32_t EPFRSPCTL;
sahilmgandhi	18:6a4db94011d3	29541
sahilmgandhi	18:6a4db94011d3	29542	/**
sahilmgandhi	18:6a4db94011d3	29543	* EPFMPS
sahilmgandhi	18:6a4db94011d3	29544	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29545	* Offset: 0x140 Endpoint F Maximum Packet Size Register
sahilmgandhi	18:6a4db94011d3	29546	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29547	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29548	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29549	* \|[0:10] \|EPMPS \|Endpoint Maximum Packet Size
sahilmgandhi	18:6a4db94011d3	29550	* \| \| \|This field determines the Maximum Packet Size of the Endpoint.
sahilmgandhi	18:6a4db94011d3	29551	*/
sahilmgandhi	18:6a4db94011d3	29552	__IO uint32_t EPFMPS;
sahilmgandhi	18:6a4db94011d3	29553
sahilmgandhi	18:6a4db94011d3	29554	/**
sahilmgandhi	18:6a4db94011d3	29555	* EPFTXCNT
sahilmgandhi	18:6a4db94011d3	29556	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29557	* Offset: 0x144 Endpoint F Transfer Count Register
sahilmgandhi	18:6a4db94011d3	29558	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29559	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29560	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29561	* \|[0:10] \|TXCNT \|Endpoint Transfer Count
sahilmgandhi	18:6a4db94011d3	29562	* \| \| \|For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
sahilmgandhi	18:6a4db94011d3	29563	* \| \| \|For OUT endpoints, this field has no effect.
sahilmgandhi	18:6a4db94011d3	29564	*/
sahilmgandhi	18:6a4db94011d3	29565	__IO uint32_t EPFTXCNT;
sahilmgandhi	18:6a4db94011d3	29566
sahilmgandhi	18:6a4db94011d3	29567	/**
sahilmgandhi	18:6a4db94011d3	29568	* EPFCFG
sahilmgandhi	18:6a4db94011d3	29569	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29570	* Offset: 0x148 Endpoint F Configuration Register
sahilmgandhi	18:6a4db94011d3	29571	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29572	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29573	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29574	* \|[0] \|EPEN \|Endpoint Valid
sahilmgandhi	18:6a4db94011d3	29575	* \| \| \|When set, this bit enables this endpoint.
sahilmgandhi	18:6a4db94011d3	29576	* \| \| \|This bit has no effect on Endpoint 0, which is always enabled.
sahilmgandhi	18:6a4db94011d3	29577	* \| \| \|0 = The endpoint Disabled.
sahilmgandhi	18:6a4db94011d3	29578	* \| \| \|1 = The endpoint Enabled.
sahilmgandhi	18:6a4db94011d3	29579	* \|[1:2] \|EPTYPE \|Endpoint Type
sahilmgandhi	18:6a4db94011d3	29580	* \| \| \|This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
sahilmgandhi	18:6a4db94011d3	29581	* \| \| \|00 = Reserved.
sahilmgandhi	18:6a4db94011d3	29582	* \| \| \|01 = Bulk.
sahilmgandhi	18:6a4db94011d3	29583	* \| \| \|10 = Interrupt.
sahilmgandhi	18:6a4db94011d3	29584	* \| \| \|11 = Isochronous.
sahilmgandhi	18:6a4db94011d3	29585	* \|[3] \|EPDIR \|Endpoint Direction
sahilmgandhi	18:6a4db94011d3	29586	* \| \| \|0 = out-endpoint (Host OUT to Device).
sahilmgandhi	18:6a4db94011d3	29587	* \| \| \|1 = in-endpoint (Host IN to Device).
sahilmgandhi	18:6a4db94011d3	29588	* \| \| \|Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
sahilmgandhi	18:6a4db94011d3	29589	* \|[4:7] \|EPNUM \|Endpoint Number
sahilmgandhi	18:6a4db94011d3	29590	* \| \| \|This field selects the number of the endpoint. Valid numbers 1 to 15.
sahilmgandhi	18:6a4db94011d3	29591	*/
sahilmgandhi	18:6a4db94011d3	29592	__IO uint32_t EPFCFG;
sahilmgandhi	18:6a4db94011d3	29593
sahilmgandhi	18:6a4db94011d3	29594	/**
sahilmgandhi	18:6a4db94011d3	29595	* EPFBUFSTART
sahilmgandhi	18:6a4db94011d3	29596	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29597	* Offset: 0x14C Endpoint F RAM Start Address Register
sahilmgandhi	18:6a4db94011d3	29598	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29599	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29600	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29601	* \|[0:11] \|SADDR \|Endpoint Start Address
sahilmgandhi	18:6a4db94011d3	29602	* \| \| \|This is the start-address of the RAM space allocated for the endpoint A~L.
sahilmgandhi	18:6a4db94011d3	29603	*/
sahilmgandhi	18:6a4db94011d3	29604	__IO uint32_t EPFBUFSTART;
sahilmgandhi	18:6a4db94011d3	29605
sahilmgandhi	18:6a4db94011d3	29606	/**
sahilmgandhi	18:6a4db94011d3	29607	* EPFBUFEND
sahilmgandhi	18:6a4db94011d3	29608	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29609	* Offset: 0x150 Endpoint F RAM End Address Register
sahilmgandhi	18:6a4db94011d3	29610	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29611	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29612	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29613	* \|[0:11] \|EADDR \|Endpoint End Address
sahilmgandhi	18:6a4db94011d3	29614	* \| \| \|This is the end-address of the RAM space allocated for the endpoint A~L.
sahilmgandhi	18:6a4db94011d3	29615	*/
sahilmgandhi	18:6a4db94011d3	29616	__IO uint32_t EPFBUFEND;
sahilmgandhi	18:6a4db94011d3	29617
sahilmgandhi	18:6a4db94011d3	29618	union {
sahilmgandhi	18:6a4db94011d3	29619
sahilmgandhi	18:6a4db94011d3	29620	/**
sahilmgandhi	18:6a4db94011d3	29621	* EPGDAT
sahilmgandhi	18:6a4db94011d3	29622	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29623	* Offset: 0x154 Endpoint G Data Register
sahilmgandhi	18:6a4db94011d3	29624	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29625	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29626	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29627	* \|[0:31] \|EPDAT \|Endpoint A~L Data Register
sahilmgandhi	18:6a4db94011d3	29628	* \| \| \|Endpoint A~L data buffer for the buffer transaction (read or write).
sahilmgandhi	18:6a4db94011d3	29629	* \| \| \|Note: Only word or byte access are supported.
sahilmgandhi	18:6a4db94011d3	29630	*/
sahilmgandhi	18:6a4db94011d3	29631	__IO uint32_t EPGDAT;
sahilmgandhi	18:6a4db94011d3	29632	/**
sahilmgandhi	18:6a4db94011d3	29633	* EPGDAT_BYTE
sahilmgandhi	18:6a4db94011d3	29634	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29635	* Offset: 0x154 Endpoint G Data Register for Byte Access
sahilmgandhi	18:6a4db94011d3	29636	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29637	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29638	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29639	* \|[0:7] \|EPDAT \|Endpoint A~L Data Register
sahilmgandhi	18:6a4db94011d3	29640	* \| \| \|Endpoint A~L data buffer for the buffer transaction (read or write).
sahilmgandhi	18:6a4db94011d3	29641	* \| \| \|Note: Only word or byte access are supported.
sahilmgandhi	18:6a4db94011d3	29642	*/
sahilmgandhi	18:6a4db94011d3	29643	__IO uint8_t EPGDAT_BYTE;
sahilmgandhi	18:6a4db94011d3	29644
sahilmgandhi	18:6a4db94011d3	29645	}; ///< Define EPG Data Register 32-bit or 8-bit access
sahilmgandhi	18:6a4db94011d3	29646
sahilmgandhi	18:6a4db94011d3	29647	/**
sahilmgandhi	18:6a4db94011d3	29648	* EPGINTSTS
sahilmgandhi	18:6a4db94011d3	29649	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29650	* Offset: 0x158 Endpoint G Interrupt Status Register
sahilmgandhi	18:6a4db94011d3	29651	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29652	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29653	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29654	* \|[0] \|BUFFULLIF \|Buffer Full
sahilmgandhi	18:6a4db94011d3	29655	* \| \| \|For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
sahilmgandhi	18:6a4db94011d3	29656	* \| \| \|For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
sahilmgandhi	18:6a4db94011d3	29657	* \| \| \|0 = The endpoint packet buffer is not full.
sahilmgandhi	18:6a4db94011d3	29658	* \| \| \|1 = The endpoint packet buffer is full.
sahilmgandhi	18:6a4db94011d3	29659	* \| \| \|Note: This bit is read-only.
sahilmgandhi	18:6a4db94011d3	29660	* \|[1] \|BUFEMPTYIF\|Buffer Empty
sahilmgandhi	18:6a4db94011d3	29661	* \| \| \|For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
sahilmgandhi	18:6a4db94011d3	29662	* \| \| \|0 = The endpoint buffer is not empty.
sahilmgandhi	18:6a4db94011d3	29663	* \| \| \|1 = The endpoint buffer is empty.
sahilmgandhi	18:6a4db94011d3	29664	* \| \| \|For an OUT endpoint:
sahilmgandhi	18:6a4db94011d3	29665	* \| \| \|0 = The currently selected buffer has not a count of 0.
sahilmgandhi	18:6a4db94011d3	29666	* \| \| \|1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
sahilmgandhi	18:6a4db94011d3	29667	* \| \| \|Note: This bit is read-only.
sahilmgandhi	18:6a4db94011d3	29668	* \|[2] \|SHORTTXIF \|Short Packet Transferred Interrupt
sahilmgandhi	18:6a4db94011d3	29669	* \| \| \|0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
sahilmgandhi	18:6a4db94011d3	29670	* \| \| \|1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
sahilmgandhi	18:6a4db94011d3	29671	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29672	* \|[3] \|TXPKIF \|Data Packet Transmitted Interrupt
sahilmgandhi	18:6a4db94011d3	29673	* \| \| \|0 = Not a data packet is transmitted from the endpoint to the host.
sahilmgandhi	18:6a4db94011d3	29674	* \| \| \|1 = A data packet is transmitted from the endpoint to the host.
sahilmgandhi	18:6a4db94011d3	29675	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29676	* \|[4] \|RXPKIF \|Data Packet Received Interrupt
sahilmgandhi	18:6a4db94011d3	29677	* \| \| \|0 = No data packet is received from the host by the endpoint.
sahilmgandhi	18:6a4db94011d3	29678	* \| \| \|1 = A data packet is received from the host by the endpoint.
sahilmgandhi	18:6a4db94011d3	29679	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29680	* \|[5] \|OUTTKIF \|Data OUT Token Interrupt
sahilmgandhi	18:6a4db94011d3	29681	* \| \| \|0 = A Data OUT token has not been received from the host.
sahilmgandhi	18:6a4db94011d3	29682	* \| \| \|1 = A Data OUT token has been received from the host.
sahilmgandhi	18:6a4db94011d3	29683	* \| \| \|This bit also set by PING tokens(in high-speed only).
sahilmgandhi	18:6a4db94011d3	29684	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29685	* \|[6] \|INTKIF \|Data IN Token Interrupt
sahilmgandhi	18:6a4db94011d3	29686	* \| \| \|0 = Not Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	29687	* \| \| \|1 = A Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	29688	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29689	* \|[7] \|PINGIF \|PING Token Interrupt
sahilmgandhi	18:6a4db94011d3	29690	* \| \| \|0 = A Data PING token has not been received from the host.
sahilmgandhi	18:6a4db94011d3	29691	* \| \| \|1 = A Data PING token has been received from the host.
sahilmgandhi	18:6a4db94011d3	29692	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29693	* \|[8] \|NAKIF \|USB NAK Sent
sahilmgandhi	18:6a4db94011d3	29694	* \| \| \|0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
sahilmgandhi	18:6a4db94011d3	29695	* \| \| \|1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
sahilmgandhi	18:6a4db94011d3	29696	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29697	* \|[9] \|STALLIF \|USB STALL Sent
sahilmgandhi	18:6a4db94011d3	29698	* \| \| \|0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
sahilmgandhi	18:6a4db94011d3	29699	* \| \| \|1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
sahilmgandhi	18:6a4db94011d3	29700	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29701	* \|[10] \|NYETIF \|NYET Sent
sahilmgandhi	18:6a4db94011d3	29702	* \| \| \|0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
sahilmgandhi	18:6a4db94011d3	29703	* \| \| \|1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
sahilmgandhi	18:6a4db94011d3	29704	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29705	* \|[11] \|ERRIF \|ERR Sent
sahilmgandhi	18:6a4db94011d3	29706	* \| \| \|0 = No any error in the transaction.
sahilmgandhi	18:6a4db94011d3	29707	* \| \| \|1 = There occurs any error in the transaction.
sahilmgandhi	18:6a4db94011d3	29708	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29709	* \|[12] \|SHORTRXIF \|Bulk Out Short Packet Received
sahilmgandhi	18:6a4db94011d3	29710	* \| \| \|0 = No bulk out short packet is received.
sahilmgandhi	18:6a4db94011d3	29711	* \| \| \|1 = Received bulk out short packet (including zero length packet ).
sahilmgandhi	18:6a4db94011d3	29712	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29713	*/
sahilmgandhi	18:6a4db94011d3	29714	__IO uint32_t EPGINTSTS;
sahilmgandhi	18:6a4db94011d3	29715
sahilmgandhi	18:6a4db94011d3	29716	/**
sahilmgandhi	18:6a4db94011d3	29717	* EPGINTEN
sahilmgandhi	18:6a4db94011d3	29718	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29719	* Offset: 0x15C Endpoint G Interrupt Enable Register
sahilmgandhi	18:6a4db94011d3	29720	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29721	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29722	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29723	* \|[0] \|BUFFULLIEN\|Buffer Full Interrupt
sahilmgandhi	18:6a4db94011d3	29724	* \| \| \|When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
sahilmgandhi	18:6a4db94011d3	29725	* \| \| \|0 = Buffer full interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29726	* \| \| \|1 = Buffer full interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29727	* \|[1] \|BUFEMPTYIEN\|Buffer Empty Interrupt
sahilmgandhi	18:6a4db94011d3	29728	* \| \| \|When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
sahilmgandhi	18:6a4db94011d3	29729	* \| \| \|0 = Buffer empty interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29730	* \| \| \|1 = Buffer empty interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29731	* \|[2] \|SHORTTXIEN\|Short Packet Transferred Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29732	* \| \| \|When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
sahilmgandhi	18:6a4db94011d3	29733	* \| \| \|0 = Short data packet interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29734	* \| \| \|1 = Short data packet interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29735	* \|[3] \|TXPKIEN \|Data Packet Transmitted Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29736	* \| \| \|When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
sahilmgandhi	18:6a4db94011d3	29737	* \| \| \|0 = Data packet has been received from the host interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29738	* \| \| \|1 = Data packet has been received from the host interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29739	* \|[4] \|RXPKIEN \|Data Packet Received Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29740	* \| \| \|When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
sahilmgandhi	18:6a4db94011d3	29741	* \| \| \|0 = Data packet has been transmitted to the host interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29742	* \| \| \|1 = Data packet has been transmitted to the host interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29743	* \|[5] \|OUTTKIEN \|Data OUT Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29744	* \| \| \|When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
sahilmgandhi	18:6a4db94011d3	29745	* \| \| \|0 = Data OUT token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29746	* \| \| \|1 = Data OUT token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29747	* \|[6] \|INTKIEN \|Data IN Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29748	* \| \| \|When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	29749	* \| \| \|0 = Data IN token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29750	* \| \| \|1 = Data IN token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29751	* \|[7] \|PINGIEN \|PING Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29752	* \| \| \|When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
sahilmgandhi	18:6a4db94011d3	29753	* \| \| \|0 = PING token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29754	* \| \| \|1 = PING token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29755	* \|[8] \|NAKIEN \|USB NAK Sent Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29756	* \| \| \|When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
sahilmgandhi	18:6a4db94011d3	29757	* \| \| \|0 = NAK token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29758	* \| \| \|1 = NAK token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29759	* \|[9] \|STALLIEN \|USB STALL Sent Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29760	* \| \| \|When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
sahilmgandhi	18:6a4db94011d3	29761	* \| \| \|0 = STALL token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29762	* \| \| \|1 = STALL token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29763	* \|[10] \|NYETIEN \|NYET Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29764	* \| \| \|When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	29765	* \| \| \|0 = NYET condition interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29766	* \| \| \|1 = NYET condition interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29767	* \|[11] \|ERRIEN \|ERR Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29768	* \| \| \|When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	29769	* \| \| \|0 = Error event interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29770	* \| \| \|1 = Error event interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29771	* \|[12] \|SHORTRXIEN\|Bulk Out Short Packet Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	29772	* \| \| \|When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	29773	* \| \| \|0 = Bulk out interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	29774	* \| \| \|1 = Bulk out interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	29775	*/
sahilmgandhi	18:6a4db94011d3	29776	__IO uint32_t EPGINTEN;
sahilmgandhi	18:6a4db94011d3	29777
sahilmgandhi	18:6a4db94011d3	29778	/**
sahilmgandhi	18:6a4db94011d3	29779	* EPGDATCNT
sahilmgandhi	18:6a4db94011d3	29780	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29781	* Offset: 0x160 Endpoint G Data Available Count Register
sahilmgandhi	18:6a4db94011d3	29782	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29783	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29784	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29785	* \|[0:15] \|DATCNT \|Data Count
sahilmgandhi	18:6a4db94011d3	29786	* \| \| \|For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
sahilmgandhi	18:6a4db94011d3	29787	* \|[16:30] \|DMALOOP \|DMA Loop
sahilmgandhi	18:6a4db94011d3	29788	* \| \| \|This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
sahilmgandhi	18:6a4db94011d3	29789	*/
sahilmgandhi	18:6a4db94011d3	29790	__I uint32_t EPGDATCNT;
sahilmgandhi	18:6a4db94011d3	29791
sahilmgandhi	18:6a4db94011d3	29792	/**
sahilmgandhi	18:6a4db94011d3	29793	* EPGRSPCTL
sahilmgandhi	18:6a4db94011d3	29794	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29795	* Offset: 0x164 Endpoint G Response Control Register
sahilmgandhi	18:6a4db94011d3	29796	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29797	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29798	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29799	* \|[0] \|FLUSH \|Buffer Flush
sahilmgandhi	18:6a4db94011d3	29800	* \| \| \|Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
sahilmgandhi	18:6a4db94011d3	29801	* \| \| \|This bit is self-clearing.
sahilmgandhi	18:6a4db94011d3	29802	* \| \| \|This bit should always be written after an configuration event.
sahilmgandhi	18:6a4db94011d3	29803	* \| \| \|0 = The packet buffer is not flushed.
sahilmgandhi	18:6a4db94011d3	29804	* \| \| \|1 = The packet buffer is flushed by user.
sahilmgandhi	18:6a4db94011d3	29805	* \|[1:2] \|MODE \|Mode Control
sahilmgandhi	18:6a4db94011d3	29806	* \| \| \|The two bits decide the operation mode of the in-endpoint.
sahilmgandhi	18:6a4db94011d3	29807	* \| \| \|00: Auto-Validate Mode
sahilmgandhi	18:6a4db94011d3	29808	* \| \| \|01: Manual-Validate Mode
sahilmgandhi	18:6a4db94011d3	29809	* \| \| \|10: Fly Mode
sahilmgandhi	18:6a4db94011d3	29810	* \| \| \|11: Reserved
sahilmgandhi	18:6a4db94011d3	29811	* \| \| \|These bits are not valid for an out-endpoint.
sahilmgandhi	18:6a4db94011d3	29812	* \| \| \|The auto validate mode will be activated when the reserved mode is selected.
sahilmgandhi	18:6a4db94011d3	29813	* \|[3] \|TOGGLE \|Endpoint Toggle
sahilmgandhi	18:6a4db94011d3	29814	* \| \| \|This bit is used to clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	29815	* \| \| \|Reading this bit returns the current state of the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	29816	* \| \| \|The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
sahilmgandhi	18:6a4db94011d3	29817	* \| \| \|Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
sahilmgandhi	18:6a4db94011d3	29818	* \| \| \|0 = Not clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	29819	* \| \| \|1 = Clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	29820	* \|[4] \|HALT \|Endpoint Halt
sahilmgandhi	18:6a4db94011d3	29821	* \| \| \|This bit is used to send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	29822	* \| \| \|When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
sahilmgandhi	18:6a4db94011d3	29823	* \| \| \|0 = Not send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	29824	* \| \| \|1 = Send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	29825	* \|[5] \|ZEROLEN \|Zero Length
sahilmgandhi	18:6a4db94011d3	29826	* \| \| \|This bit is used to send a zero-length packet n response to an IN-token.
sahilmgandhi	18:6a4db94011d3	29827	* \| \| \|When this bit is set, a zero packet is sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	29828	* \| \| \|0 = A zero packet is not sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	29829	* \| \| \|1 = A zero packet is sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	29830	* \|[6] \|SHORTTXEN \|Short Packet Transfer Enable
sahilmgandhi	18:6a4db94011d3	29831	* \| \| \|This bit is applicable only in case of Auto-Validate Method.
sahilmgandhi	18:6a4db94011d3	29832	* \| \| \|This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
sahilmgandhi	18:6a4db94011d3	29833	* \| \| \|0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
sahilmgandhi	18:6a4db94011d3	29834	* \| \| \|1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
sahilmgandhi	18:6a4db94011d3	29835	* \|[7] \|DISBUF \|Buffer Disable Control
sahilmgandhi	18:6a4db94011d3	29836	* \| \| \|This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	29837	* \| \| \|0 = Buffer Not Disabled when Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	29838	* \| \| \|1 = Buffer Disabled when Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	29839	*/
sahilmgandhi	18:6a4db94011d3	29840	__IO uint32_t EPGRSPCTL;
sahilmgandhi	18:6a4db94011d3	29841
sahilmgandhi	18:6a4db94011d3	29842	/**
sahilmgandhi	18:6a4db94011d3	29843	* EPGMPS
sahilmgandhi	18:6a4db94011d3	29844	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29845	* Offset: 0x168 Endpoint G Maximum Packet Size Register
sahilmgandhi	18:6a4db94011d3	29846	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29847	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29848	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29849	* \|[0:10] \|EPMPS \|Endpoint Maximum Packet Size
sahilmgandhi	18:6a4db94011d3	29850	* \| \| \|This field determines the Maximum Packet Size of the Endpoint.
sahilmgandhi	18:6a4db94011d3	29851	*/
sahilmgandhi	18:6a4db94011d3	29852	__IO uint32_t EPGMPS;
sahilmgandhi	18:6a4db94011d3	29853
sahilmgandhi	18:6a4db94011d3	29854	/**
sahilmgandhi	18:6a4db94011d3	29855	* EPGTXCNT
sahilmgandhi	18:6a4db94011d3	29856	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29857	* Offset: 0x16C Endpoint G Transfer Count Register
sahilmgandhi	18:6a4db94011d3	29858	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29859	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29860	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29861	* \|[0:10] \|TXCNT \|Endpoint Transfer Count
sahilmgandhi	18:6a4db94011d3	29862	* \| \| \|For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
sahilmgandhi	18:6a4db94011d3	29863	* \| \| \|For OUT endpoints, this field has no effect.
sahilmgandhi	18:6a4db94011d3	29864	*/
sahilmgandhi	18:6a4db94011d3	29865	__IO uint32_t EPGTXCNT;
sahilmgandhi	18:6a4db94011d3	29866
sahilmgandhi	18:6a4db94011d3	29867	/**
sahilmgandhi	18:6a4db94011d3	29868	* EPGCFG
sahilmgandhi	18:6a4db94011d3	29869	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29870	* Offset: 0x170 Endpoint G Configuration Register
sahilmgandhi	18:6a4db94011d3	29871	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29872	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29873	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29874	* \|[0] \|EPEN \|Endpoint Valid
sahilmgandhi	18:6a4db94011d3	29875	* \| \| \|When set, this bit enables this endpoint.
sahilmgandhi	18:6a4db94011d3	29876	* \| \| \|This bit has no effect on Endpoint 0, which is always enabled.
sahilmgandhi	18:6a4db94011d3	29877	* \| \| \|0 = The endpoint Disabled.
sahilmgandhi	18:6a4db94011d3	29878	* \| \| \|1 = The endpoint Enabled.
sahilmgandhi	18:6a4db94011d3	29879	* \|[1:2] \|EPTYPE \|Endpoint Type
sahilmgandhi	18:6a4db94011d3	29880	* \| \| \|This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
sahilmgandhi	18:6a4db94011d3	29881	* \| \| \|00 = Reserved.
sahilmgandhi	18:6a4db94011d3	29882	* \| \| \|01 = Bulk.
sahilmgandhi	18:6a4db94011d3	29883	* \| \| \|10 = Interrupt.
sahilmgandhi	18:6a4db94011d3	29884	* \| \| \|11 = Isochronous.
sahilmgandhi	18:6a4db94011d3	29885	* \|[3] \|EPDIR \|Endpoint Direction
sahilmgandhi	18:6a4db94011d3	29886	* \| \| \|0 = out-endpoint (Host OUT to Device).
sahilmgandhi	18:6a4db94011d3	29887	* \| \| \|1 = in-endpoint (Host IN to Device).
sahilmgandhi	18:6a4db94011d3	29888	* \| \| \|Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
sahilmgandhi	18:6a4db94011d3	29889	* \|[4:7] \|EPNUM \|Endpoint Number
sahilmgandhi	18:6a4db94011d3	29890	* \| \| \|This field selects the number of the endpoint. Valid numbers 1 to 15.
sahilmgandhi	18:6a4db94011d3	29891	*/
sahilmgandhi	18:6a4db94011d3	29892	__IO uint32_t EPGCFG;
sahilmgandhi	18:6a4db94011d3	29893
sahilmgandhi	18:6a4db94011d3	29894	/**
sahilmgandhi	18:6a4db94011d3	29895	* EPGBUFSTART
sahilmgandhi	18:6a4db94011d3	29896	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29897	* Offset: 0x174 Endpoint G RAM Start Address Register
sahilmgandhi	18:6a4db94011d3	29898	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29899	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29900	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29901	* \|[0:11] \|SADDR \|Endpoint Start Address
sahilmgandhi	18:6a4db94011d3	29902	* \| \| \|This is the start-address of the RAM space allocated for the endpoint A~L.
sahilmgandhi	18:6a4db94011d3	29903	*/
sahilmgandhi	18:6a4db94011d3	29904	__IO uint32_t EPGBUFSTART;
sahilmgandhi	18:6a4db94011d3	29905
sahilmgandhi	18:6a4db94011d3	29906	/**
sahilmgandhi	18:6a4db94011d3	29907	* EPGBUFEND
sahilmgandhi	18:6a4db94011d3	29908	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29909	* Offset: 0x178 Endpoint G RAM End Address Register
sahilmgandhi	18:6a4db94011d3	29910	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29911	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29912	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29913	* \|[0:11] \|EADDR \|Endpoint End Address
sahilmgandhi	18:6a4db94011d3	29914	* \| \| \|This is the end-address of the RAM space allocated for the endpoint A~L.
sahilmgandhi	18:6a4db94011d3	29915	*/
sahilmgandhi	18:6a4db94011d3	29916	__IO uint32_t EPGBUFEND;
sahilmgandhi	18:6a4db94011d3	29917
sahilmgandhi	18:6a4db94011d3	29918	union {
sahilmgandhi	18:6a4db94011d3	29919
sahilmgandhi	18:6a4db94011d3	29920	/**
sahilmgandhi	18:6a4db94011d3	29921	* EPHDAT
sahilmgandhi	18:6a4db94011d3	29922	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29923	* Offset: 0x17C Endpoint H Data Register
sahilmgandhi	18:6a4db94011d3	29924	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29925	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29926	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29927	* \|[0:31] \|EPDAT \|Endpoint A~L Data Register
sahilmgandhi	18:6a4db94011d3	29928	* \| \| \|Endpoint A~L data buffer for the buffer transaction (read or write).
sahilmgandhi	18:6a4db94011d3	29929	* \| \| \|Note: Only word or byte access are supported.
sahilmgandhi	18:6a4db94011d3	29930	*/
sahilmgandhi	18:6a4db94011d3	29931	__IO uint32_t EPHDAT;
sahilmgandhi	18:6a4db94011d3	29932	/**
sahilmgandhi	18:6a4db94011d3	29933	* EPHDAT_BYTE
sahilmgandhi	18:6a4db94011d3	29934	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29935	* Offset: 0x17C Endpoint H Data Register for Byte Access
sahilmgandhi	18:6a4db94011d3	29936	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29937	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29938	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29939	* \|[0:7] \|EPDAT \|Endpoint A~L Data Register
sahilmgandhi	18:6a4db94011d3	29940	* \| \| \|Endpoint A~L data buffer for the buffer transaction (read or write).
sahilmgandhi	18:6a4db94011d3	29941	* \| \| \|Note: Only word or byte access are supported.
sahilmgandhi	18:6a4db94011d3	29942	*/
sahilmgandhi	18:6a4db94011d3	29943	__IO uint8_t EPHDAT_BYTE;
sahilmgandhi	18:6a4db94011d3	29944
sahilmgandhi	18:6a4db94011d3	29945	}; ///< Define EPH Data Register 32-bit or 8-bit access
sahilmgandhi	18:6a4db94011d3	29946
sahilmgandhi	18:6a4db94011d3	29947	/**
sahilmgandhi	18:6a4db94011d3	29948	* EPHINTSTS
sahilmgandhi	18:6a4db94011d3	29949	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	29950	* Offset: 0x180 Endpoint H Interrupt Status Register
sahilmgandhi	18:6a4db94011d3	29951	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	29952	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	29953	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	29954	* \|[0] \|BUFFULLIF \|Buffer Full
sahilmgandhi	18:6a4db94011d3	29955	* \| \| \|For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
sahilmgandhi	18:6a4db94011d3	29956	* \| \| \|For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
sahilmgandhi	18:6a4db94011d3	29957	* \| \| \|0 = The endpoint packet buffer is not full.
sahilmgandhi	18:6a4db94011d3	29958	* \| \| \|1 = The endpoint packet buffer is full.
sahilmgandhi	18:6a4db94011d3	29959	* \| \| \|Note: This bit is read-only.
sahilmgandhi	18:6a4db94011d3	29960	* \|[1] \|BUFEMPTYIF\|Buffer Empty
sahilmgandhi	18:6a4db94011d3	29961	* \| \| \|For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
sahilmgandhi	18:6a4db94011d3	29962	* \| \| \|0 = The endpoint buffer is not empty.
sahilmgandhi	18:6a4db94011d3	29963	* \| \| \|1 = The endpoint buffer is empty.
sahilmgandhi	18:6a4db94011d3	29964	* \| \| \|For an OUT endpoint:
sahilmgandhi	18:6a4db94011d3	29965	* \| \| \|0 = The currently selected buffer has not a count of 0.
sahilmgandhi	18:6a4db94011d3	29966	* \| \| \|1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
sahilmgandhi	18:6a4db94011d3	29967	* \| \| \|Note: This bit is read-only.
sahilmgandhi	18:6a4db94011d3	29968	* \|[2] \|SHORTTXIF \|Short Packet Transferred Interrupt
sahilmgandhi	18:6a4db94011d3	29969	* \| \| \|0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
sahilmgandhi	18:6a4db94011d3	29970	* \| \| \|1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
sahilmgandhi	18:6a4db94011d3	29971	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29972	* \|[3] \|TXPKIF \|Data Packet Transmitted Interrupt
sahilmgandhi	18:6a4db94011d3	29973	* \| \| \|0 = Not a data packet is transmitted from the endpoint to the host.
sahilmgandhi	18:6a4db94011d3	29974	* \| \| \|1 = A data packet is transmitted from the endpoint to the host.
sahilmgandhi	18:6a4db94011d3	29975	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29976	* \|[4] \|RXPKIF \|Data Packet Received Interrupt
sahilmgandhi	18:6a4db94011d3	29977	* \| \| \|0 = No data packet is received from the host by the endpoint.
sahilmgandhi	18:6a4db94011d3	29978	* \| \| \|1 = A data packet is received from the host by the endpoint.
sahilmgandhi	18:6a4db94011d3	29979	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29980	* \|[5] \|OUTTKIF \|Data OUT Token Interrupt
sahilmgandhi	18:6a4db94011d3	29981	* \| \| \|0 = A Data OUT token has not been received from the host.
sahilmgandhi	18:6a4db94011d3	29982	* \| \| \|1 = A Data OUT token has been received from the host.
sahilmgandhi	18:6a4db94011d3	29983	* \| \| \|This bit also set by PING tokens(in high-speed only).
sahilmgandhi	18:6a4db94011d3	29984	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29985	* \|[6] \|INTKIF \|Data IN Token Interrupt
sahilmgandhi	18:6a4db94011d3	29986	* \| \| \|0 = Not Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	29987	* \| \| \|1 = A Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	29988	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29989	* \|[7] \|PINGIF \|PING Token Interrupt
sahilmgandhi	18:6a4db94011d3	29990	* \| \| \|0 = A Data PING token has not been received from the host.
sahilmgandhi	18:6a4db94011d3	29991	* \| \| \|1 = A Data PING token has been received from the host.
sahilmgandhi	18:6a4db94011d3	29992	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29993	* \|[8] \|NAKIF \|USB NAK Sent
sahilmgandhi	18:6a4db94011d3	29994	* \| \| \|0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
sahilmgandhi	18:6a4db94011d3	29995	* \| \| \|1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
sahilmgandhi	18:6a4db94011d3	29996	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	29997	* \|[9] \|STALLIF \|USB STALL Sent
sahilmgandhi	18:6a4db94011d3	29998	* \| \| \|0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
sahilmgandhi	18:6a4db94011d3	29999	* \| \| \|1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
sahilmgandhi	18:6a4db94011d3	30000	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30001	* \|[10] \|NYETIF \|NYET Sent
sahilmgandhi	18:6a4db94011d3	30002	* \| \| \|0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
sahilmgandhi	18:6a4db94011d3	30003	* \| \| \|1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
sahilmgandhi	18:6a4db94011d3	30004	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30005	* \|[11] \|ERRIF \|ERR Sent
sahilmgandhi	18:6a4db94011d3	30006	* \| \| \|0 = No any error in the transaction.
sahilmgandhi	18:6a4db94011d3	30007	* \| \| \|1 = There occurs any error in the transaction.
sahilmgandhi	18:6a4db94011d3	30008	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30009	* \|[12] \|SHORTRXIF \|Bulk Out Short Packet Received
sahilmgandhi	18:6a4db94011d3	30010	* \| \| \|0 = No bulk out short packet is received.
sahilmgandhi	18:6a4db94011d3	30011	* \| \| \|1 = Received bulk out short packet (including zero length packet ).
sahilmgandhi	18:6a4db94011d3	30012	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30013	*/
sahilmgandhi	18:6a4db94011d3	30014	__IO uint32_t EPHINTSTS;
sahilmgandhi	18:6a4db94011d3	30015
sahilmgandhi	18:6a4db94011d3	30016	/**
sahilmgandhi	18:6a4db94011d3	30017	* EPHINTEN
sahilmgandhi	18:6a4db94011d3	30018	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30019	* Offset: 0x184 Endpoint H Interrupt Enable Register
sahilmgandhi	18:6a4db94011d3	30020	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30021	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30022	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30023	* \|[0] \|BUFFULLIEN\|Buffer Full Interrupt
sahilmgandhi	18:6a4db94011d3	30024	* \| \| \|When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
sahilmgandhi	18:6a4db94011d3	30025	* \| \| \|0 = Buffer full interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30026	* \| \| \|1 = Buffer full interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30027	* \|[1] \|BUFEMPTYIEN\|Buffer Empty Interrupt
sahilmgandhi	18:6a4db94011d3	30028	* \| \| \|When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
sahilmgandhi	18:6a4db94011d3	30029	* \| \| \|0 = Buffer empty interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30030	* \| \| \|1 = Buffer empty interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30031	* \|[2] \|SHORTTXIEN\|Short Packet Transferred Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30032	* \| \| \|When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
sahilmgandhi	18:6a4db94011d3	30033	* \| \| \|0 = Short data packet interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30034	* \| \| \|1 = Short data packet interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30035	* \|[3] \|TXPKIEN \|Data Packet Transmitted Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30036	* \| \| \|When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
sahilmgandhi	18:6a4db94011d3	30037	* \| \| \|0 = Data packet has been received from the host interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30038	* \| \| \|1 = Data packet has been received from the host interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30039	* \|[4] \|RXPKIEN \|Data Packet Received Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30040	* \| \| \|When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
sahilmgandhi	18:6a4db94011d3	30041	* \| \| \|0 = Data packet has been transmitted to the host interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30042	* \| \| \|1 = Data packet has been transmitted to the host interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30043	* \|[5] \|OUTTKIEN \|Data OUT Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30044	* \| \| \|When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
sahilmgandhi	18:6a4db94011d3	30045	* \| \| \|0 = Data OUT token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30046	* \| \| \|1 = Data OUT token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30047	* \|[6] \|INTKIEN \|Data IN Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30048	* \| \| \|When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	30049	* \| \| \|0 = Data IN token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30050	* \| \| \|1 = Data IN token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30051	* \|[7] \|PINGIEN \|PING Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30052	* \| \| \|When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
sahilmgandhi	18:6a4db94011d3	30053	* \| \| \|0 = PING token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30054	* \| \| \|1 = PING token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30055	* \|[8] \|NAKIEN \|USB NAK Sent Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30056	* \| \| \|When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
sahilmgandhi	18:6a4db94011d3	30057	* \| \| \|0 = NAK token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30058	* \| \| \|1 = NAK token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30059	* \|[9] \|STALLIEN \|USB STALL Sent Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30060	* \| \| \|When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
sahilmgandhi	18:6a4db94011d3	30061	* \| \| \|0 = STALL token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30062	* \| \| \|1 = STALL token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30063	* \|[10] \|NYETIEN \|NYET Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30064	* \| \| \|When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	30065	* \| \| \|0 = NYET condition interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30066	* \| \| \|1 = NYET condition interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30067	* \|[11] \|ERRIEN \|ERR Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30068	* \| \| \|When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	30069	* \| \| \|0 = Error event interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30070	* \| \| \|1 = Error event interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30071	* \|[12] \|SHORTRXIEN\|Bulk Out Short Packet Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30072	* \| \| \|When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	30073	* \| \| \|0 = Bulk out interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30074	* \| \| \|1 = Bulk out interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30075	*/
sahilmgandhi	18:6a4db94011d3	30076	__IO uint32_t EPHINTEN;
sahilmgandhi	18:6a4db94011d3	30077
sahilmgandhi	18:6a4db94011d3	30078	/**
sahilmgandhi	18:6a4db94011d3	30079	* EPHDATCNT
sahilmgandhi	18:6a4db94011d3	30080	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30081	* Offset: 0x188 Endpoint H Data Available Count Register
sahilmgandhi	18:6a4db94011d3	30082	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30083	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30084	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30085	* \|[0:15] \|DATCNT \|Data Count
sahilmgandhi	18:6a4db94011d3	30086	* \| \| \|For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
sahilmgandhi	18:6a4db94011d3	30087	* \|[16:30] \|DMALOOP \|DMA Loop
sahilmgandhi	18:6a4db94011d3	30088	* \| \| \|This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
sahilmgandhi	18:6a4db94011d3	30089	*/
sahilmgandhi	18:6a4db94011d3	30090	__I uint32_t EPHDATCNT;
sahilmgandhi	18:6a4db94011d3	30091
sahilmgandhi	18:6a4db94011d3	30092	/**
sahilmgandhi	18:6a4db94011d3	30093	* EPHRSPCTL
sahilmgandhi	18:6a4db94011d3	30094	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30095	* Offset: 0x18C Endpoint H Response Control Register
sahilmgandhi	18:6a4db94011d3	30096	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30097	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30098	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30099	* \|[0] \|FLUSH \|Buffer Flush
sahilmgandhi	18:6a4db94011d3	30100	* \| \| \|Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
sahilmgandhi	18:6a4db94011d3	30101	* \| \| \|This bit is self-clearing.
sahilmgandhi	18:6a4db94011d3	30102	* \| \| \|This bit should always be written after an configuration event.
sahilmgandhi	18:6a4db94011d3	30103	* \| \| \|0 = The packet buffer is not flushed.
sahilmgandhi	18:6a4db94011d3	30104	* \| \| \|1 = The packet buffer is flushed by user.
sahilmgandhi	18:6a4db94011d3	30105	* \|[1:2] \|MODE \|Mode Control
sahilmgandhi	18:6a4db94011d3	30106	* \| \| \|The two bits decide the operation mode of the in-endpoint.
sahilmgandhi	18:6a4db94011d3	30107	* \| \| \|00: Auto-Validate Mode
sahilmgandhi	18:6a4db94011d3	30108	* \| \| \|01: Manual-Validate Mode
sahilmgandhi	18:6a4db94011d3	30109	* \| \| \|10: Fly Mode
sahilmgandhi	18:6a4db94011d3	30110	* \| \| \|11: Reserved
sahilmgandhi	18:6a4db94011d3	30111	* \| \| \|These bits are not valid for an out-endpoint.
sahilmgandhi	18:6a4db94011d3	30112	* \| \| \|The auto validate mode will be activated when the reserved mode is selected.
sahilmgandhi	18:6a4db94011d3	30113	* \|[3] \|TOGGLE \|Endpoint Toggle
sahilmgandhi	18:6a4db94011d3	30114	* \| \| \|This bit is used to clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	30115	* \| \| \|Reading this bit returns the current state of the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	30116	* \| \| \|The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
sahilmgandhi	18:6a4db94011d3	30117	* \| \| \|Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
sahilmgandhi	18:6a4db94011d3	30118	* \| \| \|0 = Not clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	30119	* \| \| \|1 = Clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	30120	* \|[4] \|HALT \|Endpoint Halt
sahilmgandhi	18:6a4db94011d3	30121	* \| \| \|This bit is used to send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	30122	* \| \| \|When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
sahilmgandhi	18:6a4db94011d3	30123	* \| \| \|0 = Not send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	30124	* \| \| \|1 = Send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	30125	* \|[5] \|ZEROLEN \|Zero Length
sahilmgandhi	18:6a4db94011d3	30126	* \| \| \|This bit is used to send a zero-length packet n response to an IN-token.
sahilmgandhi	18:6a4db94011d3	30127	* \| \| \|When this bit is set, a zero packet is sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	30128	* \| \| \|0 = A zero packet is not sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	30129	* \| \| \|1 = A zero packet is sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	30130	* \|[6] \|SHORTTXEN \|Short Packet Transfer Enable
sahilmgandhi	18:6a4db94011d3	30131	* \| \| \|This bit is applicable only in case of Auto-Validate Method.
sahilmgandhi	18:6a4db94011d3	30132	* \| \| \|This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
sahilmgandhi	18:6a4db94011d3	30133	* \| \| \|0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
sahilmgandhi	18:6a4db94011d3	30134	* \| \| \|1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
sahilmgandhi	18:6a4db94011d3	30135	* \|[7] \|DISBUF \|Buffer Disable Control
sahilmgandhi	18:6a4db94011d3	30136	* \| \| \|This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	30137	* \| \| \|0 = Buffer Not Disabled when Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	30138	* \| \| \|1 = Buffer Disabled when Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	30139	*/
sahilmgandhi	18:6a4db94011d3	30140	__IO uint32_t EPHRSPCTL;
sahilmgandhi	18:6a4db94011d3	30141
sahilmgandhi	18:6a4db94011d3	30142	/**
sahilmgandhi	18:6a4db94011d3	30143	* EPHMPS
sahilmgandhi	18:6a4db94011d3	30144	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30145	* Offset: 0x190 Endpoint H Maximum Packet Size Register
sahilmgandhi	18:6a4db94011d3	30146	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30147	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30148	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30149	* \|[0:10] \|EPMPS \|Endpoint Maximum Packet Size
sahilmgandhi	18:6a4db94011d3	30150	* \| \| \|This field determines the Maximum Packet Size of the Endpoint.
sahilmgandhi	18:6a4db94011d3	30151	*/
sahilmgandhi	18:6a4db94011d3	30152	__IO uint32_t EPHMPS;
sahilmgandhi	18:6a4db94011d3	30153
sahilmgandhi	18:6a4db94011d3	30154	/**
sahilmgandhi	18:6a4db94011d3	30155	* EPHTXCNT
sahilmgandhi	18:6a4db94011d3	30156	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30157	* Offset: 0x194 Endpoint H Transfer Count Register
sahilmgandhi	18:6a4db94011d3	30158	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30159	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30160	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30161	* \|[0:10] \|TXCNT \|Endpoint Transfer Count
sahilmgandhi	18:6a4db94011d3	30162	* \| \| \|For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
sahilmgandhi	18:6a4db94011d3	30163	* \| \| \|For OUT endpoints, this field has no effect.
sahilmgandhi	18:6a4db94011d3	30164	*/
sahilmgandhi	18:6a4db94011d3	30165	__IO uint32_t EPHTXCNT;
sahilmgandhi	18:6a4db94011d3	30166
sahilmgandhi	18:6a4db94011d3	30167	/**
sahilmgandhi	18:6a4db94011d3	30168	* EPHCFG
sahilmgandhi	18:6a4db94011d3	30169	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30170	* Offset: 0x198 Endpoint H Configuration Register
sahilmgandhi	18:6a4db94011d3	30171	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30172	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30173	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30174	* \|[0] \|EPEN \|Endpoint Valid
sahilmgandhi	18:6a4db94011d3	30175	* \| \| \|When set, this bit enables this endpoint.
sahilmgandhi	18:6a4db94011d3	30176	* \| \| \|This bit has no effect on Endpoint 0, which is always enabled.
sahilmgandhi	18:6a4db94011d3	30177	* \| \| \|0 = The endpoint Disabled.
sahilmgandhi	18:6a4db94011d3	30178	* \| \| \|1 = The endpoint Enabled.
sahilmgandhi	18:6a4db94011d3	30179	* \|[1:2] \|EPTYPE \|Endpoint Type
sahilmgandhi	18:6a4db94011d3	30180	* \| \| \|This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
sahilmgandhi	18:6a4db94011d3	30181	* \| \| \|00 = Reserved.
sahilmgandhi	18:6a4db94011d3	30182	* \| \| \|01 = Bulk.
sahilmgandhi	18:6a4db94011d3	30183	* \| \| \|10 = Interrupt.
sahilmgandhi	18:6a4db94011d3	30184	* \| \| \|11 = Isochronous.
sahilmgandhi	18:6a4db94011d3	30185	* \|[3] \|EPDIR \|Endpoint Direction
sahilmgandhi	18:6a4db94011d3	30186	* \| \| \|0 = out-endpoint (Host OUT to Device).
sahilmgandhi	18:6a4db94011d3	30187	* \| \| \|1 = in-endpoint (Host IN to Device).
sahilmgandhi	18:6a4db94011d3	30188	* \| \| \|Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
sahilmgandhi	18:6a4db94011d3	30189	* \|[4:7] \|EPNUM \|Endpoint Number
sahilmgandhi	18:6a4db94011d3	30190	* \| \| \|This field selects the number of the endpoint. Valid numbers 1 to 15.
sahilmgandhi	18:6a4db94011d3	30191	*/
sahilmgandhi	18:6a4db94011d3	30192	__IO uint32_t EPHCFG;
sahilmgandhi	18:6a4db94011d3	30193
sahilmgandhi	18:6a4db94011d3	30194	/**
sahilmgandhi	18:6a4db94011d3	30195	* EPHBUFSTART
sahilmgandhi	18:6a4db94011d3	30196	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30197	* Offset: 0x19C Endpoint H RAM Start Address Register
sahilmgandhi	18:6a4db94011d3	30198	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30199	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30200	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30201	* \|[0:11] \|SADDR \|Endpoint Start Address
sahilmgandhi	18:6a4db94011d3	30202	* \| \| \|This is the start-address of the RAM space allocated for the endpoint A~L.
sahilmgandhi	18:6a4db94011d3	30203	*/
sahilmgandhi	18:6a4db94011d3	30204	__IO uint32_t EPHBUFSTART;
sahilmgandhi	18:6a4db94011d3	30205
sahilmgandhi	18:6a4db94011d3	30206	/**
sahilmgandhi	18:6a4db94011d3	30207	* EPHBUFEND
sahilmgandhi	18:6a4db94011d3	30208	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30209	* Offset: 0x1A0 Endpoint H RAM End Address Register
sahilmgandhi	18:6a4db94011d3	30210	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30211	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30212	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30213	* \|[0:11] \|EADDR \|Endpoint End Address
sahilmgandhi	18:6a4db94011d3	30214	* \| \| \|This is the end-address of the RAM space allocated for the endpoint A~L.
sahilmgandhi	18:6a4db94011d3	30215	*/
sahilmgandhi	18:6a4db94011d3	30216	__IO uint32_t EPHBUFEND;
sahilmgandhi	18:6a4db94011d3	30217
sahilmgandhi	18:6a4db94011d3	30218	union {
sahilmgandhi	18:6a4db94011d3	30219
sahilmgandhi	18:6a4db94011d3	30220	/**
sahilmgandhi	18:6a4db94011d3	30221	* EPIDAT
sahilmgandhi	18:6a4db94011d3	30222	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30223	* Offset: 0x1A4 Endpoint I Data Register
sahilmgandhi	18:6a4db94011d3	30224	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30225	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30226	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30227	* \|[0:31] \|EPDAT \|Endpoint A~L Data Register
sahilmgandhi	18:6a4db94011d3	30228	* \| \| \|Endpoint A~L data buffer for the buffer transaction (read or write).
sahilmgandhi	18:6a4db94011d3	30229	* \| \| \|Note: Only word or byte access are supported.
sahilmgandhi	18:6a4db94011d3	30230	*/
sahilmgandhi	18:6a4db94011d3	30231	__IO uint32_t EPIDAT;
sahilmgandhi	18:6a4db94011d3	30232	/**
sahilmgandhi	18:6a4db94011d3	30233	* EPIDAT_BYTE
sahilmgandhi	18:6a4db94011d3	30234	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30235	* Offset: 0x1A4 Endpoint I Data Register for Byte Access
sahilmgandhi	18:6a4db94011d3	30236	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30237	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30238	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30239	* \|[0:7] \|EPDAT \|Endpoint A~L Data Register
sahilmgandhi	18:6a4db94011d3	30240	* \| \| \|Endpoint A~L data buffer for the buffer transaction (read or write).
sahilmgandhi	18:6a4db94011d3	30241	* \| \| \|Note: Only word or byte access are supported.
sahilmgandhi	18:6a4db94011d3	30242	*/
sahilmgandhi	18:6a4db94011d3	30243	__IO uint8_t EPIDAT_BYTE;
sahilmgandhi	18:6a4db94011d3	30244
sahilmgandhi	18:6a4db94011d3	30245	}; ///< Define EPI Data Register 32-bit or 8-bit access
sahilmgandhi	18:6a4db94011d3	30246
sahilmgandhi	18:6a4db94011d3	30247	/**
sahilmgandhi	18:6a4db94011d3	30248	* EPIINTSTS
sahilmgandhi	18:6a4db94011d3	30249	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30250	* Offset: 0x1A8 Endpoint I Interrupt Status Register
sahilmgandhi	18:6a4db94011d3	30251	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30252	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30253	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30254	* \|[0] \|BUFFULLIF \|Buffer Full
sahilmgandhi	18:6a4db94011d3	30255	* \| \| \|For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
sahilmgandhi	18:6a4db94011d3	30256	* \| \| \|For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
sahilmgandhi	18:6a4db94011d3	30257	* \| \| \|0 = The endpoint packet buffer is not full.
sahilmgandhi	18:6a4db94011d3	30258	* \| \| \|1 = The endpoint packet buffer is full.
sahilmgandhi	18:6a4db94011d3	30259	* \| \| \|Note: This bit is read-only.
sahilmgandhi	18:6a4db94011d3	30260	* \|[1] \|BUFEMPTYIF\|Buffer Empty
sahilmgandhi	18:6a4db94011d3	30261	* \| \| \|For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
sahilmgandhi	18:6a4db94011d3	30262	* \| \| \|0 = The endpoint buffer is not empty.
sahilmgandhi	18:6a4db94011d3	30263	* \| \| \|1 = The endpoint buffer is empty.
sahilmgandhi	18:6a4db94011d3	30264	* \| \| \|For an OUT endpoint:
sahilmgandhi	18:6a4db94011d3	30265	* \| \| \|0 = The currently selected buffer has not a count of 0.
sahilmgandhi	18:6a4db94011d3	30266	* \| \| \|1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
sahilmgandhi	18:6a4db94011d3	30267	* \| \| \|Note: This bit is read-only.
sahilmgandhi	18:6a4db94011d3	30268	* \|[2] \|SHORTTXIF \|Short Packet Transferred Interrupt
sahilmgandhi	18:6a4db94011d3	30269	* \| \| \|0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
sahilmgandhi	18:6a4db94011d3	30270	* \| \| \|1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
sahilmgandhi	18:6a4db94011d3	30271	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30272	* \|[3] \|TXPKIF \|Data Packet Transmitted Interrupt
sahilmgandhi	18:6a4db94011d3	30273	* \| \| \|0 = Not a data packet is transmitted from the endpoint to the host.
sahilmgandhi	18:6a4db94011d3	30274	* \| \| \|1 = A data packet is transmitted from the endpoint to the host.
sahilmgandhi	18:6a4db94011d3	30275	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30276	* \|[4] \|RXPKIF \|Data Packet Received Interrupt
sahilmgandhi	18:6a4db94011d3	30277	* \| \| \|0 = No data packet is received from the host by the endpoint.
sahilmgandhi	18:6a4db94011d3	30278	* \| \| \|1 = A data packet is received from the host by the endpoint.
sahilmgandhi	18:6a4db94011d3	30279	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30280	* \|[5] \|OUTTKIF \|Data OUT Token Interrupt
sahilmgandhi	18:6a4db94011d3	30281	* \| \| \|0 = A Data OUT token has not been received from the host.
sahilmgandhi	18:6a4db94011d3	30282	* \| \| \|1 = A Data OUT token has been received from the host.
sahilmgandhi	18:6a4db94011d3	30283	* \| \| \|This bit also set by PING tokens(in high-speed only).
sahilmgandhi	18:6a4db94011d3	30284	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30285	* \|[6] \|INTKIF \|Data IN Token Interrupt
sahilmgandhi	18:6a4db94011d3	30286	* \| \| \|0 = Not Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	30287	* \| \| \|1 = A Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	30288	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30289	* \|[7] \|PINGIF \|PING Token Interrupt
sahilmgandhi	18:6a4db94011d3	30290	* \| \| \|0 = A Data PING token has not been received from the host.
sahilmgandhi	18:6a4db94011d3	30291	* \| \| \|1 = A Data PING token has been received from the host.
sahilmgandhi	18:6a4db94011d3	30292	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30293	* \|[8] \|NAKIF \|USB NAK Sent
sahilmgandhi	18:6a4db94011d3	30294	* \| \| \|0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
sahilmgandhi	18:6a4db94011d3	30295	* \| \| \|1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
sahilmgandhi	18:6a4db94011d3	30296	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30297	* \|[9] \|STALLIF \|USB STALL Sent
sahilmgandhi	18:6a4db94011d3	30298	* \| \| \|0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
sahilmgandhi	18:6a4db94011d3	30299	* \| \| \|1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
sahilmgandhi	18:6a4db94011d3	30300	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30301	* \|[10] \|NYETIF \|NYET Sent
sahilmgandhi	18:6a4db94011d3	30302	* \| \| \|0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
sahilmgandhi	18:6a4db94011d3	30303	* \| \| \|1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
sahilmgandhi	18:6a4db94011d3	30304	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30305	* \|[11] \|ERRIF \|ERR Sent
sahilmgandhi	18:6a4db94011d3	30306	* \| \| \|0 = No any error in the transaction.
sahilmgandhi	18:6a4db94011d3	30307	* \| \| \|1 = There occurs any error in the transaction.
sahilmgandhi	18:6a4db94011d3	30308	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30309	* \|[12] \|SHORTRXIF \|Bulk Out Short Packet Received
sahilmgandhi	18:6a4db94011d3	30310	* \| \| \|0 = No bulk out short packet is received.
sahilmgandhi	18:6a4db94011d3	30311	* \| \| \|1 = Received bulk out short packet (including zero length packet ).
sahilmgandhi	18:6a4db94011d3	30312	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30313	*/
sahilmgandhi	18:6a4db94011d3	30314	__IO uint32_t EPIINTSTS;
sahilmgandhi	18:6a4db94011d3	30315
sahilmgandhi	18:6a4db94011d3	30316	/**
sahilmgandhi	18:6a4db94011d3	30317	* EPIINTEN
sahilmgandhi	18:6a4db94011d3	30318	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30319	* Offset: 0x1AC Endpoint I Interrupt Enable Register
sahilmgandhi	18:6a4db94011d3	30320	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30321	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30322	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30323	* \|[0] \|BUFFULLIEN\|Buffer Full Interrupt
sahilmgandhi	18:6a4db94011d3	30324	* \| \| \|When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
sahilmgandhi	18:6a4db94011d3	30325	* \| \| \|0 = Buffer full interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30326	* \| \| \|1 = Buffer full interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30327	* \|[1] \|BUFEMPTYIEN\|Buffer Empty Interrupt
sahilmgandhi	18:6a4db94011d3	30328	* \| \| \|When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
sahilmgandhi	18:6a4db94011d3	30329	* \| \| \|0 = Buffer empty interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30330	* \| \| \|1 = Buffer empty interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30331	* \|[2] \|SHORTTXIEN\|Short Packet Transferred Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30332	* \| \| \|When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
sahilmgandhi	18:6a4db94011d3	30333	* \| \| \|0 = Short data packet interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30334	* \| \| \|1 = Short data packet interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30335	* \|[3] \|TXPKIEN \|Data Packet Transmitted Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30336	* \| \| \|When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
sahilmgandhi	18:6a4db94011d3	30337	* \| \| \|0 = Data packet has been received from the host interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30338	* \| \| \|1 = Data packet has been received from the host interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30339	* \|[4] \|RXPKIEN \|Data Packet Received Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30340	* \| \| \|When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
sahilmgandhi	18:6a4db94011d3	30341	* \| \| \|0 = Data packet has been transmitted to the host interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30342	* \| \| \|1 = Data packet has been transmitted to the host interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30343	* \|[5] \|OUTTKIEN \|Data OUT Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30344	* \| \| \|When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
sahilmgandhi	18:6a4db94011d3	30345	* \| \| \|0 = Data OUT token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30346	* \| \| \|1 = Data OUT token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30347	* \|[6] \|INTKIEN \|Data IN Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30348	* \| \| \|When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	30349	* \| \| \|0 = Data IN token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30350	* \| \| \|1 = Data IN token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30351	* \|[7] \|PINGIEN \|PING Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30352	* \| \| \|When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
sahilmgandhi	18:6a4db94011d3	30353	* \| \| \|0 = PING token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30354	* \| \| \|1 = PING token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30355	* \|[8] \|NAKIEN \|USB NAK Sent Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30356	* \| \| \|When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
sahilmgandhi	18:6a4db94011d3	30357	* \| \| \|0 = NAK token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30358	* \| \| \|1 = NAK token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30359	* \|[9] \|STALLIEN \|USB STALL Sent Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30360	* \| \| \|When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
sahilmgandhi	18:6a4db94011d3	30361	* \| \| \|0 = STALL token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30362	* \| \| \|1 = STALL token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30363	* \|[10] \|NYETIEN \|NYET Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30364	* \| \| \|When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	30365	* \| \| \|0 = NYET condition interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30366	* \| \| \|1 = NYET condition interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30367	* \|[11] \|ERRIEN \|ERR Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30368	* \| \| \|When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	30369	* \| \| \|0 = Error event interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30370	* \| \| \|1 = Error event interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30371	* \|[12] \|SHORTRXIEN\|Bulk Out Short Packet Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30372	* \| \| \|When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	30373	* \| \| \|0 = Bulk out interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30374	* \| \| \|1 = Bulk out interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30375	*/
sahilmgandhi	18:6a4db94011d3	30376	__IO uint32_t EPIINTEN;
sahilmgandhi	18:6a4db94011d3	30377
sahilmgandhi	18:6a4db94011d3	30378	/**
sahilmgandhi	18:6a4db94011d3	30379	* EPIDATCNT
sahilmgandhi	18:6a4db94011d3	30380	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30381	* Offset: 0x1B0 Endpoint I Data Available Count Register
sahilmgandhi	18:6a4db94011d3	30382	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30383	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30384	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30385	* \|[0:15] \|DATCNT \|Data Count
sahilmgandhi	18:6a4db94011d3	30386	* \| \| \|For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
sahilmgandhi	18:6a4db94011d3	30387	* \|[16:30] \|DMALOOP \|DMA Loop
sahilmgandhi	18:6a4db94011d3	30388	* \| \| \|This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
sahilmgandhi	18:6a4db94011d3	30389	*/
sahilmgandhi	18:6a4db94011d3	30390	__I uint32_t EPIDATCNT;
sahilmgandhi	18:6a4db94011d3	30391
sahilmgandhi	18:6a4db94011d3	30392	/**
sahilmgandhi	18:6a4db94011d3	30393	* EPIRSPCTL
sahilmgandhi	18:6a4db94011d3	30394	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30395	* Offset: 0x1B4 Endpoint I Response Control Register
sahilmgandhi	18:6a4db94011d3	30396	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30397	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30398	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30399	* \|[0] \|FLUSH \|Buffer Flush
sahilmgandhi	18:6a4db94011d3	30400	* \| \| \|Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
sahilmgandhi	18:6a4db94011d3	30401	* \| \| \|This bit is self-clearing.
sahilmgandhi	18:6a4db94011d3	30402	* \| \| \|This bit should always be written after an configuration event.
sahilmgandhi	18:6a4db94011d3	30403	* \| \| \|0 = The packet buffer is not flushed.
sahilmgandhi	18:6a4db94011d3	30404	* \| \| \|1 = The packet buffer is flushed by user.
sahilmgandhi	18:6a4db94011d3	30405	* \|[1:2] \|MODE \|Mode Control
sahilmgandhi	18:6a4db94011d3	30406	* \| \| \|The two bits decide the operation mode of the in-endpoint.
sahilmgandhi	18:6a4db94011d3	30407	* \| \| \|00: Auto-Validate Mode
sahilmgandhi	18:6a4db94011d3	30408	* \| \| \|01: Manual-Validate Mode
sahilmgandhi	18:6a4db94011d3	30409	* \| \| \|10: Fly Mode
sahilmgandhi	18:6a4db94011d3	30410	* \| \| \|11: Reserved
sahilmgandhi	18:6a4db94011d3	30411	* \| \| \|These bits are not valid for an out-endpoint.
sahilmgandhi	18:6a4db94011d3	30412	* \| \| \|The auto validate mode will be activated when the reserved mode is selected.
sahilmgandhi	18:6a4db94011d3	30413	* \|[3] \|TOGGLE \|Endpoint Toggle
sahilmgandhi	18:6a4db94011d3	30414	* \| \| \|This bit is used to clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	30415	* \| \| \|Reading this bit returns the current state of the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	30416	* \| \| \|The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
sahilmgandhi	18:6a4db94011d3	30417	* \| \| \|Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
sahilmgandhi	18:6a4db94011d3	30418	* \| \| \|0 = Not clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	30419	* \| \| \|1 = Clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	30420	* \|[4] \|HALT \|Endpoint Halt
sahilmgandhi	18:6a4db94011d3	30421	* \| \| \|This bit is used to send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	30422	* \| \| \|When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
sahilmgandhi	18:6a4db94011d3	30423	* \| \| \|0 = Not send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	30424	* \| \| \|1 = Send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	30425	* \|[5] \|ZEROLEN \|Zero Length
sahilmgandhi	18:6a4db94011d3	30426	* \| \| \|This bit is used to send a zero-length packet n response to an IN-token.
sahilmgandhi	18:6a4db94011d3	30427	* \| \| \|When this bit is set, a zero packet is sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	30428	* \| \| \|0 = A zero packet is not sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	30429	* \| \| \|1 = A zero packet is sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	30430	* \|[6] \|SHORTTXEN \|Short Packet Transfer Enable
sahilmgandhi	18:6a4db94011d3	30431	* \| \| \|This bit is applicable only in case of Auto-Validate Method.
sahilmgandhi	18:6a4db94011d3	30432	* \| \| \|This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
sahilmgandhi	18:6a4db94011d3	30433	* \| \| \|0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
sahilmgandhi	18:6a4db94011d3	30434	* \| \| \|1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
sahilmgandhi	18:6a4db94011d3	30435	* \|[7] \|DISBUF \|Buffer Disable Control
sahilmgandhi	18:6a4db94011d3	30436	* \| \| \|This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	30437	* \| \| \|0 = Buffer Not Disabled when Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	30438	* \| \| \|1 = Buffer Disabled when Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	30439	*/
sahilmgandhi	18:6a4db94011d3	30440	__IO uint32_t EPIRSPCTL;
sahilmgandhi	18:6a4db94011d3	30441
sahilmgandhi	18:6a4db94011d3	30442	/**
sahilmgandhi	18:6a4db94011d3	30443	* EPIMPS
sahilmgandhi	18:6a4db94011d3	30444	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30445	* Offset: 0x1B8 Endpoint I Maximum Packet Size Register
sahilmgandhi	18:6a4db94011d3	30446	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30447	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30448	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30449	* \|[0:10] \|EPMPS \|Endpoint Maximum Packet Size
sahilmgandhi	18:6a4db94011d3	30450	* \| \| \|This field determines the Maximum Packet Size of the Endpoint.
sahilmgandhi	18:6a4db94011d3	30451	*/
sahilmgandhi	18:6a4db94011d3	30452	__IO uint32_t EPIMPS;
sahilmgandhi	18:6a4db94011d3	30453
sahilmgandhi	18:6a4db94011d3	30454	/**
sahilmgandhi	18:6a4db94011d3	30455	* EPITXCNT
sahilmgandhi	18:6a4db94011d3	30456	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30457	* Offset: 0x1BC Endpoint I Transfer Count Register
sahilmgandhi	18:6a4db94011d3	30458	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30459	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30460	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30461	* \|[0:10] \|TXCNT \|Endpoint Transfer Count
sahilmgandhi	18:6a4db94011d3	30462	* \| \| \|For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
sahilmgandhi	18:6a4db94011d3	30463	* \| \| \|For OUT endpoints, this field has no effect.
sahilmgandhi	18:6a4db94011d3	30464	*/
sahilmgandhi	18:6a4db94011d3	30465	__IO uint32_t EPITXCNT;
sahilmgandhi	18:6a4db94011d3	30466
sahilmgandhi	18:6a4db94011d3	30467	/**
sahilmgandhi	18:6a4db94011d3	30468	* EPICFG
sahilmgandhi	18:6a4db94011d3	30469	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30470	* Offset: 0x1C0 Endpoint I Configuration Register
sahilmgandhi	18:6a4db94011d3	30471	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30472	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30473	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30474	* \|[0] \|EPEN \|Endpoint Valid
sahilmgandhi	18:6a4db94011d3	30475	* \| \| \|When set, this bit enables this endpoint.
sahilmgandhi	18:6a4db94011d3	30476	* \| \| \|This bit has no effect on Endpoint 0, which is always enabled.
sahilmgandhi	18:6a4db94011d3	30477	* \| \| \|0 = The endpoint Disabled.
sahilmgandhi	18:6a4db94011d3	30478	* \| \| \|1 = The endpoint Enabled.
sahilmgandhi	18:6a4db94011d3	30479	* \|[1:2] \|EPTYPE \|Endpoint Type
sahilmgandhi	18:6a4db94011d3	30480	* \| \| \|This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
sahilmgandhi	18:6a4db94011d3	30481	* \| \| \|00 = Reserved.
sahilmgandhi	18:6a4db94011d3	30482	* \| \| \|01 = Bulk.
sahilmgandhi	18:6a4db94011d3	30483	* \| \| \|10 = Interrupt.
sahilmgandhi	18:6a4db94011d3	30484	* \| \| \|11 = Isochronous.
sahilmgandhi	18:6a4db94011d3	30485	* \|[3] \|EPDIR \|Endpoint Direction
sahilmgandhi	18:6a4db94011d3	30486	* \| \| \|0 = out-endpoint (Host OUT to Device).
sahilmgandhi	18:6a4db94011d3	30487	* \| \| \|1 = in-endpoint (Host IN to Device).
sahilmgandhi	18:6a4db94011d3	30488	* \| \| \|Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
sahilmgandhi	18:6a4db94011d3	30489	* \|[4:7] \|EPNUM \|Endpoint Number
sahilmgandhi	18:6a4db94011d3	30490	* \| \| \|This field selects the number of the endpoint. Valid numbers 1 to 15.
sahilmgandhi	18:6a4db94011d3	30491	*/
sahilmgandhi	18:6a4db94011d3	30492	__IO uint32_t EPICFG;
sahilmgandhi	18:6a4db94011d3	30493
sahilmgandhi	18:6a4db94011d3	30494	/**
sahilmgandhi	18:6a4db94011d3	30495	* EPIBUFSTART
sahilmgandhi	18:6a4db94011d3	30496	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30497	* Offset: 0x1C4 Endpoint I RAM Start Address Register
sahilmgandhi	18:6a4db94011d3	30498	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30499	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30500	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30501	* \|[0:11] \|SADDR \|Endpoint Start Address
sahilmgandhi	18:6a4db94011d3	30502	* \| \| \|This is the start-address of the RAM space allocated for the endpoint A~L.
sahilmgandhi	18:6a4db94011d3	30503	*/
sahilmgandhi	18:6a4db94011d3	30504	__IO uint32_t EPIBUFSTART;
sahilmgandhi	18:6a4db94011d3	30505
sahilmgandhi	18:6a4db94011d3	30506	/**
sahilmgandhi	18:6a4db94011d3	30507	* EPIBUFEND
sahilmgandhi	18:6a4db94011d3	30508	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30509	* Offset: 0x1C8 Endpoint I RAM End Address Register
sahilmgandhi	18:6a4db94011d3	30510	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30511	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30512	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30513	* \|[0:11] \|EADDR \|Endpoint End Address
sahilmgandhi	18:6a4db94011d3	30514	* \| \| \|This is the end-address of the RAM space allocated for the endpoint A~L.
sahilmgandhi	18:6a4db94011d3	30515	*/
sahilmgandhi	18:6a4db94011d3	30516	__IO uint32_t EPIBUFEND;
sahilmgandhi	18:6a4db94011d3	30517
sahilmgandhi	18:6a4db94011d3	30518	union {
sahilmgandhi	18:6a4db94011d3	30519
sahilmgandhi	18:6a4db94011d3	30520	/**
sahilmgandhi	18:6a4db94011d3	30521	* EPJDAT
sahilmgandhi	18:6a4db94011d3	30522	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30523	* Offset: 0x1CC Endpoint J Data Register
sahilmgandhi	18:6a4db94011d3	30524	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30525	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30526	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30527	* \|[0:31] \|EPDAT \|Endpoint A~L Data Register
sahilmgandhi	18:6a4db94011d3	30528	* \| \| \|Endpoint A~L data buffer for the buffer transaction (read or write).
sahilmgandhi	18:6a4db94011d3	30529	* \| \| \|Note: Only word or byte access are supported.
sahilmgandhi	18:6a4db94011d3	30530	*/
sahilmgandhi	18:6a4db94011d3	30531	__IO uint32_t EPJDAT;
sahilmgandhi	18:6a4db94011d3	30532	/**
sahilmgandhi	18:6a4db94011d3	30533	* EPJDAT_BYTE
sahilmgandhi	18:6a4db94011d3	30534	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30535	* Offset: 0x1CC Endpoint J Data Register for Byte Access
sahilmgandhi	18:6a4db94011d3	30536	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30537	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30538	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30539	* \|[0:7] \|EPDAT \|Endpoint A~L Data Register
sahilmgandhi	18:6a4db94011d3	30540	* \| \| \|Endpoint A~L data buffer for the buffer transaction (read or write).
sahilmgandhi	18:6a4db94011d3	30541	* \| \| \|Note: Only word or byte access are supported.
sahilmgandhi	18:6a4db94011d3	30542	*/
sahilmgandhi	18:6a4db94011d3	30543	__IO uint8_t EPJDAT_BYTE;
sahilmgandhi	18:6a4db94011d3	30544
sahilmgandhi	18:6a4db94011d3	30545	}; ///< Define EPJ Data Register 32-bit or 8-bit access
sahilmgandhi	18:6a4db94011d3	30546
sahilmgandhi	18:6a4db94011d3	30547	/**
sahilmgandhi	18:6a4db94011d3	30548	* EPJINTSTS
sahilmgandhi	18:6a4db94011d3	30549	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30550	* Offset: 0x1D0 Endpoint J Interrupt Status Register
sahilmgandhi	18:6a4db94011d3	30551	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30552	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30553	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30554	* \|[0] \|BUFFULLIF \|Buffer Full
sahilmgandhi	18:6a4db94011d3	30555	* \| \| \|For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
sahilmgandhi	18:6a4db94011d3	30556	* \| \| \|For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
sahilmgandhi	18:6a4db94011d3	30557	* \| \| \|0 = The endpoint packet buffer is not full.
sahilmgandhi	18:6a4db94011d3	30558	* \| \| \|1 = The endpoint packet buffer is full.
sahilmgandhi	18:6a4db94011d3	30559	* \| \| \|Note: This bit is read-only.
sahilmgandhi	18:6a4db94011d3	30560	* \|[1] \|BUFEMPTYIF\|Buffer Empty
sahilmgandhi	18:6a4db94011d3	30561	* \| \| \|For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
sahilmgandhi	18:6a4db94011d3	30562	* \| \| \|0 = The endpoint buffer is not empty.
sahilmgandhi	18:6a4db94011d3	30563	* \| \| \|1 = The endpoint buffer is empty.
sahilmgandhi	18:6a4db94011d3	30564	* \| \| \|For an OUT endpoint:
sahilmgandhi	18:6a4db94011d3	30565	* \| \| \|0 = The currently selected buffer has not a count of 0.
sahilmgandhi	18:6a4db94011d3	30566	* \| \| \|1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
sahilmgandhi	18:6a4db94011d3	30567	* \| \| \|Note: This bit is read-only.
sahilmgandhi	18:6a4db94011d3	30568	* \|[2] \|SHORTTXIF \|Short Packet Transferred Interrupt
sahilmgandhi	18:6a4db94011d3	30569	* \| \| \|0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
sahilmgandhi	18:6a4db94011d3	30570	* \| \| \|1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
sahilmgandhi	18:6a4db94011d3	30571	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30572	* \|[3] \|TXPKIF \|Data Packet Transmitted Interrupt
sahilmgandhi	18:6a4db94011d3	30573	* \| \| \|0 = Not a data packet is transmitted from the endpoint to the host.
sahilmgandhi	18:6a4db94011d3	30574	* \| \| \|1 = A data packet is transmitted from the endpoint to the host.
sahilmgandhi	18:6a4db94011d3	30575	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30576	* \|[4] \|RXPKIF \|Data Packet Received Interrupt
sahilmgandhi	18:6a4db94011d3	30577	* \| \| \|0 = No data packet is received from the host by the endpoint.
sahilmgandhi	18:6a4db94011d3	30578	* \| \| \|1 = A data packet is received from the host by the endpoint.
sahilmgandhi	18:6a4db94011d3	30579	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30580	* \|[5] \|OUTTKIF \|Data OUT Token Interrupt
sahilmgandhi	18:6a4db94011d3	30581	* \| \| \|0 = A Data OUT token has not been received from the host.
sahilmgandhi	18:6a4db94011d3	30582	* \| \| \|1 = A Data OUT token has been received from the host.
sahilmgandhi	18:6a4db94011d3	30583	* \| \| \|This bit also set by PING tokens(in high-speed only).
sahilmgandhi	18:6a4db94011d3	30584	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30585	* \|[6] \|INTKIF \|Data IN Token Interrupt
sahilmgandhi	18:6a4db94011d3	30586	* \| \| \|0 = Not Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	30587	* \| \| \|1 = A Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	30588	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30589	* \|[7] \|PINGIF \|PING Token Interrupt
sahilmgandhi	18:6a4db94011d3	30590	* \| \| \|0 = A Data PING token has not been received from the host.
sahilmgandhi	18:6a4db94011d3	30591	* \| \| \|1 = A Data PING token has been received from the host.
sahilmgandhi	18:6a4db94011d3	30592	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30593	* \|[8] \|NAKIF \|USB NAK Sent
sahilmgandhi	18:6a4db94011d3	30594	* \| \| \|0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
sahilmgandhi	18:6a4db94011d3	30595	* \| \| \|1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
sahilmgandhi	18:6a4db94011d3	30596	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30597	* \|[9] \|STALLIF \|USB STALL Sent
sahilmgandhi	18:6a4db94011d3	30598	* \| \| \|0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
sahilmgandhi	18:6a4db94011d3	30599	* \| \| \|1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
sahilmgandhi	18:6a4db94011d3	30600	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30601	* \|[10] \|NYETIF \|NYET Sent
sahilmgandhi	18:6a4db94011d3	30602	* \| \| \|0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
sahilmgandhi	18:6a4db94011d3	30603	* \| \| \|1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
sahilmgandhi	18:6a4db94011d3	30604	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30605	* \|[11] \|ERRIF \|ERR Sent
sahilmgandhi	18:6a4db94011d3	30606	* \| \| \|0 = No any error in the transaction.
sahilmgandhi	18:6a4db94011d3	30607	* \| \| \|1 = There occurs any error in the transaction.
sahilmgandhi	18:6a4db94011d3	30608	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30609	* \|[12] \|SHORTRXIF \|Bulk Out Short Packet Received
sahilmgandhi	18:6a4db94011d3	30610	* \| \| \|0 = No bulk out short packet is received.
sahilmgandhi	18:6a4db94011d3	30611	* \| \| \|1 = Received bulk out short packet (including zero length packet ).
sahilmgandhi	18:6a4db94011d3	30612	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30613	*/
sahilmgandhi	18:6a4db94011d3	30614	__IO uint32_t EPJINTSTS;
sahilmgandhi	18:6a4db94011d3	30615
sahilmgandhi	18:6a4db94011d3	30616	/**
sahilmgandhi	18:6a4db94011d3	30617	* EPJINTEN
sahilmgandhi	18:6a4db94011d3	30618	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30619	* Offset: 0x1D4 Endpoint J Interrupt Enable Register
sahilmgandhi	18:6a4db94011d3	30620	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30621	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30622	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30623	* \|[0] \|BUFFULLIEN\|Buffer Full Interrupt
sahilmgandhi	18:6a4db94011d3	30624	* \| \| \|When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
sahilmgandhi	18:6a4db94011d3	30625	* \| \| \|0 = Buffer full interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30626	* \| \| \|1 = Buffer full interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30627	* \|[1] \|BUFEMPTYIEN\|Buffer Empty Interrupt
sahilmgandhi	18:6a4db94011d3	30628	* \| \| \|When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
sahilmgandhi	18:6a4db94011d3	30629	* \| \| \|0 = Buffer empty interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30630	* \| \| \|1 = Buffer empty interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30631	* \|[2] \|SHORTTXIEN\|Short Packet Transferred Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30632	* \| \| \|When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
sahilmgandhi	18:6a4db94011d3	30633	* \| \| \|0 = Short data packet interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30634	* \| \| \|1 = Short data packet interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30635	* \|[3] \|TXPKIEN \|Data Packet Transmitted Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30636	* \| \| \|When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
sahilmgandhi	18:6a4db94011d3	30637	* \| \| \|0 = Data packet has been received from the host interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30638	* \| \| \|1 = Data packet has been received from the host interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30639	* \|[4] \|RXPKIEN \|Data Packet Received Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30640	* \| \| \|When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
sahilmgandhi	18:6a4db94011d3	30641	* \| \| \|0 = Data packet has been transmitted to the host interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30642	* \| \| \|1 = Data packet has been transmitted to the host interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30643	* \|[5] \|OUTTKIEN \|Data OUT Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30644	* \| \| \|When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
sahilmgandhi	18:6a4db94011d3	30645	* \| \| \|0 = Data OUT token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30646	* \| \| \|1 = Data OUT token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30647	* \|[6] \|INTKIEN \|Data IN Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30648	* \| \| \|When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	30649	* \| \| \|0 = Data IN token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30650	* \| \| \|1 = Data IN token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30651	* \|[7] \|PINGIEN \|PING Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30652	* \| \| \|When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
sahilmgandhi	18:6a4db94011d3	30653	* \| \| \|0 = PING token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30654	* \| \| \|1 = PING token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30655	* \|[8] \|NAKIEN \|USB NAK Sent Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30656	* \| \| \|When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
sahilmgandhi	18:6a4db94011d3	30657	* \| \| \|0 = NAK token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30658	* \| \| \|1 = NAK token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30659	* \|[9] \|STALLIEN \|USB STALL Sent Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30660	* \| \| \|When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
sahilmgandhi	18:6a4db94011d3	30661	* \| \| \|0 = STALL token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30662	* \| \| \|1 = STALL token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30663	* \|[10] \|NYETIEN \|NYET Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30664	* \| \| \|When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	30665	* \| \| \|0 = NYET condition interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30666	* \| \| \|1 = NYET condition interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30667	* \|[11] \|ERRIEN \|ERR Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30668	* \| \| \|When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	30669	* \| \| \|0 = Error event interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30670	* \| \| \|1 = Error event interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30671	* \|[12] \|SHORTRXIEN\|Bulk Out Short Packet Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30672	* \| \| \|When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	30673	* \| \| \|0 = Bulk out interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30674	* \| \| \|1 = Bulk out interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30675	*/
sahilmgandhi	18:6a4db94011d3	30676	__IO uint32_t EPJINTEN;
sahilmgandhi	18:6a4db94011d3	30677
sahilmgandhi	18:6a4db94011d3	30678	/**
sahilmgandhi	18:6a4db94011d3	30679	* EPJDATCNT
sahilmgandhi	18:6a4db94011d3	30680	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30681	* Offset: 0x1D8 Endpoint J Data Available Count Register
sahilmgandhi	18:6a4db94011d3	30682	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30683	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30684	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30685	* \|[0:15] \|DATCNT \|Data Count
sahilmgandhi	18:6a4db94011d3	30686	* \| \| \|For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
sahilmgandhi	18:6a4db94011d3	30687	* \|[16:30] \|DMALOOP \|DMA Loop
sahilmgandhi	18:6a4db94011d3	30688	* \| \| \|This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
sahilmgandhi	18:6a4db94011d3	30689	*/
sahilmgandhi	18:6a4db94011d3	30690	__I uint32_t EPJDATCNT;
sahilmgandhi	18:6a4db94011d3	30691
sahilmgandhi	18:6a4db94011d3	30692	/**
sahilmgandhi	18:6a4db94011d3	30693	* EPJRSPCTL
sahilmgandhi	18:6a4db94011d3	30694	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30695	* Offset: 0x1DC Endpoint J Response Control Register
sahilmgandhi	18:6a4db94011d3	30696	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30697	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30698	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30699	* \|[0] \|FLUSH \|Buffer Flush
sahilmgandhi	18:6a4db94011d3	30700	* \| \| \|Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
sahilmgandhi	18:6a4db94011d3	30701	* \| \| \|This bit is self-clearing.
sahilmgandhi	18:6a4db94011d3	30702	* \| \| \|This bit should always be written after an configuration event.
sahilmgandhi	18:6a4db94011d3	30703	* \| \| \|0 = The packet buffer is not flushed.
sahilmgandhi	18:6a4db94011d3	30704	* \| \| \|1 = The packet buffer is flushed by user.
sahilmgandhi	18:6a4db94011d3	30705	* \|[1:2] \|MODE \|Mode Control
sahilmgandhi	18:6a4db94011d3	30706	* \| \| \|The two bits decide the operation mode of the in-endpoint.
sahilmgandhi	18:6a4db94011d3	30707	* \| \| \|00: Auto-Validate Mode
sahilmgandhi	18:6a4db94011d3	30708	* \| \| \|01: Manual-Validate Mode
sahilmgandhi	18:6a4db94011d3	30709	* \| \| \|10: Fly Mode
sahilmgandhi	18:6a4db94011d3	30710	* \| \| \|11: Reserved
sahilmgandhi	18:6a4db94011d3	30711	* \| \| \|These bits are not valid for an out-endpoint.
sahilmgandhi	18:6a4db94011d3	30712	* \| \| \|The auto validate mode will be activated when the reserved mode is selected.
sahilmgandhi	18:6a4db94011d3	30713	* \|[3] \|TOGGLE \|Endpoint Toggle
sahilmgandhi	18:6a4db94011d3	30714	* \| \| \|This bit is used to clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	30715	* \| \| \|Reading this bit returns the current state of the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	30716	* \| \| \|The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
sahilmgandhi	18:6a4db94011d3	30717	* \| \| \|Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
sahilmgandhi	18:6a4db94011d3	30718	* \| \| \|0 = Not clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	30719	* \| \| \|1 = Clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	30720	* \|[4] \|HALT \|Endpoint Halt
sahilmgandhi	18:6a4db94011d3	30721	* \| \| \|This bit is used to send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	30722	* \| \| \|When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
sahilmgandhi	18:6a4db94011d3	30723	* \| \| \|0 = Not send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	30724	* \| \| \|1 = Send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	30725	* \|[5] \|ZEROLEN \|Zero Length
sahilmgandhi	18:6a4db94011d3	30726	* \| \| \|This bit is used to send a zero-length packet n response to an IN-token.
sahilmgandhi	18:6a4db94011d3	30727	* \| \| \|When this bit is set, a zero packet is sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	30728	* \| \| \|0 = A zero packet is not sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	30729	* \| \| \|1 = A zero packet is sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	30730	* \|[6] \|SHORTTXEN \|Short Packet Transfer Enable
sahilmgandhi	18:6a4db94011d3	30731	* \| \| \|This bit is applicable only in case of Auto-Validate Method.
sahilmgandhi	18:6a4db94011d3	30732	* \| \| \|This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
sahilmgandhi	18:6a4db94011d3	30733	* \| \| \|0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
sahilmgandhi	18:6a4db94011d3	30734	* \| \| \|1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
sahilmgandhi	18:6a4db94011d3	30735	* \|[7] \|DISBUF \|Buffer Disable Control
sahilmgandhi	18:6a4db94011d3	30736	* \| \| \|This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	30737	* \| \| \|0 = Buffer Not Disabled when Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	30738	* \| \| \|1 = Buffer Disabled when Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	30739	*/
sahilmgandhi	18:6a4db94011d3	30740	__IO uint32_t EPJRSPCTL;
sahilmgandhi	18:6a4db94011d3	30741
sahilmgandhi	18:6a4db94011d3	30742	/**
sahilmgandhi	18:6a4db94011d3	30743	* EPJMPS
sahilmgandhi	18:6a4db94011d3	30744	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30745	* Offset: 0x1E0 Endpoint J Maximum Packet Size Register
sahilmgandhi	18:6a4db94011d3	30746	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30747	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30748	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30749	* \|[0:10] \|EPMPS \|Endpoint Maximum Packet Size
sahilmgandhi	18:6a4db94011d3	30750	* \| \| \|This field determines the Maximum Packet Size of the Endpoint.
sahilmgandhi	18:6a4db94011d3	30751	*/
sahilmgandhi	18:6a4db94011d3	30752	__IO uint32_t EPJMPS;
sahilmgandhi	18:6a4db94011d3	30753
sahilmgandhi	18:6a4db94011d3	30754	/**
sahilmgandhi	18:6a4db94011d3	30755	* EPJTXCNT
sahilmgandhi	18:6a4db94011d3	30756	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30757	* Offset: 0x1E4 Endpoint J Transfer Count Register
sahilmgandhi	18:6a4db94011d3	30758	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30759	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30760	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30761	* \|[0:10] \|TXCNT \|Endpoint Transfer Count
sahilmgandhi	18:6a4db94011d3	30762	* \| \| \|For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
sahilmgandhi	18:6a4db94011d3	30763	* \| \| \|For OUT endpoints, this field has no effect.
sahilmgandhi	18:6a4db94011d3	30764	*/
sahilmgandhi	18:6a4db94011d3	30765	__IO uint32_t EPJTXCNT;
sahilmgandhi	18:6a4db94011d3	30766
sahilmgandhi	18:6a4db94011d3	30767	/**
sahilmgandhi	18:6a4db94011d3	30768	* EPJCFG
sahilmgandhi	18:6a4db94011d3	30769	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30770	* Offset: 0x1E8 Endpoint J Configuration Register
sahilmgandhi	18:6a4db94011d3	30771	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30772	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30773	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30774	* \|[0] \|EPEN \|Endpoint Valid
sahilmgandhi	18:6a4db94011d3	30775	* \| \| \|When set, this bit enables this endpoint.
sahilmgandhi	18:6a4db94011d3	30776	* \| \| \|This bit has no effect on Endpoint 0, which is always enabled.
sahilmgandhi	18:6a4db94011d3	30777	* \| \| \|0 = The endpoint Disabled.
sahilmgandhi	18:6a4db94011d3	30778	* \| \| \|1 = The endpoint Enabled.
sahilmgandhi	18:6a4db94011d3	30779	* \|[1:2] \|EPTYPE \|Endpoint Type
sahilmgandhi	18:6a4db94011d3	30780	* \| \| \|This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
sahilmgandhi	18:6a4db94011d3	30781	* \| \| \|00 = Reserved.
sahilmgandhi	18:6a4db94011d3	30782	* \| \| \|01 = Bulk.
sahilmgandhi	18:6a4db94011d3	30783	* \| \| \|10 = Interrupt.
sahilmgandhi	18:6a4db94011d3	30784	* \| \| \|11 = Isochronous.
sahilmgandhi	18:6a4db94011d3	30785	* \|[3] \|EPDIR \|Endpoint Direction
sahilmgandhi	18:6a4db94011d3	30786	* \| \| \|0 = out-endpoint (Host OUT to Device).
sahilmgandhi	18:6a4db94011d3	30787	* \| \| \|1 = in-endpoint (Host IN to Device).
sahilmgandhi	18:6a4db94011d3	30788	* \| \| \|Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
sahilmgandhi	18:6a4db94011d3	30789	* \|[4:7] \|EPNUM \|Endpoint Number
sahilmgandhi	18:6a4db94011d3	30790	* \| \| \|This field selects the number of the endpoint. Valid numbers 1 to 15.
sahilmgandhi	18:6a4db94011d3	30791	*/
sahilmgandhi	18:6a4db94011d3	30792	__IO uint32_t EPJCFG;
sahilmgandhi	18:6a4db94011d3	30793
sahilmgandhi	18:6a4db94011d3	30794	/**
sahilmgandhi	18:6a4db94011d3	30795	* EPJBUFSTART
sahilmgandhi	18:6a4db94011d3	30796	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30797	* Offset: 0x1EC Endpoint J RAM Start Address Register
sahilmgandhi	18:6a4db94011d3	30798	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30799	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30800	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30801	* \|[0:11] \|SADDR \|Endpoint Start Address
sahilmgandhi	18:6a4db94011d3	30802	* \| \| \|This is the start-address of the RAM space allocated for the endpoint A~L.
sahilmgandhi	18:6a4db94011d3	30803	*/
sahilmgandhi	18:6a4db94011d3	30804	__IO uint32_t EPJBUFSTART;
sahilmgandhi	18:6a4db94011d3	30805
sahilmgandhi	18:6a4db94011d3	30806	/**
sahilmgandhi	18:6a4db94011d3	30807	* EPJBUFEND
sahilmgandhi	18:6a4db94011d3	30808	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30809	* Offset: 0x1F0 Endpoint J RAM End Address Register
sahilmgandhi	18:6a4db94011d3	30810	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30811	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30812	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30813	* \|[0:11] \|EADDR \|Endpoint End Address
sahilmgandhi	18:6a4db94011d3	30814	* \| \| \|This is the end-address of the RAM space allocated for the endpoint A~L.
sahilmgandhi	18:6a4db94011d3	30815	*/
sahilmgandhi	18:6a4db94011d3	30816	__IO uint32_t EPJBUFEND;
sahilmgandhi	18:6a4db94011d3	30817
sahilmgandhi	18:6a4db94011d3	30818	union {
sahilmgandhi	18:6a4db94011d3	30819
sahilmgandhi	18:6a4db94011d3	30820	/**
sahilmgandhi	18:6a4db94011d3	30821	* EPKDAT
sahilmgandhi	18:6a4db94011d3	30822	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30823	* Offset: 0x1F4 Endpoint K Data Register
sahilmgandhi	18:6a4db94011d3	30824	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30825	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30826	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30827	* \|[0:31] \|EPDAT \|Endpoint A~L Data Register
sahilmgandhi	18:6a4db94011d3	30828	* \| \| \|Endpoint A~L data buffer for the buffer transaction (read or write).
sahilmgandhi	18:6a4db94011d3	30829	* \| \| \|Note: Only word or byte access are supported.
sahilmgandhi	18:6a4db94011d3	30830	*/
sahilmgandhi	18:6a4db94011d3	30831	__IO uint32_t EPKDAT;
sahilmgandhi	18:6a4db94011d3	30832	/**
sahilmgandhi	18:6a4db94011d3	30833	* EPKDAT_BYTE
sahilmgandhi	18:6a4db94011d3	30834	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30835	* Offset: 0x1F4 Endpoint K Data Register for Byte Access
sahilmgandhi	18:6a4db94011d3	30836	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30837	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30838	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30839	* \|[0:7] \|EPDAT \|Endpoint A~L Data Register
sahilmgandhi	18:6a4db94011d3	30840	* \| \| \|Endpoint A~L data buffer for the buffer transaction (read or write).
sahilmgandhi	18:6a4db94011d3	30841	* \| \| \|Note: Only word or byte access are supported.
sahilmgandhi	18:6a4db94011d3	30842	*/
sahilmgandhi	18:6a4db94011d3	30843	__IO uint8_t EPKDAT_BYTE;
sahilmgandhi	18:6a4db94011d3	30844
sahilmgandhi	18:6a4db94011d3	30845	}; ///< Define EPK Data Register 32-bit or 8-bit access
sahilmgandhi	18:6a4db94011d3	30846
sahilmgandhi	18:6a4db94011d3	30847	/**
sahilmgandhi	18:6a4db94011d3	30848	* EPKINTSTS
sahilmgandhi	18:6a4db94011d3	30849	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30850	* Offset: 0x1F8 Endpoint K Interrupt Status Register
sahilmgandhi	18:6a4db94011d3	30851	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30852	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30853	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30854	* \|[0] \|BUFFULLIF \|Buffer Full
sahilmgandhi	18:6a4db94011d3	30855	* \| \| \|For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
sahilmgandhi	18:6a4db94011d3	30856	* \| \| \|For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
sahilmgandhi	18:6a4db94011d3	30857	* \| \| \|0 = The endpoint packet buffer is not full.
sahilmgandhi	18:6a4db94011d3	30858	* \| \| \|1 = The endpoint packet buffer is full.
sahilmgandhi	18:6a4db94011d3	30859	* \| \| \|Note: This bit is read-only.
sahilmgandhi	18:6a4db94011d3	30860	* \|[1] \|BUFEMPTYIF\|Buffer Empty
sahilmgandhi	18:6a4db94011d3	30861	* \| \| \|For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
sahilmgandhi	18:6a4db94011d3	30862	* \| \| \|0 = The endpoint buffer is not empty.
sahilmgandhi	18:6a4db94011d3	30863	* \| \| \|1 = The endpoint buffer is empty.
sahilmgandhi	18:6a4db94011d3	30864	* \| \| \|For an OUT endpoint:
sahilmgandhi	18:6a4db94011d3	30865	* \| \| \|0 = The currently selected buffer has not a count of 0.
sahilmgandhi	18:6a4db94011d3	30866	* \| \| \|1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
sahilmgandhi	18:6a4db94011d3	30867	* \| \| \|Note: This bit is read-only.
sahilmgandhi	18:6a4db94011d3	30868	* \|[2] \|SHORTTXIF \|Short Packet Transferred Interrupt
sahilmgandhi	18:6a4db94011d3	30869	* \| \| \|0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
sahilmgandhi	18:6a4db94011d3	30870	* \| \| \|1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
sahilmgandhi	18:6a4db94011d3	30871	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30872	* \|[3] \|TXPKIF \|Data Packet Transmitted Interrupt
sahilmgandhi	18:6a4db94011d3	30873	* \| \| \|0 = Not a data packet is transmitted from the endpoint to the host.
sahilmgandhi	18:6a4db94011d3	30874	* \| \| \|1 = A data packet is transmitted from the endpoint to the host.
sahilmgandhi	18:6a4db94011d3	30875	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30876	* \|[4] \|RXPKIF \|Data Packet Received Interrupt
sahilmgandhi	18:6a4db94011d3	30877	* \| \| \|0 = No data packet is received from the host by the endpoint.
sahilmgandhi	18:6a4db94011d3	30878	* \| \| \|1 = A data packet is received from the host by the endpoint.
sahilmgandhi	18:6a4db94011d3	30879	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30880	* \|[5] \|OUTTKIF \|Data OUT Token Interrupt
sahilmgandhi	18:6a4db94011d3	30881	* \| \| \|0 = A Data OUT token has not been received from the host.
sahilmgandhi	18:6a4db94011d3	30882	* \| \| \|1 = A Data OUT token has been received from the host.
sahilmgandhi	18:6a4db94011d3	30883	* \| \| \|This bit also set by PING tokens(in high-speed only).
sahilmgandhi	18:6a4db94011d3	30884	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30885	* \|[6] \|INTKIF \|Data IN Token Interrupt
sahilmgandhi	18:6a4db94011d3	30886	* \| \| \|0 = Not Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	30887	* \| \| \|1 = A Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	30888	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30889	* \|[7] \|PINGIF \|PING Token Interrupt
sahilmgandhi	18:6a4db94011d3	30890	* \| \| \|0 = A Data PING token has not been received from the host.
sahilmgandhi	18:6a4db94011d3	30891	* \| \| \|1 = A Data PING token has been received from the host.
sahilmgandhi	18:6a4db94011d3	30892	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30893	* \|[8] \|NAKIF \|USB NAK Sent
sahilmgandhi	18:6a4db94011d3	30894	* \| \| \|0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
sahilmgandhi	18:6a4db94011d3	30895	* \| \| \|1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
sahilmgandhi	18:6a4db94011d3	30896	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30897	* \|[9] \|STALLIF \|USB STALL Sent
sahilmgandhi	18:6a4db94011d3	30898	* \| \| \|0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
sahilmgandhi	18:6a4db94011d3	30899	* \| \| \|1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
sahilmgandhi	18:6a4db94011d3	30900	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30901	* \|[10] \|NYETIF \|NYET Sent
sahilmgandhi	18:6a4db94011d3	30902	* \| \| \|0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
sahilmgandhi	18:6a4db94011d3	30903	* \| \| \|1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
sahilmgandhi	18:6a4db94011d3	30904	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30905	* \|[11] \|ERRIF \|ERR Sent
sahilmgandhi	18:6a4db94011d3	30906	* \| \| \|0 = No any error in the transaction.
sahilmgandhi	18:6a4db94011d3	30907	* \| \| \|1 = There occurs any error in the transaction.
sahilmgandhi	18:6a4db94011d3	30908	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30909	* \|[12] \|SHORTRXIF \|Bulk Out Short Packet Received
sahilmgandhi	18:6a4db94011d3	30910	* \| \| \|0 = No bulk out short packet is received.
sahilmgandhi	18:6a4db94011d3	30911	* \| \| \|1 = Received bulk out short packet (including zero length packet ).
sahilmgandhi	18:6a4db94011d3	30912	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	30913	*/
sahilmgandhi	18:6a4db94011d3	30914	__IO uint32_t EPKINTSTS;
sahilmgandhi	18:6a4db94011d3	30915
sahilmgandhi	18:6a4db94011d3	30916	/**
sahilmgandhi	18:6a4db94011d3	30917	* EPKINTEN
sahilmgandhi	18:6a4db94011d3	30918	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30919	* Offset: 0x1FC Endpoint K Interrupt Enable Register
sahilmgandhi	18:6a4db94011d3	30920	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30921	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30922	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30923	* \|[0] \|BUFFULLIEN\|Buffer Full Interrupt
sahilmgandhi	18:6a4db94011d3	30924	* \| \| \|When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
sahilmgandhi	18:6a4db94011d3	30925	* \| \| \|0 = Buffer full interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30926	* \| \| \|1 = Buffer full interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30927	* \|[1] \|BUFEMPTYIEN\|Buffer Empty Interrupt
sahilmgandhi	18:6a4db94011d3	30928	* \| \| \|When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
sahilmgandhi	18:6a4db94011d3	30929	* \| \| \|0 = Buffer empty interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30930	* \| \| \|1 = Buffer empty interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30931	* \|[2] \|SHORTTXIEN\|Short Packet Transferred Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30932	* \| \| \|When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
sahilmgandhi	18:6a4db94011d3	30933	* \| \| \|0 = Short data packet interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30934	* \| \| \|1 = Short data packet interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30935	* \|[3] \|TXPKIEN \|Data Packet Transmitted Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30936	* \| \| \|When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
sahilmgandhi	18:6a4db94011d3	30937	* \| \| \|0 = Data packet has been received from the host interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30938	* \| \| \|1 = Data packet has been received from the host interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30939	* \|[4] \|RXPKIEN \|Data Packet Received Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30940	* \| \| \|When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
sahilmgandhi	18:6a4db94011d3	30941	* \| \| \|0 = Data packet has been transmitted to the host interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30942	* \| \| \|1 = Data packet has been transmitted to the host interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30943	* \|[5] \|OUTTKIEN \|Data OUT Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30944	* \| \| \|When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
sahilmgandhi	18:6a4db94011d3	30945	* \| \| \|0 = Data OUT token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30946	* \| \| \|1 = Data OUT token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30947	* \|[6] \|INTKIEN \|Data IN Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30948	* \| \| \|When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	30949	* \| \| \|0 = Data IN token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30950	* \| \| \|1 = Data IN token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30951	* \|[7] \|PINGIEN \|PING Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30952	* \| \| \|When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
sahilmgandhi	18:6a4db94011d3	30953	* \| \| \|0 = PING token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30954	* \| \| \|1 = PING token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30955	* \|[8] \|NAKIEN \|USB NAK Sent Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30956	* \| \| \|When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
sahilmgandhi	18:6a4db94011d3	30957	* \| \| \|0 = NAK token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30958	* \| \| \|1 = NAK token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30959	* \|[9] \|STALLIEN \|USB STALL Sent Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30960	* \| \| \|When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
sahilmgandhi	18:6a4db94011d3	30961	* \| \| \|0 = STALL token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30962	* \| \| \|1 = STALL token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30963	* \|[10] \|NYETIEN \|NYET Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30964	* \| \| \|When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	30965	* \| \| \|0 = NYET condition interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30966	* \| \| \|1 = NYET condition interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30967	* \|[11] \|ERRIEN \|ERR Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30968	* \| \| \|When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	30969	* \| \| \|0 = Error event interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30970	* \| \| \|1 = Error event interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30971	* \|[12] \|SHORTRXIEN\|Bulk Out Short Packet Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	30972	* \| \| \|When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	30973	* \| \| \|0 = Bulk out interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	30974	* \| \| \|1 = Bulk out interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	30975	*/
sahilmgandhi	18:6a4db94011d3	30976	__IO uint32_t EPKINTEN;
sahilmgandhi	18:6a4db94011d3	30977
sahilmgandhi	18:6a4db94011d3	30978	/**
sahilmgandhi	18:6a4db94011d3	30979	* EPKDATCNT
sahilmgandhi	18:6a4db94011d3	30980	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30981	* Offset: 0x200 Endpoint K Data Available Count Register
sahilmgandhi	18:6a4db94011d3	30982	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30983	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30984	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30985	* \|[0:15] \|DATCNT \|Data Count
sahilmgandhi	18:6a4db94011d3	30986	* \| \| \|For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
sahilmgandhi	18:6a4db94011d3	30987	* \|[16:30] \|DMALOOP \|DMA Loop
sahilmgandhi	18:6a4db94011d3	30988	* \| \| \|This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
sahilmgandhi	18:6a4db94011d3	30989	*/
sahilmgandhi	18:6a4db94011d3	30990	__I uint32_t EPKDATCNT;
sahilmgandhi	18:6a4db94011d3	30991
sahilmgandhi	18:6a4db94011d3	30992	/**
sahilmgandhi	18:6a4db94011d3	30993	* EPKRSPCTL
sahilmgandhi	18:6a4db94011d3	30994	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	30995	* Offset: 0x204 Endpoint K Response Control Register
sahilmgandhi	18:6a4db94011d3	30996	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30997	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	30998	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	30999	* \|[0] \|FLUSH \|Buffer Flush
sahilmgandhi	18:6a4db94011d3	31000	* \| \| \|Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
sahilmgandhi	18:6a4db94011d3	31001	* \| \| \|This bit is self-clearing.
sahilmgandhi	18:6a4db94011d3	31002	* \| \| \|This bit should always be written after an configuration event.
sahilmgandhi	18:6a4db94011d3	31003	* \| \| \|0 = The packet buffer is not flushed.
sahilmgandhi	18:6a4db94011d3	31004	* \| \| \|1 = The packet buffer is flushed by user.
sahilmgandhi	18:6a4db94011d3	31005	* \|[1:2] \|MODE \|Mode Control
sahilmgandhi	18:6a4db94011d3	31006	* \| \| \|The two bits decide the operation mode of the in-endpoint.
sahilmgandhi	18:6a4db94011d3	31007	* \| \| \|00: Auto-Validate Mode
sahilmgandhi	18:6a4db94011d3	31008	* \| \| \|01: Manual-Validate Mode
sahilmgandhi	18:6a4db94011d3	31009	* \| \| \|10: Fly Mode
sahilmgandhi	18:6a4db94011d3	31010	* \| \| \|11: Reserved
sahilmgandhi	18:6a4db94011d3	31011	* \| \| \|These bits are not valid for an out-endpoint.
sahilmgandhi	18:6a4db94011d3	31012	* \| \| \|The auto validate mode will be activated when the reserved mode is selected.
sahilmgandhi	18:6a4db94011d3	31013	* \|[3] \|TOGGLE \|Endpoint Toggle
sahilmgandhi	18:6a4db94011d3	31014	* \| \| \|This bit is used to clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	31015	* \| \| \|Reading this bit returns the current state of the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	31016	* \| \| \|The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
sahilmgandhi	18:6a4db94011d3	31017	* \| \| \|Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
sahilmgandhi	18:6a4db94011d3	31018	* \| \| \|0 = Not clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	31019	* \| \| \|1 = Clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	31020	* \|[4] \|HALT \|Endpoint Halt
sahilmgandhi	18:6a4db94011d3	31021	* \| \| \|This bit is used to send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	31022	* \| \| \|When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
sahilmgandhi	18:6a4db94011d3	31023	* \| \| \|0 = Not send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	31024	* \| \| \|1 = Send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	31025	* \|[5] \|ZEROLEN \|Zero Length
sahilmgandhi	18:6a4db94011d3	31026	* \| \| \|This bit is used to send a zero-length packet n response to an IN-token.
sahilmgandhi	18:6a4db94011d3	31027	* \| \| \|When this bit is set, a zero packet is sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	31028	* \| \| \|0 = A zero packet is not sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	31029	* \| \| \|1 = A zero packet is sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	31030	* \|[6] \|SHORTTXEN \|Short Packet Transfer Enable
sahilmgandhi	18:6a4db94011d3	31031	* \| \| \|This bit is applicable only in case of Auto-Validate Method.
sahilmgandhi	18:6a4db94011d3	31032	* \| \| \|This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
sahilmgandhi	18:6a4db94011d3	31033	* \| \| \|0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
sahilmgandhi	18:6a4db94011d3	31034	* \| \| \|1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
sahilmgandhi	18:6a4db94011d3	31035	* \|[7] \|DISBUF \|Buffer Disable Control
sahilmgandhi	18:6a4db94011d3	31036	* \| \| \|This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	31037	* \| \| \|0 = Buffer Not Disabled when Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	31038	* \| \| \|1 = Buffer Disabled when Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	31039	*/
sahilmgandhi	18:6a4db94011d3	31040	__IO uint32_t EPKRSPCTL;
sahilmgandhi	18:6a4db94011d3	31041
sahilmgandhi	18:6a4db94011d3	31042	/**
sahilmgandhi	18:6a4db94011d3	31043	* EPKMPS
sahilmgandhi	18:6a4db94011d3	31044	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	31045	* Offset: 0x208 Endpoint K Maximum Packet Size Register
sahilmgandhi	18:6a4db94011d3	31046	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	31047	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	31048	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	31049	* \|[0:10] \|EPMPS \|Endpoint Maximum Packet Size
sahilmgandhi	18:6a4db94011d3	31050	* \| \| \|This field determines the Maximum Packet Size of the Endpoint.
sahilmgandhi	18:6a4db94011d3	31051	*/
sahilmgandhi	18:6a4db94011d3	31052	__IO uint32_t EPKMPS;
sahilmgandhi	18:6a4db94011d3	31053
sahilmgandhi	18:6a4db94011d3	31054	/**
sahilmgandhi	18:6a4db94011d3	31055	* EPKTXCNT
sahilmgandhi	18:6a4db94011d3	31056	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	31057	* Offset: 0x20C Endpoint K Transfer Count Register
sahilmgandhi	18:6a4db94011d3	31058	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	31059	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	31060	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	31061	* \|[0:10] \|TXCNT \|Endpoint Transfer Count
sahilmgandhi	18:6a4db94011d3	31062	* \| \| \|For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
sahilmgandhi	18:6a4db94011d3	31063	* \| \| \|For OUT endpoints, this field has no effect.
sahilmgandhi	18:6a4db94011d3	31064	*/
sahilmgandhi	18:6a4db94011d3	31065	__IO uint32_t EPKTXCNT;
sahilmgandhi	18:6a4db94011d3	31066
sahilmgandhi	18:6a4db94011d3	31067	/**
sahilmgandhi	18:6a4db94011d3	31068	* EPKCFG
sahilmgandhi	18:6a4db94011d3	31069	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	31070	* Offset: 0x210 Endpoint K Configuration Register
sahilmgandhi	18:6a4db94011d3	31071	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	31072	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	31073	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	31074	* \|[0] \|EPEN \|Endpoint Valid
sahilmgandhi	18:6a4db94011d3	31075	* \| \| \|When set, this bit enables this endpoint.
sahilmgandhi	18:6a4db94011d3	31076	* \| \| \|This bit has no effect on Endpoint 0, which is always enabled.
sahilmgandhi	18:6a4db94011d3	31077	* \| \| \|0 = The endpoint Disabled.
sahilmgandhi	18:6a4db94011d3	31078	* \| \| \|1 = The endpoint Enabled.
sahilmgandhi	18:6a4db94011d3	31079	* \|[1:2] \|EPTYPE \|Endpoint Type
sahilmgandhi	18:6a4db94011d3	31080	* \| \| \|This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
sahilmgandhi	18:6a4db94011d3	31081	* \| \| \|00 = Reserved.
sahilmgandhi	18:6a4db94011d3	31082	* \| \| \|01 = Bulk.
sahilmgandhi	18:6a4db94011d3	31083	* \| \| \|10 = Interrupt.
sahilmgandhi	18:6a4db94011d3	31084	* \| \| \|11 = Isochronous.
sahilmgandhi	18:6a4db94011d3	31085	* \|[3] \|EPDIR \|Endpoint Direction
sahilmgandhi	18:6a4db94011d3	31086	* \| \| \|0 = out-endpoint (Host OUT to Device).
sahilmgandhi	18:6a4db94011d3	31087	* \| \| \|1 = in-endpoint (Host IN to Device).
sahilmgandhi	18:6a4db94011d3	31088	* \| \| \|Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
sahilmgandhi	18:6a4db94011d3	31089	* \|[4:7] \|EPNUM \|Endpoint Number
sahilmgandhi	18:6a4db94011d3	31090	* \| \| \|This field selects the number of the endpoint. Valid numbers 1 to 15.
sahilmgandhi	18:6a4db94011d3	31091	*/
sahilmgandhi	18:6a4db94011d3	31092	__IO uint32_t EPKCFG;
sahilmgandhi	18:6a4db94011d3	31093
sahilmgandhi	18:6a4db94011d3	31094	/**
sahilmgandhi	18:6a4db94011d3	31095	* EPKBUFSTART
sahilmgandhi	18:6a4db94011d3	31096	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	31097	* Offset: 0x214 Endpoint K RAM Start Address Register
sahilmgandhi	18:6a4db94011d3	31098	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	31099	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	31100	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	31101	* \|[0:11] \|SADDR \|Endpoint Start Address
sahilmgandhi	18:6a4db94011d3	31102	* \| \| \|This is the start-address of the RAM space allocated for the endpoint A~L.
sahilmgandhi	18:6a4db94011d3	31103	*/
sahilmgandhi	18:6a4db94011d3	31104	__IO uint32_t EPKBUFSTART;
sahilmgandhi	18:6a4db94011d3	31105
sahilmgandhi	18:6a4db94011d3	31106	/**
sahilmgandhi	18:6a4db94011d3	31107	* EPKBUFEND
sahilmgandhi	18:6a4db94011d3	31108	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	31109	* Offset: 0x218 Endpoint K RAM End Address Register
sahilmgandhi	18:6a4db94011d3	31110	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	31111	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	31112	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	31113	* \|[0:11] \|EADDR \|Endpoint End Address
sahilmgandhi	18:6a4db94011d3	31114	* \| \| \|This is the end-address of the RAM space allocated for the endpoint A~L.
sahilmgandhi	18:6a4db94011d3	31115	*/
sahilmgandhi	18:6a4db94011d3	31116	__IO uint32_t EPKBUFEND;
sahilmgandhi	18:6a4db94011d3	31117
sahilmgandhi	18:6a4db94011d3	31118	union {
sahilmgandhi	18:6a4db94011d3	31119
sahilmgandhi	18:6a4db94011d3	31120	/**
sahilmgandhi	18:6a4db94011d3	31121	* EPLDAT
sahilmgandhi	18:6a4db94011d3	31122	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	31123	* Offset: 0x21C Endpoint L Data Register
sahilmgandhi	18:6a4db94011d3	31124	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	31125	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	31126	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	31127	* \|[0:31] \|EPDAT \|Endpoint A~L Data Register
sahilmgandhi	18:6a4db94011d3	31128	* \| \| \|Endpoint A~L data buffer for the buffer transaction (read or write).
sahilmgandhi	18:6a4db94011d3	31129	* \| \| \|Note: Only word or byte access are supported.
sahilmgandhi	18:6a4db94011d3	31130	*/
sahilmgandhi	18:6a4db94011d3	31131	__IO uint32_t EPLDAT;
sahilmgandhi	18:6a4db94011d3	31132	/**
sahilmgandhi	18:6a4db94011d3	31133	* EPLDAT_BYTE
sahilmgandhi	18:6a4db94011d3	31134	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	31135	* Offset: 0x21C Endpoint L Data Register for Byte Access
sahilmgandhi	18:6a4db94011d3	31136	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	31137	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	31138	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	31139	* \|[0:7] \|EPDAT \|Endpoint A~L Data Register
sahilmgandhi	18:6a4db94011d3	31140	* \| \| \|Endpoint A~L data buffer for the buffer transaction (read or write).
sahilmgandhi	18:6a4db94011d3	31141	* \| \| \|Note: Only word or byte access are supported.
sahilmgandhi	18:6a4db94011d3	31142	*/
sahilmgandhi	18:6a4db94011d3	31143	__IO uint8_t EPLDAT_BYTE;
sahilmgandhi	18:6a4db94011d3	31144
sahilmgandhi	18:6a4db94011d3	31145	}; ///< Define EPL Data Register 32-bit or 8-bit access
sahilmgandhi	18:6a4db94011d3	31146
sahilmgandhi	18:6a4db94011d3	31147	/**
sahilmgandhi	18:6a4db94011d3	31148	* EPLINTSTS
sahilmgandhi	18:6a4db94011d3	31149	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	31150	* Offset: 0x220 Endpoint L Interrupt Status Register
sahilmgandhi	18:6a4db94011d3	31151	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	31152	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	31153	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	31154	* \|[0] \|BUFFULLIF \|Buffer Full
sahilmgandhi	18:6a4db94011d3	31155	* \| \| \|For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
sahilmgandhi	18:6a4db94011d3	31156	* \| \| \|For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
sahilmgandhi	18:6a4db94011d3	31157	* \| \| \|0 = The endpoint packet buffer is not full.
sahilmgandhi	18:6a4db94011d3	31158	* \| \| \|1 = The endpoint packet buffer is full.
sahilmgandhi	18:6a4db94011d3	31159	* \| \| \|Note: This bit is read-only.
sahilmgandhi	18:6a4db94011d3	31160	* \|[1] \|BUFEMPTYIF\|Buffer Empty
sahilmgandhi	18:6a4db94011d3	31161	* \| \| \|For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
sahilmgandhi	18:6a4db94011d3	31162	* \| \| \|0 = The endpoint buffer is not empty.
sahilmgandhi	18:6a4db94011d3	31163	* \| \| \|1 = The endpoint buffer is empty.
sahilmgandhi	18:6a4db94011d3	31164	* \| \| \|For an OUT endpoint:
sahilmgandhi	18:6a4db94011d3	31165	* \| \| \|0 = The currently selected buffer has not a count of 0.
sahilmgandhi	18:6a4db94011d3	31166	* \| \| \|1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
sahilmgandhi	18:6a4db94011d3	31167	* \| \| \|Note: This bit is read-only.
sahilmgandhi	18:6a4db94011d3	31168	* \|[2] \|SHORTTXIF \|Short Packet Transferred Interrupt
sahilmgandhi	18:6a4db94011d3	31169	* \| \| \|0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
sahilmgandhi	18:6a4db94011d3	31170	* \| \| \|1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
sahilmgandhi	18:6a4db94011d3	31171	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	31172	* \|[3] \|TXPKIF \|Data Packet Transmitted Interrupt
sahilmgandhi	18:6a4db94011d3	31173	* \| \| \|0 = Not a data packet is transmitted from the endpoint to the host.
sahilmgandhi	18:6a4db94011d3	31174	* \| \| \|1 = A data packet is transmitted from the endpoint to the host.
sahilmgandhi	18:6a4db94011d3	31175	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	31176	* \|[4] \|RXPKIF \|Data Packet Received Interrupt
sahilmgandhi	18:6a4db94011d3	31177	* \| \| \|0 = No data packet is received from the host by the endpoint.
sahilmgandhi	18:6a4db94011d3	31178	* \| \| \|1 = A data packet is received from the host by the endpoint.
sahilmgandhi	18:6a4db94011d3	31179	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	31180	* \|[5] \|OUTTKIF \|Data OUT Token Interrupt
sahilmgandhi	18:6a4db94011d3	31181	* \| \| \|0 = A Data OUT token has not been received from the host.
sahilmgandhi	18:6a4db94011d3	31182	* \| \| \|1 = A Data OUT token has been received from the host.
sahilmgandhi	18:6a4db94011d3	31183	* \| \| \|This bit also set by PING tokens(in high-speed only).
sahilmgandhi	18:6a4db94011d3	31184	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	31185	* \|[6] \|INTKIF \|Data IN Token Interrupt
sahilmgandhi	18:6a4db94011d3	31186	* \| \| \|0 = Not Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	31187	* \| \| \|1 = A Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	31188	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	31189	* \|[7] \|PINGIF \|PING Token Interrupt
sahilmgandhi	18:6a4db94011d3	31190	* \| \| \|0 = A Data PING token has not been received from the host.
sahilmgandhi	18:6a4db94011d3	31191	* \| \| \|1 = A Data PING token has been received from the host.
sahilmgandhi	18:6a4db94011d3	31192	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	31193	* \|[8] \|NAKIF \|USB NAK Sent
sahilmgandhi	18:6a4db94011d3	31194	* \| \| \|0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
sahilmgandhi	18:6a4db94011d3	31195	* \| \| \|1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
sahilmgandhi	18:6a4db94011d3	31196	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	31197	* \|[9] \|STALLIF \|USB STALL Sent
sahilmgandhi	18:6a4db94011d3	31198	* \| \| \|0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
sahilmgandhi	18:6a4db94011d3	31199	* \| \| \|1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
sahilmgandhi	18:6a4db94011d3	31200	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	31201	* \|[10] \|NYETIF \|NYET Sent
sahilmgandhi	18:6a4db94011d3	31202	* \| \| \|0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
sahilmgandhi	18:6a4db94011d3	31203	* \| \| \|1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
sahilmgandhi	18:6a4db94011d3	31204	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	31205	* \|[11] \|ERRIF \|ERR Sent
sahilmgandhi	18:6a4db94011d3	31206	* \| \| \|0 = No any error in the transaction.
sahilmgandhi	18:6a4db94011d3	31207	* \| \| \|1 = There occurs any error in the transaction.
sahilmgandhi	18:6a4db94011d3	31208	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	31209	* \|[12] \|SHORTRXIF \|Bulk Out Short Packet Received
sahilmgandhi	18:6a4db94011d3	31210	* \| \| \|0 = No bulk out short packet is received.
sahilmgandhi	18:6a4db94011d3	31211	* \| \| \|1 = Received bulk out short packet (including zero length packet ).
sahilmgandhi	18:6a4db94011d3	31212	* \| \| \|Note: Write 1 to clear this bit to 0.
sahilmgandhi	18:6a4db94011d3	31213	*/
sahilmgandhi	18:6a4db94011d3	31214	__IO uint32_t EPLINTSTS;
sahilmgandhi	18:6a4db94011d3	31215
sahilmgandhi	18:6a4db94011d3	31216	/**
sahilmgandhi	18:6a4db94011d3	31217	* EPLINTEN
sahilmgandhi	18:6a4db94011d3	31218	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	31219	* Offset: 0x224 Endpoint L Interrupt Enable Register
sahilmgandhi	18:6a4db94011d3	31220	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	31221	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	31222	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	31223	* \|[0] \|BUFFULLIEN\|Buffer Full Interrupt
sahilmgandhi	18:6a4db94011d3	31224	* \| \| \|When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
sahilmgandhi	18:6a4db94011d3	31225	* \| \| \|0 = Buffer full interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	31226	* \| \| \|1 = Buffer full interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	31227	* \|[1] \|BUFEMPTYIEN\|Buffer Empty Interrupt
sahilmgandhi	18:6a4db94011d3	31228	* \| \| \|When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
sahilmgandhi	18:6a4db94011d3	31229	* \| \| \|0 = Buffer empty interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	31230	* \| \| \|1 = Buffer empty interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	31231	* \|[2] \|SHORTTXIEN\|Short Packet Transferred Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	31232	* \| \| \|When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
sahilmgandhi	18:6a4db94011d3	31233	* \| \| \|0 = Short data packet interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	31234	* \| \| \|1 = Short data packet interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	31235	* \|[3] \|TXPKIEN \|Data Packet Transmitted Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	31236	* \| \| \|When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
sahilmgandhi	18:6a4db94011d3	31237	* \| \| \|0 = Data packet has been received from the host interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	31238	* \| \| \|1 = Data packet has been received from the host interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	31239	* \|[4] \|RXPKIEN \|Data Packet Received Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	31240	* \| \| \|When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
sahilmgandhi	18:6a4db94011d3	31241	* \| \| \|0 = Data packet has been transmitted to the host interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	31242	* \| \| \|1 = Data packet has been transmitted to the host interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	31243	* \|[5] \|OUTTKIEN \|Data OUT Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	31244	* \| \| \|When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
sahilmgandhi	18:6a4db94011d3	31245	* \| \| \|0 = Data OUT token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	31246	* \| \| \|1 = Data OUT token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	31247	* \|[6] \|INTKIEN \|Data IN Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	31248	* \| \| \|When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
sahilmgandhi	18:6a4db94011d3	31249	* \| \| \|0 = Data IN token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	31250	* \| \| \|1 = Data IN token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	31251	* \|[7] \|PINGIEN \|PING Token Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	31252	* \| \| \|When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
sahilmgandhi	18:6a4db94011d3	31253	* \| \| \|0 = PING token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	31254	* \| \| \|1 = PING token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	31255	* \|[8] \|NAKIEN \|USB NAK Sent Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	31256	* \| \| \|When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
sahilmgandhi	18:6a4db94011d3	31257	* \| \| \|0 = NAK token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	31258	* \| \| \|1 = NAK token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	31259	* \|[9] \|STALLIEN \|USB STALL Sent Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	31260	* \| \| \|When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
sahilmgandhi	18:6a4db94011d3	31261	* \| \| \|0 = STALL token interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	31262	* \| \| \|1 = STALL token interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	31263	* \|[10] \|NYETIEN \|NYET Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	31264	* \| \| \|When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	31265	* \| \| \|0 = NYET condition interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	31266	* \| \| \|1 = NYET condition interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	31267	* \|[11] \|ERRIEN \|ERR Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	31268	* \| \| \|When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	31269	* \| \| \|0 = Error event interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	31270	* \| \| \|1 = Error event interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	31271	* \|[12] \|SHORTRXIEN\|Bulk Out Short Packet Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	31272	* \| \| \|When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
sahilmgandhi	18:6a4db94011d3	31273	* \| \| \|0 = Bulk out interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	31274	* \| \| \|1 = Bulk out interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	31275	*/
sahilmgandhi	18:6a4db94011d3	31276	__IO uint32_t EPLINTEN;
sahilmgandhi	18:6a4db94011d3	31277
sahilmgandhi	18:6a4db94011d3	31278	/**
sahilmgandhi	18:6a4db94011d3	31279	* EPLDATCNT
sahilmgandhi	18:6a4db94011d3	31280	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	31281	* Offset: 0x228 Endpoint L Data Available Count Register
sahilmgandhi	18:6a4db94011d3	31282	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	31283	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	31284	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	31285	* \|[0:15] \|DATCNT \|Data Count
sahilmgandhi	18:6a4db94011d3	31286	* \| \| \|For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
sahilmgandhi	18:6a4db94011d3	31287	* \|[16:30] \|DMALOOP \|DMA Loop
sahilmgandhi	18:6a4db94011d3	31288	* \| \| \|This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
sahilmgandhi	18:6a4db94011d3	31289	*/
sahilmgandhi	18:6a4db94011d3	31290	__I uint32_t EPLDATCNT;
sahilmgandhi	18:6a4db94011d3	31291
sahilmgandhi	18:6a4db94011d3	31292	/**
sahilmgandhi	18:6a4db94011d3	31293	* EPLRSPCTL
sahilmgandhi	18:6a4db94011d3	31294	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	31295	* Offset: 0x22C Endpoint L Response Control Register
sahilmgandhi	18:6a4db94011d3	31296	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	31297	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	31298	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	31299	* \|[0] \|FLUSH \|Buffer Flush
sahilmgandhi	18:6a4db94011d3	31300	* \| \| \|Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
sahilmgandhi	18:6a4db94011d3	31301	* \| \| \|This bit is self-clearing.
sahilmgandhi	18:6a4db94011d3	31302	* \| \| \|This bit should always be written after an configuration event.
sahilmgandhi	18:6a4db94011d3	31303	* \| \| \|0 = The packet buffer is not flushed.
sahilmgandhi	18:6a4db94011d3	31304	* \| \| \|1 = The packet buffer is flushed by user.
sahilmgandhi	18:6a4db94011d3	31305	* \|[1:2] \|MODE \|Mode Control
sahilmgandhi	18:6a4db94011d3	31306	* \| \| \|The two bits decide the operation mode of the in-endpoint.
sahilmgandhi	18:6a4db94011d3	31307	* \| \| \|00: Auto-Validate Mode
sahilmgandhi	18:6a4db94011d3	31308	* \| \| \|01: Manual-Validate Mode
sahilmgandhi	18:6a4db94011d3	31309	* \| \| \|10: Fly Mode
sahilmgandhi	18:6a4db94011d3	31310	* \| \| \|11: Reserved
sahilmgandhi	18:6a4db94011d3	31311	* \| \| \|These bits are not valid for an out-endpoint.
sahilmgandhi	18:6a4db94011d3	31312	* \| \| \|The auto validate mode will be activated when the reserved mode is selected.
sahilmgandhi	18:6a4db94011d3	31313	* \|[3] \|TOGGLE \|Endpoint Toggle
sahilmgandhi	18:6a4db94011d3	31314	* \| \| \|This bit is used to clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	31315	* \| \| \|Reading this bit returns the current state of the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	31316	* \| \| \|The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
sahilmgandhi	18:6a4db94011d3	31317	* \| \| \|Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
sahilmgandhi	18:6a4db94011d3	31318	* \| \| \|0 = Not clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	31319	* \| \| \|1 = Clear the endpoint data toggle bit.
sahilmgandhi	18:6a4db94011d3	31320	* \|[4] \|HALT \|Endpoint Halt
sahilmgandhi	18:6a4db94011d3	31321	* \| \| \|This bit is used to send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	31322	* \| \| \|When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
sahilmgandhi	18:6a4db94011d3	31323	* \| \| \|0 = Not send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	31324	* \| \| \|1 = Send a STALL handshake as response to the token from the host.
sahilmgandhi	18:6a4db94011d3	31325	* \|[5] \|ZEROLEN \|Zero Length
sahilmgandhi	18:6a4db94011d3	31326	* \| \| \|This bit is used to send a zero-length packet n response to an IN-token.
sahilmgandhi	18:6a4db94011d3	31327	* \| \| \|When this bit is set, a zero packet is sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	31328	* \| \| \|0 = A zero packet is not sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	31329	* \| \| \|1 = A zero packet is sent to the host on reception of an IN-token.
sahilmgandhi	18:6a4db94011d3	31330	* \|[6] \|SHORTTXEN \|Short Packet Transfer Enable
sahilmgandhi	18:6a4db94011d3	31331	* \| \| \|This bit is applicable only in case of Auto-Validate Method.
sahilmgandhi	18:6a4db94011d3	31332	* \| \| \|This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
sahilmgandhi	18:6a4db94011d3	31333	* \| \| \|0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
sahilmgandhi	18:6a4db94011d3	31334	* \| \| \|1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
sahilmgandhi	18:6a4db94011d3	31335	* \|[7] \|DISBUF \|Buffer Disable Control
sahilmgandhi	18:6a4db94011d3	31336	* \| \| \|This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	31337	* \| \| \|0 = Buffer Not Disabled when Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	31338	* \| \| \|1 = Buffer Disabled when Bulk-OUT short packet is received.
sahilmgandhi	18:6a4db94011d3	31339	*/
sahilmgandhi	18:6a4db94011d3	31340	__IO uint32_t EPLRSPCTL;
sahilmgandhi	18:6a4db94011d3	31341
sahilmgandhi	18:6a4db94011d3	31342	/**
sahilmgandhi	18:6a4db94011d3	31343	* EPLMPS
sahilmgandhi	18:6a4db94011d3	31344	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	31345	* Offset: 0x230 Endpoint L Maximum Packet Size Register
sahilmgandhi	18:6a4db94011d3	31346	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	31347	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	31348	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	31349	* \|[0:10] \|EPMPS \|Endpoint Maximum Packet Size
sahilmgandhi	18:6a4db94011d3	31350	* \| \| \|This field determines the Maximum Packet Size of the Endpoint.
sahilmgandhi	18:6a4db94011d3	31351	*/
sahilmgandhi	18:6a4db94011d3	31352	__IO uint32_t EPLMPS;
sahilmgandhi	18:6a4db94011d3	31353
sahilmgandhi	18:6a4db94011d3	31354	/**
sahilmgandhi	18:6a4db94011d3	31355	* EPLTXCNT
sahilmgandhi	18:6a4db94011d3	31356	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	31357	* Offset: 0x234 Endpoint L Transfer Count Register
sahilmgandhi	18:6a4db94011d3	31358	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	31359	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	31360	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	31361	* \|[0:10] \|TXCNT \|Endpoint Transfer Count
sahilmgandhi	18:6a4db94011d3	31362	* \| \| \|For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
sahilmgandhi	18:6a4db94011d3	31363	* \| \| \|For OUT endpoints, this field has no effect.
sahilmgandhi	18:6a4db94011d3	31364	*/
sahilmgandhi	18:6a4db94011d3	31365	__IO uint32_t EPLTXCNT;
sahilmgandhi	18:6a4db94011d3	31366
sahilmgandhi	18:6a4db94011d3	31367	/**
sahilmgandhi	18:6a4db94011d3	31368	* EPLCFG
sahilmgandhi	18:6a4db94011d3	31369	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	31370	* Offset: 0x238 Endpoint L Configuration Register
sahilmgandhi	18:6a4db94011d3	31371	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	31372	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	31373	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	31374	* \|[0] \|EPEN \|Endpoint Valid
sahilmgandhi	18:6a4db94011d3	31375	* \| \| \|When set, this bit enables this endpoint.
sahilmgandhi	18:6a4db94011d3	31376	* \| \| \|This bit has no effect on Endpoint 0, which is always enabled.
sahilmgandhi	18:6a4db94011d3	31377	* \| \| \|0 = The endpoint Disabled.
sahilmgandhi	18:6a4db94011d3	31378	* \| \| \|1 = The endpoint Enabled.
sahilmgandhi	18:6a4db94011d3	31379	* \|[1:2] \|EPTYPE \|Endpoint Type
sahilmgandhi	18:6a4db94011d3	31380	* \| \| \|This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
sahilmgandhi	18:6a4db94011d3	31381	* \| \| \|00 = Reserved.
sahilmgandhi	18:6a4db94011d3	31382	* \| \| \|01 = Bulk.
sahilmgandhi	18:6a4db94011d3	31383	* \| \| \|10 = Interrupt.
sahilmgandhi	18:6a4db94011d3	31384	* \| \| \|11 = Isochronous.
sahilmgandhi	18:6a4db94011d3	31385	* \|[3] \|EPDIR \|Endpoint Direction
sahilmgandhi	18:6a4db94011d3	31386	* \| \| \|0 = out-endpoint (Host OUT to Device).
sahilmgandhi	18:6a4db94011d3	31387	* \| \| \|1 = in-endpoint (Host IN to Device).
sahilmgandhi	18:6a4db94011d3	31388	* \| \| \|Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
sahilmgandhi	18:6a4db94011d3	31389	* \|[4:7] \|EPNUM \|Endpoint Number
sahilmgandhi	18:6a4db94011d3	31390	* \| \| \|This field selects the number of the endpoint. Valid numbers 1 to 15.
sahilmgandhi	18:6a4db94011d3	31391	*/
sahilmgandhi	18:6a4db94011d3	31392	__IO uint32_t EPLCFG;
sahilmgandhi	18:6a4db94011d3	31393
sahilmgandhi	18:6a4db94011d3	31394	/**
sahilmgandhi	18:6a4db94011d3	31395	* EPLBUFSTART
sahilmgandhi	18:6a4db94011d3	31396	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	31397	* Offset: 0x23C Endpoint L RAM Start Address Register
sahilmgandhi	18:6a4db94011d3	31398	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	31399	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	31400	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	31401	* \|[0:11] \|SADDR \|Endpoint Start Address
sahilmgandhi	18:6a4db94011d3	31402	* \| \| \|This is the start-address of the RAM space allocated for the endpoint A~L.
sahilmgandhi	18:6a4db94011d3	31403	*/
sahilmgandhi	18:6a4db94011d3	31404	__IO uint32_t EPLBUFSTART;
sahilmgandhi	18:6a4db94011d3	31405
sahilmgandhi	18:6a4db94011d3	31406	/**
sahilmgandhi	18:6a4db94011d3	31407	* EPLBUFEND
sahilmgandhi	18:6a4db94011d3	31408	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	31409	* Offset: 0x240 Endpoint L RAM End Address Register
sahilmgandhi	18:6a4db94011d3	31410	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	31411	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	31412	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	31413	* \|[0:11] \|EADDR \|Endpoint End Address
sahilmgandhi	18:6a4db94011d3	31414	* \| \| \|This is the end-address of the RAM space allocated for the endpoint A~L.
sahilmgandhi	18:6a4db94011d3	31415	*/
sahilmgandhi	18:6a4db94011d3	31416	__IO uint32_t EPLBUFEND;
sahilmgandhi	18:6a4db94011d3	31417
sahilmgandhi	18:6a4db94011d3	31418	uint32_t RESERVE2[303];
sahilmgandhi	18:6a4db94011d3	31419
sahilmgandhi	18:6a4db94011d3	31420
sahilmgandhi	18:6a4db94011d3	31421	/**
sahilmgandhi	18:6a4db94011d3	31422	* DMAADDR
sahilmgandhi	18:6a4db94011d3	31423	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	31424	* Offset: 0x700 AHB DMA Address Register
sahilmgandhi	18:6a4db94011d3	31425	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	31426	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	31427	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	31428	* \|[0:31] \|DMAADDR \|DMAADDR
sahilmgandhi	18:6a4db94011d3	31429	* \| \| \|The register specifies the address from which the DMA has to read / write.
sahilmgandhi	18:6a4db94011d3	31430	* \| \| \|The address must WORD (32-bit) aligned.
sahilmgandhi	18:6a4db94011d3	31431	*/
sahilmgandhi	18:6a4db94011d3	31432	__IO uint32_t DMAADDR;
sahilmgandhi	18:6a4db94011d3	31433
sahilmgandhi	18:6a4db94011d3	31434	/**
sahilmgandhi	18:6a4db94011d3	31435	* PHYCTL
sahilmgandhi	18:6a4db94011d3	31436	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	31437	* Offset: 0x704 USB PHY Control Register
sahilmgandhi	18:6a4db94011d3	31438	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	31439	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	31440	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	31441	* \|[8] \|DPPUEN \|DP Pull-Up
sahilmgandhi	18:6a4db94011d3	31442	* \| \| \|0 = Pull-up resistor on D+ Disabled.
sahilmgandhi	18:6a4db94011d3	31443	* \| \| \|1 = Pull-up resistor on D+ Enabled.
sahilmgandhi	18:6a4db94011d3	31444	* \|[9] \|PHYEN \|PHY Suspend Enable Control
sahilmgandhi	18:6a4db94011d3	31445	* \| \| \|0 = The USB PHY is suspend.
sahilmgandhi	18:6a4db94011d3	31446	* \| \| \|1 = The USB PHY is not suspend.
sahilmgandhi	18:6a4db94011d3	31447	* \|[24] \|WKEN \|Wake-Up Enable Control
sahilmgandhi	18:6a4db94011d3	31448	* \| \| \|0 = The wake-up function Disabled.
sahilmgandhi	18:6a4db94011d3	31449	* \| \| \|1 = The wake-up function Enabled.
sahilmgandhi	18:6a4db94011d3	31450	* \|[31] \|VBUSDET \|VBUS Status
sahilmgandhi	18:6a4db94011d3	31451	* \| \| \|0 = The VBUS is not detected yet.
sahilmgandhi	18:6a4db94011d3	31452	* \| \| \|1 = The VBUS is detected.
sahilmgandhi	18:6a4db94011d3	31453	*/
sahilmgandhi	18:6a4db94011d3	31454	__IO uint32_t PHYCTL;
sahilmgandhi	18:6a4db94011d3	31455
sahilmgandhi	18:6a4db94011d3	31456	} USBD_T;
sahilmgandhi	18:6a4db94011d3	31457
sahilmgandhi	18:6a4db94011d3	31458	/**
sahilmgandhi	18:6a4db94011d3	31459	@addtogroup USBD_CONST USBD Bit Field Definition
sahilmgandhi	18:6a4db94011d3	31460	Constant Definitions for USBD Controller
sahilmgandhi	18:6a4db94011d3	31461	@{ */
sahilmgandhi	18:6a4db94011d3	31462
sahilmgandhi	18:6a4db94011d3	31463	#define USBD_GINTSTS_USBIF_Pos (0) /!< USBD GINTSTS: USBIF Position /
sahilmgandhi	18:6a4db94011d3	31464	#define USBD_GINTSTS_USBIF_Msk (0x1ul << USBD_GINTSTS_USBIF_Pos) /!< USBD GINTSTS: USBIF Mask /
sahilmgandhi	18:6a4db94011d3	31465
sahilmgandhi	18:6a4db94011d3	31466	#define USBD_GINTSTS_CEPIF_Pos (1) /!< USBD GINTSTS: CEPIF Position /
sahilmgandhi	18:6a4db94011d3	31467	#define USBD_GINTSTS_CEPIF_Msk (0x1ul << USBD_GINTSTS_CEPIF_Pos) /!< USBD GINTSTS: CEPIF Mask /
sahilmgandhi	18:6a4db94011d3	31468
sahilmgandhi	18:6a4db94011d3	31469	#define USBD_GINTSTS_EPAIF_Pos (2) /!< USBD GINTSTS: EPAIF Position /
sahilmgandhi	18:6a4db94011d3	31470	#define USBD_GINTSTS_EPAIF_Msk (0x1ul << USBD_GINTSTS_EPAIF_Pos) /!< USBD GINTSTS: EPAIF Mask /
sahilmgandhi	18:6a4db94011d3	31471
sahilmgandhi	18:6a4db94011d3	31472	#define USBD_GINTSTS_EPBIF_Pos (3) /!< USBD GINTSTS: EPBIF Position /
sahilmgandhi	18:6a4db94011d3	31473	#define USBD_GINTSTS_EPBIF_Msk (0x1ul << USBD_GINTSTS_EPBIF_Pos) /!< USBD GINTSTS: EPBIF Mask /
sahilmgandhi	18:6a4db94011d3	31474
sahilmgandhi	18:6a4db94011d3	31475	#define USBD_GINTSTS_EPCIF_Pos (4) /!< USBD GINTSTS: EPCIF Position /
sahilmgandhi	18:6a4db94011d3	31476	#define USBD_GINTSTS_EPCIF_Msk (0x1ul << USBD_GINTSTS_EPCIF_Pos) /!< USBD GINTSTS: EPCIF Mask /
sahilmgandhi	18:6a4db94011d3	31477
sahilmgandhi	18:6a4db94011d3	31478	#define USBD_GINTSTS_EPDIF_Pos (5) /!< USBD GINTSTS: EPDIF Position /
sahilmgandhi	18:6a4db94011d3	31479	#define USBD_GINTSTS_EPDIF_Msk (0x1ul << USBD_GINTSTS_EPDIF_Pos) /!< USBD GINTSTS: EPDIF Mask /
sahilmgandhi	18:6a4db94011d3	31480
sahilmgandhi	18:6a4db94011d3	31481	#define USBD_GINTSTS_EPEIF_Pos (6) /!< USBD GINTSTS: EPEIF Position /
sahilmgandhi	18:6a4db94011d3	31482	#define USBD_GINTSTS_EPEIF_Msk (0x1ul << USBD_GINTSTS_EPEIF_Pos) /!< USBD GINTSTS: EPEIF Mask /
sahilmgandhi	18:6a4db94011d3	31483
sahilmgandhi	18:6a4db94011d3	31484	#define USBD_GINTSTS_EPFIF_Pos (7) /!< USBD GINTSTS: EPFIF Position /
sahilmgandhi	18:6a4db94011d3	31485	#define USBD_GINTSTS_EPFIF_Msk (0x1ul << USBD_GINTSTS_EPFIF_Pos) /!< USBD GINTSTS: EPFIF Mask /
sahilmgandhi	18:6a4db94011d3	31486
sahilmgandhi	18:6a4db94011d3	31487	#define USBD_GINTSTS_EPGIF_Pos (8) /!< USBD GINTSTS: EPGIF Position /
sahilmgandhi	18:6a4db94011d3	31488	#define USBD_GINTSTS_EPGIF_Msk (0x1ul << USBD_GINTSTS_EPGIF_Pos) /!< USBD GINTSTS: EPGIF Mask /
sahilmgandhi	18:6a4db94011d3	31489
sahilmgandhi	18:6a4db94011d3	31490	#define USBD_GINTSTS_EPHIF_Pos (9) /!< USBD GINTSTS: EPHIF Position /
sahilmgandhi	18:6a4db94011d3	31491	#define USBD_GINTSTS_EPHIF_Msk (0x1ul << USBD_GINTSTS_EPHIF_Pos) /!< USBD GINTSTS: EPHIF Mask /
sahilmgandhi	18:6a4db94011d3	31492
sahilmgandhi	18:6a4db94011d3	31493	#define USBD_GINTSTS_EPIIF_Pos (10) /!< USBD GINTSTS: EPIIF Position /
sahilmgandhi	18:6a4db94011d3	31494	#define USBD_GINTSTS_EPIIF_Msk (0x1ul << USBD_GINTSTS_EPIIF_Pos) /!< USBD GINTSTS: EPIIF Mask /
sahilmgandhi	18:6a4db94011d3	31495
sahilmgandhi	18:6a4db94011d3	31496	#define USBD_GINTSTS_EPJIF_Pos (11) /!< USBD GINTSTS: EPJIF Position /
sahilmgandhi	18:6a4db94011d3	31497	#define USBD_GINTSTS_EPJIF_Msk (0x1ul << USBD_GINTSTS_EPJIF_Pos) /!< USBD GINTSTS: EPJIF Mask /
sahilmgandhi	18:6a4db94011d3	31498
sahilmgandhi	18:6a4db94011d3	31499	#define USBD_GINTSTS_EPKIF_Pos (12) /!< USBD GINTSTS: EPKIF Position /
sahilmgandhi	18:6a4db94011d3	31500	#define USBD_GINTSTS_EPKIF_Msk (0x1ul << USBD_GINTSTS_EPKIF_Pos) /!< USBD GINTSTS: EPKIF Mask /
sahilmgandhi	18:6a4db94011d3	31501
sahilmgandhi	18:6a4db94011d3	31502	#define USBD_GINTSTS_EPLIF_Pos (13) /!< USBD GINTSTS: EPLIF Position /
sahilmgandhi	18:6a4db94011d3	31503	#define USBD_GINTSTS_EPLIF_Msk (0x1ul << USBD_GINTSTS_EPLIF_Pos) /!< USBD GINTSTS: EPLIF Mask /
sahilmgandhi	18:6a4db94011d3	31504
sahilmgandhi	18:6a4db94011d3	31505	#define USBD_GINTEN_USBIE_Pos (0) /!< USBD GINTEN: USBIE Position /
sahilmgandhi	18:6a4db94011d3	31506	#define USBD_GINTEN_USBIE_Msk (0x1ul << USBD_GINTEN_USBIE_Pos) /!< USBD GINTEN: USBIE Mask /
sahilmgandhi	18:6a4db94011d3	31507
sahilmgandhi	18:6a4db94011d3	31508	#define USBD_GINTEN_CEPIE_Pos (1) /!< USBD GINTEN: CEPIE Position /
sahilmgandhi	18:6a4db94011d3	31509	#define USBD_GINTEN_CEPIE_Msk (0x1ul << USBD_GINTEN_CEPIE_Pos) /!< USBD GINTEN: CEPIE Mask /
sahilmgandhi	18:6a4db94011d3	31510
sahilmgandhi	18:6a4db94011d3	31511	#define USBD_GINTEN_EPAIE_Pos (2) /!< USBD GINTEN: EPAIE Position /
sahilmgandhi	18:6a4db94011d3	31512	#define USBD_GINTEN_EPAIE_Msk (0x1ul << USBD_GINTEN_EPAIE_Pos) /!< USBD GINTEN: EPAIE Mask /
sahilmgandhi	18:6a4db94011d3	31513
sahilmgandhi	18:6a4db94011d3	31514	#define USBD_GINTEN_EPBIE_Pos (3) /!< USBD GINTEN: EPBIE Position /
sahilmgandhi	18:6a4db94011d3	31515	#define USBD_GINTEN_EPBIE_Msk (0x1ul << USBD_GINTEN_EPBIE_Pos) /!< USBD GINTEN: EPBIE Mask /
sahilmgandhi	18:6a4db94011d3	31516
sahilmgandhi	18:6a4db94011d3	31517	#define USBD_GINTEN_EPCIE_Pos (4) /!< USBD GINTEN: EPCIE Position /
sahilmgandhi	18:6a4db94011d3	31518	#define USBD_GINTEN_EPCIE_Msk (0x1ul << USBD_GINTEN_EPCIE_Pos) /!< USBD GINTEN: EPCIE Mask /
sahilmgandhi	18:6a4db94011d3	31519
sahilmgandhi	18:6a4db94011d3	31520	#define USBD_GINTEN_EPDIE_Pos (5) /!< USBD GINTEN: EPDIE Position /
sahilmgandhi	18:6a4db94011d3	31521	#define USBD_GINTEN_EPDIE_Msk (0x1ul << USBD_GINTEN_EPDIE_Pos) /!< USBD GINTEN: EPDIE Mask /
sahilmgandhi	18:6a4db94011d3	31522
sahilmgandhi	18:6a4db94011d3	31523	#define USBD_GINTEN_EPEIE_Pos (6) /!< USBD GINTEN: EPEIE Position /
sahilmgandhi	18:6a4db94011d3	31524	#define USBD_GINTEN_EPEIE_Msk (0x1ul << USBD_GINTEN_EPEIE_Pos) /!< USBD GINTEN: EPEIE Mask /
sahilmgandhi	18:6a4db94011d3	31525
sahilmgandhi	18:6a4db94011d3	31526	#define USBD_GINTEN_EPFIE_Pos (7) /!< USBD GINTEN: EPFIE Position /
sahilmgandhi	18:6a4db94011d3	31527	#define USBD_GINTEN_EPFIE_Msk (0x1ul << USBD_GINTEN_EPFIE_Pos) /!< USBD GINTEN: EPFIE Mask /
sahilmgandhi	18:6a4db94011d3	31528
sahilmgandhi	18:6a4db94011d3	31529	#define USBD_GINTEN_EPGIE_Pos (8) /!< USBD GINTEN: EPGIE Position /
sahilmgandhi	18:6a4db94011d3	31530	#define USBD_GINTEN_EPGIE_Msk (0x1ul << USBD_GINTEN_EPGIE_Pos) /!< USBD GINTEN: EPGIE Mask /
sahilmgandhi	18:6a4db94011d3	31531
sahilmgandhi	18:6a4db94011d3	31532	#define USBD_GINTEN_EPHIE_Pos (9) /!< USBD GINTEN: EPHIE Position /
sahilmgandhi	18:6a4db94011d3	31533	#define USBD_GINTEN_EPHIE_Msk (0x1ul << USBD_GINTEN_EPHIE_Pos) /!< USBD GINTEN: EPHIE Mask /
sahilmgandhi	18:6a4db94011d3	31534
sahilmgandhi	18:6a4db94011d3	31535	#define USBD_GINTEN_EPIIE_Pos (10) /!< USBD GINTEN: EPIIE Position /
sahilmgandhi	18:6a4db94011d3	31536	#define USBD_GINTEN_EPIIE_Msk (0x1ul << USBD_GINTEN_EPIIE_Pos) /!< USBD GINTEN: EPIIE Mask /
sahilmgandhi	18:6a4db94011d3	31537
sahilmgandhi	18:6a4db94011d3	31538	#define USBD_GINTEN_EPJIE_Pos (11) /!< USBD GINTEN: EPJIE Position /
sahilmgandhi	18:6a4db94011d3	31539	#define USBD_GINTEN_EPJIE_Msk (0x1ul << USBD_GINTEN_EPJIE_Pos) /!< USBD GINTEN: EPJIE Mask /
sahilmgandhi	18:6a4db94011d3	31540
sahilmgandhi	18:6a4db94011d3	31541	#define USBD_GINTEN_EPKIE_Pos (12) /!< USBD GINTEN: EPKIE Position /
sahilmgandhi	18:6a4db94011d3	31542	#define USBD_GINTEN_EPKIE_Msk (0x1ul << USBD_GINTEN_EPKIE_Pos) /!< USBD GINTEN: EPKIE Mask /
sahilmgandhi	18:6a4db94011d3	31543
sahilmgandhi	18:6a4db94011d3	31544	#define USBD_GINTEN_EPLIE_Pos (13) /!< USBD GINTEN: EPLIE Position /
sahilmgandhi	18:6a4db94011d3	31545	#define USBD_GINTEN_EPLIE_Msk (0x1ul << USBD_GINTEN_EPLIE_Pos) /!< USBD GINTEN: EPLIE Mask /
sahilmgandhi	18:6a4db94011d3	31546
sahilmgandhi	18:6a4db94011d3	31547	#define USBD_BUSINTSTS_SOFIF_Pos (0) /!< USBD BUSINTSTS: SOFIF Position /
sahilmgandhi	18:6a4db94011d3	31548	#define USBD_BUSINTSTS_SOFIF_Msk (0x1ul << USBD_BUSINTSTS_SOFIF_Pos) /!< USBD BUSINTSTS: SOFIF Mask /
sahilmgandhi	18:6a4db94011d3	31549
sahilmgandhi	18:6a4db94011d3	31550	#define USBD_BUSINTSTS_RSTIF_Pos (1) /!< USBD BUSINTSTS: RSTIF Position /
sahilmgandhi	18:6a4db94011d3	31551	#define USBD_BUSINTSTS_RSTIF_Msk (0x1ul << USBD_BUSINTSTS_RSTIF_Pos) /!< USBD BUSINTSTS: RSTIF Mask /
sahilmgandhi	18:6a4db94011d3	31552
sahilmgandhi	18:6a4db94011d3	31553	#define USBD_BUSINTSTS_RESUMEIF_Pos (2) /!< USBD BUSINTSTS: RESUMEIF Position /
sahilmgandhi	18:6a4db94011d3	31554	#define USBD_BUSINTSTS_RESUMEIF_Msk (0x1ul << USBD_BUSINTSTS_RESUMEIF_Pos) /!< USBD BUSINTSTS: RESUMEIF Mask /
sahilmgandhi	18:6a4db94011d3	31555
sahilmgandhi	18:6a4db94011d3	31556	#define USBD_BUSINTSTS_SUSPENDIF_Pos (3) /!< USBD BUSINTSTS: SUSPENDIF Position /
sahilmgandhi	18:6a4db94011d3	31557	#define USBD_BUSINTSTS_SUSPENDIF_Msk (0x1ul << USBD_BUSINTSTS_SUSPENDIF_Pos) /!< USBD BUSINTSTS: SUSPENDIF Mask /
sahilmgandhi	18:6a4db94011d3	31558
sahilmgandhi	18:6a4db94011d3	31559	#define USBD_BUSINTSTS_HISPDIF_Pos (4) /!< USBD BUSINTSTS: HISPDIF Position /
sahilmgandhi	18:6a4db94011d3	31560	#define USBD_BUSINTSTS_HISPDIF_Msk (0x1ul << USBD_BUSINTSTS_HISPDIF_Pos) /!< USBD BUSINTSTS: HISPDIF Mask /
sahilmgandhi	18:6a4db94011d3	31561
sahilmgandhi	18:6a4db94011d3	31562	#define USBD_BUSINTSTS_DMADONEIF_Pos (5) /!< USBD BUSINTSTS: DMADONEIF Position /
sahilmgandhi	18:6a4db94011d3	31563	#define USBD_BUSINTSTS_DMADONEIF_Msk (0x1ul << USBD_BUSINTSTS_DMADONEIF_Pos) /!< USBD BUSINTSTS: DMADONEIF Mask /
sahilmgandhi	18:6a4db94011d3	31564
sahilmgandhi	18:6a4db94011d3	31565	#define USBD_BUSINTSTS_PHYCLKVLDIF_Pos (6) /!< USBD BUSINTSTS: PHYCLKVLDIF Position /
sahilmgandhi	18:6a4db94011d3	31566	#define USBD_BUSINTSTS_PHYCLKVLDIF_Msk (0x1ul << USBD_BUSINTSTS_PHYCLKVLDIF_Pos) /!< USBD BUSINTSTS: PHYCLKVLDIF Mask /
sahilmgandhi	18:6a4db94011d3	31567
sahilmgandhi	18:6a4db94011d3	31568	#define USBD_BUSINTSTS_VBUSDETIF_Pos (8) /!< USBD BUSINTSTS: VBUSDETIF Position /
sahilmgandhi	18:6a4db94011d3	31569	#define USBD_BUSINTSTS_VBUSDETIF_Msk (0x1ul << USBD_BUSINTSTS_VBUSDETIF_Pos) /!< USBD BUSINTSTS: VBUSDETIF Mask /
sahilmgandhi	18:6a4db94011d3	31570
sahilmgandhi	18:6a4db94011d3	31571	#define USBD_BUSINTEN_SOFIEN_Pos (0) /!< USBD BUSINTEN: SOFIEN Position /
sahilmgandhi	18:6a4db94011d3	31572	#define USBD_BUSINTEN_SOFIEN_Msk (0x1ul << USBD_BUSINTEN_SOFIEN_Pos) /!< USBD BUSINTEN: SOFIEN Mask /
sahilmgandhi	18:6a4db94011d3	31573
sahilmgandhi	18:6a4db94011d3	31574	#define USBD_BUSINTEN_RSTIEN_Pos (1) /!< USBD BUSINTEN: RSTIEN Position /
sahilmgandhi	18:6a4db94011d3	31575	#define USBD_BUSINTEN_RSTIEN_Msk (0x1ul << USBD_BUSINTEN_RSTIEN_Pos) /!< USBD BUSINTEN: RSTIEN Mask /
sahilmgandhi	18:6a4db94011d3	31576
sahilmgandhi	18:6a4db94011d3	31577	#define USBD_BUSINTEN_RESUMEIEN_Pos (2) /!< USBD BUSINTEN: RESUMEIEN Position /
sahilmgandhi	18:6a4db94011d3	31578	#define USBD_BUSINTEN_RESUMEIEN_Msk (0x1ul << USBD_BUSINTEN_RESUMEIEN_Pos) /!< USBD BUSINTEN: RESUMEIEN Mask /
sahilmgandhi	18:6a4db94011d3	31579
sahilmgandhi	18:6a4db94011d3	31580	#define USBD_BUSINTEN_SUSPENDIEN_Pos (3) /!< USBD BUSINTEN: SUSPENDIEN Position /
sahilmgandhi	18:6a4db94011d3	31581	#define USBD_BUSINTEN_SUSPENDIEN_Msk (0x1ul << USBD_BUSINTEN_SUSPENDIEN_Pos) /!< USBD BUSINTEN: SUSPENDIEN Mask /
sahilmgandhi	18:6a4db94011d3	31582
sahilmgandhi	18:6a4db94011d3	31583	#define USBD_BUSINTEN_HISPDIEN_Pos (4) /!< USBD BUSINTEN: HISPDIEN Position /
sahilmgandhi	18:6a4db94011d3	31584	#define USBD_BUSINTEN_HISPDIEN_Msk (0x1ul << USBD_BUSINTEN_HISPDIEN_Pos) /!< USBD BUSINTEN: HISPDIEN Mask /
sahilmgandhi	18:6a4db94011d3	31585
sahilmgandhi	18:6a4db94011d3	31586	#define USBD_BUSINTEN_DMADONEIEN_Pos (5) /!< USBD BUSINTEN: DMADONEIEN Position /
sahilmgandhi	18:6a4db94011d3	31587	#define USBD_BUSINTEN_DMADONEIEN_Msk (0x1ul << USBD_BUSINTEN_DMADONEIEN_Pos) /!< USBD BUSINTEN: DMADONEIEN Mask /
sahilmgandhi	18:6a4db94011d3	31588
sahilmgandhi	18:6a4db94011d3	31589	#define USBD_BUSINTEN_PHYCLKVLDIEN_Pos (6) /!< USBD BUSINTEN: PHYCLKVLDIEN Position /
sahilmgandhi	18:6a4db94011d3	31590	#define USBD_BUSINTEN_PHYCLKVLDIEN_Msk (0x1ul << USBD_BUSINTEN_PHYCLKVLDIEN_Pos) /!< USBD BUSINTEN: PHYCLKVLDIEN Mask /
sahilmgandhi	18:6a4db94011d3	31591
sahilmgandhi	18:6a4db94011d3	31592	#define USBD_BUSINTEN_VBUSDETIEN_Pos (8) /!< USBD BUSINTEN: VBUSDETIEN Position /
sahilmgandhi	18:6a4db94011d3	31593	#define USBD_BUSINTEN_VBUSDETIEN_Msk (0x1ul << USBD_BUSINTEN_VBUSDETIEN_Pos) /!< USBD BUSINTEN: VBUSDETIEN Mask /
sahilmgandhi	18:6a4db94011d3	31594
sahilmgandhi	18:6a4db94011d3	31595	#define USBD_OPER_RESUMEEN_Pos (0) /!< USBD OPER: RESUMEEN Position /
sahilmgandhi	18:6a4db94011d3	31596	#define USBD_OPER_RESUMEEN_Msk (0x1ul << USBD_OPER_RESUMEEN_Pos) /!< USBD OPER: RESUMEEN Mask /
sahilmgandhi	18:6a4db94011d3	31597
sahilmgandhi	18:6a4db94011d3	31598	#define USBD_OPER_HISPDEN_Pos (1) /!< USBD OPER: HISPDEN Position /
sahilmgandhi	18:6a4db94011d3	31599	#define USBD_OPER_HISPDEN_Msk (0x1ul << USBD_OPER_HISPDEN_Pos) /!< USBD OPER: HISPDEN Mask /
sahilmgandhi	18:6a4db94011d3	31600
sahilmgandhi	18:6a4db94011d3	31601	#define USBD_OPER_CURSPD_Pos (2) /!< USBD OPER: CURSPD Position /
sahilmgandhi	18:6a4db94011d3	31602	#define USBD_OPER_CURSPD_Msk (0x1ul << USBD_OPER_CURSPD_Pos) /!< USBD OPER: CURSPD Mask /
sahilmgandhi	18:6a4db94011d3	31603
sahilmgandhi	18:6a4db94011d3	31604	#define USBD_FRAMECNT_MFRAMECNT_Pos (0) /!< USBD FRAMECNT: MFRAMECNT Position /
sahilmgandhi	18:6a4db94011d3	31605	#define USBD_FRAMECNT_MFRAMECNT_Msk (0x7ul << USBD_FRAMECNT_MFRAMECNT_Pos) /!< USBD FRAMECNT: MFRAMECNT Mask /
sahilmgandhi	18:6a4db94011d3	31606
sahilmgandhi	18:6a4db94011d3	31607	#define USBD_FRAMECNT_FRAMECNT_Pos (3) /!< USBD FRAMECNT: FRAMECNT Position /
sahilmgandhi	18:6a4db94011d3	31608	#define USBD_FRAMECNT_FRAMECNT_Msk (0x7fful << USBD_FRAMECNT_FRAMECNT_Pos) /!< USBD FRAMECNT: FRAMECNT Mask /
sahilmgandhi	18:6a4db94011d3	31609
sahilmgandhi	18:6a4db94011d3	31610	#define USBD_FADDR_FADDR_Pos (0) /!< USBD FADDR: FADDR Position /
sahilmgandhi	18:6a4db94011d3	31611	#define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /!< USBD FADDR: FADDR Mask /
sahilmgandhi	18:6a4db94011d3	31612
sahilmgandhi	18:6a4db94011d3	31613	#define USBD_TEST_TESTMODE_Pos (0) /!< USBD TEST: TESTMODE Position /
sahilmgandhi	18:6a4db94011d3	31614	#define USBD_TEST_TESTMODE_Msk (0x7ul << USBD_TEST_TESTMODE_Pos) /!< USBD TEST: TESTMODE Mask /
sahilmgandhi	18:6a4db94011d3	31615
sahilmgandhi	18:6a4db94011d3	31616	#define USBD_CEPDAT_DAT_Pos (0) /!< USBD CEPDAT: DAT Position /
sahilmgandhi	18:6a4db94011d3	31617	#define USBD_CEPDAT_DAT_Msk (0xfffffffful << USBD_CEPDAT_DAT_Pos) /!< USBD CEPDAT: DAT Mask /
sahilmgandhi	18:6a4db94011d3	31618
sahilmgandhi	18:6a4db94011d3	31619	#define USBD_CEPCTL_NAKCLR_Pos (0) /!< USBD CEPCTL: NAKCLR Position /
sahilmgandhi	18:6a4db94011d3	31620	#define USBD_CEPCTL_NAKCLR_Msk (0x1ul << USBD_CEPCTL_NAKCLR_Pos) /!< USBD CEPCTL: NAKCLR Mask /
sahilmgandhi	18:6a4db94011d3	31621
sahilmgandhi	18:6a4db94011d3	31622	#define USBD_CEPCTL_STALLEN_Pos (1) /!< USBD CEPCTL: STALLEN Position /
sahilmgandhi	18:6a4db94011d3	31623	#define USBD_CEPCTL_STALLEN_Msk (0x1ul << USBD_CEPCTL_STALLEN_Pos) /!< USBD CEPCTL: STALLEN Mask /
sahilmgandhi	18:6a4db94011d3	31624
sahilmgandhi	18:6a4db94011d3	31625	#define USBD_CEPCTL_ZEROLEN_Pos (2) /!< USBD CEPCTL: ZEROLEN Position /
sahilmgandhi	18:6a4db94011d3	31626	#define USBD_CEPCTL_ZEROLEN_Msk (0x1ul << USBD_CEPCTL_ZEROLEN_Pos) /!< USBD CEPCTL: ZEROLEN Mask /
sahilmgandhi	18:6a4db94011d3	31627
sahilmgandhi	18:6a4db94011d3	31628	#define USBD_CEPCTL_FLUSH_Pos (3) /!< USBD CEPCTL: FLUSH Position /
sahilmgandhi	18:6a4db94011d3	31629	#define USBD_CEPCTL_FLUSH_Msk (0x1ul << USBD_CEPCTL_FLUSH_Pos) /!< USBD CEPCTL: FLUSH Mask /
sahilmgandhi	18:6a4db94011d3	31630
sahilmgandhi	18:6a4db94011d3	31631	#define USBD_CEPINTEN_SETUPTKIEN_Pos (0) /!< USBD CEPINTEN: SETUPTKIEN Position /
sahilmgandhi	18:6a4db94011d3	31632	#define USBD_CEPINTEN_SETUPTKIEN_Msk (0x1ul << USBD_CEPINTEN_SETUPTKIEN_Pos) /!< USBD CEPINTEN: SETUPTKIEN Mask /
sahilmgandhi	18:6a4db94011d3	31633
sahilmgandhi	18:6a4db94011d3	31634	#define USBD_CEPINTEN_SETUPPKIEN_Pos (1) /!< USBD CEPINTEN: SETUPPKIEN Position /
sahilmgandhi	18:6a4db94011d3	31635	#define USBD_CEPINTEN_SETUPPKIEN_Msk (0x1ul << USBD_CEPINTEN_SETUPPKIEN_Pos) /!< USBD CEPINTEN: SETUPPKIEN Mask /
sahilmgandhi	18:6a4db94011d3	31636
sahilmgandhi	18:6a4db94011d3	31637	#define USBD_CEPINTEN_OUTTKIEN_Pos (2) /!< USBD CEPINTEN: OUTTKIEN Position /
sahilmgandhi	18:6a4db94011d3	31638	#define USBD_CEPINTEN_OUTTKIEN_Msk (0x1ul << USBD_CEPINTEN_OUTTKIEN_Pos) /!< USBD CEPINTEN: OUTTKIEN Mask /
sahilmgandhi	18:6a4db94011d3	31639
sahilmgandhi	18:6a4db94011d3	31640	#define USBD_CEPINTEN_INTKIEN_Pos (3) /!< USBD CEPINTEN: INTKIEN Position /
sahilmgandhi	18:6a4db94011d3	31641	#define USBD_CEPINTEN_INTKIEN_Msk (0x1ul << USBD_CEPINTEN_INTKIEN_Pos) /!< USBD CEPINTEN: INTKIEN Mask /
sahilmgandhi	18:6a4db94011d3	31642
sahilmgandhi	18:6a4db94011d3	31643	#define USBD_CEPINTEN_PINGIEN_Pos (4) /!< USBD CEPINTEN: PINGIEN Position /
sahilmgandhi	18:6a4db94011d3	31644	#define USBD_CEPINTEN_PINGIEN_Msk (0x1ul << USBD_CEPINTEN_PINGIEN_Pos) /!< USBD CEPINTEN: PINGIEN Mask /
sahilmgandhi	18:6a4db94011d3	31645
sahilmgandhi	18:6a4db94011d3	31646	#define USBD_CEPINTEN_TXPKIEN_Pos (5) /!< USBD CEPINTEN: TXPKIEN Position /
sahilmgandhi	18:6a4db94011d3	31647	#define USBD_CEPINTEN_TXPKIEN_Msk (0x1ul << USBD_CEPINTEN_TXPKIEN_Pos) /!< USBD CEPINTEN: TXPKIEN Mask /
sahilmgandhi	18:6a4db94011d3	31648
sahilmgandhi	18:6a4db94011d3	31649	#define USBD_CEPINTEN_RXPKIEN_Pos (6) /!< USBD CEPINTEN: RXPKIEN Position /
sahilmgandhi	18:6a4db94011d3	31650	#define USBD_CEPINTEN_RXPKIEN_Msk (0x1ul << USBD_CEPINTEN_RXPKIEN_Pos) /!< USBD CEPINTEN: RXPKIEN Mask /
sahilmgandhi	18:6a4db94011d3	31651
sahilmgandhi	18:6a4db94011d3	31652	#define USBD_CEPINTEN_NAKIEN_Pos (7) /!< USBD CEPINTEN: NAKIEN Position /
sahilmgandhi	18:6a4db94011d3	31653	#define USBD_CEPINTEN_NAKIEN_Msk (0x1ul << USBD_CEPINTEN_NAKIEN_Pos) /!< USBD CEPINTEN: NAKIEN Mask /
sahilmgandhi	18:6a4db94011d3	31654
sahilmgandhi	18:6a4db94011d3	31655	#define USBD_CEPINTEN_STALLIEN_Pos (8) /!< USBD CEPINTEN: STALLIEN Position /
sahilmgandhi	18:6a4db94011d3	31656	#define USBD_CEPINTEN_STALLIEN_Msk (0x1ul << USBD_CEPINTEN_STALLIEN_Pos) /!< USBD CEPINTEN: STALLIEN Mask /
sahilmgandhi	18:6a4db94011d3	31657
sahilmgandhi	18:6a4db94011d3	31658	#define USBD_CEPINTEN_ERRIEN_Pos (9) /!< USBD CEPINTEN: ERRIEN Position /
sahilmgandhi	18:6a4db94011d3	31659	#define USBD_CEPINTEN_ERRIEN_Msk (0x1ul << USBD_CEPINTEN_ERRIEN_Pos) /!< USBD CEPINTEN: ERRIEN Mask /
sahilmgandhi	18:6a4db94011d3	31660
sahilmgandhi	18:6a4db94011d3	31661	#define USBD_CEPINTEN_STSDONEIEN_Pos (10) /!< USBD CEPINTEN: STSDONEIEN Position /
sahilmgandhi	18:6a4db94011d3	31662	#define USBD_CEPINTEN_STSDONEIEN_Msk (0x1ul << USBD_CEPINTEN_STSDONEIEN_Pos) /!< USBD CEPINTEN: STSDONEIEN Mask /
sahilmgandhi	18:6a4db94011d3	31663
sahilmgandhi	18:6a4db94011d3	31664	#define USBD_CEPINTEN_BUFFULLIEN_Pos (11) /!< USBD CEPINTEN: BUFFULLIEN Position /
sahilmgandhi	18:6a4db94011d3	31665	#define USBD_CEPINTEN_BUFFULLIEN_Msk (0x1ul << USBD_CEPINTEN_BUFFULLIEN_Pos) /!< USBD CEPINTEN: BUFFULLIEN Mask /
sahilmgandhi	18:6a4db94011d3	31666
sahilmgandhi	18:6a4db94011d3	31667	#define USBD_CEPINTEN_BUFEMPTYIEN_Pos (12) /!< USBD CEPINTEN: BUFEMPTYIEN Position /
sahilmgandhi	18:6a4db94011d3	31668	#define USBD_CEPINTEN_BUFEMPTYIEN_Msk (0x1ul << USBD_CEPINTEN_BUFEMPTYIEN_Pos) /!< USBD CEPINTEN: BUFEMPTYIEN Mask /
sahilmgandhi	18:6a4db94011d3	31669
sahilmgandhi	18:6a4db94011d3	31670	#define USBD_CEPINTSTS_SETUPTKIF_Pos (0) /!< USBD CEPINTSTS: SETUPTKIF Position /
sahilmgandhi	18:6a4db94011d3	31671	#define USBD_CEPINTSTS_SETUPTKIF_Msk (0x1ul << USBD_CEPINTSTS_SETUPTKIF_Pos) /!< USBD CEPINTSTS: SETUPTKIF Mask /
sahilmgandhi	18:6a4db94011d3	31672
sahilmgandhi	18:6a4db94011d3	31673	#define USBD_CEPINTSTS_SETUPPKIF_Pos (1) /!< USBD CEPINTSTS: SETUPPKIF Position /
sahilmgandhi	18:6a4db94011d3	31674	#define USBD_CEPINTSTS_SETUPPKIF_Msk (0x1ul << USBD_CEPINTSTS_SETUPPKIF_Pos) /!< USBD CEPINTSTS: SETUPPKIF Mask /
sahilmgandhi	18:6a4db94011d3	31675
sahilmgandhi	18:6a4db94011d3	31676	#define USBD_CEPINTSTS_OUTTKIF_Pos (2) /!< USBD CEPINTSTS: OUTTKIF Position /
sahilmgandhi	18:6a4db94011d3	31677	#define USBD_CEPINTSTS_OUTTKIF_Msk (0x1ul << USBD_CEPINTSTS_OUTTKIF_Pos) /!< USBD CEPINTSTS: OUTTKIF Mask /
sahilmgandhi	18:6a4db94011d3	31678
sahilmgandhi	18:6a4db94011d3	31679	#define USBD_CEPINTSTS_INTKIF_Pos (3) /!< USBD CEPINTSTS: INTKIF Position /
sahilmgandhi	18:6a4db94011d3	31680	#define USBD_CEPINTSTS_INTKIF_Msk (0x1ul << USBD_CEPINTSTS_INTKIF_Pos) /!< USBD CEPINTSTS: INTKIF Mask /
sahilmgandhi	18:6a4db94011d3	31681
sahilmgandhi	18:6a4db94011d3	31682	#define USBD_CEPINTSTS_PINGIF_Pos (4) /!< USBD CEPINTSTS: PINGIF Position /
sahilmgandhi	18:6a4db94011d3	31683	#define USBD_CEPINTSTS_PINGIF_Msk (0x1ul << USBD_CEPINTSTS_PINGIF_Pos) /!< USBD CEPINTSTS: PINGIF Mask /
sahilmgandhi	18:6a4db94011d3	31684
sahilmgandhi	18:6a4db94011d3	31685	#define USBD_CEPINTSTS_TXPKIF_Pos (5) /!< USBD CEPINTSTS: TXPKIF Position /
sahilmgandhi	18:6a4db94011d3	31686	#define USBD_CEPINTSTS_TXPKIF_Msk (0x1ul << USBD_CEPINTSTS_TXPKIF_Pos) /!< USBD CEPINTSTS: TXPKIF Mask /
sahilmgandhi	18:6a4db94011d3	31687
sahilmgandhi	18:6a4db94011d3	31688	#define USBD_CEPINTSTS_RXPKIF_Pos (6) /!< USBD CEPINTSTS: RXPKIF Position /
sahilmgandhi	18:6a4db94011d3	31689	#define USBD_CEPINTSTS_RXPKIF_Msk (0x1ul << USBD_CEPINTSTS_RXPKIF_Pos) /!< USBD CEPINTSTS: RXPKIF Mask /
sahilmgandhi	18:6a4db94011d3	31690
sahilmgandhi	18:6a4db94011d3	31691	#define USBD_CEPINTSTS_NAKIF_Pos (7) /!< USBD CEPINTSTS: NAKIF Position /
sahilmgandhi	18:6a4db94011d3	31692	#define USBD_CEPINTSTS_NAKIF_Msk (0x1ul << USBD_CEPINTSTS_NAKIF_Pos) /!< USBD CEPINTSTS: NAKIF Mask /
sahilmgandhi	18:6a4db94011d3	31693
sahilmgandhi	18:6a4db94011d3	31694	#define USBD_CEPINTSTS_STALLIF_Pos (8) /!< USBD CEPINTSTS: STALLIF Position /
sahilmgandhi	18:6a4db94011d3	31695	#define USBD_CEPINTSTS_STALLIF_Msk (0x1ul << USBD_CEPINTSTS_STALLIF_Pos) /!< USBD CEPINTSTS: STALLIF Mask /
sahilmgandhi	18:6a4db94011d3	31696
sahilmgandhi	18:6a4db94011d3	31697	#define USBD_CEPINTSTS_ERRIF_Pos (9) /!< USBD CEPINTSTS: ERRIF Position /
sahilmgandhi	18:6a4db94011d3	31698	#define USBD_CEPINTSTS_ERRIF_Msk (0x1ul << USBD_CEPINTSTS_ERRIF_Pos) /!< USBD CEPINTSTS: ERRIF Mask /
sahilmgandhi	18:6a4db94011d3	31699
sahilmgandhi	18:6a4db94011d3	31700	#define USBD_CEPINTSTS_STSDONEIF_Pos (10) /!< USBD CEPINTSTS: STSDONEIF Position /
sahilmgandhi	18:6a4db94011d3	31701	#define USBD_CEPINTSTS_STSDONEIF_Msk (0x1ul << USBD_CEPINTSTS_STSDONEIF_Pos) /!< USBD CEPINTSTS: STSDONEIF Mask /
sahilmgandhi	18:6a4db94011d3	31702
sahilmgandhi	18:6a4db94011d3	31703	#define USBD_CEPINTSTS_BUFFULLIF_Pos (11) /!< USBD CEPINTSTS: BUFFULLIF Position /
sahilmgandhi	18:6a4db94011d3	31704	#define USBD_CEPINTSTS_BUFFULLIF_Msk (0x1ul << USBD_CEPINTSTS_BUFFULLIF_Pos) /!< USBD CEPINTSTS: BUFFULLIF Mask /
sahilmgandhi	18:6a4db94011d3	31705
sahilmgandhi	18:6a4db94011d3	31706	#define USBD_CEPINTSTS_BUFEMPTYIF_Pos (12) /!< USBD CEPINTSTS: BUFEMPTYIF Position /
sahilmgandhi	18:6a4db94011d3	31707	#define USBD_CEPINTSTS_BUFEMPTYIF_Msk (0x1ul << USBD_CEPINTSTS_BUFEMPTYIF_Pos) /!< USBD CEPINTSTS: BUFEMPTYIF Mask /
sahilmgandhi	18:6a4db94011d3	31708
sahilmgandhi	18:6a4db94011d3	31709	#define USBD_CEPTXCNT_TXCNT_Pos (0) /!< USBD CEPTXCNT: TXCNT Position /
sahilmgandhi	18:6a4db94011d3	31710	#define USBD_CEPTXCNT_TXCNT_Msk (0xfful << USBD_CEPTXCNT_TXCNT_Pos) /!< USBD CEPTXCNT: TXCNT Mask /
sahilmgandhi	18:6a4db94011d3	31711
sahilmgandhi	18:6a4db94011d3	31712	#define USBD_CEPRXCNT_RXCNT_Pos (0) /!< USBD CEPRXCNT: RXCNT Position /
sahilmgandhi	18:6a4db94011d3	31713	#define USBD_CEPRXCNT_RXCNT_Msk (0xfful << USBD_CEPRXCNT_RXCNT_Pos) /!< USBD CEPRXCNT: RXCNT Mask /
sahilmgandhi	18:6a4db94011d3	31714
sahilmgandhi	18:6a4db94011d3	31715	#define USBD_CEPDATCNT_DATCNT_Pos (0) /!< USBD CEPDATCNT: DATCNT Position /
sahilmgandhi	18:6a4db94011d3	31716	#define USBD_CEPDATCNT_DATCNT_Msk (0xfffful << USBD_CEPDATCNT_DATCNT_Pos) /!< USBD CEPDATCNT: DATCNT Mask /
sahilmgandhi	18:6a4db94011d3	31717
sahilmgandhi	18:6a4db94011d3	31718	#define USBD_SETUP1_0_SETUP0_Pos (0) /!< USBD SETUP1_0: SETUP0 Position /
sahilmgandhi	18:6a4db94011d3	31719	#define USBD_SETUP1_0_SETUP0_Msk (0xfful << USBD_SETUP1_0_SETUP0_Pos) /!< USBD SETUP1_0: SETUP0 Mask /
sahilmgandhi	18:6a4db94011d3	31720
sahilmgandhi	18:6a4db94011d3	31721	#define USBD_SETUP1_0_SETUP1_Pos (8) /!< USBD SETUP1_0: SETUP1 Position /
sahilmgandhi	18:6a4db94011d3	31722	#define USBD_SETUP1_0_SETUP1_Msk (0xfful << USBD_SETUP1_0_SETUP1_Pos) /!< USBD SETUP1_0: SETUP1 Mask /
sahilmgandhi	18:6a4db94011d3	31723
sahilmgandhi	18:6a4db94011d3	31724	#define USBD_SETUP3_2_SETUP2_Pos (0) /!< USBD SETUP3_2: SETUP2 Position /
sahilmgandhi	18:6a4db94011d3	31725	#define USBD_SETUP3_2_SETUP2_Msk (0xfful << USBD_SETUP3_2_SETUP2_Pos) /!< USBD SETUP3_2: SETUP2 Mask /
sahilmgandhi	18:6a4db94011d3	31726
sahilmgandhi	18:6a4db94011d3	31727	#define USBD_SETUP3_2_SETUP3_Pos (8) /!< USBD SETUP3_2: SETUP3 Position /
sahilmgandhi	18:6a4db94011d3	31728	#define USBD_SETUP3_2_SETUP3_Msk (0xfful << USBD_SETUP3_2_SETUP3_Pos) /!< USBD SETUP3_2: SETUP3 Mask /
sahilmgandhi	18:6a4db94011d3	31729
sahilmgandhi	18:6a4db94011d3	31730	#define USBD_SETUP5_4_SETUP4_Pos (0) /!< USBD SETUP5_4: SETUP4 Position /
sahilmgandhi	18:6a4db94011d3	31731	#define USBD_SETUP5_4_SETUP4_Msk (0xfful << USBD_SETUP5_4_SETUP4_Pos) /!< USBD SETUP5_4: SETUP4 Mask /
sahilmgandhi	18:6a4db94011d3	31732
sahilmgandhi	18:6a4db94011d3	31733	#define USBD_SETUP5_4_SETUP5_Pos (8) /!< USBD SETUP5_4: SETUP5 Position /
sahilmgandhi	18:6a4db94011d3	31734	#define USBD_SETUP5_4_SETUP5_Msk (0xfful << USBD_SETUP5_4_SETUP5_Pos) /!< USBD SETUP5_4: SETUP5 Mask /
sahilmgandhi	18:6a4db94011d3	31735
sahilmgandhi	18:6a4db94011d3	31736	#define USBD_SETUP7_6_SETUP6_Pos (0) /!< USBD SETUP7_6: SETUP6 Position /
sahilmgandhi	18:6a4db94011d3	31737	#define USBD_SETUP7_6_SETUP6_Msk (0xfful << USBD_SETUP7_6_SETUP6_Pos) /!< USBD SETUP7_6: SETUP6 Mask /
sahilmgandhi	18:6a4db94011d3	31738
sahilmgandhi	18:6a4db94011d3	31739	#define USBD_SETUP7_6_SETUP7_Pos (8) /!< USBD SETUP7_6: SETUP7 Position /
sahilmgandhi	18:6a4db94011d3	31740	#define USBD_SETUP7_6_SETUP7_Msk (0xfful << USBD_SETUP7_6_SETUP7_Pos) /!< USBD SETUP7_6: SETUP7 Mask /
sahilmgandhi	18:6a4db94011d3	31741
sahilmgandhi	18:6a4db94011d3	31742	#define USBD_CEPBUFSTART_SADDR_Pos (0) /!< USBD CEPBUFSTART: SADDR Position /
sahilmgandhi	18:6a4db94011d3	31743	#define USBD_CEPBUFSTART_SADDR_Msk (0xffful << USBD_CEPBUFSTART_SADDR_Pos) /!< USBD CEPBUFSTART: SADDR Mask /
sahilmgandhi	18:6a4db94011d3	31744
sahilmgandhi	18:6a4db94011d3	31745	#define USBD_CEPBUFEND_EADDR_Pos (0) /!< USBD CEPBUFEND: EADDR Position /
sahilmgandhi	18:6a4db94011d3	31746	#define USBD_CEPBUFEND_EADDR_Msk (0xffful << USBD_CEPBUFEND_EADDR_Pos) /!< USBD CEPBUFEND: EADDR Mask /
sahilmgandhi	18:6a4db94011d3	31747
sahilmgandhi	18:6a4db94011d3	31748	#define USBD_DMACTL_EPNUM_Pos (0) /!< USBD DMACTL: EPNUM Position /
sahilmgandhi	18:6a4db94011d3	31749	#define USBD_DMACTL_EPNUM_Msk (0xful << USBD_DMACTL_EPNUM_Pos) /!< USBD DMACTL: EPNUM Mask /
sahilmgandhi	18:6a4db94011d3	31750
sahilmgandhi	18:6a4db94011d3	31751	#define USBD_DMACTL_DMARD_Pos (4) /!< USBD DMACTL: DMARD Position /
sahilmgandhi	18:6a4db94011d3	31752	#define USBD_DMACTL_DMARD_Msk (0x1ul << USBD_DMACTL_DMARD_Pos) /!< USBD DMACTL: DMARD Mask /
sahilmgandhi	18:6a4db94011d3	31753
sahilmgandhi	18:6a4db94011d3	31754	#define USBD_DMACTL_DMAEN_Pos (5) /!< USBD DMACTL: DMAEN Position /
sahilmgandhi	18:6a4db94011d3	31755	#define USBD_DMACTL_DMAEN_Msk (0x1ul << USBD_DMACTL_DMAEN_Pos) /!< USBD DMACTL: DMAEN Mask /
sahilmgandhi	18:6a4db94011d3	31756
sahilmgandhi	18:6a4db94011d3	31757	#define USBD_DMACTL_SGEN_Pos (6) /!< USBD DMACTL: SGEN Position /
sahilmgandhi	18:6a4db94011d3	31758	#define USBD_DMACTL_SGEN_Msk (0x1ul << USBD_DMACTL_SGEN_Pos) /!< USBD DMACTL: SGEN Mask /
sahilmgandhi	18:6a4db94011d3	31759
sahilmgandhi	18:6a4db94011d3	31760	#define USBD_DMACTL_DMARST_Pos (7) /!< USBD DMACTL: DMARST Position /
sahilmgandhi	18:6a4db94011d3	31761	#define USBD_DMACTL_DMARST_Msk (0x1ul << USBD_DMACTL_DMARST_Pos) /!< USBD DMACTL: DMARST Mask /
sahilmgandhi	18:6a4db94011d3	31762
sahilmgandhi	18:6a4db94011d3	31763	#define USBD_DMACNT_DMACNT_Pos (0) /!< USBD DMACNT: DMACNT Position /
sahilmgandhi	18:6a4db94011d3	31764	#define USBD_DMACNT_DMACNT_Msk (0xffffful << USBD_DMACNT_DMACNT_Pos) /!< USBD DMACNT: DMACNT Mask /
sahilmgandhi	18:6a4db94011d3	31765
sahilmgandhi	18:6a4db94011d3	31766	#define USBD_EPDAT_EPDAT_Pos (0) /!< USBD EPDAT: EPDAT Position /
sahilmgandhi	18:6a4db94011d3	31767	#define USBD_EPDAT_EPDAT_Msk (0xfffffffful << USBD_EPDAT_EPDAT_Pos) /!< USBD EPDAT: EPDAT Mask /
sahilmgandhi	18:6a4db94011d3	31768
sahilmgandhi	18:6a4db94011d3	31769	#define USBD_EPINTSTS_BUFFULLIF_Pos (0) /!< USBD EPINTSTS: BUFFULLIF Position /
sahilmgandhi	18:6a4db94011d3	31770	#define USBD_EPINTSTS_BUFFULLIF_Msk (0x1ul << USBD_EPINTSTS_BUFFULLIF_Pos) /!< USBD EPINTSTS: BUFFULLIF Mask /
sahilmgandhi	18:6a4db94011d3	31771
sahilmgandhi	18:6a4db94011d3	31772	#define USBD_EPINTSTS_BUFEMPTYIF_Pos (1) /!< USBD EPINTSTS: BUFEMPTYIF Position /
sahilmgandhi	18:6a4db94011d3	31773	#define USBD_EPINTSTS_BUFEMPTYIF_Msk (0x1ul << USBD_EPINTSTS_BUFEMPTYIF_Pos) /!< USBD EPINTSTS: BUFEMPTYIF Mask /
sahilmgandhi	18:6a4db94011d3	31774
sahilmgandhi	18:6a4db94011d3	31775	#define USBD_EPINTSTS_SHORTTXIF_Pos (2) /!< USBD EPINTSTS: SHORTTXIF Position /
sahilmgandhi	18:6a4db94011d3	31776	#define USBD_EPINTSTS_SHORTTXIF_Msk (0x1ul << USBD_EPINTSTS_SHORTTXIF_Pos) /!< USBD EPINTSTS: SHORTTXIF Mask /
sahilmgandhi	18:6a4db94011d3	31777
sahilmgandhi	18:6a4db94011d3	31778	#define USBD_EPINTSTS_TXPKIF_Pos (3) /!< USBD EPINTSTS: TXPKIF Position /
sahilmgandhi	18:6a4db94011d3	31779	#define USBD_EPINTSTS_TXPKIF_Msk (0x1ul << USBD_EPINTSTS_TXPKIF_Pos) /!< USBD EPINTSTS: TXPKIF Mask /
sahilmgandhi	18:6a4db94011d3	31780
sahilmgandhi	18:6a4db94011d3	31781	#define USBD_EPINTSTS_RXPKIF_Pos (4) /!< USBD EPINTSTS: RXPKIF Position /
sahilmgandhi	18:6a4db94011d3	31782	#define USBD_EPINTSTS_RXPKIF_Msk (0x1ul << USBD_EPINTSTS_RXPKIF_Pos) /!< USBD EPINTSTS: RXPKIF Mask /
sahilmgandhi	18:6a4db94011d3	31783
sahilmgandhi	18:6a4db94011d3	31784	#define USBD_EPINTSTS_OUTTKIF_Pos (5) /!< USBD EPINTSTS: OUTTKIF Position /
sahilmgandhi	18:6a4db94011d3	31785	#define USBD_EPINTSTS_OUTTKIF_Msk (0x1ul << USBD_EPINTSTS_OUTTKIF_Pos) /!< USBD EPINTSTS: OUTTKIF Mask /
sahilmgandhi	18:6a4db94011d3	31786
sahilmgandhi	18:6a4db94011d3	31787	#define USBD_EPINTSTS_INTKIF_Pos (6) /!< USBD EPINTSTS: INTKIF Position /
sahilmgandhi	18:6a4db94011d3	31788	#define USBD_EPINTSTS_INTKIF_Msk (0x1ul << USBD_EPINTSTS_INTKIF_Pos) /!< USBD EPINTSTS: INTKIF Mask /
sahilmgandhi	18:6a4db94011d3	31789
sahilmgandhi	18:6a4db94011d3	31790	#define USBD_EPINTSTS_PINGIF_Pos (7) /!< USBD EPINTSTS: PINGIF Position /
sahilmgandhi	18:6a4db94011d3	31791	#define USBD_EPINTSTS_PINGIF_Msk (0x1ul << USBD_EPINTSTS_PINGIF_Pos) /!< USBD EPINTSTS: PINGIF Mask /
sahilmgandhi	18:6a4db94011d3	31792
sahilmgandhi	18:6a4db94011d3	31793	#define USBD_EPINTSTS_NAKIF_Pos (8) /!< USBD EPINTSTS: NAKIF Position /
sahilmgandhi	18:6a4db94011d3	31794	#define USBD_EPINTSTS_NAKIF_Msk (0x1ul << USBD_EPINTSTS_NAKIF_Pos) /!< USBD EPINTSTS: NAKIF Mask /
sahilmgandhi	18:6a4db94011d3	31795
sahilmgandhi	18:6a4db94011d3	31796	#define USBD_EPINTSTS_STALLIF_Pos (9) /!< USBD EPINTSTS: STALLIF Position /
sahilmgandhi	18:6a4db94011d3	31797	#define USBD_EPINTSTS_STALLIF_Msk (0x1ul << USBD_EPINTSTS_STALLIF_Pos) /!< USBD EPINTSTS: STALLIF Mask /
sahilmgandhi	18:6a4db94011d3	31798
sahilmgandhi	18:6a4db94011d3	31799	#define USBD_EPINTSTS_NYETIF_Pos (10) /!< USBD EPINTSTS: NYETIF Position /
sahilmgandhi	18:6a4db94011d3	31800	#define USBD_EPINTSTS_NYETIF_Msk (0x1ul << USBD_EPINTSTS_NYETIF_Pos) /!< USBD EPINTSTS: NYETIF Mask /
sahilmgandhi	18:6a4db94011d3	31801
sahilmgandhi	18:6a4db94011d3	31802	#define USBD_EPINTSTS_ERRIF_Pos (11) /!< USBD EPINTSTS: ERRIF Position /
sahilmgandhi	18:6a4db94011d3	31803	#define USBD_EPINTSTS_ERRIF_Msk (0x1ul << USBD_EPINTSTS_ERRIF_Pos) /!< USBD EPINTSTS: ERRIF Mask /
sahilmgandhi	18:6a4db94011d3	31804
sahilmgandhi	18:6a4db94011d3	31805	#define USBD_EPINTSTS_SHORTRXIF_Pos (12) /!< USBD EPINTSTS: SHORTRXIF Position /
sahilmgandhi	18:6a4db94011d3	31806	#define USBD_EPINTSTS_SHORTRXIF_Msk (0x1ul << USBD_EPINTSTS_SHORTRXIF_Pos) /!< USBD EPINTSTS: SHORTRXIF Mask /
sahilmgandhi	18:6a4db94011d3	31807
sahilmgandhi	18:6a4db94011d3	31808	#define USBD_EPINTEN_BUFFULLIEN_Pos (0) /!< USBD EPINTEN: BUFFULLIEN Position /
sahilmgandhi	18:6a4db94011d3	31809	#define USBD_EPINTEN_BUFFULLIEN_Msk (0x1ul << USBD_EPINTEN_BUFFULLIEN_Pos) /!< USBD EPINTEN: BUFFULLIEN Mask /
sahilmgandhi	18:6a4db94011d3	31810
sahilmgandhi	18:6a4db94011d3	31811	#define USBD_EPINTEN_BUFEMPTYIEN_Pos (1) /!< USBD EPINTEN: BUFEMPTYIEN Position /
sahilmgandhi	18:6a4db94011d3	31812	#define USBD_EPINTEN_BUFEMPTYIEN_Msk (0x1ul << USBD_EPINTEN_BUFEMPTYIEN_Pos) /!< USBD EPINTEN: BUFEMPTYIEN Mask /
sahilmgandhi	18:6a4db94011d3	31813
sahilmgandhi	18:6a4db94011d3	31814	#define USBD_EPINTEN_SHORTTXIEN_Pos (2) /!< USBD EPINTEN: SHORTTXIEN Position /
sahilmgandhi	18:6a4db94011d3	31815	#define USBD_EPINTEN_SHORTTXIEN_Msk (0x1ul << USBD_EPINTEN_SHORTTXIEN_Pos) /!< USBD EPINTEN: SHORTTXIEN Mask /
sahilmgandhi	18:6a4db94011d3	31816
sahilmgandhi	18:6a4db94011d3	31817	#define USBD_EPINTEN_TXPKIEN_Pos (3) /!< USBD EPINTEN: TXPKIEN Position /
sahilmgandhi	18:6a4db94011d3	31818	#define USBD_EPINTEN_TXPKIEN_Msk (0x1ul << USBD_EPINTEN_TXPKIEN_Pos) /!< USBD EPINTEN: TXPKIEN Mask /
sahilmgandhi	18:6a4db94011d3	31819
sahilmgandhi	18:6a4db94011d3	31820	#define USBD_EPINTEN_RXPKIEN_Pos (4) /!< USBD EPINTEN: RXPKIEN Position /
sahilmgandhi	18:6a4db94011d3	31821	#define USBD_EPINTEN_RXPKIEN_Msk (0x1ul << USBD_EPINTEN_RXPKIEN_Pos) /!< USBD EPINTEN: RXPKIEN Mask /
sahilmgandhi	18:6a4db94011d3	31822
sahilmgandhi	18:6a4db94011d3	31823	#define USBD_EPINTEN_OUTTKIEN_Pos (5) /!< USBD EPINTEN: OUTTKIEN Position /
sahilmgandhi	18:6a4db94011d3	31824	#define USBD_EPINTEN_OUTTKIEN_Msk (0x1ul << USBD_EPINTEN_OUTTKIEN_Pos) /!< USBD EPINTEN: OUTTKIEN Mask /
sahilmgandhi	18:6a4db94011d3	31825
sahilmgandhi	18:6a4db94011d3	31826	#define USBD_EPINTEN_INTKIEN_Pos (6) /!< USBD EPINTEN: INTKIEN Position /
sahilmgandhi	18:6a4db94011d3	31827	#define USBD_EPINTEN_INTKIEN_Msk (0x1ul << USBD_EPINTEN_INTKIEN_Pos) /!< USBD EPINTEN: INTKIEN Mask /
sahilmgandhi	18:6a4db94011d3	31828
sahilmgandhi	18:6a4db94011d3	31829	#define USBD_EPINTEN_PINGIEN_Pos (7) /!< USBD EPINTEN: PINGIEN Position /
sahilmgandhi	18:6a4db94011d3	31830	#define USBD_EPINTEN_PINGIEN_Msk (0x1ul << USBD_EPINTEN_PINGIEN_Pos) /!< USBD EPINTEN: PINGIEN Mask /
sahilmgandhi	18:6a4db94011d3	31831
sahilmgandhi	18:6a4db94011d3	31832	#define USBD_EPINTEN_NAKIEN_Pos (8) /!< USBD EPINTEN: NAKIEN Position /
sahilmgandhi	18:6a4db94011d3	31833	#define USBD_EPINTEN_NAKIEN_Msk (0x1ul << USBD_EPINTEN_NAKIEN_Pos) /!< USBD EPINTEN: NAKIEN Mask /
sahilmgandhi	18:6a4db94011d3	31834
sahilmgandhi	18:6a4db94011d3	31835	#define USBD_EPINTEN_STALLIEN_Pos (9) /!< USBD EPINTEN: STALLIEN Position /
sahilmgandhi	18:6a4db94011d3	31836	#define USBD_EPINTEN_STALLIEN_Msk (0x1ul << USBD_EPINTEN_STALLIEN_Pos) /!< USBD EPINTEN: STALLIEN Mask /
sahilmgandhi	18:6a4db94011d3	31837
sahilmgandhi	18:6a4db94011d3	31838	#define USBD_EPINTEN_NYETIEN_Pos (10) /!< USBD EPINTEN: NYETIEN Position /
sahilmgandhi	18:6a4db94011d3	31839	#define USBD_EPINTEN_NYETIEN_Msk (0x1ul << USBD_EPINTEN_NYETIEN_Pos) /!< USBD EPINTEN: NYETIEN Mask /
sahilmgandhi	18:6a4db94011d3	31840
sahilmgandhi	18:6a4db94011d3	31841	#define USBD_EPINTEN_ERRIEN_Pos (11) /!< USBD EPINTEN: ERRIEN Position /
sahilmgandhi	18:6a4db94011d3	31842	#define USBD_EPINTEN_ERRIEN_Msk (0x1ul << USBD_EPINTEN_ERRIEN_Pos) /!< USBD EPINTEN: ERRIEN Mask /
sahilmgandhi	18:6a4db94011d3	31843
sahilmgandhi	18:6a4db94011d3	31844	#define USBD_EPINTEN_SHORTRXIEN_Pos (12) /!< USBD EPINTEN: SHORTRXIEN Position /
sahilmgandhi	18:6a4db94011d3	31845	#define USBD_EPINTEN_SHORTRXIEN_Msk (0x1ul << USBD_EPINTEN_SHORTRXIEN_Pos) /!< USBD EPINTEN: SHORTRXIEN Mask /
sahilmgandhi	18:6a4db94011d3	31846
sahilmgandhi	18:6a4db94011d3	31847	#define USBD_EPDATCNT_DATCNT_Pos (0) /!< USBD EPDATCNT: DATCNT Position /
sahilmgandhi	18:6a4db94011d3	31848	#define USBD_EPDATCNT_DATCNT_Msk (0xfffful << USBD_EPDATCNT_DATCNT_Pos) /!< USBD EPDATCNT: DATCNT Mask /
sahilmgandhi	18:6a4db94011d3	31849
sahilmgandhi	18:6a4db94011d3	31850	#define USBD_EPDATCNT_DMALOOP_Pos (16) /!< USBD EPDATCNT: DMALOOP Position /
sahilmgandhi	18:6a4db94011d3	31851	#define USBD_EPDATCNT_DMALOOP_Msk (0x7ffful << USBD_EPDATCNT_DMALOOP_Pos) /!< USBD EPDATCNT: DMALOOP Mask /
sahilmgandhi	18:6a4db94011d3	31852
sahilmgandhi	18:6a4db94011d3	31853	#define USBD_EPRSPCTL_FLUSH_Pos (0) /!< USBD EPRSPCTL: FLUSH Position /
sahilmgandhi	18:6a4db94011d3	31854	#define USBD_EPRSPCTL_FLUSH_Msk (0x1ul << USBD_EPRSPCTL_FLUSH_Pos) /!< USBD EPRSPCTL: FLUSH Mask /
sahilmgandhi	18:6a4db94011d3	31855
sahilmgandhi	18:6a4db94011d3	31856	#define USBD_EPRSPCTL_MODE_Pos (1) /!< USBD EPRSPCTL: MODE Position /
sahilmgandhi	18:6a4db94011d3	31857	#define USBD_EPRSPCTL_MODE_Msk (0x3ul << USBD_EPRSPCTL_MODE_Pos) /!< USBD EPRSPCTL: MODE Mask /
sahilmgandhi	18:6a4db94011d3	31858
sahilmgandhi	18:6a4db94011d3	31859	#define USBD_EPRSPCTL_TOGGLE_Pos (3) /!< USBD EPRSPCTL: TOGGLE Position /
sahilmgandhi	18:6a4db94011d3	31860	#define USBD_EPRSPCTL_TOGGLE_Msk (0x1ul << USBD_EPRSPCTL_TOGGLE_Pos) /!< USBD EPRSPCTL: TOGGLE Mask /
sahilmgandhi	18:6a4db94011d3	31861
sahilmgandhi	18:6a4db94011d3	31862	#define USBD_EPRSPCTL_HALT_Pos (4) /!< USBD EPRSPCTL: HALT Position /
sahilmgandhi	18:6a4db94011d3	31863	#define USBD_EPRSPCTL_HALT_Msk (0x1ul << USBD_EPRSPCTL_HALT_Pos) /!< USBD EPRSPCTL: HALT Mask /
sahilmgandhi	18:6a4db94011d3	31864
sahilmgandhi	18:6a4db94011d3	31865	#define USBD_EPRSPCTL_ZEROLEN_Pos (5) /!< USBD EPRSPCTL: ZEROLEN Position /
sahilmgandhi	18:6a4db94011d3	31866	#define USBD_EPRSPCTL_ZEROLEN_Msk (0x1ul << USBD_EPRSPCTL_ZEROLEN_Pos) /!< USBD EPRSPCTL: ZEROLEN Mask /
sahilmgandhi	18:6a4db94011d3	31867
sahilmgandhi	18:6a4db94011d3	31868	#define USBD_EPRSPCTL_SHORTTXEN_Pos (6) /!< USBD EPRSPCTL: SHORTTXEN Position /
sahilmgandhi	18:6a4db94011d3	31869	#define USBD_EPRSPCTL_SHORTTXEN_Msk (0x1ul << USBD_EPRSPCTL_SHORTTXEN_Pos) /!< USBD EPRSPCTL: SHORTTXEN Mask /
sahilmgandhi	18:6a4db94011d3	31870
sahilmgandhi	18:6a4db94011d3	31871	#define USBD_EPRSPCTL_DISBUF_Pos (7) /!< USBD EPRSPCTL: DISBUF Position /
sahilmgandhi	18:6a4db94011d3	31872	#define USBD_EPRSPCTL_DISBUF_Msk (0x1ul << USBD_EPRSPCTL_DISBUF_Pos) /!< USBD EPRSPCTL: DISBUF Mask /
sahilmgandhi	18:6a4db94011d3	31873
sahilmgandhi	18:6a4db94011d3	31874	#define USBD_EPMPS_EPMPS_Pos (0) /!< USBD EPMPS: EPMPS Position /
sahilmgandhi	18:6a4db94011d3	31875	#define USBD_EPMPS_EPMPS_Msk (0x7fful << USBD_EPMPS_EPMPS_Pos) /!< USBD EPMPS: EPMPS Mask /
sahilmgandhi	18:6a4db94011d3	31876
sahilmgandhi	18:6a4db94011d3	31877	#define USBD_EPTXCNT_TXCNT_Pos (0) /!< USBD EPTXCNT: TXCNT Position /
sahilmgandhi	18:6a4db94011d3	31878	#define USBD_EPTXCNT_TXCNT_Msk (0x7fful << USBD_EPTXCNT_TXCNT_Pos) /!< USBD EPTXCNT: TXCNT Mask /
sahilmgandhi	18:6a4db94011d3	31879
sahilmgandhi	18:6a4db94011d3	31880	#define USBD_EPCFG_EPEN_Pos (0) /!< USBD EPCFG: EPEN Position /
sahilmgandhi	18:6a4db94011d3	31881	#define USBD_EPCFG_EPEN_Msk (0x1ul << USBD_EPCFG_EPEN_Pos) /!< USBD EPCFG: EPEN Mask /
sahilmgandhi	18:6a4db94011d3	31882
sahilmgandhi	18:6a4db94011d3	31883	#define USBD_EPCFG_EPTYPE_Pos (1) /!< USBD EPCFG: EPTYPE Position /
sahilmgandhi	18:6a4db94011d3	31884	#define USBD_EPCFG_EPTYPE_Msk (0x3ul << USBD_EPCFG_EPTYPE_Pos) /!< USBD EPCFG: EPTYPE Mask /
sahilmgandhi	18:6a4db94011d3	31885
sahilmgandhi	18:6a4db94011d3	31886	#define USBD_EPCFG_EPDIR_Pos (3) /!< USBD EPCFG: EPDIR Position /
sahilmgandhi	18:6a4db94011d3	31887	#define USBD_EPCFG_EPDIR_Msk (0x1ul << USBD_EPCFG_EPDIR_Pos) /!< USBD EPCFG: EPDIR Mask /
sahilmgandhi	18:6a4db94011d3	31888
sahilmgandhi	18:6a4db94011d3	31889	#define USBD_EPCFG_EPNUM_Pos (4) /!< USBD EPCFG: EPNUM Position /
sahilmgandhi	18:6a4db94011d3	31890	#define USBD_EPCFG_EPNUM_Msk (0xful << USBD_EPCFG_EPNUM_Pos) /!< USBD EPCFG: EPNUM Mask /
sahilmgandhi	18:6a4db94011d3	31891
sahilmgandhi	18:6a4db94011d3	31892	#define USBD_EPBUFSTART_SADDR_Pos (0) /!< USBD EPBUFSTART: SADDR Position /
sahilmgandhi	18:6a4db94011d3	31893	#define USBD_EPBUFSTART_SADDR_Msk (0xffful << USBD_EPBUFSTART_SADDR_Pos) /!< USBD EPBUFSTART: SADDR Mask /
sahilmgandhi	18:6a4db94011d3	31894
sahilmgandhi	18:6a4db94011d3	31895	#define USBD_EPBUFEND_EADDR_Pos (0) /!< USBD EPBUFEND: EADDR Position /
sahilmgandhi	18:6a4db94011d3	31896	#define USBD_EPBUFEND_EADDR_Msk (0xffful << USBD_EPBUFEND_EADDR_Pos) /!< USBD EPBUFEND: EADDR Mask /
sahilmgandhi	18:6a4db94011d3	31897
sahilmgandhi	18:6a4db94011d3	31898	#define USBD_DMAADDR_DMAADDR_Pos (0) /!< USBD DMAADDR: DMAADDR Position /
sahilmgandhi	18:6a4db94011d3	31899	#define USBD_DMAADDR_DMAADDR_Msk (0xfffffffful << USBD_DMAADDR_DMAADDR_Pos) /!< USBD DMAADDR: DMAADDR Mask /
sahilmgandhi	18:6a4db94011d3	31900
sahilmgandhi	18:6a4db94011d3	31901	#define USBD_PHYCTL_DPPUEN_Pos (8) /!< USBD PHYCTL: DPPUEN Position /
sahilmgandhi	18:6a4db94011d3	31902	#define USBD_PHYCTL_DPPUEN_Msk (0x1ul << USBD_PHYCTL_DPPUEN_Pos) /!< USBD PHYCTL: DPPUEN Mask /
sahilmgandhi	18:6a4db94011d3	31903
sahilmgandhi	18:6a4db94011d3	31904	#define USBD_PHYCTL_PHYEN_Pos (9) /!< USBD PHYCTL: PHYEN Position /
sahilmgandhi	18:6a4db94011d3	31905	#define USBD_PHYCTL_PHYEN_Msk (0x1ul << USBD_PHYCTL_PHYEN_Pos) /!< USBD PHYCTL: PHYEN Mask /
sahilmgandhi	18:6a4db94011d3	31906
sahilmgandhi	18:6a4db94011d3	31907	#define USBD_PHYCTL_WKEN_Pos (24) /!< USBD PHYCTL: WKEN Position /
sahilmgandhi	18:6a4db94011d3	31908	#define USBD_PHYCTL_WKEN_Msk (0x1ul << USBD_PHYCTL_WKEN_Pos) /!< USBD PHYCTL: WKEN Mask /
sahilmgandhi	18:6a4db94011d3	31909
sahilmgandhi	18:6a4db94011d3	31910	#define USBD_PHYCTL_VBUSDET_Pos (31) /!< USBD PHYCTL: VBUSDET Position /
sahilmgandhi	18:6a4db94011d3	31911	#define USBD_PHYCTL_VBUSDET_Msk (0x1ul << USBD_PHYCTL_VBUSDET_Pos) /!< USBD PHYCTL: VBUSDET Mask /
sahilmgandhi	18:6a4db94011d3	31912
sahilmgandhi	18:6a4db94011d3	31913	/*@}/ /* USBD_CONST */
sahilmgandhi	18:6a4db94011d3	31914	/*@}/ /* end of USBD register group */
sahilmgandhi	18:6a4db94011d3	31915
sahilmgandhi	18:6a4db94011d3	31916
sahilmgandhi	18:6a4db94011d3	31917	/---------------------- Watch Dog Timer Controller -------------------------/
sahilmgandhi	18:6a4db94011d3	31918	/**
sahilmgandhi	18:6a4db94011d3	31919	@addtogroup WDT Watch Dog Timer Controller(WDT)
sahilmgandhi	18:6a4db94011d3	31920	Memory Mapped Structure for WDT Controller
sahilmgandhi	18:6a4db94011d3	31921	@{ */
sahilmgandhi	18:6a4db94011d3	31922
sahilmgandhi	18:6a4db94011d3	31923	typedef struct {
sahilmgandhi	18:6a4db94011d3	31924
sahilmgandhi	18:6a4db94011d3	31925
sahilmgandhi	18:6a4db94011d3	31926	/**
sahilmgandhi	18:6a4db94011d3	31927	* CTL
sahilmgandhi	18:6a4db94011d3	31928	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	31929	* Offset: 0x00 Watchdog Timer Control Register
sahilmgandhi	18:6a4db94011d3	31930	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	31931	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	31932	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	31933	* \|[0] \|RSTCNT \|Clear Watchdog Timer (Write Protect)
sahilmgandhi	18:6a4db94011d3	31934	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	31935	* \| \| \|1 = Reset the internal 18-bit WDT counter.
sahilmgandhi	18:6a4db94011d3	31936	* \| \| \|Note: This bit will be automatically cleared by hardware.
sahilmgandhi	18:6a4db94011d3	31937	* \|[1] \|RSTEN \|Watchdog Timer Reset Enable Control (Write Protect)
sahilmgandhi	18:6a4db94011d3	31938	* \| \| \|Setting this bit will enable the Watchdog Timer time-out reset function If the WDT counter value has not been cleared after the specific WDT reset delay period expires.
sahilmgandhi	18:6a4db94011d3	31939	* \| \| \|0 = Watchdog Timer time-out reset function Disabled.
sahilmgandhi	18:6a4db94011d3	31940	* \| \| \|1 = Watchdog Timer time-out reset function Enabled.
sahilmgandhi	18:6a4db94011d3	31941	* \|[2] \|RSTF \|Watchdog Timer Reset Flag
sahilmgandhi	18:6a4db94011d3	31942	* \| \| \|This bit indicates the system has been reset by WDT time-out reset or not.
sahilmgandhi	18:6a4db94011d3	31943	* \| \| \|0 = Watchdog Timer time-out reset did not occur.
sahilmgandhi	18:6a4db94011d3	31944	* \| \| \|1 = Watchdog Timer time-out reset occurred.
sahilmgandhi	18:6a4db94011d3	31945	* \| \| \|Note: This bit is cleared by writing 1 to this bit.
sahilmgandhi	18:6a4db94011d3	31946	* \|[3] \|IF \|Watchdog Timer Interrupt Flag
sahilmgandhi	18:6a4db94011d3	31947	* \| \| \|This bit will set to 1 while WDT counter value reaches the selected WDT time-out interval
sahilmgandhi	18:6a4db94011d3	31948	* \| \| \|0 = Watchdog Timer time-out interrupt did not occur.
sahilmgandhi	18:6a4db94011d3	31949	* \| \| \|1 = Watchdog Timer time-out interrupt occurred.
sahilmgandhi	18:6a4db94011d3	31950	* \| \| \|Note: This bit is cleared by writing 1 to this bit.
sahilmgandhi	18:6a4db94011d3	31951	* \|[4] \|WKEN \|Watchdog Timer Wake-Up Function Enable Control (Write Protect)
sahilmgandhi	18:6a4db94011d3	31952	* \| \| \|If this bit is set to 1, while WDT interrupt flag (WDT_CTL[3] IF) is generated to 1 and INTEN (WDT_CTL[6] WDT interrupt enable) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
sahilmgandhi	18:6a4db94011d3	31953	* \| \| \|0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated.
sahilmgandhi	18:6a4db94011d3	31954	* \| \| \|1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated.
sahilmgandhi	18:6a4db94011d3	31955	* \| \| \|Note: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillator.
sahilmgandhi	18:6a4db94011d3	31956	* \|[5] \|WKF \|Watchdog Timer Wake-Up Flag
sahilmgandhi	18:6a4db94011d3	31957	* \| \| \|This bit indicates the interrupt wake-up flag status of WDT
sahilmgandhi	18:6a4db94011d3	31958	* \| \| \|0 = Watchdog Timer does not cause chip wake-up.
sahilmgandhi	18:6a4db94011d3	31959	* \| \| \|1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated.
sahilmgandhi	18:6a4db94011d3	31960	* \| \| \|Note: This bit is cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	31961	* \|[6] \|INTEN \|Watchdog Timer Interrupt Enable Control (Write Protect)
sahilmgandhi	18:6a4db94011d3	31962	* \| \| \|If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
sahilmgandhi	18:6a4db94011d3	31963	* \| \| \|0 = Watchdog Timer interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	31964	* \| \| \|1 = Watchdog Timer interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	31965	* \|[7] \|WDTEN \|Watchdog Timer Enable Control (Write Protect)
sahilmgandhi	18:6a4db94011d3	31966	* \| \| \|0 = Watchdog Timer Disabled (This action will reset the internal counter).
sahilmgandhi	18:6a4db94011d3	31967	* \| \| \|1 = Watchdog Timer Enabled.
sahilmgandhi	18:6a4db94011d3	31968	* \| \| \|Note: If CWDTEN (Config0[31] watchdog enable) bit is set to 0, this bit is forced as 1 and software cannot change this bit to 0.
sahilmgandhi	18:6a4db94011d3	31969	* \|[8:10] \|TOUTSEL \|Watchdog Timer Time-Out Interval Selection (Write Protect)
sahilmgandhi	18:6a4db94011d3	31970	* \| \| \|These three bits select the time-out interval period for the Watchdog Timer.
sahilmgandhi	18:6a4db94011d3	31971	* \| \| \|000 = 2^4 * TWDT.
sahilmgandhi	18:6a4db94011d3	31972	* \| \| \|001 = 2^6 * TWDT.
sahilmgandhi	18:6a4db94011d3	31973	* \| \| \|010 = 2^8 * TWDT.
sahilmgandhi	18:6a4db94011d3	31974	* \| \| \|011 = 2^10 * TWDT.
sahilmgandhi	18:6a4db94011d3	31975	* \| \| \|100 = 2^12 * TWDT.
sahilmgandhi	18:6a4db94011d3	31976	* \| \| \|101 = 2^14 * TWDT.
sahilmgandhi	18:6a4db94011d3	31977	* \| \| \|110 = 2^16 * TWDT.
sahilmgandhi	18:6a4db94011d3	31978	* \| \| \|111 = 2^18 * TWDT.
sahilmgandhi	18:6a4db94011d3	31979	* \|[31] \|ICEDEBUG \|ICE Debug Mode Acknowledge Disable Control (Write Protect)
sahilmgandhi	18:6a4db94011d3	31980	* \| \| \|0 = ICE debug mode acknowledgement affects Watchdog Timer counting.
sahilmgandhi	18:6a4db94011d3	31981	* \| \| \|Watchdog Timer counter will be held while CPU is held by ICE.
sahilmgandhi	18:6a4db94011d3	31982	* \| \| \|1 = ICE debug mode acknowledgement Disabled.
sahilmgandhi	18:6a4db94011d3	31983	* \| \| \|Watchdog Timer counter will keep going no matter CPU is held by ICE or not.
sahilmgandhi	18:6a4db94011d3	31984	*/
sahilmgandhi	18:6a4db94011d3	31985	__IO uint32_t CTL;
sahilmgandhi	18:6a4db94011d3	31986
sahilmgandhi	18:6a4db94011d3	31987	/**
sahilmgandhi	18:6a4db94011d3	31988	* ALTCTL
sahilmgandhi	18:6a4db94011d3	31989	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	31990	* Offset: 0x04 Watchdog Timer Alternative Control Register
sahilmgandhi	18:6a4db94011d3	31991	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	31992	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	31993	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	31994	* \|[0:1] \|RSTDSEL \|Watchdog Timer Reset Delay Selection (Write Protect)
sahilmgandhi	18:6a4db94011d3	31995	* \| \| \|When WDT time-out happened, software has a time named WDT reset delay period to clear WDT counter to prevent WDT time-out reset happened.
sahilmgandhi	18:6a4db94011d3	31996	* \| \| \|Software can select a suitable value of WDT reset delay period for different WDT time-out period.
sahilmgandhi	18:6a4db94011d3	31997	* \| \| \|00 = Watchdog Timer reset delay period is (1024+2) * WDT_CLK.
sahilmgandhi	18:6a4db94011d3	31998	* \| \| \|01 = Watchdog Timer reset delay period is (128+2) * WDT_CLK.
sahilmgandhi	18:6a4db94011d3	31999	* \| \| \|10 = Watchdog Timer reset delay period is (16+2) * WDT_CLK.
sahilmgandhi	18:6a4db94011d3	32000	* \| \| \|11 = Watchdog Timer reset delay period is (1+2) * WDT_CLK.
sahilmgandhi	18:6a4db94011d3	32001	* \| \| \|Note: This register will be reset to 0 if WDT time-out reset happened
sahilmgandhi	18:6a4db94011d3	32002	*/
sahilmgandhi	18:6a4db94011d3	32003	__IO uint32_t ALTCTL;
sahilmgandhi	18:6a4db94011d3	32004
sahilmgandhi	18:6a4db94011d3	32005	} WDT_T;
sahilmgandhi	18:6a4db94011d3	32006
sahilmgandhi	18:6a4db94011d3	32007	/**
sahilmgandhi	18:6a4db94011d3	32008	@addtogroup WDT_CONST WDT Bit Field Definition
sahilmgandhi	18:6a4db94011d3	32009	Constant Definitions for WDT Controller
sahilmgandhi	18:6a4db94011d3	32010	@{ */
sahilmgandhi	18:6a4db94011d3	32011
sahilmgandhi	18:6a4db94011d3	32012	#define WDT_CTL_RSTCNT_Pos (0) /!< WDT CTL: RSTCNT Position /
sahilmgandhi	18:6a4db94011d3	32013	#define WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos) /!< WDT CTL: RSTCNT Mask /
sahilmgandhi	18:6a4db94011d3	32014
sahilmgandhi	18:6a4db94011d3	32015	#define WDT_CTL_RSTEN_Pos (1) /!< WDT CTL: RSTEN Position /
sahilmgandhi	18:6a4db94011d3	32016	#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /!< WDT CTL: RSTEN Mask /
sahilmgandhi	18:6a4db94011d3	32017
sahilmgandhi	18:6a4db94011d3	32018	#define WDT_CTL_RSTF_Pos (2) /!< WDT CTL: RSTF Position /
sahilmgandhi	18:6a4db94011d3	32019	#define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /!< WDT CTL: RSTF Mask /
sahilmgandhi	18:6a4db94011d3	32020
sahilmgandhi	18:6a4db94011d3	32021	#define WDT_CTL_IF_Pos (3) /!< WDT CTL: IF Position /
sahilmgandhi	18:6a4db94011d3	32022	#define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /!< WDT CTL: IF Mask /
sahilmgandhi	18:6a4db94011d3	32023
sahilmgandhi	18:6a4db94011d3	32024	#define WDT_CTL_WKEN_Pos (4) /!< WDT CTL: WKEN Position /
sahilmgandhi	18:6a4db94011d3	32025	#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /!< WDT CTL: WKEN Mask /
sahilmgandhi	18:6a4db94011d3	32026
sahilmgandhi	18:6a4db94011d3	32027	#define WDT_CTL_WKF_Pos (5) /!< WDT CTL: WKF Position /
sahilmgandhi	18:6a4db94011d3	32028	#define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /!< WDT CTL: WKF Mask /
sahilmgandhi	18:6a4db94011d3	32029
sahilmgandhi	18:6a4db94011d3	32030	#define WDT_CTL_INTEN_Pos (6) /!< WDT CTL: INTEN Position /
sahilmgandhi	18:6a4db94011d3	32031	#define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /!< WDT CTL: INTEN Mask /
sahilmgandhi	18:6a4db94011d3	32032
sahilmgandhi	18:6a4db94011d3	32033	#define WDT_CTL_WDTEN_Pos (7) /!< WDT CTL: WDTEN Position /
sahilmgandhi	18:6a4db94011d3	32034	#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /!< WDT CTL: WDTEN Mask /
sahilmgandhi	18:6a4db94011d3	32035
sahilmgandhi	18:6a4db94011d3	32036	#define WDT_CTL_TOUTSEL_Pos (8) /!< WDT CTL: TOUTSEL Position /
sahilmgandhi	18:6a4db94011d3	32037	#define WDT_CTL_TOUTSEL_Msk (0x7ul << WDT_CTL_TOUTSEL_Pos) /!< WDT CTL: TOUTSEL Mask /
sahilmgandhi	18:6a4db94011d3	32038
sahilmgandhi	18:6a4db94011d3	32039	#define WDT_CTL_ICEDEBUG_Pos (31) /!< WDT CTL: ICEDEBUG Position /
sahilmgandhi	18:6a4db94011d3	32040	#define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /!< WDT CTL: ICEDEBUG Mask /
sahilmgandhi	18:6a4db94011d3	32041
sahilmgandhi	18:6a4db94011d3	32042	#define WDT_ALTCTL_RSTDSEL_Pos (0) /!< WDT ALTCTL: RSTDSEL Position /
sahilmgandhi	18:6a4db94011d3	32043	#define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /!< WDT ALTCTL: RSTDSEL Mask /
sahilmgandhi	18:6a4db94011d3	32044
sahilmgandhi	18:6a4db94011d3	32045	/*@}/ /* WDT_CONST */
sahilmgandhi	18:6a4db94011d3	32046	/*@}/ /* end of WDT register group */
sahilmgandhi	18:6a4db94011d3	32047
sahilmgandhi	18:6a4db94011d3	32048
sahilmgandhi	18:6a4db94011d3	32049	/---------------------- Window Watchdog Timer -------------------------/
sahilmgandhi	18:6a4db94011d3	32050	/**
sahilmgandhi	18:6a4db94011d3	32051	@addtogroup WWDT Window Watchdog Timer(WWDT)
sahilmgandhi	18:6a4db94011d3	32052	Memory Mapped Structure for WWDT Controller
sahilmgandhi	18:6a4db94011d3	32053	@{ */
sahilmgandhi	18:6a4db94011d3	32054
sahilmgandhi	18:6a4db94011d3	32055	typedef struct {
sahilmgandhi	18:6a4db94011d3	32056
sahilmgandhi	18:6a4db94011d3	32057
sahilmgandhi	18:6a4db94011d3	32058	/**
sahilmgandhi	18:6a4db94011d3	32059	* RLDCNT
sahilmgandhi	18:6a4db94011d3	32060	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	32061	* Offset: 0x00 Window Watchdog Timer Reload Counter Register
sahilmgandhi	18:6a4db94011d3	32062	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	32063	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	32064	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	32065	* \|[0:31] \|RLDCNT \|WWDT Reload Counter Bit
sahilmgandhi	18:6a4db94011d3	32066	* \| \| \|Writing 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F.
sahilmgandhi	18:6a4db94011d3	32067	* \| \| \|Note: Software can only write RLDCNT to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.
sahilmgandhi	18:6a4db94011d3	32068	* \| \| \|If software writes RLDCNT when current WWDT counter value is larger than CMPDAT, WWDT reset signal will generate immediately.
sahilmgandhi	18:6a4db94011d3	32069	*/
sahilmgandhi	18:6a4db94011d3	32070	__O uint32_t RLDCNT;
sahilmgandhi	18:6a4db94011d3	32071
sahilmgandhi	18:6a4db94011d3	32072	/**
sahilmgandhi	18:6a4db94011d3	32073	* CTL
sahilmgandhi	18:6a4db94011d3	32074	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	32075	* Offset: 0x04 Window Watchdog Timer Control Register
sahilmgandhi	18:6a4db94011d3	32076	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	32077	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	32078	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	32079	* \|[0] \|WWDTEN \|WWDT Enable Control
sahilmgandhi	18:6a4db94011d3	32080	* \| \| \|Set this bit to enable Window Watchdog Timer counter counting.
sahilmgandhi	18:6a4db94011d3	32081	* \| \| \|0 = Window Watchdog Timer counter is stopped.
sahilmgandhi	18:6a4db94011d3	32082	* \| \| \|1 = Window Watchdog Timer counter is starting counting.
sahilmgandhi	18:6a4db94011d3	32083	* \|[1] \|INTEN \|WWDT Interrupt Enable Control
sahilmgandhi	18:6a4db94011d3	32084	* \| \| \|If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.
sahilmgandhi	18:6a4db94011d3	32085	* \| \| \|0 = WWDT counter compare match interrupt Disabled.
sahilmgandhi	18:6a4db94011d3	32086	* \| \| \|1 = WWDT counter compare match interrupt Enabled.
sahilmgandhi	18:6a4db94011d3	32087	* \|[8:11] \|PSCSEL \|WWDT Counter Prescale Period Selection
sahilmgandhi	18:6a4db94011d3	32088	* \| \| \|0000 = Pre-scale is 1; Max time-out period is 1 * 64 * TWWDT.
sahilmgandhi	18:6a4db94011d3	32089	* \| \| \|0001 = Pre-scale is 2; Max time-out period is 2 * 64 * TWWDT.
sahilmgandhi	18:6a4db94011d3	32090	* \| \| \|0010 = Pre-scale is 4; Max time-out period is 4 * 64 * TWWDT.
sahilmgandhi	18:6a4db94011d3	32091	* \| \| \|0011 = Pre-scale is 8; Max time-out period is 8 * 64 * TWWDT.
sahilmgandhi	18:6a4db94011d3	32092	* \| \| \|0100 = Pre-scale is 16; Max time-out period is 16 * 64 * TWWDT.
sahilmgandhi	18:6a4db94011d3	32093	* \| \| \|0101 = Pre-scale is 32; Max time-out period is 32 * 64 * TWWDT.
sahilmgandhi	18:6a4db94011d3	32094	* \| \| \|0110 = Pre-scale is 64; Max time-out period is 64 * 64 * TWWDT.
sahilmgandhi	18:6a4db94011d3	32095	* \| \| \|0111 = Pre-scale is 128; Max time-out period is 128 * 64 * TWWDT.
sahilmgandhi	18:6a4db94011d3	32096	* \| \| \|1000 = Pre-scale is 192; Max time-out period is 192 * 64 * TWWDT.
sahilmgandhi	18:6a4db94011d3	32097	* \| \| \|1001 = Pre-scale is 256; Max time-out period is 256 * 64 * TWWDT.
sahilmgandhi	18:6a4db94011d3	32098	* \| \| \|1010 = Pre-scale is 384; Max time-out period is 384 * 64 * TWWDT.
sahilmgandhi	18:6a4db94011d3	32099	* \| \| \|1011 = Pre-scale is 512; Max time-out period is 512 * 64 * TWWDT.
sahilmgandhi	18:6a4db94011d3	32100	* \| \| \|1100 = Pre-scale is 768; Max time-out period is 768 * 64 * TWWDT.
sahilmgandhi	18:6a4db94011d3	32101	* \| \| \|1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * TWWDT.
sahilmgandhi	18:6a4db94011d3	32102	* \| \| \|1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * TWWDT.
sahilmgandhi	18:6a4db94011d3	32103	* \| \| \|1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * TWWDT.
sahilmgandhi	18:6a4db94011d3	32104	* \|[16:21] \|CMPDAT \|WWDT Window Compare Bits
sahilmgandhi	18:6a4db94011d3	32105	* \| \| \|Set this register to adjust the valid reload window.
sahilmgandhi	18:6a4db94011d3	32106	* \| \| \|Note: Software can only write RLDCNT to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.
sahilmgandhi	18:6a4db94011d3	32107	* \| \| \|If Software writes RLDCNT when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
sahilmgandhi	18:6a4db94011d3	32108	* \|[31] \|ICEDEBUG \|ICE Debug Mode Acknowledge Disable Control
sahilmgandhi	18:6a4db94011d3	32109	* \| \| \|0 = ICE debug mode acknowledgement effects WWDT counting.
sahilmgandhi	18:6a4db94011d3	32110	* \| \| \|WWDT down counter will be held while CPU is held by ICE.
sahilmgandhi	18:6a4db94011d3	32111	* \| \| \|1 = ICE debug mode acknowledgement Disabled.
sahilmgandhi	18:6a4db94011d3	32112	* \| \| \|WWDT down counter will keep going no matter CPU is held by ICE or not.
sahilmgandhi	18:6a4db94011d3	32113	*/
sahilmgandhi	18:6a4db94011d3	32114	__IO uint32_t CTL;
sahilmgandhi	18:6a4db94011d3	32115
sahilmgandhi	18:6a4db94011d3	32116	/**
sahilmgandhi	18:6a4db94011d3	32117	* STATUS
sahilmgandhi	18:6a4db94011d3	32118	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	32119	* Offset: 0x08 Window Watchdog Timer Status Register
sahilmgandhi	18:6a4db94011d3	32120	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	32121	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	32122	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	32123	* \|[0] \|WWDTIF \|WWDT Compare Match Interrupt Flag
sahilmgandhi	18:6a4db94011d3	32124	* \| \| \|This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT value.
sahilmgandhi	18:6a4db94011d3	32125	* \| \| \|0 = No effect.
sahilmgandhi	18:6a4db94011d3	32126	* \| \| \|1 = WWDT counter value matches CMPDAT value.
sahilmgandhi	18:6a4db94011d3	32127	* \| \| \|Note: This bit is cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	32128	* \|[1] \|WWDTRF \|WWDT Timer-Out Reset Flag
sahilmgandhi	18:6a4db94011d3	32129	* \| \| \|This bit indicates the system has been reset by WWDT time-out reset or not.
sahilmgandhi	18:6a4db94011d3	32130	* \| \| \|0 = WWDT time-out reset did not occur.
sahilmgandhi	18:6a4db94011d3	32131	* \| \| \|1 = WWDT time-out reset occurred.
sahilmgandhi	18:6a4db94011d3	32132	* \| \| \|Note: This bit is cleared by writing 1 to it.
sahilmgandhi	18:6a4db94011d3	32133	*/
sahilmgandhi	18:6a4db94011d3	32134	__IO uint32_t STATUS;
sahilmgandhi	18:6a4db94011d3	32135
sahilmgandhi	18:6a4db94011d3	32136	/**
sahilmgandhi	18:6a4db94011d3	32137	* CNT
sahilmgandhi	18:6a4db94011d3	32138	* ===================================================================================================
sahilmgandhi	18:6a4db94011d3	32139	* Offset: 0x0C Window Watchdog Timer Counter Value Register
sahilmgandhi	18:6a4db94011d3	32140	* ---------------------------------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	32141	* \|Bits \|Field \|Descriptions
sahilmgandhi	18:6a4db94011d3	32142	* \| :----: \| :----: \| :---- \|
sahilmgandhi	18:6a4db94011d3	32143	* \|[0:5] \|CNTDAT \|WWDT Counter Value
sahilmgandhi	18:6a4db94011d3	32144	* \| \| \|This register reflects the current WWDT counter value and is read only.
sahilmgandhi	18:6a4db94011d3	32145	*/
sahilmgandhi	18:6a4db94011d3	32146	__I uint32_t CNT;
sahilmgandhi	18:6a4db94011d3	32147
sahilmgandhi	18:6a4db94011d3	32148	} WWDT_T;
sahilmgandhi	18:6a4db94011d3	32149
sahilmgandhi	18:6a4db94011d3	32150	/**
sahilmgandhi	18:6a4db94011d3	32151	@addtogroup WWDT_CONST WWDT Bit Field Definition
sahilmgandhi	18:6a4db94011d3	32152	Constant Definitions for WWDT Controller
sahilmgandhi	18:6a4db94011d3	32153	@{ */
sahilmgandhi	18:6a4db94011d3	32154
sahilmgandhi	18:6a4db94011d3	32155	#define WWDT_RLDCNT_RLDCNT_Pos (0) /!< WWDT RLDCNT: RLDCNT Position /
sahilmgandhi	18:6a4db94011d3	32156	#define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) /!< WWDT RLDCNT: RLDCNT Mask /
sahilmgandhi	18:6a4db94011d3	32157
sahilmgandhi	18:6a4db94011d3	32158	#define WWDT_CTL_WWDTEN_Pos (0) /!< WWDT CTL: WWDTEN Position /
sahilmgandhi	18:6a4db94011d3	32159	#define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /!< WWDT CTL: WWDTEN Mask /
sahilmgandhi	18:6a4db94011d3	32160
sahilmgandhi	18:6a4db94011d3	32161	#define WWDT_CTL_INTEN_Pos (1) /!< WWDT CTL: INTEN Position /
sahilmgandhi	18:6a4db94011d3	32162	#define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /!< WWDT CTL: INTEN Mask /
sahilmgandhi	18:6a4db94011d3	32163
sahilmgandhi	18:6a4db94011d3	32164	#define WWDT_CTL_PSCSEL_Pos (8) /!< WWDT CTL: PSCSEL Position /
sahilmgandhi	18:6a4db94011d3	32165	#define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /!< WWDT CTL: PSCSEL Mask /
sahilmgandhi	18:6a4db94011d3	32166
sahilmgandhi	18:6a4db94011d3	32167	#define WWDT_CTL_CMPDAT_Pos (16) /!< WWDT CTL: CMPDAT Position /
sahilmgandhi	18:6a4db94011d3	32168	#define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /!< WWDT CTL: CMPDAT Mask /
sahilmgandhi	18:6a4db94011d3	32169
sahilmgandhi	18:6a4db94011d3	32170	#define WWDT_CTL_ICEDEBUG_Pos (31) /!< WWDT CTL: ICEDEBUG Position /
sahilmgandhi	18:6a4db94011d3	32171	#define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /!< WWDT CTL: ICEDEBUG Mask /
sahilmgandhi	18:6a4db94011d3	32172
sahilmgandhi	18:6a4db94011d3	32173	#define WWDT_STATUS_WWDTIF_Pos (0) /!< WWDT STATUS: WWDTIF Position /
sahilmgandhi	18:6a4db94011d3	32174	#define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /!< WWDT STATUS: WWDTIF Mask /
sahilmgandhi	18:6a4db94011d3	32175
sahilmgandhi	18:6a4db94011d3	32176	#define WWDT_STATUS_WWDTRF_Pos (1) /!< WWDT STATUS: WWDTRF Position /
sahilmgandhi	18:6a4db94011d3	32177	#define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /!< WWDT STATUS: WWDTRF Mask /
sahilmgandhi	18:6a4db94011d3	32178
sahilmgandhi	18:6a4db94011d3	32179	#define WWDT_CNT_CNTDAT_Pos (0) /!< WWDT CNT: CNTDAT Position /
sahilmgandhi	18:6a4db94011d3	32180	#define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /!< WWDT CNT: CNTDAT Mask /
sahilmgandhi	18:6a4db94011d3	32181
sahilmgandhi	18:6a4db94011d3	32182	/*@}/ /* WWDT_CONST */
sahilmgandhi	18:6a4db94011d3	32183	/*@}/ /* end of WWDT register group */
sahilmgandhi	18:6a4db94011d3	32184
sahilmgandhi	18:6a4db94011d3	32185	#if defined ( __CC_ARM )
sahilmgandhi	18:6a4db94011d3	32186	#pragma no_anon_unions
sahilmgandhi	18:6a4db94011d3	32187	#endif
sahilmgandhi	18:6a4db94011d3	32188
sahilmgandhi	18:6a4db94011d3	32189
sahilmgandhi	18:6a4db94011d3	32190	/@}/ /* end of group NUC472_442_Peripherals */
sahilmgandhi	18:6a4db94011d3	32191
sahilmgandhi	18:6a4db94011d3	32192	/** @addtogroup NUC472_442_PERIPHERAL_MEM_MAP NUC472/NUC442 Peripheral Memory Base
sahilmgandhi	18:6a4db94011d3	32193	Memory Mapped Structure for NUC472/NUC442 Peripheral
sahilmgandhi	18:6a4db94011d3	32194	@{
sahilmgandhi	18:6a4db94011d3	32195	*/
sahilmgandhi	18:6a4db94011d3	32196	/* Peripheral and SRAM base address */
sahilmgandhi	18:6a4db94011d3	32197	#define FLASH_BASE ((uint32_t)0x00000000) /!< Flash base address /
sahilmgandhi	18:6a4db94011d3	32198	#define SRAM_BASE ((uint32_t)0x20000000) /!< SRAM Base Address /
sahilmgandhi	18:6a4db94011d3	32199	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral Base Address /
sahilmgandhi	18:6a4db94011d3	32200	#define AHBPERIPH_BASE PERIPH_BASE /!< AHB Base Address /
sahilmgandhi	18:6a4db94011d3	32201	#define APBPERIPH_BASE (PERIPH_BASE + 0x00040000) /!< APB Base Address /
sahilmgandhi	18:6a4db94011d3	32202
sahilmgandhi	18:6a4db94011d3	32203	/!< AHB peripherals /
sahilmgandhi	18:6a4db94011d3	32204	#define SYS_BASE (AHBPERIPH_BASE + 0x00000)
sahilmgandhi	18:6a4db94011d3	32205	#define CLK_BASE (AHBPERIPH_BASE + 0x00200)
sahilmgandhi	18:6a4db94011d3	32206	#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000)
sahilmgandhi	18:6a4db94011d3	32207	#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040)
sahilmgandhi	18:6a4db94011d3	32208	#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080)
sahilmgandhi	18:6a4db94011d3	32209	#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0)
sahilmgandhi	18:6a4db94011d3	32210	#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100)
sahilmgandhi	18:6a4db94011d3	32211	#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140)
sahilmgandhi	18:6a4db94011d3	32212	#define GPIOG_BASE (AHBPERIPH_BASE + 0x04180)
sahilmgandhi	18:6a4db94011d3	32213	#define GPIOH_BASE (AHBPERIPH_BASE + 0x041C0)
sahilmgandhi	18:6a4db94011d3	32214	#define GPIOI_BASE (AHBPERIPH_BASE + 0x04200)
sahilmgandhi	18:6a4db94011d3	32215	#define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440)
sahilmgandhi	18:6a4db94011d3	32216	#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800)
sahilmgandhi	18:6a4db94011d3	32217	#define PDMA_BASE (AHBPERIPH_BASE + 0x08000)
sahilmgandhi	18:6a4db94011d3	32218	#define USBH_BASE (AHBPERIPH_BASE + 0x09000)
sahilmgandhi	18:6a4db94011d3	32219	#define EMAC_BASE (AHBPERIPH_BASE + 0x0B000)
sahilmgandhi	18:6a4db94011d3	32220	#define FMC_BASE (AHBPERIPH_BASE + 0x0C000)
sahilmgandhi	18:6a4db94011d3	32221	#define SD_BASE (AHBPERIPH_BASE + 0x0D000)
sahilmgandhi	18:6a4db94011d3	32222	#define EBI_BASE (AHBPERIPH_BASE + 0x10000)
sahilmgandhi	18:6a4db94011d3	32223	#define UDC20_BASE (AHBPERIPH_BASE + 0x19000)
sahilmgandhi	18:6a4db94011d3	32224	#define CAP_BASE (AHBPERIPH_BASE + 0x30000)
sahilmgandhi	18:6a4db94011d3	32225	#define CRC_BASE (AHBPERIPH_BASE + 0x31000)
sahilmgandhi	18:6a4db94011d3	32226	#define TAMPER_BASE (AHBPERIPH_BASE + 0xE1000)
sahilmgandhi	18:6a4db94011d3	32227
sahilmgandhi	18:6a4db94011d3	32228	/!< APB2 peripherals /
sahilmgandhi	18:6a4db94011d3	32229	#define WDT_BASE (APBPERIPH_BASE + 0x00000)
sahilmgandhi	18:6a4db94011d3	32230	#define WWDT_BASE (APBPERIPH_BASE + 0x00100)
sahilmgandhi	18:6a4db94011d3	32231	#define OPA_BASE (APBPERIPH_BASE + 0x06000)
sahilmgandhi	18:6a4db94011d3	32232	#define I2S0_BASE (APBPERIPH_BASE + 0x08000)
sahilmgandhi	18:6a4db94011d3	32233	#define TIMER0_BASE (APBPERIPH_BASE + 0x10000)
sahilmgandhi	18:6a4db94011d3	32234	#define TIMER1_BASE (APBPERIPH_BASE + 0x10020)
sahilmgandhi	18:6a4db94011d3	32235	#define PWM0_BASE (APBPERIPH_BASE + 0x18000)
sahilmgandhi	18:6a4db94011d3	32236	#define EPWM0_BASE (APBPERIPH_BASE + 0x1C000)
sahilmgandhi	18:6a4db94011d3	32237	#define SPI0_BASE (APBPERIPH_BASE + 0x20000)
sahilmgandhi	18:6a4db94011d3	32238	#define SPI2_BASE (APBPERIPH_BASE + 0x22000)
sahilmgandhi	18:6a4db94011d3	32239	#define UART0_BASE (APBPERIPH_BASE + 0x30000)
sahilmgandhi	18:6a4db94011d3	32240	#define UART2_BASE (APBPERIPH_BASE + 0x32000)
sahilmgandhi	18:6a4db94011d3	32241	#define UART4_BASE (APBPERIPH_BASE + 0x34000)
sahilmgandhi	18:6a4db94011d3	32242	#define I2C0_BASE (APBPERIPH_BASE + 0x40000)
sahilmgandhi	18:6a4db94011d3	32243	#define I2C2_BASE (APBPERIPH_BASE + 0x42000)
sahilmgandhi	18:6a4db94011d3	32244	#define I2C4_BASE (APBPERIPH_BASE + 0x44000)
sahilmgandhi	18:6a4db94011d3	32245	#define SC0_BASE (APBPERIPH_BASE + 0x50000)
sahilmgandhi	18:6a4db94011d3	32246	#define SC2_BASE (APBPERIPH_BASE + 0x52000)
sahilmgandhi	18:6a4db94011d3	32247	#define SC4_BASE (APBPERIPH_BASE + 0x54000)
sahilmgandhi	18:6a4db94011d3	32248	#define CAN0_BASE (APBPERIPH_BASE + 0x60000)
sahilmgandhi	18:6a4db94011d3	32249	#define QEI0_BASE (APBPERIPH_BASE + 0x70000)
sahilmgandhi	18:6a4db94011d3	32250	#define ECAP0_BASE (APBPERIPH_BASE + 0x74000)
sahilmgandhi	18:6a4db94011d3	32251	#define PS2D_BASE (APBPERIPH_BASE + 0xA0000)
sahilmgandhi	18:6a4db94011d3	32252
sahilmgandhi	18:6a4db94011d3	32253	/!< APB1 peripherals /
sahilmgandhi	18:6a4db94011d3	32254	#define RTC_BASE (APBPERIPH_BASE + 0x01000)
sahilmgandhi	18:6a4db94011d3	32255	#define ADC_BASE (APBPERIPH_BASE + 0x03000)
sahilmgandhi	18:6a4db94011d3	32256	#define EADC_BASE (APBPERIPH_BASE + 0x04000)
sahilmgandhi	18:6a4db94011d3	32257	#define ACMP_BASE (APBPERIPH_BASE + 0x05000)
sahilmgandhi	18:6a4db94011d3	32258	#define I2S1_BASE (APBPERIPH_BASE + 0x09000)
sahilmgandhi	18:6a4db94011d3	32259	#define OTG_BASE (APBPERIPH_BASE + 0x0D000)
sahilmgandhi	18:6a4db94011d3	32260	#define TIMER2_BASE (APBPERIPH_BASE + 0x11000)
sahilmgandhi	18:6a4db94011d3	32261	#define TIMER3_BASE (APBPERIPH_BASE + 0x11020)
sahilmgandhi	18:6a4db94011d3	32262	#define PWM1_BASE (APBPERIPH_BASE + 0x19000)
sahilmgandhi	18:6a4db94011d3	32263	#define EPWM1_BASE (APBPERIPH_BASE + 0x1D000)
sahilmgandhi	18:6a4db94011d3	32264	#define SPI1_BASE (APBPERIPH_BASE + 0x21000)
sahilmgandhi	18:6a4db94011d3	32265	#define SPI3_BASE (APBPERIPH_BASE + 0x23000)
sahilmgandhi	18:6a4db94011d3	32266	#define UART1_BASE (APBPERIPH_BASE + 0x31000)
sahilmgandhi	18:6a4db94011d3	32267	#define UART3_BASE (APBPERIPH_BASE + 0x33000)
sahilmgandhi	18:6a4db94011d3	32268	#define UART5_BASE (APBPERIPH_BASE + 0x35000)
sahilmgandhi	18:6a4db94011d3	32269	#define I2C1_BASE (APBPERIPH_BASE + 0x41000)
sahilmgandhi	18:6a4db94011d3	32270	#define I2C3_BASE (APBPERIPH_BASE + 0x43000)
sahilmgandhi	18:6a4db94011d3	32271	#define SC1_BASE (APBPERIPH_BASE + 0x51000)
sahilmgandhi	18:6a4db94011d3	32272	#define SC3_BASE (APBPERIPH_BASE + 0x53000)
sahilmgandhi	18:6a4db94011d3	32273	#define SC5_BASE (APBPERIPH_BASE + 0x55000)
sahilmgandhi	18:6a4db94011d3	32274	#define CAN1_BASE (APBPERIPH_BASE + 0x61000)
sahilmgandhi	18:6a4db94011d3	32275	#define QEI1_BASE (APBPERIPH_BASE + 0x71000)
sahilmgandhi	18:6a4db94011d3	32276	#define ECAP1_BASE (APBPERIPH_BASE + 0x75000)
sahilmgandhi	18:6a4db94011d3	32277	#define CRPT_BASE (0x50080000UL)
sahilmgandhi	18:6a4db94011d3	32278
sahilmgandhi	18:6a4db94011d3	32279	/@}/ /* end of group NUC472_442_PERIPHERAL_MEM_MAP */
sahilmgandhi	18:6a4db94011d3	32280
sahilmgandhi	18:6a4db94011d3	32281
sahilmgandhi	18:6a4db94011d3	32282	/** @addtogroup NUC472_442_PERIPHERAL_DECLARATION NUC472/NUC442 Peripheral Pointer
sahilmgandhi	18:6a4db94011d3	32283	The Declaration of NUC472/NUC442 Peripheral
sahilmgandhi	18:6a4db94011d3	32284	@{
sahilmgandhi	18:6a4db94011d3	32285	*/
sahilmgandhi	18:6a4db94011d3	32286
sahilmgandhi	18:6a4db94011d3	32287	#define SYS ((SYS_T *) SYS_BASE)
sahilmgandhi	18:6a4db94011d3	32288	#define CLK ((CLK_T *) CLK_BASE)
sahilmgandhi	18:6a4db94011d3	32289	#define PA ((GPIO_T *) GPIOA_BASE)
sahilmgandhi	18:6a4db94011d3	32290	#define PB ((GPIO_T *) GPIOB_BASE)
sahilmgandhi	18:6a4db94011d3	32291	#define PC ((GPIO_T *) GPIOC_BASE)
sahilmgandhi	18:6a4db94011d3	32292	#define PD ((GPIO_T *) GPIOD_BASE)
sahilmgandhi	18:6a4db94011d3	32293	#define PE ((GPIO_T *) GPIOE_BASE)
sahilmgandhi	18:6a4db94011d3	32294	#define PF ((GPIO_T *) GPIOF_BASE)
sahilmgandhi	18:6a4db94011d3	32295	#define PG ((GPIO_T *) GPIOG_BASE)
sahilmgandhi	18:6a4db94011d3	32296	#define PH ((GPIO_T *) GPIOH_BASE)
sahilmgandhi	18:6a4db94011d3	32297	#define GPA ((GPIO_T *) GPIOA_BASE)
sahilmgandhi	18:6a4db94011d3	32298	#define GPB ((GPIO_T *) GPIOB_BASE)
sahilmgandhi	18:6a4db94011d3	32299	#define GPC ((GPIO_T *) GPIOC_BASE)
sahilmgandhi	18:6a4db94011d3	32300	#define GPD ((GPIO_T *) GPIOD_BASE)
sahilmgandhi	18:6a4db94011d3	32301	#define GPE ((GPIO_T *) GPIOE_BASE)
sahilmgandhi	18:6a4db94011d3	32302	#define GPF ((GPIO_T *) GPIOF_BASE)
sahilmgandhi	18:6a4db94011d3	32303	#define GPG ((GPIO_T *) GPIOG_BASE)
sahilmgandhi	18:6a4db94011d3	32304	#define GPH ((GPIO_T *) GPIOH_BASE)
sahilmgandhi	18:6a4db94011d3	32305	#define GPI ((GPIO_T *) GPIOI_BASE)
sahilmgandhi	18:6a4db94011d3	32306	#define GPIO ((GPIO_DB_T *) GPIO_DBCTL_BASE)
sahilmgandhi	18:6a4db94011d3	32307	#define PDMA ((PDMA_T *) PDMA_BASE)
sahilmgandhi	18:6a4db94011d3	32308	#define USBH ((USBH_T *) USBH_BASE)
sahilmgandhi	18:6a4db94011d3	32309	#define EMAC ((EMAC_T *) EMAC_BASE)
sahilmgandhi	18:6a4db94011d3	32310	#define FMC ((FMC_T *) FMC_BASE)
sahilmgandhi	18:6a4db94011d3	32311	#define SD ((SDH_T *) SD_BASE)
sahilmgandhi	18:6a4db94011d3	32312	#define SIC ((SIC_T *) SIC_BASE)
sahilmgandhi	18:6a4db94011d3	32313	#define EBI ((EBI_T *) EBI_BASE)
sahilmgandhi	18:6a4db94011d3	32314	#define ICAP ((CAP_T *) CAP_BASE)
sahilmgandhi	18:6a4db94011d3	32315	#define SPACC ((SPACC_T *) SPACC_BASE)
sahilmgandhi	18:6a4db94011d3	32316	#define CRC ((CRC_T *) CRC_BASE)
sahilmgandhi	18:6a4db94011d3	32317	#define TAMPER ((TAMPER_T *) TAMPER_BASE)
sahilmgandhi	18:6a4db94011d3	32318
sahilmgandhi	18:6a4db94011d3	32319	#define WDT ((WDT_T *) WDT_BASE)
sahilmgandhi	18:6a4db94011d3	32320	#define WWDT ((WWDT_T *) WWDT_BASE)
sahilmgandhi	18:6a4db94011d3	32321	#define RTC ((RTC_T *) RTC_BASE)
sahilmgandhi	18:6a4db94011d3	32322	#define ADC ((ADC_T *) ADC_BASE)
sahilmgandhi	18:6a4db94011d3	32323	#define EADC ((EADC_T *) EADC_BASE)
sahilmgandhi	18:6a4db94011d3	32324	#define ACMP ((ACMP_T *) ACMP_BASE)
sahilmgandhi	18:6a4db94011d3	32325
sahilmgandhi	18:6a4db94011d3	32326	#define I2S0 ((I2S_T *) I2S0_BASE)
sahilmgandhi	18:6a4db94011d3	32327	#define I2S1 ((I2S_T *) I2S1_BASE)
sahilmgandhi	18:6a4db94011d3	32328	#define USBD ((USBD_T *) UDC20_BASE)
sahilmgandhi	18:6a4db94011d3	32329	#define OTG ((OTG_T *) OTG_BASE)
sahilmgandhi	18:6a4db94011d3	32330	#define TIMER0 ((TIMER_T *) TIMER0_BASE)
sahilmgandhi	18:6a4db94011d3	32331	#define TIMER1 ((TIMER_T *) TIMER1_BASE)
sahilmgandhi	18:6a4db94011d3	32332	#define TIMER2 ((TIMER_T *) TIMER2_BASE)
sahilmgandhi	18:6a4db94011d3	32333	#define TIMER3 ((TIMER_T *) TIMER3_BASE)
sahilmgandhi	18:6a4db94011d3	32334	#define PWM0 ((PWM_T *) PWM0_BASE)
sahilmgandhi	18:6a4db94011d3	32335	#define PWM1 ((PWM_T *) PWM1_BASE)
sahilmgandhi	18:6a4db94011d3	32336	#define EPWM0 ((EPWM_T *) EPWM0_BASE)
sahilmgandhi	18:6a4db94011d3	32337	#define EPWM1 ((EPWM_T *) EPWM1_BASE)
sahilmgandhi	18:6a4db94011d3	32338	#define ECAP0 ((ECAP_T *) ECAP0_BASE)
sahilmgandhi	18:6a4db94011d3	32339	#define ECAP1 ((ECAP_T *) ECAP1_BASE)
sahilmgandhi	18:6a4db94011d3	32340	#define QEI0 ((QEI_T *) QEI0_BASE)
sahilmgandhi	18:6a4db94011d3	32341	#define QEI1 ((QEI_T *) QEI1_BASE)
sahilmgandhi	18:6a4db94011d3	32342	#define SPI0 ((SPI_T *) SPI0_BASE)
sahilmgandhi	18:6a4db94011d3	32343	#define SPI1 ((SPI_T *) SPI1_BASE)
sahilmgandhi	18:6a4db94011d3	32344	#define SPI2 ((SPI_T *) SPI2_BASE)
sahilmgandhi	18:6a4db94011d3	32345	#define SPI3 ((SPI_T *) SPI3_BASE)
sahilmgandhi	18:6a4db94011d3	32346	#define UART0 ((UART_T *) UART0_BASE)
sahilmgandhi	18:6a4db94011d3	32347	#define UART1 ((UART_T *) UART1_BASE)
sahilmgandhi	18:6a4db94011d3	32348	#define UART2 ((UART_T *) UART2_BASE)
sahilmgandhi	18:6a4db94011d3	32349	#define UART3 ((UART_T *) UART3_BASE)
sahilmgandhi	18:6a4db94011d3	32350	#define UART4 ((UART_T *) UART4_BASE)
sahilmgandhi	18:6a4db94011d3	32351	#define UART5 ((UART_T *) UART5_BASE)
sahilmgandhi	18:6a4db94011d3	32352	#define I2C0 ((I2C_T *) I2C0_BASE)
sahilmgandhi	18:6a4db94011d3	32353	#define I2C1 ((I2C_T *) I2C1_BASE)
sahilmgandhi	18:6a4db94011d3	32354	#define I2C2 ((I2C_T *) I2C2_BASE)
sahilmgandhi	18:6a4db94011d3	32355	#define I2C3 ((I2C_T *) I2C3_BASE)
sahilmgandhi	18:6a4db94011d3	32356	#define I2C4 ((I2C_T *) I2C4_BASE)
sahilmgandhi	18:6a4db94011d3	32357	#define SC0 ((SC_T *) SC0_BASE)
sahilmgandhi	18:6a4db94011d3	32358	#define SC1 ((SC_T *) SC1_BASE)
sahilmgandhi	18:6a4db94011d3	32359	#define SC2 ((SC_T *) SC2_BASE)
sahilmgandhi	18:6a4db94011d3	32360	#define SC3 ((SC_T *) SC3_BASE)
sahilmgandhi	18:6a4db94011d3	32361	#define SC4 ((SC_T *) SC4_BASE)
sahilmgandhi	18:6a4db94011d3	32362	#define SC5 ((SC_T *) SC5_BASE)
sahilmgandhi	18:6a4db94011d3	32363	#define CAN0 ((CAN_T *) CAN0_BASE)
sahilmgandhi	18:6a4db94011d3	32364	#define CAN1 ((CAN_T *) CAN1_BASE)
sahilmgandhi	18:6a4db94011d3	32365	#define PS2 ((PS2_T *) PS2D_BASE)
sahilmgandhi	18:6a4db94011d3	32366	#define CRPT ((CRPT_T *) CRPT_BASE)
sahilmgandhi	18:6a4db94011d3	32367	/@}/ /* end of group NUC472_442_PERIPHERAL_DECLARATION */
sahilmgandhi	18:6a4db94011d3	32368
sahilmgandhi	18:6a4db94011d3	32369	/** @addtogroup NUC472_442_IO_ROUTINE NUC472/NUC442 I/O Routines
sahilmgandhi	18:6a4db94011d3	32370	The Declaration of NUC472/NUC442 I/O Routines
sahilmgandhi	18:6a4db94011d3	32371	@{
sahilmgandhi	18:6a4db94011d3	32372	*/
sahilmgandhi	18:6a4db94011d3	32373
sahilmgandhi	18:6a4db94011d3	32374	typedef volatile unsigned char vu8; ///< Define 8-bit unsigned volatile data type
sahilmgandhi	18:6a4db94011d3	32375	typedef volatile unsigned short vu16; ///< Define 16-bit unsigned volatile data type
sahilmgandhi	18:6a4db94011d3	32376	typedef volatile unsigned long vu32; ///< Define 32-bit unsigned volatile data type
sahilmgandhi	18:6a4db94011d3	32377
sahilmgandhi	18:6a4db94011d3	32378	/**
sahilmgandhi	18:6a4db94011d3	32379	* @brief Get a 8-bit unsigned value from specified address
sahilmgandhi	18:6a4db94011d3	32380	* @param[in] addr Address to get 8-bit data from
sahilmgandhi	18:6a4db94011d3	32381	* @return 8-bit unsigned value stored in specified address
sahilmgandhi	18:6a4db94011d3	32382	*/
sahilmgandhi	18:6a4db94011d3	32383	#define M8(addr) (((vu8 ) (addr)))
sahilmgandhi	18:6a4db94011d3	32384
sahilmgandhi	18:6a4db94011d3	32385	/**
sahilmgandhi	18:6a4db94011d3	32386	* @brief Get a 16-bit unsigned value from specified address
sahilmgandhi	18:6a4db94011d3	32387	* @param[in] addr Address to get 16-bit data from
sahilmgandhi	18:6a4db94011d3	32388	* @return 16-bit unsigned value stored in specified address
sahilmgandhi	18:6a4db94011d3	32389	* @note The input address must be 16-bit aligned
sahilmgandhi	18:6a4db94011d3	32390	*/
sahilmgandhi	18:6a4db94011d3	32391	#define M16(addr) (((vu16 ) (addr)))
sahilmgandhi	18:6a4db94011d3	32392
sahilmgandhi	18:6a4db94011d3	32393	/**
sahilmgandhi	18:6a4db94011d3	32394	* @brief Get a 32-bit unsigned value from specified address
sahilmgandhi	18:6a4db94011d3	32395	* @param[in] addr Address to get 32-bit data from
sahilmgandhi	18:6a4db94011d3	32396	* @return 32-bit unsigned value stored in specified address
sahilmgandhi	18:6a4db94011d3	32397	* @note The input address must be 32-bit aligned
sahilmgandhi	18:6a4db94011d3	32398	*/
sahilmgandhi	18:6a4db94011d3	32399	#define M32(addr) (((vu32 ) (addr)))
sahilmgandhi	18:6a4db94011d3	32400
sahilmgandhi	18:6a4db94011d3	32401	/**
sahilmgandhi	18:6a4db94011d3	32402	* @brief Set a 32-bit unsigned value to specified I/O port
sahilmgandhi	18:6a4db94011d3	32403	* @param[in] port Port address to set 32-bit data
sahilmgandhi	18:6a4db94011d3	32404	* @param[in] value Value to write to I/O port
sahilmgandhi	18:6a4db94011d3	32405	* @return None
sahilmgandhi	18:6a4db94011d3	32406	* @note The output port must be 32-bit aligned
sahilmgandhi	18:6a4db94011d3	32407	*/
sahilmgandhi	18:6a4db94011d3	32408	#define outpw(port,value) ((volatile unsigned int )(port)) = value
sahilmgandhi	18:6a4db94011d3	32409
sahilmgandhi	18:6a4db94011d3	32410	/**
sahilmgandhi	18:6a4db94011d3	32411	* @brief Get a 32-bit unsigned value from specified I/O port
sahilmgandhi	18:6a4db94011d3	32412	* @param[in] port Port address to get 32-bit data from
sahilmgandhi	18:6a4db94011d3	32413	* @return 32-bit unsigned value stored in specified I/O port
sahilmgandhi	18:6a4db94011d3	32414	* @note The input port must be 32-bit aligned
sahilmgandhi	18:6a4db94011d3	32415	*/
sahilmgandhi	18:6a4db94011d3	32416	#define inpw(port) (((volatile unsigned int )(port)))
sahilmgandhi	18:6a4db94011d3	32417
sahilmgandhi	18:6a4db94011d3	32418	/**
sahilmgandhi	18:6a4db94011d3	32419	* @brief Set a 16-bit unsigned value to specified I/O port
sahilmgandhi	18:6a4db94011d3	32420	* @param[in] port Port address to set 16-bit data
sahilmgandhi	18:6a4db94011d3	32421	* @param[in] value Value to write to I/O port
sahilmgandhi	18:6a4db94011d3	32422	* @return None
sahilmgandhi	18:6a4db94011d3	32423	* @note The output port must be 16-bit aligned
sahilmgandhi	18:6a4db94011d3	32424	*/
sahilmgandhi	18:6a4db94011d3	32425	#define outps(port,value) ((volatile unsigned short )(port)) = value
sahilmgandhi	18:6a4db94011d3	32426
sahilmgandhi	18:6a4db94011d3	32427	/**
sahilmgandhi	18:6a4db94011d3	32428	* @brief Get a 16-bit unsigned value from specified I/O port
sahilmgandhi	18:6a4db94011d3	32429	* @param[in] port Port address to get 16-bit data from
sahilmgandhi	18:6a4db94011d3	32430	* @return 16-bit unsigned value stored in specified I/O port
sahilmgandhi	18:6a4db94011d3	32431	* @note The input port must be 16-bit aligned
sahilmgandhi	18:6a4db94011d3	32432	*/
sahilmgandhi	18:6a4db94011d3	32433	#define inps(port) (((volatile unsigned short )(port)))
sahilmgandhi	18:6a4db94011d3	32434
sahilmgandhi	18:6a4db94011d3	32435	/**
sahilmgandhi	18:6a4db94011d3	32436	* @brief Set a 8-bit unsigned value to specified I/O port
sahilmgandhi	18:6a4db94011d3	32437	* @param[in] port Port address to set 8-bit data
sahilmgandhi	18:6a4db94011d3	32438	* @param[in] value Value to write to I/O port
sahilmgandhi	18:6a4db94011d3	32439	* @return None
sahilmgandhi	18:6a4db94011d3	32440	*/
sahilmgandhi	18:6a4db94011d3	32441	#define outpb(port,value) ((volatile unsigned char )(port)) = value
sahilmgandhi	18:6a4db94011d3	32442
sahilmgandhi	18:6a4db94011d3	32443	/**
sahilmgandhi	18:6a4db94011d3	32444	* @brief Get a 8-bit unsigned value from specified I/O port
sahilmgandhi	18:6a4db94011d3	32445	* @param[in] port Port address to get 8-bit data from
sahilmgandhi	18:6a4db94011d3	32446	* @return 8-bit unsigned value stored in specified I/O port
sahilmgandhi	18:6a4db94011d3	32447	*/
sahilmgandhi	18:6a4db94011d3	32448	#define inpb(port) (((volatile unsigned char )(port)))
sahilmgandhi	18:6a4db94011d3	32449
sahilmgandhi	18:6a4db94011d3	32450	/**
sahilmgandhi	18:6a4db94011d3	32451	* @brief Set a 32-bit unsigned value to specified I/O port
sahilmgandhi	18:6a4db94011d3	32452	* @param[in] port Port address to set 32-bit data
sahilmgandhi	18:6a4db94011d3	32453	* @param[in] value Value to write to I/O port
sahilmgandhi	18:6a4db94011d3	32454	* @return None
sahilmgandhi	18:6a4db94011d3	32455	* @note The output port must be 32-bit aligned
sahilmgandhi	18:6a4db94011d3	32456	*/
sahilmgandhi	18:6a4db94011d3	32457	#define outp32(port,value) ((volatile unsigned int )(port)) = value
sahilmgandhi	18:6a4db94011d3	32458
sahilmgandhi	18:6a4db94011d3	32459	/**
sahilmgandhi	18:6a4db94011d3	32460	* @brief Get a 32-bit unsigned value from specified I/O port
sahilmgandhi	18:6a4db94011d3	32461	* @param[in] port Port address to get 32-bit data from
sahilmgandhi	18:6a4db94011d3	32462	* @return 32-bit unsigned value stored in specified I/O port
sahilmgandhi	18:6a4db94011d3	32463	* @note The input port must be 32-bit aligned
sahilmgandhi	18:6a4db94011d3	32464	*/
sahilmgandhi	18:6a4db94011d3	32465	#define inp32(port) (((volatile unsigned int )(port)))
sahilmgandhi	18:6a4db94011d3	32466
sahilmgandhi	18:6a4db94011d3	32467	/**
sahilmgandhi	18:6a4db94011d3	32468	* @brief Set a 16-bit unsigned value to specified I/O port
sahilmgandhi	18:6a4db94011d3	32469	* @param[in] port Port address to set 16-bit data
sahilmgandhi	18:6a4db94011d3	32470	* @param[in] value Value to write to I/O port
sahilmgandhi	18:6a4db94011d3	32471	* @return None
sahilmgandhi	18:6a4db94011d3	32472	* @note The output port must be 16-bit aligned
sahilmgandhi	18:6a4db94011d3	32473	*/
sahilmgandhi	18:6a4db94011d3	32474	#define outp16(port,value) ((volatile unsigned short )(port)) = value
sahilmgandhi	18:6a4db94011d3	32475
sahilmgandhi	18:6a4db94011d3	32476	/**
sahilmgandhi	18:6a4db94011d3	32477	* @brief Get a 16-bit unsigned value from specified I/O port
sahilmgandhi	18:6a4db94011d3	32478	* @param[in] port Port address to get 16-bit data from
sahilmgandhi	18:6a4db94011d3	32479	* @return 16-bit unsigned value stored in specified I/O port
sahilmgandhi	18:6a4db94011d3	32480	* @note The input port must be 16-bit aligned
sahilmgandhi	18:6a4db94011d3	32481	*/
sahilmgandhi	18:6a4db94011d3	32482	#define inp16(port) (((volatile unsigned short )(port)))
sahilmgandhi	18:6a4db94011d3	32483
sahilmgandhi	18:6a4db94011d3	32484	/**
sahilmgandhi	18:6a4db94011d3	32485	* @brief Set a 8-bit unsigned value to specified I/O port
sahilmgandhi	18:6a4db94011d3	32486	* @param[in] port Port address to set 8-bit data
sahilmgandhi	18:6a4db94011d3	32487	* @param[in] value Value to write to I/O port
sahilmgandhi	18:6a4db94011d3	32488	* @return None
sahilmgandhi	18:6a4db94011d3	32489	*/
sahilmgandhi	18:6a4db94011d3	32490	#define outp8(port,value) ((volatile unsigned char )(port)) = value
sahilmgandhi	18:6a4db94011d3	32491
sahilmgandhi	18:6a4db94011d3	32492	/**
sahilmgandhi	18:6a4db94011d3	32493	* @brief Get a 8-bit unsigned value from specified I/O port
sahilmgandhi	18:6a4db94011d3	32494	* @param[in] port Port address to get 8-bit data from
sahilmgandhi	18:6a4db94011d3	32495	* @return 8-bit unsigned value stored in specified I/O port
sahilmgandhi	18:6a4db94011d3	32496	*/
sahilmgandhi	18:6a4db94011d3	32497	#define inp8(port) (((volatile unsigned char )(port)))
sahilmgandhi	18:6a4db94011d3	32498
sahilmgandhi	18:6a4db94011d3	32499
sahilmgandhi	18:6a4db94011d3	32500	/@}/ /* end of group NUC472_442_IO_ROUTINE */
sahilmgandhi	18:6a4db94011d3	32501
sahilmgandhi	18:6a4db94011d3	32502	/******************************************************************************/
sahilmgandhi	18:6a4db94011d3	32503	/* Legacy Constants */
sahilmgandhi	18:6a4db94011d3	32504	/******************************************************************************/
sahilmgandhi	18:6a4db94011d3	32505	/** @addtogroup NUC472_442_legacy_Constants NUC472/NUC442 Legacy Constants
sahilmgandhi	18:6a4db94011d3	32506	NUC472/NUC442 Legacy Constants
sahilmgandhi	18:6a4db94011d3	32507	@{
sahilmgandhi	18:6a4db94011d3	32508	*/
sahilmgandhi	18:6a4db94011d3	32509
sahilmgandhi	18:6a4db94011d3	32510	#ifndef NULL
sahilmgandhi	18:6a4db94011d3	32511	#define NULL (0) ///< NULL pointer
sahilmgandhi	18:6a4db94011d3	32512	#endif
sahilmgandhi	18:6a4db94011d3	32513
sahilmgandhi	18:6a4db94011d3	32514	#define TRUE (1) ///< Boolean true, define to use in API parameters or return value
sahilmgandhi	18:6a4db94011d3	32515	#define FALSE (0) ///< Boolean false, define to use in API parameters or return value
sahilmgandhi	18:6a4db94011d3	32516
sahilmgandhi	18:6a4db94011d3	32517	#define ENABLE (1) ///< Enable, define to use in API parameters
sahilmgandhi	18:6a4db94011d3	32518	#define DISABLE (0) ///< Disable, define to use in API parameters
sahilmgandhi	18:6a4db94011d3	32519
sahilmgandhi	18:6a4db94011d3	32520	/* Define one bit mask */
sahilmgandhi	18:6a4db94011d3	32521	#define BIT0 (0x00000001) ///< Bit 0 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32522	#define BIT1 (0x00000002) ///< Bit 1 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32523	#define BIT2 (0x00000004) ///< Bit 2 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32524	#define BIT3 (0x00000008) ///< Bit 3 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32525	#define BIT4 (0x00000010) ///< Bit 4 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32526	#define BIT5 (0x00000020) ///< Bit 5 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32527	#define BIT6 (0x00000040) ///< Bit 6 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32528	#define BIT7 (0x00000080) ///< Bit 7 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32529	#define BIT8 (0x00000100) ///< Bit 8 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32530	#define BIT9 (0x00000200) ///< Bit 9 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32531	#define BIT10 (0x00000400) ///< Bit 10 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32532	#define BIT11 (0x00000800) ///< Bit 11 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32533	#define BIT12 (0x00001000) ///< Bit 12 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32534	#define BIT13 (0x00002000) ///< Bit 13 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32535	#define BIT14 (0x00004000) ///< Bit 14 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32536	#define BIT15 (0x00008000) ///< Bit 15 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32537	#define BIT16 (0x00010000) ///< Bit 16 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32538	#define BIT17 (0x00020000) ///< Bit 17 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32539	#define BIT18 (0x00040000) ///< Bit 18 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32540	#define BIT19 (0x00080000) ///< Bit 19 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32541	#define BIT20 (0x00100000) ///< Bit 20 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32542	#define BIT21 (0x00200000) ///< Bit 21 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32543	#define BIT22 (0x00400000) ///< Bit 22 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32544	#define BIT23 (0x00800000) ///< Bit 23 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32545	#define BIT24 (0x01000000) ///< Bit 24 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32546	#define BIT25 (0x02000000) ///< Bit 25 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32547	#define BIT26 (0x04000000) ///< Bit 26 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32548	#define BIT27 (0x08000000) ///< Bit 27 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32549	#define BIT28 (0x10000000) ///< Bit 28 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32550	#define BIT29 (0x20000000) ///< Bit 29 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32551	#define BIT30 (0x40000000) ///< Bit 30 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32552	#define BIT31 (0x80000000) ///< Bit 31 mask of an 32 bit integer
sahilmgandhi	18:6a4db94011d3	32553
sahilmgandhi	18:6a4db94011d3	32554	/* Byte Mask Definitions */
sahilmgandhi	18:6a4db94011d3	32555	#define BYTE0_Msk (0x000000FF) ///< Mask to get bit0~bit7 from a 32 bit integer
sahilmgandhi	18:6a4db94011d3	32556	#define BYTE1_Msk (0x0000FF00) ///< Mask to get bit8~bit15 from a 32 bit integer
sahilmgandhi	18:6a4db94011d3	32557	#define BYTE2_Msk (0x00FF0000) ///< Mask to get bit16~bit23 from a 32 bit integer
sahilmgandhi	18:6a4db94011d3	32558	#define BYTE3_Msk (0xFF000000) ///< Mask to get bit24~bit31 from a 32 bit integer
sahilmgandhi	18:6a4db94011d3	32559
sahilmgandhi	18:6a4db94011d3	32560	#define GET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) ) /!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param /
sahilmgandhi	18:6a4db94011d3	32561	#define GET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8) /!< Extract Byte 1 (Bit 8~15) from parameter u32Param /
sahilmgandhi	18:6a4db94011d3	32562	#define GET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16) /!< Extract Byte 2 (Bit 16~23) from parameter u32Param /
sahilmgandhi	18:6a4db94011d3	32563	#define GET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24) /!< Extract Byte 3 (Bit 24~31) from parameter u32Param /
sahilmgandhi	18:6a4db94011d3	32564
sahilmgandhi	18:6a4db94011d3	32565	/@}/ /* end of group NUC472_442_legacy_Constants */
sahilmgandhi	18:6a4db94011d3	32566
sahilmgandhi	18:6a4db94011d3	32567
sahilmgandhi	18:6a4db94011d3	32568	/******************************************************************************/
sahilmgandhi	18:6a4db94011d3	32569	/* Peripheral header files */
sahilmgandhi	18:6a4db94011d3	32570	/******************************************************************************/
sahilmgandhi	18:6a4db94011d3	32571	#include "nuc472_sys.h"
sahilmgandhi	18:6a4db94011d3	32572	#include "nuc472_clk.h"
sahilmgandhi	18:6a4db94011d3	32573
sahilmgandhi	18:6a4db94011d3	32574	#include "nuc472_acmp.h"
sahilmgandhi	18:6a4db94011d3	32575	#include "nuc472_adc.h"
sahilmgandhi	18:6a4db94011d3	32576	#include "nuc472_eadc.h"
sahilmgandhi	18:6a4db94011d3	32577	/* Disable Capture: #include "nuc472_cap.h" */
sahilmgandhi	18:6a4db94011d3	32578	#include "nuc472_crypto.h"
sahilmgandhi	18:6a4db94011d3	32579	#include "nuc472_pdma.h"
sahilmgandhi	18:6a4db94011d3	32580	#include "nuc472_ebi.h"
sahilmgandhi	18:6a4db94011d3	32581	#include "nuc472_emac.h"
sahilmgandhi	18:6a4db94011d3	32582	#include "nuc472_fmc.h"
sahilmgandhi	18:6a4db94011d3	32583	#include "nuc472_gpio.h"
sahilmgandhi	18:6a4db94011d3	32584	#include "nuc472_i2c.h"
sahilmgandhi	18:6a4db94011d3	32585	#include "nuc472_pwm.h"
sahilmgandhi	18:6a4db94011d3	32586	#include "nuc472_rtc.h"
sahilmgandhi	18:6a4db94011d3	32587	#include "nuc472_sc.h"
sahilmgandhi	18:6a4db94011d3	32588	#include "nuc472_scuart.h"
sahilmgandhi	18:6a4db94011d3	32589	#include "nuc472_spi.h"
sahilmgandhi	18:6a4db94011d3	32590	#include "nuc472_timer.h"
sahilmgandhi	18:6a4db94011d3	32591	#include "nuc472_uart.h"
sahilmgandhi	18:6a4db94011d3	32592	#include "nuc472_usbd.h"
sahilmgandhi	18:6a4db94011d3	32593	#include "nuc472_wdt.h"
sahilmgandhi	18:6a4db94011d3	32594	#include "nuc472_wwdt.h"
sahilmgandhi	18:6a4db94011d3	32595	#include "nuc472_i2s.h"
sahilmgandhi	18:6a4db94011d3	32596	#include "nuc472_can.h"
sahilmgandhi	18:6a4db94011d3	32597	#include "nuc472_sd.h"
sahilmgandhi	18:6a4db94011d3	32598	#include "nuc472_ps2.h"
sahilmgandhi	18:6a4db94011d3	32599
sahilmgandhi	18:6a4db94011d3	32600	#ifdef __cplusplus
sahilmgandhi	18:6a4db94011d3	32601	}
sahilmgandhi	18:6a4db94011d3	32602	#endif
sahilmgandhi	18:6a4db94011d3	32603
sahilmgandhi	18:6a4db94011d3	32604	#endif /* __NUC472_442_H__ */
sahilmgandhi	18:6a4db94011d3	32605
sahilmgandhi	18:6a4db94011d3	32606	/* (C) COPYRIGHT 2014 Nuvoton Technology Corp. */

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Type:	Program
Created:	25 Apr 2017
Imports:	29
Forks:	0
Commits:	47
Dependents:	0
Dependencies:	2
Followers:	5

The code in this repository is Apache licensed.

mbed-dev/targets/TARGET_NUVOTON/TARGET_NUC472/device/NUC472_442.h@46:b156ef445742, 2017-06-03 (annotated)

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