MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2015-2016 Nuvoton
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16
sahilmgandhi 18:6a4db94011d3 17 #include "serial_api.h"
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 #if DEVICE_SERIAL
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 22 #include "mbed_error.h"
sahilmgandhi 18:6a4db94011d3 23 #include "mbed_assert.h"
sahilmgandhi 18:6a4db94011d3 24 #include "PeripheralPins.h"
sahilmgandhi 18:6a4db94011d3 25 #include "nu_modutil.h"
sahilmgandhi 18:6a4db94011d3 26 #include "nu_bitutil.h"
sahilmgandhi 18:6a4db94011d3 27
sahilmgandhi 18:6a4db94011d3 28 #if DEVICE_SERIAL_ASYNCH
sahilmgandhi 18:6a4db94011d3 29 #include "dma_api.h"
sahilmgandhi 18:6a4db94011d3 30 #include "dma.h"
sahilmgandhi 18:6a4db94011d3 31 #endif
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 struct nu_uart_var {
sahilmgandhi 18:6a4db94011d3 34 uint32_t ref_cnt; // Reference count of the H/W module
sahilmgandhi 18:6a4db94011d3 35 serial_t * obj;
sahilmgandhi 18:6a4db94011d3 36 uint32_t fifo_size_tx;
sahilmgandhi 18:6a4db94011d3 37 uint32_t fifo_size_rx;
sahilmgandhi 18:6a4db94011d3 38 void (*vec)(void);
sahilmgandhi 18:6a4db94011d3 39 #if DEVICE_SERIAL_ASYNCH
sahilmgandhi 18:6a4db94011d3 40 void (*vec_async)(void);
sahilmgandhi 18:6a4db94011d3 41 uint8_t pdma_perp_tx;
sahilmgandhi 18:6a4db94011d3 42 uint8_t pdma_perp_rx;
sahilmgandhi 18:6a4db94011d3 43 #endif
sahilmgandhi 18:6a4db94011d3 44 };
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 static void uart0_vec(void);
sahilmgandhi 18:6a4db94011d3 47 static void uart1_vec(void);
sahilmgandhi 18:6a4db94011d3 48 static void uart2_vec(void);
sahilmgandhi 18:6a4db94011d3 49 static void uart3_vec(void);
sahilmgandhi 18:6a4db94011d3 50 static void uart_irq(serial_t *obj);
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 #if DEVICE_SERIAL_ASYNCH
sahilmgandhi 18:6a4db94011d3 53 static void uart0_vec_async(void);
sahilmgandhi 18:6a4db94011d3 54 static void uart1_vec_async(void);
sahilmgandhi 18:6a4db94011d3 55 static void uart2_vec_async(void);
sahilmgandhi 18:6a4db94011d3 56 static void uart3_vec_async(void);
sahilmgandhi 18:6a4db94011d3 57 static void uart_irq_async(serial_t *obj);
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 static void uart_dma_handler_tx(uint32_t id, uint32_t event);
sahilmgandhi 18:6a4db94011d3 60 static void uart_dma_handler_rx(uint32_t id, uint32_t event);
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62 static void serial_tx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
sahilmgandhi 18:6a4db94011d3 63 static void serial_rx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
sahilmgandhi 18:6a4db94011d3 64 static int serial_write_async(serial_t *obj);
sahilmgandhi 18:6a4db94011d3 65 static int serial_read_async(serial_t *obj);
sahilmgandhi 18:6a4db94011d3 66
sahilmgandhi 18:6a4db94011d3 67 static uint32_t serial_rx_event_check(serial_t *obj);
sahilmgandhi 18:6a4db94011d3 68 static uint32_t serial_tx_event_check(serial_t *obj);
sahilmgandhi 18:6a4db94011d3 69
sahilmgandhi 18:6a4db94011d3 70 static int serial_is_tx_complete(serial_t *obj);
sahilmgandhi 18:6a4db94011d3 71 static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable);
sahilmgandhi 18:6a4db94011d3 72
sahilmgandhi 18:6a4db94011d3 73 static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width);
sahilmgandhi 18:6a4db94011d3 74 static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width);
sahilmgandhi 18:6a4db94011d3 75 static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match);
sahilmgandhi 18:6a4db94011d3 76 static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable);
sahilmgandhi 18:6a4db94011d3 77 static int serial_is_rx_complete(serial_t *obj);
sahilmgandhi 18:6a4db94011d3 78
sahilmgandhi 18:6a4db94011d3 79 static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch);
sahilmgandhi 18:6a4db94011d3 80 static int serial_is_irq_en(serial_t *obj, SerialIrq irq);
sahilmgandhi 18:6a4db94011d3 81 #endif
sahilmgandhi 18:6a4db94011d3 82
sahilmgandhi 18:6a4db94011d3 83 static struct nu_uart_var uart0_var = {
sahilmgandhi 18:6a4db94011d3 84 .ref_cnt = 0,
sahilmgandhi 18:6a4db94011d3 85 .obj = NULL,
sahilmgandhi 18:6a4db94011d3 86 .fifo_size_tx = 16,
sahilmgandhi 18:6a4db94011d3 87 .fifo_size_rx = 16,
sahilmgandhi 18:6a4db94011d3 88 .vec = uart0_vec,
sahilmgandhi 18:6a4db94011d3 89 #if DEVICE_SERIAL_ASYNCH
sahilmgandhi 18:6a4db94011d3 90 .vec_async = uart0_vec_async,
sahilmgandhi 18:6a4db94011d3 91 .pdma_perp_tx = PDMA_UART0_TX,
sahilmgandhi 18:6a4db94011d3 92 .pdma_perp_rx = PDMA_UART0_RX
sahilmgandhi 18:6a4db94011d3 93 #endif
sahilmgandhi 18:6a4db94011d3 94 };
sahilmgandhi 18:6a4db94011d3 95 static struct nu_uart_var uart1_var = {
sahilmgandhi 18:6a4db94011d3 96 .ref_cnt = 0,
sahilmgandhi 18:6a4db94011d3 97 .obj = NULL,
sahilmgandhi 18:6a4db94011d3 98 .fifo_size_tx = 16,
sahilmgandhi 18:6a4db94011d3 99 .fifo_size_rx = 16,
sahilmgandhi 18:6a4db94011d3 100 .vec = uart1_vec,
sahilmgandhi 18:6a4db94011d3 101 #if DEVICE_SERIAL_ASYNCH
sahilmgandhi 18:6a4db94011d3 102 .vec_async = uart1_vec_async,
sahilmgandhi 18:6a4db94011d3 103 .pdma_perp_tx = PDMA_UART1_TX,
sahilmgandhi 18:6a4db94011d3 104 .pdma_perp_rx = PDMA_UART1_RX
sahilmgandhi 18:6a4db94011d3 105 #endif
sahilmgandhi 18:6a4db94011d3 106 };
sahilmgandhi 18:6a4db94011d3 107 static struct nu_uart_var uart2_var = {
sahilmgandhi 18:6a4db94011d3 108 .ref_cnt = 0,
sahilmgandhi 18:6a4db94011d3 109 .obj = NULL,
sahilmgandhi 18:6a4db94011d3 110 .fifo_size_tx = 16,
sahilmgandhi 18:6a4db94011d3 111 .fifo_size_rx = 16,
sahilmgandhi 18:6a4db94011d3 112 .vec = uart2_vec,
sahilmgandhi 18:6a4db94011d3 113 #if DEVICE_SERIAL_ASYNCH
sahilmgandhi 18:6a4db94011d3 114 .vec_async = uart2_vec_async,
sahilmgandhi 18:6a4db94011d3 115 .pdma_perp_tx = PDMA_UART2_TX,
sahilmgandhi 18:6a4db94011d3 116 .pdma_perp_rx = PDMA_UART2_RX
sahilmgandhi 18:6a4db94011d3 117 #endif
sahilmgandhi 18:6a4db94011d3 118 };
sahilmgandhi 18:6a4db94011d3 119 static struct nu_uart_var uart3_var = {
sahilmgandhi 18:6a4db94011d3 120 .ref_cnt = 0,
sahilmgandhi 18:6a4db94011d3 121 .obj = NULL,
sahilmgandhi 18:6a4db94011d3 122 .fifo_size_tx = 16,
sahilmgandhi 18:6a4db94011d3 123 .fifo_size_rx = 16,
sahilmgandhi 18:6a4db94011d3 124 .vec = uart3_vec,
sahilmgandhi 18:6a4db94011d3 125 #if DEVICE_SERIAL_ASYNCH
sahilmgandhi 18:6a4db94011d3 126 .vec_async = uart3_vec_async,
sahilmgandhi 18:6a4db94011d3 127 .pdma_perp_tx = PDMA_UART3_TX,
sahilmgandhi 18:6a4db94011d3 128 .pdma_perp_rx = PDMA_UART3_RX
sahilmgandhi 18:6a4db94011d3 129 #endif
sahilmgandhi 18:6a4db94011d3 130 };
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132
sahilmgandhi 18:6a4db94011d3 133 int stdio_uart_inited = 0;
sahilmgandhi 18:6a4db94011d3 134 serial_t stdio_uart;
sahilmgandhi 18:6a4db94011d3 135 static uint32_t uart_modinit_mask = 0;
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137 static const struct nu_modinit_s uart_modinit_tab[] = {
sahilmgandhi 18:6a4db94011d3 138 {UART_0, UART0_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART0_RST, UART0_IRQn, &uart0_var},
sahilmgandhi 18:6a4db94011d3 139 {UART_1, UART1_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART1_RST, UART1_IRQn, &uart1_var},
sahilmgandhi 18:6a4db94011d3 140 {UART_2, UART2_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART2_RST, UART2_IRQn, &uart2_var},
sahilmgandhi 18:6a4db94011d3 141 {UART_3, UART3_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART3_RST, UART3_IRQn, &uart3_var},
sahilmgandhi 18:6a4db94011d3 142
sahilmgandhi 18:6a4db94011d3 143 {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
sahilmgandhi 18:6a4db94011d3 144 };
sahilmgandhi 18:6a4db94011d3 145
sahilmgandhi 18:6a4db94011d3 146 extern void mbed_sdk_init(void);
sahilmgandhi 18:6a4db94011d3 147
sahilmgandhi 18:6a4db94011d3 148 void serial_init(serial_t *obj, PinName tx, PinName rx)
sahilmgandhi 18:6a4db94011d3 149 {
sahilmgandhi 18:6a4db94011d3 150 // NOTE: With armcc, serial_init() gets called from _sys_open() timing of which is before main()/mbed_sdk_init().
sahilmgandhi 18:6a4db94011d3 151 mbed_sdk_init();
sahilmgandhi 18:6a4db94011d3 152
sahilmgandhi 18:6a4db94011d3 153 // Determine which UART_x the pins are used for
sahilmgandhi 18:6a4db94011d3 154 uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
sahilmgandhi 18:6a4db94011d3 155 uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
sahilmgandhi 18:6a4db94011d3 156 // Get the peripheral name (UART_x) from the pins and assign it to the object
sahilmgandhi 18:6a4db94011d3 157 obj->serial.uart = (UARTName) pinmap_merge(uart_tx, uart_rx);
sahilmgandhi 18:6a4db94011d3 158 MBED_ASSERT((int)obj->serial.uart != NC);
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
sahilmgandhi 18:6a4db94011d3 161 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 162 MBED_ASSERT(modinit->modname == obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 163
sahilmgandhi 18:6a4db94011d3 164 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 if (! var->ref_cnt) {
sahilmgandhi 18:6a4db94011d3 167 // Reset this module
sahilmgandhi 18:6a4db94011d3 168 SYS_ResetModule(modinit->rsetidx);
sahilmgandhi 18:6a4db94011d3 169
sahilmgandhi 18:6a4db94011d3 170 // Select IP clock source
sahilmgandhi 18:6a4db94011d3 171 CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
sahilmgandhi 18:6a4db94011d3 172 // Enable IP clock
sahilmgandhi 18:6a4db94011d3 173 CLK_EnableModuleClock(modinit->clkidx);
sahilmgandhi 18:6a4db94011d3 174
sahilmgandhi 18:6a4db94011d3 175 pinmap_pinout(tx, PinMap_UART_TX);
sahilmgandhi 18:6a4db94011d3 176 pinmap_pinout(rx, PinMap_UART_RX);
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178 obj->serial.pin_tx = tx;
sahilmgandhi 18:6a4db94011d3 179 obj->serial.pin_rx = rx;
sahilmgandhi 18:6a4db94011d3 180 }
sahilmgandhi 18:6a4db94011d3 181 var->ref_cnt ++;
sahilmgandhi 18:6a4db94011d3 182
sahilmgandhi 18:6a4db94011d3 183 // Configure the UART module and set its baudrate
sahilmgandhi 18:6a4db94011d3 184 serial_baud(obj, 9600);
sahilmgandhi 18:6a4db94011d3 185 // Configure data bits, parity, and stop bits
sahilmgandhi 18:6a4db94011d3 186 serial_format(obj, 8, ParityNone, 1);
sahilmgandhi 18:6a4db94011d3 187
sahilmgandhi 18:6a4db94011d3 188 obj->serial.vec = var->vec;
sahilmgandhi 18:6a4db94011d3 189
sahilmgandhi 18:6a4db94011d3 190 #if DEVICE_SERIAL_ASYNCH
sahilmgandhi 18:6a4db94011d3 191 obj->serial.dma_usage_tx = DMA_USAGE_NEVER;
sahilmgandhi 18:6a4db94011d3 192 obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
sahilmgandhi 18:6a4db94011d3 193 obj->serial.event = 0;
sahilmgandhi 18:6a4db94011d3 194 obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
sahilmgandhi 18:6a4db94011d3 195 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
sahilmgandhi 18:6a4db94011d3 196 #endif
sahilmgandhi 18:6a4db94011d3 197
sahilmgandhi 18:6a4db94011d3 198 // For stdio management
sahilmgandhi 18:6a4db94011d3 199 if (obj->serial.uart == STDIO_UART) {
sahilmgandhi 18:6a4db94011d3 200 stdio_uart_inited = 1;
sahilmgandhi 18:6a4db94011d3 201 memcpy(&stdio_uart, obj, sizeof(serial_t));
sahilmgandhi 18:6a4db94011d3 202 }
sahilmgandhi 18:6a4db94011d3 203
sahilmgandhi 18:6a4db94011d3 204 if (var->ref_cnt) {
sahilmgandhi 18:6a4db94011d3 205 // Mark this module to be inited.
sahilmgandhi 18:6a4db94011d3 206 int i = modinit - uart_modinit_tab;
sahilmgandhi 18:6a4db94011d3 207 uart_modinit_mask |= 1 << i;
sahilmgandhi 18:6a4db94011d3 208 }
sahilmgandhi 18:6a4db94011d3 209 }
sahilmgandhi 18:6a4db94011d3 210
sahilmgandhi 18:6a4db94011d3 211 void serial_free(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 212 {
sahilmgandhi 18:6a4db94011d3 213 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
sahilmgandhi 18:6a4db94011d3 214 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 215 MBED_ASSERT(modinit->modname == obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 216
sahilmgandhi 18:6a4db94011d3 217 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
sahilmgandhi 18:6a4db94011d3 218
sahilmgandhi 18:6a4db94011d3 219 var->ref_cnt --;
sahilmgandhi 18:6a4db94011d3 220 if (! var->ref_cnt) {
sahilmgandhi 18:6a4db94011d3 221 #if DEVICE_SERIAL_ASYNCH
sahilmgandhi 18:6a4db94011d3 222 if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
sahilmgandhi 18:6a4db94011d3 223 dma_channel_free(obj->serial.dma_chn_id_tx);
sahilmgandhi 18:6a4db94011d3 224 obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
sahilmgandhi 18:6a4db94011d3 225 }
sahilmgandhi 18:6a4db94011d3 226 if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
sahilmgandhi 18:6a4db94011d3 227 dma_channel_free(obj->serial.dma_chn_id_rx);
sahilmgandhi 18:6a4db94011d3 228 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
sahilmgandhi 18:6a4db94011d3 229 }
sahilmgandhi 18:6a4db94011d3 230 #endif
sahilmgandhi 18:6a4db94011d3 231
sahilmgandhi 18:6a4db94011d3 232 UART_Close((UART_T *) NU_MODBASE(obj->serial.uart));
sahilmgandhi 18:6a4db94011d3 233
sahilmgandhi 18:6a4db94011d3 234 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_THREIEN_Msk | UART_INTEN_RXTOIEN_Msk));
sahilmgandhi 18:6a4db94011d3 235 NVIC_DisableIRQ(modinit->irq_n);
sahilmgandhi 18:6a4db94011d3 236
sahilmgandhi 18:6a4db94011d3 237 // Disable IP clock
sahilmgandhi 18:6a4db94011d3 238 CLK_DisableModuleClock(modinit->clkidx);
sahilmgandhi 18:6a4db94011d3 239 }
sahilmgandhi 18:6a4db94011d3 240
sahilmgandhi 18:6a4db94011d3 241 if (var->obj == obj) {
sahilmgandhi 18:6a4db94011d3 242 var->obj = NULL;
sahilmgandhi 18:6a4db94011d3 243 }
sahilmgandhi 18:6a4db94011d3 244
sahilmgandhi 18:6a4db94011d3 245 if (obj->serial.uart == STDIO_UART) {
sahilmgandhi 18:6a4db94011d3 246 stdio_uart_inited = 0;
sahilmgandhi 18:6a4db94011d3 247 }
sahilmgandhi 18:6a4db94011d3 248
sahilmgandhi 18:6a4db94011d3 249 if (! var->ref_cnt) {
sahilmgandhi 18:6a4db94011d3 250 // Mark this module to be deinited.
sahilmgandhi 18:6a4db94011d3 251 int i = modinit - uart_modinit_tab;
sahilmgandhi 18:6a4db94011d3 252 uart_modinit_mask &= ~(1 << i);
sahilmgandhi 18:6a4db94011d3 253 }
sahilmgandhi 18:6a4db94011d3 254 }
sahilmgandhi 18:6a4db94011d3 255
sahilmgandhi 18:6a4db94011d3 256 void serial_baud(serial_t *obj, int baudrate) {
sahilmgandhi 18:6a4db94011d3 257 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
sahilmgandhi 18:6a4db94011d3 258 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
sahilmgandhi 18:6a4db94011d3 259
sahilmgandhi 18:6a4db94011d3 260 obj->serial.baudrate = baudrate;
sahilmgandhi 18:6a4db94011d3 261 UART_Open((UART_T *) NU_MODBASE(obj->serial.uart), baudrate);
sahilmgandhi 18:6a4db94011d3 262 }
sahilmgandhi 18:6a4db94011d3 263
sahilmgandhi 18:6a4db94011d3 264 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
sahilmgandhi 18:6a4db94011d3 265 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
sahilmgandhi 18:6a4db94011d3 266 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
sahilmgandhi 18:6a4db94011d3 267
sahilmgandhi 18:6a4db94011d3 268 // TODO: Assert for not supported parity and data bits
sahilmgandhi 18:6a4db94011d3 269 obj->serial.databits = data_bits;
sahilmgandhi 18:6a4db94011d3 270 obj->serial.parity = parity;
sahilmgandhi 18:6a4db94011d3 271 obj->serial.stopbits = stop_bits;
sahilmgandhi 18:6a4db94011d3 272
sahilmgandhi 18:6a4db94011d3 273 uint32_t databits_intern = (data_bits == 5) ? UART_WORD_LEN_5 :
sahilmgandhi 18:6a4db94011d3 274 (data_bits == 6) ? UART_WORD_LEN_6 :
sahilmgandhi 18:6a4db94011d3 275 (data_bits == 7) ? UART_WORD_LEN_7 :
sahilmgandhi 18:6a4db94011d3 276 UART_WORD_LEN_8;
sahilmgandhi 18:6a4db94011d3 277 uint32_t parity_intern = (parity == ParityOdd || parity == ParityForced1) ? UART_PARITY_ODD :
sahilmgandhi 18:6a4db94011d3 278 (parity == ParityEven || parity == ParityForced0) ? UART_PARITY_EVEN :
sahilmgandhi 18:6a4db94011d3 279 UART_PARITY_NONE;
sahilmgandhi 18:6a4db94011d3 280 uint32_t stopbits_intern = (stop_bits == 2) ? UART_STOP_BIT_2 : UART_STOP_BIT_1;
sahilmgandhi 18:6a4db94011d3 281 UART_SetLine_Config((UART_T *) NU_MODBASE(obj->serial.uart),
sahilmgandhi 18:6a4db94011d3 282 0, // Don't change baudrate
sahilmgandhi 18:6a4db94011d3 283 databits_intern,
sahilmgandhi 18:6a4db94011d3 284 parity_intern,
sahilmgandhi 18:6a4db94011d3 285 stopbits_intern);
sahilmgandhi 18:6a4db94011d3 286 }
sahilmgandhi 18:6a4db94011d3 287
sahilmgandhi 18:6a4db94011d3 288 #if DEVICE_SERIAL_FC
sahilmgandhi 18:6a4db94011d3 289
sahilmgandhi 18:6a4db94011d3 290 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
sahilmgandhi 18:6a4db94011d3 291 {
sahilmgandhi 18:6a4db94011d3 292 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 293
sahilmgandhi 18:6a4db94011d3 294 // First, disable flow control completely.
sahilmgandhi 18:6a4db94011d3 295 uart_base->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
sahilmgandhi 18:6a4db94011d3 296
sahilmgandhi 18:6a4db94011d3 297 if ((type == FlowControlRTS || type == FlowControlRTSCTS) && rxflow != NC) {
sahilmgandhi 18:6a4db94011d3 298 // Check if RTS pin matches.
sahilmgandhi 18:6a4db94011d3 299 uint32_t uart_rts = pinmap_peripheral(rxflow, PinMap_UART_RTS);
sahilmgandhi 18:6a4db94011d3 300 MBED_ASSERT(uart_rts == obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 301 // Enable the pin for RTS function
sahilmgandhi 18:6a4db94011d3 302 pinmap_pinout(rxflow, PinMap_UART_RTS);
sahilmgandhi 18:6a4db94011d3 303 // nRTS pin output is low level active
sahilmgandhi 18:6a4db94011d3 304 uart_base->MODEM |= UART_MODEM_RTSACTLV_Msk;
sahilmgandhi 18:6a4db94011d3 305 uart_base->FIFO = (uart_base->FIFO & ~UART_FIFO_RTSTRGLV_Msk) | UART_FIFO_RTSTRGLV_8BYTES;
sahilmgandhi 18:6a4db94011d3 306 // Enable RTS
sahilmgandhi 18:6a4db94011d3 307 uart_base->INTEN |= UART_INTEN_ATORTSEN_Msk;
sahilmgandhi 18:6a4db94011d3 308 }
sahilmgandhi 18:6a4db94011d3 309
sahilmgandhi 18:6a4db94011d3 310 if ((type == FlowControlCTS || type == FlowControlRTSCTS) && txflow != NC) {
sahilmgandhi 18:6a4db94011d3 311 // Check if CTS pin matches.
sahilmgandhi 18:6a4db94011d3 312 uint32_t uart_cts = pinmap_peripheral(txflow, PinMap_UART_CTS);
sahilmgandhi 18:6a4db94011d3 313 MBED_ASSERT(uart_cts == obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 314 // Enable the pin for CTS function
sahilmgandhi 18:6a4db94011d3 315 pinmap_pinout(txflow, PinMap_UART_CTS);
sahilmgandhi 18:6a4db94011d3 316 // nCTS pin input is low level active
sahilmgandhi 18:6a4db94011d3 317 uart_base->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
sahilmgandhi 18:6a4db94011d3 318 // Enable CTS
sahilmgandhi 18:6a4db94011d3 319 uart_base->INTEN |= UART_INTEN_ATOCTSEN_Msk;
sahilmgandhi 18:6a4db94011d3 320 }
sahilmgandhi 18:6a4db94011d3 321 }
sahilmgandhi 18:6a4db94011d3 322
sahilmgandhi 18:6a4db94011d3 323 #endif //DEVICE_SERIAL_FC
sahilmgandhi 18:6a4db94011d3 324
sahilmgandhi 18:6a4db94011d3 325 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
sahilmgandhi 18:6a4db94011d3 326 {
sahilmgandhi 18:6a4db94011d3 327 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
sahilmgandhi 18:6a4db94011d3 328 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
sahilmgandhi 18:6a4db94011d3 329
sahilmgandhi 18:6a4db94011d3 330 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
sahilmgandhi 18:6a4db94011d3 331 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 332 MBED_ASSERT(modinit->modname == obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 333
sahilmgandhi 18:6a4db94011d3 334 obj->serial.irq_handler = (uint32_t) handler;
sahilmgandhi 18:6a4db94011d3 335 obj->serial.irq_id = id;
sahilmgandhi 18:6a4db94011d3 336
sahilmgandhi 18:6a4db94011d3 337 // Restore sync-mode vector
sahilmgandhi 18:6a4db94011d3 338 obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec;
sahilmgandhi 18:6a4db94011d3 339 }
sahilmgandhi 18:6a4db94011d3 340
sahilmgandhi 18:6a4db94011d3 341 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
sahilmgandhi 18:6a4db94011d3 342 {
sahilmgandhi 18:6a4db94011d3 343 if (enable) {
sahilmgandhi 18:6a4db94011d3 344 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
sahilmgandhi 18:6a4db94011d3 345 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 346 MBED_ASSERT(modinit->modname == obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 347
sahilmgandhi 18:6a4db94011d3 348 NVIC_SetVector(modinit->irq_n, (uint32_t) obj->serial.vec);
sahilmgandhi 18:6a4db94011d3 349 NVIC_EnableIRQ(modinit->irq_n);
sahilmgandhi 18:6a4db94011d3 350
sahilmgandhi 18:6a4db94011d3 351 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
sahilmgandhi 18:6a4db94011d3 352 // Multiple serial S/W objects for single UART H/W module possibly.
sahilmgandhi 18:6a4db94011d3 353 // Bind serial S/W object to UART H/W module as interrupt is enabled.
sahilmgandhi 18:6a4db94011d3 354 var->obj = obj;
sahilmgandhi 18:6a4db94011d3 355
sahilmgandhi 18:6a4db94011d3 356 switch (irq) {
sahilmgandhi 18:6a4db94011d3 357 // NOTE: Setting inten_msk first to avoid race condition
sahilmgandhi 18:6a4db94011d3 358 case RxIrq:
sahilmgandhi 18:6a4db94011d3 359 obj->serial.inten_msk = obj->serial.inten_msk | (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
sahilmgandhi 18:6a4db94011d3 360 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
sahilmgandhi 18:6a4db94011d3 361 break;
sahilmgandhi 18:6a4db94011d3 362 case TxIrq:
sahilmgandhi 18:6a4db94011d3 363 obj->serial.inten_msk = obj->serial.inten_msk | UART_INTEN_THREIEN_Msk;
sahilmgandhi 18:6a4db94011d3 364 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
sahilmgandhi 18:6a4db94011d3 365 break;
sahilmgandhi 18:6a4db94011d3 366 }
sahilmgandhi 18:6a4db94011d3 367 } else { // disable
sahilmgandhi 18:6a4db94011d3 368 switch (irq) {
sahilmgandhi 18:6a4db94011d3 369 case RxIrq:
sahilmgandhi 18:6a4db94011d3 370 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
sahilmgandhi 18:6a4db94011d3 371 obj->serial.inten_msk = obj->serial.inten_msk & ~(UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
sahilmgandhi 18:6a4db94011d3 372 break;
sahilmgandhi 18:6a4db94011d3 373 case TxIrq:
sahilmgandhi 18:6a4db94011d3 374 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
sahilmgandhi 18:6a4db94011d3 375 obj->serial.inten_msk = obj->serial.inten_msk & ~UART_INTEN_THREIEN_Msk;
sahilmgandhi 18:6a4db94011d3 376 break;
sahilmgandhi 18:6a4db94011d3 377 }
sahilmgandhi 18:6a4db94011d3 378 }
sahilmgandhi 18:6a4db94011d3 379 }
sahilmgandhi 18:6a4db94011d3 380
sahilmgandhi 18:6a4db94011d3 381 int serial_getc(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 382 {
sahilmgandhi 18:6a4db94011d3 383 // TODO: Fix every byte access requires accompaniness of one interrupt. This degrades performance much.
sahilmgandhi 18:6a4db94011d3 384 while (! serial_readable(obj));
sahilmgandhi 18:6a4db94011d3 385 int c = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
sahilmgandhi 18:6a4db94011d3 386
sahilmgandhi 18:6a4db94011d3 387 // Simulate clear of the interrupt flag
sahilmgandhi 18:6a4db94011d3 388 if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
sahilmgandhi 18:6a4db94011d3 389 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
sahilmgandhi 18:6a4db94011d3 390 }
sahilmgandhi 18:6a4db94011d3 391
sahilmgandhi 18:6a4db94011d3 392 return c;
sahilmgandhi 18:6a4db94011d3 393 }
sahilmgandhi 18:6a4db94011d3 394
sahilmgandhi 18:6a4db94011d3 395 void serial_putc(serial_t *obj, int c)
sahilmgandhi 18:6a4db94011d3 396 {
sahilmgandhi 18:6a4db94011d3 397 // TODO: Fix every byte access requires accompaniness of one interrupt. This degrades performance much.
sahilmgandhi 18:6a4db94011d3 398 while (! serial_writable(obj));
sahilmgandhi 18:6a4db94011d3 399 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), c);
sahilmgandhi 18:6a4db94011d3 400
sahilmgandhi 18:6a4db94011d3 401 // Simulate clear of the interrupt flag
sahilmgandhi 18:6a4db94011d3 402 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
sahilmgandhi 18:6a4db94011d3 403 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
sahilmgandhi 18:6a4db94011d3 404 }
sahilmgandhi 18:6a4db94011d3 405 }
sahilmgandhi 18:6a4db94011d3 406
sahilmgandhi 18:6a4db94011d3 407 int serial_readable(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 408 {
sahilmgandhi 18:6a4db94011d3 409 //return UART_IS_RX_READY(((UART_T *) NU_MODBASE(obj->serial.uart)));
sahilmgandhi 18:6a4db94011d3 410 return ! UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
sahilmgandhi 18:6a4db94011d3 411 }
sahilmgandhi 18:6a4db94011d3 412
sahilmgandhi 18:6a4db94011d3 413 int serial_writable(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 414 {
sahilmgandhi 18:6a4db94011d3 415 return ! UART_IS_TX_FULL(((UART_T *) NU_MODBASE(obj->serial.uart)));
sahilmgandhi 18:6a4db94011d3 416 }
sahilmgandhi 18:6a4db94011d3 417
sahilmgandhi 18:6a4db94011d3 418 void serial_pinout_tx(PinName tx)
sahilmgandhi 18:6a4db94011d3 419 {
sahilmgandhi 18:6a4db94011d3 420 pinmap_pinout(tx, PinMap_UART_TX);
sahilmgandhi 18:6a4db94011d3 421 }
sahilmgandhi 18:6a4db94011d3 422
sahilmgandhi 18:6a4db94011d3 423 void serial_break_set(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 424 {
sahilmgandhi 18:6a4db94011d3 425 ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE |= UART_LINE_BCB_Msk;
sahilmgandhi 18:6a4db94011d3 426 }
sahilmgandhi 18:6a4db94011d3 427
sahilmgandhi 18:6a4db94011d3 428 void serial_break_clear(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 429 {
sahilmgandhi 18:6a4db94011d3 430 ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE &= ~UART_LINE_BCB_Msk;
sahilmgandhi 18:6a4db94011d3 431 }
sahilmgandhi 18:6a4db94011d3 432
sahilmgandhi 18:6a4db94011d3 433 static void uart0_vec(void)
sahilmgandhi 18:6a4db94011d3 434 {
sahilmgandhi 18:6a4db94011d3 435 uart_irq(uart0_var.obj);
sahilmgandhi 18:6a4db94011d3 436 }
sahilmgandhi 18:6a4db94011d3 437
sahilmgandhi 18:6a4db94011d3 438 static void uart1_vec(void)
sahilmgandhi 18:6a4db94011d3 439 {
sahilmgandhi 18:6a4db94011d3 440 uart_irq(uart1_var.obj);
sahilmgandhi 18:6a4db94011d3 441 }
sahilmgandhi 18:6a4db94011d3 442
sahilmgandhi 18:6a4db94011d3 443 static void uart2_vec(void)
sahilmgandhi 18:6a4db94011d3 444 {
sahilmgandhi 18:6a4db94011d3 445 uart_irq(uart2_var.obj);
sahilmgandhi 18:6a4db94011d3 446 }
sahilmgandhi 18:6a4db94011d3 447
sahilmgandhi 18:6a4db94011d3 448 static void uart3_vec(void)
sahilmgandhi 18:6a4db94011d3 449 {
sahilmgandhi 18:6a4db94011d3 450 uart_irq(uart3_var.obj);
sahilmgandhi 18:6a4db94011d3 451 }
sahilmgandhi 18:6a4db94011d3 452
sahilmgandhi 18:6a4db94011d3 453 static void uart_irq(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 454 {
sahilmgandhi 18:6a4db94011d3 455 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 456
sahilmgandhi 18:6a4db94011d3 457 if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
sahilmgandhi 18:6a4db94011d3 458 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
sahilmgandhi 18:6a4db94011d3 459 UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
sahilmgandhi 18:6a4db94011d3 460 if (obj->serial.irq_handler) {
sahilmgandhi 18:6a4db94011d3 461 ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, RxIrq);
sahilmgandhi 18:6a4db94011d3 462 }
sahilmgandhi 18:6a4db94011d3 463 }
sahilmgandhi 18:6a4db94011d3 464
sahilmgandhi 18:6a4db94011d3 465 if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
sahilmgandhi 18:6a4db94011d3 466 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
sahilmgandhi 18:6a4db94011d3 467 UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
sahilmgandhi 18:6a4db94011d3 468 if (obj->serial.irq_handler) {
sahilmgandhi 18:6a4db94011d3 469 ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, TxIrq);
sahilmgandhi 18:6a4db94011d3 470 }
sahilmgandhi 18:6a4db94011d3 471 }
sahilmgandhi 18:6a4db94011d3 472
sahilmgandhi 18:6a4db94011d3 473 // FIXME: Ignore all other interrupt flags. Clear them. Otherwise, program will get stuck in interrupt.
sahilmgandhi 18:6a4db94011d3 474 uart_base->INTSTS = uart_base->INTSTS;
sahilmgandhi 18:6a4db94011d3 475 uart_base->FIFOSTS = uart_base->FIFOSTS;
sahilmgandhi 18:6a4db94011d3 476 }
sahilmgandhi 18:6a4db94011d3 477
sahilmgandhi 18:6a4db94011d3 478
sahilmgandhi 18:6a4db94011d3 479 #if DEVICE_SERIAL_ASYNCH
sahilmgandhi 18:6a4db94011d3 480 int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
sahilmgandhi 18:6a4db94011d3 481 {
sahilmgandhi 18:6a4db94011d3 482 MBED_ASSERT(tx_width == 8 || tx_width == 16 || tx_width == 32);
sahilmgandhi 18:6a4db94011d3 483
sahilmgandhi 18:6a4db94011d3 484 obj->serial.dma_usage_tx = hint;
sahilmgandhi 18:6a4db94011d3 485 serial_check_dma_usage(&obj->serial.dma_usage_tx, &obj->serial.dma_chn_id_tx);
sahilmgandhi 18:6a4db94011d3 486
sahilmgandhi 18:6a4db94011d3 487 // UART IRQ is necessary for both interrupt way and DMA way
sahilmgandhi 18:6a4db94011d3 488 serial_tx_enable_event(obj, event, 1);
sahilmgandhi 18:6a4db94011d3 489 serial_tx_buffer_set(obj, tx, tx_length, tx_width);
sahilmgandhi 18:6a4db94011d3 490 //UART_HAL_DisableTransmitter(obj->serial.address);
sahilmgandhi 18:6a4db94011d3 491 //UART_HAL_FlushTxFifo(obj->serial.address);
sahilmgandhi 18:6a4db94011d3 492 //UART_HAL_EnableTransmitter(obj->serial.address);
sahilmgandhi 18:6a4db94011d3 493
sahilmgandhi 18:6a4db94011d3 494 int n_word = 0;
sahilmgandhi 18:6a4db94011d3 495 if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
sahilmgandhi 18:6a4db94011d3 496 // Interrupt way
sahilmgandhi 18:6a4db94011d3 497 n_word = serial_write_async(obj);
sahilmgandhi 18:6a4db94011d3 498 serial_tx_enable_interrupt(obj, handler, 1);
sahilmgandhi 18:6a4db94011d3 499 } else {
sahilmgandhi 18:6a4db94011d3 500 // DMA way
sahilmgandhi 18:6a4db94011d3 501 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
sahilmgandhi 18:6a4db94011d3 502 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 503 MBED_ASSERT(modinit->modname == obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 504
sahilmgandhi 18:6a4db94011d3 505 PDMA_T *pdma_base = dma_modbase();
sahilmgandhi 18:6a4db94011d3 506
sahilmgandhi 18:6a4db94011d3 507 pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_tx; // Enable this DMA channel
sahilmgandhi 18:6a4db94011d3 508 PDMA_SetTransferMode(obj->serial.dma_chn_id_tx,
sahilmgandhi 18:6a4db94011d3 509 ((struct nu_uart_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA
sahilmgandhi 18:6a4db94011d3 510 0, // Scatter-gather disabled
sahilmgandhi 18:6a4db94011d3 511 0); // Scatter-gather descriptor address
sahilmgandhi 18:6a4db94011d3 512 PDMA_SetTransferCnt(obj->serial.dma_chn_id_tx,
sahilmgandhi 18:6a4db94011d3 513 (tx_width == 8) ? PDMA_WIDTH_8 : (tx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
sahilmgandhi 18:6a4db94011d3 514 tx_length);
sahilmgandhi 18:6a4db94011d3 515 PDMA_SetTransferAddr(obj->serial.dma_chn_id_tx,
sahilmgandhi 18:6a4db94011d3 516 (uint32_t) tx, // NOTE:
sahilmgandhi 18:6a4db94011d3 517 // NUC472: End of source address
sahilmgandhi 18:6a4db94011d3 518 // M451: Start of source address
sahilmgandhi 18:6a4db94011d3 519 PDMA_SAR_INC, // Source address incremental
sahilmgandhi 18:6a4db94011d3 520 (uint32_t) NU_MODBASE(obj->serial.uart), // Destination address
sahilmgandhi 18:6a4db94011d3 521 PDMA_DAR_FIX); // Destination address fixed
sahilmgandhi 18:6a4db94011d3 522 PDMA_SetBurstType(obj->serial.dma_chn_id_tx,
sahilmgandhi 18:6a4db94011d3 523 PDMA_REQ_SINGLE, // Single mode
sahilmgandhi 18:6a4db94011d3 524 0); // Burst size
sahilmgandhi 18:6a4db94011d3 525 PDMA_EnableInt(obj->serial.dma_chn_id_tx,
sahilmgandhi 18:6a4db94011d3 526 PDMA_INT_TRANS_DONE); // Interrupt type
sahilmgandhi 18:6a4db94011d3 527 // Register DMA event handler
sahilmgandhi 18:6a4db94011d3 528 dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
sahilmgandhi 18:6a4db94011d3 529 serial_tx_enable_interrupt(obj, handler, 1);
sahilmgandhi 18:6a4db94011d3 530 ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_TXPDMAEN_Msk; // Start DMA transfer
sahilmgandhi 18:6a4db94011d3 531 }
sahilmgandhi 18:6a4db94011d3 532
sahilmgandhi 18:6a4db94011d3 533 return n_word;
sahilmgandhi 18:6a4db94011d3 534 }
sahilmgandhi 18:6a4db94011d3 535
sahilmgandhi 18:6a4db94011d3 536 void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
sahilmgandhi 18:6a4db94011d3 537 {
sahilmgandhi 18:6a4db94011d3 538 MBED_ASSERT(rx_width == 8 || rx_width == 16 || rx_width == 32);
sahilmgandhi 18:6a4db94011d3 539
sahilmgandhi 18:6a4db94011d3 540 obj->serial.dma_usage_rx = hint;
sahilmgandhi 18:6a4db94011d3 541 serial_check_dma_usage(&obj->serial.dma_usage_rx, &obj->serial.dma_chn_id_rx);
sahilmgandhi 18:6a4db94011d3 542 // DMA doesn't support char match, so fall back to IRQ if it is requested.
sahilmgandhi 18:6a4db94011d3 543 if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER &&
sahilmgandhi 18:6a4db94011d3 544 (event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
sahilmgandhi 18:6a4db94011d3 545 char_match != SERIAL_RESERVED_CHAR_MATCH) {
sahilmgandhi 18:6a4db94011d3 546 obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
sahilmgandhi 18:6a4db94011d3 547 dma_channel_free(obj->serial.dma_chn_id_rx);
sahilmgandhi 18:6a4db94011d3 548 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
sahilmgandhi 18:6a4db94011d3 549 }
sahilmgandhi 18:6a4db94011d3 550
sahilmgandhi 18:6a4db94011d3 551 // UART IRQ is necessary for both interrupt way and DMA way
sahilmgandhi 18:6a4db94011d3 552 serial_rx_enable_event(obj, event, 1);
sahilmgandhi 18:6a4db94011d3 553 serial_rx_buffer_set(obj, rx, rx_length, rx_width);
sahilmgandhi 18:6a4db94011d3 554 serial_rx_set_char_match(obj, char_match);
sahilmgandhi 18:6a4db94011d3 555 //UART_HAL_DisableReceiver(obj->serial.address);
sahilmgandhi 18:6a4db94011d3 556 //UART_HAL_FlushRxFifo(obj->serial.address);
sahilmgandhi 18:6a4db94011d3 557 //UART_HAL_EnableReceiver(obj->serial.address);
sahilmgandhi 18:6a4db94011d3 558
sahilmgandhi 18:6a4db94011d3 559 if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
sahilmgandhi 18:6a4db94011d3 560 // Interrupt way
sahilmgandhi 18:6a4db94011d3 561 serial_rx_enable_interrupt(obj, handler, 1);
sahilmgandhi 18:6a4db94011d3 562 } else {
sahilmgandhi 18:6a4db94011d3 563 // DMA way
sahilmgandhi 18:6a4db94011d3 564 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
sahilmgandhi 18:6a4db94011d3 565 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 566 MBED_ASSERT(modinit->modname == obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 567
sahilmgandhi 18:6a4db94011d3 568 PDMA_T *pdma_base = dma_modbase();
sahilmgandhi 18:6a4db94011d3 569
sahilmgandhi 18:6a4db94011d3 570 pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_rx; // Enable this DMA channel
sahilmgandhi 18:6a4db94011d3 571 PDMA_SetTransferMode(obj->serial.dma_chn_id_rx,
sahilmgandhi 18:6a4db94011d3 572 ((struct nu_uart_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA
sahilmgandhi 18:6a4db94011d3 573 0, // Scatter-gather disabled
sahilmgandhi 18:6a4db94011d3 574 0); // Scatter-gather descriptor address
sahilmgandhi 18:6a4db94011d3 575 PDMA_SetTransferCnt(obj->serial.dma_chn_id_rx,
sahilmgandhi 18:6a4db94011d3 576 (rx_width == 8) ? PDMA_WIDTH_8 : (rx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
sahilmgandhi 18:6a4db94011d3 577 rx_length);
sahilmgandhi 18:6a4db94011d3 578 PDMA_SetTransferAddr(obj->serial.dma_chn_id_rx,
sahilmgandhi 18:6a4db94011d3 579 (uint32_t) NU_MODBASE(obj->serial.uart), // Source address
sahilmgandhi 18:6a4db94011d3 580 PDMA_SAR_FIX, // Source address fixed
sahilmgandhi 18:6a4db94011d3 581 (uint32_t) rx, // NOTE:
sahilmgandhi 18:6a4db94011d3 582 // NUC472: End of destination address
sahilmgandhi 18:6a4db94011d3 583 // M451: Start of destination address
sahilmgandhi 18:6a4db94011d3 584 PDMA_DAR_INC); // Destination address incremental
sahilmgandhi 18:6a4db94011d3 585 PDMA_SetBurstType(obj->serial.dma_chn_id_rx,
sahilmgandhi 18:6a4db94011d3 586 PDMA_REQ_SINGLE, // Single mode
sahilmgandhi 18:6a4db94011d3 587 0); // Burst size
sahilmgandhi 18:6a4db94011d3 588 PDMA_EnableInt(obj->serial.dma_chn_id_rx,
sahilmgandhi 18:6a4db94011d3 589 PDMA_INT_TRANS_DONE); // Interrupt type
sahilmgandhi 18:6a4db94011d3 590 // Register DMA event handler
sahilmgandhi 18:6a4db94011d3 591 dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
sahilmgandhi 18:6a4db94011d3 592 serial_rx_enable_interrupt(obj, handler, 1);
sahilmgandhi 18:6a4db94011d3 593 ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_RXPDMAEN_Msk; // Start DMA transfer
sahilmgandhi 18:6a4db94011d3 594 }
sahilmgandhi 18:6a4db94011d3 595 }
sahilmgandhi 18:6a4db94011d3 596
sahilmgandhi 18:6a4db94011d3 597 void serial_tx_abort_asynch(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 598 {
sahilmgandhi 18:6a4db94011d3 599 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
sahilmgandhi 18:6a4db94011d3 600 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
sahilmgandhi 18:6a4db94011d3 601
sahilmgandhi 18:6a4db94011d3 602 if (obj->serial.dma_usage_tx != DMA_USAGE_NEVER) {
sahilmgandhi 18:6a4db94011d3 603 PDMA_T *pdma_base = dma_modbase();
sahilmgandhi 18:6a4db94011d3 604
sahilmgandhi 18:6a4db94011d3 605 if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
sahilmgandhi 18:6a4db94011d3 606 PDMA_DisableInt(obj->serial.dma_chn_id_tx, PDMA_INT_TRANS_DONE);
sahilmgandhi 18:6a4db94011d3 607 // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
sahilmgandhi 18:6a4db94011d3 608 //PDMA_STOP(obj->serial.dma_chn_id_tx);
sahilmgandhi 18:6a4db94011d3 609 pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_tx);
sahilmgandhi 18:6a4db94011d3 610 }
sahilmgandhi 18:6a4db94011d3 611 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_TXPDMAEN_Msk);
sahilmgandhi 18:6a4db94011d3 612 }
sahilmgandhi 18:6a4db94011d3 613
sahilmgandhi 18:6a4db94011d3 614 // Necessary for both interrupt way and DMA way
sahilmgandhi 18:6a4db94011d3 615 serial_irq_set(obj, TxIrq, 0);
sahilmgandhi 18:6a4db94011d3 616 // FIXME: more complete abort operation
sahilmgandhi 18:6a4db94011d3 617 //UART_HAL_DisableTransmitter(obj->serial.serial.address);
sahilmgandhi 18:6a4db94011d3 618 //UART_HAL_FlushTxFifo(obj->serial.serial.address);
sahilmgandhi 18:6a4db94011d3 619 }
sahilmgandhi 18:6a4db94011d3 620
sahilmgandhi 18:6a4db94011d3 621 void serial_rx_abort_asynch(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 622 {
sahilmgandhi 18:6a4db94011d3 623 if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER) {
sahilmgandhi 18:6a4db94011d3 624 PDMA_T *pdma_base = dma_modbase();
sahilmgandhi 18:6a4db94011d3 625
sahilmgandhi 18:6a4db94011d3 626 if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
sahilmgandhi 18:6a4db94011d3 627 PDMA_DisableInt(obj->serial.dma_chn_id_rx, PDMA_INT_TRANS_DONE);
sahilmgandhi 18:6a4db94011d3 628 // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
sahilmgandhi 18:6a4db94011d3 629 //PDMA_STOP(obj->serial.dma_chn_id_rx);
sahilmgandhi 18:6a4db94011d3 630 pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_rx);
sahilmgandhi 18:6a4db94011d3 631 }
sahilmgandhi 18:6a4db94011d3 632 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RXPDMAEN_Msk);
sahilmgandhi 18:6a4db94011d3 633 }
sahilmgandhi 18:6a4db94011d3 634
sahilmgandhi 18:6a4db94011d3 635 // Necessary for both interrupt way and DMA way
sahilmgandhi 18:6a4db94011d3 636 serial_irq_set(obj, RxIrq, 0);
sahilmgandhi 18:6a4db94011d3 637 // FIXME: more complete abort operation
sahilmgandhi 18:6a4db94011d3 638 //UART_HAL_DisableReceiver(obj->serial.serial.address);
sahilmgandhi 18:6a4db94011d3 639 //UART_HAL_FlushRxFifo(obj->serial.serial.address);
sahilmgandhi 18:6a4db94011d3 640 }
sahilmgandhi 18:6a4db94011d3 641
sahilmgandhi 18:6a4db94011d3 642 uint8_t serial_tx_active(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 643 {
sahilmgandhi 18:6a4db94011d3 644 return serial_is_irq_en(obj, TxIrq);
sahilmgandhi 18:6a4db94011d3 645 }
sahilmgandhi 18:6a4db94011d3 646
sahilmgandhi 18:6a4db94011d3 647 uint8_t serial_rx_active(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 648 {
sahilmgandhi 18:6a4db94011d3 649 return serial_is_irq_en(obj, RxIrq);
sahilmgandhi 18:6a4db94011d3 650 }
sahilmgandhi 18:6a4db94011d3 651
sahilmgandhi 18:6a4db94011d3 652 int serial_irq_handler_asynch(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 653 {
sahilmgandhi 18:6a4db94011d3 654 int event_rx = 0;
sahilmgandhi 18:6a4db94011d3 655 int event_tx = 0;
sahilmgandhi 18:6a4db94011d3 656
sahilmgandhi 18:6a4db94011d3 657 // Necessary for both interrupt way and DMA way
sahilmgandhi 18:6a4db94011d3 658 if (serial_is_irq_en(obj, RxIrq)) {
sahilmgandhi 18:6a4db94011d3 659 event_rx = serial_rx_event_check(obj);
sahilmgandhi 18:6a4db94011d3 660 if (event_rx) {
sahilmgandhi 18:6a4db94011d3 661 serial_rx_abort_asynch(obj);
sahilmgandhi 18:6a4db94011d3 662 }
sahilmgandhi 18:6a4db94011d3 663 }
sahilmgandhi 18:6a4db94011d3 664
sahilmgandhi 18:6a4db94011d3 665 if (serial_is_irq_en(obj, TxIrq)) {
sahilmgandhi 18:6a4db94011d3 666 event_tx = serial_tx_event_check(obj);
sahilmgandhi 18:6a4db94011d3 667 if (event_tx) {
sahilmgandhi 18:6a4db94011d3 668 serial_tx_abort_asynch(obj);
sahilmgandhi 18:6a4db94011d3 669 }
sahilmgandhi 18:6a4db94011d3 670 }
sahilmgandhi 18:6a4db94011d3 671
sahilmgandhi 18:6a4db94011d3 672 return (obj->serial.event & (event_rx | event_tx));
sahilmgandhi 18:6a4db94011d3 673 }
sahilmgandhi 18:6a4db94011d3 674
sahilmgandhi 18:6a4db94011d3 675 int serial_allow_powerdown(void)
sahilmgandhi 18:6a4db94011d3 676 {
sahilmgandhi 18:6a4db94011d3 677 uint32_t modinit_mask = uart_modinit_mask;
sahilmgandhi 18:6a4db94011d3 678 while (modinit_mask) {
sahilmgandhi 18:6a4db94011d3 679 int uart_idx = nu_ctz(modinit_mask);
sahilmgandhi 18:6a4db94011d3 680 const struct nu_modinit_s *modinit = uart_modinit_tab + uart_idx;
sahilmgandhi 18:6a4db94011d3 681 if (modinit->modname != NC) {
sahilmgandhi 18:6a4db94011d3 682 UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname);
sahilmgandhi 18:6a4db94011d3 683 // Disallow entering power-down mode if Tx FIFO has data to flush
sahilmgandhi 18:6a4db94011d3 684 if (! UART_IS_TX_EMPTY((uart_base))) {
sahilmgandhi 18:6a4db94011d3 685 return 0;
sahilmgandhi 18:6a4db94011d3 686 }
sahilmgandhi 18:6a4db94011d3 687 // Disallow entering power-down mode if async Rx transfer (not PDMA) is on-going
sahilmgandhi 18:6a4db94011d3 688 if (uart_base->INTEN & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
sahilmgandhi 18:6a4db94011d3 689 return 0;
sahilmgandhi 18:6a4db94011d3 690 }
sahilmgandhi 18:6a4db94011d3 691 // Disallow entering power-down mode if async Rx transfer (PDMA) is on-going
sahilmgandhi 18:6a4db94011d3 692 if (uart_base->INTEN & UART_INTEN_RXPDMAEN_Msk) {
sahilmgandhi 18:6a4db94011d3 693 return 0;
sahilmgandhi 18:6a4db94011d3 694 }
sahilmgandhi 18:6a4db94011d3 695 }
sahilmgandhi 18:6a4db94011d3 696 modinit_mask &= ~(1 << uart_idx);
sahilmgandhi 18:6a4db94011d3 697 }
sahilmgandhi 18:6a4db94011d3 698
sahilmgandhi 18:6a4db94011d3 699 return 1;
sahilmgandhi 18:6a4db94011d3 700 }
sahilmgandhi 18:6a4db94011d3 701
sahilmgandhi 18:6a4db94011d3 702 static void uart0_vec_async(void)
sahilmgandhi 18:6a4db94011d3 703 {
sahilmgandhi 18:6a4db94011d3 704 uart_irq_async(uart0_var.obj);
sahilmgandhi 18:6a4db94011d3 705 }
sahilmgandhi 18:6a4db94011d3 706
sahilmgandhi 18:6a4db94011d3 707 static void uart1_vec_async(void)
sahilmgandhi 18:6a4db94011d3 708 {
sahilmgandhi 18:6a4db94011d3 709 uart_irq_async(uart1_var.obj);
sahilmgandhi 18:6a4db94011d3 710 }
sahilmgandhi 18:6a4db94011d3 711
sahilmgandhi 18:6a4db94011d3 712 static void uart2_vec_async(void)
sahilmgandhi 18:6a4db94011d3 713 {
sahilmgandhi 18:6a4db94011d3 714 uart_irq_async(uart2_var.obj);
sahilmgandhi 18:6a4db94011d3 715 }
sahilmgandhi 18:6a4db94011d3 716
sahilmgandhi 18:6a4db94011d3 717 static void uart3_vec_async(void)
sahilmgandhi 18:6a4db94011d3 718 {
sahilmgandhi 18:6a4db94011d3 719 uart_irq_async(uart3_var.obj);
sahilmgandhi 18:6a4db94011d3 720 }
sahilmgandhi 18:6a4db94011d3 721
sahilmgandhi 18:6a4db94011d3 722 static void uart_irq_async(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 723 {
sahilmgandhi 18:6a4db94011d3 724 if (serial_is_irq_en(obj, RxIrq)) {
sahilmgandhi 18:6a4db94011d3 725 (*obj->serial.irq_handler_rx_async)();
sahilmgandhi 18:6a4db94011d3 726 }
sahilmgandhi 18:6a4db94011d3 727 if (serial_is_irq_en(obj, TxIrq)) {
sahilmgandhi 18:6a4db94011d3 728 (*obj->serial.irq_handler_tx_async)();
sahilmgandhi 18:6a4db94011d3 729 }
sahilmgandhi 18:6a4db94011d3 730 }
sahilmgandhi 18:6a4db94011d3 731
sahilmgandhi 18:6a4db94011d3 732 static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match)
sahilmgandhi 18:6a4db94011d3 733 {
sahilmgandhi 18:6a4db94011d3 734 obj->char_match = char_match;
sahilmgandhi 18:6a4db94011d3 735 obj->char_found = 0;
sahilmgandhi 18:6a4db94011d3 736 }
sahilmgandhi 18:6a4db94011d3 737
sahilmgandhi 18:6a4db94011d3 738 static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable)
sahilmgandhi 18:6a4db94011d3 739 {
sahilmgandhi 18:6a4db94011d3 740 obj->serial.event &= ~SERIAL_EVENT_TX_MASK;
sahilmgandhi 18:6a4db94011d3 741 obj->serial.event |= (event & SERIAL_EVENT_TX_MASK);
sahilmgandhi 18:6a4db94011d3 742
sahilmgandhi 18:6a4db94011d3 743 //if (event & SERIAL_EVENT_TX_COMPLETE) {
sahilmgandhi 18:6a4db94011d3 744 //}
sahilmgandhi 18:6a4db94011d3 745 }
sahilmgandhi 18:6a4db94011d3 746
sahilmgandhi 18:6a4db94011d3 747 static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable)
sahilmgandhi 18:6a4db94011d3 748 {
sahilmgandhi 18:6a4db94011d3 749 obj->serial.event &= ~SERIAL_EVENT_RX_MASK;
sahilmgandhi 18:6a4db94011d3 750 obj->serial.event |= (event & SERIAL_EVENT_RX_MASK);
sahilmgandhi 18:6a4db94011d3 751
sahilmgandhi 18:6a4db94011d3 752 //if (event & SERIAL_EVENT_RX_COMPLETE) {
sahilmgandhi 18:6a4db94011d3 753 //}
sahilmgandhi 18:6a4db94011d3 754 //if (event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
sahilmgandhi 18:6a4db94011d3 755 //}
sahilmgandhi 18:6a4db94011d3 756 if (event & SERIAL_EVENT_RX_FRAMING_ERROR) {
sahilmgandhi 18:6a4db94011d3 757 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
sahilmgandhi 18:6a4db94011d3 758 }
sahilmgandhi 18:6a4db94011d3 759 if (event & SERIAL_EVENT_RX_PARITY_ERROR) {
sahilmgandhi 18:6a4db94011d3 760 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
sahilmgandhi 18:6a4db94011d3 761 }
sahilmgandhi 18:6a4db94011d3 762 if (event & SERIAL_EVENT_RX_OVERFLOW) {
sahilmgandhi 18:6a4db94011d3 763 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_BUFERRIEN_Msk);
sahilmgandhi 18:6a4db94011d3 764 }
sahilmgandhi 18:6a4db94011d3 765 //if (event & SERIAL_EVENT_RX_CHARACTER_MATCH) {
sahilmgandhi 18:6a4db94011d3 766 //}
sahilmgandhi 18:6a4db94011d3 767 }
sahilmgandhi 18:6a4db94011d3 768
sahilmgandhi 18:6a4db94011d3 769 static int serial_is_tx_complete(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 770 {
sahilmgandhi 18:6a4db94011d3 771 // NOTE: Exclude tx fifo empty check due to no such interrupt on DMA way
sahilmgandhi 18:6a4db94011d3 772 //return (obj->tx_buff.pos == obj->tx_buff.length) && UART_GET_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
sahilmgandhi 18:6a4db94011d3 773 // FIXME: Premature abort???
sahilmgandhi 18:6a4db94011d3 774 return (obj->tx_buff.pos == obj->tx_buff.length);
sahilmgandhi 18:6a4db94011d3 775 }
sahilmgandhi 18:6a4db94011d3 776
sahilmgandhi 18:6a4db94011d3 777 static int serial_is_rx_complete(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 778 {
sahilmgandhi 18:6a4db94011d3 779 //return (obj->rx_buff.pos == obj->rx_buff.length) && UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
sahilmgandhi 18:6a4db94011d3 780 return (obj->rx_buff.pos == obj->rx_buff.length);
sahilmgandhi 18:6a4db94011d3 781 }
sahilmgandhi 18:6a4db94011d3 782
sahilmgandhi 18:6a4db94011d3 783 static uint32_t serial_tx_event_check(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 784 {
sahilmgandhi 18:6a4db94011d3 785 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 786
sahilmgandhi 18:6a4db94011d3 787 if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
sahilmgandhi 18:6a4db94011d3 788 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
sahilmgandhi 18:6a4db94011d3 789 UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
sahilmgandhi 18:6a4db94011d3 790 }
sahilmgandhi 18:6a4db94011d3 791
sahilmgandhi 18:6a4db94011d3 792 uint32_t event = 0;
sahilmgandhi 18:6a4db94011d3 793
sahilmgandhi 18:6a4db94011d3 794 if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
sahilmgandhi 18:6a4db94011d3 795 serial_write_async(obj);
sahilmgandhi 18:6a4db94011d3 796 }
sahilmgandhi 18:6a4db94011d3 797
sahilmgandhi 18:6a4db94011d3 798 if (serial_is_tx_complete(obj)) {
sahilmgandhi 18:6a4db94011d3 799 event |= SERIAL_EVENT_TX_COMPLETE;
sahilmgandhi 18:6a4db94011d3 800 }
sahilmgandhi 18:6a4db94011d3 801
sahilmgandhi 18:6a4db94011d3 802 return event;
sahilmgandhi 18:6a4db94011d3 803 }
sahilmgandhi 18:6a4db94011d3 804
sahilmgandhi 18:6a4db94011d3 805 static uint32_t serial_rx_event_check(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 806 {
sahilmgandhi 18:6a4db94011d3 807 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 808
sahilmgandhi 18:6a4db94011d3 809 if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
sahilmgandhi 18:6a4db94011d3 810 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
sahilmgandhi 18:6a4db94011d3 811 UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
sahilmgandhi 18:6a4db94011d3 812 }
sahilmgandhi 18:6a4db94011d3 813
sahilmgandhi 18:6a4db94011d3 814 uint32_t event = 0;
sahilmgandhi 18:6a4db94011d3 815
sahilmgandhi 18:6a4db94011d3 816 if (uart_base->FIFOSTS & UART_FIFOSTS_BIF_Msk) {
sahilmgandhi 18:6a4db94011d3 817 uart_base->FIFOSTS = UART_FIFOSTS_BIF_Msk;
sahilmgandhi 18:6a4db94011d3 818 }
sahilmgandhi 18:6a4db94011d3 819 if (uart_base->FIFOSTS & UART_FIFOSTS_FEF_Msk) {
sahilmgandhi 18:6a4db94011d3 820 uart_base->FIFOSTS = UART_FIFOSTS_FEF_Msk;
sahilmgandhi 18:6a4db94011d3 821 event |= SERIAL_EVENT_RX_FRAMING_ERROR;
sahilmgandhi 18:6a4db94011d3 822 }
sahilmgandhi 18:6a4db94011d3 823 if (uart_base->FIFOSTS & UART_FIFOSTS_PEF_Msk) {
sahilmgandhi 18:6a4db94011d3 824 uart_base->FIFOSTS = UART_FIFOSTS_PEF_Msk;
sahilmgandhi 18:6a4db94011d3 825 event |= SERIAL_EVENT_RX_PARITY_ERROR;
sahilmgandhi 18:6a4db94011d3 826 }
sahilmgandhi 18:6a4db94011d3 827
sahilmgandhi 18:6a4db94011d3 828 if (uart_base->FIFOSTS & UART_FIFOSTS_RXOVIF_Msk) {
sahilmgandhi 18:6a4db94011d3 829 uart_base->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk;
sahilmgandhi 18:6a4db94011d3 830 event |= SERIAL_EVENT_RX_OVERFLOW;
sahilmgandhi 18:6a4db94011d3 831 }
sahilmgandhi 18:6a4db94011d3 832
sahilmgandhi 18:6a4db94011d3 833 if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
sahilmgandhi 18:6a4db94011d3 834 serial_read_async(obj);
sahilmgandhi 18:6a4db94011d3 835 }
sahilmgandhi 18:6a4db94011d3 836
sahilmgandhi 18:6a4db94011d3 837 if (serial_is_rx_complete(obj)) {
sahilmgandhi 18:6a4db94011d3 838 event |= SERIAL_EVENT_RX_COMPLETE;
sahilmgandhi 18:6a4db94011d3 839 }
sahilmgandhi 18:6a4db94011d3 840 if ((obj->char_match != SERIAL_RESERVED_CHAR_MATCH) && obj->char_found) {
sahilmgandhi 18:6a4db94011d3 841 event |= SERIAL_EVENT_RX_CHARACTER_MATCH;
sahilmgandhi 18:6a4db94011d3 842 // FIXME: Timing to reset char_found?
sahilmgandhi 18:6a4db94011d3 843 //obj->char_found = 0;
sahilmgandhi 18:6a4db94011d3 844 }
sahilmgandhi 18:6a4db94011d3 845
sahilmgandhi 18:6a4db94011d3 846 return event;
sahilmgandhi 18:6a4db94011d3 847 }
sahilmgandhi 18:6a4db94011d3 848
sahilmgandhi 18:6a4db94011d3 849 static void uart_dma_handler_tx(uint32_t id, uint32_t event_dma)
sahilmgandhi 18:6a4db94011d3 850 {
sahilmgandhi 18:6a4db94011d3 851 serial_t *obj = (serial_t *) id;
sahilmgandhi 18:6a4db94011d3 852
sahilmgandhi 18:6a4db94011d3 853 // FIXME: Pass this error to caller
sahilmgandhi 18:6a4db94011d3 854 if (event_dma & DMA_EVENT_ABORT) {
sahilmgandhi 18:6a4db94011d3 855 }
sahilmgandhi 18:6a4db94011d3 856 // Expect UART IRQ will catch this transfer done event
sahilmgandhi 18:6a4db94011d3 857 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
sahilmgandhi 18:6a4db94011d3 858 obj->tx_buff.pos = obj->tx_buff.length;
sahilmgandhi 18:6a4db94011d3 859 }
sahilmgandhi 18:6a4db94011d3 860 // FIXME: Pass this error to caller
sahilmgandhi 18:6a4db94011d3 861 if (event_dma & DMA_EVENT_TIMEOUT) {
sahilmgandhi 18:6a4db94011d3 862 }
sahilmgandhi 18:6a4db94011d3 863
sahilmgandhi 18:6a4db94011d3 864 uart_irq_async(obj);
sahilmgandhi 18:6a4db94011d3 865 }
sahilmgandhi 18:6a4db94011d3 866
sahilmgandhi 18:6a4db94011d3 867 static void uart_dma_handler_rx(uint32_t id, uint32_t event_dma)
sahilmgandhi 18:6a4db94011d3 868 {
sahilmgandhi 18:6a4db94011d3 869 serial_t *obj = (serial_t *) id;
sahilmgandhi 18:6a4db94011d3 870
sahilmgandhi 18:6a4db94011d3 871 // FIXME: Pass this error to caller
sahilmgandhi 18:6a4db94011d3 872 if (event_dma & DMA_EVENT_ABORT) {
sahilmgandhi 18:6a4db94011d3 873 }
sahilmgandhi 18:6a4db94011d3 874 // Expect UART IRQ will catch this transfer done event
sahilmgandhi 18:6a4db94011d3 875 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
sahilmgandhi 18:6a4db94011d3 876 obj->rx_buff.pos = obj->rx_buff.length;
sahilmgandhi 18:6a4db94011d3 877 }
sahilmgandhi 18:6a4db94011d3 878 // FIXME: Pass this error to caller
sahilmgandhi 18:6a4db94011d3 879 if (event_dma & DMA_EVENT_TIMEOUT) {
sahilmgandhi 18:6a4db94011d3 880 }
sahilmgandhi 18:6a4db94011d3 881
sahilmgandhi 18:6a4db94011d3 882 uart_irq_async(obj);
sahilmgandhi 18:6a4db94011d3 883 }
sahilmgandhi 18:6a4db94011d3 884
sahilmgandhi 18:6a4db94011d3 885 static int serial_write_async(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 886 {
sahilmgandhi 18:6a4db94011d3 887 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
sahilmgandhi 18:6a4db94011d3 888 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 889 MBED_ASSERT(modinit->modname == obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 890
sahilmgandhi 18:6a4db94011d3 891 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 892
sahilmgandhi 18:6a4db94011d3 893 uint32_t tx_fifo_max = ((struct nu_uart_var *) modinit->var)->fifo_size_tx;
sahilmgandhi 18:6a4db94011d3 894 uint32_t tx_fifo_busy = (uart_base->FIFOSTS & UART_FIFOSTS_TXPTR_Msk) >> UART_FIFOSTS_TXPTR_Pos;
sahilmgandhi 18:6a4db94011d3 895 if (uart_base->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) {
sahilmgandhi 18:6a4db94011d3 896 tx_fifo_busy = tx_fifo_max;
sahilmgandhi 18:6a4db94011d3 897 }
sahilmgandhi 18:6a4db94011d3 898 uint32_t tx_fifo_free = tx_fifo_max - tx_fifo_busy;
sahilmgandhi 18:6a4db94011d3 899 if (tx_fifo_free == 0) {
sahilmgandhi 18:6a4db94011d3 900 // Simulate clear of the interrupt flag
sahilmgandhi 18:6a4db94011d3 901 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
sahilmgandhi 18:6a4db94011d3 902 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
sahilmgandhi 18:6a4db94011d3 903 }
sahilmgandhi 18:6a4db94011d3 904 return 0;
sahilmgandhi 18:6a4db94011d3 905 }
sahilmgandhi 18:6a4db94011d3 906
sahilmgandhi 18:6a4db94011d3 907 uint32_t bytes_per_word = obj->tx_buff.width / 8;
sahilmgandhi 18:6a4db94011d3 908
sahilmgandhi 18:6a4db94011d3 909 uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos;
sahilmgandhi 18:6a4db94011d3 910 int n_words = 0;
sahilmgandhi 18:6a4db94011d3 911 while (obj->tx_buff.pos < obj->tx_buff.length && tx_fifo_free >= bytes_per_word) {
sahilmgandhi 18:6a4db94011d3 912 switch (bytes_per_word) {
sahilmgandhi 18:6a4db94011d3 913 case 4:
sahilmgandhi 18:6a4db94011d3 914 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
sahilmgandhi 18:6a4db94011d3 915 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
sahilmgandhi 18:6a4db94011d3 916 case 2:
sahilmgandhi 18:6a4db94011d3 917 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
sahilmgandhi 18:6a4db94011d3 918 case 1:
sahilmgandhi 18:6a4db94011d3 919 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
sahilmgandhi 18:6a4db94011d3 920 }
sahilmgandhi 18:6a4db94011d3 921
sahilmgandhi 18:6a4db94011d3 922 n_words ++;
sahilmgandhi 18:6a4db94011d3 923 tx_fifo_free -= bytes_per_word;
sahilmgandhi 18:6a4db94011d3 924 obj->tx_buff.pos ++;
sahilmgandhi 18:6a4db94011d3 925 }
sahilmgandhi 18:6a4db94011d3 926
sahilmgandhi 18:6a4db94011d3 927 if (n_words) {
sahilmgandhi 18:6a4db94011d3 928 // Simulate clear of the interrupt flag
sahilmgandhi 18:6a4db94011d3 929 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
sahilmgandhi 18:6a4db94011d3 930 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
sahilmgandhi 18:6a4db94011d3 931 }
sahilmgandhi 18:6a4db94011d3 932 }
sahilmgandhi 18:6a4db94011d3 933
sahilmgandhi 18:6a4db94011d3 934 return n_words;
sahilmgandhi 18:6a4db94011d3 935 }
sahilmgandhi 18:6a4db94011d3 936
sahilmgandhi 18:6a4db94011d3 937 static int serial_read_async(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 938 {
sahilmgandhi 18:6a4db94011d3 939 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
sahilmgandhi 18:6a4db94011d3 940 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 941 MBED_ASSERT(modinit->modname == obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 942
sahilmgandhi 18:6a4db94011d3 943 uint32_t rx_fifo_busy = (((UART_T *) NU_MODBASE(obj->serial.uart))->FIFOSTS & UART_FIFOSTS_RXPTR_Msk) >> UART_FIFOSTS_RXPTR_Pos;
sahilmgandhi 18:6a4db94011d3 944 //uint32_t rx_fifo_free = ((struct nu_uart_var *) modinit->var)->fifo_size_rx - rx_fifo_busy;
sahilmgandhi 18:6a4db94011d3 945 //if (rx_fifo_free == 0) {
sahilmgandhi 18:6a4db94011d3 946 // return 0;
sahilmgandhi 18:6a4db94011d3 947 //}
sahilmgandhi 18:6a4db94011d3 948
sahilmgandhi 18:6a4db94011d3 949 uint32_t bytes_per_word = obj->rx_buff.width / 8;
sahilmgandhi 18:6a4db94011d3 950
sahilmgandhi 18:6a4db94011d3 951 uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos;
sahilmgandhi 18:6a4db94011d3 952 int n_words = 0;
sahilmgandhi 18:6a4db94011d3 953 while (obj->rx_buff.pos < obj->rx_buff.length && rx_fifo_busy >= bytes_per_word) {
sahilmgandhi 18:6a4db94011d3 954 switch (bytes_per_word) {
sahilmgandhi 18:6a4db94011d3 955 case 4:
sahilmgandhi 18:6a4db94011d3 956 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
sahilmgandhi 18:6a4db94011d3 957 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
sahilmgandhi 18:6a4db94011d3 958 case 2:
sahilmgandhi 18:6a4db94011d3 959 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
sahilmgandhi 18:6a4db94011d3 960 case 1:
sahilmgandhi 18:6a4db94011d3 961 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
sahilmgandhi 18:6a4db94011d3 962 }
sahilmgandhi 18:6a4db94011d3 963
sahilmgandhi 18:6a4db94011d3 964 n_words ++;
sahilmgandhi 18:6a4db94011d3 965 rx_fifo_busy -= bytes_per_word;
sahilmgandhi 18:6a4db94011d3 966 obj->rx_buff.pos ++;
sahilmgandhi 18:6a4db94011d3 967
sahilmgandhi 18:6a4db94011d3 968 if ((obj->serial.event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
sahilmgandhi 18:6a4db94011d3 969 obj->char_match != SERIAL_RESERVED_CHAR_MATCH) {
sahilmgandhi 18:6a4db94011d3 970 uint8_t *rx_cmp = rx;
sahilmgandhi 18:6a4db94011d3 971 switch (bytes_per_word) {
sahilmgandhi 18:6a4db94011d3 972 case 4:
sahilmgandhi 18:6a4db94011d3 973 rx_cmp -= 2;
sahilmgandhi 18:6a4db94011d3 974 case 2:
sahilmgandhi 18:6a4db94011d3 975 rx_cmp --;
sahilmgandhi 18:6a4db94011d3 976 case 1:
sahilmgandhi 18:6a4db94011d3 977 rx_cmp --;
sahilmgandhi 18:6a4db94011d3 978 }
sahilmgandhi 18:6a4db94011d3 979 if (*rx_cmp == obj->char_match) {
sahilmgandhi 18:6a4db94011d3 980 obj->char_found = 1;
sahilmgandhi 18:6a4db94011d3 981 break;
sahilmgandhi 18:6a4db94011d3 982 }
sahilmgandhi 18:6a4db94011d3 983 }
sahilmgandhi 18:6a4db94011d3 984 }
sahilmgandhi 18:6a4db94011d3 985
sahilmgandhi 18:6a4db94011d3 986 if (n_words) {
sahilmgandhi 18:6a4db94011d3 987 // Simulate clear of the interrupt flag
sahilmgandhi 18:6a4db94011d3 988 if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
sahilmgandhi 18:6a4db94011d3 989 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
sahilmgandhi 18:6a4db94011d3 990 }
sahilmgandhi 18:6a4db94011d3 991 }
sahilmgandhi 18:6a4db94011d3 992
sahilmgandhi 18:6a4db94011d3 993 return n_words;
sahilmgandhi 18:6a4db94011d3 994 }
sahilmgandhi 18:6a4db94011d3 995
sahilmgandhi 18:6a4db94011d3 996 static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width)
sahilmgandhi 18:6a4db94011d3 997 {
sahilmgandhi 18:6a4db94011d3 998 obj->tx_buff.buffer = (void *) tx;
sahilmgandhi 18:6a4db94011d3 999 obj->tx_buff.length = length;
sahilmgandhi 18:6a4db94011d3 1000 obj->tx_buff.pos = 0;
sahilmgandhi 18:6a4db94011d3 1001 obj->tx_buff.width = width;
sahilmgandhi 18:6a4db94011d3 1002 }
sahilmgandhi 18:6a4db94011d3 1003
sahilmgandhi 18:6a4db94011d3 1004 static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width)
sahilmgandhi 18:6a4db94011d3 1005 {
sahilmgandhi 18:6a4db94011d3 1006 obj->rx_buff.buffer = rx;
sahilmgandhi 18:6a4db94011d3 1007 obj->rx_buff.length = length;
sahilmgandhi 18:6a4db94011d3 1008 obj->rx_buff.pos = 0;
sahilmgandhi 18:6a4db94011d3 1009 obj->rx_buff.width = width;
sahilmgandhi 18:6a4db94011d3 1010 }
sahilmgandhi 18:6a4db94011d3 1011
sahilmgandhi 18:6a4db94011d3 1012 static void serial_tx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
sahilmgandhi 18:6a4db94011d3 1013 {
sahilmgandhi 18:6a4db94011d3 1014 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
sahilmgandhi 18:6a4db94011d3 1015 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 1016 MBED_ASSERT(modinit->modname == obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 1017
sahilmgandhi 18:6a4db94011d3 1018 // Necessary for both interrupt way and DMA way
sahilmgandhi 18:6a4db94011d3 1019 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
sahilmgandhi 18:6a4db94011d3 1020 // With our own async vector, tx/rx handlers can be different.
sahilmgandhi 18:6a4db94011d3 1021 obj->serial.vec = var->vec_async;
sahilmgandhi 18:6a4db94011d3 1022 obj->serial.irq_handler_tx_async = (void (*)(void)) handler;
sahilmgandhi 18:6a4db94011d3 1023 serial_irq_set(obj, TxIrq, enable);
sahilmgandhi 18:6a4db94011d3 1024 }
sahilmgandhi 18:6a4db94011d3 1025
sahilmgandhi 18:6a4db94011d3 1026 static void serial_rx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
sahilmgandhi 18:6a4db94011d3 1027 {
sahilmgandhi 18:6a4db94011d3 1028 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
sahilmgandhi 18:6a4db94011d3 1029 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 1030 MBED_ASSERT(modinit->modname == obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 1031
sahilmgandhi 18:6a4db94011d3 1032 // Necessary for both interrupt way and DMA way
sahilmgandhi 18:6a4db94011d3 1033 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
sahilmgandhi 18:6a4db94011d3 1034 // With our own async vector, tx/rx handlers can be different.
sahilmgandhi 18:6a4db94011d3 1035 obj->serial.vec = var->vec_async;
sahilmgandhi 18:6a4db94011d3 1036 obj->serial.irq_handler_rx_async = (void (*) (void)) handler;
sahilmgandhi 18:6a4db94011d3 1037 serial_irq_set(obj, RxIrq, enable);
sahilmgandhi 18:6a4db94011d3 1038 }
sahilmgandhi 18:6a4db94011d3 1039
sahilmgandhi 18:6a4db94011d3 1040 static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch)
sahilmgandhi 18:6a4db94011d3 1041 {
sahilmgandhi 18:6a4db94011d3 1042 if (*dma_usage != DMA_USAGE_NEVER) {
sahilmgandhi 18:6a4db94011d3 1043 if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
sahilmgandhi 18:6a4db94011d3 1044 *dma_ch = dma_channel_allocate(DMA_CAP_NONE);
sahilmgandhi 18:6a4db94011d3 1045 }
sahilmgandhi 18:6a4db94011d3 1046 if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
sahilmgandhi 18:6a4db94011d3 1047 *dma_usage = DMA_USAGE_NEVER;
sahilmgandhi 18:6a4db94011d3 1048 }
sahilmgandhi 18:6a4db94011d3 1049 }
sahilmgandhi 18:6a4db94011d3 1050 else {
sahilmgandhi 18:6a4db94011d3 1051 dma_channel_free(*dma_ch);
sahilmgandhi 18:6a4db94011d3 1052 *dma_ch = DMA_ERROR_OUT_OF_CHANNELS;
sahilmgandhi 18:6a4db94011d3 1053 }
sahilmgandhi 18:6a4db94011d3 1054 }
sahilmgandhi 18:6a4db94011d3 1055
sahilmgandhi 18:6a4db94011d3 1056 static int serial_is_irq_en(serial_t *obj, SerialIrq irq)
sahilmgandhi 18:6a4db94011d3 1057 {
sahilmgandhi 18:6a4db94011d3 1058 int inten_msk = 0;
sahilmgandhi 18:6a4db94011d3 1059
sahilmgandhi 18:6a4db94011d3 1060 switch (irq) {
sahilmgandhi 18:6a4db94011d3 1061 case RxIrq:
sahilmgandhi 18:6a4db94011d3 1062 inten_msk = obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
sahilmgandhi 18:6a4db94011d3 1063 break;
sahilmgandhi 18:6a4db94011d3 1064 case TxIrq:
sahilmgandhi 18:6a4db94011d3 1065 inten_msk = obj->serial.inten_msk & UART_INTEN_THREIEN_Msk;
sahilmgandhi 18:6a4db94011d3 1066 break;
sahilmgandhi 18:6a4db94011d3 1067 }
sahilmgandhi 18:6a4db94011d3 1068
sahilmgandhi 18:6a4db94011d3 1069 return !! inten_msk;
sahilmgandhi 18:6a4db94011d3 1070 }
sahilmgandhi 18:6a4db94011d3 1071
sahilmgandhi 18:6a4db94011d3 1072 #endif // #if DEVICE_SERIAL_ASYNCH
sahilmgandhi 18:6a4db94011d3 1073 #endif // #if DEVICE_SERIAL