Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /******************************************************************************
sahilmgandhi 18:6a4db94011d3 2 * @file system_M451Series.c
sahilmgandhi 18:6a4db94011d3 3 * @version V0.10
sahilmgandhi 18:6a4db94011d3 4 * $Revision: 11 $
sahilmgandhi 18:6a4db94011d3 5 * $Date: 15/09/02 10:02a $
sahilmgandhi 18:6a4db94011d3 6 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File for M451 Series MCU
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * @note
sahilmgandhi 18:6a4db94011d3 9 * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
sahilmgandhi 18:6a4db94011d3 10 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 11
sahilmgandhi 18:6a4db94011d3 12 #include "M451Series.h"
sahilmgandhi 18:6a4db94011d3 13
sahilmgandhi 18:6a4db94011d3 14
sahilmgandhi 18:6a4db94011d3 15 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 16 DEFINES
sahilmgandhi 18:6a4db94011d3 17 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19
sahilmgandhi 18:6a4db94011d3 20 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 21 Clock Variable definitions
sahilmgandhi 18:6a4db94011d3 22 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 23 uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
sahilmgandhi 18:6a4db94011d3 24 uint32_t CyclesPerUs = (__HSI / 1000000); /* Cycles per micro second */
sahilmgandhi 18:6a4db94011d3 25 uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */
sahilmgandhi 18:6a4db94011d3 26 uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0, __LIRC, 0, 0, 0, __HIRC};
sahilmgandhi 18:6a4db94011d3 27
sahilmgandhi 18:6a4db94011d3 28 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 29 Clock functions
sahilmgandhi 18:6a4db94011d3 30 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 31 void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */
sahilmgandhi 18:6a4db94011d3 32 {
sahilmgandhi 18:6a4db94011d3 33 #if 1
sahilmgandhi 18:6a4db94011d3 34 uint32_t u32Freq, u32ClkSrc;
sahilmgandhi 18:6a4db94011d3 35 uint32_t u32HclkDiv;
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37 /* Update PLL Clock */
sahilmgandhi 18:6a4db94011d3 38 PllClock = CLK_GetPLLClockFreq();
sahilmgandhi 18:6a4db94011d3 39
sahilmgandhi 18:6a4db94011d3 40 u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 if(u32ClkSrc == CLK_CLKSEL0_HCLKSEL_PLL)
sahilmgandhi 18:6a4db94011d3 43 {
sahilmgandhi 18:6a4db94011d3 44 /* Use PLL clock */
sahilmgandhi 18:6a4db94011d3 45 u32Freq = PllClock;
sahilmgandhi 18:6a4db94011d3 46 }
sahilmgandhi 18:6a4db94011d3 47 else
sahilmgandhi 18:6a4db94011d3 48 {
sahilmgandhi 18:6a4db94011d3 49 /* Use the clock sources directly */
sahilmgandhi 18:6a4db94011d3 50 u32Freq = gau32ClkSrcTbl[u32ClkSrc];
sahilmgandhi 18:6a4db94011d3 51 }
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1;
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 /* Update System Core Clock */
sahilmgandhi 18:6a4db94011d3 56 SystemCoreClock = u32Freq / u32HclkDiv;
sahilmgandhi 18:6a4db94011d3 57
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 //if(SystemCoreClock == 0)
sahilmgandhi 18:6a4db94011d3 60 // __BKPT(0);
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62 CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
sahilmgandhi 18:6a4db94011d3 63 #endif
sahilmgandhi 18:6a4db94011d3 64 }
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66 /**
sahilmgandhi 18:6a4db94011d3 67 * Initialize the system
sahilmgandhi 18:6a4db94011d3 68 *
sahilmgandhi 18:6a4db94011d3 69 * @param None
sahilmgandhi 18:6a4db94011d3 70 * @return None
sahilmgandhi 18:6a4db94011d3 71 *
sahilmgandhi 18:6a4db94011d3 72 * @brief Setup the microcontroller system.
sahilmgandhi 18:6a4db94011d3 73 * Initialize the System.
sahilmgandhi 18:6a4db94011d3 74 */
sahilmgandhi 18:6a4db94011d3 75 void SystemInit(void)
sahilmgandhi 18:6a4db94011d3 76 {
sahilmgandhi 18:6a4db94011d3 77 /* ToDo: add code to initialize the system
sahilmgandhi 18:6a4db94011d3 78 do not use global variables because this function is called before
sahilmgandhi 18:6a4db94011d3 79 reaching pre-main. RW section maybe overwritten afterwards. */
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 SYS_UnlockReg();
sahilmgandhi 18:6a4db94011d3 82 /* One-time POR18 */
sahilmgandhi 18:6a4db94011d3 83 if((SYS->PDID >> 12) == 0x945)
sahilmgandhi 18:6a4db94011d3 84 {
sahilmgandhi 18:6a4db94011d3 85 M32(GCR_BASE+0x14) |= BIT7;
sahilmgandhi 18:6a4db94011d3 86 }
sahilmgandhi 18:6a4db94011d3 87 /* Force to use INV type with HXT */
sahilmgandhi 18:6a4db94011d3 88 CLK->PWRCTL &= ~CLK_PWRCTL_HXTSELTYP_Msk;
sahilmgandhi 18:6a4db94011d3 89 SYS_LockReg();
sahilmgandhi 18:6a4db94011d3 90
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92 #if 0
sahilmgandhi 18:6a4db94011d3 93 // NOTE: C-runtime not initialized yet. Ensure no static memory (global variable) are accessed in this function.
sahilmgandhi 18:6a4db94011d3 94 nu_ebi_init();
sahilmgandhi 18:6a4db94011d3 95 #endif
sahilmgandhi 18:6a4db94011d3 96
sahilmgandhi 18:6a4db94011d3 97 /* FPU settings ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 98 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
sahilmgandhi 18:6a4db94011d3 99 SCB->CPACR |= ((3UL << 10 * 2) | /* set CP10 Full Access */
sahilmgandhi 18:6a4db94011d3 100 (3UL << 11 * 2)); /* set CP11 Full Access */
sahilmgandhi 18:6a4db94011d3 101 #endif
sahilmgandhi 18:6a4db94011d3 102
sahilmgandhi 18:6a4db94011d3 103 }
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105 #if 0
sahilmgandhi 18:6a4db94011d3 106 void nu_ebi_init(void)
sahilmgandhi 18:6a4db94011d3 107 {
sahilmgandhi 18:6a4db94011d3 108 // TO BE CONTINUED
sahilmgandhi 18:6a4db94011d3 109 }
sahilmgandhi 18:6a4db94011d3 110 #endif
sahilmgandhi 18:6a4db94011d3 111 /*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/