MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_sys.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file SYS.h
sahilmgandhi 18:6a4db94011d3 3 * @version V3.0
sahilmgandhi 18:6a4db94011d3 4 * $Revision 1 $
sahilmgandhi 18:6a4db94011d3 5 * $Date: 15/08/11 10:26a $
sahilmgandhi 18:6a4db94011d3 6 * @brief M451 Series SYS Header File
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * @note
sahilmgandhi 18:6a4db94011d3 9 * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
sahilmgandhi 18:6a4db94011d3 10 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 11
sahilmgandhi 18:6a4db94011d3 12 #ifndef __SYS_H__
sahilmgandhi 18:6a4db94011d3 13 #define __SYS_H__
sahilmgandhi 18:6a4db94011d3 14
sahilmgandhi 18:6a4db94011d3 15 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 16 extern "C"
sahilmgandhi 18:6a4db94011d3 17 {
sahilmgandhi 18:6a4db94011d3 18 #endif
sahilmgandhi 18:6a4db94011d3 19
sahilmgandhi 18:6a4db94011d3 20 /** @addtogroup Standard_Driver Standard Driver
sahilmgandhi 18:6a4db94011d3 21 @{
sahilmgandhi 18:6a4db94011d3 22 */
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24 /** @addtogroup SYS_Driver SYS Driver
sahilmgandhi 18:6a4db94011d3 25 @{
sahilmgandhi 18:6a4db94011d3 26 */
sahilmgandhi 18:6a4db94011d3 27
sahilmgandhi 18:6a4db94011d3 28 /** @addtogroup SYS_EXPORTED_CONSTANTS SYS Exported Constants
sahilmgandhi 18:6a4db94011d3 29 @{
sahilmgandhi 18:6a4db94011d3 30 */
sahilmgandhi 18:6a4db94011d3 31
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 34 /* Module Reset Control Resister constant definitions. */
sahilmgandhi 18:6a4db94011d3 35 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 36 #define PDMA_RST ((0x0<<24) | SYS_IPRST0_PDMARST_Pos ) /*!< Reset PDMA */
sahilmgandhi 18:6a4db94011d3 37 #define EBI_RST ((0x0<<24) | SYS_IPRST0_EBIRST_Pos ) /*!< Reset EBI */
sahilmgandhi 18:6a4db94011d3 38 #define USBH_RST ((0x0<<24) | SYS_IPRST0_USBHRST_Pos ) /*!< Reset USBH */
sahilmgandhi 18:6a4db94011d3 39 #define CRC_RST ((0x0<<24) | SYS_IPRST0_CRCRST_Pos ) /*!< Reset CRC */
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 #define GPIO_RST ((0x4<<24) | SYS_IPRST1_GPIORST_Pos ) /*!< Reset GPIO */
sahilmgandhi 18:6a4db94011d3 42 #define TMR0_RST ((0x4<<24) | SYS_IPRST1_TMR0RST_Pos ) /*!< Reset TMR0 */
sahilmgandhi 18:6a4db94011d3 43 #define TMR1_RST ((0x4<<24) | SYS_IPRST1_TMR1RST_Pos ) /*!< Reset TMR1 */
sahilmgandhi 18:6a4db94011d3 44 #define TMR2_RST ((0x4<<24) | SYS_IPRST1_TMR2RST_Pos ) /*!< Reset TMR2 */
sahilmgandhi 18:6a4db94011d3 45 #define TMR3_RST ((0x4<<24) | SYS_IPRST1_TMR3RST_Pos ) /*!< Reset TMR3 */
sahilmgandhi 18:6a4db94011d3 46 #define ACMP01_RST ((0x4<<24) | SYS_IPRST1_ACMP01RST_Pos ) /*!< Reset ACMP01 */
sahilmgandhi 18:6a4db94011d3 47 #define I2C0_RST ((0x4<<24) | SYS_IPRST1_I2C0RST_Pos ) /*!< Reset I2C0 */
sahilmgandhi 18:6a4db94011d3 48 #define I2C1_RST ((0x4<<24) | SYS_IPRST1_I2C1RST_Pos ) /*!< Reset I2C1 */
sahilmgandhi 18:6a4db94011d3 49 #define SPI0_RST ((0x4<<24) | SYS_IPRST1_SPI0RST_Pos ) /*!< Reset SPI0 */
sahilmgandhi 18:6a4db94011d3 50 #define SPI1_RST ((0x4<<24) | SYS_IPRST1_SPI1RST_Pos ) /*!< Reset SPI1 */
sahilmgandhi 18:6a4db94011d3 51 #define SPI2_RST ((0x4<<24) | SYS_IPRST1_SPI2RST_Pos ) /*!< Reset SPI2 */
sahilmgandhi 18:6a4db94011d3 52 #define UART0_RST ((0x4<<24) | SYS_IPRST1_UART0RST_Pos ) /*!< Reset UART0 */
sahilmgandhi 18:6a4db94011d3 53 #define UART1_RST ((0x4<<24) | SYS_IPRST1_UART1RST_Pos ) /*!< Reset UART1 */
sahilmgandhi 18:6a4db94011d3 54 #define UART2_RST ((0x4<<24) | SYS_IPRST1_UART2RST_Pos ) /*!< Reset UART2 */
sahilmgandhi 18:6a4db94011d3 55 #define UART3_RST ((0x4<<24) | SYS_IPRST1_UART3RST_Pos ) /*!< Reset UART3 */
sahilmgandhi 18:6a4db94011d3 56 #define CAN0_RST ((0x4<<24) | SYS_IPRST1_CAN0RST_Pos ) /*!< Reset CAN0 */
sahilmgandhi 18:6a4db94011d3 57 #define OTG_RST ((0x4<<24) | SYS_IPRST1_OTGRST_Pos ) /*!< Reset OTG */
sahilmgandhi 18:6a4db94011d3 58 #define USBD_RST ((0x4<<24) | SYS_IPRST1_USBDRST_Pos ) /*!< Reset USBD */
sahilmgandhi 18:6a4db94011d3 59 #define EADC_RST ((0x4<<24) | SYS_IPRST1_EADCRST_Pos ) /*!< Reset EADC */
sahilmgandhi 18:6a4db94011d3 60
sahilmgandhi 18:6a4db94011d3 61 #define SC0_RST ((0x8<<24) | SYS_IPRST2_SC0RST_Pos ) /*!< Reset SC0 */
sahilmgandhi 18:6a4db94011d3 62 #define DAC_RST ((0x8<<24) | SYS_IPRST2_DACRST_Pos ) /*!< Reset DAC */
sahilmgandhi 18:6a4db94011d3 63 #define PWM0_RST ((0x8<<24) | SYS_IPRST2_PWM0RST_Pos ) /*!< Reset PWM0 */
sahilmgandhi 18:6a4db94011d3 64 #define PWM1_RST ((0x8<<24) | SYS_IPRST2_PWM1RST_Pos ) /*!< Reset PWM1 */
sahilmgandhi 18:6a4db94011d3 65 #define TK_RST ((0x8<<24) | SYS_IPRST2_TKRST_Pos ) /*!< Reset TK */
sahilmgandhi 18:6a4db94011d3 66
sahilmgandhi 18:6a4db94011d3 67
sahilmgandhi 18:6a4db94011d3 68 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 69 /* Brown Out Detector Threshold Voltage Selection constant definitions. */
sahilmgandhi 18:6a4db94011d3 70 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 71 #define SYS_BODCTL_BOD_RST_EN (1UL<<SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Reset Enable */
sahilmgandhi 18:6a4db94011d3 72 #define SYS_BODCTL_BOD_INTERRUPT_EN (0UL<<SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 73 #define SYS_BODCTL_BODVL_4_5V (3UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 4.5V */
sahilmgandhi 18:6a4db94011d3 74 #define SYS_BODCTL_BODVL_3_7V (2UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 3.7V */
sahilmgandhi 18:6a4db94011d3 75 #define SYS_BODCTL_BODVL_2_7V (1UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.7V */
sahilmgandhi 18:6a4db94011d3 76 #define SYS_BODCTL_BODVL_2_2V (0UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.2V */
sahilmgandhi 18:6a4db94011d3 77
sahilmgandhi 18:6a4db94011d3 78
sahilmgandhi 18:6a4db94011d3 79 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 80 /* VREFCTL constant definitions. (Write-Protection Register) */
sahilmgandhi 18:6a4db94011d3 81 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 82 #define SYS_VREFCTL_VREF_2_56V (0x3UL<<SYS_VREFCTL_VREFCTL_Pos) /*!< VOUT = 2.56V */
sahilmgandhi 18:6a4db94011d3 83 #define SYS_VREFCTL_VREF_2_048V (0x7UL<<SYS_VREFCTL_VREFCTL_Pos) /*!< VOUT = 2.048V */
sahilmgandhi 18:6a4db94011d3 84 #define SYS_VREFCTL_VREF_3_072V (0xBUL<<SYS_VREFCTL_VREFCTL_Pos) /*!< VOUT = 3.072V */
sahilmgandhi 18:6a4db94011d3 85 #define SYS_VREFCTL_VREF_4_096V (0xFUL<<SYS_VREFCTL_VREFCTL_Pos) /*!< VOUT = 4.096V */
sahilmgandhi 18:6a4db94011d3 86
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 89 /* USBPHY constant definitions. (Write-Protection Register) */
sahilmgandhi 18:6a4db94011d3 90 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 91 #define SYS_USBPHY_USBROLE_OTG_V33_EN (0x1UL<<SYS_USBPHY_LDO33EN_Pos) /*!< USB LDO33 Enabled */
sahilmgandhi 18:6a4db94011d3 92 #define SYS_USBPHY_USBROLE_STD_USBD (0x0UL<<SYS_USBPHY_USBROLE_Pos) /*!< Standard USB device */
sahilmgandhi 18:6a4db94011d3 93 #define SYS_USBPHY_USBROLE_STD_USBH (0x1UL<<SYS_USBPHY_USBROLE_Pos) /*!< Standard USB host */
sahilmgandhi 18:6a4db94011d3 94 #define SYS_USBPHY_USBROLE_ID_DEPH (0x2UL<<SYS_USBPHY_USBROLE_Pos) /*!< ID dependent device */
sahilmgandhi 18:6a4db94011d3 95 #define SYS_USBPHY_USBROLE_ON_THE_GO (0x3UL<<SYS_USBPHY_USBROLE_Pos) /*!< On-The-Go device */
sahilmgandhi 18:6a4db94011d3 96
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 99 /* Multi-Function constant definitions. */
sahilmgandhi 18:6a4db94011d3 100 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 101 /* How to use below #define?
sahilmgandhi 18:6a4db94011d3 102 Example 1: If user want to set PA.0 as SC0_CLK in initial function,
sahilmgandhi 18:6a4db94011d3 103 user can issue following command to achieve it.
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105 SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk) ) | SYS_GPA_MFPL_PA0_MFP_SC0_CLK ;
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107 */
sahilmgandhi 18:6a4db94011d3 108 //PA0 MFP
sahilmgandhi 18:6a4db94011d3 109 #define SYS_GPA_MFPL_PA0MFP_GPIO (0ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 110 #define SYS_GPA_MFPL_PA0MFP_UART1_nCTS (1ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for UART1_nCTS*/
sahilmgandhi 18:6a4db94011d3 111 #define SYS_GPA_MFPL_PA0MFP_UART1_TXD (3ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for UART1_TXD*/
sahilmgandhi 18:6a4db94011d3 112 #define SYS_GPA_MFPL_PA0MFP_CAN0_RXD (4ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for CAN0_RXD*/
sahilmgandhi 18:6a4db94011d3 113 #define SYS_GPA_MFPL_PA0MFP_SC0_CLK (5ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for SC0_CLK*/
sahilmgandhi 18:6a4db94011d3 114 #define SYS_GPA_MFPL_PA0MFP_PWM1_CH5 (6ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for PWM1_CH5*/
sahilmgandhi 18:6a4db94011d3 115 #define SYS_GPA_MFPL_PA0MFP_EBI_AD0 (7ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for EBI_AD0*/
sahilmgandhi 18:6a4db94011d3 116 #define SYS_GPA_MFPL_PA0MFP_INT0 (8ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for INT0*/
sahilmgandhi 18:6a4db94011d3 117 #define SYS_GPA_MFPL_PA0MFP_SPI1_I2SMCLK (9ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for SPI1_I2SMCLK*/
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 //PA1 MFP
sahilmgandhi 18:6a4db94011d3 120 #define SYS_GPA_MFPL_PA1MFP_GPIO (0ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 121 #define SYS_GPA_MFPL_PA1MFP_UART1_nRTS (1ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for UART1_nRTS*/
sahilmgandhi 18:6a4db94011d3 122 #define SYS_GPA_MFPL_PA1MFP_UART1_RXD (3ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for UART1_RXD*/
sahilmgandhi 18:6a4db94011d3 123 #define SYS_GPA_MFPL_PA1MFP_CAN0_TXD (4ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for CAN0_TXD*/
sahilmgandhi 18:6a4db94011d3 124 #define SYS_GPA_MFPL_PA1MFP_SC0_DAT (5ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for SC0_DAT*/
sahilmgandhi 18:6a4db94011d3 125 #define SYS_GPA_MFPL_PA1MFP_PWM1_CH4 (6ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for PWM1_CH4*/
sahilmgandhi 18:6a4db94011d3 126 #define SYS_GPA_MFPL_PA1MFP_EBI_AD1 (7ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for EBI_AD1*/
sahilmgandhi 18:6a4db94011d3 127 #define SYS_GPA_MFPL_PA1MFP_STADC (10ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for STADC*/
sahilmgandhi 18:6a4db94011d3 128
sahilmgandhi 18:6a4db94011d3 129 //PA2 MFP
sahilmgandhi 18:6a4db94011d3 130 #define SYS_GPA_MFPL_PA2MFP_GPIO (0ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 131 #define SYS_GPA_MFPL_PA2MFP_USB_VBUS_EN (1ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for USB_VBUS_EN*/
sahilmgandhi 18:6a4db94011d3 132 #define SYS_GPA_MFPL_PA2MFP_UART0_TXD (2ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for UART0_TXD*/
sahilmgandhi 18:6a4db94011d3 133 #define SYS_GPA_MFPL_PA2MFP_UART0_nCTS (3ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for UART0_nCTS*/
sahilmgandhi 18:6a4db94011d3 134 #define SYS_GPA_MFPL_PA2MFP_I2C0_SDA (4ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for I2C0_SDA*/
sahilmgandhi 18:6a4db94011d3 135 #define SYS_GPA_MFPL_PA2MFP_SC0_RST (5ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for SC0_RST*/
sahilmgandhi 18:6a4db94011d3 136 #define SYS_GPA_MFPL_PA2MFP_PWM1_CH3 (6ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for PWM1_CH3*/
sahilmgandhi 18:6a4db94011d3 137 #define SYS_GPA_MFPL_PA2MFP_EBI_AD2 (7ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for EBI_AD2*/
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139 //PA3 MFP
sahilmgandhi 18:6a4db94011d3 140 #define SYS_GPA_MFPL_PA3MFP_GPIO (0ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 141 #define SYS_GPA_MFPL_PA3MFP_USB_VBUS_ST (1ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for USB_VBUS_ST*/
sahilmgandhi 18:6a4db94011d3 142 #define SYS_GPA_MFPL_PA3MFP_UART0_RXD (2ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for UART0_RXD*/
sahilmgandhi 18:6a4db94011d3 143 #define SYS_GPA_MFPL_PA3MFP_UART0_nRTS (3ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for UART0_nRTS*/
sahilmgandhi 18:6a4db94011d3 144 #define SYS_GPA_MFPL_PA3MFP_I2C0_SCL (4ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for I2C0_SCL*/
sahilmgandhi 18:6a4db94011d3 145 #define SYS_GPA_MFPL_PA3MFP_SC0_PWR (5ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for SC0_PWR*/
sahilmgandhi 18:6a4db94011d3 146 #define SYS_GPA_MFPL_PA3MFP_PWM1_CH2 (6ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for PWM1_CH2*/
sahilmgandhi 18:6a4db94011d3 147 #define SYS_GPA_MFPL_PA3MFP_EBI_AD3 (7ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for EBI_AD3*/
sahilmgandhi 18:6a4db94011d3 148
sahilmgandhi 18:6a4db94011d3 149 //PA4 MFP
sahilmgandhi 18:6a4db94011d3 150 #define SYS_GPA_MFPL_PA4MFP_GPIO (0ul << SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 151 #define SYS_GPA_MFPL_PA4MFP_SPI1_SS (2ul << SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for SPI1_SS*/
sahilmgandhi 18:6a4db94011d3 152 #define SYS_GPA_MFPL_PA4MFP_EBI_AD4 (7ul << SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for EBI_AD4*/
sahilmgandhi 18:6a4db94011d3 153
sahilmgandhi 18:6a4db94011d3 154 //PA5 MFP
sahilmgandhi 18:6a4db94011d3 155 #define SYS_GPA_MFPL_PA5MFP_GPIO (0ul << SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 156 #define SYS_GPA_MFPL_PA5MFP_SPI1_MOSI (2ul << SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for SPI1_MOSI*/
sahilmgandhi 18:6a4db94011d3 157 #define SYS_GPA_MFPL_PA5MFP_T2_EXT (3ul << SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for T2_EXT*/
sahilmgandhi 18:6a4db94011d3 158 #define SYS_GPA_MFPL_PA5MFP_EBI_AD5 (7ul << SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for EBI_AD5*/
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 //PA6 MFP
sahilmgandhi 18:6a4db94011d3 161 #define SYS_GPA_MFPL_PA6MFP_GPIO (0ul << SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 162 #define SYS_GPA_MFPL_PA6MFP_SPI1_MISO (2ul << SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for SPI1_MISO*/
sahilmgandhi 18:6a4db94011d3 163 #define SYS_GPA_MFPL_PA6MFP_T1_EXT (3ul << SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for T1_EXT*/
sahilmgandhi 18:6a4db94011d3 164 #define SYS_GPA_MFPL_PA6MFP_EBI_AD6 (7ul << SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for EBI_AD6*/
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 //PA7 MFP
sahilmgandhi 18:6a4db94011d3 167 #define SYS_GPA_MFPL_PA7MFP_GPIO (0ul << SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 168 #define SYS_GPA_MFPL_PA7MFP_SPI1_CLK (2ul << SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for SPI1_CLK*/
sahilmgandhi 18:6a4db94011d3 169 #define SYS_GPA_MFPL_PA7MFP_T0_EXT (3ul << SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for T0_EXT*/
sahilmgandhi 18:6a4db94011d3 170 #define SYS_GPA_MFPL_PA7MFP_EBI_AD7 (7ul << SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for EBI_AD7*/
sahilmgandhi 18:6a4db94011d3 171
sahilmgandhi 18:6a4db94011d3 172 //PA8 MFP
sahilmgandhi 18:6a4db94011d3 173 #define SYS_GPA_MFPH_PA8MFP_GPIO (0ul << SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 174 #define SYS_GPA_MFPH_PA8MFP_UART3_TXD (3ul << SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for UART3_TXD*/
sahilmgandhi 18:6a4db94011d3 175
sahilmgandhi 18:6a4db94011d3 176 //PA9 MFP
sahilmgandhi 18:6a4db94011d3 177 #define SYS_GPA_MFPH_PA9MFP_GPIO (0ul << SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 178 #define SYS_GPA_MFPH_PA9MFP_UART3_RXD (3ul << SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for UART3_RXD*/
sahilmgandhi 18:6a4db94011d3 179
sahilmgandhi 18:6a4db94011d3 180 //PA10 MFP
sahilmgandhi 18:6a4db94011d3 181 #define SYS_GPA_MFPH_PA10MFP_GPIO (0ul << SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 182 #define SYS_GPA_MFPH_PA10MFP_UART3_nCTS (3ul << SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for UART3_nCTS*/
sahilmgandhi 18:6a4db94011d3 183
sahilmgandhi 18:6a4db94011d3 184 //PA11 MFP
sahilmgandhi 18:6a4db94011d3 185 #define SYS_GPA_MFPH_PA11MFP_GPIO (0ul << SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 186 #define SYS_GPA_MFPH_PA11MFP_UART3_nRTS (3ul << SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for UART3_nRTS*/
sahilmgandhi 18:6a4db94011d3 187
sahilmgandhi 18:6a4db94011d3 188 //PA12 MFP
sahilmgandhi 18:6a4db94011d3 189 #define SYS_GPA_MFPH_PA12MFP_GPIO (0ul << SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 190 #define SYS_GPA_MFPH_PA12MFP_SPI1_I2SMCLK (2ul << SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for SPI1_I2SMCLK*/
sahilmgandhi 18:6a4db94011d3 191 #define SYS_GPA_MFPH_PA12MFP_CAN0_TXD (4ul << SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for CAN0_TXD*/
sahilmgandhi 18:6a4db94011d3 192
sahilmgandhi 18:6a4db94011d3 193 //PA13 MFP
sahilmgandhi 18:6a4db94011d3 194 #define SYS_GPA_MFPH_PA13MFP_GPIO (0ul << SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 195 #define SYS_GPA_MFPH_PA13MFP_CAN0_RXD (4ul << SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for CAN0_RXD*/
sahilmgandhi 18:6a4db94011d3 196
sahilmgandhi 18:6a4db94011d3 197 //PA14 MFP
sahilmgandhi 18:6a4db94011d3 198 #define SYS_GPA_MFPH_PA14MFP_GPIO (0ul << SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 199 #define SYS_GPA_MFPH_PA14MFP_UART2_nCTS (3ul << SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for UART2_nCTS*/
sahilmgandhi 18:6a4db94011d3 200 #define SYS_GPA_MFPH_PA14MFP_I2C0_SMBAL (4ul << SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for I2C0_SMBAL*/
sahilmgandhi 18:6a4db94011d3 201
sahilmgandhi 18:6a4db94011d3 202 //PA15 MFP
sahilmgandhi 18:6a4db94011d3 203 #define SYS_GPA_MFPH_PA15MFP_GPIO (0ul << SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 204 #define SYS_GPA_MFPH_PA15MFP_UART2_nRTS (3ul << SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for UART2_nRTS*/
sahilmgandhi 18:6a4db94011d3 205 #define SYS_GPA_MFPH_PA15MFP_I2C0_SMBSUS (4ul << SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for I2C0_SMBSUS*/
sahilmgandhi 18:6a4db94011d3 206
sahilmgandhi 18:6a4db94011d3 207 //PB0 MFP
sahilmgandhi 18:6a4db94011d3 208 #define SYS_GPB_MFPL_PB0MFP_GPIO (0ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 209 #define SYS_GPB_MFPL_PB0MFP_EADC_CH0 (1ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EADC_CH0*/
sahilmgandhi 18:6a4db94011d3 210 #define SYS_GPB_MFPL_PB0MFP_SPI0_MOSI1 (2ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for SPI0_MOSI1*/
sahilmgandhi 18:6a4db94011d3 211 #define SYS_GPB_MFPL_PB0MFP_UART2_RXD (3ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for UART2_RXD*/
sahilmgandhi 18:6a4db94011d3 212 #define SYS_GPB_MFPL_PB0MFP_T2 (4ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for T2*/
sahilmgandhi 18:6a4db94011d3 213 #define SYS_GPB_MFPL_PB0MFP_DAC (5ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for DAC*/
sahilmgandhi 18:6a4db94011d3 214 #define SYS_GPB_MFPL_PB0MFP_EBI_nWRL (7ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EBI_nWRL*/
sahilmgandhi 18:6a4db94011d3 215 #define SYS_GPB_MFPL_PB0MFP_INT1 (8ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for INT1*/
sahilmgandhi 18:6a4db94011d3 216
sahilmgandhi 18:6a4db94011d3 217 //PB1 MFP
sahilmgandhi 18:6a4db94011d3 218 #define SYS_GPB_MFPL_PB1MFP_GPIO (0ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 219 #define SYS_GPB_MFPL_PB1MFP_EADC_CH1 (1ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for EADC_CH1*/
sahilmgandhi 18:6a4db94011d3 220 #define SYS_GPB_MFPL_PB1MFP_SPI0_MISO1 (2ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for SPI0_MISO1*/
sahilmgandhi 18:6a4db94011d3 221 #define SYS_GPB_MFPL_PB1MFP_UART2_TXD (3ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for UART2_TXD*/
sahilmgandhi 18:6a4db94011d3 222 #define SYS_GPB_MFPL_PB1MFP_T3 (4ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for T3*/
sahilmgandhi 18:6a4db94011d3 223 #define SYS_GPB_MFPL_PB1MFP_SC0_RST (5ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for SC0_RST*/
sahilmgandhi 18:6a4db94011d3 224 #define SYS_GPB_MFPL_PB1MFP_PWM0_SYNC_OUT (6ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for PWM0_SYNC_OUT*/
sahilmgandhi 18:6a4db94011d3 225 #define SYS_GPB_MFPL_PB1MFP_EBI_nWRH (7ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for EBI_nWRH*/
sahilmgandhi 18:6a4db94011d3 226
sahilmgandhi 18:6a4db94011d3 227 //PB2 MFP
sahilmgandhi 18:6a4db94011d3 228 #define SYS_GPB_MFPL_PB2MFP_GPIO (0ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 229 #define SYS_GPB_MFPL_PB2MFP_EADC_CH2 (1ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for EADC_CH2*/
sahilmgandhi 18:6a4db94011d3 230 #define SYS_GPB_MFPL_PB2MFP_SPI0_CLK (2ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for SPI0_CLK*/
sahilmgandhi 18:6a4db94011d3 231 #define SYS_GPB_MFPL_PB2MFP_SPI1_CLK (3ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for SPI1_CLK*/
sahilmgandhi 18:6a4db94011d3 232 #define SYS_GPB_MFPL_PB2MFP_UART1_RXD (4ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for UART1_RXD*/
sahilmgandhi 18:6a4db94011d3 233 #define SYS_GPB_MFPL_PB2MFP_SC0_CD (5ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for SC0_CD*/
sahilmgandhi 18:6a4db94011d3 234 #define SYS_GPB_MFPL_PB2MFP_UART3_RXD (9ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for UART3_RXD*/
sahilmgandhi 18:6a4db94011d3 235 #define SYS_GPB_MFPL_PB2MFP_T2_EXT (11ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for T2_EXT*/
sahilmgandhi 18:6a4db94011d3 236
sahilmgandhi 18:6a4db94011d3 237 //PB3
sahilmgandhi 18:6a4db94011d3 238 #define SYS_GPB_MFPL_PB3MFP_GPIO (0ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 239 #define SYS_GPB_MFPL_PB3MFP_EADC_CH3 (1ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for EADC_CH3*/
sahilmgandhi 18:6a4db94011d3 240 #define SYS_GPB_MFPL_PB3MFP_SPI0_MISO0 (2ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for SPI0_MISO0*/
sahilmgandhi 18:6a4db94011d3 241 #define SYS_GPB_MFPL_PB3MFP_SPI1_MISO (3ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for SPI1_MISO*/
sahilmgandhi 18:6a4db94011d3 242 #define SYS_GPB_MFPL_PB3MFP_UART1_TXD (4ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for UART1_TXD*/
sahilmgandhi 18:6a4db94011d3 243 #define SYS_GPB_MFPL_PB3MFP_UART3_TXD (9ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for UART3_TXD*/
sahilmgandhi 18:6a4db94011d3 244 #define SYS_GPB_MFPL_PB3MFP_T0_EXT (11ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for T0_EXT*/
sahilmgandhi 18:6a4db94011d3 245
sahilmgandhi 18:6a4db94011d3 246 //PB4
sahilmgandhi 18:6a4db94011d3 247 #define SYS_GPB_MFPL_PB4MFP_GPIO (0ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 248 #define SYS_GPB_MFPL_PB4MFP_EADC_CH4 (1ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for EADC_CH4*/
sahilmgandhi 18:6a4db94011d3 249 #define SYS_GPB_MFPL_PB4MFP_SPI0_SS (2ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for SPI0_SS*/
sahilmgandhi 18:6a4db94011d3 250 #define SYS_GPB_MFPL_PB4MFP_SPI1_SS (3ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for SPI1_SS*/
sahilmgandhi 18:6a4db94011d3 251 #define SYS_GPB_MFPL_PB4MFP_UART1_nCTS (4ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for UART1_nCTS*/
sahilmgandhi 18:6a4db94011d3 252 #define SYS_GPB_MFPL_PB4MFP_ACMP0_N (5ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for ACMP0_N*/
sahilmgandhi 18:6a4db94011d3 253 #define SYS_GPB_MFPL_PB4MFP_EBI_AD7 (7ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for EBI_AD7*/
sahilmgandhi 18:6a4db94011d3 254 #define SYS_GPB_MFPL_PB4MFP_UART2_TXD (9ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for UART2_TXD*/
sahilmgandhi 18:6a4db94011d3 255 #define SYS_GPB_MFPL_PB4MFP_T1_EXT (11ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for T1_EXT*/
sahilmgandhi 18:6a4db94011d3 256
sahilmgandhi 18:6a4db94011d3 257 //PB5
sahilmgandhi 18:6a4db94011d3 258 #define SYS_GPB_MFPL_PB5MFP_GPIO (0ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 259 #define SYS_GPB_MFPL_PB5MFP_EADC_CH13 (1ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for EADC_CH13*/
sahilmgandhi 18:6a4db94011d3 260 #define SYS_GPB_MFPL_PB5MFP_SPI0_MOSI0 (2ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for SPI0_MOSI0*/
sahilmgandhi 18:6a4db94011d3 261 #define SYS_GPB_MFPL_PB5MFP_SPI1_MOSI (3ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for SPI1_MOSI*/
sahilmgandhi 18:6a4db94011d3 262 #define SYS_GPB_MFPL_PB5MFP_TK3 (4ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for TK3*/
sahilmgandhi 18:6a4db94011d3 263 #define SYS_GPB_MFPL_PB5MFP_ACMP0_P2 (5ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for ACMP0_P2*/
sahilmgandhi 18:6a4db94011d3 264 #define SYS_GPB_MFPL_PB5MFP_EBI_AD6 (7ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for EBI_AD6*/
sahilmgandhi 18:6a4db94011d3 265 #define SYS_GPB_MFPL_PB5MFP_UART2_RXD (9ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for UART2_RXD*/
sahilmgandhi 18:6a4db94011d3 266
sahilmgandhi 18:6a4db94011d3 267 //PB6
sahilmgandhi 18:6a4db94011d3 268 #define SYS_GPB_MFPL_PB6MFP_GPIO (0ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 269 #define SYS_GPB_MFPL_PB6MFP_EADC_CH14 (1ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EADC_CH14*/
sahilmgandhi 18:6a4db94011d3 270 #define SYS_GPB_MFPL_PB6MFP_SPI0_MISO0 (2ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for SPI0_MISO0*/
sahilmgandhi 18:6a4db94011d3 271 #define SYS_GPB_MFPL_PB6MFP_SPI1_MISO (3ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for SPI1_MISO*/
sahilmgandhi 18:6a4db94011d3 272 #define SYS_GPB_MFPL_PB6MFP_TK4 (4ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for TK4*/
sahilmgandhi 18:6a4db94011d3 273 #define SYS_GPB_MFPL_PB6MFP_ACMP0_P1 (5ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for ACMP0_P1*/
sahilmgandhi 18:6a4db94011d3 274 #define SYS_GPB_MFPL_PB6MFP_EBI_AD5 (7ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EBI_AD5*/
sahilmgandhi 18:6a4db94011d3 275
sahilmgandhi 18:6a4db94011d3 276 //PB7
sahilmgandhi 18:6a4db94011d3 277 #define SYS_GPB_MFPL_PB7MFP_GPIO (0ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 278 #define SYS_GPB_MFPL_PB7MFP_EADC_CH15 (1ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EADC_CH15*/
sahilmgandhi 18:6a4db94011d3 279 #define SYS_GPB_MFPL_PB7MFP_SPI0_CLK (2ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for SPI0_CLK*/
sahilmgandhi 18:6a4db94011d3 280 #define SYS_GPB_MFPL_PB7MFP_SPI1_CLK (3ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for SPI1_CLK*/
sahilmgandhi 18:6a4db94011d3 281 #define SYS_GPB_MFPL_PB7MFP_TK5 (4ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for TK5*/
sahilmgandhi 18:6a4db94011d3 282 #define SYS_GPB_MFPL_PB7MFP_ACMP0_P0 (5ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for ACMP0_P0*/
sahilmgandhi 18:6a4db94011d3 283 #define SYS_GPB_MFPL_PB7MFP_EBI_AD4 (7ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EBI_AD4*/
sahilmgandhi 18:6a4db94011d3 284 #define SYS_GPB_MFPL_PB7MFP_STADC (10ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for STADC*/
sahilmgandhi 18:6a4db94011d3 285
sahilmgandhi 18:6a4db94011d3 286 //PB8
sahilmgandhi 18:6a4db94011d3 287 #define SYS_GPB_MFPH_PB8MFP_GPIO (0ul << SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 288 #define SYS_GPB_MFPH_PB8MFP_EADC_CH5 (1ul << SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for EADC_CH5*/
sahilmgandhi 18:6a4db94011d3 289 #define SYS_GPB_MFPH_PB8MFP_UART1_nRTS (4ul << SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for UART1_nRTS*/
sahilmgandhi 18:6a4db94011d3 290 #define SYS_GPB_MFPH_PB8MFP_PWM0_CH2 (6ul << SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for PWM0_CH2*/
sahilmgandhi 18:6a4db94011d3 291
sahilmgandhi 18:6a4db94011d3 292 //PB9
sahilmgandhi 18:6a4db94011d3 293 #define SYS_GPB_MFPH_PB9MFP_GPIO (0ul << SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 294 #define SYS_GPB_MFPH_PB9MFP_EADC_CH6 (1ul << SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for EADC_CH6*/
sahilmgandhi 18:6a4db94011d3 295
sahilmgandhi 18:6a4db94011d3 296 //PB10
sahilmgandhi 18:6a4db94011d3 297 #define SYS_GPB_MFPH_PB10MFP_GPIO (0ul << SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH_ PB10 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 298 #define SYS_GPB_MFPH_PB10MFP_EADC_CH7 (1ul << SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH_ PB10 setting for EADC_CH7*/
sahilmgandhi 18:6a4db94011d3 299
sahilmgandhi 18:6a4db94011d3 300 //PB11
sahilmgandhi 18:6a4db94011d3 301 #define SYS_GPB_MFPH_PB11MFP_GPIO (0ul << SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH_ PB11 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 302 #define SYS_GPB_MFPH_PB11MFP_EADC_CH8 (1ul << SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH_ PB11 setting for EADC_CH8*/
sahilmgandhi 18:6a4db94011d3 303 #define SYS_GPB_MFPH_PB11MFP_TK0 (4ul << SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH_ PB11 setting for TK0*/
sahilmgandhi 18:6a4db94011d3 304
sahilmgandhi 18:6a4db94011d3 305 //PB12
sahilmgandhi 18:6a4db94011d3 306 #define SYS_GPB_MFPH_PB12MFP_GPIO (0ul << SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH_ PB12 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 307 #define SYS_GPB_MFPH_PB12MFP_EADC_CH9 (1ul << SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH_ PB12 setting for EADC_CH9*/
sahilmgandhi 18:6a4db94011d3 308 #define SYS_GPB_MFPH_PB12MFP_TK1 (4ul << SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH_ PB12 setting for TK1*/
sahilmgandhi 18:6a4db94011d3 309
sahilmgandhi 18:6a4db94011d3 310 //PB13
sahilmgandhi 18:6a4db94011d3 311 #define SYS_GPB_MFPH_PB13MFP_GPIO (0ul << SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 312 #define SYS_GPB_MFPH_PB13MFP_EADC_CH10 (1ul << SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for EADC_CH10*/
sahilmgandhi 18:6a4db94011d3 313
sahilmgandhi 18:6a4db94011d3 314 //PB14
sahilmgandhi 18:6a4db94011d3 315 #define SYS_GPB_MFPH_PB14MFP_GPIO (0ul << SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 316 #define SYS_GPB_MFPH_PB14MFP_EADC_CH11 (1ul << SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for EADC_CH11*/
sahilmgandhi 18:6a4db94011d3 317
sahilmgandhi 18:6a4db94011d3 318 //PB15
sahilmgandhi 18:6a4db94011d3 319 #define SYS_GPB_MFPH_PB15MFP_GPIO (0ul << SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 320 #define SYS_GPB_MFPH_PB15MFP_EADC_CH12 (1ul << SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for EADC_CH12*/
sahilmgandhi 18:6a4db94011d3 321 #define SYS_GPB_MFPH_PB15MFP_TK2 (4ul << SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for TK2*/
sahilmgandhi 18:6a4db94011d3 322 #define SYS_GPB_MFPH_PB15MFP_ACMP0_P3 (5ul << SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for ACMP0_P3*/
sahilmgandhi 18:6a4db94011d3 323 #define SYS_GPB_MFPH_PB15MFP_EBI_nCS1 (7ul << SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for EBI_nCS1*/
sahilmgandhi 18:6a4db94011d3 324
sahilmgandhi 18:6a4db94011d3 325 //PC0
sahilmgandhi 18:6a4db94011d3 326 #define SYS_GPC_MFPL_PC0MFP_GPIO (0ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 327 #define SYS_GPC_MFPL_PC0MFP_SPI2_CLK (2ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for SPI2_CLK*/
sahilmgandhi 18:6a4db94011d3 328 #define SYS_GPC_MFPL_PC0MFP_UART2_nCTS (3ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for UART2_nCTS*/
sahilmgandhi 18:6a4db94011d3 329 #define SYS_GPC_MFPL_PC0MFP_CAN0_TXD (4ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for CAN0_TXD*/
sahilmgandhi 18:6a4db94011d3 330 #define SYS_GPC_MFPL_PC0MFP_PWM0_CH0 (6ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for PWM0_CH0*/
sahilmgandhi 18:6a4db94011d3 331 #define SYS_GPC_MFPL_PC0MFP_EBI_AD8 (7ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for EBI_AD8*/
sahilmgandhi 18:6a4db94011d3 332 #define SYS_GPC_MFPL_PC0MFP_INT2 (8ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for INT2*/
sahilmgandhi 18:6a4db94011d3 333 #define SYS_GPC_MFPL_PC0MFP_UART3_TXD (9ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for UART3_TXD*/
sahilmgandhi 18:6a4db94011d3 334 #define SYS_GPC_MFPL_PC0MFP_T3_EXT (11ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for T3_EXT*/
sahilmgandhi 18:6a4db94011d3 335
sahilmgandhi 18:6a4db94011d3 336 //PC1
sahilmgandhi 18:6a4db94011d3 337 #define SYS_GPC_MFPL_PC1MFP_GPIO (0ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 338 #define SYS_GPC_MFPL_PC1MFP_CLKO (1ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for CLKO*/
sahilmgandhi 18:6a4db94011d3 339 #define SYS_GPC_MFPL_PC1MFP_STDAC (2ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for STDAC*/
sahilmgandhi 18:6a4db94011d3 340 #define SYS_GPC_MFPL_PC1MFP_UART2_nRTS (3ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for UART2_nRTS*/
sahilmgandhi 18:6a4db94011d3 341 #define SYS_GPC_MFPL_PC1MFP_CAN0_RXD (4ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for CAN0_RXD*/
sahilmgandhi 18:6a4db94011d3 342 #define SYS_GPC_MFPL_PC1MFP_PWM0_CH1 (6ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for PWM0_CH1*/
sahilmgandhi 18:6a4db94011d3 343 #define SYS_GPC_MFPL_PC1MFP_EBI_AD9 (7ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for EBI_AD9*/
sahilmgandhi 18:6a4db94011d3 344 #define SYS_GPC_MFPL_PC1MFP_UART3_RXD (9ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for UART3_RXD*/
sahilmgandhi 18:6a4db94011d3 345
sahilmgandhi 18:6a4db94011d3 346 //PC2
sahilmgandhi 18:6a4db94011d3 347 #define SYS_GPC_MFPL_PC2MFP_GPIO (0ul << SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 348 #define SYS_GPC_MFPL_PC2MFP_SPI2_SS (2ul << SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for SPI2_SS*/
sahilmgandhi 18:6a4db94011d3 349 #define SYS_GPC_MFPL_PC2MFP_UART2_TXD (3ul << SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for UART2_TXD*/
sahilmgandhi 18:6a4db94011d3 350 #define SYS_GPC_MFPL_PC2MFP_ACMP1_O (5ul << SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for ACMP1_O*/
sahilmgandhi 18:6a4db94011d3 351 #define SYS_GPC_MFPL_PC2MFP_PWM0_CH2 (6ul << SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for PWM0_CH2*/
sahilmgandhi 18:6a4db94011d3 352 #define SYS_GPC_MFPL_PC2MFP_EBI_AD10 (7ul << SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for EBI_AD10*/
sahilmgandhi 18:6a4db94011d3 353
sahilmgandhi 18:6a4db94011d3 354 //PC3
sahilmgandhi 18:6a4db94011d3 355 #define SYS_GPC_MFPL_PC3MFP_GPIO (0ul << SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 356 #define SYS_GPC_MFPL_PC3MFP_SPI2_MOSI (2ul << SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for SPI2_MOSI*/
sahilmgandhi 18:6a4db94011d3 357 #define SYS_GPC_MFPL_PC3MFP_UART2_RXD (3ul << SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for UART2_RXD*/
sahilmgandhi 18:6a4db94011d3 358 #define SYS_GPC_MFPL_PC3MFP_USB_VBUS_ST (4ul << SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for USB_VBUS_ST*/
sahilmgandhi 18:6a4db94011d3 359 #define SYS_GPC_MFPL_PC3MFP_PWM0_CH3 (6ul << SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for PWM0_CH3*/
sahilmgandhi 18:6a4db94011d3 360 #define SYS_GPC_MFPL_PC3MFP_EBI_AD11 (7ul << SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for EBI_AD11*/
sahilmgandhi 18:6a4db94011d3 361
sahilmgandhi 18:6a4db94011d3 362 //PC4
sahilmgandhi 18:6a4db94011d3 363 #define SYS_GPC_MFPL_PC4MFP_GPIO (0ul << SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 364 #define SYS_GPC_MFPL_PC4MFP_SPI2_MISO (2ul << SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for SPI2_MISO*/
sahilmgandhi 18:6a4db94011d3 365 #define SYS_GPC_MFPL_PC4MFP_I2C1_SCL (3ul << SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for I2C1_SCL*/
sahilmgandhi 18:6a4db94011d3 366 #define SYS_GPC_MFPL_PC4MFP_USB_VBUS_EN (4ul << SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for USB_VBUS_EN*/
sahilmgandhi 18:6a4db94011d3 367 #define SYS_GPC_MFPL_PC4MFP_PWM0_CH4 (6ul << SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for PWM0_CH4*/
sahilmgandhi 18:6a4db94011d3 368 #define SYS_GPC_MFPL_PC4MFP_EBI_AD12 (7ul << SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for EBI_AD12*/
sahilmgandhi 18:6a4db94011d3 369
sahilmgandhi 18:6a4db94011d3 370 //PC5
sahilmgandhi 18:6a4db94011d3 371 #define SYS_GPC_MFPL_PC5MFP_GPIO (0ul << SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 372 #define SYS_GPC_MFPL_PC5MFP_SPI2_I2SMCLK (2ul << SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for SPI2_I2SMCLK*/
sahilmgandhi 18:6a4db94011d3 373 #define SYS_GPC_MFPL_PC5MFP_PWM0_CH5 (6ul << SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for PWM0_CH5*/
sahilmgandhi 18:6a4db94011d3 374 #define SYS_GPC_MFPL_PC5MFP_EBI_AD13 (7ul << SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for EBI_AD13*/
sahilmgandhi 18:6a4db94011d3 375
sahilmgandhi 18:6a4db94011d3 376 //PC6
sahilmgandhi 18:6a4db94011d3 377 #define SYS_GPC_MFPL_PC6MFP_GPIO (0ul << SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 378 #define SYS_GPC_MFPL_PC6MFP_I2C1_SMBAL (3ul << SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for I2C1_SMBAL*/
sahilmgandhi 18:6a4db94011d3 379 #define SYS_GPC_MFPL_PC6MFP_ACMP1_O (5ul << SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for ACMP1_O*/
sahilmgandhi 18:6a4db94011d3 380 #define SYS_GPC_MFPL_PC6MFP_PWM1_CH0 (6ul << SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for PWM1_CH0*/
sahilmgandhi 18:6a4db94011d3 381 #define SYS_GPC_MFPL_PC6MFP_EBI_AD14 (7ul << SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for EBI_AD14*/
sahilmgandhi 18:6a4db94011d3 382 #define SYS_GPC_MFPL_PC6MFP_UART0_TXD (9ul << SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for UART0_TXD*/
sahilmgandhi 18:6a4db94011d3 383
sahilmgandhi 18:6a4db94011d3 384 //PC7
sahilmgandhi 18:6a4db94011d3 385 #define SYS_GPC_MFPL_PC7MFP_GPIO (0ul << SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 386 #define SYS_GPC_MFPL_PC7MFP_I2C1_SMBSUS (3ul << SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for I2C1_SMBSUS*/
sahilmgandhi 18:6a4db94011d3 387 #define SYS_GPC_MFPL_PC7MFP_PWM1_CH1 (6ul << SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for PWM1_CH1*/
sahilmgandhi 18:6a4db94011d3 388 #define SYS_GPC_MFPL_PC7MFP_EBI_AD15 (7ul << SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for EBI_AD15*/
sahilmgandhi 18:6a4db94011d3 389 #define SYS_GPC_MFPL_PC7MFP_UART0_RXD (9ul << SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for UART0_RXD*/
sahilmgandhi 18:6a4db94011d3 390
sahilmgandhi 18:6a4db94011d3 391 //PC8
sahilmgandhi 18:6a4db94011d3 392 #define SYS_GPC_MFPH_PC8MFP_GPIO (0ul << SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH_ PC8 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 393 #define SYS_GPC_MFPH_PC8MFP_TK7 (4ul << SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH_ PC8 setting for TK7*/
sahilmgandhi 18:6a4db94011d3 394
sahilmgandhi 18:6a4db94011d3 395 //PC9
sahilmgandhi 18:6a4db94011d3 396 #define SYS_GPC_MFPH_PC9MFP_GPIO (0ul << SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 397 #define SYS_GPC_MFPH_PC9MFP_SPI2_I2SMCLK (2ul << SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for SPI2_I2SMCLK*/
sahilmgandhi 18:6a4db94011d3 398 #define SYS_GPC_MFPH_PC9MFP_PWM1_CH0 (6ul << SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for PWM1_CH0*/
sahilmgandhi 18:6a4db94011d3 399
sahilmgandhi 18:6a4db94011d3 400 //PC10
sahilmgandhi 18:6a4db94011d3 401 #define SYS_GPC_MFPH_PC10MFP_GPIO (0ul << SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 402 #define SYS_GPC_MFPH_PC10MFP_SPI2_MOSI (2ul << SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for SPI2_MOSI*/
sahilmgandhi 18:6a4db94011d3 403 #define SYS_GPC_MFPH_PC10MFP_PWM1_CH1 (6ul << SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for PWM1_CH1*/
sahilmgandhi 18:6a4db94011d3 404
sahilmgandhi 18:6a4db94011d3 405 //PC11
sahilmgandhi 18:6a4db94011d3 406 #define SYS_GPC_MFPH_PC11MFP_GPIO (0ul << SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 407 #define SYS_GPC_MFPH_PC11MFP_SPI2_MISO (2ul << SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for SPI2_MISO*/
sahilmgandhi 18:6a4db94011d3 408 #define SYS_GPC_MFPH_PC11MFP_PWM1_CH2 (6ul << SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for PWM1_CH2*/
sahilmgandhi 18:6a4db94011d3 409
sahilmgandhi 18:6a4db94011d3 410 //PC12
sahilmgandhi 18:6a4db94011d3 411 #define SYS_GPC_MFPH_PC12MFP_GPIO (0ul << SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 412 #define SYS_GPC_MFPH_PC12MFP_SPI2_CLK (2ul << SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for SPI2_CLK*/
sahilmgandhi 18:6a4db94011d3 413 #define SYS_GPC_MFPH_PC12MFP_PWM1_CH3 (6ul << SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for PWM1_CH3*/
sahilmgandhi 18:6a4db94011d3 414
sahilmgandhi 18:6a4db94011d3 415 //PC13
sahilmgandhi 18:6a4db94011d3 416 #define SYS_GPC_MFPH_PC13MFP_GPIO (0ul << SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 417 #define SYS_GPC_MFPH_PC13MFP_SPI2_SS (2ul << SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for SPI2_SS*/
sahilmgandhi 18:6a4db94011d3 418 #define SYS_GPC_MFPH_PC13MFP_PWM1_CH4 (6ul << SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for PWM1_CH4*/
sahilmgandhi 18:6a4db94011d3 419
sahilmgandhi 18:6a4db94011d3 420 //PC14
sahilmgandhi 18:6a4db94011d3 421 #define SYS_GPC_MFPH_PC14MFP_GPIO (0ul << SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 422 #define SYS_GPC_MFPH_PC14MFP_PWM1_CH5 (6ul << SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for PWM1_CH5*/
sahilmgandhi 18:6a4db94011d3 423
sahilmgandhi 18:6a4db94011d3 424 //PC15
sahilmgandhi 18:6a4db94011d3 425 #define SYS_GPC_MFPH_PC15MFP_GPIO (0ul << SYS_GPC_MFPH_PC15MFP_Pos) /*!< GPC_MFPH PC15 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 426 #define SYS_GPC_MFPH_PC15MFP_PWM1_CH0 (6ul << SYS_GPC_MFPH_PC15MFP_Pos) /*!< GPC_MFPH PC15 setting for PWM1_CH0*/
sahilmgandhi 18:6a4db94011d3 427
sahilmgandhi 18:6a4db94011d3 428 //PD0
sahilmgandhi 18:6a4db94011d3 429 #define SYS_GPD_MFPL_PD0MFP_GPIO (0ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 430 #define SYS_GPD_MFPL_PD0MFP_EADC_CH6 (1ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for EADC_CH6*/
sahilmgandhi 18:6a4db94011d3 431 #define SYS_GPD_MFPL_PD0MFP_SPI1_I2SMCLK (2ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for SPI1_I2SMCLK*/
sahilmgandhi 18:6a4db94011d3 432 #define SYS_GPD_MFPL_PD0MFP_UART0_RXD (3ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for UART0_RXD*/
sahilmgandhi 18:6a4db94011d3 433 #define SYS_GPD_MFPL_PD0MFP_TK6 (4ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for TK6*/
sahilmgandhi 18:6a4db94011d3 434 #define SYS_GPD_MFPL_PD0MFP_ACMP1_N (5ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for ACMP1_N*/
sahilmgandhi 18:6a4db94011d3 435 #define SYS_GPD_MFPL_PD0MFP_INT3 (8ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for INT3*/
sahilmgandhi 18:6a4db94011d3 436 #define SYS_GPD_MFPL_PD0MFP_T3 (11ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for T3*/
sahilmgandhi 18:6a4db94011d3 437
sahilmgandhi 18:6a4db94011d3 438 //PD1
sahilmgandhi 18:6a4db94011d3 439 #define SYS_GPD_MFPL_PD1MFP_GPIO (0ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 440 #define SYS_GPD_MFPL_PD1MFP_EADC_CH11 (1ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for EADC_CH11*/
sahilmgandhi 18:6a4db94011d3 441 #define SYS_GPD_MFPL_PD1MFP_PWM0_SYNC_IN (2ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for PWM0_SYNC_IN*/
sahilmgandhi 18:6a4db94011d3 442 #define SYS_GPD_MFPL_PD1MFP_UART0_TXD (3ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for UART0_TXD*/
sahilmgandhi 18:6a4db94011d3 443 #define SYS_GPD_MFPL_PD1MFP_TK10 (4ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for TK10*/
sahilmgandhi 18:6a4db94011d3 444 #define SYS_GPD_MFPL_PD1MFP_ACMP1_P2 (5ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for ACMP1_P2*/
sahilmgandhi 18:6a4db94011d3 445 #define SYS_GPD_MFPL_PD1MFP_T0 (6ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for T0*/
sahilmgandhi 18:6a4db94011d3 446 #define SYS_GPD_MFPL_PD1MFP_EBI_nRD (7ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for EBI_nRD*/
sahilmgandhi 18:6a4db94011d3 447
sahilmgandhi 18:6a4db94011d3 448 //PD2
sahilmgandhi 18:6a4db94011d3 449 #define SYS_GPD_MFPL_PD2MFP_GPIO (0ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 450 #define SYS_GPD_MFPL_PD2MFP_STADC (1ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for STADC*/
sahilmgandhi 18:6a4db94011d3 451 #define SYS_GPD_MFPL_PD2MFP_T0_EXT (3ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for T0_EXT*/
sahilmgandhi 18:6a4db94011d3 452 #define SYS_GPD_MFPL_PD2MFP_TK11 (4ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for TK11*/
sahilmgandhi 18:6a4db94011d3 453 #define SYS_GPD_MFPL_PD2MFP_ACMP1_P1 (5ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for ACMP1_P1*/
sahilmgandhi 18:6a4db94011d3 454 #define SYS_GPD_MFPL_PD2MFP_PWM0_BRAKE0 (6ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for PWM0_BRAKE0*/
sahilmgandhi 18:6a4db94011d3 455 #define SYS_GPD_MFPL_PD2MFP_EBI_nWR (7ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for EBI_nWR*/
sahilmgandhi 18:6a4db94011d3 456 #define SYS_GPD_MFPL_PD2MFP_INT0 (8ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for INT0*/
sahilmgandhi 18:6a4db94011d3 457
sahilmgandhi 18:6a4db94011d3 458 //PD3
sahilmgandhi 18:6a4db94011d3 459 #define SYS_GPD_MFPL_PD3MFP_GPIO (0ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 460 #define SYS_GPD_MFPL_PD3MFP_T2 (1ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for T2*/
sahilmgandhi 18:6a4db94011d3 461 #define SYS_GPD_MFPL_PD3MFP_T1_EXT (3ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for T1_EXT*/
sahilmgandhi 18:6a4db94011d3 462 #define SYS_GPD_MFPL_PD3MFP_TK12 (4ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for TK12*/
sahilmgandhi 18:6a4db94011d3 463 #define SYS_GPD_MFPL_PD3MFP_ACMP1_P0 (5ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for ACMP1_P0*/
sahilmgandhi 18:6a4db94011d3 464 #define SYS_GPD_MFPL_PD3MFP_PWM0_BRAKE1 (6ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for PWM0_BRAKE1*/
sahilmgandhi 18:6a4db94011d3 465 #define SYS_GPD_MFPL_PD3MFP_EBI_MCLK (7ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for EBI_MCLK*/
sahilmgandhi 18:6a4db94011d3 466 #define SYS_GPD_MFPL_PD3MFP_INT1 (8ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for INT1*/
sahilmgandhi 18:6a4db94011d3 467
sahilmgandhi 18:6a4db94011d3 468 //PD4
sahilmgandhi 18:6a4db94011d3 469 #define SYS_GPD_MFPL_PD4MFP_GPIO (0ul << SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 470 #define SYS_GPD_MFPL_PD4MFP_SPI1_CLK (2ul << SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for SPI1_CLK*/
sahilmgandhi 18:6a4db94011d3 471 #define SYS_GPD_MFPL_PD4MFP_I2C0_SDA (3ul << SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for I2C0_SDA*/
sahilmgandhi 18:6a4db94011d3 472 #define SYS_GPD_MFPL_PD4MFP_TK13 (4ul << SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for TK13*/
sahilmgandhi 18:6a4db94011d3 473 #define SYS_GPD_MFPL_PD4MFP_PWM0_BRAKE0 (5ul << SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for PWM0_BRAKE0*/
sahilmgandhi 18:6a4db94011d3 474 #define SYS_GPD_MFPL_PD4MFP_T0 (6ul << SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for T0*/
sahilmgandhi 18:6a4db94011d3 475
sahilmgandhi 18:6a4db94011d3 476 //PD5
sahilmgandhi 18:6a4db94011d3 477 #define SYS_GPD_MFPL_PD5MFP_GPIO (0ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 478 #define SYS_GPD_MFPL_PD5MFP_CLKO (1ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for CLKO*/
sahilmgandhi 18:6a4db94011d3 479 #define SYS_GPD_MFPL_PD5MFP_SPI1_MISO (2ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for SPI1_MISO*/
sahilmgandhi 18:6a4db94011d3 480 #define SYS_GPD_MFPL_PD5MFP_I2C0_SCL (3ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for I2C0_SCL*/
sahilmgandhi 18:6a4db94011d3 481 #define SYS_GPD_MFPL_PD5MFP_TK14 (4ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for TK14*/
sahilmgandhi 18:6a4db94011d3 482 #define SYS_GPD_MFPL_PD5MFP_PWM0_BRAKE1 (5ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for PWM0_BRAKE1*/
sahilmgandhi 18:6a4db94011d3 483 #define SYS_GPD_MFPL_PD5MFP_T1 (6ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for T1*/
sahilmgandhi 18:6a4db94011d3 484
sahilmgandhi 18:6a4db94011d3 485 //PD6
sahilmgandhi 18:6a4db94011d3 486 #define SYS_GPD_MFPL_PD6MFP_GPIO (0ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 487 #define SYS_GPD_MFPL_PD6MFP_CLKO (1ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for CLKO*/
sahilmgandhi 18:6a4db94011d3 488 #define SYS_GPD_MFPL_PD6MFP_SPI1_SS (2ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for SPI1_SS*/
sahilmgandhi 18:6a4db94011d3 489 #define SYS_GPD_MFPL_PD6MFP_UART0_RXD (3ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for UART0_RXD*/
sahilmgandhi 18:6a4db94011d3 490 #define SYS_GPD_MFPL_PD6MFP_TK16 (4ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for TK16*/
sahilmgandhi 18:6a4db94011d3 491 #define SYS_GPD_MFPL_PD6MFP_ACMP0_O (5ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for ACMP0_O*/
sahilmgandhi 18:6a4db94011d3 492 #define SYS_GPD_MFPL_PD6MFP_PWM0_CH5 (6ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for PWM0_CH5*/
sahilmgandhi 18:6a4db94011d3 493 #define SYS_GPD_MFPL_PD6MFP_EBI_nWR (7ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for EBI_nWR*/
sahilmgandhi 18:6a4db94011d3 494
sahilmgandhi 18:6a4db94011d3 495 //PD7
sahilmgandhi 18:6a4db94011d3 496 #define SYS_GPD_MFPL_PD7MFP_GPIO (0ul << SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 497 #define SYS_GPD_MFPL_PD7MFP_PWM0_SYNC_IN (3ul << SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for PWM0_SYNC_IN*/
sahilmgandhi 18:6a4db94011d3 498 #define SYS_GPD_MFPL_PD7MFP_T1 (4ul << SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for T1*/
sahilmgandhi 18:6a4db94011d3 499 #define SYS_GPD_MFPL_PD7MFP_ACMP0_O (5ul << SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for ACMP0_O*/
sahilmgandhi 18:6a4db94011d3 500 #define SYS_GPD_MFPL_PD7MFP_PWM0_CH5 (6ul << SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for PWM0_CH5*/
sahilmgandhi 18:6a4db94011d3 501 #define SYS_GPD_MFPL_PD7MFP_EBI_nRD (7ul << SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for EBI_nRD*/
sahilmgandhi 18:6a4db94011d3 502
sahilmgandhi 18:6a4db94011d3 503 //PD8
sahilmgandhi 18:6a4db94011d3 504 #define SYS_GPD_MFPH_PD8MFP_GPIO (0ul << SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 505 #define SYS_GPD_MFPH_PD8MFP_EADC_CH7 (1ul << SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for EADC_CH7*/
sahilmgandhi 18:6a4db94011d3 506 #define SYS_GPD_MFPH_PD8MFP_TK8 (4ul << SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for TK8*/
sahilmgandhi 18:6a4db94011d3 507 #define SYS_GPD_MFPH_PD8MFP_EBI_nCS0 (7ul << SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for EBI_nCS0*/
sahilmgandhi 18:6a4db94011d3 508
sahilmgandhi 18:6a4db94011d3 509 //PD9
sahilmgandhi 18:6a4db94011d3 510 #define SYS_GPD_MFPH_PD9MFP_GPIO (0ul << SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 511 #define SYS_GPD_MFPH_PD9MFP_EADC_CH10 (1ul << SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for EADC_CH10*/
sahilmgandhi 18:6a4db94011d3 512 #define SYS_GPD_MFPH_PD9MFP_TK9 (4ul << SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for TK9*/
sahilmgandhi 18:6a4db94011d3 513 #define SYS_GPD_MFPH_PD9MFP_ACMP1_P3 (5ul << SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for ACMP1_P3*/
sahilmgandhi 18:6a4db94011d3 514 #define SYS_GPD_MFPH_PD9MFP_EBI_ALE (7ul << SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for EBI_ALE*/
sahilmgandhi 18:6a4db94011d3 515
sahilmgandhi 18:6a4db94011d3 516 //PD10
sahilmgandhi 18:6a4db94011d3 517 #define SYS_GPD_MFPH_PD10MFP_GPIO (0ul << SYS_GPD_MFPH_PD10MFP_Pos) /*!< GPD_MFPH PD10 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 518 #define SYS_GPD_MFPH_PD10MFP_T2 (4ul << SYS_GPD_MFPH_PD10MFP_Pos) /*!< GPD_MFPH PD10 setting for T2*/
sahilmgandhi 18:6a4db94011d3 519
sahilmgandhi 18:6a4db94011d3 520 //PD11
sahilmgandhi 18:6a4db94011d3 521 #define SYS_GPD_MFPH_PD11MFP_GPIO (0ul << SYS_GPD_MFPH_PD11MFP_Pos) /*!< GPD_MFPH PD11 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 522 #define SYS_GPD_MFPH_PD11MFP_T3 (4ul << SYS_GPD_MFPH_PD11MFP_Pos) /*!< GPD_MFPH PD11 setting for T3*/
sahilmgandhi 18:6a4db94011d3 523
sahilmgandhi 18:6a4db94011d3 524 //PD12
sahilmgandhi 18:6a4db94011d3 525 #define SYS_GPD_MFPH_PD12MFP_GPIO (0ul << SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 526 #define SYS_GPD_MFPH_PD12MFP_SPI2_SS (2ul << SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for SPI2_SS*/
sahilmgandhi 18:6a4db94011d3 527 #define SYS_GPD_MFPH_PD12MFP_UART3_TXD (3ul << SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for UART3_TXD*/
sahilmgandhi 18:6a4db94011d3 528 #define SYS_GPD_MFPH_PD12MFP_PWM1_CH0 (6ul << SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for PWM1_CH0*/
sahilmgandhi 18:6a4db94011d3 529 #define SYS_GPD_MFPH_PD12MFP_EBI_ADR16 (7ul << SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for EBI_ADR16*/
sahilmgandhi 18:6a4db94011d3 530
sahilmgandhi 18:6a4db94011d3 531 //PD13
sahilmgandhi 18:6a4db94011d3 532 #define SYS_GPD_MFPH_PD13MFP_GPIO (0ul << SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 533 #define SYS_GPD_MFPH_PD13MFP_SPI2_MOSI (2ul << SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for SPI2_MOSI*/
sahilmgandhi 18:6a4db94011d3 534 #define SYS_GPD_MFPH_PD13MFP_UART3_RXD (3ul << SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for UART3_RXD*/
sahilmgandhi 18:6a4db94011d3 535 #define SYS_GPD_MFPH_PD13MFP_PWM1_CH1 (6ul << SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for PWM1_CH1*/
sahilmgandhi 18:6a4db94011d3 536 #define SYS_GPD_MFPH_PD13MFP_EBI_ADR17 (7ul << SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for EBI_ADR17*/
sahilmgandhi 18:6a4db94011d3 537
sahilmgandhi 18:6a4db94011d3 538 //PD14
sahilmgandhi 18:6a4db94011d3 539 #define SYS_GPD_MFPH_PD14MFP_GPIO (0ul << SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH_ PD14 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 540 #define SYS_GPD_MFPH_PD14MFP_SPI2_MISO (2ul << SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH_ PD14 setting for SPI2_MISO*/
sahilmgandhi 18:6a4db94011d3 541 #define SYS_GPD_MFPH_PD14MFP_UART3_nCTS (3ul << SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH_ PD14 setting for UART3_nCTS*/
sahilmgandhi 18:6a4db94011d3 542 #define SYS_GPD_MFPH_PD14MFP_PWM1_CH2 (6ul << SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH_ PD14 setting for PWM1_CH2*/
sahilmgandhi 18:6a4db94011d3 543 #define SYS_GPD_MFPH_PD14MFP_EBI_ADR18 (7ul << SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH_ PD14 setting for EBI_ADR18*/
sahilmgandhi 18:6a4db94011d3 544
sahilmgandhi 18:6a4db94011d3 545 //PD15
sahilmgandhi 18:6a4db94011d3 546 #define SYS_GPD_MFPH_PD15MFP_GPIO (0ul << SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH_ PD15 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 547 #define SYS_GPD_MFPH_PD15MFP_SPI2_CLK (2ul << SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH_ PD15 setting for SPI2_CLK*/
sahilmgandhi 18:6a4db94011d3 548 #define SYS_GPD_MFPH_PD15MFP_UART3_nRTS (3ul << SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH_ PD15 setting for UART3_nRTS*/
sahilmgandhi 18:6a4db94011d3 549 #define SYS_GPD_MFPH_PD15MFP_PWM1_CH3 (6ul << SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH_ PD15 setting for PWM1_CH3*/
sahilmgandhi 18:6a4db94011d3 550 #define SYS_GPD_MFPH_PD15MFP_EBI_ADR19 (7ul << SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH_ PD15 setting for EBI_ADR19*/
sahilmgandhi 18:6a4db94011d3 551
sahilmgandhi 18:6a4db94011d3 552 //PE0
sahilmgandhi 18:6a4db94011d3 553 #define SYS_GPE_MFPL_PE0MFP_GPIO (0ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 554 #define SYS_GPE_MFPL_PE0MFP_SPI2_CLK (2ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for SPI2_CLK*/
sahilmgandhi 18:6a4db94011d3 555 #define SYS_GPE_MFPL_PE0MFP_I2C1_SDA (3ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for I2C1_SDA*/
sahilmgandhi 18:6a4db94011d3 556 #define SYS_GPE_MFPL_PE0MFP_T2_EXT (4ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for T2_EXT*/
sahilmgandhi 18:6a4db94011d3 557 #define SYS_GPE_MFPL_PE0MFP_SC0_CD (5ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for SC0_CD*/
sahilmgandhi 18:6a4db94011d3 558 #define SYS_GPE_MFPL_PE0MFP_PWM0_CH0 (6ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for PWM0_CH0*/
sahilmgandhi 18:6a4db94011d3 559 #define SYS_GPE_MFPL_PE0MFP_EBI_nCS1 (7ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for EBI_nCS1*/
sahilmgandhi 18:6a4db94011d3 560 #define SYS_GPE_MFPL_PE0MFP_INT4 (8ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for INT4*/
sahilmgandhi 18:6a4db94011d3 561
sahilmgandhi 18:6a4db94011d3 562 //PE1
sahilmgandhi 18:6a4db94011d3 563 #define SYS_GPE_MFPL_PE1MFP_GPIO (0ul << SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 564 #define SYS_GPE_MFPL_PE1MFP_T3_EXT (3ul << SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for T3_EXT*/
sahilmgandhi 18:6a4db94011d3 565 #define SYS_GPE_MFPL_PE1MFP_SC0_CD (5ul << SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for SC0_CD*/
sahilmgandhi 18:6a4db94011d3 566 #define SYS_GPE_MFPL_PE1MFP_PWM0_CH1 (6ul << SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for PWM0_CH1*/
sahilmgandhi 18:6a4db94011d3 567
sahilmgandhi 18:6a4db94011d3 568 //PE2
sahilmgandhi 18:6a4db94011d3 569 #define SYS_GPE_MFPL_PE2MFP_GPIO (0ul << SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 570 #define SYS_GPE_MFPL_PE2MFP_PWM1_CH1 (6ul << SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for PWM1_CH1*/
sahilmgandhi 18:6a4db94011d3 571
sahilmgandhi 18:6a4db94011d3 572 //PE3
sahilmgandhi 18:6a4db94011d3 573 #define SYS_GPE_MFPL_PE3MFP_GPIO (0ul << SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 574 #define SYS_GPE_MFPL_PE3MFP_SPI1_MOSI (2ul << SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for SPI1_MOSI*/
sahilmgandhi 18:6a4db94011d3 575 #define SYS_GPE_MFPL_PE3MFP_TK15 (4ul << SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for TK15*/
sahilmgandhi 18:6a4db94011d3 576 #define SYS_GPE_MFPL_PE3MFP_PWM0_CH3 (6ul << SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for PWM0_CH3*/
sahilmgandhi 18:6a4db94011d3 577
sahilmgandhi 18:6a4db94011d3 578 //PE4
sahilmgandhi 18:6a4db94011d3 579 #define SYS_GPE_MFPL_PE4MFP_GPIO (0ul << SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 580 #define SYS_GPE_MFPL_PE4MFP_I2C1_SCL (3ul << SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for I2C1_SCL*/
sahilmgandhi 18:6a4db94011d3 581 #define SYS_GPE_MFPL_PE4MFP_SC0_PWR (5ul << SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for SC0_PWR*/
sahilmgandhi 18:6a4db94011d3 582 #define SYS_GPE_MFPL_PE4MFP_PWM1_BRAKE0 (6ul << SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for PWM1_BRAKE0*/
sahilmgandhi 18:6a4db94011d3 583 #define SYS_GPE_MFPL_PE4MFP_EBI_nCS0 (7ul << SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for EBI_nCS0*/
sahilmgandhi 18:6a4db94011d3 584 #define SYS_GPE_MFPL_PE4MFP_INT0 (8ul << SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for INT0*/
sahilmgandhi 18:6a4db94011d3 585
sahilmgandhi 18:6a4db94011d3 586 //PE5
sahilmgandhi 18:6a4db94011d3 587 #define SYS_GPE_MFPL_PE5MFP_GPIO (0ul << SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 588 #define SYS_GPE_MFPL_PE5MFP_I2C1_SDA (3ul << SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for I2C1_SDA*/
sahilmgandhi 18:6a4db94011d3 589 #define SYS_GPE_MFPL_PE5MFP_SC0_RST (5ul << SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for SC0_RST*/
sahilmgandhi 18:6a4db94011d3 590 #define SYS_GPE_MFPL_PE5MFP_PWM1_BRAKE1 (6ul << SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for PWM1_BRAKE1*/
sahilmgandhi 18:6a4db94011d3 591 #define SYS_GPE_MFPL_PE5MFP_EBI_ALE (7ul << SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for EBI_ALE*/
sahilmgandhi 18:6a4db94011d3 592 #define SYS_GPE_MFPL_PE5MFP_INT1 (8ul << SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for INT1*/
sahilmgandhi 18:6a4db94011d3 593
sahilmgandhi 18:6a4db94011d3 594 //PE6
sahilmgandhi 18:6a4db94011d3 595 #define SYS_GPE_MFPL_PE6MFP_GPIO (0ul << SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 596 #define SYS_GPE_MFPL_PE6MFP_T3_EXT (3ul << SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for T3_EXT*/
sahilmgandhi 18:6a4db94011d3 597
sahilmgandhi 18:6a4db94011d3 598 //PE7
sahilmgandhi 18:6a4db94011d3 599 #define SYS_GPE_MFPL_PE7MFP_GPIO (0ul << SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 600
sahilmgandhi 18:6a4db94011d3 601 //PE8
sahilmgandhi 18:6a4db94011d3 602 #define SYS_GPE_MFPH_PE8MFP_GPIO (0ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 603 #define SYS_GPE_MFPH_PE8MFP_UART1_TXD (1ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for UART1_TXD*/
sahilmgandhi 18:6a4db94011d3 604 #define SYS_GPE_MFPH_PE8MFP_SPI0_MISO1 (2ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for SPI0_MISO1*/
sahilmgandhi 18:6a4db94011d3 605 #define SYS_GPE_MFPH_PE8MFP_I2C1_SCL (4ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for I2C1_SCL*/
sahilmgandhi 18:6a4db94011d3 606 #define SYS_GPE_MFPH_PE8MFP_SC0_PWR (5ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for SC0_PWR*/
sahilmgandhi 18:6a4db94011d3 607 #define SYS_GPE_MFPH_PE8MFP_CLKO (9ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for CLKO*/
sahilmgandhi 18:6a4db94011d3 608 #define SYS_GPE_MFPH_PE8MFP_PWM0_BRAKE0 (10ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for PWM0_BRAKE0*/
sahilmgandhi 18:6a4db94011d3 609 #define SYS_GPE_MFPH_PE8MFP_T1 (11ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for T1*/
sahilmgandhi 18:6a4db94011d3 610
sahilmgandhi 18:6a4db94011d3 611 //PE9
sahilmgandhi 18:6a4db94011d3 612 #define SYS_GPE_MFPH_PE9MFP_GPIO (0ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 613 #define SYS_GPE_MFPH_PE9MFP_UART1_RXD (1ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for UART1_RXD*/
sahilmgandhi 18:6a4db94011d3 614 #define SYS_GPE_MFPH_PE9MFP_SPI0_MOSI1 (2ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for SPI0_MOSI1*/
sahilmgandhi 18:6a4db94011d3 615 #define SYS_GPE_MFPH_PE9MFP_I2C1_SDA (4ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for I2C1_SDA*/
sahilmgandhi 18:6a4db94011d3 616 #define SYS_GPE_MFPH_PE9MFP_SC0_RST (5ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for SC0_RST*/
sahilmgandhi 18:6a4db94011d3 617 #define SYS_GPE_MFPH_PE9MFP_SPI1_I2SMCLK (9ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for SPI1_I2SMCLK*/
sahilmgandhi 18:6a4db94011d3 618 #define SYS_GPE_MFPH_PE9MFP_PWM1_BRAKE1 (10ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for PWM1_BRAKE1*/
sahilmgandhi 18:6a4db94011d3 619 #define SYS_GPE_MFPH_PE9MFP_T2 (11ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for T2*/
sahilmgandhi 18:6a4db94011d3 620
sahilmgandhi 18:6a4db94011d3 621 //PE10
sahilmgandhi 18:6a4db94011d3 622 #define SYS_GPE_MFPH_PE10MFP_GPIO (0ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 623 #define SYS_GPE_MFPH_PE10MFP_SPI1_MISO (1ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for SPI1_MISO*/
sahilmgandhi 18:6a4db94011d3 624 #define SYS_GPE_MFPH_PE10MFP_SPI0_MISO0 (2ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for SPI0_MISO0*/
sahilmgandhi 18:6a4db94011d3 625 #define SYS_GPE_MFPH_PE10MFP_UART1_nCTS (3ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for UART1_nCTS*/
sahilmgandhi 18:6a4db94011d3 626 #define SYS_GPE_MFPH_PE10MFP_I2C0_SMBAL (4ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for I2C0_SMBAL*/
sahilmgandhi 18:6a4db94011d3 627 #define SYS_GPE_MFPH_PE10MFP_SC0_DAT (5ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for SC0_DAT*/
sahilmgandhi 18:6a4db94011d3 628 #define SYS_GPE_MFPH_PE10MFP_UART3_TXD (9ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for UART3_TXD*/
sahilmgandhi 18:6a4db94011d3 629 #define SYS_GPE_MFPH_PE10MFP_I2C1_SCL (11ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for I2C1_SCL*/
sahilmgandhi 18:6a4db94011d3 630
sahilmgandhi 18:6a4db94011d3 631 //PE11
sahilmgandhi 18:6a4db94011d3 632 #define SYS_GPE_MFPH_PE11MFP_GPIO (0ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 633 #define SYS_GPE_MFPH_PE11MFP_SPI1_MOSI (1ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for SPI1_MOSI*/
sahilmgandhi 18:6a4db94011d3 634 #define SYS_GPE_MFPH_PE11MFP_SPI0_MOSI0 (2ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for SPI0_MOSI0*/
sahilmgandhi 18:6a4db94011d3 635 #define SYS_GPE_MFPH_PE11MFP_UART1_nRTS (3ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for UART1_nRTS*/
sahilmgandhi 18:6a4db94011d3 636 #define SYS_GPE_MFPH_PE11MFP_I2C0_SMBSUS (4ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for I2C0_SMBSUS*/
sahilmgandhi 18:6a4db94011d3 637 #define SYS_GPE_MFPH_PE11MFP_SC0_CLK (5ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for SC0_CLK*/
sahilmgandhi 18:6a4db94011d3 638 #define SYS_GPE_MFPH_PE11MFP_UART3_RXD (9ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for UART3_RXD*/
sahilmgandhi 18:6a4db94011d3 639 #define SYS_GPE_MFPH_PE11MFP_I2C1_SDA (11ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for I2C1_SDA*/
sahilmgandhi 18:6a4db94011d3 640
sahilmgandhi 18:6a4db94011d3 641 //PE12
sahilmgandhi 18:6a4db94011d3 642 #define SYS_GPE_MFPH_PE12MFP_GPIO (0ul << SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 643 #define SYS_GPE_MFPH_PE12MFP_SPI1_SS (1ul << SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for SPI1_SS*/
sahilmgandhi 18:6a4db94011d3 644 #define SYS_GPE_MFPH_PE12MFP_SPI0_SS (2ul << SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for SPI0_SS*/
sahilmgandhi 18:6a4db94011d3 645 #define SYS_GPE_MFPH_PE12MFP_UART1_TXD (3ul << SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for UART1_TXD*/
sahilmgandhi 18:6a4db94011d3 646 #define SYS_GPE_MFPH_PE12MFP_I2C0_SCL (4ul << SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for I2C0_SCL*/
sahilmgandhi 18:6a4db94011d3 647
sahilmgandhi 18:6a4db94011d3 648 //PE13
sahilmgandhi 18:6a4db94011d3 649 #define SYS_GPE_MFPH_PE13MFP_GPIO (0ul << SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 650 #define SYS_GPE_MFPH_PE13MFP_SPI1_CLK (1ul << SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for SPI1_CLK*/
sahilmgandhi 18:6a4db94011d3 651 #define SYS_GPE_MFPH_PE13MFP_SPI0_CLK (2ul << SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for SPI0_CLK*/
sahilmgandhi 18:6a4db94011d3 652 #define SYS_GPE_MFPH_PE13MFP_UART1_RXD (3ul << SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for UART1_RXD*/
sahilmgandhi 18:6a4db94011d3 653 #define SYS_GPE_MFPH_PE13MFP_I2C0_SDA (4ul << SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for I2C0_SDA*/
sahilmgandhi 18:6a4db94011d3 654
sahilmgandhi 18:6a4db94011d3 655 //PE14
sahilmgandhi 18:6a4db94011d3 656 #define SYS_GPE_MFPH_PE14MFP_GPIO (0ul << SYS_GPE_MFPH_PE14MFP_Pos) /*!< GPE_MFPH PE14 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 657
sahilmgandhi 18:6a4db94011d3 658 //PF0
sahilmgandhi 18:6a4db94011d3 659 #define SYS_GPF_MFPL_PF0MFP_GPIO (0ul << SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 660 #define SYS_GPF_MFPL_PF0MFP_X32_OUT (1ul << SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for X32_OUT*/
sahilmgandhi 18:6a4db94011d3 661 #define SYS_GPF_MFPL_PF0MFP_INT5 (8ul << SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for INT5*/
sahilmgandhi 18:6a4db94011d3 662
sahilmgandhi 18:6a4db94011d3 663 //PF1
sahilmgandhi 18:6a4db94011d3 664 #define SYS_GPF_MFPL_PF1MFP_GPIO (0ul << SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 665 #define SYS_GPF_MFPL_PF1MFP_X32_IN (1ul << SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for X32_IN*/
sahilmgandhi 18:6a4db94011d3 666
sahilmgandhi 18:6a4db94011d3 667 //PF2
sahilmgandhi 18:6a4db94011d3 668 #define SYS_GPF_MFPL_PF2MFP_GPIO (0ul << SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 669 #define SYS_GPF_MFPL_PF2MFP_TAMPER (1ul << SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for TAMPER*/
sahilmgandhi 18:6a4db94011d3 670
sahilmgandhi 18:6a4db94011d3 671 //PF3
sahilmgandhi 18:6a4db94011d3 672 #define SYS_GPF_MFPL_PF3MFP_GPIO (0ul << SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 673 #define SYS_GPF_MFPL_PF3MFP_XT1_OUT (1ul << SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for XT1_OUT*/
sahilmgandhi 18:6a4db94011d3 674 #define SYS_GPF_MFPL_PF3MFP_I2C1_SCL (3ul << SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for I2C1_SCL*/
sahilmgandhi 18:6a4db94011d3 675
sahilmgandhi 18:6a4db94011d3 676 //PF4
sahilmgandhi 18:6a4db94011d3 677 #define SYS_GPF_MFPL_PF4MFP_GPIO (0ul << SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 678 #define SYS_GPF_MFPL_PF4MFP_XT1_IN (1ul << SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for XT1_IN*/
sahilmgandhi 18:6a4db94011d3 679 #define SYS_GPF_MFPL_PF4MFP_I2C1_SDA (3ul << SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for I2C1_SDA*/
sahilmgandhi 18:6a4db94011d3 680
sahilmgandhi 18:6a4db94011d3 681 //PF5
sahilmgandhi 18:6a4db94011d3 682 #define SYS_GPF_MFPL_PF5MFP_GPIO (0ul << SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 683 #define SYS_GPF_MFPL_PF5MFP_ICE_CLK (1ul << SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for ICE_CLK*/
sahilmgandhi 18:6a4db94011d3 684
sahilmgandhi 18:6a4db94011d3 685 //PF6
sahilmgandhi 18:6a4db94011d3 686 #define SYS_GPF_MFPL_PF6MFP_GPIO (0ul << SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 687 #define SYS_GPF_MFPL_PF6MFP_ICE_DAT (1ul << SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for ICE_DAT*/
sahilmgandhi 18:6a4db94011d3 688
sahilmgandhi 18:6a4db94011d3 689 //PF7
sahilmgandhi 18:6a4db94011d3 690 #define SYS_GPF_MFPL_PF7MFP_GPIO (0ul << SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for GPIO*/
sahilmgandhi 18:6a4db94011d3 691
sahilmgandhi 18:6a4db94011d3 692
sahilmgandhi 18:6a4db94011d3 693 /*@}*/ /* end of group SYS_EXPORTED_CONSTANTS */
sahilmgandhi 18:6a4db94011d3 694
sahilmgandhi 18:6a4db94011d3 695
sahilmgandhi 18:6a4db94011d3 696 /** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions
sahilmgandhi 18:6a4db94011d3 697 @{
sahilmgandhi 18:6a4db94011d3 698 */
sahilmgandhi 18:6a4db94011d3 699
sahilmgandhi 18:6a4db94011d3 700
sahilmgandhi 18:6a4db94011d3 701 /**
sahilmgandhi 18:6a4db94011d3 702 * @brief Clear Brown-out detector interrupt flag
sahilmgandhi 18:6a4db94011d3 703 * @param None
sahilmgandhi 18:6a4db94011d3 704 * @return None
sahilmgandhi 18:6a4db94011d3 705 * @details This macro clear Brown-out detector interrupt flag.
sahilmgandhi 18:6a4db94011d3 706 */
sahilmgandhi 18:6a4db94011d3 707 #define SYS_CLEAR_BOD_INT_FLAG() (SYS->BODCTL |= SYS_BODCTL_BODIF_Msk)
sahilmgandhi 18:6a4db94011d3 708
sahilmgandhi 18:6a4db94011d3 709 /**
sahilmgandhi 18:6a4db94011d3 710 * @brief Set Brown-out detector function to normal mode
sahilmgandhi 18:6a4db94011d3 711 * @param None
sahilmgandhi 18:6a4db94011d3 712 * @return None
sahilmgandhi 18:6a4db94011d3 713 * @details This macro set Brown-out detector to normal mode.
sahilmgandhi 18:6a4db94011d3 714 * The register write-protection function should be disabled before using this macro.
sahilmgandhi 18:6a4db94011d3 715 */
sahilmgandhi 18:6a4db94011d3 716 #define SYS_CLEAR_BOD_LPM() (SYS->BODCTL &= ~SYS_BODCTL_BODLPM_Msk)
sahilmgandhi 18:6a4db94011d3 717
sahilmgandhi 18:6a4db94011d3 718 /**
sahilmgandhi 18:6a4db94011d3 719 * @brief Disable Brown-out detector function
sahilmgandhi 18:6a4db94011d3 720 * @param None
sahilmgandhi 18:6a4db94011d3 721 * @return None
sahilmgandhi 18:6a4db94011d3 722 * @details This macro disable Brown-out detector function.
sahilmgandhi 18:6a4db94011d3 723 * The register write-protection function should be disabled before using this macro.
sahilmgandhi 18:6a4db94011d3 724 */
sahilmgandhi 18:6a4db94011d3 725 #define SYS_DISABLE_BOD() (SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk)
sahilmgandhi 18:6a4db94011d3 726
sahilmgandhi 18:6a4db94011d3 727 /**
sahilmgandhi 18:6a4db94011d3 728 * @brief Enable Brown-out detector function
sahilmgandhi 18:6a4db94011d3 729 * @param None
sahilmgandhi 18:6a4db94011d3 730 * @return None
sahilmgandhi 18:6a4db94011d3 731 * @details This macro enable Brown-out detector function.
sahilmgandhi 18:6a4db94011d3 732 * The register write-protection function should be disabled before using this macro.
sahilmgandhi 18:6a4db94011d3 733 */
sahilmgandhi 18:6a4db94011d3 734 #define SYS_ENABLE_BOD() (SYS->BODCTL |= SYS_BODCTL_BODEN_Msk)
sahilmgandhi 18:6a4db94011d3 735
sahilmgandhi 18:6a4db94011d3 736 /**
sahilmgandhi 18:6a4db94011d3 737 * @brief Get Brown-out detector interrupt flag
sahilmgandhi 18:6a4db94011d3 738 * @param None
sahilmgandhi 18:6a4db94011d3 739 * @retval 0 Brown-out detect interrupt flag is not set.
sahilmgandhi 18:6a4db94011d3 740 * @retval >=1 Brown-out detect interrupt flag is set.
sahilmgandhi 18:6a4db94011d3 741 * @details This macro get Brown-out detector interrupt flag.
sahilmgandhi 18:6a4db94011d3 742 */
sahilmgandhi 18:6a4db94011d3 743 #define SYS_GET_BOD_INT_FLAG() (SYS->BODCTL & SYS_BODCTL_BODIF_Msk)
sahilmgandhi 18:6a4db94011d3 744
sahilmgandhi 18:6a4db94011d3 745 /**
sahilmgandhi 18:6a4db94011d3 746 * @brief Get Brown-out detector status
sahilmgandhi 18:6a4db94011d3 747 * @param None
sahilmgandhi 18:6a4db94011d3 748 * @retval 0 System voltage is higher than BOD threshold voltage setting or BOD function is disabled.
sahilmgandhi 18:6a4db94011d3 749 * @retval >=1 System voltage is lower than BOD threshold voltage setting.
sahilmgandhi 18:6a4db94011d3 750 * @details This macro get Brown-out detector output status.
sahilmgandhi 18:6a4db94011d3 751 * If the BOD function is disabled, this function always return 0.
sahilmgandhi 18:6a4db94011d3 752 */
sahilmgandhi 18:6a4db94011d3 753 #define SYS_GET_BOD_OUTPUT() (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk)
sahilmgandhi 18:6a4db94011d3 754
sahilmgandhi 18:6a4db94011d3 755 /**
sahilmgandhi 18:6a4db94011d3 756 * @brief Enable Brown-out detector interrupt function
sahilmgandhi 18:6a4db94011d3 757 * @param None
sahilmgandhi 18:6a4db94011d3 758 * @return None
sahilmgandhi 18:6a4db94011d3 759 * @details This macro enable Brown-out detector interrupt function.
sahilmgandhi 18:6a4db94011d3 760 * The register write-protection function should be disabled before using this macro.
sahilmgandhi 18:6a4db94011d3 761 */
sahilmgandhi 18:6a4db94011d3 762 #define SYS_DISABLE_BOD_RST() (SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk)
sahilmgandhi 18:6a4db94011d3 763
sahilmgandhi 18:6a4db94011d3 764 /**
sahilmgandhi 18:6a4db94011d3 765 * @brief Enable Brown-out detector reset function
sahilmgandhi 18:6a4db94011d3 766 * @param None
sahilmgandhi 18:6a4db94011d3 767 * @return None
sahilmgandhi 18:6a4db94011d3 768 * @details This macro enable Brown-out detect reset function.
sahilmgandhi 18:6a4db94011d3 769 * The register write-protection function should be disabled before using this macro.
sahilmgandhi 18:6a4db94011d3 770 */
sahilmgandhi 18:6a4db94011d3 771 #define SYS_ENABLE_BOD_RST() (SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk)
sahilmgandhi 18:6a4db94011d3 772
sahilmgandhi 18:6a4db94011d3 773 /**
sahilmgandhi 18:6a4db94011d3 774 * @brief Set Brown-out detector function low power mode
sahilmgandhi 18:6a4db94011d3 775 * @param None
sahilmgandhi 18:6a4db94011d3 776 * @return None
sahilmgandhi 18:6a4db94011d3 777 * @details This macro set Brown-out detector to low power mode.
sahilmgandhi 18:6a4db94011d3 778 * The register write-protection function should be disabled before using this macro.
sahilmgandhi 18:6a4db94011d3 779 */
sahilmgandhi 18:6a4db94011d3 780 #define SYS_SET_BOD_LPM() (SYS->BODCTL |= SYS_BODCTL_BODLPM_Msk)
sahilmgandhi 18:6a4db94011d3 781
sahilmgandhi 18:6a4db94011d3 782 /**
sahilmgandhi 18:6a4db94011d3 783 * @brief Set Brown-out detector voltage level
sahilmgandhi 18:6a4db94011d3 784 * @param[in] u32Level is Brown-out voltage level. Including :
sahilmgandhi 18:6a4db94011d3 785 * - \ref SYS_BODCTL_BODVL_4_5V
sahilmgandhi 18:6a4db94011d3 786 * - \ref SYS_BODCTL_BODVL_3_7V
sahilmgandhi 18:6a4db94011d3 787 * - \ref SYS_BODCTL_BODVL_2_7V
sahilmgandhi 18:6a4db94011d3 788 * - \ref SYS_BODCTL_BODVL_2_2V
sahilmgandhi 18:6a4db94011d3 789 * @return None
sahilmgandhi 18:6a4db94011d3 790 * @details This macro set Brown-out detector voltage level.
sahilmgandhi 18:6a4db94011d3 791 * The write-protection function should be disabled before using this macro.
sahilmgandhi 18:6a4db94011d3 792 */
sahilmgandhi 18:6a4db94011d3 793 #define SYS_SET_BOD_LEVEL(u32Level) (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level))
sahilmgandhi 18:6a4db94011d3 794
sahilmgandhi 18:6a4db94011d3 795 /**
sahilmgandhi 18:6a4db94011d3 796 * @brief Get reset source is from Brown-out detector reset
sahilmgandhi 18:6a4db94011d3 797 * @param None
sahilmgandhi 18:6a4db94011d3 798 * @retval 0 Previous reset source is not from Brown-out detector reset
sahilmgandhi 18:6a4db94011d3 799 * @retval >=1 Previous reset source is from Brown-out detector reset
sahilmgandhi 18:6a4db94011d3 800 * @details This macro get previous reset source is from Brown-out detect reset or not.
sahilmgandhi 18:6a4db94011d3 801 */
sahilmgandhi 18:6a4db94011d3 802 #define SYS_IS_BOD_RST() (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk)
sahilmgandhi 18:6a4db94011d3 803
sahilmgandhi 18:6a4db94011d3 804 /**
sahilmgandhi 18:6a4db94011d3 805 * @brief Get reset source is from CPU reset
sahilmgandhi 18:6a4db94011d3 806 * @param None
sahilmgandhi 18:6a4db94011d3 807 * @retval 0 Previous reset source is not from CPU reset
sahilmgandhi 18:6a4db94011d3 808 * @retval >=1 Previous reset source is from CPU reset
sahilmgandhi 18:6a4db94011d3 809 * @details This macro get previous reset source is from CPU reset.
sahilmgandhi 18:6a4db94011d3 810 */
sahilmgandhi 18:6a4db94011d3 811 #define SYS_IS_CPU_RST() (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk)
sahilmgandhi 18:6a4db94011d3 812
sahilmgandhi 18:6a4db94011d3 813 /**
sahilmgandhi 18:6a4db94011d3 814 * @brief Get reset source is from LVR Reset
sahilmgandhi 18:6a4db94011d3 815 * @param None
sahilmgandhi 18:6a4db94011d3 816 * @retval 0 Previous reset source is not from Low-Voltage-Reset
sahilmgandhi 18:6a4db94011d3 817 * @retval >=1 Previous reset source is from Low-Voltage-Reset
sahilmgandhi 18:6a4db94011d3 818 * @details This macro get previous reset source is from Low-Voltage-Reset.
sahilmgandhi 18:6a4db94011d3 819 */
sahilmgandhi 18:6a4db94011d3 820 #define SYS_IS_LVR_RST() (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk)
sahilmgandhi 18:6a4db94011d3 821
sahilmgandhi 18:6a4db94011d3 822 /**
sahilmgandhi 18:6a4db94011d3 823 * @brief Get reset source is from Power-on Reset
sahilmgandhi 18:6a4db94011d3 824 * @param None
sahilmgandhi 18:6a4db94011d3 825 * @retval 0 Previous reset source is not from Power-on Reset
sahilmgandhi 18:6a4db94011d3 826 * @retval >=1 Previous reset source is from Power-on Reset
sahilmgandhi 18:6a4db94011d3 827 * @details This macro get previous reset source is from Power-on Reset.
sahilmgandhi 18:6a4db94011d3 828 */
sahilmgandhi 18:6a4db94011d3 829 #define SYS_IS_POR_RST() (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk)
sahilmgandhi 18:6a4db94011d3 830
sahilmgandhi 18:6a4db94011d3 831 /**
sahilmgandhi 18:6a4db94011d3 832 * @brief Get reset source is from reset pin reset
sahilmgandhi 18:6a4db94011d3 833 * @param None
sahilmgandhi 18:6a4db94011d3 834 * @retval 0 Previous reset source is not from reset pin reset
sahilmgandhi 18:6a4db94011d3 835 * @retval >=1 Previous reset source is from reset pin reset
sahilmgandhi 18:6a4db94011d3 836 * @details This macro get previous reset source is from reset pin reset.
sahilmgandhi 18:6a4db94011d3 837 */
sahilmgandhi 18:6a4db94011d3 838 #define SYS_IS_RSTPIN_RST() (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk)
sahilmgandhi 18:6a4db94011d3 839
sahilmgandhi 18:6a4db94011d3 840 /**
sahilmgandhi 18:6a4db94011d3 841 * @brief Get reset source is from system reset
sahilmgandhi 18:6a4db94011d3 842 * @param None
sahilmgandhi 18:6a4db94011d3 843 * @retval 0 Previous reset source is not from system reset
sahilmgandhi 18:6a4db94011d3 844 * @retval >=1 Previous reset source is from system reset
sahilmgandhi 18:6a4db94011d3 845 * @details This macro get previous reset source is from system reset.
sahilmgandhi 18:6a4db94011d3 846 */
sahilmgandhi 18:6a4db94011d3 847 #define SYS_IS_SYSTEM_RST() (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk)
sahilmgandhi 18:6a4db94011d3 848
sahilmgandhi 18:6a4db94011d3 849 /**
sahilmgandhi 18:6a4db94011d3 850 * @brief Get reset source is from window watch dog reset
sahilmgandhi 18:6a4db94011d3 851 * @param None
sahilmgandhi 18:6a4db94011d3 852 * @retval 0 Previous reset source is not from window watch dog reset
sahilmgandhi 18:6a4db94011d3 853 * @retval >=1 Previous reset source is from window watch dog reset
sahilmgandhi 18:6a4db94011d3 854 * @details This macro get previous reset source is from window watch dog reset.
sahilmgandhi 18:6a4db94011d3 855 */
sahilmgandhi 18:6a4db94011d3 856 #define SYS_IS_WDT_RST() (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk)
sahilmgandhi 18:6a4db94011d3 857
sahilmgandhi 18:6a4db94011d3 858 /**
sahilmgandhi 18:6a4db94011d3 859 * @brief Disable Low-Voltage-Reset function
sahilmgandhi 18:6a4db94011d3 860 * @param None
sahilmgandhi 18:6a4db94011d3 861 * @return None
sahilmgandhi 18:6a4db94011d3 862 * @details This macro disable Low-Voltage-Reset function.
sahilmgandhi 18:6a4db94011d3 863 * The register write-protection function should be disabled before using this macro.
sahilmgandhi 18:6a4db94011d3 864 */
sahilmgandhi 18:6a4db94011d3 865 #define SYS_DISABLE_LVR() (SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk)
sahilmgandhi 18:6a4db94011d3 866
sahilmgandhi 18:6a4db94011d3 867 /**
sahilmgandhi 18:6a4db94011d3 868 * @brief Enable Low-Voltage-Reset function
sahilmgandhi 18:6a4db94011d3 869 * @param None
sahilmgandhi 18:6a4db94011d3 870 * @return None
sahilmgandhi 18:6a4db94011d3 871 * @details This macro enable Low-Voltage-Reset function.
sahilmgandhi 18:6a4db94011d3 872 * The register write-protection function should be disabled before using this macro.
sahilmgandhi 18:6a4db94011d3 873 */
sahilmgandhi 18:6a4db94011d3 874 #define SYS_ENABLE_LVR() (SYS->BODCTL |= SYS_BODCTL_LVREN_Msk)
sahilmgandhi 18:6a4db94011d3 875
sahilmgandhi 18:6a4db94011d3 876 /**
sahilmgandhi 18:6a4db94011d3 877 * @brief Disable Power-on Reset function
sahilmgandhi 18:6a4db94011d3 878 * @param None
sahilmgandhi 18:6a4db94011d3 879 * @return None
sahilmgandhi 18:6a4db94011d3 880 * @details This macro disable Power-on Reset function.
sahilmgandhi 18:6a4db94011d3 881 * The register write-protection function should be disabled before using this macro.
sahilmgandhi 18:6a4db94011d3 882 */
sahilmgandhi 18:6a4db94011d3 883 #define SYS_DISABLE_POR() (SYS->PORCTL = 0x5AA5)
sahilmgandhi 18:6a4db94011d3 884
sahilmgandhi 18:6a4db94011d3 885 /**
sahilmgandhi 18:6a4db94011d3 886 * @brief Enable Power-on Reset function
sahilmgandhi 18:6a4db94011d3 887 * @param None
sahilmgandhi 18:6a4db94011d3 888 * @return None
sahilmgandhi 18:6a4db94011d3 889 * @details This macro enable Power-on Reset function.
sahilmgandhi 18:6a4db94011d3 890 * The register write-protection function should be disabled before using this macro.
sahilmgandhi 18:6a4db94011d3 891 */
sahilmgandhi 18:6a4db94011d3 892 #define SYS_ENABLE_POR() (SYS->PORCTL = 0)
sahilmgandhi 18:6a4db94011d3 893
sahilmgandhi 18:6a4db94011d3 894 /**
sahilmgandhi 18:6a4db94011d3 895 * @brief Clear reset source flag
sahilmgandhi 18:6a4db94011d3 896 * @param[in] u32RstSrc is reset source. Including :
sahilmgandhi 18:6a4db94011d3 897 * - \ref SYS_RSTSTS_PORF_Msk
sahilmgandhi 18:6a4db94011d3 898 * - \ref SYS_RSTSTS_PINRF_Msk
sahilmgandhi 18:6a4db94011d3 899 * - \ref SYS_RSTSTS_WDTRF_Msk
sahilmgandhi 18:6a4db94011d3 900 * - \ref SYS_RSTSTS_LVRF_Msk
sahilmgandhi 18:6a4db94011d3 901 * - \ref SYS_RSTSTS_BODRF_Msk
sahilmgandhi 18:6a4db94011d3 902 * - \ref SYS_RSTSTS_SYSRF_Msk
sahilmgandhi 18:6a4db94011d3 903 * - \ref SYS_RSTSTS_CPURF_Msk
sahilmgandhi 18:6a4db94011d3 904 * - \ref SYS_RSTSTS_CPULKRF_Msk
sahilmgandhi 18:6a4db94011d3 905 * @return None
sahilmgandhi 18:6a4db94011d3 906 * @details This macro clear reset source flag.
sahilmgandhi 18:6a4db94011d3 907 */
sahilmgandhi 18:6a4db94011d3 908 #define SYS_CLEAR_RST_SOURCE(u32RstSrc) ((SYS->RSTSTS) = (u32RstSrc) )
sahilmgandhi 18:6a4db94011d3 909
sahilmgandhi 18:6a4db94011d3 910
sahilmgandhi 18:6a4db94011d3 911 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 912 /* static inline functions */
sahilmgandhi 18:6a4db94011d3 913 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 914
sahilmgandhi 18:6a4db94011d3 915
sahilmgandhi 18:6a4db94011d3 916 /**
sahilmgandhi 18:6a4db94011d3 917 * @brief Disable register write-protection function
sahilmgandhi 18:6a4db94011d3 918 * @param None
sahilmgandhi 18:6a4db94011d3 919 * @return None
sahilmgandhi 18:6a4db94011d3 920 * @details This function disable register write-protection function.
sahilmgandhi 18:6a4db94011d3 921 * To unlock the protected register to allow write access.
sahilmgandhi 18:6a4db94011d3 922 */
sahilmgandhi 18:6a4db94011d3 923 __STATIC_INLINE void SYS_UnlockReg(void)
sahilmgandhi 18:6a4db94011d3 924 {
sahilmgandhi 18:6a4db94011d3 925 do
sahilmgandhi 18:6a4db94011d3 926 {
sahilmgandhi 18:6a4db94011d3 927 SYS->REGLCTL = 0x59;
sahilmgandhi 18:6a4db94011d3 928 SYS->REGLCTL = 0x16;
sahilmgandhi 18:6a4db94011d3 929 SYS->REGLCTL = 0x88;
sahilmgandhi 18:6a4db94011d3 930 }
sahilmgandhi 18:6a4db94011d3 931 while(SYS->REGLCTL == 0);
sahilmgandhi 18:6a4db94011d3 932 }
sahilmgandhi 18:6a4db94011d3 933
sahilmgandhi 18:6a4db94011d3 934 /**
sahilmgandhi 18:6a4db94011d3 935 * @brief Enable register write-protection function
sahilmgandhi 18:6a4db94011d3 936 * @param None
sahilmgandhi 18:6a4db94011d3 937 * @return None
sahilmgandhi 18:6a4db94011d3 938 * @details This function is used to enable register write-protection function.
sahilmgandhi 18:6a4db94011d3 939 * To lock the protected register to forbid write access.
sahilmgandhi 18:6a4db94011d3 940 */
sahilmgandhi 18:6a4db94011d3 941 __STATIC_INLINE void SYS_LockReg(void)
sahilmgandhi 18:6a4db94011d3 942 {
sahilmgandhi 18:6a4db94011d3 943 SYS->REGLCTL = 0;
sahilmgandhi 18:6a4db94011d3 944 }
sahilmgandhi 18:6a4db94011d3 945
sahilmgandhi 18:6a4db94011d3 946
sahilmgandhi 18:6a4db94011d3 947 void SYS_ClearResetSrc(uint32_t u32Src);
sahilmgandhi 18:6a4db94011d3 948 uint32_t SYS_GetBODStatus(void);
sahilmgandhi 18:6a4db94011d3 949 uint32_t SYS_GetResetSrc(void);
sahilmgandhi 18:6a4db94011d3 950 uint32_t SYS_IsRegLocked(void);
sahilmgandhi 18:6a4db94011d3 951 uint32_t SYS_ReadPDID(void);
sahilmgandhi 18:6a4db94011d3 952 void SYS_ResetChip(void);
sahilmgandhi 18:6a4db94011d3 953 void SYS_ResetCPU(void);
sahilmgandhi 18:6a4db94011d3 954 void SYS_ResetModule(uint32_t u32ModuleIndex);
sahilmgandhi 18:6a4db94011d3 955 void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel);
sahilmgandhi 18:6a4db94011d3 956 void SYS_DisableBOD(void);
sahilmgandhi 18:6a4db94011d3 957
sahilmgandhi 18:6a4db94011d3 958
sahilmgandhi 18:6a4db94011d3 959 /*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */
sahilmgandhi 18:6a4db94011d3 960
sahilmgandhi 18:6a4db94011d3 961 /*@}*/ /* end of group SYS_Driver */
sahilmgandhi 18:6a4db94011d3 962
sahilmgandhi 18:6a4db94011d3 963 /*@}*/ /* end of group Standard_Driver */
sahilmgandhi 18:6a4db94011d3 964
sahilmgandhi 18:6a4db94011d3 965
sahilmgandhi 18:6a4db94011d3 966 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 967 }
sahilmgandhi 18:6a4db94011d3 968 #endif
sahilmgandhi 18:6a4db94011d3 969
sahilmgandhi 18:6a4db94011d3 970 #endif //__SYS_H__