MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_spi.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /******************************************************************************
sahilmgandhi 18:6a4db94011d3 2 * @file spi.h
sahilmgandhi 18:6a4db94011d3 3 * @version V0.10
sahilmgandhi 18:6a4db94011d3 4 * $Revision: 17 $
sahilmgandhi 18:6a4db94011d3 5 * $Date: 15/08/11 10:26a $
sahilmgandhi 18:6a4db94011d3 6 * @brief M451 series SPI driver header file
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * @note
sahilmgandhi 18:6a4db94011d3 9 * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
sahilmgandhi 18:6a4db94011d3 10 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 11 #ifndef __SPI_H__
sahilmgandhi 18:6a4db94011d3 12 #define __SPI_H__
sahilmgandhi 18:6a4db94011d3 13
sahilmgandhi 18:6a4db94011d3 14 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 15 /* Include related headers */
sahilmgandhi 18:6a4db94011d3 16 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 17 #include "M451Series.h"
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 20 extern "C"
sahilmgandhi 18:6a4db94011d3 21 {
sahilmgandhi 18:6a4db94011d3 22 #endif
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25 /** @addtogroup Standard_Driver Standard Driver
sahilmgandhi 18:6a4db94011d3 26 @{
sahilmgandhi 18:6a4db94011d3 27 */
sahilmgandhi 18:6a4db94011d3 28
sahilmgandhi 18:6a4db94011d3 29 /** @addtogroup SPI_Driver SPI Driver
sahilmgandhi 18:6a4db94011d3 30 @{
sahilmgandhi 18:6a4db94011d3 31 */
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 /** @addtogroup SPI_EXPORTED_CONSTANTS SPI Exported Constants
sahilmgandhi 18:6a4db94011d3 34 @{
sahilmgandhi 18:6a4db94011d3 35 */
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37 #define SPI_MODE_0 (SPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 */
sahilmgandhi 18:6a4db94011d3 38 #define SPI_MODE_1 (SPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 */
sahilmgandhi 18:6a4db94011d3 39 #define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 */
sahilmgandhi 18:6a4db94011d3 40 #define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 */
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 #define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave */
sahilmgandhi 18:6a4db94011d3 43 #define SPI_MASTER (0x0) /*!< Set as master */
sahilmgandhi 18:6a4db94011d3 44
sahilmgandhi 18:6a4db94011d3 45 #define SPI_SS (SPI_SSCTL_SS_Msk) /*!< Set SS */
sahilmgandhi 18:6a4db94011d3 46 #define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk) /*!< SS active high */
sahilmgandhi 18:6a4db94011d3 47 #define SPI_SS_ACTIVE_LOW (0x0) /*!< SS active low */
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 /* SPI Interrupt Mask */
sahilmgandhi 18:6a4db94011d3 50 #define SPI_UNIT_INT_MASK (0x001) /*!< Unit transfer interrupt mask */
sahilmgandhi 18:6a4db94011d3 51 #define SPI_SSACT_INT_MASK (0x002) /*!< Slave selection signal active interrupt mask */
sahilmgandhi 18:6a4db94011d3 52 #define SPI_SSINACT_INT_MASK (0x004) /*!< Slave selection signal inactive interrupt mask */
sahilmgandhi 18:6a4db94011d3 53 #define SPI_SLVUR_INT_MASK (0x008) /*!< Slave under run interrupt mask */
sahilmgandhi 18:6a4db94011d3 54 #define SPI_SLVBE_INT_MASK (0x010) /*!< Slave bit count error interrupt mask */
sahilmgandhi 18:6a4db94011d3 55 #define SPI_SLVTO_INT_MASK (0x020) /*!< Slave time-out interrupt mask */
sahilmgandhi 18:6a4db94011d3 56 #define SPI_TXUF_INT_MASK (0x040) /*!< Slave TX underflow interrupt mask */
sahilmgandhi 18:6a4db94011d3 57 #define SPI_FIFO_TXTH_INT_MASK (0x080) /*!< FIFO TX threshold interrupt mask */
sahilmgandhi 18:6a4db94011d3 58 #define SPI_FIFO_RXTH_INT_MASK (0x100) /*!< FIFO RX threshold interrupt mask */
sahilmgandhi 18:6a4db94011d3 59 #define SPI_FIFO_RXOV_INT_MASK (0x200) /*!< FIFO RX overrun interrupt mask */
sahilmgandhi 18:6a4db94011d3 60 #define SPI_FIFO_RXTO_INT_MASK (0x400) /*!< FIFO RX time-out interrupt mask */
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62 /* SPI Status Mask */
sahilmgandhi 18:6a4db94011d3 63 #define SPI_BUSY_MASK (0x01) /*!< Busy status mask */
sahilmgandhi 18:6a4db94011d3 64 #define SPI_RX_EMPTY_MASK (0x02) /*!< RX empty status mask */
sahilmgandhi 18:6a4db94011d3 65 #define SPI_RX_FULL_MASK (0x04) /*!< RX full status mask */
sahilmgandhi 18:6a4db94011d3 66 #define SPI_TX_EMPTY_MASK (0x08) /*!< TX empty status mask */
sahilmgandhi 18:6a4db94011d3 67 #define SPI_TX_FULL_MASK (0x10) /*!< TX full status mask */
sahilmgandhi 18:6a4db94011d3 68 #define SPI_TXRX_RESET_MASK (0x20) /*!< TX or RX reset status mask */
sahilmgandhi 18:6a4db94011d3 69 #define SPI_SPIEN_STS_MASK (0x40) /*!< SPIEN status mask */
sahilmgandhi 18:6a4db94011d3 70 #define SPI_SSLINE_STS_MASK (0x80) /*!< SPIn_SS line status mask */
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72
sahilmgandhi 18:6a4db94011d3 73 /* I2S Data Width */
sahilmgandhi 18:6a4db94011d3 74 #define I2S_DATABIT_8 (0 << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 8-bit */
sahilmgandhi 18:6a4db94011d3 75 #define I2S_DATABIT_16 (1 << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 16-bit */
sahilmgandhi 18:6a4db94011d3 76 #define I2S_DATABIT_24 (2 << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 24-bit */
sahilmgandhi 18:6a4db94011d3 77 #define I2S_DATABIT_32 (3 << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 32-bit */
sahilmgandhi 18:6a4db94011d3 78
sahilmgandhi 18:6a4db94011d3 79 /* I2S Audio Format */
sahilmgandhi 18:6a4db94011d3 80 #define I2S_MONO SPI_I2SCTL_MONO_Msk /*!< Monaural channel */
sahilmgandhi 18:6a4db94011d3 81 #define I2S_STEREO 0 /*!< Stereo channel */
sahilmgandhi 18:6a4db94011d3 82
sahilmgandhi 18:6a4db94011d3 83 /* I2S Data Format */
sahilmgandhi 18:6a4db94011d3 84 #define I2S_FORMAT_I2S (0<<SPI_I2SCTL_FORMAT_Pos) /*!< I2S data format */
sahilmgandhi 18:6a4db94011d3 85 #define I2S_FORMAT_MSB (1<<SPI_I2SCTL_FORMAT_Pos) /*!< MSB justified data format */
sahilmgandhi 18:6a4db94011d3 86 #define I2S_FORMAT_PCMA (2<<SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode A data format */
sahilmgandhi 18:6a4db94011d3 87 #define I2S_FORMAT_PCMB (3<<SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode B data format */
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 /* I2S Operation mode */
sahilmgandhi 18:6a4db94011d3 90 #define I2S_MODE_SLAVE SPI_I2SCTL_SLAVE_Msk /*!< As slave mode */
sahilmgandhi 18:6a4db94011d3 91 #define I2S_MODE_MASTER 0 /*!< As master mode */
sahilmgandhi 18:6a4db94011d3 92
sahilmgandhi 18:6a4db94011d3 93 /* I2S TX FIFO Threshold */
sahilmgandhi 18:6a4db94011d3 94 #define I2S_FIFO_TX_LEVEL_WORD_0 0 /*!< TX threshold is 0 word */
sahilmgandhi 18:6a4db94011d3 95 #define I2S_FIFO_TX_LEVEL_WORD_1 (1 << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 1 word */
sahilmgandhi 18:6a4db94011d3 96 #define I2S_FIFO_TX_LEVEL_WORD_2 (2 << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 2 words */
sahilmgandhi 18:6a4db94011d3 97 #define I2S_FIFO_TX_LEVEL_WORD_3 (3 << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 3 words */
sahilmgandhi 18:6a4db94011d3 98 /* I2S RX FIFO Threshold */
sahilmgandhi 18:6a4db94011d3 99 #define I2S_FIFO_RX_LEVEL_WORD_1 0 /*!< RX threshold is 1 word */
sahilmgandhi 18:6a4db94011d3 100 #define I2S_FIFO_RX_LEVEL_WORD_2 (1 << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 2 words */
sahilmgandhi 18:6a4db94011d3 101 #define I2S_FIFO_RX_LEVEL_WORD_3 (2 << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 3 words */
sahilmgandhi 18:6a4db94011d3 102 #define I2S_FIFO_RX_LEVEL_WORD_4 (3 << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 4 words */
sahilmgandhi 18:6a4db94011d3 103
sahilmgandhi 18:6a4db94011d3 104 /* I2S Record Channel */
sahilmgandhi 18:6a4db94011d3 105 #define I2S_MONO_RIGHT 0 /*!< Record mono right channel */
sahilmgandhi 18:6a4db94011d3 106 #define I2S_MONO_LEFT SPI_I2SCTL_RXLCH_Msk /*!< Record mono left channel */
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 /* I2S Channel */
sahilmgandhi 18:6a4db94011d3 109 #define I2S_RIGHT 0 /*!< Select right channel */
sahilmgandhi 18:6a4db94011d3 110 #define I2S_LEFT 1 /*!< Select left channel */
sahilmgandhi 18:6a4db94011d3 111
sahilmgandhi 18:6a4db94011d3 112 /* I2S Interrupt Mask */
sahilmgandhi 18:6a4db94011d3 113 #define I2S_FIFO_TXTH_INT_MASK (0x01) /*!< TX FIFO threshold interrupt mask */
sahilmgandhi 18:6a4db94011d3 114 #define I2S_FIFO_RXTH_INT_MASK (0x02) /*!< RX FIFO threshold interrupt mask */
sahilmgandhi 18:6a4db94011d3 115 #define I2S_FIFO_RXOV_INT_MASK (0x04) /*!< RX FIFO overrun interrupt mask */
sahilmgandhi 18:6a4db94011d3 116 #define I2S_FIFO_RXTO_INT_MASK (0x08) /*!< RX FIFO time-out interrupt mask */
sahilmgandhi 18:6a4db94011d3 117 #define I2S_TXUF_INT_MASK (0x10) /*!< TX FIFO underflow interrupt mask */
sahilmgandhi 18:6a4db94011d3 118 #define I2S_RIGHT_ZC_INT_MASK (0x20) /*!< Right channel zero cross interrupt mask */
sahilmgandhi 18:6a4db94011d3 119 #define I2S_LEFT_ZC_INT_MASK (0x40) /*!< Left channel zero cross interrupt mask */
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 /*@}*/ /* end of group SPI_EXPORTED_CONSTANTS */
sahilmgandhi 18:6a4db94011d3 122
sahilmgandhi 18:6a4db94011d3 123
sahilmgandhi 18:6a4db94011d3 124 /** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions
sahilmgandhi 18:6a4db94011d3 125 @{
sahilmgandhi 18:6a4db94011d3 126 */
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 /**
sahilmgandhi 18:6a4db94011d3 129 * @brief Clear the unit transfer interrupt flag.
sahilmgandhi 18:6a4db94011d3 130 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 131 * @return None.
sahilmgandhi 18:6a4db94011d3 132 * @details Write 1 to UNITIF bit of SPI_STATUS register to clear the unit transfer interrupt flag.
sahilmgandhi 18:6a4db94011d3 133 */
sahilmgandhi 18:6a4db94011d3 134 #define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ((spi)->STATUS = SPI_STATUS_UNITIF_Msk)
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 /**
sahilmgandhi 18:6a4db94011d3 137 * @brief Disable 2-bit Transfer mode.
sahilmgandhi 18:6a4db94011d3 138 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 139 * @return None.
sahilmgandhi 18:6a4db94011d3 140 * @details Clear TWOBIT bit of SPI_CTL register to disable 2-bit Transfer mode.
sahilmgandhi 18:6a4db94011d3 141 */
sahilmgandhi 18:6a4db94011d3 142 #define SPI_DISABLE_2BIT_MODE(spi) ((spi)->CTL &= ~SPI_CTL_TWOBIT_Msk)
sahilmgandhi 18:6a4db94011d3 143
sahilmgandhi 18:6a4db94011d3 144 /**
sahilmgandhi 18:6a4db94011d3 145 * @brief Disable Slave 3-wire mode.
sahilmgandhi 18:6a4db94011d3 146 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 147 * @return None.
sahilmgandhi 18:6a4db94011d3 148 * @details Clear SLV3WIRE bit of SPI_SSCTL register to disable Slave 3-wire mode.
sahilmgandhi 18:6a4db94011d3 149 */
sahilmgandhi 18:6a4db94011d3 150 #define SPI_DISABLE_3WIRE_MODE(spi) ((spi)->SSCTL &= ~SPI_SSCTL_SLV3WIRE_Msk)
sahilmgandhi 18:6a4db94011d3 151
sahilmgandhi 18:6a4db94011d3 152 /**
sahilmgandhi 18:6a4db94011d3 153 * @brief Disable Dual I/O mode.
sahilmgandhi 18:6a4db94011d3 154 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 155 * @return None.
sahilmgandhi 18:6a4db94011d3 156 * @details Clear DUALIOEN bit of SPI_CTL register to disable Dual I/O mode.
sahilmgandhi 18:6a4db94011d3 157 */
sahilmgandhi 18:6a4db94011d3 158 #define SPI_DISABLE_DUAL_MODE(spi) ((spi)->CTL &= ~SPI_CTL_DUALIOEN_Msk)
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 /**
sahilmgandhi 18:6a4db94011d3 161 * @brief Disable Quad I/O mode.
sahilmgandhi 18:6a4db94011d3 162 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 163 * @return None.
sahilmgandhi 18:6a4db94011d3 164 * @details Clear QUADIOEN bit of SPI_CTL register to disable Quad I/O mode.
sahilmgandhi 18:6a4db94011d3 165 */
sahilmgandhi 18:6a4db94011d3 166 #define SPI_DISABLE_QUAD_MODE(spi) ((spi)->CTL &= ~SPI_CTL_QUADIOEN_Msk)
sahilmgandhi 18:6a4db94011d3 167
sahilmgandhi 18:6a4db94011d3 168 /**
sahilmgandhi 18:6a4db94011d3 169 * @brief Enable 2-bit Transfer mode.
sahilmgandhi 18:6a4db94011d3 170 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 171 * @return None.
sahilmgandhi 18:6a4db94011d3 172 * @details Set TWOBIT bit of SPI_CTL register to enable 2-bit Transfer mode.
sahilmgandhi 18:6a4db94011d3 173 */
sahilmgandhi 18:6a4db94011d3 174 #define SPI_ENABLE_2BIT_MODE(spi) ((spi)->CTL |= SPI_CTL_TWOBIT_Msk)
sahilmgandhi 18:6a4db94011d3 175
sahilmgandhi 18:6a4db94011d3 176 /**
sahilmgandhi 18:6a4db94011d3 177 * @brief Enable Slave 3-wire mode.
sahilmgandhi 18:6a4db94011d3 178 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 179 * @return None.
sahilmgandhi 18:6a4db94011d3 180 * @details Set SLV3WIRE bit of SPI_SSCTL register to enable Slave 3-wire mode.
sahilmgandhi 18:6a4db94011d3 181 */
sahilmgandhi 18:6a4db94011d3 182 #define SPI_ENABLE_3WIRE_MODE(spi) ((spi)->SSCTL |= SPI_SSCTL_SLV3WIRE_Msk)
sahilmgandhi 18:6a4db94011d3 183
sahilmgandhi 18:6a4db94011d3 184 /**
sahilmgandhi 18:6a4db94011d3 185 * @brief Enable Dual input mode.
sahilmgandhi 18:6a4db94011d3 186 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 187 * @return None.
sahilmgandhi 18:6a4db94011d3 188 * @details Clear QDIODIR bit and set DUALIOEN bit of SPI_CTL register to enable Dual input mode.
sahilmgandhi 18:6a4db94011d3 189 */
sahilmgandhi 18:6a4db94011d3 190 #define SPI_ENABLE_DUAL_INPUT_MODE(spi) ((spi)->CTL = ((spi)->CTL & (~SPI_CTL_QDIODIR_Msk)) | SPI_CTL_DUALIOEN_Msk)
sahilmgandhi 18:6a4db94011d3 191
sahilmgandhi 18:6a4db94011d3 192 /**
sahilmgandhi 18:6a4db94011d3 193 * @brief Enable Dual output mode.
sahilmgandhi 18:6a4db94011d3 194 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 195 * @return None.
sahilmgandhi 18:6a4db94011d3 196 * @details Set QDIODIR bit and DUALIOEN bit of SPI_CTL register to enable Dual output mode.
sahilmgandhi 18:6a4db94011d3 197 */
sahilmgandhi 18:6a4db94011d3 198 #define SPI_ENABLE_DUAL_OUTPUT_MODE(spi) ((spi)->CTL |= (SPI_CTL_QDIODIR_Msk | SPI_CTL_DUALIOEN_Msk))
sahilmgandhi 18:6a4db94011d3 199
sahilmgandhi 18:6a4db94011d3 200 /**
sahilmgandhi 18:6a4db94011d3 201 * @brief Enable Quad input mode.
sahilmgandhi 18:6a4db94011d3 202 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 203 * @return None.
sahilmgandhi 18:6a4db94011d3 204 * @details Clear QDIODIR bit and set QUADIOEN bit of SPI_CTL register to enable Quad input mode.
sahilmgandhi 18:6a4db94011d3 205 */
sahilmgandhi 18:6a4db94011d3 206 #define SPI_ENABLE_QUAD_INPUT_MODE(spi) ((spi)->CTL = ((spi)->CTL & (~SPI_CTL_QDIODIR_Msk)) | SPI_CTL_QUADIOEN_Msk)
sahilmgandhi 18:6a4db94011d3 207
sahilmgandhi 18:6a4db94011d3 208 /**
sahilmgandhi 18:6a4db94011d3 209 * @brief Enable Quad output mode.
sahilmgandhi 18:6a4db94011d3 210 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 211 * @return None.
sahilmgandhi 18:6a4db94011d3 212 * @details Set QDIODIR bit and QUADIOEN bit of SPI_CTL register to enable Quad output mode.
sahilmgandhi 18:6a4db94011d3 213 */
sahilmgandhi 18:6a4db94011d3 214 #define SPI_ENABLE_QUAD_OUTPUT_MODE(spi) ((spi)->CTL |= (SPI_CTL_QDIODIR_Msk | SPI_CTL_QUADIOEN_Msk))
sahilmgandhi 18:6a4db94011d3 215
sahilmgandhi 18:6a4db94011d3 216 /**
sahilmgandhi 18:6a4db94011d3 217 * @brief Trigger RX PDMA function.
sahilmgandhi 18:6a4db94011d3 218 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 219 * @return None.
sahilmgandhi 18:6a4db94011d3 220 * @details Set RXPDMAEN bit of SPI_PDMACTL register to enable RX PDMA transfer function.
sahilmgandhi 18:6a4db94011d3 221 */
sahilmgandhi 18:6a4db94011d3 222 #define SPI_TRIGGER_RX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk)
sahilmgandhi 18:6a4db94011d3 223
sahilmgandhi 18:6a4db94011d3 224 /**
sahilmgandhi 18:6a4db94011d3 225 * @brief Trigger TX PDMA function.
sahilmgandhi 18:6a4db94011d3 226 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 227 * @return None.
sahilmgandhi 18:6a4db94011d3 228 * @details Set TXPDMAEN bit of SPI_PDMACTL register to enable TX PDMA transfer function.
sahilmgandhi 18:6a4db94011d3 229 */
sahilmgandhi 18:6a4db94011d3 230 #define SPI_TRIGGER_TX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk)
sahilmgandhi 18:6a4db94011d3 231
sahilmgandhi 18:6a4db94011d3 232 /**
sahilmgandhi 18:6a4db94011d3 233 * @brief Disable RX PDMA transfer.
sahilmgandhi 18:6a4db94011d3 234 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 235 * @return None.
sahilmgandhi 18:6a4db94011d3 236 * @details Clear RXPDMAEN bit of SPI_PDMACTL register to disable RX PDMA transfer function.
sahilmgandhi 18:6a4db94011d3 237 */
sahilmgandhi 18:6a4db94011d3 238 #define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
sahilmgandhi 18:6a4db94011d3 239
sahilmgandhi 18:6a4db94011d3 240 /**
sahilmgandhi 18:6a4db94011d3 241 * @brief Disable TX PDMA transfer.
sahilmgandhi 18:6a4db94011d3 242 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 243 * @return None.
sahilmgandhi 18:6a4db94011d3 244 * @details Clear TXPDMAEN bit of SPI_PDMACTL register to disable TX PDMA transfer function.
sahilmgandhi 18:6a4db94011d3 245 */
sahilmgandhi 18:6a4db94011d3 246 #define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
sahilmgandhi 18:6a4db94011d3 247
sahilmgandhi 18:6a4db94011d3 248 /**
sahilmgandhi 18:6a4db94011d3 249 * @brief Get the count of available data in RX FIFO.
sahilmgandhi 18:6a4db94011d3 250 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 251 * @return The count of available data in RX FIFO.
sahilmgandhi 18:6a4db94011d3 252 * @details Read RXCNT (SPI_STATUS[27:24]) to get the count of available data in RX FIFO.
sahilmgandhi 18:6a4db94011d3 253 */
sahilmgandhi 18:6a4db94011d3 254 #define SPI_GET_RX_FIFO_COUNT(spi) (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos)
sahilmgandhi 18:6a4db94011d3 255
sahilmgandhi 18:6a4db94011d3 256 /**
sahilmgandhi 18:6a4db94011d3 257 * @brief Get the RX FIFO empty flag.
sahilmgandhi 18:6a4db94011d3 258 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 259 * @retval 0 RX FIFO is not empty.
sahilmgandhi 18:6a4db94011d3 260 * @retval 1 RX FIFO is empty.
sahilmgandhi 18:6a4db94011d3 261 * @details Read RXEMPTY bit of SPI_STATUS register to get the RX FIFO empty flag.
sahilmgandhi 18:6a4db94011d3 262 */
sahilmgandhi 18:6a4db94011d3 263 #define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk)>>SPI_STATUS_RXEMPTY_Pos)
sahilmgandhi 18:6a4db94011d3 264
sahilmgandhi 18:6a4db94011d3 265 /**
sahilmgandhi 18:6a4db94011d3 266 * @brief Get the TX FIFO empty flag.
sahilmgandhi 18:6a4db94011d3 267 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 268 * @retval 0 TX FIFO is not empty.
sahilmgandhi 18:6a4db94011d3 269 * @retval 1 TX FIFO is empty.
sahilmgandhi 18:6a4db94011d3 270 * @details Read TXEMPTY bit of SPI_STATUS register to get the TX FIFO empty flag.
sahilmgandhi 18:6a4db94011d3 271 */
sahilmgandhi 18:6a4db94011d3 272 #define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk)>>SPI_STATUS_TXEMPTY_Pos)
sahilmgandhi 18:6a4db94011d3 273
sahilmgandhi 18:6a4db94011d3 274 /**
sahilmgandhi 18:6a4db94011d3 275 * @brief Get the TX FIFO full flag.
sahilmgandhi 18:6a4db94011d3 276 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 277 * @retval 0 TX FIFO is not full.
sahilmgandhi 18:6a4db94011d3 278 * @retval 1 TX FIFO is full.
sahilmgandhi 18:6a4db94011d3 279 * @details Read TXFULL bit of SPI_STATUS register to get the TX FIFO full flag.
sahilmgandhi 18:6a4db94011d3 280 */
sahilmgandhi 18:6a4db94011d3 281 #define SPI_GET_TX_FIFO_FULL_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXFULL_Msk)>>SPI_STATUS_TXFULL_Pos)
sahilmgandhi 18:6a4db94011d3 282
sahilmgandhi 18:6a4db94011d3 283 /**
sahilmgandhi 18:6a4db94011d3 284 * @brief Get the datum read from RX register.
sahilmgandhi 18:6a4db94011d3 285 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 286 * @return Data in RX register.
sahilmgandhi 18:6a4db94011d3 287 * @details Read SPI_RX register to get the received datum.
sahilmgandhi 18:6a4db94011d3 288 */
sahilmgandhi 18:6a4db94011d3 289 #define SPI_READ_RX(spi) ((spi)->RX)
sahilmgandhi 18:6a4db94011d3 290
sahilmgandhi 18:6a4db94011d3 291 /**
sahilmgandhi 18:6a4db94011d3 292 * @brief Write datum to TX register.
sahilmgandhi 18:6a4db94011d3 293 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 294 * @param[in] u32TxData The datum which user attempt to transfer through SPI bus.
sahilmgandhi 18:6a4db94011d3 295 * @return None.
sahilmgandhi 18:6a4db94011d3 296 * @details Write u32TxData to SPI_TX register.
sahilmgandhi 18:6a4db94011d3 297 */
sahilmgandhi 18:6a4db94011d3 298 #define SPI_WRITE_TX(spi, u32TxData) ((spi)->TX = (u32TxData))
sahilmgandhi 18:6a4db94011d3 299
sahilmgandhi 18:6a4db94011d3 300 /**
sahilmgandhi 18:6a4db94011d3 301 * @brief Set SPIn_SS pin to high state.
sahilmgandhi 18:6a4db94011d3 302 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 303 * @return None.
sahilmgandhi 18:6a4db94011d3 304 * @details Disable automatic slave selection function and set SPIn_SS pin to high state.
sahilmgandhi 18:6a4db94011d3 305 */
sahilmgandhi 18:6a4db94011d3 306 #define SPI_SET_SS_HIGH(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))
sahilmgandhi 18:6a4db94011d3 307
sahilmgandhi 18:6a4db94011d3 308 /**
sahilmgandhi 18:6a4db94011d3 309 * @brief Set SPIn_SS pin to low state.
sahilmgandhi 18:6a4db94011d3 310 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 311 * @return None.
sahilmgandhi 18:6a4db94011d3 312 * @details Disable automatic slave selection function and set SPIn_SS pin to low state.
sahilmgandhi 18:6a4db94011d3 313 */
sahilmgandhi 18:6a4db94011d3 314 #define SPI_SET_SS_LOW(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk)
sahilmgandhi 18:6a4db94011d3 315
sahilmgandhi 18:6a4db94011d3 316 /**
sahilmgandhi 18:6a4db94011d3 317 * @brief Enable Byte Reorder function.
sahilmgandhi 18:6a4db94011d3 318 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 319 * @return None.
sahilmgandhi 18:6a4db94011d3 320 * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4]).
sahilmgandhi 18:6a4db94011d3 321 */
sahilmgandhi 18:6a4db94011d3 322 #define SPI_ENABLE_BYTE_REORDER(spi) ((spi)->CTL |= SPI_CTL_REORDER_Msk)
sahilmgandhi 18:6a4db94011d3 323
sahilmgandhi 18:6a4db94011d3 324 /**
sahilmgandhi 18:6a4db94011d3 325 * @brief Disable Byte Reorder function.
sahilmgandhi 18:6a4db94011d3 326 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 327 * @return None.
sahilmgandhi 18:6a4db94011d3 328 * @details Clear REORDER bit field of SPI_CTL register to disable Byte Reorder function.
sahilmgandhi 18:6a4db94011d3 329 */
sahilmgandhi 18:6a4db94011d3 330 #define SPI_DISABLE_BYTE_REORDER(spi) ((spi)->CTL &= ~SPI_CTL_REORDER_Msk)
sahilmgandhi 18:6a4db94011d3 331
sahilmgandhi 18:6a4db94011d3 332 /**
sahilmgandhi 18:6a4db94011d3 333 * @brief Set the length of suspend interval.
sahilmgandhi 18:6a4db94011d3 334 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 335 * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15.
sahilmgandhi 18:6a4db94011d3 336 * @return None.
sahilmgandhi 18:6a4db94011d3 337 * @details Set the length of suspend interval according to u32SuspCycle.
sahilmgandhi 18:6a4db94011d3 338 * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle).
sahilmgandhi 18:6a4db94011d3 339 */
sahilmgandhi 18:6a4db94011d3 340 #define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos))
sahilmgandhi 18:6a4db94011d3 341
sahilmgandhi 18:6a4db94011d3 342 /**
sahilmgandhi 18:6a4db94011d3 343 * @brief Set the SPI transfer sequence with LSB first.
sahilmgandhi 18:6a4db94011d3 344 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 345 * @return None.
sahilmgandhi 18:6a4db94011d3 346 * @details Set LSB bit of SPI_CTL register to set the SPI transfer sequence with LSB first.
sahilmgandhi 18:6a4db94011d3 347 */
sahilmgandhi 18:6a4db94011d3 348 #define SPI_SET_LSB_FIRST(spi) ((spi)->CTL |= SPI_CTL_LSB_Msk)
sahilmgandhi 18:6a4db94011d3 349
sahilmgandhi 18:6a4db94011d3 350 /**
sahilmgandhi 18:6a4db94011d3 351 * @brief Set the SPI transfer sequence with MSB first.
sahilmgandhi 18:6a4db94011d3 352 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 353 * @return None.
sahilmgandhi 18:6a4db94011d3 354 * @details Clear LSB bit of SPI_CTL register to set the SPI transfer sequence with MSB first.
sahilmgandhi 18:6a4db94011d3 355 */
sahilmgandhi 18:6a4db94011d3 356 #define SPI_SET_MSB_FIRST(spi) ((spi)->CTL &= ~SPI_CTL_LSB_Msk)
sahilmgandhi 18:6a4db94011d3 357
sahilmgandhi 18:6a4db94011d3 358 /**
sahilmgandhi 18:6a4db94011d3 359 * @brief Set the data width of a SPI transaction.
sahilmgandhi 18:6a4db94011d3 360 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 361 * @param[in] u32Width The bit width of one transaction.
sahilmgandhi 18:6a4db94011d3 362 * @return None.
sahilmgandhi 18:6a4db94011d3 363 * @details The data width can be 8 ~ 32 bits.
sahilmgandhi 18:6a4db94011d3 364 */
sahilmgandhi 18:6a4db94011d3 365 #define SPI_SET_DATA_WIDTH(spi, u32Width) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << SPI_CTL_DWIDTH_Pos))
sahilmgandhi 18:6a4db94011d3 366
sahilmgandhi 18:6a4db94011d3 367 /**
sahilmgandhi 18:6a4db94011d3 368 * @brief Get the SPI busy state.
sahilmgandhi 18:6a4db94011d3 369 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 370 * @retval 0 SPI controller is not busy.
sahilmgandhi 18:6a4db94011d3 371 * @retval 1 SPI controller is busy.
sahilmgandhi 18:6a4db94011d3 372 * @details This macro will return the busy state of SPI controller.
sahilmgandhi 18:6a4db94011d3 373 */
sahilmgandhi 18:6a4db94011d3 374 #define SPI_IS_BUSY(spi) ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk)>>SPI_STATUS_BUSY_Pos )
sahilmgandhi 18:6a4db94011d3 375
sahilmgandhi 18:6a4db94011d3 376 /**
sahilmgandhi 18:6a4db94011d3 377 * @brief Enable SPI controller.
sahilmgandhi 18:6a4db94011d3 378 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 379 * @return None.
sahilmgandhi 18:6a4db94011d3 380 * @details Set SPIEN (SPI_CTL[0]) to enable SPI controller.
sahilmgandhi 18:6a4db94011d3 381 */
sahilmgandhi 18:6a4db94011d3 382 #define SPI_ENABLE(spi) ((spi)->CTL |= SPI_CTL_SPIEN_Msk)
sahilmgandhi 18:6a4db94011d3 383
sahilmgandhi 18:6a4db94011d3 384 /**
sahilmgandhi 18:6a4db94011d3 385 * @brief Disable SPI controller.
sahilmgandhi 18:6a4db94011d3 386 * @param[in] spi The pointer of the specified SPI module.
sahilmgandhi 18:6a4db94011d3 387 * @return None.
sahilmgandhi 18:6a4db94011d3 388 * @details Clear SPIEN (SPI_CTL[0]) to disable SPI controller.
sahilmgandhi 18:6a4db94011d3 389 */
sahilmgandhi 18:6a4db94011d3 390 #define SPI_DISABLE(spi) ((spi)->CTL &= ~SPI_CTL_SPIEN_Msk)
sahilmgandhi 18:6a4db94011d3 391
sahilmgandhi 18:6a4db94011d3 392
sahilmgandhi 18:6a4db94011d3 393 /**
sahilmgandhi 18:6a4db94011d3 394 * @brief Enable zero cross detection function.
sahilmgandhi 18:6a4db94011d3 395 * @param[in] i2s The pointer of the specified I2S module.
sahilmgandhi 18:6a4db94011d3 396 * @param[in] u32ChMask The mask for left or right channel. Valid values are:
sahilmgandhi 18:6a4db94011d3 397 * - \ref I2S_RIGHT
sahilmgandhi 18:6a4db94011d3 398 * - \ref I2S_LEFT
sahilmgandhi 18:6a4db94011d3 399 * @return None
sahilmgandhi 18:6a4db94011d3 400 * @details This function will set RZCEN or LZCEN bit of SPI_I2SCTL register to enable zero cross detection function.
sahilmgandhi 18:6a4db94011d3 401 */
sahilmgandhi 18:6a4db94011d3 402 static __INLINE void I2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
sahilmgandhi 18:6a4db94011d3 403 {
sahilmgandhi 18:6a4db94011d3 404 if(u32ChMask == I2S_RIGHT)
sahilmgandhi 18:6a4db94011d3 405 i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk;
sahilmgandhi 18:6a4db94011d3 406 else
sahilmgandhi 18:6a4db94011d3 407 i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk;
sahilmgandhi 18:6a4db94011d3 408 }
sahilmgandhi 18:6a4db94011d3 409
sahilmgandhi 18:6a4db94011d3 410 /**
sahilmgandhi 18:6a4db94011d3 411 * @brief Disable zero cross detection function.
sahilmgandhi 18:6a4db94011d3 412 * @param[in] i2s The pointer of the specified I2S module.
sahilmgandhi 18:6a4db94011d3 413 * @param[in] u32ChMask The mask for left or right channel. Valid values are:
sahilmgandhi 18:6a4db94011d3 414 * - \ref I2S_RIGHT
sahilmgandhi 18:6a4db94011d3 415 * - \ref I2S_LEFT
sahilmgandhi 18:6a4db94011d3 416 * @return None
sahilmgandhi 18:6a4db94011d3 417 * @details This function will clear RZCEN or LZCEN bit of SPI_I2SCTL register to disable zero cross detection function.
sahilmgandhi 18:6a4db94011d3 418 */
sahilmgandhi 18:6a4db94011d3 419 static __INLINE void I2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
sahilmgandhi 18:6a4db94011d3 420 {
sahilmgandhi 18:6a4db94011d3 421 if(u32ChMask == I2S_RIGHT)
sahilmgandhi 18:6a4db94011d3 422 i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk;
sahilmgandhi 18:6a4db94011d3 423 else
sahilmgandhi 18:6a4db94011d3 424 i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk;
sahilmgandhi 18:6a4db94011d3 425 }
sahilmgandhi 18:6a4db94011d3 426
sahilmgandhi 18:6a4db94011d3 427 /**
sahilmgandhi 18:6a4db94011d3 428 * @brief Enable I2S TX DMA function.
sahilmgandhi 18:6a4db94011d3 429 * @param[in] i2s The pointer of the specified I2S module.
sahilmgandhi 18:6a4db94011d3 430 * @return None
sahilmgandhi 18:6a4db94011d3 431 * @details This macro will set TXPDMAEN bit of SPI_PDMACTL register to transmit data with PDMA.
sahilmgandhi 18:6a4db94011d3 432 */
sahilmgandhi 18:6a4db94011d3 433 #define I2S_ENABLE_TXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk )
sahilmgandhi 18:6a4db94011d3 434
sahilmgandhi 18:6a4db94011d3 435 /**
sahilmgandhi 18:6a4db94011d3 436 * @brief Disable I2S TX DMA function.
sahilmgandhi 18:6a4db94011d3 437 * @param[in] i2s The pointer of the specified I2S module.
sahilmgandhi 18:6a4db94011d3 438 * @return None
sahilmgandhi 18:6a4db94011d3 439 * @details This macro will clear TXPDMAEN bit of SPI_PDMACTL register to disable TX DMA function.
sahilmgandhi 18:6a4db94011d3 440 */
sahilmgandhi 18:6a4db94011d3 441 #define I2S_DISABLE_TXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
sahilmgandhi 18:6a4db94011d3 442
sahilmgandhi 18:6a4db94011d3 443 /**
sahilmgandhi 18:6a4db94011d3 444 * @brief Enable I2S RX DMA function.
sahilmgandhi 18:6a4db94011d3 445 * @param[in] i2s The pointer of the specified I2S module.
sahilmgandhi 18:6a4db94011d3 446 * @return None
sahilmgandhi 18:6a4db94011d3 447 * @details This macro will set RXPDMAEN bit of SPI_PDMACTL register to receive data with PDMA.
sahilmgandhi 18:6a4db94011d3 448 */
sahilmgandhi 18:6a4db94011d3 449 #define I2S_ENABLE_RXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk )
sahilmgandhi 18:6a4db94011d3 450
sahilmgandhi 18:6a4db94011d3 451 /**
sahilmgandhi 18:6a4db94011d3 452 * @brief Disable I2S RX DMA function.
sahilmgandhi 18:6a4db94011d3 453 * @param[in] i2s The pointer of the specified I2S module.
sahilmgandhi 18:6a4db94011d3 454 * @return None
sahilmgandhi 18:6a4db94011d3 455 * @details This macro will clear RXPDMAEN bit of SPI_PDMACTL register to disable RX DMA function.
sahilmgandhi 18:6a4db94011d3 456 */
sahilmgandhi 18:6a4db94011d3 457 #define I2S_DISABLE_RXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
sahilmgandhi 18:6a4db94011d3 458
sahilmgandhi 18:6a4db94011d3 459 /**
sahilmgandhi 18:6a4db94011d3 460 * @brief Enable I2S TX function.
sahilmgandhi 18:6a4db94011d3 461 * @param[in] i2s The pointer of the specified I2S module.
sahilmgandhi 18:6a4db94011d3 462 * @return None
sahilmgandhi 18:6a4db94011d3 463 * @details This macro will set TXEN bit of SPI_I2SCTL register to enable I2S TX function.
sahilmgandhi 18:6a4db94011d3 464 */
sahilmgandhi 18:6a4db94011d3 465 #define I2S_ENABLE_TX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk )
sahilmgandhi 18:6a4db94011d3 466
sahilmgandhi 18:6a4db94011d3 467 /**
sahilmgandhi 18:6a4db94011d3 468 * @brief Disable I2S TX function.
sahilmgandhi 18:6a4db94011d3 469 * @param[in] i2s The pointer of the specified I2S module.
sahilmgandhi 18:6a4db94011d3 470 * @return None
sahilmgandhi 18:6a4db94011d3 471 * @details This macro will clear TXEN bit of SPI_I2SCTL register to disable I2S TX function.
sahilmgandhi 18:6a4db94011d3 472 */
sahilmgandhi 18:6a4db94011d3 473 #define I2S_DISABLE_TX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk )
sahilmgandhi 18:6a4db94011d3 474
sahilmgandhi 18:6a4db94011d3 475 /**
sahilmgandhi 18:6a4db94011d3 476 * @brief Enable I2S RX function.
sahilmgandhi 18:6a4db94011d3 477 * @param[in] i2s The pointer of the specified I2S module.
sahilmgandhi 18:6a4db94011d3 478 * @return None
sahilmgandhi 18:6a4db94011d3 479 * @details This macro will set RXEN bit of SPI_I2SCTL register to enable I2S RX function.
sahilmgandhi 18:6a4db94011d3 480 */
sahilmgandhi 18:6a4db94011d3 481 #define I2S_ENABLE_RX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk )
sahilmgandhi 18:6a4db94011d3 482
sahilmgandhi 18:6a4db94011d3 483 /**
sahilmgandhi 18:6a4db94011d3 484 * @brief Disable I2S RX function.
sahilmgandhi 18:6a4db94011d3 485 * @param[in] i2s The pointer of the specified I2S module.
sahilmgandhi 18:6a4db94011d3 486 * @return None
sahilmgandhi 18:6a4db94011d3 487 * @details This macro will clear RXEN bit of SPI_I2SCTL register to disable I2S RX function.
sahilmgandhi 18:6a4db94011d3 488 */
sahilmgandhi 18:6a4db94011d3 489 #define I2S_DISABLE_RX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk )
sahilmgandhi 18:6a4db94011d3 490
sahilmgandhi 18:6a4db94011d3 491 /**
sahilmgandhi 18:6a4db94011d3 492 * @brief Enable TX Mute function.
sahilmgandhi 18:6a4db94011d3 493 * @param[in] i2s The pointer of the specified I2S module.
sahilmgandhi 18:6a4db94011d3 494 * @return None
sahilmgandhi 18:6a4db94011d3 495 * @details This macro will set MUTE bit of SPI_I2SCTL register to enable I2S TX mute function.
sahilmgandhi 18:6a4db94011d3 496 */
sahilmgandhi 18:6a4db94011d3 497 #define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk )
sahilmgandhi 18:6a4db94011d3 498
sahilmgandhi 18:6a4db94011d3 499 /**
sahilmgandhi 18:6a4db94011d3 500 * @brief Disable TX Mute function.
sahilmgandhi 18:6a4db94011d3 501 * @param[in] i2s The pointer of the specified I2S module.
sahilmgandhi 18:6a4db94011d3 502 * @return None
sahilmgandhi 18:6a4db94011d3 503 * @details This macro will clear MUTE bit of SPI_I2SCTL register to disable I2S TX mute function.
sahilmgandhi 18:6a4db94011d3 504 */
sahilmgandhi 18:6a4db94011d3 505 #define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk )
sahilmgandhi 18:6a4db94011d3 506
sahilmgandhi 18:6a4db94011d3 507 /**
sahilmgandhi 18:6a4db94011d3 508 * @brief Clear TX FIFO.
sahilmgandhi 18:6a4db94011d3 509 * @param[in] i2s The pointer of the specified I2S module.
sahilmgandhi 18:6a4db94011d3 510 * @return None
sahilmgandhi 18:6a4db94011d3 511 * @details This macro will clear TX FIFO. The internal TX FIFO pointer will be reset to FIFO start point.
sahilmgandhi 18:6a4db94011d3 512 */
sahilmgandhi 18:6a4db94011d3 513 #define I2S_CLR_TX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk )
sahilmgandhi 18:6a4db94011d3 514
sahilmgandhi 18:6a4db94011d3 515 /**
sahilmgandhi 18:6a4db94011d3 516 * @brief Clear RX FIFO.
sahilmgandhi 18:6a4db94011d3 517 * @param[in] i2s The pointer of the specified I2S module.
sahilmgandhi 18:6a4db94011d3 518 * @return None
sahilmgandhi 18:6a4db94011d3 519 * @details This macro will clear RX FIFO. The internal RX FIFO pointer will be reset to FIFO start point.
sahilmgandhi 18:6a4db94011d3 520 */
sahilmgandhi 18:6a4db94011d3 521 #define I2S_CLR_RX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk )
sahilmgandhi 18:6a4db94011d3 522
sahilmgandhi 18:6a4db94011d3 523 /**
sahilmgandhi 18:6a4db94011d3 524 * @brief This function sets the recording source channel when mono mode is used.
sahilmgandhi 18:6a4db94011d3 525 * @param[in] i2s The pointer of the specified I2S module.
sahilmgandhi 18:6a4db94011d3 526 * @param[in] u32Ch left or right channel. Valid values are:
sahilmgandhi 18:6a4db94011d3 527 * - \ref I2S_MONO_LEFT
sahilmgandhi 18:6a4db94011d3 528 * - \ref I2S_MONO_RIGHT
sahilmgandhi 18:6a4db94011d3 529 * @return None
sahilmgandhi 18:6a4db94011d3 530 * @details This function selects the recording source channel of monaural mode.
sahilmgandhi 18:6a4db94011d3 531 */
sahilmgandhi 18:6a4db94011d3 532 static __INLINE void I2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch)
sahilmgandhi 18:6a4db94011d3 533 {
sahilmgandhi 18:6a4db94011d3 534 u32Ch == I2S_MONO_LEFT ?
sahilmgandhi 18:6a4db94011d3 535 (i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) :
sahilmgandhi 18:6a4db94011d3 536 (i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk);
sahilmgandhi 18:6a4db94011d3 537 }
sahilmgandhi 18:6a4db94011d3 538
sahilmgandhi 18:6a4db94011d3 539 /**
sahilmgandhi 18:6a4db94011d3 540 * @brief Write data to I2S TX FIFO.
sahilmgandhi 18:6a4db94011d3 541 * @param[in] i2s The pointer of the specified I2S module.
sahilmgandhi 18:6a4db94011d3 542 * @param[in] u32Data The value written to TX FIFO.
sahilmgandhi 18:6a4db94011d3 543 * @return None
sahilmgandhi 18:6a4db94011d3 544 * @details This macro will write a value to TX FIFO.
sahilmgandhi 18:6a4db94011d3 545 */
sahilmgandhi 18:6a4db94011d3 546 #define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TX = (u32Data) )
sahilmgandhi 18:6a4db94011d3 547
sahilmgandhi 18:6a4db94011d3 548 /**
sahilmgandhi 18:6a4db94011d3 549 * @brief Read RX FIFO.
sahilmgandhi 18:6a4db94011d3 550 * @param[in] i2s The pointer of the specified I2S module.
sahilmgandhi 18:6a4db94011d3 551 * @return The value read from RX FIFO.
sahilmgandhi 18:6a4db94011d3 552 * @details This function will return a value read from RX FIFO.
sahilmgandhi 18:6a4db94011d3 553 */
sahilmgandhi 18:6a4db94011d3 554 #define I2S_READ_RX_FIFO(i2s) ( (i2s)->RX )
sahilmgandhi 18:6a4db94011d3 555
sahilmgandhi 18:6a4db94011d3 556 /**
sahilmgandhi 18:6a4db94011d3 557 * @brief Get the interrupt flag.
sahilmgandhi 18:6a4db94011d3 558 * @param[in] i2s The pointer of the specified I2S module.
sahilmgandhi 18:6a4db94011d3 559 * @param[in] u32Mask The mask value for all interrupt flags.
sahilmgandhi 18:6a4db94011d3 560 * @return The interrupt flags specified by the u32mask parameter.
sahilmgandhi 18:6a4db94011d3 561 * @details This macro will return the combination interrupt flags of SPI_I2SSTS register. The flags are specified by the u32mask parameter.
sahilmgandhi 18:6a4db94011d3 562 */
sahilmgandhi 18:6a4db94011d3 563 #define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS & (u32Mask) )
sahilmgandhi 18:6a4db94011d3 564
sahilmgandhi 18:6a4db94011d3 565 /**
sahilmgandhi 18:6a4db94011d3 566 * @brief Clear the interrupt flag.
sahilmgandhi 18:6a4db94011d3 567 * @param[in] i2s The pointer of the specified I2S module.
sahilmgandhi 18:6a4db94011d3 568 * @param[in] u32Mask The mask value for all interrupt flags.
sahilmgandhi 18:6a4db94011d3 569 * @return None
sahilmgandhi 18:6a4db94011d3 570 * @details This macro will clear the interrupt flags specified by the u32mask parameter.
sahilmgandhi 18:6a4db94011d3 571 * @note Except TX and RX FIFO threshold interrupt flags, the other interrupt flags can be cleared by writing 1 to itself.
sahilmgandhi 18:6a4db94011d3 572 */
sahilmgandhi 18:6a4db94011d3 573 #define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS = (u32Mask) )
sahilmgandhi 18:6a4db94011d3 574
sahilmgandhi 18:6a4db94011d3 575 /**
sahilmgandhi 18:6a4db94011d3 576 * @brief Get transmit FIFO level
sahilmgandhi 18:6a4db94011d3 577 * @param[in] i2s The pointer of the specified I2S module.
sahilmgandhi 18:6a4db94011d3 578 * @return TX FIFO level
sahilmgandhi 18:6a4db94011d3 579 * @details This macro will return the number of available words in TX FIFO.
sahilmgandhi 18:6a4db94011d3 580 */
sahilmgandhi 18:6a4db94011d3 581 #define I2S_GET_TX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos )
sahilmgandhi 18:6a4db94011d3 582
sahilmgandhi 18:6a4db94011d3 583 /**
sahilmgandhi 18:6a4db94011d3 584 * @brief Get receive FIFO level
sahilmgandhi 18:6a4db94011d3 585 * @param[in] i2s The pointer of the specified I2S module.
sahilmgandhi 18:6a4db94011d3 586 * @return RX FIFO level
sahilmgandhi 18:6a4db94011d3 587 * @details This macro will return the number of available words in RX FIFO.
sahilmgandhi 18:6a4db94011d3 588 */
sahilmgandhi 18:6a4db94011d3 589 #define I2S_GET_RX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos )
sahilmgandhi 18:6a4db94011d3 590
sahilmgandhi 18:6a4db94011d3 591
sahilmgandhi 18:6a4db94011d3 592
sahilmgandhi 18:6a4db94011d3 593 /* Function prototype declaration */
sahilmgandhi 18:6a4db94011d3 594 uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
sahilmgandhi 18:6a4db94011d3 595 void SPI_Close(SPI_T *spi);
sahilmgandhi 18:6a4db94011d3 596 void SPI_ClearRxFIFO(SPI_T *spi);
sahilmgandhi 18:6a4db94011d3 597 void SPI_ClearTxFIFO(SPI_T *spi);
sahilmgandhi 18:6a4db94011d3 598 void SPI_DisableAutoSS(SPI_T *spi);
sahilmgandhi 18:6a4db94011d3 599 void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
sahilmgandhi 18:6a4db94011d3 600 uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
sahilmgandhi 18:6a4db94011d3 601 void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
sahilmgandhi 18:6a4db94011d3 602 uint32_t SPI_GetBusClock(SPI_T *spi);
sahilmgandhi 18:6a4db94011d3 603 void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
sahilmgandhi 18:6a4db94011d3 604 void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
sahilmgandhi 18:6a4db94011d3 605 uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask);
sahilmgandhi 18:6a4db94011d3 606 void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask);
sahilmgandhi 18:6a4db94011d3 607 uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask);
sahilmgandhi 18:6a4db94011d3 608
sahilmgandhi 18:6a4db94011d3 609 uint32_t I2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat);
sahilmgandhi 18:6a4db94011d3 610 void I2S_Close(SPI_T *i2s);
sahilmgandhi 18:6a4db94011d3 611 void I2S_EnableInt(SPI_T *i2s, uint32_t u32Mask);
sahilmgandhi 18:6a4db94011d3 612 void I2S_DisableInt(SPI_T *i2s, uint32_t u32Mask);
sahilmgandhi 18:6a4db94011d3 613 uint32_t I2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock);
sahilmgandhi 18:6a4db94011d3 614 void I2S_DisableMCLK(SPI_T *i2s);
sahilmgandhi 18:6a4db94011d3 615 void I2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
sahilmgandhi 18:6a4db94011d3 616
sahilmgandhi 18:6a4db94011d3 617
sahilmgandhi 18:6a4db94011d3 618 /*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */
sahilmgandhi 18:6a4db94011d3 619
sahilmgandhi 18:6a4db94011d3 620 /*@}*/ /* end of group SPI_Driver */
sahilmgandhi 18:6a4db94011d3 621
sahilmgandhi 18:6a4db94011d3 622 /*@}*/ /* end of group Standard_Driver */
sahilmgandhi 18:6a4db94011d3 623
sahilmgandhi 18:6a4db94011d3 624 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 625 }
sahilmgandhi 18:6a4db94011d3 626 #endif
sahilmgandhi 18:6a4db94011d3 627
sahilmgandhi 18:6a4db94011d3 628 #endif //__SPI_H__
sahilmgandhi 18:6a4db94011d3 629
sahilmgandhi 18:6a4db94011d3 630 /*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/