MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_pwm.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file pwm.h
sahilmgandhi 18:6a4db94011d3 3 * @version V1.00
sahilmgandhi 18:6a4db94011d3 4 * $Revision: 26 $
sahilmgandhi 18:6a4db94011d3 5 * $Date: 15/08/11 10:26a $
sahilmgandhi 18:6a4db94011d3 6 * @brief M451 series PWM driver header file
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * @note
sahilmgandhi 18:6a4db94011d3 9 * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
sahilmgandhi 18:6a4db94011d3 10 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 11 #ifndef __PWM_H__
sahilmgandhi 18:6a4db94011d3 12 #define __PWM_H__
sahilmgandhi 18:6a4db94011d3 13
sahilmgandhi 18:6a4db94011d3 14 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 15 extern "C"
sahilmgandhi 18:6a4db94011d3 16 {
sahilmgandhi 18:6a4db94011d3 17 #endif
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19
sahilmgandhi 18:6a4db94011d3 20 /** @addtogroup Standard_Driver Standard Driver
sahilmgandhi 18:6a4db94011d3 21 @{
sahilmgandhi 18:6a4db94011d3 22 */
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24 /** @addtogroup PWM_Driver PWM Driver
sahilmgandhi 18:6a4db94011d3 25 @{
sahilmgandhi 18:6a4db94011d3 26 */
sahilmgandhi 18:6a4db94011d3 27
sahilmgandhi 18:6a4db94011d3 28 /** @addtogroup PWM_EXPORTED_CONSTANTS PWM Exported Constants
sahilmgandhi 18:6a4db94011d3 29 @{
sahilmgandhi 18:6a4db94011d3 30 */
sahilmgandhi 18:6a4db94011d3 31 #define PWM_CHANNEL_NUM (6) /*!< PWM channel number */
sahilmgandhi 18:6a4db94011d3 32 #define PWM_CH_0_MASK (0x1UL) /*!< PWM channel 0 mask \hideinitializer */
sahilmgandhi 18:6a4db94011d3 33 #define PWM_CH_1_MASK (0x2UL) /*!< PWM channel 1 mask \hideinitializer */
sahilmgandhi 18:6a4db94011d3 34 #define PWM_CH_2_MASK (0x4UL) /*!< PWM channel 2 mask \hideinitializer */
sahilmgandhi 18:6a4db94011d3 35 #define PWM_CH_3_MASK (0x8UL) /*!< PWM channel 3 mask \hideinitializer */
sahilmgandhi 18:6a4db94011d3 36 #define PWM_CH_4_MASK (0x10UL) /*!< PWM channel 4 mask \hideinitializer */
sahilmgandhi 18:6a4db94011d3 37 #define PWM_CH_5_MASK (0x20UL) /*!< PWM channel 5 mask \hideinitializer */
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 40 /* Counter Type Constant Definitions */
sahilmgandhi 18:6a4db94011d3 41 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 42 #define PWM_UP_COUNTER (0UL) /*!< Up counter type */
sahilmgandhi 18:6a4db94011d3 43 #define PWM_DOWN_COUNTER (1UL) /*!< Down counter type */
sahilmgandhi 18:6a4db94011d3 44 #define PWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type */
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 47 /* Aligned Type Constant Definitions */
sahilmgandhi 18:6a4db94011d3 48 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 49 #define PWM_EDGE_ALIGNED (1UL) /*!< PWM working in edge aligned type(down count) */
sahilmgandhi 18:6a4db94011d3 50 #define PWM_CENTER_ALIGNED (2UL) /*!< PWM working in center aligned type */
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 53 /* Output Level Constant Definitions */
sahilmgandhi 18:6a4db94011d3 54 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 55 #define PWM_OUTPUT_NOTHING (0UL) /*!< PWM output nothing */
sahilmgandhi 18:6a4db94011d3 56 #define PWM_OUTPUT_LOW (1UL) /*!< PWM output low */
sahilmgandhi 18:6a4db94011d3 57 #define PWM_OUTPUT_HIGH (2UL) /*!< PWM output high */
sahilmgandhi 18:6a4db94011d3 58 #define PWM_OUTPUT_TOGGLE (3UL) /*!< PWM output toggle */
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 61 /* Trigger Source Select Constant Definitions */
sahilmgandhi 18:6a4db94011d3 62 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 63 #define PWM_TRIGGER_ADC_EVEN_ZERO_POINT (0UL) /*!< PWM trigger ADC while counter of even channel matches zero point */
sahilmgandhi 18:6a4db94011d3 64 #define PWM_TRIGGER_ADC_EVEN_PERIOD_POINT (1UL) /*!< PWM trigger ADC while counter of even channel matches period point */
sahilmgandhi 18:6a4db94011d3 65 #define PWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT (2UL) /*!< PWM trigger ADC while counter of even channel matches zero or period point */
sahilmgandhi 18:6a4db94011d3 66 #define PWM_TRIGGER_ADC_EVEN_COMPARE_UP_COUNT_POINT (3UL) /*!< PWM trigger ADC while counter of even channel matches up count to comparator point */
sahilmgandhi 18:6a4db94011d3 67 #define PWM_TRIGGER_ADC_EVEN_COMPARE_DOWN_COUNT_POINT (4UL) /*!< PWM trigger ADC while counter of even channel matches down count to comparator point */
sahilmgandhi 18:6a4db94011d3 68 #define PWM_TRIGGER_ADC_ODD_ZERO_POINT (5UL) /*!< PWM trigger ADC while counter of odd channel matches zero point */
sahilmgandhi 18:6a4db94011d3 69 #define PWM_TRIGGER_ADC_ODD_PERIOD_POINT (6UL) /*!< PWM trigger ADC while counter of odd channel matches period point */
sahilmgandhi 18:6a4db94011d3 70 #define PWM_TRIGGER_ADC_ODD_ZERO_OR_PERIOD_POINT (7UL) /*!< PWM trigger ADC while counter of odd channel matches zero or period point */
sahilmgandhi 18:6a4db94011d3 71 #define PWM_TRIGGER_ADC_ODD_COMPARE_UP_COUNT_POINT (8UL) /*!< PWM trigger ADC while counter of odd channel matches up count to comparator point */
sahilmgandhi 18:6a4db94011d3 72 #define PWM_TRIGGER_ADC_ODD_COMPARE_DOWN_COUNT_POINT (9UL) /*!< PWM trigger ADC while counter of odd channel matches down count to comparator point */
sahilmgandhi 18:6a4db94011d3 73 #define PWM_TRIGGER_ADC_CH_0_FREE_COMPARE_UP_COUNT_POINT (10UL) /*!< PWM trigger ADC while counter of channel 0 matches up count to free comparator point */
sahilmgandhi 18:6a4db94011d3 74 #define PWM_TRIGGER_ADC_CH_0_FREE_COMPARE_DOWN_COUNT_POINT (11UL) /*!< PWM trigger ADC while counter of channel 0 matches down count to free comparator point */
sahilmgandhi 18:6a4db94011d3 75 #define PWM_TRIGGER_ADC_CH_2_FREE_COMPARE_UP_COUNT_POINT (12UL) /*!< PWM trigger ADC while counter of channel 2 matches up count to free comparator point */
sahilmgandhi 18:6a4db94011d3 76 #define PWM_TRIGGER_ADC_CH_2_FREE_COMPARE_DOWN_COUNT_POINT (13UL) /*!< PWM trigger ADC while counter of channel 2 matches down count to free comparator point */
sahilmgandhi 18:6a4db94011d3 77 #define PWM_TRIGGER_ADC_CH_4_FREE_COMPARE_UP_COUNT_POINT (14UL) /*!< PWM trigger ADC while counter of channel 4 matches up count to free comparator point */
sahilmgandhi 18:6a4db94011d3 78 #define PWM_TRIGGER_ADC_CH_4_FREE_COMPARE_DOWN_COUNT_POINT (15UL) /*!< PWM trigger ADC while counter of channel 4 matches down count to free comparator point */
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 #define PWM_TRIGGER_DAC_ZERO_POINT (0x1UL) /*!< PWM trigger ADC while counter down count to 0 \hideinitializer */
sahilmgandhi 18:6a4db94011d3 81 #define PWM_TRIGGER_DAC_PERIOD_POINT (0x100UL) /*!< PWM trigger ADC while counter matches (PERIOD + 1) \hideinitializer */
sahilmgandhi 18:6a4db94011d3 82 #define PWM_TRIGGER_DAC_COMPARE_UP_COUNT_POINT (0x10000UL) /*!< PWM trigger ADC while counter up count to CMPDAT \hideinitializer */
sahilmgandhi 18:6a4db94011d3 83 #define PWM_TRIGGER_DAC_COMPARE_DOWN_COUNT_POINT (0x1000000UL) /*!< PWM trigger ADC while counter down count to CMPDAT \hideinitializer */
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 86 /* Fail brake Control Constant Definitions */
sahilmgandhi 18:6a4db94011d3 87 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 88 #define PWM_FB_EDGE_ACMP0 (PWM_BRKCTL0_1_CPO0EBEN_Msk) /*!< Comparator 0 as edge-detect fault brake source */
sahilmgandhi 18:6a4db94011d3 89 #define PWM_FB_EDGE_ACMP1 (PWM_BRKCTL0_1_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source */
sahilmgandhi 18:6a4db94011d3 90 #define PWM_FB_EDGE_BKP0 (PWM_BRKCTL0_1_BRKP0EEN_Msk) /*!< BKP0 pin as edge-detect fault brake source */
sahilmgandhi 18:6a4db94011d3 91 #define PWM_FB_EDGE_BKP1 (PWM_BRKCTL0_1_BRKP1EEN_Msk) /*!< BKP1 pin as edge-detect fault brake source */
sahilmgandhi 18:6a4db94011d3 92 #define PWM_FB_EDGE_SYS_CSS (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as edge-detect fault brake source */
sahilmgandhi 18:6a4db94011d3 93 #define PWM_FB_EDGE_SYS_BOD (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as edge-detect fault brake source */
sahilmgandhi 18:6a4db94011d3 94 #define PWM_FB_EDGE_SYS_RAM (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_RAMBRKEN_Msk) /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source */
sahilmgandhi 18:6a4db94011d3 95 #define PWM_FB_EDGE_SYS_COR (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as edge-detect fault brake source */
sahilmgandhi 18:6a4db94011d3 96
sahilmgandhi 18:6a4db94011d3 97 #define PWM_FB_LEVEL_ACMP0 (PWM_BRKCTL0_1_CPO0LBEN_Msk) /*!< Comparator 0 as level-detect fault brake source */
sahilmgandhi 18:6a4db94011d3 98 #define PWM_FB_LEVEL_ACMP1 (PWM_BRKCTL0_1_CPO1LBEN_Msk) /*!< Comparator 1 as level-detect fault brake source */
sahilmgandhi 18:6a4db94011d3 99 #define PWM_FB_LEVEL_BKP0 (PWM_BRKCTL0_1_BRKP0LEN_Msk) /*!< BKP0 pin as level-detect fault brake source */
sahilmgandhi 18:6a4db94011d3 100 #define PWM_FB_LEVEL_BKP1 (PWM_BRKCTL0_1_BRKP1LEN_Msk) /*!< BKP1 pin as level-detect fault brake source */
sahilmgandhi 18:6a4db94011d3 101 #define PWM_FB_LEVEL_SYS_CSS (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as level-detect fault brake source */
sahilmgandhi 18:6a4db94011d3 102 #define PWM_FB_LEVEL_SYS_BOD (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as level-detect fault brake source */
sahilmgandhi 18:6a4db94011d3 103 #define PWM_FB_LEVEL_SYS_RAM (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_RAMBRKEN_Msk) /*!< System fail condition: SRAM parity error detection as level-detect fault brake source */
sahilmgandhi 18:6a4db94011d3 104 #define PWM_FB_LEVEL_SYS_COR (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as level-detect fault brake source */
sahilmgandhi 18:6a4db94011d3 105
sahilmgandhi 18:6a4db94011d3 106 #define PWM_FB_EDGE (0UL) /*!< edge-detect fault brake */
sahilmgandhi 18:6a4db94011d3 107 #define PWM_FB_LEVEL (8UL) /*!< level-detect fault brake */
sahilmgandhi 18:6a4db94011d3 108
sahilmgandhi 18:6a4db94011d3 109 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 110 /* Capture Control Constant Definitions */
sahilmgandhi 18:6a4db94011d3 111 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 112 #define PWM_CAPTURE_INT_RISING_LATCH (1UL) /*!< PWM capture interrupt if channel has rising transition */
sahilmgandhi 18:6a4db94011d3 113 #define PWM_CAPTURE_INT_FALLING_LATCH (0x100UL) /*!< PWM capture interrupt if channel has falling transition */
sahilmgandhi 18:6a4db94011d3 114
sahilmgandhi 18:6a4db94011d3 115 #define PWM_CAPTURE_PDMA_RISING_LATCH (0x2UL) /*!< PWM capture rising latched data transfer by PDMA */
sahilmgandhi 18:6a4db94011d3 116 #define PWM_CAPTURE_PDMA_FALLING_LATCH (0x4UL) /*!< PWM capture falling latched data transfer by PDMA */
sahilmgandhi 18:6a4db94011d3 117 #define PWM_CAPTURE_PDMA_RISING_FALLING_LATCH (0x6UL) /*!< PWM capture rising and falling latched data transfer by PDMA */
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 120 /* Duty Interrupt Type Constant Definitions */
sahilmgandhi 18:6a4db94011d3 121 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 122 #define PWM_DUTY_INT_DOWN_COUNT_MATCH_CMP (PWM_INTEN0_CMPDIEN0_Msk) /*!< PWM duty interrupt triggered if down count match comparator */
sahilmgandhi 18:6a4db94011d3 123 #define PWM_DUTY_INT_UP_COUNT_MATCH_CMP (PWM_INTEN0_CMPUIEN0_Msk) /*!< PWM duty interrupt triggered if up down match comparator */
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 126 /* Interrupt Flag Accumulator Constant Definitions */
sahilmgandhi 18:6a4db94011d3 127 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 128 #define PWM_IFA_EVEN_ZERO_POINT (0UL) /*!< PWM counter equal to zero in even channel \hideinitializer */
sahilmgandhi 18:6a4db94011d3 129 #define PWM_IFA_EVEN_PERIOD_POINT (1UL) /*!< PWM counter equal to period in even channel \hideinitializer */
sahilmgandhi 18:6a4db94011d3 130 #define PWM_IFA_EVEN_COMPARE_UP_COUNT_POINT (2UL) /*!< PWM counter up count to comparator value in even channel \hideinitializer */
sahilmgandhi 18:6a4db94011d3 131 #define PWM_IFA_EVEN_COMPARE_DOWN_COUNT_POINT (3UL) /*!< PWM counter down count to comparator value in even channel \hideinitializer */
sahilmgandhi 18:6a4db94011d3 132 #define PWM_IFA_ODD_ZERO_POINT (4UL) /*!< PWM counter equal to zero in odd channel \hideinitializer */
sahilmgandhi 18:6a4db94011d3 133 #define PWM_IFA_ODD_PERIOD_POINT (5UL) /*!< PWM counter equal to period in odd channel \hideinitializer */
sahilmgandhi 18:6a4db94011d3 134 #define PWM_IFA_ODD_COMPARE_UP_COUNT_POINT (6UL) /*!< PWM counter up count to comparator value in odd channel \hideinitializer */
sahilmgandhi 18:6a4db94011d3 135 #define PWM_IFA_ODD_COMPARE_DOWN_COUNT_POINT (7UL) /*!< PWM counter down count to comparator value in odd channel \hideinitializer */
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 138 /* Load Mode Constant Definitions */
sahilmgandhi 18:6a4db94011d3 139 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 140 #define PWM_LOAD_MODE_IMMEDIATE (PWM_CTL0_IMMLDEN0_Msk) /*!< PWM immediately load mode \hideinitializer */
sahilmgandhi 18:6a4db94011d3 141 #define PWM_LOAD_MODE_WINDOW (PWM_CTL0_WINLDEN0_Msk) /*!< PWM window load mode \hideinitializer */
sahilmgandhi 18:6a4db94011d3 142 #define PWM_LOAD_MODE_CENTER (PWM_CTL0_CTRLD0_Msk) /*!< PWM center load mode \hideinitializer */
sahilmgandhi 18:6a4db94011d3 143
sahilmgandhi 18:6a4db94011d3 144 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 145 /* Synchronize Control Constant Definitions */
sahilmgandhi 18:6a4db94011d3 146 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 147 #define PWM_SYNC_OUT_FROM_SYNCIN_SWSYNC (0UL) /*!< Synchronize source from SYNC_IN or SWSYNC \hideinitializer */
sahilmgandhi 18:6a4db94011d3 148 #define PWM_SYNC_OUT_FROM_COUNT_TO_ZERO (1UL) /*!< Synchronize source from counter equal to 0 \hideinitializer */
sahilmgandhi 18:6a4db94011d3 149 #define PWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR (2UL) /*!< Synchronize source from counter equal to CMPDAT1, CMPDAT3, CMPDAT5 \hideinitializer */
sahilmgandhi 18:6a4db94011d3 150 #define PWM_SYNC_OUT_DISABLE (3UL) /*!< SYNC_OUT will not be generated \hideinitializer */
sahilmgandhi 18:6a4db94011d3 151 #define PWM_PHS_DIR_DECREMENT (0UL) /*!< PWM counter count decrement \hideinitializer */
sahilmgandhi 18:6a4db94011d3 152 #define PWM_PHS_DIR_INCREMENT (1UL) /*!< PWM counter count increment \hideinitializer */
sahilmgandhi 18:6a4db94011d3 153
sahilmgandhi 18:6a4db94011d3 154 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 155 /* Noise Filter Clock Divide Select Constant Definitions */
sahilmgandhi 18:6a4db94011d3 156 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 157 #define PWM_NF_CLK_DIV_1 (0UL) /*!< Noise filter clock is HCLK divide by 1 \hideinitializer */
sahilmgandhi 18:6a4db94011d3 158 #define PWM_NF_CLK_DIV_2 (1UL) /*!< Noise filter clock is HCLK divide by 2 \hideinitializer */
sahilmgandhi 18:6a4db94011d3 159 #define PWM_NF_CLK_DIV_4 (2UL) /*!< Noise filter clock is HCLK divide by 4 \hideinitializer */
sahilmgandhi 18:6a4db94011d3 160 #define PWM_NF_CLK_DIV_8 (3UL) /*!< Noise filter clock is HCLK divide by 8 \hideinitializer */
sahilmgandhi 18:6a4db94011d3 161 #define PWM_NF_CLK_DIV_16 (4UL) /*!< Noise filter clock is HCLK divide by 16 \hideinitializer */
sahilmgandhi 18:6a4db94011d3 162 #define PWM_NF_CLK_DIV_32 (5UL) /*!< Noise filter clock is HCLK divide by 32 \hideinitializer */
sahilmgandhi 18:6a4db94011d3 163 #define PWM_NF_CLK_DIV_64 (6UL) /*!< Noise filter clock is HCLK divide by 64 \hideinitializer */
sahilmgandhi 18:6a4db94011d3 164 #define PWM_NF_CLK_DIV_128 (7UL) /*!< Noise filter clock is HCLK divide by 128 \hideinitializer */
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 167 /* Clock Source Select Constant Definitions */
sahilmgandhi 18:6a4db94011d3 168 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 169 #define PWM_CLKSRC_PWM_CLK (0UL) /*!< PWM Clock source selects to PWM0_CLK or PWM1_CLK \hideinitializer */
sahilmgandhi 18:6a4db94011d3 170 #define PWM_CLKSRC_TIMER0 (1UL) /*!< PWM Clock source selects to TIMER0 overflow \hideinitializer */
sahilmgandhi 18:6a4db94011d3 171 #define PWM_CLKSRC_TIMER1 (2UL) /*!< PWM Clock source selects to TIMER1 overflow \hideinitializer */
sahilmgandhi 18:6a4db94011d3 172 #define PWM_CLKSRC_TIMER2 (3UL) /*!< PWM Clock source selects to TIMER2 overflow \hideinitializer */
sahilmgandhi 18:6a4db94011d3 173 #define PWM_CLKSRC_TIMER3 (4UL) /*!< PWM Clock source selects to TIMER3 overflow \hideinitializer */
sahilmgandhi 18:6a4db94011d3 174
sahilmgandhi 18:6a4db94011d3 175
sahilmgandhi 18:6a4db94011d3 176 /*@}*/ /* end of group PWM_EXPORTED_CONSTANTS */
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178
sahilmgandhi 18:6a4db94011d3 179 /** @addtogroup PWM_EXPORTED_FUNCTIONS PWM Exported Functions
sahilmgandhi 18:6a4db94011d3 180 @{
sahilmgandhi 18:6a4db94011d3 181 */
sahilmgandhi 18:6a4db94011d3 182
sahilmgandhi 18:6a4db94011d3 183 /**
sahilmgandhi 18:6a4db94011d3 184 * @brief This macro enable complementary mode
sahilmgandhi 18:6a4db94011d3 185 * @param[in] pwm The pointer of the specified PWM module
sahilmgandhi 18:6a4db94011d3 186 * @return None
sahilmgandhi 18:6a4db94011d3 187 * @details This macro is used to enable complementary mode of PWM module.
sahilmgandhi 18:6a4db94011d3 188 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 189 */
sahilmgandhi 18:6a4db94011d3 190 #define PWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL1 = (pwm)->CTL1 | PWM_CTL1_OUTMODEn_Msk)
sahilmgandhi 18:6a4db94011d3 191
sahilmgandhi 18:6a4db94011d3 192 /**
sahilmgandhi 18:6a4db94011d3 193 * @brief This macro disable complementary mode, and enable independent mode.
sahilmgandhi 18:6a4db94011d3 194 * @param[in] pwm The pointer of the specified PWM module
sahilmgandhi 18:6a4db94011d3 195 * @return None
sahilmgandhi 18:6a4db94011d3 196 * @details This macro is used to disable complementary mode of PWM module.
sahilmgandhi 18:6a4db94011d3 197 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 198 */
sahilmgandhi 18:6a4db94011d3 199 #define PWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL1 = (pwm)->CTL1 & ~PWM_CTL1_OUTMODEn_Msk)
sahilmgandhi 18:6a4db94011d3 200
sahilmgandhi 18:6a4db94011d3 201 /**
sahilmgandhi 18:6a4db94011d3 202 * @brief This macro enable group mode
sahilmgandhi 18:6a4db94011d3 203 * @param[in] pwm The pointer of the specified PWM module
sahilmgandhi 18:6a4db94011d3 204 * @return None
sahilmgandhi 18:6a4db94011d3 205 * @details This macro is used to enable group mode of PWM module.
sahilmgandhi 18:6a4db94011d3 206 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 207 */
sahilmgandhi 18:6a4db94011d3 208 #define PWM_ENABLE_GROUP_MODE(pwm) ((pwm)->CTL0 = (pwm)->CTL0 | PWM_CTL0_GROUPEN_Msk)
sahilmgandhi 18:6a4db94011d3 209
sahilmgandhi 18:6a4db94011d3 210 /**
sahilmgandhi 18:6a4db94011d3 211 * @brief This macro disable group mode
sahilmgandhi 18:6a4db94011d3 212 * @param[in] pwm The pointer of the specified PWM module
sahilmgandhi 18:6a4db94011d3 213 * @return None
sahilmgandhi 18:6a4db94011d3 214 * @details This macro is used to disable group mode of PWM module.
sahilmgandhi 18:6a4db94011d3 215 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 216 */
sahilmgandhi 18:6a4db94011d3 217 #define PWM_DISABLE_GROUP_MODE(pwm) ((pwm)->CTL0 = (pwm)->CTL0 & ~PWM_CTL0_GROUPEN_Msk)
sahilmgandhi 18:6a4db94011d3 218
sahilmgandhi 18:6a4db94011d3 219 /**
sahilmgandhi 18:6a4db94011d3 220 * @brief Enable timer synchronous mode of specified channel(s)
sahilmgandhi 18:6a4db94011d3 221 * @param[in] pwm The pointer of the specified PWM module
sahilmgandhi 18:6a4db94011d3 222 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
sahilmgandhi 18:6a4db94011d3 223 * Bit 0 represents channel 0, bit 1 represents channel 1...
sahilmgandhi 18:6a4db94011d3 224 * @return None
sahilmgandhi 18:6a4db94011d3 225 * @details This macro is used to enable timer synchronous mode of specified channel(s).
sahilmgandhi 18:6a4db94011d3 226 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 227 */
sahilmgandhi 18:6a4db94011d3 228 #define PWM_ENABLE_TIMER_SYNC(pwm, u32ChannelMask) ((pwm)->SSCTL |= (u32ChannelMask))
sahilmgandhi 18:6a4db94011d3 229
sahilmgandhi 18:6a4db94011d3 230 /**
sahilmgandhi 18:6a4db94011d3 231 * @brief Disable timer synchronous mode of specified channel(s)
sahilmgandhi 18:6a4db94011d3 232 * @param[in] pwm The pointer of the specified PWM module
sahilmgandhi 18:6a4db94011d3 233 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
sahilmgandhi 18:6a4db94011d3 234 * Bit 0 represents channel 0, bit 1 represents channel 1...
sahilmgandhi 18:6a4db94011d3 235 * @return None
sahilmgandhi 18:6a4db94011d3 236 * @details This macro is used to disable timer synchronous mode of specified channel(s).
sahilmgandhi 18:6a4db94011d3 237 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 238 */
sahilmgandhi 18:6a4db94011d3 239 #define PWM_DISABLE_TIMER_SYNC(pwm, u32ChannelMask) \
sahilmgandhi 18:6a4db94011d3 240 do{ \
sahilmgandhi 18:6a4db94011d3 241 int i;\
sahilmgandhi 18:6a4db94011d3 242 for(i = 0; i < 6; i++) { \
sahilmgandhi 18:6a4db94011d3 243 if((u32ChannelMask) & (1 << i)) \
sahilmgandhi 18:6a4db94011d3 244 (pwm)->SSCTL &= ~(1UL << i); \
sahilmgandhi 18:6a4db94011d3 245 } \
sahilmgandhi 18:6a4db94011d3 246 }while(0)
sahilmgandhi 18:6a4db94011d3 247
sahilmgandhi 18:6a4db94011d3 248 /**
sahilmgandhi 18:6a4db94011d3 249 * @brief This macro enable output inverter of specified channel(s)
sahilmgandhi 18:6a4db94011d3 250 * @param[in] pwm The pointer of the specified PWM module
sahilmgandhi 18:6a4db94011d3 251 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
sahilmgandhi 18:6a4db94011d3 252 * Bit 0 represents channel 0, bit 1 represents channel 1...
sahilmgandhi 18:6a4db94011d3 253 * @return None
sahilmgandhi 18:6a4db94011d3 254 * @details This macro is used to enable output inverter of specified channel(s).
sahilmgandhi 18:6a4db94011d3 255 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 256 */
sahilmgandhi 18:6a4db94011d3 257 #define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) ((pwm)->POLCTL = (u32ChannelMask))
sahilmgandhi 18:6a4db94011d3 258
sahilmgandhi 18:6a4db94011d3 259 /**
sahilmgandhi 18:6a4db94011d3 260 * @brief This macro get captured rising data
sahilmgandhi 18:6a4db94011d3 261 * @param[in] pwm The pointer of the specified PWM module
sahilmgandhi 18:6a4db94011d3 262 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 263 * @return None
sahilmgandhi 18:6a4db94011d3 264 * @details This macro is used to get captured rising data of specified channel.
sahilmgandhi 18:6a4db94011d3 265 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 266 */
sahilmgandhi 18:6a4db94011d3 267 #define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&((pwm)->RCAPDAT0) + 2 * (u32ChannelNum)))
sahilmgandhi 18:6a4db94011d3 268
sahilmgandhi 18:6a4db94011d3 269 /**
sahilmgandhi 18:6a4db94011d3 270 * @brief This macro get captured falling data
sahilmgandhi 18:6a4db94011d3 271 * @param[in] pwm The pointer of the specified PWM module
sahilmgandhi 18:6a4db94011d3 272 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 273 * @return None
sahilmgandhi 18:6a4db94011d3 274 * @details This macro is used to get captured falling data of specified channel.
sahilmgandhi 18:6a4db94011d3 275 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 276 */
sahilmgandhi 18:6a4db94011d3 277 #define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&((pwm)->FCAPDAT0) + 2 * (u32ChannelNum)))
sahilmgandhi 18:6a4db94011d3 278
sahilmgandhi 18:6a4db94011d3 279 /**
sahilmgandhi 18:6a4db94011d3 280 * @brief This macro mask output logic to high or low
sahilmgandhi 18:6a4db94011d3 281 * @param[in] pwm The pointer of the specified PWM module
sahilmgandhi 18:6a4db94011d3 282 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
sahilmgandhi 18:6a4db94011d3 283 * Bit 0 represents channel 0, bit 1 represents channel 1...
sahilmgandhi 18:6a4db94011d3 284 * @param[in] u32LevelMask Output logic to high or low
sahilmgandhi 18:6a4db94011d3 285 * @return None
sahilmgandhi 18:6a4db94011d3 286 * @details This macro is used to mask output logic to high or low of specified channel(s).
sahilmgandhi 18:6a4db94011d3 287 * @note If u32ChannelMask parameter is 0, then mask function will be disabled.
sahilmgandhi 18:6a4db94011d3 288 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 289 */
sahilmgandhi 18:6a4db94011d3 290 #define PWM_MASK_OUTPUT(pwm, u32ChannelMask, u32LevelMask) \
sahilmgandhi 18:6a4db94011d3 291 { \
sahilmgandhi 18:6a4db94011d3 292 (pwm)->MSKEN = (u32ChannelMask); \
sahilmgandhi 18:6a4db94011d3 293 (pwm)->MSK = (u32LevelMask); \
sahilmgandhi 18:6a4db94011d3 294 }
sahilmgandhi 18:6a4db94011d3 295
sahilmgandhi 18:6a4db94011d3 296 /**
sahilmgandhi 18:6a4db94011d3 297 * @brief This macro set the prescaler of the selected channel
sahilmgandhi 18:6a4db94011d3 298 * @param[in] pwm The pointer of the specified PWM module
sahilmgandhi 18:6a4db94011d3 299 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 300 * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFFF
sahilmgandhi 18:6a4db94011d3 301 * @return None
sahilmgandhi 18:6a4db94011d3 302 * @details This macro is used to set the prescaler of specified channel.
sahilmgandhi 18:6a4db94011d3 303 * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed,
sahilmgandhi 18:6a4db94011d3 304 * channel 1 will also be affected.
sahilmgandhi 18:6a4db94011d3 305 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 306 */
sahilmgandhi 18:6a4db94011d3 307 #define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) (*(__IO uint32_t *) (&((pwm)->CLKPSC0_1) + ((u32ChannelNum) >> 1)) = (u32Prescaler))
sahilmgandhi 18:6a4db94011d3 308
sahilmgandhi 18:6a4db94011d3 309 /**
sahilmgandhi 18:6a4db94011d3 310 * @brief This macro set the comparator of the selected channel
sahilmgandhi 18:6a4db94011d3 311 * @param[in] pwm The pointer of the specified PWM module
sahilmgandhi 18:6a4db94011d3 312 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 313 * @param[in] u32CMR Comparator of specified channel. Valid values are between 0~0xFFFF
sahilmgandhi 18:6a4db94011d3 314 * @return None
sahilmgandhi 18:6a4db94011d3 315 * @details This macro is used to set the comparator of specified channel.
sahilmgandhi 18:6a4db94011d3 316 * @note This new setting will take effect on next PWM period.
sahilmgandhi 18:6a4db94011d3 317 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 318 */
sahilmgandhi 18:6a4db94011d3 319 #define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) ((pwm)->CMPDAT[(u32ChannelNum)]= (u32CMR))
sahilmgandhi 18:6a4db94011d3 320
sahilmgandhi 18:6a4db94011d3 321 /**
sahilmgandhi 18:6a4db94011d3 322 * @brief This macro set the free trigger comparator of the selected channel
sahilmgandhi 18:6a4db94011d3 323 * @param[in] pwm The pointer of the specified PWM module
sahilmgandhi 18:6a4db94011d3 324 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 325 * @param[in] u32FTCMR Free trigger comparator of specified channel. Valid values are between 0~0xFFFF
sahilmgandhi 18:6a4db94011d3 326 * @return None
sahilmgandhi 18:6a4db94011d3 327 * @details This macro is used to set the free trigger comparator of specified channel.
sahilmgandhi 18:6a4db94011d3 328 * @note This new setting will take effect on next PWM period.
sahilmgandhi 18:6a4db94011d3 329 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 330 */
sahilmgandhi 18:6a4db94011d3 331 #define PWM_SET_FTCMR(pwm, u32ChannelNum, u32FTCMR) (*(__IO uint32_t *) (&((pwm)->FTCMPDAT0_1) + ((u32ChannelNum) >> 1)) = (u32FTCMR))
sahilmgandhi 18:6a4db94011d3 332
sahilmgandhi 18:6a4db94011d3 333 /**
sahilmgandhi 18:6a4db94011d3 334 * @brief This macro set the period of the selected channel
sahilmgandhi 18:6a4db94011d3 335 * @param[in] pwm The pointer of the specified PWM module
sahilmgandhi 18:6a4db94011d3 336 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 337 * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
sahilmgandhi 18:6a4db94011d3 338 * @return None
sahilmgandhi 18:6a4db94011d3 339 * @details This macro is used to set the period of specified channel.
sahilmgandhi 18:6a4db94011d3 340 * @note This new setting will take effect on next PWM period.
sahilmgandhi 18:6a4db94011d3 341 * @note PWM counter will stop if period length set to 0.
sahilmgandhi 18:6a4db94011d3 342 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 343 */
sahilmgandhi 18:6a4db94011d3 344 #define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) ((pwm)->PERIOD[(u32ChannelNum)] = (u32CNR))
sahilmgandhi 18:6a4db94011d3 345
sahilmgandhi 18:6a4db94011d3 346 /**
sahilmgandhi 18:6a4db94011d3 347 * @brief This macro set the PWM aligned type
sahilmgandhi 18:6a4db94011d3 348 * @param[in] pwm The pointer of the specified PWM module
sahilmgandhi 18:6a4db94011d3 349 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
sahilmgandhi 18:6a4db94011d3 350 * Bit 0 represents channel 0, bit 1 represents channel 1...
sahilmgandhi 18:6a4db94011d3 351 * @param[in] u32AlignedType PWM aligned type, valid values are:
sahilmgandhi 18:6a4db94011d3 352 * - \ref PWM_EDGE_ALIGNED
sahilmgandhi 18:6a4db94011d3 353 * - \ref PWM_CENTER_ALIGNED
sahilmgandhi 18:6a4db94011d3 354 * @return None
sahilmgandhi 18:6a4db94011d3 355 * @details This macro is used to set the PWM aligned type of specified channel(s).
sahilmgandhi 18:6a4db94011d3 356 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 357 */
sahilmgandhi 18:6a4db94011d3 358 #define PWM_SET_ALIGNED_TYPE(pwm, u32ChannelMask, u32AlignedType) \
sahilmgandhi 18:6a4db94011d3 359 do{ \
sahilmgandhi 18:6a4db94011d3 360 int i; \
sahilmgandhi 18:6a4db94011d3 361 for(i = 0; i < 6; i++) { \
sahilmgandhi 18:6a4db94011d3 362 if((u32ChannelMask) & (1 << i)) \
sahilmgandhi 18:6a4db94011d3 363 (pwm)->CTL1 = (((pwm)->CTL1 & ~(3UL << (2 * i))) | ((u32AlignedType) << ( 2 * i))); \
sahilmgandhi 18:6a4db94011d3 364 } \
sahilmgandhi 18:6a4db94011d3 365 }while(0)
sahilmgandhi 18:6a4db94011d3 366
sahilmgandhi 18:6a4db94011d3 367 /**
sahilmgandhi 18:6a4db94011d3 368 * @brief Set load window of window loading mode for specified channel(s)
sahilmgandhi 18:6a4db94011d3 369 * @param[in] pwm The pointer of the specified PWM module
sahilmgandhi 18:6a4db94011d3 370 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
sahilmgandhi 18:6a4db94011d3 371 * Bit 0 represents channel 0, bit 1 represents channel 1...
sahilmgandhi 18:6a4db94011d3 372 * @return None
sahilmgandhi 18:6a4db94011d3 373 * @details This macro is used to set load window of window loading mode for specified channel(s).
sahilmgandhi 18:6a4db94011d3 374 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 375 */
sahilmgandhi 18:6a4db94011d3 376 #define PWM_SET_LOAD_WINDOW(pwm, u32ChannelMask) ((pwm)->LOAD |= (u32ChannelMask))
sahilmgandhi 18:6a4db94011d3 377
sahilmgandhi 18:6a4db94011d3 378 /**
sahilmgandhi 18:6a4db94011d3 379 * @brief Trigger synchronous event from specified channel(s)
sahilmgandhi 18:6a4db94011d3 380 * @param[in] pwm The pointer of the specified PWM module
sahilmgandhi 18:6a4db94011d3 381 * @param[in] u32ChannelNum PWM channel number. Valid values are 0, 2, 4
sahilmgandhi 18:6a4db94011d3 382 * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4
sahilmgandhi 18:6a4db94011d3 383 * @return None
sahilmgandhi 18:6a4db94011d3 384 * @details This macro is used to trigger synchronous event from specified channel(s).
sahilmgandhi 18:6a4db94011d3 385 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 386 */
sahilmgandhi 18:6a4db94011d3 387 #define PWM_TRIGGER_SYNC(pwm, u32ChannelNum) ((pwm)->SWSYNC |= (1 << ((u32ChannelNum) >> 1)))
sahilmgandhi 18:6a4db94011d3 388
sahilmgandhi 18:6a4db94011d3 389 /**
sahilmgandhi 18:6a4db94011d3 390 * @brief Clear counter of specified channel(s)
sahilmgandhi 18:6a4db94011d3 391 * @param[in] pwm The pointer of the specified PWM module
sahilmgandhi 18:6a4db94011d3 392 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
sahilmgandhi 18:6a4db94011d3 393 * Bit 0 represents channel 0, bit 1 represents channel 1...
sahilmgandhi 18:6a4db94011d3 394 * @return None
sahilmgandhi 18:6a4db94011d3 395 * @details This macro is used to clear counter of specified channel(s).
sahilmgandhi 18:6a4db94011d3 396 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 397 */
sahilmgandhi 18:6a4db94011d3 398 #define PWM_CLR_COUNTER(pwm, u32ChannelMask) ((pwm)->CNTCLR |= (u32ChannelMask))
sahilmgandhi 18:6a4db94011d3 399
sahilmgandhi 18:6a4db94011d3 400 /**
sahilmgandhi 18:6a4db94011d3 401 * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s)
sahilmgandhi 18:6a4db94011d3 402 * @param[in] pwm The pointer of the specified PWM module
sahilmgandhi 18:6a4db94011d3 403 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
sahilmgandhi 18:6a4db94011d3 404 * Bit 0 represents channel 0, bit 1 represents channel 1...
sahilmgandhi 18:6a4db94011d3 405 * @param[in] u32ZeroLevel output level at zero point, valid values are:
sahilmgandhi 18:6a4db94011d3 406 * - \ref PWM_OUTPUT_NOTHING
sahilmgandhi 18:6a4db94011d3 407 * - \ref PWM_OUTPUT_LOW
sahilmgandhi 18:6a4db94011d3 408 * - \ref PWM_OUTPUT_HIGH
sahilmgandhi 18:6a4db94011d3 409 * - \ref PWM_OUTPUT_TOGGLE
sahilmgandhi 18:6a4db94011d3 410 * @param[in] u32CmpUpLevel output level at compare up point, valid values are:
sahilmgandhi 18:6a4db94011d3 411 * - \ref PWM_OUTPUT_NOTHING
sahilmgandhi 18:6a4db94011d3 412 * - \ref PWM_OUTPUT_LOW
sahilmgandhi 18:6a4db94011d3 413 * - \ref PWM_OUTPUT_HIGH
sahilmgandhi 18:6a4db94011d3 414 * - \ref PWM_OUTPUT_TOGGLE
sahilmgandhi 18:6a4db94011d3 415 * @param[in] u32PeriodLevel output level at period(center) point, valid values are:
sahilmgandhi 18:6a4db94011d3 416 * - \ref PWM_OUTPUT_NOTHING
sahilmgandhi 18:6a4db94011d3 417 * - \ref PWM_OUTPUT_LOW
sahilmgandhi 18:6a4db94011d3 418 * - \ref PWM_OUTPUT_HIGH
sahilmgandhi 18:6a4db94011d3 419 * - \ref PWM_OUTPUT_TOGGLE
sahilmgandhi 18:6a4db94011d3 420 * @param[in] u32CmpDownLevel output level at compare down point, valid values are:
sahilmgandhi 18:6a4db94011d3 421 * - \ref PWM_OUTPUT_NOTHING
sahilmgandhi 18:6a4db94011d3 422 * - \ref PWM_OUTPUT_LOW
sahilmgandhi 18:6a4db94011d3 423 * - \ref PWM_OUTPUT_HIGH
sahilmgandhi 18:6a4db94011d3 424 * - \ref PWM_OUTPUT_TOGGLE
sahilmgandhi 18:6a4db94011d3 425 * @return None
sahilmgandhi 18:6a4db94011d3 426 * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s).
sahilmgandhi 18:6a4db94011d3 427 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 428 */
sahilmgandhi 18:6a4db94011d3 429 #define PWM_SET_OUTPUT_LEVEL(pwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \
sahilmgandhi 18:6a4db94011d3 430 do{ \
sahilmgandhi 18:6a4db94011d3 431 int i; \
sahilmgandhi 18:6a4db94011d3 432 for(i = 0; i < 6; i++) { \
sahilmgandhi 18:6a4db94011d3 433 if((u32ChannelMask) & (1 << i)) { \
sahilmgandhi 18:6a4db94011d3 434 (pwm)->WGCTL0 = (((pwm)->WGCTL0 & ~(3UL << (2 * i))) | ((u32ZeroLevel) << (2 * i))); \
sahilmgandhi 18:6a4db94011d3 435 (pwm)->WGCTL0 = (((pwm)->WGCTL0 & ~(3UL << (PWM_WGCTL0_PRDPCTLn_Pos + (2 * i)))) | ((u32PeriodLevel) << (PWM_WGCTL0_PRDPCTLn_Pos + (2 * i)))); \
sahilmgandhi 18:6a4db94011d3 436 (pwm)->WGCTL1 = (((pwm)->WGCTL1 & ~(3UL << (2 * i))) | ((u32CmpUpLevel) << (2 * i))); \
sahilmgandhi 18:6a4db94011d3 437 (pwm)->WGCTL1 = (((pwm)->WGCTL1 & ~(3UL << (PWM_WGCTL1_CMPDCTLn_Pos + (2 * i)))) | ((u32CmpDownLevel) << (PWM_WGCTL1_CMPDCTLn_Pos + (2 * i)))); \
sahilmgandhi 18:6a4db94011d3 438 } \
sahilmgandhi 18:6a4db94011d3 439 } \
sahilmgandhi 18:6a4db94011d3 440 }while(0)
sahilmgandhi 18:6a4db94011d3 441
sahilmgandhi 18:6a4db94011d3 442 /**
sahilmgandhi 18:6a4db94011d3 443 * @brief Trigger brake event from specified channel(s)
sahilmgandhi 18:6a4db94011d3 444 * @param[in] pwm The pointer of the specified PWM module
sahilmgandhi 18:6a4db94011d3 445 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
sahilmgandhi 18:6a4db94011d3 446 * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4
sahilmgandhi 18:6a4db94011d3 447 * @param[in] u32BrakeType Type of brake trigger. PWM_FB_EDGE of this macro is only supported in M45xD/M45xC.
sahilmgandhi 18:6a4db94011d3 448 * - \ref PWM_FB_EDGE
sahilmgandhi 18:6a4db94011d3 449 * - \ref PWM_FB_LEVEL
sahilmgandhi 18:6a4db94011d3 450 * @return None
sahilmgandhi 18:6a4db94011d3 451 * @details This macro is used to trigger brake event from specified channel(s).
sahilmgandhi 18:6a4db94011d3 452 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 453 */
sahilmgandhi 18:6a4db94011d3 454 #define PWM_TRIGGER_BRAKE(pwm, u32ChannelMask, u32BrakeType) ((pwm)->SWBRK |= ((u32ChannelMask) << (u32BrakeType)))
sahilmgandhi 18:6a4db94011d3 455
sahilmgandhi 18:6a4db94011d3 456 /**
sahilmgandhi 18:6a4db94011d3 457 * @brief Set Dead zone clock source
sahilmgandhi 18:6a4db94011d3 458 * @param[in] pwm The pointer of the specified PWM module
sahilmgandhi 18:6a4db94011d3 459 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
sahilmgandhi 18:6a4db94011d3 460 * @param[in] u32AfterPrescaler Dead zone clock source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler).
sahilmgandhi 18:6a4db94011d3 461 * @return None
sahilmgandhi 18:6a4db94011d3 462 * @details This macro is used to set Dead zone clock source. Every two channels share the same setting.
sahilmgandhi 18:6a4db94011d3 463 * @note The write-protection function should be disabled before using this function.
sahilmgandhi 18:6a4db94011d3 464 * @note This function is only supported in M45xD/M45xC.
sahilmgandhi 18:6a4db94011d3 465 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 466 */
sahilmgandhi 18:6a4db94011d3 467 #define PWM_SET_DEADZONE_CLK_SRC(pwm, u32ChannelNum, u32AfterPrescaler) \
sahilmgandhi 18:6a4db94011d3 468 (*(__IO uint32_t *) (&((pwm)->DTCTL0_1) + ((u32ChannelNum) >> 1)) = (*(__IO uint32_t *) (&((pwm)->DTCTL0_1) + ((u32ChannelNum) >> 1)) & ~PWM_DTCTL0_1_DTCKSEL_Msk) | \
sahilmgandhi 18:6a4db94011d3 469 ((u32AfterPrescaler) << PWM_DTCTL0_1_DTCKSEL_Pos))
sahilmgandhi 18:6a4db94011d3 470
sahilmgandhi 18:6a4db94011d3 471 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 472 /* Define PWM functions prototype */
sahilmgandhi 18:6a4db94011d3 473 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 474 uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge);
sahilmgandhi 18:6a4db94011d3 475 uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle);
sahilmgandhi 18:6a4db94011d3 476 uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm,
sahilmgandhi 18:6a4db94011d3 477 uint32_t u32ChannelNum,
sahilmgandhi 18:6a4db94011d3 478 uint32_t u32Frequency,
sahilmgandhi 18:6a4db94011d3 479 uint32_t u32DutyCycle,
sahilmgandhi 18:6a4db94011d3 480 uint32_t u32Frequency2);
sahilmgandhi 18:6a4db94011d3 481 void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask);
sahilmgandhi 18:6a4db94011d3 482 void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask);
sahilmgandhi 18:6a4db94011d3 483 void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask);
sahilmgandhi 18:6a4db94011d3 484 void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
sahilmgandhi 18:6a4db94011d3 485 void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 486 void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
sahilmgandhi 18:6a4db94011d3 487 uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 488 void PWM_EnableDACTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
sahilmgandhi 18:6a4db94011d3 489 void PWM_DisableDACTrigger(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 490 void PWM_ClearDACTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
sahilmgandhi 18:6a4db94011d3 491 uint32_t PWM_GetDACTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 492 void PWM_EnableFaultBrake(PWM_T *pwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource);
sahilmgandhi 18:6a4db94011d3 493 void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
sahilmgandhi 18:6a4db94011d3 494 void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
sahilmgandhi 18:6a4db94011d3 495 void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
sahilmgandhi 18:6a4db94011d3 496 void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
sahilmgandhi 18:6a4db94011d3 497 void PWM_EnablePDMA(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode);
sahilmgandhi 18:6a4db94011d3 498 void PWM_DisablePDMA(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 499 void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration);
sahilmgandhi 18:6a4db94011d3 500 void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 501 void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
sahilmgandhi 18:6a4db94011d3 502 void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
sahilmgandhi 18:6a4db94011d3 503 void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
sahilmgandhi 18:6a4db94011d3 504 uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 505 void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
sahilmgandhi 18:6a4db94011d3 506 void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 507 void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 508 uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 509 void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
sahilmgandhi 18:6a4db94011d3 510 void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
sahilmgandhi 18:6a4db94011d3 511 void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
sahilmgandhi 18:6a4db94011d3 512 uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
sahilmgandhi 18:6a4db94011d3 513 void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
sahilmgandhi 18:6a4db94011d3 514 void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 515 void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 516 uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 517 void PWM_EnableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 518 void PWM_DisableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 519 void PWM_ClearZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 520 uint32_t PWM_GetZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 521 void PWM_EnableAcc(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc);
sahilmgandhi 18:6a4db94011d3 522 void PWM_DisableAcc(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 523 void PWM_EnableAccInt(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 524 void PWM_DisableAccInt(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 525 void PWM_ClearAccInt(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 526 uint32_t PWM_GetAccInt(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 527 void PWM_ClearFTDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 528 uint32_t PWM_GetFTDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 529 void PWM_EnableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
sahilmgandhi 18:6a4db94011d3 530 void PWM_DisableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
sahilmgandhi 18:6a4db94011d3 531 void PWM_ConfigSyncPhase(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase);
sahilmgandhi 18:6a4db94011d3 532 void PWM_EnableSyncPhase(PWM_T *pwm, uint32_t u32ChannelMask);
sahilmgandhi 18:6a4db94011d3 533 void PWM_DisableSyncPhase(PWM_T *pwm, uint32_t u32ChannelMask);
sahilmgandhi 18:6a4db94011d3 534 void PWM_EnableSyncNoiseFilter(PWM_T *pwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel);
sahilmgandhi 18:6a4db94011d3 535 void PWM_DisableSyncNoiseFilter(PWM_T *pwm);
sahilmgandhi 18:6a4db94011d3 536 void PWM_EnableSyncPinInverse(PWM_T *pwm);
sahilmgandhi 18:6a4db94011d3 537 void PWM_DisableSyncPinInverse(PWM_T *pwm);
sahilmgandhi 18:6a4db94011d3 538 void PWM_SetClockSource(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel);
sahilmgandhi 18:6a4db94011d3 539 void PWM_EnableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel);
sahilmgandhi 18:6a4db94011d3 540 void PWM_DisableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum);
sahilmgandhi 18:6a4db94011d3 541 void PWM_EnableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum);
sahilmgandhi 18:6a4db94011d3 542 void PWM_DisableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum);
sahilmgandhi 18:6a4db94011d3 543 void PWM_SetBrakePinSource(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule);
sahilmgandhi 18:6a4db94011d3 544 uint32_t PWM_GetWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 545 void PWM_ClearWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum);
sahilmgandhi 18:6a4db94011d3 546
sahilmgandhi 18:6a4db94011d3 547
sahilmgandhi 18:6a4db94011d3 548 /*@}*/ /* end of group PWM_EXPORTED_FUNCTIONS */
sahilmgandhi 18:6a4db94011d3 549
sahilmgandhi 18:6a4db94011d3 550 /*@}*/ /* end of group PWM_Driver */
sahilmgandhi 18:6a4db94011d3 551
sahilmgandhi 18:6a4db94011d3 552 /*@}*/ /* end of group Standard_Driver */
sahilmgandhi 18:6a4db94011d3 553
sahilmgandhi 18:6a4db94011d3 554 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 555 }
sahilmgandhi 18:6a4db94011d3 556 #endif
sahilmgandhi 18:6a4db94011d3 557
sahilmgandhi 18:6a4db94011d3 558 #endif //__PWM_H__
sahilmgandhi 18:6a4db94011d3 559
sahilmgandhi 18:6a4db94011d3 560 /*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/