MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_dac.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /******************************************************************************
sahilmgandhi 18:6a4db94011d3 2 * @file dac.h
sahilmgandhi 18:6a4db94011d3 3 * @version V0.10
sahilmgandhi 18:6a4db94011d3 4 * $Revision: 12 $
sahilmgandhi 18:6a4db94011d3 5 * $Date: 15/08/11 10:26a $
sahilmgandhi 18:6a4db94011d3 6 * @brief M451 series DAC driver header file
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * @note
sahilmgandhi 18:6a4db94011d3 9 * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
sahilmgandhi 18:6a4db94011d3 10 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 11 #ifndef __DAC_H__
sahilmgandhi 18:6a4db94011d3 12 #define __DAC_H__
sahilmgandhi 18:6a4db94011d3 13
sahilmgandhi 18:6a4db94011d3 14 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 15 /* Include related headers */
sahilmgandhi 18:6a4db94011d3 16 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 17 #include "M451Series.h"
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19
sahilmgandhi 18:6a4db94011d3 20 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 21 extern "C"
sahilmgandhi 18:6a4db94011d3 22 {
sahilmgandhi 18:6a4db94011d3 23 #endif
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 /** @addtogroup Standard_Driver Standard Driver
sahilmgandhi 18:6a4db94011d3 27 @{
sahilmgandhi 18:6a4db94011d3 28 */
sahilmgandhi 18:6a4db94011d3 29
sahilmgandhi 18:6a4db94011d3 30 /** @addtogroup DAC_Driver DAC Driver
sahilmgandhi 18:6a4db94011d3 31 @{
sahilmgandhi 18:6a4db94011d3 32 */
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34
sahilmgandhi 18:6a4db94011d3 35 /** @addtogroup DAC_EXPORTED_CONSTANTS DAC Exported Constants
sahilmgandhi 18:6a4db94011d3 36 @{
sahilmgandhi 18:6a4db94011d3 37 */
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 40 /* DAC_CTL Constant Definitions */
sahilmgandhi 18:6a4db94011d3 41 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 42 #define DAC_CTL_LALIGN_RIGHT_ALIGN (0UL<<DAC_CTL_LALIGN_Pos) /*!< Right alignment. */
sahilmgandhi 18:6a4db94011d3 43 #define DAC_CTL_LALIGN_LEFT_ALIGN (1UL<<DAC_CTL_LALIGN_Pos) /*!< Left alignment */
sahilmgandhi 18:6a4db94011d3 44
sahilmgandhi 18:6a4db94011d3 45 #define DAC_WRITE_DAT_TRIGGER (0UL) /*!< Write DAC_DAT trigger */
sahilmgandhi 18:6a4db94011d3 46 #define DAC_SOFTWARE_TRIGGER (0UL|DAC_CTL_TRGEN_Msk) /*!< Software trigger */
sahilmgandhi 18:6a4db94011d3 47 #define DAC_LOW_LEVEL_TRIGGER ((0UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin low level trigger */
sahilmgandhi 18:6a4db94011d3 48 #define DAC_HIGH_LEVEL_TRIGGER ((1UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin high level trigger */
sahilmgandhi 18:6a4db94011d3 49 #define DAC_FALLING_EDGE_TRIGGER ((2UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin falling edge trigger */
sahilmgandhi 18:6a4db94011d3 50 #define DAC_RISING_EDGE_TRIGGER ((3UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin rising edge trigger */
sahilmgandhi 18:6a4db94011d3 51 #define DAC_TIMER0_TRIGGER ((2UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 0 trigger */
sahilmgandhi 18:6a4db94011d3 52 #define DAC_TIMER1_TRIGGER ((3UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 1 trigger */
sahilmgandhi 18:6a4db94011d3 53 #define DAC_TIMER2_TRIGGER ((4UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 2 trigger */
sahilmgandhi 18:6a4db94011d3 54 #define DAC_TIMER3_TRIGGER ((5UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 3 trigger */
sahilmgandhi 18:6a4db94011d3 55 #define DAC_PWM0_TRIGGER ((6UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< PWM0 trigger */
sahilmgandhi 18:6a4db94011d3 56 #define DAC_PWM1_TRIGGER ((7UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< PWM1 trigger */
sahilmgandhi 18:6a4db94011d3 57
sahilmgandhi 18:6a4db94011d3 58 #define DAC_TRIGGER_MODE_DISABLE (0UL<<DAC_CTL_TRGEN_Pos) /*!< Trigger mode disable */
sahilmgandhi 18:6a4db94011d3 59 #define DAC_TRIGGER_MODE_ENABLE (1UL<<DAC_CTL_TRGEN_Pos) /*!< Trigger mode enable */
sahilmgandhi 18:6a4db94011d3 60
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62 /*@}*/ /* end of group DAC_EXPORTED_CONSTANTS */
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64
sahilmgandhi 18:6a4db94011d3 65 /** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions
sahilmgandhi 18:6a4db94011d3 66 @{
sahilmgandhi 18:6a4db94011d3 67 */
sahilmgandhi 18:6a4db94011d3 68 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 69 /* DAC Macro Definitions */
sahilmgandhi 18:6a4db94011d3 70 /*---------------------------------------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72 /**
sahilmgandhi 18:6a4db94011d3 73 * @brief Start the D/A conversion.
sahilmgandhi 18:6a4db94011d3 74 * @param[in] dac Base address of DAC module.
sahilmgandhi 18:6a4db94011d3 75 * @return None
sahilmgandhi 18:6a4db94011d3 76 * @details User writes SWTRG bit (DAC_SWTRG[0]) to generate one shot pulse and it is cleared to 0 by hardware automatically.
sahilmgandhi 18:6a4db94011d3 77 */
sahilmgandhi 18:6a4db94011d3 78 #define DAC_START_CONV(dac) ((dac)->SWTRG = DAC_SWTRG_SWTRG_Msk)
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 /**
sahilmgandhi 18:6a4db94011d3 81 * @brief Enable DAC data left-aligned.
sahilmgandhi 18:6a4db94011d3 82 * @param[in] dac Base address of DAC module.
sahilmgandhi 18:6a4db94011d3 83 * @return None
sahilmgandhi 18:6a4db94011d3 84 * @details User has to load data into DAC_DAT[15:4] bits. DAC_DAT[31:16] and DAC_DAT[3:0] are ignored in DAC conversion.
sahilmgandhi 18:6a4db94011d3 85 */
sahilmgandhi 18:6a4db94011d3 86 #define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk)
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 /**
sahilmgandhi 18:6a4db94011d3 89 * @brief Enable DAC data right-aligned.
sahilmgandhi 18:6a4db94011d3 90 * @param[in] dac Base address of DAC module.
sahilmgandhi 18:6a4db94011d3 91 * @return None
sahilmgandhi 18:6a4db94011d3 92 * @details User has to load data into DAC_DAT[11:0] bits, DAC_DAT[31:12] are ignored in DAC conversion.
sahilmgandhi 18:6a4db94011d3 93 */
sahilmgandhi 18:6a4db94011d3 94 #define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk)
sahilmgandhi 18:6a4db94011d3 95
sahilmgandhi 18:6a4db94011d3 96 /**
sahilmgandhi 18:6a4db94011d3 97 * @brief Enable output voltage buffer.
sahilmgandhi 18:6a4db94011d3 98 * @param[in] dac Base address of DAC module.
sahilmgandhi 18:6a4db94011d3 99 * @return None
sahilmgandhi 18:6a4db94011d3 100 * @details The DAC integrates a voltage output buffer that can be used to reduce output impedance and
sahilmgandhi 18:6a4db94011d3 101 * drive external loads directly without having to add an external operational amplifier.
sahilmgandhi 18:6a4db94011d3 102 */
sahilmgandhi 18:6a4db94011d3 103 #define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk)
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105 /**
sahilmgandhi 18:6a4db94011d3 106 * @brief Disable output voltage buffer.
sahilmgandhi 18:6a4db94011d3 107 * @param[in] dac Base address of DAC module.
sahilmgandhi 18:6a4db94011d3 108 * @return None
sahilmgandhi 18:6a4db94011d3 109 * @details This macro is used to disable output voltage buffer.
sahilmgandhi 18:6a4db94011d3 110 */
sahilmgandhi 18:6a4db94011d3 111 #define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk)
sahilmgandhi 18:6a4db94011d3 112
sahilmgandhi 18:6a4db94011d3 113 /**
sahilmgandhi 18:6a4db94011d3 114 * @brief Enable the interrupt.
sahilmgandhi 18:6a4db94011d3 115 * @param[in] dac Base address of DAC module.
sahilmgandhi 18:6a4db94011d3 116 * @param[in] u32Ch Not used in M451 Series DAC.
sahilmgandhi 18:6a4db94011d3 117 * @return None
sahilmgandhi 18:6a4db94011d3 118 * @details This macro is used to enable DAC interrupt.
sahilmgandhi 18:6a4db94011d3 119 */
sahilmgandhi 18:6a4db94011d3 120 #define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk)
sahilmgandhi 18:6a4db94011d3 121
sahilmgandhi 18:6a4db94011d3 122 /**
sahilmgandhi 18:6a4db94011d3 123 * @brief Disable the interrupt.
sahilmgandhi 18:6a4db94011d3 124 * @param[in] dac Base address of DAC module.
sahilmgandhi 18:6a4db94011d3 125 * @param[in] u32Ch Not used in M451 Series DAC.
sahilmgandhi 18:6a4db94011d3 126 * @return None
sahilmgandhi 18:6a4db94011d3 127 * @details This macro is used to disable DAC interrupt.
sahilmgandhi 18:6a4db94011d3 128 */
sahilmgandhi 18:6a4db94011d3 129 #define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk)
sahilmgandhi 18:6a4db94011d3 130
sahilmgandhi 18:6a4db94011d3 131 /**
sahilmgandhi 18:6a4db94011d3 132 * @brief Enable DMA under-run interrupt.
sahilmgandhi 18:6a4db94011d3 133 * @param[in] dac Base address of DAC module.
sahilmgandhi 18:6a4db94011d3 134 * @return None
sahilmgandhi 18:6a4db94011d3 135 * @details This macro is used to enable DMA under-run interrupt.
sahilmgandhi 18:6a4db94011d3 136 */
sahilmgandhi 18:6a4db94011d3 137 #define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk)
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139 /**
sahilmgandhi 18:6a4db94011d3 140 * @brief Disable DMA under-run interrupt.
sahilmgandhi 18:6a4db94011d3 141 * @param[in] dac Base address of DAC module.
sahilmgandhi 18:6a4db94011d3 142 * @return None
sahilmgandhi 18:6a4db94011d3 143 * @details This macro is used to disable DMA under-run interrupt.
sahilmgandhi 18:6a4db94011d3 144 */
sahilmgandhi 18:6a4db94011d3 145 #define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk)
sahilmgandhi 18:6a4db94011d3 146
sahilmgandhi 18:6a4db94011d3 147 /**
sahilmgandhi 18:6a4db94011d3 148 * @brief Enable PDMA mode.
sahilmgandhi 18:6a4db94011d3 149 * @param[in] dac Base address of DAC module.
sahilmgandhi 18:6a4db94011d3 150 * @return None
sahilmgandhi 18:6a4db94011d3 151 * @details DAC DMA request is generated when a hardware trigger event occurs while DMAEN (DAC_CTL[2]) is set.
sahilmgandhi 18:6a4db94011d3 152 */
sahilmgandhi 18:6a4db94011d3 153 #define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk)
sahilmgandhi 18:6a4db94011d3 154
sahilmgandhi 18:6a4db94011d3 155 /**
sahilmgandhi 18:6a4db94011d3 156 * @brief Disable PDMA mode.
sahilmgandhi 18:6a4db94011d3 157 * @param[in] dac Base address of DAC module.
sahilmgandhi 18:6a4db94011d3 158 * @return None
sahilmgandhi 18:6a4db94011d3 159 * @details This macro is used to disable DMA mode.
sahilmgandhi 18:6a4db94011d3 160 */
sahilmgandhi 18:6a4db94011d3 161 #define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk)
sahilmgandhi 18:6a4db94011d3 162
sahilmgandhi 18:6a4db94011d3 163 /**
sahilmgandhi 18:6a4db94011d3 164 * @brief Write data for conversion.
sahilmgandhi 18:6a4db94011d3 165 * @param[in] dac Base address of DAC module.
sahilmgandhi 18:6a4db94011d3 166 * @param[in] u32Ch Not used in M451 Series DAC.
sahilmgandhi 18:6a4db94011d3 167 * @param[in] u32Data Decides the data for conversion, valid range are between 0~0xFFF.
sahilmgandhi 18:6a4db94011d3 168 * @return None
sahilmgandhi 18:6a4db94011d3 169 * @details 12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.
sahilmgandhi 18:6a4db94011d3 170 * 12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.
sahilmgandhi 18:6a4db94011d3 171 */
sahilmgandhi 18:6a4db94011d3 172 #define DAC_WRITE_DATA(dac, u32Ch, u32Data) ((dac)->DAT = (u32Data))
sahilmgandhi 18:6a4db94011d3 173
sahilmgandhi 18:6a4db94011d3 174 /**
sahilmgandhi 18:6a4db94011d3 175 * @brief Read DAC 12-bit holding data.
sahilmgandhi 18:6a4db94011d3 176 * @param[in] dac Base address of DAC module.
sahilmgandhi 18:6a4db94011d3 177 * @param[in] u32Ch Not used in M451 Series DAC.
sahilmgandhi 18:6a4db94011d3 178 * @return Return DAC 12-bit holding data.
sahilmgandhi 18:6a4db94011d3 179 * @details This macro is used to read DAC_DAT register.
sahilmgandhi 18:6a4db94011d3 180 */
sahilmgandhi 18:6a4db94011d3 181 #define DAC_READ_DATA(dac, u32Ch) ((dac)->DAT)
sahilmgandhi 18:6a4db94011d3 182
sahilmgandhi 18:6a4db94011d3 183 /**
sahilmgandhi 18:6a4db94011d3 184 * @brief Get the busy state of DAC.
sahilmgandhi 18:6a4db94011d3 185 * @param[in] dac Base address of DAC module.
sahilmgandhi 18:6a4db94011d3 186 * @param[in] u32Ch Not used in M451 Series DAC.
sahilmgandhi 18:6a4db94011d3 187 * @retval 0 Idle state.
sahilmgandhi 18:6a4db94011d3 188 * @retval 1 Busy state.
sahilmgandhi 18:6a4db94011d3 189 * @details This macro is used to read BUSY bit (DAC_STATUS[8]) to get busy state.
sahilmgandhi 18:6a4db94011d3 190 */
sahilmgandhi 18:6a4db94011d3 191 #define DAC_IS_BUSY(dac, u32Ch) (((dac)->STATUS & DAC_STATUS_BUSY_Msk) >> DAC_STATUS_BUSY_Pos)
sahilmgandhi 18:6a4db94011d3 192
sahilmgandhi 18:6a4db94011d3 193 /**
sahilmgandhi 18:6a4db94011d3 194 * @brief Get the interrupt flag.
sahilmgandhi 18:6a4db94011d3 195 * @param[in] dac Base address of DAC module.
sahilmgandhi 18:6a4db94011d3 196 * @param[in] u32Ch Not used in M451 Series DAC.
sahilmgandhi 18:6a4db94011d3 197 * @retval 0 DAC is in conversion state.
sahilmgandhi 18:6a4db94011d3 198 * @retval 1 DAC conversion finish.
sahilmgandhi 18:6a4db94011d3 199 * @details This macro is used to read FINISH bit (DAC_STATUS[0]) to get DAC conversion complete finish flag.
sahilmgandhi 18:6a4db94011d3 200 */
sahilmgandhi 18:6a4db94011d3 201 #define DAC_GET_INT_FLAG(dac, u32Ch) ((dac)->STATUS & DAC_STATUS_FINISH_Msk)
sahilmgandhi 18:6a4db94011d3 202
sahilmgandhi 18:6a4db94011d3 203 /**
sahilmgandhi 18:6a4db94011d3 204 * @brief Get the DMA under-run flag.
sahilmgandhi 18:6a4db94011d3 205 * @param[in] dac Base address of DAC module.
sahilmgandhi 18:6a4db94011d3 206 * @retval 0 No DMA under-run error condition occurred.
sahilmgandhi 18:6a4db94011d3 207 * @retval 1 DMA under-run error condition occurred.
sahilmgandhi 18:6a4db94011d3 208 * @details This macro is used to read DMAUDR bit (DAC_STATUS[1]) to get DMA under-run state.
sahilmgandhi 18:6a4db94011d3 209 */
sahilmgandhi 18:6a4db94011d3 210 #define DAC_GET_DMAUDR_FLAG(dac) (((dac)->STATUS & DAC_STATUS_DMAUDR_Msk) >> DAC_STATUS_DMAUDR_Pos)
sahilmgandhi 18:6a4db94011d3 211
sahilmgandhi 18:6a4db94011d3 212 /**
sahilmgandhi 18:6a4db94011d3 213 * @brief This macro clear the interrupt status bit.
sahilmgandhi 18:6a4db94011d3 214 * @param[in] dac Base address of DAC module.
sahilmgandhi 18:6a4db94011d3 215 * @param[in] u32Ch Not used in M451 Series DAC.
sahilmgandhi 18:6a4db94011d3 216 * @return None
sahilmgandhi 18:6a4db94011d3 217 * @details User writes FINISH bit (DAC_STATUS[0]) to clear DAC conversion complete finish flag.
sahilmgandhi 18:6a4db94011d3 218 */
sahilmgandhi 18:6a4db94011d3 219 #define DAC_CLR_INT_FLAG(dac, u32Ch) ((dac)->STATUS = DAC_STATUS_FINISH_Msk)
sahilmgandhi 18:6a4db94011d3 220
sahilmgandhi 18:6a4db94011d3 221 /**
sahilmgandhi 18:6a4db94011d3 222 * @brief This macro clear the DMA under-run flag.
sahilmgandhi 18:6a4db94011d3 223 * @param[in] dac Base address of DAC module.
sahilmgandhi 18:6a4db94011d3 224 * @return None
sahilmgandhi 18:6a4db94011d3 225 * @details User writes DMAUDR bit (DAC_STATUS[1]) to clear DMA under-run flag.
sahilmgandhi 18:6a4db94011d3 226 */
sahilmgandhi 18:6a4db94011d3 227 #define DAC_CLR_DMAUDR_FLAG(dac) ((dac)->STATUS = DAC_STATUS_DMAUDR_Msk)
sahilmgandhi 18:6a4db94011d3 228
sahilmgandhi 18:6a4db94011d3 229 void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc);
sahilmgandhi 18:6a4db94011d3 230 void DAC_Close(DAC_T *dac, uint32_t u32Ch);
sahilmgandhi 18:6a4db94011d3 231 float DAC_SetDelayTime(DAC_T *dac, uint32_t u16Delay);
sahilmgandhi 18:6a4db94011d3 232
sahilmgandhi 18:6a4db94011d3 233 /*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */
sahilmgandhi 18:6a4db94011d3 234
sahilmgandhi 18:6a4db94011d3 235 /*@}*/ /* end of group DAC_Driver */
sahilmgandhi 18:6a4db94011d3 236
sahilmgandhi 18:6a4db94011d3 237 /*@}*/ /* end of group Standard_Driver */
sahilmgandhi 18:6a4db94011d3 238
sahilmgandhi 18:6a4db94011d3 239 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 240 }
sahilmgandhi 18:6a4db94011d3 241 #endif
sahilmgandhi 18:6a4db94011d3 242
sahilmgandhi 18:6a4db94011d3 243 #endif //__DAC_H__
sahilmgandhi 18:6a4db94011d3 244
sahilmgandhi 18:6a4db94011d3 245 /*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/