MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_crc.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file crc.c
sahilmgandhi 18:6a4db94011d3 3 * @version V3.00
sahilmgandhi 18:6a4db94011d3 4 * $Revision: 7 $
sahilmgandhi 18:6a4db94011d3 5 * $Date: 15/08/11 10:26a $
sahilmgandhi 18:6a4db94011d3 6 * @brief M451 series CRC driver source file
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * @note
sahilmgandhi 18:6a4db94011d3 9 * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
sahilmgandhi 18:6a4db94011d3 10 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 11 #include "M451Series.h"
sahilmgandhi 18:6a4db94011d3 12
sahilmgandhi 18:6a4db94011d3 13
sahilmgandhi 18:6a4db94011d3 14 /** @addtogroup Standard_Driver Standard Driver
sahilmgandhi 18:6a4db94011d3 15 @{
sahilmgandhi 18:6a4db94011d3 16 */
sahilmgandhi 18:6a4db94011d3 17
sahilmgandhi 18:6a4db94011d3 18 /** @addtogroup CRC_Driver CRC Driver
sahilmgandhi 18:6a4db94011d3 19 @{
sahilmgandhi 18:6a4db94011d3 20 */
sahilmgandhi 18:6a4db94011d3 21
sahilmgandhi 18:6a4db94011d3 22 /** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions
sahilmgandhi 18:6a4db94011d3 23 @{
sahilmgandhi 18:6a4db94011d3 24 */
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 /**
sahilmgandhi 18:6a4db94011d3 27 * @brief CRC Open
sahilmgandhi 18:6a4db94011d3 28 *
sahilmgandhi 18:6a4db94011d3 29 * @param[in] u32Mode CRC operation polynomial mode. Valid values are:
sahilmgandhi 18:6a4db94011d3 30 * - \ref CRC_CCITT
sahilmgandhi 18:6a4db94011d3 31 * - \ref CRC_8
sahilmgandhi 18:6a4db94011d3 32 * - \ref CRC_16
sahilmgandhi 18:6a4db94011d3 33 * - \ref CRC_32
sahilmgandhi 18:6a4db94011d3 34 * @param[in] u32Attribute CRC operation data attribute. Valid values are combined with:
sahilmgandhi 18:6a4db94011d3 35 * - \ref CRC_CHECKSUM_COM
sahilmgandhi 18:6a4db94011d3 36 * - \ref CRC_CHECKSUM_RVS
sahilmgandhi 18:6a4db94011d3 37 * - \ref CRC_WDATA_COM
sahilmgandhi 18:6a4db94011d3 38 * - \ref CRC_WDATA_RVS
sahilmgandhi 18:6a4db94011d3 39 * @param[in] u32Seed Seed value.
sahilmgandhi 18:6a4db94011d3 40 * @param[in] u32DataLen CPU Write Data Length. Valid values are:
sahilmgandhi 18:6a4db94011d3 41 * - \ref CRC_CPU_WDATA_8
sahilmgandhi 18:6a4db94011d3 42 * - \ref CRC_CPU_WDATA_16
sahilmgandhi 18:6a4db94011d3 43 * - \ref CRC_CPU_WDATA_32
sahilmgandhi 18:6a4db94011d3 44 *
sahilmgandhi 18:6a4db94011d3 45 * @return None
sahilmgandhi 18:6a4db94011d3 46 *
sahilmgandhi 18:6a4db94011d3 47 * @details This function will enable the CRC controller by specify CRC operation mode, attribute, initial seed and write data length. \n
sahilmgandhi 18:6a4db94011d3 48 * After that, user can start to perform CRC calculate by calling CRC_WRITE_DATA macro or CRC_DAT register directly.
sahilmgandhi 18:6a4db94011d3 49 */
sahilmgandhi 18:6a4db94011d3 50 void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen)
sahilmgandhi 18:6a4db94011d3 51 {
sahilmgandhi 18:6a4db94011d3 52 CRC->SEED = u32Seed;
sahilmgandhi 18:6a4db94011d3 53 CRC->CTL = u32Mode | u32Attribute | u32DataLen | CRC_CTL_CRCEN_Msk;
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 /* Setting CRCRST bit will reload the initial seed value(CRC_SEED register) to CRC controller */
sahilmgandhi 18:6a4db94011d3 56 CRC->CTL |= CRC_CTL_CRCRST_Msk;
sahilmgandhi 18:6a4db94011d3 57 }
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 /**
sahilmgandhi 18:6a4db94011d3 60 * @brief Get CRC Checksum
sahilmgandhi 18:6a4db94011d3 61 *
sahilmgandhi 18:6a4db94011d3 62 * @param[in] None
sahilmgandhi 18:6a4db94011d3 63 *
sahilmgandhi 18:6a4db94011d3 64 * @return Checksum Result
sahilmgandhi 18:6a4db94011d3 65 *
sahilmgandhi 18:6a4db94011d3 66 * @details This macro gets the CRC checksum result by current CRC polynomial mode.
sahilmgandhi 18:6a4db94011d3 67 */
sahilmgandhi 18:6a4db94011d3 68 uint32_t CRC_GetChecksum(void)
sahilmgandhi 18:6a4db94011d3 69 {
sahilmgandhi 18:6a4db94011d3 70 switch(CRC->CTL & CRC_CTL_CRCMODE_Msk)
sahilmgandhi 18:6a4db94011d3 71 {
sahilmgandhi 18:6a4db94011d3 72 case CRC_CCITT:
sahilmgandhi 18:6a4db94011d3 73 case CRC_16:
sahilmgandhi 18:6a4db94011d3 74 return (CRC->CHECKSUM & 0xFFFF);
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76 case CRC_32:
sahilmgandhi 18:6a4db94011d3 77 return (CRC->CHECKSUM);
sahilmgandhi 18:6a4db94011d3 78
sahilmgandhi 18:6a4db94011d3 79 case CRC_8:
sahilmgandhi 18:6a4db94011d3 80 return (CRC->CHECKSUM & 0xFF);
sahilmgandhi 18:6a4db94011d3 81
sahilmgandhi 18:6a4db94011d3 82 default:
sahilmgandhi 18:6a4db94011d3 83 return 0;
sahilmgandhi 18:6a4db94011d3 84 }
sahilmgandhi 18:6a4db94011d3 85 }
sahilmgandhi 18:6a4db94011d3 86
sahilmgandhi 18:6a4db94011d3 87 /*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 /*@}*/ /* end of group CRC_Driver */
sahilmgandhi 18:6a4db94011d3 90
sahilmgandhi 18:6a4db94011d3 91 /*@}*/ /* end of group Standard_Driver */
sahilmgandhi 18:6a4db94011d3 92
sahilmgandhi 18:6a4db94011d3 93 /*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/