MacroRat
Mouse code for the MacroRat
mbed-dev/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_clk.c@46:b156ef445742, 2017-06-03 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sat Jun 03 00:22:44 2017 +0000
- Revision:
- 46:b156ef445742
- Parent:
- 18:6a4db94011d3
Final code for internal battlebot competition.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| sahilmgandhi | 18:6a4db94011d3 | 1 | /**************************************************************************//** |
| sahilmgandhi | 18:6a4db94011d3 | 2 | * @file clk.c |
| sahilmgandhi | 18:6a4db94011d3 | 3 | * @version V3.00 |
| sahilmgandhi | 18:6a4db94011d3 | 4 | * $Revision: 35 $ |
| sahilmgandhi | 18:6a4db94011d3 | 5 | * $Date: 15/08/11 10:26a $ |
| sahilmgandhi | 18:6a4db94011d3 | 6 | * @brief M451 series CLK driver source file |
| sahilmgandhi | 18:6a4db94011d3 | 7 | * |
| sahilmgandhi | 18:6a4db94011d3 | 8 | * @note |
| sahilmgandhi | 18:6a4db94011d3 | 9 | * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved. |
| sahilmgandhi | 18:6a4db94011d3 | 10 | *****************************************************************************/ |
| sahilmgandhi | 18:6a4db94011d3 | 11 | |
| sahilmgandhi | 18:6a4db94011d3 | 12 | #include "M451Series.h" |
| sahilmgandhi | 18:6a4db94011d3 | 13 | |
| sahilmgandhi | 18:6a4db94011d3 | 14 | /** @addtogroup Standard_Driver Standard Driver |
| sahilmgandhi | 18:6a4db94011d3 | 15 | @{ |
| sahilmgandhi | 18:6a4db94011d3 | 16 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 17 | |
| sahilmgandhi | 18:6a4db94011d3 | 18 | /** @addtogroup CLK_Driver CLK Driver |
| sahilmgandhi | 18:6a4db94011d3 | 19 | @{ |
| sahilmgandhi | 18:6a4db94011d3 | 20 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 21 | |
| sahilmgandhi | 18:6a4db94011d3 | 22 | /** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions |
| sahilmgandhi | 18:6a4db94011d3 | 23 | @{ |
| sahilmgandhi | 18:6a4db94011d3 | 24 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 25 | |
| sahilmgandhi | 18:6a4db94011d3 | 26 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 27 | * @brief Disable clock divider output function |
| sahilmgandhi | 18:6a4db94011d3 | 28 | * @param None |
| sahilmgandhi | 18:6a4db94011d3 | 29 | * @return None |
| sahilmgandhi | 18:6a4db94011d3 | 30 | * @details This function disable clock divider output function. |
| sahilmgandhi | 18:6a4db94011d3 | 31 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 32 | void CLK_DisableCKO(void) |
| sahilmgandhi | 18:6a4db94011d3 | 33 | { |
| sahilmgandhi | 18:6a4db94011d3 | 34 | /* Disable CKO clock source */ |
| sahilmgandhi | 18:6a4db94011d3 | 35 | CLK_DisableModuleClock(CLKO_MODULE); |
| sahilmgandhi | 18:6a4db94011d3 | 36 | } |
| sahilmgandhi | 18:6a4db94011d3 | 37 | |
| sahilmgandhi | 18:6a4db94011d3 | 38 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 39 | * @brief This function enable clock divider output module clock, |
| sahilmgandhi | 18:6a4db94011d3 | 40 | * enable clock divider output function and set frequency selection. |
| sahilmgandhi | 18:6a4db94011d3 | 41 | * @param[in] u32ClkSrc is frequency divider function clock source. Including : |
| sahilmgandhi | 18:6a4db94011d3 | 42 | * - \ref CLK_CLKSEL1_CLKOSEL_HXT |
| sahilmgandhi | 18:6a4db94011d3 | 43 | * - \ref CLK_CLKSEL1_CLKOSEL_LXT |
| sahilmgandhi | 18:6a4db94011d3 | 44 | * - \ref CLK_CLKSEL1_CLKOSEL_HCLK |
| sahilmgandhi | 18:6a4db94011d3 | 45 | * - \ref CLK_CLKSEL1_CLKOSEL_HIRC |
| sahilmgandhi | 18:6a4db94011d3 | 46 | * @param[in] u32ClkDiv is divider output frequency selection. It could be 0~15. |
| sahilmgandhi | 18:6a4db94011d3 | 47 | * @param[in] u32ClkDivBy1En is clock divided by one enabled. |
| sahilmgandhi | 18:6a4db94011d3 | 48 | * @return None |
| sahilmgandhi | 18:6a4db94011d3 | 49 | * @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. \n |
| sahilmgandhi | 18:6a4db94011d3 | 50 | * The formula is: \n |
| sahilmgandhi | 18:6a4db94011d3 | 51 | * CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) \n |
| sahilmgandhi | 18:6a4db94011d3 | 52 | * This function is just used to set CKO clock. |
| sahilmgandhi | 18:6a4db94011d3 | 53 | * User must enable I/O for CKO clock output pin by themselves. \n |
| sahilmgandhi | 18:6a4db94011d3 | 54 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 55 | void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En) |
| sahilmgandhi | 18:6a4db94011d3 | 56 | { |
| sahilmgandhi | 18:6a4db94011d3 | 57 | /* CKO = clock source / 2^(u32ClkDiv + 1) */ |
| sahilmgandhi | 18:6a4db94011d3 | 58 | CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | u32ClkDiv | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos); |
| sahilmgandhi | 18:6a4db94011d3 | 59 | |
| sahilmgandhi | 18:6a4db94011d3 | 60 | /* Enable CKO clock source */ |
| sahilmgandhi | 18:6a4db94011d3 | 61 | CLK_EnableModuleClock(CLKO_MODULE); |
| sahilmgandhi | 18:6a4db94011d3 | 62 | |
| sahilmgandhi | 18:6a4db94011d3 | 63 | /* Select CKO clock source */ |
| sahilmgandhi | 18:6a4db94011d3 | 64 | CLK_SetModuleClock(CLKO_MODULE, u32ClkSrc, 0); |
| sahilmgandhi | 18:6a4db94011d3 | 65 | } |
| sahilmgandhi | 18:6a4db94011d3 | 66 | |
| sahilmgandhi | 18:6a4db94011d3 | 67 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 68 | * @brief Enter to Power-down mode |
| sahilmgandhi | 18:6a4db94011d3 | 69 | * @param None |
| sahilmgandhi | 18:6a4db94011d3 | 70 | * @return None |
| sahilmgandhi | 18:6a4db94011d3 | 71 | * @details This function is used to let system enter to Power-down mode. \n |
| sahilmgandhi | 18:6a4db94011d3 | 72 | * The register write-protection function should be disabled before using this function. |
| sahilmgandhi | 18:6a4db94011d3 | 73 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 74 | void CLK_PowerDown(void) |
| sahilmgandhi | 18:6a4db94011d3 | 75 | { |
| sahilmgandhi | 18:6a4db94011d3 | 76 | /* Set the processor uses deep sleep as its low power mode */ |
| sahilmgandhi | 18:6a4db94011d3 | 77 | SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; |
| sahilmgandhi | 18:6a4db94011d3 | 78 | |
| sahilmgandhi | 18:6a4db94011d3 | 79 | /* Set system Power-down enabled and Power-down entry condition */ |
| sahilmgandhi | 18:6a4db94011d3 | 80 | CLK->PWRCTL |= (CLK_PWRCTL_PDEN_Msk | CLK_PWRCTL_PDWTCPU_Msk); |
| sahilmgandhi | 18:6a4db94011d3 | 81 | |
| sahilmgandhi | 18:6a4db94011d3 | 82 | /* Chip enter Power-down mode after CPU run WFI instruction */ |
| sahilmgandhi | 18:6a4db94011d3 | 83 | __WFI(); |
| sahilmgandhi | 18:6a4db94011d3 | 84 | } |
| sahilmgandhi | 18:6a4db94011d3 | 85 | |
| sahilmgandhi | 18:6a4db94011d3 | 86 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 87 | * @brief Enter to Idle mode |
| sahilmgandhi | 18:6a4db94011d3 | 88 | * @param None |
| sahilmgandhi | 18:6a4db94011d3 | 89 | * @return None |
| sahilmgandhi | 18:6a4db94011d3 | 90 | * @details This function let system enter to Idle mode. \n |
| sahilmgandhi | 18:6a4db94011d3 | 91 | * The register write-protection function should be disabled before using this function. |
| sahilmgandhi | 18:6a4db94011d3 | 92 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 93 | void CLK_Idle(void) |
| sahilmgandhi | 18:6a4db94011d3 | 94 | { |
| sahilmgandhi | 18:6a4db94011d3 | 95 | /* Set the processor uses sleep as its low power mode */ |
| sahilmgandhi | 18:6a4db94011d3 | 96 | SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; |
| sahilmgandhi | 18:6a4db94011d3 | 97 | |
| sahilmgandhi | 18:6a4db94011d3 | 98 | /* Set chip in idle mode because of WFI command */ |
| sahilmgandhi | 18:6a4db94011d3 | 99 | CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk; |
| sahilmgandhi | 18:6a4db94011d3 | 100 | |
| sahilmgandhi | 18:6a4db94011d3 | 101 | /* Chip enter idle mode after CPU run WFI instruction */ |
| sahilmgandhi | 18:6a4db94011d3 | 102 | __WFI(); |
| sahilmgandhi | 18:6a4db94011d3 | 103 | } |
| sahilmgandhi | 18:6a4db94011d3 | 104 | |
| sahilmgandhi | 18:6a4db94011d3 | 105 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 106 | * @brief Get external high speed crystal clock frequency |
| sahilmgandhi | 18:6a4db94011d3 | 107 | * @param None |
| sahilmgandhi | 18:6a4db94011d3 | 108 | * @return External high frequency crystal frequency |
| sahilmgandhi | 18:6a4db94011d3 | 109 | * @details This function get external high frequency crystal frequency. The frequency unit is Hz. |
| sahilmgandhi | 18:6a4db94011d3 | 110 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 111 | uint32_t CLK_GetHXTFreq(void) |
| sahilmgandhi | 18:6a4db94011d3 | 112 | { |
| sahilmgandhi | 18:6a4db94011d3 | 113 | if(CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) |
| sahilmgandhi | 18:6a4db94011d3 | 114 | return __HXT; |
| sahilmgandhi | 18:6a4db94011d3 | 115 | else |
| sahilmgandhi | 18:6a4db94011d3 | 116 | return 0; |
| sahilmgandhi | 18:6a4db94011d3 | 117 | } |
| sahilmgandhi | 18:6a4db94011d3 | 118 | |
| sahilmgandhi | 18:6a4db94011d3 | 119 | |
| sahilmgandhi | 18:6a4db94011d3 | 120 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 121 | * @brief Get external low speed crystal clock frequency |
| sahilmgandhi | 18:6a4db94011d3 | 122 | * @param None |
| sahilmgandhi | 18:6a4db94011d3 | 123 | * @return External low speed crystal clock frequency |
| sahilmgandhi | 18:6a4db94011d3 | 124 | * @details This function get external low frequency crystal frequency. The frequency unit is Hz. |
| sahilmgandhi | 18:6a4db94011d3 | 125 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 126 | uint32_t CLK_GetLXTFreq(void) |
| sahilmgandhi | 18:6a4db94011d3 | 127 | { |
| sahilmgandhi | 18:6a4db94011d3 | 128 | if(CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk) |
| sahilmgandhi | 18:6a4db94011d3 | 129 | return __LXT; |
| sahilmgandhi | 18:6a4db94011d3 | 130 | else |
| sahilmgandhi | 18:6a4db94011d3 | 131 | return 0; |
| sahilmgandhi | 18:6a4db94011d3 | 132 | } |
| sahilmgandhi | 18:6a4db94011d3 | 133 | |
| sahilmgandhi | 18:6a4db94011d3 | 134 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 135 | * @brief Get PCLK0 frequency |
| sahilmgandhi | 18:6a4db94011d3 | 136 | * @param None |
| sahilmgandhi | 18:6a4db94011d3 | 137 | * @return PCLK0 frequency |
| sahilmgandhi | 18:6a4db94011d3 | 138 | * @details This function get PCLK0 frequency. The frequency unit is Hz. |
| sahilmgandhi | 18:6a4db94011d3 | 139 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 140 | uint32_t CLK_GetPCLK0Freq(void) |
| sahilmgandhi | 18:6a4db94011d3 | 141 | { |
| sahilmgandhi | 18:6a4db94011d3 | 142 | SystemCoreClockUpdate(); |
| sahilmgandhi | 18:6a4db94011d3 | 143 | if(CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) |
| sahilmgandhi | 18:6a4db94011d3 | 144 | return SystemCoreClock / 2; |
| sahilmgandhi | 18:6a4db94011d3 | 145 | else |
| sahilmgandhi | 18:6a4db94011d3 | 146 | return SystemCoreClock; |
| sahilmgandhi | 18:6a4db94011d3 | 147 | } |
| sahilmgandhi | 18:6a4db94011d3 | 148 | |
| sahilmgandhi | 18:6a4db94011d3 | 149 | |
| sahilmgandhi | 18:6a4db94011d3 | 150 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 151 | * @brief Get PCLK1 frequency |
| sahilmgandhi | 18:6a4db94011d3 | 152 | * @param None |
| sahilmgandhi | 18:6a4db94011d3 | 153 | * @return PCLK1 frequency |
| sahilmgandhi | 18:6a4db94011d3 | 154 | * @details This function get PCLK1 frequency. The frequency unit is Hz. |
| sahilmgandhi | 18:6a4db94011d3 | 155 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 156 | uint32_t CLK_GetPCLK1Freq(void) |
| sahilmgandhi | 18:6a4db94011d3 | 157 | { |
| sahilmgandhi | 18:6a4db94011d3 | 158 | SystemCoreClockUpdate(); |
| sahilmgandhi | 18:6a4db94011d3 | 159 | if(CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) |
| sahilmgandhi | 18:6a4db94011d3 | 160 | return SystemCoreClock / 2; |
| sahilmgandhi | 18:6a4db94011d3 | 161 | else |
| sahilmgandhi | 18:6a4db94011d3 | 162 | return SystemCoreClock; |
| sahilmgandhi | 18:6a4db94011d3 | 163 | } |
| sahilmgandhi | 18:6a4db94011d3 | 164 | |
| sahilmgandhi | 18:6a4db94011d3 | 165 | |
| sahilmgandhi | 18:6a4db94011d3 | 166 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 167 | * @brief Get HCLK frequency |
| sahilmgandhi | 18:6a4db94011d3 | 168 | * @param None |
| sahilmgandhi | 18:6a4db94011d3 | 169 | * @return HCLK frequency |
| sahilmgandhi | 18:6a4db94011d3 | 170 | * @details This function get HCLK frequency. The frequency unit is Hz. |
| sahilmgandhi | 18:6a4db94011d3 | 171 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 172 | uint32_t CLK_GetHCLKFreq(void) |
| sahilmgandhi | 18:6a4db94011d3 | 173 | { |
| sahilmgandhi | 18:6a4db94011d3 | 174 | SystemCoreClockUpdate(); |
| sahilmgandhi | 18:6a4db94011d3 | 175 | return SystemCoreClock; |
| sahilmgandhi | 18:6a4db94011d3 | 176 | } |
| sahilmgandhi | 18:6a4db94011d3 | 177 | |
| sahilmgandhi | 18:6a4db94011d3 | 178 | |
| sahilmgandhi | 18:6a4db94011d3 | 179 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 180 | * @brief Get CPU frequency |
| sahilmgandhi | 18:6a4db94011d3 | 181 | * @param None |
| sahilmgandhi | 18:6a4db94011d3 | 182 | * @return CPU frequency |
| sahilmgandhi | 18:6a4db94011d3 | 183 | * @details This function get CPU frequency. The frequency unit is Hz. |
| sahilmgandhi | 18:6a4db94011d3 | 184 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 185 | uint32_t CLK_GetCPUFreq(void) |
| sahilmgandhi | 18:6a4db94011d3 | 186 | { |
| sahilmgandhi | 18:6a4db94011d3 | 187 | SystemCoreClockUpdate(); |
| sahilmgandhi | 18:6a4db94011d3 | 188 | return SystemCoreClock; |
| sahilmgandhi | 18:6a4db94011d3 | 189 | } |
| sahilmgandhi | 18:6a4db94011d3 | 190 | |
| sahilmgandhi | 18:6a4db94011d3 | 191 | |
| sahilmgandhi | 18:6a4db94011d3 | 192 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 193 | * @brief Set HCLK frequency |
| sahilmgandhi | 18:6a4db94011d3 | 194 | * @param[in] u32Hclk is HCLK frequency. The range of u32Hclk is 25 MHz ~ 72 MHz. |
| sahilmgandhi | 18:6a4db94011d3 | 195 | * @return HCLK frequency |
| sahilmgandhi | 18:6a4db94011d3 | 196 | * @details This function is used to set HCLK frequency. The frequency unit is Hz. \n |
| sahilmgandhi | 18:6a4db94011d3 | 197 | * It would configure PLL frequency to 50MHz ~ 144MHz, |
| sahilmgandhi | 18:6a4db94011d3 | 198 | * set HCLK clock divider as 2 and switch HCLK clock source to PLL. \n |
| sahilmgandhi | 18:6a4db94011d3 | 199 | * The register write-protection function should be disabled before using this function. |
| sahilmgandhi | 18:6a4db94011d3 | 200 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 201 | uint32_t CLK_SetCoreClock(uint32_t u32Hclk) |
| sahilmgandhi | 18:6a4db94011d3 | 202 | { |
| sahilmgandhi | 18:6a4db94011d3 | 203 | uint32_t u32HIRCSTB; |
| sahilmgandhi | 18:6a4db94011d3 | 204 | |
| sahilmgandhi | 18:6a4db94011d3 | 205 | /* Read HIRC clock source stable flag */ |
| sahilmgandhi | 18:6a4db94011d3 | 206 | u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk; |
| sahilmgandhi | 18:6a4db94011d3 | 207 | |
| sahilmgandhi | 18:6a4db94011d3 | 208 | /* The range of u32Hclk is 25 MHz ~ 72 MHz */ |
| sahilmgandhi | 18:6a4db94011d3 | 209 | if(u32Hclk > FREQ_72MHZ) |
| sahilmgandhi | 18:6a4db94011d3 | 210 | u32Hclk = FREQ_72MHZ; |
| sahilmgandhi | 18:6a4db94011d3 | 211 | if(u32Hclk < FREQ_25MHZ) |
| sahilmgandhi | 18:6a4db94011d3 | 212 | u32Hclk = FREQ_25MHZ; |
| sahilmgandhi | 18:6a4db94011d3 | 213 | |
| sahilmgandhi | 18:6a4db94011d3 | 214 | /* Switch HCLK clock source to HIRC clock for safe */ |
| sahilmgandhi | 18:6a4db94011d3 | 215 | CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; |
| sahilmgandhi | 18:6a4db94011d3 | 216 | CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); |
| sahilmgandhi | 18:6a4db94011d3 | 217 | CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk; |
| sahilmgandhi | 18:6a4db94011d3 | 218 | CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk); |
| sahilmgandhi | 18:6a4db94011d3 | 219 | |
| sahilmgandhi | 18:6a4db94011d3 | 220 | /* Configure PLL setting if HXT clock is enabled */ |
| sahilmgandhi | 18:6a4db94011d3 | 221 | if(CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) |
| sahilmgandhi | 18:6a4db94011d3 | 222 | u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HXT, (u32Hclk << 1)); |
| sahilmgandhi | 18:6a4db94011d3 | 223 | |
| sahilmgandhi | 18:6a4db94011d3 | 224 | /* Configure PLL setting if HXT clock is not enabled */ |
| sahilmgandhi | 18:6a4db94011d3 | 225 | else |
| sahilmgandhi | 18:6a4db94011d3 | 226 | { |
| sahilmgandhi | 18:6a4db94011d3 | 227 | u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HIRC, (u32Hclk << 1)); |
| sahilmgandhi | 18:6a4db94011d3 | 228 | |
| sahilmgandhi | 18:6a4db94011d3 | 229 | /* Read HIRC clock source stable flag */ |
| sahilmgandhi | 18:6a4db94011d3 | 230 | u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk; |
| sahilmgandhi | 18:6a4db94011d3 | 231 | } |
| sahilmgandhi | 18:6a4db94011d3 | 232 | |
| sahilmgandhi | 18:6a4db94011d3 | 233 | /* Select HCLK clock source to PLL, |
| sahilmgandhi | 18:6a4db94011d3 | 234 | Select HCLK clock source divider as 2 |
| sahilmgandhi | 18:6a4db94011d3 | 235 | and update system core clock |
| sahilmgandhi | 18:6a4db94011d3 | 236 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 237 | CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(2)); |
| sahilmgandhi | 18:6a4db94011d3 | 238 | |
| sahilmgandhi | 18:6a4db94011d3 | 239 | /* Disable HIRC if HIRC is disabled before setting core clock */ |
| sahilmgandhi | 18:6a4db94011d3 | 240 | if(u32HIRCSTB == 0) |
| sahilmgandhi | 18:6a4db94011d3 | 241 | CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk; |
| sahilmgandhi | 18:6a4db94011d3 | 242 | |
| sahilmgandhi | 18:6a4db94011d3 | 243 | /* Return actually HCLK frequency is PLL frequency divide 2 */ |
| sahilmgandhi | 18:6a4db94011d3 | 244 | return u32Hclk >> 1; |
| sahilmgandhi | 18:6a4db94011d3 | 245 | } |
| sahilmgandhi | 18:6a4db94011d3 | 246 | |
| sahilmgandhi | 18:6a4db94011d3 | 247 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 248 | * @brief This function set HCLK clock source and HCLK clock divider |
| sahilmgandhi | 18:6a4db94011d3 | 249 | * @param[in] u32ClkSrc is HCLK clock source. Including : |
| sahilmgandhi | 18:6a4db94011d3 | 250 | * - \ref CLK_CLKSEL0_HCLKSEL_HXT |
| sahilmgandhi | 18:6a4db94011d3 | 251 | * - \ref CLK_CLKSEL0_HCLKSEL_LXT |
| sahilmgandhi | 18:6a4db94011d3 | 252 | * - \ref CLK_CLKSEL0_HCLKSEL_PLL |
| sahilmgandhi | 18:6a4db94011d3 | 253 | * - \ref CLK_CLKSEL0_HCLKSEL_LIRC |
| sahilmgandhi | 18:6a4db94011d3 | 254 | * - \ref CLK_CLKSEL0_HCLKSEL_HIRC |
| sahilmgandhi | 18:6a4db94011d3 | 255 | * @param[in] u32ClkDiv is HCLK clock divider. Including : |
| sahilmgandhi | 18:6a4db94011d3 | 256 | * - \ref CLK_CLKDIV0_HCLK(x) |
| sahilmgandhi | 18:6a4db94011d3 | 257 | * @return None |
| sahilmgandhi | 18:6a4db94011d3 | 258 | * @details This function set HCLK clock source and HCLK clock divider. \n |
| sahilmgandhi | 18:6a4db94011d3 | 259 | * The register write-protection function should be disabled before using this function. |
| sahilmgandhi | 18:6a4db94011d3 | 260 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 261 | void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv) |
| sahilmgandhi | 18:6a4db94011d3 | 262 | { |
| sahilmgandhi | 18:6a4db94011d3 | 263 | uint32_t u32HIRCSTB; |
| sahilmgandhi | 18:6a4db94011d3 | 264 | |
| sahilmgandhi | 18:6a4db94011d3 | 265 | /* Read HIRC clock source stable flag */ |
| sahilmgandhi | 18:6a4db94011d3 | 266 | u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk; |
| sahilmgandhi | 18:6a4db94011d3 | 267 | |
| sahilmgandhi | 18:6a4db94011d3 | 268 | /* Switch to HIRC for Safe. Avoid HCLK too high when applying new divider. */ |
| sahilmgandhi | 18:6a4db94011d3 | 269 | CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; |
| sahilmgandhi | 18:6a4db94011d3 | 270 | CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); |
| sahilmgandhi | 18:6a4db94011d3 | 271 | CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | CLK_CLKSEL0_HCLKSEL_HIRC; |
| sahilmgandhi | 18:6a4db94011d3 | 272 | |
| sahilmgandhi | 18:6a4db94011d3 | 273 | /* Apply new Divider */ |
| sahilmgandhi | 18:6a4db94011d3 | 274 | CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv; |
| sahilmgandhi | 18:6a4db94011d3 | 275 | |
| sahilmgandhi | 18:6a4db94011d3 | 276 | /* Switch HCLK to new HCLK source */ |
| sahilmgandhi | 18:6a4db94011d3 | 277 | CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc; |
| sahilmgandhi | 18:6a4db94011d3 | 278 | |
| sahilmgandhi | 18:6a4db94011d3 | 279 | /* Update System Core Clock */ |
| sahilmgandhi | 18:6a4db94011d3 | 280 | SystemCoreClockUpdate(); |
| sahilmgandhi | 18:6a4db94011d3 | 281 | |
| sahilmgandhi | 18:6a4db94011d3 | 282 | /* Disable HIRC if HIRC is disabled before switching HCLK source */ |
| sahilmgandhi | 18:6a4db94011d3 | 283 | if(u32HIRCSTB == 0) |
| sahilmgandhi | 18:6a4db94011d3 | 284 | CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk; |
| sahilmgandhi | 18:6a4db94011d3 | 285 | } |
| sahilmgandhi | 18:6a4db94011d3 | 286 | |
| sahilmgandhi | 18:6a4db94011d3 | 287 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 288 | * @brief This function set selected module clock source and module clock divider |
| sahilmgandhi | 18:6a4db94011d3 | 289 | * @param[in] u32ModuleIdx is module index. |
| sahilmgandhi | 18:6a4db94011d3 | 290 | * @param[in] u32ClkSrc is module clock source. |
| sahilmgandhi | 18:6a4db94011d3 | 291 | * @param[in] u32ClkDiv is module clock divider. |
| sahilmgandhi | 18:6a4db94011d3 | 292 | * @return None |
| sahilmgandhi | 18:6a4db94011d3 | 293 | * @details Valid parameter combinations listed in following table: |
| sahilmgandhi | 18:6a4db94011d3 | 294 | * |
| sahilmgandhi | 18:6a4db94011d3 | 295 | * |Module index |Clock source |Divider | |
| sahilmgandhi | 18:6a4db94011d3 | 296 | * | :---------------- | :----------------------------------- | :---------------------- | |
| sahilmgandhi | 18:6a4db94011d3 | 297 | * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LXT | x | |
| sahilmgandhi | 18:6a4db94011d3 | 298 | * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_PCLK0_DIV2048 | x | |
| sahilmgandhi | 18:6a4db94011d3 | 299 | * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LIRC | x | |
| sahilmgandhi | 18:6a4db94011d3 | 300 | * |\ref RTC_MODULE |\ref CLK_CLKSEL3_RTCSEL_LXT | x | |
| sahilmgandhi | 18:6a4db94011d3 | 301 | * |\ref RTC_MODULE |\ref CLK_CLKSEL3_RTCSEL_LIRC | x | |
| sahilmgandhi | 18:6a4db94011d3 | 302 | * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HXT | x | |
| sahilmgandhi | 18:6a4db94011d3 | 303 | * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LXT | x | |
| sahilmgandhi | 18:6a4db94011d3 | 304 | * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_PCLK0 | x | |
| sahilmgandhi | 18:6a4db94011d3 | 305 | * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_EXT_TRG | x | |
| sahilmgandhi | 18:6a4db94011d3 | 306 | * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LIRC | x | |
| sahilmgandhi | 18:6a4db94011d3 | 307 | * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HIRC | x | |
| sahilmgandhi | 18:6a4db94011d3 | 308 | * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HXT | x | |
| sahilmgandhi | 18:6a4db94011d3 | 309 | * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LXT | x | |
| sahilmgandhi | 18:6a4db94011d3 | 310 | * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_PCLK0 | x | |
| sahilmgandhi | 18:6a4db94011d3 | 311 | * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_EXT_TRG | x | |
| sahilmgandhi | 18:6a4db94011d3 | 312 | * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LIRC | x | |
| sahilmgandhi | 18:6a4db94011d3 | 313 | * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HIRC | x | |
| sahilmgandhi | 18:6a4db94011d3 | 314 | * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HXT | x | |
| sahilmgandhi | 18:6a4db94011d3 | 315 | * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LXT | x | |
| sahilmgandhi | 18:6a4db94011d3 | 316 | * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_PCLK1 | x | |
| sahilmgandhi | 18:6a4db94011d3 | 317 | * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_EXT_TRG | x | |
| sahilmgandhi | 18:6a4db94011d3 | 318 | * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LIRC | x | |
| sahilmgandhi | 18:6a4db94011d3 | 319 | * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HIRC | x | |
| sahilmgandhi | 18:6a4db94011d3 | 320 | * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HXT | x | |
| sahilmgandhi | 18:6a4db94011d3 | 321 | * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LXT | x | |
| sahilmgandhi | 18:6a4db94011d3 | 322 | * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_PCLK1 | x | |
| sahilmgandhi | 18:6a4db94011d3 | 323 | * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_EXT_TRG | x | |
| sahilmgandhi | 18:6a4db94011d3 | 324 | * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LIRC | x | |
| sahilmgandhi | 18:6a4db94011d3 | 325 | * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HIRC | x | |
| sahilmgandhi | 18:6a4db94011d3 | 326 | * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HXT | x | |
| sahilmgandhi | 18:6a4db94011d3 | 327 | * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_LXT | x | |
| sahilmgandhi | 18:6a4db94011d3 | 328 | * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HCLK | x | |
| sahilmgandhi | 18:6a4db94011d3 | 329 | * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HIRC | x | |
| sahilmgandhi | 18:6a4db94011d3 | 330 | * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HXT | x | |
| sahilmgandhi | 18:6a4db94011d3 | 331 | * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PLL | x | |
| sahilmgandhi | 18:6a4db94011d3 | 332 | * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PCLK0 | x | |
| sahilmgandhi | 18:6a4db94011d3 | 333 | * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HIRC | x | |
| sahilmgandhi | 18:6a4db94011d3 | 334 | * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HXT | x | |
| sahilmgandhi | 18:6a4db94011d3 | 335 | * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PLL | x | |
| sahilmgandhi | 18:6a4db94011d3 | 336 | * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PCLK1 | x | |
| sahilmgandhi | 18:6a4db94011d3 | 337 | * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HIRC | x | |
| sahilmgandhi | 18:6a4db94011d3 | 338 | * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HXT | x | |
| sahilmgandhi | 18:6a4db94011d3 | 339 | * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PLL | x | |
| sahilmgandhi | 18:6a4db94011d3 | 340 | * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PCLK0 | x | |
| sahilmgandhi | 18:6a4db94011d3 | 341 | * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HIRC | x | |
| sahilmgandhi | 18:6a4db94011d3 | 342 | * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) | |
| sahilmgandhi | 18:6a4db94011d3 | 343 | * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) | |
| sahilmgandhi | 18:6a4db94011d3 | 344 | * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_LXT |\ref CLK_CLKDIV0_UART(x) | |
| sahilmgandhi | 18:6a4db94011d3 | 345 | * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) | |
| sahilmgandhi | 18:6a4db94011d3 | 346 | * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) | |
| sahilmgandhi | 18:6a4db94011d3 | 347 | * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) | |
| sahilmgandhi | 18:6a4db94011d3 | 348 | * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_LXT |\ref CLK_CLKDIV0_UART(x) | |
| sahilmgandhi | 18:6a4db94011d3 | 349 | * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) | |
| sahilmgandhi | 18:6a4db94011d3 | 350 | * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) | |
| sahilmgandhi | 18:6a4db94011d3 | 351 | * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) | |
| sahilmgandhi | 18:6a4db94011d3 | 352 | * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_LXT |\ref CLK_CLKDIV0_UART(x) | |
| sahilmgandhi | 18:6a4db94011d3 | 353 | * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) | |
| sahilmgandhi | 18:6a4db94011d3 | 354 | * |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) | |
| sahilmgandhi | 18:6a4db94011d3 | 355 | * |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_LXT |\ref CLK_CLKDIV0_UART(x) | |
| sahilmgandhi | 18:6a4db94011d3 | 356 | * |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) | |
| sahilmgandhi | 18:6a4db94011d3 | 357 | * |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) | |
| sahilmgandhi | 18:6a4db94011d3 | 358 | * |\ref USBH_MODULE | x |\ref CLK_CLKDIV0_USB(x) | |
| sahilmgandhi | 18:6a4db94011d3 | 359 | * |\ref USBD_MODULE | x |\ref CLK_CLKDIV0_USB(x) | |
| sahilmgandhi | 18:6a4db94011d3 | 360 | * |\ref OTG_MODULE | x |\ref CLK_CLKDIV0_USB(x) | |
| sahilmgandhi | 18:6a4db94011d3 | 361 | * |\ref EADC_MODULE | x |\ref CLK_CLKDIV0_EADC(x) | |
| sahilmgandhi | 18:6a4db94011d3 | 362 | * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HXT |\ref CLK_CLKDIV1_SC0(x) | |
| sahilmgandhi | 18:6a4db94011d3 | 363 | * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PLL |\ref CLK_CLKDIV1_SC0(x) | |
| sahilmgandhi | 18:6a4db94011d3 | 364 | * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PCLK0 |\ref CLK_CLKDIV1_SC0(x) | |
| sahilmgandhi | 18:6a4db94011d3 | 365 | * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HIRC |\ref CLK_CLKDIV1_SC0(x) | |
| sahilmgandhi | 18:6a4db94011d3 | 366 | * |\ref PWM0_MODULE |\ref CLK_CLKSEL2_PWM0SEL_PLL | x | |
| sahilmgandhi | 18:6a4db94011d3 | 367 | * |\ref PWM0_MODULE |\ref CLK_CLKSEL2_PWM0SEL_PCLK0 | x | |
| sahilmgandhi | 18:6a4db94011d3 | 368 | * |\ref PWM1_MODULE |\ref CLK_CLKSEL2_PWM1SEL_PLL | x | |
| sahilmgandhi | 18:6a4db94011d3 | 369 | * |\ref PWM1_MODULE |\ref CLK_CLKSEL2_PWM1SEL_PCLK1 | x | |
| sahilmgandhi | 18:6a4db94011d3 | 370 | * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_PCLK0_DIV2048 | x | |
| sahilmgandhi | 18:6a4db94011d3 | 371 | * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_LIRC | x | |
| sahilmgandhi | 18:6a4db94011d3 | 372 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 373 | void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv) |
| sahilmgandhi | 18:6a4db94011d3 | 374 | { |
| sahilmgandhi | 18:6a4db94011d3 | 375 | uint32_t u32sel = 0, u32div = 0; |
| sahilmgandhi | 18:6a4db94011d3 | 376 | |
| sahilmgandhi | 18:6a4db94011d3 | 377 | if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk) |
| sahilmgandhi | 18:6a4db94011d3 | 378 | { |
| sahilmgandhi | 18:6a4db94011d3 | 379 | /* Get clock divider control register address */ |
| sahilmgandhi | 18:6a4db94011d3 | 380 | u32div = (uint32_t)&CLK->CLKDIV0 + ((MODULE_CLKDIV(u32ModuleIdx)) * 4); |
| sahilmgandhi | 18:6a4db94011d3 | 381 | /* Apply new divider */ |
| sahilmgandhi | 18:6a4db94011d3 | 382 | M32(u32div) = (M32(u32div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv; |
| sahilmgandhi | 18:6a4db94011d3 | 383 | } |
| sahilmgandhi | 18:6a4db94011d3 | 384 | |
| sahilmgandhi | 18:6a4db94011d3 | 385 | if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk) |
| sahilmgandhi | 18:6a4db94011d3 | 386 | { |
| sahilmgandhi | 18:6a4db94011d3 | 387 | /* Get clock select control register address */ |
| sahilmgandhi | 18:6a4db94011d3 | 388 | u32sel = (uint32_t)&CLK->CLKSEL0 + ((MODULE_CLKSEL(u32ModuleIdx)) * 4); |
| sahilmgandhi | 18:6a4db94011d3 | 389 | /* Set new clock selection setting */ |
| sahilmgandhi | 18:6a4db94011d3 | 390 | M32(u32sel) = (M32(u32sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc; |
| sahilmgandhi | 18:6a4db94011d3 | 391 | } |
| sahilmgandhi | 18:6a4db94011d3 | 392 | } |
| sahilmgandhi | 18:6a4db94011d3 | 393 | |
| sahilmgandhi | 18:6a4db94011d3 | 394 | |
| sahilmgandhi | 18:6a4db94011d3 | 395 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 396 | * @brief Set SysTick clock source |
| sahilmgandhi | 18:6a4db94011d3 | 397 | * @param[in] u32ClkSrc is module clock source. Including: |
| sahilmgandhi | 18:6a4db94011d3 | 398 | * - \ref CLK_CLKSEL0_STCLKSEL_HXT |
| sahilmgandhi | 18:6a4db94011d3 | 399 | * - \ref CLK_CLKSEL0_STCLKSEL_LXT |
| sahilmgandhi | 18:6a4db94011d3 | 400 | * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2 |
| sahilmgandhi | 18:6a4db94011d3 | 401 | * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 |
| sahilmgandhi | 18:6a4db94011d3 | 402 | * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 |
| sahilmgandhi | 18:6a4db94011d3 | 403 | * @return None |
| sahilmgandhi | 18:6a4db94011d3 | 404 | * @details This function set SysTick clock source. \n |
| sahilmgandhi | 18:6a4db94011d3 | 405 | * The register write-protection function should be disabled before using this function. |
| sahilmgandhi | 18:6a4db94011d3 | 406 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 407 | void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc) |
| sahilmgandhi | 18:6a4db94011d3 | 408 | { |
| sahilmgandhi | 18:6a4db94011d3 | 409 | CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc; |
| sahilmgandhi | 18:6a4db94011d3 | 410 | |
| sahilmgandhi | 18:6a4db94011d3 | 411 | } |
| sahilmgandhi | 18:6a4db94011d3 | 412 | |
| sahilmgandhi | 18:6a4db94011d3 | 413 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 414 | * @brief Enable clock source |
| sahilmgandhi | 18:6a4db94011d3 | 415 | * @param[in] u32ClkMask is clock source mask. Including : |
| sahilmgandhi | 18:6a4db94011d3 | 416 | * - \ref CLK_PWRCTL_HXTEN_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 417 | * - \ref CLK_PWRCTL_LXTEN_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 418 | * - \ref CLK_PWRCTL_HIRCEN_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 419 | * - \ref CLK_PWRCTL_LIRCEN_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 420 | * @return None |
| sahilmgandhi | 18:6a4db94011d3 | 421 | * @details This function enable clock source. \n |
| sahilmgandhi | 18:6a4db94011d3 | 422 | * The register write-protection function should be disabled before using this function. |
| sahilmgandhi | 18:6a4db94011d3 | 423 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 424 | void CLK_EnableXtalRC(uint32_t u32ClkMask) |
| sahilmgandhi | 18:6a4db94011d3 | 425 | { |
| sahilmgandhi | 18:6a4db94011d3 | 426 | CLK->PWRCTL |= u32ClkMask; |
| sahilmgandhi | 18:6a4db94011d3 | 427 | } |
| sahilmgandhi | 18:6a4db94011d3 | 428 | |
| sahilmgandhi | 18:6a4db94011d3 | 429 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 430 | * @brief Disable clock source |
| sahilmgandhi | 18:6a4db94011d3 | 431 | * @param[in] u32ClkMask is clock source mask. Including : |
| sahilmgandhi | 18:6a4db94011d3 | 432 | * - \ref CLK_PWRCTL_HXTEN_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 433 | * - \ref CLK_PWRCTL_LXTEN_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 434 | * - \ref CLK_PWRCTL_HIRCEN_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 435 | * - \ref CLK_PWRCTL_LIRCEN_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 436 | * @return None |
| sahilmgandhi | 18:6a4db94011d3 | 437 | * @details This function disable clock source. \n |
| sahilmgandhi | 18:6a4db94011d3 | 438 | * The register write-protection function should be disabled before using this function. |
| sahilmgandhi | 18:6a4db94011d3 | 439 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 440 | void CLK_DisableXtalRC(uint32_t u32ClkMask) |
| sahilmgandhi | 18:6a4db94011d3 | 441 | { |
| sahilmgandhi | 18:6a4db94011d3 | 442 | CLK->PWRCTL &= ~u32ClkMask; |
| sahilmgandhi | 18:6a4db94011d3 | 443 | } |
| sahilmgandhi | 18:6a4db94011d3 | 444 | |
| sahilmgandhi | 18:6a4db94011d3 | 445 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 446 | * @brief Enable module clock |
| sahilmgandhi | 18:6a4db94011d3 | 447 | * @param[in] u32ModuleIdx is module index. Including : |
| sahilmgandhi | 18:6a4db94011d3 | 448 | * - \ref PDMA_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 449 | * - \ref ISP_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 450 | * - \ref EBI_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 451 | * - \ref USBH_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 452 | * - \ref CRC_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 453 | * - \ref WDT_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 454 | * - \ref WWDT_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 455 | * - \ref RTC_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 456 | * - \ref TMR0_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 457 | * - \ref TMR1_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 458 | * - \ref TMR2_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 459 | * - \ref TMR3_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 460 | * - \ref CLKO_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 461 | * - \ref ACMP01_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 462 | * - \ref I2C0_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 463 | * - \ref I2C1_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 464 | * - \ref SPI0_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 465 | * - \ref SPI1_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 466 | * - \ref SPI2_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 467 | * - \ref UART0_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 468 | * - \ref UART1_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 469 | * - \ref UART2_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 470 | * - \ref UART3_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 471 | * - \ref CAN0_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 472 | * - \ref OTG_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 473 | * - \ref USBD_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 474 | * - \ref EADC_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 475 | * - \ref SC0_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 476 | * - \ref DAC_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 477 | * - \ref PWM0_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 478 | * - \ref PWM1_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 479 | * - \ref TK_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 480 | * @return None |
| sahilmgandhi | 18:6a4db94011d3 | 481 | * @details This function is used to enable module clock. |
| sahilmgandhi | 18:6a4db94011d3 | 482 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 483 | void CLK_EnableModuleClock(uint32_t u32ModuleIdx) |
| sahilmgandhi | 18:6a4db94011d3 | 484 | { |
| sahilmgandhi | 18:6a4db94011d3 | 485 | *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK + (MODULE_APBCLK(u32ModuleIdx) * 4)) |= 1 << MODULE_IP_EN_Pos(u32ModuleIdx); |
| sahilmgandhi | 18:6a4db94011d3 | 486 | } |
| sahilmgandhi | 18:6a4db94011d3 | 487 | |
| sahilmgandhi | 18:6a4db94011d3 | 488 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 489 | * @brief Disable module clock |
| sahilmgandhi | 18:6a4db94011d3 | 490 | * @param[in] u32ModuleIdx is module index. Including : |
| sahilmgandhi | 18:6a4db94011d3 | 491 | * - \ref PDMA_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 492 | * - \ref ISP_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 493 | * - \ref EBI_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 494 | * - \ref USBH_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 495 | * - \ref CRC_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 496 | * - \ref WDT_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 497 | * - \ref WWDT_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 498 | * - \ref RTC_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 499 | * - \ref TMR0_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 500 | * - \ref TMR1_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 501 | * - \ref TMR2_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 502 | * - \ref TMR3_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 503 | * - \ref CLKO_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 504 | * - \ref ACMP01_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 505 | * - \ref I2C0_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 506 | * - \ref I2C1_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 507 | * - \ref SPI0_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 508 | * - \ref SPI1_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 509 | * - \ref SPI2_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 510 | * - \ref UART0_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 511 | * - \ref UART1_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 512 | * - \ref UART2_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 513 | * - \ref UART3_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 514 | * - \ref CAN0_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 515 | * - \ref OTG_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 516 | * - \ref USBD_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 517 | * - \ref EADC_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 518 | * - \ref SC0_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 519 | * - \ref DAC_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 520 | * - \ref PWM0_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 521 | * - \ref PWM1_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 522 | * - \ref TK_MODULE |
| sahilmgandhi | 18:6a4db94011d3 | 523 | * @return None |
| sahilmgandhi | 18:6a4db94011d3 | 524 | * @details This function is used to disable module clock. |
| sahilmgandhi | 18:6a4db94011d3 | 525 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 526 | void CLK_DisableModuleClock(uint32_t u32ModuleIdx) |
| sahilmgandhi | 18:6a4db94011d3 | 527 | { |
| sahilmgandhi | 18:6a4db94011d3 | 528 | *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK + (MODULE_APBCLK(u32ModuleIdx) * 4)) &= ~(1 << MODULE_IP_EN_Pos(u32ModuleIdx)); |
| sahilmgandhi | 18:6a4db94011d3 | 529 | } |
| sahilmgandhi | 18:6a4db94011d3 | 530 | |
| sahilmgandhi | 18:6a4db94011d3 | 531 | |
| sahilmgandhi | 18:6a4db94011d3 | 532 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 533 | * @brief Set PLL frequency |
| sahilmgandhi | 18:6a4db94011d3 | 534 | * @param[in] u32PllClkSrc is PLL clock source. Including : |
| sahilmgandhi | 18:6a4db94011d3 | 535 | * - \ref CLK_PLLCTL_PLLSRC_HXT |
| sahilmgandhi | 18:6a4db94011d3 | 536 | * - \ref CLK_PLLCTL_PLLSRC_HIRC |
| sahilmgandhi | 18:6a4db94011d3 | 537 | * @param[in] u32PllFreq is PLL frequency. |
| sahilmgandhi | 18:6a4db94011d3 | 538 | * @return PLL frequency |
| sahilmgandhi | 18:6a4db94011d3 | 539 | * @details This function is used to configure PLLCTL register to set specified PLL frequency. \n |
| sahilmgandhi | 18:6a4db94011d3 | 540 | * The register write-protection function should be disabled before using this function. |
| sahilmgandhi | 18:6a4db94011d3 | 541 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 542 | uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq) |
| sahilmgandhi | 18:6a4db94011d3 | 543 | { |
| sahilmgandhi | 18:6a4db94011d3 | 544 | uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32CLK_SRC; |
| sahilmgandhi | 18:6a4db94011d3 | 545 | uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR; |
| sahilmgandhi | 18:6a4db94011d3 | 546 | |
| sahilmgandhi | 18:6a4db94011d3 | 547 | /* Disable PLL first to avoid unstable when setting PLL */ |
| sahilmgandhi | 18:6a4db94011d3 | 548 | CLK_DisablePLL(); |
| sahilmgandhi | 18:6a4db94011d3 | 549 | |
| sahilmgandhi | 18:6a4db94011d3 | 550 | /* PLL source clock is from HXT */ |
| sahilmgandhi | 18:6a4db94011d3 | 551 | if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) |
| sahilmgandhi | 18:6a4db94011d3 | 552 | { |
| sahilmgandhi | 18:6a4db94011d3 | 553 | /* Enable HXT clock */ |
| sahilmgandhi | 18:6a4db94011d3 | 554 | CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk; |
| sahilmgandhi | 18:6a4db94011d3 | 555 | |
| sahilmgandhi | 18:6a4db94011d3 | 556 | /* Wait for HXT clock ready */ |
| sahilmgandhi | 18:6a4db94011d3 | 557 | CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); |
| sahilmgandhi | 18:6a4db94011d3 | 558 | |
| sahilmgandhi | 18:6a4db94011d3 | 559 | /* Select PLL source clock from HXT */ |
| sahilmgandhi | 18:6a4db94011d3 | 560 | u32CLK_SRC = CLK_PLLCTL_PLLSRC_HXT; |
| sahilmgandhi | 18:6a4db94011d3 | 561 | u32PllSrcClk = __HXT; |
| sahilmgandhi | 18:6a4db94011d3 | 562 | |
| sahilmgandhi | 18:6a4db94011d3 | 563 | /* u32NR start from 2 */ |
| sahilmgandhi | 18:6a4db94011d3 | 564 | u32NR = 2; |
| sahilmgandhi | 18:6a4db94011d3 | 565 | } |
| sahilmgandhi | 18:6a4db94011d3 | 566 | |
| sahilmgandhi | 18:6a4db94011d3 | 567 | /* PLL source clock is from HIRC */ |
| sahilmgandhi | 18:6a4db94011d3 | 568 | else |
| sahilmgandhi | 18:6a4db94011d3 | 569 | { |
| sahilmgandhi | 18:6a4db94011d3 | 570 | /* Enable HIRC clock */ |
| sahilmgandhi | 18:6a4db94011d3 | 571 | CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; |
| sahilmgandhi | 18:6a4db94011d3 | 572 | |
| sahilmgandhi | 18:6a4db94011d3 | 573 | /* Wait for HIRC clock ready */ |
| sahilmgandhi | 18:6a4db94011d3 | 574 | CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); |
| sahilmgandhi | 18:6a4db94011d3 | 575 | |
| sahilmgandhi | 18:6a4db94011d3 | 576 | /* Select PLL source clock from HIRC */ |
| sahilmgandhi | 18:6a4db94011d3 | 577 | u32CLK_SRC = CLK_PLLCTL_PLLSRC_HIRC; |
| sahilmgandhi | 18:6a4db94011d3 | 578 | u32PllSrcClk = __HIRC; |
| sahilmgandhi | 18:6a4db94011d3 | 579 | |
| sahilmgandhi | 18:6a4db94011d3 | 580 | /* u32NR start from 4 when FIN = 22.1184MHz to avoid calculation overflow */ |
| sahilmgandhi | 18:6a4db94011d3 | 581 | u32NR = 4; |
| sahilmgandhi | 18:6a4db94011d3 | 582 | } |
| sahilmgandhi | 18:6a4db94011d3 | 583 | |
| sahilmgandhi | 18:6a4db94011d3 | 584 | /* Select "NO" according to request frequency */ |
| sahilmgandhi | 18:6a4db94011d3 | 585 | if((u32PllFreq <= FREQ_500MHZ) && (u32PllFreq > FREQ_250MHZ)) |
| sahilmgandhi | 18:6a4db94011d3 | 586 | { |
| sahilmgandhi | 18:6a4db94011d3 | 587 | u32NO = 0; |
| sahilmgandhi | 18:6a4db94011d3 | 588 | } |
| sahilmgandhi | 18:6a4db94011d3 | 589 | else if((u32PllFreq <= FREQ_250MHZ) && (u32PllFreq > FREQ_125MHZ)) |
| sahilmgandhi | 18:6a4db94011d3 | 590 | { |
| sahilmgandhi | 18:6a4db94011d3 | 591 | u32NO = 1; |
| sahilmgandhi | 18:6a4db94011d3 | 592 | u32PllFreq = u32PllFreq << 1; |
| sahilmgandhi | 18:6a4db94011d3 | 593 | } |
| sahilmgandhi | 18:6a4db94011d3 | 594 | else if((u32PllFreq <= FREQ_125MHZ) && (u32PllFreq >= FREQ_50MHZ)) |
| sahilmgandhi | 18:6a4db94011d3 | 595 | { |
| sahilmgandhi | 18:6a4db94011d3 | 596 | u32NO = 3; |
| sahilmgandhi | 18:6a4db94011d3 | 597 | u32PllFreq = u32PllFreq << 2; |
| sahilmgandhi | 18:6a4db94011d3 | 598 | } |
| sahilmgandhi | 18:6a4db94011d3 | 599 | else |
| sahilmgandhi | 18:6a4db94011d3 | 600 | { |
| sahilmgandhi | 18:6a4db94011d3 | 601 | /* Wrong frequency request. Just return default setting. */ |
| sahilmgandhi | 18:6a4db94011d3 | 602 | goto lexit; |
| sahilmgandhi | 18:6a4db94011d3 | 603 | } |
| sahilmgandhi | 18:6a4db94011d3 | 604 | |
| sahilmgandhi | 18:6a4db94011d3 | 605 | /* Find best solution */ |
| sahilmgandhi | 18:6a4db94011d3 | 606 | u32Min = (uint32_t) - 1; |
| sahilmgandhi | 18:6a4db94011d3 | 607 | u32MinNR = 0; |
| sahilmgandhi | 18:6a4db94011d3 | 608 | u32MinNF = 0; |
| sahilmgandhi | 18:6a4db94011d3 | 609 | for(; u32NR <= 33; u32NR++) |
| sahilmgandhi | 18:6a4db94011d3 | 610 | { |
| sahilmgandhi | 18:6a4db94011d3 | 611 | u32Tmp = u32PllSrcClk / u32NR; |
| sahilmgandhi | 18:6a4db94011d3 | 612 | if((u32Tmp > 1600000) && (u32Tmp < 16000000)) |
| sahilmgandhi | 18:6a4db94011d3 | 613 | { |
| sahilmgandhi | 18:6a4db94011d3 | 614 | for(u32NF = 2; u32NF <= 513; u32NF++) |
| sahilmgandhi | 18:6a4db94011d3 | 615 | { |
| sahilmgandhi | 18:6a4db94011d3 | 616 | u32Tmp2 = u32Tmp * u32NF; |
| sahilmgandhi | 18:6a4db94011d3 | 617 | if((u32Tmp2 >= 200000000) && (u32Tmp2 <= 500000000)) |
| sahilmgandhi | 18:6a4db94011d3 | 618 | { |
| sahilmgandhi | 18:6a4db94011d3 | 619 | u32Tmp3 = (u32Tmp2 > u32PllFreq) ? u32Tmp2 - u32PllFreq : u32PllFreq - u32Tmp2; |
| sahilmgandhi | 18:6a4db94011d3 | 620 | if(u32Tmp3 < u32Min) |
| sahilmgandhi | 18:6a4db94011d3 | 621 | { |
| sahilmgandhi | 18:6a4db94011d3 | 622 | u32Min = u32Tmp3; |
| sahilmgandhi | 18:6a4db94011d3 | 623 | u32MinNR = u32NR; |
| sahilmgandhi | 18:6a4db94011d3 | 624 | u32MinNF = u32NF; |
| sahilmgandhi | 18:6a4db94011d3 | 625 | |
| sahilmgandhi | 18:6a4db94011d3 | 626 | /* Break when get good results */ |
| sahilmgandhi | 18:6a4db94011d3 | 627 | if(u32Min == 0) |
| sahilmgandhi | 18:6a4db94011d3 | 628 | break; |
| sahilmgandhi | 18:6a4db94011d3 | 629 | } |
| sahilmgandhi | 18:6a4db94011d3 | 630 | } |
| sahilmgandhi | 18:6a4db94011d3 | 631 | } |
| sahilmgandhi | 18:6a4db94011d3 | 632 | } |
| sahilmgandhi | 18:6a4db94011d3 | 633 | } |
| sahilmgandhi | 18:6a4db94011d3 | 634 | |
| sahilmgandhi | 18:6a4db94011d3 | 635 | /* Enable and apply new PLL setting. */ |
| sahilmgandhi | 18:6a4db94011d3 | 636 | CLK->PLLCTL = u32CLK_SRC | (u32NO << 14) | ((u32MinNR - 2) << 9) | (u32MinNF - 2); |
| sahilmgandhi | 18:6a4db94011d3 | 637 | |
| sahilmgandhi | 18:6a4db94011d3 | 638 | /* Wait for PLL clock stable */ |
| sahilmgandhi | 18:6a4db94011d3 | 639 | CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); |
| sahilmgandhi | 18:6a4db94011d3 | 640 | |
| sahilmgandhi | 18:6a4db94011d3 | 641 | /* Return actual PLL output clock frequency */ |
| sahilmgandhi | 18:6a4db94011d3 | 642 | return u32PllSrcClk / ((u32NO + 1) * u32MinNR) * u32MinNF; |
| sahilmgandhi | 18:6a4db94011d3 | 643 | |
| sahilmgandhi | 18:6a4db94011d3 | 644 | lexit: |
| sahilmgandhi | 18:6a4db94011d3 | 645 | |
| sahilmgandhi | 18:6a4db94011d3 | 646 | /* Apply default PLL setting and return */ |
| sahilmgandhi | 18:6a4db94011d3 | 647 | if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) |
| sahilmgandhi | 18:6a4db94011d3 | 648 | CLK->PLLCTL = CLK_PLLCTL_72MHz_HXT; /* 72MHz */ |
| sahilmgandhi | 18:6a4db94011d3 | 649 | else |
| sahilmgandhi | 18:6a4db94011d3 | 650 | CLK->PLLCTL = CLK_PLLCTL_72MHz_HIRC; /* 71.8848MHz */ |
| sahilmgandhi | 18:6a4db94011d3 | 651 | |
| sahilmgandhi | 18:6a4db94011d3 | 652 | /* Wait for PLL clock stable */ |
| sahilmgandhi | 18:6a4db94011d3 | 653 | CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); |
| sahilmgandhi | 18:6a4db94011d3 | 654 | |
| sahilmgandhi | 18:6a4db94011d3 | 655 | return CLK_GetPLLClockFreq(); |
| sahilmgandhi | 18:6a4db94011d3 | 656 | |
| sahilmgandhi | 18:6a4db94011d3 | 657 | } |
| sahilmgandhi | 18:6a4db94011d3 | 658 | |
| sahilmgandhi | 18:6a4db94011d3 | 659 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 660 | * @brief Disable PLL |
| sahilmgandhi | 18:6a4db94011d3 | 661 | * @param None |
| sahilmgandhi | 18:6a4db94011d3 | 662 | * @return None |
| sahilmgandhi | 18:6a4db94011d3 | 663 | * @details This function set PLL in Power-down mode. \n |
| sahilmgandhi | 18:6a4db94011d3 | 664 | * The register write-protection function should be disabled before using this function. |
| sahilmgandhi | 18:6a4db94011d3 | 665 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 666 | void CLK_DisablePLL(void) |
| sahilmgandhi | 18:6a4db94011d3 | 667 | { |
| sahilmgandhi | 18:6a4db94011d3 | 668 | CLK->PLLCTL |= CLK_PLLCTL_PD_Msk; |
| sahilmgandhi | 18:6a4db94011d3 | 669 | } |
| sahilmgandhi | 18:6a4db94011d3 | 670 | |
| sahilmgandhi | 18:6a4db94011d3 | 671 | |
| sahilmgandhi | 18:6a4db94011d3 | 672 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 673 | * @brief This function check selected clock source status |
| sahilmgandhi | 18:6a4db94011d3 | 674 | * @param[in] u32ClkMask is selected clock source. Including : |
| sahilmgandhi | 18:6a4db94011d3 | 675 | * - \ref CLK_STATUS_HXTSTB_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 676 | * - \ref CLK_STATUS_LXTSTB_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 677 | * - \ref CLK_STATUS_HIRCSTB_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 678 | * - \ref CLK_STATUS_LIRCSTB_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 679 | * - \ref CLK_STATUS_PLLSTB_Msk |
| sahilmgandhi | 18:6a4db94011d3 | 680 | * @retval 0 clock is not stable |
| sahilmgandhi | 18:6a4db94011d3 | 681 | * @retval 1 clock is stable |
| sahilmgandhi | 18:6a4db94011d3 | 682 | * @details To wait for clock ready by specified clock source stable flag or timeout (~300ms) |
| sahilmgandhi | 18:6a4db94011d3 | 683 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 684 | uint32_t CLK_WaitClockReady(uint32_t u32ClkMask) |
| sahilmgandhi | 18:6a4db94011d3 | 685 | { |
| sahilmgandhi | 18:6a4db94011d3 | 686 | int32_t i32TimeOutCnt = 2160000; |
| sahilmgandhi | 18:6a4db94011d3 | 687 | |
| sahilmgandhi | 18:6a4db94011d3 | 688 | while((CLK->STATUS & u32ClkMask) != u32ClkMask) |
| sahilmgandhi | 18:6a4db94011d3 | 689 | { |
| sahilmgandhi | 18:6a4db94011d3 | 690 | if(i32TimeOutCnt-- <= 0) |
| sahilmgandhi | 18:6a4db94011d3 | 691 | return 0; |
| sahilmgandhi | 18:6a4db94011d3 | 692 | } |
| sahilmgandhi | 18:6a4db94011d3 | 693 | |
| sahilmgandhi | 18:6a4db94011d3 | 694 | return 1; |
| sahilmgandhi | 18:6a4db94011d3 | 695 | } |
| sahilmgandhi | 18:6a4db94011d3 | 696 | |
| sahilmgandhi | 18:6a4db94011d3 | 697 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 698 | * @brief Enable System Tick counter |
| sahilmgandhi | 18:6a4db94011d3 | 699 | * @param[in] u32ClkSrc is System Tick clock source. Including: |
| sahilmgandhi | 18:6a4db94011d3 | 700 | * - \ref CLK_CLKSEL0_STCLKSEL_HXT |
| sahilmgandhi | 18:6a4db94011d3 | 701 | * - \ref CLK_CLKSEL0_STCLKSEL_LXT |
| sahilmgandhi | 18:6a4db94011d3 | 702 | * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2 |
| sahilmgandhi | 18:6a4db94011d3 | 703 | * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 |
| sahilmgandhi | 18:6a4db94011d3 | 704 | * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 |
| sahilmgandhi | 18:6a4db94011d3 | 705 | * - \ref CLK_CLKSEL0_STCLKSEL_HCLK |
| sahilmgandhi | 18:6a4db94011d3 | 706 | * @param[in] u32Count is System Tick reload value. It could be 0~0xFFFFFF. |
| sahilmgandhi | 18:6a4db94011d3 | 707 | * @return None |
| sahilmgandhi | 18:6a4db94011d3 | 708 | * @details This function set System Tick clock source, reload value, enable System Tick counter and interrupt. \n |
| sahilmgandhi | 18:6a4db94011d3 | 709 | * The register write-protection function should be disabled before using this function. |
| sahilmgandhi | 18:6a4db94011d3 | 710 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 711 | void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count) |
| sahilmgandhi | 18:6a4db94011d3 | 712 | { |
| sahilmgandhi | 18:6a4db94011d3 | 713 | /* Set System Tick counter disabled */ |
| sahilmgandhi | 18:6a4db94011d3 | 714 | SysTick->CTRL = 0; |
| sahilmgandhi | 18:6a4db94011d3 | 715 | |
| sahilmgandhi | 18:6a4db94011d3 | 716 | /* Set System Tick clock source */ |
| sahilmgandhi | 18:6a4db94011d3 | 717 | if( u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK ) |
| sahilmgandhi | 18:6a4db94011d3 | 718 | SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk; |
| sahilmgandhi | 18:6a4db94011d3 | 719 | else |
| sahilmgandhi | 18:6a4db94011d3 | 720 | CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc; |
| sahilmgandhi | 18:6a4db94011d3 | 721 | |
| sahilmgandhi | 18:6a4db94011d3 | 722 | /* Set System Tick reload value */ |
| sahilmgandhi | 18:6a4db94011d3 | 723 | SysTick->LOAD = u32Count; |
| sahilmgandhi | 18:6a4db94011d3 | 724 | |
| sahilmgandhi | 18:6a4db94011d3 | 725 | /* Clear System Tick current value and counter flag */ |
| sahilmgandhi | 18:6a4db94011d3 | 726 | SysTick->VAL = 0; |
| sahilmgandhi | 18:6a4db94011d3 | 727 | |
| sahilmgandhi | 18:6a4db94011d3 | 728 | /* Set System Tick interrupt enabled and counter enabled */ |
| sahilmgandhi | 18:6a4db94011d3 | 729 | SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; |
| sahilmgandhi | 18:6a4db94011d3 | 730 | } |
| sahilmgandhi | 18:6a4db94011d3 | 731 | |
| sahilmgandhi | 18:6a4db94011d3 | 732 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 733 | * @brief Disable System Tick counter |
| sahilmgandhi | 18:6a4db94011d3 | 734 | * @param None |
| sahilmgandhi | 18:6a4db94011d3 | 735 | * @return None |
| sahilmgandhi | 18:6a4db94011d3 | 736 | * @details This function disable System Tick counter. |
| sahilmgandhi | 18:6a4db94011d3 | 737 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 738 | void CLK_DisableSysTick(void) |
| sahilmgandhi | 18:6a4db94011d3 | 739 | { |
| sahilmgandhi | 18:6a4db94011d3 | 740 | /* Set System Tick counter disabled */ |
| sahilmgandhi | 18:6a4db94011d3 | 741 | SysTick->CTRL = 0; |
| sahilmgandhi | 18:6a4db94011d3 | 742 | } |
| sahilmgandhi | 18:6a4db94011d3 | 743 | |
| sahilmgandhi | 18:6a4db94011d3 | 744 | |
| sahilmgandhi | 18:6a4db94011d3 | 745 | /*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */ |
| sahilmgandhi | 18:6a4db94011d3 | 746 | |
| sahilmgandhi | 18:6a4db94011d3 | 747 | /*@}*/ /* end of group CLK_Driver */ |
| sahilmgandhi | 18:6a4db94011d3 | 748 | |
| sahilmgandhi | 18:6a4db94011d3 | 749 | /*@}*/ /* end of group Standard_Driver */ |
| sahilmgandhi | 18:6a4db94011d3 | 750 | |
| sahilmgandhi | 18:6a4db94011d3 | 751 | /*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/ |