MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NUVOTON/TARGET_M451/device/M451Series.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /******************************************************************************
sahilmgandhi 18:6a4db94011d3 2 * @file M451Series.h
sahilmgandhi 18:6a4db94011d3 3 * @version V3.10
sahilmgandhi 18:6a4db94011d3 4 * $Revision: 179 $
sahilmgandhi 18:6a4db94011d3 5 * $Date: 15/09/04 3:45p $
sahilmgandhi 18:6a4db94011d3 6 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for M451 Series MCU
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * @note
sahilmgandhi 18:6a4db94011d3 9 * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
sahilmgandhi 18:6a4db94011d3 10 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 11
sahilmgandhi 18:6a4db94011d3 12
sahilmgandhi 18:6a4db94011d3 13 /**
sahilmgandhi 18:6a4db94011d3 14 \mainpage Introduction
sahilmgandhi 18:6a4db94011d3 15 *
sahilmgandhi 18:6a4db94011d3 16 *
sahilmgandhi 18:6a4db94011d3 17 * This user manual describes the usage of M451 Series MCU device driver
sahilmgandhi 18:6a4db94011d3 18 *
sahilmgandhi 18:6a4db94011d3 19 * <b>Disclaimer</b>
sahilmgandhi 18:6a4db94011d3 20 *
sahilmgandhi 18:6a4db94011d3 21 * The Software is furnished "AS IS", without warranty as to performance or results, and
sahilmgandhi 18:6a4db94011d3 22 * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all
sahilmgandhi 18:6a4db94011d3 23 * warranties, express, implied or otherwise, with regard to the Software, its use, or
sahilmgandhi 18:6a4db94011d3 24 * operation, including without limitation any and all warranties of merchantability, fitness
sahilmgandhi 18:6a4db94011d3 25 * for a particular purpose, and non-infringement of intellectual property rights.
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * <b>Copyright Notice</b>
sahilmgandhi 18:6a4db94011d3 28 *
sahilmgandhi 18:6a4db94011d3 29 * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
sahilmgandhi 18:6a4db94011d3 30 */
sahilmgandhi 18:6a4db94011d3 31
sahilmgandhi 18:6a4db94011d3 32 /**
sahilmgandhi 18:6a4db94011d3 33 * \page PG_REV Revision History
sahilmgandhi 18:6a4db94011d3 34 *
sahilmgandhi 18:6a4db94011d3 35 * <b>Revision 3.01.001</b>
sahilmgandhi 18:6a4db94011d3 36 * \li Added Nu-LB-M451, NuEdu and USB device sample code.
sahilmgandhi 18:6a4db94011d3 37 * \li Added a lacking macro SYS_IS_LVR_RST() to SYS driver.
sahilmgandhi 18:6a4db94011d3 38 * \li Added a sample code DAC_PDMA_ScatterGather_PWMTrigger to use PDMA scatter gather mode and trigger DAC by PWM.
sahilmgandhi 18:6a4db94011d3 39 * \li Added counter type constant definitions: PWM_UP_COUNTER, PWM_DOWN_COUNTER, and PWM_UP_DOWN_COUNTER.
sahilmgandhi 18:6a4db94011d3 40 * \li Added DAC_PDMA_PWMTrigger sample code to use PDMA and trigger DAC by PWM.
sahilmgandhi 18:6a4db94011d3 41 * \li Added a sample code EADC_PDMA_PWM_Trigger to trigger EADC with PWM and copy result by PDMA.
sahilmgandhi 18:6a4db94011d3 42 * \li Added a new function to control systick and select systick clock source CLK_EnableSysTick() and CLK_DisableSysTick() in CLK driver.
sahilmgandhi 18:6a4db94011d3 43 * \li Added 'NMIEN' and 'NMISTS' control registers to M451Series.h for NMI control.
sahilmgandhi 18:6a4db94011d3 44 * \li Added PDMA_ScatterGather_PingPongBuffer sample code to create ping-pong buffer with PDMA scatter gather mode.
sahilmgandhi 18:6a4db94011d3 45 * \li Added 'PE_DRVCTL' register of GPIO to M451Series.h for GPIO driving strength control.
sahilmgandhi 18:6a4db94011d3 46 * \li Added a sample code PWM_PDMA_Capture to transfer PWM capture data by PDMA.
sahilmgandhi 18:6a4db94011d3 47 * \li Added SCLIB_ActivateDelay API for initial SC with non-standard H/W design in SC driver
sahilmgandhi 18:6a4db94011d3 48 * \li Fixed the bug of EADC_IS_INT_FLAG_OV() that accesses the incorrect register.
sahilmgandhi 18:6a4db94011d3 49 * \li Fixed the bug of EADC_IS_SAMPLE_MODULE_OV() that accesses the incorrect register.
sahilmgandhi 18:6a4db94011d3 50 * \li Fixed the bug of EADC_SetExtendSampleTime() for position shift error in EADC driver.
sahilmgandhi 18:6a4db94011d3 51 * \li Fixed the bug of EADC_SetTriggerDelayTime() for position shift error in EADC driver.
sahilmgandhi 18:6a4db94011d3 52 * \li Fixed the bug of PWM_ENABLE_OUTPUT_INVERTER () that output inverter function cannot be disabled.
sahilmgandhi 18:6a4db94011d3 53 * \li Fixed the bug of PWM_MASK_OUTPUT() in PWM driver that mask function cannot be disabled.
sahilmgandhi 18:6a4db94011d3 54 * \li Fixed CAN_STATUS_LEC_Msk from 0x03 to 0x07.
sahilmgandhi 18:6a4db94011d3 55 * \li Fixed the bug of CLK_SysTickDelay() that COUNTFLAG may not be cleared in CLK driver.
sahilmgandhi 18:6a4db94011d3 56 * \li Fixed CTL and PINCTL regsiter synchronize issue by waiting synchronized ready flag in SC driver.
sahilmgandhi 18:6a4db94011d3 57 * \li Fixed DAC_SetDelayTime() calculation error in DAC driver because the dac->TCTL only used 10 bits, not 14 bits.
sahilmgandhi 18:6a4db94011d3 58 * \li Fixed EADC_CMP_ADCMPIE_DISABLE definition error.
sahilmgandhi 18:6a4db94011d3 59 * \li Fixed EADC_CMP_ADCMPIE_DISABLE definition error.
sahilmgandhi 18:6a4db94011d3 60 * \li Fixed IAR entry point from __iar_program_start to Reset_Handler
sahilmgandhi 18:6a4db94011d3 61 * \li Fixed PWM_ConfigOutputChannel() return value bug in PWM driver.
sahilmgandhi 18:6a4db94011d3 62 * \li Fixed the bug of PWM_ConfigSyncPhase() that cannot configure synchronized source for channel2~5.
sahilmgandhi 18:6a4db94011d3 63 * \li Fixed SC_SET_STOP_BIT_LEN definition error.
sahilmgandhi 18:6a4db94011d3 64 * \li Fixed SCUART baudrate return error in SCUART_Open and SCUART_SetLineConfig API of SCUART driver.
sahilmgandhi 18:6a4db94011d3 65 * \li Fixed SCUART_PARITY_NONE/SCUART_PARITY_EVEN/SCUART_PARITY_ODD definition bug in SCUART driver.
sahilmgandhi 18:6a4db94011d3 66 * \li Fixed u32DataWidth setting error by sc->UARTCTL in SCUART_SetLineConfig API of SCUART driver.
sahilmgandhi 18:6a4db94011d3 67 * \li Fixed SMBD_Enable constant value definition error in I2C driver.
sahilmgandhi 18:6a4db94011d3 68 * \li Fixed the problem that MSC device detection is aborted due to REQUEST_SENSE command not ready.
sahilmgandhi 18:6a4db94011d3 69 * \li Fixed UART clock setting bug in UART_Open(), UART_SetLine_Config() and UART_SelectIrDAMode() of UART driver.
sahilmgandhi 18:6a4db94011d3 70 * \li Improved compatibility of USBH driver for pen driver.
sahilmgandhi 18:6a4db94011d3 71 * \li Improved EADC_ConfigSampleModule() to support rising and falling trigger at the same time.
sahilmgandhi 18:6a4db94011d3 72 * \li Improved EBI_SRAM sample code to add PDMA data transfer with EBI.
sahilmgandhi 18:6a4db94011d3 73 * \li Improved SC driver to support more than one SC port.
sahilmgandhi 18:6a4db94011d3 74 * \li Improved USBH driver to support composite HID devices
sahilmgandhi 18:6a4db94011d3 75 * \li Improved USBD driver to support more USB device sample code.
sahilmgandhi 18:6a4db94011d3 76 * \li Modified I2C_STOP() from #define to inline and add waiting STO bit clear to 0 . This modified is safe for next START coming soon.
sahilmgandhi 18:6a4db94011d3 77 * \li Removed CRC clock enabled in CRC_Open(). User should enable CRC clock in system initialization before any CRC operation.
sahilmgandhi 18:6a4db94011d3 78 * \li Removed FMC_ReadDID() in FMC driver. This function was no longer supported.
sahilmgandhi 18:6a4db94011d3 79 * \li Removed I2C_CTL_STA_STO_SI and I2C_CTL_STA_STO_SI_AA definitions to avoid STOP and START write to control bit at the same time.
sahilmgandhi 18:6a4db94011d3 80 *
sahilmgandhi 18:6a4db94011d3 81 * <b>Revision 3.00.005</b>
sahilmgandhi 18:6a4db94011d3 82 * \li Fixed EADC_CTL_DMOF_STRAIGHT_BINARY and EADC_CTL_DMOF_TWOS_COMPLEMENT definition error in EADC driver.
sahilmgandhi 18:6a4db94011d3 83 * \li Fixed EADC_FALLING_EDGE_TRIGGER definition error in EADC driver.
sahilmgandhi 18:6a4db94011d3 84 * \li Fixed EADC_RISING_EDGE_TRIGGER definition error in EADC driver.
sahilmgandhi 18:6a4db94011d3 85 * \li Fixed UART transmit data bug in UART_TEST_HANDLE() of UART_TxRxFunction sample code.
sahilmgandhi 18:6a4db94011d3 86 * \li Fixed the data missing bug when BULK IN transfer is end by max packet size packet at last packet in USBD_VCOM sample code.
sahilmgandhi 18:6a4db94011d3 87 * \li Fixed program user configuration area without erase in USBD_MassStorage_DataFlash sample code.
sahilmgandhi 18:6a4db94011d3 88 * \li Fixed the bug of switching HCLK to HIRC before enabling PLL in CLK_SetCoreClock() of CLK driver.
sahilmgandhi 18:6a4db94011d3 89 * \li Fixed isochronous transfer bugs of USB Host library.
sahilmgandhi 18:6a4db94011d3 90 * \li Fixed Clear Modem Status Interrupt flag bug in UART_ClearIntFlag() of UART driver.
sahilmgandhi 18:6a4db94011d3 91 * \li Fixed the time-out flag clear bug in I2C_ClearTimeoutFlag() of I2C driver.
sahilmgandhi 18:6a4db94011d3 92 * \li Replaced PERIOD0~5 with PERIOD[6] in PWM_T, and modified PERIOD bit field constant definition in M451Series.h.
sahilmgandhi 18:6a4db94011d3 93 * \li Replaced CMPDAT0~5 with CMPDAT0[6] in PWM_T, and modified CMPDAT bit field constant definition in M451Series.h.
sahilmgandhi 18:6a4db94011d3 94 * \li Replaced CNT0~5 with CNT[6] in PWM_T, and modified CNT bit field constant definition in M451Series.h.
sahilmgandhi 18:6a4db94011d3 95 * \li Replaced PBUF0~5 with PBUF[6] in PWM_T, and modified PBUF bit field constant definition in M451Series.h.
sahilmgandhi 18:6a4db94011d3 96 * \li Replaced CMPBUF0~5 with CMPBUF[6] in PWM_T, and modified CMPBUF bit field constant definition in M451Series.h.
sahilmgandhi 18:6a4db94011d3 97 * \li Replaced CURSCAT0~CURSCAT11 with CURSCAT[12] in PDMA_T of M451Series.h.
sahilmgandhi 18:6a4db94011d3 98 * \li Modified CLK_WaitClockReady() time-out to about 300 ms in CLK driver.
sahilmgandhi 18:6a4db94011d3 99 * \li Updated USB USBD_MassStorage_DataFlash sample code and USB Driver to pass USB-IF MSC test. (The MassStorage size must be greater than 64 KB; otherwise, Command Set test will fail in MSC test).
sahilmgandhi 18:6a4db94011d3 100 * \li Replaced old HID library file (open source) with Nuvoton HID library in USB Host library.
sahilmgandhi 18:6a4db94011d3 101 * \li Added USBH_Audio_Class and USBH_UAC_HID sample code for USB Host to support UAC + HID device.
sahilmgandhi 18:6a4db94011d3 102 *
sahilmgandhi 18:6a4db94011d3 103 * <b>Revision 3.00.004</b>
sahilmgandhi 18:6a4db94011d3 104 * \li Fixed the time-out from 5 ms to 300 ms in CLK_WaitClockReady() of CLK driver.
sahilmgandhi 18:6a4db94011d3 105 * \li Fixed the bug of UART_ClearIntFlag() in UART driver to only clear one flag at one time.
sahilmgandhi 18:6a4db94011d3 106 * \li Fixed the missing parameter, UART clock source LXT, for CLK_SetModuleClock() in UART driver.
sahilmgandhi 18:6a4db94011d3 107 * \li Fixed the bug of clearing data and CTS wake-up flag to clear one flag at one time in UART1_IRQHandler() of UART_Wakeup sample code.
sahilmgandhi 18:6a4db94011d3 108 * \li Fixed the bug of RS485_HANDLE() in the UART_RS485_Slave sample code to only clear one flag at one time.
sahilmgandhi 18:6a4db94011d3 109 * \li Fixed the bug of clearing auto baud rate detect finished and time-out flag to clear one flag at one time in AutoBaudRate_RxTest() of UART_AutoBaudRate_Slave sample code.
sahilmgandhi 18:6a4db94011d3 110 * \li Fixed NVIC_EnableIRQ() to NVIC_DisableIRQ() after chip wake-up in I2C_Wakeup_Slave sample code.
sahilmgandhi 18:6a4db94011d3 111 * \li Fixed multi-function setting error of SC CD pin in USBD_CCID sample code.
sahilmgandhi 18:6a4db94011d3 112 * \li Fixed PD.7 (Headphone output control pin) output mode configuration in WAU8822_Setup() of USBD_Audio_NAU8822 sample code.
sahilmgandhi 18:6a4db94011d3 113 * \li Fixed wrong CLK_WaitClockReady parameter in I2C_GCMode_Slave sample code.
sahilmgandhi 18:6a4db94011d3 114 * \li Fixed UART data transfer bug of USBD_VCOM sample code.
sahilmgandhi 18:6a4db94011d3 115 * \li Updated CLK driver to avoid HIRC force enabled in CLK_SetHCLK() and CLK_SetCoreClock().
sahilmgandhi 18:6a4db94011d3 116 * \li Updated USBD driver to pass USB-IF MSC test.
sahilmgandhi 18:6a4db94011d3 117 * \li Updated USBD_MassStorage_DataFlash sample code to pass USB-IF MSC test.
sahilmgandhi 18:6a4db94011d3 118 * \li Updated driver of VCOM for win8 certification in USBD_VCOM sample code.
sahilmgandhi 18:6a4db94011d3 119 * \li Added HID Media key supporting in USBD_Audio_HID_NAU8822 sample code.
sahilmgandhi 18:6a4db94011d3 120 * \li Added new sample code USBH_UAC_HID of USB Host to support UAC + HID device.
sahilmgandhi 18:6a4db94011d3 121 * \li Added new sample code USBH_Audio_Class to support USB audio class device (UAC).
sahilmgandhi 18:6a4db94011d3 122 *
sahilmgandhi 18:6a4db94011d3 123 * <b>Revision 3.00.003</b>
sahilmgandhi 18:6a4db94011d3 124 * \li Added USBD_Audio_HID_NAU8822 sample code.
sahilmgandhi 18:6a4db94011d3 125 *
sahilmgandhi 18:6a4db94011d3 126 * <b>Revision 3.00.002</b>
sahilmgandhi 18:6a4db94011d3 127 * \li Fixed serial number code in device descriptor.
sahilmgandhi 18:6a4db94011d3 128 * \li Fixed EBI_Open API did not perform u32CSActiveLevel parameters to set CS pin polar.
sahilmgandhi 18:6a4db94011d3 129 * \li Fixed SMBus bus time-out and Clock Lo time-out API.
sahilmgandhi 18:6a4db94011d3 130 * \li Fixed I2C0,1 IP reset of SYS_IPRST1.
sahilmgandhi 18:6a4db94011d3 131 * \li Fixed include path of CMSIS.
sahilmgandhi 18:6a4db94011d3 132 * \li Fixed SPI_CLR_UNIT_TRANS_INT_FLAG( ) definition.
sahilmgandhi 18:6a4db94011d3 133 * \li Fixed USBD_INT_WAKEUP definition.
sahilmgandhi 18:6a4db94011d3 134 * \li Modified USBD driver to support USB remote wake-up function.
sahilmgandhi 18:6a4db94011d3 135 *
sahilmgandhi 18:6a4db94011d3 136 * <b>Revision 3.00.001</b>
sahilmgandhi 18:6a4db94011d3 137 * \li Initial Release.
sahilmgandhi 18:6a4db94011d3 138 */
sahilmgandhi 18:6a4db94011d3 139
sahilmgandhi 18:6a4db94011d3 140 #ifndef __M451SERIES_H__
sahilmgandhi 18:6a4db94011d3 141 #define __M451SERIES_H__
sahilmgandhi 18:6a4db94011d3 142
sahilmgandhi 18:6a4db94011d3 143 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 144 extern "C" {
sahilmgandhi 18:6a4db94011d3 145 #endif
sahilmgandhi 18:6a4db94011d3 146
sahilmgandhi 18:6a4db94011d3 147 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 148 /* Processor and Core Peripherals */
sahilmgandhi 18:6a4db94011d3 149 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 150 /** @addtogroup CMSIS Device CMSIS Definitions
sahilmgandhi 18:6a4db94011d3 151 Configuration of the Cortex-M4 Processor and Core Peripherals
sahilmgandhi 18:6a4db94011d3 152 @{
sahilmgandhi 18:6a4db94011d3 153 */
sahilmgandhi 18:6a4db94011d3 154
sahilmgandhi 18:6a4db94011d3 155 /*
sahilmgandhi 18:6a4db94011d3 156 * ==========================================================================
sahilmgandhi 18:6a4db94011d3 157 * ---------- Interrupt Number Definition -----------------------------------
sahilmgandhi 18:6a4db94011d3 158 * ==========================================================================
sahilmgandhi 18:6a4db94011d3 159 */
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161 typedef enum IRQn
sahilmgandhi 18:6a4db94011d3 162 {
sahilmgandhi 18:6a4db94011d3 163 /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
sahilmgandhi 18:6a4db94011d3 164 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
sahilmgandhi 18:6a4db94011d3 165 MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */
sahilmgandhi 18:6a4db94011d3 166 BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */
sahilmgandhi 18:6a4db94011d3 167 UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */
sahilmgandhi 18:6a4db94011d3 168 SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
sahilmgandhi 18:6a4db94011d3 169 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */
sahilmgandhi 18:6a4db94011d3 170 PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
sahilmgandhi 18:6a4db94011d3 171 SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 /****** M451 Specific Interrupt Numbers ********************************************************/
sahilmgandhi 18:6a4db94011d3 174
sahilmgandhi 18:6a4db94011d3 175 BOD_IRQn = 0, /*!< Brown Out detection Interrupt */
sahilmgandhi 18:6a4db94011d3 176 IRC_IRQn = 1, /*!< Internal RC Interrupt */
sahilmgandhi 18:6a4db94011d3 177 PWRWU_IRQn = 2, /*!< Power Down Wake Up Interrupt */
sahilmgandhi 18:6a4db94011d3 178 RAMPE_IRQn = 3, /*!< SRAM parity check failed Interrupt */
sahilmgandhi 18:6a4db94011d3 179 CKFAIL_IRQn = 4, /*!< Clock failed Interrupt */
sahilmgandhi 18:6a4db94011d3 180 RTC_IRQn = 6, /*!< Real Time Clock Interrupt */
sahilmgandhi 18:6a4db94011d3 181 TAMPER_IRQn = 7, /*!< Tamper detection Interrupt */
sahilmgandhi 18:6a4db94011d3 182 WDT_IRQn = 8, /*!< Watchdog Timer Interrupt */
sahilmgandhi 18:6a4db94011d3 183 WWDT_IRQn = 9, /*!< Window Watchdog Timer Interrupt */
sahilmgandhi 18:6a4db94011d3 184 EINT0_IRQn = 10, /*!< External Input 0 Interrupt */
sahilmgandhi 18:6a4db94011d3 185 EINT1_IRQn = 11, /*!< External Input 1 Interrupt */
sahilmgandhi 18:6a4db94011d3 186 EINT2_IRQn = 12, /*!< External Input 2 Interrupt */
sahilmgandhi 18:6a4db94011d3 187 EINT3_IRQn = 13, /*!< External Input 3 Interrupt */
sahilmgandhi 18:6a4db94011d3 188 EINT4_IRQn = 14, /*!< External Input 4 Interrupt */
sahilmgandhi 18:6a4db94011d3 189 EINT5_IRQn = 15, /*!< External Input 5 Interrupt */
sahilmgandhi 18:6a4db94011d3 190 GPA_IRQn = 16, /*!< GPIO Port A Interrupt */
sahilmgandhi 18:6a4db94011d3 191 GPB_IRQn = 17, /*!< GPIO Port B Interrupt */
sahilmgandhi 18:6a4db94011d3 192 GPC_IRQn = 18, /*!< GPIO Port C Interrupt */
sahilmgandhi 18:6a4db94011d3 193 GPD_IRQn = 19, /*!< GPIO Port D Interrupt */
sahilmgandhi 18:6a4db94011d3 194 GPE_IRQn = 20, /*!< GPIO Port E Interrupt */
sahilmgandhi 18:6a4db94011d3 195 GPF_IRQn = 21, /*!< GPIO Port F Interrupt */
sahilmgandhi 18:6a4db94011d3 196 SPI0_IRQn = 22, /*!< SPI0 Interrupt */
sahilmgandhi 18:6a4db94011d3 197 SPI1_IRQn = 23, /*!< SPI1 Interrupt */
sahilmgandhi 18:6a4db94011d3 198 BRAKE0_IRQn = 24, /*!< BRAKE0 Interrupt */
sahilmgandhi 18:6a4db94011d3 199 PWM0P0_IRQn = 25, /*!< PWM0P0 Interrupt */
sahilmgandhi 18:6a4db94011d3 200 PWM0P1_IRQn = 26, /*!< PWM0P1 Interrupt */
sahilmgandhi 18:6a4db94011d3 201 PWM0P2_IRQn = 27, /*!< PWM0P2 Interrupt */
sahilmgandhi 18:6a4db94011d3 202 BRAKE1_IRQn = 28, /*!< BRAKE1 Interrupt */
sahilmgandhi 18:6a4db94011d3 203 PWM1P0_IRQn = 29, /*!< PWM1P0 Interrupt */
sahilmgandhi 18:6a4db94011d3 204 PWM1P1_IRQn = 30, /*!< PWM1P1 Interrupt */
sahilmgandhi 18:6a4db94011d3 205 PWM1P2_IRQn = 31, /*!< PWM1P2 Interrupt */
sahilmgandhi 18:6a4db94011d3 206 TMR0_IRQn = 32, /*!< Timer 0 Interrupt */
sahilmgandhi 18:6a4db94011d3 207 TMR1_IRQn = 33, /*!< Timer 1 Interrupt */
sahilmgandhi 18:6a4db94011d3 208 TMR2_IRQn = 34, /*!< Timer 2 Interrupt */
sahilmgandhi 18:6a4db94011d3 209 TMR3_IRQn = 35, /*!< Timer 3 Interrupt */
sahilmgandhi 18:6a4db94011d3 210 UART0_IRQn = 36, /*!< UART 0 Interrupt */
sahilmgandhi 18:6a4db94011d3 211 UART1_IRQn = 37, /*!< UART 1 Interrupt */
sahilmgandhi 18:6a4db94011d3 212 I2C0_IRQn = 38, /*!< I2C 0 Interrupt */
sahilmgandhi 18:6a4db94011d3 213 I2C1_IRQn = 39, /*!< I2C 1 Interrupt */
sahilmgandhi 18:6a4db94011d3 214 PDMA_IRQn = 40, /*!< Peripheral DMA Interrupt */
sahilmgandhi 18:6a4db94011d3 215 DAC_IRQn = 41, /*!< DAC Interrupt */
sahilmgandhi 18:6a4db94011d3 216 ADC00_IRQn = 42, /*!< ADC0 Source 0 Interrupt */
sahilmgandhi 18:6a4db94011d3 217 ADC01_IRQn = 43, /*!< ADC0 Source 1 Interrupt */
sahilmgandhi 18:6a4db94011d3 218 ACMP01_IRQn = 44, /*!< Analog Comparator 0 and 1 Interrupt */
sahilmgandhi 18:6a4db94011d3 219 ADC02_IRQn = 46, /*!< ADC0 Source 2 Interrupt */
sahilmgandhi 18:6a4db94011d3 220 ADC03_IRQn = 47, /*!< ADC0 Source 3 Interrupt */
sahilmgandhi 18:6a4db94011d3 221 UART2_IRQn = 48, /*!< UART2 Interrupt */
sahilmgandhi 18:6a4db94011d3 222 UART3_IRQn = 49, /*!< UART3 Interrupt */
sahilmgandhi 18:6a4db94011d3 223 SPI2_IRQn = 51, /*!< SPI2 Interrupt */
sahilmgandhi 18:6a4db94011d3 224 USBD_IRQn = 53, /*!< USB device Interrupt */
sahilmgandhi 18:6a4db94011d3 225 USBH_IRQn = 54, /*!< USB host Interrupt */
sahilmgandhi 18:6a4db94011d3 226 USBOTG_IRQn = 55, /*!< USB OTG Interrupt */
sahilmgandhi 18:6a4db94011d3 227 CAN0_IRQn = 56, /*!< CAN0 Interrupt */
sahilmgandhi 18:6a4db94011d3 228 SC0_IRQn = 58, /*!< Smart Card 0 Interrupt */
sahilmgandhi 18:6a4db94011d3 229 TK_IRQn = 63 /*!< Touch Key Interrupt */
sahilmgandhi 18:6a4db94011d3 230 } IRQn_Type;
sahilmgandhi 18:6a4db94011d3 231
sahilmgandhi 18:6a4db94011d3 232
sahilmgandhi 18:6a4db94011d3 233 /*
sahilmgandhi 18:6a4db94011d3 234 * ==========================================================================
sahilmgandhi 18:6a4db94011d3 235 * ----------- Processor and Core Peripheral Section ------------------------
sahilmgandhi 18:6a4db94011d3 236 * ==========================================================================
sahilmgandhi 18:6a4db94011d3 237 */
sahilmgandhi 18:6a4db94011d3 238
sahilmgandhi 18:6a4db94011d3 239 /* Configuration of the Cortex-M# Processor and Core Peripherals */
sahilmgandhi 18:6a4db94011d3 240 #define __CM4_REV 0x0201 /*!< Core Revision r2p1 */
sahilmgandhi 18:6a4db94011d3 241 #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
sahilmgandhi 18:6a4db94011d3 242 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
sahilmgandhi 18:6a4db94011d3 243 #define __MPU_PRESENT 1 /*!< MPU present or not */
sahilmgandhi 18:6a4db94011d3 244 #define __FPU_PRESENT 1 /*!< FPU present or not */
sahilmgandhi 18:6a4db94011d3 245
sahilmgandhi 18:6a4db94011d3 246 /*@}*/ /* end of group CMSIS */
sahilmgandhi 18:6a4db94011d3 247
sahilmgandhi 18:6a4db94011d3 248 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
sahilmgandhi 18:6a4db94011d3 249 #include "system_M451Series.h" /* M451 System include file */
sahilmgandhi 18:6a4db94011d3 250 #include <stdint.h>
sahilmgandhi 18:6a4db94011d3 251
sahilmgandhi 18:6a4db94011d3 252
sahilmgandhi 18:6a4db94011d3 253
sahilmgandhi 18:6a4db94011d3 254 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 255 /* Device Specific Peripheral registers structures */
sahilmgandhi 18:6a4db94011d3 256 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 257
sahilmgandhi 18:6a4db94011d3 258 /** @addtogroup REGISTER Control Register
sahilmgandhi 18:6a4db94011d3 259
sahilmgandhi 18:6a4db94011d3 260 @{
sahilmgandhi 18:6a4db94011d3 261
sahilmgandhi 18:6a4db94011d3 262 */
sahilmgandhi 18:6a4db94011d3 263
sahilmgandhi 18:6a4db94011d3 264
sahilmgandhi 18:6a4db94011d3 265 /*---------------------- Analog Comparator Controller -------------------------*/
sahilmgandhi 18:6a4db94011d3 266 /**
sahilmgandhi 18:6a4db94011d3 267 @addtogroup ACMP Analog Comparator Controller(ACMP)
sahilmgandhi 18:6a4db94011d3 268 Memory Mapped Structure for ACMP Controller
sahilmgandhi 18:6a4db94011d3 269 @{ */
sahilmgandhi 18:6a4db94011d3 270
sahilmgandhi 18:6a4db94011d3 271
sahilmgandhi 18:6a4db94011d3 272 typedef struct
sahilmgandhi 18:6a4db94011d3 273 {
sahilmgandhi 18:6a4db94011d3 274
sahilmgandhi 18:6a4db94011d3 275
sahilmgandhi 18:6a4db94011d3 276 /**
sahilmgandhi 18:6a4db94011d3 277 * @var ACMP_T::CTL
sahilmgandhi 18:6a4db94011d3 278 * Offset: 0x00 Analog Comparator 0 Control Register
sahilmgandhi 18:6a4db94011d3 279 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 280 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 281 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 282 * |[0] |ACMPEN |Comparator Enable Bit
sahilmgandhi 18:6a4db94011d3 283 * | | |0 = Comparator 0 Disabled.
sahilmgandhi 18:6a4db94011d3 284 * | | |1 = Comparator 0 Enabled.
sahilmgandhi 18:6a4db94011d3 285 * |[1] |ACMPIE |Comparator Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 286 * | | |0 = Comparator 0 interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 287 * | | |1 = Comparator 0 interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 288 * | | |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well.
sahilmgandhi 18:6a4db94011d3 289 * |[2] |HYSEN |Comparator Hysteresis Enable Bit
sahilmgandhi 18:6a4db94011d3 290 * | | |0 = Comparator 0 hysteresis Disabled.
sahilmgandhi 18:6a4db94011d3 291 * | | |1 = Comparator 0 hysteresis Enabled.
sahilmgandhi 18:6a4db94011d3 292 * |[3] |ACMPOINV |Comparator Output Inverse
sahilmgandhi 18:6a4db94011d3 293 * | | |0 = Comparator 0 output inverse Disabled.
sahilmgandhi 18:6a4db94011d3 294 * | | |1 = Comparator 0 output inverse Enabled.
sahilmgandhi 18:6a4db94011d3 295 * |[5:4] |NEGSEL |Comparator Negative Input Selection
sahilmgandhi 18:6a4db94011d3 296 * | | |00 = ACMP0_N pin.
sahilmgandhi 18:6a4db94011d3 297 * | | |01 = Internal comparator reference voltage (CRV).
sahilmgandhi 18:6a4db94011d3 298 * | | |10 = Band-gap voltage.
sahilmgandhi 18:6a4db94011d3 299 * | | |11 = DAC output.
sahilmgandhi 18:6a4db94011d3 300 * |[7:6] |POSSEL |Comparator Positive Input Selection
sahilmgandhi 18:6a4db94011d3 301 * | | |00 = Input from ACMP0_P0.
sahilmgandhi 18:6a4db94011d3 302 * | | |01 = Input from ACMP0_P1.
sahilmgandhi 18:6a4db94011d3 303 * | | |10 = Input from ACMP0_P2.
sahilmgandhi 18:6a4db94011d3 304 * | | |11 = Input from ACMP0_P3.
sahilmgandhi 18:6a4db94011d3 305 * |[9:8] |INTPOL |Interrupt Condition Polarity Selection
sahilmgandhi 18:6a4db94011d3 306 * | | |ACMPIF0 will be set to 1 when comparator output edge condition is detected.
sahilmgandhi 18:6a4db94011d3 307 * | | |00 = Rising edge or falling edge.
sahilmgandhi 18:6a4db94011d3 308 * | | |01 = Rising edge.
sahilmgandhi 18:6a4db94011d3 309 * | | |10 = Falling edge.
sahilmgandhi 18:6a4db94011d3 310 * | | |11 = Reserved.
sahilmgandhi 18:6a4db94011d3 311 * |[12] |OUTSEL |Comparator Output Select
sahilmgandhi 18:6a4db94011d3 312 * | | |0 = Comparator 0 output to ACMP0_O pin is unfiltered comparator output.
sahilmgandhi 18:6a4db94011d3 313 * | | |1 = Comparator 0 output to ACMP0_O pin is from filter output.
sahilmgandhi 18:6a4db94011d3 314 * |[15:13] |FILTSEL |Comparator Output Filter Count Selection
sahilmgandhi 18:6a4db94011d3 315 * | | |000 = Filter function is Disabled.
sahilmgandhi 18:6a4db94011d3 316 * | | |001 = ACMP0 output is sampled 1 consecutive PCLK.
sahilmgandhi 18:6a4db94011d3 317 * | | |010 = ACMP0 output is sampled 2 consecutive PCLKs.
sahilmgandhi 18:6a4db94011d3 318 * | | |011 = ACMP0 output is sampled 4 consecutive PCLKs.
sahilmgandhi 18:6a4db94011d3 319 * | | |100 = ACMP0 output is sampled 8 consecutive PCLKs.
sahilmgandhi 18:6a4db94011d3 320 * | | |101 = ACMP0 output is sampled 16 consecutive PCLKs.
sahilmgandhi 18:6a4db94011d3 321 * | | |110 = ACMP0 output is sampled 32 consecutive PCLKs.
sahilmgandhi 18:6a4db94011d3 322 * | | |111 = ACMP0 output is sampled 64 consecutive PCLKs.
sahilmgandhi 18:6a4db94011d3 323 * |[16] |WKEN |Power Down Wake-Up Enable Bit
sahilmgandhi 18:6a4db94011d3 324 * | | |0 = Wake-up function Disabled.
sahilmgandhi 18:6a4db94011d3 325 * | | |1 = Wake-up function Enabled.
sahilmgandhi 18:6a4db94011d3 326 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 327 * Offset: 0x04 Analog Comparator 1 Control Register
sahilmgandhi 18:6a4db94011d3 328 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 329 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 330 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 331 * |[0] |ACMPEN |Comparator Enable Bit
sahilmgandhi 18:6a4db94011d3 332 * | | |0 = Comparator 1 Disabled.
sahilmgandhi 18:6a4db94011d3 333 * | | |1 = Comparator 1 Enabled.
sahilmgandhi 18:6a4db94011d3 334 * |[1] |ACMPIE |Comparator Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 335 * | | |0 = Comparator 1 interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 336 * | | |1 = Comparator 1 interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 337 * | | |If WKEN (ACMP_CTL1[16]) is set to 1, the wake-up interrupt function will be enabled as well.
sahilmgandhi 18:6a4db94011d3 338 * |[2] |HYSEN |Comparator Hysteresis Enable Bit
sahilmgandhi 18:6a4db94011d3 339 * | | |0 = Comparator 1 hysteresis Disabled.
sahilmgandhi 18:6a4db94011d3 340 * | | |1 = Comparator 1 hysteresis Enabled.
sahilmgandhi 18:6a4db94011d3 341 * |[3] |ACMPOINV |Comparator Output Inverse Control
sahilmgandhi 18:6a4db94011d3 342 * | | |0 = Comparator 1 output inverse Disabled.
sahilmgandhi 18:6a4db94011d3 343 * | | |1 = Comparator 1 output inverse Enabled.
sahilmgandhi 18:6a4db94011d3 344 * |[5:4] |NEGSEL |Comparator Negative Input Selection
sahilmgandhi 18:6a4db94011d3 345 * | | |00 = ACMP1_N pin.
sahilmgandhi 18:6a4db94011d3 346 * | | |01 = Internal comparator reference voltage (CRV).
sahilmgandhi 18:6a4db94011d3 347 * | | |10 = Band-gap voltage.
sahilmgandhi 18:6a4db94011d3 348 * | | |11 = DAC output.
sahilmgandhi 18:6a4db94011d3 349 * |[7:6] |POSSEL |Comparator Positive Input Selection
sahilmgandhi 18:6a4db94011d3 350 * | | |00 = Input from ACMP1_P0.
sahilmgandhi 18:6a4db94011d3 351 * | | |01 = Input from ACMP1_P1.
sahilmgandhi 18:6a4db94011d3 352 * | | |10 = Input from ACMP1_P2.
sahilmgandhi 18:6a4db94011d3 353 * | | |11 = Input from ACMP1_P3.
sahilmgandhi 18:6a4db94011d3 354 * |[9:8] |INTPOL |Interrupt Condition Polarity Selection
sahilmgandhi 18:6a4db94011d3 355 * | | |ACMPIF1 will be set to 1 when comparator output edge condition is detected.
sahilmgandhi 18:6a4db94011d3 356 * | | |00 = Rising edge or falling edge.
sahilmgandhi 18:6a4db94011d3 357 * | | |01 = Rising edge.
sahilmgandhi 18:6a4db94011d3 358 * | | |10 = Falling edge.
sahilmgandhi 18:6a4db94011d3 359 * | | |11 = Reserved.
sahilmgandhi 18:6a4db94011d3 360 * |[12] |OUTSEL |Comparator Output Select
sahilmgandhi 18:6a4db94011d3 361 * | | |0 = Comparator 1 output to ACMP1_O pin is unfiltered comparator output.
sahilmgandhi 18:6a4db94011d3 362 * | | |1 = Comparator 1 output to ACMP1_O pin is from filter output.
sahilmgandhi 18:6a4db94011d3 363 * |[15:13] |FILTSEL |Comparator Output Filter Count Selection
sahilmgandhi 18:6a4db94011d3 364 * | | |000 = Filter function is Disabled.
sahilmgandhi 18:6a4db94011d3 365 * | | |001 = ACMP1 output is sampled 1 consecutive PCLK.
sahilmgandhi 18:6a4db94011d3 366 * | | |010 = ACMP1 output is sampled 2 consecutive PCLKs.
sahilmgandhi 18:6a4db94011d3 367 * | | |011 = ACMP1 output is sampled 4 consecutive PCLKs.
sahilmgandhi 18:6a4db94011d3 368 * | | |100 = ACMP1 output is sampled 8 consecutive PCLKs.
sahilmgandhi 18:6a4db94011d3 369 * | | |101 = ACMP1 output is sampled 16 consecutive PCLKs.
sahilmgandhi 18:6a4db94011d3 370 * | | |110 = ACMP1 output is sampled 32 consecutive PCLKs.
sahilmgandhi 18:6a4db94011d3 371 * | | |111 = ACMP1 output is sampled 64 consecutive PCLKs.
sahilmgandhi 18:6a4db94011d3 372 * |[16] |WKEN |Power Down Wakeup Enable Bit
sahilmgandhi 18:6a4db94011d3 373 * | | |0 = Wake-up function Disabled.
sahilmgandhi 18:6a4db94011d3 374 * | | |1 = Wake-up function Enabled.
sahilmgandhi 18:6a4db94011d3 375 * @var ACMP_T::STATUS
sahilmgandhi 18:6a4db94011d3 376 * Offset: 0x08 Analog Comparator Status Register
sahilmgandhi 18:6a4db94011d3 377 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 378 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 379 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 380 * |[0] |ACMPIF0 |Comparator 0 Interrupt Flag
sahilmgandhi 18:6a4db94011d3 381 * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output.
sahilmgandhi 18:6a4db94011d3 382 * | | |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.
sahilmgandhi 18:6a4db94011d3 383 * | | |Note: Write 1 to clear this bit to 0.
sahilmgandhi 18:6a4db94011d3 384 * |[1] |ACMPIF1 |Comparator 1 Interrupt Flag
sahilmgandhi 18:6a4db94011d3 385 * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output.
sahilmgandhi 18:6a4db94011d3 386 * | | |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.
sahilmgandhi 18:6a4db94011d3 387 * | | |Note: Write 1 to clear this bit to 0.
sahilmgandhi 18:6a4db94011d3 388 * |[4] |ACMPO0 |Comparator 0 Output
sahilmgandhi 18:6a4db94011d3 389 * | | |Synchronized to the PCLK to allow reading by software.
sahilmgandhi 18:6a4db94011d3 390 * | | |Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0.
sahilmgandhi 18:6a4db94011d3 391 * |[5] |ACMPO1 |Comparator 1 Output
sahilmgandhi 18:6a4db94011d3 392 * | | |Synchronized to the PCLK to allow reading by software.
sahilmgandhi 18:6a4db94011d3 393 * | | |Cleared when the comparator 1 is disabled, i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0.
sahilmgandhi 18:6a4db94011d3 394 * |[8] |WKIF0 |Comparator 0 Power Down Wake-Up Interrupt Flag
sahilmgandhi 18:6a4db94011d3 395 * | | |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs.
sahilmgandhi 18:6a4db94011d3 396 * | | |0 = No power down wake-up occurred.
sahilmgandhi 18:6a4db94011d3 397 * | | |1 = Power down wake-up occurred.
sahilmgandhi 18:6a4db94011d3 398 * | | |Note: Write 1 to clear this bit to 0.
sahilmgandhi 18:6a4db94011d3 399 * |[9] |WKIF1 |Comparator 1 Power Down Wake-Up Interrupt Flag
sahilmgandhi 18:6a4db94011d3 400 * | | |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs.
sahilmgandhi 18:6a4db94011d3 401 * | | |0 = No power down wake-up occurred.
sahilmgandhi 18:6a4db94011d3 402 * | | |1 = Power down wake-up occurred.
sahilmgandhi 18:6a4db94011d3 403 * | | |Note: Write 1 to clear this bit to 0.
sahilmgandhi 18:6a4db94011d3 404 * @var ACMP_T::VREF
sahilmgandhi 18:6a4db94011d3 405 * Offset: 0x0C Analog Comparator Reference Voltage Control Register
sahilmgandhi 18:6a4db94011d3 406 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 407 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 408 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 409 * |[3:0] |CRVCTL |Comparator Reference Voltage Setting
sahilmgandhi 18:6a4db94011d3 410 * | | |CRV = CRV source voltage * (1/6+CRVCTL/24).
sahilmgandhi 18:6a4db94011d3 411 * |[6] |CRVSSEL |CRV Source Voltage Selection
sahilmgandhi 18:6a4db94011d3 412 * | | |0 = VDDA is selected as CRV source voltage.
sahilmgandhi 18:6a4db94011d3 413 * | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage.
sahilmgandhi 18:6a4db94011d3 414 */
sahilmgandhi 18:6a4db94011d3 415
sahilmgandhi 18:6a4db94011d3 416 __IO uint32_t CTL[2]; /* Offset: 0x00 Analog Comparator Control Register */
sahilmgandhi 18:6a4db94011d3 417 __IO uint32_t STATUS; /* Offset: 0x08 Analog Comparator Status Register */
sahilmgandhi 18:6a4db94011d3 418 __IO uint32_t VREF; /* Offset: 0x0C Analog Comparator Reference Voltage Control Register */
sahilmgandhi 18:6a4db94011d3 419
sahilmgandhi 18:6a4db94011d3 420 } ACMP_T;
sahilmgandhi 18:6a4db94011d3 421
sahilmgandhi 18:6a4db94011d3 422
sahilmgandhi 18:6a4db94011d3 423
sahilmgandhi 18:6a4db94011d3 424 /**
sahilmgandhi 18:6a4db94011d3 425 @addtogroup ACMP_CONST ACMP Bit Field Definition
sahilmgandhi 18:6a4db94011d3 426 Constant Definitions for ACMP Controller
sahilmgandhi 18:6a4db94011d3 427 @{ */
sahilmgandhi 18:6a4db94011d3 428
sahilmgandhi 18:6a4db94011d3 429 #define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP_T::CTL: ACMPEN Position */
sahilmgandhi 18:6a4db94011d3 430 #define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP_T::CTL: ACMPEN Mask */
sahilmgandhi 18:6a4db94011d3 431
sahilmgandhi 18:6a4db94011d3 432 #define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP_T::CTL: ACMPIE Position */
sahilmgandhi 18:6a4db94011d3 433 #define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP_T::CTL: ACMPIE Mask */
sahilmgandhi 18:6a4db94011d3 434
sahilmgandhi 18:6a4db94011d3 435 #define ACMP_CTL_HYSEN_Pos (2) /*!< ACMP_T::CTL: HYSEN Position */
sahilmgandhi 18:6a4db94011d3 436 #define ACMP_CTL_HYSEN_Msk (0x1ul << ACMP_CTL_HYSEN_Pos) /*!< ACMP_T::CTL: HYSEN Mask */
sahilmgandhi 18:6a4db94011d3 437
sahilmgandhi 18:6a4db94011d3 438 #define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP_T::CTL: ACMPOINV Position */
sahilmgandhi 18:6a4db94011d3 439 #define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP_T::CTL: ACMPOINV Mask */
sahilmgandhi 18:6a4db94011d3 440
sahilmgandhi 18:6a4db94011d3 441 #define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP_T::CTL: NEGSEL Position */
sahilmgandhi 18:6a4db94011d3 442 #define ACMP_CTL_NEGSEL_Msk (0x3ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_T::CTL: NEGSEL Mask */
sahilmgandhi 18:6a4db94011d3 443
sahilmgandhi 18:6a4db94011d3 444 #define ACMP_CTL_POSSEL_Pos (6) /*!< ACMP_T::CTL: POSSEL Position */
sahilmgandhi 18:6a4db94011d3 445 #define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP_T::CTL: POSSEL Mask */
sahilmgandhi 18:6a4db94011d3 446
sahilmgandhi 18:6a4db94011d3 447 #define ACMP_CTL_INTPOL_Pos (8) /*!< ACMP_T::CTL: INTPOL Position */
sahilmgandhi 18:6a4db94011d3 448 #define ACMP_CTL_INTPOL_Msk (0x3ul << ACMP_CTL_INTPOL_Pos) /*!< ACMP_T::CTL: INTPOL Mask */
sahilmgandhi 18:6a4db94011d3 449
sahilmgandhi 18:6a4db94011d3 450 #define ACMP_CTL_OUTSEL_Pos (12) /*!< ACMP_T::CTL: OUTSEL Position */
sahilmgandhi 18:6a4db94011d3 451 #define ACMP_CTL_OUTSEL_Msk (0x1ul << ACMP_CTL_OUTSEL_Pos) /*!< ACMP_T::CTL: OUTSEL Mask */
sahilmgandhi 18:6a4db94011d3 452
sahilmgandhi 18:6a4db94011d3 453 #define ACMP_CTL_FILTSEL_Pos (13) /*!< ACMP_T::CTL: FILTSEL Position */
sahilmgandhi 18:6a4db94011d3 454 #define ACMP_CTL_FILTSEL_Msk (0x7ul << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_T::CTL: FILTSEL Mask */
sahilmgandhi 18:6a4db94011d3 455
sahilmgandhi 18:6a4db94011d3 456 #define ACMP_CTL_WKEN_Pos (16) /*!< ACMP_T::CTL: WKEN Position */
sahilmgandhi 18:6a4db94011d3 457 #define ACMP_CTL_WKEN_Msk (0x1ul << ACMP_CTL_WKEN_Pos) /*!< ACMP_T::CTL: WKEN Mask */
sahilmgandhi 18:6a4db94011d3 458
sahilmgandhi 18:6a4db94011d3 459 #define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP_T::STATUS: ACMPIF0 Position */
sahilmgandhi 18:6a4db94011d3 460 #define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP_T::STATUS: ACMPIF0 Mask */
sahilmgandhi 18:6a4db94011d3 461
sahilmgandhi 18:6a4db94011d3 462 #define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP_T::STATUS: ACMPIF1 Position */
sahilmgandhi 18:6a4db94011d3 463 #define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP_T::STATUS: ACMPIF1 Mask */
sahilmgandhi 18:6a4db94011d3 464
sahilmgandhi 18:6a4db94011d3 465 #define ACMP_STATUS_ACMPO0_Pos (4) /*!< ACMP_T::STATUS: ACMPO0 Position */
sahilmgandhi 18:6a4db94011d3 466 #define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP_T::STATUS: ACMPO0 Mask */
sahilmgandhi 18:6a4db94011d3 467
sahilmgandhi 18:6a4db94011d3 468 #define ACMP_STATUS_ACMPO1_Pos (5) /*!< ACMP_T::STATUS: ACMPO1 Position */
sahilmgandhi 18:6a4db94011d3 469 #define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP_T::STATUS: ACMPO1 Mask */
sahilmgandhi 18:6a4db94011d3 470
sahilmgandhi 18:6a4db94011d3 471 #define ACMP_STATUS_WKIF0_Pos (8) /*!< ACMP_T::STATUS: WKIF0 Position */
sahilmgandhi 18:6a4db94011d3 472 #define ACMP_STATUS_WKIF0_Msk (0x1ul << ACMP_STATUS_WKIF0_Pos) /*!< ACMP_T::STATUS: WKIF0 Mask */
sahilmgandhi 18:6a4db94011d3 473
sahilmgandhi 18:6a4db94011d3 474 #define ACMP_STATUS_WKIF1_Pos (9) /*!< ACMP_T::STATUS: WKIF1 Position */
sahilmgandhi 18:6a4db94011d3 475 #define ACMP_STATUS_WKIF1_Msk (0x1ul << ACMP_STATUS_WKIF1_Pos) /*!< ACMP_T::STATUS: WKIF1 Mask */
sahilmgandhi 18:6a4db94011d3 476
sahilmgandhi 18:6a4db94011d3 477 #define ACMP_VREF_CRVCTL_Pos (0) /*!< ACMP_T::VREF: CRVCTL Position */
sahilmgandhi 18:6a4db94011d3 478 #define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) /*!< ACMP_T::VREF: CRVCTL Mask */
sahilmgandhi 18:6a4db94011d3 479
sahilmgandhi 18:6a4db94011d3 480 #define ACMP_VREF_CRVSSEL_Pos (6) /*!< ACMP_T::VREF: CRVSSEL Position */
sahilmgandhi 18:6a4db94011d3 481 #define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_T::VREF: CRVSSEL Mask */
sahilmgandhi 18:6a4db94011d3 482
sahilmgandhi 18:6a4db94011d3 483 /**@}*/ /* ACMP_CONST */
sahilmgandhi 18:6a4db94011d3 484 /**@}*/ /* end of ACMP register group */
sahilmgandhi 18:6a4db94011d3 485
sahilmgandhi 18:6a4db94011d3 486
sahilmgandhi 18:6a4db94011d3 487 /*---------------------- Enhanced Analog to Digital Converter -------------------------*/
sahilmgandhi 18:6a4db94011d3 488 /**
sahilmgandhi 18:6a4db94011d3 489 @addtogroup Enhanced Analog to Digital Converter(EADC)
sahilmgandhi 18:6a4db94011d3 490 Memory Mapped Structure for EADC Controller
sahilmgandhi 18:6a4db94011d3 491 @{ */
sahilmgandhi 18:6a4db94011d3 492
sahilmgandhi 18:6a4db94011d3 493
sahilmgandhi 18:6a4db94011d3 494 typedef struct
sahilmgandhi 18:6a4db94011d3 495 {
sahilmgandhi 18:6a4db94011d3 496
sahilmgandhi 18:6a4db94011d3 497
sahilmgandhi 18:6a4db94011d3 498 /**
sahilmgandhi 18:6a4db94011d3 499 * @var EADC_T::DAT
sahilmgandhi 18:6a4db94011d3 500 * Offset: 0x00-0x48 A/D Data Register n for Sample Module n, n=0~18
sahilmgandhi 18:6a4db94011d3 501 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 502 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 503 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 504 * |[15:0] |RESULT |A/D Conversion Result
sahilmgandhi 18:6a4db94011d3 505 * | | |This field contains 12 bits conversion result.
sahilmgandhi 18:6a4db94011d3 506 * | | |When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].
sahilmgandhi 18:6a4db94011d3 507 * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12].
sahilmgandhi 18:6a4db94011d3 508 * |[16] |OV |Overrun Flag
sahilmgandhi 18:6a4db94011d3 509 * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1.
sahilmgandhi 18:6a4db94011d3 510 * | | |0 = Data in RESULT[11:0] is recent conversion result.
sahilmgandhi 18:6a4db94011d3 511 * | | |1 = Data in RESULT[11:0] is overwrite.
sahilmgandhi 18:6a4db94011d3 512 * | | |Note: It is cleared by hardware after EADC_DAT register is read.
sahilmgandhi 18:6a4db94011d3 513 * |[17] |VALID |Valid Flag
sahilmgandhi 18:6a4db94011d3 514 * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read.
sahilmgandhi 18:6a4db94011d3 515 * | | |0 = Data in RESULT[11:0] bits is not valid.
sahilmgandhi 18:6a4db94011d3 516 * | | |1 = Data in RESULT[11:0] bits is valid.
sahilmgandhi 18:6a4db94011d3 517 * @var EADC_T::CURDAT
sahilmgandhi 18:6a4db94011d3 518 * Offset: 0x4C EADC PDMA Current Transfer Data Register
sahilmgandhi 18:6a4db94011d3 519 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 520 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 521 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 522 * |[17:0] |CURDAT |ADC PDMA Current Transfer Data Register
sahilmgandhi 18:6a4db94011d3 523 * | | |This register is a shadow register of EADC_DATn (n=0~18) for PDMA support.
sahilmgandhi 18:6a4db94011d3 524 * | | |This is a read only register.
sahilmgandhi 18:6a4db94011d3 525 * @var EADC_T::CTL
sahilmgandhi 18:6a4db94011d3 526 * Offset: 0x50 A/D Control Register
sahilmgandhi 18:6a4db94011d3 527 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 528 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 529 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 530 * |[0] |ADCEN |A/D Converter Enable Bit
sahilmgandhi 18:6a4db94011d3 531 * | | |0 = Disabled.
sahilmgandhi 18:6a4db94011d3 532 * | | |1 = Enabled.
sahilmgandhi 18:6a4db94011d3 533 * | | |Note: Before starting A/D conversion function, this bit should be set to 1.
sahilmgandhi 18:6a4db94011d3 534 * | | |Clear it to 0 to disable A/D converter analog circuit power consumption.
sahilmgandhi 18:6a4db94011d3 535 * |[1] |ADCRST |ADC A/D Converter Control Circuits Reset
sahilmgandhi 18:6a4db94011d3 536 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 537 * | | |1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value.
sahilmgandhi 18:6a4db94011d3 538 * | | |Note: ADCRST bit remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0.
sahilmgandhi 18:6a4db94011d3 539 * |[2] |ADCIEN0 |Specific Sample Module A/D ADINT0 Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 540 * | | |The A/D converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module A/D conversion.
sahilmgandhi 18:6a4db94011d3 541 * | | |If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated.
sahilmgandhi 18:6a4db94011d3 542 * | | |0 = Specific sample module A/D ADINT0 interrupt function Disabled.
sahilmgandhi 18:6a4db94011d3 543 * | | |1 = Specific sample module A/D ADINT0 interrupt function Enabled.
sahilmgandhi 18:6a4db94011d3 544 * |[3] |ADCIEN1 |Specific Sample Module A/D ADINT1 Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 545 * | | |The A/D converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module A/D conversion.
sahilmgandhi 18:6a4db94011d3 546 * | | |If ADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated.
sahilmgandhi 18:6a4db94011d3 547 * | | |0 = Specific sample module A/D ADINT1 interrupt function Disabled.
sahilmgandhi 18:6a4db94011d3 548 * | | |1 = Specific sample module A/D ADINT1 interrupt function Enabled.
sahilmgandhi 18:6a4db94011d3 549 * |[4] |ADCIEN2 |Specific Sample Module A/D ADINT2 Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 550 * | | |The A/D converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module A/D conversion.
sahilmgandhi 18:6a4db94011d3 551 * | | |If ADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated.
sahilmgandhi 18:6a4db94011d3 552 * | | |0 = Specific sample module A/D ADINT2 interrupt function Disabled.
sahilmgandhi 18:6a4db94011d3 553 * | | |1 = Specific sample module A/D ADINT2 interrupt function Enabled.
sahilmgandhi 18:6a4db94011d3 554 * |[5] |ADCIEN3 |Specific Sample Module A/D ADINT3 Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 555 * | | |The A/D converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module A/D conversion.
sahilmgandhi 18:6a4db94011d3 556 * | | |If ADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated.
sahilmgandhi 18:6a4db94011d3 557 * | | |0 = Specific sample module A/D ADINT3 interrupt function Disabled.
sahilmgandhi 18:6a4db94011d3 558 * | | |1 = Specific sample module A/D ADINT3 interrupt function Enabled.
sahilmgandhi 18:6a4db94011d3 559 * |[8] |DIFFEN |Differential Analog Input Mode Enable Bit
sahilmgandhi 18:6a4db94011d3 560 * | | |0 = Single-end analog input mode.
sahilmgandhi 18:6a4db94011d3 561 * | | |1 = Differential analog input mode.
sahilmgandhi 18:6a4db94011d3 562 * |[9] |DMOF |ADC Differential Input Mode Output Format
sahilmgandhi 18:6a4db94011d3 563 * | | |0 = A/D conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with unsigned format.
sahilmgandhi 18:6a4db94011d3 564 * | | |1 = A/D conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with 2'complement format.
sahilmgandhi 18:6a4db94011d3 565 * |[11] |PDMAEN |PDMA Transfer Enable Bit
sahilmgandhi 18:6a4db94011d3 566 * | | |When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, user can enable this bit to generate a PDMA data transfer request.
sahilmgandhi 18:6a4db94011d3 567 * | | |0 = PDMA data transfer Disabled.
sahilmgandhi 18:6a4db94011d3 568 * | | |1 = PDMA data transfer Enabled.
sahilmgandhi 18:6a4db94011d3 569 * | | |Note: When set this bit field to 1, user must set ADCIENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt.
sahilmgandhi 18:6a4db94011d3 570 * |[18:16] |SMPTSEL |ADC Internal Sampling Time Selection
sahilmgandhi 18:6a4db94011d3 571 * | | |ADC internal sampling cycle = SMPTSEL + 1.
sahilmgandhi 18:6a4db94011d3 572 * | | |000 = 1 ADC clock sampling time.
sahilmgandhi 18:6a4db94011d3 573 * | | |001 = 2 ADC clock sampling time.
sahilmgandhi 18:6a4db94011d3 574 * | | |010 = 3 ADC clock sampling time.
sahilmgandhi 18:6a4db94011d3 575 * | | |011 = 4 ADC clock sampling time.
sahilmgandhi 18:6a4db94011d3 576 * | | |100 = 5 ADC clock sampling time.
sahilmgandhi 18:6a4db94011d3 577 * | | |101 = 6 ADC clock sampling time.
sahilmgandhi 18:6a4db94011d3 578 * | | |110 = 7 ADC clock sampling time.
sahilmgandhi 18:6a4db94011d3 579 * | | |111 = 8 ADC clock sampling time.
sahilmgandhi 18:6a4db94011d3 580 * @var EADC_T::SWTRG
sahilmgandhi 18:6a4db94011d3 581 * Offset: 0x54 A/D Sample Module Software Start Register
sahilmgandhi 18:6a4db94011d3 582 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 583 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 584 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 585 * |[18:0] |SWTRG |A/D Sample Module
sahilmgandhi 18:6a4db94011d3 586 * | | |0~18 Software Force To Start ADC Conversion
sahilmgandhi 18:6a4db94011d3 587 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 588 * | | |1 = Cause an ADC conversion when the priority is given to sample module.
sahilmgandhi 18:6a4db94011d3 589 * | | |Note: After write this register to start ADC conversion, the EADC_PENDSTS register will show which sample module will conversion.
sahilmgandhi 18:6a4db94011d3 590 * | | |If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
sahilmgandhi 18:6a4db94011d3 591 * @var EADC_T::PENDSTS
sahilmgandhi 18:6a4db94011d3 592 * Offset: 0x58 A/D Start of Conversion Pending Flag Register
sahilmgandhi 18:6a4db94011d3 593 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 594 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 595 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 596 * |[18:0] |STPF |A/D Sample Module 0~18 Start Of Conversion Pending Flag
sahilmgandhi 18:6a4db94011d3 597 * | | |Read:
sahilmgandhi 18:6a4db94011d3 598 * | | |0 = There is no pending conversion for sample module.
sahilmgandhi 18:6a4db94011d3 599 * | | |1 = Sample module ADC start of conversion is pending.
sahilmgandhi 18:6a4db94011d3 600 * | | |Write:
sahilmgandhi 18:6a4db94011d3 601 * | | |1 = clear pending flag and cancel the conversion for sample module.
sahilmgandhi 18:6a4db94011d3 602 * | | |Note: This bit remains 1 during pending state, when the respective ADC conversion is end, the STPFn (n=0~18) bit is automatically cleared to 0
sahilmgandhi 18:6a4db94011d3 603 * @var EADC_T::OVSTS
sahilmgandhi 18:6a4db94011d3 604 * Offset: 0x5C A/D Sample Module Start of Conversion Overrun Flag Register
sahilmgandhi 18:6a4db94011d3 605 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 606 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 607 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 608 * |[18:0] |SPOVF |A/D SAMPLE0~18 Overrun Flag
sahilmgandhi 18:6a4db94011d3 609 * | | |0 = No sample module event overrun.
sahilmgandhi 18:6a4db94011d3 610 * | | |1 = Indicates a new sample module event is generated while an old one event is pending.
sahilmgandhi 18:6a4db94011d3 611 * | | |Note: This bit is cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 612 * @var EADC_T::SCTL
sahilmgandhi 18:6a4db94011d3 613 * Offset: 0x80-0x8C A/D Sample Module n Control Register, n=0~3
sahilmgandhi 18:6a4db94011d3 614 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 615 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 616 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 617 * |[3:0] |CHSEL |A/D Sample Module Channel Selection
sahilmgandhi 18:6a4db94011d3 618 * | | |00H = EADC_CH0.
sahilmgandhi 18:6a4db94011d3 619 * | | |01H = EADC_CH1.
sahilmgandhi 18:6a4db94011d3 620 * | | |02H = EADC_CH2.
sahilmgandhi 18:6a4db94011d3 621 * | | |03H = EADC_CH3.
sahilmgandhi 18:6a4db94011d3 622 * | | |04H = EADC_CH4.
sahilmgandhi 18:6a4db94011d3 623 * | | |05H = EADC_CH5.
sahilmgandhi 18:6a4db94011d3 624 * | | |06H = EADC_CH6.
sahilmgandhi 18:6a4db94011d3 625 * | | |07H = EADC_CH7.
sahilmgandhi 18:6a4db94011d3 626 * | | |08H = EADC_CH8.
sahilmgandhi 18:6a4db94011d3 627 * | | |09H = EADC_CH9.
sahilmgandhi 18:6a4db94011d3 628 * | | |0AH = EADC_CH10.
sahilmgandhi 18:6a4db94011d3 629 * | | |0BH = EADC_CH11.
sahilmgandhi 18:6a4db94011d3 630 * | | |0CH = EADC_CH12.
sahilmgandhi 18:6a4db94011d3 631 * | | |0DH = EADC_CH13.
sahilmgandhi 18:6a4db94011d3 632 * | | |0EH = EADC_CH14.
sahilmgandhi 18:6a4db94011d3 633 * | | |0FH = EADC_CH15.
sahilmgandhi 18:6a4db94011d3 634 * |[4] |EXTREN |A/D External Trigger Rising Edge Enable Bit
sahilmgandhi 18:6a4db94011d3 635 * | | |0 = Rising edge Disabled when A/D selects STADC as trigger source.
sahilmgandhi 18:6a4db94011d3 636 * | | |1 = Rising edge Enabled when A/D selects STADC as trigger source.
sahilmgandhi 18:6a4db94011d3 637 * |[5] |EXTFEN |A/D External Trigger Falling Edge Enable Bit
sahilmgandhi 18:6a4db94011d3 638 * | | |0 = Falling edge Disabled when A/D selects STADC as trigger source.
sahilmgandhi 18:6a4db94011d3 639 * | | |1 = Falling edge Enabled when A/D selects STADC as trigger source.
sahilmgandhi 18:6a4db94011d3 640 * |[7:6] |TRGDLYDIV |A/D Sample Module Start Of Conversion Trigger Delay Clock Divider Selection
sahilmgandhi 18:6a4db94011d3 641 * | | |Trigger delay clock frequency:
sahilmgandhi 18:6a4db94011d3 642 * | | |00 = ADC_CLK/1.
sahilmgandhi 18:6a4db94011d3 643 * | | |01 = ADC_CLK/2.
sahilmgandhi 18:6a4db94011d3 644 * | | |10 = ADC_CLK/4.
sahilmgandhi 18:6a4db94011d3 645 * | | |11 = ADC_CLK/16.
sahilmgandhi 18:6a4db94011d3 646 * |[15:8] |TRGDLYCNT |A/D Sample Module Start Of Conversion Trigger Delay Time
sahilmgandhi 18:6a4db94011d3 647 * | | |Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting).
sahilmgandhi 18:6a4db94011d3 648 * |[20:16] |TRGSEL |A/D Sample Module Start Of Conversion Trigger Source Selection
sahilmgandhi 18:6a4db94011d3 649 * | | |0H = Disable trigger.
sahilmgandhi 18:6a4db94011d3 650 * | | |1H = External trigger from STADC pin input.
sahilmgandhi 18:6a4db94011d3 651 * | | |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger.
sahilmgandhi 18:6a4db94011d3 652 * | | |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger.
sahilmgandhi 18:6a4db94011d3 653 * | | |4H = Timer0 overflow pulse trigger.
sahilmgandhi 18:6a4db94011d3 654 * | | |5H = Timer1 overflow pulse trigger.
sahilmgandhi 18:6a4db94011d3 655 * | | |6H = Timer2 overflow pulse trigger.
sahilmgandhi 18:6a4db94011d3 656 * | | |7H = Timer3 overflow pulse trigger.
sahilmgandhi 18:6a4db94011d3 657 * | | |8H = PWM0TG0.
sahilmgandhi 18:6a4db94011d3 658 * | | |9H = PWM0TG1.
sahilmgandhi 18:6a4db94011d3 659 * | | |AH = PWM0TG2.
sahilmgandhi 18:6a4db94011d3 660 * | | |BH = PWM0TG3.
sahilmgandhi 18:6a4db94011d3 661 * | | |CH = PWM0TG4.
sahilmgandhi 18:6a4db94011d3 662 * | | |DH = PWM0TG5.
sahilmgandhi 18:6a4db94011d3 663 * | | |EH = PWM1TG0.
sahilmgandhi 18:6a4db94011d3 664 * | | |FH = PWM1TG1.
sahilmgandhi 18:6a4db94011d3 665 * | | |10H = PWM1TG2.
sahilmgandhi 18:6a4db94011d3 666 * | | |11H = PWM1TG3.
sahilmgandhi 18:6a4db94011d3 667 * | | |12H = PWM1TG4.
sahilmgandhi 18:6a4db94011d3 668 * | | |13H = PWM1TG5.
sahilmgandhi 18:6a4db94011d3 669 * | | |other = Reserved.
sahilmgandhi 18:6a4db94011d3 670 * |[22] |INTPOS |Interrupt Flag Position Select
sahilmgandhi 18:6a4db94011d3 671 * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D end of conversion.
sahilmgandhi 18:6a4db94011d3 672 * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D start of conversion.
sahilmgandhi 18:6a4db94011d3 673 * |[23] |DBMEN |Double Buffer Mode Enable Bit
sahilmgandhi 18:6a4db94011d3 674 * | | |0 = Sample has one sample result register. (default).
sahilmgandhi 18:6a4db94011d3 675 * | | |1 = Sample has two sample result registers.
sahilmgandhi 18:6a4db94011d3 676 * |[31:24] |EXTSMPT |ADC Sampling Time Extend
sahilmgandhi 18:6a4db94011d3 677 * | | |When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend A/D sampling time after trigger source is coming to get enough sampling time.
sahilmgandhi 18:6a4db94011d3 678 * | | |The range of start delay time is from 0~255 ADC clock.
sahilmgandhi 18:6a4db94011d3 679 * @var EADC_T::SCTL
sahilmgandhi 18:6a4db94011d3 680 * Offset: 0x90-0xBC A/D Sample Module n Control Register, n=4~15
sahilmgandhi 18:6a4db94011d3 681 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 682 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 683 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 684 * |[3:0] |CHSEL |A/D Sample Module Channel Selection
sahilmgandhi 18:6a4db94011d3 685 * | | |00H = EADC_CH0.
sahilmgandhi 18:6a4db94011d3 686 * | | |01H = EADC_CH1.
sahilmgandhi 18:6a4db94011d3 687 * | | |02H = EADC_CH2.
sahilmgandhi 18:6a4db94011d3 688 * | | |03H = EADC_CH3.
sahilmgandhi 18:6a4db94011d3 689 * | | |04H = EADC_CH4.
sahilmgandhi 18:6a4db94011d3 690 * | | |05H = EADC_CH5.
sahilmgandhi 18:6a4db94011d3 691 * | | |06H = EADC_CH6.
sahilmgandhi 18:6a4db94011d3 692 * | | |07H = EADC_CH7.
sahilmgandhi 18:6a4db94011d3 693 * | | |08H = EADC_CH8.
sahilmgandhi 18:6a4db94011d3 694 * | | |09H = EADC_CH9.
sahilmgandhi 18:6a4db94011d3 695 * | | |0AH = EADC_CH10.
sahilmgandhi 18:6a4db94011d3 696 * | | |0BH = EADC_CH11.
sahilmgandhi 18:6a4db94011d3 697 * | | |0CH = EADC_CH12.
sahilmgandhi 18:6a4db94011d3 698 * | | |0DH = EADC_CH13.
sahilmgandhi 18:6a4db94011d3 699 * | | |0EH = EADC_CH14.
sahilmgandhi 18:6a4db94011d3 700 * | | |0FH = EADC_CH15.
sahilmgandhi 18:6a4db94011d3 701 * |[4] |EXTREN |A/D External Trigger Rising Edge Enable Bit
sahilmgandhi 18:6a4db94011d3 702 * | | |0 = Rising edge Disabled when A/D selects STADC as trigger source.
sahilmgandhi 18:6a4db94011d3 703 * | | |1 = Rising edge Enabled when A/D selects STADC as trigger source.
sahilmgandhi 18:6a4db94011d3 704 * |[5] |EXTFEN |A/D External Trigger Falling Edge Enable Bit
sahilmgandhi 18:6a4db94011d3 705 * | | |0 = Falling edge Disabled when A/D selects STADC as trigger source.
sahilmgandhi 18:6a4db94011d3 706 * | | |1 = Falling edge Enabled when A/D selects STADC as trigger source.
sahilmgandhi 18:6a4db94011d3 707 * |[7:6] |TRGDLYDIV[1:0]|A/D Sample Module Start Of Conversion Trigger Delay Clock Divider Selection
sahilmgandhi 18:6a4db94011d3 708 * | | |Trigger delay clock frequency:
sahilmgandhi 18:6a4db94011d3 709 * | | |00 = ADC_CLK/1.
sahilmgandhi 18:6a4db94011d3 710 * | | |01 = ADC_CLK/2.
sahilmgandhi 18:6a4db94011d3 711 * | | |10 = ADC_CLK/4.
sahilmgandhi 18:6a4db94011d3 712 * | | |11 = ADC_CLK/16.
sahilmgandhi 18:6a4db94011d3 713 * |[15:8] |TRGDLYCNT[7:0]|A/D Sample Module Start Of Conversion Trigger Delay Time
sahilmgandhi 18:6a4db94011d3 714 * | | |Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting).
sahilmgandhi 18:6a4db94011d3 715 * |[20:16] |TRGSEL |A/D Sample Module Start Of Conversion Trigger Source Selection
sahilmgandhi 18:6a4db94011d3 716 * | | |0H = Disable trigger.
sahilmgandhi 18:6a4db94011d3 717 * | | |1H = External trigger from STADC pin input.
sahilmgandhi 18:6a4db94011d3 718 * | | |2H = ADC ADINT0 interrupt EOC pulse trigger.
sahilmgandhi 18:6a4db94011d3 719 * | | |3H = ADC ADINT1 interrupt EOC pulse trigger.
sahilmgandhi 18:6a4db94011d3 720 * | | |4H = Timer0 overflow pulse trigger.
sahilmgandhi 18:6a4db94011d3 721 * | | |5H = Timer1 overflow pulse trigger.
sahilmgandhi 18:6a4db94011d3 722 * | | |6H = Timer2 overflow pulse trigger.
sahilmgandhi 18:6a4db94011d3 723 * | | |7H = Timer3 overflow pulse trigger.
sahilmgandhi 18:6a4db94011d3 724 * | | |8H = PWM0TG0.
sahilmgandhi 18:6a4db94011d3 725 * | | |9H = PWM0TG1.
sahilmgandhi 18:6a4db94011d3 726 * | | |AH = PWM0TG2.
sahilmgandhi 18:6a4db94011d3 727 * | | |BH = PWM0TG3.
sahilmgandhi 18:6a4db94011d3 728 * | | |CH = PWM0TG4.
sahilmgandhi 18:6a4db94011d3 729 * | | |DH = PWM0TG5.
sahilmgandhi 18:6a4db94011d3 730 * | | |EH = PWM1TG0.
sahilmgandhi 18:6a4db94011d3 731 * | | |FH = PWM1TG1.
sahilmgandhi 18:6a4db94011d3 732 * | | |10H = PWM1TG2.
sahilmgandhi 18:6a4db94011d3 733 * | | |11H = PWM1TG3.
sahilmgandhi 18:6a4db94011d3 734 * | | |12H = PWM1TG4.
sahilmgandhi 18:6a4db94011d3 735 * | | |13H = PWM1TG5.
sahilmgandhi 18:6a4db94011d3 736 * | | |other = Reserved.
sahilmgandhi 18:6a4db94011d3 737 * |[22] |INTPOS |Interrupt Flag Position Select
sahilmgandhi 18:6a4db94011d3 738 * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D end of conversion.
sahilmgandhi 18:6a4db94011d3 739 * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D start of conversion.
sahilmgandhi 18:6a4db94011d3 740 * |[31:24] |EXTSMPT |ADC Sampling Time Extend
sahilmgandhi 18:6a4db94011d3 741 * | | |When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.
sahilmgandhi 18:6a4db94011d3 742 * | | |The range of start delay time is from 0~255 ADC clock.
sahilmgandhi 18:6a4db94011d3 743 * @var EADC_T::SCTL
sahilmgandhi 18:6a4db94011d3 744 * Offset: 0xC0~0xC8 A/D Sample Module n Control Register, n=16~18
sahilmgandhi 18:6a4db94011d3 745 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 746 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 747 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 748 * |[31:24] |EXTSMPT |ADC Sampling Time Extend
sahilmgandhi 18:6a4db94011d3 749 * | | |When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.
sahilmgandhi 18:6a4db94011d3 750 * | | |The range of start delay time is from 0~255 ADC clock.
sahilmgandhi 18:6a4db94011d3 751 * @var EADC_T::INTSRC
sahilmgandhi 18:6a4db94011d3 752 * Offset: 0xDC ADC interrupt n Source Enable Control Register, n=0~3
sahilmgandhi 18:6a4db94011d3 753 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 754 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 755 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 756 * |[0] |SPLIE0 |Sample Module 0 Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 757 * | | |0 = Sample Module 0 interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 758 * | | |1 = Sample Module 0 interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 759 * |[1] |SPLIE1 |Sample Module 1 Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 760 * | | |0 = Sample Module 1 interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 761 * | | |1 = Sample Module 1 interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 762 * |[2] |SPLIE2 |Sample Module 2 Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 763 * | | |0 = Sample Module 2 interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 764 * | | |1 = Sample Module 2 interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 765 * |[3] |SPLIE3 |Sample Module 3 Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 766 * | | |0 = Sample Module 3 interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 767 * | | |1 = Sample Module 3 interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 768 * |[4] |SPLIE4 |Sample Module 4 Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 769 * | | |0 = Sample Module 4 interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 770 * | | |1 = Sample Module 4 interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 771 * |[5] |SPLIE5 |Sample Module 5 Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 772 * | | |0 = Sample Module 5 interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 773 * | | |1 = Sample Module 5 interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 774 * |[6] |SPLIE6 |Sample Module 6 Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 775 * | | |0 = Sample Module 6 interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 776 * | | |1 = Sample Module 6 interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 777 * |[7] |SPLIE7 |Sample Module 7 Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 778 * | | |0 = Sample Module 7 interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 779 * | | |1 = Sample Module 7 interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 780 * |[8] |SPLIE8 |Sample Module 8 Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 781 * | | |0 = Sample Module 8 interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 782 * | | |1 = Sample Module 8 interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 783 * |[9] |SPLIE9 |Sample Module 9 Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 784 * | | |0 = Sample Module 9 interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 785 * | | |1 = Sample Module 9 interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 786 * |[10] |SPLIE10 |Sample Module 10 Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 787 * | | |0 = Sample Module 10 interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 788 * | | |1 = Sample Module 10 interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 789 * |[11] |SPLIE11 |Sample Module 11 Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 790 * | | |0 = Sample Module 11 interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 791 * | | |1 = Sample Module 11 interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 792 * |[12] |SPLIE12 |Sample Module 12 Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 793 * | | |0 = Sample Module 12 interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 794 * | | |1 = Sample Module 12 interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 795 * |[13] |SPLIE13 |Sample Module 13 Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 796 * | | |0 = Sample Module 13 interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 797 * | | |1 = Sample Module 13 interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 798 * |[14] |SPLIE14 |Sample Module 14 Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 799 * | | |0 = Sample Module 14 interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 800 * | | |1 = Sample Module 14 interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 801 * |[15] |SPLIE15 |Sample Module 15 Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 802 * | | |0 = Sample Module 15 interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 803 * | | |1 = Sample Module 15 interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 804 * |[16] |SPLIE16 |Sample Module 16 Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 805 * | | |0 = Sample Module 16 interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 806 * | | |1 = Sample Module 16 interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 807 * |[17] |SPLIE17 |Sample Module 17 Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 808 * | | |0 = Sample Module 17 interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 809 * | | |1 = Sample Module 17 interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 810 * |[18] |SPLIE18 |Sample Module 18 Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 811 * | | |0 = Sample Module 18 interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 812 * | | |1 = Sample Module 18 interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 813 * @var EADC_T::CMP
sahilmgandhi 18:6a4db94011d3 814 * Offset: 0xEC A/D Result Compare Register n, n=0~3
sahilmgandhi 18:6a4db94011d3 815 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 816 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 817 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 818 * |[0] |ADCMPEN |A/D Result Compare Enable Bit
sahilmgandhi 18:6a4db94011d3 819 * | | |0 = Compare Disabled.
sahilmgandhi 18:6a4db94011d3 820 * | | |1 = Compare Enabled.
sahilmgandhi 18:6a4db94011d3 821 * | | |Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register.
sahilmgandhi 18:6a4db94011d3 822 * |[1] |ADCMPIE |A/D Result Compare Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 823 * | | |0 = Compare function interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 824 * | | |1 = Compare function interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 825 * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated.
sahilmgandhi 18:6a4db94011d3 826 * |[2] |CMPCOND |Compare Condition
sahilmgandhi 18:6a4db94011d3 827 * | | |0= Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPDAT (EADC_CMPn
sahilmgandhi 18:6a4db94011d3 828 * | | |[27:16]), the internal match counter will increase one.
sahilmgandhi 18:6a4db94011d3 829 * | | |1= Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one.
sahilmgandhi 18:6a4db94011d3 830 * | | |Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the CMPF bit will be set.
sahilmgandhi 18:6a4db94011d3 831 * |[7:3] |CMPSPL |Compare Sample Module Selection
sahilmgandhi 18:6a4db94011d3 832 * | | |00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared.
sahilmgandhi 18:6a4db94011d3 833 * | | |00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared.
sahilmgandhi 18:6a4db94011d3 834 * | | |00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared.
sahilmgandhi 18:6a4db94011d3 835 * | | |00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared.
sahilmgandhi 18:6a4db94011d3 836 * | | |00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared.
sahilmgandhi 18:6a4db94011d3 837 * | | |00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared.
sahilmgandhi 18:6a4db94011d3 838 * | | |00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared.
sahilmgandhi 18:6a4db94011d3 839 * | | |00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared.
sahilmgandhi 18:6a4db94011d3 840 * | | |01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared.
sahilmgandhi 18:6a4db94011d3 841 * | | |01001 = Sample Module 9 conversion result EADC_DAT9 is selected to be compared.
sahilmgandhi 18:6a4db94011d3 842 * | | |01010 = Sample Module 10 conversion result EADC_DAT10 is selected to be compared.
sahilmgandhi 18:6a4db94011d3 843 * | | |01011 = Sample Module 11 conversion result EADC_DAT11 is selected to be compared.
sahilmgandhi 18:6a4db94011d3 844 * | | |01100 = Sample Module 12 conversion result EADC_DAT12 is selected to be compared.
sahilmgandhi 18:6a4db94011d3 845 * | | |01101 = Sample Module 13 conversion result EADC_DAT13 is selected to be compared.
sahilmgandhi 18:6a4db94011d3 846 * | | |01110 = Sample Module 14 conversion result EADC_DAT14 is selected to be compared.
sahilmgandhi 18:6a4db94011d3 847 * | | |01111 = Sample Module 15 conversion result EADC_DAT15 is selected to be compared.
sahilmgandhi 18:6a4db94011d3 848 * | | |10000 = Sample Module 16 conversion result EADC_DAT16 is selected to be compared.
sahilmgandhi 18:6a4db94011d3 849 * | | |10001 = Sample Module 17 conversion result EADC_DAT17 is selected to be compared.
sahilmgandhi 18:6a4db94011d3 850 * | | |10010 = Sample Module 18 conversion result EADC_DAT18 is selected to be compared.
sahilmgandhi 18:6a4db94011d3 851 * |[11:8] |CMPMCNT |Compare Match Count
sahilmgandhi 18:6a4db94011d3 852 * | | |When the specified A/D sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1.
sahilmgandhi 18:6a4db94011d3 853 * | | |If the compare result does not meet the compare condition, the internal compare match counter will reset to 0.
sahilmgandhi 18:6a4db94011d3 854 * | | |When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set.
sahilmgandhi 18:6a4db94011d3 855 * |[15] |CMPWEN |Compare Window Mode Enable Bit
sahilmgandhi 18:6a4db94011d3 856 * | | |0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched.
sahilmgandhi 18:6a4db94011d3 857 * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched.
sahilmgandhi 18:6a4db94011d3 858 * | | |1 = ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched.
sahilmgandhi 18:6a4db94011d3 859 * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.
sahilmgandhi 18:6a4db94011d3 860 * | | |Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register.
sahilmgandhi 18:6a4db94011d3 861 * |[27:16] |CMPDAT |Comparison Data
sahilmgandhi 18:6a4db94011d3 862 * | | |The 12 bits data is used to compare with conversion result of specified sample module.
sahilmgandhi 18:6a4db94011d3 863 * | | |User can use it to monitor the external analog input pin voltage transition without imposing a load on software.
sahilmgandhi 18:6a4db94011d3 864 * @var EADC_T::STATUS0
sahilmgandhi 18:6a4db94011d3 865 * Offset: 0xF0 A/D Status Register 0
sahilmgandhi 18:6a4db94011d3 866 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 867 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 868 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 869 * |[15:0] |VALID |EADC_DAT0~15 Data Valid Flag
sahilmgandhi 18:6a4db94011d3 870 * | | |It is a mirror of VALID bit in sample module A/D result data register EADC_DATn. (n=0~18).
sahilmgandhi 18:6a4db94011d3 871 * |[31:16] |OV |EADC_DAT0~15 Overrun Flag
sahilmgandhi 18:6a4db94011d3 872 * | | |It is a mirror to OV bit in sample module A/D result data register EADC_DATn. (n=0~18).
sahilmgandhi 18:6a4db94011d3 873 * @var EADC_T::STATUS1
sahilmgandhi 18:6a4db94011d3 874 * Offset: 0xF4 A/D Status Register 1
sahilmgandhi 18:6a4db94011d3 875 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 876 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 877 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 878 * |[2:0] |VALID |EADC_DAT16~18 Data Valid Flag
sahilmgandhi 18:6a4db94011d3 879 * | | |It is a mirror of VALID bit in sample module A/D result data register EADC_DATn. (n=0~18).
sahilmgandhi 18:6a4db94011d3 880 * |[18:16] |OV |EADC_DAT16~18 Overrun Flag
sahilmgandhi 18:6a4db94011d3 881 * | | |It is a mirror to OV bit in sample module A/D result data register EADC_DATn. (n=0~18).
sahilmgandhi 18:6a4db94011d3 882 * @var EADC_T::STATUS2
sahilmgandhi 18:6a4db94011d3 883 * Offset: 0xF8 A/D Status Register 2
sahilmgandhi 18:6a4db94011d3 884 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 885 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 886 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 887 * |[0] |ADIF0 |A/D ADINT0 Interrupt Flag
sahilmgandhi 18:6a4db94011d3 888 * | | |0 = No ADINT0 interrupt pulse received.
sahilmgandhi 18:6a4db94011d3 889 * | | |1 = ADINT0 interrupt pulse has been received.
sahilmgandhi 18:6a4db94011d3 890 * | | |Note1: This bit is cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 891 * | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
sahilmgandhi 18:6a4db94011d3 892 * |[1] |ADIF1 |A/D ADINT1 Interrupt Flag
sahilmgandhi 18:6a4db94011d3 893 * | | |0 = No ADINT1 interrupt pulse received.
sahilmgandhi 18:6a4db94011d3 894 * | | |1 = ADINT1 interrupt pulse has been received.
sahilmgandhi 18:6a4db94011d3 895 * | | |Note1: This bit is cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 896 * | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
sahilmgandhi 18:6a4db94011d3 897 * |[2] |ADIF2 |A/D ADINT2 Interrupt Flag
sahilmgandhi 18:6a4db94011d3 898 * | | |0 = No ADINT2 interrupt pulse received.
sahilmgandhi 18:6a4db94011d3 899 * | | |1 = ADINT2 interrupt pulse has been received.
sahilmgandhi 18:6a4db94011d3 900 * | | |Note1: This bit is cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 901 * | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
sahilmgandhi 18:6a4db94011d3 902 * |[3] |ADIF3 |A/D ADINT3 Interrupt Flag
sahilmgandhi 18:6a4db94011d3 903 * | | |0 = No ADINT3 interrupt pulse received.
sahilmgandhi 18:6a4db94011d3 904 * | | |1 = ADINT3 interrupt pulse has been received.
sahilmgandhi 18:6a4db94011d3 905 * | | |Note1: This bit is cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 906 * | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
sahilmgandhi 18:6a4db94011d3 907 * |[4] |ADCMPF0 |ADC Compare 0 Flag
sahilmgandhi 18:6a4db94011d3 908 * | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.
sahilmgandhi 18:6a4db94011d3 909 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP0 register setting.
sahilmgandhi 18:6a4db94011d3 910 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP0 register setting.
sahilmgandhi 18:6a4db94011d3 911 * | | |Note: This bit is cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 912 * |[5] |ADCMPF1 |ADC Compare 1 Flag
sahilmgandhi 18:6a4db94011d3 913 * | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.
sahilmgandhi 18:6a4db94011d3 914 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP1 register setting.
sahilmgandhi 18:6a4db94011d3 915 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP1 register setting.
sahilmgandhi 18:6a4db94011d3 916 * | | |Note: This bit is cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 917 * |[6] |ADCMPF2 |ADC Compare 2 Flag
sahilmgandhi 18:6a4db94011d3 918 * | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.
sahilmgandhi 18:6a4db94011d3 919 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP2 register setting.
sahilmgandhi 18:6a4db94011d3 920 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP2 register setting.
sahilmgandhi 18:6a4db94011d3 921 * | | |Note: This bit is cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 922 * |[7] |ADCMPF3 |ADC Compare 3 Flag
sahilmgandhi 18:6a4db94011d3 923 * | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.
sahilmgandhi 18:6a4db94011d3 924 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP3 register setting.
sahilmgandhi 18:6a4db94011d3 925 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP3 register setting.
sahilmgandhi 18:6a4db94011d3 926 * | | |Note: This bit is cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 927 * |[8] |ADOVIF0 |A/D ADINT0 Interrupt Flag Overrun
sahilmgandhi 18:6a4db94011d3 928 * | | |0 = ADINT0 interrupt flag is not overwritten to 1.
sahilmgandhi 18:6a4db94011d3 929 * | | |1 = ADINT0 interrupt flag is overwritten to 1.
sahilmgandhi 18:6a4db94011d3 930 * | | |Note: This bit is cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 931 * |[9] |ADOVIF1 |A/D ADINT1 Interrupt Flag Overrun
sahilmgandhi 18:6a4db94011d3 932 * | | |0 = ADINT1 interrupt flag is not overwritten to 1.
sahilmgandhi 18:6a4db94011d3 933 * | | |1 = ADINT1 interrupt flag is overwritten to 1.
sahilmgandhi 18:6a4db94011d3 934 * | | |Note: This bit is cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 935 * |[10] |ADOVIF2 |A/D ADINT2 Interrupt Flag Overrun
sahilmgandhi 18:6a4db94011d3 936 * | | |0 = ADINT2 interrupt flag is not overwritten to 1.
sahilmgandhi 18:6a4db94011d3 937 * | | |1 = ADINT2 interrupt flag is s overwritten to 1.
sahilmgandhi 18:6a4db94011d3 938 * | | |Note: This bit is cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 939 * |[11] |ADOVIF3 |A/D ADINT3 Interrupt Flag Overrun
sahilmgandhi 18:6a4db94011d3 940 * | | |0 = ADINT3 interrupt flag is not overwritten to 1.
sahilmgandhi 18:6a4db94011d3 941 * | | |1 = ADINT3 interrupt flag is overwritten to 1.
sahilmgandhi 18:6a4db94011d3 942 * | | |Note: This bit is cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 943 * |[12] |ADCMPO0 |ADC Compare 0 Output Status
sahilmgandhi 18:6a4db94011d3 944 * | | |The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module.
sahilmgandhi 18:6a4db94011d3 945 * | | |User can use it to monitor the external analog input pin voltage status.
sahilmgandhi 18:6a4db94011d3 946 * | | |0 = Conversion result in EADC_DAT less than CMPDAT0 setting.
sahilmgandhi 18:6a4db94011d3 947 * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT0
sahilmgandhi 18:6a4db94011d3 948 * | | |setting.
sahilmgandhi 18:6a4db94011d3 949 * |[13] |ADCMPO1 |ADC Compare 1 Output Status
sahilmgandhi 18:6a4db94011d3 950 * | | |The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module.
sahilmgandhi 18:6a4db94011d3 951 * | | |User can use it to monitor the external analog input pin voltage status.
sahilmgandhi 18:6a4db94011d3 952 * | | |0 = Conversion result in EADC_DAT less than CMPDAT1 setting.
sahilmgandhi 18:6a4db94011d3 953 * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT1
sahilmgandhi 18:6a4db94011d3 954 * | | |setting.
sahilmgandhi 18:6a4db94011d3 955 * |[14] |ADCMPO2 |ADC Compare 2 Output Status
sahilmgandhi 18:6a4db94011d3 956 * | | |The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module.
sahilmgandhi 18:6a4db94011d3 957 * | | |User can use it to monitor the external analog input pin voltage status.
sahilmgandhi 18:6a4db94011d3 958 * | | |0 = Conversion result in EADC_DAT less than CMPDAT2 setting.
sahilmgandhi 18:6a4db94011d3 959 * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT2
sahilmgandhi 18:6a4db94011d3 960 * | | |setting.
sahilmgandhi 18:6a4db94011d3 961 * |[15] |ADCMPO3 |ADC Compare 3 Output Status
sahilmgandhi 18:6a4db94011d3 962 * | | |The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module.
sahilmgandhi 18:6a4db94011d3 963 * | | |User can use it to monitor the external analog input pin voltage status.
sahilmgandhi 18:6a4db94011d3 964 * | | |0 = Conversion result in EADC_DAT less than CMPDAT3 setting.
sahilmgandhi 18:6a4db94011d3 965 * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT3
sahilmgandhi 18:6a4db94011d3 966 * | | |setting.
sahilmgandhi 18:6a4db94011d3 967 * |[20:16] |CHANNEL |Current Conversion Channel
sahilmgandhi 18:6a4db94011d3 968 * | | |This filed reflects ADC current conversion channel when BUSY=1.
sahilmgandhi 18:6a4db94011d3 969 * | | |It is read only.
sahilmgandhi 18:6a4db94011d3 970 * | | |00H = EADC_CH0.
sahilmgandhi 18:6a4db94011d3 971 * | | |01H = EADC_CH1.
sahilmgandhi 18:6a4db94011d3 972 * | | |02H = EADC_CH2.
sahilmgandhi 18:6a4db94011d3 973 * | | |03H = EADC_CH3.
sahilmgandhi 18:6a4db94011d3 974 * | | |04H = EADC_CH4.
sahilmgandhi 18:6a4db94011d3 975 * | | |05H = EADC_CH5.
sahilmgandhi 18:6a4db94011d3 976 * | | |06H = EADC_CH6.
sahilmgandhi 18:6a4db94011d3 977 * | | |07H = EADC_CH7.
sahilmgandhi 18:6a4db94011d3 978 * | | |08H = EADC_CH8.
sahilmgandhi 18:6a4db94011d3 979 * | | |09H = EADC_CH9.
sahilmgandhi 18:6a4db94011d3 980 * | | |0AH = EADC_CH10.
sahilmgandhi 18:6a4db94011d3 981 * | | |0BH = EADC_CH11.
sahilmgandhi 18:6a4db94011d3 982 * | | |0CH = EADC_CH12.
sahilmgandhi 18:6a4db94011d3 983 * | | |0DH = EADC_CH13.
sahilmgandhi 18:6a4db94011d3 984 * | | |0EH = EADC_CH14.
sahilmgandhi 18:6a4db94011d3 985 * | | |0FH = EADC_CH15.
sahilmgandhi 18:6a4db94011d3 986 * | | |10H = VBG.
sahilmgandhi 18:6a4db94011d3 987 * | | |11H = VTEMP.
sahilmgandhi 18:6a4db94011d3 988 * | | |12H = VBAT.
sahilmgandhi 18:6a4db94011d3 989 * |[23] |BUSY |Busy/Idle
sahilmgandhi 18:6a4db94011d3 990 * | | |0 = EADC is in idle state.
sahilmgandhi 18:6a4db94011d3 991 * | | |1 = EADC is busy at conversion.
sahilmgandhi 18:6a4db94011d3 992 * | | |Note: This bit is read only.
sahilmgandhi 18:6a4db94011d3 993 * |[24] |ADOVIF |All A/D Interrupt Flag Overrun Bits Check
sahilmgandhi 18:6a4db94011d3 994 * | | |n=0~3.
sahilmgandhi 18:6a4db94011d3 995 * | | |0 = None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
sahilmgandhi 18:6a4db94011d3 996 * | | |1 = Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
sahilmgandhi 18:6a4db94011d3 997 * | | |Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1.
sahilmgandhi 18:6a4db94011d3 998 * |[25] |STOVF |For All A/D Sample Module Start Of Conversion Overrun Flags Check
sahilmgandhi 18:6a4db94011d3 999 * | | |n=0~18.
sahilmgandhi 18:6a4db94011d3 1000 * | | |0 = None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
sahilmgandhi 18:6a4db94011d3 1001 * | | |1 = Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
sahilmgandhi 18:6a4db94011d3 1002 * | | |Note: This bit will keep 1 when any SPOVFn Flag is equal to 1.
sahilmgandhi 18:6a4db94011d3 1003 * |[26] |AVALID |For All Sample Module A/D Result Data Register EADC_DAT Data Valid Flag Check
sahilmgandhi 18:6a4db94011d3 1004 * | | |n=0~18.
sahilmgandhi 18:6a4db94011d3 1005 * | | |0 = None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
sahilmgandhi 18:6a4db94011d3 1006 * | | |1 = Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
sahilmgandhi 18:6a4db94011d3 1007 * | | |Note: This bit will keep 1 when any VALIDn Flag is equal to 1.
sahilmgandhi 18:6a4db94011d3 1008 * |[27] |AOV |For All Sample Module A/D Result Data Register Overrun Flags Check
sahilmgandhi 18:6a4db94011d3 1009 * | | |n=0~18.
sahilmgandhi 18:6a4db94011d3 1010 * | | |0 = None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
sahilmgandhi 18:6a4db94011d3 1011 * | | |1 = Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
sahilmgandhi 18:6a4db94011d3 1012 * | | |Note: This bit will keep 1 when any OVn Flag is equal to 1.
sahilmgandhi 18:6a4db94011d3 1013 * @var EADC_T::STATUS3
sahilmgandhi 18:6a4db94011d3 1014 * Offset: 0xFC A/D Status Register 3
sahilmgandhi 18:6a4db94011d3 1015 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1016 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1017 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1018 * |[4:0] |CURSPL |ADC Current Sample Module
sahilmgandhi 18:6a4db94011d3 1019 * | | |This register show the current ADC is controlled by which sample module control logic modules.
sahilmgandhi 18:6a4db94011d3 1020 * | | |If the ADC is Idle, this bit filed will set to 0x1F.
sahilmgandhi 18:6a4db94011d3 1021 * | | |This is a read only register.
sahilmgandhi 18:6a4db94011d3 1022 * @var EADC_T::DDAT
sahilmgandhi 18:6a4db94011d3 1023 * Offset: 0x100-0x10C A/D Double Data Register n for Sample Module n, n=0~3
sahilmgandhi 18:6a4db94011d3 1024 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1025 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1026 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1027 * |[15:0] |RESULT |A/D Conversion Results
sahilmgandhi 18:6a4db94011d3 1028 * | | |This field contains 12 bits conversion results.
sahilmgandhi 18:6a4db94011d3 1029 * | | |When the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].
sahilmgandhi 18:6a4db94011d3 1030 * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12].
sahilmgandhi 18:6a4db94011d3 1031 * |[16] |OV |Overrun Flag
sahilmgandhi 18:6a4db94011d3 1032 * | | |0 = Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result.
sahilmgandhi 18:6a4db94011d3 1033 * | | |1 = Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite.
sahilmgandhi 18:6a4db94011d3 1034 * | | |If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1.
sahilmgandhi 18:6a4db94011d3 1035 * | | |It is cleared by hardware after EADC_DDAT register is read.
sahilmgandhi 18:6a4db94011d3 1036 * |[17] |VALID |Valid Flag
sahilmgandhi 18:6a4db94011d3 1037 * | | |0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid.
sahilmgandhi 18:6a4db94011d3 1038 * | | |1 = Double data in RESULT (EADC_DDATn[15:0]) is valid.
sahilmgandhi 18:6a4db94011d3 1039 * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read.
sahilmgandhi 18:6a4db94011d3 1040 * | | |(n=0~3).
sahilmgandhi 18:6a4db94011d3 1041 */
sahilmgandhi 18:6a4db94011d3 1042
sahilmgandhi 18:6a4db94011d3 1043 __I uint32_t DAT[19]; /* Offset: 0x00-0x48 A/D Data Register n for Sample Module n, n=0~18 */
sahilmgandhi 18:6a4db94011d3 1044 __I uint32_t CURDAT; /* Offset: 0x4C EADC PDMA Current Transfer Data Register */
sahilmgandhi 18:6a4db94011d3 1045 __IO uint32_t CTL; /* Offset: 0x50 A/D Control Register */
sahilmgandhi 18:6a4db94011d3 1046 __O uint32_t SWTRG; /* Offset: 0x54 A/D Sample Module Software Start Register */
sahilmgandhi 18:6a4db94011d3 1047 __IO uint32_t PENDSTS; /* Offset: 0x58 A/D Start of Conversion Pending Flag Register */
sahilmgandhi 18:6a4db94011d3 1048 __IO uint32_t OVSTS; /* Offset: 0x5C A/D Sample Module Start of Conversion Overrun Flag Register */
sahilmgandhi 18:6a4db94011d3 1049 __I uint32_t RESERVE0[8];
sahilmgandhi 18:6a4db94011d3 1050 __IO uint32_t SCTL[19]; /* Offset: 0x80-0xC8 A/D Sample Module n Control Register, n=0~3 */
sahilmgandhi 18:6a4db94011d3 1051 __I uint32_t RESERVE1[1];
sahilmgandhi 18:6a4db94011d3 1052 __IO uint32_t INTSRC[4]; /* Offset: 0xDC ADC interrupt n Source Enable Control Register, n=0~3 */
sahilmgandhi 18:6a4db94011d3 1053 __IO uint32_t CMP[4]; /* Offset: 0xEC A/D Result Compare Register n, n=0~3 */
sahilmgandhi 18:6a4db94011d3 1054 __I uint32_t STATUS0; /* Offset: 0xF0 A/D Status Register 0 */
sahilmgandhi 18:6a4db94011d3 1055 __I uint32_t STATUS1; /* Offset: 0xF4 A/D Status Register 1 */
sahilmgandhi 18:6a4db94011d3 1056 __IO uint32_t STATUS2; /* Offset: 0xF8 A/D Status Register 2 */
sahilmgandhi 18:6a4db94011d3 1057 __I uint32_t STATUS3; /* Offset: 0xFC A/D Status Register 3 */
sahilmgandhi 18:6a4db94011d3 1058 __I uint32_t DDAT[4]; /* Offset: 0x100-0x10C A/D Double Data Register n for Sample Module n, n=0~3 */
sahilmgandhi 18:6a4db94011d3 1059
sahilmgandhi 18:6a4db94011d3 1060 } EADC_T;
sahilmgandhi 18:6a4db94011d3 1061
sahilmgandhi 18:6a4db94011d3 1062
sahilmgandhi 18:6a4db94011d3 1063
sahilmgandhi 18:6a4db94011d3 1064 /**
sahilmgandhi 18:6a4db94011d3 1065 @addtogroup EADC_CONST EADC Bit Field Definition
sahilmgandhi 18:6a4db94011d3 1066 Constant Definitions for EADC Controller
sahilmgandhi 18:6a4db94011d3 1067 @{ */
sahilmgandhi 18:6a4db94011d3 1068 #define EADC_DAT_RESULT_Pos (0) /*!< EADC_T::DAT: RESULT Position */
sahilmgandhi 18:6a4db94011d3 1069 #define EADC_DAT_RESULT_Msk (0xfffful << EADC_DAT_RESULT_Pos) /*!< EADC_T::DAT: RESULT Mask */
sahilmgandhi 18:6a4db94011d3 1070
sahilmgandhi 18:6a4db94011d3 1071 #define EADC_DAT_OV_Pos (16) /*!< EADC_T::DAT: OV Position */
sahilmgandhi 18:6a4db94011d3 1072 #define EADC_DAT_OV_Msk (0x1ul << EADC_DAT_OV_Pos) /*!< EADC_T::DAT: OV Mask */
sahilmgandhi 18:6a4db94011d3 1073
sahilmgandhi 18:6a4db94011d3 1074 #define EADC_DAT_VALID_Pos (17) /*!< EADC_T::DAT: VALID Position */
sahilmgandhi 18:6a4db94011d3 1075 #define EADC_DAT_VALID_Msk (0x1ul << EADC_DAT_VALID_Pos) /*!< EADC_T::DAT: VALID Mask */
sahilmgandhi 18:6a4db94011d3 1076
sahilmgandhi 18:6a4db94011d3 1077 #define EADC_CURDAT_CURDAT_Pos (0) /*!< EADC_T::CURDAT: CURDAT Position */
sahilmgandhi 18:6a4db94011d3 1078 #define EADC_CURDAT_CURDAT_Msk (0x3fffful << EADC_CURDAT_CURDAT_Pos) /*!< EADC_T::CURDAT: CURDAT Mask */
sahilmgandhi 18:6a4db94011d3 1079
sahilmgandhi 18:6a4db94011d3 1080 #define EADC_CTL_ADCEN_Pos (0) /*!< EADC_T::CTL: ADCEN Position */
sahilmgandhi 18:6a4db94011d3 1081 #define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) /*!< EADC_T::CTL: ADCEN Mask */
sahilmgandhi 18:6a4db94011d3 1082
sahilmgandhi 18:6a4db94011d3 1083 #define EADC_CTL_ADRST_Pos (1) /*!< EADC_T::CTL: ADRST Position */
sahilmgandhi 18:6a4db94011d3 1084 #define EADC_CTL_ADRST_Msk (0x1ul << EADC_CTL_ADRST_Pos) /*!< EADC_T::CTL: ADRST Mask */
sahilmgandhi 18:6a4db94011d3 1085
sahilmgandhi 18:6a4db94011d3 1086 #define EADC_CTL_ADCIEN0_Pos (2) /*!< EADC_T::CTL: ADCIEN0 Position */
sahilmgandhi 18:6a4db94011d3 1087 #define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) /*!< EADC_T::CTL: ADCIEN0 Mask */
sahilmgandhi 18:6a4db94011d3 1088
sahilmgandhi 18:6a4db94011d3 1089 #define EADC_CTL_ADCIEN1_Pos (3) /*!< EADC_T::CTL: ADCIEN1 Position */
sahilmgandhi 18:6a4db94011d3 1090 #define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) /*!< EADC_T::CTL: ADCIEN1 Mask */
sahilmgandhi 18:6a4db94011d3 1091
sahilmgandhi 18:6a4db94011d3 1092 #define EADC_CTL_ADCIEN2_Pos (4) /*!< EADC_T::CTL: ADCIEN2 Position */
sahilmgandhi 18:6a4db94011d3 1093 #define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) /*!< EADC_T::CTL: ADCIEN2 Mask */
sahilmgandhi 18:6a4db94011d3 1094
sahilmgandhi 18:6a4db94011d3 1095 #define EADC_CTL_ADCIEN3_Pos (5) /*!< EADC_T::CTL: ADCIEN3 Position */
sahilmgandhi 18:6a4db94011d3 1096 #define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) /*!< EADC_T::CTL: ADCIEN3 Mask */
sahilmgandhi 18:6a4db94011d3 1097
sahilmgandhi 18:6a4db94011d3 1098 #define EADC_CTL_DIFFEN_Pos (8) /*!< EADC_T::CTL: DIFFEN Position */
sahilmgandhi 18:6a4db94011d3 1099 #define EADC_CTL_DIFFEN_Msk (0x1ul << EADC_CTL_DIFFEN_Pos) /*!< EADC_T::CTL: DIFFEN Mask */
sahilmgandhi 18:6a4db94011d3 1100
sahilmgandhi 18:6a4db94011d3 1101 #define EADC_CTL_DMOF_Pos (9) /*!< EADC_T::CTL: DMOF Position */
sahilmgandhi 18:6a4db94011d3 1102 #define EADC_CTL_DMOF_Msk (0x1ul << EADC_CTL_DMOF_Pos) /*!< EADC_T::CTL: DMOF Mask */
sahilmgandhi 18:6a4db94011d3 1103
sahilmgandhi 18:6a4db94011d3 1104 #define EADC_CTL_PDMAEN_Pos (11) /*!< EADC_T::CTL: PDMAEN Position */
sahilmgandhi 18:6a4db94011d3 1105 #define EADC_CTL_PDMAEN_Msk (0x1ul << EADC_CTL_PDMAEN_Pos) /*!< EADC_T::CTL: PDMAEN Mask */
sahilmgandhi 18:6a4db94011d3 1106
sahilmgandhi 18:6a4db94011d3 1107 #define EADC_CTL_SMPTSEL_Pos (16) /*!< EADC_T::CTL: SMPTSEL Position */
sahilmgandhi 18:6a4db94011d3 1108 #define EADC_CTL_SMPTSEL_Msk (0x7ul << EADC_CTL_SMPTSEL_Pos) /*!< EADC_T::CTL: SMPTSEL Mask */
sahilmgandhi 18:6a4db94011d3 1109
sahilmgandhi 18:6a4db94011d3 1110 #define EADC_SWTRG_SWTRG_Pos (0) /*!< EADC_T::SWTRG: SWTRG Position */
sahilmgandhi 18:6a4db94011d3 1111 #define EADC_SWTRG_SWTRG_Msk (0x7fffful << EADC_SWTRG_SWTRG_Pos) /*!< EADC_T::SWTRG: SWTRG Mask */
sahilmgandhi 18:6a4db94011d3 1112
sahilmgandhi 18:6a4db94011d3 1113 #define EADC_PENDSTS_STPF_Pos (0) /*!< EADC_T::PENDSTS: STPF Position */
sahilmgandhi 18:6a4db94011d3 1114 #define EADC_PENDSTS_STPF_Msk (0x7fffful << EADC_PENDSTS_STPF_Pos) /*!< EADC_T::PENDSTS: STPF Mask */
sahilmgandhi 18:6a4db94011d3 1115
sahilmgandhi 18:6a4db94011d3 1116 #define EADC_OVSTS_SPOVF_Pos (0) /*!< EADC_T::OVSTS: SPOVF Position */
sahilmgandhi 18:6a4db94011d3 1117 #define EADC_OVSTS_SPOVF_Msk (0x7fffful << EADC_OVSTS_SPOVF_Pos) /*!< EADC_T::OVSTS: SPOVF Mask */
sahilmgandhi 18:6a4db94011d3 1118
sahilmgandhi 18:6a4db94011d3 1119 #define EADC_SCTL_CHSEL_Pos (0) /*!< EADC_T::SCTL: CHSEL Position */
sahilmgandhi 18:6a4db94011d3 1120 #define EADC_SCTL_CHSEL_Msk (0xful << EADC_SCTL_CHSEL_Pos) /*!< EADC_T::SCTL: CHSEL Mask */
sahilmgandhi 18:6a4db94011d3 1121
sahilmgandhi 18:6a4db94011d3 1122 #define EADC_SCTL_EXTREN_Pos (4) /*!< EADC_T::SCTL: EXTREN Position */
sahilmgandhi 18:6a4db94011d3 1123 #define EADC_SCTL_EXTREN_Msk (0x1ul << EADC_SCTL_EXTREN_Pos) /*!< EADC_T::SCTL: EXTREN Mask */
sahilmgandhi 18:6a4db94011d3 1124
sahilmgandhi 18:6a4db94011d3 1125 #define EADC_SCTL_EXTFEN_Pos (5) /*!< EADC_T::SCTL: EXTFEN Position */
sahilmgandhi 18:6a4db94011d3 1126 #define EADC_SCTL_EXTFEN_Msk (0x1ul << EADC_SCTL_EXTFEN_Pos) /*!< EADC_T::SCTL: EXTFEN Mask */
sahilmgandhi 18:6a4db94011d3 1127
sahilmgandhi 18:6a4db94011d3 1128 #define EADC_SCTL_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL: TRGDLYDIV Position */
sahilmgandhi 18:6a4db94011d3 1129 #define EADC_SCTL_TRGDLYDIV_Msk (0x3ul << EADC_SCTL_TRGDLYDIV_Pos) /*!< EADC_T::SCTL: TRGDLYDIV Mask */
sahilmgandhi 18:6a4db94011d3 1130
sahilmgandhi 18:6a4db94011d3 1131 #define EADC_SCTL_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL: TRGDLYCNT Position */
sahilmgandhi 18:6a4db94011d3 1132 #define EADC_SCTL_TRGDLYCNT_Msk (0xfful << EADC_SCTL_TRGDLYCNT_Pos) /*!< EADC_T::SCTL: TRGDLYCNT Mask */
sahilmgandhi 18:6a4db94011d3 1133
sahilmgandhi 18:6a4db94011d3 1134 #define EADC_SCTL_TRGSEL_Pos (16) /*!< EADC_T::SCTL: TRGSEL Position */
sahilmgandhi 18:6a4db94011d3 1135 #define EADC_SCTL_TRGSEL_Msk (0x1ful << EADC_SCTL_TRGSEL_Pos) /*!< EADC_T::SCTL: TRGSEL Mask */
sahilmgandhi 18:6a4db94011d3 1136
sahilmgandhi 18:6a4db94011d3 1137 #define EADC_SCTL_INTPOS_Pos (22) /*!< EADC_T::SCTL: INTPOS Position */
sahilmgandhi 18:6a4db94011d3 1138 #define EADC_SCTL_INTPOS_Msk (0x1ul << EADC_SCTL_INTPOS_Pos) /*!< EADC_T::SCTL: INTPOS Mask */
sahilmgandhi 18:6a4db94011d3 1139
sahilmgandhi 18:6a4db94011d3 1140 #define EADC_SCTL_DBMEN_Pos (23) /*!< EADC_T::SCTL: DBMEN Position */
sahilmgandhi 18:6a4db94011d3 1141 #define EADC_SCTL_DBMEN_Msk (0x1ul << EADC_SCTL_DBMEN_Pos) /*!< EADC_T::SCTL: DBMEN Mask */
sahilmgandhi 18:6a4db94011d3 1142
sahilmgandhi 18:6a4db94011d3 1143 #define EADC_SCTL_EXTSMPT_Pos (24) /*!< EADC_T::SCTL: EXTSMPT Position */
sahilmgandhi 18:6a4db94011d3 1144 #define EADC_SCTL_EXTSMPT_Msk (0xfful << EADC_SCTL_EXTSMPT_Pos) /*!< EADC_T::SCTL: EXTSMPT Mask */
sahilmgandhi 18:6a4db94011d3 1145
sahilmgandhi 18:6a4db94011d3 1146 #define EADC_INTSRC_SPLIE_Pos (0) /*!< EADC_T::INTSRC: SPLIE Position */
sahilmgandhi 18:6a4db94011d3 1147 #define EADC_INTSRC_SPLIE_Msk (0x7FFFFul << EADC_INTSRC_SPLIE_Pos) /*!< EADC_T::INTSRC: SPLIE Mask */
sahilmgandhi 18:6a4db94011d3 1148
sahilmgandhi 18:6a4db94011d3 1149 #define EADC_CMP_ADCMPEN_Pos (0) /*!< EADC_T::CMP: ADCMPEN Position */
sahilmgandhi 18:6a4db94011d3 1150 #define EADC_CMP_ADCMPEN_Msk (0x1ul << EADC_CMP_ADCMPEN_Pos) /*!< EADC_T::CMP: ADCMPEN Mask */
sahilmgandhi 18:6a4db94011d3 1151
sahilmgandhi 18:6a4db94011d3 1152 #define EADC_CMP_ADCMPIE_Pos (1) /*!< EADC_T::CMP: ADCMPIE Position */
sahilmgandhi 18:6a4db94011d3 1153 #define EADC_CMP_ADCMPIE_Msk (0x1ul << EADC_CMP_ADCMPIE_Pos) /*!< EADC_T::CMP: ADCMPIE Mask */
sahilmgandhi 18:6a4db94011d3 1154
sahilmgandhi 18:6a4db94011d3 1155 #define EADC_CMP_CMPCOND_Pos (2) /*!< EADC_T::CMP: CMPCOND Position */
sahilmgandhi 18:6a4db94011d3 1156 #define EADC_CMP_CMPCOND_Msk (0x1ul << EADC_CMP_CMPCOND_Pos) /*!< EADC_T::CMP: CMPCOND Mask */
sahilmgandhi 18:6a4db94011d3 1157
sahilmgandhi 18:6a4db94011d3 1158 #define EADC_CMP_CMPSPL_Pos (3) /*!< EADC_T::CMP: CMPSPL Position */
sahilmgandhi 18:6a4db94011d3 1159 #define EADC_CMP_CMPSPL_Msk (0x1ful << EADC_CMP_CMPSPL_Pos) /*!< EADC_T::CMP: CMPSPL Mask */
sahilmgandhi 18:6a4db94011d3 1160
sahilmgandhi 18:6a4db94011d3 1161 #define EADC_CMP_CMPMCNT_Pos (8) /*!< EADC_T::CMP: CMPMCNT Position */
sahilmgandhi 18:6a4db94011d3 1162 #define EADC_CMP_CMPMCNT_Msk (0xful << EADC_CMP_CMPMCNT_Pos) /*!< EADC_T::CMP: CMPMCNT Mask */
sahilmgandhi 18:6a4db94011d3 1163
sahilmgandhi 18:6a4db94011d3 1164 #define EADC_CMP_CMPWEN_Pos (15) /*!< EADC_T::CMP: CMPWEN Position */
sahilmgandhi 18:6a4db94011d3 1165 #define EADC_CMP_CMPWEN_Msk (0x1ul << EADC_CMP_CMPWEN_Pos) /*!< EADC_T::CMP: CMPWEN Mask */
sahilmgandhi 18:6a4db94011d3 1166
sahilmgandhi 18:6a4db94011d3 1167 #define EADC_CMP_CMPDAT_Pos (16) /*!< EADC_T::CMP: CMPDAT Position */
sahilmgandhi 18:6a4db94011d3 1168 #define EADC_CMP_CMPDAT_Msk (0xffful << EADC_CMP_CMPDAT_Pos) /*!< EADC_T::CMP: CMPDAT Mask */
sahilmgandhi 18:6a4db94011d3 1169
sahilmgandhi 18:6a4db94011d3 1170 #define EADC_STATUS0_VALID_Pos (0) /*!< EADC_T::STATUS0: VALID Position */
sahilmgandhi 18:6a4db94011d3 1171 #define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) /*!< EADC_T::STATUS0: VALID Mask */
sahilmgandhi 18:6a4db94011d3 1172
sahilmgandhi 18:6a4db94011d3 1173 #define EADC_STATUS0_OV_Pos (16) /*!< EADC_T::STATUS0: OV Position */
sahilmgandhi 18:6a4db94011d3 1174 #define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) /*!< EADC_T::STATUS0: OV Mask */
sahilmgandhi 18:6a4db94011d3 1175
sahilmgandhi 18:6a4db94011d3 1176 #define EADC_STATUS1_VALID_Pos (0) /*!< EADC_T::STATUS1: VALID Position */
sahilmgandhi 18:6a4db94011d3 1177 #define EADC_STATUS1_VALID_Msk (0x7ul << EADC_STATUS1_VALID_Pos) /*!< EADC_T::STATUS1: VALID Mask */
sahilmgandhi 18:6a4db94011d3 1178
sahilmgandhi 18:6a4db94011d3 1179 #define EADC_STATUS1_OV_Pos (16) /*!< EADC_T::STATUS1: OV Position */
sahilmgandhi 18:6a4db94011d3 1180 #define EADC_STATUS1_OV_Msk (0x7ul << EADC_STATUS1_OV_Pos) /*!< EADC_T::STATUS1: OV Mask */
sahilmgandhi 18:6a4db94011d3 1181
sahilmgandhi 18:6a4db94011d3 1182 #define EADC_STATUS2_ADIF0_Pos (0) /*!< EADC_T::STATUS2: ADIF0 Position */
sahilmgandhi 18:6a4db94011d3 1183 #define EADC_STATUS2_ADIF0_Msk (0x1ul << EADC_STATUS2_ADIF0_Pos) /*!< EADC_T::STATUS2: ADIF0 Mask */
sahilmgandhi 18:6a4db94011d3 1184
sahilmgandhi 18:6a4db94011d3 1185 #define EADC_STATUS2_ADIF1_Pos (1) /*!< EADC_T::STATUS2: ADIF1 Position */
sahilmgandhi 18:6a4db94011d3 1186 #define EADC_STATUS2_ADIF1_Msk (0x1ul << EADC_STATUS2_ADIF1_Pos) /*!< EADC_T::STATUS2: ADIF1 Mask */
sahilmgandhi 18:6a4db94011d3 1187
sahilmgandhi 18:6a4db94011d3 1188 #define EADC_STATUS2_ADIF2_Pos (2) /*!< EADC_T::STATUS2: ADIF2 Position */
sahilmgandhi 18:6a4db94011d3 1189 #define EADC_STATUS2_ADIF2_Msk (0x1ul << EADC_STATUS2_ADIF2_Pos) /*!< EADC_T::STATUS2: ADIF2 Mask */
sahilmgandhi 18:6a4db94011d3 1190
sahilmgandhi 18:6a4db94011d3 1191 #define EADC_STATUS2_ADIF3_Pos (3) /*!< EADC_T::STATUS2: ADIF3 Position */
sahilmgandhi 18:6a4db94011d3 1192 #define EADC_STATUS2_ADIF3_Msk (0x1ul << EADC_STATUS2_ADIF3_Pos) /*!< EADC_T::STATUS2: ADIF3 Mask */
sahilmgandhi 18:6a4db94011d3 1193
sahilmgandhi 18:6a4db94011d3 1194 #define EADC_STATUS2_ADCMPF0_Pos (4) /*!< EADC_T::STATUS2: ADCMPF0 Position */
sahilmgandhi 18:6a4db94011d3 1195 #define EADC_STATUS2_ADCMPF0_Msk (0x1ul << EADC_STATUS2_ADCMPF0_Pos) /*!< EADC_T::STATUS2: ADCMPF0 Mask */
sahilmgandhi 18:6a4db94011d3 1196
sahilmgandhi 18:6a4db94011d3 1197 #define EADC_STATUS2_ADCMPF1_Pos (5) /*!< EADC_T::STATUS2: ADCMPF1 Position */
sahilmgandhi 18:6a4db94011d3 1198 #define EADC_STATUS2_ADCMPF1_Msk (0x1ul << EADC_STATUS2_ADCMPF1_Pos) /*!< EADC_T::STATUS2: ADCMPF1 Mask */
sahilmgandhi 18:6a4db94011d3 1199
sahilmgandhi 18:6a4db94011d3 1200 #define EADC_STATUS2_ADCMPF2_Pos (6) /*!< EADC_T::STATUS2: ADCMPF2 Position */
sahilmgandhi 18:6a4db94011d3 1201 #define EADC_STATUS2_ADCMPF2_Msk (0x1ul << EADC_STATUS2_ADCMPF2_Pos) /*!< EADC_T::STATUS2: ADCMPF2 Mask */
sahilmgandhi 18:6a4db94011d3 1202
sahilmgandhi 18:6a4db94011d3 1203 #define EADC_STATUS2_ADCMPF3_Pos (7) /*!< EADC_T::STATUS2: ADCMPF3 Position */
sahilmgandhi 18:6a4db94011d3 1204 #define EADC_STATUS2_ADCMPF3_Msk (0x1ul << EADC_STATUS2_ADCMPF3_Pos) /*!< EADC_T::STATUS2: ADCMPF3 Mask */
sahilmgandhi 18:6a4db94011d3 1205
sahilmgandhi 18:6a4db94011d3 1206 #define EADC_STATUS2_ADOVIF0_Pos (8) /*!< EADC_T::STATUS2: ADOVIF0 Position */
sahilmgandhi 18:6a4db94011d3 1207 #define EADC_STATUS2_ADOVIF0_Msk (0x1ul << EADC_STATUS2_ADOVIF0_Pos) /*!< EADC_T::STATUS2: ADOVIF0 Mask */
sahilmgandhi 18:6a4db94011d3 1208
sahilmgandhi 18:6a4db94011d3 1209 #define EADC_STATUS2_ADOVIF1_Pos (9) /*!< EADC_T::STATUS2: ADOVIF1 Position */
sahilmgandhi 18:6a4db94011d3 1210 #define EADC_STATUS2_ADOVIF1_Msk (0x1ul << EADC_STATUS2_ADOVIF1_Pos) /*!< EADC_T::STATUS2: ADOVIF1 Mask */
sahilmgandhi 18:6a4db94011d3 1211
sahilmgandhi 18:6a4db94011d3 1212 #define EADC_STATUS2_ADOVIF2_Pos (10) /*!< EADC_T::STATUS2: ADOVIF2 Position */
sahilmgandhi 18:6a4db94011d3 1213 #define EADC_STATUS2_ADOVIF2_Msk (0x1ul << EADC_STATUS2_ADOVIF2_Pos) /*!< EADC_T::STATUS2: ADOVIF2 Mask */
sahilmgandhi 18:6a4db94011d3 1214
sahilmgandhi 18:6a4db94011d3 1215 #define EADC_STATUS2_ADOVIF3_Pos (11) /*!< EADC_T::STATUS2: ADOVIF3 Position */
sahilmgandhi 18:6a4db94011d3 1216 #define EADC_STATUS2_ADOVIF3_Msk (0x1ul << EADC_STATUS2_ADOVIF3_Pos) /*!< EADC_T::STATUS2: ADOVIF3 Mask */
sahilmgandhi 18:6a4db94011d3 1217
sahilmgandhi 18:6a4db94011d3 1218 #define EADC_STATUS2_ADCMPO0_Pos (12) /*!< EADC_T::STATUS2: ADCMPO0 Position */
sahilmgandhi 18:6a4db94011d3 1219 #define EADC_STATUS2_ADCMPO0_Msk (0x1ul << EADC_STATUS2_ADCMPO0_Pos) /*!< EADC_T::STATUS2: ADCMPO0 Mask */
sahilmgandhi 18:6a4db94011d3 1220
sahilmgandhi 18:6a4db94011d3 1221 #define EADC_STATUS2_ADCMPO1_Pos (13) /*!< EADC_T::STATUS2: ADCMPO1 Position */
sahilmgandhi 18:6a4db94011d3 1222 #define EADC_STATUS2_ADCMPO1_Msk (0x1ul << EADC_STATUS2_ADCMPO1_Pos) /*!< EADC_T::STATUS2: ADCMPO1 Mask */
sahilmgandhi 18:6a4db94011d3 1223
sahilmgandhi 18:6a4db94011d3 1224 #define EADC_STATUS2_ADCMPO2_Pos (14) /*!< EADC_T::STATUS2: ADCMPO2 Position */
sahilmgandhi 18:6a4db94011d3 1225 #define EADC_STATUS2_ADCMPO2_Msk (0x1ul << EADC_STATUS2_ADCMPO2_Pos) /*!< EADC_T::STATUS2: ADCMPO2 Mask */
sahilmgandhi 18:6a4db94011d3 1226
sahilmgandhi 18:6a4db94011d3 1227 #define EADC_STATUS2_ADCMPO3_Pos (15) /*!< EADC_T::STATUS2: ADCMPO3 Position */
sahilmgandhi 18:6a4db94011d3 1228 #define EADC_STATUS2_ADCMPO3_Msk (0x1ul << EADC_STATUS2_ADCMPO3_Pos) /*!< EADC_T::STATUS2: ADCMPO3 Mask */
sahilmgandhi 18:6a4db94011d3 1229
sahilmgandhi 18:6a4db94011d3 1230 #define EADC_STATUS2_CHANNEL_Pos (16) /*!< EADC_T::STATUS2: CHANNEL Position */
sahilmgandhi 18:6a4db94011d3 1231 #define EADC_STATUS2_CHANNEL_Msk (0x1ful << EADC_STATUS2_CHANNEL_Pos) /*!< EADC_T::STATUS2: CHANNEL Mask */
sahilmgandhi 18:6a4db94011d3 1232
sahilmgandhi 18:6a4db94011d3 1233 #define EADC_STATUS2_BUSY_Pos (23) /*!< EADC_T::STATUS2: BUSY Position */
sahilmgandhi 18:6a4db94011d3 1234 #define EADC_STATUS2_BUSY_Msk (0x1ul << EADC_STATUS2_BUSY_Pos) /*!< EADC_T::STATUS2: BUSY Mask */
sahilmgandhi 18:6a4db94011d3 1235
sahilmgandhi 18:6a4db94011d3 1236 #define EADC_STATUS2_ADOVIF_Pos (24) /*!< EADC_T::STATUS2: ADOVIF Position */
sahilmgandhi 18:6a4db94011d3 1237 #define EADC_STATUS2_ADOVIF_Msk (0x1ul << EADC_STATUS2_ADOVIF_Pos) /*!< EADC_T::STATUS2: ADOVIF Mask */
sahilmgandhi 18:6a4db94011d3 1238
sahilmgandhi 18:6a4db94011d3 1239 #define EADC_STATUS2_STOVF_Pos (25) /*!< EADC_T::STATUS2: STOVF Position */
sahilmgandhi 18:6a4db94011d3 1240 #define EADC_STATUS2_STOVF_Msk (0x1ul << EADC_STATUS2_STOVF_Pos) /*!< EADC_T::STATUS2: STOVF Mask */
sahilmgandhi 18:6a4db94011d3 1241
sahilmgandhi 18:6a4db94011d3 1242 #define EADC_STATUS2_AVALID_Pos (26) /*!< EADC_T::STATUS2: AVALID Position */
sahilmgandhi 18:6a4db94011d3 1243 #define EADC_STATUS2_AVALID_Msk (0x1ul << EADC_STATUS2_AVALID_Pos) /*!< EADC_T::STATUS2: AVALID Mask */
sahilmgandhi 18:6a4db94011d3 1244
sahilmgandhi 18:6a4db94011d3 1245 #define EADC_STATUS2_AOV_Pos (27) /*!< EADC_T::STATUS2: AOV Position */
sahilmgandhi 18:6a4db94011d3 1246 #define EADC_STATUS2_AOV_Msk (0x1ul << EADC_STATUS2_AOV_Pos) /*!< EADC_T::STATUS2: AOV Mask */
sahilmgandhi 18:6a4db94011d3 1247
sahilmgandhi 18:6a4db94011d3 1248 #define EADC_STATUS3_CURSPL_Pos (0) /*!< EADC_T::STATUS3: CURSPL Position */
sahilmgandhi 18:6a4db94011d3 1249 #define EADC_STATUS3_CURSPL_Msk (0x1ful << EADC_STATUS3_CURSPL_Pos) /*!< EADC_T::STATUS3: CURSPL Mask */
sahilmgandhi 18:6a4db94011d3 1250
sahilmgandhi 18:6a4db94011d3 1251 #define EADC_DDAT_RESULT_Pos (0) /*!< EADC_T::DDAT: RESULT Position */
sahilmgandhi 18:6a4db94011d3 1252 #define EADC_DDAT_RESULT_Msk (0xfffful << EADC_DDAT_RESULT_Pos) /*!< EADC_T::DDAT: RESULT Mask */
sahilmgandhi 18:6a4db94011d3 1253
sahilmgandhi 18:6a4db94011d3 1254 #define EADC_DDAT_OV_Pos (16) /*!< EADC_T::DDAT: OV Position */
sahilmgandhi 18:6a4db94011d3 1255 #define EADC_DDAT_OV_Msk (0x1ul << EADC_DDAT_OV_Pos) /*!< EADC_T::DDAT: OV Mask */
sahilmgandhi 18:6a4db94011d3 1256
sahilmgandhi 18:6a4db94011d3 1257 #define EADC_DDAT_VALID_Pos (17) /*!< EADC_T::DDAT: VALID Position */
sahilmgandhi 18:6a4db94011d3 1258 #define EADC_DDAT_VALID_Msk (0x1ul << EADC_DDAT_VALID_Pos) /*!< EADC_T::DDAT: VALID Mask */
sahilmgandhi 18:6a4db94011d3 1259
sahilmgandhi 18:6a4db94011d3 1260
sahilmgandhi 18:6a4db94011d3 1261 /**@}*/ /* EADC_CONST */
sahilmgandhi 18:6a4db94011d3 1262 /**@}*/ /* end of EADC register group */
sahilmgandhi 18:6a4db94011d3 1263
sahilmgandhi 18:6a4db94011d3 1264
sahilmgandhi 18:6a4db94011d3 1265 /*---------------------- Controller Area Network Controller -------------------------*/
sahilmgandhi 18:6a4db94011d3 1266 /**
sahilmgandhi 18:6a4db94011d3 1267 @addtogroup CAN Controller Area Network Controller(CAN)
sahilmgandhi 18:6a4db94011d3 1268 Memory Mapped Structure for CAN Controller
sahilmgandhi 18:6a4db94011d3 1269 @{ */
sahilmgandhi 18:6a4db94011d3 1270
sahilmgandhi 18:6a4db94011d3 1271
sahilmgandhi 18:6a4db94011d3 1272 typedef struct
sahilmgandhi 18:6a4db94011d3 1273 {
sahilmgandhi 18:6a4db94011d3 1274
sahilmgandhi 18:6a4db94011d3 1275
sahilmgandhi 18:6a4db94011d3 1276
sahilmgandhi 18:6a4db94011d3 1277 /**
sahilmgandhi 18:6a4db94011d3 1278 * @var CAN_IF_T::CREQ
sahilmgandhi 18:6a4db94011d3 1279 * Offset: 0x20, 0x80 IFn (Register Map Note 2) Command Request Registers
sahilmgandhi 18:6a4db94011d3 1280 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1281 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1282 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1283 * |[5:0] |MessageNumber|Message Number
sahilmgandhi 18:6a4db94011d3 1284 * | | |0x01-0x20: Valid Message Number, the Message Object in the Message
sahilmgandhi 18:6a4db94011d3 1285 * | | |RAM is selected for data transfer.
sahilmgandhi 18:6a4db94011d3 1286 * | | |0x00: Not a valid Message Number, interpreted as 0x20.
sahilmgandhi 18:6a4db94011d3 1287 * | | |0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F.
sahilmgandhi 18:6a4db94011d3 1288 * |[15] |Busy |Busy Flag
sahilmgandhi 18:6a4db94011d3 1289 * | | |0 = Read/write action has finished.
sahilmgandhi 18:6a4db94011d3 1290 * | | |1 = Writing to the IFn Command Request Register is in progress.
sahilmgandhi 18:6a4db94011d3 1291 * | | |This bit can only be read by the software.
sahilmgandhi 18:6a4db94011d3 1292 * @var CAN_IF_T::CMASK
sahilmgandhi 18:6a4db94011d3 1293 * Offset: 0x24, 0x84 IFn Command Mask Register
sahilmgandhi 18:6a4db94011d3 1294 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1295 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1296 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1297 * |[0] |DAT_B |Access Data Bytes [7:4]
sahilmgandhi 18:6a4db94011d3 1298 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 1299 * | | |0 = Data Bytes [7:4] unchanged.
sahilmgandhi 18:6a4db94011d3 1300 * | | |1 = Transfer Data Bytes [7:4] to Message Object.
sahilmgandhi 18:6a4db94011d3 1301 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 1302 * | | |0 = Data Bytes [7:4] unchanged.
sahilmgandhi 18:6a4db94011d3 1303 * | | |1 = Transfer Data Bytes [7:4] to IFn Message Buffer Register.
sahilmgandhi 18:6a4db94011d3 1304 * |[1] |DAT_A |Access Data Bytes [3:0]
sahilmgandhi 18:6a4db94011d3 1305 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 1306 * | | |0 = Data Bytes [3:0] unchanged.
sahilmgandhi 18:6a4db94011d3 1307 * | | |1 = Transfer Data Bytes [3:0] to Message Object.
sahilmgandhi 18:6a4db94011d3 1308 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 1309 * | | |0 = Data Bytes [3:0] unchanged.
sahilmgandhi 18:6a4db94011d3 1310 * | | |1 = Transfer Data Bytes [3:0] to IFn Message Buffer Register.
sahilmgandhi 18:6a4db94011d3 1311 * |[2] |TxRqst_NewDat|Access Transmission Request Bit When Write Operation
sahilmgandhi 18:6a4db94011d3 1312 * | | |0 = TxRqst bit unchanged.
sahilmgandhi 18:6a4db94011d3 1313 * | | |1 = Set TxRqst bit.
sahilmgandhi 18:6a4db94011d3 1314 * | | |Note: If a transmission is requested by programming bit TxRqst/NewDat in the IFn Command Mask Register, bit TxRqst in the IFn Message Control Register will be ignored.
sahilmgandhi 18:6a4db94011d3 1315 * | | |Access New Data Bit when Read Operation.
sahilmgandhi 18:6a4db94011d3 1316 * | | |0 = NewDat bit remains unchanged.
sahilmgandhi 18:6a4db94011d3 1317 * | | |1 = Clear NewDat bit in the Message Object.
sahilmgandhi 18:6a4db94011d3 1318 * | | |Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat.
sahilmgandhi 18:6a4db94011d3 1319 * | | |The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits.
sahilmgandhi 18:6a4db94011d3 1320 * |[3] |ClrIntPnd |Clear Interrupt Pending Bit
sahilmgandhi 18:6a4db94011d3 1321 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 1322 * | | |When writing to a Message Object, this bit is ignored.
sahilmgandhi 18:6a4db94011d3 1323 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 1324 * | | |0 = IntPnd bit (CAN_IFn_MCON[13]) remains unchanged.
sahilmgandhi 18:6a4db94011d3 1325 * | | |1 = Clear IntPnd bit in the Message Object.
sahilmgandhi 18:6a4db94011d3 1326 * |[4] |Control |Control Access Control Bits
sahilmgandhi 18:6a4db94011d3 1327 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 1328 * | | |0 = Control Bits unchanged.
sahilmgandhi 18:6a4db94011d3 1329 * | | |1 = Transfer Control Bits to Message Object.
sahilmgandhi 18:6a4db94011d3 1330 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 1331 * | | |0 = Control Bits unchanged.
sahilmgandhi 18:6a4db94011d3 1332 * | | |1 = Transfer Control Bits to IFn Message Buffer Register.
sahilmgandhi 18:6a4db94011d3 1333 * |[5] |Arb |Access Arbitration Bits
sahilmgandhi 18:6a4db94011d3 1334 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 1335 * | | |0 = Arbitration bits unchanged.
sahilmgandhi 18:6a4db94011d3 1336 * | | |1 = Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_APB2[15]) to Message Object.
sahilmgandhi 18:6a4db94011d3 1337 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 1338 * | | |0 = Arbitration bits unchanged.
sahilmgandhi 18:6a4db94011d3 1339 * | | |1 = Transfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register.
sahilmgandhi 18:6a4db94011d3 1340 * |[6] |Mask |Access Mask Bits
sahilmgandhi 18:6a4db94011d3 1341 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 1342 * | | |0 = Mask bits unchanged.
sahilmgandhi 18:6a4db94011d3 1343 * | | |1 = Transfer Identifier Mask + MDir + MXtd to Message Object.
sahilmgandhi 18:6a4db94011d3 1344 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 1345 * | | |0 = Mask bits unchanged.
sahilmgandhi 18:6a4db94011d3 1346 * | | |1 = Transfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register.
sahilmgandhi 18:6a4db94011d3 1347 * |[7] |WR_RD |Write / Read Mode
sahilmgandhi 18:6a4db94011d3 1348 * | | |0 = Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers.
sahilmgandhi 18:6a4db94011d3 1349 * | | |1 = Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register.
sahilmgandhi 18:6a4db94011d3 1350 * @var CAN_IF_T::MASK1
sahilmgandhi 18:6a4db94011d3 1351 * Offset: 0x28, 0x88 IFn Mask 1 Register
sahilmgandhi 18:6a4db94011d3 1352 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1353 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1354 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1355 * |[15:0] |Msk[15:0] |Identifier Mask 15-0
sahilmgandhi 18:6a4db94011d3 1356 * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
sahilmgandhi 18:6a4db94011d3 1357 * | | |1 = The corresponding identifier bit is used for acceptance filtering.
sahilmgandhi 18:6a4db94011d3 1358 * @var CAN_IF_T::MASK2
sahilmgandhi 18:6a4db94011d3 1359 * Offset: 0x2C, 0x8C IFn Mask 2 Register
sahilmgandhi 18:6a4db94011d3 1360 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1361 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1362 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1363 * |[12:0] |Msk[28:16]|Identifier Mask 28-16
sahilmgandhi 18:6a4db94011d3 1364 * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
sahilmgandhi 18:6a4db94011d3 1365 * | | |1 = The corresponding identifier bit is used for acceptance filtering.
sahilmgandhi 18:6a4db94011d3 1366 * |[14] |MDir |Mask Message Direction
sahilmgandhi 18:6a4db94011d3 1367 * | | |0 = The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering.
sahilmgandhi 18:6a4db94011d3 1368 * | | |1 = The message direction bit (Dir) is used for acceptance filtering.
sahilmgandhi 18:6a4db94011d3 1369 * |[15] |MXtd |Mask Extended Identifier
sahilmgandhi 18:6a4db94011d3 1370 * | | |0 = The extended identifier bit (IDE) has no effect on the acceptance filtering.
sahilmgandhi 18:6a4db94011d3 1371 * | | |1 = The extended identifier bit (IDE) is used for acceptance filtering.
sahilmgandhi 18:6a4db94011d3 1372 * | | |Note: When 11-bit ("standard") Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]).
sahilmgandhi 18:6a4db94011d3 1373 * | | |For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered.
sahilmgandhi 18:6a4db94011d3 1374 * @var CAN_IF_T::ARB1
sahilmgandhi 18:6a4db94011d3 1375 * Offset: 0x30, 0x90 IFn Arbitration 1 Register
sahilmgandhi 18:6a4db94011d3 1376 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1377 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1378 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1379 * |[15:0] |ID[15:0] |Message Identifier 15-0
sahilmgandhi 18:6a4db94011d3 1380 * | | |ID28 - ID0, 29-bit Identifier ("Extended Frame").
sahilmgandhi 18:6a4db94011d3 1381 * | | |ID28 - ID18, 11-bit Identifier ("Standard Frame")
sahilmgandhi 18:6a4db94011d3 1382 * @var CAN_IF_T::ARB2
sahilmgandhi 18:6a4db94011d3 1383 * Offset: 0x34, 0x94 IFn Arbitration 2 Register
sahilmgandhi 18:6a4db94011d3 1384 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1385 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1386 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1387 * |[12:0] |ID[28:16] |Message Identifier 28-16
sahilmgandhi 18:6a4db94011d3 1388 * | | |ID28 - ID0, 29-bit Identifier ("Extended Frame").
sahilmgandhi 18:6a4db94011d3 1389 * | | |ID28 - ID18, 11-bit Identifier ("Standard Frame")
sahilmgandhi 18:6a4db94011d3 1390 * |[13] |Dir |Message Direction
sahilmgandhi 18:6a4db94011d3 1391 * | | |0 = Direction is receive.
sahilmgandhi 18:6a4db94011d3 1392 * | | |On TxRqst, a Remote Frame with the identifier of this Message Object is transmitted.
sahilmgandhi 18:6a4db94011d3 1393 * | | |On reception of a Data Frame with matching identifier, that message is stored in this Message Object.
sahilmgandhi 18:6a4db94011d3 1394 * | | |1 = Direction is transmit.
sahilmgandhi 18:6a4db94011d3 1395 * | | |On TxRqst, the respective Message Object is transmitted as a Data Frame.
sahilmgandhi 18:6a4db94011d3 1396 * | | |On reception of a Remote Frame with matching identifier, the TxRqst bit (CAN_IFn_CMASK[2]) of this Message Object is set (if RmtEn (CAN_IFn_MCON[9]) = one).
sahilmgandhi 18:6a4db94011d3 1397 * |[14] |Xtd |Extended Identifier
sahilmgandhi 18:6a4db94011d3 1398 * | | |0 = The 11-bit ("standard") Identifier will be used for this Message Object.
sahilmgandhi 18:6a4db94011d3 1399 * | | |1 = The 29-bit ("extended") Identifier will be used for this Message Object.
sahilmgandhi 18:6a4db94011d3 1400 * |[15] |MsgVal |Message Valid
sahilmgandhi 18:6a4db94011d3 1401 * | | |0 = The Message Object is ignored by the Message Handler.
sahilmgandhi 18:6a4db94011d3 1402 * | | |1 = The Message Object is configured and should be considered by the Message Handler.
sahilmgandhi 18:6a4db94011d3 1403 * | | |Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]).
sahilmgandhi 18:6a4db94011d3 1404 * | | |This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_APB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required.
sahilmgandhi 18:6a4db94011d3 1405 * @var CAN_IF_T::MCON
sahilmgandhi 18:6a4db94011d3 1406 * Offset: 0x38, 0x98 IFn Message Control Register
sahilmgandhi 18:6a4db94011d3 1407 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1408 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1409 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1410 * |[3:0] |DLC |Data Length Code
sahilmgandhi 18:6a4db94011d3 1411 * | | |0-8: Data Frame has 0-8 data bytes.
sahilmgandhi 18:6a4db94011d3 1412 * | | |9-15: Data Frame has 8 data bytes
sahilmgandhi 18:6a4db94011d3 1413 * | | |Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes.
sahilmgandhi 18:6a4db94011d3 1414 * | | |When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.
sahilmgandhi 18:6a4db94011d3 1415 * | | |Data 0: 1st data byte of a CAN Data Frame
sahilmgandhi 18:6a4db94011d3 1416 * | | |Data 1: 2nd data byte of a CAN Data Frame
sahilmgandhi 18:6a4db94011d3 1417 * | | |Data 2: 3rd data byte of a CAN Data Frame
sahilmgandhi 18:6a4db94011d3 1418 * | | |Data 3: 4th data byte of a CAN Data Frame
sahilmgandhi 18:6a4db94011d3 1419 * | | |Data 4: 5th data byte of a CAN Data Frame
sahilmgandhi 18:6a4db94011d3 1420 * | | |Data 5: 6th data byte of a CAN Data Frame
sahilmgandhi 18:6a4db94011d3 1421 * | | |Data 6: 7th data byte of a CAN Data Frame
sahilmgandhi 18:6a4db94011d3 1422 * | | |Data 7 : 8th data byte of a CAN Data Frame
sahilmgandhi 18:6a4db94011d3 1423 * | | |Note: The Data 0 Byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data 7 byte is the last.
sahilmgandhi 18:6a4db94011d3 1424 * | | |When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object.
sahilmgandhi 18:6a4db94011d3 1425 * | | |If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values.
sahilmgandhi 18:6a4db94011d3 1426 * |[7] |EoB |End Of Buffer
sahilmgandhi 18:6a4db94011d3 1427 * | | |0 = Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer.
sahilmgandhi 18:6a4db94011d3 1428 * | | |1 = Single Message Object or last Message Object of a FIFO Buffer.
sahilmgandhi 18:6a4db94011d3 1429 * | | |Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer.
sahilmgandhi 18:6a4db94011d3 1430 * | | |For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one.
sahilmgandhi 18:6a4db94011d3 1431 * |[8] |TxRqst |Transmit Request
sahilmgandhi 18:6a4db94011d3 1432 * | | |0 = This Message Object is not waiting for transmission.
sahilmgandhi 18:6a4db94011d3 1433 * | | |1 = The transmission of this Message Object is requested and is not yet done.
sahilmgandhi 18:6a4db94011d3 1434 * |[9] |RmtEn |Remote Enable Control
sahilmgandhi 18:6a4db94011d3 1435 * | | |0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged.
sahilmgandhi 18:6a4db94011d3 1436 * | | |1 = At the reception of a Remote Frame, TxRqst is set.
sahilmgandhi 18:6a4db94011d3 1437 * |[10] |RxIE |Receive Interrupt Enable Control
sahilmgandhi 18:6a4db94011d3 1438 * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame.
sahilmgandhi 18:6a4db94011d3 1439 * | | |1 = IntPnd will be set after a successful reception of a frame.
sahilmgandhi 18:6a4db94011d3 1440 * |[11] |TxIE |Transmit Interrupt Enable Control
sahilmgandhi 18:6a4db94011d3 1441 * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame.
sahilmgandhi 18:6a4db94011d3 1442 * | | |1 = IntPnd will be set after a successful transmission of a frame.
sahilmgandhi 18:6a4db94011d3 1443 * |[12] |UMask |Use Acceptance Mask
sahilmgandhi 18:6a4db94011d3 1444 * | | |0 = Mask ignored.
sahilmgandhi 18:6a4db94011d3 1445 * | | |1 = Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering.
sahilmgandhi 18:6a4db94011d3 1446 * | | |Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_APB2[15]) is set to one.
sahilmgandhi 18:6a4db94011d3 1447 * |[13] |IntPnd |Interrupt Pending
sahilmgandhi 18:6a4db94011d3 1448 * | | |0 = This message object is not the source of an interrupt.
sahilmgandhi 18:6a4db94011d3 1449 * | | |1 = This message object is the source of an interrupt.
sahilmgandhi 18:6a4db94011d3 1450 * | | |The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.
sahilmgandhi 18:6a4db94011d3 1451 * |[14] |MsgLst |Message Lost (only valid for Message Objects with direction = receive).
sahilmgandhi 18:6a4db94011d3 1452 * | | |0 = No message lost since last time this bit was reset by the CPU.
sahilmgandhi 18:6a4db94011d3 1453 * | | |1 = The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message.
sahilmgandhi 18:6a4db94011d3 1454 * |[15] |NewDat |New Data
sahilmgandhi 18:6a4db94011d3 1455 * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software.
sahilmgandhi 18:6a4db94011d3 1456 * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
sahilmgandhi 18:6a4db94011d3 1457 * @var CAN_IF_T::DAT_A1
sahilmgandhi 18:6a4db94011d3 1458 * Offset: 0x3C, 0x9C IFn Data A1 Register (Register Map Note 3)
sahilmgandhi 18:6a4db94011d3 1459 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1460 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1461 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1462 * |[7:0] |Data0 |Data Byte 0
sahilmgandhi 18:6a4db94011d3 1463 * | | |1st data byte of a CAN Data Frame
sahilmgandhi 18:6a4db94011d3 1464 * |[15:8] |Data1 |Data Byte 1
sahilmgandhi 18:6a4db94011d3 1465 * | | |2nd data byte of a CAN Data Frame
sahilmgandhi 18:6a4db94011d3 1466 * @var CAN_IF_T::DAT_A2
sahilmgandhi 18:6a4db94011d3 1467 * Offset: 0x40, 0xA0 IFn Data A2 Register (Register Map Note 3)
sahilmgandhi 18:6a4db94011d3 1468 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1469 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1470 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1471 * |[7:0] |Data2 |Data Byte 2
sahilmgandhi 18:6a4db94011d3 1472 * | | |3rd data byte of CAN Data Frame
sahilmgandhi 18:6a4db94011d3 1473 * |[15:8] |Data3 |Data Byte 3
sahilmgandhi 18:6a4db94011d3 1474 * | | |4th data byte of CAN Data Frame
sahilmgandhi 18:6a4db94011d3 1475 * @var CAN_IF_T::DAT_B1
sahilmgandhi 18:6a4db94011d3 1476 * Offset: 0x44, 0xA4 IFn Data B1 Register (Register Map Note 3)
sahilmgandhi 18:6a4db94011d3 1477 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1478 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1479 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1480 * |[7:0] |Data4 |Data Byte 4
sahilmgandhi 18:6a4db94011d3 1481 * | | |5th data byte of CAN Data Frame
sahilmgandhi 18:6a4db94011d3 1482 * |[15:8] |Data5 |Data Byte 5
sahilmgandhi 18:6a4db94011d3 1483 * | | |6th data byte of CAN Data Frame
sahilmgandhi 18:6a4db94011d3 1484 * @var CAN_IF_T::DAT_B2
sahilmgandhi 18:6a4db94011d3 1485 * Offset: 0x48, 0xA8 IFn Data B2 Register (Register Map Note 3)
sahilmgandhi 18:6a4db94011d3 1486 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1487 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1488 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1489 * |[7:0] |Data6 |Data Byte 6
sahilmgandhi 18:6a4db94011d3 1490 * | | |7th data byte of CAN Data Frame.
sahilmgandhi 18:6a4db94011d3 1491 * |[15:8] |Data7 |Data Byte 7
sahilmgandhi 18:6a4db94011d3 1492 * | | |8th data byte of CAN Data Frame.
sahilmgandhi 18:6a4db94011d3 1493 */
sahilmgandhi 18:6a4db94011d3 1494
sahilmgandhi 18:6a4db94011d3 1495 __IO uint32_t CREQ; /* Offset: 0x20, 0x80 IFn (Register Map Note 2) Command Request Registers */
sahilmgandhi 18:6a4db94011d3 1496 __IO uint32_t CMASK; /* Offset: 0x24, 0x84 IFn Command Mask Register */
sahilmgandhi 18:6a4db94011d3 1497 __IO uint32_t MASK1; /* Offset: 0x28, 0x88 IFn Mask 1 Register */
sahilmgandhi 18:6a4db94011d3 1498 __IO uint32_t MASK2; /* Offset: 0x2C, 0x8C IFn Mask 2 Register */
sahilmgandhi 18:6a4db94011d3 1499 __IO uint32_t ARB1; /* Offset: 0x30, 0x90 IFn Arbitration 1 Register */
sahilmgandhi 18:6a4db94011d3 1500 __IO uint32_t ARB2; /* Offset: 0x34, 0x94 IFn Arbitration 2 Register */
sahilmgandhi 18:6a4db94011d3 1501 __IO uint32_t MCON; /* Offset: 0x38, 0x98 IFn Message Control Register */
sahilmgandhi 18:6a4db94011d3 1502 __IO uint32_t DAT_A1; /* Offset: 0x3C, 0x9C IFn Data A1 Register (Register Map Note 3) */
sahilmgandhi 18:6a4db94011d3 1503 __IO uint32_t DAT_A2; /* Offset: 0x40, 0xA0 IFn Data A2 Register (Register Map Note 3) */
sahilmgandhi 18:6a4db94011d3 1504 __IO uint32_t DAT_B1; /* Offset: 0x44, 0xA4 IFn Data B1 Register (Register Map Note 3) */
sahilmgandhi 18:6a4db94011d3 1505 __IO uint32_t DAT_B2; /* Offset: 0x48, 0xA8 IFn Data B2 Register (Register Map Note 3) */
sahilmgandhi 18:6a4db94011d3 1506 __I uint32_t RESERVE0[13];
sahilmgandhi 18:6a4db94011d3 1507
sahilmgandhi 18:6a4db94011d3 1508 } CAN_IF_T;
sahilmgandhi 18:6a4db94011d3 1509
sahilmgandhi 18:6a4db94011d3 1510
sahilmgandhi 18:6a4db94011d3 1511
sahilmgandhi 18:6a4db94011d3 1512
sahilmgandhi 18:6a4db94011d3 1513 typedef struct
sahilmgandhi 18:6a4db94011d3 1514 {
sahilmgandhi 18:6a4db94011d3 1515
sahilmgandhi 18:6a4db94011d3 1516
sahilmgandhi 18:6a4db94011d3 1517
sahilmgandhi 18:6a4db94011d3 1518 /**
sahilmgandhi 18:6a4db94011d3 1519 * @var CAN_T::CON
sahilmgandhi 18:6a4db94011d3 1520 * Offset: 0x00 Control Register
sahilmgandhi 18:6a4db94011d3 1521 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1522 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1523 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1524 * |[0] |Init |Init Initialization
sahilmgandhi 18:6a4db94011d3 1525 * | | |0 = Normal Operation.
sahilmgandhi 18:6a4db94011d3 1526 * | | |1 = Initialization is started.
sahilmgandhi 18:6a4db94011d3 1527 * |[1] |IE |Module Interrupt Enable Control
sahilmgandhi 18:6a4db94011d3 1528 * | | |0 = Disabled.
sahilmgandhi 18:6a4db94011d3 1529 * | | |1 = Enabled.
sahilmgandhi 18:6a4db94011d3 1530 * |[2] |SIE |Status Change Interrupt Enable Control
sahilmgandhi 18:6a4db94011d3 1531 * | | |0 = Disabled - No Status Change Interrupt will be generated.
sahilmgandhi 18:6a4db94011d3 1532 * | | |1 = Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected.
sahilmgandhi 18:6a4db94011d3 1533 * |[3] |EIE |Error Interrupt Enable Control
sahilmgandhi 18:6a4db94011d3 1534 * | | |0 = Disabled - No Error Status Interrupt will be generated.
sahilmgandhi 18:6a4db94011d3 1535 * | | |1 = Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt.
sahilmgandhi 18:6a4db94011d3 1536 * |[5] |DAR |Automatic Re-Transmission Disable Control
sahilmgandhi 18:6a4db94011d3 1537 * | | |0 = Automatic Retransmission of disturbed messages enabled.
sahilmgandhi 18:6a4db94011d3 1538 * | | |1 = Automatic Retransmission disabled.
sahilmgandhi 18:6a4db94011d3 1539 * |[6] |CCE |Configuration Change Enable Control
sahilmgandhi 18:6a4db94011d3 1540 * | | |0 = No write access to the Bit Timing Register.
sahilmgandhi 18:6a4db94011d3 1541 * | | |1 = Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1).
sahilmgandhi 18:6a4db94011d3 1542 * |[7] |Test |Test Mode Enable Control
sahilmgandhi 18:6a4db94011d3 1543 * | | |0 = Normal Operation.
sahilmgandhi 18:6a4db94011d3 1544 * | | |1 = Test Mode.
sahilmgandhi 18:6a4db94011d3 1545 * @var CAN_T::STATUS
sahilmgandhi 18:6a4db94011d3 1546 * Offset: 0x04 Status Register
sahilmgandhi 18:6a4db94011d3 1547 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1548 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1549 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1550 * |[2:0] |LEC |Last Error Code (Type Of The Last Error To Occur On The CAN Bus)
sahilmgandhi 18:6a4db94011d3 1551 * | | |The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus.
sahilmgandhi 18:6a4db94011d3 1552 * | | |This field will be cleared to '0' when a message has been transferred (reception or transmission) without error.
sahilmgandhi 18:6a4db94011d3 1553 * | | |The unused code '7' may be written by the CPU to check for updates.
sahilmgandhi 18:6a4db94011d3 1554 * | | |The following table describes the error code.
sahilmgandhi 18:6a4db94011d3 1555 * |[3] |TxOK |Transmitted A Message Successfully
sahilmgandhi 18:6a4db94011d3 1556 * | | |0 = Since this bit was reset by the CPU, no message has been successfully transmitted.
sahilmgandhi 18:6a4db94011d3 1557 * | | |This bit is never reset by the CAN Core.
sahilmgandhi 18:6a4db94011d3 1558 * | | |1 = Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted.
sahilmgandhi 18:6a4db94011d3 1559 * |[4] |RxOK |Received A Message Successfully
sahilmgandhi 18:6a4db94011d3 1560 * | | |0 = No message has been successfully received since this bit was last reset by the CPU.
sahilmgandhi 18:6a4db94011d3 1561 * | | |This bit is never reset by the CAN Core.
sahilmgandhi 18:6a4db94011d3 1562 * | | |1 = A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering).
sahilmgandhi 18:6a4db94011d3 1563 * |[5] |EPass |Error Passive (Read Only)
sahilmgandhi 18:6a4db94011d3 1564 * | | |0 = The CAN Core is error active.
sahilmgandhi 18:6a4db94011d3 1565 * | | |1 = The CAN Core is in the error passive state as defined in the CAN Specification.
sahilmgandhi 18:6a4db94011d3 1566 * |[6] |EWarn |Error Warning Status (Read Only)
sahilmgandhi 18:6a4db94011d3 1567 * | | |0 = Both error counters are below the error warning limit of 96.
sahilmgandhi 18:6a4db94011d3 1568 * | | |1 = At least one of the error counters in the EML has reached the error warning limit of 96.
sahilmgandhi 18:6a4db94011d3 1569 * |[7] |BOff |Bus-Off Status (Read Only)
sahilmgandhi 18:6a4db94011d3 1570 * | | |0 = The CAN module is not in bus-off state.
sahilmgandhi 18:6a4db94011d3 1571 * | | |1 = The CAN module is in bus-off state.
sahilmgandhi 18:6a4db94011d3 1572 * @var CAN_T::ERR
sahilmgandhi 18:6a4db94011d3 1573 * Offset: 0x08 Error Counter Register
sahilmgandhi 18:6a4db94011d3 1574 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1575 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1576 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1577 * |[7:0] |TEC |Transmit Error Counter
sahilmgandhi 18:6a4db94011d3 1578 * | | |Actual state of the Transmit Error Counter. Values between 0 and 255.
sahilmgandhi 18:6a4db94011d3 1579 * |[14:8] |REC |Receive Error Counter
sahilmgandhi 18:6a4db94011d3 1580 * | | |Actual state of the Receive Error Counter. Values between 0 and 127.
sahilmgandhi 18:6a4db94011d3 1581 * |[15] |RP |Receive Error Passive
sahilmgandhi 18:6a4db94011d3 1582 * | | |0 = The Receive Error Counter is below the error passive level.
sahilmgandhi 18:6a4db94011d3 1583 * | | |1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification.
sahilmgandhi 18:6a4db94011d3 1584 * @var CAN_T::BTIME
sahilmgandhi 18:6a4db94011d3 1585 * Offset: 0x0C Bit Timing Register
sahilmgandhi 18:6a4db94011d3 1586 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1587 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1588 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1589 * |[5:0] |BRP |Baud Rate Prescaler
sahilmgandhi 18:6a4db94011d3 1590 * | | |0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta.
sahilmgandhi 18:6a4db94011d3 1591 * | | |The bit time is built up from a multiple of this quanta.
sahilmgandhi 18:6a4db94011d3 1592 * | | |Valid values for the Baud Rate Prescaler are [ 0 ... 63 ].
sahilmgandhi 18:6a4db94011d3 1593 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
sahilmgandhi 18:6a4db94011d3 1594 * |[7:6] |SJW |(Re)Synchronization Jump Width
sahilmgandhi 18:6a4db94011d3 1595 * | | |0x0-0x3: Valid programmed values are [0 ... 3].
sahilmgandhi 18:6a4db94011d3 1596 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
sahilmgandhi 18:6a4db94011d3 1597 * |[11:8] |TSeg1 |Time Segment Before The Sample Point Minus Sync_Seg
sahilmgandhi 18:6a4db94011d3 1598 * | | |0x01-0x0F: valid values for TSeg1 are [1 ... 15].
sahilmgandhi 18:6a4db94011d3 1599 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed is used.
sahilmgandhi 18:6a4db94011d3 1600 * |[14:12] |TSeg2 |Time Segment After Sample Point
sahilmgandhi 18:6a4db94011d3 1601 * | | |0x0-0x7: Valid values for TSeg2 are [0 ... 7].
sahilmgandhi 18:6a4db94011d3 1602 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
sahilmgandhi 18:6a4db94011d3 1603 * @var CAN_T::IIDR
sahilmgandhi 18:6a4db94011d3 1604 * Offset: 0x10 Interrupt Identifier Register
sahilmgandhi 18:6a4db94011d3 1605 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1606 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1607 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1608 * |[15:0] |IntId |Interrupt Identifier (Indicates The Source Of The Interrupt)
sahilmgandhi 18:6a4db94011d3 1609 * | | |If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order.
sahilmgandhi 18:6a4db94011d3 1610 * | | |An interrupt remains pending until the application software has cleared it.
sahilmgandhi 18:6a4db94011d3 1611 * | | |If IntId is different from 0x0000 and IE (CAN_IFn_MCON[1]) is set, the IRQ interrupt signal to the EIC is active.
sahilmgandhi 18:6a4db94011d3 1612 * | | |The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.
sahilmgandhi 18:6a4db94011d3 1613 * | | |The Status Interrupt has the highest priority.
sahilmgandhi 18:6a4db94011d3 1614 * | | |Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number.
sahilmgandhi 18:6a4db94011d3 1615 * | | |A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]).
sahilmgandhi 18:6a4db94011d3 1616 * | | |The Status Interrupt is cleared by reading the Status Register.
sahilmgandhi 18:6a4db94011d3 1617 * @var CAN_T::TEST
sahilmgandhi 18:6a4db94011d3 1618 * Offset: 0x14 Test Register (Register Map Note 1)
sahilmgandhi 18:6a4db94011d3 1619 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1620 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1621 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1622 * |[1:0] |Res |Reserved
sahilmgandhi 18:6a4db94011d3 1623 * | | |There are reserved bits.
sahilmgandhi 18:6a4db94011d3 1624 * | | |These bits are always read as '0' and must always be written with '0'.
sahilmgandhi 18:6a4db94011d3 1625 * |[2] |Basic |Basic Mode
sahilmgandhi 18:6a4db94011d3 1626 * | | |0 = Basic Mode disabled.
sahilmgandhi 18:6a4db94011d3 1627 * | | |1= IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.
sahilmgandhi 18:6a4db94011d3 1628 * |[3] |Silent |Silent Mode
sahilmgandhi 18:6a4db94011d3 1629 * | | |0 = Normal operation.
sahilmgandhi 18:6a4db94011d3 1630 * | | |1 = The module is in Silent Mode.
sahilmgandhi 18:6a4db94011d3 1631 * |[4] |LBack |Loop Back Mode Enable Control
sahilmgandhi 18:6a4db94011d3 1632 * | | |0 = Loop Back Mode is disabled.
sahilmgandhi 18:6a4db94011d3 1633 * | | |1 = Loop Back Mode is enabled.
sahilmgandhi 18:6a4db94011d3 1634 * |[6:5] |Tx10 |Tx[1:0]: Control Of CAN_TX Pin
sahilmgandhi 18:6a4db94011d3 1635 * | | |00 = Reset value, CAN_TX pin is controlled by the CAN Core.
sahilmgandhi 18:6a4db94011d3 1636 * | | |01 = Sample Point can be monitored at CAN_TX pin.
sahilmgandhi 18:6a4db94011d3 1637 * | | |10 = CAN_TX pin drives a dominant ('0') value.
sahilmgandhi 18:6a4db94011d3 1638 * | | |11 = CAN_TX pin drives a recessive ('1') value.
sahilmgandhi 18:6a4db94011d3 1639 * |[7] |Rx |Monitors The Actual Value Of CAN_RX Pin (Read Only)
sahilmgandhi 18:6a4db94011d3 1640 * | | |0 = The CAN bus is dominant (CAN_RX = '0').
sahilmgandhi 18:6a4db94011d3 1641 * | | |1 = The CAN bus is recessive (CAN_RX = '1').
sahilmgandhi 18:6a4db94011d3 1642 * @var CAN_T::BRPE
sahilmgandhi 18:6a4db94011d3 1643 * Offset: 0x18 Baud Rate Prescaler Extension Register
sahilmgandhi 18:6a4db94011d3 1644 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1645 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1646 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1647 * |[3:0] |BRPE |BRPE: Baud Rate Prescaler Extension
sahilmgandhi 18:6a4db94011d3 1648 * | | |0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023.
sahilmgandhi 18:6a4db94011d3 1649 * | | |The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used.
sahilmgandhi 18:6a4db94011d3 1650 * @var CAN_T::IF
sahilmgandhi 18:6a4db94011d3 1651 * Offset: 0x20~0xFC CAN Interface Registers
sahilmgandhi 18:6a4db94011d3 1652 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1653 * CAN interface structure. Refer to \ref CAN_IF_T for detail information.
sahilmgandhi 18:6a4db94011d3 1654 *
sahilmgandhi 18:6a4db94011d3 1655 * @var CAN_T::TXREQ1
sahilmgandhi 18:6a4db94011d3 1656 * Offset: 0x100 Transmission Request Register 1
sahilmgandhi 18:6a4db94011d3 1657 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1658 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1659 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1660 * |[15:0] |TxRqst[16:1]|Transmission Request Bits 16-1 (Of All Message Objects)
sahilmgandhi 18:6a4db94011d3 1661 * | | |0 = This Message Object is not waiting for transmission.
sahilmgandhi 18:6a4db94011d3 1662 * | | |1 = The transmission of this Message Object is requested and is not yet done.
sahilmgandhi 18:6a4db94011d3 1663 * | | |These bits are read only.
sahilmgandhi 18:6a4db94011d3 1664 * @var CAN_T::TXREQ2
sahilmgandhi 18:6a4db94011d3 1665 * Offset: 0x104 Transmission Request Register 2
sahilmgandhi 18:6a4db94011d3 1666 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1667 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1668 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1669 * |[15:0] |TxRqst[32:17]|Transmission Request Bits 32-17 (Of All Message Objects)
sahilmgandhi 18:6a4db94011d3 1670 * | | |0 = This Message Object is not waiting for transmission.
sahilmgandhi 18:6a4db94011d3 1671 * | | |1 = The transmission of this Message Object is requested and is not yet done.
sahilmgandhi 18:6a4db94011d3 1672 * | | |These bits are read only.
sahilmgandhi 18:6a4db94011d3 1673 * @var CAN_T::NDAT1
sahilmgandhi 18:6a4db94011d3 1674 * Offset: 0x120 New Data Register 1
sahilmgandhi 18:6a4db94011d3 1675 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1676 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1677 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1678 * |[15:0] |NewData[16:1]|New Data Bits 16-1 (Of All Message Objects)
sahilmgandhi 18:6a4db94011d3 1679 * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
sahilmgandhi 18:6a4db94011d3 1680 * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
sahilmgandhi 18:6a4db94011d3 1681 * @var CAN_T::NDAT2
sahilmgandhi 18:6a4db94011d3 1682 * Offset: 0x124 New Data Register 2
sahilmgandhi 18:6a4db94011d3 1683 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1684 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1685 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1686 * |[15:0] |NewData[32:17]|New Data Bits 32-17 (Of All Message Objects)
sahilmgandhi 18:6a4db94011d3 1687 * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
sahilmgandhi 18:6a4db94011d3 1688 * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
sahilmgandhi 18:6a4db94011d3 1689 * @var CAN_T::IPND1
sahilmgandhi 18:6a4db94011d3 1690 * Offset: 0x140 Interrupt Pending Register 1
sahilmgandhi 18:6a4db94011d3 1691 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1692 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1693 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1694 * |[15:0] |IntPnd[16:1]|Interrupt Pending Bits 16-1 (Of All Message Objects)
sahilmgandhi 18:6a4db94011d3 1695 * | | |0 = This message object is not the source of an interrupt.
sahilmgandhi 18:6a4db94011d3 1696 * | | |1 = This message object is the source of an interrupt.
sahilmgandhi 18:6a4db94011d3 1697 * @var CAN_T::IPND2
sahilmgandhi 18:6a4db94011d3 1698 * Offset: 0x144 Interrupt Pending Register 2
sahilmgandhi 18:6a4db94011d3 1699 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1700 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1701 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1702 * |[15:0] |IntPnd[32:17]|Interrupt Pending Bits 32-17(Of All Message Objects)
sahilmgandhi 18:6a4db94011d3 1703 * | | |0 = This message object is not the source of an interrupt.
sahilmgandhi 18:6a4db94011d3 1704 * | | |1 = This message object is the source of an interrupt.
sahilmgandhi 18:6a4db94011d3 1705 * @var CAN_T::MVLD1
sahilmgandhi 18:6a4db94011d3 1706 * Offset: 0x160 Message Valid Register 1
sahilmgandhi 18:6a4db94011d3 1707 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1708 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1709 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1710 * |[15:0] |MsgVal[16:1]|Message Valid Bits 16-1 (Of All Message Objects) (Read Only)
sahilmgandhi 18:6a4db94011d3 1711 * | | |0 = This Message Object is ignored by the Message Handler.
sahilmgandhi 18:6a4db94011d3 1712 * | | |1 = This Message Object is configured and should be considered by the Message Handler.
sahilmgandhi 18:6a4db94011d3 1713 * | | |Ex.
sahilmgandhi 18:6a4db94011d3 1714 * | | |CAN_MVLD1[0] means Message object No.1 is valid or not.
sahilmgandhi 18:6a4db94011d3 1715 * | | |If CAN_MVLD1[0] is set, message object No.1 is configured.
sahilmgandhi 18:6a4db94011d3 1716 * @var CAN_T::MVLD2
sahilmgandhi 18:6a4db94011d3 1717 * Offset: 0x164 Message Valid Register 2
sahilmgandhi 18:6a4db94011d3 1718 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1719 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1720 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1721 * |[15:0] |MsgVal[32:17]|Message Valid Bits 32-17 (Of All Message Objects) (Read Only)
sahilmgandhi 18:6a4db94011d3 1722 * | | |0 = This Message Object is ignored by the Message Handler.
sahilmgandhi 18:6a4db94011d3 1723 * | | |1 = This Message Object is configured and should be considered by the Message Handler.
sahilmgandhi 18:6a4db94011d3 1724 * | | |Ex.CAN_MVLD2[15] means Message object No.32 is valid or not.
sahilmgandhi 18:6a4db94011d3 1725 * | | |If CAN_MVLD2[15] is set, message object No.32 is configured.
sahilmgandhi 18:6a4db94011d3 1726 * @var CAN_T::WU_EN
sahilmgandhi 18:6a4db94011d3 1727 * Offset: 0x168 Wake-up Enable Register
sahilmgandhi 18:6a4db94011d3 1728 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1729 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1730 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1731 * |[0] |WAKUP_EN |Wake-Up Enable Control
sahilmgandhi 18:6a4db94011d3 1732 * | | |0 = The wake-up function Disabled.
sahilmgandhi 18:6a4db94011d3 1733 * | | |1 = The wake-up function Enabled.
sahilmgandhi 18:6a4db94011d3 1734 * | | |Note: User can wake-up system when there is a falling edge in the CAN_Rx pin.
sahilmgandhi 18:6a4db94011d3 1735 * @var CAN_T::WU_STATUS
sahilmgandhi 18:6a4db94011d3 1736 * Offset: 0x16C Wake-up Status Register
sahilmgandhi 18:6a4db94011d3 1737 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1738 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 1739 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 1740 * |[0] |WAKUP_STS |Wake-Up Status
sahilmgandhi 18:6a4db94011d3 1741 * | | |0 = No wake-up event occurred.
sahilmgandhi 18:6a4db94011d3 1742 * | | |1 = Wake-up event occurred.
sahilmgandhi 18:6a4db94011d3 1743 * | | |Note: This bit can be cleared by writing '0'.
sahilmgandhi 18:6a4db94011d3 1744 */
sahilmgandhi 18:6a4db94011d3 1745
sahilmgandhi 18:6a4db94011d3 1746 __IO uint32_t CON; /* Offset: 0x00 Control Register */
sahilmgandhi 18:6a4db94011d3 1747 __IO uint32_t STATUS; /* Offset: 0x04 Status Register */
sahilmgandhi 18:6a4db94011d3 1748 __I uint32_t ERR; /* Offset: 0x08 Error Counter Register */
sahilmgandhi 18:6a4db94011d3 1749 __IO uint32_t BTIME; /* Offset: 0x0C Bit Timing Register */
sahilmgandhi 18:6a4db94011d3 1750 __I uint32_t IIDR; /* Offset: 0x10 Interrupt Identifier Register */
sahilmgandhi 18:6a4db94011d3 1751 __IO uint32_t TEST; /* Offset: 0x14 Test Register (Register Map Note 1) */
sahilmgandhi 18:6a4db94011d3 1752 __IO uint32_t BRPE; /* Offset: 0x18 Baud Rate Prescaler Extension Register */
sahilmgandhi 18:6a4db94011d3 1753 __I uint32_t RESERVE0[1];
sahilmgandhi 18:6a4db94011d3 1754 __IO CAN_IF_T IF[2]; /* Offset: 0x20~0xFC CAN Interface Registers */
sahilmgandhi 18:6a4db94011d3 1755 __I uint32_t RESERVE1[8];
sahilmgandhi 18:6a4db94011d3 1756 __I uint32_t TXREQ1; /* Offset: 0x100 Transmission Request Register 1 */
sahilmgandhi 18:6a4db94011d3 1757 __I uint32_t TXREQ2; /* Offset: 0x104 Transmission Request Register 2 */
sahilmgandhi 18:6a4db94011d3 1758 __I uint32_t RESERVE3[6];
sahilmgandhi 18:6a4db94011d3 1759 __I uint32_t NDAT1; /* Offset: 0x120 New Data Register 1 */
sahilmgandhi 18:6a4db94011d3 1760 __I uint32_t NDAT2; /* Offset: 0x124 New Data Register 2 */
sahilmgandhi 18:6a4db94011d3 1761 __I uint32_t RESERVE4[6];
sahilmgandhi 18:6a4db94011d3 1762 __I uint32_t IPND1; /* Offset: 0x140 Interrupt Pending Register 1 */
sahilmgandhi 18:6a4db94011d3 1763 __I uint32_t IPND2; /* Offset: 0x144 Interrupt Pending Register 2 */
sahilmgandhi 18:6a4db94011d3 1764 __I uint32_t RESERVE5[6];
sahilmgandhi 18:6a4db94011d3 1765 __I uint32_t MVLD1; /* Offset: 0x160 Message Valid Register 1 */
sahilmgandhi 18:6a4db94011d3 1766 __I uint32_t MVLD2; /* Offset: 0x164 Message Valid Register 2 */
sahilmgandhi 18:6a4db94011d3 1767 __IO uint32_t WU_EN; /* Offset: 0x168 Wake-up Enable Register */
sahilmgandhi 18:6a4db94011d3 1768 __IO uint32_t WU_STATUS; /* Offset: 0x16C Wake-up Status Register */
sahilmgandhi 18:6a4db94011d3 1769
sahilmgandhi 18:6a4db94011d3 1770 } CAN_T;
sahilmgandhi 18:6a4db94011d3 1771
sahilmgandhi 18:6a4db94011d3 1772
sahilmgandhi 18:6a4db94011d3 1773
sahilmgandhi 18:6a4db94011d3 1774 /**
sahilmgandhi 18:6a4db94011d3 1775 @addtogroup CAN_CONST CAN Bit Field Definition
sahilmgandhi 18:6a4db94011d3 1776 Constant Definitions for CAN Controller
sahilmgandhi 18:6a4db94011d3 1777 @{ */
sahilmgandhi 18:6a4db94011d3 1778 /* CAN CON Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 1779 #define CAN_CON_TEST_Pos 7 /*!< CAN_T::CON: TEST Position */
sahilmgandhi 18:6a4db94011d3 1780 #define CAN_CON_TEST_Msk (0x1ul << CAN_CON_TEST_Pos) /*!< CAN_T::CON: TEST Mask */
sahilmgandhi 18:6a4db94011d3 1781
sahilmgandhi 18:6a4db94011d3 1782 #define CAN_CON_CCE_Pos 6 /*!< CAN_T::CON: CCE Position */
sahilmgandhi 18:6a4db94011d3 1783 #define CAN_CON_CCE_Msk (0x1ul << CAN_CON_CCE_Pos) /*!< CAN_T::CON: CCE Mask */
sahilmgandhi 18:6a4db94011d3 1784
sahilmgandhi 18:6a4db94011d3 1785 #define CAN_CON_DAR_Pos 5 /*!< CAN_T::CON: DAR Position */
sahilmgandhi 18:6a4db94011d3 1786 #define CAN_CON_DAR_Msk (0x1ul << CAN_CON_DAR_Pos) /*!< CAN_T::CON: DAR Mask */
sahilmgandhi 18:6a4db94011d3 1787
sahilmgandhi 18:6a4db94011d3 1788 #define CAN_CON_EIE_Pos 3 /*!< CAN_T::CON: EIE Position */
sahilmgandhi 18:6a4db94011d3 1789 #define CAN_CON_EIE_Msk (0x1ul << CAN_CON_EIE_Pos) /*!< CAN_T::CON: EIE Mask */
sahilmgandhi 18:6a4db94011d3 1790
sahilmgandhi 18:6a4db94011d3 1791 #define CAN_CON_SIE_Pos 2 /*!< CAN_T::CON: SIE Position */
sahilmgandhi 18:6a4db94011d3 1792 #define CAN_CON_SIE_Msk (0x1ul << CAN_CON_SIE_Pos) /*!< CAN_T::CON: SIE Mask */
sahilmgandhi 18:6a4db94011d3 1793
sahilmgandhi 18:6a4db94011d3 1794 #define CAN_CON_IE_Pos 1 /*!< CAN_T::CON: IE Position */
sahilmgandhi 18:6a4db94011d3 1795 #define CAN_CON_IE_Msk (0x1ul << CAN_CON_IE_Pos) /*!< CAN_T::CON: IE Mask */
sahilmgandhi 18:6a4db94011d3 1796
sahilmgandhi 18:6a4db94011d3 1797 #define CAN_CON_INIT_Pos 0 /*!< CAN_T::CON: INIT Position */
sahilmgandhi 18:6a4db94011d3 1798 #define CAN_CON_INIT_Msk (0x1ul << CAN_CON_INIT_Pos) /*!< CAN_T::CON: INIT Mask */
sahilmgandhi 18:6a4db94011d3 1799
sahilmgandhi 18:6a4db94011d3 1800 /* CAN STATUS Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 1801 #define CAN_STATUS_BOFF_Pos 7 /*!< CAN_T::STATUS: BOFF Position */
sahilmgandhi 18:6a4db94011d3 1802 #define CAN_STATUS_BOFF_Msk (0x1ul << CAN_STATUS_BOFF_Pos) /*!< CAN_T::STATUS: BOFF Mask */
sahilmgandhi 18:6a4db94011d3 1803
sahilmgandhi 18:6a4db94011d3 1804 #define CAN_STATUS_EWARN_Pos 6 /*!< CAN_T::STATUS: EWARN Position */
sahilmgandhi 18:6a4db94011d3 1805 #define CAN_STATUS_EWARN_Msk (0x1ul << CAN_STATUS_EWARN_Pos) /*!< CAN_T::STATUS: EWARN Mask */
sahilmgandhi 18:6a4db94011d3 1806
sahilmgandhi 18:6a4db94011d3 1807 #define CAN_STATUS_EPASS_Pos 5 /*!< CAN_T::STATUS: EPASS Position */
sahilmgandhi 18:6a4db94011d3 1808 #define CAN_STATUS_EPASS_Msk (0x1ul << CAN_STATUS_EPASS_Pos) /*!< CAN_T::STATUS: EPASS Mask */
sahilmgandhi 18:6a4db94011d3 1809
sahilmgandhi 18:6a4db94011d3 1810 #define CAN_STATUS_RXOK_Pos 4 /*!< CAN_T::STATUS: RXOK Position */
sahilmgandhi 18:6a4db94011d3 1811 #define CAN_STATUS_RXOK_Msk (0x1ul << CAN_STATUS_RXOK_Pos) /*!< CAN_T::STATUS: RXOK Mask */
sahilmgandhi 18:6a4db94011d3 1812
sahilmgandhi 18:6a4db94011d3 1813 #define CAN_STATUS_TXOK_Pos 3 /*!< CAN_T::STATUS: TXOK Position */
sahilmgandhi 18:6a4db94011d3 1814 #define CAN_STATUS_TXOK_Msk (0x1ul << CAN_STATUS_TXOK_Pos) /*!< CAN_T::STATUS: TXOK Mask */
sahilmgandhi 18:6a4db94011d3 1815
sahilmgandhi 18:6a4db94011d3 1816 #define CAN_STATUS_LEC_Pos 0 /*!< CAN_T::STATUS: LEC Position */
sahilmgandhi 18:6a4db94011d3 1817 #define CAN_STATUS_LEC_Msk (0x7ul << CAN_STATUS_LEC_Pos) /*!< CAN_T::STATUS: LEC Mask */
sahilmgandhi 18:6a4db94011d3 1818
sahilmgandhi 18:6a4db94011d3 1819 /* CAN ERR Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 1820 #define CAN_ERR_RP_Pos 15 /*!< CAN_T::ERR: RP Position */
sahilmgandhi 18:6a4db94011d3 1821 #define CAN_ERR_RP_Msk (0x1ul << CAN_ERR_RP_Pos) /*!< CAN_T::ERR: RP Mask */
sahilmgandhi 18:6a4db94011d3 1822
sahilmgandhi 18:6a4db94011d3 1823 #define CAN_ERR_REC_Pos 8 /*!< CAN_T::ERR: REC Position */
sahilmgandhi 18:6a4db94011d3 1824 #define CAN_ERR_REC_Msk (0x7Ful << CAN_ERR_REC_Pos) /*!< CAN_T::ERR: REC Mask */
sahilmgandhi 18:6a4db94011d3 1825
sahilmgandhi 18:6a4db94011d3 1826 #define CAN_ERR_TEC_Pos 0 /*!< CAN_T::ERR: TEC Position */
sahilmgandhi 18:6a4db94011d3 1827 #define CAN_ERR_TEC_Msk (0xFFul << CAN_ERR_TEC_Pos) /*!< CAN_T::ERR: TEC Mask */
sahilmgandhi 18:6a4db94011d3 1828
sahilmgandhi 18:6a4db94011d3 1829 /* CAN BTIME Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 1830 #define CAN_BTIME_TSEG2_Pos 12 /*!< CAN_T::BTIME: TSEG2 Position */
sahilmgandhi 18:6a4db94011d3 1831 #define CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos) /*!< CAN_T::BTIME: TSEG2 Mask */
sahilmgandhi 18:6a4db94011d3 1832
sahilmgandhi 18:6a4db94011d3 1833 #define CAN_BTIME_TSEG1_Pos 8 /*!< CAN_T::BTIME: TSEG1 Position */
sahilmgandhi 18:6a4db94011d3 1834 #define CAN_BTIME_TSEG1_Msk (0xFul << CAN_BTIME_TSEG1_Pos) /*!< CAN_T::BTIME: TSEG1 Mask */
sahilmgandhi 18:6a4db94011d3 1835
sahilmgandhi 18:6a4db94011d3 1836 #define CAN_BTIME_SJW_Pos 6 /*!< CAN_T::BTIME: SJW Position */
sahilmgandhi 18:6a4db94011d3 1837 #define CAN_BTIME_SJW_Msk (0x3ul << CAN_BTIME_SJW_Pos) /*!< CAN_T::BTIME: SJW Mask */
sahilmgandhi 18:6a4db94011d3 1838
sahilmgandhi 18:6a4db94011d3 1839 #define CAN_BTIME_BRP_Pos 0 /*!< CAN_T::BTIME: BRP Position */
sahilmgandhi 18:6a4db94011d3 1840 #define CAN_BTIME_BRP_Msk (0x3Ful << CAN_BTIME_BRP_Pos) /*!< CAN_T::BTIME: BRP Mask */
sahilmgandhi 18:6a4db94011d3 1841
sahilmgandhi 18:6a4db94011d3 1842 /* CAN IIDR Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 1843 #define CAN_IIDR_INTID_Pos 0 /*!< CAN_T::IIDR: INTID Position */
sahilmgandhi 18:6a4db94011d3 1844 #define CAN_IIDR_INTID_Msk (0xFFFFul << CAN_IIDR_INTID_Pos) /*!< CAN_T::IIDR: INTID Mask */
sahilmgandhi 18:6a4db94011d3 1845
sahilmgandhi 18:6a4db94011d3 1846 /* CAN TEST Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 1847 #define CAN_TEST_RX_Pos 7 /*!< CAN_T::TEST: RX Position */
sahilmgandhi 18:6a4db94011d3 1848 #define CAN_TEST_RX_Msk (0x1ul << CAN_TEST_RX_Pos) /*!< CAN_T::TEST: RX Mask */
sahilmgandhi 18:6a4db94011d3 1849
sahilmgandhi 18:6a4db94011d3 1850 #define CAN_TEST_TX_Pos 5 /*!< CAN_T::TEST: TX Position */
sahilmgandhi 18:6a4db94011d3 1851 #define CAN_TEST_TX_Msk (0x3ul << CAN_TEST_TX_Pos) /*!< CAN_T::TEST: TX Mask */
sahilmgandhi 18:6a4db94011d3 1852
sahilmgandhi 18:6a4db94011d3 1853 #define CAN_TEST_LBACK_Pos 4 /*!< CAN_T::TEST: LBACK Position */
sahilmgandhi 18:6a4db94011d3 1854 #define CAN_TEST_LBACK_Msk (0x1ul << CAN_TEST_LBACK_Pos) /*!< CAN_T::TEST: LBACK Mask */
sahilmgandhi 18:6a4db94011d3 1855
sahilmgandhi 18:6a4db94011d3 1856 #define CAN_TEST_SILENT_Pos 3 /*!< CAN_T::TEST: Silent Position */
sahilmgandhi 18:6a4db94011d3 1857 #define CAN_TEST_SILENT_Msk (0x1ul << CAN_TEST_SILENT_Pos) /*!< CAN_T::TEST: Silent Mask */
sahilmgandhi 18:6a4db94011d3 1858
sahilmgandhi 18:6a4db94011d3 1859 #define CAN_TEST_BASIC_Pos 2 /*!< CAN_T::TEST: Basic Position */
sahilmgandhi 18:6a4db94011d3 1860 #define CAN_TEST_BASIC_Msk (0x1ul << CAN_TEST_BASIC_Pos) /*!< CAN_T::TEST: Basic Mask */
sahilmgandhi 18:6a4db94011d3 1861
sahilmgandhi 18:6a4db94011d3 1862 /* CAN BPRE Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 1863 #define CAN_BRPE_BRPE_Pos 0 /*!< CAN_T::BRPE: BRPE Position */
sahilmgandhi 18:6a4db94011d3 1864 #define CAN_BRPE_BRPE_Msk (0xFul << CAN_BRPE_BRPE_Pos) /*!< CAN_T::BRPE: BRPE Mask */
sahilmgandhi 18:6a4db94011d3 1865
sahilmgandhi 18:6a4db94011d3 1866 /* CAN IFn_CREQ Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 1867 #define CAN_IF_CREQ_BUSY_Pos 15 /*!< CAN_IF_T::CREQ: BUSY Position */
sahilmgandhi 18:6a4db94011d3 1868 #define CAN_IF_CREQ_BUSY_Msk (0x1ul << CAN_IF_CREQ_BUSY_Pos) /*!< CAN_IF_T::CREQ: BUSY Mask */
sahilmgandhi 18:6a4db94011d3 1869
sahilmgandhi 18:6a4db94011d3 1870 #define CAN_IF_CREQ_MSGNUM_Pos 0 /*!< CAN_IF_T::CREQ: MSGNUM Position */
sahilmgandhi 18:6a4db94011d3 1871 #define CAN_IF_CREQ_MSGNUM_Msk (0x3Ful << CAN_IF_CREQ_MSGNUM_Pos) /*!< CAN_IF_T::CREQ: MSGNUM Mask */
sahilmgandhi 18:6a4db94011d3 1872
sahilmgandhi 18:6a4db94011d3 1873 /* CAN IFn_CMASK Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 1874 #define CAN_IF_CMASK_WRRD_Pos 7 /*!< CAN_IF_T::CMASK: WRRD Position */
sahilmgandhi 18:6a4db94011d3 1875 #define CAN_IF_CMASK_WRRD_Msk (0x1ul << CAN_IF_CMASK_WRRD_Pos) /*!< CAN_IF_T::CMASK: WRRD Mask */
sahilmgandhi 18:6a4db94011d3 1876
sahilmgandhi 18:6a4db94011d3 1877 #define CAN_IF_CMASK_MASK_Pos 6 /*!< CAN_IF_T::CMASK: MASK Position */
sahilmgandhi 18:6a4db94011d3 1878 #define CAN_IF_CMASK_MASK_Msk (0x1ul << CAN_IF_CMASK_MASK_Pos) /*!< CAN_IF_T::CMASK: MASK Mask */
sahilmgandhi 18:6a4db94011d3 1879
sahilmgandhi 18:6a4db94011d3 1880 #define CAN_IF_CMASK_ARB_Pos 5 /*!< CAN_IF_T::CMASK: ARB Position */
sahilmgandhi 18:6a4db94011d3 1881 #define CAN_IF_CMASK_ARB_Msk (0x1ul << CAN_IF_CMASK_ARB_Pos) /*!< CAN_IF_T::CMASK: ARB Mask */
sahilmgandhi 18:6a4db94011d3 1882
sahilmgandhi 18:6a4db94011d3 1883 #define CAN_IF_CMASK_CONTROL_Pos 4 /*!< CAN_IF_T::CMASK: CONTROL Position */
sahilmgandhi 18:6a4db94011d3 1884 #define CAN_IF_CMASK_CONTROL_Msk (0x1ul << CAN_IF_CMASK_CONTROL_Pos) /*!< CAN_IF_T::CMASK: CONTROL Mask */
sahilmgandhi 18:6a4db94011d3 1885
sahilmgandhi 18:6a4db94011d3 1886 #define CAN_IF_CMASK_CLRINTPND_Pos 3 /*!< CAN_IF_T::CMASK: CLRINTPND Position */
sahilmgandhi 18:6a4db94011d3 1887 #define CAN_IF_CMASK_CLRINTPND_Msk (0x1ul << CAN_IF_CMASK_CLRINTPND_Pos) /*!< CAN_IF_T::CMASK: CLRINTPND Mask */
sahilmgandhi 18:6a4db94011d3 1888
sahilmgandhi 18:6a4db94011d3 1889 #define CAN_IF_CMASK_TXRQSTNEWDAT_Pos 2 /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Position */
sahilmgandhi 18:6a4db94011d3 1890 #define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (0x1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Mask */
sahilmgandhi 18:6a4db94011d3 1891
sahilmgandhi 18:6a4db94011d3 1892 #define CAN_IF_CMASK_DATAA_Pos 1 /*!< CAN_IF_T::CMASK: DATAA Position */
sahilmgandhi 18:6a4db94011d3 1893 #define CAN_IF_CMASK_DATAA_Msk (0x1ul << CAN_IF_CMASK_DATAA_Pos) /*!< CAN_IF_T::CMASK: DATAA Mask */
sahilmgandhi 18:6a4db94011d3 1894
sahilmgandhi 18:6a4db94011d3 1895 #define CAN_IF_CMASK_DATAB_Pos 0 /*!< CAN_IF_T::CMASK: DATAB Position */
sahilmgandhi 18:6a4db94011d3 1896 #define CAN_IF_CMASK_DATAB_Msk (0x1ul << CAN_IF_CMASK_DATAB_Pos) /*!< CAN_IF_T::CMASK: DATAB Mask */
sahilmgandhi 18:6a4db94011d3 1897
sahilmgandhi 18:6a4db94011d3 1898 /* CAN IFn_MASK1 Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 1899 #define CAN_IF_MASK1_MSK_Pos 0 /*!< CAN_IF_T::MASK1: MSK Position */
sahilmgandhi 18:6a4db94011d3 1900 #define CAN_IF_MASK1_MSK_Msk (0xFFul << CAN_IF_MASK1_MSK_Pos) /*!< CAN_IF_T::MASK1: MSK Mask */
sahilmgandhi 18:6a4db94011d3 1901
sahilmgandhi 18:6a4db94011d3 1902 /* CAN IFn_MASK2 Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 1903 #define CAN_IF_MASK2_MXTD_Pos 15 /*!< CAN_IF_T::MASK2: MXTD Position */
sahilmgandhi 18:6a4db94011d3 1904 #define CAN_IF_MASK2_MXTD_Msk (0x1ul << CAN_IF_MASK2_MXTD_Pos) /*!< CAN_IF_T::MASK2: MXTD Mask */
sahilmgandhi 18:6a4db94011d3 1905
sahilmgandhi 18:6a4db94011d3 1906 #define CAN_IF_MASK2_MDIR_Pos 14 /*!< CAN_IF_T::MASK2: MDIR Position */
sahilmgandhi 18:6a4db94011d3 1907 #define CAN_IF_MASK2_MDIR_Msk (0x1ul << CAN_IF_MASK2_MDIR_Pos) /*!< CAN_IF_T::MASK2: MDIR Mask */
sahilmgandhi 18:6a4db94011d3 1908
sahilmgandhi 18:6a4db94011d3 1909 #define CAN_IF_MASK2_MSK_Pos 0 /*!< CAN_IF_T::MASK2: MSK Position */
sahilmgandhi 18:6a4db94011d3 1910 #define CAN_IF_MASK2_MSK_Msk (0x1FFul << CAN_IF_MASK2_MSK_Pos) /*!< CAN_IF_T::MASK2: MSK Mask */
sahilmgandhi 18:6a4db94011d3 1911
sahilmgandhi 18:6a4db94011d3 1912 /* CAN IFn_ARB1 Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 1913 #define CAN_IF_ARB1_ID_Pos 0 /*!< CAN_IF_T::ARB1: ID Position */
sahilmgandhi 18:6a4db94011d3 1914 #define CAN_IF_ARB1_ID_Msk (0xFFFFul << CAN_IF_ARB1_ID_Pos) /*!< CAN_IF_T::ARB1: ID Mask */
sahilmgandhi 18:6a4db94011d3 1915
sahilmgandhi 18:6a4db94011d3 1916 /* CAN IFn_ARB2 Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 1917 #define CAN_IF_ARB2_MSGVAL_Pos 15 /*!< CAN_IF_T::ARB2: MSGVAL Position */
sahilmgandhi 18:6a4db94011d3 1918 #define CAN_IF_ARB2_MSGVAL_Msk (0x1ul << CAN_IF_ARB2_MSGVAL_Pos) /*!< CAN_IF_T::ARB2: MSGVAL Mask */
sahilmgandhi 18:6a4db94011d3 1919
sahilmgandhi 18:6a4db94011d3 1920 #define CAN_IF_ARB2_XTD_Pos 14 /*!< CAN_IF_T::ARB2: XTD Position */
sahilmgandhi 18:6a4db94011d3 1921 #define CAN_IF_ARB2_XTD_Msk (0x1ul << CAN_IF_ARB2_XTD_Pos) /*!< CAN_IF_T::ARB2: XTD Mask */
sahilmgandhi 18:6a4db94011d3 1922
sahilmgandhi 18:6a4db94011d3 1923 #define CAN_IF_ARB2_DIR_Pos 13 /*!< CAN_IF_T::ARB2: DIR Position */
sahilmgandhi 18:6a4db94011d3 1924 #define CAN_IF_ARB2_DIR_Msk (0x1ul << CAN_IF_ARB2_DIR_Pos) /*!< CAN_IF_T::ARB2: DIR Mask */
sahilmgandhi 18:6a4db94011d3 1925
sahilmgandhi 18:6a4db94011d3 1926 #define CAN_IF_ARB2_ID_Pos 0 /*!< CAN_IF_T::ARB2: ID Position */
sahilmgandhi 18:6a4db94011d3 1927 #define CAN_IF_ARB2_ID_Msk (0x1FFFul << CAN_IF_ARB2_ID_Pos) /*!< CAN_IF_T::ARB2: ID Mask */
sahilmgandhi 18:6a4db94011d3 1928
sahilmgandhi 18:6a4db94011d3 1929 /* CAN IFn_MCON Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 1930 #define CAN_IF_MCON_NEWDAT_Pos 15 /*!< CAN_IF_T::MCON: NEWDAT Position */
sahilmgandhi 18:6a4db94011d3 1931 #define CAN_IF_MCON_NEWDAT_Msk (0x1ul << CAN_IF_MCON_NEWDAT_Pos) /*!< CAN_IF_T::MCON: NEWDAT Mask */
sahilmgandhi 18:6a4db94011d3 1932
sahilmgandhi 18:6a4db94011d3 1933 #define CAN_IF_MCON_MSGLST_Pos 14 /*!< CAN_IF_T::MCON: MSGLST Position */
sahilmgandhi 18:6a4db94011d3 1934 #define CAN_IF_MCON_MSGLST_Msk (0x1ul << CAN_IF_MCON_MSGLST_Pos) /*!< CAN_IF_T::MCON: MSGLST Mask */
sahilmgandhi 18:6a4db94011d3 1935
sahilmgandhi 18:6a4db94011d3 1936 #define CAN_IF_MCON_INTPND_Pos 13 /*!< CAN_IF_T::MCON: INTPND Position */
sahilmgandhi 18:6a4db94011d3 1937 #define CAN_IF_MCON_INTPND_Msk (0x1ul << CAN_IF_MCON_INTPND_Pos) /*!< CAN_IF_T::MCON: INTPND Mask */
sahilmgandhi 18:6a4db94011d3 1938
sahilmgandhi 18:6a4db94011d3 1939 #define CAN_IF_MCON_UMASK_Pos 12 /*!< CAN_IF_T::MCON: UMASK Position */
sahilmgandhi 18:6a4db94011d3 1940 #define CAN_IF_MCON_UMASK_Msk (0x1ul << CAN_IF_MCON_UMASK_Pos) /*!< CAN_IF_T::MCON: UMASK Mask */
sahilmgandhi 18:6a4db94011d3 1941
sahilmgandhi 18:6a4db94011d3 1942 #define CAN_IF_MCON_TXIE_Pos 11 /*!< CAN_IF_T::MCON: TXIE Position */
sahilmgandhi 18:6a4db94011d3 1943 #define CAN_IF_MCON_TXIE_Msk (0x1ul << CAN_IF_MCON_TXIE_Pos) /*!< CAN_IF_T::MCON: TXIE Mask */
sahilmgandhi 18:6a4db94011d3 1944
sahilmgandhi 18:6a4db94011d3 1945 #define CAN_IF_MCON_RXIE_Pos 10 /*!< CAN_IF_T::MCON: RXIE Position */
sahilmgandhi 18:6a4db94011d3 1946 #define CAN_IF_MCON_RXIE_Msk (0x1ul << CAN_IF_MCON_RXIE_Pos) /*!< CAN_IF_T::MCON: RXIE Mask */
sahilmgandhi 18:6a4db94011d3 1947
sahilmgandhi 18:6a4db94011d3 1948 #define CAN_IF_MCON_RMTEN_Pos 9 /*!< CAN_IF_T::MCON: RMTEN Position */
sahilmgandhi 18:6a4db94011d3 1949 #define CAN_IF_MCON_RMTEN_Msk (0x1ul << CAN_IF_MCON_RMTEN_Pos) /*!< CAN_IF_T::MCON: RMTEN Mask */
sahilmgandhi 18:6a4db94011d3 1950
sahilmgandhi 18:6a4db94011d3 1951 #define CAN_IF_MCON_TXRQST_Pos 8 /*!< CAN_IF_T::MCON: TXRQST Position */
sahilmgandhi 18:6a4db94011d3 1952 #define CAN_IF_MCON_TXRQST_Msk (0x1ul << CAN_IF_MCON_TXRQST_Pos) /*!< CAN_IF_T::MCON: TXRQST Mask */
sahilmgandhi 18:6a4db94011d3 1953
sahilmgandhi 18:6a4db94011d3 1954 #define CAN_IF_MCON_EOB_Pos 7 /*!< CAN_IF_T::MCON: EOB Position */
sahilmgandhi 18:6a4db94011d3 1955 #define CAN_IF_MCON_EOB_Msk (0x1ul << CAN_IF_MCON_EOB_Pos) /*!< CAN_IF_T::MCON: EOB Mask */
sahilmgandhi 18:6a4db94011d3 1956
sahilmgandhi 18:6a4db94011d3 1957 #define CAN_IF_MCON_DLC_Pos 0 /*!< CAN_IF_T::MCON: DLC Position */
sahilmgandhi 18:6a4db94011d3 1958 #define CAN_IF_MCON_DLC_Msk (0xFul << CAN_IF_MCON_DLC_Pos) /*!< CAN_IF_T::MCON: DLC Mask */
sahilmgandhi 18:6a4db94011d3 1959
sahilmgandhi 18:6a4db94011d3 1960 /* CAN IFn_DATA_A1 Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 1961 #define CAN_IF_DAT_A1_DATA1_Pos 8 /*!< CAN_IF_T::DATAA1: DATA1 Position */
sahilmgandhi 18:6a4db94011d3 1962 #define CAN_IF_DAT_A1_DATA1_Msk (0xFFul << CAN_IF_DAT_A1_DATA1_Pos) /*!< CAN_IF_T::DATAA1: DATA1 Mask */
sahilmgandhi 18:6a4db94011d3 1963
sahilmgandhi 18:6a4db94011d3 1964 #define CAN_IF_DAT_A1_DATA0_Pos 0 /*!< CAN_IF_T::DATAA1: DATA0 Position */
sahilmgandhi 18:6a4db94011d3 1965 #define CAN_IF_DAT_A1_DATA0_Msk (0xFFul << CAN_IF_DAT_A1_DATA0_Pos) /*!< CAN_IF_T::DATAA1: DATA0 Mask */
sahilmgandhi 18:6a4db94011d3 1966
sahilmgandhi 18:6a4db94011d3 1967 /* CAN IFn_DATA_A2 Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 1968 #define CAN_IF_DAT_A2_DATA3_Pos 8 /*!< CAN_IF_T::DATAA1: DATA3 Position */
sahilmgandhi 18:6a4db94011d3 1969 #define CAN_IF_DAT_A2_DATA3_Msk (0xFFul << CAN_IF_DAT_A2_DATA3_Pos) /*!< CAN_IF_T::DATAA1: DATA3 Mask */
sahilmgandhi 18:6a4db94011d3 1970
sahilmgandhi 18:6a4db94011d3 1971 #define CAN_IF_DAT_A2_DATA2_Pos 0 /*!< CAN_IF_T::DATAA1: DATA2 Position */
sahilmgandhi 18:6a4db94011d3 1972 #define CAN_IF_DAT_A2_DATA2_Msk (0xFFul << CAN_IF_DAT_A2_DATA2_Pos) /*!< CAN_IF_T::DATAA1: DATA2 Mask */
sahilmgandhi 18:6a4db94011d3 1973
sahilmgandhi 18:6a4db94011d3 1974 /* CAN IFn_DATA_B1 Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 1975 #define CAN_IF_DAT_B1_DATA5_Pos 8 /*!< CAN_IF_T::DATAB1: DATA5 Position */
sahilmgandhi 18:6a4db94011d3 1976 #define CAN_IF_DAT_B1_DATA5_Msk (0xFFul << CAN_IF_DAT_B1_DATA5_Pos) /*!< CAN_IF_T::DATAB1: DATA5 Mask */
sahilmgandhi 18:6a4db94011d3 1977
sahilmgandhi 18:6a4db94011d3 1978 #define CAN_IF_DAT_B1_DATA4_Pos 0 /*!< CAN_IF_T::DATAB1: DATA4 Position */
sahilmgandhi 18:6a4db94011d3 1979 #define CAN_IF_DAT_B1_DATA4_Msk (0xFFul << CAN_IF_DAT_B1_DATA4_Pos) /*!< CAN_IF_T::DATAB1: DATA4 Mask */
sahilmgandhi 18:6a4db94011d3 1980
sahilmgandhi 18:6a4db94011d3 1981 /* CAN IFn_DATA_B2 Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 1982 #define CAN_IF_DAT_B2_DATA7_Pos 8 /*!< CAN_IF_T::DATAB2: DATA7 Position */
sahilmgandhi 18:6a4db94011d3 1983 #define CAN_IF_DAT_B2_DATA7_Msk (0xFFul << CAN_IF_DAT_B2_DATA7_Pos) /*!< CAN_IF_T::DATAB2: DATA7 Mask */
sahilmgandhi 18:6a4db94011d3 1984
sahilmgandhi 18:6a4db94011d3 1985 #define CAN_IF_DAT_B2_DATA6_Pos 0 /*!< CAN_IF_T::DATAB2: DATA6 Position */
sahilmgandhi 18:6a4db94011d3 1986 #define CAN_IF_DAT_B2_DATA6_Msk (0xFFul << CAN_IF_DAT_B2_DATA6_Pos) /*!< CAN_IF_T::DATAB2: DATA6 Mask */
sahilmgandhi 18:6a4db94011d3 1987
sahilmgandhi 18:6a4db94011d3 1988 /* CAN IFn_TXRQST1 Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 1989 #define CAN_TXRQST1_TXRQST_Pos 0 /*!< CAN_T::TXRQST1: TXRQST Position */
sahilmgandhi 18:6a4db94011d3 1990 #define CAN_TXRQST1_TXRQST_Msk (0xFFFFul << CAN_TXRQST1_TXRQST_Pos) /*!< CAN_T::TXRQST1: TXRQST Mask */
sahilmgandhi 18:6a4db94011d3 1991
sahilmgandhi 18:6a4db94011d3 1992 /* CAN IFn_TXRQST2 Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 1993 #define CAN_TXRQST2_TXRQST_Pos 0 /*!< CAN_T::TXRQST2: TXRQST Position */
sahilmgandhi 18:6a4db94011d3 1994 #define CAN_TXRQST2_TXRQST_Msk (0xFFFFul << CAN_TXRQST2_TXRQST_Pos) /*!< CAN_T::TXRQST2: TXRQST Mask */
sahilmgandhi 18:6a4db94011d3 1995
sahilmgandhi 18:6a4db94011d3 1996 /* CAN IFn_NDAT1 Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 1997 #define CAN_NDAT1_NEWDATA_Pos 0 /*!< CAN_T::NDAT1: NEWDATA Position */
sahilmgandhi 18:6a4db94011d3 1998 #define CAN_NDAT1_NEWDATA_Msk (0xFFFFul << CAN_NDAT1_NEWDATA_Pos) /*!< CAN_T::NDAT1: NEWDATA Mask */
sahilmgandhi 18:6a4db94011d3 1999
sahilmgandhi 18:6a4db94011d3 2000 /* CAN IFn_NDAT2 Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 2001 #define CAN_NDAT2_NEWDATA_Pos 0 /*!< CAN_T::NDAT2: NEWDATA Position */
sahilmgandhi 18:6a4db94011d3 2002 #define CAN_NDAT2_NEWDATA_Msk (0xFFFFul << CAN_NDAT2_NEWDATA_Pos) /*!< CAN_T::NDAT2: NEWDATA Mask */
sahilmgandhi 18:6a4db94011d3 2003
sahilmgandhi 18:6a4db94011d3 2004 /* CAN IFn_IPND1 Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 2005 #define CAN_IPND1_INTPND_Pos 0 /*!< CAN_T::IPND1: INTPND Position */
sahilmgandhi 18:6a4db94011d3 2006 #define CAN_IPND1_INTPND_Msk (0xFFFFul << CAN_IPND1_INTPND_Pos) /*!< CAN_T::IPND1: INTPND Mask */
sahilmgandhi 18:6a4db94011d3 2007
sahilmgandhi 18:6a4db94011d3 2008 /* CAN IFn_IPND2 Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 2009 #define CAN_IPND2_INTPND_Pos 0 /*!< CAN_T::IPND2: INTPND Position */
sahilmgandhi 18:6a4db94011d3 2010 #define CAN_IPND2_INTPND_Msk (0xFFFFul << CAN_IPND2_INTPND_Pos) /*!< CAN_T::IPND2: INTPND Mask */
sahilmgandhi 18:6a4db94011d3 2011
sahilmgandhi 18:6a4db94011d3 2012 /* CAN IFn_MVLD1 Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 2013 #define CAN_MVLD1_MSGVAL_Pos 0 /*!< CAN_T::MVLD1: MSGVAL Position */
sahilmgandhi 18:6a4db94011d3 2014 #define CAN_MVLD1_MSGVAL_Msk (0xFFFFul << CAN_MVLD1_MSGVAL_Pos) /*!< CAN_T::MVLD1: MSGVAL Mask */
sahilmgandhi 18:6a4db94011d3 2015
sahilmgandhi 18:6a4db94011d3 2016 /* CAN IFn_MVLD2 Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 2017 #define CAN_MVLD2_MSGVAL_Pos 0 /*!< CAN_T::MVLD2: MSGVAL Position */
sahilmgandhi 18:6a4db94011d3 2018 #define CAN_MVLD2_MSGVAL_Msk (0xFFFFul << CAN_MVLD2_MSGVAL_Pos) /*!< CAN_T::MVLD2: MSGVAL Mask */
sahilmgandhi 18:6a4db94011d3 2019
sahilmgandhi 18:6a4db94011d3 2020 /* CAN WUEN Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 2021 #define CAN_WUEN_WAKUP_EN_Pos 0 /*!< CAN_T::WU_EN: WAKUP_EN Position */
sahilmgandhi 18:6a4db94011d3 2022 #define CAN_WUEN_WAKUP_EN_Msk (0x1ul << CAN_WUEN_WAKUP_EN_Pos) /*!< CAN_T::WU_EN: WAKUP_EN Mask */
sahilmgandhi 18:6a4db94011d3 2023
sahilmgandhi 18:6a4db94011d3 2024 /* CAN WUSTATUS Bit Field Definitions */
sahilmgandhi 18:6a4db94011d3 2025 #define CAN_WUSTATUS_WAKUP_STS_Pos 0 /*!< CAN_T::WU_STATUS: WAKUP_STS Position */
sahilmgandhi 18:6a4db94011d3 2026 #define CAN_WUSTATUS_WAKUP_STS_Msk (0x1ul << CAN_WUSTATUS_WAKUP_STS_Pos) /*!< CAN_T::WU_STATUS: WAKUP_STS Mask */
sahilmgandhi 18:6a4db94011d3 2027
sahilmgandhi 18:6a4db94011d3 2028
sahilmgandhi 18:6a4db94011d3 2029 /**@}*/ /* CAN_CONST */
sahilmgandhi 18:6a4db94011d3 2030 /**@}*/ /* end of CAN register group */
sahilmgandhi 18:6a4db94011d3 2031
sahilmgandhi 18:6a4db94011d3 2032
sahilmgandhi 18:6a4db94011d3 2033 /*---------------------- System Clock Controller -------------------------*/
sahilmgandhi 18:6a4db94011d3 2034 /**
sahilmgandhi 18:6a4db94011d3 2035 @addtogroup CLK System Clock Controller(CLK)
sahilmgandhi 18:6a4db94011d3 2036 Memory Mapped Structure for CLK Controller
sahilmgandhi 18:6a4db94011d3 2037 @{ */
sahilmgandhi 18:6a4db94011d3 2038
sahilmgandhi 18:6a4db94011d3 2039
sahilmgandhi 18:6a4db94011d3 2040 typedef struct
sahilmgandhi 18:6a4db94011d3 2041 {
sahilmgandhi 18:6a4db94011d3 2042
sahilmgandhi 18:6a4db94011d3 2043
sahilmgandhi 18:6a4db94011d3 2044
sahilmgandhi 18:6a4db94011d3 2045
sahilmgandhi 18:6a4db94011d3 2046 /**
sahilmgandhi 18:6a4db94011d3 2047 * @var CLK_T::PWRCTL
sahilmgandhi 18:6a4db94011d3 2048 * Offset: 0x00 System Power-down Control Register
sahilmgandhi 18:6a4db94011d3 2049 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2050 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 2051 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 2052 * |[0] |HXTEN |External 4~24 MHz High-Speed Crystal Enable Bit (Write Protect)
sahilmgandhi 18:6a4db94011d3 2053 * | | |The bit default value is set by flash controller user configuration register CONFIG0 [26:24].
sahilmgandhi 18:6a4db94011d3 2054 * | | |When the default clock source is from external 4~24 MHz high-speed crystal, this bit is set to 1 automatically.
sahilmgandhi 18:6a4db94011d3 2055 * | | |0 = External 4 ~ 24 MHz high speed crystal oscillator (HXT) Disabled.
sahilmgandhi 18:6a4db94011d3 2056 * | | |1 = External 4 MH~ 24 z high speed crystal oscillator (HXT) Enabled.
sahilmgandhi 18:6a4db94011d3 2057 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 2058 * |[1] |LXTEN |External 32.768 KHz Low-Speed Crystal Enable Bit (Write Protect)
sahilmgandhi 18:6a4db94011d3 2059 * | | |0 = External 32.768 kHz low-speed crystal oscillator (LXT) Disabled.
sahilmgandhi 18:6a4db94011d3 2060 * | | |1 = External 32.768 kHz low-speed crystal oscillator (LXT) Enabled.
sahilmgandhi 18:6a4db94011d3 2061 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 2062 * |[2] |HIRCEN |Internal 22.1184 MHz High-Speed Oscillator Enable Bit (Write Protect)
sahilmgandhi 18:6a4db94011d3 2063 * | | |0 = Internal 22.1184 MHz high-speed RC oscillator (HIRC) Disabled.
sahilmgandhi 18:6a4db94011d3 2064 * | | |1 = Internal 22.1184 MHz high-speed RC oscillator (HIRC) Enabled.
sahilmgandhi 18:6a4db94011d3 2065 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 2066 * |[3] |LIRCEN |Internal 10 KHz Low-Speed Oscillator Enable Bit (Write Protect)
sahilmgandhi 18:6a4db94011d3 2067 * | | |0 = Internal 10 kHz low speed RC oscillator (LIRC) Disabled.
sahilmgandhi 18:6a4db94011d3 2068 * | | |1 = Internal 10 kHz low speed RC oscillator (LIRC) Enabled.
sahilmgandhi 18:6a4db94011d3 2069 * |[4] |PDWKDLY |Enable The Wake-Up Delay Counter (Write Protect)
sahilmgandhi 18:6a4db94011d3 2070 * | | |When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
sahilmgandhi 18:6a4db94011d3 2071 * | | |The delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz high-speed crystal, and 256 clock cycles when chip work at internal 22.1184 MHz high-speed oscillator.
sahilmgandhi 18:6a4db94011d3 2072 * | | |0 = Clock cycles delay Disabled.
sahilmgandhi 18:6a4db94011d3 2073 * | | |1 = Clock cycles delay Enabled.
sahilmgandhi 18:6a4db94011d3 2074 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 2075 * |[5] |PDWKIEN |Power-Down Mode Wake-Up Interrupt Enable Bit (Write Protect)
sahilmgandhi 18:6a4db94011d3 2076 * | | |0 = Power-down Mode Wake-up Interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 2077 * | | |1 = Power-down Mode Wake-up Interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 2078 * | | |Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high.
sahilmgandhi 18:6a4db94011d3 2079 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 2080 * |[6] |PDWKIF |Power-Down Mode Wake-Up Interrupt Status
sahilmgandhi 18:6a4db94011d3 2081 * | | |Set by "Power-down wake-up event", it indicates that resume from Power-down mode
sahilmgandhi 18:6a4db94011d3 2082 * | | |The flag is set if the EINT0~5, GPIO, USBH, USBD, OTG, UART0~3, WDT, CAN0, ACMP01, BOD, RTC, TMR0~3, I2C0~1 or TK wake-up occurred.
sahilmgandhi 18:6a4db94011d3 2083 * | | |Note1: Write 1 to clear the bit to 0.
sahilmgandhi 18:6a4db94011d3 2084 * | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
sahilmgandhi 18:6a4db94011d3 2085 * |[7] |PDEN |System Power-Down Enable (Write Protect)
sahilmgandhi 18:6a4db94011d3 2086 * | | |When this bit is set to 1, Power-down mode is enabled and chip Power-down behavior will depend on the PDWTCPU bit.
sahilmgandhi 18:6a4db94011d3 2087 * | | |(a) If the PDWTCPU is 0, then the chip enters Power-down mode immediately after the PDEN bit set.(default)
sahilmgandhi 18:6a4db94011d3 2088 * | | |(b) if the PDWTCPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.
sahilmgandhi 18:6a4db94011d3 2089 * | | |When chip wakes up from Power-down mode, this bit is auto cleared.
sahilmgandhi 18:6a4db94011d3 2090 * | | |Users need to set this bit again for next Power-down.
sahilmgandhi 18:6a4db94011d3 2091 * | | |In Power-down mode, external 4~24 MHz high-speed crystal and the internal 22.1184 MHz high-speed oscillator will be disabled in this mode, but the external 32.768 kHz low-speed crystal and internal 10 kHz low-speed oscillator are not controlled by Power-down mode.
sahilmgandhi 18:6a4db94011d3 2092 * | | |In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection.
sahilmgandhi 18:6a4db94011d3 2093 * | | |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from external 32.768 kHz low-speed crystal or the internal 10 kHz low-speed oscillator.
sahilmgandhi 18:6a4db94011d3 2094 * | | |0 = Chip operating normally or chip in idle mode because of WFI command.
sahilmgandhi 18:6a4db94011d3 2095 * | | |1 = Chip enters Power-down mode instant or wait CPU sleep command WFI.
sahilmgandhi 18:6a4db94011d3 2096 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 2097 * |[8] |PDWTCPU |This Bit Control The Power-Down Entry Condition (Write Protect)
sahilmgandhi 18:6a4db94011d3 2098 * | | |0 = Chip enters Power-down mode when the PDEN bit is set to 1.
sahilmgandhi 18:6a4db94011d3 2099 * | | |1 = Chip enters Power-down mode when the both PDWTCPU and PDEN bits are set to 1 and CPU run WFI instruction.
sahilmgandhi 18:6a4db94011d3 2100 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 2101 * |[11:10] |HXTGAIN |4~24 MHz High-Speed Crystal Gain Control Bit
sahilmgandhi 18:6a4db94011d3 2102 * | | |(Write Protect)
sahilmgandhi 18:6a4db94011d3 2103 * | | |This is a protected register. Please refer to open lock sequence to program it.
sahilmgandhi 18:6a4db94011d3 2104 * | | |Gain control is used to enlarge the gain of crystal to make sure crystal work normally.
sahilmgandhi 18:6a4db94011d3 2105 * | | |If gain control is enabled, crystal will consume more power than gain control off.
sahilmgandhi 18:6a4db94011d3 2106 * | | |00 = HXT frequency is lower than from 8 MHz.
sahilmgandhi 18:6a4db94011d3 2107 * | | |01 = HXT frequency is from 8 MHz to 12 MHz.
sahilmgandhi 18:6a4db94011d3 2108 * | | |10 = HXT frequency is from 12 MHz to 16 MHz.
sahilmgandhi 18:6a4db94011d3 2109 * | | |11 = HXT frequency is higher than 16 MHz.
sahilmgandhi 18:6a4db94011d3 2110 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 2111 * |[12] |HXTSELTYP |4~24 MHz High-Speed Crystal Type Select Bit (Write Protect)
sahilmgandhi 18:6a4db94011d3 2112 * | | |This is a protected register. Please refer to open lock sequence to program it.
sahilmgandhi 18:6a4db94011d3 2113 * | | |0 = Select INV type.
sahilmgandhi 18:6a4db94011d3 2114 * | | |1 = Select GM type.
sahilmgandhi 18:6a4db94011d3 2115 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 2116 * @var CLK_T::AHBCLK
sahilmgandhi 18:6a4db94011d3 2117 * Offset: 0x04 AHB Devices Clock Enable Control Register
sahilmgandhi 18:6a4db94011d3 2118 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2119 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 2120 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 2121 * |[1] |PDMACKEN |PDMA Controller Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2122 * | | |0 = PDMA peripheral clock Disabled.
sahilmgandhi 18:6a4db94011d3 2123 * | | |1 = PDMA peripheral clock Enabled.
sahilmgandhi 18:6a4db94011d3 2124 * |[2] |ISPCKEN |Flash ISP Controller Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2125 * | | |0 = Flash ISP peripheral clock Disabled.
sahilmgandhi 18:6a4db94011d3 2126 * | | |1 = Flash ISP peripheral clock Enabled.
sahilmgandhi 18:6a4db94011d3 2127 * |[3] |EBICKEN |EBI Controller Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2128 * | | |0 = EBI peripheral clock Disabled.
sahilmgandhi 18:6a4db94011d3 2129 * | | |1 = EBI peripheral clock Enabled.
sahilmgandhi 18:6a4db94011d3 2130 * |[4] |USBHCKEN |USB HOST Controller Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2131 * | | |0 = USB HOST peripheral clock Disabled.
sahilmgandhi 18:6a4db94011d3 2132 * | | |1 = USB HOST peripheral clock Enabled.
sahilmgandhi 18:6a4db94011d3 2133 * |[7] |CRCCKEN |CRC Generator Controller Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2134 * | | |0 = CRC peripheral clock Disabled.
sahilmgandhi 18:6a4db94011d3 2135 * | | |1 = CRC peripheral clock Enabled.
sahilmgandhi 18:6a4db94011d3 2136 * |[15] |FMCIDLE |Flash Memory Controller Clock Enable Bit In IDLE Mode
sahilmgandhi 18:6a4db94011d3 2137 * | | |0 = FMC peripheral clock Disabled when chip operating at IDLE mode.
sahilmgandhi 18:6a4db94011d3 2138 * | | |1 = FMC peripheral clock Enabled when chip operating at IDLE mode.
sahilmgandhi 18:6a4db94011d3 2139 * @var CLK_T::APBCLK0
sahilmgandhi 18:6a4db94011d3 2140 * Offset: 0x08 APB Devices Clock Enable Control Register 0
sahilmgandhi 18:6a4db94011d3 2141 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2142 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 2143 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 2144 * |[0] |WDTCKEN |Watchdog Timer Clock Enable Bit (Write Protect)
sahilmgandhi 18:6a4db94011d3 2145 * | | |0 = Watchdog Timer Clock Disabled.
sahilmgandhi 18:6a4db94011d3 2146 * | | |1 = Watchdog Timer Clock Enabled.
sahilmgandhi 18:6a4db94011d3 2147 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 2148 * |[1] |RTCCKEN |Real-Time-Clock APB Interface Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2149 * | | |This bit is used to control the RTC APB clock only.
sahilmgandhi 18:6a4db94011d3 2150 * | | |The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8]).
sahilmgandhi 18:6a4db94011d3 2151 * | | |It can be selected to external 32.768 kHz low speed crystal or internal 10 kHz low speed oscillator.
sahilmgandhi 18:6a4db94011d3 2152 * | | |0 = RTC Clock Disabled.
sahilmgandhi 18:6a4db94011d3 2153 * | | |1 = RTC Clock Enabled.
sahilmgandhi 18:6a4db94011d3 2154 * |[2] |TMR0CKEN |Timer0 Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2155 * | | |0 = Timer0 Clock Disabled.
sahilmgandhi 18:6a4db94011d3 2156 * | | |1 = Timer0 Clock Enabled.
sahilmgandhi 18:6a4db94011d3 2157 * |[3] |TMR1CKEN |Timer1 Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2158 * | | |0 = Timer1 Clock Disabled.
sahilmgandhi 18:6a4db94011d3 2159 * | | |1 = Timer1 Clock Enabled.
sahilmgandhi 18:6a4db94011d3 2160 * |[4] |TMR2CKEN |Timer2 Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2161 * | | |0 = Timer2 Clock Disabled.
sahilmgandhi 18:6a4db94011d3 2162 * | | |1 = Timer2 Clock Enabled.
sahilmgandhi 18:6a4db94011d3 2163 * |[5] |TMR3CKEN |Timer3 Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2164 * | | |0 = Timer3 Clock Disabled.
sahilmgandhi 18:6a4db94011d3 2165 * | | |1 = Timer3 Clock Enabled.
sahilmgandhi 18:6a4db94011d3 2166 * |[6] |CLKOCKEN |CLKO Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2167 * | | |0 = CLKO Clock Disabled.
sahilmgandhi 18:6a4db94011d3 2168 * | | |1 = CLKO Clock Enabled.
sahilmgandhi 18:6a4db94011d3 2169 * |[7] |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2170 * | | |0 = Analog Comparator 0/1 Clock Disabled.
sahilmgandhi 18:6a4db94011d3 2171 * | | |1 = Analog Comparator 0/1 Clock Enabled.
sahilmgandhi 18:6a4db94011d3 2172 * |[8] |I2C0CKEN |I2C0 Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2173 * | | |0 = I2C0 Clock Disabled.
sahilmgandhi 18:6a4db94011d3 2174 * | | |1 = I2C0 Clock Enabled.
sahilmgandhi 18:6a4db94011d3 2175 * |[9] |I2C1CKEN |I2C1 Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2176 * | | |0 = I2C1 Clock Disabled.
sahilmgandhi 18:6a4db94011d3 2177 * | | |1 = I2C1 Clock Enabled.
sahilmgandhi 18:6a4db94011d3 2178 * |[12] |SPI0CKEN |SPI0 Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2179 * | | |0 = SPI0 Clock Disabled.
sahilmgandhi 18:6a4db94011d3 2180 * | | |1 = SPI0 Clock Enabled.
sahilmgandhi 18:6a4db94011d3 2181 * |[13] |SPI1CKEN |SPI1 Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2182 * | | |0 = SPI1 Clock Disabled.
sahilmgandhi 18:6a4db94011d3 2183 * | | |1 = SPI1 Clock Enabled.
sahilmgandhi 18:6a4db94011d3 2184 * |[14] |SPI2CKEN |SPI2 Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2185 * | | |0 = SPI2 Clock Disabled.
sahilmgandhi 18:6a4db94011d3 2186 * | | |1 = SPI2 Clock Enabled.
sahilmgandhi 18:6a4db94011d3 2187 * |[16] |UART0CKEN |UART0 Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2188 * | | |0 = UART0 clock Disabled.
sahilmgandhi 18:6a4db94011d3 2189 * | | |1 = UART0 clock Enabled.
sahilmgandhi 18:6a4db94011d3 2190 * |[17] |UART1CKEN |UART1 Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2191 * | | |0 = UART1 clock Disabled.
sahilmgandhi 18:6a4db94011d3 2192 * | | |1 = UART1 clock Enabled.
sahilmgandhi 18:6a4db94011d3 2193 * |[18] |UART2CKEN |UART2 Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2194 * | | |0 = UART2 clock Disabled.
sahilmgandhi 18:6a4db94011d3 2195 * | | |1 = UART2 clock Enabled.
sahilmgandhi 18:6a4db94011d3 2196 * |[19] |UART3CKEN |UART3 Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2197 * | | |0 = UART3 clock Disabled.
sahilmgandhi 18:6a4db94011d3 2198 * | | |1 = UART3 clock Enabled.
sahilmgandhi 18:6a4db94011d3 2199 * |[24] |CAN0CKEN |CAN0 Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2200 * | | |0 = CAN0 clock Disabled.
sahilmgandhi 18:6a4db94011d3 2201 * | | |1 = CAN0 clock Enabled.
sahilmgandhi 18:6a4db94011d3 2202 * |[26] |OTGCKEN |USB OTG Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2203 * | | |0 = USB OTG clock Disabled.
sahilmgandhi 18:6a4db94011d3 2204 * | | |1 = USB OTG clock Enabled.
sahilmgandhi 18:6a4db94011d3 2205 * |[27] |USBDCKEN |USB Device Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2206 * | | |0 = USB Device clock Disabled.
sahilmgandhi 18:6a4db94011d3 2207 * | | |1 = USB Device clock Enabled.
sahilmgandhi 18:6a4db94011d3 2208 * |[28] |EADCCKEN |Enhanced Analog-Digital-Converter (EADC) Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2209 * | | |0 = EADC clock Disabled.
sahilmgandhi 18:6a4db94011d3 2210 * | | |1 = EADC clock Enabled.
sahilmgandhi 18:6a4db94011d3 2211 * @var CLK_T::APBCLK1
sahilmgandhi 18:6a4db94011d3 2212 * Offset: 0x0C APB Devices Clock Enable Control Register 1
sahilmgandhi 18:6a4db94011d3 2213 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2214 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 2215 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 2216 * |[0] |SC0CKEN |SC0 Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2217 * | | |0 = SC0 Clock Disabled.
sahilmgandhi 18:6a4db94011d3 2218 * | | |1 = SC0 Clock Enabled.
sahilmgandhi 18:6a4db94011d3 2219 * |[12] |DACCKEN |DAC Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2220 * | | |0 = DAC Clock Disabled.
sahilmgandhi 18:6a4db94011d3 2221 * | | |1 = DAC Clock Enabled.
sahilmgandhi 18:6a4db94011d3 2222 * |[16] |PWM0CKEN |PWM0 Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2223 * | | |0 = PWM0 Clock Disabled.
sahilmgandhi 18:6a4db94011d3 2224 * | | |1 = PWM0 Clock Enabled.
sahilmgandhi 18:6a4db94011d3 2225 * |[17] |PWM1CKEN |PWM1 Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2226 * | | |0 = PWM1 Clock Disabled.
sahilmgandhi 18:6a4db94011d3 2227 * | | |1 = PWM1 Clock Enabled.
sahilmgandhi 18:6a4db94011d3 2228 * |[25] |TKCKEN |Touch Key Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 2229 * | | |0 = Touch Key Clock Disabled.
sahilmgandhi 18:6a4db94011d3 2230 * | | |1 = Touch key Clock Enabled.
sahilmgandhi 18:6a4db94011d3 2231 * @var CLK_T::CLKSEL0
sahilmgandhi 18:6a4db94011d3 2232 * Offset: 0x10 Clock Source Select Control Register 0
sahilmgandhi 18:6a4db94011d3 2233 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2234 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 2235 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 2236 * |[2:0] |HCLKSEL |HCLK Clock Source Selection (Write Protect)
sahilmgandhi 18:6a4db94011d3 2237 * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on.
sahilmgandhi 18:6a4db94011d3 2238 * | | |The default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration register of Flash controller by any reset.
sahilmgandhi 18:6a4db94011d3 2239 * | | |Therefore the default value is either 000b or 111b.
sahilmgandhi 18:6a4db94011d3 2240 * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
sahilmgandhi 18:6a4db94011d3 2241 * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
sahilmgandhi 18:6a4db94011d3 2242 * | | |010 = Clock source from PLL clock.
sahilmgandhi 18:6a4db94011d3 2243 * | | |011 = Clock source from internal 10 kHz low-speed oscillator clock.
sahilmgandhi 18:6a4db94011d3 2244 * | | |111= Clock source from internal 22.1184 MHz high-speed oscillator clock.
sahilmgandhi 18:6a4db94011d3 2245 * | | |Other = Reserved.
sahilmgandhi 18:6a4db94011d3 2246 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 2247 * |[5:3] |STCLKSEL |Cortex-M4 SysTick Clock Source Selection (Write Protect)
sahilmgandhi 18:6a4db94011d3 2248 * | | |If SYST_CTRL[2]=0, SysTick uses listed clock source below.
sahilmgandhi 18:6a4db94011d3 2249 * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
sahilmgandhi 18:6a4db94011d3 2250 * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
sahilmgandhi 18:6a4db94011d3 2251 * | | |010 = Clock source from external 4~24 MHz high-speed crystal clock/2.
sahilmgandhi 18:6a4db94011d3 2252 * | | |011 = Clock source from HCLK/2.
sahilmgandhi 18:6a4db94011d3 2253 * | | |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock/2.
sahilmgandhi 18:6a4db94011d3 2254 * | | |Note: if SysTick clock source is not from HCLK (i.e.
sahilmgandhi 18:6a4db94011d3 2255 * | | |SYST_CTRL[2] = 0), SysTick clock source must less than or equal to HCLK/2.
sahilmgandhi 18:6a4db94011d3 2256 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 2257 * |[6] |PCLK0SEL |PCLK0 Clock Source Selection (Write Protect)
sahilmgandhi 18:6a4db94011d3 2258 * | | |0 = APB0 BUS clock source from HCLK.
sahilmgandhi 18:6a4db94011d3 2259 * | | |1 = APB0 BUS clock source from HCLK/2.
sahilmgandhi 18:6a4db94011d3 2260 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 2261 * |[7] |PCLK1SEL |PCLK1 Clock Source Selection (Write Protect)
sahilmgandhi 18:6a4db94011d3 2262 * | | |0 = APB1 BUS clock source from HCLK.
sahilmgandhi 18:6a4db94011d3 2263 * | | |1 = APB1 BUS clock source from HCLK/2.
sahilmgandhi 18:6a4db94011d3 2264 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 2265 * @var CLK_T::CLKSEL1
sahilmgandhi 18:6a4db94011d3 2266 * Offset: 0x14 Clock Source Select Control Register 1
sahilmgandhi 18:6a4db94011d3 2267 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2268 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 2269 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 2270 * |[1:0] |WDTSEL |Watchdog Timer Clock Source Selection (Write Protect)
sahilmgandhi 18:6a4db94011d3 2271 * | | |00 = Reserved.
sahilmgandhi 18:6a4db94011d3 2272 * | | |01 = Clock source from external 32.768 kHz low-speed crystal clock.
sahilmgandhi 18:6a4db94011d3 2273 * | | |10 = Clock source from PCLK0/2048 clock.
sahilmgandhi 18:6a4db94011d3 2274 * | | |11 = Clock source from internal 10 kHz low-speed oscillator clock.
sahilmgandhi 18:6a4db94011d3 2275 * |[10:8] |TMR0SEL |TIMER0 Clock Source Selection
sahilmgandhi 18:6a4db94011d3 2276 * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
sahilmgandhi 18:6a4db94011d3 2277 * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
sahilmgandhi 18:6a4db94011d3 2278 * | | |010 = Clock source from PCLK0.
sahilmgandhi 18:6a4db94011d3 2279 * | | |011 = Clock source from external clock T0 pin
sahilmgandhi 18:6a4db94011d3 2280 * | | |101 = Clock source from internal 10 kHz low-speed oscillator clock.
sahilmgandhi 18:6a4db94011d3 2281 * | | |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
sahilmgandhi 18:6a4db94011d3 2282 * | | |Others = Reserved.
sahilmgandhi 18:6a4db94011d3 2283 * |[14:12] |TMR1SEL |TIMER1 Clock Source Selection
sahilmgandhi 18:6a4db94011d3 2284 * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
sahilmgandhi 18:6a4db94011d3 2285 * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
sahilmgandhi 18:6a4db94011d3 2286 * | | |010 = Clock source from PCLK0.
sahilmgandhi 18:6a4db94011d3 2287 * | | |011 = Clock source from external clock T1 pin
sahilmgandhi 18:6a4db94011d3 2288 * | | |101 = Clock source from internal 10 kHz low-speed oscillator clock.
sahilmgandhi 18:6a4db94011d3 2289 * | | |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
sahilmgandhi 18:6a4db94011d3 2290 * | | |Others = Reserved.
sahilmgandhi 18:6a4db94011d3 2291 * |[18:16] |TMR2SEL |TIMER2 Clock Source Selection
sahilmgandhi 18:6a4db94011d3 2292 * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
sahilmgandhi 18:6a4db94011d3 2293 * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
sahilmgandhi 18:6a4db94011d3 2294 * | | |010 = Clock source from PCLK1.
sahilmgandhi 18:6a4db94011d3 2295 * | | |011 = Clock source from external clock T2 pin
sahilmgandhi 18:6a4db94011d3 2296 * | | |101 = Clock source from internal 10 kHz low-speed oscillator clock.
sahilmgandhi 18:6a4db94011d3 2297 * | | |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
sahilmgandhi 18:6a4db94011d3 2298 * | | |Others = Reserved.
sahilmgandhi 18:6a4db94011d3 2299 * |[22:20] |TMR3SEL |TIMER3 Clock Source Selection
sahilmgandhi 18:6a4db94011d3 2300 * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
sahilmgandhi 18:6a4db94011d3 2301 * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
sahilmgandhi 18:6a4db94011d3 2302 * | | |010 = Clock source from PCLK1.
sahilmgandhi 18:6a4db94011d3 2303 * | | |011 = Clock source from external clock T3 pin.
sahilmgandhi 18:6a4db94011d3 2304 * | | |101 = Clock source from internal 10 kHz low-speed oscillator clock.
sahilmgandhi 18:6a4db94011d3 2305 * | | |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
sahilmgandhi 18:6a4db94011d3 2306 * | | |Others = Reserved.
sahilmgandhi 18:6a4db94011d3 2307 * |[25:24] |UARTSEL |UART Clock Source Selection
sahilmgandhi 18:6a4db94011d3 2308 * | | |00 = Clock source from external 4~24 MHz high-speed crystal clock (HXT).
sahilmgandhi 18:6a4db94011d3 2309 * | | |01 = Clock source from PLL clock.
sahilmgandhi 18:6a4db94011d3 2310 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
sahilmgandhi 18:6a4db94011d3 2311 * | | |11 = Clock source from internal 22.1184 MHz high-speed oscillator clock (HIRC).
sahilmgandhi 18:6a4db94011d3 2312 * |[29:28] |CLKOSEL |Clock Divider Clock Source Selection
sahilmgandhi 18:6a4db94011d3 2313 * | | |00 = Clock source from external 4~24 MHz high-speed crystal clock.
sahilmgandhi 18:6a4db94011d3 2314 * | | |01 = Clock source from external 32.768 kHz low-speed crystal clock.
sahilmgandhi 18:6a4db94011d3 2315 * | | |10 = Clock source from HCLK.
sahilmgandhi 18:6a4db94011d3 2316 * | | |11 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
sahilmgandhi 18:6a4db94011d3 2317 * |[31:30] |WWDTSEL |Window Watchdog Timer Clock Source Selection
sahilmgandhi 18:6a4db94011d3 2318 * | | |10 = Clock source from PCLK0/2048 clock.
sahilmgandhi 18:6a4db94011d3 2319 * | | |11 = Clock source from internal 10 kHz low-speed oscillator clock.
sahilmgandhi 18:6a4db94011d3 2320 * | | |Others = Reserved.
sahilmgandhi 18:6a4db94011d3 2321 * @var CLK_T::CLKSEL2
sahilmgandhi 18:6a4db94011d3 2322 * Offset: 0x18 Clock Source Select Control Register 2
sahilmgandhi 18:6a4db94011d3 2323 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2324 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 2325 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 2326 * |[0] |PWM0SEL |PWM0 Clock Source Selection
sahilmgandhi 18:6a4db94011d3 2327 * | | |The peripheral clock source of PWM0 is defined by PWM0SEL.
sahilmgandhi 18:6a4db94011d3 2328 * | | |0 = Clock source from PLL clock.
sahilmgandhi 18:6a4db94011d3 2329 * | | |1 = Clock source from PCLK0.
sahilmgandhi 18:6a4db94011d3 2330 * |[1] |PWM1SEL |PWM1 Clock Source Selection
sahilmgandhi 18:6a4db94011d3 2331 * | | |The peripheral clock source of PWM1 is defined by PWM1SEL.
sahilmgandhi 18:6a4db94011d3 2332 * | | |0 = Clock source from PLL clock.
sahilmgandhi 18:6a4db94011d3 2333 * | | |1 = Clock source from PCLK1.
sahilmgandhi 18:6a4db94011d3 2334 * |[3:2] |SPI0SEL |SPI0 Clock Source Selection
sahilmgandhi 18:6a4db94011d3 2335 * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
sahilmgandhi 18:6a4db94011d3 2336 * | | |01 = Clock source from PLL clock.
sahilmgandhi 18:6a4db94011d3 2337 * | | |10 = Clock source from PCLK0.
sahilmgandhi 18:6a4db94011d3 2338 * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
sahilmgandhi 18:6a4db94011d3 2339 * |[5:4] |SPI1SEL |SPI1 Clock Source Selection
sahilmgandhi 18:6a4db94011d3 2340 * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
sahilmgandhi 18:6a4db94011d3 2341 * | | |01 = Clock source from PLL clock.
sahilmgandhi 18:6a4db94011d3 2342 * | | |10 = Clock source from PCLK1.
sahilmgandhi 18:6a4db94011d3 2343 * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
sahilmgandhi 18:6a4db94011d3 2344 * |[7:6] |SPI2SEL |SPI2 Clock Source Selection
sahilmgandhi 18:6a4db94011d3 2345 * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
sahilmgandhi 18:6a4db94011d3 2346 * | | |01 = Clock source from PLL clock.
sahilmgandhi 18:6a4db94011d3 2347 * | | |10 = Clock source from PCLK0.
sahilmgandhi 18:6a4db94011d3 2348 * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
sahilmgandhi 18:6a4db94011d3 2349 * @var CLK_T::CLKSEL3
sahilmgandhi 18:6a4db94011d3 2350 * Offset: 0x1C Clock Source Select Control Register 3
sahilmgandhi 18:6a4db94011d3 2351 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2352 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 2353 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 2354 * |[1:0] |SC0SEL |SC0 Clock Source Selection
sahilmgandhi 18:6a4db94011d3 2355 * | | |00 = Clock source from external 4~24 MHz high-speed crystal clock.
sahilmgandhi 18:6a4db94011d3 2356 * | | |01 = Clock source from PLL clock.
sahilmgandhi 18:6a4db94011d3 2357 * | | |10 = Clock source from PCLK0.
sahilmgandhi 18:6a4db94011d3 2358 * | | |11 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
sahilmgandhi 18:6a4db94011d3 2359 * |[8] |RTCSEL |RTC Clock Source Selection
sahilmgandhi 18:6a4db94011d3 2360 * | | |0 = Clock source from external 32.768 kHz low-speed oscillator.
sahilmgandhi 18:6a4db94011d3 2361 * | | |1 = Clock source from internal 10 kHz low speed RC oscillator.
sahilmgandhi 18:6a4db94011d3 2362 * @var CLK_T::CLKDIV0
sahilmgandhi 18:6a4db94011d3 2363 * Offset: 0x20 Clock Divider Number Register 0
sahilmgandhi 18:6a4db94011d3 2364 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2365 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 2366 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 2367 * |[3:0] |HCLKDIV |HCLK Clock Divide Number From HCLK Clock Source
sahilmgandhi 18:6a4db94011d3 2368 * | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1).
sahilmgandhi 18:6a4db94011d3 2369 * |[7:4] |USBDIV |USB Clock Divide Number From PLL Clock
sahilmgandhi 18:6a4db94011d3 2370 * | | |USB clock frequency = (PLL frequency) / (USBDIV + 1).
sahilmgandhi 18:6a4db94011d3 2371 * |[11:8] |UARTDIV |UART Clock Divide Number From UART Clock Source
sahilmgandhi 18:6a4db94011d3 2372 * | | |UART clock frequency = (UART clock source frequency) / (UARTDIV + 1).
sahilmgandhi 18:6a4db94011d3 2373 * |[23:16] |EADCDIV |EADC Clock Divide Number From EADC Clock Source
sahilmgandhi 18:6a4db94011d3 2374 * | | |EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1).
sahilmgandhi 18:6a4db94011d3 2375 * @var CLK_T::CLKDIV1
sahilmgandhi 18:6a4db94011d3 2376 * Offset: 0x24 Clock Divider Number Register 1
sahilmgandhi 18:6a4db94011d3 2377 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2378 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 2379 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 2380 * |[7:0] |SC0DIV |SC0 Clock Divide Number From SC0 Clock Source
sahilmgandhi 18:6a4db94011d3 2381 * | | |SC0 clock frequency = (SC0 clock source frequency ) / (SC0DIV + 1).
sahilmgandhi 18:6a4db94011d3 2382 * @var CLK_T::PLLCTL
sahilmgandhi 18:6a4db94011d3 2383 * Offset: 0x40 PLL Control Register
sahilmgandhi 18:6a4db94011d3 2384 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2385 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 2386 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 2387 * |[8:0] |FBDIV |PLL Feedback Divider Control Pins (Write Protect)
sahilmgandhi 18:6a4db94011d3 2388 * | | |Refer to the formulas below the table.
sahilmgandhi 18:6a4db94011d3 2389 * |[13:9] |INDIV |PLL Input Divider Control Pins (Write Protect)
sahilmgandhi 18:6a4db94011d3 2390 * | | |Refer to the formulas below the table.
sahilmgandhi 18:6a4db94011d3 2391 * |[15:14] |OUTDIV |PLL Output Divider Control Pins (Write Protect)
sahilmgandhi 18:6a4db94011d3 2392 * | | |Refer to the formulas below the table.
sahilmgandhi 18:6a4db94011d3 2393 * |[16] |PD |Power-Down Mode (Write Protect)
sahilmgandhi 18:6a4db94011d3 2394 * | | |If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.
sahilmgandhi 18:6a4db94011d3 2395 * | | |0 = PLL is in normal mode.
sahilmgandhi 18:6a4db94011d3 2396 * | | |1 = PLL is in Power-down mode (default).
sahilmgandhi 18:6a4db94011d3 2397 * |[17] |BP |PLL Bypass Control (Write Protect)
sahilmgandhi 18:6a4db94011d3 2398 * | | |0 = PLL is in normal mode (default).
sahilmgandhi 18:6a4db94011d3 2399 * | | |1 = PLL clock output is same as PLL input clock FIN.
sahilmgandhi 18:6a4db94011d3 2400 * |[18] |OE |PLL OE (FOUT Enable) Pin Control (Write Protect)
sahilmgandhi 18:6a4db94011d3 2401 * | | |0 = PLL FOUT Enabled.
sahilmgandhi 18:6a4db94011d3 2402 * | | |1 = PLL FOUT is fixed low.
sahilmgandhi 18:6a4db94011d3 2403 * |[19] |PLLSRC |PLL Source Clock Selection (Write Protect)
sahilmgandhi 18:6a4db94011d3 2404 * | | |0 = PLL source clock from external 4~24 MHz high-speed crystal (HXT).
sahilmgandhi 18:6a4db94011d3 2405 * | | |1 = PLL source clock from internal 22.1184 MHz high-speed oscillator (HIRC).
sahilmgandhi 18:6a4db94011d3 2406 * |[23] |STBSEL |PLL Stable Counter Selection (Write Protect)
sahilmgandhi 18:6a4db94011d3 2407 * | | |0 = PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12MHz).
sahilmgandhi 18:6a4db94011d3 2408 * | | |1 = PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12MHz).
sahilmgandhi 18:6a4db94011d3 2409 * @var CLK_T::STATUS
sahilmgandhi 18:6a4db94011d3 2410 * Offset: 0x50 Clock Status Monitor Register
sahilmgandhi 18:6a4db94011d3 2411 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2412 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 2413 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 2414 * |[0] |HXTSTB |External 4~24 MHz High-Speed Crystal Clock Source Stable Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 2415 * | | |0 = External 4~24 MHz high-speed crystal clock is not stable or disabled.
sahilmgandhi 18:6a4db94011d3 2416 * | | |1 = External 4~24 MHz high-speed crystal clock is stable and enabled.
sahilmgandhi 18:6a4db94011d3 2417 * |[1] |LXTSTB |External 32.768 kHz Low-Speed Crystal Clock Source Stable Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 2418 * | | |0 = External 32.768 kHz low-speed crystal clock is not stable or disabled.
sahilmgandhi 18:6a4db94011d3 2419 * | | |1 = External 32.768 kHz low-speed crystal clock is stabled and enabled.
sahilmgandhi 18:6a4db94011d3 2420 * |[2] |PLLSTB |Internal PLL Clock Source Stable Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 2421 * | | |0 = Internal PLL clock is not stable or disabled.
sahilmgandhi 18:6a4db94011d3 2422 * | | |1 = Internal PLL clock is stable and enabled.
sahilmgandhi 18:6a4db94011d3 2423 * |[3] |LIRCSTB |Internal 10 KHz Low-Speed Oscillator Clock Source Stable Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 2424 * | | |0 = Internal 10 kHz low-speed oscillator clock is not stable or disabled.
sahilmgandhi 18:6a4db94011d3 2425 * | | |1 = Internal 10 kHz low-speed oscillator clock is stable and enabled.
sahilmgandhi 18:6a4db94011d3 2426 * |[4] |HIRCSTB |Internal 22.1184 MHz High-Speed Oscillator Clock Source Stable Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 2427 * | | |0 = Internal 22.1184 MHz high-speed oscillator clock is not stable or disabled.
sahilmgandhi 18:6a4db94011d3 2428 * | | |1 = Internal 22.1184 MHz high-speed oscillator clock is stable and enabled.
sahilmgandhi 18:6a4db94011d3 2429 * |[7] |CLKSFAIL |Clock Switching Fail Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 2430 * | | |This bit is updated when software switches system clock source.
sahilmgandhi 18:6a4db94011d3 2431 * | | |If switch target clock is stable, this bit will be set to 0.
sahilmgandhi 18:6a4db94011d3 2432 * | | |If switch target clock is not stable, this bit will be set to 1.
sahilmgandhi 18:6a4db94011d3 2433 * | | |0 = Clock switching success.
sahilmgandhi 18:6a4db94011d3 2434 * | | |1 = Clock switching failure.
sahilmgandhi 18:6a4db94011d3 2435 * | | |Note: Write 1 to clear the bit to 0.
sahilmgandhi 18:6a4db94011d3 2436 * @var CLK_T::CLKOCTL
sahilmgandhi 18:6a4db94011d3 2437 * Offset: 0x60 Clock Output Control Register
sahilmgandhi 18:6a4db94011d3 2438 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2439 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 2440 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 2441 * |[3:0] |FREQSEL |Clock Output Frequency Selection
sahilmgandhi 18:6a4db94011d3 2442 * | | |The formula of output frequency is
sahilmgandhi 18:6a4db94011d3 2443 * | | |Fout = Fin/2(N+1).
sahilmgandhi 18:6a4db94011d3 2444 * | | |Fin is the input clock frequency.
sahilmgandhi 18:6a4db94011d3 2445 * | | |Fout is the frequency of divider output clock.
sahilmgandhi 18:6a4db94011d3 2446 * | | |N is the 4-bit value of FREQSEL[3:0].
sahilmgandhi 18:6a4db94011d3 2447 * |[4] |CLKOEN |Clock Output Enable Bit
sahilmgandhi 18:6a4db94011d3 2448 * | | |0 =Clock Output function Disabled.
sahilmgandhi 18:6a4db94011d3 2449 * | | |1 = Clock Output function Enabled.
sahilmgandhi 18:6a4db94011d3 2450 * |[5] |DIV1EN |Clock Output Divide One Enable Bit
sahilmgandhi 18:6a4db94011d3 2451 * | | |0 = Clock Output will output clock with source frequency divided by FREQSEL.
sahilmgandhi 18:6a4db94011d3 2452 * | | |1 = Clock Output will output clock with source frequency.
sahilmgandhi 18:6a4db94011d3 2453 * |[6] |CLK1HZEN |Clock Output 1Hz Enable Bit
sahilmgandhi 18:6a4db94011d3 2454 * | | |0 = 1 Hz clock output for 32.768kHz frequency compensation Disabled.
sahilmgandhi 18:6a4db94011d3 2455 * | | |1 = 1 Hz clock output for 332.768kHz frequency compensation Enabled.
sahilmgandhi 18:6a4db94011d3 2456 * @var CLK_T::CLKDCTL
sahilmgandhi 18:6a4db94011d3 2457 * Offset: 0x70 Clock Fail Detector Control Register
sahilmgandhi 18:6a4db94011d3 2458 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2459 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 2460 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 2461 * |[4] |HXTFDEN |HXT Clock Fail Detector Enable Bit
sahilmgandhi 18:6a4db94011d3 2462 * | | |0 = HXT clock Fail detector Disabled.
sahilmgandhi 18:6a4db94011d3 2463 * | | |1 = HXT clock Fail detector Enabled.
sahilmgandhi 18:6a4db94011d3 2464 * |[5] |HXTFIEN |HXT Clock Fail Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 2465 * | | |0 = HXT clock Fail interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 2466 * | | |1 = HXT clock Fail interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 2467 * |[12] |LXTFDEN |LXT Clock Fail Detector Enable Bit
sahilmgandhi 18:6a4db94011d3 2468 * | | |0 = LXT clock Fail detector Disabled.
sahilmgandhi 18:6a4db94011d3 2469 * | | |1 = LXT clock Fail detector Enabled.
sahilmgandhi 18:6a4db94011d3 2470 * |[13] |LXTFIEN |LXT Clock Fail Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 2471 * | | |0 = LXT clock Fail interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 2472 * | | |1 = LXT clock Fail interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 2473 * |[16] |HXTFQDEN |HXT Clock Frequency Monitor Enable Bit
sahilmgandhi 18:6a4db94011d3 2474 * | | |0 = HXT clock frequency monitor Disabled.
sahilmgandhi 18:6a4db94011d3 2475 * | | |1 = HXT clock frequency monitor Enabled.
sahilmgandhi 18:6a4db94011d3 2476 * |[17] |HXTFQIEN |HXT Clock Frequency Monitor Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 2477 * | | |0 = HXT clock frequency monitor fail interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 2478 * | | |1 = HXT clock frequency monitor fail interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 2479 * @var CLK_T::CLKDSTS
sahilmgandhi 18:6a4db94011d3 2480 * Offset: 0x74 Clock Fail Detector Status Register
sahilmgandhi 18:6a4db94011d3 2481 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2482 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 2483 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 2484 * |[0] |HXTFIF |HXT Clock Fail Interrupt Flag
sahilmgandhi 18:6a4db94011d3 2485 * | | |0 = HXT clock normal.
sahilmgandhi 18:6a4db94011d3 2486 * | | |1 = HXT clock stop
sahilmgandhi 18:6a4db94011d3 2487 * | | |Note: Write 1 to clear the bit to 0.
sahilmgandhi 18:6a4db94011d3 2488 * |[1] |LXTFIF |LXT Clock Fail Interrupt Flag
sahilmgandhi 18:6a4db94011d3 2489 * | | |0 = LXT clock normal.
sahilmgandhi 18:6a4db94011d3 2490 * | | |1 = LXT stop
sahilmgandhi 18:6a4db94011d3 2491 * | | |Note: Write 1 to clear the bit to 0.
sahilmgandhi 18:6a4db94011d3 2492 * |[8] |HXTFQIF |HXT Clock Frequency Monitor Interrupt Flag
sahilmgandhi 18:6a4db94011d3 2493 * | | |0 = HXT clock normal.
sahilmgandhi 18:6a4db94011d3 2494 * | | |1 = HXT clock frequency abnormal
sahilmgandhi 18:6a4db94011d3 2495 * | | |Note: Write 1 to clear the bit to 0.
sahilmgandhi 18:6a4db94011d3 2496 * @var CLK_T::CDUPB
sahilmgandhi 18:6a4db94011d3 2497 * Offset: 0x78 Clock Frequency Detector Upper Boundary Register
sahilmgandhi 18:6a4db94011d3 2498 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2499 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 2500 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 2501 * |[9:0] |UPERBD |HXT Clock Frequency Detector Upper Boundary
sahilmgandhi 18:6a4db94011d3 2502 * | | |The bits define the high value of frequency monitor window.
sahilmgandhi 18:6a4db94011d3 2503 * | | |When HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1.
sahilmgandhi 18:6a4db94011d3 2504 * @var CLK_T::CDLOWB
sahilmgandhi 18:6a4db94011d3 2505 * Offset: 0x7C Clock Frequency Detector Low Boundary Register
sahilmgandhi 18:6a4db94011d3 2506 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2507 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 2508 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 2509 * |[9:0] |LOWERBD |HXT Clock Frequency Detector Low Boundary
sahilmgandhi 18:6a4db94011d3 2510 * | | |The bits define the low value of frequency monitor window.
sahilmgandhi 18:6a4db94011d3 2511 * | | |When HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will set to 1.
sahilmgandhi 18:6a4db94011d3 2512 */
sahilmgandhi 18:6a4db94011d3 2513
sahilmgandhi 18:6a4db94011d3 2514 __IO uint32_t PWRCTL; /* Offset: 0x00 System Power-down Control Register */
sahilmgandhi 18:6a4db94011d3 2515 __IO uint32_t AHBCLK; /* Offset: 0x04 AHB Devices Clock Enable Control Register */
sahilmgandhi 18:6a4db94011d3 2516 __IO uint32_t APBCLK0; /* Offset: 0x08 APB Devices Clock Enable Control Register 0 */
sahilmgandhi 18:6a4db94011d3 2517 __IO uint32_t APBCLK1; /* Offset: 0x0C APB Devices Clock Enable Control Register 1 */
sahilmgandhi 18:6a4db94011d3 2518 __IO uint32_t CLKSEL0; /* Offset: 0x10 Clock Source Select Control Register 0 */
sahilmgandhi 18:6a4db94011d3 2519 __IO uint32_t CLKSEL1; /* Offset: 0x14 Clock Source Select Control Register 1 */
sahilmgandhi 18:6a4db94011d3 2520 __IO uint32_t CLKSEL2; /* Offset: 0x18 Clock Source Select Control Register 2 */
sahilmgandhi 18:6a4db94011d3 2521 __IO uint32_t CLKSEL3; /* Offset: 0x1C Clock Source Select Control Register 3 */
sahilmgandhi 18:6a4db94011d3 2522 __IO uint32_t CLKDIV0; /* Offset: 0x20 Clock Divider Number Register 0 */
sahilmgandhi 18:6a4db94011d3 2523 __IO uint32_t CLKDIV1; /* Offset: 0x24 Clock Divider Number Register 1 */
sahilmgandhi 18:6a4db94011d3 2524 __I uint32_t RESERVE0[6];
sahilmgandhi 18:6a4db94011d3 2525 __IO uint32_t PLLCTL; /* Offset: 0x40 PLL Control Register */
sahilmgandhi 18:6a4db94011d3 2526 __I uint32_t RESERVE1[3];
sahilmgandhi 18:6a4db94011d3 2527 __I uint32_t STATUS; /* Offset: 0x50 Clock Status Monitor Register */
sahilmgandhi 18:6a4db94011d3 2528 __I uint32_t RESERVE2[3];
sahilmgandhi 18:6a4db94011d3 2529 __IO uint32_t CLKOCTL; /* Offset: 0x60 Clock Output Control Register */
sahilmgandhi 18:6a4db94011d3 2530 __I uint32_t RESERVE3[3];
sahilmgandhi 18:6a4db94011d3 2531 __IO uint32_t CLKDCTL; /* Offset: 0x70 Clock Fail Detector Control Register */
sahilmgandhi 18:6a4db94011d3 2532 __IO uint32_t CLKDSTS; /* Offset: 0x74 Clock Fail Detector Status Register */
sahilmgandhi 18:6a4db94011d3 2533 __IO uint32_t CDUPB; /* Offset: 0x78 Clock Frequency Detector Upper Boundary Register */
sahilmgandhi 18:6a4db94011d3 2534 __IO uint32_t CDLOWB; /* Offset: 0x7C Clock Frequency Detector Low Boundary Register */
sahilmgandhi 18:6a4db94011d3 2535
sahilmgandhi 18:6a4db94011d3 2536 } CLK_T;
sahilmgandhi 18:6a4db94011d3 2537
sahilmgandhi 18:6a4db94011d3 2538
sahilmgandhi 18:6a4db94011d3 2539
sahilmgandhi 18:6a4db94011d3 2540 /**
sahilmgandhi 18:6a4db94011d3 2541 @addtogroup CLK_CONST CLK Bit Field Definition
sahilmgandhi 18:6a4db94011d3 2542 Constant Definitions for CLK Controller
sahilmgandhi 18:6a4db94011d3 2543 @{ */
sahilmgandhi 18:6a4db94011d3 2544
sahilmgandhi 18:6a4db94011d3 2545 #define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK_T::PWRCTL: HXTEN Position */
sahilmgandhi 18:6a4db94011d3 2546 #define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK_T::PWRCTL: HXTEN Mask */
sahilmgandhi 18:6a4db94011d3 2547
sahilmgandhi 18:6a4db94011d3 2548 #define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK_T::PWRCTL: LXTEN Position */
sahilmgandhi 18:6a4db94011d3 2549 #define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK_T::PWRCTL: LXTEN Mask */
sahilmgandhi 18:6a4db94011d3 2550
sahilmgandhi 18:6a4db94011d3 2551 #define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK_T::PWRCTL: HIRCEN Position */
sahilmgandhi 18:6a4db94011d3 2552 #define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK_T::PWRCTL: HIRCEN Mask */
sahilmgandhi 18:6a4db94011d3 2553
sahilmgandhi 18:6a4db94011d3 2554 #define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK_T::PWRCTL: LIRCEN Position */
sahilmgandhi 18:6a4db94011d3 2555 #define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK_T::PWRCTL: LIRCEN Mask */
sahilmgandhi 18:6a4db94011d3 2556
sahilmgandhi 18:6a4db94011d3 2557 #define CLK_PWRCTL_PDWKDLY_Pos (4) /*!< CLK_T::PWRCTL: PDWKDLY Position */
sahilmgandhi 18:6a4db94011d3 2558 #define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) /*!< CLK_T::PWRCTL: PDWKDLY Mask */
sahilmgandhi 18:6a4db94011d3 2559
sahilmgandhi 18:6a4db94011d3 2560 #define CLK_PWRCTL_PDWKIEN_Pos (5) /*!< CLK_T::PWRCTL: PDWKIEN Position */
sahilmgandhi 18:6a4db94011d3 2561 #define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /*!< CLK_T::PWRCTL: PDWKIEN Mask */
sahilmgandhi 18:6a4db94011d3 2562
sahilmgandhi 18:6a4db94011d3 2563 #define CLK_PWRCTL_PDWKIF_Pos (6) /*!< CLK_T::PWRCTL: PDWKIF Position */
sahilmgandhi 18:6a4db94011d3 2564 #define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /*!< CLK_T::PWRCTL: PDWKIF Mask */
sahilmgandhi 18:6a4db94011d3 2565
sahilmgandhi 18:6a4db94011d3 2566 #define CLK_PWRCTL_PDEN_Pos (7) /*!< CLK_T::PWRCTL: PDEN Position */
sahilmgandhi 18:6a4db94011d3 2567 #define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /*!< CLK_T::PWRCTL: PDEN Mask */
sahilmgandhi 18:6a4db94011d3 2568
sahilmgandhi 18:6a4db94011d3 2569 #define CLK_PWRCTL_PDWTCPU_Pos (8) /*!< CLK_T::PWRCTL: PDWTCPU Position */
sahilmgandhi 18:6a4db94011d3 2570 #define CLK_PWRCTL_PDWTCPU_Msk (0x1ul << CLK_PWRCTL_PDWTCPU_Pos) /*!< CLK_T::PWRCTL: PDWTCPU Mask */
sahilmgandhi 18:6a4db94011d3 2571
sahilmgandhi 18:6a4db94011d3 2572 #define CLK_PWRCTL_HXTGAIN_Pos (10) /*!< CLK_T::PWRCTL: HXTGAIN Position */
sahilmgandhi 18:6a4db94011d3 2573 #define CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos) /*!< CLK_T::PWRCTL: HXTGAIN Mask */
sahilmgandhi 18:6a4db94011d3 2574
sahilmgandhi 18:6a4db94011d3 2575 #define CLK_PWRCTL_HXTSELTYP_Pos (12) /*!< CLK_T::PWRCTL: HXTSELTYP Position */
sahilmgandhi 18:6a4db94011d3 2576 #define CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos) /*!< CLK_T::PWRCTL: HXTSELTYP Mask */
sahilmgandhi 18:6a4db94011d3 2577
sahilmgandhi 18:6a4db94011d3 2578 #define CLK_AHBCLK_PDMACKEN_Pos (1) /*!< CLK_T::AHBCLK: PDMACKEN Position */
sahilmgandhi 18:6a4db94011d3 2579 #define CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos) /*!< CLK_T::AHBCLK: PDMACKEN Mask */
sahilmgandhi 18:6a4db94011d3 2580
sahilmgandhi 18:6a4db94011d3 2581 #define CLK_AHBCLK_ISPCKEN_Pos (2) /*!< CLK_T::AHBCLK: ISPCKEN Position */
sahilmgandhi 18:6a4db94011d3 2582 #define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) /*!< CLK_T::AHBCLK: ISPCKEN Mask */
sahilmgandhi 18:6a4db94011d3 2583
sahilmgandhi 18:6a4db94011d3 2584 #define CLK_AHBCLK_EBICKEN_Pos (3) /*!< CLK_T::AHBCLK: EBICKEN Position */
sahilmgandhi 18:6a4db94011d3 2585 #define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) /*!< CLK_T::AHBCLK: EBICKEN Mask */
sahilmgandhi 18:6a4db94011d3 2586
sahilmgandhi 18:6a4db94011d3 2587 #define CLK_AHBCLK_USBHCKEN_Pos (4) /*!< CLK_T::AHBCLK: USBHCKEN Position */
sahilmgandhi 18:6a4db94011d3 2588 #define CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos) /*!< CLK_T::AHBCLK: USBHCKEN Mask */
sahilmgandhi 18:6a4db94011d3 2589
sahilmgandhi 18:6a4db94011d3 2590 #define CLK_AHBCLK_CRCCKEN_Pos (7) /*!< CLK_T::AHBCLK: CRCCKEN Position */
sahilmgandhi 18:6a4db94011d3 2591 #define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) /*!< CLK_T::AHBCLK: CRCCKEN Mask */
sahilmgandhi 18:6a4db94011d3 2592
sahilmgandhi 18:6a4db94011d3 2593 #define CLK_AHBCLK_FMCIDLE_Pos (15) /*!< CLK_T::AHBCLK: FMCIDLE Position */
sahilmgandhi 18:6a4db94011d3 2594 #define CLK_AHBCLK_FMCIDLE_Msk (0x1ul << CLK_AHBCLK_FMCIDLE_Pos) /*!< CLK_T::AHBCLK: FMCIDLE Mask */
sahilmgandhi 18:6a4db94011d3 2595
sahilmgandhi 18:6a4db94011d3 2596 #define CLK_APBCLK0_WDTCKEN_Pos (0) /*!< CLK_T::APBCLK0: WDTCKEN Position */
sahilmgandhi 18:6a4db94011d3 2597 #define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) /*!< CLK_T::APBCLK0: WDTCKEN Mask */
sahilmgandhi 18:6a4db94011d3 2598
sahilmgandhi 18:6a4db94011d3 2599 #define CLK_APBCLK0_RTCCKEN_Pos (1) /*!< CLK_T::APBCLK0: RTCCKEN Position */
sahilmgandhi 18:6a4db94011d3 2600 #define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK_T::APBCLK0: RTCCKEN Mask */
sahilmgandhi 18:6a4db94011d3 2601
sahilmgandhi 18:6a4db94011d3 2602 #define CLK_APBCLK0_TMR0CKEN_Pos (2) /*!< CLK_T::APBCLK0: TMR0CKEN Position */
sahilmgandhi 18:6a4db94011d3 2603 #define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK_T::APBCLK0: TMR0CKEN Mask */
sahilmgandhi 18:6a4db94011d3 2604
sahilmgandhi 18:6a4db94011d3 2605 #define CLK_APBCLK0_TMR1CKEN_Pos (3) /*!< CLK_T::APBCLK0: TMR1CKEN Position */
sahilmgandhi 18:6a4db94011d3 2606 #define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK_T::APBCLK0: TMR1CKEN Mask */
sahilmgandhi 18:6a4db94011d3 2607
sahilmgandhi 18:6a4db94011d3 2608 #define CLK_APBCLK0_TMR2CKEN_Pos (4) /*!< CLK_T::APBCLK0: TMR2CKEN Position */
sahilmgandhi 18:6a4db94011d3 2609 #define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK_T::APBCLK0: TMR2CKEN Mask */
sahilmgandhi 18:6a4db94011d3 2610
sahilmgandhi 18:6a4db94011d3 2611 #define CLK_APBCLK0_TMR3CKEN_Pos (5) /*!< CLK_T::APBCLK0: TMR3CKEN Position */
sahilmgandhi 18:6a4db94011d3 2612 #define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK_T::APBCLK0: TMR3CKEN Mask */
sahilmgandhi 18:6a4db94011d3 2613
sahilmgandhi 18:6a4db94011d3 2614 #define CLK_APBCLK0_CLKOCKEN_Pos (6) /*!< CLK_T::APBCLK0: CLKOCKEN Position */
sahilmgandhi 18:6a4db94011d3 2615 #define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLK_T::APBCLK0: CLKOCKEN Mask */
sahilmgandhi 18:6a4db94011d3 2616
sahilmgandhi 18:6a4db94011d3 2617 #define CLK_APBCLK0_ACMP01CKEN_Pos (7) /*!< CLK_T::APBCLK0: ACMP01CKEN Position */
sahilmgandhi 18:6a4db94011d3 2618 #define CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos) /*!< CLK_T::APBCLK0: ACMP01CKEN Mask */
sahilmgandhi 18:6a4db94011d3 2619
sahilmgandhi 18:6a4db94011d3 2620 #define CLK_APBCLK0_I2C0CKEN_Pos (8) /*!< CLK_T::APBCLK0: I2C0CKEN Position */
sahilmgandhi 18:6a4db94011d3 2621 #define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /*!< CLK_T::APBCLK0: I2C0CKEN Mask */
sahilmgandhi 18:6a4db94011d3 2622
sahilmgandhi 18:6a4db94011d3 2623 #define CLK_APBCLK0_I2C1CKEN_Pos (9) /*!< CLK_T::APBCLK0: I2C1CKEN Position */
sahilmgandhi 18:6a4db94011d3 2624 #define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /*!< CLK_T::APBCLK0: I2C1CKEN Mask */
sahilmgandhi 18:6a4db94011d3 2625
sahilmgandhi 18:6a4db94011d3 2626 #define CLK_APBCLK0_SPI0CKEN_Pos (12) /*!< CLK_T::APBCLK0: SPI0CKEN Position */
sahilmgandhi 18:6a4db94011d3 2627 #define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /*!< CLK_T::APBCLK0: SPI0CKEN Mask */
sahilmgandhi 18:6a4db94011d3 2628
sahilmgandhi 18:6a4db94011d3 2629 #define CLK_APBCLK0_SPI1CKEN_Pos (13) /*!< CLK_T::APBCLK0: SPI1CKEN Position */
sahilmgandhi 18:6a4db94011d3 2630 #define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) /*!< CLK_T::APBCLK0: SPI1CKEN Mask */
sahilmgandhi 18:6a4db94011d3 2631
sahilmgandhi 18:6a4db94011d3 2632 #define CLK_APBCLK0_SPI2CKEN_Pos (14) /*!< CLK_T::APBCLK0: SPI2CKEN Position */
sahilmgandhi 18:6a4db94011d3 2633 #define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) /*!< CLK_T::APBCLK0: SPI2CKEN Mask */
sahilmgandhi 18:6a4db94011d3 2634
sahilmgandhi 18:6a4db94011d3 2635 #define CLK_APBCLK0_UART0CKEN_Pos (16) /*!< CLK_T::APBCLK0: UART0CKEN Position */
sahilmgandhi 18:6a4db94011d3 2636 #define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK_T::APBCLK0: UART0CKEN Mask */
sahilmgandhi 18:6a4db94011d3 2637
sahilmgandhi 18:6a4db94011d3 2638 #define CLK_APBCLK0_UART1CKEN_Pos (17) /*!< CLK_T::APBCLK0: UART1CKEN Position */
sahilmgandhi 18:6a4db94011d3 2639 #define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK_T::APBCLK0: UART1CKEN Mask */
sahilmgandhi 18:6a4db94011d3 2640
sahilmgandhi 18:6a4db94011d3 2641 #define CLK_APBCLK0_UART2CKEN_Pos (18) /*!< CLK_T::APBCLK0: UART2CKEN Position */
sahilmgandhi 18:6a4db94011d3 2642 #define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK_T::APBCLK0: UART2CKEN Mask */
sahilmgandhi 18:6a4db94011d3 2643
sahilmgandhi 18:6a4db94011d3 2644 #define CLK_APBCLK0_UART3CKEN_Pos (19) /*!< CLK_T::APBCLK0: UART3CKEN Position */
sahilmgandhi 18:6a4db94011d3 2645 #define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /*!< CLK_T::APBCLK0: UART3CKEN Mask */
sahilmgandhi 18:6a4db94011d3 2646
sahilmgandhi 18:6a4db94011d3 2647 #define CLK_APBCLK0_CAN0CKEN_Pos (24) /*!< CLK_T::APBCLK0: CAN0CKEN Position */
sahilmgandhi 18:6a4db94011d3 2648 #define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos) /*!< CLK_T::APBCLK0: CAN0CKEN Mask */
sahilmgandhi 18:6a4db94011d3 2649
sahilmgandhi 18:6a4db94011d3 2650 #define CLK_APBCLK0_OTGCKEN_Pos (26) /*!< CLK_T::APBCLK0: OTGCKEN Position */
sahilmgandhi 18:6a4db94011d3 2651 #define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) /*!< CLK_T::APBCLK0: OTGCKEN Mask */
sahilmgandhi 18:6a4db94011d3 2652
sahilmgandhi 18:6a4db94011d3 2653 #define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */
sahilmgandhi 18:6a4db94011d3 2654 #define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */
sahilmgandhi 18:6a4db94011d3 2655
sahilmgandhi 18:6a4db94011d3 2656 #define CLK_APBCLK0_EADCCKEN_Pos (28) /*!< CLK_T::APBCLK0: EADCCKEN Position */
sahilmgandhi 18:6a4db94011d3 2657 #define CLK_APBCLK0_EADCCKEN_Msk (0x1ul << CLK_APBCLK0_EADCCKEN_Pos) /*!< CLK_T::APBCLK0: EADCCKEN Mask */
sahilmgandhi 18:6a4db94011d3 2658
sahilmgandhi 18:6a4db94011d3 2659 #define CLK_APBCLK1_SC0CKEN_Pos (0) /*!< CLK_T::APBCLK1: SC0CKEN Position */
sahilmgandhi 18:6a4db94011d3 2660 #define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) /*!< CLK_T::APBCLK1: SC0CKEN Mask */
sahilmgandhi 18:6a4db94011d3 2661
sahilmgandhi 18:6a4db94011d3 2662 #define CLK_APBCLK1_DACCKEN_Pos (12) /*!< CLK_T::APBCLK1: DACCKEN Position */
sahilmgandhi 18:6a4db94011d3 2663 #define CLK_APBCLK1_DACCKEN_Msk (0x1ul << CLK_APBCLK1_DACCKEN_Pos) /*!< CLK_T::APBCLK1: DACCKEN Mask */
sahilmgandhi 18:6a4db94011d3 2664
sahilmgandhi 18:6a4db94011d3 2665 #define CLK_APBCLK1_PWM0CKEN_Pos (16) /*!< CLK_T::APBCLK1: PWM0CKEN Position */
sahilmgandhi 18:6a4db94011d3 2666 #define CLK_APBCLK1_PWM0CKEN_Msk (0x1ul << CLK_APBCLK1_PWM0CKEN_Pos) /*!< CLK_T::APBCLK1: PWM0CKEN Mask */
sahilmgandhi 18:6a4db94011d3 2667
sahilmgandhi 18:6a4db94011d3 2668 #define CLK_APBCLK1_PWM1CKEN_Pos (17) /*!< CLK_T::APBCLK1: PWM1CKEN Position */
sahilmgandhi 18:6a4db94011d3 2669 #define CLK_APBCLK1_PWM1CKEN_Msk (0x1ul << CLK_APBCLK1_PWM1CKEN_Pos) /*!< CLK_T::APBCLK1: PWM1CKEN Mask */
sahilmgandhi 18:6a4db94011d3 2670
sahilmgandhi 18:6a4db94011d3 2671 #define CLK_APBCLK1_TKCKEN_Pos (25) /*!< CLK_T::APBCLK1: TKCKEN Position */
sahilmgandhi 18:6a4db94011d3 2672 #define CLK_APBCLK1_TKCKEN_Msk (0x1ul << CLK_APBCLK1_TKCKEN_Pos) /*!< CLK_T::APBCLK1: TKCKEN Mask */
sahilmgandhi 18:6a4db94011d3 2673
sahilmgandhi 18:6a4db94011d3 2674 #define CLK_CLKSEL0_HCLKSEL_Pos (0) /*!< CLK_T::CLKSEL0: HCLKSEL Position */
sahilmgandhi 18:6a4db94011d3 2675 #define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) /*!< CLK_T::CLKSEL0: HCLKSEL Mask */
sahilmgandhi 18:6a4db94011d3 2676
sahilmgandhi 18:6a4db94011d3 2677 #define CLK_CLKSEL0_STCLKSEL_Pos (3) /*!< CLK_T::CLKSEL0: STCLKSEL Position */
sahilmgandhi 18:6a4db94011d3 2678 #define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /*!< CLK_T::CLKSEL0: STCLKSEL Mask */
sahilmgandhi 18:6a4db94011d3 2679
sahilmgandhi 18:6a4db94011d3 2680 #define CLK_CLKSEL0_PCLK0SEL_Pos (6) /*!< CLK_T::CLKSEL0: PCLK0SEL Position */
sahilmgandhi 18:6a4db94011d3 2681 #define CLK_CLKSEL0_PCLK0SEL_Msk (0x1ul << CLK_CLKSEL0_PCLK0SEL_Pos) /*!< CLK_T::CLKSEL0: PCLK0SEL Mask */
sahilmgandhi 18:6a4db94011d3 2682
sahilmgandhi 18:6a4db94011d3 2683 #define CLK_CLKSEL0_PCLK1SEL_Pos (7) /*!< CLK_T::CLKSEL0: PCLK1SEL Position */
sahilmgandhi 18:6a4db94011d3 2684 #define CLK_CLKSEL0_PCLK1SEL_Msk (0x1ul << CLK_CLKSEL0_PCLK1SEL_Pos) /*!< CLK_T::CLKSEL0: PCLK1SEL Mask */
sahilmgandhi 18:6a4db94011d3 2685
sahilmgandhi 18:6a4db94011d3 2686 #define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK_T::CLKSEL1: WDTSEL Position */
sahilmgandhi 18:6a4db94011d3 2687 #define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK_T::CLKSEL1: WDTSEL Mask */
sahilmgandhi 18:6a4db94011d3 2688
sahilmgandhi 18:6a4db94011d3 2689 #define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR0SEL Position */
sahilmgandhi 18:6a4db94011d3 2690 #define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */
sahilmgandhi 18:6a4db94011d3 2691
sahilmgandhi 18:6a4db94011d3 2692 #define CLK_CLKSEL1_TMR1SEL_Pos (12) /*!< CLK_T::CLKSEL1: TMR1SEL Position */
sahilmgandhi 18:6a4db94011d3 2693 #define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK_T::CLKSEL1: TMR1SEL Mask */
sahilmgandhi 18:6a4db94011d3 2694
sahilmgandhi 18:6a4db94011d3 2695 #define CLK_CLKSEL1_TMR2SEL_Pos (16) /*!< CLK_T::CLKSEL1: TMR2SEL Position */
sahilmgandhi 18:6a4db94011d3 2696 #define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK_T::CLKSEL1: TMR2SEL Mask */
sahilmgandhi 18:6a4db94011d3 2697
sahilmgandhi 18:6a4db94011d3 2698 #define CLK_CLKSEL1_TMR3SEL_Pos (20) /*!< CLK_T::CLKSEL1: TMR3SEL Position */
sahilmgandhi 18:6a4db94011d3 2699 #define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK_T::CLKSEL1: TMR3SEL Mask */
sahilmgandhi 18:6a4db94011d3 2700
sahilmgandhi 18:6a4db94011d3 2701 #define CLK_CLKSEL1_UARTSEL_Pos (24) /*!< CLK_T::CLKSEL1: UARTSEL Position */
sahilmgandhi 18:6a4db94011d3 2702 #define CLK_CLKSEL1_UARTSEL_Msk (0x3ul << CLK_CLKSEL1_UARTSEL_Pos) /*!< CLK_T::CLKSEL1: UARTSEL Mask */
sahilmgandhi 18:6a4db94011d3 2703
sahilmgandhi 18:6a4db94011d3 2704 #define CLK_CLKSEL1_CLKOSEL_Pos (28) /*!< CLK_T::CLKSEL1: CLKOSEL Position */
sahilmgandhi 18:6a4db94011d3 2705 #define CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos) /*!< CLK_T::CLKSEL1: CLKOSEL Mask */
sahilmgandhi 18:6a4db94011d3 2706
sahilmgandhi 18:6a4db94011d3 2707 #define CLK_CLKSEL1_WWDTSEL_Pos (30) /*!< CLK_T::CLKSEL1: WWDTSEL Position */
sahilmgandhi 18:6a4db94011d3 2708 #define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /*!< CLK_T::CLKSEL1: WWDTSEL Mask */
sahilmgandhi 18:6a4db94011d3 2709
sahilmgandhi 18:6a4db94011d3 2710 #define CLK_CLKSEL2_PWM0SEL_Pos (0) /*!< CLK_T::CLKSEL2: PWM0SEL Position */
sahilmgandhi 18:6a4db94011d3 2711 #define CLK_CLKSEL2_PWM0SEL_Msk (0x1ul << CLK_CLKSEL2_PWM0SEL_Pos) /*!< CLK_T::CLKSEL2: PWM0SEL Mask */
sahilmgandhi 18:6a4db94011d3 2712
sahilmgandhi 18:6a4db94011d3 2713 #define CLK_CLKSEL2_PWM1SEL_Pos (1) /*!< CLK_T::CLKSEL2: PWM1SEL Position */
sahilmgandhi 18:6a4db94011d3 2714 #define CLK_CLKSEL2_PWM1SEL_Msk (0x1ul << CLK_CLKSEL2_PWM1SEL_Pos) /*!< CLK_T::CLKSEL2: PWM1SEL Mask */
sahilmgandhi 18:6a4db94011d3 2715
sahilmgandhi 18:6a4db94011d3 2716 #define CLK_CLKSEL2_SPI0SEL_Pos (2) /*!< CLK_T::CLKSEL2: SPI0SEL Position */
sahilmgandhi 18:6a4db94011d3 2717 #define CLK_CLKSEL2_SPI0SEL_Msk (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos) /*!< CLK_T::CLKSEL2: SPI0SEL Mask */
sahilmgandhi 18:6a4db94011d3 2718
sahilmgandhi 18:6a4db94011d3 2719 #define CLK_CLKSEL2_SPI1SEL_Pos (4) /*!< CLK_T::CLKSEL2: SPI1SEL Position */
sahilmgandhi 18:6a4db94011d3 2720 #define CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos) /*!< CLK_T::CLKSEL2: SPI1SEL Mask */
sahilmgandhi 18:6a4db94011d3 2721
sahilmgandhi 18:6a4db94011d3 2722 #define CLK_CLKSEL2_SPI2SEL_Pos (6) /*!< CLK_T::CLKSEL2: SPI2SEL Position */
sahilmgandhi 18:6a4db94011d3 2723 #define CLK_CLKSEL2_SPI2SEL_Msk (0x3ul << CLK_CLKSEL2_SPI2SEL_Pos) /*!< CLK_T::CLKSEL2: SPI2SEL Mask */
sahilmgandhi 18:6a4db94011d3 2724
sahilmgandhi 18:6a4db94011d3 2725 #define CLK_CLKSEL3_SC0SEL_Pos (0) /*!< CLK_T::CLKSEL3: SC0SEL Position */
sahilmgandhi 18:6a4db94011d3 2726 #define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /*!< CLK_T::CLKSEL3: SC0SEL Mask */
sahilmgandhi 18:6a4db94011d3 2727
sahilmgandhi 18:6a4db94011d3 2728 #define CLK_CLKSEL3_RTCSEL_Pos (8) /*!< CLK_T::CLKSEL3: RTCSEL Position */
sahilmgandhi 18:6a4db94011d3 2729 #define CLK_CLKSEL3_RTCSEL_Msk (0x1ul << CLK_CLKSEL3_RTCSEL_Pos) /*!< CLK_T::CLKSEL3: RTCSEL Mask */
sahilmgandhi 18:6a4db94011d3 2730
sahilmgandhi 18:6a4db94011d3 2731 #define CLK_CLKDIV0_HCLKDIV_Pos (0) /*!< CLK_T::CLKDIV0: HCLKDIV Position */
sahilmgandhi 18:6a4db94011d3 2732 #define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLK_T::CLKDIV0: HCLKDIV Mask */
sahilmgandhi 18:6a4db94011d3 2733
sahilmgandhi 18:6a4db94011d3 2734 #define CLK_CLKDIV0_USBDIV_Pos (4) /*!< CLK_T::CLKDIV0: USBDIV Position */
sahilmgandhi 18:6a4db94011d3 2735 #define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos) /*!< CLK_T::CLKDIV0: USBDIV Mask */
sahilmgandhi 18:6a4db94011d3 2736
sahilmgandhi 18:6a4db94011d3 2737 #define CLK_CLKDIV0_UARTDIV_Pos (8) /*!< CLK_T::CLKDIV0: UARTDIV Position */
sahilmgandhi 18:6a4db94011d3 2738 #define CLK_CLKDIV0_UARTDIV_Msk (0xful << CLK_CLKDIV0_UARTDIV_Pos) /*!< CLK_T::CLKDIV0: UARTDIV Mask */
sahilmgandhi 18:6a4db94011d3 2739
sahilmgandhi 18:6a4db94011d3 2740 #define CLK_CLKDIV0_EADCDIV_Pos (16) /*!< CLK_T::CLKDIV0: EADCDIV Position */
sahilmgandhi 18:6a4db94011d3 2741 #define CLK_CLKDIV0_EADCDIV_Msk (0xfful << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLK_T::CLKDIV0: EADCDIV Mask */
sahilmgandhi 18:6a4db94011d3 2742
sahilmgandhi 18:6a4db94011d3 2743 #define CLK_CLKDIV1_SC0DIV_Pos (0) /*!< CLK_T::CLKDIV1: SC0DIV Position */
sahilmgandhi 18:6a4db94011d3 2744 #define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLK_T::CLKDIV1: SC0DIV Mask */
sahilmgandhi 18:6a4db94011d3 2745
sahilmgandhi 18:6a4db94011d3 2746 #define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK_T::PLLCTL: FBDIV Position */
sahilmgandhi 18:6a4db94011d3 2747 #define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK_T::PLLCTL: FBDIV Mask */
sahilmgandhi 18:6a4db94011d3 2748
sahilmgandhi 18:6a4db94011d3 2749 #define CLK_PLLCTL_INDIV_Pos (9) /*!< CLK_T::PLLCTL: INDIV Position */
sahilmgandhi 18:6a4db94011d3 2750 #define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) /*!< CLK_T::PLLCTL: INDIV Mask */
sahilmgandhi 18:6a4db94011d3 2751
sahilmgandhi 18:6a4db94011d3 2752 #define CLK_PLLCTL_OUTDIV_Pos (14) /*!< CLK_T::PLLCTL: OUTDIV Position */
sahilmgandhi 18:6a4db94011d3 2753 #define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos) /*!< CLK_T::PLLCTL: OUTDIV Mask */
sahilmgandhi 18:6a4db94011d3 2754
sahilmgandhi 18:6a4db94011d3 2755 #define CLK_PLLCTL_PD_Pos (16) /*!< CLK_T::PLLCTL: PD Position */
sahilmgandhi 18:6a4db94011d3 2756 #define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK_T::PLLCTL: PD Mask */
sahilmgandhi 18:6a4db94011d3 2757
sahilmgandhi 18:6a4db94011d3 2758 #define CLK_PLLCTL_BP_Pos (17) /*!< CLK_T::PLLCTL: BP Position */
sahilmgandhi 18:6a4db94011d3 2759 #define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /*!< CLK_T::PLLCTL: BP Mask */
sahilmgandhi 18:6a4db94011d3 2760
sahilmgandhi 18:6a4db94011d3 2761 #define CLK_PLLCTL_OE_Pos (18) /*!< CLK_T::PLLCTL: OE Position */
sahilmgandhi 18:6a4db94011d3 2762 #define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) /*!< CLK_T::PLLCTL: OE Mask */
sahilmgandhi 18:6a4db94011d3 2763
sahilmgandhi 18:6a4db94011d3 2764 #define CLK_PLLCTL_PLLSRC_Pos (19) /*!< CLK_T::PLLCTL: PLLSRC Position */
sahilmgandhi 18:6a4db94011d3 2765 #define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /*!< CLK_T::PLLCTL: PLLSRC Mask */
sahilmgandhi 18:6a4db94011d3 2766
sahilmgandhi 18:6a4db94011d3 2767 #define CLK_PLLCTL_STBSEL_Pos (23) /*!< CLK_T::PLLCTL: STBSEL Position */
sahilmgandhi 18:6a4db94011d3 2768 #define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos) /*!< CLK_T::PLLCTL: STBSEL Mask */
sahilmgandhi 18:6a4db94011d3 2769
sahilmgandhi 18:6a4db94011d3 2770 #define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK_T::STATUS: HXTSTB Position */
sahilmgandhi 18:6a4db94011d3 2771 #define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK_T::STATUS: HXTSTB Mask */
sahilmgandhi 18:6a4db94011d3 2772
sahilmgandhi 18:6a4db94011d3 2773 #define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK_T::STATUS: LXTSTB Position */
sahilmgandhi 18:6a4db94011d3 2774 #define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK_T::STATUS: LXTSTB Mask */
sahilmgandhi 18:6a4db94011d3 2775
sahilmgandhi 18:6a4db94011d3 2776 #define CLK_STATUS_PLLSTB_Pos (2) /*!< CLK_T::STATUS: PLLSTB Position */
sahilmgandhi 18:6a4db94011d3 2777 #define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /*!< CLK_T::STATUS: PLLSTB Mask */
sahilmgandhi 18:6a4db94011d3 2778
sahilmgandhi 18:6a4db94011d3 2779 #define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK_T::STATUS: LIRCSTB Position */
sahilmgandhi 18:6a4db94011d3 2780 #define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK_T::STATUS: LIRCSTB Mask */
sahilmgandhi 18:6a4db94011d3 2781
sahilmgandhi 18:6a4db94011d3 2782 #define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK_T::STATUS: HIRCSTB Position */
sahilmgandhi 18:6a4db94011d3 2783 #define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK_T::STATUS: HIRCSTB Mask */
sahilmgandhi 18:6a4db94011d3 2784
sahilmgandhi 18:6a4db94011d3 2785 #define CLK_STATUS_CLKSFAIL_Pos (7) /*!< CLK_T::STATUS: CLKSFAIL Position */
sahilmgandhi 18:6a4db94011d3 2786 #define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /*!< CLK_T::STATUS: CLKSFAIL Mask */
sahilmgandhi 18:6a4db94011d3 2787
sahilmgandhi 18:6a4db94011d3 2788 #define CLK_CLKOCTL_FREQSEL_Pos (0) /*!< CLK_T::CLKOCTL: FREQSEL Position */
sahilmgandhi 18:6a4db94011d3 2789 #define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) /*!< CLK_T::CLKOCTL: FREQSEL Mask */
sahilmgandhi 18:6a4db94011d3 2790
sahilmgandhi 18:6a4db94011d3 2791 #define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK_T::CLKOCTL: CLKOEN Position */
sahilmgandhi 18:6a4db94011d3 2792 #define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK_T::CLKOCTL: CLKOEN Mask */
sahilmgandhi 18:6a4db94011d3 2793
sahilmgandhi 18:6a4db94011d3 2794 #define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK_T::CLKOCTL: DIV1EN Position */
sahilmgandhi 18:6a4db94011d3 2795 #define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK_T::CLKOCTL: DIV1EN Mask */
sahilmgandhi 18:6a4db94011d3 2796
sahilmgandhi 18:6a4db94011d3 2797 #define CLK_CLKOCTL_CLK1HZEN_Pos (6) /*!< CLK_T::CLKOCTL: CLK1HZEN Position */
sahilmgandhi 18:6a4db94011d3 2798 #define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos) /*!< CLK_T::CLKOCTL: CLK1HZEN Mask */
sahilmgandhi 18:6a4db94011d3 2799
sahilmgandhi 18:6a4db94011d3 2800 #define CLK_CLKDCTL_HXTFDEN_Pos (4) /*!< CLK_T::CLKDCTL: HXTFDEN Position */
sahilmgandhi 18:6a4db94011d3 2801 #define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFDEN Mask */
sahilmgandhi 18:6a4db94011d3 2802
sahilmgandhi 18:6a4db94011d3 2803 #define CLK_CLKDCTL_HXTFIEN_Pos (5) /*!< CLK_T::CLKDCTL: HXTFIEN Position */
sahilmgandhi 18:6a4db94011d3 2804 #define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFIEN Mask */
sahilmgandhi 18:6a4db94011d3 2805
sahilmgandhi 18:6a4db94011d3 2806 #define CLK_CLKDCTL_LXTFDEN_Pos (12) /*!< CLK_T::CLKDCTL: LXTFDEN Position */
sahilmgandhi 18:6a4db94011d3 2807 #define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) /*!< CLK_T::CLKDCTL: LXTFDEN Mask */
sahilmgandhi 18:6a4db94011d3 2808
sahilmgandhi 18:6a4db94011d3 2809 #define CLK_CLKDCTL_LXTFIEN_Pos (13) /*!< CLK_T::CLKDCTL: LXTFIEN Position */
sahilmgandhi 18:6a4db94011d3 2810 #define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) /*!< CLK_T::CLKDCTL: LXTFIEN Mask */
sahilmgandhi 18:6a4db94011d3 2811
sahilmgandhi 18:6a4db94011d3 2812 #define CLK_CLKDCTL_HXTFQDEN_Pos (16) /*!< CLK_T::CLKDCTL: HXTFQDEN Position */
sahilmgandhi 18:6a4db94011d3 2813 #define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQDEN Mask */
sahilmgandhi 18:6a4db94011d3 2814
sahilmgandhi 18:6a4db94011d3 2815 #define CLK_CLKDCTL_HXTFQIEN_Pos (17) /*!< CLK_T::CLKDCTL: HXTFQIEN Position */
sahilmgandhi 18:6a4db94011d3 2816 #define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQIEN Mask */
sahilmgandhi 18:6a4db94011d3 2817
sahilmgandhi 18:6a4db94011d3 2818 #define CLK_CLKDSTS_HXTFIF_Pos (0) /*!< CLK_T::CLKDSTS: HXTFIF Position */
sahilmgandhi 18:6a4db94011d3 2819 #define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) /*!< CLK_T::CLKDSTS: HXTFIF Mask */
sahilmgandhi 18:6a4db94011d3 2820
sahilmgandhi 18:6a4db94011d3 2821 #define CLK_CLKDSTS_LXTFIF_Pos (1) /*!< CLK_T::CLKDSTS: LXTFIF Position */
sahilmgandhi 18:6a4db94011d3 2822 #define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) /*!< CLK_T::CLKDSTS: LXTFIF Mask */
sahilmgandhi 18:6a4db94011d3 2823
sahilmgandhi 18:6a4db94011d3 2824 #define CLK_CLKDSTS_HXTFQIF_Pos (8) /*!< CLK_T::CLKDSTS: HXTFQIF Position */
sahilmgandhi 18:6a4db94011d3 2825 #define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) /*!< CLK_T::CLKDSTS: HXTFQIF Mask */
sahilmgandhi 18:6a4db94011d3 2826
sahilmgandhi 18:6a4db94011d3 2827 #define CLK_CDUPB_UPERBD_Pos (0) /*!< CLK_T::CDUPB: UPERBD Position */
sahilmgandhi 18:6a4db94011d3 2828 #define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos) /*!< CLK_T::CDUPB: UPERBD Mask */
sahilmgandhi 18:6a4db94011d3 2829
sahilmgandhi 18:6a4db94011d3 2830 #define CLK_CDLOWB_LOWERBD_Pos (0) /*!< CLK_T::CDLOWB: LOWERBD Position */
sahilmgandhi 18:6a4db94011d3 2831 #define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) /*!< CLK_T::CDLOWB: LOWERBD Mask */
sahilmgandhi 18:6a4db94011d3 2832
sahilmgandhi 18:6a4db94011d3 2833
sahilmgandhi 18:6a4db94011d3 2834 /**@}*/ /* CLK_CONST */
sahilmgandhi 18:6a4db94011d3 2835 /**@}*/ /* end of CLK register group */
sahilmgandhi 18:6a4db94011d3 2836
sahilmgandhi 18:6a4db94011d3 2837
sahilmgandhi 18:6a4db94011d3 2838
sahilmgandhi 18:6a4db94011d3 2839 /*---------------------- Cyclic Redundancy Check Controller -------------------------*/
sahilmgandhi 18:6a4db94011d3 2840 /**
sahilmgandhi 18:6a4db94011d3 2841 @addtogroup CRC Cyclic Redundancy Check Controller(CRC)
sahilmgandhi 18:6a4db94011d3 2842 Memory Mapped Structure for CRC Controller
sahilmgandhi 18:6a4db94011d3 2843 @{ */
sahilmgandhi 18:6a4db94011d3 2844
sahilmgandhi 18:6a4db94011d3 2845
sahilmgandhi 18:6a4db94011d3 2846 typedef struct
sahilmgandhi 18:6a4db94011d3 2847 {
sahilmgandhi 18:6a4db94011d3 2848
sahilmgandhi 18:6a4db94011d3 2849
sahilmgandhi 18:6a4db94011d3 2850
sahilmgandhi 18:6a4db94011d3 2851
sahilmgandhi 18:6a4db94011d3 2852 /**
sahilmgandhi 18:6a4db94011d3 2853 * @var CRC_T::CTL
sahilmgandhi 18:6a4db94011d3 2854 * Offset: 0x00 CRC Control Register
sahilmgandhi 18:6a4db94011d3 2855 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2856 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 2857 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 2858 * |[0] |CRCEN |CRC Channel Enable Bit
sahilmgandhi 18:6a4db94011d3 2859 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 2860 * | | |1 = CRC operation Enabled.
sahilmgandhi 18:6a4db94011d3 2861 * |[1] |CRCRST |CRC Engine Reset
sahilmgandhi 18:6a4db94011d3 2862 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 2863 * | | |1 = Reset the internal CRC state machine and internal buffer.
sahilmgandhi 18:6a4db94011d3 2864 * | | |The others contents of CRC_CTL register will not be cleared.
sahilmgandhi 18:6a4db94011d3 2865 * | | |Note1: This bit will be cleared automatically.
sahilmgandhi 18:6a4db94011d3 2866 * | | |Note2: Setting this bit will reload the initial seed value (CRC_SEED register).
sahilmgandhi 18:6a4db94011d3 2867 * |[24] |DATREV |Write Data Bit Order Reverse
sahilmgandhi 18:6a4db94011d3 2868 * | | |This bit is used to enable the bit order reverse function for write data value in CRC_DAT register.
sahilmgandhi 18:6a4db94011d3 2869 * | | |0 = Bit order reversed for CRC write data in Disabled.
sahilmgandhi 18:6a4db94011d3 2870 * | | |1 = Bit order reversed for CRC write data in Enabled (per byte).
sahilmgandhi 18:6a4db94011d3 2871 * | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
sahilmgandhi 18:6a4db94011d3 2872 * |[25] |CHKSREV |Checksum Bit Order Reverse
sahilmgandhi 18:6a4db94011d3 2873 * | | |This bit is used to enable the bit order reverse function for write data value in CRC_CHECKSUM register.
sahilmgandhi 18:6a4db94011d3 2874 * | | |0 = Bit order reverse for CRC checksum Disabled.
sahilmgandhi 18:6a4db94011d3 2875 * | | |1 = Bit order reverse for CRC checksum Enabled.
sahilmgandhi 18:6a4db94011d3 2876 * | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
sahilmgandhi 18:6a4db94011d3 2877 * |[26] |DATFMT |Write Data 1's Complement
sahilmgandhi 18:6a4db94011d3 2878 * | | |This bit is used to enable the 1's complement function for write data value in CRC_DAT register.
sahilmgandhi 18:6a4db94011d3 2879 * | | |0 = 1's complement for CRC writes data in Disabled.
sahilmgandhi 18:6a4db94011d3 2880 * | | |1 = 1's complement for CRC writes data in Enabled.
sahilmgandhi 18:6a4db94011d3 2881 * |[27] |CHKSFMT |Checksum 1's Complement
sahilmgandhi 18:6a4db94011d3 2882 * | | |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
sahilmgandhi 18:6a4db94011d3 2883 * | | |0 = 1's complement for CRC checksum Disabled.
sahilmgandhi 18:6a4db94011d3 2884 * | | |1 = 1's complement for CRC checksum Enabled.
sahilmgandhi 18:6a4db94011d3 2885 * |[29:28] |DATLEN |CPU Write Data Length
sahilmgandhi 18:6a4db94011d3 2886 * | | |This field indicates the write data length.
sahilmgandhi 18:6a4db94011d3 2887 * | | |00 = Data length is 8-bit mode.
sahilmgandhi 18:6a4db94011d3 2888 * | | |01 = Data length is 16-bit mode.
sahilmgandhi 18:6a4db94011d3 2889 * | | |1x = Data length is 32-bit mode.
sahilmgandhi 18:6a4db94011d3 2890 * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]
sahilmgandhi 18:6a4db94011d3 2891 * |[31:30] |CRCMODE |CRC Polynomial Mode
sahilmgandhi 18:6a4db94011d3 2892 * | | |This field indicates the CRC operation polynomial mode.
sahilmgandhi 18:6a4db94011d3 2893 * | | |00 = CRC-CCITT Polynomial mode.
sahilmgandhi 18:6a4db94011d3 2894 * | | |01 = CRC-8 Polynomial mode.
sahilmgandhi 18:6a4db94011d3 2895 * | | |10 = CRC-16 Polynomial mode.
sahilmgandhi 18:6a4db94011d3 2896 * | | |11 = CRC-32 Polynomial mode.
sahilmgandhi 18:6a4db94011d3 2897 * @var CRC_T::DAT
sahilmgandhi 18:6a4db94011d3 2898 * Offset: 0x04 CRC Write Data Register
sahilmgandhi 18:6a4db94011d3 2899 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2900 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 2901 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 2902 * |[31:0] |DATA |CRC Write Data Bits
sahilmgandhi 18:6a4db94011d3 2903 * | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
sahilmgandhi 18:6a4db94011d3 2904 * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
sahilmgandhi 18:6a4db94011d3 2905 * @var CRC_T::SEED
sahilmgandhi 18:6a4db94011d3 2906 * Offset: 0x08 CRC Seed Register
sahilmgandhi 18:6a4db94011d3 2907 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2908 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 2909 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 2910 * |[31:0] |SEED |CRC Seed Value
sahilmgandhi 18:6a4db94011d3 2911 * | | |This field indicates the CRC seed value.
sahilmgandhi 18:6a4db94011d3 2912 * @var CRC_T::CHECKSUM
sahilmgandhi 18:6a4db94011d3 2913 * Offset: 0x0C CRC Checksum Register
sahilmgandhi 18:6a4db94011d3 2914 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2915 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 2916 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 2917 * |[31:0] |CHECKSUM |CRC Checksum Results
sahilmgandhi 18:6a4db94011d3 2918 * | | |This field indicates the CRC checksum result.
sahilmgandhi 18:6a4db94011d3 2919 */
sahilmgandhi 18:6a4db94011d3 2920
sahilmgandhi 18:6a4db94011d3 2921 __IO uint32_t CTL; /* Offset: 0x00 CRC Control Register */
sahilmgandhi 18:6a4db94011d3 2922 __IO uint32_t DAT; /* Offset: 0x04 CRC Write Data Register */
sahilmgandhi 18:6a4db94011d3 2923 __IO uint32_t SEED; /* Offset: 0x08 CRC Seed Register */
sahilmgandhi 18:6a4db94011d3 2924 __I uint32_t CHECKSUM; /* Offset: 0x0C CRC Checksum Register */
sahilmgandhi 18:6a4db94011d3 2925
sahilmgandhi 18:6a4db94011d3 2926 } CRC_T;
sahilmgandhi 18:6a4db94011d3 2927
sahilmgandhi 18:6a4db94011d3 2928
sahilmgandhi 18:6a4db94011d3 2929
sahilmgandhi 18:6a4db94011d3 2930 /**
sahilmgandhi 18:6a4db94011d3 2931 @addtogroup CRC_CONST CRC Bit Field Definition
sahilmgandhi 18:6a4db94011d3 2932 Constant Definitions for CRC Controller
sahilmgandhi 18:6a4db94011d3 2933 @{ */
sahilmgandhi 18:6a4db94011d3 2934
sahilmgandhi 18:6a4db94011d3 2935 #define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */
sahilmgandhi 18:6a4db94011d3 2936 #define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */
sahilmgandhi 18:6a4db94011d3 2937
sahilmgandhi 18:6a4db94011d3 2938 #define CRC_CTL_CRCRST_Pos (1) /*!< CRC_T::CTL: CRCRST Position */
sahilmgandhi 18:6a4db94011d3 2939 #define CRC_CTL_CRCRST_Msk (0x1ul << CRC_CTL_CRCRST_Pos) /*!< CRC_T::CTL: CRCRST Mask */
sahilmgandhi 18:6a4db94011d3 2940
sahilmgandhi 18:6a4db94011d3 2941 #define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */
sahilmgandhi 18:6a4db94011d3 2942 #define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */
sahilmgandhi 18:6a4db94011d3 2943
sahilmgandhi 18:6a4db94011d3 2944 #define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */
sahilmgandhi 18:6a4db94011d3 2945 #define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */
sahilmgandhi 18:6a4db94011d3 2946
sahilmgandhi 18:6a4db94011d3 2947 #define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */
sahilmgandhi 18:6a4db94011d3 2948 #define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */
sahilmgandhi 18:6a4db94011d3 2949
sahilmgandhi 18:6a4db94011d3 2950 #define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */
sahilmgandhi 18:6a4db94011d3 2951 #define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */
sahilmgandhi 18:6a4db94011d3 2952
sahilmgandhi 18:6a4db94011d3 2953 #define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */
sahilmgandhi 18:6a4db94011d3 2954 #define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */
sahilmgandhi 18:6a4db94011d3 2955
sahilmgandhi 18:6a4db94011d3 2956 #define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */
sahilmgandhi 18:6a4db94011d3 2957 #define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */
sahilmgandhi 18:6a4db94011d3 2958
sahilmgandhi 18:6a4db94011d3 2959 #define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */
sahilmgandhi 18:6a4db94011d3 2960 #define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */
sahilmgandhi 18:6a4db94011d3 2961
sahilmgandhi 18:6a4db94011d3 2962 #define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */
sahilmgandhi 18:6a4db94011d3 2963 #define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */
sahilmgandhi 18:6a4db94011d3 2964
sahilmgandhi 18:6a4db94011d3 2965 #define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */
sahilmgandhi 18:6a4db94011d3 2966 #define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */
sahilmgandhi 18:6a4db94011d3 2967
sahilmgandhi 18:6a4db94011d3 2968 /**@}*/ /* CRC_CONST */
sahilmgandhi 18:6a4db94011d3 2969 /**@}*/ /* end of CRC register group */
sahilmgandhi 18:6a4db94011d3 2970
sahilmgandhi 18:6a4db94011d3 2971
sahilmgandhi 18:6a4db94011d3 2972 /*---------------------- Digital to Analog Converter -------------------------*/
sahilmgandhi 18:6a4db94011d3 2973 /**
sahilmgandhi 18:6a4db94011d3 2974 @addtogroup DAC Digital to Analog Converter(DAC)
sahilmgandhi 18:6a4db94011d3 2975 Memory Mapped Structure for DAC Controller
sahilmgandhi 18:6a4db94011d3 2976 @{ */
sahilmgandhi 18:6a4db94011d3 2977
sahilmgandhi 18:6a4db94011d3 2978
sahilmgandhi 18:6a4db94011d3 2979 typedef struct
sahilmgandhi 18:6a4db94011d3 2980 {
sahilmgandhi 18:6a4db94011d3 2981
sahilmgandhi 18:6a4db94011d3 2982
sahilmgandhi 18:6a4db94011d3 2983
sahilmgandhi 18:6a4db94011d3 2984 /**
sahilmgandhi 18:6a4db94011d3 2985 * @var DAC_T::CTL
sahilmgandhi 18:6a4db94011d3 2986 * Offset: 0x00 DAC Control Register
sahilmgandhi 18:6a4db94011d3 2987 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2988 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 2989 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 2990 * |[0] |DACEN |DAC Enable Bit
sahilmgandhi 18:6a4db94011d3 2991 * | | |0 = DAC is Disabled.
sahilmgandhi 18:6a4db94011d3 2992 * | | |1 = DAC is Enabled.
sahilmgandhi 18:6a4db94011d3 2993 * |[1] |DACIEN |DAC Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 2994 * | | |0 = Interrupt is Disabled.
sahilmgandhi 18:6a4db94011d3 2995 * | | |1 = Interrupt is Enabled.
sahilmgandhi 18:6a4db94011d3 2996 * |[2] |DMAEN |DMA Mode Enable Bit
sahilmgandhi 18:6a4db94011d3 2997 * | | |0 = DMA mode Disabled.
sahilmgandhi 18:6a4db94011d3 2998 * | | |1 = DMA mode Enabled.
sahilmgandhi 18:6a4db94011d3 2999 * |[3] |DMAURIEN |DMA Under-Run Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 3000 * | | |0 = DMA under run interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 3001 * | | |1 = DMA under run interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 3002 * |[4] |TRGEN |Trigger Mode Enable Bit
sahilmgandhi 18:6a4db94011d3 3003 * | | |0 = DAC event trigger mode Disabled.
sahilmgandhi 18:6a4db94011d3 3004 * | | |1 = DAC event trigger mode Enabled.
sahilmgandhi 18:6a4db94011d3 3005 * |[7:5] |TRGSEL |Trigger Source Selection
sahilmgandhi 18:6a4db94011d3 3006 * | | |000 = Software trigger.
sahilmgandhi 18:6a4db94011d3 3007 * | | |001 = External pin STDAC trigger.
sahilmgandhi 18:6a4db94011d3 3008 * | | |010 = Timer 0 trigger.
sahilmgandhi 18:6a4db94011d3 3009 * | | |011 = Timer 1 trigger.
sahilmgandhi 18:6a4db94011d3 3010 * | | |100 = Timer 2 trigger.
sahilmgandhi 18:6a4db94011d3 3011 * | | |101 = Timer 3 trigger.
sahilmgandhi 18:6a4db94011d3 3012 * | | |110 = PWM0 trigger.
sahilmgandhi 18:6a4db94011d3 3013 * | | |111 = PWM1 trigger.
sahilmgandhi 18:6a4db94011d3 3014 * |[8] |BYPASS |Bypass Buffer Mode
sahilmgandhi 18:6a4db94011d3 3015 * | | |0 = Output voltage buffer Enabled.
sahilmgandhi 18:6a4db94011d3 3016 * | | |1 = Output voltage buffer Disabled.
sahilmgandhi 18:6a4db94011d3 3017 * |[10] |LALIGN |DAC Data Left-Aligned Enabled Control
sahilmgandhi 18:6a4db94011d3 3018 * | | |0 = Right alignment.
sahilmgandhi 18:6a4db94011d3 3019 * | | |1 = Left alignment.
sahilmgandhi 18:6a4db94011d3 3020 * |[13:12] |ETRGSEL |External Pin Trigger Selection
sahilmgandhi 18:6a4db94011d3 3021 * | | |00 = Low level trigger.
sahilmgandhi 18:6a4db94011d3 3022 * | | |01 = High level trigger.
sahilmgandhi 18:6a4db94011d3 3023 * | | |10 = Falling edge trigger.
sahilmgandhi 18:6a4db94011d3 3024 * | | |11 = Rising edge trigger.
sahilmgandhi 18:6a4db94011d3 3025 * @var DAC_T::SWTRG
sahilmgandhi 18:6a4db94011d3 3026 * Offset: 0x04 DAC Software Trigger Control Register
sahilmgandhi 18:6a4db94011d3 3027 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3028 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3029 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3030 * |[0] |SWTRG |Software Trigger
sahilmgandhi 18:6a4db94011d3 3031 * | | |0 = Software trigger Disabled.
sahilmgandhi 18:6a4db94011d3 3032 * | | |1 = Software trigger Enabled.
sahilmgandhi 18:6a4db94011d3 3033 * | | |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0.
sahilmgandhi 18:6a4db94011d3 3034 * @var DAC_T::DAT
sahilmgandhi 18:6a4db94011d3 3035 * Offset: 0x08 DAC Data Holding Register
sahilmgandhi 18:6a4db94011d3 3036 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3037 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3038 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3039 * |[15:0] |DAC_DAT |DAC 12-Bit Holding Data
sahilmgandhi 18:6a4db94011d3 3040 * | | |These bits are written by user software which specifies 12-bit conversion data for DAC output.
sahilmgandhi 18:6a4db94011d3 3041 * | | |The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
sahilmgandhi 18:6a4db94011d3 3042 * | | |12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.
sahilmgandhi 18:6a4db94011d3 3043 * | | |12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.
sahilmgandhi 18:6a4db94011d3 3044 * @var DAC_T::DATOUT
sahilmgandhi 18:6a4db94011d3 3045 * Offset: 0x0C DAC Data Output Register
sahilmgandhi 18:6a4db94011d3 3046 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3047 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3048 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3049 * |[11:0] |DATOUT |DAC 12-Bit Output Data
sahilmgandhi 18:6a4db94011d3 3050 * | | |These bits are current digital data for DAC output conversion.
sahilmgandhi 18:6a4db94011d3 3051 * | | |It is loaded from DAC_DAT register and user cannot write it directly.
sahilmgandhi 18:6a4db94011d3 3052 * @var DAC_T::STATUS
sahilmgandhi 18:6a4db94011d3 3053 * Offset: 0x10 DAC Status Register
sahilmgandhi 18:6a4db94011d3 3054 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3055 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3056 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3057 * |[0] |FINISH |DAC Conversion Complete Finish Flag
sahilmgandhi 18:6a4db94011d3 3058 * | | |0 = DAC is in conversion state.
sahilmgandhi 18:6a4db94011d3 3059 * | | |1 = DAC conversion finish.
sahilmgandhi 18:6a4db94011d3 3060 * | | |This bit set to 1 when conversion time counter counts to SETTLET.
sahilmgandhi 18:6a4db94011d3 3061 * | | |It is cleared to 0 when DAC starts a new conversion.
sahilmgandhi 18:6a4db94011d3 3062 * | | |User writes 1 to clear this bit to 0.
sahilmgandhi 18:6a4db94011d3 3063 * |[1] |DMAUDR |DMA Under Run Interrupt Flag
sahilmgandhi 18:6a4db94011d3 3064 * | | |0 = No DMA under-run error condition occurred.
sahilmgandhi 18:6a4db94011d3 3065 * | | |1 = DMA under-run error condition occurred.
sahilmgandhi 18:6a4db94011d3 3066 * | | |User writes 1 to clear this bit.
sahilmgandhi 18:6a4db94011d3 3067 * |[8] |BUSY |DAC Busy Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 3068 * | | |0 = DAC is ready for next conversion.
sahilmgandhi 18:6a4db94011d3 3069 * | | |1 = DAC is busy in conversion.
sahilmgandhi 18:6a4db94011d3 3070 * | | |This is read only bit.
sahilmgandhi 18:6a4db94011d3 3071 * @var DAC_T::TCTL
sahilmgandhi 18:6a4db94011d3 3072 * Offset: 0x14 DAC Timing Control Register
sahilmgandhi 18:6a4db94011d3 3073 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3074 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3075 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3076 * |[9:0] |SETTLET |DAC Output Settling Time
sahilmgandhi 18:6a4db94011d3 3077 * | | |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.
sahilmgandhi 18:6a4db94011d3 3078 * | | |For example, DAC controller clock speed is 72MHz and DAC conversion setting time is 1 us, SETTLET value must be greater than 0x48.
sahilmgandhi 18:6a4db94011d3 3079 */
sahilmgandhi 18:6a4db94011d3 3080
sahilmgandhi 18:6a4db94011d3 3081 __IO uint32_t CTL; /* Offset: 0x00 DAC Control Register */
sahilmgandhi 18:6a4db94011d3 3082 __IO uint32_t SWTRG; /* Offset: 0x04 DAC Software Trigger Control Register */
sahilmgandhi 18:6a4db94011d3 3083 __IO uint32_t DAT; /* Offset: 0x08 DAC Data Holding Register */
sahilmgandhi 18:6a4db94011d3 3084 __I uint32_t DATOUT; /* Offset: 0x0C DAC Data Output Register */
sahilmgandhi 18:6a4db94011d3 3085 __IO uint32_t STATUS; /* Offset: 0x10 DAC Status Register */
sahilmgandhi 18:6a4db94011d3 3086 __IO uint32_t TCTL; /* Offset: 0x14 DAC Timing Control Register */
sahilmgandhi 18:6a4db94011d3 3087
sahilmgandhi 18:6a4db94011d3 3088 } DAC_T;
sahilmgandhi 18:6a4db94011d3 3089
sahilmgandhi 18:6a4db94011d3 3090
sahilmgandhi 18:6a4db94011d3 3091
sahilmgandhi 18:6a4db94011d3 3092 /**
sahilmgandhi 18:6a4db94011d3 3093 @addtogroup DAC_CONST DAC Bit Field Definition
sahilmgandhi 18:6a4db94011d3 3094 Constant Definitions for DAC Controller
sahilmgandhi 18:6a4db94011d3 3095 @{ */
sahilmgandhi 18:6a4db94011d3 3096
sahilmgandhi 18:6a4db94011d3 3097 #define DAC_CTL_DACEN_Pos (0) /*!< DAC_T::CTL: DACEN Position */
sahilmgandhi 18:6a4db94011d3 3098 #define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos) /*!< DAC_T::CTL: DACEN Mask */
sahilmgandhi 18:6a4db94011d3 3099
sahilmgandhi 18:6a4db94011d3 3100 #define DAC_CTL_DACIEN_Pos (1) /*!< DAC_T::CTL: DACIEN Position */
sahilmgandhi 18:6a4db94011d3 3101 #define DAC_CTL_DACIEN_Msk (0x1ul << DAC_CTL_DACIEN_Pos) /*!< DAC_T::CTL: DACIEN Mask */
sahilmgandhi 18:6a4db94011d3 3102
sahilmgandhi 18:6a4db94011d3 3103 #define DAC_CTL_DMAEN_Pos (2) /*!< DAC_T::CTL: DMAEN Position */
sahilmgandhi 18:6a4db94011d3 3104 #define DAC_CTL_DMAEN_Msk (0x1ul << DAC_CTL_DMAEN_Pos) /*!< DAC_T::CTL: DMAEN Mask */
sahilmgandhi 18:6a4db94011d3 3105
sahilmgandhi 18:6a4db94011d3 3106 #define DAC_CTL_DMAURIEN_Pos (3) /*!< DAC_T::CTL: DMAURIEN Position */
sahilmgandhi 18:6a4db94011d3 3107 #define DAC_CTL_DMAURIEN_Msk (0x1ul << DAC_CTL_DMAURIEN_Pos) /*!< DAC_T::CTL: DMAURIEN Mask */
sahilmgandhi 18:6a4db94011d3 3108
sahilmgandhi 18:6a4db94011d3 3109 #define DAC_CTL_TRGEN_Pos (4) /*!< DAC_T::CTL: TRGEN Position */
sahilmgandhi 18:6a4db94011d3 3110 #define DAC_CTL_TRGEN_Msk (0x1ul << DAC_CTL_TRGEN_Pos) /*!< DAC_T::CTL: TRGEN Mask */
sahilmgandhi 18:6a4db94011d3 3111
sahilmgandhi 18:6a4db94011d3 3112 #define DAC_CTL_TRGSEL_Pos (5) /*!< DAC_T::CTL: TRGSEL Position */
sahilmgandhi 18:6a4db94011d3 3113 #define DAC_CTL_TRGSEL_Msk (0x7ul << DAC_CTL_TRGSEL_Pos) /*!< DAC_T::CTL: TRGSEL Mask */
sahilmgandhi 18:6a4db94011d3 3114
sahilmgandhi 18:6a4db94011d3 3115 #define DAC_CTL_BYPASS_Pos (8) /*!< DAC_T::CTL: BYPASS Position */
sahilmgandhi 18:6a4db94011d3 3116 #define DAC_CTL_BYPASS_Msk (0x1ul << DAC_CTL_BYPASS_Pos) /*!< DAC_T::CTL: BYPASS Mask */
sahilmgandhi 18:6a4db94011d3 3117
sahilmgandhi 18:6a4db94011d3 3118 #define DAC_CTL_LALIGN_Pos (10) /*!< DAC_T::CTL: LALIGN Position */
sahilmgandhi 18:6a4db94011d3 3119 #define DAC_CTL_LALIGN_Msk (0x1ul << DAC_CTL_LALIGN_Pos) /*!< DAC_T::CTL: LALIGN Mask */
sahilmgandhi 18:6a4db94011d3 3120
sahilmgandhi 18:6a4db94011d3 3121 #define DAC_CTL_ETRGSEL_Pos (12) /*!< DAC_T::CTL: ETRGSEL Position */
sahilmgandhi 18:6a4db94011d3 3122 #define DAC_CTL_ETRGSEL_Msk (0x3ul << DAC_CTL_ETRGSEL_Pos) /*!< DAC_T::CTL: ETRGSEL Mask */
sahilmgandhi 18:6a4db94011d3 3123
sahilmgandhi 18:6a4db94011d3 3124 #define DAC_SWTRG_SWTRG_Pos (0) /*!< DAC_T::SWTRG: SWTRG Position */
sahilmgandhi 18:6a4db94011d3 3125 #define DAC_SWTRG_SWTRG_Msk (0x1ul << DAC_SWTRG_SWTRG_Pos) /*!< DAC_T::SWTRG: SWTRG Mask */
sahilmgandhi 18:6a4db94011d3 3126
sahilmgandhi 18:6a4db94011d3 3127 #define DAC_DAT_DAC_DAT_Pos (0) /*!< DAC_T::DAT: DAC_DAT Position */
sahilmgandhi 18:6a4db94011d3 3128 #define DAC_DAT_DAC_DAT_Msk (0xfffful << DAC_DAT_DAC_DAT_Pos) /*!< DAC_T::DAT: DAC_DAT Mask */
sahilmgandhi 18:6a4db94011d3 3129
sahilmgandhi 18:6a4db94011d3 3130 #define DAC_DATOUT_DATOUT_Pos (0) /*!< DAC_T::DATOUT: DATOUT Position */
sahilmgandhi 18:6a4db94011d3 3131 #define DAC_DATOUT_DATOUT_Msk (0xffful << DAC_DATOUT_DATOUT_Pos) /*!< DAC_T::DATOUT: DATOUT Mask */
sahilmgandhi 18:6a4db94011d3 3132
sahilmgandhi 18:6a4db94011d3 3133 #define DAC_STATUS_FINISH_Pos (0) /*!< DAC_T::STATUS: FINISH Position */
sahilmgandhi 18:6a4db94011d3 3134 #define DAC_STATUS_FINISH_Msk (0x1ul << DAC_STATUS_FINISH_Pos) /*!< DAC_T::STATUS: FINISH Mask */
sahilmgandhi 18:6a4db94011d3 3135
sahilmgandhi 18:6a4db94011d3 3136 #define DAC_STATUS_DMAUDR_Pos (1) /*!< DAC_T::STATUS: DMAUDR Position */
sahilmgandhi 18:6a4db94011d3 3137 #define DAC_STATUS_DMAUDR_Msk (0x1ul << DAC_STATUS_DMAUDR_Pos) /*!< DAC_T::STATUS: DMAUDR Mask */
sahilmgandhi 18:6a4db94011d3 3138
sahilmgandhi 18:6a4db94011d3 3139 #define DAC_STATUS_BUSY_Pos (8) /*!< DAC_T::STATUS: BUSY Position */
sahilmgandhi 18:6a4db94011d3 3140 #define DAC_STATUS_BUSY_Msk (0x1ul << DAC_STATUS_BUSY_Pos) /*!< DAC_T::STATUS: BUSY Mask */
sahilmgandhi 18:6a4db94011d3 3141
sahilmgandhi 18:6a4db94011d3 3142 #define DAC_TCTL_SETTLET_Pos (0) /*!< DAC_T::TCTL: SETTLET Position */
sahilmgandhi 18:6a4db94011d3 3143 #define DAC_TCTL_SETTLET_Msk (0x3fful << DAC_TCTL_SETTLET_Pos) /*!< DAC_T::TCTL: SETTLET Mask */
sahilmgandhi 18:6a4db94011d3 3144
sahilmgandhi 18:6a4db94011d3 3145 /**@}*/ /* DAC_CONST */
sahilmgandhi 18:6a4db94011d3 3146 /**@}*/ /* end of DAC register group */
sahilmgandhi 18:6a4db94011d3 3147
sahilmgandhi 18:6a4db94011d3 3148
sahilmgandhi 18:6a4db94011d3 3149 /*---------------------- External Bus Interface Controller -------------------------*/
sahilmgandhi 18:6a4db94011d3 3150 /**
sahilmgandhi 18:6a4db94011d3 3151 @addtogroup EBI External Bus Interface Controller(EBI)
sahilmgandhi 18:6a4db94011d3 3152 Memory Mapped Structure for EBI Controller
sahilmgandhi 18:6a4db94011d3 3153 @{ */
sahilmgandhi 18:6a4db94011d3 3154
sahilmgandhi 18:6a4db94011d3 3155
sahilmgandhi 18:6a4db94011d3 3156 typedef struct
sahilmgandhi 18:6a4db94011d3 3157 {
sahilmgandhi 18:6a4db94011d3 3158
sahilmgandhi 18:6a4db94011d3 3159
sahilmgandhi 18:6a4db94011d3 3160
sahilmgandhi 18:6a4db94011d3 3161
sahilmgandhi 18:6a4db94011d3 3162 /**
sahilmgandhi 18:6a4db94011d3 3163 * @var EBI_T::CTL0
sahilmgandhi 18:6a4db94011d3 3164 * Offset: 0x00 External Bus Interface Bank0 Control Register
sahilmgandhi 18:6a4db94011d3 3165 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3166 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3167 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3168 * |[0] |EN |EBI Enable Bit
sahilmgandhi 18:6a4db94011d3 3169 * | | |This bit is the functional enable bit for EBI.
sahilmgandhi 18:6a4db94011d3 3170 * | | |0 = EBI function Disabled.
sahilmgandhi 18:6a4db94011d3 3171 * | | |1 = EBI function Enabled.
sahilmgandhi 18:6a4db94011d3 3172 * |[1] |DW16 |EBI Data Width 16-Bit Select
sahilmgandhi 18:6a4db94011d3 3173 * | | |This bit defines if the EBI data width is 8-bit or 16-bit.
sahilmgandhi 18:6a4db94011d3 3174 * | | |0 = EBI data width is 8-bit.
sahilmgandhi 18:6a4db94011d3 3175 * | | |1 = EBI data width is 16-bit.
sahilmgandhi 18:6a4db94011d3 3176 * |[2] |CSPOLINV |Chip Select Pin Polar Inverse
sahilmgandhi 18:6a4db94011d3 3177 * | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
sahilmgandhi 18:6a4db94011d3 3178 * | | |0 = Chip select pin (EBI_nCS) is active low.
sahilmgandhi 18:6a4db94011d3 3179 * | | |1 = Chip select pin (EBI_nCS) is active high.
sahilmgandhi 18:6a4db94011d3 3180 * |[10:8] |MCLKDIV |External Output Clock Divider
sahilmgandhi 18:6a4db94011d3 3181 * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
sahilmgandhi 18:6a4db94011d3 3182 * | | |000 = HCLK/1.
sahilmgandhi 18:6a4db94011d3 3183 * | | |001 = HCLK/2.
sahilmgandhi 18:6a4db94011d3 3184 * | | |010 = HCLK/4.
sahilmgandhi 18:6a4db94011d3 3185 * | | |011 = HCLK/8.
sahilmgandhi 18:6a4db94011d3 3186 * | | |100 = HCLK/16.
sahilmgandhi 18:6a4db94011d3 3187 * | | |101 = HCLK/32.
sahilmgandhi 18:6a4db94011d3 3188 * | | |110 = Reserved.
sahilmgandhi 18:6a4db94011d3 3189 * | | |111 = Reserved.
sahilmgandhi 18:6a4db94011d3 3190 * |[18:16] |TALE |Extend Time Of ALE
sahilmgandhi 18:6a4db94011d3 3191 * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
sahilmgandhi 18:6a4db94011d3 3192 * | | |tALE = (TALE+1)*EBI_MCLK.
sahilmgandhi 18:6a4db94011d3 3193 * | | |Note: This field only available in EBI_CTL0 register
sahilmgandhi 18:6a4db94011d3 3194 * |[24] |WBUFEN |EBI Write Buffer Enable Bit
sahilmgandhi 18:6a4db94011d3 3195 * | | |0 = EBI write buffer Disabled.
sahilmgandhi 18:6a4db94011d3 3196 * | | |1 = EBI write buffer Enabled.
sahilmgandhi 18:6a4db94011d3 3197 * | | |Note: This bit only available in EBI_CTL0 register
sahilmgandhi 18:6a4db94011d3 3198 * @var EBI_T::TCTL0
sahilmgandhi 18:6a4db94011d3 3199 * Offset: 0x04 External Bus Interface Bank0 Timing Control Register
sahilmgandhi 18:6a4db94011d3 3200 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3201 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3202 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3203 * |[7:3] |TACC |EBI Data Access Time
sahilmgandhi 18:6a4db94011d3 3204 * | | |TACC define data access time (tACC).
sahilmgandhi 18:6a4db94011d3 3205 * | | |tACC = (TACC +1) * EBI_MCLK.
sahilmgandhi 18:6a4db94011d3 3206 * |[10:8] |TAHD |EBI Data Access Hold Time
sahilmgandhi 18:6a4db94011d3 3207 * | | |TAHD define data access hold time (tAHD).
sahilmgandhi 18:6a4db94011d3 3208 * | | |tAHD = (TAHD +1) * EBI_MCLK.
sahilmgandhi 18:6a4db94011d3 3209 * |[15:12] |W2X |Idle Cycle After Write
sahilmgandhi 18:6a4db94011d3 3210 * | | |This field defines the number of W2X idle cycle.
sahilmgandhi 18:6a4db94011d3 3211 * | | |W2X idle cycle = (W2X * EBI_MCLK).
sahilmgandhi 18:6a4db94011d3 3212 * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
sahilmgandhi 18:6a4db94011d3 3213 * |[22] |RAHDOFF |Access Hold Time Disable Control When Read
sahilmgandhi 18:6a4db94011d3 3214 * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
sahilmgandhi 18:6a4db94011d3 3215 * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
sahilmgandhi 18:6a4db94011d3 3216 * |[23] |WAHDOFF |Access Hold Time Disable Control When Write
sahilmgandhi 18:6a4db94011d3 3217 * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
sahilmgandhi 18:6a4db94011d3 3218 * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
sahilmgandhi 18:6a4db94011d3 3219 * |[27:24] |R2R |Idle Cycle Between Read-To-Read
sahilmgandhi 18:6a4db94011d3 3220 * | | |This field defines the number of R2R idle cycle.
sahilmgandhi 18:6a4db94011d3 3221 * | | |R2R idle cycle = (R2R * EBI_MCLK).
sahilmgandhi 18:6a4db94011d3 3222 * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
sahilmgandhi 18:6a4db94011d3 3223 * @var EBI_T::CTL1
sahilmgandhi 18:6a4db94011d3 3224 * Offset: 0x10 External Bus Interface Bank1 Control Register
sahilmgandhi 18:6a4db94011d3 3225 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3226 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3227 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3228 * |[0] |EN |EBI Enable Bit
sahilmgandhi 18:6a4db94011d3 3229 * | | |This bit is the functional enable bit for EBI.
sahilmgandhi 18:6a4db94011d3 3230 * | | |0 = EBI function Disabled.
sahilmgandhi 18:6a4db94011d3 3231 * | | |1 = EBI function Enabled.
sahilmgandhi 18:6a4db94011d3 3232 * |[1] |DW16 |EBI Data Width 16-Bit Select
sahilmgandhi 18:6a4db94011d3 3233 * | | |This bit defines if the EBI data width is 8-bit or 16-bit.
sahilmgandhi 18:6a4db94011d3 3234 * | | |0 = EBI data width is 8-bit.
sahilmgandhi 18:6a4db94011d3 3235 * | | |1 = EBI data width is 16-bit.
sahilmgandhi 18:6a4db94011d3 3236 * |[2] |CSPOLINV |Chip Select Pin Polar Inverse
sahilmgandhi 18:6a4db94011d3 3237 * | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
sahilmgandhi 18:6a4db94011d3 3238 * | | |0 = Chip select pin (EBI_nCS) is active low.
sahilmgandhi 18:6a4db94011d3 3239 * | | |1 = Chip select pin (EBI_nCS) is active high.
sahilmgandhi 18:6a4db94011d3 3240 * |[10:8] |MCLKDIV |External Output Clock Divider
sahilmgandhi 18:6a4db94011d3 3241 * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
sahilmgandhi 18:6a4db94011d3 3242 * | | |000 = HCLK/1.
sahilmgandhi 18:6a4db94011d3 3243 * | | |001 = HCLK/2.
sahilmgandhi 18:6a4db94011d3 3244 * | | |010 = HCLK/4.
sahilmgandhi 18:6a4db94011d3 3245 * | | |011 = HCLK/8.
sahilmgandhi 18:6a4db94011d3 3246 * | | |100 = HCLK/16.
sahilmgandhi 18:6a4db94011d3 3247 * | | |101 = HCLK/32.
sahilmgandhi 18:6a4db94011d3 3248 * | | |110 = Reserved.
sahilmgandhi 18:6a4db94011d3 3249 * | | |111 = Reserved.
sahilmgandhi 18:6a4db94011d3 3250 * |[18:16] |TALE |Extend Time Of ALE
sahilmgandhi 18:6a4db94011d3 3251 * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
sahilmgandhi 18:6a4db94011d3 3252 * | | |tALE = (TALE+1)*EBI_MCLK.
sahilmgandhi 18:6a4db94011d3 3253 * | | |Note: This field only available in EBI_CTL0 register
sahilmgandhi 18:6a4db94011d3 3254 * |[24] |WBUFEN |EBI Write Buffer Enable Bit
sahilmgandhi 18:6a4db94011d3 3255 * | | |0 = EBI write buffer Disabled.
sahilmgandhi 18:6a4db94011d3 3256 * | | |1 = EBI write buffer Enabled.
sahilmgandhi 18:6a4db94011d3 3257 * | | |Note: This bit only available in EBI_CTL0 register
sahilmgandhi 18:6a4db94011d3 3258 * @var EBI_T::TCTL1
sahilmgandhi 18:6a4db94011d3 3259 * Offset: 0x14 External Bus Interface Bank1 Timing Control Register
sahilmgandhi 18:6a4db94011d3 3260 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3261 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3262 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3263 * |[7:3] |TACC |EBI Data Access Time
sahilmgandhi 18:6a4db94011d3 3264 * | | |TACC define data access time (tACC).
sahilmgandhi 18:6a4db94011d3 3265 * | | |tACC = (TACC +1) * EBI_MCLK.
sahilmgandhi 18:6a4db94011d3 3266 * |[10:8] |TAHD |EBI Data Access Hold Time
sahilmgandhi 18:6a4db94011d3 3267 * | | |TAHD define data access hold time (tAHD).
sahilmgandhi 18:6a4db94011d3 3268 * | | |tAHD = (TAHD +1) * EBI_MCLK.
sahilmgandhi 18:6a4db94011d3 3269 * |[15:12] |W2X |Idle Cycle After Write
sahilmgandhi 18:6a4db94011d3 3270 * | | |This field defines the number of W2X idle cycle.
sahilmgandhi 18:6a4db94011d3 3271 * | | |W2X idle cycle = (W2X * EBI_MCLK).
sahilmgandhi 18:6a4db94011d3 3272 * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
sahilmgandhi 18:6a4db94011d3 3273 * |[22] |RAHDOFF |Access Hold Time Disable Control When Read
sahilmgandhi 18:6a4db94011d3 3274 * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
sahilmgandhi 18:6a4db94011d3 3275 * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
sahilmgandhi 18:6a4db94011d3 3276 * |[23] |WAHDOFF |Access Hold Time Disable Control When Write
sahilmgandhi 18:6a4db94011d3 3277 * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
sahilmgandhi 18:6a4db94011d3 3278 * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
sahilmgandhi 18:6a4db94011d3 3279 * |[27:24] |R2R |Idle Cycle Between Read-To-Read
sahilmgandhi 18:6a4db94011d3 3280 * | | |This field defines the number of R2R idle cycle.
sahilmgandhi 18:6a4db94011d3 3281 * | | |R2R idle cycle = (R2R * EBI_MCLK).
sahilmgandhi 18:6a4db94011d3 3282 * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
sahilmgandhi 18:6a4db94011d3 3283 */
sahilmgandhi 18:6a4db94011d3 3284
sahilmgandhi 18:6a4db94011d3 3285 __IO uint32_t CTL0; /* Offset: 0x00 External Bus Interface Bank0 Control Register */
sahilmgandhi 18:6a4db94011d3 3286 __IO uint32_t TCTL0; /* Offset: 0x04 External Bus Interface Bank0 Timing Control Register */
sahilmgandhi 18:6a4db94011d3 3287 __I uint32_t RESERVE0[2];
sahilmgandhi 18:6a4db94011d3 3288 __IO uint32_t CTL1; /* Offset: 0x10 External Bus Interface Bank1 Control Register */
sahilmgandhi 18:6a4db94011d3 3289 __IO uint32_t TCTL1; /* Offset: 0x14 External Bus Interface Bank1 Timing Control Register */
sahilmgandhi 18:6a4db94011d3 3290
sahilmgandhi 18:6a4db94011d3 3291 } EBI_T;
sahilmgandhi 18:6a4db94011d3 3292
sahilmgandhi 18:6a4db94011d3 3293
sahilmgandhi 18:6a4db94011d3 3294
sahilmgandhi 18:6a4db94011d3 3295 /**
sahilmgandhi 18:6a4db94011d3 3296 @addtogroup EBI_CONST EBI Bit Field Definition
sahilmgandhi 18:6a4db94011d3 3297 Constant Definitions for EBI Controller
sahilmgandhi 18:6a4db94011d3 3298 @{ */
sahilmgandhi 18:6a4db94011d3 3299
sahilmgandhi 18:6a4db94011d3 3300 #define EBI_CTL0_EN_Pos (0) /*!< EBI_T::CTL0: EN Position */
sahilmgandhi 18:6a4db94011d3 3301 #define EBI_CTL0_EN_Msk (0x1ul << EBI_CTL0_EN_Pos) /*!< EBI_T::CTL0: EN Mask */
sahilmgandhi 18:6a4db94011d3 3302
sahilmgandhi 18:6a4db94011d3 3303 #define EBI_CTL0_DW16_Pos (1) /*!< EBI_T::CTL0: DW16 Position */
sahilmgandhi 18:6a4db94011d3 3304 #define EBI_CTL0_DW16_Msk (0x1ul << EBI_CTL0_DW16_Pos) /*!< EBI_T::CTL0: DW16 Mask */
sahilmgandhi 18:6a4db94011d3 3305
sahilmgandhi 18:6a4db94011d3 3306 #define EBI_CTL0_CSPOLINV_Pos (2) /*!< EBI_T::CTL0: CSPOLINV Position */
sahilmgandhi 18:6a4db94011d3 3307 #define EBI_CTL0_CSPOLINV_Msk (0x1ul << EBI_CTL0_CSPOLINV_Pos) /*!< EBI_T::CTL0: CSPOLINV Mask */
sahilmgandhi 18:6a4db94011d3 3308
sahilmgandhi 18:6a4db94011d3 3309 #define EBI_CTL0_MCLKDIV_Pos (8) /*!< EBI_T::CTL0: MCLKDIV Position */
sahilmgandhi 18:6a4db94011d3 3310 #define EBI_CTL0_MCLKDIV_Msk (0x7ul << EBI_CTL0_MCLKDIV_Pos) /*!< EBI_T::CTL0: MCLKDIV Mask */
sahilmgandhi 18:6a4db94011d3 3311
sahilmgandhi 18:6a4db94011d3 3312 #define EBI_CTL0_TALE_Pos (16) /*!< EBI_T::CTL0: TALE Position */
sahilmgandhi 18:6a4db94011d3 3313 #define EBI_CTL0_TALE_Msk (0x7ul << EBI_CTL0_TALE_Pos) /*!< EBI_T::CTL0: TALE Mask */
sahilmgandhi 18:6a4db94011d3 3314
sahilmgandhi 18:6a4db94011d3 3315 #define EBI_CTL0_WBUFEN_Pos (24) /*!< EBI_T::CTL0: WBUFEN Position */
sahilmgandhi 18:6a4db94011d3 3316 #define EBI_CTL0_WBUFEN_Msk (0x1ul << EBI_CTL0_WBUFEN_Pos) /*!< EBI_T::CTL0: WBUFEN Mask */
sahilmgandhi 18:6a4db94011d3 3317
sahilmgandhi 18:6a4db94011d3 3318 #define EBI_TCTL0_TACC_Pos (3) /*!< EBI_T::TCTL0: TACC Position */
sahilmgandhi 18:6a4db94011d3 3319 #define EBI_TCTL0_TACC_Msk (0x1ful << EBI_TCTL0_TACC_Pos) /*!< EBI_T::TCTL0: TACC Mask */
sahilmgandhi 18:6a4db94011d3 3320
sahilmgandhi 18:6a4db94011d3 3321 #define EBI_TCTL0_TAHD_Pos (8) /*!< EBI_T::TCTL0: TAHD Position */
sahilmgandhi 18:6a4db94011d3 3322 #define EBI_TCTL0_TAHD_Msk (0x7ul << EBI_TCTL0_TAHD_Pos) /*!< EBI_T::TCTL0: TAHD Mask */
sahilmgandhi 18:6a4db94011d3 3323
sahilmgandhi 18:6a4db94011d3 3324 #define EBI_TCTL0_W2X_Pos (12) /*!< EBI_T::TCTL0: W2X Position */
sahilmgandhi 18:6a4db94011d3 3325 #define EBI_TCTL0_W2X_Msk (0xful << EBI_TCTL0_W2X_Pos) /*!< EBI_T::TCTL0: W2X Mask */
sahilmgandhi 18:6a4db94011d3 3326
sahilmgandhi 18:6a4db94011d3 3327 #define EBI_TCTL0_RAHDOFF_Pos (22) /*!< EBI_T::TCTL0: RAHDOFF Position */
sahilmgandhi 18:6a4db94011d3 3328 #define EBI_TCTL0_RAHDOFF_Msk (0x1ul << EBI_TCTL0_RAHDOFF_Pos) /*!< EBI_T::TCTL0: RAHDOFF Mask */
sahilmgandhi 18:6a4db94011d3 3329
sahilmgandhi 18:6a4db94011d3 3330 #define EBI_TCTL0_WAHDOFF_Pos (23) /*!< EBI_T::TCTL0: WAHDOFF Position */
sahilmgandhi 18:6a4db94011d3 3331 #define EBI_TCTL0_WAHDOFF_Msk (0x1ul << EBI_TCTL0_WAHDOFF_Pos) /*!< EBI_T::TCTL0: WAHDOFF Mask */
sahilmgandhi 18:6a4db94011d3 3332
sahilmgandhi 18:6a4db94011d3 3333 #define EBI_TCTL0_R2R_Pos (24) /*!< EBI_T::TCTL0: R2R Position */
sahilmgandhi 18:6a4db94011d3 3334 #define EBI_TCTL0_R2R_Msk (0xful << EBI_TCTL0_R2R_Pos) /*!< EBI_T::TCTL0: R2R Mask */
sahilmgandhi 18:6a4db94011d3 3335
sahilmgandhi 18:6a4db94011d3 3336 #define EBI_CTL1_EN_Pos (0) /*!< EBI_T::CTL1: EN Position */
sahilmgandhi 18:6a4db94011d3 3337 #define EBI_CTL1_EN_Msk (0x1ul << EBI_CTL1_EN_Pos) /*!< EBI_T::CTL1: EN Mask */
sahilmgandhi 18:6a4db94011d3 3338
sahilmgandhi 18:6a4db94011d3 3339 #define EBI_CTL1_DW16_Pos (1) /*!< EBI_T::CTL1: DW16 Position */
sahilmgandhi 18:6a4db94011d3 3340 #define EBI_CTL1_DW16_Msk (0x1ul << EBI_CTL1_DW16_Pos) /*!< EBI_T::CTL1: DW16 Mask */
sahilmgandhi 18:6a4db94011d3 3341
sahilmgandhi 18:6a4db94011d3 3342 #define EBI_CTL1_CSPOLINV_Pos (2) /*!< EBI_T::CTL1: CSPOLINV Position */
sahilmgandhi 18:6a4db94011d3 3343 #define EBI_CTL1_CSPOLINV_Msk (0x1ul << EBI_CTL1_CSPOLINV_Pos) /*!< EBI_T::CTL1: CSPOLINV Mask */
sahilmgandhi 18:6a4db94011d3 3344
sahilmgandhi 18:6a4db94011d3 3345 #define EBI_CTL1_MCLKDIV_Pos (8) /*!< EBI_T::CTL1: MCLKDIV Position */
sahilmgandhi 18:6a4db94011d3 3346 #define EBI_CTL1_MCLKDIV_Msk (0x7ul << EBI_CTL1_MCLKDIV_Pos) /*!< EBI_T::CTL1: MCLKDIV Mask */
sahilmgandhi 18:6a4db94011d3 3347
sahilmgandhi 18:6a4db94011d3 3348 #define EBI_CTL1_TALE_Pos (16) /*!< EBI_T::CTL1: TALE Position */
sahilmgandhi 18:6a4db94011d3 3349 #define EBI_CTL1_TALE_Msk (0x7ul << EBI_CTL1_TALE_Pos) /*!< EBI_T::CTL1: TALE Mask */
sahilmgandhi 18:6a4db94011d3 3350
sahilmgandhi 18:6a4db94011d3 3351 #define EBI_CTL1_WBUFEN_Pos (24) /*!< EBI_T::CTL1: WBUFEN Position */
sahilmgandhi 18:6a4db94011d3 3352 #define EBI_CTL1_WBUFEN_Msk (0x1ul << EBI_CTL1_WBUFEN_Pos) /*!< EBI_T::CTL1: WBUFEN Mask */
sahilmgandhi 18:6a4db94011d3 3353
sahilmgandhi 18:6a4db94011d3 3354 #define EBI_TCTL1_TACC_Pos (3) /*!< EBI_T::TCTL1: TACC Position */
sahilmgandhi 18:6a4db94011d3 3355 #define EBI_TCTL1_TACC_Msk (0x1ful << EBI_TCTL1_TACC_Pos) /*!< EBI_T::TCTL1: TACC Mask */
sahilmgandhi 18:6a4db94011d3 3356
sahilmgandhi 18:6a4db94011d3 3357 #define EBI_TCTL1_TAHD_Pos (8) /*!< EBI_T::TCTL1: TAHD Position */
sahilmgandhi 18:6a4db94011d3 3358 #define EBI_TCTL1_TAHD_Msk (0x7ul << EBI_TCTL1_TAHD_Pos) /*!< EBI_T::TCTL1: TAHD Mask */
sahilmgandhi 18:6a4db94011d3 3359
sahilmgandhi 18:6a4db94011d3 3360 #define EBI_TCTL1_W2X_Pos (12) /*!< EBI_T::TCTL1: W2X Position */
sahilmgandhi 18:6a4db94011d3 3361 #define EBI_TCTL1_W2X_Msk (0xful << EBI_TCTL1_W2X_Pos) /*!< EBI_T::TCTL1: W2X Mask */
sahilmgandhi 18:6a4db94011d3 3362
sahilmgandhi 18:6a4db94011d3 3363 #define EBI_TCTL1_RAHDOFF_Pos (22) /*!< EBI_T::TCTL1: RAHDOFF Position */
sahilmgandhi 18:6a4db94011d3 3364 #define EBI_TCTL1_RAHDOFF_Msk (0x1ul << EBI_TCTL1_RAHDOFF_Pos) /*!< EBI_T::TCTL1: RAHDOFF Mask */
sahilmgandhi 18:6a4db94011d3 3365
sahilmgandhi 18:6a4db94011d3 3366 #define EBI_TCTL1_WAHDOFF_Pos (23) /*!< EBI_T::TCTL1: WAHDOFF Position */
sahilmgandhi 18:6a4db94011d3 3367 #define EBI_TCTL1_WAHDOFF_Msk (0x1ul << EBI_TCTL1_WAHDOFF_Pos) /*!< EBI_T::TCTL1: WAHDOFF Mask */
sahilmgandhi 18:6a4db94011d3 3368
sahilmgandhi 18:6a4db94011d3 3369 #define EBI_TCTL1_R2R_Pos (24) /*!< EBI_T::TCTL1: R2R Position */
sahilmgandhi 18:6a4db94011d3 3370 #define EBI_TCTL1_R2R_Msk (0xful << EBI_TCTL1_R2R_Pos) /*!< EBI_T::TCTL1: R2R Mask */
sahilmgandhi 18:6a4db94011d3 3371
sahilmgandhi 18:6a4db94011d3 3372 /**@}*/ /* EBI_CONST */
sahilmgandhi 18:6a4db94011d3 3373 /**@}*/ /* end of EBI register group */
sahilmgandhi 18:6a4db94011d3 3374
sahilmgandhi 18:6a4db94011d3 3375
sahilmgandhi 18:6a4db94011d3 3376 /*---------------------- Flash Memory Controller -------------------------*/
sahilmgandhi 18:6a4db94011d3 3377 /**
sahilmgandhi 18:6a4db94011d3 3378 @addtogroup FMC Flash Memory Controller(FMC)
sahilmgandhi 18:6a4db94011d3 3379 Memory Mapped Structure for FMC Controller
sahilmgandhi 18:6a4db94011d3 3380 @{ */
sahilmgandhi 18:6a4db94011d3 3381
sahilmgandhi 18:6a4db94011d3 3382
sahilmgandhi 18:6a4db94011d3 3383 typedef struct
sahilmgandhi 18:6a4db94011d3 3384 {
sahilmgandhi 18:6a4db94011d3 3385
sahilmgandhi 18:6a4db94011d3 3386
sahilmgandhi 18:6a4db94011d3 3387
sahilmgandhi 18:6a4db94011d3 3388
sahilmgandhi 18:6a4db94011d3 3389 /**
sahilmgandhi 18:6a4db94011d3 3390 * @var FMC_T::ISPCTL
sahilmgandhi 18:6a4db94011d3 3391 * Offset: 0x00 ISP Control Register
sahilmgandhi 18:6a4db94011d3 3392 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3393 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3394 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3395 * |[0] |ISPEN |ISP Enable Bit (Write Protect)
sahilmgandhi 18:6a4db94011d3 3396 * | | |ISP function enable bit. Set this bit to enable ISP function.
sahilmgandhi 18:6a4db94011d3 3397 * | | |0 = ISP function Disabled.
sahilmgandhi 18:6a4db94011d3 3398 * | | |1 = ISP function Enabled.
sahilmgandhi 18:6a4db94011d3 3399 * |[1] |BS |Boot Select (Write Protect)
sahilmgandhi 18:6a4db94011d3 3400 * | | |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively.
sahilmgandhi 18:6a4db94011d3 3401 * | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from.
sahilmgandhi 18:6a4db94011d3 3402 * | | |This bit is initiated with the inverted value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
sahilmgandhi 18:6a4db94011d3 3403 * | | |0 = Booting from APROM when MBS (CONFIG0[5]) is 1.
sahilmgandhi 18:6a4db94011d3 3404 * | | |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1.
sahilmgandhi 18:6a4db94011d3 3405 * |[3] |APUEN |APROM Update Enable Bit (Write Protect)
sahilmgandhi 18:6a4db94011d3 3406 * | | |0 = APROM cannot be updated when the chip runs in APROM.
sahilmgandhi 18:6a4db94011d3 3407 * | | |1 = APROM can be updated when the chip runs in APROM.
sahilmgandhi 18:6a4db94011d3 3408 * |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect)
sahilmgandhi 18:6a4db94011d3 3409 * | | |0 = CONFIG cannot be updated.
sahilmgandhi 18:6a4db94011d3 3410 * | | |1 = CONFIG can be updated.
sahilmgandhi 18:6a4db94011d3 3411 * |[5] |LDUEN |LDROM Update Enable Bit (Write Protect)
sahilmgandhi 18:6a4db94011d3 3412 * | | |LDROM update enable bit.
sahilmgandhi 18:6a4db94011d3 3413 * | | |0 = LDROM cannot be updated.
sahilmgandhi 18:6a4db94011d3 3414 * | | |1 = LDROM can be updated.
sahilmgandhi 18:6a4db94011d3 3415 * |[6] |ISPFF |ISP Fail Flag (Write Protect)
sahilmgandhi 18:6a4db94011d3 3416 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
sahilmgandhi 18:6a4db94011d3 3417 * | | |This bit needs to be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 3418 * | | |(1) APROM writes to itself if APUEN is set to 0.
sahilmgandhi 18:6a4db94011d3 3419 * | | |(2) LDROM writes to itself if LDUEN is set to 0.
sahilmgandhi 18:6a4db94011d3 3420 * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
sahilmgandhi 18:6a4db94011d3 3421 * | | |(4) SPROM is erased/programmed if SPUEN is set to 0
sahilmgandhi 18:6a4db94011d3 3422 * | | |(5) SPROM is programmed at SPROM secured mode.
sahilmgandhi 18:6a4db94011d3 3423 * | | |(6) Page Erase command at LOCK mode with ICE connection
sahilmgandhi 18:6a4db94011d3 3424 * | | |(7) Erase or Program command at brown-out detected
sahilmgandhi 18:6a4db94011d3 3425 * | | |(8) Destination address is illegal, such as over an available range.
sahilmgandhi 18:6a4db94011d3 3426 * | | |(9) Invalid ISP commands
sahilmgandhi 18:6a4db94011d3 3427 * |[16] |BL |Boot Loader Booting (Write Protect)
sahilmgandhi 18:6a4db94011d3 3428 * | | |This bit is initiated with the inverted value of MBS (CONFIG0[5]).
sahilmgandhi 18:6a4db94011d3 3429 * | | |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded.
sahilmgandhi 18:6a4db94011d3 3430 * | | |This bit is used to check chip boot from Boot Loader or not.
sahilmgandhi 18:6a4db94011d3 3431 * | | |User should keep original value of this bit when updating FMC_ISPCTL register.
sahilmgandhi 18:6a4db94011d3 3432 * | | |0 = Booting from APROM or LDROM.
sahilmgandhi 18:6a4db94011d3 3433 * | | |1 = Booting from Boot Loader.
sahilmgandhi 18:6a4db94011d3 3434 * @var FMC_T::ISPADDR
sahilmgandhi 18:6a4db94011d3 3435 * Offset: 0x04 ISP Address Register
sahilmgandhi 18:6a4db94011d3 3436 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3437 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3438 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3439 * |[31:0] |ISPADDR |ISP Address
sahilmgandhi 18:6a4db94011d3 3440 * | | |The NuMicro M451 series is equipped with embedded flash.
sahilmgandhi 18:6a4db94011d3 3441 * | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation.
sahilmgandhi 18:6a4db94011d3 3442 * | | |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.
sahilmgandhi 18:6a4db94011d3 3443 * | | |For Checksum Calculation command, this field is the flash starting address for checksum calculation, 2 Kbytes alignment is necessary for checksum calculation.
sahilmgandhi 18:6a4db94011d3 3444 * @var FMC_T::ISPDAT
sahilmgandhi 18:6a4db94011d3 3445 * Offset: 0x08 ISP Data Register
sahilmgandhi 18:6a4db94011d3 3446 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3447 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3448 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3449 * |[31:0] |ISPDAT |ISP Data
sahilmgandhi 18:6a4db94011d3 3450 * | | |Write data to this register before ISP program operation.
sahilmgandhi 18:6a4db94011d3 3451 * | | |Read data from this register after ISP read operation.
sahilmgandhi 18:6a4db94011d3 3452 * | | |For Run Checksum Calculation command, ISPDAT is the memory size (byte) and 2 Kbytes alignment.
sahilmgandhi 18:6a4db94011d3 3453 * | | |For ISP Read Checksum command, ISPDAT is the checksum result.
sahilmgandhi 18:6a4db94011d3 3454 * | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, (2) the memory range for checksum calculation is incorrect, or (3) all of data are 0.
sahilmgandhi 18:6a4db94011d3 3455 * @var FMC_T::ISPCMD
sahilmgandhi 18:6a4db94011d3 3456 * Offset: 0x0C ISP CMD Register
sahilmgandhi 18:6a4db94011d3 3457 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3458 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3459 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3460 * |[6:0] |CMD |ISP CMD
sahilmgandhi 18:6a4db94011d3 3461 * | | |ISP command table is shown below:
sahilmgandhi 18:6a4db94011d3 3462 * | | |0x00= FLASH Read.
sahilmgandhi 18:6a4db94011d3 3463 * | | |0x04= Read Unique ID.
sahilmgandhi 18:6a4db94011d3 3464 * | | |0x0B= Read Company ID.
sahilmgandhi 18:6a4db94011d3 3465 * | | |0x0C= Read Device ID.
sahilmgandhi 18:6a4db94011d3 3466 * | | |0x0D= Read Checksum.
sahilmgandhi 18:6a4db94011d3 3467 * | | |0x21= FLASH 32-bit Program.
sahilmgandhi 18:6a4db94011d3 3468 * | | |0x22= FLASH Page Erase.
sahilmgandhi 18:6a4db94011d3 3469 * | | |0x27= FLASH Multi-Word Program.
sahilmgandhi 18:6a4db94011d3 3470 * | | |0x2D= Run Checksum Calculation.
sahilmgandhi 18:6a4db94011d3 3471 * | | |0x2E= Vector Remap.
sahilmgandhi 18:6a4db94011d3 3472 * | | |0x61= FLASH 64-bit Program.
sahilmgandhi 18:6a4db94011d3 3473 * | | |The other commands are invalid.
sahilmgandhi 18:6a4db94011d3 3474 * @var FMC_T::ISPTRG
sahilmgandhi 18:6a4db94011d3 3475 * Offset: 0x10 ISP Trigger Control Register
sahilmgandhi 18:6a4db94011d3 3476 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3477 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3478 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3479 * |[0] |ISPGO |ISP Start Trigger (Write Protect)
sahilmgandhi 18:6a4db94011d3 3480 * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
sahilmgandhi 18:6a4db94011d3 3481 * | | |0 = ISP operation is finished.
sahilmgandhi 18:6a4db94011d3 3482 * | | |1 = ISP is progressed.
sahilmgandhi 18:6a4db94011d3 3483 * @var FMC_T::DFBA
sahilmgandhi 18:6a4db94011d3 3484 * Offset: 0x14 Data Flash Base Address
sahilmgandhi 18:6a4db94011d3 3485 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3486 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3487 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3488 * |[31:0] |DFBA |Data Flash Base Address
sahilmgandhi 18:6a4db94011d3 3489 * | | |This register indicates Data Flash start address. It is a read only register.
sahilmgandhi 18:6a4db94011d3 3490 * | | |The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1
sahilmgandhi 18:6a4db94011d3 3491 * | | |This register is valid when DFEN (CONFIG0[0]) =0 .
sahilmgandhi 18:6a4db94011d3 3492 * @var FMC_T::FTCTL
sahilmgandhi 18:6a4db94011d3 3493 * Offset: 0x18 Flash Access Time Control Register
sahilmgandhi 18:6a4db94011d3 3494 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3495 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3496 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3497 * |[6:4] |FOM |Frequency Optimization Mode (Write Protect)
sahilmgandhi 18:6a4db94011d3 3498 * | | |The NuMicro M451 series support adjustable flash access timing to optimize the flash access cycles in different working frequency.
sahilmgandhi 18:6a4db94011d3 3499 * | | |001 = Frequency <= 12MHz.
sahilmgandhi 18:6a4db94011d3 3500 * | | |010 = Frequency <= 36MHz.
sahilmgandhi 18:6a4db94011d3 3501 * | | |100 = Frequency <= 60MHz.
sahilmgandhi 18:6a4db94011d3 3502 * | | |Others = Frequency <= 72MHz.
sahilmgandhi 18:6a4db94011d3 3503 * @var FMC_T::ISPSTS
sahilmgandhi 18:6a4db94011d3 3504 * Offset: 0x40 ISP Status Register
sahilmgandhi 18:6a4db94011d3 3505 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3506 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3507 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3508 * |[0] |ISPBUSY |ISP Busy Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 3509 * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
sahilmgandhi 18:6a4db94011d3 3510 * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
sahilmgandhi 18:6a4db94011d3 3511 * | | |0 = ISP operation is finished.
sahilmgandhi 18:6a4db94011d3 3512 * | | |1 = ISP is progressed.
sahilmgandhi 18:6a4db94011d3 3513 * |[2:1] |CBS |Boot Selection Of CONFIG (Read Only)
sahilmgandhi 18:6a4db94011d3 3514 * | | |This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
sahilmgandhi 18:6a4db94011d3 3515 * | | |The following function is valid when MBS (FMC_ISPSTS[3])= 1.
sahilmgandhi 18:6a4db94011d3 3516 * | | |00 = LDROM with IAP mode.
sahilmgandhi 18:6a4db94011d3 3517 * | | |01 = LDROM without IAP mode.
sahilmgandhi 18:6a4db94011d3 3518 * | | |10 = APROM with IAP mode.
sahilmgandhi 18:6a4db94011d3 3519 * | | |11 = APROM without IAP mode.
sahilmgandhi 18:6a4db94011d3 3520 * |[3] |MBS |Boot From Boot Loader Selection Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 3521 * | | |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
sahilmgandhi 18:6a4db94011d3 3522 * | | |0 = Booting from Boot Loader.
sahilmgandhi 18:6a4db94011d3 3523 * | | |1 = Booting
sahilmgandhi 18:6a4db94011d3 3524 * | | |from LDROM/APROM.(see CBS bit setting)
sahilmgandhi 18:6a4db94011d3 3525 * |[5] |PGFF |Flash Program With Fast Verification Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 3526 * | | |This bit is set if data is mismatched at ISP programming verification.
sahilmgandhi 18:6a4db94011d3 3527 * | | |This bit is clear by performing ISP flash erase or ISP read CID operation.
sahilmgandhi 18:6a4db94011d3 3528 * | | |0 = Flash Program is success.
sahilmgandhi 18:6a4db94011d3 3529 * | | |1 = Flash Program is fail. Program data is different with data in the flash memory
sahilmgandhi 18:6a4db94011d3 3530 * |[6] |ISPFF |ISP Fail Flag (Write Protect)
sahilmgandhi 18:6a4db94011d3 3531 * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6].
sahilmgandhi 18:6a4db94011d3 3532 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
sahilmgandhi 18:6a4db94011d3 3533 * | | |(1) APROM writes to itself if APUEN is set to 0.
sahilmgandhi 18:6a4db94011d3 3534 * | | |(2) LDROM writes to itself if LDUEN is set to 0.
sahilmgandhi 18:6a4db94011d3 3535 * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
sahilmgandhi 18:6a4db94011d3 3536 * | | |(4) SPROM is erased/programmed if SPUEN is set to 0
sahilmgandhi 18:6a4db94011d3 3537 * | | |(5) SPROM is programmed at SPROM secured mode.
sahilmgandhi 18:6a4db94011d3 3538 * | | |(6) Page Erase command at LOCK mode with ICE connection
sahilmgandhi 18:6a4db94011d3 3539 * | | |(7) Erase or Program command at brown-out detected
sahilmgandhi 18:6a4db94011d3 3540 * | | |(8) Destination address is illegal, such as over an available range.
sahilmgandhi 18:6a4db94011d3 3541 * | | |(9) Invalid ISP commands
sahilmgandhi 18:6a4db94011d3 3542 * |[23:9] |VECMAP |Vector Page Mapping Address (Read Only)
sahilmgandhi 18:6a4db94011d3 3543 * | | |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9'h000} ~ {VECMAP[14:0], 9'h1FF}
sahilmgandhi 18:6a4db94011d3 3544 * @var FMC_T::MPDAT0
sahilmgandhi 18:6a4db94011d3 3545 * Offset: 0x80 ISP Data0 Register
sahilmgandhi 18:6a4db94011d3 3546 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3547 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3548 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3549 * |[31:0] |ISPDAT0 |ISP Data 0
sahilmgandhi 18:6a4db94011d3 3550 * | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data
sahilmgandhi 18:6a4db94011d3 3551 * @var FMC_T::MPDAT1
sahilmgandhi 18:6a4db94011d3 3552 * Offset: 0x84 ISP Data1 Register
sahilmgandhi 18:6a4db94011d3 3553 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3554 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3555 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3556 * |[31:0] |ISPDAT1 |ISP Data 1
sahilmgandhi 18:6a4db94011d3 3557 * | | |This register is the second 32-bit data for 64-bit/multi-word programming.
sahilmgandhi 18:6a4db94011d3 3558 * @var FMC_T::MPDAT2
sahilmgandhi 18:6a4db94011d3 3559 * Offset: 0x88 ISP Data2 Register
sahilmgandhi 18:6a4db94011d3 3560 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3561 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3562 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3563 * |[31:0] |ISPDAT2 |ISP Data 2
sahilmgandhi 18:6a4db94011d3 3564 * | | |This register is the third 32-bit data for multi-word programming.
sahilmgandhi 18:6a4db94011d3 3565 * @var FMC_T::MPDAT3
sahilmgandhi 18:6a4db94011d3 3566 * Offset: 0x8C ISP Data3 Register
sahilmgandhi 18:6a4db94011d3 3567 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3568 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3569 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3570 * |[31:0] |ISPDAT3 |ISP Data 3
sahilmgandhi 18:6a4db94011d3 3571 * | | |This register is the fourth 32-bit data for multi-word programming.
sahilmgandhi 18:6a4db94011d3 3572 * @var FMC_T::MPSTS
sahilmgandhi 18:6a4db94011d3 3573 * Offset: 0xC0 ISP Multi-Program Status Register
sahilmgandhi 18:6a4db94011d3 3574 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3575 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3576 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3577 * |[0] |MPBUSY |ISP Multi-Word Program Busy Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 3578 * | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.
sahilmgandhi 18:6a4db94011d3 3579 * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
sahilmgandhi 18:6a4db94011d3 3580 * | | |0 = ISP Multi-Word program operation is finished.
sahilmgandhi 18:6a4db94011d3 3581 * | | |1 = ISP Multi-Word program operation
sahilmgandhi 18:6a4db94011d3 3582 * | | |is progressed.
sahilmgandhi 18:6a4db94011d3 3583 * |[1] |PPGO |ISP Multi-Program Status (Read Only)
sahilmgandhi 18:6a4db94011d3 3584 * | | |0 = ISP multi-word program operation is not active.
sahilmgandhi 18:6a4db94011d3 3585 * | | |1 = ISP multi-word program operation is in progress.
sahilmgandhi 18:6a4db94011d3 3586 * |[2] |ISPFF |ISP Fail Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 3587 * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6].
sahilmgandhi 18:6a4db94011d3 3588 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
sahilmgandhi 18:6a4db94011d3 3589 * | | |(1) APROM writes to itself if APUEN is set to 0.
sahilmgandhi 18:6a4db94011d3 3590 * | | |(2) LDROM writes to itself if LDUEN is set to 0.
sahilmgandhi 18:6a4db94011d3 3591 * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
sahilmgandhi 18:6a4db94011d3 3592 * | | |(4) SPROM is erased/programmed if SPUEN is set to 0
sahilmgandhi 18:6a4db94011d3 3593 * | | |(5) SPROM is programmed at SPROM secured mode.
sahilmgandhi 18:6a4db94011d3 3594 * | | |(6) Page Erase command at LOCK mode with ICE connection
sahilmgandhi 18:6a4db94011d3 3595 * | | |(7) Erase or Program command at brown-out detected
sahilmgandhi 18:6a4db94011d3 3596 * | | |(8) Destination address is illegal, such as over an available range.
sahilmgandhi 18:6a4db94011d3 3597 * | | |(9) Invalid ISP commands
sahilmgandhi 18:6a4db94011d3 3598 * |[4] |D0 |ISP DATA 0 Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 3599 * | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete.
sahilmgandhi 18:6a4db94011d3 3600 * | | |0 = FMC_MPDAT0 register is empty, or program to flash complete.
sahilmgandhi 18:6a4db94011d3 3601 * | | |1 = FMC_MPDAT0 register has been written, and not program to flash complete.
sahilmgandhi 18:6a4db94011d3 3602 * |[5] |D1 |ISP DATA 1 Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 3603 * | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete.
sahilmgandhi 18:6a4db94011d3 3604 * | | |0 = FMC_MPDAT1 register is empty, or program to flash complete.
sahilmgandhi 18:6a4db94011d3 3605 * | | |1 = FMC_MPDAT1 register has been written, and not program to flash complete.
sahilmgandhi 18:6a4db94011d3 3606 * |[6] |D2 |ISP DATA 2 Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 3607 * | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete.
sahilmgandhi 18:6a4db94011d3 3608 * | | |0 = FMC_MPDAT2 register is empty, or program to flash complete.
sahilmgandhi 18:6a4db94011d3 3609 * | | |1 = FMC_MPDAT2 register has been written, and not program to flash complete.
sahilmgandhi 18:6a4db94011d3 3610 * |[7] |D3 |ISP DATA 3 Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 3611 * | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete.
sahilmgandhi 18:6a4db94011d3 3612 * | | |0 = FMC_MPDAT3 register is empty, or program to flash complete.
sahilmgandhi 18:6a4db94011d3 3613 * | | |1 = FMC_MPDAT3 register has been written, and not program to flash complete.
sahilmgandhi 18:6a4db94011d3 3614 * @var FMC_T::MPADDR
sahilmgandhi 18:6a4db94011d3 3615 * Offset: 0xC4 ISP Multi-Program Address Register
sahilmgandhi 18:6a4db94011d3 3616 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3617 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3618 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3619 * |[31:0] |MPADDR |ISP Multi-Word Program Address
sahilmgandhi 18:6a4db94011d3 3620 * | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.
sahilmgandhi 18:6a4db94011d3 3621 * | | |MPADDR will keep the final ISP address when ISP multi-word program is complete.
sahilmgandhi 18:6a4db94011d3 3622 */
sahilmgandhi 18:6a4db94011d3 3623
sahilmgandhi 18:6a4db94011d3 3624 __IO uint32_t ISPCTL; /* Offset: 0x00 ISP Control Register */
sahilmgandhi 18:6a4db94011d3 3625 __IO uint32_t ISPADDR; /* Offset: 0x04 ISP Address Register */
sahilmgandhi 18:6a4db94011d3 3626 __IO uint32_t ISPDAT; /* Offset: 0x08 ISP Data Register */
sahilmgandhi 18:6a4db94011d3 3627 __IO uint32_t ISPCMD; /* Offset: 0x0C ISP CMD Register */
sahilmgandhi 18:6a4db94011d3 3628 __IO uint32_t ISPTRG; /* Offset: 0x10 ISP Trigger Control Register */
sahilmgandhi 18:6a4db94011d3 3629 __I uint32_t DFBA; /* Offset: 0x14 Data Flash Base Address */
sahilmgandhi 18:6a4db94011d3 3630 __IO uint32_t FTCTL; /* Offset: 0x18 Flash Access Time Control Register */
sahilmgandhi 18:6a4db94011d3 3631 __I uint32_t RESERVE0[9];
sahilmgandhi 18:6a4db94011d3 3632 __I uint32_t ISPSTS; /* Offset: 0x40 ISP Status Register */
sahilmgandhi 18:6a4db94011d3 3633 __I uint32_t RESERVE1[15];
sahilmgandhi 18:6a4db94011d3 3634 __IO uint32_t MPDAT0; /* Offset: 0x80 ISP Data0 Register */
sahilmgandhi 18:6a4db94011d3 3635 __IO uint32_t MPDAT1; /* Offset: 0x84 ISP Data1 Register */
sahilmgandhi 18:6a4db94011d3 3636 __IO uint32_t MPDAT2; /* Offset: 0x88 ISP Data2 Register */
sahilmgandhi 18:6a4db94011d3 3637 __IO uint32_t MPDAT3; /* Offset: 0x8C ISP Data3 Register */
sahilmgandhi 18:6a4db94011d3 3638 __I uint32_t RESERVE2[12];
sahilmgandhi 18:6a4db94011d3 3639 __I uint32_t MPSTS; /* Offset: 0xC0 ISP Multi-Program Status Register */
sahilmgandhi 18:6a4db94011d3 3640 __I uint32_t MPADDR; /* Offset: 0xC4 ISP Multi-Program Address Register */
sahilmgandhi 18:6a4db94011d3 3641
sahilmgandhi 18:6a4db94011d3 3642 } FMC_T;
sahilmgandhi 18:6a4db94011d3 3643
sahilmgandhi 18:6a4db94011d3 3644
sahilmgandhi 18:6a4db94011d3 3645
sahilmgandhi 18:6a4db94011d3 3646
sahilmgandhi 18:6a4db94011d3 3647 /**
sahilmgandhi 18:6a4db94011d3 3648 @addtogroup FMC_CONST FMC Bit Field Definition
sahilmgandhi 18:6a4db94011d3 3649 Constant Definitions for FMC Controller
sahilmgandhi 18:6a4db94011d3 3650 @{ */
sahilmgandhi 18:6a4db94011d3 3651
sahilmgandhi 18:6a4db94011d3 3652 #define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */
sahilmgandhi 18:6a4db94011d3 3653 #define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */
sahilmgandhi 18:6a4db94011d3 3654
sahilmgandhi 18:6a4db94011d3 3655 #define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */
sahilmgandhi 18:6a4db94011d3 3656 #define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */
sahilmgandhi 18:6a4db94011d3 3657
sahilmgandhi 18:6a4db94011d3 3658 #define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */
sahilmgandhi 18:6a4db94011d3 3659 #define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */
sahilmgandhi 18:6a4db94011d3 3660
sahilmgandhi 18:6a4db94011d3 3661 #define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */
sahilmgandhi 18:6a4db94011d3 3662 #define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */
sahilmgandhi 18:6a4db94011d3 3663
sahilmgandhi 18:6a4db94011d3 3664 #define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */
sahilmgandhi 18:6a4db94011d3 3665 #define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */
sahilmgandhi 18:6a4db94011d3 3666
sahilmgandhi 18:6a4db94011d3 3667 #define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */
sahilmgandhi 18:6a4db94011d3 3668 #define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */
sahilmgandhi 18:6a4db94011d3 3669
sahilmgandhi 18:6a4db94011d3 3670 #define FMC_ISPCTL_BL_Pos (16) /*!< FMC_T::ISPCTL: BL Position */
sahilmgandhi 18:6a4db94011d3 3671 #define FMC_ISPCTL_BL_Msk (0x1ul << FMC_ISPCTL_BL_Pos) /*!< FMC_T::ISPCTL: BL Mask */
sahilmgandhi 18:6a4db94011d3 3672
sahilmgandhi 18:6a4db94011d3 3673 #define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */
sahilmgandhi 18:6a4db94011d3 3674 #define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */
sahilmgandhi 18:6a4db94011d3 3675
sahilmgandhi 18:6a4db94011d3 3676 #define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */
sahilmgandhi 18:6a4db94011d3 3677 #define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */
sahilmgandhi 18:6a4db94011d3 3678
sahilmgandhi 18:6a4db94011d3 3679 #define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */
sahilmgandhi 18:6a4db94011d3 3680 #define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */
sahilmgandhi 18:6a4db94011d3 3681
sahilmgandhi 18:6a4db94011d3 3682 #define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */
sahilmgandhi 18:6a4db94011d3 3683 #define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */
sahilmgandhi 18:6a4db94011d3 3684
sahilmgandhi 18:6a4db94011d3 3685 #define FMC_DFBA_DFBA_Pos (0) /*!< FMC_T::DFBA: DFBA Position */
sahilmgandhi 18:6a4db94011d3 3686 #define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) /*!< FMC_T::DFBA: DFBA Mask */
sahilmgandhi 18:6a4db94011d3 3687
sahilmgandhi 18:6a4db94011d3 3688 #define FMC_FTCTL_FOM_Pos (4) /*!< FMC_T::FTCTL: FOM Position */
sahilmgandhi 18:6a4db94011d3 3689 #define FMC_FTCTL_FOM_Msk (0x7ul << FMC_FTCTL_FOM_Pos) /*!< FMC_T::FTCTL: FOM Mask */
sahilmgandhi 18:6a4db94011d3 3690
sahilmgandhi 18:6a4db94011d3 3691 #define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */
sahilmgandhi 18:6a4db94011d3 3692 #define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */
sahilmgandhi 18:6a4db94011d3 3693
sahilmgandhi 18:6a4db94011d3 3694 #define FMC_ISPSTS_CBS_Pos (1) /*!< FMC_T::ISPSTS: CBS Position */
sahilmgandhi 18:6a4db94011d3 3695 #define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */
sahilmgandhi 18:6a4db94011d3 3696
sahilmgandhi 18:6a4db94011d3 3697 #define FMC_ISPSTS_MBS_Pos (3) /*!< FMC_T::ISPSTS: MBS Position */
sahilmgandhi 18:6a4db94011d3 3698 #define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos) /*!< FMC_T::ISPSTS: MBS Mask */
sahilmgandhi 18:6a4db94011d3 3699
sahilmgandhi 18:6a4db94011d3 3700 #define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */
sahilmgandhi 18:6a4db94011d3 3701 #define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */
sahilmgandhi 18:6a4db94011d3 3702
sahilmgandhi 18:6a4db94011d3 3703 #define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */
sahilmgandhi 18:6a4db94011d3 3704 #define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */
sahilmgandhi 18:6a4db94011d3 3705
sahilmgandhi 18:6a4db94011d3 3706 #define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */
sahilmgandhi 18:6a4db94011d3 3707 #define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */
sahilmgandhi 18:6a4db94011d3 3708
sahilmgandhi 18:6a4db94011d3 3709 #define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */
sahilmgandhi 18:6a4db94011d3 3710 #define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */
sahilmgandhi 18:6a4db94011d3 3711
sahilmgandhi 18:6a4db94011d3 3712 #define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */
sahilmgandhi 18:6a4db94011d3 3713 #define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */
sahilmgandhi 18:6a4db94011d3 3714
sahilmgandhi 18:6a4db94011d3 3715 #define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */
sahilmgandhi 18:6a4db94011d3 3716 #define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */
sahilmgandhi 18:6a4db94011d3 3717
sahilmgandhi 18:6a4db94011d3 3718 #define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */
sahilmgandhi 18:6a4db94011d3 3719 #define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */
sahilmgandhi 18:6a4db94011d3 3720
sahilmgandhi 18:6a4db94011d3 3721 #define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */
sahilmgandhi 18:6a4db94011d3 3722 #define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */
sahilmgandhi 18:6a4db94011d3 3723
sahilmgandhi 18:6a4db94011d3 3724 #define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */
sahilmgandhi 18:6a4db94011d3 3725 #define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */
sahilmgandhi 18:6a4db94011d3 3726
sahilmgandhi 18:6a4db94011d3 3727 #define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */
sahilmgandhi 18:6a4db94011d3 3728 #define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */
sahilmgandhi 18:6a4db94011d3 3729
sahilmgandhi 18:6a4db94011d3 3730 #define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */
sahilmgandhi 18:6a4db94011d3 3731 #define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */
sahilmgandhi 18:6a4db94011d3 3732
sahilmgandhi 18:6a4db94011d3 3733 #define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */
sahilmgandhi 18:6a4db94011d3 3734 #define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */
sahilmgandhi 18:6a4db94011d3 3735
sahilmgandhi 18:6a4db94011d3 3736 #define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */
sahilmgandhi 18:6a4db94011d3 3737 #define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */
sahilmgandhi 18:6a4db94011d3 3738
sahilmgandhi 18:6a4db94011d3 3739 #define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */
sahilmgandhi 18:6a4db94011d3 3740 #define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */
sahilmgandhi 18:6a4db94011d3 3741
sahilmgandhi 18:6a4db94011d3 3742 #define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */
sahilmgandhi 18:6a4db94011d3 3743 #define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */
sahilmgandhi 18:6a4db94011d3 3744
sahilmgandhi 18:6a4db94011d3 3745 /**@}*/ /* FMC_CONST */
sahilmgandhi 18:6a4db94011d3 3746 /**@}*/ /* end of FMC register group */
sahilmgandhi 18:6a4db94011d3 3747
sahilmgandhi 18:6a4db94011d3 3748
sahilmgandhi 18:6a4db94011d3 3749 /*---------------------- General Purpose Input/Output Controller -------------------------*/
sahilmgandhi 18:6a4db94011d3 3750 /**
sahilmgandhi 18:6a4db94011d3 3751 @addtogroup GPIO General Purpose Input/Output Controller(GPIO)
sahilmgandhi 18:6a4db94011d3 3752 Memory Mapped Structure for GPIO Controller
sahilmgandhi 18:6a4db94011d3 3753 @{ */
sahilmgandhi 18:6a4db94011d3 3754
sahilmgandhi 18:6a4db94011d3 3755
sahilmgandhi 18:6a4db94011d3 3756 typedef struct
sahilmgandhi 18:6a4db94011d3 3757 {
sahilmgandhi 18:6a4db94011d3 3758
sahilmgandhi 18:6a4db94011d3 3759
sahilmgandhi 18:6a4db94011d3 3760
sahilmgandhi 18:6a4db94011d3 3761 /**
sahilmgandhi 18:6a4db94011d3 3762 * @var GPIO_T::MODE
sahilmgandhi 18:6a4db94011d3 3763 * Offset: 0x00/0x40/0x80/0xC0/0x100/0x140 Port A-F I/O Mode Control
sahilmgandhi 18:6a4db94011d3 3764 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3765 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3766 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3767 * |[2n+1:2n]|MODEn |Port A-F I/O Pin[n] Mode Control
sahilmgandhi 18:6a4db94011d3 3768 * | | |Determine each I/O mode of Px.n pins.
sahilmgandhi 18:6a4db94011d3 3769 * | | |00 = Px.n is in Input mode.
sahilmgandhi 18:6a4db94011d3 3770 * | | |01 = Px.n is in Push-pull Output mode.
sahilmgandhi 18:6a4db94011d3 3771 * | | |10 = Px.n is in Open-drain Output mode.
sahilmgandhi 18:6a4db94011d3 3772 * | | |11 = Px.n is in Quasi-bidirectional mode.
sahilmgandhi 18:6a4db94011d3 3773 * | | |Note1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).
sahilmgandhi 18:6a4db94011d3 3774 * | | |If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.
sahilmgandhi 18:6a4db94011d3 3775 * | | |If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be
sahilmgandhi 18:6a4db94011d3 3776 * | | |input mode after chip powered on.
sahilmgandhi 18:6a4db94011d3 3777 * | | |Note2:
sahilmgandhi 18:6a4db94011d3 3778 * | | |n=0~15 for port A/B/C/D.
sahilmgandhi 18:6a4db94011d3 3779 * | | |n=0~14 for port E.
sahilmgandhi 18:6a4db94011d3 3780 * | | |n=0~7 for port F.
sahilmgandhi 18:6a4db94011d3 3781 * @var GPIO_T::DINOFF
sahilmgandhi 18:6a4db94011d3 3782 * Offset: 0x04/0x44/0x84/0xC4/0x104/0x144 Port A-F Digital Input Path Disable Control
sahilmgandhi 18:6a4db94011d3 3783 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3784 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3785 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3786 * |[n+16] |DINOFFn |Port A-F Pin[n] Digital Input Path Disable Control
sahilmgandhi 18:6a4db94011d3 3787 * | | |Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled.
sahilmgandhi 18:6a4db94011d3 3788 * | | |If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
sahilmgandhi 18:6a4db94011d3 3789 * | | |0 = Px.n digital input path Enabled.
sahilmgandhi 18:6a4db94011d3 3790 * | | |1 = Px.n digital input path Disabled (digital input tied to low).
sahilmgandhi 18:6a4db94011d3 3791 * | | |Note:
sahilmgandhi 18:6a4db94011d3 3792 * | | |n=0~15 for port A/B/C/D.
sahilmgandhi 18:6a4db94011d3 3793 * | | |n=0~14 for port E.
sahilmgandhi 18:6a4db94011d3 3794 * | | |n=0~7 for port F.
sahilmgandhi 18:6a4db94011d3 3795 * @var GPIO_T::DOUT
sahilmgandhi 18:6a4db94011d3 3796 * Offset: 0x08/0x48/0x88/0xC8/0x108/0x148 Port A-F Data Output Value
sahilmgandhi 18:6a4db94011d3 3797 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3798 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3799 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3800 * |[n] |DOUTn |Port A-F Pin[n] Output Value
sahilmgandhi 18:6a4db94011d3 3801 * | | |Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
sahilmgandhi 18:6a4db94011d3 3802 * | | |0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
sahilmgandhi 18:6a4db94011d3 3803 * | | |1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode.
sahilmgandhi 18:6a4db94011d3 3804 * | | |Note:
sahilmgandhi 18:6a4db94011d3 3805 * | | |n=0~15 for port A/B/C/D.
sahilmgandhi 18:6a4db94011d3 3806 * | | |n=0~14 for port E.
sahilmgandhi 18:6a4db94011d3 3807 * | | |n=0~7 for port F.
sahilmgandhi 18:6a4db94011d3 3808 * @var GPIO_T::DATMSK
sahilmgandhi 18:6a4db94011d3 3809 * Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C Port A-F Data Output Write Mask
sahilmgandhi 18:6a4db94011d3 3810 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3811 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3812 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3813 * |[n] |DMASKn |Port A-F Pin[n] Data Output Write Mask
sahilmgandhi 18:6a4db94011d3 3814 * | | |These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit.
sahilmgandhi 18:6a4db94011d3 3815 * | | |When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected.
sahilmgandhi 18:6a4db94011d3 3816 * | | |If the write signal is masked, writing data to the protect bit is ignored.
sahilmgandhi 18:6a4db94011d3 3817 * | | |0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
sahilmgandhi 18:6a4db94011d3 3818 * | | |1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
sahilmgandhi 18:6a4db94011d3 3819 * | | |Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
sahilmgandhi 18:6a4db94011d3 3820 * | | |Note2:
sahilmgandhi 18:6a4db94011d3 3821 * | | |n=0~15 for port A/B/C/D.
sahilmgandhi 18:6a4db94011d3 3822 * | | |n=0~14 for port E.
sahilmgandhi 18:6a4db94011d3 3823 * | | |n=0~7 for port F.
sahilmgandhi 18:6a4db94011d3 3824 * @var GPIO_T::PIN
sahilmgandhi 18:6a4db94011d3 3825 * Offset: 0x10/0x50/0x90/0xD0/0x110/0x150 Port A-F Pin Value
sahilmgandhi 18:6a4db94011d3 3826 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3827 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3828 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3829 * |[n] |PINn |Port A-F Pin[n] Pin Value
sahilmgandhi 18:6a4db94011d3 3830 * | | |Each bit of the register reflects the actual status of the respective Px.n pin.
sahilmgandhi 18:6a4db94011d3 3831 * | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
sahilmgandhi 18:6a4db94011d3 3832 * | | |Note:
sahilmgandhi 18:6a4db94011d3 3833 * | | |n=0~15 for port A/B/C/D.
sahilmgandhi 18:6a4db94011d3 3834 * | | |n=0~14 for port E.
sahilmgandhi 18:6a4db94011d3 3835 * | | |n=0~7 for port F.
sahilmgandhi 18:6a4db94011d3 3836 * @var GPIO_T::DBEN
sahilmgandhi 18:6a4db94011d3 3837 * Offset: 0x14/0x54/0x94/0xD4/0x114/0x154 Port A-F De-Bounce Enable Control Register
sahilmgandhi 18:6a4db94011d3 3838 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3839 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3840 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3841 * |[n] |DBENn |Port A-F Pin[n] Input Signal De-Bounce Enable Bit
sahilmgandhi 18:6a4db94011d3 3842 * | | |The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit.
sahilmgandhi 18:6a4db94011d3 3843 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt.
sahilmgandhi 18:6a4db94011d3 3844 * | | |The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
sahilmgandhi 18:6a4db94011d3 3845 * | | |0 = Px.n de-bounce function Disabled.
sahilmgandhi 18:6a4db94011d3 3846 * | | |1 = Px.n de-bounce function Enabled.
sahilmgandhi 18:6a4db94011d3 3847 * | | |The de-bounce function is valid only for edge triggered interrupt.
sahilmgandhi 18:6a4db94011d3 3848 * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
sahilmgandhi 18:6a4db94011d3 3849 * | | |Note:
sahilmgandhi 18:6a4db94011d3 3850 * | | |n=0~15 for port A/B/C/D.
sahilmgandhi 18:6a4db94011d3 3851 * | | |n=0~14 for port E.
sahilmgandhi 18:6a4db94011d3 3852 * | | |n=0~7 for port F.
sahilmgandhi 18:6a4db94011d3 3853 * @var GPIO_T::INTTYPE
sahilmgandhi 18:6a4db94011d3 3854 * Offset: 0x18/0x58/0x98/0xD8/0x118/0x158 Port A-F Interrupt Trigger Type Control
sahilmgandhi 18:6a4db94011d3 3855 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3856 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3857 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3858 * |[n] |TYPEn |Port A-F Pin[n] Edge Or Level Detection Interrupt Trigger Type Control
sahilmgandhi 18:6a4db94011d3 3859 * | | |TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger.
sahilmgandhi 18:6a4db94011d3 3860 * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
sahilmgandhi 18:6a4db94011d3 3861 * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
sahilmgandhi 18:6a4db94011d3 3862 * | | |0 = Edge trigger interrupt.
sahilmgandhi 18:6a4db94011d3 3863 * | | |1 = Level trigger interrupt.
sahilmgandhi 18:6a4db94011d3 3864 * | | |If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]).
sahilmgandhi 18:6a4db94011d3 3865 * | | |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
sahilmgandhi 18:6a4db94011d3 3866 * | | |The de-bounce function is valid only for edge triggered interrupt.
sahilmgandhi 18:6a4db94011d3 3867 * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
sahilmgandhi 18:6a4db94011d3 3868 * | | |Note:
sahilmgandhi 18:6a4db94011d3 3869 * | | |n=0~15 for port A/B/C/D.
sahilmgandhi 18:6a4db94011d3 3870 * | | |n=0~14 for port E.
sahilmgandhi 18:6a4db94011d3 3871 * | | |n=0~7 for port F.
sahilmgandhi 18:6a4db94011d3 3872 * @var GPIO_T::INTEN
sahilmgandhi 18:6a4db94011d3 3873 * Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C Port A-F Interrupt Enable Control Register
sahilmgandhi 18:6a4db94011d3 3874 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3875 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3876 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3877 * |[n] |FLIENn |Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
sahilmgandhi 18:6a4db94011d3 3878 * | | |The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
sahilmgandhi 18:6a4db94011d3 3879 * | | |Set bit to 1 also enable the pin wake-up function.
sahilmgandhi 18:6a4db94011d3 3880 * | | |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
sahilmgandhi 18:6a4db94011d3 3881 * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
sahilmgandhi 18:6a4db94011d3 3882 * | | |If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
sahilmgandhi 18:6a4db94011d3 3883 * | | |0 = Px.n level low or high to low interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 3884 * | | |1 = Px.n level low or high to low interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 3885 * | | |Note:
sahilmgandhi 18:6a4db94011d3 3886 * | | |n=0~15 for port A/B/C/D.
sahilmgandhi 18:6a4db94011d3 3887 * | | |n=0~14 for port E.
sahilmgandhi 18:6a4db94011d3 3888 * | | |n=0~7 for port F.
sahilmgandhi 18:6a4db94011d3 3889 * @var GPIO_T::INTSRC
sahilmgandhi 18:6a4db94011d3 3890 * Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160 Port A-F Interrupt Source Flag
sahilmgandhi 18:6a4db94011d3 3891 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3892 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3893 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3894 * |[n] |INTSRCn |Port A-F Pin[n] Interrupt Source Flag
sahilmgandhi 18:6a4db94011d3 3895 * | | |Write Operation :
sahilmgandhi 18:6a4db94011d3 3896 * | | |0 = No action.
sahilmgandhi 18:6a4db94011d3 3897 * | | |1 = Clear the corresponding pending interrupt.
sahilmgandhi 18:6a4db94011d3 3898 * | | |Read Operation :
sahilmgandhi 18:6a4db94011d3 3899 * | | |0 = No interrupt at Px.n.
sahilmgandhi 18:6a4db94011d3 3900 * | | |1 = Px.n generates an interrupt.
sahilmgandhi 18:6a4db94011d3 3901 * | | |Note:
sahilmgandhi 18:6a4db94011d3 3902 * | | |n=0~15 for port A/B/C/D.
sahilmgandhi 18:6a4db94011d3 3903 * | | |n=0~14 for port E.
sahilmgandhi 18:6a4db94011d3 3904 * | | |n=0~7 for port F.
sahilmgandhi 18:6a4db94011d3 3905 * @var GPIO_T::SMTEN
sahilmgandhi 18:6a4db94011d3 3906 * Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164 Port A-F Input Schmitt Trigger Enable Register
sahilmgandhi 18:6a4db94011d3 3907 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3908 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3909 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3910 * |[n] |SMTENn |Port A-F Pin[n] Input Schmitt Trigger Enable Bit
sahilmgandhi 18:6a4db94011d3 3911 * | | |0 = Px.n input Schmitt trigger function Disabled.
sahilmgandhi 18:6a4db94011d3 3912 * | | |1 = Px.n input Schmitt trigger function Enabled.
sahilmgandhi 18:6a4db94011d3 3913 * | | |Note:
sahilmgandhi 18:6a4db94011d3 3914 * | | |n=0~15 for port A/B/C/D.
sahilmgandhi 18:6a4db94011d3 3915 * | | |n=0~14 for port E.
sahilmgandhi 18:6a4db94011d3 3916 * | | |n=0~7 for port F.
sahilmgandhi 18:6a4db94011d3 3917 * @var GPIO_T::SLEWCTL
sahilmgandhi 18:6a4db94011d3 3918 * Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168 Port A-F High Slew Rate Control Register
sahilmgandhi 18:6a4db94011d3 3919 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3920 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3921 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3922 * |[n] |HSRENn |Port A-F Pin[n] High Slew Rate Control
sahilmgandhi 18:6a4db94011d3 3923 * | | |0 = Px.n output with basic slew rate.
sahilmgandhi 18:6a4db94011d3 3924 * | | |1 = Px.n output with higher slew rate.
sahilmgandhi 18:6a4db94011d3 3925 * | | |Note:
sahilmgandhi 18:6a4db94011d3 3926 * | | |n=0~15 for port A/B/C/D.
sahilmgandhi 18:6a4db94011d3 3927 * | | |n=0~14 for port E.
sahilmgandhi 18:6a4db94011d3 3928 * | | |n=0~7 for port F.
sahilmgandhi 18:6a4db94011d3 3929 * @var GPIO_T::DRVCTL
sahilmgandhi 18:6a4db94011d3 3930 * Offset: 0x2C Port E High Drive Strength Control Register
sahilmgandhi 18:6a4db94011d3 3931 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3932 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3933 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3934 * |[n] |HDRVENn |Port E Pin[n] Driving Strength Control
sahilmgandhi 18:6a4db94011d3 3935 * | | |0 = Px.n output with basic driving strength.
sahilmgandhi 18:6a4db94011d3 3936 * | | |1 = Px.n output with high driving strength.
sahilmgandhi 18:6a4db94011d3 3937 * | | |Note:
sahilmgandhi 18:6a4db94011d3 3938 * | | |n=8,9..13 for port E.
sahilmgandhi 18:6a4db94011d3 3939 */
sahilmgandhi 18:6a4db94011d3 3940
sahilmgandhi 18:6a4db94011d3 3941 __IO uint32_t MODE; /* Offset: 0x00/0x40/0x80/0xC0/0x100/0x140 Port A-F I/O Mode Control */
sahilmgandhi 18:6a4db94011d3 3942 __IO uint32_t DINOFF; /* Offset: 0x04/0x44/0x84/0xC4/0x104/0x144 Port A-F Digital Input Path Disable Control */
sahilmgandhi 18:6a4db94011d3 3943 __IO uint32_t DOUT; /* Offset: 0x08/0x48/0x88/0xC8/0x108/0x148 Port A-F Data Output Value */
sahilmgandhi 18:6a4db94011d3 3944 __IO uint32_t DATMSK; /* Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C Port A-F Data Output Write Mask */
sahilmgandhi 18:6a4db94011d3 3945 __I uint32_t PIN; /* Offset: 0x10/0x50/0x90/0xD0/0x110/0x150 Port A-F Pin Value */
sahilmgandhi 18:6a4db94011d3 3946 __IO uint32_t DBEN; /* Offset: 0x14/0x54/0x94/0xD4/0x114/0x154 Port A-F De-Bounce Enable Control Register */
sahilmgandhi 18:6a4db94011d3 3947 __IO uint32_t INTTYPE; /* Offset: 0x18/0x58/0x98/0xD8/0x118/0x158 Port A-F Interrupt Trigger Type Control */
sahilmgandhi 18:6a4db94011d3 3948 __IO uint32_t INTEN; /* Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C Port A-F Interrupt Enable Control Register */
sahilmgandhi 18:6a4db94011d3 3949 __IO uint32_t INTSRC; /* Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160 Port A-F Interrupt Source Flag */
sahilmgandhi 18:6a4db94011d3 3950 __IO uint32_t SMTEN; /* Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164 Port A-F Input Schmitt Trigger Enable Register */
sahilmgandhi 18:6a4db94011d3 3951 __IO uint32_t SLEWCTL; /* Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168 Port A-F High Slew Rate Control Register */
sahilmgandhi 18:6a4db94011d3 3952 __IO uint32_t DRVCTL; /* Offset: 0x12C Port E High Drive Strength Control Register */
sahilmgandhi 18:6a4db94011d3 3953
sahilmgandhi 18:6a4db94011d3 3954 } GPIO_T;
sahilmgandhi 18:6a4db94011d3 3955
sahilmgandhi 18:6a4db94011d3 3956
sahilmgandhi 18:6a4db94011d3 3957
sahilmgandhi 18:6a4db94011d3 3958
sahilmgandhi 18:6a4db94011d3 3959 typedef struct
sahilmgandhi 18:6a4db94011d3 3960 {
sahilmgandhi 18:6a4db94011d3 3961
sahilmgandhi 18:6a4db94011d3 3962
sahilmgandhi 18:6a4db94011d3 3963
sahilmgandhi 18:6a4db94011d3 3964 /**
sahilmgandhi 18:6a4db94011d3 3965 * @var GPIO_DBCTL_T::DBCTL
sahilmgandhi 18:6a4db94011d3 3966 * Offset: 0x440 Interrupt De-bounce Control Register
sahilmgandhi 18:6a4db94011d3 3967 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3968 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 3969 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 3970 * |[3:0] |DBCLKSEL |De-Bounce Sampling Cycle Selection
sahilmgandhi 18:6a4db94011d3 3971 * | | |0000 = Sample interrupt input once per 1 clocks.
sahilmgandhi 18:6a4db94011d3 3972 * | | |0001 = Sample interrupt input once per 2 clocks.
sahilmgandhi 18:6a4db94011d3 3973 * | | |0010 = Sample interrupt input once per 4 clocks.
sahilmgandhi 18:6a4db94011d3 3974 * | | |0011 = Sample interrupt input once per 8 clocks.
sahilmgandhi 18:6a4db94011d3 3975 * | | |0100 = Sample interrupt input once per 16 clocks.
sahilmgandhi 18:6a4db94011d3 3976 * | | |0101 = Sample interrupt input once per 32 clocks.
sahilmgandhi 18:6a4db94011d3 3977 * | | |0110 = Sample interrupt input once per 64 clocks.
sahilmgandhi 18:6a4db94011d3 3978 * | | |0111 = Sample interrupt input once per 128 clocks.
sahilmgandhi 18:6a4db94011d3 3979 * | | |1000 = Sample interrupt input once per 256 clocks.
sahilmgandhi 18:6a4db94011d3 3980 * | | |1001 = Sample interrupt input once per 2*256 clocks.
sahilmgandhi 18:6a4db94011d3 3981 * | | |1010 = Sample interrupt input once per 4*256 clocks.
sahilmgandhi 18:6a4db94011d3 3982 * | | |1011 = Sample interrupt input once per 8*256 clocks.
sahilmgandhi 18:6a4db94011d3 3983 * | | |1100 = Sample interrupt input once per 16*256 clocks.
sahilmgandhi 18:6a4db94011d3 3984 * | | |1101 = Sample interrupt input once per 32*256 clocks.
sahilmgandhi 18:6a4db94011d3 3985 * | | |1110 = Sample interrupt input once per 64*256 clocks.
sahilmgandhi 18:6a4db94011d3 3986 * | | |1111 = Sample interrupt input once per 128*256 clocks.
sahilmgandhi 18:6a4db94011d3 3987 * |[4] |DBCLKSRC |De-Bounce Counter Clock Source Selection
sahilmgandhi 18:6a4db94011d3 3988 * | | |0 = De-bounce counter clock source is the HCLK.
sahilmgandhi 18:6a4db94011d3 3989 * | | |1 = De-bounce counter clock source is the internal 10 kHz internal low speed oscillator.
sahilmgandhi 18:6a4db94011d3 3990 * |[5] |ICLKON |Interrupt Clock On Mode
sahilmgandhi 18:6a4db94011d3 3991 * | | |0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1.
sahilmgandhi 18:6a4db94011d3 3992 * | | |1 = All I/O pins edge detection circuit is always active after reset.
sahilmgandhi 18:6a4db94011d3 3993 * | | |Note: It is recommended to disable this bit to save system power if no special application concern.
sahilmgandhi 18:6a4db94011d3 3994 */
sahilmgandhi 18:6a4db94011d3 3995
sahilmgandhi 18:6a4db94011d3 3996 __IO uint32_t DBCTL; /* Offset: 0x440 Interrupt De-bounce Control Register */
sahilmgandhi 18:6a4db94011d3 3997
sahilmgandhi 18:6a4db94011d3 3998 } GPIO_DBCTL_T;
sahilmgandhi 18:6a4db94011d3 3999
sahilmgandhi 18:6a4db94011d3 4000
sahilmgandhi 18:6a4db94011d3 4001
sahilmgandhi 18:6a4db94011d3 4002
sahilmgandhi 18:6a4db94011d3 4003 /**
sahilmgandhi 18:6a4db94011d3 4004 @addtogroup GPIO_CONST GPIO Bit Field Definition
sahilmgandhi 18:6a4db94011d3 4005 Constant Definitions for GPIO Controller
sahilmgandhi 18:6a4db94011d3 4006 @{ */
sahilmgandhi 18:6a4db94011d3 4007
sahilmgandhi 18:6a4db94011d3 4008 #define GPIO_MODE_MODE0_Pos (0) /*!< GPIO_T::MODE: MODE0 Position */
sahilmgandhi 18:6a4db94011d3 4009 #define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) /*!< GPIO_T::MODE: MODE0 Mask */
sahilmgandhi 18:6a4db94011d3 4010
sahilmgandhi 18:6a4db94011d3 4011 #define GPIO_MODE_MODE1_Pos (2) /*!< GPIO_T::MODE: MODE1 Position */
sahilmgandhi 18:6a4db94011d3 4012 #define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) /*!< GPIO_T::MODE: MODE1 Mask */
sahilmgandhi 18:6a4db94011d3 4013
sahilmgandhi 18:6a4db94011d3 4014 #define GPIO_MODE_MODE2_Pos (4) /*!< GPIO_T::MODE: MODE2 Position */
sahilmgandhi 18:6a4db94011d3 4015 #define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) /*!< GPIO_T::MODE: MODE2 Mask */
sahilmgandhi 18:6a4db94011d3 4016
sahilmgandhi 18:6a4db94011d3 4017 #define GPIO_MODE_MODE3_Pos (6) /*!< GPIO_T::MODE: MODE3 Position */
sahilmgandhi 18:6a4db94011d3 4018 #define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) /*!< GPIO_T::MODE: MODE3 Mask */
sahilmgandhi 18:6a4db94011d3 4019
sahilmgandhi 18:6a4db94011d3 4020 #define GPIO_MODE_MODE4_Pos (8) /*!< GPIO_T::MODE: MODE4 Position */
sahilmgandhi 18:6a4db94011d3 4021 #define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) /*!< GPIO_T::MODE: MODE4 Mask */
sahilmgandhi 18:6a4db94011d3 4022
sahilmgandhi 18:6a4db94011d3 4023 #define GPIO_MODE_MODE5_Pos (10) /*!< GPIO_T::MODE: MODE5 Position */
sahilmgandhi 18:6a4db94011d3 4024 #define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) /*!< GPIO_T::MODE: MODE5 Mask */
sahilmgandhi 18:6a4db94011d3 4025
sahilmgandhi 18:6a4db94011d3 4026 #define GPIO_MODE_MODE6_Pos (12) /*!< GPIO_T::MODE: MODE6 Position */
sahilmgandhi 18:6a4db94011d3 4027 #define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) /*!< GPIO_T::MODE: MODE6 Mask */
sahilmgandhi 18:6a4db94011d3 4028
sahilmgandhi 18:6a4db94011d3 4029 #define GPIO_MODE_MODE7_Pos (14) /*!< GPIO_T::MODE: MODE7 Position */
sahilmgandhi 18:6a4db94011d3 4030 #define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) /*!< GPIO_T::MODE: MODE7 Mask */
sahilmgandhi 18:6a4db94011d3 4031
sahilmgandhi 18:6a4db94011d3 4032 #define GPIO_MODE_MODE8_Pos (16) /*!< GPIO_T::MODE: MODE8 Position */
sahilmgandhi 18:6a4db94011d3 4033 #define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) /*!< GPIO_T::MODE: MODE8 Mask */
sahilmgandhi 18:6a4db94011d3 4034
sahilmgandhi 18:6a4db94011d3 4035 #define GPIO_MODE_MODE9_Pos (18) /*!< GPIO_T::MODE: MODE9 Position */
sahilmgandhi 18:6a4db94011d3 4036 #define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) /*!< GPIO_T::MODE: MODE9 Mask */
sahilmgandhi 18:6a4db94011d3 4037
sahilmgandhi 18:6a4db94011d3 4038 #define GPIO_MODE_MODE10_Pos (20) /*!< GPIO_T::MODE: MODE10 Position */
sahilmgandhi 18:6a4db94011d3 4039 #define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) /*!< GPIO_T::MODE: MODE10 Mask */
sahilmgandhi 18:6a4db94011d3 4040
sahilmgandhi 18:6a4db94011d3 4041 #define GPIO_MODE_MODE11_Pos (22) /*!< GPIO_T::MODE: MODE11 Position */
sahilmgandhi 18:6a4db94011d3 4042 #define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) /*!< GPIO_T::MODE: MODE11 Mask */
sahilmgandhi 18:6a4db94011d3 4043
sahilmgandhi 18:6a4db94011d3 4044 #define GPIO_MODE_MODE12_Pos (24) /*!< GPIO_T::MODE: MODE12 Position */
sahilmgandhi 18:6a4db94011d3 4045 #define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) /*!< GPIO_T::MODE: MODE12 Mask */
sahilmgandhi 18:6a4db94011d3 4046
sahilmgandhi 18:6a4db94011d3 4047 #define GPIO_MODE_MODE13_Pos (26) /*!< GPIO_T::MODE: MODE13 Position */
sahilmgandhi 18:6a4db94011d3 4048 #define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) /*!< GPIO_T::MODE: MODE13 Mask */
sahilmgandhi 18:6a4db94011d3 4049
sahilmgandhi 18:6a4db94011d3 4050 #define GPIO_MODE_MODE14_Pos (28) /*!< GPIO_T::MODE: MODE14 Position */
sahilmgandhi 18:6a4db94011d3 4051 #define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) /*!< GPIO_T::MODE: MODE14 Mask */
sahilmgandhi 18:6a4db94011d3 4052
sahilmgandhi 18:6a4db94011d3 4053 #define GPIO_MODE_MODE15_Pos (30) /*!< GPIO_T::MODE: MODE15 Position */
sahilmgandhi 18:6a4db94011d3 4054 #define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) /*!< GPIO_T::MODE: MODE15 Mask */
sahilmgandhi 18:6a4db94011d3 4055
sahilmgandhi 18:6a4db94011d3 4056 #define GPIO_DINOFF_DINOFF0_Pos (16) /*!< GPIO_T::DINOFF: DINOFF0 Position */
sahilmgandhi 18:6a4db94011d3 4057 #define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) /*!< GPIO_T::DINOFF: DINOFF0 Mask */
sahilmgandhi 18:6a4db94011d3 4058
sahilmgandhi 18:6a4db94011d3 4059 #define GPIO_DINOFF_DINOFF1_Pos (17) /*!< GPIO_T::DINOFF: DINOFF1 Position */
sahilmgandhi 18:6a4db94011d3 4060 #define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) /*!< GPIO_T::DINOFF: DINOFF1 Mask */
sahilmgandhi 18:6a4db94011d3 4061
sahilmgandhi 18:6a4db94011d3 4062 #define GPIO_DINOFF_DINOFF2_Pos (18) /*!< GPIO_T::DINOFF: DINOFF2 Position */
sahilmgandhi 18:6a4db94011d3 4063 #define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) /*!< GPIO_T::DINOFF: DINOFF2 Mask */
sahilmgandhi 18:6a4db94011d3 4064
sahilmgandhi 18:6a4db94011d3 4065 #define GPIO_DINOFF_DINOFF3_Pos (19) /*!< GPIO_T::DINOFF: DINOFF3 Position */
sahilmgandhi 18:6a4db94011d3 4066 #define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) /*!< GPIO_T::DINOFF: DINOFF3 Mask */
sahilmgandhi 18:6a4db94011d3 4067
sahilmgandhi 18:6a4db94011d3 4068 #define GPIO_DINOFF_DINOFF4_Pos (20) /*!< GPIO_T::DINOFF: DINOFF4 Position */
sahilmgandhi 18:6a4db94011d3 4069 #define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) /*!< GPIO_T::DINOFF: DINOFF4 Mask */
sahilmgandhi 18:6a4db94011d3 4070
sahilmgandhi 18:6a4db94011d3 4071 #define GPIO_DINOFF_DINOFF5_Pos (21) /*!< GPIO_T::DINOFF: DINOFF5 Position */
sahilmgandhi 18:6a4db94011d3 4072 #define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) /*!< GPIO_T::DINOFF: DINOFF5 Mask */
sahilmgandhi 18:6a4db94011d3 4073
sahilmgandhi 18:6a4db94011d3 4074 #define GPIO_DINOFF_DINOFF6_Pos (22) /*!< GPIO_T::DINOFF: DINOFF6 Position */
sahilmgandhi 18:6a4db94011d3 4075 #define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) /*!< GPIO_T::DINOFF: DINOFF6 Mask */
sahilmgandhi 18:6a4db94011d3 4076
sahilmgandhi 18:6a4db94011d3 4077 #define GPIO_DINOFF_DINOFF7_Pos (23) /*!< GPIO_T::DINOFF: DINOFF7 Position */
sahilmgandhi 18:6a4db94011d3 4078 #define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) /*!< GPIO_T::DINOFF: DINOFF7 Mask */
sahilmgandhi 18:6a4db94011d3 4079
sahilmgandhi 18:6a4db94011d3 4080 #define GPIO_DINOFF_DINOFF8_Pos (24) /*!< GPIO_T::DINOFF: DINOFF8 Position */
sahilmgandhi 18:6a4db94011d3 4081 #define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) /*!< GPIO_T::DINOFF: DINOFF8 Mask */
sahilmgandhi 18:6a4db94011d3 4082
sahilmgandhi 18:6a4db94011d3 4083 #define GPIO_DINOFF_DINOFF9_Pos (25) /*!< GPIO_T::DINOFF: DINOFF9 Position */
sahilmgandhi 18:6a4db94011d3 4084 #define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) /*!< GPIO_T::DINOFF: DINOFF9 Mask */
sahilmgandhi 18:6a4db94011d3 4085
sahilmgandhi 18:6a4db94011d3 4086 #define GPIO_DINOFF_DINOFF10_Pos (26) /*!< GPIO_T::DINOFF: DINOFF10 Position */
sahilmgandhi 18:6a4db94011d3 4087 #define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) /*!< GPIO_T::DINOFF: DINOFF10 Mask */
sahilmgandhi 18:6a4db94011d3 4088
sahilmgandhi 18:6a4db94011d3 4089 #define GPIO_DINOFF_DINOFF11_Pos (27) /*!< GPIO_T::DINOFF: DINOFF11 Position */
sahilmgandhi 18:6a4db94011d3 4090 #define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) /*!< GPIO_T::DINOFF: DINOFF11 Mask */
sahilmgandhi 18:6a4db94011d3 4091
sahilmgandhi 18:6a4db94011d3 4092 #define GPIO_DINOFF_DINOFF12_Pos (28) /*!< GPIO_T::DINOFF: DINOFF12 Position */
sahilmgandhi 18:6a4db94011d3 4093 #define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) /*!< GPIO_T::DINOFF: DINOFF12 Mask */
sahilmgandhi 18:6a4db94011d3 4094
sahilmgandhi 18:6a4db94011d3 4095 #define GPIO_DINOFF_DINOFF13_Pos (29) /*!< GPIO_T::DINOFF: DINOFF13 Position */
sahilmgandhi 18:6a4db94011d3 4096 #define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) /*!< GPIO_T::DINOFF: DINOFF13 Mask */
sahilmgandhi 18:6a4db94011d3 4097
sahilmgandhi 18:6a4db94011d3 4098 #define GPIO_DINOFF_DINOFF14_Pos (30) /*!< GPIO_T::DINOFF: DINOFF14 Position */
sahilmgandhi 18:6a4db94011d3 4099 #define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) /*!< GPIO_T::DINOFF: DINOFF14 Mask */
sahilmgandhi 18:6a4db94011d3 4100
sahilmgandhi 18:6a4db94011d3 4101 #define GPIO_DINOFF_DINOFF15_Pos (31) /*!< GPIO_T::DINOFF: DINOFF15 Position */
sahilmgandhi 18:6a4db94011d3 4102 #define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) /*!< GPIO_T::DINOFF: DINOFF15 Mask */
sahilmgandhi 18:6a4db94011d3 4103
sahilmgandhi 18:6a4db94011d3 4104 #define GPIO_DOUT_DOUT0_Pos (0) /*!< GPIO_T::DOUT: DOUT0 Position */
sahilmgandhi 18:6a4db94011d3 4105 #define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) /*!< GPIO_T::DOUT: DOUT0 Mask */
sahilmgandhi 18:6a4db94011d3 4106
sahilmgandhi 18:6a4db94011d3 4107 #define GPIO_DOUT_DOUT1_Pos (1) /*!< GPIO_T::DOUT: DOUT1 Position */
sahilmgandhi 18:6a4db94011d3 4108 #define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) /*!< GPIO_T::DOUT: DOUT1 Mask */
sahilmgandhi 18:6a4db94011d3 4109
sahilmgandhi 18:6a4db94011d3 4110 #define GPIO_DOUT_DOUT2_Pos (2) /*!< GPIO_T::DOUT: DOUT2 Position */
sahilmgandhi 18:6a4db94011d3 4111 #define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) /*!< GPIO_T::DOUT: DOUT2 Mask */
sahilmgandhi 18:6a4db94011d3 4112
sahilmgandhi 18:6a4db94011d3 4113 #define GPIO_DOUT_DOUT3_Pos (3) /*!< GPIO_T::DOUT: DOUT3 Position */
sahilmgandhi 18:6a4db94011d3 4114 #define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) /*!< GPIO_T::DOUT: DOUT3 Mask */
sahilmgandhi 18:6a4db94011d3 4115
sahilmgandhi 18:6a4db94011d3 4116 #define GPIO_DOUT_DOUT4_Pos (4) /*!< GPIO_T::DOUT: DOUT4 Position */
sahilmgandhi 18:6a4db94011d3 4117 #define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) /*!< GPIO_T::DOUT: DOUT4 Mask */
sahilmgandhi 18:6a4db94011d3 4118
sahilmgandhi 18:6a4db94011d3 4119 #define GPIO_DOUT_DOUT5_Pos (5) /*!< GPIO_T::DOUT: DOUT5 Position */
sahilmgandhi 18:6a4db94011d3 4120 #define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) /*!< GPIO_T::DOUT: DOUT5 Mask */
sahilmgandhi 18:6a4db94011d3 4121
sahilmgandhi 18:6a4db94011d3 4122 #define GPIO_DOUT_DOUT6_Pos (6) /*!< GPIO_T::DOUT: DOUT6 Position */
sahilmgandhi 18:6a4db94011d3 4123 #define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) /*!< GPIO_T::DOUT: DOUT6 Mask */
sahilmgandhi 18:6a4db94011d3 4124
sahilmgandhi 18:6a4db94011d3 4125 #define GPIO_DOUT_DOUT7_Pos (7) /*!< GPIO_T::DOUT: DOUT7 Position */
sahilmgandhi 18:6a4db94011d3 4126 #define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) /*!< GPIO_T::DOUT: DOUT7 Mask */
sahilmgandhi 18:6a4db94011d3 4127
sahilmgandhi 18:6a4db94011d3 4128 #define GPIO_DOUT_DOUT8_Pos (8) /*!< GPIO_T::DOUT: DOUT8 Position */
sahilmgandhi 18:6a4db94011d3 4129 #define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) /*!< GPIO_T::DOUT: DOUT8 Mask */
sahilmgandhi 18:6a4db94011d3 4130
sahilmgandhi 18:6a4db94011d3 4131 #define GPIO_DOUT_DOUT9_Pos (9) /*!< GPIO_T::DOUT: DOUT9 Position */
sahilmgandhi 18:6a4db94011d3 4132 #define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) /*!< GPIO_T::DOUT: DOUT9 Mask */
sahilmgandhi 18:6a4db94011d3 4133
sahilmgandhi 18:6a4db94011d3 4134 #define GPIO_DOUT_DOUT10_Pos (10) /*!< GPIO_T::DOUT: DOUT10 Position */
sahilmgandhi 18:6a4db94011d3 4135 #define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) /*!< GPIO_T::DOUT: DOUT10 Mask */
sahilmgandhi 18:6a4db94011d3 4136
sahilmgandhi 18:6a4db94011d3 4137 #define GPIO_DOUT_DOUT11_Pos (11) /*!< GPIO_T::DOUT: DOUT11 Position */
sahilmgandhi 18:6a4db94011d3 4138 #define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) /*!< GPIO_T::DOUT: DOUT11 Mask */
sahilmgandhi 18:6a4db94011d3 4139
sahilmgandhi 18:6a4db94011d3 4140 #define GPIO_DOUT_DOUT12_Pos (12) /*!< GPIO_T::DOUT: DOUT12 Position */
sahilmgandhi 18:6a4db94011d3 4141 #define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) /*!< GPIO_T::DOUT: DOUT12 Mask */
sahilmgandhi 18:6a4db94011d3 4142
sahilmgandhi 18:6a4db94011d3 4143 #define GPIO_DOUT_DOUT13_Pos (13) /*!< GPIO_T::DOUT: DOUT13 Position */
sahilmgandhi 18:6a4db94011d3 4144 #define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) /*!< GPIO_T::DOUT: DOUT13 Mask */
sahilmgandhi 18:6a4db94011d3 4145
sahilmgandhi 18:6a4db94011d3 4146 #define GPIO_DOUT_DOUT14_Pos (14) /*!< GPIO_T::DOUT: DOUT14 Position */
sahilmgandhi 18:6a4db94011d3 4147 #define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) /*!< GPIO_T::DOUT: DOUT14 Mask */
sahilmgandhi 18:6a4db94011d3 4148
sahilmgandhi 18:6a4db94011d3 4149 #define GPIO_DOUT_DOUT15_Pos (15) /*!< GPIO_T::DOUT: DOUT15 Position */
sahilmgandhi 18:6a4db94011d3 4150 #define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) /*!< GPIO_T::DOUT: DOUT15 Mask */
sahilmgandhi 18:6a4db94011d3 4151
sahilmgandhi 18:6a4db94011d3 4152 #define GPIO_DATMSK_DMASK0_Pos (0) /*!< GPIO_T::DATMSK: DMASK0 Position */
sahilmgandhi 18:6a4db94011d3 4153 #define GPIO_DATMSK_DMASK0_Msk (0x1ul << GPIO_DATMSK_DMASK0_Pos) /*!< GPIO_T::DATMSK: DMASK0 Mask */
sahilmgandhi 18:6a4db94011d3 4154
sahilmgandhi 18:6a4db94011d3 4155 #define GPIO_DATMSK_DMASK1_Pos (1) /*!< GPIO_T::DATMSK: DMASK1 Position */
sahilmgandhi 18:6a4db94011d3 4156 #define GPIO_DATMSK_DMASK1_Msk (0x1ul << GPIO_DATMSK_DMASK1_Pos) /*!< GPIO_T::DATMSK: DMASK1 Mask */
sahilmgandhi 18:6a4db94011d3 4157
sahilmgandhi 18:6a4db94011d3 4158 #define GPIO_DATMSK_DMASK2_Pos (2) /*!< GPIO_T::DATMSK: DMASK2 Position */
sahilmgandhi 18:6a4db94011d3 4159 #define GPIO_DATMSK_DMASK2_Msk (0x1ul << GPIO_DATMSK_DMASK2_Pos) /*!< GPIO_T::DATMSK: DMASK2 Mask */
sahilmgandhi 18:6a4db94011d3 4160
sahilmgandhi 18:6a4db94011d3 4161 #define GPIO_DATMSK_DMASK3_Pos (3) /*!< GPIO_T::DATMSK: DMASK3 Position */
sahilmgandhi 18:6a4db94011d3 4162 #define GPIO_DATMSK_DMASK3_Msk (0x1ul << GPIO_DATMSK_DMASK3_Pos) /*!< GPIO_T::DATMSK: DMASK3 Mask */
sahilmgandhi 18:6a4db94011d3 4163
sahilmgandhi 18:6a4db94011d3 4164 #define GPIO_DATMSK_DMASK4_Pos (4) /*!< GPIO_T::DATMSK: DMASK4 Position */
sahilmgandhi 18:6a4db94011d3 4165 #define GPIO_DATMSK_DMASK4_Msk (0x1ul << GPIO_DATMSK_DMASK4_Pos) /*!< GPIO_T::DATMSK: DMASK4 Mask */
sahilmgandhi 18:6a4db94011d3 4166
sahilmgandhi 18:6a4db94011d3 4167 #define GPIO_DATMSK_DMASK5_Pos (5) /*!< GPIO_T::DATMSK: DMASK5 Position */
sahilmgandhi 18:6a4db94011d3 4168 #define GPIO_DATMSK_DMASK5_Msk (0x1ul << GPIO_DATMSK_DMASK5_Pos) /*!< GPIO_T::DATMSK: DMASK5 Mask */
sahilmgandhi 18:6a4db94011d3 4169
sahilmgandhi 18:6a4db94011d3 4170 #define GPIO_DATMSK_DMASK6_Pos (6) /*!< GPIO_T::DATMSK: DMASK6 Position */
sahilmgandhi 18:6a4db94011d3 4171 #define GPIO_DATMSK_DMASK6_Msk (0x1ul << GPIO_DATMSK_DMASK6_Pos) /*!< GPIO_T::DATMSK: DMASK6 Mask */
sahilmgandhi 18:6a4db94011d3 4172
sahilmgandhi 18:6a4db94011d3 4173 #define GPIO_DATMSK_DMASK7_Pos (7) /*!< GPIO_T::DATMSK: DMASK7 Position */
sahilmgandhi 18:6a4db94011d3 4174 #define GPIO_DATMSK_DMASK7_Msk (0x1ul << GPIO_DATMSK_DMASK7_Pos) /*!< GPIO_T::DATMSK: DMASK7 Mask */
sahilmgandhi 18:6a4db94011d3 4175
sahilmgandhi 18:6a4db94011d3 4176 #define GPIO_DATMSK_DMASK8_Pos (8) /*!< GPIO_T::DATMSK: DMASK8 Position */
sahilmgandhi 18:6a4db94011d3 4177 #define GPIO_DATMSK_DMASK8_Msk (0x1ul << GPIO_DATMSK_DMASK8_Pos) /*!< GPIO_T::DATMSK: DMASK8 Mask */
sahilmgandhi 18:6a4db94011d3 4178
sahilmgandhi 18:6a4db94011d3 4179 #define GPIO_DATMSK_DMASK9_Pos (9) /*!< GPIO_T::DATMSK: DMASK9 Position */
sahilmgandhi 18:6a4db94011d3 4180 #define GPIO_DATMSK_DMASK9_Msk (0x1ul << GPIO_DATMSK_DMASK9_Pos) /*!< GPIO_T::DATMSK: DMASK9 Mask */
sahilmgandhi 18:6a4db94011d3 4181
sahilmgandhi 18:6a4db94011d3 4182 #define GPIO_DATMSK_DMASK10_Pos (10) /*!< GPIO_T::DATMSK: DMASK10 Position */
sahilmgandhi 18:6a4db94011d3 4183 #define GPIO_DATMSK_DMASK10_Msk (0x1ul << GPIO_DATMSK_DMASK10_Pos) /*!< GPIO_T::DATMSK: DMASK10 Mask */
sahilmgandhi 18:6a4db94011d3 4184
sahilmgandhi 18:6a4db94011d3 4185 #define GPIO_DATMSK_DMASK11_Pos (11) /*!< GPIO_T::DATMSK: DMASK11 Position */
sahilmgandhi 18:6a4db94011d3 4186 #define GPIO_DATMSK_DMASK11_Msk (0x1ul << GPIO_DATMSK_DMASK11_Pos) /*!< GPIO_T::DATMSK: DMASK11 Mask */
sahilmgandhi 18:6a4db94011d3 4187
sahilmgandhi 18:6a4db94011d3 4188 #define GPIO_DATMSK_DMASK12_Pos (12) /*!< GPIO_T::DATMSK: DMASK12 Position */
sahilmgandhi 18:6a4db94011d3 4189 #define GPIO_DATMSK_DMASK12_Msk (0x1ul << GPIO_DATMSK_DMASK12_Pos) /*!< GPIO_T::DATMSK: DMASK12 Mask */
sahilmgandhi 18:6a4db94011d3 4190
sahilmgandhi 18:6a4db94011d3 4191 #define GPIO_DATMSK_DMASK13_Pos (13) /*!< GPIO_T::DATMSK: DMASK13 Position */
sahilmgandhi 18:6a4db94011d3 4192 #define GPIO_DATMSK_DMASK13_Msk (0x1ul << GPIO_DATMSK_DMASK13_Pos) /*!< GPIO_T::DATMSK: DMASK13 Mask */
sahilmgandhi 18:6a4db94011d3 4193
sahilmgandhi 18:6a4db94011d3 4194 #define GPIO_DATMSK_DMASK14_Pos (14) /*!< GPIO_T::DATMSK: DMASK14 Position */
sahilmgandhi 18:6a4db94011d3 4195 #define GPIO_DATMSK_DMASK14_Msk (0x1ul << GPIO_DATMSK_DMASK14_Pos) /*!< GPIO_T::DATMSK: DMASK14 Mask */
sahilmgandhi 18:6a4db94011d3 4196
sahilmgandhi 18:6a4db94011d3 4197 #define GPIO_DATMSK_DMASK15_Pos (15) /*!< GPIO_T::DATMSK: DMASK15 Position */
sahilmgandhi 18:6a4db94011d3 4198 #define GPIO_DATMSK_DMASK15_Msk (0x1ul << GPIO_DATMSK_DMASK15_Pos) /*!< GPIO_T::DATMSK: DMASK15 Mask */
sahilmgandhi 18:6a4db94011d3 4199
sahilmgandhi 18:6a4db94011d3 4200 #define GPIO_PIN_PIN0_Pos (0) /*!< GPIO_T::PIN: PIN0 Position */
sahilmgandhi 18:6a4db94011d3 4201 #define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) /*!< GPIO_T::PIN: PIN0 Mask */
sahilmgandhi 18:6a4db94011d3 4202
sahilmgandhi 18:6a4db94011d3 4203 #define GPIO_PIN_PIN1_Pos (1) /*!< GPIO_T::PIN: PIN1 Position */
sahilmgandhi 18:6a4db94011d3 4204 #define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) /*!< GPIO_T::PIN: PIN1 Mask */
sahilmgandhi 18:6a4db94011d3 4205
sahilmgandhi 18:6a4db94011d3 4206 #define GPIO_PIN_PIN2_Pos (2) /*!< GPIO_T::PIN: PIN2 Position */
sahilmgandhi 18:6a4db94011d3 4207 #define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) /*!< GPIO_T::PIN: PIN2 Mask */
sahilmgandhi 18:6a4db94011d3 4208
sahilmgandhi 18:6a4db94011d3 4209 #define GPIO_PIN_PIN3_Pos (3) /*!< GPIO_T::PIN: PIN3 Position */
sahilmgandhi 18:6a4db94011d3 4210 #define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) /*!< GPIO_T::PIN: PIN3 Mask */
sahilmgandhi 18:6a4db94011d3 4211
sahilmgandhi 18:6a4db94011d3 4212 #define GPIO_PIN_PIN4_Pos (4) /*!< GPIO_T::PIN: PIN4 Position */
sahilmgandhi 18:6a4db94011d3 4213 #define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) /*!< GPIO_T::PIN: PIN4 Mask */
sahilmgandhi 18:6a4db94011d3 4214
sahilmgandhi 18:6a4db94011d3 4215 #define GPIO_PIN_PIN5_Pos (5) /*!< GPIO_T::PIN: PIN5 Position */
sahilmgandhi 18:6a4db94011d3 4216 #define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) /*!< GPIO_T::PIN: PIN5 Mask */
sahilmgandhi 18:6a4db94011d3 4217
sahilmgandhi 18:6a4db94011d3 4218 #define GPIO_PIN_PIN6_Pos (6) /*!< GPIO_T::PIN: PIN6 Position */
sahilmgandhi 18:6a4db94011d3 4219 #define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) /*!< GPIO_T::PIN: PIN6 Mask */
sahilmgandhi 18:6a4db94011d3 4220
sahilmgandhi 18:6a4db94011d3 4221 #define GPIO_PIN_PIN7_Pos (7) /*!< GPIO_T::PIN: PIN7 Position */
sahilmgandhi 18:6a4db94011d3 4222 #define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) /*!< GPIO_T::PIN: PIN7 Mask */
sahilmgandhi 18:6a4db94011d3 4223
sahilmgandhi 18:6a4db94011d3 4224 #define GPIO_PIN_PIN8_Pos (8) /*!< GPIO_T::PIN: PIN8 Position */
sahilmgandhi 18:6a4db94011d3 4225 #define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) /*!< GPIO_T::PIN: PIN8 Mask */
sahilmgandhi 18:6a4db94011d3 4226
sahilmgandhi 18:6a4db94011d3 4227 #define GPIO_PIN_PIN9_Pos (9) /*!< GPIO_T::PIN: PIN9 Position */
sahilmgandhi 18:6a4db94011d3 4228 #define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) /*!< GPIO_T::PIN: PIN9 Mask */
sahilmgandhi 18:6a4db94011d3 4229
sahilmgandhi 18:6a4db94011d3 4230 #define GPIO_PIN_PIN10_Pos (10) /*!< GPIO_T::PIN: PIN10 Position */
sahilmgandhi 18:6a4db94011d3 4231 #define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) /*!< GPIO_T::PIN: PIN10 Mask */
sahilmgandhi 18:6a4db94011d3 4232
sahilmgandhi 18:6a4db94011d3 4233 #define GPIO_PIN_PIN11_Pos (11) /*!< GPIO_T::PIN: PIN11 Position */
sahilmgandhi 18:6a4db94011d3 4234 #define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) /*!< GPIO_T::PIN: PIN11 Mask */
sahilmgandhi 18:6a4db94011d3 4235
sahilmgandhi 18:6a4db94011d3 4236 #define GPIO_PIN_PIN12_Pos (12) /*!< GPIO_T::PIN: PIN12 Position */
sahilmgandhi 18:6a4db94011d3 4237 #define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) /*!< GPIO_T::PIN: PIN12 Mask */
sahilmgandhi 18:6a4db94011d3 4238
sahilmgandhi 18:6a4db94011d3 4239 #define GPIO_PIN_PIN13_Pos (13) /*!< GPIO_T::PIN: PIN13 Position */
sahilmgandhi 18:6a4db94011d3 4240 #define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) /*!< GPIO_T::PIN: PIN13 Mask */
sahilmgandhi 18:6a4db94011d3 4241
sahilmgandhi 18:6a4db94011d3 4242 #define GPIO_PIN_PIN14_Pos (14) /*!< GPIO_T::PIN: PIN14 Position */
sahilmgandhi 18:6a4db94011d3 4243 #define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) /*!< GPIO_T::PIN: PIN14 Mask */
sahilmgandhi 18:6a4db94011d3 4244
sahilmgandhi 18:6a4db94011d3 4245 #define GPIO_PIN_PIN15_Pos (15) /*!< GPIO_T::PIN: PIN15 Position */
sahilmgandhi 18:6a4db94011d3 4246 #define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) /*!< GPIO_T::PIN: PIN15 Mask */
sahilmgandhi 18:6a4db94011d3 4247
sahilmgandhi 18:6a4db94011d3 4248 #define GPIO_DBEN_DBEN0_Pos (0) /*!< GPIO_T::DBEN: DBEN0 Position */
sahilmgandhi 18:6a4db94011d3 4249 #define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) /*!< GPIO_T::DBEN: DBEN0 Mask */
sahilmgandhi 18:6a4db94011d3 4250
sahilmgandhi 18:6a4db94011d3 4251 #define GPIO_DBEN_DBEN1_Pos (1) /*!< GPIO_T::DBEN: DBEN1 Position */
sahilmgandhi 18:6a4db94011d3 4252 #define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) /*!< GPIO_T::DBEN: DBEN1 Mask */
sahilmgandhi 18:6a4db94011d3 4253
sahilmgandhi 18:6a4db94011d3 4254 #define GPIO_DBEN_DBEN2_Pos (2) /*!< GPIO_T::DBEN: DBEN2 Position */
sahilmgandhi 18:6a4db94011d3 4255 #define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) /*!< GPIO_T::DBEN: DBEN2 Mask */
sahilmgandhi 18:6a4db94011d3 4256
sahilmgandhi 18:6a4db94011d3 4257 #define GPIO_DBEN_DBEN3_Pos (3) /*!< GPIO_T::DBEN: DBEN3 Position */
sahilmgandhi 18:6a4db94011d3 4258 #define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) /*!< GPIO_T::DBEN: DBEN3 Mask */
sahilmgandhi 18:6a4db94011d3 4259
sahilmgandhi 18:6a4db94011d3 4260 #define GPIO_DBEN_DBEN4_Pos (4) /*!< GPIO_T::DBEN: DBEN4 Position */
sahilmgandhi 18:6a4db94011d3 4261 #define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) /*!< GPIO_T::DBEN: DBEN4 Mask */
sahilmgandhi 18:6a4db94011d3 4262
sahilmgandhi 18:6a4db94011d3 4263 #define GPIO_DBEN_DBEN5_Pos (5) /*!< GPIO_T::DBEN: DBEN5 Position */
sahilmgandhi 18:6a4db94011d3 4264 #define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) /*!< GPIO_T::DBEN: DBEN5 Mask */
sahilmgandhi 18:6a4db94011d3 4265
sahilmgandhi 18:6a4db94011d3 4266 #define GPIO_DBEN_DBEN6_Pos (6) /*!< GPIO_T::DBEN: DBEN6 Position */
sahilmgandhi 18:6a4db94011d3 4267 #define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) /*!< GPIO_T::DBEN: DBEN6 Mask */
sahilmgandhi 18:6a4db94011d3 4268
sahilmgandhi 18:6a4db94011d3 4269 #define GPIO_DBEN_DBEN7_Pos (7) /*!< GPIO_T::DBEN: DBEN7 Position */
sahilmgandhi 18:6a4db94011d3 4270 #define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) /*!< GPIO_T::DBEN: DBEN7 Mask */
sahilmgandhi 18:6a4db94011d3 4271
sahilmgandhi 18:6a4db94011d3 4272 #define GPIO_DBEN_DBEN8_Pos (8) /*!< GPIO_T::DBEN: DBEN8 Position */
sahilmgandhi 18:6a4db94011d3 4273 #define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) /*!< GPIO_T::DBEN: DBEN8 Mask */
sahilmgandhi 18:6a4db94011d3 4274
sahilmgandhi 18:6a4db94011d3 4275 #define GPIO_DBEN_DBEN9_Pos (9) /*!< GPIO_T::DBEN: DBEN9 Position */
sahilmgandhi 18:6a4db94011d3 4276 #define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) /*!< GPIO_T::DBEN: DBEN9 Mask */
sahilmgandhi 18:6a4db94011d3 4277
sahilmgandhi 18:6a4db94011d3 4278 #define GPIO_DBEN_DBEN10_Pos (10) /*!< GPIO_T::DBEN: DBEN10 Position */
sahilmgandhi 18:6a4db94011d3 4279 #define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) /*!< GPIO_T::DBEN: DBEN10 Mask */
sahilmgandhi 18:6a4db94011d3 4280
sahilmgandhi 18:6a4db94011d3 4281 #define GPIO_DBEN_DBEN11_Pos (11) /*!< GPIO_T::DBEN: DBEN11 Position */
sahilmgandhi 18:6a4db94011d3 4282 #define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) /*!< GPIO_T::DBEN: DBEN11 Mask */
sahilmgandhi 18:6a4db94011d3 4283
sahilmgandhi 18:6a4db94011d3 4284 #define GPIO_DBEN_DBEN12_Pos (12) /*!< GPIO_T::DBEN: DBEN12 Position */
sahilmgandhi 18:6a4db94011d3 4285 #define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) /*!< GPIO_T::DBEN: DBEN12 Mask */
sahilmgandhi 18:6a4db94011d3 4286
sahilmgandhi 18:6a4db94011d3 4287 #define GPIO_DBEN_DBEN13_Pos (13) /*!< GPIO_T::DBEN: DBEN13 Position */
sahilmgandhi 18:6a4db94011d3 4288 #define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) /*!< GPIO_T::DBEN: DBEN13 Mask */
sahilmgandhi 18:6a4db94011d3 4289
sahilmgandhi 18:6a4db94011d3 4290 #define GPIO_DBEN_DBEN14_Pos (14) /*!< GPIO_T::DBEN: DBEN14 Position */
sahilmgandhi 18:6a4db94011d3 4291 #define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) /*!< GPIO_T::DBEN: DBEN14 Mask */
sahilmgandhi 18:6a4db94011d3 4292
sahilmgandhi 18:6a4db94011d3 4293 #define GPIO_DBEN_DBEN15_Pos (15) /*!< GPIO_T::DBEN: DBEN15 Position */
sahilmgandhi 18:6a4db94011d3 4294 #define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) /*!< GPIO_T::DBEN: DBEN15 Mask */
sahilmgandhi 18:6a4db94011d3 4295
sahilmgandhi 18:6a4db94011d3 4296 #define GPIO_INTTYPE_TYPE0_Pos (0) /*!< GPIO_T::INTTYPE: TYPE0 Position */
sahilmgandhi 18:6a4db94011d3 4297 #define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) /*!< GPIO_T::INTTYPE: TYPE0 Mask */
sahilmgandhi 18:6a4db94011d3 4298
sahilmgandhi 18:6a4db94011d3 4299 #define GPIO_INTTYPE_TYPE1_Pos (1) /*!< GPIO_T::INTTYPE: TYPE1 Position */
sahilmgandhi 18:6a4db94011d3 4300 #define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) /*!< GPIO_T::INTTYPE: TYPE1 Mask */
sahilmgandhi 18:6a4db94011d3 4301
sahilmgandhi 18:6a4db94011d3 4302 #define GPIO_INTTYPE_TYPE2_Pos (2) /*!< GPIO_T::INTTYPE: TYPE2 Position */
sahilmgandhi 18:6a4db94011d3 4303 #define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) /*!< GPIO_T::INTTYPE: TYPE2 Mask */
sahilmgandhi 18:6a4db94011d3 4304
sahilmgandhi 18:6a4db94011d3 4305 #define GPIO_INTTYPE_TYPE3_Pos (3) /*!< GPIO_T::INTTYPE: TYPE3 Position */
sahilmgandhi 18:6a4db94011d3 4306 #define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) /*!< GPIO_T::INTTYPE: TYPE3 Mask */
sahilmgandhi 18:6a4db94011d3 4307
sahilmgandhi 18:6a4db94011d3 4308 #define GPIO_INTTYPE_TYPE4_Pos (4) /*!< GPIO_T::INTTYPE: TYPE4 Position */
sahilmgandhi 18:6a4db94011d3 4309 #define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) /*!< GPIO_T::INTTYPE: TYPE4 Mask */
sahilmgandhi 18:6a4db94011d3 4310
sahilmgandhi 18:6a4db94011d3 4311 #define GPIO_INTTYPE_TYPE5_Pos (5) /*!< GPIO_T::INTTYPE: TYPE5 Position */
sahilmgandhi 18:6a4db94011d3 4312 #define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) /*!< GPIO_T::INTTYPE: TYPE5 Mask */
sahilmgandhi 18:6a4db94011d3 4313
sahilmgandhi 18:6a4db94011d3 4314 #define GPIO_INTTYPE_TYPE6_Pos (6) /*!< GPIO_T::INTTYPE: TYPE6 Position */
sahilmgandhi 18:6a4db94011d3 4315 #define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) /*!< GPIO_T::INTTYPE: TYPE6 Mask */
sahilmgandhi 18:6a4db94011d3 4316
sahilmgandhi 18:6a4db94011d3 4317 #define GPIO_INTTYPE_TYPE7_Pos (7) /*!< GPIO_T::INTTYPE: TYPE7 Position */
sahilmgandhi 18:6a4db94011d3 4318 #define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) /*!< GPIO_T::INTTYPE: TYPE7 Mask */
sahilmgandhi 18:6a4db94011d3 4319
sahilmgandhi 18:6a4db94011d3 4320 #define GPIO_INTTYPE_TYPE8_Pos (8) /*!< GPIO_T::INTTYPE: TYPE8 Position */
sahilmgandhi 18:6a4db94011d3 4321 #define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) /*!< GPIO_T::INTTYPE: TYPE8 Mask */
sahilmgandhi 18:6a4db94011d3 4322
sahilmgandhi 18:6a4db94011d3 4323 #define GPIO_INTTYPE_TYPE9_Pos (9) /*!< GPIO_T::INTTYPE: TYPE9 Position */
sahilmgandhi 18:6a4db94011d3 4324 #define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) /*!< GPIO_T::INTTYPE: TYPE9 Mask */
sahilmgandhi 18:6a4db94011d3 4325
sahilmgandhi 18:6a4db94011d3 4326 #define GPIO_INTTYPE_TYPE10_Pos (10) /*!< GPIO_T::INTTYPE: TYPE10 Position */
sahilmgandhi 18:6a4db94011d3 4327 #define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) /*!< GPIO_T::INTTYPE: TYPE10 Mask */
sahilmgandhi 18:6a4db94011d3 4328
sahilmgandhi 18:6a4db94011d3 4329 #define GPIO_INTTYPE_TYPE11_Pos (11) /*!< GPIO_T::INTTYPE: TYPE11 Position */
sahilmgandhi 18:6a4db94011d3 4330 #define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) /*!< GPIO_T::INTTYPE: TYPE11 Mask */
sahilmgandhi 18:6a4db94011d3 4331
sahilmgandhi 18:6a4db94011d3 4332 #define GPIO_INTTYPE_TYPE12_Pos (12) /*!< GPIO_T::INTTYPE: TYPE12 Position */
sahilmgandhi 18:6a4db94011d3 4333 #define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) /*!< GPIO_T::INTTYPE: TYPE12 Mask */
sahilmgandhi 18:6a4db94011d3 4334
sahilmgandhi 18:6a4db94011d3 4335 #define GPIO_INTTYPE_TYPE13_Pos (13) /*!< GPIO_T::INTTYPE: TYPE13 Position */
sahilmgandhi 18:6a4db94011d3 4336 #define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) /*!< GPIO_T::INTTYPE: TYPE13 Mask */
sahilmgandhi 18:6a4db94011d3 4337
sahilmgandhi 18:6a4db94011d3 4338 #define GPIO_INTTYPE_TYPE14_Pos (14) /*!< GPIO_T::INTTYPE: TYPE14 Position */
sahilmgandhi 18:6a4db94011d3 4339 #define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) /*!< GPIO_T::INTTYPE: TYPE14 Mask */
sahilmgandhi 18:6a4db94011d3 4340
sahilmgandhi 18:6a4db94011d3 4341 #define GPIO_INTTYPE_TYPE15_Pos (15) /*!< GPIO_T::INTTYPE: TYPE15 Position */
sahilmgandhi 18:6a4db94011d3 4342 #define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) /*!< GPIO_T::INTTYPE: TYPE15 Mask */
sahilmgandhi 18:6a4db94011d3 4343
sahilmgandhi 18:6a4db94011d3 4344 #define GPIO_INTEN_FLIEN0_Pos (0) /*!< GPIO_T::INTEN: FLIEN0 Position */
sahilmgandhi 18:6a4db94011d3 4345 #define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) /*!< GPIO_T::INTEN: FLIEN0 Mask */
sahilmgandhi 18:6a4db94011d3 4346
sahilmgandhi 18:6a4db94011d3 4347 #define GPIO_INTEN_FLIEN1_Pos (1) /*!< GPIO_T::INTEN: FLIEN1 Position */
sahilmgandhi 18:6a4db94011d3 4348 #define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) /*!< GPIO_T::INTEN: FLIEN1 Mask */
sahilmgandhi 18:6a4db94011d3 4349
sahilmgandhi 18:6a4db94011d3 4350 #define GPIO_INTEN_FLIEN2_Pos (2) /*!< GPIO_T::INTEN: FLIEN2 Position */
sahilmgandhi 18:6a4db94011d3 4351 #define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) /*!< GPIO_T::INTEN: FLIEN2 Mask */
sahilmgandhi 18:6a4db94011d3 4352
sahilmgandhi 18:6a4db94011d3 4353 #define GPIO_INTEN_FLIEN3_Pos (3) /*!< GPIO_T::INTEN: FLIEN3 Position */
sahilmgandhi 18:6a4db94011d3 4354 #define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) /*!< GPIO_T::INTEN: FLIEN3 Mask */
sahilmgandhi 18:6a4db94011d3 4355
sahilmgandhi 18:6a4db94011d3 4356 #define GPIO_INTEN_FLIEN4_Pos (4) /*!< GPIO_T::INTEN: FLIEN4 Position */
sahilmgandhi 18:6a4db94011d3 4357 #define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) /*!< GPIO_T::INTEN: FLIEN4 Mask */
sahilmgandhi 18:6a4db94011d3 4358
sahilmgandhi 18:6a4db94011d3 4359 #define GPIO_INTEN_FLIEN5_Pos (5) /*!< GPIO_T::INTEN: FLIEN5 Position */
sahilmgandhi 18:6a4db94011d3 4360 #define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) /*!< GPIO_T::INTEN: FLIEN5 Mask */
sahilmgandhi 18:6a4db94011d3 4361
sahilmgandhi 18:6a4db94011d3 4362 #define GPIO_INTEN_FLIEN6_Pos (6) /*!< GPIO_T::INTEN: FLIEN6 Position */
sahilmgandhi 18:6a4db94011d3 4363 #define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) /*!< GPIO_T::INTEN: FLIEN6 Mask */
sahilmgandhi 18:6a4db94011d3 4364
sahilmgandhi 18:6a4db94011d3 4365 #define GPIO_INTEN_FLIEN7_Pos (7) /*!< GPIO_T::INTEN: FLIEN7 Position */
sahilmgandhi 18:6a4db94011d3 4366 #define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) /*!< GPIO_T::INTEN: FLIEN7 Mask */
sahilmgandhi 18:6a4db94011d3 4367
sahilmgandhi 18:6a4db94011d3 4368 #define GPIO_INTEN_FLIEN8_Pos (8) /*!< GPIO_T::INTEN: FLIEN8 Position */
sahilmgandhi 18:6a4db94011d3 4369 #define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) /*!< GPIO_T::INTEN: FLIEN8 Mask */
sahilmgandhi 18:6a4db94011d3 4370
sahilmgandhi 18:6a4db94011d3 4371 #define GPIO_INTEN_FLIEN9_Pos (9) /*!< GPIO_T::INTEN: FLIEN9 Position */
sahilmgandhi 18:6a4db94011d3 4372 #define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) /*!< GPIO_T::INTEN: FLIEN9 Mask */
sahilmgandhi 18:6a4db94011d3 4373
sahilmgandhi 18:6a4db94011d3 4374 #define GPIO_INTEN_FLIEN10_Pos (10) /*!< GPIO_T::INTEN: FLIEN10 Position */
sahilmgandhi 18:6a4db94011d3 4375 #define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) /*!< GPIO_T::INTEN: FLIEN10 Mask */
sahilmgandhi 18:6a4db94011d3 4376
sahilmgandhi 18:6a4db94011d3 4377 #define GPIO_INTEN_FLIEN11_Pos (11) /*!< GPIO_T::INTEN: FLIEN11 Position */
sahilmgandhi 18:6a4db94011d3 4378 #define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) /*!< GPIO_T::INTEN: FLIEN11 Mask */
sahilmgandhi 18:6a4db94011d3 4379
sahilmgandhi 18:6a4db94011d3 4380 #define GPIO_INTEN_FLIEN12_Pos (12) /*!< GPIO_T::INTEN: FLIEN12 Position */
sahilmgandhi 18:6a4db94011d3 4381 #define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) /*!< GPIO_T::INTEN: FLIEN12 Mask */
sahilmgandhi 18:6a4db94011d3 4382
sahilmgandhi 18:6a4db94011d3 4383 #define GPIO_INTEN_FLIEN13_Pos (13) /*!< GPIO_T::INTEN: FLIEN13 Position */
sahilmgandhi 18:6a4db94011d3 4384 #define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) /*!< GPIO_T::INTEN: FLIEN13 Mask */
sahilmgandhi 18:6a4db94011d3 4385
sahilmgandhi 18:6a4db94011d3 4386 #define GPIO_INTEN_FLIEN14_Pos (14) /*!< GPIO_T::INTEN: FLIEN14 Position */
sahilmgandhi 18:6a4db94011d3 4387 #define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) /*!< GPIO_T::INTEN: FLIEN14 Mask */
sahilmgandhi 18:6a4db94011d3 4388
sahilmgandhi 18:6a4db94011d3 4389 #define GPIO_INTEN_FLIEN15_Pos (15) /*!< GPIO_T::INTEN: FLIEN15 Position */
sahilmgandhi 18:6a4db94011d3 4390 #define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) /*!< GPIO_T::INTEN: FLIEN15 Mask */
sahilmgandhi 18:6a4db94011d3 4391
sahilmgandhi 18:6a4db94011d3 4392 #define GPIO_INTEN_RHIEN0_Pos (16) /*!< GPIO_T::INTEN: RHIEN0 Position */
sahilmgandhi 18:6a4db94011d3 4393 #define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) /*!< GPIO_T::INTEN: RHIEN0 Mask */
sahilmgandhi 18:6a4db94011d3 4394
sahilmgandhi 18:6a4db94011d3 4395 #define GPIO_INTEN_RHIEN1_Pos (17) /*!< GPIO_T::INTEN: RHIEN1 Position */
sahilmgandhi 18:6a4db94011d3 4396 #define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) /*!< GPIO_T::INTEN: RHIEN1 Mask */
sahilmgandhi 18:6a4db94011d3 4397
sahilmgandhi 18:6a4db94011d3 4398 #define GPIO_INTEN_RHIEN2_Pos (18) /*!< GPIO_T::INTEN: RHIEN2 Position */
sahilmgandhi 18:6a4db94011d3 4399 #define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) /*!< GPIO_T::INTEN: RHIEN2 Mask */
sahilmgandhi 18:6a4db94011d3 4400
sahilmgandhi 18:6a4db94011d3 4401 #define GPIO_INTEN_RHIEN3_Pos (19) /*!< GPIO_T::INTEN: RHIEN3 Position */
sahilmgandhi 18:6a4db94011d3 4402 #define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) /*!< GPIO_T::INTEN: RHIEN3 Mask */
sahilmgandhi 18:6a4db94011d3 4403
sahilmgandhi 18:6a4db94011d3 4404 #define GPIO_INTEN_RHIEN4_Pos (20) /*!< GPIO_T::INTEN: RHIEN4 Position */
sahilmgandhi 18:6a4db94011d3 4405 #define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) /*!< GPIO_T::INTEN: RHIEN4 Mask */
sahilmgandhi 18:6a4db94011d3 4406
sahilmgandhi 18:6a4db94011d3 4407 #define GPIO_INTEN_RHIEN5_Pos (21) /*!< GPIO_T::INTEN: RHIEN5 Position */
sahilmgandhi 18:6a4db94011d3 4408 #define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) /*!< GPIO_T::INTEN: RHIEN5 Mask */
sahilmgandhi 18:6a4db94011d3 4409
sahilmgandhi 18:6a4db94011d3 4410 #define GPIO_INTEN_RHIEN6_Pos (22) /*!< GPIO_T::INTEN: RHIEN6 Position */
sahilmgandhi 18:6a4db94011d3 4411 #define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) /*!< GPIO_T::INTEN: RHIEN6 Mask */
sahilmgandhi 18:6a4db94011d3 4412
sahilmgandhi 18:6a4db94011d3 4413 #define GPIO_INTEN_RHIEN7_Pos (23) /*!< GPIO_T::INTEN: RHIEN7 Position */
sahilmgandhi 18:6a4db94011d3 4414 #define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) /*!< GPIO_T::INTEN: RHIEN7 Mask */
sahilmgandhi 18:6a4db94011d3 4415
sahilmgandhi 18:6a4db94011d3 4416 #define GPIO_INTEN_RHIEN8_Pos (24) /*!< GPIO_T::INTEN: RHIEN8 Position */
sahilmgandhi 18:6a4db94011d3 4417 #define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) /*!< GPIO_T::INTEN: RHIEN8 Mask */
sahilmgandhi 18:6a4db94011d3 4418
sahilmgandhi 18:6a4db94011d3 4419 #define GPIO_INTEN_RHIEN9_Pos (25) /*!< GPIO_T::INTEN: RHIEN9 Position */
sahilmgandhi 18:6a4db94011d3 4420 #define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) /*!< GPIO_T::INTEN: RHIEN9 Mask */
sahilmgandhi 18:6a4db94011d3 4421
sahilmgandhi 18:6a4db94011d3 4422 #define GPIO_INTEN_RHIEN10_Pos (26) /*!< GPIO_T::INTEN: RHIEN10 Position */
sahilmgandhi 18:6a4db94011d3 4423 #define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) /*!< GPIO_T::INTEN: RHIEN10 Mask */
sahilmgandhi 18:6a4db94011d3 4424
sahilmgandhi 18:6a4db94011d3 4425 #define GPIO_INTEN_RHIEN11_Pos (27) /*!< GPIO_T::INTEN: RHIEN11 Position */
sahilmgandhi 18:6a4db94011d3 4426 #define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) /*!< GPIO_T::INTEN: RHIEN11 Mask */
sahilmgandhi 18:6a4db94011d3 4427
sahilmgandhi 18:6a4db94011d3 4428 #define GPIO_INTEN_RHIEN12_Pos (28) /*!< GPIO_T::INTEN: RHIEN12 Position */
sahilmgandhi 18:6a4db94011d3 4429 #define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) /*!< GPIO_T::INTEN: RHIEN12 Mask */
sahilmgandhi 18:6a4db94011d3 4430
sahilmgandhi 18:6a4db94011d3 4431 #define GPIO_INTEN_RHIEN13_Pos (29) /*!< GPIO_T::INTEN: RHIEN13 Position */
sahilmgandhi 18:6a4db94011d3 4432 #define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) /*!< GPIO_T::INTEN: RHIEN13 Mask */
sahilmgandhi 18:6a4db94011d3 4433
sahilmgandhi 18:6a4db94011d3 4434 #define GPIO_INTEN_RHIEN14_Pos (30) /*!< GPIO_T::INTEN: RHIEN14 Position */
sahilmgandhi 18:6a4db94011d3 4435 #define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) /*!< GPIO_T::INTEN: RHIEN14 Mask */
sahilmgandhi 18:6a4db94011d3 4436
sahilmgandhi 18:6a4db94011d3 4437 #define GPIO_INTEN_RHIEN15_Pos (31) /*!< GPIO_T::INTEN: RHIEN15 Position */
sahilmgandhi 18:6a4db94011d3 4438 #define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) /*!< GPIO_T::INTEN: RHIEN15 Mask */
sahilmgandhi 18:6a4db94011d3 4439
sahilmgandhi 18:6a4db94011d3 4440 #define GPIO_INTSRC_INTSRC0_Pos (0) /*!< GPIO_T::INTSRC: INTSRC0 Position */
sahilmgandhi 18:6a4db94011d3 4441 #define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) /*!< GPIO_T::INTSRC: INTSRC0 Mask */
sahilmgandhi 18:6a4db94011d3 4442
sahilmgandhi 18:6a4db94011d3 4443 #define GPIO_INTSRC_INTSRC1_Pos (1) /*!< GPIO_T::INTSRC: INTSRC1 Position */
sahilmgandhi 18:6a4db94011d3 4444 #define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) /*!< GPIO_T::INTSRC: INTSRC1 Mask */
sahilmgandhi 18:6a4db94011d3 4445
sahilmgandhi 18:6a4db94011d3 4446 #define GPIO_INTSRC_INTSRC2_Pos (2) /*!< GPIO_T::INTSRC: INTSRC2 Position */
sahilmgandhi 18:6a4db94011d3 4447 #define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) /*!< GPIO_T::INTSRC: INTSRC2 Mask */
sahilmgandhi 18:6a4db94011d3 4448
sahilmgandhi 18:6a4db94011d3 4449 #define GPIO_INTSRC_INTSRC3_Pos (3) /*!< GPIO_T::INTSRC: INTSRC3 Position */
sahilmgandhi 18:6a4db94011d3 4450 #define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) /*!< GPIO_T::INTSRC: INTSRC3 Mask */
sahilmgandhi 18:6a4db94011d3 4451
sahilmgandhi 18:6a4db94011d3 4452 #define GPIO_INTSRC_INTSRC4_Pos (4) /*!< GPIO_T::INTSRC: INTSRC4 Position */
sahilmgandhi 18:6a4db94011d3 4453 #define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) /*!< GPIO_T::INTSRC: INTSRC4 Mask */
sahilmgandhi 18:6a4db94011d3 4454
sahilmgandhi 18:6a4db94011d3 4455 #define GPIO_INTSRC_INTSRC5_Pos (5) /*!< GPIO_T::INTSRC: INTSRC5 Position */
sahilmgandhi 18:6a4db94011d3 4456 #define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) /*!< GPIO_T::INTSRC: INTSRC5 Mask */
sahilmgandhi 18:6a4db94011d3 4457
sahilmgandhi 18:6a4db94011d3 4458 #define GPIO_INTSRC_INTSRC6_Pos (6) /*!< GPIO_T::INTSRC: INTSRC6 Position */
sahilmgandhi 18:6a4db94011d3 4459 #define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) /*!< GPIO_T::INTSRC: INTSRC6 Mask */
sahilmgandhi 18:6a4db94011d3 4460
sahilmgandhi 18:6a4db94011d3 4461 #define GPIO_INTSRC_INTSRC7_Pos (7) /*!< GPIO_T::INTSRC: INTSRC7 Position */
sahilmgandhi 18:6a4db94011d3 4462 #define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) /*!< GPIO_T::INTSRC: INTSRC7 Mask */
sahilmgandhi 18:6a4db94011d3 4463
sahilmgandhi 18:6a4db94011d3 4464 #define GPIO_INTSRC_INTSRC8_Pos (8) /*!< GPIO_T::INTSRC: INTSRC8 Position */
sahilmgandhi 18:6a4db94011d3 4465 #define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) /*!< GPIO_T::INTSRC: INTSRC8 Mask */
sahilmgandhi 18:6a4db94011d3 4466
sahilmgandhi 18:6a4db94011d3 4467 #define GPIO_INTSRC_INTSRC9_Pos (9) /*!< GPIO_T::INTSRC: INTSRC9 Position */
sahilmgandhi 18:6a4db94011d3 4468 #define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) /*!< GPIO_T::INTSRC: INTSRC9 Mask */
sahilmgandhi 18:6a4db94011d3 4469
sahilmgandhi 18:6a4db94011d3 4470 #define GPIO_INTSRC_INTSRC10_Pos (10) /*!< GPIO_T::INTSRC: INTSRC10 Position */
sahilmgandhi 18:6a4db94011d3 4471 #define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) /*!< GPIO_T::INTSRC: INTSRC10 Mask */
sahilmgandhi 18:6a4db94011d3 4472
sahilmgandhi 18:6a4db94011d3 4473 #define GPIO_INTSRC_INTSRC11_Pos (11) /*!< GPIO_T::INTSRC: INTSRC11 Position */
sahilmgandhi 18:6a4db94011d3 4474 #define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) /*!< GPIO_T::INTSRC: INTSRC11 Mask */
sahilmgandhi 18:6a4db94011d3 4475
sahilmgandhi 18:6a4db94011d3 4476 #define GPIO_INTSRC_INTSRC12_Pos (12) /*!< GPIO_T::INTSRC: INTSRC12 Position */
sahilmgandhi 18:6a4db94011d3 4477 #define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) /*!< GPIO_T::INTSRC: INTSRC12 Mask */
sahilmgandhi 18:6a4db94011d3 4478
sahilmgandhi 18:6a4db94011d3 4479 #define GPIO_INTSRC_INTSRC13_Pos (13) /*!< GPIO_T::INTSRC: INTSRC13 Position */
sahilmgandhi 18:6a4db94011d3 4480 #define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) /*!< GPIO_T::INTSRC: INTSRC13 Mask */
sahilmgandhi 18:6a4db94011d3 4481
sahilmgandhi 18:6a4db94011d3 4482 #define GPIO_INTSRC_INTSRC14_Pos (14) /*!< GPIO_T::INTSRC: INTSRC14 Position */
sahilmgandhi 18:6a4db94011d3 4483 #define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) /*!< GPIO_T::INTSRC: INTSRC14 Mask */
sahilmgandhi 18:6a4db94011d3 4484
sahilmgandhi 18:6a4db94011d3 4485 #define GPIO_INTSRC_INTSRC15_Pos (15) /*!< GPIO_T::INTSRC: INTSRC15 Position */
sahilmgandhi 18:6a4db94011d3 4486 #define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) /*!< GPIO_T::INTSRC: INTSRC15 Mask */
sahilmgandhi 18:6a4db94011d3 4487
sahilmgandhi 18:6a4db94011d3 4488 #define GPIO_SMTEN_SMTEN0_Pos (0) /*!< GPIO_T::SMTEN: SMTEN0 Position */
sahilmgandhi 18:6a4db94011d3 4489 #define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) /*!< GPIO_T::SMTEN: SMTEN0 Mask */
sahilmgandhi 18:6a4db94011d3 4490
sahilmgandhi 18:6a4db94011d3 4491 #define GPIO_SMTEN_SMTEN1_Pos (1) /*!< GPIO_T::SMTEN: SMTEN1 Position */
sahilmgandhi 18:6a4db94011d3 4492 #define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) /*!< GPIO_T::SMTEN: SMTEN1 Mask */
sahilmgandhi 18:6a4db94011d3 4493
sahilmgandhi 18:6a4db94011d3 4494 #define GPIO_SMTEN_SMTEN2_Pos (2) /*!< GPIO_T::SMTEN: SMTEN2 Position */
sahilmgandhi 18:6a4db94011d3 4495 #define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) /*!< GPIO_T::SMTEN: SMTEN2 Mask */
sahilmgandhi 18:6a4db94011d3 4496
sahilmgandhi 18:6a4db94011d3 4497 #define GPIO_SMTEN_SMTEN3_Pos (3) /*!< GPIO_T::SMTEN: SMTEN3 Position */
sahilmgandhi 18:6a4db94011d3 4498 #define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) /*!< GPIO_T::SMTEN: SMTEN3 Mask */
sahilmgandhi 18:6a4db94011d3 4499
sahilmgandhi 18:6a4db94011d3 4500 #define GPIO_SMTEN_SMTEN4_Pos (4) /*!< GPIO_T::SMTEN: SMTEN4 Position */
sahilmgandhi 18:6a4db94011d3 4501 #define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) /*!< GPIO_T::SMTEN: SMTEN4 Mask */
sahilmgandhi 18:6a4db94011d3 4502
sahilmgandhi 18:6a4db94011d3 4503 #define GPIO_SMTEN_SMTEN5_Pos (5) /*!< GPIO_T::SMTEN: SMTEN5 Position */
sahilmgandhi 18:6a4db94011d3 4504 #define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) /*!< GPIO_T::SMTEN: SMTEN5 Mask */
sahilmgandhi 18:6a4db94011d3 4505
sahilmgandhi 18:6a4db94011d3 4506 #define GPIO_SMTEN_SMTEN6_Pos (6) /*!< GPIO_T::SMTEN: SMTEN6 Position */
sahilmgandhi 18:6a4db94011d3 4507 #define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) /*!< GPIO_T::SMTEN: SMTEN6 Mask */
sahilmgandhi 18:6a4db94011d3 4508
sahilmgandhi 18:6a4db94011d3 4509 #define GPIO_SMTEN_SMTEN7_Pos (7) /*!< GPIO_T::SMTEN: SMTEN7 Position */
sahilmgandhi 18:6a4db94011d3 4510 #define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) /*!< GPIO_T::SMTEN: SMTEN7 Mask */
sahilmgandhi 18:6a4db94011d3 4511
sahilmgandhi 18:6a4db94011d3 4512 #define GPIO_SMTEN_SMTEN8_Pos (8) /*!< GPIO_T::SMTEN: SMTEN8 Position */
sahilmgandhi 18:6a4db94011d3 4513 #define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) /*!< GPIO_T::SMTEN: SMTEN8 Mask */
sahilmgandhi 18:6a4db94011d3 4514
sahilmgandhi 18:6a4db94011d3 4515 #define GPIO_SMTEN_SMTEN9_Pos (9) /*!< GPIO_T::SMTEN: SMTEN9 Position */
sahilmgandhi 18:6a4db94011d3 4516 #define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) /*!< GPIO_T::SMTEN: SMTEN9 Mask */
sahilmgandhi 18:6a4db94011d3 4517
sahilmgandhi 18:6a4db94011d3 4518 #define GPIO_SMTEN_SMTEN10_Pos (10) /*!< GPIO_T::SMTEN: SMTEN10 Position */
sahilmgandhi 18:6a4db94011d3 4519 #define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) /*!< GPIO_T::SMTEN: SMTEN10 Mask */
sahilmgandhi 18:6a4db94011d3 4520
sahilmgandhi 18:6a4db94011d3 4521 #define GPIO_SMTEN_SMTEN11_Pos (11) /*!< GPIO_T::SMTEN: SMTEN11 Position */
sahilmgandhi 18:6a4db94011d3 4522 #define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) /*!< GPIO_T::SMTEN: SMTEN11 Mask */
sahilmgandhi 18:6a4db94011d3 4523
sahilmgandhi 18:6a4db94011d3 4524 #define GPIO_SMTEN_SMTEN12_Pos (12) /*!< GPIO_T::SMTEN: SMTEN12 Position */
sahilmgandhi 18:6a4db94011d3 4525 #define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) /*!< GPIO_T::SMTEN: SMTEN12 Mask */
sahilmgandhi 18:6a4db94011d3 4526
sahilmgandhi 18:6a4db94011d3 4527 #define GPIO_SMTEN_SMTEN13_Pos (13) /*!< GPIO_T::SMTEN: SMTEN13 Position */
sahilmgandhi 18:6a4db94011d3 4528 #define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) /*!< GPIO_T::SMTEN: SMTEN13 Mask */
sahilmgandhi 18:6a4db94011d3 4529
sahilmgandhi 18:6a4db94011d3 4530 #define GPIO_SMTEN_SMTEN14_Pos (14) /*!< GPIO_T::SMTEN: SMTEN14 Position */
sahilmgandhi 18:6a4db94011d3 4531 #define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) /*!< GPIO_T::SMTEN: SMTEN14 Mask */
sahilmgandhi 18:6a4db94011d3 4532
sahilmgandhi 18:6a4db94011d3 4533 #define GPIO_SMTEN_SMTEN15_Pos (15) /*!< GPIO_T::SMTEN: SMTEN15 Position */
sahilmgandhi 18:6a4db94011d3 4534 #define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) /*!< GPIO_T::SMTEN: SMTEN15 Mask */
sahilmgandhi 18:6a4db94011d3 4535
sahilmgandhi 18:6a4db94011d3 4536 #define GPIO_SLEWCTL_HSREN0_Pos (0) /*!< GPIO_T::SLEWCTL: HSREN0 Position */
sahilmgandhi 18:6a4db94011d3 4537 #define GPIO_SLEWCTL_HSREN0_Msk (0x1ul << GPIO_SLEWCTL_HSREN0_Pos) /*!< GPIO_T::SLEWCTL: HSREN0 Mask */
sahilmgandhi 18:6a4db94011d3 4538
sahilmgandhi 18:6a4db94011d3 4539 #define GPIO_SLEWCTL_HSREN1_Pos (1) /*!< GPIO_T::SLEWCTL: HSREN1 Position */
sahilmgandhi 18:6a4db94011d3 4540 #define GPIO_SLEWCTL_HSREN1_Msk (0x1ul << GPIO_SLEWCTL_HSREN1_Pos) /*!< GPIO_T::SLEWCTL: HSREN1 Mask */
sahilmgandhi 18:6a4db94011d3 4541
sahilmgandhi 18:6a4db94011d3 4542 #define GPIO_SLEWCTL_HSREN2_Pos (2) /*!< GPIO_T::SLEWCTL: HSREN2 Position */
sahilmgandhi 18:6a4db94011d3 4543 #define GPIO_SLEWCTL_HSREN2_Msk (0x1ul << GPIO_SLEWCTL_HSREN2_Pos) /*!< GPIO_T::SLEWCTL: HSREN2 Mask */
sahilmgandhi 18:6a4db94011d3 4544
sahilmgandhi 18:6a4db94011d3 4545 #define GPIO_SLEWCTL_HSREN3_Pos (3) /*!< GPIO_T::SLEWCTL: HSREN3 Position */
sahilmgandhi 18:6a4db94011d3 4546 #define GPIO_SLEWCTL_HSREN3_Msk (0x1ul << GPIO_SLEWCTL_HSREN3_Pos) /*!< GPIO_T::SLEWCTL: HSREN3 Mask */
sahilmgandhi 18:6a4db94011d3 4547
sahilmgandhi 18:6a4db94011d3 4548 #define GPIO_SLEWCTL_HSREN4_Pos (4) /*!< GPIO_T::SLEWCTL: HSREN4 Position */
sahilmgandhi 18:6a4db94011d3 4549 #define GPIO_SLEWCTL_HSREN4_Msk (0x1ul << GPIO_SLEWCTL_HSREN4_Pos) /*!< GPIO_T::SLEWCTL: HSREN4 Mask */
sahilmgandhi 18:6a4db94011d3 4550
sahilmgandhi 18:6a4db94011d3 4551 #define GPIO_SLEWCTL_HSREN5_Pos (5) /*!< GPIO_T::SLEWCTL: HSREN5 Position */
sahilmgandhi 18:6a4db94011d3 4552 #define GPIO_SLEWCTL_HSREN5_Msk (0x1ul << GPIO_SLEWCTL_HSREN5_Pos) /*!< GPIO_T::SLEWCTL: HSREN5 Mask */
sahilmgandhi 18:6a4db94011d3 4553
sahilmgandhi 18:6a4db94011d3 4554 #define GPIO_SLEWCTL_HSREN6_Pos (6) /*!< GPIO_T::SLEWCTL: HSREN6 Position */
sahilmgandhi 18:6a4db94011d3 4555 #define GPIO_SLEWCTL_HSREN6_Msk (0x1ul << GPIO_SLEWCTL_HSREN6_Pos) /*!< GPIO_T::SLEWCTL: HSREN6 Mask */
sahilmgandhi 18:6a4db94011d3 4556
sahilmgandhi 18:6a4db94011d3 4557 #define GPIO_SLEWCTL_HSREN7_Pos (7) /*!< GPIO_T::SLEWCTL: HSREN7 Position */
sahilmgandhi 18:6a4db94011d3 4558 #define GPIO_SLEWCTL_HSREN7_Msk (0x1ul << GPIO_SLEWCTL_HSREN7_Pos) /*!< GPIO_T::SLEWCTL: HSREN7 Mask */
sahilmgandhi 18:6a4db94011d3 4559
sahilmgandhi 18:6a4db94011d3 4560 #define GPIO_SLEWCTL_HSREN8_Pos (8) /*!< GPIO_T::SLEWCTL: HSREN8 Position */
sahilmgandhi 18:6a4db94011d3 4561 #define GPIO_SLEWCTL_HSREN8_Msk (0x1ul << GPIO_SLEWCTL_HSREN8_Pos) /*!< GPIO_T::SLEWCTL: HSREN8 Mask */
sahilmgandhi 18:6a4db94011d3 4562
sahilmgandhi 18:6a4db94011d3 4563 #define GPIO_SLEWCTL_HSREN9_Pos (9) /*!< GPIO_T::SLEWCTL: HSREN9 Position */
sahilmgandhi 18:6a4db94011d3 4564 #define GPIO_SLEWCTL_HSREN9_Msk (0x1ul << GPIO_SLEWCTL_HSREN9_Pos) /*!< GPIO_T::SLEWCTL: HSREN9 Mask */
sahilmgandhi 18:6a4db94011d3 4565
sahilmgandhi 18:6a4db94011d3 4566 #define GPIO_SLEWCTL_HSREN10_Pos (10) /*!< GPIO_T::SLEWCTL: HSREN10 Position */
sahilmgandhi 18:6a4db94011d3 4567 #define GPIO_SLEWCTL_HSREN10_Msk (0x1ul << GPIO_SLEWCTL_HSREN10_Pos) /*!< GPIO_T::SLEWCTL: HSREN10 Mask */
sahilmgandhi 18:6a4db94011d3 4568
sahilmgandhi 18:6a4db94011d3 4569 #define GPIO_SLEWCTL_HSREN11_Pos (11) /*!< GPIO_T::SLEWCTL: HSREN11 Position */
sahilmgandhi 18:6a4db94011d3 4570 #define GPIO_SLEWCTL_HSREN11_Msk (0x1ul << GPIO_SLEWCTL_HSREN11_Pos) /*!< GPIO_T::SLEWCTL: HSREN11 Mask */
sahilmgandhi 18:6a4db94011d3 4571
sahilmgandhi 18:6a4db94011d3 4572 #define GPIO_SLEWCTL_HSREN12_Pos (12) /*!< GPIO_T::SLEWCTL: HSREN12 Position */
sahilmgandhi 18:6a4db94011d3 4573 #define GPIO_SLEWCTL_HSREN12_Msk (0x1ul << GPIO_SLEWCTL_HSREN12_Pos) /*!< GPIO_T::SLEWCTL: HSREN12 Mask */
sahilmgandhi 18:6a4db94011d3 4574
sahilmgandhi 18:6a4db94011d3 4575 #define GPIO_SLEWCTL_HSREN13_Pos (13) /*!< GPIO_T::SLEWCTL: HSREN13 Position */
sahilmgandhi 18:6a4db94011d3 4576 #define GPIO_SLEWCTL_HSREN13_Msk (0x1ul << GPIO_SLEWCTL_HSREN13_Pos) /*!< GPIO_T::SLEWCTL: HSREN13 Mask */
sahilmgandhi 18:6a4db94011d3 4577
sahilmgandhi 18:6a4db94011d3 4578 #define GPIO_SLEWCTL_HSREN14_Pos (14) /*!< GPIO_T::SLEWCTL: HSREN14 Position */
sahilmgandhi 18:6a4db94011d3 4579 #define GPIO_SLEWCTL_HSREN14_Msk (0x1ul << GPIO_SLEWCTL_HSREN14_Pos) /*!< GPIO_T::SLEWCTL: HSREN14 Mask */
sahilmgandhi 18:6a4db94011d3 4580
sahilmgandhi 18:6a4db94011d3 4581 #define GPIO_SLEWCTL_HSREN15_Pos (15) /*!< GPIO_T::SLEWCTL: HSREN15 Position */
sahilmgandhi 18:6a4db94011d3 4582 #define GPIO_SLEWCTL_HSREN15_Msk (0x1ul << GPIO_SLEWCTL_HSREN15_Pos) /*!< GPIO_T::SLEWCTL: HSREN15 Mask */
sahilmgandhi 18:6a4db94011d3 4583
sahilmgandhi 18:6a4db94011d3 4584 #define GPIO_DRVCTL_HDRVEN8_Pos (8) /*!< GPIO_T::DRVCTL: HDRVEN8 Position */
sahilmgandhi 18:6a4db94011d3 4585 #define GPIO_DRVCTL_HDRVEN8_Msk (0x1ul << GPIO_DRVCTL_HDRVEN8_Pos) /*!< GPIO_T::DRVCTL: HDRVEN8 Mask */
sahilmgandhi 18:6a4db94011d3 4586
sahilmgandhi 18:6a4db94011d3 4587 #define GPIO_DRVCTL_HDRVEN9_Pos (9) /*!< GPIO_T::DRVCTL: HDRVEN9 Position */
sahilmgandhi 18:6a4db94011d3 4588 #define GPIO_DRVCTL_HDRVEN9_Msk (0x1ul << GPIO_DRVCTL_HDRVEN9_Pos) /*!< GPIO_T::DRVCTL: HDRVEN9 Mask */
sahilmgandhi 18:6a4db94011d3 4589
sahilmgandhi 18:6a4db94011d3 4590 #define GPIO_DRVCTL_HDRVEN10_Pos (10) /*!< GPIO_T::DRVCTL: HDRVEN10 Position */
sahilmgandhi 18:6a4db94011d3 4591 #define GPIO_DRVCTL_HDRVEN10_Msk (0x1ul << GPIO_DRVCTL_HDRVEN10_Pos) /*!< GPIO_T::DRVCTL: HDRVEN10 Mask */
sahilmgandhi 18:6a4db94011d3 4592
sahilmgandhi 18:6a4db94011d3 4593 #define GPIO_DRVCTL_HDRVEN11_Pos (11) /*!< GPIO_T::DRVCTL: HDRVEN11 Position */
sahilmgandhi 18:6a4db94011d3 4594 #define GPIO_DRVCTL_HDRVEN11_Msk (0x1ul << GPIO_DRVCTL_HDRVEN11_Pos) /*!< GPIO_T::DRVCTL: HDRVEN11 Mask */
sahilmgandhi 18:6a4db94011d3 4595
sahilmgandhi 18:6a4db94011d3 4596 #define GPIO_DRVCTL_HDRVEN12_Pos (12) /*!< GPIO_T::DRVCTL: HDRVEN12 Position */
sahilmgandhi 18:6a4db94011d3 4597 #define GPIO_DRVCTL_HDRVEN12_Msk (0x1ul << GPIO_DRVCTL_HDRVEN12_Pos) /*!< GPIO_T::DRVCTL: HDRVEN12 Mask */
sahilmgandhi 18:6a4db94011d3 4598
sahilmgandhi 18:6a4db94011d3 4599 #define GPIO_DRVCTL_HDRVEN13_Pos (13) /*!< GPIO_T::DRVCTL: HDRVEN13 Position */
sahilmgandhi 18:6a4db94011d3 4600 #define GPIO_DRVCTL_HDRVEN13_Msk (0x1ul << GPIO_DRVCTL_HDRVEN13_Pos) /*!< GPIO_T::DRVCTL: HDRVEN13 Mask */
sahilmgandhi 18:6a4db94011d3 4601
sahilmgandhi 18:6a4db94011d3 4602 #define GPIO_DBCTL_DBCLKSEL_Pos (0) /*!< GPIO_T::DBCTL: DBCLKSEL Position */
sahilmgandhi 18:6a4db94011d3 4603 #define GPIO_DBCTL_DBCLKSEL_Msk (0xFul << GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_T::DBCTL: DBCLKSEL Mask */
sahilmgandhi 18:6a4db94011d3 4604
sahilmgandhi 18:6a4db94011d3 4605 #define GPIO_DBCTL_DBCLKSRC_Pos (4) /*!< GPIO_T::DBCTL: DBCLKSRC Position */
sahilmgandhi 18:6a4db94011d3 4606 #define GPIO_DBCTL_DBCLKSRC_Msk (1ul << GPIO_DBCTL_DBCLKSRC_Pos) /*!< GPIO_T::DBCTL: DBCLKSRC Mask */
sahilmgandhi 18:6a4db94011d3 4607
sahilmgandhi 18:6a4db94011d3 4608 #define GPIO_DBCTL_ICLKON_Pos (5) /*!< GPIO_T::DBCTL: ICLKON Position */
sahilmgandhi 18:6a4db94011d3 4609 #define GPIO_DBCTL_ICLKON_Msk (1ul << GPIO_DBCTL_ICLKON_Pos) /*!< GPIO_T::DBCTL: ICLKON Mask */
sahilmgandhi 18:6a4db94011d3 4610
sahilmgandhi 18:6a4db94011d3 4611
sahilmgandhi 18:6a4db94011d3 4612 /**@}*/ /* GPIO_CONST */
sahilmgandhi 18:6a4db94011d3 4613 /**@}*/ /* end of GPIO register group */
sahilmgandhi 18:6a4db94011d3 4614
sahilmgandhi 18:6a4db94011d3 4615
sahilmgandhi 18:6a4db94011d3 4616 /*---------------------- Inter-IC Bus Controller -------------------------*/
sahilmgandhi 18:6a4db94011d3 4617 /**
sahilmgandhi 18:6a4db94011d3 4618 @addtogroup I2C Inter-IC Bus Controller(I2C)
sahilmgandhi 18:6a4db94011d3 4619 Memory Mapped Structure for I2C Controller
sahilmgandhi 18:6a4db94011d3 4620 @{ */
sahilmgandhi 18:6a4db94011d3 4621
sahilmgandhi 18:6a4db94011d3 4622
sahilmgandhi 18:6a4db94011d3 4623 typedef struct
sahilmgandhi 18:6a4db94011d3 4624 {
sahilmgandhi 18:6a4db94011d3 4625
sahilmgandhi 18:6a4db94011d3 4626
sahilmgandhi 18:6a4db94011d3 4627
sahilmgandhi 18:6a4db94011d3 4628
sahilmgandhi 18:6a4db94011d3 4629 /**
sahilmgandhi 18:6a4db94011d3 4630 * @var I2C_T::CTL
sahilmgandhi 18:6a4db94011d3 4631 * Offset: 0x00 I2C Control Register
sahilmgandhi 18:6a4db94011d3 4632 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4633 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 4634 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 4635 * |[2] |AA |Assert Acknowledge Control
sahilmgandhi 18:6a4db94011d3 4636 * | | |When AA =1 prior to address or data is received,
sahilmgandhi 18:6a4db94011d3 4637 * | | |an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when
sahilmgandhi 18:6a4db94011d3 4638 * | | |1. A slave is acknowledging the address sent from master.
sahilmgandhi 18:6a4db94011d3 4639 * | | |2. The receiver devices are acknowledging the data sent by transmitter.
sahilmgandhi 18:6a4db94011d3 4640 * | | |When AA=0 prior to address or data received,
sahilmgandhi 18:6a4db94011d3 4641 * | | |a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.
sahilmgandhi 18:6a4db94011d3 4642 * |[3] |SI |I2C Interrupt Flag
sahilmgandhi 18:6a4db94011d3 4643 * | | |When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware.
sahilmgandhi 18:6a4db94011d3 4644 * | | |If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested.
sahilmgandhi 18:6a4db94011d3 4645 * | | |SI must be cleared by software.
sahilmgandhi 18:6a4db94011d3 4646 * | | |Clear SI by writing 1 to this bit.
sahilmgandhi 18:6a4db94011d3 4647 * | | |For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
sahilmgandhi 18:6a4db94011d3 4648 * |[4] |STO |I2C STOP Control
sahilmgandhi 18:6a4db94011d3 4649 * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected.
sahilmgandhi 18:6a4db94011d3 4650 * | | |This bit will be cleared by hardware automatically.
sahilmgandhi 18:6a4db94011d3 4651 * |[5] |STA |I2C START Control
sahilmgandhi 18:6a4db94011d3 4652 * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
sahilmgandhi 18:6a4db94011d3 4653 * |[6] |I2CEN |I2C Controller Enable Bit
sahilmgandhi 18:6a4db94011d3 4654 * | | |Set to enable I2C serial function controller.
sahilmgandhi 18:6a4db94011d3 4655 * | | |When I2CEN=1 the I2C serial function enable.
sahilmgandhi 18:6a4db94011d3 4656 * | | |The multi-function pin function must set to SDA, and SCL of I2C function first.
sahilmgandhi 18:6a4db94011d3 4657 * | | |0 = Disabled.
sahilmgandhi 18:6a4db94011d3 4658 * | | |1 = Enabled.
sahilmgandhi 18:6a4db94011d3 4659 * |[7] |INTEN |Enable Interrupt
sahilmgandhi 18:6a4db94011d3 4660 * | | |0 = I2C interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 4661 * | | |1 = I2C interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 4662 * @var I2C_T::ADDR0
sahilmgandhi 18:6a4db94011d3 4663 * Offset: 0x04 I2C Slave Address Register0
sahilmgandhi 18:6a4db94011d3 4664 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4665 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 4666 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 4667 * |[0] |GC |General Call Function
sahilmgandhi 18:6a4db94011d3 4668 * | | |0 = General Call Function Disabled.
sahilmgandhi 18:6a4db94011d3 4669 * | | |1 = General Call Function Enabled.
sahilmgandhi 18:6a4db94011d3 4670 * |[7:1] |ADDR |I2C Address
sahilmgandhi 18:6a4db94011d3 4671 * | | |The content of this register is irrelevant when I2C is in Master mode.
sahilmgandhi 18:6a4db94011d3 4672 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
sahilmgandhi 18:6a4db94011d3 4673 * | | |The I2C hardware will react if either of the address is matched.
sahilmgandhi 18:6a4db94011d3 4674 * @var I2C_T::DAT
sahilmgandhi 18:6a4db94011d3 4675 * Offset: 0x08 I2C Data Register
sahilmgandhi 18:6a4db94011d3 4676 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4677 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 4678 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 4679 * |[7:0] |DAT |I2C Data
sahilmgandhi 18:6a4db94011d3 4680 * | | |Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
sahilmgandhi 18:6a4db94011d3 4681 * @var I2C_T::STATUS
sahilmgandhi 18:6a4db94011d3 4682 * Offset: 0x0C I2C Status Register
sahilmgandhi 18:6a4db94011d3 4683 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4684 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 4685 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 4686 * |[7:0] |STATUS |I2C Status
sahilmgandhi 18:6a4db94011d3 4687 * | | |The three least significant bits are always 0.
sahilmgandhi 18:6a4db94011d3 4688 * | | |The five most significant bits contain the status code.
sahilmgandhi 18:6a4db94011d3 4689 * | | |There are 28 possible status codes.
sahilmgandhi 18:6a4db94011d3 4690 * | | |When the content of I2C_STATUS is F8H, no serial interrupt is requested.
sahilmgandhi 18:6a4db94011d3 4691 * | | |Others I2C_STATUS values correspond to defined I2C states.
sahilmgandhi 18:6a4db94011d3 4692 * | | |When each of these states is entered, a status interrupt is requested (SI = 1).
sahilmgandhi 18:6a4db94011d3 4693 * | | |A valid status code is present in I2C_STATUS one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software.
sahilmgandhi 18:6a4db94011d3 4694 * | | |In addition, states 00H stands for a Bus Error.
sahilmgandhi 18:6a4db94011d3 4695 * | | |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame.
sahilmgandhi 18:6a4db94011d3 4696 * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.
sahilmgandhi 18:6a4db94011d3 4697 * | | |Note:
sahilmgandhi 18:6a4db94011d3 4698 * | | |1.
sahilmgandhi 18:6a4db94011d3 4699 * | | |If the BUSEN and ACKMEN are enabled in slave received mode, there is SI interrupt in the 8th clock.
sahilmgandhi 18:6a4db94011d3 4700 * | | |The user can read the I2C_STATUS = 0xf0 for the function condition has done.
sahilmgandhi 18:6a4db94011d3 4701 * | | |2.
sahilmgandhi 18:6a4db94011d3 4702 * | | |If the BUSEN and PECEN are enabled, the status of PECERR, I2C_BUSSTS[3], is used to substitute for I2C_STATUS to check the ACK status in the last frame when the byte count done interrupt has active and the PEC frame has been transformed.
sahilmgandhi 18:6a4db94011d3 4703 * @var I2C_T::CLKDIV
sahilmgandhi 18:6a4db94011d3 4704 * Offset: 0x10 I2C Clock Divided Register
sahilmgandhi 18:6a4db94011d3 4705 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4706 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 4707 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 4708 * |[7:0] |DIVIDER |I2C Clock Divided
sahilmgandhi 18:6a4db94011d3 4709 * | | |Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (I2C_CLKDIV+1)).
sahilmgandhi 18:6a4db94011d3 4710 * | | |Note: The minimum value of I2C_CLKDIV is 4.
sahilmgandhi 18:6a4db94011d3 4711 * @var I2C_T::TOCTL
sahilmgandhi 18:6a4db94011d3 4712 * Offset: 0x14 I2C Time-out Control Register
sahilmgandhi 18:6a4db94011d3 4713 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4714 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 4715 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 4716 * |[0] |TOIF |Time-Out Flag
sahilmgandhi 18:6a4db94011d3 4717 * | | |This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
sahilmgandhi 18:6a4db94011d3 4718 * | | |Note: Software can write 1 to clear this bit.
sahilmgandhi 18:6a4db94011d3 4719 * |[1] |TOCDIV4 |Time-Out Counter Input Clock Divided By 4
sahilmgandhi 18:6a4db94011d3 4720 * | | |When Enabled, The time-out period is extend 4 times.
sahilmgandhi 18:6a4db94011d3 4721 * | | |0 = Disabled.
sahilmgandhi 18:6a4db94011d3 4722 * | | |1 = Enabled.
sahilmgandhi 18:6a4db94011d3 4723 * |[2] |TOCEN |Time-Out Counter Enable Bit
sahilmgandhi 18:6a4db94011d3 4724 * | | |When Enabled, the 14-bit time-out counter will start counting when SI is clear.
sahilmgandhi 18:6a4db94011d3 4725 * | | |Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
sahilmgandhi 18:6a4db94011d3 4726 * | | |0 = Disabled.
sahilmgandhi 18:6a4db94011d3 4727 * | | |1 = Enabled.
sahilmgandhi 18:6a4db94011d3 4728 * @var I2C_T::ADDR1
sahilmgandhi 18:6a4db94011d3 4729 * Offset: 0x18 I2C Slave Address Register1
sahilmgandhi 18:6a4db94011d3 4730 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4731 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 4732 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 4733 * |[0] |GC |General Call Function
sahilmgandhi 18:6a4db94011d3 4734 * | | |0 = General Call Function Disabled.
sahilmgandhi 18:6a4db94011d3 4735 * | | |1 = General Call Function Enabled.
sahilmgandhi 18:6a4db94011d3 4736 * |[7:1] |ADDR |I2C Address
sahilmgandhi 18:6a4db94011d3 4737 * | | |The content of this register is irrelevant when I2C is in Master mode.
sahilmgandhi 18:6a4db94011d3 4738 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
sahilmgandhi 18:6a4db94011d3 4739 * | | |The I2C hardware will react if either of the address is matched.
sahilmgandhi 18:6a4db94011d3 4740 * @var I2C_T::ADDR2
sahilmgandhi 18:6a4db94011d3 4741 * Offset: 0x1C I2C Slave Address Register2
sahilmgandhi 18:6a4db94011d3 4742 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4743 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 4744 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 4745 * |[0] |GC |General Call Function
sahilmgandhi 18:6a4db94011d3 4746 * | | |0 = General Call Function Disabled.
sahilmgandhi 18:6a4db94011d3 4747 * | | |1 = General Call Function Enabled.
sahilmgandhi 18:6a4db94011d3 4748 * |[7:1] |ADDR |I2C Address
sahilmgandhi 18:6a4db94011d3 4749 * | | |The content of this register is irrelevant when I2C is in Master mode.
sahilmgandhi 18:6a4db94011d3 4750 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
sahilmgandhi 18:6a4db94011d3 4751 * | | |The I2C hardware will react if either of the address is matched.
sahilmgandhi 18:6a4db94011d3 4752 * @var I2C_T::ADDR3
sahilmgandhi 18:6a4db94011d3 4753 * Offset: 0x20 I2C Slave Address Register3
sahilmgandhi 18:6a4db94011d3 4754 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4755 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 4756 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 4757 * |[0] |GC |General Call Function
sahilmgandhi 18:6a4db94011d3 4758 * | | |0 = General Call Function Disabled.
sahilmgandhi 18:6a4db94011d3 4759 * | | |1 = General Call Function Enabled.
sahilmgandhi 18:6a4db94011d3 4760 * |[7:1] |ADDR |I2C Address
sahilmgandhi 18:6a4db94011d3 4761 * | | |The content of this register is irrelevant when I2C is in Master mode.
sahilmgandhi 18:6a4db94011d3 4762 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
sahilmgandhi 18:6a4db94011d3 4763 * | | |The I2C hardware will react if either of the address is matched.
sahilmgandhi 18:6a4db94011d3 4764 * @var I2C_T::ADDRMSK0
sahilmgandhi 18:6a4db94011d3 4765 * Offset: 0x24 I2C Slave Address Mask Register0
sahilmgandhi 18:6a4db94011d3 4766 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4767 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 4768 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 4769 * |[7:1] |ADDRMSK |I2C Address Mask
sahilmgandhi 18:6a4db94011d3 4770 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
sahilmgandhi 18:6a4db94011d3 4771 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
sahilmgandhi 18:6a4db94011d3 4772 * | | |I2C bus controllers support multiple address recognition with four address mask register.
sahilmgandhi 18:6a4db94011d3 4773 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
sahilmgandhi 18:6a4db94011d3 4774 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
sahilmgandhi 18:6a4db94011d3 4775 * @var I2C_T::ADDRMSK1
sahilmgandhi 18:6a4db94011d3 4776 * Offset: 0x28 I2C Slave Address Mask Register1
sahilmgandhi 18:6a4db94011d3 4777 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4778 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 4779 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 4780 * |[7:1] |ADDRMSK |I2C Address Mask
sahilmgandhi 18:6a4db94011d3 4781 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
sahilmgandhi 18:6a4db94011d3 4782 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
sahilmgandhi 18:6a4db94011d3 4783 * | | |I2C bus controllers support multiple address recognition with four address mask register.
sahilmgandhi 18:6a4db94011d3 4784 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
sahilmgandhi 18:6a4db94011d3 4785 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
sahilmgandhi 18:6a4db94011d3 4786 * @var I2C_T::ADDRMSK2
sahilmgandhi 18:6a4db94011d3 4787 * Offset: 0x2C I2C Slave Address Mask Register2
sahilmgandhi 18:6a4db94011d3 4788 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4789 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 4790 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 4791 * |[7:1] |ADDRMSK |I2C Address Mask
sahilmgandhi 18:6a4db94011d3 4792 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
sahilmgandhi 18:6a4db94011d3 4793 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
sahilmgandhi 18:6a4db94011d3 4794 * | | |I2C bus controllers support multiple address recognition with four address mask register.
sahilmgandhi 18:6a4db94011d3 4795 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
sahilmgandhi 18:6a4db94011d3 4796 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
sahilmgandhi 18:6a4db94011d3 4797 * @var I2C_T::ADDRMSK3
sahilmgandhi 18:6a4db94011d3 4798 * Offset: 0x30 I2C Slave Address Mask Register3
sahilmgandhi 18:6a4db94011d3 4799 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4800 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 4801 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 4802 * |[7:1] |ADDRMSK |I2C Address Mask
sahilmgandhi 18:6a4db94011d3 4803 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
sahilmgandhi 18:6a4db94011d3 4804 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
sahilmgandhi 18:6a4db94011d3 4805 * | | |I2C bus controllers support multiple address recognition with four address mask register.
sahilmgandhi 18:6a4db94011d3 4806 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
sahilmgandhi 18:6a4db94011d3 4807 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
sahilmgandhi 18:6a4db94011d3 4808 * @var I2C_T::WKCTL
sahilmgandhi 18:6a4db94011d3 4809 * Offset: 0x3C I2C Wake-up Control Register
sahilmgandhi 18:6a4db94011d3 4810 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4811 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 4812 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 4813 * |[0] |WKEN |I2C Wake-Up Enable Bit
sahilmgandhi 18:6a4db94011d3 4814 * | | |0 = I2C wake-up function Disabled.
sahilmgandhi 18:6a4db94011d3 4815 * | | |1= I2C wake-up function Enabled.
sahilmgandhi 18:6a4db94011d3 4816 * @var I2C_T::WKSTS
sahilmgandhi 18:6a4db94011d3 4817 * Offset: 0x40 I2C Wake-up Status Register
sahilmgandhi 18:6a4db94011d3 4818 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4819 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 4820 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 4821 * |[0] |WKIF |I2C Wake-Up Flag
sahilmgandhi 18:6a4db94011d3 4822 * | | |When chip is woken up from Power-down mode by I2C, this bit is set to 1.
sahilmgandhi 18:6a4db94011d3 4823 * | | |Software can write 1 to clear this bit.
sahilmgandhi 18:6a4db94011d3 4824 * @var I2C_T::BUSCTL
sahilmgandhi 18:6a4db94011d3 4825 * Offset: 0x44 I2C Bus Management Control Register
sahilmgandhi 18:6a4db94011d3 4826 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4827 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 4828 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 4829 * |[0] |ACKMEN |Acknowledge Control By Manual
sahilmgandhi 18:6a4db94011d3 4830 * | | |In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit.
sahilmgandhi 18:6a4db94011d3 4831 * | | |0 = Slave byte control Disabled.
sahilmgandhi 18:6a4db94011d3 4832 * | | |1 = Slave byte control Enabled.
sahilmgandhi 18:6a4db94011d3 4833 * | | |The 9th bit can response the ACK or NACK according the received data by user.
sahilmgandhi 18:6a4db94011d3 4834 * | | |When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse.
sahilmgandhi 18:6a4db94011d3 4835 * | | |Note: If the BMDEN =1 and this bit is enabled, the information of I2C_STATUS will be fixed as 0xF0 in slave receive condition.
sahilmgandhi 18:6a4db94011d3 4836 * |[1] |PECEN |Packet Error Checking Calculation Enable Bit
sahilmgandhi 18:6a4db94011d3 4837 * | | |0 = Packet Error Checking Calculation Disabled.
sahilmgandhi 18:6a4db94011d3 4838 * | | |1 = Packet Error Checking Calculation Enabled.
sahilmgandhi 18:6a4db94011d3 4839 * |[2] |BMDEN |Bus Management Device Default Address Enable Bit
sahilmgandhi 18:6a4db94011d3 4840 * | | |0 = Device default address Disable.
sahilmgandhi 18:6a4db94011d3 4841 * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed.
sahilmgandhi 18:6a4db94011d3 4842 * | | |1 = Device default address Enabled.
sahilmgandhi 18:6a4db94011d3 4843 * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed.
sahilmgandhi 18:6a4db94011d3 4844 * |[3] |BMHEN |Bus Management Host Enable Bit
sahilmgandhi 18:6a4db94011d3 4845 * | | |0 = Host function Disabled.
sahilmgandhi 18:6a4db94011d3 4846 * | | |1 = Host function Enabled and the SUSCON will be used as CONTROL function.
sahilmgandhi 18:6a4db94011d3 4847 * |[4] |ALERTEN |Bus Management Alert Enable Bit
sahilmgandhi 18:6a4db94011d3 4848 * | | |Device Mode (BMHEN =0).
sahilmgandhi 18:6a4db94011d3 4849 * | | |0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.
sahilmgandhi 18:6a4db94011d3 4850 * | | |1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.
sahilmgandhi 18:6a4db94011d3 4851 * | | |Host Mode (BMHEN =1).
sahilmgandhi 18:6a4db94011d3 4852 * | | |0 = BM_ALERT pin not supported.
sahilmgandhi 18:6a4db94011d3 4853 * | | |1 = BM_ALERT pin supported.
sahilmgandhi 18:6a4db94011d3 4854 * |[5] |SCTLOSTS |Suspend/Control Data Output Status
sahilmgandhi 18:6a4db94011d3 4855 * | | |0 = The output of SUSCON pin is low.
sahilmgandhi 18:6a4db94011d3 4856 * | | |1 = The output of SUSCON pin is high.
sahilmgandhi 18:6a4db94011d3 4857 * |[6] |SCTLOEN |Suspend Or Control Pin Output Enable Bit
sahilmgandhi 18:6a4db94011d3 4858 * | | |0 = The SUSCON pin in input.
sahilmgandhi 18:6a4db94011d3 4859 * | | |1 = The output enable is active on the SUSCON pin.
sahilmgandhi 18:6a4db94011d3 4860 * |[7] |BUSEN |BUS Enable Bit
sahilmgandhi 18:6a4db94011d3 4861 * | | |0 = The system management function is Disabled.
sahilmgandhi 18:6a4db94011d3 4862 * | | |1 = The system management function is Enable.
sahilmgandhi 18:6a4db94011d3 4863 * | | |Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition.
sahilmgandhi 18:6a4db94011d3 4864 * |[8] |PECTXEN |Packet Error Checking Byte Transmission/Reception
sahilmgandhi 18:6a4db94011d3 4865 * | | |This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address Matched is received
sahilmgandhi 18:6a4db94011d3 4866 * | | |0 = No PEC transfer.
sahilmgandhi 18:6a4db94011d3 4867 * | | |1 = PEC transmission/reception is requested.
sahilmgandhi 18:6a4db94011d3 4868 * | | |Note: 1.This bit has no effect in slave mode when ACKMEN =0.
sahilmgandhi 18:6a4db94011d3 4869 * |[9] |TIDLE |Timer Check In Idle State
sahilmgandhi 18:6a4db94011d3 4870 * | | |The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle.
sahilmgandhi 18:6a4db94011d3 4871 * | | |This bit is used to define which condition is enabled.
sahilmgandhi 18:6a4db94011d3 4872 * | | |0 = The BUSTOUT is used to calculate the clock low period in bus active.
sahilmgandhi 18:6a4db94011d3 4873 * | | |1 = The BUSTOUT is used to calculate the IDLE period in bus Idle.
sahilmgandhi 18:6a4db94011d3 4874 * | | |Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state.
sahilmgandhi 18:6a4db94011d3 4875 * |[10] |PECCLR |PEC Clear At Repeat Start
sahilmgandhi 18:6a4db94011d3 4876 * | | |The calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected.
sahilmgandhi 18:6a4db94011d3 4877 * | | |This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation.
sahilmgandhi 18:6a4db94011d3 4878 * | | |0 = The PEC calculation is cleared by "Repeat Start" function is Disabled.
sahilmgandhi 18:6a4db94011d3 4879 * | | |1 = The PEC calculation is cleared by "Repeat Start" function is Enabled.
sahilmgandhi 18:6a4db94011d3 4880 * |[11] |ACKM9SI |Acknowledge Manual Enable Extra SI Interrupt
sahilmgandhi 18:6a4db94011d3 4881 * | | |0 = There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1.
sahilmgandhi 18:6a4db94011d3 4882 * | | |1 = There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1.
sahilmgandhi 18:6a4db94011d3 4883 * @var I2C_T::BUSTCTL
sahilmgandhi 18:6a4db94011d3 4884 * Offset: 0x48 I2C Bus Management Timer Control Register
sahilmgandhi 18:6a4db94011d3 4885 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4886 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 4887 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 4888 * |[0] |BUSTOEN |Bus Time Out Enable Bit
sahilmgandhi 18:6a4db94011d3 4889 * | | |0 = Indicates the bus clock low time-out detection is Disabled.
sahilmgandhi 18:6a4db94011d3 4890 * | | |1 = Indicates the bus clock low time-out detection is Enabled
sahilmgandhi 18:6a4db94011d3 4891 * | | |bus clock is low for more than Time-out (in BIDLE=0) or high more than Time-out(in BIDLE =1),
sahilmgandhi 18:6a4db94011d3 4892 * |[1] |CLKTOEN |Cumulative Clock Low Time Out Enable Bit
sahilmgandhi 18:6a4db94011d3 4893 * | | |0 = Indicates the cumulative clock low time-out detection is Disabled.
sahilmgandhi 18:6a4db94011d3 4894 * | | |1 = Indicates the cumulative clock low time-out detection is Enabled.
sahilmgandhi 18:6a4db94011d3 4895 * | | |For Master, it calculates the period from START to ACK
sahilmgandhi 18:6a4db94011d3 4896 * | | |For Slave, it calculates the period from START to STOP
sahilmgandhi 18:6a4db94011d3 4897 * |[2] |BUSTOIEN |Time-Out Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 4898 * | | |BUSY =1.
sahilmgandhi 18:6a4db94011d3 4899 * | | |0 = Indicates the SCLK low time-out interrupt is Disabled.
sahilmgandhi 18:6a4db94011d3 4900 * | | |1 = Indicates the SCLK low time-out interrupt is Enabled.
sahilmgandhi 18:6a4db94011d3 4901 * | | |BUSY =0.
sahilmgandhi 18:6a4db94011d3 4902 * | | |0 = Indicates the bus IDLE time-out interrupt is Disabled.
sahilmgandhi 18:6a4db94011d3 4903 * | | |1 = Indicates the bus IDLE time-out interrupt is Enabled.
sahilmgandhi 18:6a4db94011d3 4904 * |[3] |CLKTOIEN |Extended Clock Time Out Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 4905 * | | |0 = Indicates the time extended interrupt is Disabled.
sahilmgandhi 18:6a4db94011d3 4906 * | | |1 = Indicates the time extended interrupt is Enabled.
sahilmgandhi 18:6a4db94011d3 4907 * |[4] |TORSTEN |Time Out Reset Enable Bit
sahilmgandhi 18:6a4db94011d3 4908 * | | |0 = Indicates the I2C state machine reset is Disable.
sahilmgandhi 18:6a4db94011d3 4909 * | | |1 = Indicates the I2C state machine reset is Enable. (The clock and data bus will be released to high)
sahilmgandhi 18:6a4db94011d3 4910 * |[5] |PECIEN |Packet Error Checking Byte Count Done Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 4911 * | | |0 = Indicates the byte count done interrupt is Disabled.
sahilmgandhi 18:6a4db94011d3 4912 * | | |1 = Indicates the byte count done interrupt is Enabled.
sahilmgandhi 18:6a4db94011d3 4913 * | | |Note: This bit is used in PECEN =1.
sahilmgandhi 18:6a4db94011d3 4914 * @var I2C_T::BUSSTS
sahilmgandhi 18:6a4db94011d3 4915 * Offset: 0x4C I2C Bus Management Status Register
sahilmgandhi 18:6a4db94011d3 4916 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4917 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 4918 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 4919 * |[0] |BUSY |Bus Busy
sahilmgandhi 18:6a4db94011d3 4920 * | | |Indicates that a communication is in progress on the bus.
sahilmgandhi 18:6a4db94011d3 4921 * | | |It is set by hardware when a START condition is detected.
sahilmgandhi 18:6a4db94011d3 4922 * | | |It is cleared by hardware when a STOP condition is detected.
sahilmgandhi 18:6a4db94011d3 4923 * | | |0 = The bus is IDLE (both SCLK and SDA High).
sahilmgandhi 18:6a4db94011d3 4924 * | | |1 = The bus is busy.
sahilmgandhi 18:6a4db94011d3 4925 * |[1] |BCDONE |Byte Count Transmission/Receive Done
sahilmgandhi 18:6a4db94011d3 4926 * | | |0 = Indicates the transmission/ receive is not finished when the PECEN is set.
sahilmgandhi 18:6a4db94011d3 4927 * | | |1 = Indicates the transmission/ receive is finished when the PECEN is set.
sahilmgandhi 18:6a4db94011d3 4928 * | | |Note: Software can write 1 to clear this bit.
sahilmgandhi 18:6a4db94011d3 4929 * |[2] |PECERR |PEC Error In Reception
sahilmgandhi 18:6a4db94011d3 4930 * | | |0 = Indicates the PEC value equal the received PEC data packet.
sahilmgandhi 18:6a4db94011d3 4931 * | | |1 = Indicates the PEC value doesn't match the receive PEC data packet.
sahilmgandhi 18:6a4db94011d3 4932 * | | |Note: Software can write 1 to clear this bit.
sahilmgandhi 18:6a4db94011d3 4933 * |[3] |ALERT |SMBus Alert Status
sahilmgandhi 18:6a4db94011d3 4934 * | | |Device Mode (BMHEN =0).
sahilmgandhi 18:6a4db94011d3 4935 * | | |0 = Indicates SMALERT pin state is low.
sahilmgandhi 18:6a4db94011d3 4936 * | | |1 = Indicates SMALERT pin state is high
sahilmgandhi 18:6a4db94011d3 4937 * | | |Host Mode (BMHEN =1).
sahilmgandhi 18:6a4db94011d3 4938 * | | |0 = No SMBALERT event.
sahilmgandhi 18:6a4db94011d3 4939 * | | |1 = Indicates there is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1.
sahilmgandhi 18:6a4db94011d3 4940 * | | |Note: 1.
sahilmgandhi 18:6a4db94011d3 4941 * | | |The SMALERT pin is an open-drain pin, the pull-high resistor is must in the system.
sahilmgandhi 18:6a4db94011d3 4942 * | | |2.
sahilmgandhi 18:6a4db94011d3 4943 * | | |Software can write 1 to clear this bit.
sahilmgandhi 18:6a4db94011d3 4944 * |[4] |SCTLDIN |Bus Suspend Or Control Signal Input Status
sahilmgandhi 18:6a4db94011d3 4945 * | | |0 = The input status of SUSCON pin is 0.
sahilmgandhi 18:6a4db94011d3 4946 * | | |1 = The input status of SUSCON pin is 1.
sahilmgandhi 18:6a4db94011d3 4947 * |[5] |BUSTO |Bus Time-out Status
sahilmgandhi 18:6a4db94011d3 4948 * | | |0 = Indicates that there is no any time-out or external clock time-out.
sahilmgandhi 18:6a4db94011d3 4949 * | | |1 = Indicates that a time-out or external clock time-out occurred.
sahilmgandhi 18:6a4db94011d3 4950 * | | |In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred.
sahilmgandhi 18:6a4db94011d3 4951 * | | |Note: Software can write 1 to clear this bit.
sahilmgandhi 18:6a4db94011d3 4952 * |[6] |CLKTO |Clock Low Cumulate Time-out Status
sahilmgandhi 18:6a4db94011d3 4953 * | | |0 = Indicates that the cumulative clock low is no any time-out.
sahilmgandhi 18:6a4db94011d3 4954 * | | |1 = Indicates that the cumulative clock low time-out occurred.
sahilmgandhi 18:6a4db94011d3 4955 * | | |Note: Software can write 1 to clear this bit.
sahilmgandhi 18:6a4db94011d3 4956 * @var I2C_T::PKTSIZE
sahilmgandhi 18:6a4db94011d3 4957 * Offset: 0x50 I2C Packet Error Checking Byte Number Register
sahilmgandhi 18:6a4db94011d3 4958 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4959 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 4960 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 4961 * |[7:0] |PLDSIZE |Transfer Byte Number
sahilmgandhi 18:6a4db94011d3 4962 * | | |The transmission or receive byte number in one transaction when the PECEN is set.
sahilmgandhi 18:6a4db94011d3 4963 * | | |The maximum transaction or receive byte is 255 Bytes.
sahilmgandhi 18:6a4db94011d3 4964 * @var I2C_T::PKTCRC
sahilmgandhi 18:6a4db94011d3 4965 * Offset: 0x54 I2C Packet Error Checking Byte Value Register
sahilmgandhi 18:6a4db94011d3 4966 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4967 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 4968 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 4969 * |[7:0] |PECCRC |Packet Error Checking Byte Value
sahilmgandhi 18:6a4db94011d3 4970 * | | |This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = X8 + X2 + X + 1.
sahilmgandhi 18:6a4db94011d3 4971 * | | |I t is read only.
sahilmgandhi 18:6a4db94011d3 4972 * @var I2C_T::BUSTOUT
sahilmgandhi 18:6a4db94011d3 4973 * Offset: 0x58 I2C Bus Management Timer Register
sahilmgandhi 18:6a4db94011d3 4974 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4975 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 4976 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 4977 * |[7:0] |BUSTO |Bus Management Time-out Value
sahilmgandhi 18:6a4db94011d3 4978 * | | |Indicate the bus time-out value in bus is IDLE or SCLK low.
sahilmgandhi 18:6a4db94011d3 4979 * | | |Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set.
sahilmgandhi 18:6a4db94011d3 4980 * @var I2C_T::CLKTOUT
sahilmgandhi 18:6a4db94011d3 4981 * Offset: 0x5C I2C Bus Management Clock Low Timer Register
sahilmgandhi 18:6a4db94011d3 4982 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4983 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 4984 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 4985 * |[7:0] |CLKTO |Bus Clock Low Timer
sahilmgandhi 18:6a4db94011d3 4986 * | | |The field is used to configure the cumulative clock extension time-out.
sahilmgandhi 18:6a4db94011d3 4987 * | | |Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and d clear to 0 first in the BUSEN is set.
sahilmgandhi 18:6a4db94011d3 4988 */
sahilmgandhi 18:6a4db94011d3 4989
sahilmgandhi 18:6a4db94011d3 4990 __IO uint32_t CTL; /* Offset: 0x00 I2C Control Register */
sahilmgandhi 18:6a4db94011d3 4991 __IO uint32_t ADDR0; /* Offset: 0x04 I2C Slave Address Register0 */
sahilmgandhi 18:6a4db94011d3 4992 __IO uint32_t DAT; /* Offset: 0x08 I2C Data Register */
sahilmgandhi 18:6a4db94011d3 4993 __I uint32_t STATUS; /* Offset: 0x0C I2C Status Register */
sahilmgandhi 18:6a4db94011d3 4994 __IO uint32_t CLKDIV; /* Offset: 0x10 I2C Clock Divided Register */
sahilmgandhi 18:6a4db94011d3 4995 __IO uint32_t TOCTL; /* Offset: 0x14 I2C Time-out Control Register */
sahilmgandhi 18:6a4db94011d3 4996 __IO uint32_t ADDR1; /* Offset: 0x18 I2C Slave Address Register1 */
sahilmgandhi 18:6a4db94011d3 4997 __IO uint32_t ADDR2; /* Offset: 0x1C I2C Slave Address Register2 */
sahilmgandhi 18:6a4db94011d3 4998 __IO uint32_t ADDR3; /* Offset: 0x20 I2C Slave Address Register3 */
sahilmgandhi 18:6a4db94011d3 4999 __IO uint32_t ADDRMSK0; /* Offset: 0x24 I2C Slave Address Mask Register0 */
sahilmgandhi 18:6a4db94011d3 5000 __IO uint32_t ADDRMSK1; /* Offset: 0x28 I2C Slave Address Mask Register1 */
sahilmgandhi 18:6a4db94011d3 5001 __IO uint32_t ADDRMSK2; /* Offset: 0x2C I2C Slave Address Mask Register2 */
sahilmgandhi 18:6a4db94011d3 5002 __IO uint32_t ADDRMSK3; /* Offset: 0x30 I2C Slave Address Mask Register3 */
sahilmgandhi 18:6a4db94011d3 5003 __I uint32_t RESERVE0[2];
sahilmgandhi 18:6a4db94011d3 5004 __IO uint32_t WKCTL; /* Offset: 0x3C I2C Wake-up Control Register */
sahilmgandhi 18:6a4db94011d3 5005 __IO uint32_t WKSTS; /* Offset: 0x40 I2C Wake-up Status Register */
sahilmgandhi 18:6a4db94011d3 5006 __IO uint32_t BUSCTL; /* Offset: 0x44 I2C Bus Management Control Register */
sahilmgandhi 18:6a4db94011d3 5007 __IO uint32_t BUSTCTL; /* Offset: 0x48 I2C Bus Management Timer Control Register */
sahilmgandhi 18:6a4db94011d3 5008 __IO uint32_t BUSSTS; /* Offset: 0x4C I2C Bus Management Status Register */
sahilmgandhi 18:6a4db94011d3 5009 __IO uint32_t PKTSIZE; /* Offset: 0x50 I2C Packet Error Checking Byte Number Register */
sahilmgandhi 18:6a4db94011d3 5010 __I uint32_t PKTCRC; /* Offset: 0x54 I2C Packet Error Checking Byte Value Register */
sahilmgandhi 18:6a4db94011d3 5011 __IO uint32_t BUSTOUT; /* Offset: 0x58 I2C Bus Management Timer Register */
sahilmgandhi 18:6a4db94011d3 5012 __IO uint32_t CLKTOUT; /* Offset: 0x5C I2C Bus Management Clock Low Timer Register */
sahilmgandhi 18:6a4db94011d3 5013
sahilmgandhi 18:6a4db94011d3 5014 } I2C_T;
sahilmgandhi 18:6a4db94011d3 5015
sahilmgandhi 18:6a4db94011d3 5016
sahilmgandhi 18:6a4db94011d3 5017
sahilmgandhi 18:6a4db94011d3 5018 /**
sahilmgandhi 18:6a4db94011d3 5019 @addtogroup I2C_CONST I2C Bit Field Definition
sahilmgandhi 18:6a4db94011d3 5020 Constant Definitions for I2C Controller
sahilmgandhi 18:6a4db94011d3 5021 @{ */
sahilmgandhi 18:6a4db94011d3 5022
sahilmgandhi 18:6a4db94011d3 5023 #define I2C_CTL_AA_Pos (2) /*!< I2C_T::CTL: AA Position */
sahilmgandhi 18:6a4db94011d3 5024 #define I2C_CTL_AA_Msk (0x1ul << I2C_CTL_AA_Pos) /*!< I2C_T::CTL: AA Mask */
sahilmgandhi 18:6a4db94011d3 5025
sahilmgandhi 18:6a4db94011d3 5026 #define I2C_CTL_SI_Pos (3) /*!< I2C_T::CTL: SI Position */
sahilmgandhi 18:6a4db94011d3 5027 #define I2C_CTL_SI_Msk (0x1ul << I2C_CTL_SI_Pos) /*!< I2C_T::CTL: SI Mask */
sahilmgandhi 18:6a4db94011d3 5028
sahilmgandhi 18:6a4db94011d3 5029 #define I2C_CTL_STO_Pos (4) /*!< I2C_T::CTL: STO Position */
sahilmgandhi 18:6a4db94011d3 5030 #define I2C_CTL_STO_Msk (0x1ul << I2C_CTL_STO_Pos) /*!< I2C_T::CTL: STO Mask */
sahilmgandhi 18:6a4db94011d3 5031
sahilmgandhi 18:6a4db94011d3 5032 #define I2C_CTL_STA_Pos (5) /*!< I2C_T::CTL: STA Position */
sahilmgandhi 18:6a4db94011d3 5033 #define I2C_CTL_STA_Msk (0x1ul << I2C_CTL_STA_Pos) /*!< I2C_T::CTL: STA Mask */
sahilmgandhi 18:6a4db94011d3 5034
sahilmgandhi 18:6a4db94011d3 5035 #define I2C_CTL_I2CEN_Pos (6) /*!< I2C_T::CTL: I2CEN Position */
sahilmgandhi 18:6a4db94011d3 5036 #define I2C_CTL_I2CEN_Msk (0x1ul << I2C_CTL_I2CEN_Pos) /*!< I2C_T::CTL: I2CEN Mask */
sahilmgandhi 18:6a4db94011d3 5037
sahilmgandhi 18:6a4db94011d3 5038 #define I2C_CTL_INTEN_Pos (7) /*!< I2C_T::CTL: INTEN Position */
sahilmgandhi 18:6a4db94011d3 5039 #define I2C_CTL_INTEN_Msk (0x1ul << I2C_CTL_INTEN_Pos) /*!< I2C_T::CTL: INTEN Mask */
sahilmgandhi 18:6a4db94011d3 5040
sahilmgandhi 18:6a4db94011d3 5041 #define I2C_ADDR0_GC_Pos (0) /*!< I2C_T::ADDR0: GC Position */
sahilmgandhi 18:6a4db94011d3 5042 #define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) /*!< I2C_T::ADDR0: GC Mask */
sahilmgandhi 18:6a4db94011d3 5043
sahilmgandhi 18:6a4db94011d3 5044 #define I2C_ADDR0_ADDR_Pos (1) /*!< I2C_T::ADDR0: ADDR Position */
sahilmgandhi 18:6a4db94011d3 5045 #define I2C_ADDR0_ADDR_Msk (0x7ful << I2C_ADDR0_ADDR_Pos) /*!< I2C_T::ADDR0: ADDR Mask */
sahilmgandhi 18:6a4db94011d3 5046
sahilmgandhi 18:6a4db94011d3 5047 #define I2C_DAT_DAT_Pos (0) /*!< I2C_T::DAT: DAT Position */
sahilmgandhi 18:6a4db94011d3 5048 #define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) /*!< I2C_T::DAT: DAT Mask */
sahilmgandhi 18:6a4db94011d3 5049
sahilmgandhi 18:6a4db94011d3 5050 #define I2C_STATUS_STATUS_Pos (0) /*!< I2C_T::STATUS: STATUS Position */
sahilmgandhi 18:6a4db94011d3 5051 #define I2C_STATUS_STATUS_Msk (0xfful << I2C_STATUS_STATUS_Pos) /*!< I2C_T::STATUS: STATUS Mask */
sahilmgandhi 18:6a4db94011d3 5052
sahilmgandhi 18:6a4db94011d3 5053 #define I2C_CLKDIV_DIVIDER_Pos (0) /*!< I2C_T::CLKDIV: DIVIDER Position */
sahilmgandhi 18:6a4db94011d3 5054 #define I2C_CLKDIV_DIVIDER_Msk (0xfful << I2C_CLKDIV_DIVIDER_Pos) /*!< I2C_T::CLKDIV: DIVIDER Mask */
sahilmgandhi 18:6a4db94011d3 5055
sahilmgandhi 18:6a4db94011d3 5056 #define I2C_TOCTL_TOIF_Pos (0) /*!< I2C_T::TOCTL: TOIF Position */
sahilmgandhi 18:6a4db94011d3 5057 #define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) /*!< I2C_T::TOCTL: TOIF Mask */
sahilmgandhi 18:6a4db94011d3 5058
sahilmgandhi 18:6a4db94011d3 5059 #define I2C_TOCTL_TOCDIV4_Pos (1) /*!< I2C_T::TOCTL: TOCDIV4 Position */
sahilmgandhi 18:6a4db94011d3 5060 #define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) /*!< I2C_T::TOCTL: TOCDIV4 Mask */
sahilmgandhi 18:6a4db94011d3 5061
sahilmgandhi 18:6a4db94011d3 5062 #define I2C_TOCTL_TOCEN_Pos (2) /*!< I2C_T::TOCTL: TOCEN Position */
sahilmgandhi 18:6a4db94011d3 5063 #define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) /*!< I2C_T::TOCTL: TOCEN Mask */
sahilmgandhi 18:6a4db94011d3 5064
sahilmgandhi 18:6a4db94011d3 5065 #define I2C_ADDR1_GC_Pos (0) /*!< I2C_T::ADDR1: GC Position */
sahilmgandhi 18:6a4db94011d3 5066 #define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) /*!< I2C_T::ADDR1: GC Mask */
sahilmgandhi 18:6a4db94011d3 5067
sahilmgandhi 18:6a4db94011d3 5068 #define I2C_ADDR1_ADDR_Pos (1) /*!< I2C_T::ADDR1: ADDR Position */
sahilmgandhi 18:6a4db94011d3 5069 #define I2C_ADDR1_ADDR_Msk (0x7ful << I2C_ADDR1_ADDR_Pos) /*!< I2C_T::ADDR1: ADDR Mask */
sahilmgandhi 18:6a4db94011d3 5070
sahilmgandhi 18:6a4db94011d3 5071 #define I2C_ADDR2_GC_Pos (0) /*!< I2C_T::ADDR2: GC Position */
sahilmgandhi 18:6a4db94011d3 5072 #define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) /*!< I2C_T::ADDR2: GC Mask */
sahilmgandhi 18:6a4db94011d3 5073
sahilmgandhi 18:6a4db94011d3 5074 #define I2C_ADDR2_ADDR_Pos (1) /*!< I2C_T::ADDR2: ADDR Position */
sahilmgandhi 18:6a4db94011d3 5075 #define I2C_ADDR2_ADDR_Msk (0x7ful << I2C_ADDR2_ADDR_Pos) /*!< I2C_T::ADDR2: ADDR Mask */
sahilmgandhi 18:6a4db94011d3 5076
sahilmgandhi 18:6a4db94011d3 5077 #define I2C_ADDR3_GC_Pos (0) /*!< I2C_T::ADDR3: GC Position */
sahilmgandhi 18:6a4db94011d3 5078 #define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) /*!< I2C_T::ADDR3: GC Mask */
sahilmgandhi 18:6a4db94011d3 5079
sahilmgandhi 18:6a4db94011d3 5080 #define I2C_ADDR3_ADDR_Pos (1) /*!< I2C_T::ADDR3: ADDR Position */
sahilmgandhi 18:6a4db94011d3 5081 #define I2C_ADDR3_ADDR_Msk (0x7ful << I2C_ADDR3_ADDR_Pos) /*!< I2C_T::ADDR3: ADDR Mask */
sahilmgandhi 18:6a4db94011d3 5082
sahilmgandhi 18:6a4db94011d3 5083 #define I2C_ADDRMSK0_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK0: ADDRMSK Position */
sahilmgandhi 18:6a4db94011d3 5084 #define I2C_ADDRMSK0_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK0_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK0: ADDRMSK Mask */
sahilmgandhi 18:6a4db94011d3 5085
sahilmgandhi 18:6a4db94011d3 5086 #define I2C_ADDRMSK1_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK1: ADDRMSK Position */
sahilmgandhi 18:6a4db94011d3 5087 #define I2C_ADDRMSK1_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK1_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK1: ADDRMSK Mask */
sahilmgandhi 18:6a4db94011d3 5088
sahilmgandhi 18:6a4db94011d3 5089 #define I2C_ADDRMSK2_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK2: ADDRMSK Position */
sahilmgandhi 18:6a4db94011d3 5090 #define I2C_ADDRMSK2_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK2_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK2: ADDRMSK Mask */
sahilmgandhi 18:6a4db94011d3 5091
sahilmgandhi 18:6a4db94011d3 5092 #define I2C_ADDRMSK3_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK3: ADDRMSK Position */
sahilmgandhi 18:6a4db94011d3 5093 #define I2C_ADDRMSK3_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK3_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK3: ADDRMSK Mask */
sahilmgandhi 18:6a4db94011d3 5094
sahilmgandhi 18:6a4db94011d3 5095 #define I2C_WKCTL_WKEN_Pos (0) /*!< I2C_T::WKCTL: WKEN Position */
sahilmgandhi 18:6a4db94011d3 5096 #define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) /*!< I2C_T::WKCTL: WKEN Mask */
sahilmgandhi 18:6a4db94011d3 5097
sahilmgandhi 18:6a4db94011d3 5098 #define I2C_WKSTS_WKIF_Pos (0) /*!< I2C_T::WKSTS: WKIF Position */
sahilmgandhi 18:6a4db94011d3 5099 #define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /*!< I2C_T::WKSTS: WKIF Mask */
sahilmgandhi 18:6a4db94011d3 5100
sahilmgandhi 18:6a4db94011d3 5101 #define I2C_BUSCTL_ACKMEN_Pos (0) /*!< I2C_T::BUSCTL: ACKMEN Position */
sahilmgandhi 18:6a4db94011d3 5102 #define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos) /*!< I2C_T::BUSCTL: ACKMEN Mask */
sahilmgandhi 18:6a4db94011d3 5103
sahilmgandhi 18:6a4db94011d3 5104 #define I2C_BUSCTL_PECEN_Pos (1) /*!< I2C_T::BUSCTL: PECEN Position */
sahilmgandhi 18:6a4db94011d3 5105 #define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos) /*!< I2C_T::BUSCTL: PECEN Mask */
sahilmgandhi 18:6a4db94011d3 5106
sahilmgandhi 18:6a4db94011d3 5107 #define I2C_BUSCTL_BMDEN_Pos (2) /*!< I2C_T::BUSCTL: BMDEN Position */
sahilmgandhi 18:6a4db94011d3 5108 #define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos) /*!< I2C_T::BUSCTL: BMDEN Mask */
sahilmgandhi 18:6a4db94011d3 5109
sahilmgandhi 18:6a4db94011d3 5110 #define I2C_BUSCTL_BMHEN_Pos (3) /*!< I2C_T::BUSCTL: BMHEN Position */
sahilmgandhi 18:6a4db94011d3 5111 #define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos) /*!< I2C_T::BUSCTL: BMHEN Mask */
sahilmgandhi 18:6a4db94011d3 5112
sahilmgandhi 18:6a4db94011d3 5113 #define I2C_BUSCTL_ALERTEN_Pos (4) /*!< I2C_T::BUSCTL: ALERTEN Position */
sahilmgandhi 18:6a4db94011d3 5114 #define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos) /*!< I2C_T::BUSCTL: ALERTEN Mask */
sahilmgandhi 18:6a4db94011d3 5115
sahilmgandhi 18:6a4db94011d3 5116 #define I2C_BUSCTL_SCTLOSTS_Pos (5) /*!< I2C_T::BUSCTL: SCTLOSTS Position */
sahilmgandhi 18:6a4db94011d3 5117 #define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos) /*!< I2C_T::BUSCTL: SCTLOSTS Mask */
sahilmgandhi 18:6a4db94011d3 5118
sahilmgandhi 18:6a4db94011d3 5119 #define I2C_BUSCTL_SCTLOEN_Pos (6) /*!< I2C_T::BUSCTL: SCTLOEN Position */
sahilmgandhi 18:6a4db94011d3 5120 #define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos) /*!< I2C_T::BUSCTL: SCTLOEN Mask */
sahilmgandhi 18:6a4db94011d3 5121
sahilmgandhi 18:6a4db94011d3 5122 #define I2C_BUSCTL_BUSEN_Pos (7) /*!< I2C_T::BUSCTL: BUSEN Position */
sahilmgandhi 18:6a4db94011d3 5123 #define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos) /*!< I2C_T::BUSCTL: BUSEN Mask */
sahilmgandhi 18:6a4db94011d3 5124
sahilmgandhi 18:6a4db94011d3 5125 #define I2C_BUSCTL_PECTXEN_Pos (8) /*!< I2C_T::BUSCTL: PECTXEN Position */
sahilmgandhi 18:6a4db94011d3 5126 #define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos) /*!< I2C_T::BUSCTL: PECTXEN Mask */
sahilmgandhi 18:6a4db94011d3 5127
sahilmgandhi 18:6a4db94011d3 5128 #define I2C_BUSCTL_TIDLE_Pos (9) /*!< I2C_T::BUSCTL: TIDLE Position */
sahilmgandhi 18:6a4db94011d3 5129 #define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos) /*!< I2C_T::BUSCTL: TIDLE Mask */
sahilmgandhi 18:6a4db94011d3 5130
sahilmgandhi 18:6a4db94011d3 5131 #define I2C_BUSCTL_PECCLR_Pos (10) /*!< I2C_T::BUSCTL: PECCLR Position */
sahilmgandhi 18:6a4db94011d3 5132 #define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos) /*!< I2C_T::BUSCTL: PECCLR Mask */
sahilmgandhi 18:6a4db94011d3 5133
sahilmgandhi 18:6a4db94011d3 5134 #define I2C_BUSCTL_ACKM9SI_Pos (11) /*!< I2C_T::BUSCTL: ACKM9SI Position */
sahilmgandhi 18:6a4db94011d3 5135 #define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos) /*!< I2C_T::BUSCTL: ACKM9SI Mask */
sahilmgandhi 18:6a4db94011d3 5136
sahilmgandhi 18:6a4db94011d3 5137 #define I2C_BUSTCTL_BUSTOEN_Pos (0) /*!< I2C_T::BUSTCTL: BUSTOEN Position */
sahilmgandhi 18:6a4db94011d3 5138 #define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOEN Mask */
sahilmgandhi 18:6a4db94011d3 5139
sahilmgandhi 18:6a4db94011d3 5140 #define I2C_BUSTCTL_CLKTOEN_Pos (1) /*!< I2C_T::BUSTCTL: CLKTOEN Position */
sahilmgandhi 18:6a4db94011d3 5141 #define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOEN Mask */
sahilmgandhi 18:6a4db94011d3 5142
sahilmgandhi 18:6a4db94011d3 5143 #define I2C_BUSTCTL_BUSTOIEN_Pos (2) /*!< I2C_T::BUSTCTL: BUSTOIEN Position */
sahilmgandhi 18:6a4db94011d3 5144 #define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOIEN Mask */
sahilmgandhi 18:6a4db94011d3 5145
sahilmgandhi 18:6a4db94011d3 5146 #define I2C_BUSTCTL_CLKTOIEN_Pos (3) /*!< I2C_T::BUSTCTL: CLKTOIEN Position */
sahilmgandhi 18:6a4db94011d3 5147 #define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOIEN Mask */
sahilmgandhi 18:6a4db94011d3 5148
sahilmgandhi 18:6a4db94011d3 5149 #define I2C_BUSTCTL_TORSTEN_Pos (4) /*!< I2C_T::BUSTCTL: TORSTEN Position */
sahilmgandhi 18:6a4db94011d3 5150 #define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos) /*!< I2C_T::BUSTCTL: TORSTEN Mask */
sahilmgandhi 18:6a4db94011d3 5151
sahilmgandhi 18:6a4db94011d3 5152 #define I2C_BUSTCTL_PECIEN_Pos (5) /*!< I2C_T::BUSTCTL: PECIEN Position */
sahilmgandhi 18:6a4db94011d3 5153 #define I2C_BUSTCTL_PECIEN_Msk (0x1ul << I2C_BUSTCTL_PECIEN_Pos) /*!< I2C_T::BUSTCTL: PECIEN Mask */
sahilmgandhi 18:6a4db94011d3 5154
sahilmgandhi 18:6a4db94011d3 5155 #define I2C_BUSSTS_BUSY_Pos (0) /*!< I2C_T::BUSSTS: BUSY Position */
sahilmgandhi 18:6a4db94011d3 5156 #define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos) /*!< I2C_T::BUSSTS: BUSY Mask */
sahilmgandhi 18:6a4db94011d3 5157
sahilmgandhi 18:6a4db94011d3 5158 #define I2C_BUSSTS_BCDONE_Pos (1) /*!< I2C_T::BUSSTS: BCDONE Position */
sahilmgandhi 18:6a4db94011d3 5159 #define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos) /*!< I2C_T::BUSSTS: BCDONE Mask */
sahilmgandhi 18:6a4db94011d3 5160
sahilmgandhi 18:6a4db94011d3 5161 #define I2C_BUSSTS_PECERR_Pos (2) /*!< I2C_T::BUSSTS: PECERR Position */
sahilmgandhi 18:6a4db94011d3 5162 #define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos) /*!< I2C_T::BUSSTS: PECERR Mask */
sahilmgandhi 18:6a4db94011d3 5163
sahilmgandhi 18:6a4db94011d3 5164 #define I2C_BUSSTS_ALERT_Pos (3) /*!< I2C_T::BUSSTS: ALERT Position */
sahilmgandhi 18:6a4db94011d3 5165 #define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos) /*!< I2C_T::BUSSTS: ALERT Mask */
sahilmgandhi 18:6a4db94011d3 5166
sahilmgandhi 18:6a4db94011d3 5167 #define I2C_BUSSTS_SCTLDIN_Pos (4) /*!< I2C_T::BUSSTS: SCTLDIN Position */
sahilmgandhi 18:6a4db94011d3 5168 #define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos) /*!< I2C_T::BUSSTS: SCTLDIN Mask */
sahilmgandhi 18:6a4db94011d3 5169
sahilmgandhi 18:6a4db94011d3 5170 #define I2C_BUSSTS_BUSTO_Pos (5) /*!< I2C_T::BUSSTS: BUSTO Position */
sahilmgandhi 18:6a4db94011d3 5171 #define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos) /*!< I2C_T::BUSSTS: BUSTO Mask */
sahilmgandhi 18:6a4db94011d3 5172
sahilmgandhi 18:6a4db94011d3 5173 #define I2C_BUSSTS_CLKTO_Pos (6) /*!< I2C_T::BUSSTS: CLKTO Position */
sahilmgandhi 18:6a4db94011d3 5174 #define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos) /*!< I2C_T::BUSSTS: CLKTO Mask */
sahilmgandhi 18:6a4db94011d3 5175
sahilmgandhi 18:6a4db94011d3 5176 #define I2C_PKTSIZE_PLDSIZE_Pos (0) /*!< I2C_T::PKTSIZE: PLDSIZE Position */
sahilmgandhi 18:6a4db94011d3 5177 #define I2C_PKTSIZE_PLDSIZE_Msk (0xfful << I2C_PKTSIZE_PLDSIZE_Pos) /*!< I2C_T::PKTSIZE: PLDSIZE Mask */
sahilmgandhi 18:6a4db94011d3 5178
sahilmgandhi 18:6a4db94011d3 5179 #define I2C_PKTCRC_PECCRC_Pos (0) /*!< I2C_T::PKTCRC: PECCRC Position */
sahilmgandhi 18:6a4db94011d3 5180 #define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos) /*!< I2C_T::PKTCRC: PECCRC Mask */
sahilmgandhi 18:6a4db94011d3 5181
sahilmgandhi 18:6a4db94011d3 5182 #define I2C_BUSTOUT_BUSTO_Pos (0) /*!< I2C_T::BUSTOUT: BUSTO Position */
sahilmgandhi 18:6a4db94011d3 5183 #define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos) /*!< I2C_T::BUSTOUT: BUSTO Mask */
sahilmgandhi 18:6a4db94011d3 5184
sahilmgandhi 18:6a4db94011d3 5185 #define I2C_CLKTOUT_CLKTO_Pos (0) /*!< I2C_T::CLKTOUT: CLKTO Position */
sahilmgandhi 18:6a4db94011d3 5186 #define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos) /*!< I2C_T::CLKTOUT: CLKTO Mask */
sahilmgandhi 18:6a4db94011d3 5187
sahilmgandhi 18:6a4db94011d3 5188
sahilmgandhi 18:6a4db94011d3 5189 /**@}*/ /* I2C_CONST */
sahilmgandhi 18:6a4db94011d3 5190 /**@}*/ /* end of I2C register group */
sahilmgandhi 18:6a4db94011d3 5191
sahilmgandhi 18:6a4db94011d3 5192 /*---------------------- USB On-The-Go Controller -------------------------*/
sahilmgandhi 18:6a4db94011d3 5193 /**
sahilmgandhi 18:6a4db94011d3 5194 @addtogroup OTG USB On-The-Go Controller(OTG)
sahilmgandhi 18:6a4db94011d3 5195 Memory Mapped Structure for OTG Controller
sahilmgandhi 18:6a4db94011d3 5196 @{ */
sahilmgandhi 18:6a4db94011d3 5197
sahilmgandhi 18:6a4db94011d3 5198
sahilmgandhi 18:6a4db94011d3 5199 typedef struct
sahilmgandhi 18:6a4db94011d3 5200 {
sahilmgandhi 18:6a4db94011d3 5201
sahilmgandhi 18:6a4db94011d3 5202
sahilmgandhi 18:6a4db94011d3 5203 /**
sahilmgandhi 18:6a4db94011d3 5204 * @var OTG_T::CTL
sahilmgandhi 18:6a4db94011d3 5205 * Offset: 0x00 OTG Control Register
sahilmgandhi 18:6a4db94011d3 5206 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5207 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5208 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5209 * |[0] |VBUSDROP |Drop VBUS Control
sahilmgandhi 18:6a4db94011d3 5210 * | | |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS.
sahilmgandhi 18:6a4db94011d3 5211 * | | |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device.
sahilmgandhi 18:6a4db94011d3 5212 * | | |0 = Not drop the VBUS.
sahilmgandhi 18:6a4db94011d3 5213 * | | |1 = Drop the VBUS.
sahilmgandhi 18:6a4db94011d3 5214 * |[1] |BUSREQ |OTG Bus Request
sahilmgandhi 18:6a4db94011d3 5215 * | | |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection.
sahilmgandhi 18:6a4db94011d3 5216 * | | |If user won't use the bus any more, clearing this bit will drop VBUS to save power.
sahilmgandhi 18:6a4db94011d3 5217 * | | |This bit will be cleared when A-device goes to A_wait_vfall state. A_wait_vfall state is defined in OTG specification.
sahilmgandhi 18:6a4db94011d3 5218 * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed.
sahilmgandhi 18:6a4db94011d3 5219 * | | |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol.
sahilmgandhi 18:6a4db94011d3 5220 * | | |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues ARP in specified interval, defined in OTG specification).
sahilmgandhi 18:6a4db94011d3 5221 * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set IDSTS (OTG_STATUS[1]) changed.
sahilmgandhi 18:6a4db94011d3 5222 * | | |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device.
sahilmgandhi 18:6a4db94011d3 5223 * | | |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device.
sahilmgandhi 18:6a4db94011d3 5224 * |[2] |HNPREQEN |OTG HNP Request Enable Bit
sahilmgandhi 18:6a4db94011d3 5225 * | | |When USB frame as A-device, set this bit when A-device allows to process Host Negotiation Protocol.
sahilmgandhi 18:6a4db94011d3 5226 * | | |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state.
sahilmgandhi 18:6a4db94011d3 5227 * | | |When USB frame is as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change.
sahilmgandhi 18:6a4db94011d3 5228 * | | |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state.
sahilmgandhi 18:6a4db94011d3 5229 * | | |0 = HNP request Disabled.
sahilmgandhi 18:6a4db94011d3 5230 * | | |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host).
sahilmgandhi 18:6a4db94011d3 5231 * | | |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state.
sahilmgandhi 18:6a4db94011d3 5232 * |[4] |OTGEN |OTG Function Enable Bit
sahilmgandhi 18:6a4db94011d3 5233 * | | |User needs to set this bit to enable OTG function while USB frame configured as OTG device.
sahilmgandhi 18:6a4db94011d3 5234 * | | |When USB frame not configured as OTG device, this bit is must be low.
sahilmgandhi 18:6a4db94011d3 5235 * | | |0 = OTG function Disabled.
sahilmgandhi 18:6a4db94011d3 5236 * | | |1 = OTG function Enabled.
sahilmgandhi 18:6a4db94011d3 5237 * |[5] |WKEN |OTG ID Pin Wake-Up Enable Bit
sahilmgandhi 18:6a4db94011d3 5238 * | | |0 = OTG ID pin status change wake-up function Disabled.
sahilmgandhi 18:6a4db94011d3 5239 * | | |1 = OTG ID pin status change wake-up function Enabled.
sahilmgandhi 18:6a4db94011d3 5240 * @var OTG_T::PHYCTL
sahilmgandhi 18:6a4db94011d3 5241 * Offset: 0x04 OTG PHY Control Register
sahilmgandhi 18:6a4db94011d3 5242 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5243 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5244 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5245 * |[0] |OTGPHYEN |OTG PHY Enable
sahilmgandhi 18:6a4db94011d3 5246 * | | |When USB frame is configured as OTG-device, user needs to set this bit before using OTG function.
sahilmgandhi 18:6a4db94011d3 5247 * | | |If device is not configured as OTG-device, this bit is "don't care".
sahilmgandhi 18:6a4db94011d3 5248 * | | |0 = OTG PHY Disabled.
sahilmgandhi 18:6a4db94011d3 5249 * | | |1 = OTG PHY Enabled.
sahilmgandhi 18:6a4db94011d3 5250 * |[1] |IDDETEN |ID Detection Enable Bit
sahilmgandhi 18:6a4db94011d3 5251 * | | |0 = Detect ID pin status Disabled.
sahilmgandhi 18:6a4db94011d3 5252 * | | |1 = Detect ID pin status Enabled.
sahilmgandhi 18:6a4db94011d3 5253 * |[4] |VBENPOL |Off-Chip USB VBUS Power Switch Enable Polarity
sahilmgandhi 18:6a4db94011d3 5254 * | | |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need.
sahilmgandhi 18:6a4db94011d3 5255 * | | |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch.
sahilmgandhi 18:6a4db94011d3 5256 * | | |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component.
sahilmgandhi 18:6a4db94011d3 5257 * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
sahilmgandhi 18:6a4db94011d3 5258 * | | |0 = The off-chip USB VBUS power switch enable is active high.
sahilmgandhi 18:6a4db94011d3 5259 * | | |1 = The off-chip USB VBUS power switch enable is active low.
sahilmgandhi 18:6a4db94011d3 5260 * |[5] |VBSTSPOL |Off-Chip USB VBUS Power Switch Status Polarity
sahilmgandhi 18:6a4db94011d3 5261 * | | |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component.
sahilmgandhi 18:6a4db94011d3 5262 * | | |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch.
sahilmgandhi 18:6a4db94011d3 5263 * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
sahilmgandhi 18:6a4db94011d3 5264 * | | |0 = The polarity of off-chip USB VBUS power switch valid status is high.
sahilmgandhi 18:6a4db94011d3 5265 * | | |1 = The polarity of off-chip USB VBUS power switch valid status is low.
sahilmgandhi 18:6a4db94011d3 5266 * @var OTG_T::INTEN
sahilmgandhi 18:6a4db94011d3 5267 * Offset: 0x08 OTG Interrupt Enable Register
sahilmgandhi 18:6a4db94011d3 5268 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5269 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5270 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5271 * |[0] |ROLECHGIEN|Role (Host Or Peripheral) Changed Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 5272 * | | |0 = Interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 5273 * | | |1 = Interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 5274 * |[1] |VBEIEN |VBUS Error Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 5275 * | | |0 = Interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 5276 * | | |1 = Interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 5277 * | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec.
sahilmgandhi 18:6a4db94011d3 5278 * |[2] |SRPFIEN |SRP Fail Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 5279 * | | |0 = Interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 5280 * | | |1 = Interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 5281 * |[3] |HNPFIEN |HNP Fail Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 5282 * | | |0 = Interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 5283 * | | |1 = Interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 5284 * |[4] |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 5285 * | | |0 = Interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 5286 * | | |1 = Interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 5287 * | | |Note: Going to idle state means going to a_idle or b_idle state.
sahilmgandhi 18:6a4db94011d3 5288 * | | |Please refer to A-device state diagram and B-device state diagram in OTG spec.
sahilmgandhi 18:6a4db94011d3 5289 * |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 5290 * | | |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, a interrupt will be asserted.
sahilmgandhi 18:6a4db94011d3 5291 * | | |0 = Interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 5292 * | | |1 = Interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 5293 * |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 5294 * | | |If this bit is set to 1 and the device is changed as a peripheral, a interrupt will be asserted.
sahilmgandhi 18:6a4db94011d3 5295 * | | |0 = This device as a peripheral interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 5296 * | | |1 = This device as a peripheral interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 5297 * |[7] |HOSTIEN |Act As Host Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 5298 * | | |If this bit is set to 1 and the device is changed as a host, a interrupt will be asserted.
sahilmgandhi 18:6a4db94011d3 5299 * | | |0 = This device as a host interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 5300 * | | |1 = This device as a host interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 5301 * |[8] |BVLDCHGIEN|B-Device Session Valid Status Changed Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 5302 * | | |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, a interrupt will be asserted.
sahilmgandhi 18:6a4db94011d3 5303 * | | |0 = Interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 5304 * | | |1 = Interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 5305 * |[9] |AVLDCHGIEN|A-Device Session Valid Status Changed Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 5306 * | | |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, a interrupt will be asserted.
sahilmgandhi 18:6a4db94011d3 5307 * | | |0 = Interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 5308 * | | |1 = Interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 5309 * |[10] |VBCHGIEN |VBUSVLD Status Changed
sahilmgandhi 18:6a4db94011d3 5310 * | | |Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 5311 * | | |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, a interrupt will be asserted.
sahilmgandhi 18:6a4db94011d3 5312 * | | |0 = Interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 5313 * | | |1 = Interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 5314 * |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 5315 * | | |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, a interrupt will be asserted.
sahilmgandhi 18:6a4db94011d3 5316 * | | |0 = Interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 5317 * | | |1 = Interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 5318 * |[13] |SRPDETIEN |SRP Detected Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 5319 * | | |0 = Interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 5320 * | | |1 = Interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 5321 * @var OTG_T::INTSTS
sahilmgandhi 18:6a4db94011d3 5322 * Offset: 0x0C OTG Interrupt Status Register
sahilmgandhi 18:6a4db94011d3 5323 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5324 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5325 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5326 * |[0] |ROLECHGIF |OTG Role Change Interrupt Status
sahilmgandhi 18:6a4db94011d3 5327 * | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change.
sahilmgandhi 18:6a4db94011d3 5328 * | | |0 = OTG device role not changed.
sahilmgandhi 18:6a4db94011d3 5329 * | | |1 = OTG device role changed.
sahilmgandhi 18:6a4db94011d3 5330 * | | |Note: Write 1 to clear this flag.
sahilmgandhi 18:6a4db94011d3 5331 * |[1] |VBEIF |VBUS Error Interrupt Status
sahilmgandhi 18:6a4db94011d3 5332 * | | |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high.
sahilmgandhi 18:6a4db94011d3 5333 * | | |0 = OTG A-device drives VBUS over threshold voltage before this interval expires.
sahilmgandhi 18:6a4db94011d3 5334 * | | |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires.
sahilmgandhi 18:6a4db94011d3 5335 * | | |Note: Write 1 to clear this flag and recover from the VBUS error state.
sahilmgandhi 18:6a4db94011d3 5336 * |[2] |SRPFIF |SRP Fail Interrupt Status
sahilmgandhi 18:6a4db94011d3 5337 * | | |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification.
sahilmgandhi 18:6a4db94011d3 5338 * | | |This flag is set when the OTG B-device does not get VBUS high after this interval.
sahilmgandhi 18:6a4db94011d3 5339 * | | |0 = OTG B-device gets VBUS high before this interval.
sahilmgandhi 18:6a4db94011d3 5340 * | | |1 = OTG B-device does not get VBUS high before this interval.
sahilmgandhi 18:6a4db94011d3 5341 * | | |Note: Write 1 to clear this flag.
sahilmgandhi 18:6a4db94011d3 5342 * |[3] |HNPFIF |HNP Fail Interrupt Status
sahilmgandhi 18:6a4db94011d3 5343 * | | |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires.
sahilmgandhi 18:6a4db94011d3 5344 * | | |0 = A-device connects to B-device before specified interval expires.
sahilmgandhi 18:6a4db94011d3 5345 * | | |1 = A-device does not connect to B-device before specified interval expires.
sahilmgandhi 18:6a4db94011d3 5346 * | | |Note: Write 1 to clear this flag.
sahilmgandhi 18:6a4db94011d3 5347 * |[4] |GOIDLEIF |OTG Device Goes to IDLE Interrupt Status
sahilmgandhi 18:6a4db94011d3 5348 * | | |Flag is set if the OTG device transfers from non-idle state to idle state.
sahilmgandhi 18:6a4db94011d3 5349 * | | |The OTG device will be neither a host nor a peripheral.
sahilmgandhi 18:6a4db94011d3 5350 * | | |0 = OTG device does not go back to idle state (a_idle or b_idle).
sahilmgandhi 18:6a4db94011d3 5351 * | | |1 = OTG device goes back to idle state (a_idle or b_idle).
sahilmgandhi 18:6a4db94011d3 5352 * | | |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification for the details of a_idle state and b_idle state.
sahilmgandhi 18:6a4db94011d3 5353 * | | |Note 2: Write 1 to clear this flag.
sahilmgandhi 18:6a4db94011d3 5354 * |[5] |IDCHGIF |ID State Change Interrupt Status
sahilmgandhi 18:6a4db94011d3 5355 * | | |0 = IDSTS (OTG_STATUS[1]) not toggled.
sahilmgandhi 18:6a4db94011d3 5356 * | | |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high.
sahilmgandhi 18:6a4db94011d3 5357 * | | |Note: Write 1 to clear this flag.
sahilmgandhi 18:6a4db94011d3 5358 * |[6] |PDEVIF |Act As Peripheral Interrupt Status
sahilmgandhi 18:6a4db94011d3 5359 * | | |0 = This device does not act as a peripheral.
sahilmgandhi 18:6a4db94011d3 5360 * | | |1 = This device acts as a peripheral.
sahilmgandhi 18:6a4db94011d3 5361 * | | |Note: Write 1 to clear this flag.
sahilmgandhi 18:6a4db94011d3 5362 * |[7] |HOSTIF |Act As Host Interrupt Status
sahilmgandhi 18:6a4db94011d3 5363 * | | |0 = This device does not act as a host.
sahilmgandhi 18:6a4db94011d3 5364 * | | |1 = This device acts as a host.
sahilmgandhi 18:6a4db94011d3 5365 * | | |Note: Write 1 to clear this flag.
sahilmgandhi 18:6a4db94011d3 5366 * |[8] |BVLDCHGIF |B-Device Session Valid State Change Interrupt Status
sahilmgandhi 18:6a4db94011d3 5367 * | | |0 = BVLD (OTG_STATUS[3]) is not toggled.
sahilmgandhi 18:6a4db94011d3 5368 * | | |1 = BVLD (OTG_STATUS[3]) from high to low or low to high.
sahilmgandhi 18:6a4db94011d3 5369 * | | |Note: Write 1 to clear this status.
sahilmgandhi 18:6a4db94011d3 5370 * |[9] |AVLDCHGIF |A-Device Session Valid State Change Interrupt Status
sahilmgandhi 18:6a4db94011d3 5371 * | | |0 = AVLD (OTG_STATUS[4]) not toggled.
sahilmgandhi 18:6a4db94011d3 5372 * | | |1 = AVLD (OTG_STATUS[4]) from high to low or low to high.
sahilmgandhi 18:6a4db94011d3 5373 * | | |Note: Write 1 to clear this status.
sahilmgandhi 18:6a4db94011d3 5374 * |[10] |VBCHGIF |VBUSVLD State Change Interrupt Status
sahilmgandhi 18:6a4db94011d3 5375 * | | |0 = VBUSVLD (OTG_STATUS[5]) not toggled.
sahilmgandhi 18:6a4db94011d3 5376 * | | |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high.
sahilmgandhi 18:6a4db94011d3 5377 * | | |Note: Write 1 to clear this status.
sahilmgandhi 18:6a4db94011d3 5378 * |[11] |SECHGIF |SESSEND State Change Interrupt Status
sahilmgandhi 18:6a4db94011d3 5379 * | | |0 = SESSEND (OTG_STATUS[2]) not toggled.
sahilmgandhi 18:6a4db94011d3 5380 * | | |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high.
sahilmgandhi 18:6a4db94011d3 5381 * | | |Note: Write 1 to clear this flag.
sahilmgandhi 18:6a4db94011d3 5382 * |[13] |SRPDETIF |SRP Detected Interrupt Status
sahilmgandhi 18:6a4db94011d3 5383 * | | |0 = SRP not detected.
sahilmgandhi 18:6a4db94011d3 5384 * | | |1 = SRP detected.
sahilmgandhi 18:6a4db94011d3 5385 * | | |Note: Write 1 to clear this status.
sahilmgandhi 18:6a4db94011d3 5386 * @var OTG_T::STATUS
sahilmgandhi 18:6a4db94011d3 5387 * Offset: 0x10 OTG Status Register
sahilmgandhi 18:6a4db94011d3 5388 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5389 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5390 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5391 * |[0] |OVERCUR |Over Current Condition
sahilmgandhi 18:6a4db94011d3 5392 * | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high.
sahilmgandhi 18:6a4db94011d3 5393 * | | |0 = OTG A-device drives VBUS successfully.
sahilmgandhi 18:6a4db94011d3 5394 * | | |1 = OTG A-device cannot drives VBUS high in this interval.
sahilmgandhi 18:6a4db94011d3 5395 * |[1] |IDSTS |USB_ID Pin State Of Mini-B/Micro-Plug
sahilmgandhi 18:6a4db94011d3 5396 * | | |0 = Mini-A/Micro-A plug is attached.
sahilmgandhi 18:6a4db94011d3 5397 * | | |1 = Mini-B/Micro-B plug is attached.
sahilmgandhi 18:6a4db94011d3 5398 * |[2] |SESSEND |Session End Status
sahilmgandhi 18:6a4db94011d3 5399 * | | |When VBUS voltage is lower than 0.4V, this bit will be set to 1.
sahilmgandhi 18:6a4db94011d3 5400 * | | |Session end means no meaningful power on VBUS.
sahilmgandhi 18:6a4db94011d3 5401 * | | |0 = Session is not end.
sahilmgandhi 18:6a4db94011d3 5402 * | | |1 = Session is end.
sahilmgandhi 18:6a4db94011d3 5403 * |[3] |BVLD |B-Device Session Valid Status
sahilmgandhi 18:6a4db94011d3 5404 * | | |0 = B-device session is not valid.
sahilmgandhi 18:6a4db94011d3 5405 * | | |1 = B-device session is valid.
sahilmgandhi 18:6a4db94011d3 5406 * |[4] |AVLD |A-Device Session Valid Status
sahilmgandhi 18:6a4db94011d3 5407 * | | |0 = A-device session is not valid.
sahilmgandhi 18:6a4db94011d3 5408 * | | |1 = A-device session is valid.
sahilmgandhi 18:6a4db94011d3 5409 * |[5] |VBUSVLD |VBUS Valid Status
sahilmgandhi 18:6a4db94011d3 5410 * | | |When VBUS is larger than 4.7V, this bit will be set to 1.
sahilmgandhi 18:6a4db94011d3 5411 * | | |0 = VBUS is not valid.
sahilmgandhi 18:6a4db94011d3 5412 * | | |1 = VBUS is valid.
sahilmgandhi 18:6a4db94011d3 5413 */
sahilmgandhi 18:6a4db94011d3 5414
sahilmgandhi 18:6a4db94011d3 5415 __IO uint32_t CTL; /* Offset: 0x00 OTG Control Register */
sahilmgandhi 18:6a4db94011d3 5416 __IO uint32_t PHYCTL; /* Offset: 0x04 OTG PHY Control Register */
sahilmgandhi 18:6a4db94011d3 5417 __IO uint32_t INTEN; /* Offset: 0x08 OTG Interrupt Enable Register */
sahilmgandhi 18:6a4db94011d3 5418 __IO uint32_t INTSTS; /* Offset: 0x0C OTG Interrupt Status Register */
sahilmgandhi 18:6a4db94011d3 5419 __I uint32_t STATUS; /* Offset: 0x10 OTG Status Register */
sahilmgandhi 18:6a4db94011d3 5420
sahilmgandhi 18:6a4db94011d3 5421 } OTG_T;
sahilmgandhi 18:6a4db94011d3 5422
sahilmgandhi 18:6a4db94011d3 5423
sahilmgandhi 18:6a4db94011d3 5424
sahilmgandhi 18:6a4db94011d3 5425 /**
sahilmgandhi 18:6a4db94011d3 5426 @addtogroup OTG_CONST OTG Bit Field Definition
sahilmgandhi 18:6a4db94011d3 5427 Constant Definitions for OTG Controller
sahilmgandhi 18:6a4db94011d3 5428 @{ */
sahilmgandhi 18:6a4db94011d3 5429
sahilmgandhi 18:6a4db94011d3 5430 #define OTG_CTL_VBUSDROP_Pos (0) /*!< OTG_T::CTL: VBUSDROP Position */
sahilmgandhi 18:6a4db94011d3 5431 #define OTG_CTL_VBUSDROP_Msk (0x1ul << OTG_CTL_VBUSDROP_Pos) /*!< OTG_T::CTL: VBUSDROP Mask */
sahilmgandhi 18:6a4db94011d3 5432
sahilmgandhi 18:6a4db94011d3 5433 #define OTG_CTL_BUSREQ_Pos (1) /*!< OTG_T::CTL: BUSREQ Position */
sahilmgandhi 18:6a4db94011d3 5434 #define OTG_CTL_BUSREQ_Msk (0x1ul << OTG_CTL_BUSREQ_Pos) /*!< OTG_T::CTL: BUSREQ Mask */
sahilmgandhi 18:6a4db94011d3 5435
sahilmgandhi 18:6a4db94011d3 5436 #define OTG_CTL_HNPREQEN_Pos (2) /*!< OTG_T::CTL: HNPREQEN Position */
sahilmgandhi 18:6a4db94011d3 5437 #define OTG_CTL_HNPREQEN_Msk (0x1ul << OTG_CTL_HNPREQEN_Pos) /*!< OTG_T::CTL: HNPREQEN Mask */
sahilmgandhi 18:6a4db94011d3 5438
sahilmgandhi 18:6a4db94011d3 5439 #define OTG_CTL_OTGEN_Pos (4) /*!< OTG_T::CTL: OTGEN Position */
sahilmgandhi 18:6a4db94011d3 5440 #define OTG_CTL_OTGEN_Msk (0x1ul << OTG_CTL_OTGEN_Pos) /*!< OTG_T::CTL: OTGEN Mask */
sahilmgandhi 18:6a4db94011d3 5441
sahilmgandhi 18:6a4db94011d3 5442 #define OTG_CTL_WKEN_Pos (5) /*!< OTG_T::CTL: WKEN Position */
sahilmgandhi 18:6a4db94011d3 5443 #define OTG_CTL_WKEN_Msk (0x1ul << OTG_CTL_WKEN_Pos) /*!< OTG_T::CTL: WKEN Mask */
sahilmgandhi 18:6a4db94011d3 5444
sahilmgandhi 18:6a4db94011d3 5445 #define OTG_PHYCTL_OTGPHYEN_Pos (0) /*!< OTG_T::PHYCTL: OTGPHYEN Position */
sahilmgandhi 18:6a4db94011d3 5446 #define OTG_PHYCTL_OTGPHYEN_Msk (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos) /*!< OTG_T::PHYCTL: OTGPHYEN Mask */
sahilmgandhi 18:6a4db94011d3 5447
sahilmgandhi 18:6a4db94011d3 5448 #define OTG_PHYCTL_IDDETEN_Pos (1) /*!< OTG_T::PHYCTL: IDDETEN Position */
sahilmgandhi 18:6a4db94011d3 5449 #define OTG_PHYCTL_IDDETEN_Msk (0x1ul << OTG_PHYCTL_IDDETEN_Pos) /*!< OTG_T::PHYCTL: IDDETEN Mask */
sahilmgandhi 18:6a4db94011d3 5450
sahilmgandhi 18:6a4db94011d3 5451 #define OTG_PHYCTL_VBENPOL_Pos (4) /*!< OTG_T::PHYCTL: VBENPOL Position */
sahilmgandhi 18:6a4db94011d3 5452 #define OTG_PHYCTL_VBENPOL_Msk (0x1ul << OTG_PHYCTL_VBENPOL_Pos) /*!< OTG_T::PHYCTL: VBENPOL Mask */
sahilmgandhi 18:6a4db94011d3 5453
sahilmgandhi 18:6a4db94011d3 5454 #define OTG_PHYCTL_VBSTSPOL_Pos (5) /*!< OTG_T::PHYCTL: VBSTSPOL Position */
sahilmgandhi 18:6a4db94011d3 5455 #define OTG_PHYCTL_VBSTSPOL_Msk (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos) /*!< OTG_T::PHYCTL: VBSTSPOL Mask */
sahilmgandhi 18:6a4db94011d3 5456
sahilmgandhi 18:6a4db94011d3 5457 #define OTG_INTEN_ROLECHGIEN_Pos (0) /*!< OTG_T::INTEN: ROLECHGIEN Position */
sahilmgandhi 18:6a4db94011d3 5458 #define OTG_INTEN_ROLECHGIEN_Msk (0x1ul << OTG_INTEN_ROLECHGIEN_Pos) /*!< OTG_T::INTEN: ROLECHGIEN Mask */
sahilmgandhi 18:6a4db94011d3 5459
sahilmgandhi 18:6a4db94011d3 5460 #define OTG_INTEN_VBEIEN_Pos (1) /*!< OTG_T::INTEN: VBEIEN Position */
sahilmgandhi 18:6a4db94011d3 5461 #define OTG_INTEN_VBEIEN_Msk (0x1ul << OTG_INTEN_VBEIEN_Pos) /*!< OTG_T::INTEN: VBEIEN Mask */
sahilmgandhi 18:6a4db94011d3 5462
sahilmgandhi 18:6a4db94011d3 5463 #define OTG_INTEN_SRPFIEN_Pos (2) /*!< OTG_T::INTEN: SRPFIEN Position */
sahilmgandhi 18:6a4db94011d3 5464 #define OTG_INTEN_SRPFIEN_Msk (0x1ul << OTG_INTEN_SRPFIEN_Pos) /*!< OTG_T::INTEN: SRPFIEN Mask */
sahilmgandhi 18:6a4db94011d3 5465
sahilmgandhi 18:6a4db94011d3 5466 #define OTG_INTEN_HNPFIEN_Pos (3) /*!< OTG_T::INTEN: HNPFIEN Position */
sahilmgandhi 18:6a4db94011d3 5467 #define OTG_INTEN_HNPFIEN_Msk (0x1ul << OTG_INTEN_HNPFIEN_Pos) /*!< OTG_T::INTEN: HNPFIEN Mask */
sahilmgandhi 18:6a4db94011d3 5468
sahilmgandhi 18:6a4db94011d3 5469 #define OTG_INTEN_GOIDLEIEN_Pos (4) /*!< OTG_T::INTEN: GOIDLEIEN Position */
sahilmgandhi 18:6a4db94011d3 5470 #define OTG_INTEN_GOIDLEIEN_Msk (0x1ul << OTG_INTEN_GOIDLEIEN_Pos) /*!< OTG_T::INTEN: GOIDLEIEN Mask */
sahilmgandhi 18:6a4db94011d3 5471
sahilmgandhi 18:6a4db94011d3 5472 #define OTG_INTEN_IDCHGIEN_Pos (5) /*!< OTG_T::INTEN: IDCHGIEN Position */
sahilmgandhi 18:6a4db94011d3 5473 #define OTG_INTEN_IDCHGIEN_Msk (0x1ul << OTG_INTEN_IDCHGIEN_Pos) /*!< OTG_T::INTEN: IDCHGIEN Mask */
sahilmgandhi 18:6a4db94011d3 5474
sahilmgandhi 18:6a4db94011d3 5475 #define OTG_INTEN_PDEVIEN_Pos (6) /*!< OTG_T::INTEN: PDEVIEN Position */
sahilmgandhi 18:6a4db94011d3 5476 #define OTG_INTEN_PDEVIEN_Msk (0x1ul << OTG_INTEN_PDEVIEN_Pos) /*!< OTG_T::INTEN: PDEVIEN Mask */
sahilmgandhi 18:6a4db94011d3 5477
sahilmgandhi 18:6a4db94011d3 5478 #define OTG_INTEN_HOSTIEN_Pos (7) /*!< OTG_T::INTEN: HOSTIEN Position */
sahilmgandhi 18:6a4db94011d3 5479 #define OTG_INTEN_HOSTIEN_Msk (0x1ul << OTG_INTEN_HOSTIEN_Pos) /*!< OTG_T::INTEN: HOSTIEN Mask */
sahilmgandhi 18:6a4db94011d3 5480
sahilmgandhi 18:6a4db94011d3 5481 #define OTG_INTEN_BVLDCHGIEN_Pos (8) /*!< OTG_T::INTEN: BVLDCHGIEN Position */
sahilmgandhi 18:6a4db94011d3 5482 #define OTG_INTEN_BVLDCHGIEN_Msk (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos) /*!< OTG_T::INTEN: BVLDCHGIEN Mask */
sahilmgandhi 18:6a4db94011d3 5483
sahilmgandhi 18:6a4db94011d3 5484 #define OTG_INTEN_AVLDCHGIEN_Pos (9) /*!< OTG_T::INTEN: AVLDCHGIEN Position */
sahilmgandhi 18:6a4db94011d3 5485 #define OTG_INTEN_AVLDCHGIEN_Msk (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos) /*!< OTG_T::INTEN: AVLDCHGIEN Mask */
sahilmgandhi 18:6a4db94011d3 5486
sahilmgandhi 18:6a4db94011d3 5487 #define OTG_INTEN_VBCHGIEN_Pos (10) /*!< OTG_T::INTEN: VBCHGIEN Position */
sahilmgandhi 18:6a4db94011d3 5488 #define OTG_INTEN_VBCHGIEN_Msk (0x1ul << OTG_INTEN_VBCHGIEN_Pos) /*!< OTG_T::INTEN: VBCHGIEN Mask */
sahilmgandhi 18:6a4db94011d3 5489
sahilmgandhi 18:6a4db94011d3 5490 #define OTG_INTEN_SECHGIEN_Pos (11) /*!< OTG_T::INTEN: SECHGIEN Position */
sahilmgandhi 18:6a4db94011d3 5491 #define OTG_INTEN_SECHGIEN_Msk (0x1ul << OTG_INTEN_SECHGIEN_Pos) /*!< OTG_T::INTEN: SECHGIEN Mask */
sahilmgandhi 18:6a4db94011d3 5492
sahilmgandhi 18:6a4db94011d3 5493 #define OTG_INTEN_SRPDETIEN_Pos (13) /*!< OTG_T::INTEN: SRPDETIEN Position */
sahilmgandhi 18:6a4db94011d3 5494 #define OTG_INTEN_SRPDETIEN_Msk (0x1ul << OTG_INTEN_SRPDETIEN_Pos) /*!< OTG_T::INTEN: SRPDETIEN Mask */
sahilmgandhi 18:6a4db94011d3 5495
sahilmgandhi 18:6a4db94011d3 5496 #define OTG_INTSTS_ROLECHGIF_Pos (0) /*!< OTG_T::INTSTS: ROLECHGIF Position */
sahilmgandhi 18:6a4db94011d3 5497 #define OTG_INTSTS_ROLECHGIF_Msk (0x1ul << OTG_INTSTS_ROLECHGIF_Pos) /*!< OTG_T::INTSTS: ROLECHGIF Mask */
sahilmgandhi 18:6a4db94011d3 5498
sahilmgandhi 18:6a4db94011d3 5499 #define OTG_INTSTS_VBEIF_Pos (1) /*!< OTG_T::INTSTS: VBEIF Position */
sahilmgandhi 18:6a4db94011d3 5500 #define OTG_INTSTS_VBEIF_Msk (0x1ul << OTG_INTSTS_VBEIF_Pos) /*!< OTG_T::INTSTS: VBEIF Mask */
sahilmgandhi 18:6a4db94011d3 5501
sahilmgandhi 18:6a4db94011d3 5502 #define OTG_INTSTS_SRPFIF_Pos (2) /*!< OTG_T::INTSTS: SRPFIF Position */
sahilmgandhi 18:6a4db94011d3 5503 #define OTG_INTSTS_SRPFIF_Msk (0x1ul << OTG_INTSTS_SRPFIF_Pos) /*!< OTG_T::INTSTS: SRPFIF Mask */
sahilmgandhi 18:6a4db94011d3 5504
sahilmgandhi 18:6a4db94011d3 5505 #define OTG_INTSTS_HNPFIF_Pos (3) /*!< OTG_T::INTSTS: HNPFIF Position */
sahilmgandhi 18:6a4db94011d3 5506 #define OTG_INTSTS_HNPFIF_Msk (0x1ul << OTG_INTSTS_HNPFIF_Pos) /*!< OTG_T::INTSTS: HNPFIF Mask */
sahilmgandhi 18:6a4db94011d3 5507
sahilmgandhi 18:6a4db94011d3 5508 #define OTG_INTSTS_GOIDLEIF_Pos (4) /*!< OTG_T::INTSTS: GOIDLEIF Position */
sahilmgandhi 18:6a4db94011d3 5509 #define OTG_INTSTS_GOIDLEIF_Msk (0x1ul << OTG_INTSTS_GOIDLEIF_Pos) /*!< OTG_T::INTSTS: GOIDLEIF Mask */
sahilmgandhi 18:6a4db94011d3 5510
sahilmgandhi 18:6a4db94011d3 5511 #define OTG_INTSTS_IDCHGIF_Pos (5) /*!< OTG_T::INTSTS: IDCHGIF Position */
sahilmgandhi 18:6a4db94011d3 5512 #define OTG_INTSTS_IDCHGIF_Msk (0x1ul << OTG_INTSTS_IDCHGIF_Pos) /*!< OTG_T::INTSTS: IDCHGIF Mask */
sahilmgandhi 18:6a4db94011d3 5513
sahilmgandhi 18:6a4db94011d3 5514 #define OTG_INTSTS_PDEVIF_Pos (6) /*!< OTG_T::INTSTS: PDEVIF Position */
sahilmgandhi 18:6a4db94011d3 5515 #define OTG_INTSTS_PDEVIF_Msk (0x1ul << OTG_INTSTS_PDEVIF_Pos) /*!< OTG_T::INTSTS: PDEVIF Mask */
sahilmgandhi 18:6a4db94011d3 5516
sahilmgandhi 18:6a4db94011d3 5517 #define OTG_INTSTS_HOSTIF_Pos (7) /*!< OTG_T::INTSTS: HOSTIF Position */
sahilmgandhi 18:6a4db94011d3 5518 #define OTG_INTSTS_HOSTIF_Msk (0x1ul << OTG_INTSTS_HOSTIF_Pos) /*!< OTG_T::INTSTS: HOSTIF Mask */
sahilmgandhi 18:6a4db94011d3 5519
sahilmgandhi 18:6a4db94011d3 5520 #define OTG_INTSTS_BVLDCHGIF_Pos (8) /*!< OTG_T::INTSTS: BVLDCHGIF Position */
sahilmgandhi 18:6a4db94011d3 5521 #define OTG_INTSTS_BVLDCHGIF_Msk (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos) /*!< OTG_T::INTSTS: BVLDCHGIF Mask */
sahilmgandhi 18:6a4db94011d3 5522
sahilmgandhi 18:6a4db94011d3 5523 #define OTG_INTSTS_AVLDCHGIF_Pos (9) /*!< OTG_T::INTSTS: AVLDCHGIF Position */
sahilmgandhi 18:6a4db94011d3 5524 #define OTG_INTSTS_AVLDCHGIF_Msk (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos) /*!< OTG_T::INTSTS: AVLDCHGIF Mask */
sahilmgandhi 18:6a4db94011d3 5525
sahilmgandhi 18:6a4db94011d3 5526 #define OTG_INTSTS_VBCHGIF_Pos (10) /*!< OTG_T::INTSTS: VBCHGIF Position */
sahilmgandhi 18:6a4db94011d3 5527 #define OTG_INTSTS_VBCHGIF_Msk (0x1ul << OTG_INTSTS_VBCHGIF_Pos) /*!< OTG_T::INTSTS: VBCHGIF Mask */
sahilmgandhi 18:6a4db94011d3 5528
sahilmgandhi 18:6a4db94011d3 5529 #define OTG_INTSTS_SECHGIF_Pos (11) /*!< OTG_T::INTSTS: SECHGIF Position */
sahilmgandhi 18:6a4db94011d3 5530 #define OTG_INTSTS_SECHGIF_Msk (0x1ul << OTG_INTSTS_SECHGIF_Pos) /*!< OTG_T::INTSTS: SECHGIF Mask */
sahilmgandhi 18:6a4db94011d3 5531
sahilmgandhi 18:6a4db94011d3 5532 #define OTG_INTSTS_SRPDETIF_Pos (13) /*!< OTG_T::INTSTS: SRPDETIF Position */
sahilmgandhi 18:6a4db94011d3 5533 #define OTG_INTSTS_SRPDETIF_Msk (0x1ul << OTG_INTSTS_SRPDETIF_Pos) /*!< OTG_T::INTSTS: SRPDETIF Mask */
sahilmgandhi 18:6a4db94011d3 5534
sahilmgandhi 18:6a4db94011d3 5535 #define OTG_STATUS_OVERCUR_Pos (0) /*!< OTG_T::STATUS: OVERCUR Position */
sahilmgandhi 18:6a4db94011d3 5536 #define OTG_STATUS_OVERCUR_Msk (0x1ul << OTG_STATUS_OVERCUR_Pos) /*!< OTG_T::STATUS: OVERCUR Mask */
sahilmgandhi 18:6a4db94011d3 5537
sahilmgandhi 18:6a4db94011d3 5538 #define OTG_STATUS_IDSTS_Pos (1) /*!< OTG_T::STATUS: IDSTS Position */
sahilmgandhi 18:6a4db94011d3 5539 #define OTG_STATUS_IDSTS_Msk (0x1ul << OTG_STATUS_IDSTS_Pos) /*!< OTG_T::STATUS: IDSTS Mask */
sahilmgandhi 18:6a4db94011d3 5540
sahilmgandhi 18:6a4db94011d3 5541 #define OTG_STATUS_SESSEND_Pos (2) /*!< OTG_T::STATUS: SESSEND Position */
sahilmgandhi 18:6a4db94011d3 5542 #define OTG_STATUS_SESSEND_Msk (0x1ul << OTG_STATUS_SESSEND_Pos) /*!< OTG_T::STATUS: SESSEND Mask */
sahilmgandhi 18:6a4db94011d3 5543
sahilmgandhi 18:6a4db94011d3 5544 #define OTG_STATUS_BVLD_Pos (3) /*!< OTG_T::STATUS: BVLD Position */
sahilmgandhi 18:6a4db94011d3 5545 #define OTG_STATUS_BVLD_Msk (0x1ul << OTG_STATUS_BVLD_Pos) /*!< OTG_T::STATUS: BVLD Mask */
sahilmgandhi 18:6a4db94011d3 5546
sahilmgandhi 18:6a4db94011d3 5547 #define OTG_STATUS_AVLD_Pos (4) /*!< OTG_T::STATUS: AVLD Position */
sahilmgandhi 18:6a4db94011d3 5548 #define OTG_STATUS_AVLD_Msk (0x1ul << OTG_STATUS_AVLD_Pos) /*!< OTG_T::STATUS: AVLD Mask */
sahilmgandhi 18:6a4db94011d3 5549
sahilmgandhi 18:6a4db94011d3 5550 #define OTG_STATUS_VBUSVLD_Pos (5) /*!< OTG_T::STATUS: VBUSVLD Position */
sahilmgandhi 18:6a4db94011d3 5551 #define OTG_STATUS_VBUSVLD_Msk (0x1ul << OTG_STATUS_VBUSVLD_Pos) /*!< OTG_T::STATUS: VBUSVLD Mask */
sahilmgandhi 18:6a4db94011d3 5552
sahilmgandhi 18:6a4db94011d3 5553 /**@}*/ /* OTG_CONST */
sahilmgandhi 18:6a4db94011d3 5554 /**@}*/ /* end of OTG register group */
sahilmgandhi 18:6a4db94011d3 5555
sahilmgandhi 18:6a4db94011d3 5556
sahilmgandhi 18:6a4db94011d3 5557 /*---------------------- Peripheral Direct Memory Access Controller -------------------------*/
sahilmgandhi 18:6a4db94011d3 5558 /**
sahilmgandhi 18:6a4db94011d3 5559 @addtogroup PDMA Peripheral Direct Memory Access Controller(PDMA)
sahilmgandhi 18:6a4db94011d3 5560 Memory Mapped Structure for PDMA Controller
sahilmgandhi 18:6a4db94011d3 5561 @{ */
sahilmgandhi 18:6a4db94011d3 5562
sahilmgandhi 18:6a4db94011d3 5563
sahilmgandhi 18:6a4db94011d3 5564 typedef struct
sahilmgandhi 18:6a4db94011d3 5565 {
sahilmgandhi 18:6a4db94011d3 5566
sahilmgandhi 18:6a4db94011d3 5567
sahilmgandhi 18:6a4db94011d3 5568 /**
sahilmgandhi 18:6a4db94011d3 5569 * @var DSCT_T::CTL
sahilmgandhi 18:6a4db94011d3 5570 * Offset: 0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70/0x80/0x90/0xA0/0xB0 Descriptor Table Control Register of PDMA Channel 0~11
sahilmgandhi 18:6a4db94011d3 5571 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5572 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5573 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5574 * |[1:0] |OPMODE |PDMA Operation Mode Selection
sahilmgandhi 18:6a4db94011d3 5575 * | | |0 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically.
sahilmgandhi 18:6a4db94011d3 5576 * | | |1 = Basic mode: The descriptor table only has one task.
sahilmgandhi 18:6a4db94011d3 5577 * | | |When this task is finished, the PDMA_INTSTS[x] will be asserted.
sahilmgandhi 18:6a4db94011d3 5578 * | | |2 = Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register; PDMA controller will ignore this task, then load the next task to execute.
sahilmgandhi 18:6a4db94011d3 5579 * | | |3 = Reserved.
sahilmgandhi 18:6a4db94011d3 5580 * | | |Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete.
sahilmgandhi 18:6a4db94011d3 5581 * |[2] |TXTYPE |Transfer Type
sahilmgandhi 18:6a4db94011d3 5582 * | | |0 = Burst transfer type.
sahilmgandhi 18:6a4db94011d3 5583 * | | |1 = Single transfer type.
sahilmgandhi 18:6a4db94011d3 5584 * |[6:4] |BURSIZE |Burst Size
sahilmgandhi 18:6a4db94011d3 5585 * | | |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.
sahilmgandhi 18:6a4db94011d3 5586 * | | |000 = 128 Transfers.
sahilmgandhi 18:6a4db94011d3 5587 * | | |001 = 64 Transfers.
sahilmgandhi 18:6a4db94011d3 5588 * | | |010 = 32 Transfers.
sahilmgandhi 18:6a4db94011d3 5589 * | | |011 = 16 Transfers.
sahilmgandhi 18:6a4db94011d3 5590 * | | |100 = 8 Transfers.
sahilmgandhi 18:6a4db94011d3 5591 * | | |101 = 4 Transfers.
sahilmgandhi 18:6a4db94011d3 5592 * | | |110 = 2 Transfers.
sahilmgandhi 18:6a4db94011d3 5593 * | | |111 = 1 Transfers.
sahilmgandhi 18:6a4db94011d3 5594 * | | |Note: This field is only useful in burst transfer type.
sahilmgandhi 18:6a4db94011d3 5595 * |[7] |TBINTDIS |Table Interrupt Disable
sahilmgandhi 18:6a4db94011d3 5596 * | | |This field can be used to decide whether to enable table interrupt or not.
sahilmgandhi 18:6a4db94011d3 5597 * | | |If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates interrupt.
sahilmgandhi 18:6a4db94011d3 5598 * | | |0 = Table interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 5599 * | | |1 = Table interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 5600 * | | |Note: If this bit set to '1', the TEMPTYF will not be set.
sahilmgandhi 18:6a4db94011d3 5601 * |[9:8] |SAINC |Source Address Increment
sahilmgandhi 18:6a4db94011d3 5602 * | | |This field is used to set the source address increment size.
sahilmgandhi 18:6a4db94011d3 5603 * | | |11 = No increment (fixed address).
sahilmgandhi 18:6a4db94011d3 5604 * | | |Others = Increment and size is depended on TXWIDTH selection.
sahilmgandhi 18:6a4db94011d3 5605 * |[11:10] |DAINC |Destination Address Increment
sahilmgandhi 18:6a4db94011d3 5606 * | | |This field is used to set the destination address increment size.
sahilmgandhi 18:6a4db94011d3 5607 * | | |11 = No increment (fixed address).
sahilmgandhi 18:6a4db94011d3 5608 * | | |Others = Increment and size is depended on TXWIDTH selection.
sahilmgandhi 18:6a4db94011d3 5609 * |[13:12] |TXWIDTH |Transfer Width Selection
sahilmgandhi 18:6a4db94011d3 5610 * | | |This field is used for transfer width.
sahilmgandhi 18:6a4db94011d3 5611 * | | |00 = One byte (8 bit) is transferred for every operation.
sahilmgandhi 18:6a4db94011d3 5612 * | | |01= One half-word (16 bit) is transferred for every operation.
sahilmgandhi 18:6a4db94011d3 5613 * | | |10 = One word (32-bit) is transferred for every operation.
sahilmgandhi 18:6a4db94011d3 5614 * | | |11 = Reserved.
sahilmgandhi 18:6a4db94011d3 5615 * | | |Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection
sahilmgandhi 18:6a4db94011d3 5616 * |[29:16] |TXCNT |Transfer Count
sahilmgandhi 18:6a4db94011d3 5617 * | | |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field.
sahilmgandhi 18:6a4db94011d3 5618 * | | |Note: When PDMA finish each transfer data, this field will be decrease immediately.
sahilmgandhi 18:6a4db94011d3 5619 * @var DSCT_T::SA
sahilmgandhi 18:6a4db94011d3 5620 * Offset: 0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74/0x84/0x94/0xA4/0xB4 Source Address Register of PDMA Channel 0~11
sahilmgandhi 18:6a4db94011d3 5621 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5622 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5623 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5624 * |[31:0] |SA |PDMA Transfer Source Address Register
sahilmgandhi 18:6a4db94011d3 5625 * | | |This field indicates a 32-bit source address of PDMA controller.
sahilmgandhi 18:6a4db94011d3 5626 * @var DSCT_T::DA
sahilmgandhi 18:6a4db94011d3 5627 * Offset: 0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78/0x88/0x98/0xA8/0xB8 Destination Address Register of PDMA Channel 0~11
sahilmgandhi 18:6a4db94011d3 5628 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5629 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5630 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5631 * |[31:0] |DA |PDMA Transfer Destination Address Register
sahilmgandhi 18:6a4db94011d3 5632 * | | |This field indicates a 32-bit destination address of PDMA controller.
sahilmgandhi 18:6a4db94011d3 5633 * @var DSCT_T::NEXT
sahilmgandhi 18:6a4db94011d3 5634 * Offset: 0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C/0x8C/0x9C/0xAC/0xBC First Scatter-Gather Descriptor Table Offset Address of PDMA Channel 0~11
sahilmgandhi 18:6a4db94011d3 5635 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5636 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5637 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5638 * |[15:2] |NEXT |PDMA Next Descriptor Table Offset Address Register
sahilmgandhi 18:6a4db94011d3 5639 * | | |This field indicates the offset of next descriptor table address in system memory.
sahilmgandhi 18:6a4db94011d3 5640 * | | |The system memory based address is 0x2000_0000 (PDMA_SCATBA), if the next descriptor table is 0x2000_0100, then this field must fill in 0x0100.
sahilmgandhi 18:6a4db94011d3 5641 * | | |Note1: The next descriptor table address must be word boundary.
sahilmgandhi 18:6a4db94011d3 5642 * | | |Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.
sahilmgandhi 18:6a4db94011d3 5643 */
sahilmgandhi 18:6a4db94011d3 5644
sahilmgandhi 18:6a4db94011d3 5645 __IO uint32_t CTL; /* Offset: 0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70/0x80/0x90/0xA0/0xB0 Descriptor Table Control Register of PDMA Channel 0~11 */
sahilmgandhi 18:6a4db94011d3 5646 __IO uint32_t SA; /* Offset: 0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74/0x84/0x94/0xA4/0xB4 Source Address Register of PDMA Channel 0~11 */
sahilmgandhi 18:6a4db94011d3 5647 __IO uint32_t DA; /* Offset: 0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78/0x88/0x98/0xA8/0xB8 Destination Address Register of PDMA Channel 0~11 */
sahilmgandhi 18:6a4db94011d3 5648 __IO uint32_t NEXT; /* Offset: 0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C/0x8C/0x9C/0xAC/0xBC First Scatter-Gather Descriptor Table Offset Address of PDMA Channel 0~11 */
sahilmgandhi 18:6a4db94011d3 5649
sahilmgandhi 18:6a4db94011d3 5650 } DSCT_T;
sahilmgandhi 18:6a4db94011d3 5651
sahilmgandhi 18:6a4db94011d3 5652
sahilmgandhi 18:6a4db94011d3 5653
sahilmgandhi 18:6a4db94011d3 5654
sahilmgandhi 18:6a4db94011d3 5655 typedef struct
sahilmgandhi 18:6a4db94011d3 5656 {
sahilmgandhi 18:6a4db94011d3 5657
sahilmgandhi 18:6a4db94011d3 5658
sahilmgandhi 18:6a4db94011d3 5659 /**
sahilmgandhi 18:6a4db94011d3 5660 * @var PDMA_T::DSCT
sahilmgandhi 18:6a4db94011d3 5661 * Offset: 0x0000 ~ 0x00BC DMA Embedded Description Table 0~11
sahilmgandhi 18:6a4db94011d3 5662 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5663 * @var PDMA_T::CURSCAT
sahilmgandhi 18:6a4db94011d3 5664 * Offset: 0xC0 ~ 0xEC Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~11
sahilmgandhi 18:6a4db94011d3 5665 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5666 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5667 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5668 * |[31:0] |CURADDR |PDMA Current Description Address Register (Read Only)
sahilmgandhi 18:6a4db94011d3 5669 * | | |This field indicates a 32-bit current external description address of PDMA controller.
sahilmgandhi 18:6a4db94011d3 5670 * | | |Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address.
sahilmgandhi 18:6a4db94011d3 5671 * @var PDMA_T::CHCTL
sahilmgandhi 18:6a4db94011d3 5672 * Offset: 0x400 PDMA Channel Control Register
sahilmgandhi 18:6a4db94011d3 5673 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5674 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5675 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5676 * |[11:0] |CHENn |PDMA Channel Enable Bit
sahilmgandhi 18:6a4db94011d3 5677 * | | |Set this bit to 1 to enable PDMAn operation.
sahilmgandhi 18:6a4db94011d3 5678 * | | |If each channel is not set as enabled, each channel cannot be active.
sahilmgandhi 18:6a4db94011d3 5679 * | | |0 = PDMA channel [n] Disabled.
sahilmgandhi 18:6a4db94011d3 5680 * | | |1 = PDMA channel [n] Enabled.
sahilmgandhi 18:6a4db94011d3 5681 * | | |Note1: If software stops each PDMA transfer by setting PDMA_STOP register, this bit will be cleared automatically after finishing current transfer.
sahilmgandhi 18:6a4db94011d3 5682 * | | |Note2: Software reset (writing 0xFFFF_FFFF to PDMA_STOP register) will also clear this bit.
sahilmgandhi 18:6a4db94011d3 5683 * @var PDMA_T::STOP
sahilmgandhi 18:6a4db94011d3 5684 * Offset: 0x404 PDMA Transfer Stop Control Register
sahilmgandhi 18:6a4db94011d3 5685 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5686 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5687 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5688 * |[11:0] |STOPn |PDMA Transfer Stop Control Register (Write Only)
sahilmgandhi 18:6a4db94011d3 5689 * | | |User can stop the PDMA transfer by STOPn bit field or by software reset (writing '0xFFFF_FFFF' to PDMA_STOP register).
sahilmgandhi 18:6a4db94011d3 5690 * | | |By bit field:
sahilmgandhi 18:6a4db94011d3 5691 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 5692 * | | |1 = Stop PDMA transfer[n].
sahilmgandhi 18:6a4db94011d3 5693 * | | |When software set PDMA_STOP bit, the operation will finish the on-going transfer channel and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and request active flag.
sahilmgandhi 18:6a4db94011d3 5694 * | | |By write 0xFFFF_FFFF to PDMA_STOP:
sahilmgandhi 18:6a4db94011d3 5695 * | | |Setting all PDMA_STOP bit to "1" will generate software reset to reset internal state machine (the DSCT will not be reset).
sahilmgandhi 18:6a4db94011d3 5696 * | | |When software reset, the operation will be stopped imminently that include the on-going transfer and the channel enable bit (PDMA_CHCTL [CHEN]) and request active flag will be cleared to '0'.
sahilmgandhi 18:6a4db94011d3 5697 * | | |Note: User can poll channel enable bit to know if the on-going transfer is finished.
sahilmgandhi 18:6a4db94011d3 5698 * @var PDMA_T::SWREQ
sahilmgandhi 18:6a4db94011d3 5699 * Offset: 0x408 PDMA Software Request Register
sahilmgandhi 18:6a4db94011d3 5700 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5701 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5702 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5703 * |[11:0] |SWREQn |PDMA Software Request Register (Write Only)
sahilmgandhi 18:6a4db94011d3 5704 * | | |Set this bit to 1 to generate a software request to PDMA [n].
sahilmgandhi 18:6a4db94011d3 5705 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 5706 * | | |1 = Generate a software request.
sahilmgandhi 18:6a4db94011d3 5707 * | | |Note1: User can read PDMA_TRGSTS register to know which channel is on active.
sahilmgandhi 18:6a4db94011d3 5708 * | | |Active flag may be triggered by software request or peripheral request.
sahilmgandhi 18:6a4db94011d3 5709 * | | |Note2: If user does not enable each PDMA channel, the software request will be ignored.
sahilmgandhi 18:6a4db94011d3 5710 * @var PDMA_T::TRGSTS
sahilmgandhi 18:6a4db94011d3 5711 * Offset: 0x40C PDMA Channel Request Status Register
sahilmgandhi 18:6a4db94011d3 5712 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5713 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5714 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5715 * |[11:0] |REQSTSn |PDMA Channel Request Status (Read Only)
sahilmgandhi 18:6a4db94011d3 5716 * | | |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral.
sahilmgandhi 18:6a4db94011d3 5717 * | | |When PDMA controller finishes channel transfer, this bit will be cleared automatically.
sahilmgandhi 18:6a4db94011d3 5718 * | | |0 = PDMA Channel n has no request.
sahilmgandhi 18:6a4db94011d3 5719 * | | |1 = PDMA Channel n has a request.
sahilmgandhi 18:6a4db94011d3 5720 * | | |Note1: If software stops each PDMA transfer by setting PDMA_STOP register, this bit will be cleared automatically after finishing current transfer.
sahilmgandhi 18:6a4db94011d3 5721 * | | |Note2: Software reset (writing 0xFFFF_FFFF to PDMA_STOP register) will also clear this bit.
sahilmgandhi 18:6a4db94011d3 5722 * @var PDMA_T::PRISET
sahilmgandhi 18:6a4db94011d3 5723 * Offset: 0x410 PDMA Fixed Priority Setting Register
sahilmgandhi 18:6a4db94011d3 5724 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5725 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5726 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5727 * |[11:0] |FPRISETn |PDMA Fixed Priority Setting Register
sahilmgandhi 18:6a4db94011d3 5728 * | | |Set this bit to 1 to enable fixed priority level.
sahilmgandhi 18:6a4db94011d3 5729 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 5730 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 5731 * | | |1 = Set PDMA channel [n] to fixed priority channel.
sahilmgandhi 18:6a4db94011d3 5732 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 5733 * | | |0 = Corresponding PDMA channel is round-robin priority.
sahilmgandhi 18:6a4db94011d3 5734 * | | |1 = Corresponding PDMA channel is fixed priority.
sahilmgandhi 18:6a4db94011d3 5735 * | | |Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
sahilmgandhi 18:6a4db94011d3 5736 * @var PDMA_T::PRICLR
sahilmgandhi 18:6a4db94011d3 5737 * Offset: 0x414 PDMA Fixed Priority Clear Register
sahilmgandhi 18:6a4db94011d3 5738 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5739 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5740 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5741 * |[11:0] |FPRICLRn |PDMA Fixed Priority Clear Register (Write Only)
sahilmgandhi 18:6a4db94011d3 5742 * | | |Set this bit to 1 to clear fixed priority level.
sahilmgandhi 18:6a4db94011d3 5743 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 5744 * | | |1 = Clear PDMA channel [n] fixed priority setting.
sahilmgandhi 18:6a4db94011d3 5745 * | | |Note: User can read PDMA_PRISET register to know the channel priority.
sahilmgandhi 18:6a4db94011d3 5746 * @var PDMA_T::INTEN
sahilmgandhi 18:6a4db94011d3 5747 * Offset: 0x418 PDMA Interrupt Enable Register
sahilmgandhi 18:6a4db94011d3 5748 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5749 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5750 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5751 * |[11:0] |INTENn |PDMA Interrupt Enable Register
sahilmgandhi 18:6a4db94011d3 5752 * | | |This field is used for enabling PDMA channel[n] interrupt.
sahilmgandhi 18:6a4db94011d3 5753 * | | |0 = PDMA channel n interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 5754 * | | |1 = PDMA channel n interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 5755 * |[31:12] |Reserved |should be keep 0.
sahilmgandhi 18:6a4db94011d3 5756 * @var PDMA_T::INTSTS
sahilmgandhi 18:6a4db94011d3 5757 * Offset: 0x41C PDMA Interrupt Status Register
sahilmgandhi 18:6a4db94011d3 5758 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5759 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5760 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5761 * |[0] |ABTIF |PDMA Read/Write Target Abort Interrupt Flag (Read-Only)
sahilmgandhi 18:6a4db94011d3 5762 * | | |This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error.
sahilmgandhi 18:6a4db94011d3 5763 * | | |0 = No AHB bus ERROR response received.
sahilmgandhi 18:6a4db94011d3 5764 * | | |1 = AHB bus ERROR response received.
sahilmgandhi 18:6a4db94011d3 5765 * |[1] |TDIF |Transfer Done Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 5766 * | | |This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer.
sahilmgandhi 18:6a4db94011d3 5767 * | | |0 = Not finished yet.
sahilmgandhi 18:6a4db94011d3 5768 * | | |1 = PDMA channel has finished transmission.
sahilmgandhi 18:6a4db94011d3 5769 * |[2] |TEIF |Table Empty Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 5770 * | | |This bit indicates that PDMA controller has finished each table transmission and the operation is Stop mode.
sahilmgandhi 18:6a4db94011d3 5771 * | | |User can read TEIF register to indicate which channel finished transfer.
sahilmgandhi 18:6a4db94011d3 5772 * | | |0 = PDMA channel transfer is not finished.
sahilmgandhi 18:6a4db94011d3 5773 * | | |1 = PDMA channel transfer is finished and the operation is in idle state.
sahilmgandhi 18:6a4db94011d3 5774 * |[8:15] |REQTOFn |Request Time-out Flag For Each Channel [N](M45xD/M45xC Only)
sahilmgandhi 18:6a4db94011d3 5775 * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn, user can write 1 to clear these bits.
sahilmgandhi 18:6a4db94011d3 5776 * | | |0 = No request time-out.
sahilmgandhi 18:6a4db94011d3 5777 * | | |1 = Peripheral request time-out.
sahilmgandhi 18:6a4db94011d3 5778 * @var PDMA_T::ABTSTS
sahilmgandhi 18:6a4db94011d3 5779 * Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register
sahilmgandhi 18:6a4db94011d3 5780 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5781 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5782 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5783 * |[11:0] |ABTIFn |PDMA Read/Write Target Abort Interrupt Status Flag
sahilmgandhi 18:6a4db94011d3 5784 * | | |This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
sahilmgandhi 18:6a4db94011d3 5785 * | | |0 = No AHB bus ERROR response received when channel n transfer.
sahilmgandhi 18:6a4db94011d3 5786 * | | |1 = AHB bus ERROR response received when channel n transfer.
sahilmgandhi 18:6a4db94011d3 5787 * @var PDMA_T::TDSTS
sahilmgandhi 18:6a4db94011d3 5788 * Offset: 0x424 PDMA Channel Transfer Done Flag Register
sahilmgandhi 18:6a4db94011d3 5789 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5790 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5791 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5792 * |[11:0] |TDIFn |Transfer Done Flag Register
sahilmgandhi 18:6a4db94011d3 5793 * | | |This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
sahilmgandhi 18:6a4db94011d3 5794 * | | |0 = PDMA channel transfer has not finished.
sahilmgandhi 18:6a4db94011d3 5795 * | | |1 = PDMA channel has finished transmission.
sahilmgandhi 18:6a4db94011d3 5796 * @var PDMA_T::SCATSTS
sahilmgandhi 18:6a4db94011d3 5797 * Offset: 0x428 PDMA Scatter-Gather Table Empty Status Register
sahilmgandhi 18:6a4db94011d3 5798 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5799 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5800 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5801 * |[11:0] |TEMPTYFn |Scatter-Gather Table Empty Flag Register
sahilmgandhi 18:6a4db94011d3 5802 * | | |This bit indicates which PDMA channel n Scatter Gather table is empty when SWREQn set to high or channel has finished transmission and the operation mode is Stop mode.
sahilmgandhi 18:6a4db94011d3 5803 * | | |User can write 1 to clear these bits.
sahilmgandhi 18:6a4db94011d3 5804 * | | |0 = PDMA channel scatter-gather table is not empty.
sahilmgandhi 18:6a4db94011d3 5805 * | | |1 = PDMA channel scatter-gather table is empty and PDMA SWREQ has be set.
sahilmgandhi 18:6a4db94011d3 5806 * @var PDMA_T::TACTSTS
sahilmgandhi 18:6a4db94011d3 5807 * Offset: 0x42C PDMA Transfer Active Flag Register
sahilmgandhi 18:6a4db94011d3 5808 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5809 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5810 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5811 * |[11:0] |TXACTFn |Transfer On Active Flag Register (Read Only)
sahilmgandhi 18:6a4db94011d3 5812 * | | |This bit indicates which PDMA channel is in active.
sahilmgandhi 18:6a4db94011d3 5813 * | | |0 = PDMA channel is not finished.
sahilmgandhi 18:6a4db94011d3 5814 * | | |1 = PDMA channel is active.
sahilmgandhi 18:6a4db94011d3 5815 * @var PDMA_T::TOUTEN
sahilmgandhi 18:6a4db94011d3 5816 * Offset: 0x434 PDMA Time-out Enable register
sahilmgandhi 18:6a4db94011d3 5817 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5818 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5819 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5820 * |[7:0] |TOUTENn |PDMA Time-Out Enable Bits
sahilmgandhi 18:6a4db94011d3 5821 * | | |0 = PDMA Channel n time-out function Disable.
sahilmgandhi 18:6a4db94011d3 5822 * | | |1 = PDMA Channel n time-out function Enable.
sahilmgandhi 18:6a4db94011d3 5823 * @var PDMA_T::TOUTIEN
sahilmgandhi 18:6a4db94011d3 5824 * Offset: 0x438 PDMA Time-out Interrupt Enable register
sahilmgandhi 18:6a4db94011d3 5825 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5826 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5827 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5828 * |[7:0] |TOUTIENn |PDMA Time-Out Interrupt Enable Bits
sahilmgandhi 18:6a4db94011d3 5829 * | | |0 = PDMA Channel n time-out interrupt Disable.
sahilmgandhi 18:6a4db94011d3 5830 * | | |1 = PDMA Channel n time-out interrupt Enable.
sahilmgandhi 18:6a4db94011d3 5831 * @var PDMA_T::SCATBA
sahilmgandhi 18:6a4db94011d3 5832 * Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register
sahilmgandhi 18:6a4db94011d3 5833 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5834 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5835 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5836 * |[31:16] |SCATBA |PDMA Scatter-Gather Descriptor Table Address Register
sahilmgandhi 18:6a4db94011d3 5837 * | | |In Scatter-Gather mode, this is the base address for calculating the next link - list address.
sahilmgandhi 18:6a4db94011d3 5838 * | | |The next link address equation is.
sahilmgandhi 18:6a4db94011d3 5839 * | | |Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT.
sahilmgandhi 18:6a4db94011d3 5840 * | | |Note: Only useful in Scatter-Gather mode.
sahilmgandhi 18:6a4db94011d3 5841 * @var PDMA_T::TOC0_1
sahilmgandhi 18:6a4db94011d3 5842 * Offset: 0x440 PDMA Time-out Counter Ch1 and Ch0 Register
sahilmgandhi 18:6a4db94011d3 5843 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5844 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5845 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5846 * |[31:16] |TOC1 |Time-Out Counter For Channel 1
sahilmgandhi 18:6a4db94011d3 5847 * | | |This controls the period of time-out function for channel 1. The calculation unit is based on 10 kHz clock.
sahilmgandhi 18:6a4db94011d3 5848 * |[15:0] |TOC0 |Time-Out Counter For Channel 0
sahilmgandhi 18:6a4db94011d3 5849 * | | |This controls the period of time-out function for channel 0. The calculation unit is based on 10 kHz clock.
sahilmgandhi 18:6a4db94011d3 5850 * @var PDMA_T::TOC2_3
sahilmgandhi 18:6a4db94011d3 5851 * Offset: 0x444 PDMA Time-out Counter Ch3 and Ch2 Register
sahilmgandhi 18:6a4db94011d3 5852 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5853 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5854 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5855 * |[31:16] |TOC3 |Time-Out Counter For Channel 3
sahilmgandhi 18:6a4db94011d3 5856 * | | |This controls the period of time-out function for channel 3. The calculation unit is based on 10 kHz clock.
sahilmgandhi 18:6a4db94011d3 5857 * |[15:0] |TOC2 |Time-Out Counter For Channel 2
sahilmgandhi 18:6a4db94011d3 5858 * | | |This controls the period of time-out function for channel 2. The calculation unit is based on 10 kHz clock.
sahilmgandhi 18:6a4db94011d3 5859 * @var PDMA_T::TOC4_5
sahilmgandhi 18:6a4db94011d3 5860 * Offset: 0x448 PDMA Time-out Counter Ch5 and Ch4 Register
sahilmgandhi 18:6a4db94011d3 5861 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5862 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5863 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5864 * |[31:16] |TOC5 |Time-Out Counter For Channel 5
sahilmgandhi 18:6a4db94011d3 5865 * | | |This controls the period of time-out function for channel 5. The calculation unit is based on 10 kHz clock.
sahilmgandhi 18:6a4db94011d3 5866 * |[15:0] |TOC4 |Time-Out Counter For Channel 4
sahilmgandhi 18:6a4db94011d3 5867 * | | |This controls the period of time-out function for channel 4. The calculation unit is based on 10 kHz clock.
sahilmgandhi 18:6a4db94011d3 5868 * @var PDMA_T::TOC6_7
sahilmgandhi 18:6a4db94011d3 5869 * Offset: 0x44C PDMA Time-out Counter Ch7 and Ch6 Register
sahilmgandhi 18:6a4db94011d3 5870 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5871 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5872 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5873 * |[31:16] |TOC7 |Time-Out Counter For Channel 7
sahilmgandhi 18:6a4db94011d3 5874 * | | |This controls the period of time-out function for channel 7. The calculation unit is based on 10 kHz clock.
sahilmgandhi 18:6a4db94011d3 5875 * |[15:0] |TOC6 |Time-Out Counter For Channel 6
sahilmgandhi 18:6a4db94011d3 5876 * | | |This controls the period of time-out function for channel 6. The calculation unit is based on 10 kHz clock.
sahilmgandhi 18:6a4db94011d3 5877 * @var PDMA_T::REQSEL0_3
sahilmgandhi 18:6a4db94011d3 5878 * Offset: 0x480 PDMA Request Source Select Register 0
sahilmgandhi 18:6a4db94011d3 5879 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5880 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5881 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5882 * |[4:0] |REQSRC0 |Channel 0 Request Source Selection
sahilmgandhi 18:6a4db94011d3 5883 * | | |This filed defines which peripheral is connected to PDMA channel 0.
sahilmgandhi 18:6a4db94011d3 5884 * | | |User can configure the peripheral by setting REQSRC0.
sahilmgandhi 18:6a4db94011d3 5885 * | | |1 = Channel connects to SPI0_TX.
sahilmgandhi 18:6a4db94011d3 5886 * | | |2 = Channel connects to SPI1_TX.
sahilmgandhi 18:6a4db94011d3 5887 * | | |3 = Channel connects to SPI2_TX.
sahilmgandhi 18:6a4db94011d3 5888 * | | |4 = Channel connects to UART0_TX.
sahilmgandhi 18:6a4db94011d3 5889 * | | |5 = Channel connects to UART1_TX.
sahilmgandhi 18:6a4db94011d3 5890 * | | |6 = Channel connects to UART2_TX.
sahilmgandhi 18:6a4db94011d3 5891 * | | |7 = Channel connects to UART3_TX.
sahilmgandhi 18:6a4db94011d3 5892 * | | |8 = Channel connects to DAC_TX.
sahilmgandhi 18:6a4db94011d3 5893 * | | |9 = Channel connects to ADC_RX.
sahilmgandhi 18:6a4db94011d3 5894 * | | |11 = Channel connects to PWM0_P1_RX.
sahilmgandhi 18:6a4db94011d3 5895 * | | |12 = Channel connects to PWM0_P2_RX.
sahilmgandhi 18:6a4db94011d3 5896 * | | |13 = Channel connects to PWM0_P3_RX.
sahilmgandhi 18:6a4db94011d3 5897 * | | |14 = Channel connects to PWM1_P1_RX.
sahilmgandhi 18:6a4db94011d3 5898 * | | |15 = Channel connects to PWM1_P2_RX.
sahilmgandhi 18:6a4db94011d3 5899 * | | |16 = Channel connects to PWM1_P3_RX.
sahilmgandhi 18:6a4db94011d3 5900 * | | |17 = Channel connects to SPI0_RX.
sahilmgandhi 18:6a4db94011d3 5901 * | | |18 = Channel connects to SPI1_RX.
sahilmgandhi 18:6a4db94011d3 5902 * | | |19 = Channel connects to SPI2_RX.
sahilmgandhi 18:6a4db94011d3 5903 * | | |20 = Channel connects to UART0_RX.
sahilmgandhi 18:6a4db94011d3 5904 * | | |21 = Channel connects to UART1_RX.
sahilmgandhi 18:6a4db94011d3 5905 * | | |22 = Channel connects to UART2_RX.
sahilmgandhi 18:6a4db94011d3 5906 * | | |23 = Channel connects to UART3_RX.
sahilmgandhi 18:6a4db94011d3 5907 * | | |31 = Disable PDMA.
sahilmgandhi 18:6a4db94011d3 5908 * | | |Others = Reserved.
sahilmgandhi 18:6a4db94011d3 5909 * | | |Note 1: A peripheral can't assign to two channels at the same time.
sahilmgandhi 18:6a4db94011d3 5910 * | | |Note 2: This field is useless when transfer between memory and memory.
sahilmgandhi 18:6a4db94011d3 5911 * |[12:8] |REQSRC1 |Channel 1 Request Source Selection
sahilmgandhi 18:6a4db94011d3 5912 * | | |This filed defines which peripheral is connected to PDMA channel 1.
sahilmgandhi 18:6a4db94011d3 5913 * | | |User can configure the peripheral setting by REQSRC1.
sahilmgandhi 18:6a4db94011d3 5914 * | | |Note: The channel configuration is the same as REQSRC0 field.
sahilmgandhi 18:6a4db94011d3 5915 * | | |Please refer to the explanation of REQSRC0.
sahilmgandhi 18:6a4db94011d3 5916 * |[20:16] |REQSRC2 |Channel 2 Request Source Selection
sahilmgandhi 18:6a4db94011d3 5917 * | | |This filed defines which peripheral is connected to PDMA channel 2.
sahilmgandhi 18:6a4db94011d3 5918 * | | |User can configure the peripheral setting by REQSRC2.
sahilmgandhi 18:6a4db94011d3 5919 * | | |Note: The channel configuration is the same as REQSRC0 field.
sahilmgandhi 18:6a4db94011d3 5920 * | | |Please refer to the explanation of REQSRC0.
sahilmgandhi 18:6a4db94011d3 5921 * |[28:24] |REQSRC3 |Channel 3 Request Source Selection
sahilmgandhi 18:6a4db94011d3 5922 * | | |This filed defines which peripheral is connected to PDMA channel 3.
sahilmgandhi 18:6a4db94011d3 5923 * | | |User can configure the peripheral setting by REQSRC3.
sahilmgandhi 18:6a4db94011d3 5924 * | | |Note: The channel configuration is the same as REQSRC0 field.
sahilmgandhi 18:6a4db94011d3 5925 * | | |Please refer to the explanation of REQSRC0.
sahilmgandhi 18:6a4db94011d3 5926 * @var PDMA_T::REQSEL4_7
sahilmgandhi 18:6a4db94011d3 5927 * Offset: 0x484 PDMA Request Source Select Register 1
sahilmgandhi 18:6a4db94011d3 5928 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5929 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5930 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5931 * |[4:0] |REQSRC4 |Channel 4 Request Source Selection
sahilmgandhi 18:6a4db94011d3 5932 * | | |This filed defines which peripheral is connected to PDMA channel 4.
sahilmgandhi 18:6a4db94011d3 5933 * | | |User can configure the peripheral setting by REQSRC4.
sahilmgandhi 18:6a4db94011d3 5934 * | | |Note: The channel configuration is the same as REQSRC0 field.
sahilmgandhi 18:6a4db94011d3 5935 * | | |Please refer to the explanation of REQSRC0.
sahilmgandhi 18:6a4db94011d3 5936 * |[12:8] |REQSRC5 |Channel 5 Request Source Selection
sahilmgandhi 18:6a4db94011d3 5937 * | | |This filed defines which peripheral is connected to PDMA channel 5.
sahilmgandhi 18:6a4db94011d3 5938 * | | |User can configure the peripheral setting by REQSRC5.
sahilmgandhi 18:6a4db94011d3 5939 * | | |Note: The channel configuration is the same as REQSRC0 field.
sahilmgandhi 18:6a4db94011d3 5940 * | | |Please refer to the explanation of REQSRC0.
sahilmgandhi 18:6a4db94011d3 5941 * |[20:16] |REQSRC6 |Channel 6 Request Source Selection
sahilmgandhi 18:6a4db94011d3 5942 * | | |This filed defines which peripheral is connected to PDMA channel 6.
sahilmgandhi 18:6a4db94011d3 5943 * | | |User can configure the peripheral setting by REQSRC6.
sahilmgandhi 18:6a4db94011d3 5944 * | | |Note: The channel configuration is the same as REQSRC0 field.
sahilmgandhi 18:6a4db94011d3 5945 * | | |Please refer to the explanation of REQSRC0.
sahilmgandhi 18:6a4db94011d3 5946 * |[28:24] |REQSRC7 |Channel 7 Request Source Selection
sahilmgandhi 18:6a4db94011d3 5947 * | | |This filed defines which peripheral is connected to PDMA channel 7.
sahilmgandhi 18:6a4db94011d3 5948 * | | |User can configure the peripheral setting by REQSRC7.
sahilmgandhi 18:6a4db94011d3 5949 * | | |Note: The channel configuration is the same as REQSRC0 field.
sahilmgandhi 18:6a4db94011d3 5950 * | | |Please refer to the explanation of REQSRC0.
sahilmgandhi 18:6a4db94011d3 5951 * @var PDMA_T::REQSEL8_11
sahilmgandhi 18:6a4db94011d3 5952 * Offset: 0x488 PDMA Request Source Select Register 2
sahilmgandhi 18:6a4db94011d3 5953 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5954 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 5955 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 5956 * |[4:0] |REQSRC8 |Channel 8 Request Source Selection
sahilmgandhi 18:6a4db94011d3 5957 * | | |This filed defines which peripheral is connected to PDMA channel 8.
sahilmgandhi 18:6a4db94011d3 5958 * | | |User can configure the peripheral setting by REQSRC8.
sahilmgandhi 18:6a4db94011d3 5959 * | | |Note: The channel configuration is the same as REQSRC0 field.
sahilmgandhi 18:6a4db94011d3 5960 * | | |Please refer to the explanation of REQSRC0.
sahilmgandhi 18:6a4db94011d3 5961 * |[12:8] |REQSRC9 |Channel 9 Request Source Selection
sahilmgandhi 18:6a4db94011d3 5962 * | | |This filed defines which peripheral is connected to PDMA channel 9.
sahilmgandhi 18:6a4db94011d3 5963 * | | |User can configure the peripheral setting by REQSRC9.
sahilmgandhi 18:6a4db94011d3 5964 * | | |Note: The channel configuration is the same as REQSRC0 field.
sahilmgandhi 18:6a4db94011d3 5965 * | | |Please refer to the explanation of REQSRC0.
sahilmgandhi 18:6a4db94011d3 5966 * |[20:16] |REQSRC10 |Channel 10 Request Source Selection
sahilmgandhi 18:6a4db94011d3 5967 * | | |This filed defines which peripheral is connected to PDMA channel 10.
sahilmgandhi 18:6a4db94011d3 5968 * | | |User can configure the peripheral setting by REQSRC10.
sahilmgandhi 18:6a4db94011d3 5969 * | | |Note: The channel configuration is the same as REQSRC0 field.
sahilmgandhi 18:6a4db94011d3 5970 * | | |Please refer to the explanation of REQSRC0.
sahilmgandhi 18:6a4db94011d3 5971 * |[28:24] |REQSRC11 |Channel 11 Request Source Selection
sahilmgandhi 18:6a4db94011d3 5972 * | | |This filed defines which peripheral is connected to PDMA channel 11.
sahilmgandhi 18:6a4db94011d3 5973 * | | |User can configure the peripheral setting by REQSRC11.
sahilmgandhi 18:6a4db94011d3 5974 * | | |Note: The channel configuration is the same as REQSRC0 field.
sahilmgandhi 18:6a4db94011d3 5975 * | | |Please refer to the explanation of REQSRC0.
sahilmgandhi 18:6a4db94011d3 5976 */
sahilmgandhi 18:6a4db94011d3 5977
sahilmgandhi 18:6a4db94011d3 5978 DSCT_T DSCT[12]; /* Offset: 0x0000 ~ 0x00BC DMA Embedded Description Table 0~11 */
sahilmgandhi 18:6a4db94011d3 5979 __I uint32_t CURSCAT[12];
sahilmgandhi 18:6a4db94011d3 5980 __I uint32_t RESERVE0[196]; /* Offset: 0xC0 ~ 0xEC Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~11 */
sahilmgandhi 18:6a4db94011d3 5981 __IO uint32_t CHCTL; /* Offset: 0x400 PDMA Channel Control Register */
sahilmgandhi 18:6a4db94011d3 5982 __O uint32_t STOP; /* Offset: 0x404 PDMA Transfer Stop Control Register */
sahilmgandhi 18:6a4db94011d3 5983 __O uint32_t SWREQ; /* Offset: 0x408 PDMA Software Request Register */
sahilmgandhi 18:6a4db94011d3 5984 __I uint32_t TRGSTS; /* Offset: 0x40C PDMA Channel Request Status Register */
sahilmgandhi 18:6a4db94011d3 5985 __IO uint32_t PRISET; /* Offset: 0x410 PDMA Fixed Priority Setting Register */
sahilmgandhi 18:6a4db94011d3 5986 __O uint32_t PRICLR; /* Offset: 0x414 PDMA Fixed Priority Clear Register */
sahilmgandhi 18:6a4db94011d3 5987 __IO uint32_t INTEN; /* Offset: 0x418 PDMA Interrupt Enable Register */
sahilmgandhi 18:6a4db94011d3 5988 __IO uint32_t INTSTS; /* Offset: 0x41C PDMA Interrupt Status Register */
sahilmgandhi 18:6a4db94011d3 5989 __IO uint32_t ABTSTS; /* Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register */
sahilmgandhi 18:6a4db94011d3 5990 __IO uint32_t TDSTS; /* Offset: 0x424 PDMA Channel Transfer Done Flag Register */
sahilmgandhi 18:6a4db94011d3 5991 __IO uint32_t SCATSTS; /* Offset: 0x428 PDMA Scatter-Gather Table Empty Status Register */
sahilmgandhi 18:6a4db94011d3 5992 __I uint32_t TACTSTS;
sahilmgandhi 18:6a4db94011d3 5993 __I uint32_t RESERVE1[1]; /* Offset: 0x42C PDMA Transfer Active Flag Register */
sahilmgandhi 18:6a4db94011d3 5994 __IO uint32_t TOUTEN; /* Offset: 0x434 PDMA Time-out Enable register */
sahilmgandhi 18:6a4db94011d3 5995 __IO uint32_t TOUTIEN; /* Offset: 0x438 PDMA Time-out Interrupt Enable register */
sahilmgandhi 18:6a4db94011d3 5996 __IO uint32_t SCATBA; /* Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register */
sahilmgandhi 18:6a4db94011d3 5997 __IO uint32_t TOC0_1; /* Offset: 0x440 PDMA Time-out Counter Ch1 and Ch0 Register */
sahilmgandhi 18:6a4db94011d3 5998 __IO uint32_t TOC2_3; /* Offset: 0x444 PDMA Time-out Counter Ch3 and Ch2 Register */
sahilmgandhi 18:6a4db94011d3 5999 __IO uint32_t TOC4_5; /* Offset: 0x448 PDMA Time-out Counter Ch5 and Ch4 Register */
sahilmgandhi 18:6a4db94011d3 6000 __IO uint32_t TOC6_7;
sahilmgandhi 18:6a4db94011d3 6001 __I uint32_t RESERVE2[12]; /* Offset: 0x44C PDMA Time-out Counter Ch7 and Ch6 Register */
sahilmgandhi 18:6a4db94011d3 6002 __IO uint32_t REQSEL0_3; /* Offset: 0x480 PDMA Request Source Select Register 0 */
sahilmgandhi 18:6a4db94011d3 6003 __IO uint32_t REQSEL4_7; /* Offset: 0x484 PDMA Request Source Select Register 1 */
sahilmgandhi 18:6a4db94011d3 6004 __IO uint32_t REQSEL8_11; /* Offset: 0x484 PDMA Request Source Select Register 2 */
sahilmgandhi 18:6a4db94011d3 6005
sahilmgandhi 18:6a4db94011d3 6006 } PDMA_T;
sahilmgandhi 18:6a4db94011d3 6007
sahilmgandhi 18:6a4db94011d3 6008
sahilmgandhi 18:6a4db94011d3 6009
sahilmgandhi 18:6a4db94011d3 6010 /**
sahilmgandhi 18:6a4db94011d3 6011 @addtogroup PDMA_CONST PDMA Bit Field Definition
sahilmgandhi 18:6a4db94011d3 6012 Constant Definitions for PDMA Controller
sahilmgandhi 18:6a4db94011d3 6013 @{ */
sahilmgandhi 18:6a4db94011d3 6014
sahilmgandhi 18:6a4db94011d3 6015 #define PDMA_DSCT_CTL_OPMODE_Pos (0) /*!< DSCT_T::CTL: OPMODE Position */
sahilmgandhi 18:6a4db94011d3 6016 #define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) /*!< DSCT_T::CTL: OPMODE Mask */
sahilmgandhi 18:6a4db94011d3 6017
sahilmgandhi 18:6a4db94011d3 6018 #define PDMA_DSCT_CTL_TXTYPE_Pos (2) /*!< DSCT_T::CTL: TXTYPE Position */
sahilmgandhi 18:6a4db94011d3 6019 #define PDMA_DSCT_CTL_TXTYPE_Msk (1ul << PDMA_DSCT_CTL_TXTYPE_Pos) /*!< DSCT_T::CTL: TXTYPE Mask */
sahilmgandhi 18:6a4db94011d3 6020
sahilmgandhi 18:6a4db94011d3 6021 #define PDMA_DSCT_CTL_BURSIZE_Pos (4) /*!< DSCT_T::CTL: BURSIZE Position */
sahilmgandhi 18:6a4db94011d3 6022 #define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) /*!< DSCT_T::CTL: BURSIZE Mask */
sahilmgandhi 18:6a4db94011d3 6023
sahilmgandhi 18:6a4db94011d3 6024 #define PDMA_DSCT_CTL_TBINTDIS_Pos (7) /*!< DSCT_T::CTL: TBINTDIS Position */
sahilmgandhi 18:6a4db94011d3 6025 #define PDMA_DSCT_CTL_TBINTDIS_Msk (1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) /*!< DSCT_T::CTL: TBINTDIS Mask */
sahilmgandhi 18:6a4db94011d3 6026
sahilmgandhi 18:6a4db94011d3 6027 #define PDMA_DSCT_CTL_SAINC_Pos (8) /*!< DSCT_T::CTL: SAINC Position */
sahilmgandhi 18:6a4db94011d3 6028 #define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) /*!< DSCT_T::CTL: SAINC Mask */
sahilmgandhi 18:6a4db94011d3 6029
sahilmgandhi 18:6a4db94011d3 6030 #define PDMA_DSCT_CTL_DAINC_Pos (10) /*!< DSCT_T::CTL: DAINC Position */
sahilmgandhi 18:6a4db94011d3 6031 #define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) /*!< DSCT_T::CTL: DAINC Mask */
sahilmgandhi 18:6a4db94011d3 6032
sahilmgandhi 18:6a4db94011d3 6033 #define PDMA_DSCT_CTL_TXWIDTH_Pos (12) /*!< DSCT_T::CTL: TXWIDTH Position */
sahilmgandhi 18:6a4db94011d3 6034 #define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) /*!< DSCT_T::CTL: TXWIDTH Mask */
sahilmgandhi 18:6a4db94011d3 6035
sahilmgandhi 18:6a4db94011d3 6036 #define PDMA_DSCT_CTL_TXCNT_Pos (16) /*!< DSCT_T::CTL: TXCNT Position */
sahilmgandhi 18:6a4db94011d3 6037 #define PDMA_DSCT_CTL_TXCNT_Msk (0x3FFFul << PDMA_DSCT_CTL_TXCNT_Pos) /*!< DSCT_T::CTL: TXCNT Mask */
sahilmgandhi 18:6a4db94011d3 6038
sahilmgandhi 18:6a4db94011d3 6039 #define PDMA_DSCT_SA_SA_Pos (0) /*!< DSCT_T::SA: SA Position */
sahilmgandhi 18:6a4db94011d3 6040 #define PDMA_DSCT_SA_SA_Msk (0xFFFFFFFFul << PDMA_DSCT_SA_SA_Pos) /*!< DSCT_T::SA: SA Mask */
sahilmgandhi 18:6a4db94011d3 6041
sahilmgandhi 18:6a4db94011d3 6042 #define PDMA_DSCT_DA_DA_Pos (0) /*!< DSCT_T::DA: DA Position */
sahilmgandhi 18:6a4db94011d3 6043 #define PDMA_DSCT_DA_DA_Msk (0xFFFFFFFFul << PDMA_DSCT_DA_DA_Pos) /*!< DSCT_T::DA: DA Mask */
sahilmgandhi 18:6a4db94011d3 6044
sahilmgandhi 18:6a4db94011d3 6045 #define PDMA_DSCT_NEXT_NEXT_Pos (0) /*!< DSCT_T::NEXT: NEXT Position */
sahilmgandhi 18:6a4db94011d3 6046 #define PDMA_DSCT_NEXT_NEXT_Msk (0xFFFFul << PDMA_DSCT_NEXT_NEXT_Pos) /*!< DSCT_T::NEXT: NEXT Mask */
sahilmgandhi 18:6a4db94011d3 6047
sahilmgandhi 18:6a4db94011d3 6048 #define PDMA_CURSCAT_CURADDR_Pos (0) /*!< PDMA_T::CURSCAT: CURADDR Position */
sahilmgandhi 18:6a4db94011d3 6049 #define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos) /*!< PDMA_T::CURSCAT: CURADDR Mask */
sahilmgandhi 18:6a4db94011d3 6050
sahilmgandhi 18:6a4db94011d3 6051 #define PDMA_CHCTL_CHENn_Pos (0) /*!< PDMA_T::CHCTL: CHENn Position */
sahilmgandhi 18:6a4db94011d3 6052 #define PDMA_CHCTL_CHENn_Msk (0xffful << PDMA_CHCTL_CHENn_Pos) /*!< PDMA_T::CHCTL: CHENn Mask */
sahilmgandhi 18:6a4db94011d3 6053
sahilmgandhi 18:6a4db94011d3 6054 #define PDMA_STOP_STOPn_Pos (0) /*!< PDMA_T::STOP: STOPn Position */
sahilmgandhi 18:6a4db94011d3 6055 #define PDMA_STOP_STOPn_Msk (0xffful << PDMA_STOP_STOPn_Pos) /*!< PDMA_T::STOP: STOPn Mask */
sahilmgandhi 18:6a4db94011d3 6056
sahilmgandhi 18:6a4db94011d3 6057 #define PDMA_SWREQ_SWREQn_Pos (0) /*!< PDMA_T::SWREQ: SWREQn Position */
sahilmgandhi 18:6a4db94011d3 6058 #define PDMA_SWREQ_SWREQn_Msk (0xffful << PDMA_SWREQ_SWREQn_Pos) /*!< PDMA_T::SWREQ: SWREQn Mask */
sahilmgandhi 18:6a4db94011d3 6059
sahilmgandhi 18:6a4db94011d3 6060 #define PDMA_TRGSTS_REQSTSn_Pos (0) /*!< PDMA_T::TRGSTS: REQSTSn Position */
sahilmgandhi 18:6a4db94011d3 6061 #define PDMA_TRGSTS_REQSTSn_Msk (0xffful << PDMA_TRGSTS_REQSTSn_Pos) /*!< PDMA_T::TRGSTS: REQSTSn Mask */
sahilmgandhi 18:6a4db94011d3 6062
sahilmgandhi 18:6a4db94011d3 6063 #define PDMA_PRISET_FPRISETn_Pos (0) /*!< PDMA_T::PRISET: FPRISETn Position */
sahilmgandhi 18:6a4db94011d3 6064 #define PDMA_PRISET_FPRISETn_Msk (0xffful << PDMA_PRISET_FPRISETn_Pos) /*!< PDMA_T::PRISET: FPRISETn Mask */
sahilmgandhi 18:6a4db94011d3 6065
sahilmgandhi 18:6a4db94011d3 6066 #define PDMA_PRICLR_FPRICLRn_Pos (0) /*!< PDMA_T::PRICLR: FPRICLRn Position */
sahilmgandhi 18:6a4db94011d3 6067 #define PDMA_PRICLR_FPRICLRn_Msk (0xffful << PDMA_PRICLR_FPRICLRn_Pos) /*!< PDMA_T::PRICLR: FPRICLRn Mask */
sahilmgandhi 18:6a4db94011d3 6068
sahilmgandhi 18:6a4db94011d3 6069 #define PDMA_INTEN_INTENn_Pos (0) /*!< PDMA_T::INTEN: INTENn Position */
sahilmgandhi 18:6a4db94011d3 6070 #define PDMA_INTEN_INTENn_Msk (0xffful << PDMA_INTEN_INTENn_Pos) /*!< PDMA_T::INTEN: INTENn Mask */
sahilmgandhi 18:6a4db94011d3 6071
sahilmgandhi 18:6a4db94011d3 6072 #define PDMA_INTSTS_ABTIF_Pos (0) /*!< PDMA_T::INTSTS: ABTIF Position */
sahilmgandhi 18:6a4db94011d3 6073 #define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) /*!< PDMA_T::INTSTS: ABTIF Mask */
sahilmgandhi 18:6a4db94011d3 6074
sahilmgandhi 18:6a4db94011d3 6075 #define PDMA_INTSTS_TDIF_Pos (1) /*!< PDMA_T::INTSTS: TDIF Position */
sahilmgandhi 18:6a4db94011d3 6076 #define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) /*!< PDMA_T::INTSTS: TDIF Mask */
sahilmgandhi 18:6a4db94011d3 6077
sahilmgandhi 18:6a4db94011d3 6078 #define PDMA_INTSTS_TEIF_Pos (2) /*!< PDMA_T::INTSTS: TEIF Position */
sahilmgandhi 18:6a4db94011d3 6079 #define PDMA_INTSTS_TEIF_Msk (0x1ul << PDMA_INTSTS_TEIF_Pos) /*!< PDMA_T::INTSTS: TEIF Mask */
sahilmgandhi 18:6a4db94011d3 6080
sahilmgandhi 18:6a4db94011d3 6081 #define PDMA_INTSTS_REQTOFn_Pos (8) /*!< PDMA_T::INTSTS: REQTOFn Position */
sahilmgandhi 18:6a4db94011d3 6082 #define PDMA_INTSTS_REQTOFn_Msk (0xfful << PDMA_INTSTS_REQTOFn_Pos) /*!< PDMA_T::INTSTS: REQTOFn Mask */
sahilmgandhi 18:6a4db94011d3 6083
sahilmgandhi 18:6a4db94011d3 6084 #define PDMA_ABTSTS_ABTIFn_Pos (0) /*!< PDMA_T::ABTSTS: ABTIFn Position */
sahilmgandhi 18:6a4db94011d3 6085 #define PDMA_ABTSTS_ABTIFn_Msk (0xffful << PDMA_ABTSTS_ABTIFn_Pos) /*!< PDMA_T::ABTSTS: ABTIFn Mask */
sahilmgandhi 18:6a4db94011d3 6086
sahilmgandhi 18:6a4db94011d3 6087 #define PDMA_TDSTS_TDIFn_Pos (0) /*!< PDMA_T::TDSTS: TDIFn Position */
sahilmgandhi 18:6a4db94011d3 6088 #define PDMA_TDSTS_TDIFn_Msk (0xffful << PDMA_TDSTS_TDIFn_Pos) /*!< PDMA_T::TDSTS: TDIFn Mask */
sahilmgandhi 18:6a4db94011d3 6089
sahilmgandhi 18:6a4db94011d3 6090 #define PDMA_SCATSTS_TEMPTYFn_Pos (0) /*!< PDMA_T::SCATSTS: TEMPTYFn Position */
sahilmgandhi 18:6a4db94011d3 6091 #define PDMA_SCATSTS_TEMPTYFn_Msk (0xffful << PDMA_SCATSTS_TEMPTYFn_Pos) /*!< PDMA_T::SCATSTS: TEMPTYFn Mask */
sahilmgandhi 18:6a4db94011d3 6092
sahilmgandhi 18:6a4db94011d3 6093 #define PDMA_TACTSTS_TXACTFn_Pos (0) /*!< PDMA_T::TACTSTS: TXACTFn Position */
sahilmgandhi 18:6a4db94011d3 6094 #define PDMA_TACTSTS_TXACTFn_Msk (0xffful << PDMA_TACTSTS_TXACTFn_Pos) /*!< PDMA_T::TACTSTS: TXACTFn Mask */
sahilmgandhi 18:6a4db94011d3 6095
sahilmgandhi 18:6a4db94011d3 6096 #define PDMA_TOUTEN_TOUTENn_Pos (0) /*!< PDMA_T::TOUTEN: TOUTENn Position */
sahilmgandhi 18:6a4db94011d3 6097 #define PDMA_TOUTEN_TOUTENn_Msk (0xfful << PDMA_TOUTEN_TOUTENn_Pos) /*!< PDMA_T::TOUTEN: TOUTENn Mask */
sahilmgandhi 18:6a4db94011d3 6098
sahilmgandhi 18:6a4db94011d3 6099 #define PDMA_TOUTIEN_TOUTIENn_Pos (0) /*!< PDMA_T::TOUTIEN: TOUTIENn Position */
sahilmgandhi 18:6a4db94011d3 6100 #define PDMA_TOUTIEN_TOUTIENn_Msk (0xfful << PDMA_TOUTIEN_TOUTIENn_Pos) /*!< PDMA_T::TOUTIEN: TOUTIENn Mask */
sahilmgandhi 18:6a4db94011d3 6101
sahilmgandhi 18:6a4db94011d3 6102 #define PDMA_SCATBA_SCATBA_Pos (16) /*!< PDMA_T::SCATBA: SCATBA Position */
sahilmgandhi 18:6a4db94011d3 6103 #define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) /*!< PDMA_T::SCATBA: SCATBA Mask */
sahilmgandhi 18:6a4db94011d3 6104
sahilmgandhi 18:6a4db94011d3 6105 #define PDMA_TOC0_1_TOC0_Pos (0) /*!< PDMA_T::TOC0_1: TOC0 Position */
sahilmgandhi 18:6a4db94011d3 6106 #define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) /*!< PDMA_T::TOC0_1: TOC0 Mask */
sahilmgandhi 18:6a4db94011d3 6107
sahilmgandhi 18:6a4db94011d3 6108 #define PDMA_TOC0_1_TOC1_Pos (16) /*!< PDMA_T::TOC0_1: TOC1 Position */
sahilmgandhi 18:6a4db94011d3 6109 #define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) /*!< PDMA_T::TOC0_1: TOC1 Mask */
sahilmgandhi 18:6a4db94011d3 6110
sahilmgandhi 18:6a4db94011d3 6111 #define PDMA_TOC2_3_TOC2_Pos (0) /*!< PDMA_T::TOC2_3: TOC2 Position */
sahilmgandhi 18:6a4db94011d3 6112 #define PDMA_TOC2_3_TOC2_Msk (0xfffful << PDMA_TOC2_3_TOC2_Pos) /*!< PDMA_T::TOC2_3: TOC2 Mask */
sahilmgandhi 18:6a4db94011d3 6113
sahilmgandhi 18:6a4db94011d3 6114 #define PDMA_TOC2_3_TOC3_Pos (16) /*!< PDMA_T::TOC2_3: TOC3 Position */
sahilmgandhi 18:6a4db94011d3 6115 #define PDMA_TOC2_3_TOC3_Msk (0xfffful << PDMA_TOC2_3_TOC3_Pos) /*!< PDMA_T::TOC2_3: TOC3 Mask */
sahilmgandhi 18:6a4db94011d3 6116
sahilmgandhi 18:6a4db94011d3 6117 #define PDMA_TOC4_5_TOC4_Pos (0) /*!< PDMA_T::TOC4_5: TOC4 Position */
sahilmgandhi 18:6a4db94011d3 6118 #define PDMA_TOC4_5_TOC4_Msk (0xfffful << PDMA_TOC4_5_TOC4_Pos) /*!< PDMA_T::TOC4_5: TOC4 Mask */
sahilmgandhi 18:6a4db94011d3 6119
sahilmgandhi 18:6a4db94011d3 6120 #define PDMA_TOC4_5_TOC5_Pos (16) /*!< PDMA_T::TOC4_5: TOC5 Position */
sahilmgandhi 18:6a4db94011d3 6121 #define PDMA_TOC4_5_TOC5_Msk (0xfffful << PDMA_TOC4_5_TOC5_Pos) /*!< PDMA_T::TOC4_5: TOC5 Mask */
sahilmgandhi 18:6a4db94011d3 6122
sahilmgandhi 18:6a4db94011d3 6123 #define PDMA_TOC6_7_TOC6_Pos (0) /*!< PDMA_T::TOC6_7: TOC6 Position */
sahilmgandhi 18:6a4db94011d3 6124 #define PDMA_TOC6_7_TOC6_Msk (0xfffful << PDMA_TOC6_7_TOC6_Pos) /*!< PDMA_T::TOC6_7: TOC6 Mask */
sahilmgandhi 18:6a4db94011d3 6125
sahilmgandhi 18:6a4db94011d3 6126 #define PDMA_TOC6_7_TOC7_Pos (16) /*!< PDMA_T::TOC6_7: TOC7 Position */
sahilmgandhi 18:6a4db94011d3 6127 #define PDMA_TOC6_7_TOC7_Msk (0xfffful << PDMA_TOC6_7_TOC7_Pos) /*!< PDMA_T::TOC6_7: TOC7 Mask */
sahilmgandhi 18:6a4db94011d3 6128
sahilmgandhi 18:6a4db94011d3 6129 #define PDMA_REQSEL0_3_REQSRC0_Pos (0) /*!< PDMA_T::REQSEL0_3: REQSRC0 Position */
sahilmgandhi 18:6a4db94011d3 6130 #define PDMA_REQSEL0_3_REQSRC0_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC0_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC0 Mask */
sahilmgandhi 18:6a4db94011d3 6131
sahilmgandhi 18:6a4db94011d3 6132 #define PDMA_REQSEL0_3_REQSRC1_Pos (8) /*!< PDMA_T::REQSEL0_3: REQSRC1 Position */
sahilmgandhi 18:6a4db94011d3 6133 #define PDMA_REQSEL0_3_REQSRC1_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC1_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC1 Mask */
sahilmgandhi 18:6a4db94011d3 6134
sahilmgandhi 18:6a4db94011d3 6135 #define PDMA_REQSEL0_3_REQSRC2_Pos (16) /*!< PDMA_T::REQSEL0_3: REQSRC2 Position */
sahilmgandhi 18:6a4db94011d3 6136 #define PDMA_REQSEL0_3_REQSRC2_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC2_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC2 Mask */
sahilmgandhi 18:6a4db94011d3 6137
sahilmgandhi 18:6a4db94011d3 6138 #define PDMA_REQSEL0_3_REQSRC3_Pos (24) /*!< PDMA_T::REQSEL0_3: REQSRC3 Position */
sahilmgandhi 18:6a4db94011d3 6139 #define PDMA_REQSEL0_3_REQSRC3_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC3_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC3 Mask */
sahilmgandhi 18:6a4db94011d3 6140
sahilmgandhi 18:6a4db94011d3 6141 #define PDMA_REQSEL4_7_REQSRC4_Pos (0) /*!< PDMA_T::REQSEL4_7: REQSRC4 Position */
sahilmgandhi 18:6a4db94011d3 6142 #define PDMA_REQSEL4_7_REQSRC4_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC4_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC4 Mask */
sahilmgandhi 18:6a4db94011d3 6143
sahilmgandhi 18:6a4db94011d3 6144 #define PDMA_REQSEL4_7_REQSRC5_Pos (8) /*!< PDMA_T::REQSEL4_7: REQSRC5 Position */
sahilmgandhi 18:6a4db94011d3 6145 #define PDMA_REQSEL4_7_REQSRC5_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC5_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC5 Mask */
sahilmgandhi 18:6a4db94011d3 6146
sahilmgandhi 18:6a4db94011d3 6147 #define PDMA_REQSEL4_7_REQSRC6_Pos (16) /*!< PDMA_T::REQSEL4_7: REQSRC6 Position */
sahilmgandhi 18:6a4db94011d3 6148 #define PDMA_REQSEL4_7_REQSRC6_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC6_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC6 Mask */
sahilmgandhi 18:6a4db94011d3 6149
sahilmgandhi 18:6a4db94011d3 6150 #define PDMA_REQSEL4_7_REQSRC7_Pos (24) /*!< PDMA_T::REQSEL4_7: REQSRC7 Position */
sahilmgandhi 18:6a4db94011d3 6151 #define PDMA_REQSEL4_7_REQSRC7_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC7_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC7 Mask */
sahilmgandhi 18:6a4db94011d3 6152
sahilmgandhi 18:6a4db94011d3 6153 #define PDMA_REQSEL8_11_REQSRC8_Pos (0) /*!< PDMA_T::REQSEL8_11: REQSRC8 Position */
sahilmgandhi 18:6a4db94011d3 6154 #define PDMA_REQSEL8_11_REQSRC8_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC8_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC8 Mask */
sahilmgandhi 18:6a4db94011d3 6155
sahilmgandhi 18:6a4db94011d3 6156 #define PDMA_REQSEL8_11_REQSRC9_Pos (8) /*!< PDMA_T::REQSEL8_11: REQSRC9 Position */
sahilmgandhi 18:6a4db94011d3 6157 #define PDMA_REQSEL8_11_REQSRC9_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC9_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC9 Mask */
sahilmgandhi 18:6a4db94011d3 6158
sahilmgandhi 18:6a4db94011d3 6159 #define PDMA_REQSEL8_11_REQSRC10_Pos (16) /*!< PDMA_T::REQSEL8_11: REQSRC10 Position */
sahilmgandhi 18:6a4db94011d3 6160 #define PDMA_REQSEL8_11_REQSRC10_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC10_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC10 Mask */
sahilmgandhi 18:6a4db94011d3 6161
sahilmgandhi 18:6a4db94011d3 6162 #define PDMA_REQSEL8_11_REQSRC11_Pos (24) /*!< PDMA_T::REQSEL8_11: REQSRC11 Position */
sahilmgandhi 18:6a4db94011d3 6163 #define PDMA_REQSEL8_11_REQSRC11_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC11_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC11 Mask */
sahilmgandhi 18:6a4db94011d3 6164
sahilmgandhi 18:6a4db94011d3 6165 /**@}*/ /* PDMA_CONST */
sahilmgandhi 18:6a4db94011d3 6166 /**@}*/ /* end of PDMA register group */
sahilmgandhi 18:6a4db94011d3 6167
sahilmgandhi 18:6a4db94011d3 6168
sahilmgandhi 18:6a4db94011d3 6169 /*---------------------- Pulse Width Modulation Controller -------------------------*/
sahilmgandhi 18:6a4db94011d3 6170 /**
sahilmgandhi 18:6a4db94011d3 6171 @addtogroup PWM Pulse Width Modulation Controller(PWM)
sahilmgandhi 18:6a4db94011d3 6172 Memory Mapped Structure for PWM Controller
sahilmgandhi 18:6a4db94011d3 6173 @{ */
sahilmgandhi 18:6a4db94011d3 6174
sahilmgandhi 18:6a4db94011d3 6175
sahilmgandhi 18:6a4db94011d3 6176 typedef struct
sahilmgandhi 18:6a4db94011d3 6177 {
sahilmgandhi 18:6a4db94011d3 6178
sahilmgandhi 18:6a4db94011d3 6179
sahilmgandhi 18:6a4db94011d3 6180 /**
sahilmgandhi 18:6a4db94011d3 6181 * @var PWM_T::CTL0
sahilmgandhi 18:6a4db94011d3 6182 * Offset: 0x00 PWM Control Register 0
sahilmgandhi 18:6a4db94011d3 6183 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6184 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6185 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6186 * |[5:0] |CTRLDn |Center Re-Load
sahilmgandhi 18:6a4db94011d3 6187 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6188 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period.
sahilmgandhi 18:6a4db94011d3 6189 * | | |CMPDAT will load to CMPBUF at the center point of a period.
sahilmgandhi 18:6a4db94011d3 6190 * |[13:8] |WINLDENn |Window Load Enable
sahilmgandhi 18:6a4db94011d3 6191 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6192 * | | |0 = PERIOD will load to PBUF at the end point of each period.
sahilmgandhi 18:6a4db94011d3 6193 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
sahilmgandhi 18:6a4db94011d3 6194 * | | |1 = PERIOD will load to PBUF at the end point of each period.
sahilmgandhi 18:6a4db94011d3 6195 * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set.
sahilmgandhi 18:6a4db94011d3 6196 * | | |The valid reload window is set by software write 1 to PWM_LOAD register and cleared by hardware after load success.
sahilmgandhi 18:6a4db94011d3 6197 * |[21:16] |IMMLDENn |Immediately Load Enable
sahilmgandhi 18:6a4db94011d3 6198 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6199 * | | |0 = PERIOD will load to PBUF at the end point of each period.
sahilmgandhi 18:6a4db94011d3 6200 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
sahilmgandhi 18:6a4db94011d3 6201 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
sahilmgandhi 18:6a4db94011d3 6202 * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
sahilmgandhi 18:6a4db94011d3 6203 * |[24] |GROUPEN |Group Function Enable
sahilmgandhi 18:6a4db94011d3 6204 * | | |0 = The output waveform of each PWM channel are independent.
sahilmgandhi 18:6a4db94011d3 6205 * | | |1 = Unify the PWM_CH2 and PWM_CH4 to output the same waveform as PWM_CH0 and unify the PWM_CH3 and PWM_CH5 to output the same waveform as PWM_CH1.
sahilmgandhi 18:6a4db94011d3 6206 * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect)
sahilmgandhi 18:6a4db94011d3 6207 * | | |If counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode.
sahilmgandhi 18:6a4db94011d3 6208 * | | |0 = ICE debug mode counter halt disable.
sahilmgandhi 18:6a4db94011d3 6209 * | | |1 = ICE debug mode counter halt enable.
sahilmgandhi 18:6a4db94011d3 6210 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6211 * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect)
sahilmgandhi 18:6a4db94011d3 6212 * | | |0 = ICE debug mode acknowledgement effects PWM output.
sahilmgandhi 18:6a4db94011d3 6213 * | | |PWM pin will be forced as tri-state while ICE debug mode acknowledged.
sahilmgandhi 18:6a4db94011d3 6214 * | | |1 = ICE debug mode acknowledgement disabled.
sahilmgandhi 18:6a4db94011d3 6215 * | | |PWM pin will keep output no matter ICE debug mode acknowledged or not.
sahilmgandhi 18:6a4db94011d3 6216 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6217 * @var PWM_T::CTL1
sahilmgandhi 18:6a4db94011d3 6218 * Offset: 0x04 PWM Control Register 1
sahilmgandhi 18:6a4db94011d3 6219 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6220 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6221 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6222 * |[11:0] |CNTTYPEn |PWM Counter Behavior Type
sahilmgandhi 18:6a4db94011d3 6223 * | | |Each bit n controls corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6224 * | | |00 = Up counter type (supports in capture mode).
sahilmgandhi 18:6a4db94011d3 6225 * | | |01 = Down count type (supports in capture mode).
sahilmgandhi 18:6a4db94011d3 6226 * | | |10 = Up-down counter type.
sahilmgandhi 18:6a4db94011d3 6227 * | | |11 = Reserved.
sahilmgandhi 18:6a4db94011d3 6228 * |[21:16] |CNTMODEn |PWM Counter Mode
sahilmgandhi 18:6a4db94011d3 6229 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6230 * | | |0 = Auto-reload mode.
sahilmgandhi 18:6a4db94011d3 6231 * | | |1 = One-shot mode.
sahilmgandhi 18:6a4db94011d3 6232 * |[26:24] |OUTMODEn |PWM Output Mode
sahilmgandhi 18:6a4db94011d3 6233 * | | |Each bit n controls the
sahilmgandhi 18:6a4db94011d3 6234 * | | |output mode of
sahilmgandhi 18:6a4db94011d3 6235 * | | |corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6236 * | | |0 = PWM independent mode.
sahilmgandhi 18:6a4db94011d3 6237 * | | |1 = PWM complementary mode.
sahilmgandhi 18:6a4db94011d3 6238 * | | |Note: When operating in group function, these bits must all set to the same mode.
sahilmgandhi 18:6a4db94011d3 6239 * @var PWM_T::SYNC
sahilmgandhi 18:6a4db94011d3 6240 * Offset: 0x08 PWM Synchronization Register
sahilmgandhi 18:6a4db94011d3 6241 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6242 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6243 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6244 * |[2:0] |PHSENn |SYNC Phase Enable
sahilmgandhi 18:6a4db94011d3 6245 * | | |Each bit n controls corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6246 * | | |0 = PWM counter disable to load PHS value.
sahilmgandhi 18:6a4db94011d3 6247 * | | |1 = PWM counter enable to load PHS value.
sahilmgandhi 18:6a4db94011d3 6248 * |[13:8] |SINSRCn |PWM_SYNC_IN Source Selection
sahilmgandhi 18:6a4db94011d3 6249 * | | |Each bit n controls corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6250 * | | |00 = Synchronize source from SYNC_IN or SWSYNC.
sahilmgandhi 18:6a4db94011d3 6251 * | | |01 = Counter equal to 0.
sahilmgandhi 18:6a4db94011d3 6252 * | | |10 = Counter equal to PWM_CMPDATm, m denotes 1, 3, 5.
sahilmgandhi 18:6a4db94011d3 6253 * | | |11 = SYNC_OUT will not be generated.
sahilmgandhi 18:6a4db94011d3 6254 * |[16] |SNFLTEN |PWM_SYNC_IN Noise Filter Enable
sahilmgandhi 18:6a4db94011d3 6255 * | | |0 = Noise filter of input pin PWM_SYNC_IN is Disabled.
sahilmgandhi 18:6a4db94011d3 6256 * | | |1 = Noise filter of input pin PWM_SYNC_IN is Enabled.
sahilmgandhi 18:6a4db94011d3 6257 * |[19:17] |SFLTCSEL |SYNC Edge Detector Filter Clock Selection
sahilmgandhi 18:6a4db94011d3 6258 * | | |000 = Filter clock = HCLK.
sahilmgandhi 18:6a4db94011d3 6259 * | | |001 = Filter clock = HCLK/2.
sahilmgandhi 18:6a4db94011d3 6260 * | | |010 = Filter clock = HCLK/4.
sahilmgandhi 18:6a4db94011d3 6261 * | | |011 = Filter clock = HCLK/8.
sahilmgandhi 18:6a4db94011d3 6262 * | | |100 = Filter clock = HCLK/16.
sahilmgandhi 18:6a4db94011d3 6263 * | | |101 = Filter clock = HCLK/32.
sahilmgandhi 18:6a4db94011d3 6264 * | | |110 = Filter clock = HCLK/64.
sahilmgandhi 18:6a4db94011d3 6265 * | | |111 = Filter clock = HCLK/128.
sahilmgandhi 18:6a4db94011d3 6266 * |[22:20] |SFLTCNT |SYNC Edge Detector Filter Count
sahilmgandhi 18:6a4db94011d3 6267 * | | |The register bits control the counter number of edge detector.
sahilmgandhi 18:6a4db94011d3 6268 * |[23] |SINPINV |SYNC Input Pin Inverse
sahilmgandhi 18:6a4db94011d3 6269 * | | |0 = The state of pin SYNC is passed to the negative edge detector.
sahilmgandhi 18:6a4db94011d3 6270 * | | |1 = The inverted state of pin SYNC is passed to the negative edge detector.
sahilmgandhi 18:6a4db94011d3 6271 * |[26:24] |PHSDIRn |PWM Phase Direction Control
sahilmgandhi 18:6a4db94011d3 6272 * | | |Each bit n controls corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6273 * | | |0 = Control PWM counter count decrement after synchronizing.
sahilmgandhi 18:6a4db94011d3 6274 * | | |1 = Control PWM counter count increment after synchronizing.
sahilmgandhi 18:6a4db94011d3 6275 * @var PWM_T::SWSYNC
sahilmgandhi 18:6a4db94011d3 6276 * Offset: 0x0C PWM Software Control Synchronization Register
sahilmgandhi 18:6a4db94011d3 6277 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6278 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6279 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6280 * |[2:0] |SWSYNCn |Software SYNC Function
sahilmgandhi 18:6a4db94011d3 6281 * | | |Each bit n controls corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6282 * | | |When SINSRCn (PWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
sahilmgandhi 18:6a4db94011d3 6283 * @var PWM_T::CLKSRC
sahilmgandhi 18:6a4db94011d3 6284 * Offset: 0x10 PWM Clock Source Register
sahilmgandhi 18:6a4db94011d3 6285 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6286 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6287 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6288 * |[2:0] |ECLKSRC0 |PWM_CH01 External Clock Source Select
sahilmgandhi 18:6a4db94011d3 6289 * | | |000 = PWMx_CLK, x denotes 0 or 1.
sahilmgandhi 18:6a4db94011d3 6290 * | | |001 = TIMER0 overflow.
sahilmgandhi 18:6a4db94011d3 6291 * | | |010 = TIMER1 overflow.
sahilmgandhi 18:6a4db94011d3 6292 * | | |011 = TIMER2 overflow.
sahilmgandhi 18:6a4db94011d3 6293 * | | |100 = TIMER3 overflow.
sahilmgandhi 18:6a4db94011d3 6294 * | | |Others = Reserved.
sahilmgandhi 18:6a4db94011d3 6295 * |[10:8] |ECLKSRC2 |PWM_CH23 External Clock Source Select
sahilmgandhi 18:6a4db94011d3 6296 * | | |000 = PWMx_CLK, x denotes 0 or 1.
sahilmgandhi 18:6a4db94011d3 6297 * | | |001 = TIMER0 overflow.
sahilmgandhi 18:6a4db94011d3 6298 * | | |010 = TIMER1 overflow.
sahilmgandhi 18:6a4db94011d3 6299 * | | |011 = TIMER2 overflow.
sahilmgandhi 18:6a4db94011d3 6300 * | | |100 = TIMER3 overflow.
sahilmgandhi 18:6a4db94011d3 6301 * | | |Others = Reserved.
sahilmgandhi 18:6a4db94011d3 6302 * |[18:16] |ECLKSRC4 |PWM_CH45 External Clock Source Select
sahilmgandhi 18:6a4db94011d3 6303 * | | |000 = PWMx_CLK, x denotes 0 or 1.
sahilmgandhi 18:6a4db94011d3 6304 * | | |001 = TIMER0 overflow.
sahilmgandhi 18:6a4db94011d3 6305 * | | |010 = TIMER1 overflow.
sahilmgandhi 18:6a4db94011d3 6306 * | | |011 = TIMER2 overflow.
sahilmgandhi 18:6a4db94011d3 6307 * | | |100 = TIMER3 overflow.
sahilmgandhi 18:6a4db94011d3 6308 * | | |Others = Reserved.
sahilmgandhi 18:6a4db94011d3 6309 * @var PWM_T::CLKPSC0_1
sahilmgandhi 18:6a4db94011d3 6310 * Offset: 0x14 PWM Clock Pre-scale Register 0
sahilmgandhi 18:6a4db94011d3 6311 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6312 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6313 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6314 * |[11:0] |CLKPSC |PWM Counter Clock Pre-Scale
sahilmgandhi 18:6a4db94011d3 6315 * | | |The clock of PWM counter is decided by clock prescaler.
sahilmgandhi 18:6a4db94011d3 6316 * | | |Each PWM pair share one PWM counter clock prescaler.
sahilmgandhi 18:6a4db94011d3 6317 * | | |The clock of PWM counter is divided by (CLKPSC+ 1).
sahilmgandhi 18:6a4db94011d3 6318 * @var PWM_T::CLKPSC2_3
sahilmgandhi 18:6a4db94011d3 6319 * Offset: 0x18 PWM Clock Pre-scale Register 2
sahilmgandhi 18:6a4db94011d3 6320 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6321 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6322 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6323 * |[11:0] |CLKPSC |PWM Counter Clock Pre-Scale
sahilmgandhi 18:6a4db94011d3 6324 * | | |The clock of PWM counter is decided by clock prescaler.
sahilmgandhi 18:6a4db94011d3 6325 * | | |Each PWM pair share one PWM counter clock prescaler.
sahilmgandhi 18:6a4db94011d3 6326 * | | |The clock of PWM counter is divided by (CLKPSC+ 1).
sahilmgandhi 18:6a4db94011d3 6327 * @var PWM_T::CLKPSC4_5
sahilmgandhi 18:6a4db94011d3 6328 * Offset: 0x1C PWM Clock Pre-scale Register 4
sahilmgandhi 18:6a4db94011d3 6329 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6330 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6331 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6332 * |[11:0] |CLKPSC |PWM Counter Clock Pre-Scale
sahilmgandhi 18:6a4db94011d3 6333 * | | |The clock of PWM counter is decided by clock prescaler.
sahilmgandhi 18:6a4db94011d3 6334 * | | |Each PWM pair share one PWM counter clock prescaler.
sahilmgandhi 18:6a4db94011d3 6335 * | | |The clock of PWM counter is divided by (CLKPSC+ 1).
sahilmgandhi 18:6a4db94011d3 6336 * @var PWM_T::CNTEN
sahilmgandhi 18:6a4db94011d3 6337 * Offset: 0x20 PWM Counter Enable Register
sahilmgandhi 18:6a4db94011d3 6338 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6339 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6340 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6341 * |[5:0] |CNTENn |PWM Counter Enable
sahilmgandhi 18:6a4db94011d3 6342 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6343 * | | |0 = PWM Counter and clock prescaler Stop Running.
sahilmgandhi 18:6a4db94011d3 6344 * | | |1 = PWM Counter and clock prescaler Start Running.
sahilmgandhi 18:6a4db94011d3 6345 * @var PWM_T::CNTCLR
sahilmgandhi 18:6a4db94011d3 6346 * Offset: 0x24 PWM Clear Counter Register
sahilmgandhi 18:6a4db94011d3 6347 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6348 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6349 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6350 * |[5:0] |CNTCLRn |Clear PWM Counter Control Bit
sahilmgandhi 18:6a4db94011d3 6351 * | | |It is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6352 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 6353 * | | |1 = Clear 16-bit PWM counter to 0000H.
sahilmgandhi 18:6a4db94011d3 6354 * @var PWM_T::LOAD
sahilmgandhi 18:6a4db94011d3 6355 * Offset: 0x28 PWM Load Register
sahilmgandhi 18:6a4db94011d3 6356 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6357 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6358 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6359 * |[5:0] |LOADn |Re-Load PWM Comparator Register (CMPDAT) Control Bit
sahilmgandhi 18:6a4db94011d3 6360 * | | |This bit is software write, hardware clear when current PWM period end.
sahilmgandhi 18:6a4db94011d3 6361 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6362 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 6363 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 6364 * | | |1 = Set load window of window loading mode.
sahilmgandhi 18:6a4db94011d3 6365 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 6366 * | | |0 = No load window is set.
sahilmgandhi 18:6a4db94011d3 6367 * | | |1 = Load window is set.
sahilmgandhi 18:6a4db94011d3 6368 * | | |Note: This bit only use in window loading mode, WINLDENn(PWM_CTL0[13:8]) = 1.
sahilmgandhi 18:6a4db94011d3 6369 * @var PWM_T::PERIOD
sahilmgandhi 18:6a4db94011d3 6370 * Offset: 0x30~0x44 PWM Period Register 0~5
sahilmgandhi 18:6a4db94011d3 6371 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6372 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6373 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6374 * |[15:0] |PERIOD |PWM Period Register
sahilmgandhi 18:6a4db94011d3 6375 * | | |Up-Count mode: In this mode, PWM counter counts from 0 to PERIOD, and restarts from 0.
sahilmgandhi 18:6a4db94011d3 6376 * | | |Down-Count mode: In this mode, PWM counter counts from PERIOD to 0, and restarts from PERIOD.
sahilmgandhi 18:6a4db94011d3 6377 * | | |PWM period time = (PERIOD+1) * PWM_CLK period.
sahilmgandhi 18:6a4db94011d3 6378 * | | |Up-Down-Count mode: In this mode, PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
sahilmgandhi 18:6a4db94011d3 6379 * | | |PWM period time = 2 * PERIOD * PWM_CLK period.
sahilmgandhi 18:6a4db94011d3 6380 * @var PWM_T::CMPDAT
sahilmgandhi 18:6a4db94011d3 6381 * Offset: 0x50~0x64 PWM Comparator Register 0~5
sahilmgandhi 18:6a4db94011d3 6382 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6383 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6384 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6385 * |[15:0] |CMP |PWM Comparator Register
sahilmgandhi 18:6a4db94011d3 6386 * | | |CMP use to compare with CNTR to generate PWM waveform, interrupt and trigger EADC/DAC.
sahilmgandhi 18:6a4db94011d3 6387 * | | |In independent mode, CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.
sahilmgandhi 18:6a4db94011d3 6388 * | | |In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM_CH0 and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
sahilmgandhi 18:6a4db94011d3 6389 * @var PWM_T::DTCTL0_1
sahilmgandhi 18:6a4db94011d3 6390 * Offset: 0x70 PWM Dead-Time Control Register 0
sahilmgandhi 18:6a4db94011d3 6391 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6392 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6393 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6394 * |[11:0] |DTCNT |Dead-Time Counter (Write Protect)
sahilmgandhi 18:6a4db94011d3 6395 * | | |The dead-time can be calculated from the following formula:
sahilmgandhi 18:6a4db94011d3 6396 * | | |Dead-time = (DTCNT[11:0]+1) * PWM_CLK period.
sahilmgandhi 18:6a4db94011d3 6397 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6398 * |[16] |DTEN |Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)
sahilmgandhi 18:6a4db94011d3 6399 * | | |Dead-time insertion is only active when this pair of complementary PWM is enabled.
sahilmgandhi 18:6a4db94011d3 6400 * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
sahilmgandhi 18:6a4db94011d3 6401 * | | |0 = Dead-time insertion Disabled on the pin pair.
sahilmgandhi 18:6a4db94011d3 6402 * | | |1 = Dead-time insertion Enabled on the pin pair.
sahilmgandhi 18:6a4db94011d3 6403 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6404 * |[24] |DTCKSEL |Dead-Time Clock Select (Write Protect) (M45xD/M45xC Only)
sahilmgandhi 18:6a4db94011d3 6405 * | | |0 = Dead-time clock source from PWM_CLK.
sahilmgandhi 18:6a4db94011d3 6406 * | | |1 = Dead-time clock source from prescaler output.
sahilmgandhi 18:6a4db94011d3 6407 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6408 * @var PWM_T::DTCTL2_3
sahilmgandhi 18:6a4db94011d3 6409 * Offset: 0x74 PWM Dead-Time Control Register 2
sahilmgandhi 18:6a4db94011d3 6410 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6411 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6412 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6413 * |[11:0] |DTCNT |Dead-Time Counter (Write Protect)
sahilmgandhi 18:6a4db94011d3 6414 * | | |The dead-time can be calculated from the following formula:
sahilmgandhi 18:6a4db94011d3 6415 * | | |Dead-time = (DTCNT[11:0]+1) * PWM_CLK period.
sahilmgandhi 18:6a4db94011d3 6416 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6417 * |[16] |DTEN |Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)
sahilmgandhi 18:6a4db94011d3 6418 * | | |Dead-time insertion is only active when this pair of complementary PWM is enabled.
sahilmgandhi 18:6a4db94011d3 6419 * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
sahilmgandhi 18:6a4db94011d3 6420 * | | |0 = Dead-time insertion Disabled on the pin pair.
sahilmgandhi 18:6a4db94011d3 6421 * | | |1 = Dead-time insertion Enabled on the pin pair.
sahilmgandhi 18:6a4db94011d3 6422 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6423 * |[24] |DTCKSEL |Dead-Time Clock Select (Write Protect) (M45xD/M45xC Only)
sahilmgandhi 18:6a4db94011d3 6424 * | | |0 = Dead-time clock source from PWM_CLK.
sahilmgandhi 18:6a4db94011d3 6425 * | | |1 = Dead-time clock source from prescaler output.
sahilmgandhi 18:6a4db94011d3 6426 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6427 * @var PWM_T::DTCTL4_5
sahilmgandhi 18:6a4db94011d3 6428 * Offset: 0x78 PWM Dead-Time Control Register 4
sahilmgandhi 18:6a4db94011d3 6429 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6430 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6431 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6432 * |[11:0] |DTCNT |Dead-Time Counter (Write Protect)
sahilmgandhi 18:6a4db94011d3 6433 * | | |The dead-time can be calculated from the following formula:
sahilmgandhi 18:6a4db94011d3 6434 * | | |Dead-time = (DTCNT[11:0]+1) * PWM_CLK period.
sahilmgandhi 18:6a4db94011d3 6435 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6436 * |[16] |DTEN |Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)
sahilmgandhi 18:6a4db94011d3 6437 * | | |Dead-time insertion is only active when this pair of complementary PWM is enabled.
sahilmgandhi 18:6a4db94011d3 6438 * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
sahilmgandhi 18:6a4db94011d3 6439 * | | |0 = Dead-time insertion Disabled on the pin pair.
sahilmgandhi 18:6a4db94011d3 6440 * | | |1 = Dead-time insertion Enabled on the pin pair.
sahilmgandhi 18:6a4db94011d3 6441 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6442 * |[24] |DTCKSEL |Dead-Time Clock Select (Write Protect) (M45xD/M45xC Only)
sahilmgandhi 18:6a4db94011d3 6443 * | | |0 = Dead-time clock source from PWM_CLK.
sahilmgandhi 18:6a4db94011d3 6444 * | | |1 = Dead-time clock source from prescaler output.
sahilmgandhi 18:6a4db94011d3 6445 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6446 * @var PWM_T::PHS0_1
sahilmgandhi 18:6a4db94011d3 6447 * Offset: 0x80 PWM Counter Phase Register 0
sahilmgandhi 18:6a4db94011d3 6448 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6449 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6450 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6451 * |[15:0] |PHS |PWM Synchronous Start Phase Bits
sahilmgandhi 18:6a4db94011d3 6452 * | | |PHS determines the PWM synchronous start phase value. These bits only use in synchronous function.
sahilmgandhi 18:6a4db94011d3 6453 * @var PWM_T::PHS2_3
sahilmgandhi 18:6a4db94011d3 6454 * Offset: 0x84 PWM Counter Phase Register 2
sahilmgandhi 18:6a4db94011d3 6455 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6456 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6457 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6458 * |[15:0] |PHS |PWM Synchronous Start Phase Bits
sahilmgandhi 18:6a4db94011d3 6459 * | | |PHS determines the PWM synchronous start phase value. These bits only use in synchronous function.
sahilmgandhi 18:6a4db94011d3 6460 * @var PWM_T::PHS4_5
sahilmgandhi 18:6a4db94011d3 6461 * Offset: 0x88 PWM Counter Phase Register 4
sahilmgandhi 18:6a4db94011d3 6462 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6463 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6464 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6465 * |[15:0] |PHS |PWM Synchronous Start Phase Bits
sahilmgandhi 18:6a4db94011d3 6466 * | | |PHS determines the PWM synchronous start phase value. These bits only use in synchronous function.
sahilmgandhi 18:6a4db94011d3 6467 * @var PWM_T::CNT
sahilmgandhi 18:6a4db94011d3 6468 * Offset: 0x90~0xA4 PWM Counter Register 0~5
sahilmgandhi 18:6a4db94011d3 6469 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6470 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6471 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6472 * |[15:0] |CNT |PWM Data Register (Read Only)
sahilmgandhi 18:6a4db94011d3 6473 * | | |User can monitor CNTR to know the current value in 16-bit period counter.
sahilmgandhi 18:6a4db94011d3 6474 * |[16] |DIRF |PWM Direction Indicator Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 6475 * | | |0 = Counter is Down count.
sahilmgandhi 18:6a4db94011d3 6476 * | | |1 = Counter is UP count.
sahilmgandhi 18:6a4db94011d3 6477 * @var PWM_T::WGCTL0
sahilmgandhi 18:6a4db94011d3 6478 * Offset: 0xB0 PWM Generation Register 0
sahilmgandhi 18:6a4db94011d3 6479 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6480 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6481 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6482 * |[11:0] |ZPCTLn |PWM Zero Point Control
sahilmgandhi 18:6a4db94011d3 6483 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6484 * | | |00 = Do nothing.
sahilmgandhi 18:6a4db94011d3 6485 * | | |01 = PWM zero point output Low.
sahilmgandhi 18:6a4db94011d3 6486 * | | |10 = PWM zero point output High.
sahilmgandhi 18:6a4db94011d3 6487 * | | |11 = PWM zero point output Toggle.
sahilmgandhi 18:6a4db94011d3 6488 * | | |PWM can control output level when PWM counter count to zero.
sahilmgandhi 18:6a4db94011d3 6489 * |[27:16] |PRDPCTLn |PWM Period (Center) Point Control
sahilmgandhi 18:6a4db94011d3 6490 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6491 * | | |00 = Do nothing.
sahilmgandhi 18:6a4db94011d3 6492 * | | |01 = PWM period (center) point output Low.
sahilmgandhi 18:6a4db94011d3 6493 * | | |10 = PWM period (center) point output High.
sahilmgandhi 18:6a4db94011d3 6494 * | | |11 = PWM period (center) point output Toggle.
sahilmgandhi 18:6a4db94011d3 6495 * | | |PWM can control output level when PWM counter count to (PERIODn+1).
sahilmgandhi 18:6a4db94011d3 6496 * | | |Note: This bit is center point control when PWM counter operating in up-down counter type.
sahilmgandhi 18:6a4db94011d3 6497 * @var PWM_T::WGCTL1
sahilmgandhi 18:6a4db94011d3 6498 * Offset: 0xB4 PWM Generation Register 1
sahilmgandhi 18:6a4db94011d3 6499 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6500 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6501 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6502 * |[11:0] |CMPUCTLn |PWM Compare Up Point Control
sahilmgandhi 18:6a4db94011d3 6503 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6504 * | | |00 = Do nothing.
sahilmgandhi 18:6a4db94011d3 6505 * | | |01 = PWM compare up point output Low.
sahilmgandhi 18:6a4db94011d3 6506 * | | |10 = PWM compare up point output High.
sahilmgandhi 18:6a4db94011d3 6507 * | | |11 = PWM compare up point output Toggle.
sahilmgandhi 18:6a4db94011d3 6508 * | | |PWM can control output level when PWM counter up count to CMPDAT.
sahilmgandhi 18:6a4db94011d3 6509 * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
sahilmgandhi 18:6a4db94011d3 6510 * |[27:16] |CMPDCTLn |PWM Compare Down Point Control
sahilmgandhi 18:6a4db94011d3 6511 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6512 * | | |00 = Do nothing.
sahilmgandhi 18:6a4db94011d3 6513 * | | |01 = PWM compare down point output Low.
sahilmgandhi 18:6a4db94011d3 6514 * | | |10 = PWM compare down point output High.
sahilmgandhi 18:6a4db94011d3 6515 * | | |11 = PWM compare down point output Toggle.
sahilmgandhi 18:6a4db94011d3 6516 * | | |PWM can control output level when PWM counter down count to CMPDAT.
sahilmgandhi 18:6a4db94011d3 6517 * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
sahilmgandhi 18:6a4db94011d3 6518 * @var PWM_T::MSKEN
sahilmgandhi 18:6a4db94011d3 6519 * Offset: 0xB8 PWM Mask Enable Register
sahilmgandhi 18:6a4db94011d3 6520 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6521 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6522 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6523 * |[5:0] |MSKENn |PWM Mask Enable
sahilmgandhi 18:6a4db94011d3 6524 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6525 * | | |The PWM output signal will be masked when this bit is enabled.
sahilmgandhi 18:6a4db94011d3 6526 * | | |The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
sahilmgandhi 18:6a4db94011d3 6527 * | | |0 = PWM output signal is non-masked.
sahilmgandhi 18:6a4db94011d3 6528 * | | |1 = PWM output signal is masked and output MSKDATn data.
sahilmgandhi 18:6a4db94011d3 6529 * @var PWM_T::MSK
sahilmgandhi 18:6a4db94011d3 6530 * Offset: 0xBC PWM Mask Data Register
sahilmgandhi 18:6a4db94011d3 6531 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6532 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6533 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6534 * |[5:0] |MSKDATn |PWM Mask Data Bit
sahilmgandhi 18:6a4db94011d3 6535 * | | |This data bit control the state of PWMn output pin, if corresponding mask function is enabled.
sahilmgandhi 18:6a4db94011d3 6536 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6537 * | | |0 = Output logic low to PWMn.
sahilmgandhi 18:6a4db94011d3 6538 * | | |1 = Output logic high to PWMn.
sahilmgandhi 18:6a4db94011d3 6539 * @var PWM_T::BNF
sahilmgandhi 18:6a4db94011d3 6540 * Offset: 0xC0 PWM Brake Noise Filter Register
sahilmgandhi 18:6a4db94011d3 6541 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6542 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6543 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6544 * |[0] |BRK0NFEN |PWM Brake 0 Noise Filter Enable
sahilmgandhi 18:6a4db94011d3 6545 * | | |0 = Noise filter of PWM Brake 0 Disabled.
sahilmgandhi 18:6a4db94011d3 6546 * | | |1 = Noise filter of PWM Brake 0 Enabled.
sahilmgandhi 18:6a4db94011d3 6547 * |[3:1] |BRK0NFSEL |Brake 0 Edge Detector Filter Clock Selection
sahilmgandhi 18:6a4db94011d3 6548 * | | |000 = Filter clock = HCLK.
sahilmgandhi 18:6a4db94011d3 6549 * | | |001 = Filter clock = HCLK/2.
sahilmgandhi 18:6a4db94011d3 6550 * | | |010 = Filter clock = HCLK/4.
sahilmgandhi 18:6a4db94011d3 6551 * | | |011 = Filter clock = HCLK/8.
sahilmgandhi 18:6a4db94011d3 6552 * | | |100 = Filter clock = HCLK/16.
sahilmgandhi 18:6a4db94011d3 6553 * | | |101 = Filter clock = HCLK/32.
sahilmgandhi 18:6a4db94011d3 6554 * | | |110 = Filter clock = HCLK/64.
sahilmgandhi 18:6a4db94011d3 6555 * | | |111 = Filter clock = HCLK/128.
sahilmgandhi 18:6a4db94011d3 6556 * |[6:4] |BRK0FCNT |Brake 0 Edge Detector Filter Count
sahilmgandhi 18:6a4db94011d3 6557 * | | |The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT.
sahilmgandhi 18:6a4db94011d3 6558 * |[7] |BRK0PINV |Brake 0 Pin Inverse
sahilmgandhi 18:6a4db94011d3 6559 * | | |0 = The state of pin PWMx_BRAKE0 is passed to the negative edge detector.
sahilmgandhi 18:6a4db94011d3 6560 * | | |1 = The inverted state of pin PWMx_BRAKE10 is passed to the negative edge detector.
sahilmgandhi 18:6a4db94011d3 6561 * |[8] |BRK1NFEN |PWM Brake 1 Noise Filter Enable
sahilmgandhi 18:6a4db94011d3 6562 * | | |0 = Noise filter of PWM Brake 1 Disabled.
sahilmgandhi 18:6a4db94011d3 6563 * | | |1 = Noise filter of PWM Brake 1 Enabled.
sahilmgandhi 18:6a4db94011d3 6564 * |[11:9] |BRK1NFSEL |Brake 1 Edge Detector Filter Clock Selection
sahilmgandhi 18:6a4db94011d3 6565 * | | |000 = Filter clock = HCLK.
sahilmgandhi 18:6a4db94011d3 6566 * | | |001 = Filter clock = HCLK/2.
sahilmgandhi 18:6a4db94011d3 6567 * | | |010 = Filter clock = HCLK/4.
sahilmgandhi 18:6a4db94011d3 6568 * | | |011 = Filter clock = HCLK/8.
sahilmgandhi 18:6a4db94011d3 6569 * | | |100 = Filter clock = HCLK/16.
sahilmgandhi 18:6a4db94011d3 6570 * | | |101 = Filter clock = HCLK/32.
sahilmgandhi 18:6a4db94011d3 6571 * | | |110 = Filter clock = HCLK/64.
sahilmgandhi 18:6a4db94011d3 6572 * | | |111 = Filter clock = HCLK/128.
sahilmgandhi 18:6a4db94011d3 6573 * |[14:12] |BRK1FCNT |Brake 1 Edge Detector Filter Count
sahilmgandhi 18:6a4db94011d3 6574 * | | |The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT.
sahilmgandhi 18:6a4db94011d3 6575 * |[15] |BRK1PINV |Brake 1 Pin Inverse
sahilmgandhi 18:6a4db94011d3 6576 * | | |0 = The state of pin PWMx_BRAKE1 is passed to the negative edge detector.
sahilmgandhi 18:6a4db94011d3 6577 * | | |1 = The inverted state of pin PWMx_BRAKE1 is passed to the negative edge detector.
sahilmgandhi 18:6a4db94011d3 6578 * |[16] |BK0SRC |Brake 0 Pin Source Select (M45xD/M45xC Only)
sahilmgandhi 18:6a4db94011d3 6579 * | | |For PWM0 setting:
sahilmgandhi 18:6a4db94011d3 6580 * | | |0 = Brake 0 pin source come from PWM0_BRAKE0.
sahilmgandhi 18:6a4db94011d3 6581 * | | |1 = Brake 0 pin source come from PWM1_BRAKE0.
sahilmgandhi 18:6a4db94011d3 6582 * | | |For PWM1 setting:
sahilmgandhi 18:6a4db94011d3 6583 * | | |0 = Brake 0 pin source come from PWM1_BRAKE0.
sahilmgandhi 18:6a4db94011d3 6584 * | | |1 = Brake 0 pin source come from PWM0_BRAKE0.
sahilmgandhi 18:6a4db94011d3 6585 * |[24] |BK1SRC |Brake 1 Pin Source Select (M45xD/M45xC Only)
sahilmgandhi 18:6a4db94011d3 6586 * | | |For PWM0 setting:
sahilmgandhi 18:6a4db94011d3 6587 * | | |0 = Brake 1 pin source come from PWM0_BRAKE1.
sahilmgandhi 18:6a4db94011d3 6588 * | | |1 = Brake 1 pin source come from PWM1_BRAKE1.
sahilmgandhi 18:6a4db94011d3 6589 * | | |For PWM1 setting:
sahilmgandhi 18:6a4db94011d3 6590 * | | |0 = Brake 1 pin source come from PWM1_BRAKE1.
sahilmgandhi 18:6a4db94011d3 6591 * | | |1 = Brake 1 pin source come from PWM0_BRAKE1.
sahilmgandhi 18:6a4db94011d3 6592 * @var PWM_T::FAILBRK
sahilmgandhi 18:6a4db94011d3 6593 * Offset: 0xC4 PWM System Fail Brake Control Register
sahilmgandhi 18:6a4db94011d3 6594 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6595 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6596 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6597 * |[0] |CSSBRKEN |Clock Security System Detection Trigger PWM Brake Function 0 Enable
sahilmgandhi 18:6a4db94011d3 6598 * | | |0 = Brake Function triggered by CSS detection Disabled.
sahilmgandhi 18:6a4db94011d3 6599 * | | |1 = Brake Function triggered by CSS detection Enabled.
sahilmgandhi 18:6a4db94011d3 6600 * |[1] |BODBRKEN |Brown-Out Detection Trigger PWM Brake Function 0 Enable
sahilmgandhi 18:6a4db94011d3 6601 * | | |0 = Brake Function triggered by BOD Disabled.
sahilmgandhi 18:6a4db94011d3 6602 * | | |1 = Brake Function triggered by BOD Enabled.
sahilmgandhi 18:6a4db94011d3 6603 * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger PWM Brake Function 0 Enable
sahilmgandhi 18:6a4db94011d3 6604 * | | |0 = Brake Function triggered by SRAM parity error detection Disabled.
sahilmgandhi 18:6a4db94011d3 6605 * | | |1 = Brake Function triggered by SRAM parity error detection Enabled.
sahilmgandhi 18:6a4db94011d3 6606 * |[3] |CORBRKEN |Core Lockup Detection Trigger PWM Brake Function 0 Enable
sahilmgandhi 18:6a4db94011d3 6607 * | | |0 = Brake Function triggered by Core lockup detection Disabled.
sahilmgandhi 18:6a4db94011d3 6608 * | | |1 = Brake Function triggered by Core lockup detection Enabled.
sahilmgandhi 18:6a4db94011d3 6609 * @var PWM_T::BRKCTL0_1
sahilmgandhi 18:6a4db94011d3 6610 * Offset: 0xC8 PWM Brake Edge Detect Control Register 0
sahilmgandhi 18:6a4db94011d3 6611 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6612 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6613 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6614 * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6615 * | | |0 = ACMP0_O as edge-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6616 * | | |1 = ACMP0_O as edge-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6617 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6618 * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6619 * | | |0 = ACMP1_O as edge-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6620 * | | |1 = ACMP1_O as edge-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6621 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6622 * |[4] |BRKP0EEN |Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6623 * | | |0 = BKP0 pin as edge-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6624 * | | |1 = BKP0 pin as edge-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6625 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6626 * |[5] |BRKP1EEN |Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6627 * | | |0 = BKP1 pin as edge-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6628 * | | |1 = BKP1 pin as edge-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6629 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6630 * |[7] |SYSEBEN |Enable System Fail As Edge-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6631 * | | |0 = System Fail condition as edge-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6632 * | | |1 = System Fail condition as edge-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6633 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6634 * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6635 * | | |0 = ACMP0_O as level-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6636 * | | |1 = ACMP0_O as level-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6637 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6638 * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6639 * | | |0 = ACMP1_O as level-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6640 * | | |1 = ACMP1_O as level-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6641 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6642 * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6643 * | | |0 = PWMx_BRAKE0 pin as level-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6644 * | | |1 = PWMx_BRAKE0 pin as level-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6645 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6646 * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6647 * | | |0 = PWMx_BRAKE1 pin as level-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6648 * | | |1 = PWMx_BRAKE1 pin as level-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6649 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6650 * |[15] |SYSLBEN |Enable System Fail As Level-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6651 * | | |0 = System Fail condition as level-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6652 * | | |1 = System Fail condition as level-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6653 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6654 * |[17:16] |BRKAEVEN |PWM Brake Action Select For Even Channel (Write Protect)
sahilmgandhi 18:6a4db94011d3 6655 * | | |00 = PWM even channel level-detect brake function not affect channel output.
sahilmgandhi 18:6a4db94011d3 6656 * | | |01 = PWM even channel output tri-state when level-detect brake happened.
sahilmgandhi 18:6a4db94011d3 6657 * | | |10 = PWM even channel output low level when level-detect brake happened.
sahilmgandhi 18:6a4db94011d3 6658 * | | |11 = PWM even channel output high level when level-detect brake happened.
sahilmgandhi 18:6a4db94011d3 6659 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6660 * |[19:18] |BRKAODD |PWM Brake Action Select For Odd Channel (Write Protect)
sahilmgandhi 18:6a4db94011d3 6661 * | | |00 = PWM odd channel level-detect brake function not affect channel output.
sahilmgandhi 18:6a4db94011d3 6662 * | | |01 = PWM odd channel output tri-state when level-detect brake happened.
sahilmgandhi 18:6a4db94011d3 6663 * | | |10 = PWM odd channel output low level when level-detect brake happened.
sahilmgandhi 18:6a4db94011d3 6664 * | | |11 = PWM odd channel output high level when level-detect brake happened.
sahilmgandhi 18:6a4db94011d3 6665 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6666 * @var PWM_T::BRKCTL2_3
sahilmgandhi 18:6a4db94011d3 6667 * Offset: 0xCC PWM Brake Edge Detect Control Register 2
sahilmgandhi 18:6a4db94011d3 6668 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6669 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6670 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6671 * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6672 * | | |0 = ACMP0_O as edge-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6673 * | | |1 = ACMP0_O as edge-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6674 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6675 * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6676 * | | |0 = ACMP1_O as edge-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6677 * | | |1 = ACMP1_O as edge-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6678 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6679 * |[4] |BRKP0EEN |Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6680 * | | |0 = BKP0 pin as edge-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6681 * | | |1 = BKP0 pin as edge-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6682 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6683 * |[5] |BRKP1EEN |Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6684 * | | |0 = BKP1 pin as edge-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6685 * | | |1 = BKP1 pin as edge-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6686 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6687 * |[7] |SYSEBEN |Enable System Fail As Edge-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6688 * | | |0 = System Fail condition as edge-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6689 * | | |1 = System Fail condition as edge-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6690 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6691 * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6692 * | | |0 = ACMP0_O as level-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6693 * | | |1 = ACMP0_O as level-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6694 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6695 * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6696 * | | |0 = ACMP1_O as level-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6697 * | | |1 = ACMP1_O as level-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6698 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6699 * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6700 * | | |0 = PWMx_BRAKE0 pin as level-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6701 * | | |1 = PWMx_BRAKE0 pin as level-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6702 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6703 * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6704 * | | |0 = PWMx_BRAKE1 pin as level-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6705 * | | |1 = PWMx_BRAKE1 pin as level-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6706 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6707 * |[15] |SYSLBEN |Enable System Fail As Level-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6708 * | | |0 = System Fail condition as level-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6709 * | | |1 = System Fail condition as level-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6710 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6711 * |[17:16] |BRKAEVEN |PWM Brake Action Select For Even Channel (Write Protect)
sahilmgandhi 18:6a4db94011d3 6712 * | | |00 = PWM even channel level-detect brake function not affect channel output.
sahilmgandhi 18:6a4db94011d3 6713 * | | |01 = PWM even channel output tri-state when level-detect brake happened.
sahilmgandhi 18:6a4db94011d3 6714 * | | |10 = PWM even channel output low level when level-detect brake happened.
sahilmgandhi 18:6a4db94011d3 6715 * | | |11 = PWM even channel output high level when level-detect brake happened.
sahilmgandhi 18:6a4db94011d3 6716 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6717 * |[19:18] |BRKAODD |PWM Brake Action Select For Odd Channel (Write Protect)
sahilmgandhi 18:6a4db94011d3 6718 * | | |00 = PWM odd channel level-detect brake function not affect channel output.
sahilmgandhi 18:6a4db94011d3 6719 * | | |01 = PWM odd channel output tri-state when level-detect brake happened.
sahilmgandhi 18:6a4db94011d3 6720 * | | |10 = PWM odd channel output low level when level-detect brake happened.
sahilmgandhi 18:6a4db94011d3 6721 * | | |11 = PWM odd channel output high level when level-detect brake happened.
sahilmgandhi 18:6a4db94011d3 6722 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6723 * @var PWM_T::BRKCTL4_5
sahilmgandhi 18:6a4db94011d3 6724 * Offset: 0xD0 PWM Brake Edge Detect Control Register 4
sahilmgandhi 18:6a4db94011d3 6725 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6726 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6727 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6728 * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6729 * | | |0 = ACMP0_O as edge-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6730 * | | |1 = ACMP0_O as edge-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6731 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6732 * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6733 * | | |0 = ACMP1_O as edge-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6734 * | | |1 = ACMP1_O as edge-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6735 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6736 * |[4] |BRKP0EEN |Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6737 * | | |0 = BKP0 pin as edge-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6738 * | | |1 = BKP0 pin as edge-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6739 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6740 * |[5] |BRKP1EEN |Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6741 * | | |0 = BKP1 pin as edge-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6742 * | | |1 = BKP1 pin as edge-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6743 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6744 * |[7] |SYSEBEN |Enable System Fail As Edge-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6745 * | | |0 = System Fail condition as edge-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6746 * | | |1 = System Fail condition as edge-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6747 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6748 * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6749 * | | |0 = ACMP0_O as level-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6750 * | | |1 = ACMP0_O as level-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6751 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6752 * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6753 * | | |0 = ACMP1_O as level-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6754 * | | |1 = ACMP1_O as level-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6755 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6756 * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6757 * | | |0 = PWMx_BRAKE0 pin as level-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6758 * | | |1 = PWMx_BRAKE0 pin as level-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6759 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6760 * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6761 * | | |0 = PWMx_BRAKE1 pin as level-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6762 * | | |1 = PWMx_BRAKE1 pin as level-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6763 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6764 * |[15] |SYSLBEN |Enable System Fail As Level-Detect Brake Source (Write Protect)
sahilmgandhi 18:6a4db94011d3 6765 * | | |0 = System Fail condition as level-detect brake source Disabled.
sahilmgandhi 18:6a4db94011d3 6766 * | | |1 = System Fail condition as level-detect brake source Enabled.
sahilmgandhi 18:6a4db94011d3 6767 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6768 * |[17:16] |BRKAEVEN |PWM Brake Action Select For Even Channel (Write Protect)
sahilmgandhi 18:6a4db94011d3 6769 * | | |00 = PWM even channel level-detect brake function not affect channel output.
sahilmgandhi 18:6a4db94011d3 6770 * | | |01 = PWM even channel output tri-state when level-detect brake happened.
sahilmgandhi 18:6a4db94011d3 6771 * | | |10 = PWM even channel output low level when level-detect brake happened.
sahilmgandhi 18:6a4db94011d3 6772 * | | |11 = PWM even channel output high level when level-detect brake happened.
sahilmgandhi 18:6a4db94011d3 6773 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6774 * |[19:18] |BRKAODD |PWM Brake Action Select For Odd Channel (Write Protect)
sahilmgandhi 18:6a4db94011d3 6775 * | | |00 = PWM odd channel level-detect brake function not affect channel output.
sahilmgandhi 18:6a4db94011d3 6776 * | | |01 = PWM odd channel output tri-state when level-detect brake happened.
sahilmgandhi 18:6a4db94011d3 6777 * | | |10 = PWM odd channel output low level when level-detect brake happened.
sahilmgandhi 18:6a4db94011d3 6778 * | | |11 = PWM odd channel output high level when level-detect brake happened.
sahilmgandhi 18:6a4db94011d3 6779 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6780 * @var PWM_T::POLCTL
sahilmgandhi 18:6a4db94011d3 6781 * Offset: 0xD4 PWM Pin Polar Inverse Register
sahilmgandhi 18:6a4db94011d3 6782 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6783 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6784 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6785 * |[5:0] |PINVn |PWM PIN Polar Inverse Control
sahilmgandhi 18:6a4db94011d3 6786 * | | |The register controls polarity state of PWM output.
sahilmgandhi 18:6a4db94011d3 6787 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6788 * | | |0 = PWM output polar inverse Disabled.
sahilmgandhi 18:6a4db94011d3 6789 * | | |1 = PWM output polar inverse Enabled.
sahilmgandhi 18:6a4db94011d3 6790 * @var PWM_T::POEN
sahilmgandhi 18:6a4db94011d3 6791 * Offset: 0xD8 PWM Output Enable Register
sahilmgandhi 18:6a4db94011d3 6792 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6793 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6794 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6795 * |[5:0] |POENn |PWM Pin Output Enable
sahilmgandhi 18:6a4db94011d3 6796 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6797 * | | |0 = PWM pin at tri-state.
sahilmgandhi 18:6a4db94011d3 6798 * | | |1 = PWM pin in output mode.
sahilmgandhi 18:6a4db94011d3 6799 * @var PWM_T::SWBRK
sahilmgandhi 18:6a4db94011d3 6800 * Offset: 0xDC PWM Software Brake Control Register
sahilmgandhi 18:6a4db94011d3 6801 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6802 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6803 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6804 * |[2:0] |BRKETRGn |PWM Edge Brake Software Trigger (Write Only) (Write Protect) (M45xD/M45xC Only)
sahilmgandhi 18:6a4db94011d3 6805 * | | |Each bit n controls the corresponding PWM pair n.
sahilmgandhi 18:6a4db94011d3 6806 * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register.
sahilmgandhi 18:6a4db94011d3 6807 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6808 * |[10:8] |BRKLTRGn |PWM Level Brake Software Trigger (Write Only) (Write Protect)
sahilmgandhi 18:6a4db94011d3 6809 * | | |Each bit n controls the corresponding PWM pair n.
sahilmgandhi 18:6a4db94011d3 6810 * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register.
sahilmgandhi 18:6a4db94011d3 6811 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6812 * @var PWM_T::INTEN0
sahilmgandhi 18:6a4db94011d3 6813 * Offset: 0xE0 PWM Interrupt Enable Register 0
sahilmgandhi 18:6a4db94011d3 6814 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6815 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6816 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6817 * |[5:0] |ZIENn |PWM Zero Point Interrupt Enable
sahilmgandhi 18:6a4db94011d3 6818 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6819 * | | |0 = Zero point interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 6820 * | | |1 = Zero point interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 6821 * | | |Note: Odd channels will read always 0 at complementary mode.
sahilmgandhi 18:6a4db94011d3 6822 * |[7] |IFAIEN0_1 |PWM_CH0/1 Interrupt Flag Accumulator Interrupt Enable
sahilmgandhi 18:6a4db94011d3 6823 * | | |0 = Interrupt Flag accumulator interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 6824 * | | |1 = Interrupt Flag accumulator interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 6825 * |[13:8] |PIENn |PWM Period Point Interrupt Enable
sahilmgandhi 18:6a4db94011d3 6826 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6827 * | | |0 = Period point interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 6828 * | | |1 = Period point interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 6829 * | | |Note1: When up-down counter type period point means center point.
sahilmgandhi 18:6a4db94011d3 6830 * | | |Note2: Odd channels will read always 0 at complementary mode.
sahilmgandhi 18:6a4db94011d3 6831 * |[15] |IFAIEN2_3 |PWM_CH2/3 Interrupt Flag Accumulator Interrupt Enable
sahilmgandhi 18:6a4db94011d3 6832 * | | |0 = Interrupt Flag accumulator interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 6833 * | | |1 = Interrupt Flag accumulator interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 6834 * |[21:16] |CMPUIENn |PWM Compare Up Count Interrupt Enable
sahilmgandhi 18:6a4db94011d3 6835 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6836 * | | |0 = Compare up count interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 6837 * | | |1 = Compare up count interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 6838 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
sahilmgandhi 18:6a4db94011d3 6839 * |[23] |IFAIEN4_5 |PWM_CH4/5 Interrupt Flag Accumulator Interrupt Enable
sahilmgandhi 18:6a4db94011d3 6840 * | | |0 = Interrupt Flag accumulator interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 6841 * | | |1 = Interrupt Flag accumulator interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 6842 * |[29:24] |CMPDIENn |PWM Compare Down Count Interrupt Enable
sahilmgandhi 18:6a4db94011d3 6843 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6844 * | | |0 = Compare down count interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 6845 * | | |1 = Compare down count interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 6846 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
sahilmgandhi 18:6a4db94011d3 6847 * @var PWM_T::INTEN1
sahilmgandhi 18:6a4db94011d3 6848 * Offset: 0xE4 PWM Interrupt Enable Register 1
sahilmgandhi 18:6a4db94011d3 6849 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6850 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6851 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6852 * |[0] |BRKEIEN0_1|PWM Edge-Detect Brake Interrupt Enable For Channel0/1 (Write Protect)
sahilmgandhi 18:6a4db94011d3 6853 * | | |0 = Edge-detect Brake interrupt for channel0/1 Disabled.
sahilmgandhi 18:6a4db94011d3 6854 * | | |1 = Edge-detect Brake interrupt for channel0/1 Enabled.
sahilmgandhi 18:6a4db94011d3 6855 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6856 * |[1] |BRKEIEN2_3|PWM Edge-Detect Brake Interrupt Enable For Channel2/3 (Write Protect)
sahilmgandhi 18:6a4db94011d3 6857 * | | |0 = Edge-detect Brake interrupt for channel2/3 Disabled.
sahilmgandhi 18:6a4db94011d3 6858 * | | |1 = Edge-detect Brake interrupt for channel2/3 Enabled.
sahilmgandhi 18:6a4db94011d3 6859 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6860 * |[2] |BRKEIEN4_5|PWM Edge-Detect Brake Interrupt Enable For Channel4/5 (Write Protect)
sahilmgandhi 18:6a4db94011d3 6861 * | | |0 = Edge-detect Brake interrupt for channel4/5 Disabled.
sahilmgandhi 18:6a4db94011d3 6862 * | | |1 = Edge-detect Brake interrupt for channel4/5 Enabled.
sahilmgandhi 18:6a4db94011d3 6863 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6864 * |[8] |BRKLIEN0_1|PWM Level-Detect Brake Interrupt Enable For Channel0/1 (Write Protect)
sahilmgandhi 18:6a4db94011d3 6865 * | | |0 = Level-detect Brake interrupt for channel0/1 Disabled.
sahilmgandhi 18:6a4db94011d3 6866 * | | |1 = Level-detect Brake interrupt for channel0/1 Enabled.
sahilmgandhi 18:6a4db94011d3 6867 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6868 * |[9] |BRKLIEN2_3|PWM Level-Detect Brake Interrupt Enable For Channel2/3 (Write Protect)
sahilmgandhi 18:6a4db94011d3 6869 * | | |0 = Level-detect Brake interrupt for channel2/3 Disabled.
sahilmgandhi 18:6a4db94011d3 6870 * | | |1 = Level-detect Brake interrupt for channel2/3 Enabled.
sahilmgandhi 18:6a4db94011d3 6871 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6872 * |[10] |BRKLIEN4_5|PWM Level-Detect Brake Interrupt Enable For Channel4/5 (Write Protect)
sahilmgandhi 18:6a4db94011d3 6873 * | | |0 = Level-detect Brake interrupt for channel4/5 Disabled.
sahilmgandhi 18:6a4db94011d3 6874 * | | |1 = Level-detect Brake interrupt for channel4/5 Enabled.
sahilmgandhi 18:6a4db94011d3 6875 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6876 * @var PWM_T::INTSTS0
sahilmgandhi 18:6a4db94011d3 6877 * Offset: 0xE8 PWM Interrupt Flag Register 0
sahilmgandhi 18:6a4db94011d3 6878 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6879 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6880 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6881 * |[5:0] |ZIFn |PWM Zero Point Interrupt Flag
sahilmgandhi 18:6a4db94011d3 6882 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6883 * | | |This bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero.
sahilmgandhi 18:6a4db94011d3 6884 * |[7] |IFAIF0_1 |PWM_CH0/1 Interrupt Flag Accumulator Interrupt Flag
sahilmgandhi 18:6a4db94011d3 6885 * | | |Flag is set by hardware when condition match IFSEL0_1 in PWM_IFA register, software can clear this bit by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 6886 * |[13:8] |PIFn |PWM Period Point Interrupt Flag
sahilmgandhi 18:6a4db94011d3 6887 * | | |This bit is set by hardware when PWM counter reaches PWM_PERIODn, software can write 1 to clear this bit to zero.
sahilmgandhi 18:6a4db94011d3 6888 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6889 * |[15] |IFAIF2_3 |PWM_CH2/3 Interrupt Flag Accumulator Interrupt Flag
sahilmgandhi 18:6a4db94011d3 6890 * | | |Flag is set by hardware when condition match IFSEL2_3 in PWM_IFA register, software can clear this bit by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 6891 * |[21:16] |CMPUIFn |PWM Compare Up Count Interrupt Flag
sahilmgandhi 18:6a4db94011d3 6892 * | | |Flag is set by hardware when PWM counter up count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 6893 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6894 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
sahilmgandhi 18:6a4db94011d3 6895 * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
sahilmgandhi 18:6a4db94011d3 6896 * |[23] |IFAIF4_5 |PWM_CH4/5 Interrupt Flag Accumulator Interrupt Flag
sahilmgandhi 18:6a4db94011d3 6897 * | | |Flag is set by hardware when condition match IFSEL4_5 in PWM_IFA register, software can clear this bit by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 6898 * |[29:24] |CMPDIFn |PWM Compare Down Count Interrupt Flag
sahilmgandhi 18:6a4db94011d3 6899 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 6900 * | | |Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 6901 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
sahilmgandhi 18:6a4db94011d3 6902 * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
sahilmgandhi 18:6a4db94011d3 6903 * @var PWM_T::INTSTS1
sahilmgandhi 18:6a4db94011d3 6904 * Offset: 0xEC PWM Interrupt Flag Register 1
sahilmgandhi 18:6a4db94011d3 6905 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6906 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 6907 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 6908 * |[0] |BRKEIF0 |PWM Channel0 Edge-Detect Brake Interrupt Flag (Write Protect)
sahilmgandhi 18:6a4db94011d3 6909 * | | |0 = PWM channel0 edge-detect brake event do not happened.
sahilmgandhi 18:6a4db94011d3 6910 * | | |1 = When PWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
sahilmgandhi 18:6a4db94011d3 6911 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6912 * |[1] |BRKEIF1 |PWM Channel1 Edge-Detect Brake Interrupt Flag (Write Protect)
sahilmgandhi 18:6a4db94011d3 6913 * | | |0 = PWM channel1 edge-detect brake event do not happened.
sahilmgandhi 18:6a4db94011d3 6914 * | | |1 = When PWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
sahilmgandhi 18:6a4db94011d3 6915 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6916 * |[2] |BRKEIF2 |PWM Channel2 Edge-Detect Brake Interrupt Flag (Write Protect)
sahilmgandhi 18:6a4db94011d3 6917 * | | |0 = PWM channel2 edge-detect brake event do not happened.
sahilmgandhi 18:6a4db94011d3 6918 * | | |1 = When PWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
sahilmgandhi 18:6a4db94011d3 6919 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6920 * |[3] |BRKEIF3 |PWM Channel3 Edge-Detect Brake Interrupt Flag (Write Protect)
sahilmgandhi 18:6a4db94011d3 6921 * | | |0 = PWM channel3 edge-detect brake event do not happened.
sahilmgandhi 18:6a4db94011d3 6922 * | | |1 = When PWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
sahilmgandhi 18:6a4db94011d3 6923 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6924 * |[4] |BRKEIF4 |PWM Channel4 Edge-Detect Brake Interrupt Flag (Write Protect)
sahilmgandhi 18:6a4db94011d3 6925 * | | |0 = PWM channel4 edge-detect brake event do not happened.
sahilmgandhi 18:6a4db94011d3 6926 * | | |1 = When PWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
sahilmgandhi 18:6a4db94011d3 6927 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6928 * |[5] |BRKEIF5 |PWM Channel5 Edge-Detect Brake Interrupt Flag (Write Protect)
sahilmgandhi 18:6a4db94011d3 6929 * | | |0 = PWM channel5 edge-detect brake event do not happened.
sahilmgandhi 18:6a4db94011d3 6930 * | | |1 = When PWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
sahilmgandhi 18:6a4db94011d3 6931 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6932 * |[8] |BRKLIF0 |PWM Channel0 Level-Detect Brake Interrupt Flag (Write Protect)
sahilmgandhi 18:6a4db94011d3 6933 * | | |0 = PWM channel0 level-detect brake event do not happened.
sahilmgandhi 18:6a4db94011d3 6934 * | | |1 = When PWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
sahilmgandhi 18:6a4db94011d3 6935 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6936 * |[9] |BRKLIF1 |PWM Channel1 Level-Detect Brake Interrupt Flag (Write Protect)
sahilmgandhi 18:6a4db94011d3 6937 * | | |0 = PWM channel1 level-detect brake event do not happened.
sahilmgandhi 18:6a4db94011d3 6938 * | | |1 = When PWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
sahilmgandhi 18:6a4db94011d3 6939 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6940 * |[10] |BRKLIF2 |PWM Channel2 Level-Detect Brake Interrupt Flag (Write Protect)
sahilmgandhi 18:6a4db94011d3 6941 * | | |0 = PWM channel2 level-detect brake event do not happened.
sahilmgandhi 18:6a4db94011d3 6942 * | | |1 = When PWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
sahilmgandhi 18:6a4db94011d3 6943 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6944 * |[11] |BRKLIF3 |PWM Channel3 Level-Detect Brake Interrupt Flag (Write Protect)
sahilmgandhi 18:6a4db94011d3 6945 * | | |0 = PWM channel3 level-detect brake event do not happened.
sahilmgandhi 18:6a4db94011d3 6946 * | | |1 = When PWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
sahilmgandhi 18:6a4db94011d3 6947 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6948 * |[12] |BRKLIF4 |PWM Channel4 Level-Detect Brake Interrupt Flag (Write Protect)
sahilmgandhi 18:6a4db94011d3 6949 * | | |0 = PWM channel4 level-detect brake event do not happened.
sahilmgandhi 18:6a4db94011d3 6950 * | | |1 = When PWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
sahilmgandhi 18:6a4db94011d3 6951 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6952 * |[13] |BRKLIF5 |PWM Channel5 Level-Detect Brake Interrupt Flag (Write Protect)
sahilmgandhi 18:6a4db94011d3 6953 * | | |0 = PWM channel5 level-detect brake event do not happened.
sahilmgandhi 18:6a4db94011d3 6954 * | | |1 = When PWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
sahilmgandhi 18:6a4db94011d3 6955 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 6956 * |[16] |BRKESTS0 |PWM Channel0 Edge-Detect Brake Status
sahilmgandhi 18:6a4db94011d3 6957 * | | |0 = PWM channel0 edge-detect brake state is released.
sahilmgandhi 18:6a4db94011d3 6958 * | | |1 = When PWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state, writing 1 to clear.
sahilmgandhi 18:6a4db94011d3 6959 * |[17] |BRKESTS1 |PWM Channel1 Edge-Detect Brake Status
sahilmgandhi 18:6a4db94011d3 6960 * | | |0 = PWM channel1 edge-detect brake state is released.
sahilmgandhi 18:6a4db94011d3 6961 * | | |1 = When PWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state, writing 1 to clear.
sahilmgandhi 18:6a4db94011d3 6962 * |[18] |BRKESTS2 |PWM Channel2 Edge-Detect Brake Status
sahilmgandhi 18:6a4db94011d3 6963 * | | |0 = PWM channel2 edge-detect brake state is released.
sahilmgandhi 18:6a4db94011d3 6964 * | | |1 = When PWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state, writing 1 to clear.
sahilmgandhi 18:6a4db94011d3 6965 * |[19] |BRKESTS3 |PWM Channel3 Edge-Detect Brake Status
sahilmgandhi 18:6a4db94011d3 6966 * | | |0 = PWM channel3 edge-detect brake state is released.
sahilmgandhi 18:6a4db94011d3 6967 * | | |1 = When PWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state, writing 1 to clear.
sahilmgandhi 18:6a4db94011d3 6968 * |[20] |BRKESTS4 |PWM Channel4 Edge-Detect Brake Status
sahilmgandhi 18:6a4db94011d3 6969 * | | |0 = PWM channel4 edge-detect brake state is released.
sahilmgandhi 18:6a4db94011d3 6970 * | | |1 = When PWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state, writing 1 to clear.
sahilmgandhi 18:6a4db94011d3 6971 * |[21] |BRKESTS5 |PWM Channel5 Edge-Detect Brake Status
sahilmgandhi 18:6a4db94011d3 6972 * | | |0 = PWM channel5 edge-detect brake state is released.
sahilmgandhi 18:6a4db94011d3 6973 * | | |1 = When PWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state, writing 1 to clear.
sahilmgandhi 18:6a4db94011d3 6974 * |[24] |BRKLSTS0 |PWM Channel0 Level-Detect Brake Status (Read Only)
sahilmgandhi 18:6a4db94011d3 6975 * | | |0 = PWM channel0 level-detect brake state is released.
sahilmgandhi 18:6a4db94011d3 6976 * | | |1 = When PWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state.
sahilmgandhi 18:6a4db94011d3 6977 * | | |Note: This bit is read only and auto cleared by hardware.
sahilmgandhi 18:6a4db94011d3 6978 * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
sahilmgandhi 18:6a4db94011d3 6979 * | | |The PWM waveform will start output from next full PWM period.
sahilmgandhi 18:6a4db94011d3 6980 * |[25] |BRKLSTS1 |PWM Channel1 Level-Detect Brake Status (Read Only)
sahilmgandhi 18:6a4db94011d3 6981 * | | |0 = PWM channel1 level-detect brake state is released.
sahilmgandhi 18:6a4db94011d3 6982 * | | |1 = When PWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state.
sahilmgandhi 18:6a4db94011d3 6983 * | | |Note: This bit is read only and auto cleared by hardware.
sahilmgandhi 18:6a4db94011d3 6984 * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
sahilmgandhi 18:6a4db94011d3 6985 * | | |The PWM waveform will start output from next full PWM period.
sahilmgandhi 18:6a4db94011d3 6986 * |[26] |BRKLSTS2 |PWM Channel2 Level-Detect Brake Status (Read Only)
sahilmgandhi 18:6a4db94011d3 6987 * | | |0 = PWM channel2 level-detect brake state is released.
sahilmgandhi 18:6a4db94011d3 6988 * | | |1 = When PWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state.
sahilmgandhi 18:6a4db94011d3 6989 * | | |Note: This bit is read only and auto cleared by hardware.
sahilmgandhi 18:6a4db94011d3 6990 * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
sahilmgandhi 18:6a4db94011d3 6991 * | | |The PWM waveform will start output from next full PWM period.
sahilmgandhi 18:6a4db94011d3 6992 * |[27] |BRKLSTS3 |PWM Channel3 Level-Detect Brake Status (Read Only)
sahilmgandhi 18:6a4db94011d3 6993 * | | |0 = PWM channel3 level-detect brake state is released.
sahilmgandhi 18:6a4db94011d3 6994 * | | |1 = When PWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state.
sahilmgandhi 18:6a4db94011d3 6995 * | | |Note: This bit is read only and auto cleared by hardware.
sahilmgandhi 18:6a4db94011d3 6996 * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
sahilmgandhi 18:6a4db94011d3 6997 * | | |The PWM waveform will start output from next full PWM period.
sahilmgandhi 18:6a4db94011d3 6998 * |[28] |BRKLSTS4 |PWM Channel4 Level-Detect Brake Status (Read Only)
sahilmgandhi 18:6a4db94011d3 6999 * | | |0 = PWM channel4 level-detect brake state is released.
sahilmgandhi 18:6a4db94011d3 7000 * | | |1 = When PWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state.
sahilmgandhi 18:6a4db94011d3 7001 * | | |Note: This bit is read only and auto cleared by hardware.
sahilmgandhi 18:6a4db94011d3 7002 * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
sahilmgandhi 18:6a4db94011d3 7003 * | | |The PWM waveform will start output from next full PWM period.
sahilmgandhi 18:6a4db94011d3 7004 * |[29] |BRKLSTS5 |PWM Channel5 Level-Detect Brake Status (Read Only)
sahilmgandhi 18:6a4db94011d3 7005 * | | |0 = PWM channel5 level-detect brake state is released.
sahilmgandhi 18:6a4db94011d3 7006 * | | |1 = When PWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state.
sahilmgandhi 18:6a4db94011d3 7007 * | | |Note: This bit is read only and auto cleared by hardware.
sahilmgandhi 18:6a4db94011d3 7008 * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
sahilmgandhi 18:6a4db94011d3 7009 * | | |The PWM waveform will start output from next full PWM period.
sahilmgandhi 18:6a4db94011d3 7010 * @var PWM_T::IFA
sahilmgandhi 18:6a4db94011d3 7011 * Offset: 0xF0 PWM Interrupt Flag Accumulator Register
sahilmgandhi 18:6a4db94011d3 7012 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7013 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7014 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7015 * |[3:0] |IFCNT0_1 |PWM_CH0 And PWM_CH1 Interrupt Flag Counter
sahilmgandhi 18:6a4db94011d3 7016 * | | |The register sets the count number which defines how many times of PWM_CH0 and PWM_CH1 period occurs to set bit IFAIF0_1 to request the PWM period interrupt.
sahilmgandhi 18:6a4db94011d3 7017 * | | |PWM flag will be set in every IFCNT0_1 [3:0] times of PWM period.
sahilmgandhi 18:6a4db94011d3 7018 * |[6:4] |IFSEL0_1 |PWM_CH0 And PWM_CH1 Interrupt Flag Accumulator Source Select
sahilmgandhi 18:6a4db94011d3 7019 * | | |000 = CNT equal to Zero in channel 0.
sahilmgandhi 18:6a4db94011d3 7020 * | | |001 = CNT equal to PERIOD in channel 0.
sahilmgandhi 18:6a4db94011d3 7021 * | | |010 = CNT equal to CMPU in channel 0.
sahilmgandhi 18:6a4db94011d3 7022 * | | |011 = CNT equal to CMPD in channel 0.
sahilmgandhi 18:6a4db94011d3 7023 * | | |100 = CNT equal to Zero in channel 1.
sahilmgandhi 18:6a4db94011d3 7024 * | | |101 = CNT equal to PERIOD in channel 1.
sahilmgandhi 18:6a4db94011d3 7025 * | | |110 = CNT equal to CMPU in channel 1.
sahilmgandhi 18:6a4db94011d3 7026 * | | |111 = CNT equal to CMPD in channel 1.
sahilmgandhi 18:6a4db94011d3 7027 * |[7] |IFAEN0_1 |PWM_CH0 And PWM_CH1 Interrupt Flag Accumulator Enable
sahilmgandhi 18:6a4db94011d3 7028 * | | |0 = PWM_CH0 and PWM_CH1 interrupt flag accumulator disable.
sahilmgandhi 18:6a4db94011d3 7029 * | | |1 = PWM_CH0 and PWM_CH1 interrupt flag accumulator enable.
sahilmgandhi 18:6a4db94011d3 7030 * |[11:8] |IFCNT2_3 |PWM_CH2 And PWM_CH3 Interrupt Flag Counter
sahilmgandhi 18:6a4db94011d3 7031 * | | |The register sets the count number which defines how many times of PWM_CH2 and PWM_CH3 period occurs to set bit IFAIF2_3 to request the PWM period interrupt.
sahilmgandhi 18:6a4db94011d3 7032 * | | |PWM flag will be set in every IFCNT2_3[3:0] times of PWM period.
sahilmgandhi 18:6a4db94011d3 7033 * |[14:12] |IFSEL2_3 |PWM_CH2 And PWM_CH3 Interrupt Flag Accumulator Source Select
sahilmgandhi 18:6a4db94011d3 7034 * | | |000 = CNT equal to Zero in channel 2.
sahilmgandhi 18:6a4db94011d3 7035 * | | |001 = CNT equal to PERIOD in channel 2.
sahilmgandhi 18:6a4db94011d3 7036 * | | |010 = CNT equal to CMPU in channel 2.
sahilmgandhi 18:6a4db94011d3 7037 * | | |011 = CNT equal to CMPD in channel 2.
sahilmgandhi 18:6a4db94011d3 7038 * | | |100 = CNT equal to Zero in channel 3.
sahilmgandhi 18:6a4db94011d3 7039 * | | |101 = CNT equal to PERIOD in channel 3.
sahilmgandhi 18:6a4db94011d3 7040 * | | |110 = CNT equal to CMPU in channel 3.
sahilmgandhi 18:6a4db94011d3 7041 * | | |111 = CNT equal to CMPD in channel 3.
sahilmgandhi 18:6a4db94011d3 7042 * |[15] |IFAEN2_3 |PWM_CH2 And PWM_CH3 Interrupt Flag Accumulator Enable
sahilmgandhi 18:6a4db94011d3 7043 * | | |0 = PWM_CH2 and PWM_CH3 interrupt flag accumulator disable.
sahilmgandhi 18:6a4db94011d3 7044 * | | |1 = PWM_CH2 and PWM_CH3 interrupt flag accumulator enable.
sahilmgandhi 18:6a4db94011d3 7045 * |[19:16] |IFCNT4_5 |PWM_CH4 And PWM_CH5 Interrupt Flag Counter
sahilmgandhi 18:6a4db94011d3 7046 * | | |The register sets the count number which defines how many times of PWM_CH4 and PWM_CH5 period occurs to set bit IFAIF4_5 to request the PWM period interrupt.
sahilmgandhi 18:6a4db94011d3 7047 * | | |PWM flag will be set in every IFCNT4_5[3:0] times of PWM period.
sahilmgandhi 18:6a4db94011d3 7048 * |[22:20] |IFSEL4_5 |PWM_CH4 And PWM_CH5 Interrupt Flag Accumulator Source Select
sahilmgandhi 18:6a4db94011d3 7049 * | | |000 = CNT equal to Zero in channel 4.
sahilmgandhi 18:6a4db94011d3 7050 * | | |001 = CNT equal to PERIOD in channel 4.
sahilmgandhi 18:6a4db94011d3 7051 * | | |010 = CNT equal to CMPU in channel 4.
sahilmgandhi 18:6a4db94011d3 7052 * | | |011 = CNT equal to CMPD in channel 4.
sahilmgandhi 18:6a4db94011d3 7053 * | | |100 = CNT equal to Zero in channel 5.
sahilmgandhi 18:6a4db94011d3 7054 * | | |101 = CNT equal to PERIOD in channel 5.
sahilmgandhi 18:6a4db94011d3 7055 * | | |110 = CNT equal to CMPU in channel 5.
sahilmgandhi 18:6a4db94011d3 7056 * | | |111 = CNT equal to CMPD in channel 5.
sahilmgandhi 18:6a4db94011d3 7057 * |[23] |IFAEN4_5 |PWM_CH4 And PWM_CH5 Interrupt Flag Accumulator Enable
sahilmgandhi 18:6a4db94011d3 7058 * | | |0 = PWM_CH4 and PWM_CH5 interrupt flag accumulator disable.
sahilmgandhi 18:6a4db94011d3 7059 * | | |1 = PWM_CH4 and PWM_CH5 interrupt flag accumulator enable.
sahilmgandhi 18:6a4db94011d3 7060 * @var PWM_T::DACTRGEN
sahilmgandhi 18:6a4db94011d3 7061 * Offset: 0xF4 PWM Trigger DAC Enable Register
sahilmgandhi 18:6a4db94011d3 7062 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7063 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7064 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7065 * |[5:0] |ZTEn |PWM Zero Point Trigger DAC Enable
sahilmgandhi 18:6a4db94011d3 7066 * | | |0 = PWM period point trigger DAC function Disabled.
sahilmgandhi 18:6a4db94011d3 7067 * | | |1 = PWM period point trigger DAC function Enabled.
sahilmgandhi 18:6a4db94011d3 7068 * | | |PWM can trigger EADC/DAC/DMA to start action when PWM counter down count to zero if this bit is set to 1.
sahilmgandhi 18:6a4db94011d3 7069 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 7070 * |[13:8] |PTEn |PWM Period Point Trigger DAC Enable
sahilmgandhi 18:6a4db94011d3 7071 * | | |0 = PWM period point trigger DAC function Disabled.
sahilmgandhi 18:6a4db94011d3 7072 * | | |1 = PWM period point trigger DAC function Enabled.
sahilmgandhi 18:6a4db94011d3 7073 * | | |PWM can trigger DAC to start action when PWM counter up count to (PERIODn+1) if this bit is set to 1.
sahilmgandhi 18:6a4db94011d3 7074 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 7075 * |[21:16] |CUTRGEn |PWM Compare Up Count Point Trigger DAC Enable
sahilmgandhi 18:6a4db94011d3 7076 * | | |0 = PWM Compare Up point trigger DAC function Disabled.
sahilmgandhi 18:6a4db94011d3 7077 * | | |1 = PWM Compare Up point trigger DAC function Enabled.
sahilmgandhi 18:6a4db94011d3 7078 * | | |PWM can trigger DAC to start action when PWM counter up count to CMPDAT if this bit is set to 1.
sahilmgandhi 18:6a4db94011d3 7079 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 7080 * | | |Note1: This bit should keep at 0 when PWM counter operating in down counter type.
sahilmgandhi 18:6a4db94011d3 7081 * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
sahilmgandhi 18:6a4db94011d3 7082 * |[29:24] |CDTRGEn |PWM Compare Down Count Point Trigger DAC Enable
sahilmgandhi 18:6a4db94011d3 7083 * | | |0 = PWM Compare Down count point trigger DAC function Disabled.
sahilmgandhi 18:6a4db94011d3 7084 * | | |1 = PWM Compare Down count point trigger DAC function Enabled.
sahilmgandhi 18:6a4db94011d3 7085 * | | |PWM can trigger DAC to start action when PWM counter down count to CMPDAT if this bit is set to 1.
sahilmgandhi 18:6a4db94011d3 7086 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 7087 * | | |Note1: This bit should keep at 0 when PWM counter operating in up counter type.
sahilmgandhi 18:6a4db94011d3 7088 * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
sahilmgandhi 18:6a4db94011d3 7089 * @var PWM_T::EADCTS0
sahilmgandhi 18:6a4db94011d3 7090 * Offset: 0xF8 PWM Trigger EADC Source Select Register 0
sahilmgandhi 18:6a4db94011d3 7091 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7092 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7093 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7094 * |[3:0] |TRGSEL0 |PWM_CH0 Trigger EADC Source Select
sahilmgandhi 18:6a4db94011d3 7095 * | | |0000 = PWM_CH0 zero point.
sahilmgandhi 18:6a4db94011d3 7096 * | | |0001 = PWM_CH0 period point.
sahilmgandhi 18:6a4db94011d3 7097 * | | |0010 = PWM_CH0 zero or period point.
sahilmgandhi 18:6a4db94011d3 7098 * | | |0011 = PWM_CH0 up-count CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7099 * | | |0100 = PWM_CH0 down-count CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7100 * | | |0101 = PWM_CH1 zero point.
sahilmgandhi 18:6a4db94011d3 7101 * | | |0110 = PWM_CH1 period point.
sahilmgandhi 18:6a4db94011d3 7102 * | | |0111 = PWM_CH1 zero or period point.
sahilmgandhi 18:6a4db94011d3 7103 * | | |1000 = PWM_CH1 up-count CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7104 * | | |1001 = PWM_CH1 down-count CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7105 * | | |1010 = PWM_CH0 up-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7106 * | | |1011 = PWM_CH0 down-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7107 * | | |1100 = PWM_CH2 up-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7108 * | | |1101 = PWM_CH2 down-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7109 * | | |1110 = PWM_CH4 up-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7110 * | | |1111 = PWM_CH4 down-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7111 * |[7] |TRGEN0 |PWM_CH0 Trigger EADC enable bit
sahilmgandhi 18:6a4db94011d3 7112 * |[11:8] |TRGSEL1 |PWM_CH1 Trigger EADC Source Select
sahilmgandhi 18:6a4db94011d3 7113 * | | |0000 = PWM_CH0 zero point.
sahilmgandhi 18:6a4db94011d3 7114 * | | |0001 = PWM_CH0 period point.
sahilmgandhi 18:6a4db94011d3 7115 * | | |0010 = PWM_CH0 zero or period point.
sahilmgandhi 18:6a4db94011d3 7116 * | | |0011 = PWM_CH0 up-count CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7117 * | | |0100 = PWM_CH0 down-count CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7118 * | | |0101 = PWM_CH1 zero point.
sahilmgandhi 18:6a4db94011d3 7119 * | | |0110 = PWM_CH1 period point.
sahilmgandhi 18:6a4db94011d3 7120 * | | |0111 = PWM_CH1 zero or period point.
sahilmgandhi 18:6a4db94011d3 7121 * | | |1000 = PWM_CH1 up-count CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7122 * | | |1001 = PWM_CH1 down-count CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7123 * | | |1010 = PWM_CH0 up-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7124 * | | |1011 = PWM_CH0 down-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7125 * | | |1100 = PWM_CH2 up-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7126 * | | |1101 = PWM_CH2 down-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7127 * | | |1110 = PWM_CH4 up-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7128 * | | |1111 = PWM_CH4 down-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7129 * |[15] |TRGEN1 |PWM_CH1 Trigger EADC enable bit
sahilmgandhi 18:6a4db94011d3 7130 * |[19:16] |TRGSEL2 |PWM_CH2 Trigger EADC Source Select
sahilmgandhi 18:6a4db94011d3 7131 * | | |0000 = PWM_CH2 zero point.
sahilmgandhi 18:6a4db94011d3 7132 * | | |0001 = PWM_CH2 period point.
sahilmgandhi 18:6a4db94011d3 7133 * | | |0010 = PWM_CH2 zero or period point.
sahilmgandhi 18:6a4db94011d3 7134 * | | |0011 = PWM_CH2 up-count CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7135 * | | |0100 = PWM_CH2 down-count CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7136 * | | |0101 = PWM_CH3 zero point.
sahilmgandhi 18:6a4db94011d3 7137 * | | |0110 = PWM_CH3 period point.
sahilmgandhi 18:6a4db94011d3 7138 * | | |0111 = PWM_CH3 zero or period point.
sahilmgandhi 18:6a4db94011d3 7139 * | | |1000 = PWM_CH3 up-count CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7140 * | | |1001 = PWM_CH3 down-count CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7141 * | | |1010 = PWM_CH0 up-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7142 * | | |1011 = PWM_CH0 down-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7143 * | | |1100 = PWM_CH2 up-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7144 * | | |1101 = PWM_CH2 down-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7145 * | | |1110 = PWM_CH4 up-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7146 * | | |1111 = PWM_CH4 down-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7147 * |[23] |TRGEN2 |PWM_CH2 Trigger EADC enable bit
sahilmgandhi 18:6a4db94011d3 7148 * |[27:24] |TRGSEL3 |PWM_CH3 Trigger EADC Source Select
sahilmgandhi 18:6a4db94011d3 7149 * | | |0000 = PWM_CH2 zero point.
sahilmgandhi 18:6a4db94011d3 7150 * | | |0001 = PWM_CH2 period point.
sahilmgandhi 18:6a4db94011d3 7151 * | | |0010 = PWM_CH2 zero or period point.
sahilmgandhi 18:6a4db94011d3 7152 * | | |0011 = PWM_CH2 up-count CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7153 * | | |0100 = PWM_CH2 down-count CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7154 * | | |0101 = PWM_CH3 zero point.
sahilmgandhi 18:6a4db94011d3 7155 * | | |0110 = PWM_CH3 period point.
sahilmgandhi 18:6a4db94011d3 7156 * | | |0111 = PWM_CH3 zero or period point.
sahilmgandhi 18:6a4db94011d3 7157 * | | |1000 = PWM_CH3 up-count CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7158 * | | |1001 = PWM_CH3 down-count CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7159 * | | |1010 = PWM_CH0 up-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7160 * | | |1011 = PWM_CH0 down-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7161 * | | |1100 = PWM_CH2 up-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7162 * | | |1101 = PWM_CH2 down-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7163 * | | |1110 = PWM_CH4 up-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7164 * | | |1111 = PWM_CH4 down-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7165 * |[31] |TRGEN3 |PWM_CH3 Trigger EADC enable bit
sahilmgandhi 18:6a4db94011d3 7166 * @var PWM_T::EADCTS1
sahilmgandhi 18:6a4db94011d3 7167 * Offset: 0xFC PWM Trigger EADC Source Select Register 1
sahilmgandhi 18:6a4db94011d3 7168 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7169 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7170 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7171 * |[3:0] |TRGSEL4 |PWM_CH4 Trigger EADC Source Select
sahilmgandhi 18:6a4db94011d3 7172 * | | |0000 = PWM_CH4 zero point.
sahilmgandhi 18:6a4db94011d3 7173 * | | |0001 = PWM_CH4 period point.
sahilmgandhi 18:6a4db94011d3 7174 * | | |0010 = PWM_CH4 zero or period point.
sahilmgandhi 18:6a4db94011d3 7175 * | | |0011 = PWM_CH4 up-count CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7176 * | | |0100 = PWM_CH4 down-count CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7177 * | | |0101 = PWM_CH5 zero point.
sahilmgandhi 18:6a4db94011d3 7178 * | | |0110 = PWM_CH5 period point.
sahilmgandhi 18:6a4db94011d3 7179 * | | |0111 = PWM_CH5 zero or period point.
sahilmgandhi 18:6a4db94011d3 7180 * | | |1000 = PWM_CH5 up-count CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7181 * | | |1001 = PWM_CH5 down-count CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7182 * | | |1010 = PWM_CH0 up-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7183 * | | |1011 = PWM_CH0 down-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7184 * | | |1100 = PWM_CH2 up-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7185 * | | |1101 = PWM_CH2 down-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7186 * | | |1110 = PWM_CH4 up-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7187 * | | |1111 = PWM_CH4 down-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7188 * |[7] |TRGEN4 |PWM_CH4 Trigger EADC enable bit
sahilmgandhi 18:6a4db94011d3 7189 * |[11:8] |TRGSEL5 |PWM_CH5 Trigger EADC Source Select
sahilmgandhi 18:6a4db94011d3 7190 * | | |0000 = PWM_CH4 zero point.
sahilmgandhi 18:6a4db94011d3 7191 * | | |0001 = PWM_CH4 period point.
sahilmgandhi 18:6a4db94011d3 7192 * | | |0010 = PWM_CH4 zero or period point.
sahilmgandhi 18:6a4db94011d3 7193 * | | |0011 = PWM_CH4 up-count CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7194 * | | |0100 = PWM_CH4 down-count CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7195 * | | |0101 = PWM_CH5 zero point.
sahilmgandhi 18:6a4db94011d3 7196 * | | |0110 = PWM_CH5 period point.
sahilmgandhi 18:6a4db94011d3 7197 * | | |0111 = PWM_CH5 zero or period point.
sahilmgandhi 18:6a4db94011d3 7198 * | | |1000 = PWM_CH5 up-count CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7199 * | | |1001 = PWM_CH5 down-count CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7200 * | | |1010 = PWM_CH0 up-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7201 * | | |1011 = PWM_CH0 down-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7202 * | | |1100 = PWM_CH2 up-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7203 * | | |1101 = PWM_CH2 down-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7204 * | | |1110 = PWM_CH4 up-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7205 * | | |1111 = PWM_CH4 down-count free CMPDAT point.
sahilmgandhi 18:6a4db94011d3 7206 * |[15] |TRGEN5 |PWM_CH5 Trigger EADC enable bit
sahilmgandhi 18:6a4db94011d3 7207 * @var PWM_T::FTCMPDAT0_1
sahilmgandhi 18:6a4db94011d3 7208 * Offset: 0x100 PWM Free Trigger Compare Register 0
sahilmgandhi 18:6a4db94011d3 7209 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7210 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7211 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7212 * |[15:0] |FTCMP |PWM Free Trigger Compare Register
sahilmgandhi 18:6a4db94011d3 7213 * | | |FTCMP use to compare with even CNTR to trigger EADC.
sahilmgandhi 18:6a4db94011d3 7214 * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs PWM_CH0and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
sahilmgandhi 18:6a4db94011d3 7215 * @var PWM_T::FTCMPDAT2_3
sahilmgandhi 18:6a4db94011d3 7216 * Offset: 0x104 PWM Free Trigger Compare Register 2
sahilmgandhi 18:6a4db94011d3 7217 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7218 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7219 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7220 * |[15:0] |FTCMP |PWM Free Trigger Compare Register
sahilmgandhi 18:6a4db94011d3 7221 * | | |FTCMP use to compare with even CNTR to trigger EADC.
sahilmgandhi 18:6a4db94011d3 7222 * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs PWM_CH0and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
sahilmgandhi 18:6a4db94011d3 7223 * @var PWM_T::FTCMPDAT4_5
sahilmgandhi 18:6a4db94011d3 7224 * Offset: 0x108 PWM Free Trigger Compare Register 4
sahilmgandhi 18:6a4db94011d3 7225 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7226 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7227 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7228 * |[15:0] |FTCMP |PWM Free Trigger Compare Register
sahilmgandhi 18:6a4db94011d3 7229 * | | |FTCMP use to compare with even CNTR to trigger EADC.
sahilmgandhi 18:6a4db94011d3 7230 * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs PWM_CH0and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
sahilmgandhi 18:6a4db94011d3 7231 * @var PWM_T::SSCTL
sahilmgandhi 18:6a4db94011d3 7232 * Offset: 0x110 PWM Synchronous Start Control Register
sahilmgandhi 18:6a4db94011d3 7233 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7234 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7235 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7236 * |[5:0] |SSENn |PWM Synchronous Start Function Enable
sahilmgandhi 18:6a4db94011d3 7237 * | | |When synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
sahilmgandhi 18:6a4db94011d3 7238 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 7239 * | | |0 = PWM synchronous start function Disabled.
sahilmgandhi 18:6a4db94011d3 7240 * | | |1 = PWM synchronous start function Enabled.
sahilmgandhi 18:6a4db94011d3 7241 * @var PWM_T::SSTRG
sahilmgandhi 18:6a4db94011d3 7242 * Offset: 0x114 PWM Synchronous Start Trigger Register
sahilmgandhi 18:6a4db94011d3 7243 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7244 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7245 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7246 * |[0] |CNTSEN |PWM Counter Synchronous Start Enable (Write Only)
sahilmgandhi 18:6a4db94011d3 7247 * | | |PMW counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time.
sahilmgandhi 18:6a4db94011d3 7248 * | | |Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated PWM channel counter synchronous start function is enabled.
sahilmgandhi 18:6a4db94011d3 7249 * | | |Note: This bit only present in PWM0_BA.
sahilmgandhi 18:6a4db94011d3 7250 * @var PWM_T::STATUS
sahilmgandhi 18:6a4db94011d3 7251 * Offset: 0x120 PWM Status Register
sahilmgandhi 18:6a4db94011d3 7252 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7253 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7254 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7255 * |[5:0] |CNTMAXFn |Time-Base Counter Equal To 0xFFFF Latched Flag
sahilmgandhi 18:6a4db94011d3 7256 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 7257 * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
sahilmgandhi 18:6a4db94011d3 7258 * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
sahilmgandhi 18:6a4db94011d3 7259 * |[10:8] |SYNCINFn |Input Synchronization Latched Flag
sahilmgandhi 18:6a4db94011d3 7260 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 7261 * | | |0 = Indicates no SYNC_IN event has occurred.
sahilmgandhi 18:6a4db94011d3 7262 * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.
sahilmgandhi 18:6a4db94011d3 7263 * |[21:16] |ADCTRGFn |EADC Start Of Conversion Flag
sahilmgandhi 18:6a4db94011d3 7264 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 7265 * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
sahilmgandhi 18:6a4db94011d3 7266 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
sahilmgandhi 18:6a4db94011d3 7267 * |[24] |DACTRGF |DAC Start Of Conversion Flag
sahilmgandhi 18:6a4db94011d3 7268 * | | |0 = Indicates no DAC start of conversion trigger event has occurred.
sahilmgandhi 18:6a4db94011d3 7269 * | | |1 = Indicates an DAC start of conversion trigger event has occurred, software can write 1 to clear this bit
sahilmgandhi 18:6a4db94011d3 7270 * @var PWM_T::CAPINEN
sahilmgandhi 18:6a4db94011d3 7271 * Offset: 0x200 PWM Capture Input Enable Register
sahilmgandhi 18:6a4db94011d3 7272 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7273 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7274 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7275 * |[5:0] |CAPINENn |Capture Input Enable
sahilmgandhi 18:6a4db94011d3 7276 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 7277 * | | |0 = PWM Channel capture input path Disabled.
sahilmgandhi 18:6a4db94011d3 7278 * | | |The input of PWM channel capture function is always regarded as 0.
sahilmgandhi 18:6a4db94011d3 7279 * | | |1 = PWM Channel capture input path Enabled.
sahilmgandhi 18:6a4db94011d3 7280 * | | |The input of PWM channel capture function comes from correlative multifunction pin.
sahilmgandhi 18:6a4db94011d3 7281 * @var PWM_T::CAPCTL
sahilmgandhi 18:6a4db94011d3 7282 * Offset: 0x204 PWM Capture Control Register
sahilmgandhi 18:6a4db94011d3 7283 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7284 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7285 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7286 * |[5:0] |CAPENn |Capture Function Enable
sahilmgandhi 18:6a4db94011d3 7287 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 7288 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
sahilmgandhi 18:6a4db94011d3 7289 * | | |1 = Capture function Enabled.
sahilmgandhi 18:6a4db94011d3 7290 * | | |Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
sahilmgandhi 18:6a4db94011d3 7291 * |[13:8] |CAPINVn |Capture Inverter Enable
sahilmgandhi 18:6a4db94011d3 7292 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 7293 * | | |0 = Capture source inverter Disabled.
sahilmgandhi 18:6a4db94011d3 7294 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
sahilmgandhi 18:6a4db94011d3 7295 * |[21:16] |RCRLDENn |Rising Capture Reload Enable
sahilmgandhi 18:6a4db94011d3 7296 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 7297 * | | |0 = Rising capture reload counter Disabled.
sahilmgandhi 18:6a4db94011d3 7298 * | | |1 = Rising capture reload counter Enabled.
sahilmgandhi 18:6a4db94011d3 7299 * |[29:24] |FCRLDENn |Falling Capture Reload Enable
sahilmgandhi 18:6a4db94011d3 7300 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 7301 * | | |0 = Falling capture reload counter Disabled.
sahilmgandhi 18:6a4db94011d3 7302 * | | |1 = Falling capture reload counter Enabled.
sahilmgandhi 18:6a4db94011d3 7303 * @var PWM_T::CAPSTS
sahilmgandhi 18:6a4db94011d3 7304 * Offset: 0x208 PWM Capture Status Register
sahilmgandhi 18:6a4db94011d3 7305 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7306 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7307 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7308 * |[5:0] |CRLIFOVn |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
sahilmgandhi 18:6a4db94011d3 7309 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
sahilmgandhi 18:6a4db94011d3 7310 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 7311 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
sahilmgandhi 18:6a4db94011d3 7312 * |[13:8] |CFLIFOVn |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
sahilmgandhi 18:6a4db94011d3 7313 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
sahilmgandhi 18:6a4db94011d3 7314 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 7315 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
sahilmgandhi 18:6a4db94011d3 7316 * @var PWM_T::RCAPDAT0
sahilmgandhi 18:6a4db94011d3 7317 * Offset: 0x20C PWM Rising Capture Data Register 0
sahilmgandhi 18:6a4db94011d3 7318 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7319 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7320 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7321 * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
sahilmgandhi 18:6a4db94011d3 7322 * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
sahilmgandhi 18:6a4db94011d3 7323 * @var PWM_T::FCAPDAT0
sahilmgandhi 18:6a4db94011d3 7324 * Offset: 0x210 PWM Falling Capture Data Register 0
sahilmgandhi 18:6a4db94011d3 7325 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7326 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7327 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7328 * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
sahilmgandhi 18:6a4db94011d3 7329 * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
sahilmgandhi 18:6a4db94011d3 7330 * @var PWM_T::RCAPDAT1
sahilmgandhi 18:6a4db94011d3 7331 * Offset: 0x214 PWM Rising Capture Data Register 1
sahilmgandhi 18:6a4db94011d3 7332 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7333 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7334 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7335 * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
sahilmgandhi 18:6a4db94011d3 7336 * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
sahilmgandhi 18:6a4db94011d3 7337 * @var PWM_T::FCAPDAT1
sahilmgandhi 18:6a4db94011d3 7338 * Offset: 0x218 PWM Falling Capture Data Register 1
sahilmgandhi 18:6a4db94011d3 7339 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7340 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7341 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7342 * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
sahilmgandhi 18:6a4db94011d3 7343 * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
sahilmgandhi 18:6a4db94011d3 7344 * @var PWM_T::RCAPDAT2
sahilmgandhi 18:6a4db94011d3 7345 * Offset: 0x21C PWM Rising Capture Data Register 2
sahilmgandhi 18:6a4db94011d3 7346 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7347 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7348 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7349 * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
sahilmgandhi 18:6a4db94011d3 7350 * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
sahilmgandhi 18:6a4db94011d3 7351 * @var PWM_T::FCAPDAT2
sahilmgandhi 18:6a4db94011d3 7352 * Offset: 0x220 PWM Falling Capture Data Register 2
sahilmgandhi 18:6a4db94011d3 7353 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7354 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7355 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7356 * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
sahilmgandhi 18:6a4db94011d3 7357 * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
sahilmgandhi 18:6a4db94011d3 7358 * @var PWM_T::RCAPDAT3
sahilmgandhi 18:6a4db94011d3 7359 * Offset: 0x224 PWM Rising Capture Data Register 3
sahilmgandhi 18:6a4db94011d3 7360 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7361 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7362 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7363 * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
sahilmgandhi 18:6a4db94011d3 7364 * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
sahilmgandhi 18:6a4db94011d3 7365 * @var PWM_T::FCAPDAT3
sahilmgandhi 18:6a4db94011d3 7366 * Offset: 0x228 PWM Falling Capture Data Register 3
sahilmgandhi 18:6a4db94011d3 7367 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7368 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7369 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7370 * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
sahilmgandhi 18:6a4db94011d3 7371 * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
sahilmgandhi 18:6a4db94011d3 7372 * @var PWM_T::RCAPDAT4
sahilmgandhi 18:6a4db94011d3 7373 * Offset: 0x22C PWM Rising Capture Data Register 4
sahilmgandhi 18:6a4db94011d3 7374 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7375 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7376 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7377 * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
sahilmgandhi 18:6a4db94011d3 7378 * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
sahilmgandhi 18:6a4db94011d3 7379 * @var PWM_T::FCAPDAT4
sahilmgandhi 18:6a4db94011d3 7380 * Offset: 0x230 PWM Falling Capture Data Register 4
sahilmgandhi 18:6a4db94011d3 7381 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7382 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7383 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7384 * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
sahilmgandhi 18:6a4db94011d3 7385 * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
sahilmgandhi 18:6a4db94011d3 7386 * @var PWM_T::RCAPDAT5
sahilmgandhi 18:6a4db94011d3 7387 * Offset: 0x234 PWM Rising Capture Data Register 5
sahilmgandhi 18:6a4db94011d3 7388 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7389 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7390 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7391 * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
sahilmgandhi 18:6a4db94011d3 7392 * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
sahilmgandhi 18:6a4db94011d3 7393 * @var PWM_T::FCAPDAT5
sahilmgandhi 18:6a4db94011d3 7394 * Offset: 0x238 PWM Falling Capture Data Register 5
sahilmgandhi 18:6a4db94011d3 7395 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7396 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7397 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7398 * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
sahilmgandhi 18:6a4db94011d3 7399 * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
sahilmgandhi 18:6a4db94011d3 7400 * @var PWM_T::PDMACTL
sahilmgandhi 18:6a4db94011d3 7401 * Offset: 0x23C PWM PDMA Control Register
sahilmgandhi 18:6a4db94011d3 7402 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7403 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7404 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7405 * |[0] |CHEN0_1 |Channel 0/1 PDMA Enable
sahilmgandhi 18:6a4db94011d3 7406 * | | |0 = Channel 0/1 PDMA function Disabled.
sahilmgandhi 18:6a4db94011d3 7407 * | | |1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory.
sahilmgandhi 18:6a4db94011d3 7408 * |[2:1] |CAPMOD0_1 |Select PWM_RCAPDAT0/1 Or PWM_FCAPDAT0/1 To Do PDMA Transfer
sahilmgandhi 18:6a4db94011d3 7409 * | | |00 = Reserved.
sahilmgandhi 18:6a4db94011d3 7410 * | | |01 = PWM_RCAPDAT0/1.
sahilmgandhi 18:6a4db94011d3 7411 * | | |10 = PWM_FCAPDAT0/1.
sahilmgandhi 18:6a4db94011d3 7412 * | | |11 = Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1.
sahilmgandhi 18:6a4db94011d3 7413 * |[3] |CAPORD0_1 |Capture Channel 0/1 Rising/Falling Order
sahilmgandhi 18:6a4db94011d3 7414 * | | |Set this bit to determine whether the PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 is the first captured data transferred to memory through PDMA when CAPMOD0_1 = 11.
sahilmgandhi 18:6a4db94011d3 7415 * | | |0 = PWM_FCAPDAT0/1 is the first captured data to memory.
sahilmgandhi 18:6a4db94011d3 7416 * | | |1 = PWM_RCAPDAT0/1 is the first captured data to memory.
sahilmgandhi 18:6a4db94011d3 7417 * |[4] |CHSEL0_1 |Select Channel 0/1 To Do PDMA Transfer
sahilmgandhi 18:6a4db94011d3 7418 * | | |0 = Channel0.
sahilmgandhi 18:6a4db94011d3 7419 * | | |1 = Channel1.
sahilmgandhi 18:6a4db94011d3 7420 * |[8] |CHEN2_3 |Channel 2/3 PDMA Enable
sahilmgandhi 18:6a4db94011d3 7421 * | | |0 = Channel 2/3 PDMA function Disabled.
sahilmgandhi 18:6a4db94011d3 7422 * | | |1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory.
sahilmgandhi 18:6a4db94011d3 7423 * |[10:9] |CAPMOD2_3 |Select PWM_RCAPDAT2/3 Or PWM_FCAODAT2/3 To Do PDMA Transfer
sahilmgandhi 18:6a4db94011d3 7424 * | | |00 = Reserved.
sahilmgandhi 18:6a4db94011d3 7425 * | | |01 = PWM_RCAPDAT2/3.
sahilmgandhi 18:6a4db94011d3 7426 * | | |10 = PWM_FCAPDAT2/3.
sahilmgandhi 18:6a4db94011d3 7427 * | | |11 = Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3.
sahilmgandhi 18:6a4db94011d3 7428 * |[11] |CAPORD2_3 |Capture Channel 2/3 Rising/Falling Order
sahilmgandhi 18:6a4db94011d3 7429 * | | |Set this bit to determine whether the PWM_RCAPDAT2/3 or PWM_FCAPDAT2/3 is the first captured data transferred to memory through PDMA when CAPMOD2_3 = 11.
sahilmgandhi 18:6a4db94011d3 7430 * | | |0 = PWM_FCAPDAT2/3 is the first captured data to memory.
sahilmgandhi 18:6a4db94011d3 7431 * | | |1 = PWM_RCAPDAT2/3 is the first captured data to memory.
sahilmgandhi 18:6a4db94011d3 7432 * |[12] |CHSEL2_3 |Select Channel 2/3 To Do PDMA Transfer
sahilmgandhi 18:6a4db94011d3 7433 * | | |0 = Channel2.
sahilmgandhi 18:6a4db94011d3 7434 * | | |1 = Channel3.
sahilmgandhi 18:6a4db94011d3 7435 * |[16] |CHEN4_5 |Channel 4/5 PDMA Enable
sahilmgandhi 18:6a4db94011d3 7436 * | | |0 = Channel 4/5 PDMA function Disabled.
sahilmgandhi 18:6a4db94011d3 7437 * | | |1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory.
sahilmgandhi 18:6a4db94011d3 7438 * |[18:17] |CAPMOD4_5 |Select PWM_RCAPDAT4/5 Or PWM_FCAPDAT4/5 To Do PDMA Transfer
sahilmgandhi 18:6a4db94011d3 7439 * | | |00 = Reserved.
sahilmgandhi 18:6a4db94011d3 7440 * | | |01 = PWM_RCAPDAT4/5.
sahilmgandhi 18:6a4db94011d3 7441 * | | |10 = PWM_FCAPDAT4/5.
sahilmgandhi 18:6a4db94011d3 7442 * | | |11 = Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5.
sahilmgandhi 18:6a4db94011d3 7443 * |[19] |CAPORD4_5 |Capture Channel 4/5 Rising/Falling Order
sahilmgandhi 18:6a4db94011d3 7444 * | | |Set this bit to determine whether the PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 is the first captured data transferred to memory through PDMA when CAPMOD4_5 = 11.
sahilmgandhi 18:6a4db94011d3 7445 * | | |0 = PWM_FCAPDAT4/5 is the first captured data to memory.
sahilmgandhi 18:6a4db94011d3 7446 * | | |1 = PWM_RCAPDAT4/5 is the first captured data to memory.
sahilmgandhi 18:6a4db94011d3 7447 * |[20] |CHSEL4_5 |Select Channel 4/5 To Do PDMA Transfer
sahilmgandhi 18:6a4db94011d3 7448 * | | |0 = Channel4.
sahilmgandhi 18:6a4db94011d3 7449 * | | |1 = Channel5.
sahilmgandhi 18:6a4db94011d3 7450 * @var PWM_T::PDMACAP0_1
sahilmgandhi 18:6a4db94011d3 7451 * Offset: 0x240 PWM Capture Channel 01 PDMA Register
sahilmgandhi 18:6a4db94011d3 7452 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7453 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7454 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7455 * |[15:0] |CAPBUF |PWM Capture PDMA Register
sahilmgandhi 18:6a4db94011d3 7456 * | | |(Read Only)
sahilmgandhi 18:6a4db94011d3 7457 * | | |This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA.
sahilmgandhi 18:6a4db94011d3 7458 * @var PWM_T::PDMACAP2_3
sahilmgandhi 18:6a4db94011d3 7459 * Offset: 0x244 PWM Capture Channel 23 PDMA Register
sahilmgandhi 18:6a4db94011d3 7460 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7461 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7462 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7463 * |[15:0] |CAPBUF |PWM Capture PDMA Register
sahilmgandhi 18:6a4db94011d3 7464 * | | |(Read Only)
sahilmgandhi 18:6a4db94011d3 7465 * | | |This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA.
sahilmgandhi 18:6a4db94011d3 7466 * @var PWM_T::PDMACAP4_5
sahilmgandhi 18:6a4db94011d3 7467 * Offset: 0x248 PWM Capture Channel 45 PDMA Register
sahilmgandhi 18:6a4db94011d3 7468 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7469 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7470 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7471 * |[15:0] |CAPBUF |PWM Capture PDMA Register
sahilmgandhi 18:6a4db94011d3 7472 * | | |(Read Only)
sahilmgandhi 18:6a4db94011d3 7473 * | | |This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA.
sahilmgandhi 18:6a4db94011d3 7474 * @var PWM_T::CAPIEN
sahilmgandhi 18:6a4db94011d3 7475 * Offset: 0x250 PWM Capture Interrupt Enable Register
sahilmgandhi 18:6a4db94011d3 7476 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7477 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7478 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7479 * |[5:0] |CAPRIENn |PWM Capture Rising Latch Interrupt Enable
sahilmgandhi 18:6a4db94011d3 7480 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 7481 * | | |0 = Capture rising edge latch interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 7482 * | | |1 = Capture rising edge latch interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 7483 * | | |Note: When Capture with PDMA operating, CINTENR corresponding channel CAPRIEN must be disabled.
sahilmgandhi 18:6a4db94011d3 7484 * |[13:8] |CAPFIENn |PWM Capture Falling Latch Interrupt Enable
sahilmgandhi 18:6a4db94011d3 7485 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 7486 * | | |0 = Capture falling edge latch interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 7487 * | | |1 = Capture falling edge latch interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 7488 * | | |Note: When Capture with PDMA operating, CINTENR corresponding channel CAPFIEN must be disabled.
sahilmgandhi 18:6a4db94011d3 7489 * @var PWM_T::CAPIF
sahilmgandhi 18:6a4db94011d3 7490 * Offset: 0x254 PWM Capture Interrupt Flag Register
sahilmgandhi 18:6a4db94011d3 7491 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7492 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7493 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7494 * |[5:0] |CRLIFn |PWM Capture Rising Latch Interrupt Flag
sahilmgandhi 18:6a4db94011d3 7495 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 7496 * | | |0 = No capture rising latch condition happened.
sahilmgandhi 18:6a4db94011d3 7497 * | | |1 = Capture rising latch condition happened, this flag will be set to high.
sahilmgandhi 18:6a4db94011d3 7498 * | | |Note: When Capture with PDMA operating, CIFR corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
sahilmgandhi 18:6a4db94011d3 7499 * |[13:8] |CFLIFn |PWM Capture Falling Latch Interrupt Flag
sahilmgandhi 18:6a4db94011d3 7500 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 7501 * | | |0 = No capture falling latch condition happened.
sahilmgandhi 18:6a4db94011d3 7502 * | | |1 = Capture falling latch condition happened, this flag will be set to high.
sahilmgandhi 18:6a4db94011d3 7503 * | | |Note: When Capture with PDMA operating, CIFR corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
sahilmgandhi 18:6a4db94011d3 7504 * @var PWM_T::PBUF
sahilmgandhi 18:6a4db94011d3 7505 * Offset: 0x304~0x318 PWM PERIOD0~5 Buffer
sahilmgandhi 18:6a4db94011d3 7506 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7507 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7508 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7509 * |[15:0] |PBUF |PWM Period Register Buffer
sahilmgandhi 18:6a4db94011d3 7510 * | | |(Read Only)
sahilmgandhi 18:6a4db94011d3 7511 * | | |Used as PERIOD active register.
sahilmgandhi 18:6a4db94011d3 7512 * @var PWM_T::CMPBUF
sahilmgandhi 18:6a4db94011d3 7513 * Offset: 0x31C~0x330 PWM CMPDAT0~5 Buffer
sahilmgandhi 18:6a4db94011d3 7514 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7515 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7516 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7517 * |[15:0] |CMPBUF |PWM Comparator Register Buffer
sahilmgandhi 18:6a4db94011d3 7518 * | | |(Read Only)
sahilmgandhi 18:6a4db94011d3 7519 * | | |Used as CMP active register.
sahilmgandhi 18:6a4db94011d3 7520 * @var PWM_T::FTCBUF0_1
sahilmgandhi 18:6a4db94011d3 7521 * Offset: 0x340 PWM FTCMPDAT0_1 Buffer
sahilmgandhi 18:6a4db94011d3 7522 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7523 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7524 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7525 * |[15:0] |FTCMPBUF |PWM FTCMPDAT Buffer (Read Only)
sahilmgandhi 18:6a4db94011d3 7526 * | | |Used as FTCMPDAT active register.
sahilmgandhi 18:6a4db94011d3 7527 * @var PWM_T::FTCBUF2_3
sahilmgandhi 18:6a4db94011d3 7528 * Offset: 0x344 PWM FTCMPDAT2_3 Buffer
sahilmgandhi 18:6a4db94011d3 7529 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7530 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7531 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7532 * |[15:0] |FTCMPBUF |PWM FTCMPDAT Buffer (Read Only)
sahilmgandhi 18:6a4db94011d3 7533 * | | |Used as FTCMPDAT active register.
sahilmgandhi 18:6a4db94011d3 7534 * @var PWM_T::FTCBUF4_5
sahilmgandhi 18:6a4db94011d3 7535 * Offset: 0x348 PWM FTCMPDAT4_5 Buffer
sahilmgandhi 18:6a4db94011d3 7536 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7537 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7538 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7539 * |[15:0] |FTCMPBUF |PWM FTCMPDAT Buffer (Read Only)
sahilmgandhi 18:6a4db94011d3 7540 * | | |Used as FTCMPDAT active register.
sahilmgandhi 18:6a4db94011d3 7541 * @var PWM_T::FTCI
sahilmgandhi 18:6a4db94011d3 7542 * Offset: 0x34C PWM FTCMPDAT Indicator Register
sahilmgandhi 18:6a4db94011d3 7543 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 7544 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 7545 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 7546 * |[2:0] |FTCMUn |PWM FTCMPDAT Up Indicator
sahilmgandhi 18:6a4db94011d3 7547 * | | |Indicator will be set to high when FTCMPDATn equal to PERIODn and DIRF=1, software can write 1 to clear this bit.
sahilmgandhi 18:6a4db94011d3 7548 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 7549 * |[10:8] |FTCMDn |PWM FTCMPDAT Down Indicator
sahilmgandhi 18:6a4db94011d3 7550 * | | |Indicator will be set to high when FTCMPDATn equal to PERIODn and DIRF=0, software can write 1 to clear this bit.
sahilmgandhi 18:6a4db94011d3 7551 * | | |Each bit n controls the corresponding PWM channel n.
sahilmgandhi 18:6a4db94011d3 7552 */
sahilmgandhi 18:6a4db94011d3 7553
sahilmgandhi 18:6a4db94011d3 7554 __IO uint32_t CTL0; /* Offset: 0x00 PWM Control Register 0 */
sahilmgandhi 18:6a4db94011d3 7555 __IO uint32_t CTL1; /* Offset: 0x04 PWM Control Register 1 */
sahilmgandhi 18:6a4db94011d3 7556 __IO uint32_t SYNC; /* Offset: 0x08 PWM Synchronization Register */
sahilmgandhi 18:6a4db94011d3 7557 __IO uint32_t SWSYNC; /* Offset: 0x0C PWM Software Control Synchronization Register */
sahilmgandhi 18:6a4db94011d3 7558 __IO uint32_t CLKSRC; /* Offset: 0x10 PWM Clock Source Register */
sahilmgandhi 18:6a4db94011d3 7559 __IO uint32_t CLKPSC0_1; /* Offset: 0x14 PWM Clock Pre-scale Register 0 */
sahilmgandhi 18:6a4db94011d3 7560 __IO uint32_t CLKPSC2_3; /* Offset: 0x18 PWM Clock Pre-scale Register 2 */
sahilmgandhi 18:6a4db94011d3 7561 __IO uint32_t CLKPSC4_5; /* Offset: 0x1C PWM Clock Pre-scale Register 4 */
sahilmgandhi 18:6a4db94011d3 7562 __IO uint32_t CNTEN; /* Offset: 0x20 PWM Counter Enable Register */
sahilmgandhi 18:6a4db94011d3 7563 __IO uint32_t CNTCLR; /* Offset: 0x24 PWM Clear Counter Register */
sahilmgandhi 18:6a4db94011d3 7564 __IO uint32_t LOAD; /* Offset: 0x28 PWM Load Register */
sahilmgandhi 18:6a4db94011d3 7565 __I uint32_t RESERVE0[1];
sahilmgandhi 18:6a4db94011d3 7566 __IO uint32_t PERIOD[6]; /* Offset: 0x30~0x44 PWM Period Register 0~5 */
sahilmgandhi 18:6a4db94011d3 7567 __I uint32_t RESERVE1[2];
sahilmgandhi 18:6a4db94011d3 7568 __IO uint32_t CMPDAT[6]; /* Offset: 0x50~0x64 PWM Comparator Register 0~5 */
sahilmgandhi 18:6a4db94011d3 7569 __I uint32_t RESERVE2[2];
sahilmgandhi 18:6a4db94011d3 7570 __IO uint32_t DTCTL0_1; /* Offset: 0x70 PWM Dead-Time Control Register 0 */
sahilmgandhi 18:6a4db94011d3 7571 __IO uint32_t DTCTL2_3; /* Offset: 0x74 PWM Dead-Time Control Register 2 */
sahilmgandhi 18:6a4db94011d3 7572 __IO uint32_t DTCTL4_5; /* Offset: 0x78 PWM Dead-Time Control Register 4 */
sahilmgandhi 18:6a4db94011d3 7573 __I uint32_t RESERVE3[1];
sahilmgandhi 18:6a4db94011d3 7574 __IO uint32_t PHS0_1; /* Offset: 0x80 PWM Counter Phase Register 0 */
sahilmgandhi 18:6a4db94011d3 7575 __IO uint32_t PHS2_3; /* Offset: 0x84 PWM Counter Phase Register 2 */
sahilmgandhi 18:6a4db94011d3 7576 __IO uint32_t PHS4_5; /* Offset: 0x88 PWM Counter Phase Register 4 */
sahilmgandhi 18:6a4db94011d3 7577 __I uint32_t RESERVE4[1];
sahilmgandhi 18:6a4db94011d3 7578 __I uint32_t CNT[6]; /* Offset: 0x90~0xA4 PWM Counter Register 0~5 */
sahilmgandhi 18:6a4db94011d3 7579 __I uint32_t RESERVE5[2];
sahilmgandhi 18:6a4db94011d3 7580 __IO uint32_t WGCTL0; /* Offset: 0xB0 PWM Generation Register 0 */
sahilmgandhi 18:6a4db94011d3 7581 __IO uint32_t WGCTL1; /* Offset: 0xB4 PWM Generation Register 1 */
sahilmgandhi 18:6a4db94011d3 7582 __IO uint32_t MSKEN; /* Offset: 0xB8 PWM Mask Enable Register */
sahilmgandhi 18:6a4db94011d3 7583 __IO uint32_t MSK; /* Offset: 0xBC PWM Mask Data Register */
sahilmgandhi 18:6a4db94011d3 7584 __IO uint32_t BNF; /* Offset: 0xC0 PWM Brake Noise Filter Register */
sahilmgandhi 18:6a4db94011d3 7585 __IO uint32_t FAILBRK; /* Offset: 0xC4 PWM System Fail Brake Control Register */
sahilmgandhi 18:6a4db94011d3 7586 __IO uint32_t BRKCTL0_1; /* Offset: 0xC8 PWM Brake Edge Detect Control Register 0 */
sahilmgandhi 18:6a4db94011d3 7587 __IO uint32_t BRKCTL2_3; /* Offset: 0xCC PWM Brake Edge Detect Control Register 2 */
sahilmgandhi 18:6a4db94011d3 7588 __IO uint32_t BRKCTL4_5; /* Offset: 0xD0 PWM Brake Edge Detect Control Register 4 */
sahilmgandhi 18:6a4db94011d3 7589 __IO uint32_t POLCTL; /* Offset: 0xD4 PWM Pin Polar Inverse Register */
sahilmgandhi 18:6a4db94011d3 7590 __IO uint32_t POEN; /* Offset: 0xD8 PWM Output Enable Register */
sahilmgandhi 18:6a4db94011d3 7591 __O uint32_t SWBRK; /* Offset: 0xDC PWM Software Brake Control Register */
sahilmgandhi 18:6a4db94011d3 7592 __IO uint32_t INTEN0; /* Offset: 0xE0 PWM Interrupt Enable Register 0 */
sahilmgandhi 18:6a4db94011d3 7593 __IO uint32_t INTEN1; /* Offset: 0xE4 PWM Interrupt Enable Register 1 */
sahilmgandhi 18:6a4db94011d3 7594 __IO uint32_t INTSTS0; /* Offset: 0xE8 PWM Interrupt Flag Register 0 */
sahilmgandhi 18:6a4db94011d3 7595 __IO uint32_t INTSTS1; /* Offset: 0xEC PWM Interrupt Flag Register 1 */
sahilmgandhi 18:6a4db94011d3 7596 __IO uint32_t IFA; /* Offset: 0xF0 PWM Interrupt Flag Accumulator Register */
sahilmgandhi 18:6a4db94011d3 7597 __IO uint32_t DACTRGEN; /* Offset: 0xF4 PWM Trigger DAC Enable Register */
sahilmgandhi 18:6a4db94011d3 7598 __IO uint32_t EADCTS0; /* Offset: 0xF8 PWM Trigger EADC Source Select Register 0 */
sahilmgandhi 18:6a4db94011d3 7599 __IO uint32_t EADCTS1; /* Offset: 0xFC PWM Trigger EADC Source Select Register 1 */
sahilmgandhi 18:6a4db94011d3 7600 __IO uint32_t FTCMPDAT0_1; /* Offset: 0x100 PWM Free Trigger Compare Register 0 */
sahilmgandhi 18:6a4db94011d3 7601 __IO uint32_t FTCMPDAT2_3; /* Offset: 0x104 PWM Free Trigger Compare Register 2 */
sahilmgandhi 18:6a4db94011d3 7602 __IO uint32_t FTCMPDAT4_5; /* Offset: 0x108 PWM Free Trigger Compare Register 4 */
sahilmgandhi 18:6a4db94011d3 7603 __I uint32_t RESERVE6[1];
sahilmgandhi 18:6a4db94011d3 7604 __IO uint32_t SSCTL; /* Offset: 0x110 PWM Synchronous Start Control Register */
sahilmgandhi 18:6a4db94011d3 7605 __O uint32_t SSTRG; /* Offset: 0x114 PWM Synchronous Start Trigger Register */
sahilmgandhi 18:6a4db94011d3 7606 __I uint32_t RESERVE7[2];
sahilmgandhi 18:6a4db94011d3 7607 __IO uint32_t STATUS; /* Offset: 0x120 PWM Status Register */
sahilmgandhi 18:6a4db94011d3 7608 __I uint32_t RESERVE8[55];
sahilmgandhi 18:6a4db94011d3 7609 __IO uint32_t CAPINEN; /* Offset: 0x200 PWM Capture Input Enable Register */
sahilmgandhi 18:6a4db94011d3 7610 __IO uint32_t CAPCTL; /* Offset: 0x204 PWM Capture Control Register */
sahilmgandhi 18:6a4db94011d3 7611 __I uint32_t CAPSTS; /* Offset: 0x208 PWM Capture Status Register */
sahilmgandhi 18:6a4db94011d3 7612 __I uint32_t RCAPDAT0; /* Offset: 0x20C PWM Rising Capture Data Register 0 */
sahilmgandhi 18:6a4db94011d3 7613 __I uint32_t FCAPDAT0; /* Offset: 0x210 PWM Falling Capture Data Register 0 */
sahilmgandhi 18:6a4db94011d3 7614 __I uint32_t RCAPDAT1; /* Offset: 0x214 PWM Rising Capture Data Register 1 */
sahilmgandhi 18:6a4db94011d3 7615 __I uint32_t FCAPDAT1; /* Offset: 0x218 PWM Falling Capture Data Register 1 */
sahilmgandhi 18:6a4db94011d3 7616 __I uint32_t RCAPDAT2; /* Offset: 0x21C PWM Rising Capture Data Register 2 */
sahilmgandhi 18:6a4db94011d3 7617 __I uint32_t FCAPDAT2; /* Offset: 0x220 PWM Falling Capture Data Register 2 */
sahilmgandhi 18:6a4db94011d3 7618 __I uint32_t RCAPDAT3; /* Offset: 0x224 PWM Rising Capture Data Register 3 */
sahilmgandhi 18:6a4db94011d3 7619 __I uint32_t FCAPDAT3; /* Offset: 0x228 PWM Falling Capture Data Register 3 */
sahilmgandhi 18:6a4db94011d3 7620 __I uint32_t RCAPDAT4; /* Offset: 0x22C PWM Rising Capture Data Register 4 */
sahilmgandhi 18:6a4db94011d3 7621 __I uint32_t FCAPDAT4; /* Offset: 0x230 PWM Falling Capture Data Register 4 */
sahilmgandhi 18:6a4db94011d3 7622 __I uint32_t RCAPDAT5; /* Offset: 0x234 PWM Rising Capture Data Register 5 */
sahilmgandhi 18:6a4db94011d3 7623 __I uint32_t FCAPDAT5; /* Offset: 0x238 PWM Falling Capture Data Register 5 */
sahilmgandhi 18:6a4db94011d3 7624 __IO uint32_t PDMACTL; /* Offset: 0x23C PWM PDMA Control Register */
sahilmgandhi 18:6a4db94011d3 7625 __I uint32_t PDMACAP0_1; /* Offset: 0x240 PWM Capture Channel 01 PDMA Register */
sahilmgandhi 18:6a4db94011d3 7626 __I uint32_t PDMACAP2_3; /* Offset: 0x244 PWM Capture Channel 23 PDMA Register */
sahilmgandhi 18:6a4db94011d3 7627 __I uint32_t PDMACAP4_5; /* Offset: 0x248 PWM Capture Channel 45 PDMA Register */
sahilmgandhi 18:6a4db94011d3 7628 __I uint32_t RESERVE9[1];
sahilmgandhi 18:6a4db94011d3 7629 __IO uint32_t CAPIEN; /* Offset: 0x250 PWM Capture Interrupt Enable Register */
sahilmgandhi 18:6a4db94011d3 7630 __IO uint32_t CAPIF; /* Offset: 0x254 PWM Capture Interrupt Flag Register */
sahilmgandhi 18:6a4db94011d3 7631 __I uint32_t RESERVE10[43];
sahilmgandhi 18:6a4db94011d3 7632 __I uint32_t PBUF[6]; /* Offset: 0x304~0x318 PWM PERIOD0~5 Buffer */
sahilmgandhi 18:6a4db94011d3 7633 __I uint32_t CMPBUF[6]; /* Offset: 0x31C~0x330 PWM CMPDAT0~5 Buffer */
sahilmgandhi 18:6a4db94011d3 7634 __I uint32_t RESERVE11[3];
sahilmgandhi 18:6a4db94011d3 7635 __I uint32_t FTCBUF0_1; /* Offset: 0x340 PWM FTCMPDAT0_1 Buffer */
sahilmgandhi 18:6a4db94011d3 7636 __I uint32_t FTCBUF2_3; /* Offset: 0x344 PWM FTCMPDAT2_3 Buffer */
sahilmgandhi 18:6a4db94011d3 7637 __I uint32_t FTCBUF4_5; /* Offset: 0x348 PWM FTCMPDAT4_5 Buffer */
sahilmgandhi 18:6a4db94011d3 7638 __IO uint32_t FTCI; /* Offset: 0x34C PWM FTCMPDAT Indicator Register */
sahilmgandhi 18:6a4db94011d3 7639
sahilmgandhi 18:6a4db94011d3 7640 } PWM_T;
sahilmgandhi 18:6a4db94011d3 7641
sahilmgandhi 18:6a4db94011d3 7642
sahilmgandhi 18:6a4db94011d3 7643
sahilmgandhi 18:6a4db94011d3 7644 /**
sahilmgandhi 18:6a4db94011d3 7645 @addtogroup PWM_CONST PWM Bit Field Definition
sahilmgandhi 18:6a4db94011d3 7646 Constant Definitions for PWM Controller
sahilmgandhi 18:6a4db94011d3 7647 @{ */
sahilmgandhi 18:6a4db94011d3 7648
sahilmgandhi 18:6a4db94011d3 7649 #define PWM_CTL0_CTRLDn_Pos (0) /*!< PWM_T::CTL0: CTRLDn Position */
sahilmgandhi 18:6a4db94011d3 7650 #define PWM_CTL0_CTRLDn_Msk (0x3ful << PWM_CTL0_CTRLDn_Pos) /*!< PWM_T::CTL0: CTRLDn Mask */
sahilmgandhi 18:6a4db94011d3 7651
sahilmgandhi 18:6a4db94011d3 7652 #define PWM_CTL0_CTRLD0_Pos (0) /*!< PWM_T::CTL0: CTRLD0 Position */
sahilmgandhi 18:6a4db94011d3 7653 #define PWM_CTL0_CTRLD0_Msk (0x1ul << PWM_CTL0_CTRLD0_Pos) /*!< PWM_T::CTL0: CTRLD0 Mask */
sahilmgandhi 18:6a4db94011d3 7654
sahilmgandhi 18:6a4db94011d3 7655 #define PWM_CTL0_CTRLD1_Pos (1) /*!< PWM_T::CTL0: CTRLD1 Position */
sahilmgandhi 18:6a4db94011d3 7656 #define PWM_CTL0_CTRLD1_Msk (0x1ul << PWM_CTL0_CTRLD1_Pos) /*!< PWM_T::CTL0: CTRLD1 Mask */
sahilmgandhi 18:6a4db94011d3 7657
sahilmgandhi 18:6a4db94011d3 7658 #define PWM_CTL0_CTRLD2_Pos (2) /*!< PWM_T::CTL0: CTRLD2 Position */
sahilmgandhi 18:6a4db94011d3 7659 #define PWM_CTL0_CTRLD2_Msk (0x1ul << PWM_CTL0_CTRLD2_Pos) /*!< PWM_T::CTL0: CTRLD2 Mask */
sahilmgandhi 18:6a4db94011d3 7660
sahilmgandhi 18:6a4db94011d3 7661 #define PWM_CTL0_CTRLD3_Pos (3) /*!< PWM_T::CTL0: CTRLD3 Position */
sahilmgandhi 18:6a4db94011d3 7662 #define PWM_CTL0_CTRLD3_Msk (0x1ul << PWM_CTL0_CTRLD3_Pos) /*!< PWM_T::CTL0: CTRLD3 Mask */
sahilmgandhi 18:6a4db94011d3 7663
sahilmgandhi 18:6a4db94011d3 7664 #define PWM_CTL0_CTRLD4_Pos (4) /*!< PWM_T::CTL0: CTRLD4 Position */
sahilmgandhi 18:6a4db94011d3 7665 #define PWM_CTL0_CTRLD4_Msk (0x1ul << PWM_CTL0_CTRLD4_Pos) /*!< PWM_T::CTL0: CTRLD4 Mask */
sahilmgandhi 18:6a4db94011d3 7666
sahilmgandhi 18:6a4db94011d3 7667 #define PWM_CTL0_CTRLD5_Pos (5) /*!< PWM_T::CTL0: CTRLD5 Position */
sahilmgandhi 18:6a4db94011d3 7668 #define PWM_CTL0_CTRLD5_Msk (0x1ul << PWM_CTL0_CTRLD5_Pos) /*!< PWM_T::CTL0: CTRLD5 Mask */
sahilmgandhi 18:6a4db94011d3 7669
sahilmgandhi 18:6a4db94011d3 7670 #define PWM_CTL0_WINLDENn_Pos (8) /*!< PWM_T::CTL0: WINLDENn Position */
sahilmgandhi 18:6a4db94011d3 7671 #define PWM_CTL0_WINLDENn_Msk (0x3ful << PWM_CTL0_WINLDENn_Pos) /*!< PWM_T::CTL0: WINLDENn Mask */
sahilmgandhi 18:6a4db94011d3 7672
sahilmgandhi 18:6a4db94011d3 7673 #define PWM_CTL0_WINLDEN0_Pos (8) /*!< PWM_T::CTL0: WINLDEN0 Position */
sahilmgandhi 18:6a4db94011d3 7674 #define PWM_CTL0_WINLDEN0_Msk (0x1ul << PWM_CTL0_WINLDEN0_Pos) /*!< PWM_T::CTL0: WINLDEN0 Mask */
sahilmgandhi 18:6a4db94011d3 7675
sahilmgandhi 18:6a4db94011d3 7676 #define PWM_CTL0_WINLDEN1_Pos (9) /*!< PWM_T::CTL0: WINLDEN1 Position */
sahilmgandhi 18:6a4db94011d3 7677 #define PWM_CTL0_WINLDEN1_Msk (0x1ul << PWM_CTL0_WINLDEN1_Pos) /*!< PWM_T::CTL0: WINLDEN1 Mask */
sahilmgandhi 18:6a4db94011d3 7678
sahilmgandhi 18:6a4db94011d3 7679 #define PWM_CTL0_WINLDEN2_Pos (10) /*!< PWM_T::CTL0: WINLDEN2 Position */
sahilmgandhi 18:6a4db94011d3 7680 #define PWM_CTL0_WINLDEN2_Msk (0x1ul << PWM_CTL0_WINLDEN2_Pos) /*!< PWM_T::CTL0: WINLDEN2 Mask */
sahilmgandhi 18:6a4db94011d3 7681
sahilmgandhi 18:6a4db94011d3 7682 #define PWM_CTL0_WINLDEN3_Pos (11) /*!< PWM_T::CTL0: WINLDEN3 Position */
sahilmgandhi 18:6a4db94011d3 7683 #define PWM_CTL0_WINLDEN3_Msk (0x1ul << PWM_CTL0_WINLDEN3_Pos) /*!< PWM_T::CTL0: WINLDEN3 Mask */
sahilmgandhi 18:6a4db94011d3 7684
sahilmgandhi 18:6a4db94011d3 7685 #define PWM_CTL0_WINLDEN4_Pos (12) /*!< PWM_T::CTL0: WINLDEN4 Position */
sahilmgandhi 18:6a4db94011d3 7686 #define PWM_CTL0_WINLDEN4_Msk (0x1ul << PWM_CTL0_WINLDEN4_Pos) /*!< PWM_T::CTL0: WINLDEN4 Mask */
sahilmgandhi 18:6a4db94011d3 7687
sahilmgandhi 18:6a4db94011d3 7688 #define PWM_CTL0_WINLDEN5_Pos (13) /*!< PWM_T::CTL0: WINLDEN5 Position */
sahilmgandhi 18:6a4db94011d3 7689 #define PWM_CTL0_WINLDEN5_Msk (0x1ul << PWM_CTL0_WINLDEN5_Pos) /*!< PWM_T::CTL0: WINLDEN5 Mask */
sahilmgandhi 18:6a4db94011d3 7690
sahilmgandhi 18:6a4db94011d3 7691 #define PWM_CTL0_IMMLDENn_Pos (16) /*!< PWM_T::CTL0: IMMLDENn Position */
sahilmgandhi 18:6a4db94011d3 7692 #define PWM_CTL0_IMMLDENn_Msk (0x3ful << PWM_CTL0_IMMLDENn_Pos) /*!< PWM_T::CTL0: IMMLDENn Mask */
sahilmgandhi 18:6a4db94011d3 7693
sahilmgandhi 18:6a4db94011d3 7694 #define PWM_CTL0_IMMLDEN0_Pos (16) /*!< PWM_T::CTL0: IMMLDEN0 Position */
sahilmgandhi 18:6a4db94011d3 7695 #define PWM_CTL0_IMMLDEN0_Msk (0x1ul << PWM_CTL0_IMMLDEN0_Pos) /*!< PWM_T::CTL0: IMMLDEN0 Mask */
sahilmgandhi 18:6a4db94011d3 7696
sahilmgandhi 18:6a4db94011d3 7697 #define PWM_CTL0_IMMLDEN1_Pos (17) /*!< PWM_T::CTL0: IMMLDEN1 Position */
sahilmgandhi 18:6a4db94011d3 7698 #define PWM_CTL0_IMMLDEN1_Msk (0x1ul << PWM_CTL0_IMMLDEN1_Pos) /*!< PWM_T::CTL0: IMMLDEN1 Mask */
sahilmgandhi 18:6a4db94011d3 7699
sahilmgandhi 18:6a4db94011d3 7700 #define PWM_CTL0_IMMLDEN2_Pos (18) /*!< PWM_T::CTL0: IMMLDEN2 Position */
sahilmgandhi 18:6a4db94011d3 7701 #define PWM_CTL0_IMMLDEN2_Msk (0x1ul << PWM_CTL0_IMMLDEN2_Pos) /*!< PWM_T::CTL0: IMMLDEN2 Mask */
sahilmgandhi 18:6a4db94011d3 7702
sahilmgandhi 18:6a4db94011d3 7703 #define PWM_CTL0_IMMLDEN3_Pos (19) /*!< PWM_T::CTL0: IMMLDEN3 Position */
sahilmgandhi 18:6a4db94011d3 7704 #define PWM_CTL0_IMMLDEN3_Msk (0x1ul << PWM_CTL0_IMMLDEN3_Pos) /*!< PWM_T::CTL0: IMMLDEN3 Mask */
sahilmgandhi 18:6a4db94011d3 7705
sahilmgandhi 18:6a4db94011d3 7706 #define PWM_CTL0_IMMLDEN4_Pos (20) /*!< PWM_T::CTL0: IMMLDEN4 Position */
sahilmgandhi 18:6a4db94011d3 7707 #define PWM_CTL0_IMMLDEN4_Msk (0x1ul << PWM_CTL0_IMMLDEN4_Pos) /*!< PWM_T::CTL0: IMMLDEN4 Mask */
sahilmgandhi 18:6a4db94011d3 7708
sahilmgandhi 18:6a4db94011d3 7709 #define PWM_CTL0_IMMLDEN5_Pos (21) /*!< PWM_T::CTL0: IMMLDEN5 Position */
sahilmgandhi 18:6a4db94011d3 7710 #define PWM_CTL0_IMMLDEN5_Msk (0x1ul << PWM_CTL0_IMMLDEN5_Pos) /*!< PWM_T::CTL0: IMMLDEN5 Mask */
sahilmgandhi 18:6a4db94011d3 7711
sahilmgandhi 18:6a4db94011d3 7712 #define PWM_CTL0_GROUPEN_Pos (24) /*!< PWM_T::CTL0: GROUPEN Position */
sahilmgandhi 18:6a4db94011d3 7713 #define PWM_CTL0_GROUPEN_Msk (0x1ul << PWM_CTL0_GROUPEN_Pos) /*!< PWM_T::CTL0: GROUPEN Mask */
sahilmgandhi 18:6a4db94011d3 7714
sahilmgandhi 18:6a4db94011d3 7715 #define PWM_CTL0_DBGHALT_Pos (30) /*!< PWM_T::CTL0: DBGHALT Position */
sahilmgandhi 18:6a4db94011d3 7716 #define PWM_CTL0_DBGHALT_Msk (0x1ul << PWM_CTL0_DBGHALT_Pos) /*!< PWM_T::CTL0: DBGHALT Mask */
sahilmgandhi 18:6a4db94011d3 7717
sahilmgandhi 18:6a4db94011d3 7718 #define PWM_CTL0_DBGTRIOFF_Pos (31) /*!< PWM_T::CTL0: DBGTRIOFF Position */
sahilmgandhi 18:6a4db94011d3 7719 #define PWM_CTL0_DBGTRIOFF_Msk (0x1ul << PWM_CTL0_DBGTRIOFF_Pos) /*!< PWM_T::CTL0: DBGTRIOFF Mask */
sahilmgandhi 18:6a4db94011d3 7720
sahilmgandhi 18:6a4db94011d3 7721 #define PWM_CTL1_CNTTYPEn_Pos (0) /*!< PWM_T::CTL1: CNTTYPEn Position */
sahilmgandhi 18:6a4db94011d3 7722 #define PWM_CTL1_CNTTYPEn_Msk (0xffful << PWM_CTL1_CNTTYPEn_Pos) /*!< PWM_T::CTL1: CNTTYPEn Mask */
sahilmgandhi 18:6a4db94011d3 7723
sahilmgandhi 18:6a4db94011d3 7724 #define PWM_CTL1_CNTTYPE0_Pos (0) /*!< PWM_T::CTL1: CNTTYPE0 Position */
sahilmgandhi 18:6a4db94011d3 7725 #define PWM_CTL1_CNTTYPE0_Msk (0x3ul << PWM_CTL1_CNTTYPE0_Pos) /*!< PWM_T::CTL1: CNTTYPE0 Mask */
sahilmgandhi 18:6a4db94011d3 7726
sahilmgandhi 18:6a4db94011d3 7727 #define PWM_CTL1_CNTTYPE1_Pos (2) /*!< PWM_T::CTL1: CNTTYPE1 Position */
sahilmgandhi 18:6a4db94011d3 7728 #define PWM_CTL1_CNTTYPE1_Msk (0x3ul << PWM_CTL1_CNTTYPE1_Pos) /*!< PWM_T::CTL1: CNTTYPE1 Mask */
sahilmgandhi 18:6a4db94011d3 7729
sahilmgandhi 18:6a4db94011d3 7730 #define PWM_CTL1_CNTTYPE2_Pos (4) /*!< PWM_T::CTL1: CNTTYPE2 Position */
sahilmgandhi 18:6a4db94011d3 7731 #define PWM_CTL1_CNTTYPE2_Msk (0x3ul << PWM_CTL1_CNTTYPE2_Pos) /*!< PWM_T::CTL1: CNTTYPE2 Mask */
sahilmgandhi 18:6a4db94011d3 7732
sahilmgandhi 18:6a4db94011d3 7733 #define PWM_CTL1_CNTTYPE3_Pos (6) /*!< PWM_T::CTL1: CNTTYPE3 Position */
sahilmgandhi 18:6a4db94011d3 7734 #define PWM_CTL1_CNTTYPE3_Msk (0x3ul << PWM_CTL1_CNTTYPE3_Pos) /*!< PWM_T::CTL1: CNTTYPE3 Mask */
sahilmgandhi 18:6a4db94011d3 7735
sahilmgandhi 18:6a4db94011d3 7736 #define PWM_CTL1_CNTTYPE4_Pos (8) /*!< PWM_T::CTL1: CNTTYPE4 Position */
sahilmgandhi 18:6a4db94011d3 7737 #define PWM_CTL1_CNTTYPE4_Msk (0x3ul << PWM_CTL1_CNTTYPE4_Pos) /*!< PWM_T::CTL1: CNTTYPE4 Mask */
sahilmgandhi 18:6a4db94011d3 7738
sahilmgandhi 18:6a4db94011d3 7739 #define PWM_CTL1_CNTTYPE5_Pos (10) /*!< PWM_T::CTL1: CNTTYPE5 Position */
sahilmgandhi 18:6a4db94011d3 7740 #define PWM_CTL1_CNTTYPE5_Msk (0x3ul << PWM_CTL1_CNTTYPE5_Pos) /*!< PWM_T::CTL1: CNTTYPE5 Mask */
sahilmgandhi 18:6a4db94011d3 7741
sahilmgandhi 18:6a4db94011d3 7742 #define PWM_CTL1_CNTMODEn_Pos (16) /*!< PWM_T::CTL1: CNTMODEn Position */
sahilmgandhi 18:6a4db94011d3 7743 #define PWM_CTL1_CNTMODEn_Msk (0x3ful << PWM_CTL1_CNTMODEn_Pos) /*!< PWM_T::CTL1: CNTMODEn Mask */
sahilmgandhi 18:6a4db94011d3 7744
sahilmgandhi 18:6a4db94011d3 7745 #define PWM_CTL1_CNTMODE0_Pos (16) /*!< PWM_T::CTL1: CNTMODE0 Position */
sahilmgandhi 18:6a4db94011d3 7746 #define PWM_CTL1_CNTMODE0_Msk (0x1ul << PWM_CTL1_CNTMODE0_Pos) /*!< PWM_T::CTL1: CNTMODE0 Mask */
sahilmgandhi 18:6a4db94011d3 7747
sahilmgandhi 18:6a4db94011d3 7748 #define PWM_CTL1_CNTMODE1_Pos (17) /*!< PWM_T::CTL1: CNTMODE1 Position */
sahilmgandhi 18:6a4db94011d3 7749 #define PWM_CTL1_CNTMODE1_Msk (0x1ul << PWM_CTL1_CNTMODE1_Pos) /*!< PWM_T::CTL1: CNTMODE1 Mask */
sahilmgandhi 18:6a4db94011d3 7750
sahilmgandhi 18:6a4db94011d3 7751 #define PWM_CTL1_CNTMODE2_Pos (18) /*!< PWM_T::CTL1: CNTMODE2 Position */
sahilmgandhi 18:6a4db94011d3 7752 #define PWM_CTL1_CNTMODE2_Msk (0x1ul << PWM_CTL1_CNTMODE2_Pos) /*!< PWM_T::CTL1: CNTMODE2 Mask */
sahilmgandhi 18:6a4db94011d3 7753
sahilmgandhi 18:6a4db94011d3 7754 #define PWM_CTL1_CNTMODE3_Pos (19) /*!< PWM_T::CTL1: CNTMODE3 Position */
sahilmgandhi 18:6a4db94011d3 7755 #define PWM_CTL1_CNTMODE3_Msk (0x1ul << PWM_CTL1_CNTMODE3_Pos) /*!< PWM_T::CTL1: CNTMODE3 Mask */
sahilmgandhi 18:6a4db94011d3 7756
sahilmgandhi 18:6a4db94011d3 7757 #define PWM_CTL1_CNTMODE4_Pos (20) /*!< PWM_T::CTL1: CNTMODE4 Position */
sahilmgandhi 18:6a4db94011d3 7758 #define PWM_CTL1_CNTMODE4_Msk (0x1ul << PWM_CTL1_CNTMODE4_Pos) /*!< PWM_T::CTL1: CNTMODE4 Mask */
sahilmgandhi 18:6a4db94011d3 7759
sahilmgandhi 18:6a4db94011d3 7760 #define PWM_CTL1_CNTMODE5_Pos (21) /*!< PWM_T::CTL1: CNTMODE5 Position */
sahilmgandhi 18:6a4db94011d3 7761 #define PWM_CTL1_CNTMODE5_Msk (0x1ul << PWM_CTL1_CNTMODE5_Pos) /*!< PWM_T::CTL1: CNTMODE5 Mask */
sahilmgandhi 18:6a4db94011d3 7762
sahilmgandhi 18:6a4db94011d3 7763 #define PWM_CTL1_OUTMODEn_Pos (24) /*!< PWM_T::CTL1: OUTMODEn Position */
sahilmgandhi 18:6a4db94011d3 7764 #define PWM_CTL1_OUTMODEn_Msk (0x7ul << PWM_CTL1_OUTMODEn_Pos) /*!< PWM_T::CTL1: OUTMODEn Mask */
sahilmgandhi 18:6a4db94011d3 7765
sahilmgandhi 18:6a4db94011d3 7766 #define PWM_CTL1_OUTMODE0_Pos (24) /*!< PWM_T::CTL1: OUTMODE0 Position */
sahilmgandhi 18:6a4db94011d3 7767 #define PWM_CTL1_OUTMODE0_Msk (0x1ul << PWM_CTL1_OUTMODE0_Pos) /*!< PWM_T::CTL1: OUTMODE0 Mask */
sahilmgandhi 18:6a4db94011d3 7768
sahilmgandhi 18:6a4db94011d3 7769 #define PWM_CTL1_OUTMODE2_Pos (25) /*!< PWM_T::CTL1: OUTMODE2 Position */
sahilmgandhi 18:6a4db94011d3 7770 #define PWM_CTL1_OUTMODE2_Msk (0x1ul << PWM_CTL1_OUTMODE2_Pos) /*!< PWM_T::CTL1: OUTMODE2 Mask */
sahilmgandhi 18:6a4db94011d3 7771
sahilmgandhi 18:6a4db94011d3 7772 #define PWM_CTL1_OUTMODE4_Pos (26) /*!< PWM_T::CTL1: OUTMODE4 Position */
sahilmgandhi 18:6a4db94011d3 7773 #define PWM_CTL1_OUTMODE4_Msk (0x1ul << PWM_CTL1_OUTMODE4_Pos) /*!< PWM_T::CTL1: OUTMODE4 Mask */
sahilmgandhi 18:6a4db94011d3 7774
sahilmgandhi 18:6a4db94011d3 7775 #define PWM_SYNC_PHSENn_Pos (0) /*!< PWM_T::SYNC: PHSENn Position */
sahilmgandhi 18:6a4db94011d3 7776 #define PWM_SYNC_PHSENn_Msk (0x7ul << PWM_SYNC_PHSENn_Pos) /*!< PWM_T::SYNC: PHSENn Mask */
sahilmgandhi 18:6a4db94011d3 7777
sahilmgandhi 18:6a4db94011d3 7778 #define PWM_SYNC_PHSEN0_Pos (0) /*!< PWM_T::SYNC: PHSEN0 Position */
sahilmgandhi 18:6a4db94011d3 7779 #define PWM_SYNC_PHSEN0_Msk (0x1ul << PWM_SYNC_PHSEN0_Pos) /*!< PWM_T::SYNC: PHSEN0 Mask */
sahilmgandhi 18:6a4db94011d3 7780
sahilmgandhi 18:6a4db94011d3 7781 #define PWM_SYNC_PHSEN2_Pos (1) /*!< PWM_T::SYNC: PHSEN2 Position */
sahilmgandhi 18:6a4db94011d3 7782 #define PWM_SYNC_PHSEN2_Msk (0x1ul << PWM_SYNC_PHSEN2_Pos) /*!< PWM_T::SYNC: PHSEN2 Mask */
sahilmgandhi 18:6a4db94011d3 7783
sahilmgandhi 18:6a4db94011d3 7784 #define PWM_SYNC_PHSEN4_Pos (2) /*!< PWM_T::SYNC: PHSEN4 Position */
sahilmgandhi 18:6a4db94011d3 7785 #define PWM_SYNC_PHSEN4_Msk (0x1ul << PWM_SYNC_PHSEN4_Pos) /*!< PWM_T::SYNC: PHSEN4 Mask */
sahilmgandhi 18:6a4db94011d3 7786
sahilmgandhi 18:6a4db94011d3 7787 #define PWM_SYNC_SINSRCn_Pos (8) /*!< PWM_T::SYNC: SINSRCn Position */
sahilmgandhi 18:6a4db94011d3 7788 #define PWM_SYNC_SINSRCn_Msk (0x3ful << PWM_SYNC_SINSRCn_Pos) /*!< PWM_T::SYNC: SINSRCn Mask */
sahilmgandhi 18:6a4db94011d3 7789
sahilmgandhi 18:6a4db94011d3 7790 #define PWM_SYNC_SINSRC0_Pos (8) /*!< PWM_T::SYNC: SINSRC0 Position */
sahilmgandhi 18:6a4db94011d3 7791 #define PWM_SYNC_SINSRC0_Msk (0x3ul << PWM_SYNC_SINSRC0_Pos) /*!< PWM_T::SYNC: SINSRC0 Mask */
sahilmgandhi 18:6a4db94011d3 7792
sahilmgandhi 18:6a4db94011d3 7793 #define PWM_SYNC_SINSRC2_Pos (10) /*!< PWM_T::SYNC: SINSRC2 Position */
sahilmgandhi 18:6a4db94011d3 7794 #define PWM_SYNC_SINSRC2_Msk (0x3ul << PWM_SYNC_SINSRC2_Pos) /*!< PWM_T::SYNC: SINSRC2 Mask */
sahilmgandhi 18:6a4db94011d3 7795
sahilmgandhi 18:6a4db94011d3 7796 #define PWM_SYNC_SINSRC4_Pos (12) /*!< PWM_T::SYNC: SINSRC4 Position */
sahilmgandhi 18:6a4db94011d3 7797 #define PWM_SYNC_SINSRC4_Msk (0x3ul << PWM_SYNC_SINSRC4_Pos) /*!< PWM_T::SYNC: SINSRC4 Mask */
sahilmgandhi 18:6a4db94011d3 7798
sahilmgandhi 18:6a4db94011d3 7799 #define PWM_SYNC_SNFLTEN_Pos (16) /*!< PWM_T::SYNC: SNFLTEN Position */
sahilmgandhi 18:6a4db94011d3 7800 #define PWM_SYNC_SNFLTEN_Msk (0x1ul << PWM_SYNC_SNFLTEN_Pos) /*!< PWM_T::SYNC: SNFLTEN Mask */
sahilmgandhi 18:6a4db94011d3 7801
sahilmgandhi 18:6a4db94011d3 7802 #define PWM_SYNC_SFLTCSEL_Pos (17) /*!< PWM_T::SYNC: SFLTCSEL Position */
sahilmgandhi 18:6a4db94011d3 7803 #define PWM_SYNC_SFLTCSEL_Msk (0x7ul << PWM_SYNC_SFLTCSEL_Pos) /*!< PWM_T::SYNC: SFLTCSEL Mask */
sahilmgandhi 18:6a4db94011d3 7804
sahilmgandhi 18:6a4db94011d3 7805 #define PWM_SYNC_SFLTCNT_Pos (20) /*!< PWM_T::SYNC: SFLTCNT Position */
sahilmgandhi 18:6a4db94011d3 7806 #define PWM_SYNC_SFLTCNT_Msk (0x7ul << PWM_SYNC_SFLTCNT_Pos) /*!< PWM_T::SYNC: SFLTCNT Mask */
sahilmgandhi 18:6a4db94011d3 7807
sahilmgandhi 18:6a4db94011d3 7808 #define PWM_SYNC_SINPINV_Pos (23) /*!< PWM_T::SYNC: SINPINV Position */
sahilmgandhi 18:6a4db94011d3 7809 #define PWM_SYNC_SINPINV_Msk (0x1ul << PWM_SYNC_SINPINV_Pos) /*!< PWM_T::SYNC: SINPINV Mask */
sahilmgandhi 18:6a4db94011d3 7810
sahilmgandhi 18:6a4db94011d3 7811 #define PWM_SYNC_PHSDIRn_Pos (24) /*!< PWM_T::SYNC: PHSDIRn Position */
sahilmgandhi 18:6a4db94011d3 7812 #define PWM_SYNC_PHSDIRn_Msk (0x7ul << PWM_SYNC_PHSDIRn_Pos) /*!< PWM_T::SYNC: PHSDIRn Mask */
sahilmgandhi 18:6a4db94011d3 7813
sahilmgandhi 18:6a4db94011d3 7814 #define PWM_SYNC_PHSDIR0_Pos (24) /*!< PWM_T::SYNC: PHSDIR0 Position */
sahilmgandhi 18:6a4db94011d3 7815 #define PWM_SYNC_PHSDIR0_Msk (0x1ul << PWM_SYNC_PHSDIR0_Pos) /*!< PWM_T::SYNC: PHSDIR0 Mask */
sahilmgandhi 18:6a4db94011d3 7816
sahilmgandhi 18:6a4db94011d3 7817 #define PWM_SYNC_PHSDIR2_Pos (25) /*!< PWM_T::SYNC: PHSDIR2 Position */
sahilmgandhi 18:6a4db94011d3 7818 #define PWM_SYNC_PHSDIR2_Msk (0x1ul << PWM_SYNC_PHSDIR2_Pos) /*!< PWM_T::SYNC: PHSDIR2 Mask */
sahilmgandhi 18:6a4db94011d3 7819
sahilmgandhi 18:6a4db94011d3 7820 #define PWM_SYNC_PHSDIR4_Pos (26) /*!< PWM_T::SYNC: PHSDIR4 Position */
sahilmgandhi 18:6a4db94011d3 7821 #define PWM_SYNC_PHSDIR4_Msk (0x1ul << PWM_SYNC_PHSDIR4_Pos) /*!< PWM_T::SYNC: PHSDIR4 Mask */
sahilmgandhi 18:6a4db94011d3 7822
sahilmgandhi 18:6a4db94011d3 7823 #define PWM_SWSYNC_SWSYNCn_Pos (0) /*!< PWM_T::SWSYNC: SWSYNCn Position */
sahilmgandhi 18:6a4db94011d3 7824 #define PWM_SWSYNC_SWSYNCn_Msk (0x7ul << PWM_SWSYNC_SWSYNCn_Pos) /*!< PWM_T::SWSYNC: SWSYNCn Mask */
sahilmgandhi 18:6a4db94011d3 7825
sahilmgandhi 18:6a4db94011d3 7826 #define PWM_SWSYNC_SWSYNC0_Pos (0) /*!< PWM_T::SWSYNC: SWSYNC0 Position */
sahilmgandhi 18:6a4db94011d3 7827 #define PWM_SWSYNC_SWSYNC0_Msk (0x1ul << PWM_SWSYNC_SWSYNC0_Pos) /*!< PWM_T::SWSYNC: SWSYNC0 Mask */
sahilmgandhi 18:6a4db94011d3 7828
sahilmgandhi 18:6a4db94011d3 7829 #define PWM_SWSYNC_SWSYNC2_Pos (1) /*!< PWM_T::SWSYNC: SWSYNC2 Position */
sahilmgandhi 18:6a4db94011d3 7830 #define PWM_SWSYNC_SWSYNC2_Msk (0x1ul << PWM_SWSYNC_SWSYNC2_Pos) /*!< PWM_T::SWSYNC: SWSYNC2 Mask */
sahilmgandhi 18:6a4db94011d3 7831
sahilmgandhi 18:6a4db94011d3 7832 #define PWM_SWSYNC_SWSYNC4_Pos (2) /*!< PWM_T::SWSYNC: SWSYNC4 Position */
sahilmgandhi 18:6a4db94011d3 7833 #define PWM_SWSYNC_SWSYNC4_Msk (0x1ul << PWM_SWSYNC_SWSYNC4_Pos) /*!< PWM_T::SWSYNC: SWSYNC4 Mask */
sahilmgandhi 18:6a4db94011d3 7834
sahilmgandhi 18:6a4db94011d3 7835 #define PWM_CLKSRC_ECLKSRC0_Pos (0) /*!< PWM_T::CLKSRC: ECLKSRC0 Position */
sahilmgandhi 18:6a4db94011d3 7836 #define PWM_CLKSRC_ECLKSRC0_Msk (0x7ul << PWM_CLKSRC_ECLKSRC0_Pos) /*!< PWM_T::CLKSRC: ECLKSRC0 Mask */
sahilmgandhi 18:6a4db94011d3 7837
sahilmgandhi 18:6a4db94011d3 7838 #define PWM_CLKSRC_ECLKSRC2_Pos (8) /*!< PWM_T::CLKSRC: ECLKSRC2 Position */
sahilmgandhi 18:6a4db94011d3 7839 #define PWM_CLKSRC_ECLKSRC2_Msk (0x7ul << PWM_CLKSRC_ECLKSRC2_Pos) /*!< PWM_T::CLKSRC: ECLKSRC2 Mask */
sahilmgandhi 18:6a4db94011d3 7840
sahilmgandhi 18:6a4db94011d3 7841 #define PWM_CLKSRC_ECLKSRC4_Pos (16) /*!< PWM_T::CLKSRC: ECLKSRC4 Position */
sahilmgandhi 18:6a4db94011d3 7842 #define PWM_CLKSRC_ECLKSRC4_Msk (0x7ul << PWM_CLKSRC_ECLKSRC4_Pos) /*!< PWM_T::CLKSRC: ECLKSRC4 Mask */
sahilmgandhi 18:6a4db94011d3 7843
sahilmgandhi 18:6a4db94011d3 7844 #define PWM_CLKPSC0_1_CLKPSC_Pos (0) /*!< PWM_T::CLKPSC0_1: CLKPSC Position */
sahilmgandhi 18:6a4db94011d3 7845 #define PWM_CLKPSC0_1_CLKPSC_Msk (0xffful << PWM_CLKPSC0_1_CLKPSC_Pos) /*!< PWM_T::CLKPSC0_1: CLKPSC Mask */
sahilmgandhi 18:6a4db94011d3 7846
sahilmgandhi 18:6a4db94011d3 7847 #define PWM_CLKPSC2_3_CLKPSC_Pos (0) /*!< PWM_T::CLKPSC2_3: CLKPSC Position */
sahilmgandhi 18:6a4db94011d3 7848 #define PWM_CLKPSC2_3_CLKPSC_Msk (0xffful << PWM_CLKPSC2_3_CLKPSC_Pos) /*!< PWM_T::CLKPSC2_3: CLKPSC Mask */
sahilmgandhi 18:6a4db94011d3 7849
sahilmgandhi 18:6a4db94011d3 7850 #define PWM_CLKPSC4_5_CLKPSC_Pos (0) /*!< PWM_T::CLKPSC4_5: CLKPSC Position */
sahilmgandhi 18:6a4db94011d3 7851 #define PWM_CLKPSC4_5_CLKPSC_Msk (0xffful << PWM_CLKPSC4_5_CLKPSC_Pos) /*!< PWM_T::CLKPSC4_5: CLKPSC Mask */
sahilmgandhi 18:6a4db94011d3 7852
sahilmgandhi 18:6a4db94011d3 7853 #define PWM_CNTEN_CNTENn_Pos (0) /*!< PWM_T::CNTEN: CNTENn Position */
sahilmgandhi 18:6a4db94011d3 7854 #define PWM_CNTEN_CNTENn_Msk (0x3ful << PWM_CNTEN_CNTENn_Pos) /*!< PWM_T::CNTEN: CNTENn Mask */
sahilmgandhi 18:6a4db94011d3 7855
sahilmgandhi 18:6a4db94011d3 7856 #define PWM_CNTEN_CNTEN0_Pos (0) /*!< PWM_T::CNTEN: CNTEN0 Position */
sahilmgandhi 18:6a4db94011d3 7857 #define PWM_CNTEN_CNTEN0_Msk (0x1ul << PWM_CNTEN_CNTEN0_Pos) /*!< PWM_T::CNTEN: CNTEN0 Mask */
sahilmgandhi 18:6a4db94011d3 7858
sahilmgandhi 18:6a4db94011d3 7859 #define PWM_CNTEN_CNTEN1_Pos (1) /*!< PWM_T::CNTEN: CNTEN1 Position */
sahilmgandhi 18:6a4db94011d3 7860 #define PWM_CNTEN_CNTEN1_Msk (0x1ul << PWM_CNTEN_CNTEN1_Pos) /*!< PWM_T::CNTEN: CNTEN1 Mask */
sahilmgandhi 18:6a4db94011d3 7861
sahilmgandhi 18:6a4db94011d3 7862 #define PWM_CNTEN_CNTEN2_Pos (2) /*!< PWM_T::CNTEN: CNTEN2 Position */
sahilmgandhi 18:6a4db94011d3 7863 #define PWM_CNTEN_CNTEN2_Msk (0x1ul << PWM_CNTEN_CNTEN2_Pos) /*!< PWM_T::CNTEN: CNTEN2 Mask */
sahilmgandhi 18:6a4db94011d3 7864
sahilmgandhi 18:6a4db94011d3 7865 #define PWM_CNTEN_CNTEN3_Pos (3) /*!< PWM_T::CNTEN: CNTEN3 Position */
sahilmgandhi 18:6a4db94011d3 7866 #define PWM_CNTEN_CNTEN3_Msk (0x1ul << PWM_CNTEN_CNTEN3_Pos) /*!< PWM_T::CNTEN: CNTEN3 Mask */
sahilmgandhi 18:6a4db94011d3 7867
sahilmgandhi 18:6a4db94011d3 7868 #define PWM_CNTEN_CNTEN4_Pos (4) /*!< PWM_T::CNTEN: CNTEN4 Position */
sahilmgandhi 18:6a4db94011d3 7869 #define PWM_CNTEN_CNTEN4_Msk (0x1ul << PWM_CNTEN_CNTEN4_Pos) /*!< PWM_T::CNTEN: CNTEN4 Mask */
sahilmgandhi 18:6a4db94011d3 7870
sahilmgandhi 18:6a4db94011d3 7871 #define PWM_CNTEN_CNTEN5_Pos (5) /*!< PWM_T::CNTEN: CNTEN5 Position */
sahilmgandhi 18:6a4db94011d3 7872 #define PWM_CNTEN_CNTEN5_Msk (0x1ul << PWM_CNTEN_CNTEN5_Pos) /*!< PWM_T::CNTEN: CNTEN5 Mask */
sahilmgandhi 18:6a4db94011d3 7873
sahilmgandhi 18:6a4db94011d3 7874 #define PWM_CNTCLR_CNTCLRn_Pos (0) /*!< PWM_T::CNTCLR: CNTCLRn Position */
sahilmgandhi 18:6a4db94011d3 7875 #define PWM_CNTCLR_CNTCLRn_Msk (0x3ful << PWM_CNTCLR_CNTCLRn_Pos) /*!< PWM_T::CNTCLR: CNTCLRn Mask */
sahilmgandhi 18:6a4db94011d3 7876
sahilmgandhi 18:6a4db94011d3 7877 #define PWM_CNTCLR_CNTCLR0_Pos (0) /*!< PWM_T::CNTCLR: CNTCLR0 Position */
sahilmgandhi 18:6a4db94011d3 7878 #define PWM_CNTCLR_CNTCLR0_Msk (0x1ul << PWM_CNTCLR_CNTCLR0_Pos) /*!< PWM_T::CNTCLR: CNTCLR0 Mask */
sahilmgandhi 18:6a4db94011d3 7879
sahilmgandhi 18:6a4db94011d3 7880 #define PWM_CNTCLR_CNTCLR1_Pos (1) /*!< PWM_T::CNTCLR: CNTCLR1 Position */
sahilmgandhi 18:6a4db94011d3 7881 #define PWM_CNTCLR_CNTCLR1_Msk (0x1ul << PWM_CNTCLR_CNTCLR1_Pos) /*!< PWM_T::CNTCLR: CNTCLR1 Mask */
sahilmgandhi 18:6a4db94011d3 7882
sahilmgandhi 18:6a4db94011d3 7883 #define PWM_CNTCLR_CNTCLR2_Pos (2) /*!< PWM_T::CNTCLR: CNTCLR2 Position */
sahilmgandhi 18:6a4db94011d3 7884 #define PWM_CNTCLR_CNTCLR2_Msk (0x1ul << PWM_CNTCLR_CNTCLR2_Pos) /*!< PWM_T::CNTCLR: CNTCLR2 Mask */
sahilmgandhi 18:6a4db94011d3 7885
sahilmgandhi 18:6a4db94011d3 7886 #define PWM_CNTCLR_CNTCLR3_Pos (3) /*!< PWM_T::CNTCLR: CNTCLR3 Position */
sahilmgandhi 18:6a4db94011d3 7887 #define PWM_CNTCLR_CNTCLR3_Msk (0x1ul << PWM_CNTCLR_CNTCLR3_Pos) /*!< PWM_T::CNTCLR: CNTCLR3 Mask */
sahilmgandhi 18:6a4db94011d3 7888
sahilmgandhi 18:6a4db94011d3 7889 #define PWM_CNTCLR_CNTCLR4_Pos (4) /*!< PWM_T::CNTCLR: CNTCLR4 Position */
sahilmgandhi 18:6a4db94011d3 7890 #define PWM_CNTCLR_CNTCLR4_Msk (0x1ul << PWM_CNTCLR_CNTCLR4_Pos) /*!< PWM_T::CNTCLR: CNTCLR4 Mask */
sahilmgandhi 18:6a4db94011d3 7891
sahilmgandhi 18:6a4db94011d3 7892 #define PWM_CNTCLR_CNTCLR5_Pos (5) /*!< PWM_T::CNTCLR: CNTCLR5 Position */
sahilmgandhi 18:6a4db94011d3 7893 #define PWM_CNTCLR_CNTCLR5_Msk (0x1ul << PWM_CNTCLR_CNTCLR5_Pos) /*!< PWM_T::CNTCLR: CNTCLR5 Mask */
sahilmgandhi 18:6a4db94011d3 7894
sahilmgandhi 18:6a4db94011d3 7895 #define PWM_LOAD_LOADn_Pos (0) /*!< PWM_T::LOAD: LOADn Position */
sahilmgandhi 18:6a4db94011d3 7896 #define PWM_LOAD_LOADn_Msk (0x3ful << PWM_LOAD_LOADn_Pos) /*!< PWM_T::LOAD: LOADn Mask */
sahilmgandhi 18:6a4db94011d3 7897
sahilmgandhi 18:6a4db94011d3 7898 #define PWM_LOAD_LOAD0_Pos (0) /*!< PWM_T::LOAD: LOAD0 Position */
sahilmgandhi 18:6a4db94011d3 7899 #define PWM_LOAD_LOAD0_Msk (0x1ul << PWM_LOAD_LOAD0_Pos) /*!< PWM_T::LOAD: LOAD0 Mask */
sahilmgandhi 18:6a4db94011d3 7900
sahilmgandhi 18:6a4db94011d3 7901 #define PWM_LOAD_LOAD1_Pos (1) /*!< PWM_T::LOAD: LOAD1 Position */
sahilmgandhi 18:6a4db94011d3 7902 #define PWM_LOAD_LOAD1_Msk (0x1ul << PWM_LOAD_LOAD1_Pos) /*!< PWM_T::LOAD: LOAD1 Mask */
sahilmgandhi 18:6a4db94011d3 7903
sahilmgandhi 18:6a4db94011d3 7904 #define PWM_LOAD_LOAD2_Pos (2) /*!< PWM_T::LOAD: LOAD2 Position */
sahilmgandhi 18:6a4db94011d3 7905 #define PWM_LOAD_LOAD2_Msk (0x1ul << PWM_LOAD_LOAD2_Pos) /*!< PWM_T::LOAD: LOAD2 Mask */
sahilmgandhi 18:6a4db94011d3 7906
sahilmgandhi 18:6a4db94011d3 7907 #define PWM_LOAD_LOAD3_Pos (3) /*!< PWM_T::LOAD: LOAD3 Position */
sahilmgandhi 18:6a4db94011d3 7908 #define PWM_LOAD_LOAD3_Msk (0x1ul << PWM_LOAD_LOAD3_Pos) /*!< PWM_T::LOAD: LOAD3 Mask */
sahilmgandhi 18:6a4db94011d3 7909
sahilmgandhi 18:6a4db94011d3 7910 #define PWM_LOAD_LOAD4_Pos (4) /*!< PWM_T::LOAD: LOAD4 Position */
sahilmgandhi 18:6a4db94011d3 7911 #define PWM_LOAD_LOAD4_Msk (0x1ul << PWM_LOAD_LOAD4_Pos) /*!< PWM_T::LOAD: LOAD4 Mask */
sahilmgandhi 18:6a4db94011d3 7912
sahilmgandhi 18:6a4db94011d3 7913 #define PWM_LOAD_LOAD5_Pos (5) /*!< PWM_T::LOAD: LOAD5 Position */
sahilmgandhi 18:6a4db94011d3 7914 #define PWM_LOAD_LOAD5_Msk (0x1ul << PWM_LOAD_LOAD5_Pos) /*!< PWM_T::LOAD: LOAD5 Mask */
sahilmgandhi 18:6a4db94011d3 7915
sahilmgandhi 18:6a4db94011d3 7916 #define PWM_PERIOD_PERIOD_Pos (0) /*!< PWM_T::PERIOD: PERIOD Position */
sahilmgandhi 18:6a4db94011d3 7917 #define PWM_PERIOD_PERIOD_Msk (0xfffful << PWM_PERIOD_PERIOD_Pos) /*!< PWM_T::PERIOD: PERIOD Mask */
sahilmgandhi 18:6a4db94011d3 7918
sahilmgandhi 18:6a4db94011d3 7919 #define PWM_CMPDAT_CMP_Pos (0) /*!< PWM_T::CMPDAT: CMP Position */
sahilmgandhi 18:6a4db94011d3 7920 #define PWM_CMPDAT_CMP_Msk (0xfffful << PWM_CMPDAT_CMP_Pos) /*!< PWM_T::CMPDAT: CMP Mask */
sahilmgandhi 18:6a4db94011d3 7921
sahilmgandhi 18:6a4db94011d3 7922 #define PWM_DTCTL0_1_DTCNT_Pos (0) /*!< PWM_T::DTCTL0_1: DTCNT Position */
sahilmgandhi 18:6a4db94011d3 7923 #define PWM_DTCTL0_1_DTCNT_Msk (0xffful << PWM_DTCTL0_1_DTCNT_Pos) /*!< PWM_T::DTCTL0_1: DTCNT Mask */
sahilmgandhi 18:6a4db94011d3 7924
sahilmgandhi 18:6a4db94011d3 7925 #define PWM_DTCTL0_1_DTEN_Pos (16) /*!< PWM_T::DTCTL0_1: DTEN Position */
sahilmgandhi 18:6a4db94011d3 7926 #define PWM_DTCTL0_1_DTEN_Msk (0x1ul << PWM_DTCTL0_1_DTEN_Pos) /*!< PWM_T::DTCTL0_1: DTEN Mask */
sahilmgandhi 18:6a4db94011d3 7927
sahilmgandhi 18:6a4db94011d3 7928 #define PWM_DTCTL0_1_DTCKSEL_Pos (24) /*!< PWM_T::DTCTL0_1: DTCKSEL Position */
sahilmgandhi 18:6a4db94011d3 7929 #define PWM_DTCTL0_1_DTCKSEL_Msk (0x1ul << PWM_DTCTL0_1_DTCKSEL_Pos) /*!< PWM_T::DTCTL0_1: DTCKSEL Mask */
sahilmgandhi 18:6a4db94011d3 7930
sahilmgandhi 18:6a4db94011d3 7931 #define PWM_DTCTL2_3_DTCNT_Pos (0) /*!< PWM_T::DTCTL2_3: DTCNT Position */
sahilmgandhi 18:6a4db94011d3 7932 #define PWM_DTCTL2_3_DTCNT_Msk (0xffful << PWM_DTCTL2_3_DTCNT_Pos) /*!< PWM_T::DTCTL2_3: DTCNT Mask */
sahilmgandhi 18:6a4db94011d3 7933
sahilmgandhi 18:6a4db94011d3 7934 #define PWM_DTCTL2_3_DTEN_Pos (16) /*!< PWM_T::DTCTL2_3: DTEN Position */
sahilmgandhi 18:6a4db94011d3 7935 #define PWM_DTCTL2_3_DTEN_Msk (0x1ul << PWM_DTCTL2_3_DTEN_Pos) /*!< PWM_T::DTCTL2_3: DTEN Mask */
sahilmgandhi 18:6a4db94011d3 7936
sahilmgandhi 18:6a4db94011d3 7937 #define PWM_DTCTL2_3_DTCKSEL_Pos (24) /*!< PWM_T::DTCTL2_3: DTCKSEL Position */
sahilmgandhi 18:6a4db94011d3 7938 #define PWM_DTCTL2_3_DTCKSEL_Msk (0x1ul << PWM_DTCTL2_3_DTCKSEL_Pos) /*!< PWM_T::DTCTL2_3: DTCKSEL Mask */
sahilmgandhi 18:6a4db94011d3 7939
sahilmgandhi 18:6a4db94011d3 7940 #define PWM_DTCTL4_5_DTCNT_Pos (0) /*!< PWM_T::DTCTL4_5: DTCNT Position */
sahilmgandhi 18:6a4db94011d3 7941 #define PWM_DTCTL4_5_DTCNT_Msk (0xffful << PWM_DTCTL4_5_DTCNT_Pos) /*!< PWM_T::DTCTL4_5: DTCNT Mask */
sahilmgandhi 18:6a4db94011d3 7942
sahilmgandhi 18:6a4db94011d3 7943 #define PWM_DTCTL4_5_DTEN_Pos (16) /*!< PWM_T::DTCTL4_5: DTEN Position */
sahilmgandhi 18:6a4db94011d3 7944 #define PWM_DTCTL4_5_DTEN_Msk (0x1ul << PWM_DTCTL4_5_DTEN_Pos) /*!< PWM_T::DTCTL4_5: DTEN Mask */
sahilmgandhi 18:6a4db94011d3 7945
sahilmgandhi 18:6a4db94011d3 7946 #define PWM_DTCTL4_5_DTCKSEL_Pos (24) /*!< PWM_T::DTCTL4_5: DTCKSEL Position */
sahilmgandhi 18:6a4db94011d3 7947 #define PWM_DTCTL4_5_DTCKSEL_Msk (0x1ul << PWM_DTCTL4_5_DTCKSEL_Pos) /*!< PWM_T::DTCTL4_5: DTCKSEL Mask */
sahilmgandhi 18:6a4db94011d3 7948
sahilmgandhi 18:6a4db94011d3 7949 #define PWM_PHS0_1_PHS_Pos (0) /*!< PWM_T::PHS0_1: PHS Position */
sahilmgandhi 18:6a4db94011d3 7950 #define PWM_PHS0_1_PHS_Msk (0xfffful << PWM_PHS0_1_PHS_Pos) /*!< PWM_T::PHS0_1: PHS Mask */
sahilmgandhi 18:6a4db94011d3 7951
sahilmgandhi 18:6a4db94011d3 7952 #define PWM_PHS2_3_PHS_Pos (0) /*!< PWM_T::PHS2_3: PHS Position */
sahilmgandhi 18:6a4db94011d3 7953 #define PWM_PHS2_3_PHS_Msk (0xfffful << PWM_PHS2_3_PHS_Pos) /*!< PWM_T::PHS2_3: PHS Mask */
sahilmgandhi 18:6a4db94011d3 7954
sahilmgandhi 18:6a4db94011d3 7955 #define PWM_PHS4_5_PHS_Pos (0) /*!< PWM_T::PHS4_5: PHS Position */
sahilmgandhi 18:6a4db94011d3 7956 #define PWM_PHS4_5_PHS_Msk (0xfffful << PWM_PHS4_5_PHS_Pos) /*!< PWM_T::PHS4_5: PHS Mask */
sahilmgandhi 18:6a4db94011d3 7957
sahilmgandhi 18:6a4db94011d3 7958 #define PWM_CNT_CNT_Pos (0) /*!< PWM_T::CNT: CNT Position */
sahilmgandhi 18:6a4db94011d3 7959 #define PWM_CNT_CNT_Msk (0xfffful << PWM_CNT_CNT_Pos) /*!< PWM_T::CNT: CNT Mask */
sahilmgandhi 18:6a4db94011d3 7960
sahilmgandhi 18:6a4db94011d3 7961 #define PWM_CNT_DIRF_Pos (16) /*!< PWM_T::CNT: DIRF Position */
sahilmgandhi 18:6a4db94011d3 7962 #define PWM_CNT_DIRF_Msk (0x1ul << PWM_CNT_DIRF_Pos) /*!< PWM_T::CNT: DIRF Mask */
sahilmgandhi 18:6a4db94011d3 7963
sahilmgandhi 18:6a4db94011d3 7964 #define PWM_WGCTL0_ZPCTLn_Pos (0) /*!< PWM_T::WGCTL0: ZPCTLn Position */
sahilmgandhi 18:6a4db94011d3 7965 #define PWM_WGCTL0_ZPCTLn_Msk (0xffful << PWM_WGCTL0_ZPCTLn_Pos) /*!< PWM_T::WGCTL0: ZPCTLn Mask */
sahilmgandhi 18:6a4db94011d3 7966
sahilmgandhi 18:6a4db94011d3 7967 #define PWM_WGCTL0_ZPCTL0_Pos (0) /*!< PWM_T::WGCTL0: ZPCTL0 Position */
sahilmgandhi 18:6a4db94011d3 7968 #define PWM_WGCTL0_ZPCTL0_Msk (0x3ul << PWM_WGCTL0_ZPCTL0_Pos) /*!< PWM_T::WGCTL0: ZPCTL0 Mask */
sahilmgandhi 18:6a4db94011d3 7969
sahilmgandhi 18:6a4db94011d3 7970 #define PWM_WGCTL0_ZPCTL1_Pos (2) /*!< PWM_T::WGCTL0: ZPCTL1 Position */
sahilmgandhi 18:6a4db94011d3 7971 #define PWM_WGCTL0_ZPCTL1_Msk (0x3ul << PWM_WGCTL0_ZPCTL1_Pos) /*!< PWM_T::WGCTL0: ZPCTL1 Mask */
sahilmgandhi 18:6a4db94011d3 7972
sahilmgandhi 18:6a4db94011d3 7973 #define PWM_WGCTL0_ZPCTL2_Pos (4) /*!< PWM_T::WGCTL0: ZPCTL2 Position */
sahilmgandhi 18:6a4db94011d3 7974 #define PWM_WGCTL0_ZPCTL2_Msk (0x3ul << PWM_WGCTL0_ZPCTL2_Pos) /*!< PWM_T::WGCTL0: ZPCTL2 Mask */
sahilmgandhi 18:6a4db94011d3 7975
sahilmgandhi 18:6a4db94011d3 7976 #define PWM_WGCTL0_ZPCTL3_Pos (6) /*!< PWM_T::WGCTL0: ZPCTL3 Position */
sahilmgandhi 18:6a4db94011d3 7977 #define PWM_WGCTL0_ZPCTL3_Msk (0x3ul << PWM_WGCTL0_ZPCTL3_Pos) /*!< PWM_T::WGCTL0: ZPCTL3 Mask */
sahilmgandhi 18:6a4db94011d3 7978
sahilmgandhi 18:6a4db94011d3 7979 #define PWM_WGCTL0_ZPCTL4_Pos (8) /*!< PWM_T::WGCTL0: ZPCTL4 Position */
sahilmgandhi 18:6a4db94011d3 7980 #define PWM_WGCTL0_ZPCTL4_Msk (0x3ul << PWM_WGCTL0_ZPCTL4_Pos) /*!< PWM_T::WGCTL0: ZPCTL4 Mask */
sahilmgandhi 18:6a4db94011d3 7981
sahilmgandhi 18:6a4db94011d3 7982 #define PWM_WGCTL0_ZPCTL5_Pos (10) /*!< PWM_T::WGCTL0: ZPCTL5 Position */
sahilmgandhi 18:6a4db94011d3 7983 #define PWM_WGCTL0_ZPCTL5_Msk (0x3ul << PWM_WGCTL0_ZPCTL5_Pos) /*!< PWM_T::WGCTL0: ZPCTL5 Mask */
sahilmgandhi 18:6a4db94011d3 7984
sahilmgandhi 18:6a4db94011d3 7985 #define PWM_WGCTL0_PRDPCTLn_Pos (16) /*!< PWM_T::WGCTL0: PRDPCTLn Position */
sahilmgandhi 18:6a4db94011d3 7986 #define PWM_WGCTL0_PRDPCTLn_Msk (0xffful << PWM_WGCTL0_PRDPCTLn_Pos) /*!< PWM_T::WGCTL0: PRDPCTLn Mask */
sahilmgandhi 18:6a4db94011d3 7987
sahilmgandhi 18:6a4db94011d3 7988 #define PWM_WGCTL0_PRDPCTL0_Pos (16) /*!< PWM_T::WGCTL0: PRDPCTL0 Position */
sahilmgandhi 18:6a4db94011d3 7989 #define PWM_WGCTL0_PRDPCTL0_Msk (0x3ul << PWM_WGCTL0_PRDPCTL0_Pos) /*!< PWM_T::WGCTL0: PRDPCTL0 Mask */
sahilmgandhi 18:6a4db94011d3 7990
sahilmgandhi 18:6a4db94011d3 7991 #define PWM_WGCTL0_PRDPCTL1_Pos (18) /*!< PWM_T::WGCTL0: PRDPCTL1 Position */
sahilmgandhi 18:6a4db94011d3 7992 #define PWM_WGCTL0_PRDPCTL1_Msk (0x3ul << PWM_WGCTL0_PRDPCTL1_Pos) /*!< PWM_T::WGCTL0: PRDPCTL1 Mask */
sahilmgandhi 18:6a4db94011d3 7993
sahilmgandhi 18:6a4db94011d3 7994 #define PWM_WGCTL0_PRDPCTL2_Pos (20) /*!< PWM_T::WGCTL0: PRDPCTL2 Position */
sahilmgandhi 18:6a4db94011d3 7995 #define PWM_WGCTL0_PRDPCTL2_Msk (0x3ul << PWM_WGCTL0_PRDPCTL2_Pos) /*!< PWM_T::WGCTL0: PRDPCTL2 Mask */
sahilmgandhi 18:6a4db94011d3 7996
sahilmgandhi 18:6a4db94011d3 7997 #define PWM_WGCTL0_PRDPCTL3_Pos (22) /*!< PWM_T::WGCTL0: PRDPCTL3 Position */
sahilmgandhi 18:6a4db94011d3 7998 #define PWM_WGCTL0_PRDPCTL3_Msk (0x3ul << PWM_WGCTL0_PRDPCTL3_Pos) /*!< PWM_T::WGCTL0: PRDPCTL3 Mask */
sahilmgandhi 18:6a4db94011d3 7999
sahilmgandhi 18:6a4db94011d3 8000 #define PWM_WGCTL0_PRDPCTL4_Pos (24) /*!< PWM_T::WGCTL0: PRDPCTL4 Position */
sahilmgandhi 18:6a4db94011d3 8001 #define PWM_WGCTL0_PRDPCTL4_Msk (0x3ul << PWM_WGCTL0_PRDPCTL4_Pos) /*!< PWM_T::WGCTL0: PRDPCTL4 Mask */
sahilmgandhi 18:6a4db94011d3 8002
sahilmgandhi 18:6a4db94011d3 8003 #define PWM_WGCTL0_PRDPCTL5_Pos (26) /*!< PWM_T::WGCTL0: PRDPCTL5 Position */
sahilmgandhi 18:6a4db94011d3 8004 #define PWM_WGCTL0_PRDPCTL5_Msk (0x3ul << PWM_WGCTL0_PRDPCTL5_Pos) /*!< PWM_T::WGCTL0: PRDPCTL5 Mask */
sahilmgandhi 18:6a4db94011d3 8005
sahilmgandhi 18:6a4db94011d3 8006 #define PWM_WGCTL1_CMPUCTLn_Pos (0) /*!< PWM_T::WGCTL1: CMPUCTLn Position */
sahilmgandhi 18:6a4db94011d3 8007 #define PWM_WGCTL1_CMPUCTLn_Msk (0xffful << PWM_WGCTL1_CMPUCTLn_Pos) /*!< PWM_T::WGCTL1: CMPUCTLn Mask */
sahilmgandhi 18:6a4db94011d3 8008
sahilmgandhi 18:6a4db94011d3 8009 #define PWM_WGCTL1_CMPUCTL0_Pos (0) /*!< PWM_T::WGCTL1: CMPUCTL0 Position */
sahilmgandhi 18:6a4db94011d3 8010 #define PWM_WGCTL1_CMPUCTL0_Msk (0x3ul << PWM_WGCTL1_CMPUCTL0_Pos) /*!< PWM_T::WGCTL1: CMPUCTL0 Mask */
sahilmgandhi 18:6a4db94011d3 8011
sahilmgandhi 18:6a4db94011d3 8012 #define PWM_WGCTL1_CMPUCTL1_Pos (2) /*!< PWM_T::WGCTL1: CMPUCTL1 Position */
sahilmgandhi 18:6a4db94011d3 8013 #define PWM_WGCTL1_CMPUCTL1_Msk (0x3ul << PWM_WGCTL1_CMPUCTL1_Pos) /*!< PWM_T::WGCTL1: CMPUCTL1 Mask */
sahilmgandhi 18:6a4db94011d3 8014
sahilmgandhi 18:6a4db94011d3 8015 #define PWM_WGCTL1_CMPUCTL2_Pos (4) /*!< PWM_T::WGCTL1: CMPUCTL2 Position */
sahilmgandhi 18:6a4db94011d3 8016 #define PWM_WGCTL1_CMPUCTL2_Msk (0x3ul << PWM_WGCTL1_CMPUCTL2_Pos) /*!< PWM_T::WGCTL1: CMPUCTL2 Mask */
sahilmgandhi 18:6a4db94011d3 8017
sahilmgandhi 18:6a4db94011d3 8018 #define PWM_WGCTL1_CMPUCTL3_Pos (6) /*!< PWM_T::WGCTL1: CMPUCTL3 Position */
sahilmgandhi 18:6a4db94011d3 8019 #define PWM_WGCTL1_CMPUCTL3_Msk (0x3ul << PWM_WGCTL1_CMPUCTL3_Pos) /*!< PWM_T::WGCTL1: CMPUCTL3 Mask */
sahilmgandhi 18:6a4db94011d3 8020
sahilmgandhi 18:6a4db94011d3 8021 #define PWM_WGCTL1_CMPUCTL4_Pos (8) /*!< PWM_T::WGCTL1: CMPUCTL4 Position */
sahilmgandhi 18:6a4db94011d3 8022 #define PWM_WGCTL1_CMPUCTL4_Msk (0x3ul << PWM_WGCTL1_CMPUCTL4_Pos) /*!< PWM_T::WGCTL1: CMPUCTL4 Mask */
sahilmgandhi 18:6a4db94011d3 8023
sahilmgandhi 18:6a4db94011d3 8024 #define PWM_WGCTL1_CMPUCTL5_Pos (10) /*!< PWM_T::WGCTL1: CMPUCTL5 Position */
sahilmgandhi 18:6a4db94011d3 8025 #define PWM_WGCTL1_CMPUCTL5_Msk (0x3ul << PWM_WGCTL1_CMPUCTL5_Pos) /*!< PWM_T::WGCTL1: CMPUCTL5 Mask */
sahilmgandhi 18:6a4db94011d3 8026
sahilmgandhi 18:6a4db94011d3 8027 #define PWM_WGCTL1_CMPDCTLn_Pos (16) /*!< PWM_T::WGCTL1: CMPDCTLn Position */
sahilmgandhi 18:6a4db94011d3 8028 #define PWM_WGCTL1_CMPDCTLn_Msk (0xffful << PWM_WGCTL1_CMPDCTLn_Pos) /*!< PWM_T::WGCTL1: CMPDCTLn Mask */
sahilmgandhi 18:6a4db94011d3 8029
sahilmgandhi 18:6a4db94011d3 8030 #define PWM_WGCTL1_CMPDCTL0_Pos (16) /*!< PWM_T::WGCTL1: CMPDCTL0 Position */
sahilmgandhi 18:6a4db94011d3 8031 #define PWM_WGCTL1_CMPDCTL0_Msk (0x3ul << PWM_WGCTL1_CMPDCTL0_Pos) /*!< PWM_T::WGCTL1: CMPDCTL0 Mask */
sahilmgandhi 18:6a4db94011d3 8032
sahilmgandhi 18:6a4db94011d3 8033 #define PWM_WGCTL1_CMPDCTL1_Pos (18) /*!< PWM_T::WGCTL1: CMPDCTL1 Position */
sahilmgandhi 18:6a4db94011d3 8034 #define PWM_WGCTL1_CMPDCTL1_Msk (0x3ul << PWM_WGCTL1_CMPDCTL1_Pos) /*!< PWM_T::WGCTL1: CMPDCTL1 Mask */
sahilmgandhi 18:6a4db94011d3 8035
sahilmgandhi 18:6a4db94011d3 8036 #define PWM_WGCTL1_CMPDCTL2_Pos (20) /*!< PWM_T::WGCTL1: CMPDCTL2 Position */
sahilmgandhi 18:6a4db94011d3 8037 #define PWM_WGCTL1_CMPDCTL2_Msk (0x3ul << PWM_WGCTL1_CMPDCTL2_Pos) /*!< PWM_T::WGCTL1: CMPDCTL2 Mask */
sahilmgandhi 18:6a4db94011d3 8038
sahilmgandhi 18:6a4db94011d3 8039 #define PWM_WGCTL1_CMPDCTL3_Pos (22) /*!< PWM_T::WGCTL1: CMPDCTL3 Position */
sahilmgandhi 18:6a4db94011d3 8040 #define PWM_WGCTL1_CMPDCTL3_Msk (0x3ul << PWM_WGCTL1_CMPDCTL3_Pos) /*!< PWM_T::WGCTL1: CMPDCTL3 Mask */
sahilmgandhi 18:6a4db94011d3 8041
sahilmgandhi 18:6a4db94011d3 8042 #define PWM_WGCTL1_CMPDCTL4_Pos (24) /*!< PWM_T::WGCTL1: CMPDCTL4 Position */
sahilmgandhi 18:6a4db94011d3 8043 #define PWM_WGCTL1_CMPDCTL4_Msk (0x3ul << PWM_WGCTL1_CMPDCTL4_Pos) /*!< PWM_T::WGCTL1: CMPDCTL4 Mask */
sahilmgandhi 18:6a4db94011d3 8044
sahilmgandhi 18:6a4db94011d3 8045 #define PWM_WGCTL1_CMPDCTL5_Pos (26) /*!< PWM_T::WGCTL1: CMPDCTL5 Position */
sahilmgandhi 18:6a4db94011d3 8046 #define PWM_WGCTL1_CMPDCTL5_Msk (0x3ul << PWM_WGCTL1_CMPDCTL5_Pos) /*!< PWM_T::WGCTL1: CMPDCTL5 Mask */
sahilmgandhi 18:6a4db94011d3 8047
sahilmgandhi 18:6a4db94011d3 8048 #define PWM_MSKEN_MSKENn_Pos (0) /*!< PWM_T::MSKEN: MSKENn Position */
sahilmgandhi 18:6a4db94011d3 8049 #define PWM_MSKEN_MSKENn_Msk (0x3ful << PWM_MSKEN_MSKENn_Pos) /*!< PWM_T::MSKEN: MSKENn Mask */
sahilmgandhi 18:6a4db94011d3 8050
sahilmgandhi 18:6a4db94011d3 8051 #define PWM_MSKEN_MSKEN0_Pos (0) /*!< PWM_T::MSKEN: MSKEN0 Position */
sahilmgandhi 18:6a4db94011d3 8052 #define PWM_MSKEN_MSKEN0_Msk (0x1ul << PWM_MSKEN_MSKEN0_Pos) /*!< PWM_T::MSKEN: MSKEN0 Mask */
sahilmgandhi 18:6a4db94011d3 8053
sahilmgandhi 18:6a4db94011d3 8054 #define PWM_MSKEN_MSKEN1_Pos (1) /*!< PWM_T::MSKEN: MSKEN1 Position */
sahilmgandhi 18:6a4db94011d3 8055 #define PWM_MSKEN_MSKEN1_Msk (0x1ul << PWM_MSKEN_MSKEN1_Pos) /*!< PWM_T::MSKEN: MSKEN1 Mask */
sahilmgandhi 18:6a4db94011d3 8056
sahilmgandhi 18:6a4db94011d3 8057 #define PWM_MSKEN_MSKEN2_Pos (2) /*!< PWM_T::MSKEN: MSKEN2 Position */
sahilmgandhi 18:6a4db94011d3 8058 #define PWM_MSKEN_MSKEN2_Msk (0x1ul << PWM_MSKEN_MSKEN2_Pos) /*!< PWM_T::MSKEN: MSKEN2 Mask */
sahilmgandhi 18:6a4db94011d3 8059
sahilmgandhi 18:6a4db94011d3 8060 #define PWM_MSKEN_MSKEN3_Pos (3) /*!< PWM_T::MSKEN: MSKEN3 Position */
sahilmgandhi 18:6a4db94011d3 8061 #define PWM_MSKEN_MSKEN3_Msk (0x1ul << PWM_MSKEN_MSKEN3_Pos) /*!< PWM_T::MSKEN: MSKEN3 Mask */
sahilmgandhi 18:6a4db94011d3 8062
sahilmgandhi 18:6a4db94011d3 8063 #define PWM_MSKEN_MSKEN4_Pos (4) /*!< PWM_T::MSKEN: MSKEN4 Position */
sahilmgandhi 18:6a4db94011d3 8064 #define PWM_MSKEN_MSKEN4_Msk (0x1ul << PWM_MSKEN_MSKEN4_Pos) /*!< PWM_T::MSKEN: MSKEN4 Mask */
sahilmgandhi 18:6a4db94011d3 8065
sahilmgandhi 18:6a4db94011d3 8066 #define PWM_MSKEN_MSKEN5_Pos (5) /*!< PWM_T::MSKEN: MSKEN5 Position */
sahilmgandhi 18:6a4db94011d3 8067 #define PWM_MSKEN_MSKEN5_Msk (0x1ul << PWM_MSKEN_MSKEN5_Pos) /*!< PWM_T::MSKEN: MSKEN5 Mask */
sahilmgandhi 18:6a4db94011d3 8068
sahilmgandhi 18:6a4db94011d3 8069 #define PWM_MSK_MSKDATn_Pos (0) /*!< PWM_T::MSK: MSKDATn Position */
sahilmgandhi 18:6a4db94011d3 8070 #define PWM_MSK_MSKDATn_Msk (0x3ful << PWM_MSK_MSKDATn_Pos) /*!< PWM_T::MSK: MSKDATn Mask */
sahilmgandhi 18:6a4db94011d3 8071
sahilmgandhi 18:6a4db94011d3 8072 #define PWM_MSK_MSKDAT0_Pos (0) /*!< PWM_T::MSK: MSKDAT0 Position */
sahilmgandhi 18:6a4db94011d3 8073 #define PWM_MSK_MSKDAT0_Msk (0x1ul << PWM_MSK_MSKDAT0_Pos) /*!< PWM_T::MSK: MSKDAT0 Mask */
sahilmgandhi 18:6a4db94011d3 8074
sahilmgandhi 18:6a4db94011d3 8075 #define PWM_MSK_MSKDAT1_Pos (1) /*!< PWM_T::MSK: MSKDAT1 Position */
sahilmgandhi 18:6a4db94011d3 8076 #define PWM_MSK_MSKDAT1_Msk (0x1ul << PWM_MSK_MSKDAT1_Pos) /*!< PWM_T::MSK: MSKDAT1 Mask */
sahilmgandhi 18:6a4db94011d3 8077
sahilmgandhi 18:6a4db94011d3 8078 #define PWM_MSK_MSKDAT2_Pos (2) /*!< PWM_T::MSK: MSKDAT2 Position */
sahilmgandhi 18:6a4db94011d3 8079 #define PWM_MSK_MSKDAT2_Msk (0x1ul << PWM_MSK_MSKDAT2_Pos) /*!< PWM_T::MSK: MSKDAT2 Mask */
sahilmgandhi 18:6a4db94011d3 8080
sahilmgandhi 18:6a4db94011d3 8081 #define PWM_MSK_MSKDAT3_Pos (3) /*!< PWM_T::MSK: MSKDAT3 Position */
sahilmgandhi 18:6a4db94011d3 8082 #define PWM_MSK_MSKDAT3_Msk (0x1ul << PWM_MSK_MSKDAT3_Pos) /*!< PWM_T::MSK: MSKDAT3 Mask */
sahilmgandhi 18:6a4db94011d3 8083
sahilmgandhi 18:6a4db94011d3 8084 #define PWM_MSK_MSKDAT4_Pos (4) /*!< PWM_T::MSK: MSKDAT4 Position */
sahilmgandhi 18:6a4db94011d3 8085 #define PWM_MSK_MSKDAT4_Msk (0x1ul << PWM_MSK_MSKDAT4_Pos) /*!< PWM_T::MSK: MSKDAT4 Mask */
sahilmgandhi 18:6a4db94011d3 8086
sahilmgandhi 18:6a4db94011d3 8087 #define PWM_MSK_MSKDAT5_Pos (5) /*!< PWM_T::MSK: MSKDAT5 Position */
sahilmgandhi 18:6a4db94011d3 8088 #define PWM_MSK_MSKDAT5_Msk (0x1ul << PWM_MSK_MSKDAT5_Pos) /*!< PWM_T::MSK: MSKDAT5 Mask */
sahilmgandhi 18:6a4db94011d3 8089
sahilmgandhi 18:6a4db94011d3 8090 #define PWM_BNF_BRK0NFEN_Pos (0) /*!< PWM_T::BNF: BRK0NFEN Position */
sahilmgandhi 18:6a4db94011d3 8091 #define PWM_BNF_BRK0NFEN_Msk (0x1ul << PWM_BNF_BRK0NFEN_Pos) /*!< PWM_T::BNF: BRK0NFEN Mask */
sahilmgandhi 18:6a4db94011d3 8092
sahilmgandhi 18:6a4db94011d3 8093 #define PWM_BNF_BRK0NFSEL_Pos (1) /*!< PWM_T::BNF: BRK0NFSEL Position */
sahilmgandhi 18:6a4db94011d3 8094 #define PWM_BNF_BRK0NFSEL_Msk (0x7ul << PWM_BNF_BRK0NFSEL_Pos) /*!< PWM_T::BNF: BRK0NFSEL Mask */
sahilmgandhi 18:6a4db94011d3 8095
sahilmgandhi 18:6a4db94011d3 8096 #define PWM_BNF_BRK0FCNT_Pos (4) /*!< PWM_T::BNF: BRK0FCNT Position */
sahilmgandhi 18:6a4db94011d3 8097 #define PWM_BNF_BRK0FCNT_Msk (0x7ul << PWM_BNF_BRK0FCNT_Pos) /*!< PWM_T::BNF: BRK0FCNT Mask */
sahilmgandhi 18:6a4db94011d3 8098
sahilmgandhi 18:6a4db94011d3 8099 #define PWM_BNF_BRK0PINV_Pos (7) /*!< PWM_T::BNF: BRK0PINV Position */
sahilmgandhi 18:6a4db94011d3 8100 #define PWM_BNF_BRK0PINV_Msk (0x1ul << PWM_BNF_BRK0PINV_Pos) /*!< PWM_T::BNF: BRK0PINV Mask */
sahilmgandhi 18:6a4db94011d3 8101
sahilmgandhi 18:6a4db94011d3 8102 #define PWM_BNF_BRK1NFEN_Pos (8) /*!< PWM_T::BNF: BRK1NFEN Position */
sahilmgandhi 18:6a4db94011d3 8103 #define PWM_BNF_BRK1NFEN_Msk (0x1ul << PWM_BNF_BRK1NFEN_Pos) /*!< PWM_T::BNF: BRK1NFEN Mask */
sahilmgandhi 18:6a4db94011d3 8104
sahilmgandhi 18:6a4db94011d3 8105 #define PWM_BNF_BRK1NFSEL_Pos (9) /*!< PWM_T::BNF: BRK1NFSEL Position */
sahilmgandhi 18:6a4db94011d3 8106 #define PWM_BNF_BRK1NFSEL_Msk (0x7ul << PWM_BNF_BRK1NFSEL_Pos) /*!< PWM_T::BNF: BRK1NFSEL Mask */
sahilmgandhi 18:6a4db94011d3 8107
sahilmgandhi 18:6a4db94011d3 8108 #define PWM_BNF_BRK1FCNT_Pos (12) /*!< PWM_T::BNF: BRK1FCNT Position */
sahilmgandhi 18:6a4db94011d3 8109 #define PWM_BNF_BRK1FCNT_Msk (0x7ul << PWM_BNF_BRK1FCNT_Pos) /*!< PWM_T::BNF: BRK1FCNT Mask */
sahilmgandhi 18:6a4db94011d3 8110
sahilmgandhi 18:6a4db94011d3 8111 #define PWM_BNF_BRK1PINV_Pos (15) /*!< PWM_T::BNF: BRK1PINV Position */
sahilmgandhi 18:6a4db94011d3 8112 #define PWM_BNF_BRK1PINV_Msk (0x1ul << PWM_BNF_BRK1PINV_Pos) /*!< PWM_T::BNF: BRK1PINV Mask */
sahilmgandhi 18:6a4db94011d3 8113
sahilmgandhi 18:6a4db94011d3 8114 #define PWM_BNF_BK0SRC_Pos (16) /*!< PWM_T::BNF: BK0SRC Position */
sahilmgandhi 18:6a4db94011d3 8115 #define PWM_BNF_BK0SRC_Msk (0x1ul << PWM_BNF_BK0SRC_Pos) /*!< PWM_T::BNF: BK0SRC Mask */
sahilmgandhi 18:6a4db94011d3 8116
sahilmgandhi 18:6a4db94011d3 8117 #define PWM_BNF_BK1SRC_Pos (24) /*!< PWM_T::BNF: BK1SRC Position */
sahilmgandhi 18:6a4db94011d3 8118 #define PWM_BNF_BK1SRC_Msk (0x1ul << PWM_BNF_BK1SRC_Pos) /*!< PWM_T::BNF: BK1SRC Mask */
sahilmgandhi 18:6a4db94011d3 8119
sahilmgandhi 18:6a4db94011d3 8120 #define PWM_FAILBRK_CSSBRKEN_Pos (0) /*!< PWM_T::FAILBRK: CSSBRKEN Position */
sahilmgandhi 18:6a4db94011d3 8121 #define PWM_FAILBRK_CSSBRKEN_Msk (0x1ul << PWM_FAILBRK_CSSBRKEN_Pos) /*!< PWM_T::FAILBRK: CSSBRKEN Mask */
sahilmgandhi 18:6a4db94011d3 8122
sahilmgandhi 18:6a4db94011d3 8123 #define PWM_FAILBRK_BODBRKEN_Pos (1) /*!< PWM_T::FAILBRK: BODBRKEN Position */
sahilmgandhi 18:6a4db94011d3 8124 #define PWM_FAILBRK_BODBRKEN_Msk (0x1ul << PWM_FAILBRK_BODBRKEN_Pos) /*!< PWM_T::FAILBRK: BODBRKEN Mask */
sahilmgandhi 18:6a4db94011d3 8125
sahilmgandhi 18:6a4db94011d3 8126 #define PWM_FAILBRK_RAMBRKEN_Pos (2) /*!< PWM_T::FAILBRK: RAMBRKEN Position */
sahilmgandhi 18:6a4db94011d3 8127 #define PWM_FAILBRK_RAMBRKEN_Msk (0x1ul << PWM_FAILBRK_RAMBRKEN_Pos) /*!< PWM_T::FAILBRK: RAMBRKEN Mask */
sahilmgandhi 18:6a4db94011d3 8128
sahilmgandhi 18:6a4db94011d3 8129 #define PWM_FAILBRK_CORBRKEN_Pos (3) /*!< PWM_T::FAILBRK: CORBRKEN Position */
sahilmgandhi 18:6a4db94011d3 8130 #define PWM_FAILBRK_CORBRKEN_Msk (0x1ul << PWM_FAILBRK_CORBRKEN_Pos) /*!< PWM_T::FAILBRK: CORBRKEN Mask */
sahilmgandhi 18:6a4db94011d3 8131
sahilmgandhi 18:6a4db94011d3 8132 #define PWM_BRKCTL0_1_CPO0EBEN_Pos (0) /*!< PWM_T::BRKCTL0_1: CPO0EBEN Position */
sahilmgandhi 18:6a4db94011d3 8133 #define PWM_BRKCTL0_1_CPO0EBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO0EBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO0EBEN Mask */
sahilmgandhi 18:6a4db94011d3 8134
sahilmgandhi 18:6a4db94011d3 8135 #define PWM_BRKCTL0_1_CPO1EBEN_Pos (1) /*!< PWM_T::BRKCTL0_1: CPO1EBEN Position */
sahilmgandhi 18:6a4db94011d3 8136 #define PWM_BRKCTL0_1_CPO1EBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO1EBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO1EBEN Mask */
sahilmgandhi 18:6a4db94011d3 8137
sahilmgandhi 18:6a4db94011d3 8138 #define PWM_BRKCTL0_1_BRKP0EEN_Pos (4) /*!< PWM_T::BRKCTL0_1: BRKP0EEN Position */
sahilmgandhi 18:6a4db94011d3 8139 #define PWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP0EEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP0EEN Mask */
sahilmgandhi 18:6a4db94011d3 8140
sahilmgandhi 18:6a4db94011d3 8141 #define PWM_BRKCTL0_1_BRKP1EEN_Pos (5) /*!< PWM_T::BRKCTL0_1: BRKP1EEN Position */
sahilmgandhi 18:6a4db94011d3 8142 #define PWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP1EEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP1EEN Mask */
sahilmgandhi 18:6a4db94011d3 8143
sahilmgandhi 18:6a4db94011d3 8144 #define PWM_BRKCTL0_1_SYSEBEN_Pos (7) /*!< PWM_T::BRKCTL0_1: SYSEBEN Position */
sahilmgandhi 18:6a4db94011d3 8145 #define PWM_BRKCTL0_1_SYSEBEN_Msk (0x1ul << PWM_BRKCTL0_1_SYSEBEN_Pos) /*!< PWM_T::BRKCTL0_1: SYSEBEN Mask */
sahilmgandhi 18:6a4db94011d3 8146
sahilmgandhi 18:6a4db94011d3 8147 #define PWM_BRKCTL0_1_CPO0LBEN_Pos (8) /*!< PWM_T::BRKCTL0_1: CPO0LBEN Position */
sahilmgandhi 18:6a4db94011d3 8148 #define PWM_BRKCTL0_1_CPO0LBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO0LBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO0LBEN Mask */
sahilmgandhi 18:6a4db94011d3 8149
sahilmgandhi 18:6a4db94011d3 8150 #define PWM_BRKCTL0_1_CPO1LBEN_Pos (9) /*!< PWM_T::BRKCTL0_1: CPO1LBEN Position */
sahilmgandhi 18:6a4db94011d3 8151 #define PWM_BRKCTL0_1_CPO1LBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO1LBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO1LBEN Mask */
sahilmgandhi 18:6a4db94011d3 8152
sahilmgandhi 18:6a4db94011d3 8153 #define PWM_BRKCTL0_1_BRKP0LEN_Pos (12) /*!< PWM_T::BRKCTL0_1: BRKP0LEN Position */
sahilmgandhi 18:6a4db94011d3 8154 #define PWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP0LEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP0LEN Mask */
sahilmgandhi 18:6a4db94011d3 8155
sahilmgandhi 18:6a4db94011d3 8156 #define PWM_BRKCTL0_1_BRKP1LEN_Pos (13) /*!< PWM_T::BRKCTL0_1: BRKP1LEN Position */
sahilmgandhi 18:6a4db94011d3 8157 #define PWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP1LEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP1LEN Mask */
sahilmgandhi 18:6a4db94011d3 8158
sahilmgandhi 18:6a4db94011d3 8159 #define PWM_BRKCTL0_1_SYSLBEN_Pos (15) /*!< PWM_T::BRKCTL0_1: SYSLBEN Position */
sahilmgandhi 18:6a4db94011d3 8160 #define PWM_BRKCTL0_1_SYSLBEN_Msk (0x1ul << PWM_BRKCTL0_1_SYSLBEN_Pos) /*!< PWM_T::BRKCTL0_1: SYSLBEN Mask */
sahilmgandhi 18:6a4db94011d3 8161
sahilmgandhi 18:6a4db94011d3 8162 #define PWM_BRKCTL0_1_BRKAEVEN_Pos (16) /*!< PWM_T::BRKCTL0_1: BRKAEVEN Position */
sahilmgandhi 18:6a4db94011d3 8163 #define PWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL0_1_BRKAEVEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKAEVEN Mask */
sahilmgandhi 18:6a4db94011d3 8164
sahilmgandhi 18:6a4db94011d3 8165 #define PWM_BRKCTL0_1_BRKAODD_Pos (18) /*!< PWM_T::BRKCTL0_1: BRKAODD Position */
sahilmgandhi 18:6a4db94011d3 8166 #define PWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << PWM_BRKCTL0_1_BRKAODD_Pos) /*!< PWM_T::BRKCTL0_1: BRKAODD Mask */
sahilmgandhi 18:6a4db94011d3 8167
sahilmgandhi 18:6a4db94011d3 8168 #define PWM_BRKCTL2_3_CPO0EBEN_Pos (0) /*!< PWM_T::BRKCTL2_3: CPO0EBEN Position */
sahilmgandhi 18:6a4db94011d3 8169 #define PWM_BRKCTL2_3_CPO0EBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO0EBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO0EBEN Mask */
sahilmgandhi 18:6a4db94011d3 8170
sahilmgandhi 18:6a4db94011d3 8171 #define PWM_BRKCTL2_3_CPO1EBEN_Pos (1) /*!< PWM_T::BRKCTL2_3: CPO1EBEN Position */
sahilmgandhi 18:6a4db94011d3 8172 #define PWM_BRKCTL2_3_CPO1EBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO1EBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO1EBEN Mask */
sahilmgandhi 18:6a4db94011d3 8173
sahilmgandhi 18:6a4db94011d3 8174 #define PWM_BRKCTL2_3_BRKP0EEN_Pos (4) /*!< PWM_T::BRKCTL2_3: BRKP0EEN Position */
sahilmgandhi 18:6a4db94011d3 8175 #define PWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP0EEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP0EEN Mask */
sahilmgandhi 18:6a4db94011d3 8176
sahilmgandhi 18:6a4db94011d3 8177 #define PWM_BRKCTL2_3_BRKP1EEN_Pos (5) /*!< PWM_T::BRKCTL2_3: BRKP1EEN Position */
sahilmgandhi 18:6a4db94011d3 8178 #define PWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP1EEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP1EEN Mask */
sahilmgandhi 18:6a4db94011d3 8179
sahilmgandhi 18:6a4db94011d3 8180 #define PWM_BRKCTL2_3_SYSEBEN_Pos (7) /*!< PWM_T::BRKCTL2_3: SYSEBEN Position */
sahilmgandhi 18:6a4db94011d3 8181 #define PWM_BRKCTL2_3_SYSEBEN_Msk (0x1ul << PWM_BRKCTL2_3_SYSEBEN_Pos) /*!< PWM_T::BRKCTL2_3: SYSEBEN Mask */
sahilmgandhi 18:6a4db94011d3 8182
sahilmgandhi 18:6a4db94011d3 8183 #define PWM_BRKCTL2_3_CPO0LBEN_Pos (8) /*!< PWM_T::BRKCTL2_3: CPO0LBEN Position */
sahilmgandhi 18:6a4db94011d3 8184 #define PWM_BRKCTL2_3_CPO0LBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO0LBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO0LBEN Mask */
sahilmgandhi 18:6a4db94011d3 8185
sahilmgandhi 18:6a4db94011d3 8186 #define PWM_BRKCTL2_3_CPO1LBEN_Pos (9) /*!< PWM_T::BRKCTL2_3: CPO1LBEN Position */
sahilmgandhi 18:6a4db94011d3 8187 #define PWM_BRKCTL2_3_CPO1LBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO1LBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO1LBEN Mask */
sahilmgandhi 18:6a4db94011d3 8188
sahilmgandhi 18:6a4db94011d3 8189 #define PWM_BRKCTL2_3_BRKP0LEN_Pos (12) /*!< PWM_T::BRKCTL2_3: BRKP0LEN Position */
sahilmgandhi 18:6a4db94011d3 8190 #define PWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP0LEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP0LEN Mask */
sahilmgandhi 18:6a4db94011d3 8191
sahilmgandhi 18:6a4db94011d3 8192 #define PWM_BRKCTL2_3_BRKP1LEN_Pos (13) /*!< PWM_T::BRKCTL2_3: BRKP1LEN Position */
sahilmgandhi 18:6a4db94011d3 8193 #define PWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP1LEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP1LEN Mask */
sahilmgandhi 18:6a4db94011d3 8194
sahilmgandhi 18:6a4db94011d3 8195 #define PWM_BRKCTL2_3_SYSLBEN_Pos (15) /*!< PWM_T::BRKCTL2_3: SYSLBEN Position */
sahilmgandhi 18:6a4db94011d3 8196 #define PWM_BRKCTL2_3_SYSLBEN_Msk (0x1ul << PWM_BRKCTL2_3_SYSLBEN_Pos) /*!< PWM_T::BRKCTL2_3: SYSLBEN Mask */
sahilmgandhi 18:6a4db94011d3 8197
sahilmgandhi 18:6a4db94011d3 8198 #define PWM_BRKCTL2_3_BRKAEVEN_Pos (16) /*!< PWM_T::BRKCTL2_3: BRKAEVEN Position */
sahilmgandhi 18:6a4db94011d3 8199 #define PWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL2_3_BRKAEVEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKAEVEN Mask */
sahilmgandhi 18:6a4db94011d3 8200
sahilmgandhi 18:6a4db94011d3 8201 #define PWM_BRKCTL2_3_BRKAODD_Pos (18) /*!< PWM_T::BRKCTL2_3: BRKAODD Position */
sahilmgandhi 18:6a4db94011d3 8202 #define PWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << PWM_BRKCTL2_3_BRKAODD_Pos) /*!< PWM_T::BRKCTL2_3: BRKAODD Mask */
sahilmgandhi 18:6a4db94011d3 8203
sahilmgandhi 18:6a4db94011d3 8204 #define PWM_BRKCTL4_5_CPO0EBEN_Pos (0) /*!< PWM_T::BRKCTL4_5: CPO0EBEN Position */
sahilmgandhi 18:6a4db94011d3 8205 #define PWM_BRKCTL4_5_CPO0EBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO0EBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO0EBEN Mask */
sahilmgandhi 18:6a4db94011d3 8206
sahilmgandhi 18:6a4db94011d3 8207 #define PWM_BRKCTL4_5_CPO1EBEN_Pos (1) /*!< PWM_T::BRKCTL4_5: CPO1EBEN Position */
sahilmgandhi 18:6a4db94011d3 8208 #define PWM_BRKCTL4_5_CPO1EBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO1EBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO1EBEN Mask */
sahilmgandhi 18:6a4db94011d3 8209
sahilmgandhi 18:6a4db94011d3 8210 #define PWM_BRKCTL4_5_BRKP0EEN_Pos (4) /*!< PWM_T::BRKCTL4_5: BRKP0EEN Position */
sahilmgandhi 18:6a4db94011d3 8211 #define PWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP0EEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP0EEN Mask */
sahilmgandhi 18:6a4db94011d3 8212
sahilmgandhi 18:6a4db94011d3 8213 #define PWM_BRKCTL4_5_BRKP1EEN_Pos (5) /*!< PWM_T::BRKCTL4_5: BRKP1EEN Position */
sahilmgandhi 18:6a4db94011d3 8214 #define PWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP1EEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP1EEN Mask */
sahilmgandhi 18:6a4db94011d3 8215
sahilmgandhi 18:6a4db94011d3 8216 #define PWM_BRKCTL4_5_SYSEBEN_Pos (7) /*!< PWM_T::BRKCTL4_5: SYSEBEN Position */
sahilmgandhi 18:6a4db94011d3 8217 #define PWM_BRKCTL4_5_SYSEBEN_Msk (0x1ul << PWM_BRKCTL4_5_SYSEBEN_Pos) /*!< PWM_T::BRKCTL4_5: SYSEBEN Mask */
sahilmgandhi 18:6a4db94011d3 8218
sahilmgandhi 18:6a4db94011d3 8219 #define PWM_BRKCTL4_5_CPO0LBEN_Pos (8) /*!< PWM_T::BRKCTL4_5: CPO0LBEN Position */
sahilmgandhi 18:6a4db94011d3 8220 #define PWM_BRKCTL4_5_CPO0LBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO0LBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO0LBEN Mask */
sahilmgandhi 18:6a4db94011d3 8221
sahilmgandhi 18:6a4db94011d3 8222 #define PWM_BRKCTL4_5_CPO1LBEN_Pos (9) /*!< PWM_T::BRKCTL4_5: CPO1LBEN Position */
sahilmgandhi 18:6a4db94011d3 8223 #define PWM_BRKCTL4_5_CPO1LBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO1LBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO1LBEN Mask */
sahilmgandhi 18:6a4db94011d3 8224
sahilmgandhi 18:6a4db94011d3 8225 #define PWM_BRKCTL4_5_BRKP0LEN_Pos (12) /*!< PWM_T::BRKCTL4_5: BRKP0LEN Position */
sahilmgandhi 18:6a4db94011d3 8226 #define PWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP0LEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP0LEN Mask */
sahilmgandhi 18:6a4db94011d3 8227
sahilmgandhi 18:6a4db94011d3 8228 #define PWM_BRKCTL4_5_BRKP1LEN_Pos (13) /*!< PWM_T::BRKCTL4_5: BRKP1LEN Position */
sahilmgandhi 18:6a4db94011d3 8229 #define PWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP1LEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP1LEN Mask */
sahilmgandhi 18:6a4db94011d3 8230
sahilmgandhi 18:6a4db94011d3 8231 #define PWM_BRKCTL4_5_SYSLBEN_Pos (15) /*!< PWM_T::BRKCTL4_5: SYSLBEN Position */
sahilmgandhi 18:6a4db94011d3 8232 #define PWM_BRKCTL4_5_SYSLBEN_Msk (0x1ul << PWM_BRKCTL4_5_SYSLBEN_Pos) /*!< PWM_T::BRKCTL4_5: SYSLBEN Mask */
sahilmgandhi 18:6a4db94011d3 8233
sahilmgandhi 18:6a4db94011d3 8234 #define PWM_BRKCTL4_5_BRKAEVEN_Pos (16) /*!< PWM_T::BRKCTL4_5: BRKAEVEN Position */
sahilmgandhi 18:6a4db94011d3 8235 #define PWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL4_5_BRKAEVEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKAEVEN Mask */
sahilmgandhi 18:6a4db94011d3 8236
sahilmgandhi 18:6a4db94011d3 8237 #define PWM_BRKCTL4_5_BRKAODD_Pos (18) /*!< PWM_T::BRKCTL4_5: BRKAODD Position */
sahilmgandhi 18:6a4db94011d3 8238 #define PWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << PWM_BRKCTL4_5_BRKAODD_Pos) /*!< PWM_T::BRKCTL4_5: BRKAODD Mask */
sahilmgandhi 18:6a4db94011d3 8239
sahilmgandhi 18:6a4db94011d3 8240 #define PWM_POLCTL_PINVn_Pos (0) /*!< PWM_T::POLCTL: PINVn Position */
sahilmgandhi 18:6a4db94011d3 8241 #define PWM_POLCTL_PINVn_Msk (0x3ful << PWM_POLCTL_PINVn_Pos) /*!< PWM_T::POLCTL: PINVn Mask */
sahilmgandhi 18:6a4db94011d3 8242
sahilmgandhi 18:6a4db94011d3 8243 #define PWM_POLCTL_PINV0_Pos (0) /*!< PWM_T::POLCTL: PINV0 Position */
sahilmgandhi 18:6a4db94011d3 8244 #define PWM_POLCTL_PINV0_Msk (0x1ul << PWM_POLCTL_PINV0_Pos) /*!< PWM_T::POLCTL: PINV0 Mask */
sahilmgandhi 18:6a4db94011d3 8245
sahilmgandhi 18:6a4db94011d3 8246 #define PWM_POLCTL_PINV1_Pos (1) /*!< PWM_T::POLCTL: PINV1 Position */
sahilmgandhi 18:6a4db94011d3 8247 #define PWM_POLCTL_PINV1_Msk (0x1ul << PWM_POLCTL_PINV1_Pos) /*!< PWM_T::POLCTL: PINV1 Mask */
sahilmgandhi 18:6a4db94011d3 8248
sahilmgandhi 18:6a4db94011d3 8249 #define PWM_POLCTL_PINV2_Pos (2) /*!< PWM_T::POLCTL: PINV2 Position */
sahilmgandhi 18:6a4db94011d3 8250 #define PWM_POLCTL_PINV2_Msk (0x1ul << PWM_POLCTL_PINV2_Pos) /*!< PWM_T::POLCTL: PINV2 Mask */
sahilmgandhi 18:6a4db94011d3 8251
sahilmgandhi 18:6a4db94011d3 8252 #define PWM_POLCTL_PINV3_Pos (3) /*!< PWM_T::POLCTL: PINV3 Position */
sahilmgandhi 18:6a4db94011d3 8253 #define PWM_POLCTL_PINV3_Msk (0x1ul << PWM_POLCTL_PINV3_Pos) /*!< PWM_T::POLCTL: PINV3 Mask */
sahilmgandhi 18:6a4db94011d3 8254
sahilmgandhi 18:6a4db94011d3 8255 #define PWM_POLCTL_PINV4_Pos (4) /*!< PWM_T::POLCTL: PINV4 Position */
sahilmgandhi 18:6a4db94011d3 8256 #define PWM_POLCTL_PINV4_Msk (0x1ul << PWM_POLCTL_PINV4_Pos) /*!< PWM_T::POLCTL: PINV4 Mask */
sahilmgandhi 18:6a4db94011d3 8257
sahilmgandhi 18:6a4db94011d3 8258 #define PWM_POLCTL_PINV5_Pos (5) /*!< PWM_T::POLCTL: PINV5 Position */
sahilmgandhi 18:6a4db94011d3 8259 #define PWM_POLCTL_PINV5_Msk (0x1ul << PWM_POLCTL_PINV5_Pos) /*!< PWM_T::POLCTL: PINV5 Mask */
sahilmgandhi 18:6a4db94011d3 8260
sahilmgandhi 18:6a4db94011d3 8261 #define PWM_POEN_POENn_Pos (0) /*!< PWM_T::POEN: POENn Position */
sahilmgandhi 18:6a4db94011d3 8262 #define PWM_POEN_POENn_Msk (0x3ful << PWM_POEN_POENn_Pos) /*!< PWM_T::POEN: POENn Mask */
sahilmgandhi 18:6a4db94011d3 8263
sahilmgandhi 18:6a4db94011d3 8264 #define PWM_POEN_POEN0_Pos (0) /*!< PWM_T::POEN: POEN0 Position */
sahilmgandhi 18:6a4db94011d3 8265 #define PWM_POEN_POEN0_Msk (0x1ul << PWM_POEN_POEN0_Pos) /*!< PWM_T::POEN: POEN0 Mask */
sahilmgandhi 18:6a4db94011d3 8266
sahilmgandhi 18:6a4db94011d3 8267 #define PWM_POEN_POEN1_Pos (1) /*!< PWM_T::POEN: POEN1 Position */
sahilmgandhi 18:6a4db94011d3 8268 #define PWM_POEN_POEN1_Msk (0x1ul << PWM_POEN_POEN1_Pos) /*!< PWM_T::POEN: POEN1 Mask */
sahilmgandhi 18:6a4db94011d3 8269
sahilmgandhi 18:6a4db94011d3 8270 #define PWM_POEN_POEN2_Pos (2) /*!< PWM_T::POEN: POEN2 Position */
sahilmgandhi 18:6a4db94011d3 8271 #define PWM_POEN_POEN2_Msk (0x1ul << PWM_POEN_POEN2_Pos) /*!< PWM_T::POEN: POEN2 Mask */
sahilmgandhi 18:6a4db94011d3 8272
sahilmgandhi 18:6a4db94011d3 8273 #define PWM_POEN_POEN3_Pos (3) /*!< PWM_T::POEN: POEN3 Position */
sahilmgandhi 18:6a4db94011d3 8274 #define PWM_POEN_POEN3_Msk (0x1ul << PWM_POEN_POEN3_Pos) /*!< PWM_T::POEN: POEN3 Mask */
sahilmgandhi 18:6a4db94011d3 8275
sahilmgandhi 18:6a4db94011d3 8276 #define PWM_POEN_POEN4_Pos (4) /*!< PWM_T::POEN: POEN4 Position */
sahilmgandhi 18:6a4db94011d3 8277 #define PWM_POEN_POEN4_Msk (0x1ul << PWM_POEN_POEN4_Pos) /*!< PWM_T::POEN: POEN4 Mask */
sahilmgandhi 18:6a4db94011d3 8278
sahilmgandhi 18:6a4db94011d3 8279 #define PWM_POEN_POEN5_Pos (5) /*!< PWM_T::POEN: POEN5 Position */
sahilmgandhi 18:6a4db94011d3 8280 #define PWM_POEN_POEN5_Msk (0x1ul << PWM_POEN_POEN5_Pos) /*!< PWM_T::POEN: POEN5 Mask */
sahilmgandhi 18:6a4db94011d3 8281
sahilmgandhi 18:6a4db94011d3 8282 #define PWM_SWBRK_BRKETRGn_Pos (0) /*!< PWM_T::SWBRK: BRKETRGn Position */
sahilmgandhi 18:6a4db94011d3 8283 #define PWM_SWBRK_BRKETRGn_Msk (0x7ul << PWM_SWBRK_BRKETRGn_Pos) /*!< PWM_T::SWBRK: BRKETRGn Mask */
sahilmgandhi 18:6a4db94011d3 8284
sahilmgandhi 18:6a4db94011d3 8285 #define PWM_SWBRK_BRKETRG0_Pos (0) /*!< PWM_T::SWBRK: BRKETRG0 Position */
sahilmgandhi 18:6a4db94011d3 8286 #define PWM_SWBRK_BRKETRG0_Msk (0x1ul << PWM_SWBRK_BRKETRG0_Pos) /*!< PWM_T::SWBRK: BRKETRG0 Mask */
sahilmgandhi 18:6a4db94011d3 8287
sahilmgandhi 18:6a4db94011d3 8288 #define PWM_SWBRK_BRKETRG2_Pos (1) /*!< PWM_T::SWBRK: BRKETRG2 Position */
sahilmgandhi 18:6a4db94011d3 8289 #define PWM_SWBRK_BRKETRG2_Msk (0x1ul << PWM_SWBRK_BRKETRG2_Pos) /*!< PWM_T::SWBRK: BRKETRG2 Mask */
sahilmgandhi 18:6a4db94011d3 8290
sahilmgandhi 18:6a4db94011d3 8291 #define PWM_SWBRK_BRKETRG4_Pos (2) /*!< PWM_T::SWBRK: BRKETRG4 Position */
sahilmgandhi 18:6a4db94011d3 8292 #define PWM_SWBRK_BRKETRG4_Msk (0x1ul << PWM_SWBRK_BRKETRG4_Pos) /*!< PWM_T::SWBRK: BRKETRG4 Mask */
sahilmgandhi 18:6a4db94011d3 8293
sahilmgandhi 18:6a4db94011d3 8294 #define PWM_SWBRK_BRKLTRGn_Pos (8) /*!< PWM_T::SWBRK: BRKLTRGn Position */
sahilmgandhi 18:6a4db94011d3 8295 #define PWM_SWBRK_BRKLTRGn_Msk (0x7ul << PWM_SWBRK_BRKLTRGn_Pos) /*!< PWM_T::SWBRK: BRKLTRGn Mask */
sahilmgandhi 18:6a4db94011d3 8296
sahilmgandhi 18:6a4db94011d3 8297 #define PWM_SWBRK_BRKLTRG0_Pos (8) /*!< PWM_T::SWBRK: BRKLTRG0 Position */
sahilmgandhi 18:6a4db94011d3 8298 #define PWM_SWBRK_BRKLTRG0_Msk (0x1ul << PWM_SWBRK_BRKLTRG0_Pos) /*!< PWM_T::SWBRK: BRKLTRG0 Mask */
sahilmgandhi 18:6a4db94011d3 8299
sahilmgandhi 18:6a4db94011d3 8300 #define PWM_SWBRK_BRKLTRG2_Pos (9) /*!< PWM_T::SWBRK: BRKLTRG2 Position */
sahilmgandhi 18:6a4db94011d3 8301 #define PWM_SWBRK_BRKLTRG2_Msk (0x1ul << PWM_SWBRK_BRKLTRG2_Pos) /*!< PWM_T::SWBRK: BRKLTRG2 Mask */
sahilmgandhi 18:6a4db94011d3 8302
sahilmgandhi 18:6a4db94011d3 8303 #define PWM_SWBRK_BRKLTRG4_Pos (10) /*!< PWM_T::SWBRK: BRKLTRG4 Position */
sahilmgandhi 18:6a4db94011d3 8304 #define PWM_SWBRK_BRKLTRG4_Msk (0x1ul << PWM_SWBRK_BRKLTRG4_Pos) /*!< PWM_T::SWBRK: BRKLTRG4 Mask */
sahilmgandhi 18:6a4db94011d3 8305
sahilmgandhi 18:6a4db94011d3 8306 #define PWM_INTEN0_ZIENn_Pos (0) /*!< PWM_T::INTEN0: ZIENn Position */
sahilmgandhi 18:6a4db94011d3 8307 #define PWM_INTEN0_ZIENn_Msk (0x3ful << PWM_INTEN0_ZIENn_Pos) /*!< PWM_T::INTEN0: ZIENn Mask */
sahilmgandhi 18:6a4db94011d3 8308
sahilmgandhi 18:6a4db94011d3 8309 #define PWM_INTEN0_ZIEN0_Pos (0) /*!< PWM_T::INTEN0: ZIEN0 Position */
sahilmgandhi 18:6a4db94011d3 8310 #define PWM_INTEN0_ZIEN0_Msk (0x1ul << PWM_INTEN0_ZIEN0_Pos) /*!< PWM_T::INTEN0: ZIEN0 Mask */
sahilmgandhi 18:6a4db94011d3 8311
sahilmgandhi 18:6a4db94011d3 8312 #define PWM_INTEN0_ZIEN1_Pos (1) /*!< PWM_T::INTEN0: ZIEN1 Position */
sahilmgandhi 18:6a4db94011d3 8313 #define PWM_INTEN0_ZIEN1_Msk (0x1ul << PWM_INTEN0_ZIEN1_Pos) /*!< PWM_T::INTEN0: ZIEN1 Mask */
sahilmgandhi 18:6a4db94011d3 8314
sahilmgandhi 18:6a4db94011d3 8315 #define PWM_INTEN0_ZIEN2_Pos (2) /*!< PWM_T::INTEN0: ZIEN2 Position */
sahilmgandhi 18:6a4db94011d3 8316 #define PWM_INTEN0_ZIEN2_Msk (0x1ul << PWM_INTEN0_ZIEN2_Pos) /*!< PWM_T::INTEN0: ZIEN2 Mask */
sahilmgandhi 18:6a4db94011d3 8317
sahilmgandhi 18:6a4db94011d3 8318 #define PWM_INTEN0_ZIEN3_Pos (3) /*!< PWM_T::INTEN0: ZIEN3 Position */
sahilmgandhi 18:6a4db94011d3 8319 #define PWM_INTEN0_ZIEN3_Msk (0x1ul << PWM_INTEN0_ZIEN3_Pos) /*!< PWM_T::INTEN0: ZIEN3 Mask */
sahilmgandhi 18:6a4db94011d3 8320
sahilmgandhi 18:6a4db94011d3 8321 #define PWM_INTEN0_ZIEN4_Pos (4) /*!< PWM_T::INTEN0: ZIEN4 Position */
sahilmgandhi 18:6a4db94011d3 8322 #define PWM_INTEN0_ZIEN4_Msk (0x1ul << PWM_INTEN0_ZIEN4_Pos) /*!< PWM_T::INTEN0: ZIEN4 Mask */
sahilmgandhi 18:6a4db94011d3 8323
sahilmgandhi 18:6a4db94011d3 8324 #define PWM_INTEN0_ZIEN5_Pos (5) /*!< PWM_T::INTEN0: ZIEN5 Position */
sahilmgandhi 18:6a4db94011d3 8325 #define PWM_INTEN0_ZIEN5_Msk (0x1ul << PWM_INTEN0_ZIEN5_Pos) /*!< PWM_T::INTEN0: ZIEN5 Mask */
sahilmgandhi 18:6a4db94011d3 8326
sahilmgandhi 18:6a4db94011d3 8327 #define PWM_INTEN0_IFAIEN0_1_Pos (7) /*!< PWM_T::INTEN0: IFAIEN0_1 Position */
sahilmgandhi 18:6a4db94011d3 8328 #define PWM_INTEN0_IFAIEN0_1_Msk (0x1ul << PWM_INTEN0_IFAIEN0_1_Pos) /*!< PWM_T::INTEN0: IFAIEN0_1 Mask */
sahilmgandhi 18:6a4db94011d3 8329
sahilmgandhi 18:6a4db94011d3 8330 #define PWM_INTEN0_PIENn_Pos (8) /*!< PWM_T::INTEN0: PIENn Position */
sahilmgandhi 18:6a4db94011d3 8331 #define PWM_INTEN0_PIENn_Msk (0x3ful << PWM_INTEN0_PIENn_Pos) /*!< PWM_T::INTEN0: PIENn Mask */
sahilmgandhi 18:6a4db94011d3 8332
sahilmgandhi 18:6a4db94011d3 8333 #define PWM_INTEN0_PIEN0_Pos (8) /*!< PWM_T::INTEN0: PIEN0 Position */
sahilmgandhi 18:6a4db94011d3 8334 #define PWM_INTEN0_PIEN0_Msk (0x1ul << PWM_INTEN0_PIEN0_Pos) /*!< PWM_T::INTEN0: PIEN0 Mask */
sahilmgandhi 18:6a4db94011d3 8335
sahilmgandhi 18:6a4db94011d3 8336 #define PWM_INTEN0_PIEN1_Pos (9) /*!< PWM_T::INTEN0: PIEN1 Position */
sahilmgandhi 18:6a4db94011d3 8337 #define PWM_INTEN0_PIEN1_Msk (0x1ul << PWM_INTEN0_PIEN1_Pos) /*!< PWM_T::INTEN0: PIEN1 Mask */
sahilmgandhi 18:6a4db94011d3 8338
sahilmgandhi 18:6a4db94011d3 8339 #define PWM_INTEN0_PIEN2_Pos (10) /*!< PWM_T::INTEN0: PIEN2 Position */
sahilmgandhi 18:6a4db94011d3 8340 #define PWM_INTEN0_PIEN2_Msk (0x1ul << PWM_INTEN0_PIEN2_Pos) /*!< PWM_T::INTEN0: PIEN2 Mask */
sahilmgandhi 18:6a4db94011d3 8341
sahilmgandhi 18:6a4db94011d3 8342 #define PWM_INTEN0_PIEN3_Pos (11) /*!< PWM_T::INTEN0: PIEN3 Position */
sahilmgandhi 18:6a4db94011d3 8343 #define PWM_INTEN0_PIEN3_Msk (0x1ul << PWM_INTEN0_PIEN3_Pos) /*!< PWM_T::INTEN0: PIEN3 Mask */
sahilmgandhi 18:6a4db94011d3 8344
sahilmgandhi 18:6a4db94011d3 8345 #define PWM_INTEN0_PIEN4_Pos (12) /*!< PWM_T::INTEN0: PIEN4 Position */
sahilmgandhi 18:6a4db94011d3 8346 #define PWM_INTEN0_PIEN4_Msk (0x1ul << PWM_INTEN0_PIEN4_Pos) /*!< PWM_T::INTEN0: PIEN4 Mask */
sahilmgandhi 18:6a4db94011d3 8347
sahilmgandhi 18:6a4db94011d3 8348 #define PWM_INTEN0_PIEN5_Pos (13) /*!< PWM_T::INTEN0: PIEN5 Position */
sahilmgandhi 18:6a4db94011d3 8349 #define PWM_INTEN0_PIEN5_Msk (0x1ul << PWM_INTEN0_PIEN5_Pos) /*!< PWM_T::INTEN0: PIEN5 Mask */
sahilmgandhi 18:6a4db94011d3 8350
sahilmgandhi 18:6a4db94011d3 8351 #define PWM_INTEN0_IFAIEN2_3_Pos (15) /*!< PWM_T::INTEN0: IFAIEN2_3 Position */
sahilmgandhi 18:6a4db94011d3 8352 #define PWM_INTEN0_IFAIEN2_3_Msk (0x1ul << PWM_INTEN0_IFAIEN2_3_Pos) /*!< PWM_T::INTEN0: IFAIEN2_3 Mask */
sahilmgandhi 18:6a4db94011d3 8353
sahilmgandhi 18:6a4db94011d3 8354 #define PWM_INTEN0_CMPUIENn_Pos (16) /*!< PWM_T::INTEN0: CMPUIENn Position */
sahilmgandhi 18:6a4db94011d3 8355 #define PWM_INTEN0_CMPUIENn_Msk (0x3ful << PWM_INTEN0_CMPUIENn_Pos) /*!< PWM_T::INTEN0: CMPUIENn Mask */
sahilmgandhi 18:6a4db94011d3 8356
sahilmgandhi 18:6a4db94011d3 8357 #define PWM_INTEN0_CMPUIEN0_Pos (16) /*!< PWM_T::INTEN0: CMPUIEN0 Position */
sahilmgandhi 18:6a4db94011d3 8358 #define PWM_INTEN0_CMPUIEN0_Msk (0x1ul << PWM_INTEN0_CMPUIEN0_Pos) /*!< PWM_T::INTEN0: CMPUIEN0 Mask */
sahilmgandhi 18:6a4db94011d3 8359
sahilmgandhi 18:6a4db94011d3 8360 #define PWM_INTEN0_CMPUIEN1_Pos (17) /*!< PWM_T::INTEN0: CMPUIEN1 Position */
sahilmgandhi 18:6a4db94011d3 8361 #define PWM_INTEN0_CMPUIEN1_Msk (0x1ul << PWM_INTEN0_CMPUIEN1_Pos) /*!< PWM_T::INTEN0: CMPUIEN1 Mask */
sahilmgandhi 18:6a4db94011d3 8362
sahilmgandhi 18:6a4db94011d3 8363 #define PWM_INTEN0_CMPUIEN2_Pos (18) /*!< PWM_T::INTEN0: CMPUIEN2 Position */
sahilmgandhi 18:6a4db94011d3 8364 #define PWM_INTEN0_CMPUIEN2_Msk (0x1ul << PWM_INTEN0_CMPUIEN2_Pos) /*!< PWM_T::INTEN0: CMPUIEN2 Mask */
sahilmgandhi 18:6a4db94011d3 8365
sahilmgandhi 18:6a4db94011d3 8366 #define PWM_INTEN0_CMPUIEN3_Pos (19) /*!< PWM_T::INTEN0: CMPUIEN3 Position */
sahilmgandhi 18:6a4db94011d3 8367 #define PWM_INTEN0_CMPUIEN3_Msk (0x1ul << PWM_INTEN0_CMPUIEN3_Pos) /*!< PWM_T::INTEN0: CMPUIEN3 Mask */
sahilmgandhi 18:6a4db94011d3 8368
sahilmgandhi 18:6a4db94011d3 8369 #define PWM_INTEN0_CMPUIEN4_Pos (20) /*!< PWM_T::INTEN0: CMPUIEN4 Position */
sahilmgandhi 18:6a4db94011d3 8370 #define PWM_INTEN0_CMPUIEN4_Msk (0x1ul << PWM_INTEN0_CMPUIEN4_Pos) /*!< PWM_T::INTEN0: CMPUIEN4 Mask */
sahilmgandhi 18:6a4db94011d3 8371
sahilmgandhi 18:6a4db94011d3 8372 #define PWM_INTEN0_CMPUIEN5_Pos (21) /*!< PWM_T::INTEN0: CMPUIEN5 Position */
sahilmgandhi 18:6a4db94011d3 8373 #define PWM_INTEN0_CMPUIEN5_Msk (0x1ul << PWM_INTEN0_CMPUIEN5_Pos) /*!< PWM_T::INTEN0: CMPUIEN5 Mask */
sahilmgandhi 18:6a4db94011d3 8374
sahilmgandhi 18:6a4db94011d3 8375 #define PWM_INTEN0_IFAIEN4_5_Pos (23) /*!< PWM_T::INTEN0: IFAIEN4_5 Position */
sahilmgandhi 18:6a4db94011d3 8376 #define PWM_INTEN0_IFAIEN4_5_Msk (0x1ul << PWM_INTEN0_IFAIEN4_5_Pos) /*!< PWM_T::INTEN0: IFAIEN4_5 Mask */
sahilmgandhi 18:6a4db94011d3 8377
sahilmgandhi 18:6a4db94011d3 8378 #define PWM_INTEN0_CMPDIENn_Pos (24) /*!< PWM_T::INTEN0: CMPDIENn Position */
sahilmgandhi 18:6a4db94011d3 8379 #define PWM_INTEN0_CMPDIENn_Msk (0x3ful << PWM_INTEN0_CMPDIENn_Pos) /*!< PWM_T::INTEN0: CMPDIENn Mask */
sahilmgandhi 18:6a4db94011d3 8380
sahilmgandhi 18:6a4db94011d3 8381 #define PWM_INTEN0_CMPDIEN0_Pos (24) /*!< PWM_T::INTEN0: CMPDIEN0 Position */
sahilmgandhi 18:6a4db94011d3 8382 #define PWM_INTEN0_CMPDIEN0_Msk (0x1ul << PWM_INTEN0_CMPDIEN0_Pos) /*!< PWM_T::INTEN0: CMPDIEN0 Mask */
sahilmgandhi 18:6a4db94011d3 8383
sahilmgandhi 18:6a4db94011d3 8384 #define PWM_INTEN0_CMPDIEN1_Pos (25) /*!< PWM_T::INTEN0: CMPDIEN1 Position */
sahilmgandhi 18:6a4db94011d3 8385 #define PWM_INTEN0_CMPDIEN1_Msk (0x1ul << PWM_INTEN0_CMPDIEN1_Pos) /*!< PWM_T::INTEN0: CMPDIEN1 Mask */
sahilmgandhi 18:6a4db94011d3 8386
sahilmgandhi 18:6a4db94011d3 8387 #define PWM_INTEN0_CMPDIEN2_Pos (26) /*!< PWM_T::INTEN0: CMPDIEN2 Position */
sahilmgandhi 18:6a4db94011d3 8388 #define PWM_INTEN0_CMPDIEN2_Msk (0x1ul << PWM_INTEN0_CMPDIEN2_Pos) /*!< PWM_T::INTEN0: CMPDIEN2 Mask */
sahilmgandhi 18:6a4db94011d3 8389
sahilmgandhi 18:6a4db94011d3 8390 #define PWM_INTEN0_CMPDIEN3_Pos (27) /*!< PWM_T::INTEN0: CMPDIEN3 Position */
sahilmgandhi 18:6a4db94011d3 8391 #define PWM_INTEN0_CMPDIEN3_Msk (0x1ul << PWM_INTEN0_CMPDIEN3_Pos) /*!< PWM_T::INTEN0: CMPDIEN3 Mask */
sahilmgandhi 18:6a4db94011d3 8392
sahilmgandhi 18:6a4db94011d3 8393 #define PWM_INTEN0_CMPDIEN4_Pos (28) /*!< PWM_T::INTEN0: CMPDIEN4 Position */
sahilmgandhi 18:6a4db94011d3 8394 #define PWM_INTEN0_CMPDIEN4_Msk (0x1ul << PWM_INTEN0_CMPDIEN4_Pos) /*!< PWM_T::INTEN0: CMPDIEN4 Mask */
sahilmgandhi 18:6a4db94011d3 8395
sahilmgandhi 18:6a4db94011d3 8396 #define PWM_INTEN0_CMPDIEN5_Pos (29) /*!< PWM_T::INTEN0: CMPDIEN5 Position */
sahilmgandhi 18:6a4db94011d3 8397 #define PWM_INTEN0_CMPDIEN5_Msk (0x1ul << PWM_INTEN0_CMPDIEN5_Pos) /*!< PWM_T::INTEN0: CMPDIEN5 Mask */
sahilmgandhi 18:6a4db94011d3 8398
sahilmgandhi 18:6a4db94011d3 8399 #define PWM_INTEN1_BRKEIEN0_1_Pos (0) /*!< PWM_T::INTEN1: BRKEIEN0_1 Position */
sahilmgandhi 18:6a4db94011d3 8400 #define PWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << PWM_INTEN1_BRKEIEN0_1_Pos) /*!< PWM_T::INTEN1: BRKEIEN0_1 Mask */
sahilmgandhi 18:6a4db94011d3 8401
sahilmgandhi 18:6a4db94011d3 8402 #define PWM_INTEN1_BRKEIEN2_3_Pos (1) /*!< PWM_T::INTEN1: BRKEIEN2_3 Position */
sahilmgandhi 18:6a4db94011d3 8403 #define PWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << PWM_INTEN1_BRKEIEN2_3_Pos) /*!< PWM_T::INTEN1: BRKEIEN2_3 Mask */
sahilmgandhi 18:6a4db94011d3 8404
sahilmgandhi 18:6a4db94011d3 8405 #define PWM_INTEN1_BRKEIEN4_5_Pos (2) /*!< PWM_T::INTEN1: BRKEIEN4_5 Position */
sahilmgandhi 18:6a4db94011d3 8406 #define PWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << PWM_INTEN1_BRKEIEN4_5_Pos) /*!< PWM_T::INTEN1: BRKEIEN4_5 Mask */
sahilmgandhi 18:6a4db94011d3 8407
sahilmgandhi 18:6a4db94011d3 8408 #define PWM_INTEN1_BRKLIEN0_1_Pos (8) /*!< PWM_T::INTEN1: BRKLIEN0_1 Position */
sahilmgandhi 18:6a4db94011d3 8409 #define PWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << PWM_INTEN1_BRKLIEN0_1_Pos) /*!< PWM_T::INTEN1: BRKLIEN0_1 Mask */
sahilmgandhi 18:6a4db94011d3 8410
sahilmgandhi 18:6a4db94011d3 8411 #define PWM_INTEN1_BRKLIEN2_3_Pos (9) /*!< PWM_T::INTEN1: BRKLIEN2_3 Position */
sahilmgandhi 18:6a4db94011d3 8412 #define PWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << PWM_INTEN1_BRKLIEN2_3_Pos) /*!< PWM_T::INTEN1: BRKLIEN2_3 Mask */
sahilmgandhi 18:6a4db94011d3 8413
sahilmgandhi 18:6a4db94011d3 8414 #define PWM_INTEN1_BRKLIEN4_5_Pos (10) /*!< PWM_T::INTEN1: BRKLIEN4_5 Position */
sahilmgandhi 18:6a4db94011d3 8415 #define PWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << PWM_INTEN1_BRKLIEN4_5_Pos) /*!< PWM_T::INTEN1: BRKLIEN4_5 Mask */
sahilmgandhi 18:6a4db94011d3 8416
sahilmgandhi 18:6a4db94011d3 8417 #define PWM_INTSTS0_ZIFn_Pos (0) /*!< PWM_T::INTSTS0: ZIFn Position */
sahilmgandhi 18:6a4db94011d3 8418 #define PWM_INTSTS0_ZIFn_Msk (0x3ful << PWM_INTSTS0_ZIFn_Pos) /*!< PWM_T::INTSTS0: ZIFn Mask */
sahilmgandhi 18:6a4db94011d3 8419
sahilmgandhi 18:6a4db94011d3 8420 #define PWM_INTSTS0_ZIF0_Pos (0) /*!< PWM_T::INTSTS0: ZIF0 Position */
sahilmgandhi 18:6a4db94011d3 8421 #define PWM_INTSTS0_ZIF0_Msk (0x1ul << PWM_INTSTS0_ZIF0_Pos) /*!< PWM_T::INTSTS0: ZIF0 Mask */
sahilmgandhi 18:6a4db94011d3 8422
sahilmgandhi 18:6a4db94011d3 8423 #define PWM_INTSTS0_ZIF1_Pos (1) /*!< PWM_T::INTSTS0: ZIF1 Position */
sahilmgandhi 18:6a4db94011d3 8424 #define PWM_INTSTS0_ZIF1_Msk (0x1ul << PWM_INTSTS0_ZIF1_Pos) /*!< PWM_T::INTSTS0: ZIF1 Mask */
sahilmgandhi 18:6a4db94011d3 8425
sahilmgandhi 18:6a4db94011d3 8426 #define PWM_INTSTS0_ZIF2_Pos (2) /*!< PWM_T::INTSTS0: ZIF2 Position */
sahilmgandhi 18:6a4db94011d3 8427 #define PWM_INTSTS0_ZIF2_Msk (0x1ul << PWM_INTSTS0_ZIF2_Pos) /*!< PWM_T::INTSTS0: ZIF2 Mask */
sahilmgandhi 18:6a4db94011d3 8428
sahilmgandhi 18:6a4db94011d3 8429 #define PWM_INTSTS0_ZIF3_Pos (3) /*!< PWM_T::INTSTS0: ZIF3 Position */
sahilmgandhi 18:6a4db94011d3 8430 #define PWM_INTSTS0_ZIF3_Msk (0x1ul << PWM_INTSTS0_ZIF3_Pos) /*!< PWM_T::INTSTS0: ZIF3 Mask */
sahilmgandhi 18:6a4db94011d3 8431
sahilmgandhi 18:6a4db94011d3 8432 #define PWM_INTSTS0_ZIF4_Pos (4) /*!< PWM_T::INTSTS0: ZIF4 Position */
sahilmgandhi 18:6a4db94011d3 8433 #define PWM_INTSTS0_ZIF4_Msk (0x1ul << PWM_INTSTS0_ZIF4_Pos) /*!< PWM_T::INTSTS0: ZIF4 Mask */
sahilmgandhi 18:6a4db94011d3 8434
sahilmgandhi 18:6a4db94011d3 8435 #define PWM_INTSTS0_ZIF5_Pos (5) /*!< PWM_T::INTSTS0: ZIF5 Position */
sahilmgandhi 18:6a4db94011d3 8436 #define PWM_INTSTS0_ZIF5_Msk (0x1ul << PWM_INTSTS0_ZIF5_Pos) /*!< PWM_T::INTSTS0: ZIF5 Mask */
sahilmgandhi 18:6a4db94011d3 8437
sahilmgandhi 18:6a4db94011d3 8438 #define PWM_INTSTS0_IFAIF0_1_Pos (7) /*!< PWM_T::INTSTS0: IFAIF0_1 Position */
sahilmgandhi 18:6a4db94011d3 8439 #define PWM_INTSTS0_IFAIF0_1_Msk (0x1ul << PWM_INTSTS0_IFAIF0_1_Pos) /*!< PWM_T::INTSTS0: IFAIF0_1 Mask */
sahilmgandhi 18:6a4db94011d3 8440
sahilmgandhi 18:6a4db94011d3 8441 #define PWM_INTSTS0_PIFn_Pos (8) /*!< PWM_T::INTSTS0: PIFn Position */
sahilmgandhi 18:6a4db94011d3 8442 #define PWM_INTSTS0_PIFn_Msk (0x3ful << PWM_INTSTS0_PIFn_Pos) /*!< PWM_T::INTSTS0: PIFn Mask */
sahilmgandhi 18:6a4db94011d3 8443
sahilmgandhi 18:6a4db94011d3 8444 #define PWM_INTSTS0_PIF0_Pos (8) /*!< PWM_T::INTSTS0: PIF0 Position */
sahilmgandhi 18:6a4db94011d3 8445 #define PWM_INTSTS0_PIF0_Msk (0x1ul << PWM_INTSTS0_PIF0_Pos) /*!< PWM_T::INTSTS0: PIF0 Mask */
sahilmgandhi 18:6a4db94011d3 8446
sahilmgandhi 18:6a4db94011d3 8447 #define PWM_INTSTS0_PIF1_Pos (9) /*!< PWM_T::INTSTS0: PIF1 Position */
sahilmgandhi 18:6a4db94011d3 8448 #define PWM_INTSTS0_PIF1_Msk (0x1ul << PWM_INTSTS0_PIF1_Pos) /*!< PWM_T::INTSTS0: PIF1 Mask */
sahilmgandhi 18:6a4db94011d3 8449
sahilmgandhi 18:6a4db94011d3 8450 #define PWM_INTSTS0_PIF2_Pos (10) /*!< PWM_T::INTSTS0: PIF2 Position */
sahilmgandhi 18:6a4db94011d3 8451 #define PWM_INTSTS0_PIF2_Msk (0x1ul << PWM_INTSTS0_PIF2_Pos) /*!< PWM_T::INTSTS0: PIF2 Mask */
sahilmgandhi 18:6a4db94011d3 8452
sahilmgandhi 18:6a4db94011d3 8453 #define PWM_INTSTS0_PIF3_Pos (11) /*!< PWM_T::INTSTS0: PIF3 Position */
sahilmgandhi 18:6a4db94011d3 8454 #define PWM_INTSTS0_PIF3_Msk (0x1ul << PWM_INTSTS0_PIF3_Pos) /*!< PWM_T::INTSTS0: PIF3 Mask */
sahilmgandhi 18:6a4db94011d3 8455
sahilmgandhi 18:6a4db94011d3 8456 #define PWM_INTSTS0_PIF4_Pos (12) /*!< PWM_T::INTSTS0: PIF4 Position */
sahilmgandhi 18:6a4db94011d3 8457 #define PWM_INTSTS0_PIF4_Msk (0x1ul << PWM_INTSTS0_PIF4_Pos) /*!< PWM_T::INTSTS0: PIF4 Mask */
sahilmgandhi 18:6a4db94011d3 8458
sahilmgandhi 18:6a4db94011d3 8459 #define PWM_INTSTS0_PIF5_Pos (13) /*!< PWM_T::INTSTS0: PIF5 Position */
sahilmgandhi 18:6a4db94011d3 8460 #define PWM_INTSTS0_PIF5_Msk (0x1ul << PWM_INTSTS0_PIF5_Pos) /*!< PWM_T::INTSTS0: PIF5 Mask */
sahilmgandhi 18:6a4db94011d3 8461
sahilmgandhi 18:6a4db94011d3 8462 #define PWM_INTSTS0_IFAIF2_3_Pos (15) /*!< PWM_T::INTSTS0: IFAIF2_3 Position */
sahilmgandhi 18:6a4db94011d3 8463 #define PWM_INTSTS0_IFAIF2_3_Msk (0x1ul << PWM_INTSTS0_IFAIF2_3_Pos) /*!< PWM_T::INTSTS0: IFAIF2_3 Mask */
sahilmgandhi 18:6a4db94011d3 8464
sahilmgandhi 18:6a4db94011d3 8465 #define PWM_INTSTS0_CMPUIFn_Pos (16) /*!< PWM_T::INTSTS0: CMPUIFn Position */
sahilmgandhi 18:6a4db94011d3 8466 #define PWM_INTSTS0_CMPUIFn_Msk (0x3ful << PWM_INTSTS0_CMPUIFn_Pos) /*!< PWM_T::INTSTS0: CMPUIFn Mask */
sahilmgandhi 18:6a4db94011d3 8467
sahilmgandhi 18:6a4db94011d3 8468 #define PWM_INTSTS0_CMPUIF0_Pos (16) /*!< PWM_T::INTSTS0: CMPUIF0 Position */
sahilmgandhi 18:6a4db94011d3 8469 #define PWM_INTSTS0_CMPUIF0_Msk (0x1ul << PWM_INTSTS0_CMPUIF0_Pos) /*!< PWM_T::INTSTS0: CMPUIF0 Mask */
sahilmgandhi 18:6a4db94011d3 8470
sahilmgandhi 18:6a4db94011d3 8471 #define PWM_INTSTS0_CMPUIF1_Pos (17) /*!< PWM_T::INTSTS0: CMPUIF1 Position */
sahilmgandhi 18:6a4db94011d3 8472 #define PWM_INTSTS0_CMPUIF1_Msk (0x1ul << PWM_INTSTS0_CMPUIF1_Pos) /*!< PWM_T::INTSTS0: CMPUIF1 Mask */
sahilmgandhi 18:6a4db94011d3 8473
sahilmgandhi 18:6a4db94011d3 8474 #define PWM_INTSTS0_CMPUIF2_Pos (18) /*!< PWM_T::INTSTS0: CMPUIF2 Position */
sahilmgandhi 18:6a4db94011d3 8475 #define PWM_INTSTS0_CMPUIF2_Msk (0x1ul << PWM_INTSTS0_CMPUIF2_Pos) /*!< PWM_T::INTSTS0: CMPUIF2 Mask */
sahilmgandhi 18:6a4db94011d3 8476
sahilmgandhi 18:6a4db94011d3 8477 #define PWM_INTSTS0_CMPUIF3_Pos (19) /*!< PWM_T::INTSTS0: CMPUIF3 Position */
sahilmgandhi 18:6a4db94011d3 8478 #define PWM_INTSTS0_CMPUIF3_Msk (0x1ul << PWM_INTSTS0_CMPUIF3_Pos) /*!< PWM_T::INTSTS0: CMPUIF3 Mask */
sahilmgandhi 18:6a4db94011d3 8479
sahilmgandhi 18:6a4db94011d3 8480 #define PWM_INTSTS0_CMPUIF4_Pos (20) /*!< PWM_T::INTSTS0: CMPUIF4 Position */
sahilmgandhi 18:6a4db94011d3 8481 #define PWM_INTSTS0_CMPUIF4_Msk (0x1ul << PWM_INTSTS0_CMPUIF4_Pos) /*!< PWM_T::INTSTS0: CMPUIF4 Mask */
sahilmgandhi 18:6a4db94011d3 8482
sahilmgandhi 18:6a4db94011d3 8483 #define PWM_INTSTS0_CMPUIF5_Pos (21) /*!< PWM_T::INTSTS0: CMPUIF5 Position */
sahilmgandhi 18:6a4db94011d3 8484 #define PWM_INTSTS0_CMPUIF5_Msk (0x1ul << PWM_INTSTS0_CMPUIF5_Pos) /*!< PWM_T::INTSTS0: CMPUIF5 Mask */
sahilmgandhi 18:6a4db94011d3 8485
sahilmgandhi 18:6a4db94011d3 8486 #define PWM_INTSTS0_IFAIF4_5_Pos (23) /*!< PWM_T::INTSTS0: IFAIF4_5 Position */
sahilmgandhi 18:6a4db94011d3 8487 #define PWM_INTSTS0_IFAIF4_5_Msk (0x1ul << PWM_INTSTS0_IFAIF4_5_Pos) /*!< PWM_T::INTSTS0: IFAIF4_5 Mask */
sahilmgandhi 18:6a4db94011d3 8488
sahilmgandhi 18:6a4db94011d3 8489 #define PWM_INTSTS0_CMPDIFn_Pos (24) /*!< PWM_T::INTSTS0: CMPDIFn Position */
sahilmgandhi 18:6a4db94011d3 8490 #define PWM_INTSTS0_CMPDIFn_Msk (0x3ful << PWM_INTSTS0_CMPDIFn_Pos) /*!< PWM_T::INTSTS0: CMPDIFn Mask */
sahilmgandhi 18:6a4db94011d3 8491
sahilmgandhi 18:6a4db94011d3 8492 #define PWM_INTSTS0_CMPDIF0_Pos (24) /*!< PWM_T::INTSTS0: CMPDIF0 Position */
sahilmgandhi 18:6a4db94011d3 8493 #define PWM_INTSTS0_CMPDIF0_Msk (0x1ul << PWM_INTSTS0_CMPDIF0_Pos) /*!< PWM_T::INTSTS0: CMPDIF0 Mask */
sahilmgandhi 18:6a4db94011d3 8494
sahilmgandhi 18:6a4db94011d3 8495 #define PWM_INTSTS0_CMPDIF1_Pos (25) /*!< PWM_T::INTSTS0: CMPDIF1 Position */
sahilmgandhi 18:6a4db94011d3 8496 #define PWM_INTSTS0_CMPDIF1_Msk (0x1ul << PWM_INTSTS0_CMPDIF1_Pos) /*!< PWM_T::INTSTS0: CMPDIF1 Mask */
sahilmgandhi 18:6a4db94011d3 8497
sahilmgandhi 18:6a4db94011d3 8498 #define PWM_INTSTS0_CMPDIF2_Pos (26) /*!< PWM_T::INTSTS0: CMPDIF2 Position */
sahilmgandhi 18:6a4db94011d3 8499 #define PWM_INTSTS0_CMPDIF2_Msk (0x1ul << PWM_INTSTS0_CMPDIF2_Pos) /*!< PWM_T::INTSTS0: CMPDIF2 Mask */
sahilmgandhi 18:6a4db94011d3 8500
sahilmgandhi 18:6a4db94011d3 8501 #define PWM_INTSTS0_CMPDIF3_Pos (27) /*!< PWM_T::INTSTS0: CMPDIF3 Position */
sahilmgandhi 18:6a4db94011d3 8502 #define PWM_INTSTS0_CMPDIF3_Msk (0x1ul << PWM_INTSTS0_CMPDIF3_Pos) /*!< PWM_T::INTSTS0: CMPDIF3 Mask */
sahilmgandhi 18:6a4db94011d3 8503
sahilmgandhi 18:6a4db94011d3 8504 #define PWM_INTSTS0_CMPDIF4_Pos (28) /*!< PWM_T::INTSTS0: CMPDIF4 Position */
sahilmgandhi 18:6a4db94011d3 8505 #define PWM_INTSTS0_CMPDIF4_Msk (0x1ul << PWM_INTSTS0_CMPDIF4_Pos) /*!< PWM_T::INTSTS0: CMPDIF4 Mask */
sahilmgandhi 18:6a4db94011d3 8506
sahilmgandhi 18:6a4db94011d3 8507 #define PWM_INTSTS0_CMPDIF5_Pos (29) /*!< PWM_T::INTSTS0: CMPDIF5 Position */
sahilmgandhi 18:6a4db94011d3 8508 #define PWM_INTSTS0_CMPDIF5_Msk (0x1ul << PWM_INTSTS0_CMPDIF5_Pos) /*!< PWM_T::INTSTS0: CMPDIF5 Mask */
sahilmgandhi 18:6a4db94011d3 8509
sahilmgandhi 18:6a4db94011d3 8510 #define PWM_INTSTS1_BRKEIFn_Pos (0) /*!< PWM_T::INTSTS1: BRKEIFn Position */
sahilmgandhi 18:6a4db94011d3 8511 #define PWM_INTSTS1_BRKEIFn_Msk (0x3ful << PWM_INTSTS1_BRKEIFn_Pos) /*!< PWM_T::INTSTS1: BRKEIFn Mask */
sahilmgandhi 18:6a4db94011d3 8512
sahilmgandhi 18:6a4db94011d3 8513 #define PWM_INTSTS1_BRKEIF0_Pos (0) /*!< PWM_T::INTSTS1: BRKEIF0 Position */
sahilmgandhi 18:6a4db94011d3 8514 #define PWM_INTSTS1_BRKEIF0_Msk (0x1ul << PWM_INTSTS1_BRKEIF0_Pos) /*!< PWM_T::INTSTS1: BRKEIF0 Mask */
sahilmgandhi 18:6a4db94011d3 8515
sahilmgandhi 18:6a4db94011d3 8516 #define PWM_INTSTS1_BRKEIF1_Pos (1) /*!< PWM_T::INTSTS1: BRKEIF1 Position */
sahilmgandhi 18:6a4db94011d3 8517 #define PWM_INTSTS1_BRKEIF1_Msk (0x1ul << PWM_INTSTS1_BRKEIF1_Pos) /*!< PWM_T::INTSTS1: BRKEIF1 Mask */
sahilmgandhi 18:6a4db94011d3 8518
sahilmgandhi 18:6a4db94011d3 8519 #define PWM_INTSTS1_BRKEIF2_Pos (2) /*!< PWM_T::INTSTS1: BRKEIF2 Position */
sahilmgandhi 18:6a4db94011d3 8520 #define PWM_INTSTS1_BRKEIF2_Msk (0x1ul << PWM_INTSTS1_BRKEIF2_Pos) /*!< PWM_T::INTSTS1: BRKEIF2 Mask */
sahilmgandhi 18:6a4db94011d3 8521
sahilmgandhi 18:6a4db94011d3 8522 #define PWM_INTSTS1_BRKEIF3_Pos (3) /*!< PWM_T::INTSTS1: BRKEIF3 Position */
sahilmgandhi 18:6a4db94011d3 8523 #define PWM_INTSTS1_BRKEIF3_Msk (0x1ul << PWM_INTSTS1_BRKEIF3_Pos) /*!< PWM_T::INTSTS1: BRKEIF3 Mask */
sahilmgandhi 18:6a4db94011d3 8524
sahilmgandhi 18:6a4db94011d3 8525 #define PWM_INTSTS1_BRKEIF4_Pos (4) /*!< PWM_T::INTSTS1: BRKEIF4 Position */
sahilmgandhi 18:6a4db94011d3 8526 #define PWM_INTSTS1_BRKEIF4_Msk (0x1ul << PWM_INTSTS1_BRKEIF4_Pos) /*!< PWM_T::INTSTS1: BRKEIF4 Mask */
sahilmgandhi 18:6a4db94011d3 8527
sahilmgandhi 18:6a4db94011d3 8528 #define PWM_INTSTS1_BRKEIF5_Pos (5) /*!< PWM_T::INTSTS1: BRKEIF5 Position */
sahilmgandhi 18:6a4db94011d3 8529 #define PWM_INTSTS1_BRKEIF5_Msk (0x1ul << PWM_INTSTS1_BRKEIF5_Pos) /*!< PWM_T::INTSTS1: BRKEIF5 Mask */
sahilmgandhi 18:6a4db94011d3 8530
sahilmgandhi 18:6a4db94011d3 8531 #define PWM_INTSTS1_BRKLIFn_Pos (8) /*!< PWM_T::INTSTS1: BRKLIFn Position */
sahilmgandhi 18:6a4db94011d3 8532 #define PWM_INTSTS1_BRKLIFn_Msk (0x3ful << PWM_INTSTS1_BRKLIFn_Pos) /*!< PWM_T::INTSTS1: BRKLIFn Mask */
sahilmgandhi 18:6a4db94011d3 8533
sahilmgandhi 18:6a4db94011d3 8534 #define PWM_INTSTS1_BRKLIF0_Pos (8) /*!< PWM_T::INTSTS1: BRKLIF0 Position */
sahilmgandhi 18:6a4db94011d3 8535 #define PWM_INTSTS1_BRKLIF0_Msk (0x1ul << PWM_INTSTS1_BRKLIF0_Pos) /*!< PWM_T::INTSTS1: BRKLIF0 Mask */
sahilmgandhi 18:6a4db94011d3 8536
sahilmgandhi 18:6a4db94011d3 8537 #define PWM_INTSTS1_BRKLIF1_Pos (9) /*!< PWM_T::INTSTS1: BRKLIF1 Position */
sahilmgandhi 18:6a4db94011d3 8538 #define PWM_INTSTS1_BRKLIF1_Msk (0x1ul << PWM_INTSTS1_BRKLIF1_Pos) /*!< PWM_T::INTSTS1: BRKLIF1 Mask */
sahilmgandhi 18:6a4db94011d3 8539
sahilmgandhi 18:6a4db94011d3 8540 #define PWM_INTSTS1_BRKLIF2_Pos (10) /*!< PWM_T::INTSTS1: BRKLIF2 Position */
sahilmgandhi 18:6a4db94011d3 8541 #define PWM_INTSTS1_BRKLIF2_Msk (0x1ul << PWM_INTSTS1_BRKLIF2_Pos) /*!< PWM_T::INTSTS1: BRKLIF2 Mask */
sahilmgandhi 18:6a4db94011d3 8542
sahilmgandhi 18:6a4db94011d3 8543 #define PWM_INTSTS1_BRKLIF3_Pos (11) /*!< PWM_T::INTSTS1: BRKLIF3 Position */
sahilmgandhi 18:6a4db94011d3 8544 #define PWM_INTSTS1_BRKLIF3_Msk (0x1ul << PWM_INTSTS1_BRKLIF3_Pos) /*!< PWM_T::INTSTS1: BRKLIF3 Mask */
sahilmgandhi 18:6a4db94011d3 8545
sahilmgandhi 18:6a4db94011d3 8546 #define PWM_INTSTS1_BRKLIF4_Pos (12) /*!< PWM_T::INTSTS1: BRKLIF4 Position */
sahilmgandhi 18:6a4db94011d3 8547 #define PWM_INTSTS1_BRKLIF4_Msk (0x1ul << PWM_INTSTS1_BRKLIF4_Pos) /*!< PWM_T::INTSTS1: BRKLIF4 Mask */
sahilmgandhi 18:6a4db94011d3 8548
sahilmgandhi 18:6a4db94011d3 8549 #define PWM_INTSTS1_BRKLIF5_Pos (13) /*!< PWM_T::INTSTS1: BRKLIF5 Position */
sahilmgandhi 18:6a4db94011d3 8550 #define PWM_INTSTS1_BRKLIF5_Msk (0x1ul << PWM_INTSTS1_BRKLIF5_Pos) /*!< PWM_T::INTSTS1: BRKLIF5 Mask */
sahilmgandhi 18:6a4db94011d3 8551
sahilmgandhi 18:6a4db94011d3 8552 #define PWM_INTSTS1_BRKESTS0_Pos (16) /*!< PWM_T::INTSTS1: BRKESTS0 Position */
sahilmgandhi 18:6a4db94011d3 8553 #define PWM_INTSTS1_BRKESTS0_Msk (0x1ul << PWM_INTSTS1_BRKESTS0_Pos) /*!< PWM_T::INTSTS1: BRKESTS0 Mask */
sahilmgandhi 18:6a4db94011d3 8554
sahilmgandhi 18:6a4db94011d3 8555 #define PWM_INTSTS1_BRKESTS1_Pos (17) /*!< PWM_T::INTSTS1: BRKESTS1 Position */
sahilmgandhi 18:6a4db94011d3 8556 #define PWM_INTSTS1_BRKESTS1_Msk (0x1ul << PWM_INTSTS1_BRKESTS1_Pos) /*!< PWM_T::INTSTS1: BRKESTS1 Mask */
sahilmgandhi 18:6a4db94011d3 8557
sahilmgandhi 18:6a4db94011d3 8558 #define PWM_INTSTS1_BRKESTS2_Pos (18) /*!< PWM_T::INTSTS1: BRKESTS2 Position */
sahilmgandhi 18:6a4db94011d3 8559 #define PWM_INTSTS1_BRKESTS2_Msk (0x1ul << PWM_INTSTS1_BRKESTS2_Pos) /*!< PWM_T::INTSTS1: BRKESTS2 Mask */
sahilmgandhi 18:6a4db94011d3 8560
sahilmgandhi 18:6a4db94011d3 8561 #define PWM_INTSTS1_BRKESTS3_Pos (19) /*!< PWM_T::INTSTS1: BRKESTS3 Position */
sahilmgandhi 18:6a4db94011d3 8562 #define PWM_INTSTS1_BRKESTS3_Msk (0x1ul << PWM_INTSTS1_BRKESTS3_Pos) /*!< PWM_T::INTSTS1: BRKESTS3 Mask */
sahilmgandhi 18:6a4db94011d3 8563
sahilmgandhi 18:6a4db94011d3 8564 #define PWM_INTSTS1_BRKESTS4_Pos (20) /*!< PWM_T::INTSTS1: BRKESTS4 Position */
sahilmgandhi 18:6a4db94011d3 8565 #define PWM_INTSTS1_BRKESTS4_Msk (0x1ul << PWM_INTSTS1_BRKESTS4_Pos) /*!< PWM_T::INTSTS1: BRKESTS4 Mask */
sahilmgandhi 18:6a4db94011d3 8566
sahilmgandhi 18:6a4db94011d3 8567 #define PWM_INTSTS1_BRKESTS5_Pos (21) /*!< PWM_T::INTSTS1: BRKESTS5 Position */
sahilmgandhi 18:6a4db94011d3 8568 #define PWM_INTSTS1_BRKESTS5_Msk (0x1ul << PWM_INTSTS1_BRKESTS5_Pos) /*!< PWM_T::INTSTS1: BRKESTS5 Mask */
sahilmgandhi 18:6a4db94011d3 8569
sahilmgandhi 18:6a4db94011d3 8570 #define PWM_INTSTS1_BRKLSTS0_Pos (24) /*!< PWM_T::INTSTS1: BRKLSTS0 Position */
sahilmgandhi 18:6a4db94011d3 8571 #define PWM_INTSTS1_BRKLSTS0_Msk (0x1ul << PWM_INTSTS1_BRKLSTS0_Pos) /*!< PWM_T::INTSTS1: BRKLSTS0 Mask */
sahilmgandhi 18:6a4db94011d3 8572
sahilmgandhi 18:6a4db94011d3 8573 #define PWM_INTSTS1_BRKLSTS1_Pos (25) /*!< PWM_T::INTSTS1: BRKLSTS1 Position */
sahilmgandhi 18:6a4db94011d3 8574 #define PWM_INTSTS1_BRKLSTS1_Msk (0x1ul << PWM_INTSTS1_BRKLSTS1_Pos) /*!< PWM_T::INTSTS1: BRKLSTS1 Mask */
sahilmgandhi 18:6a4db94011d3 8575
sahilmgandhi 18:6a4db94011d3 8576 #define PWM_INTSTS1_BRKLSTS2_Pos (26) /*!< PWM_T::INTSTS1: BRKLSTS2 Position */
sahilmgandhi 18:6a4db94011d3 8577 #define PWM_INTSTS1_BRKLSTS2_Msk (0x1ul << PWM_INTSTS1_BRKLSTS2_Pos) /*!< PWM_T::INTSTS1: BRKLSTS2 Mask */
sahilmgandhi 18:6a4db94011d3 8578
sahilmgandhi 18:6a4db94011d3 8579 #define PWM_INTSTS1_BRKLSTS3_Pos (27) /*!< PWM_T::INTSTS1: BRKLSTS3 Position */
sahilmgandhi 18:6a4db94011d3 8580 #define PWM_INTSTS1_BRKLSTS3_Msk (0x1ul << PWM_INTSTS1_BRKLSTS3_Pos) /*!< PWM_T::INTSTS1: BRKLSTS3 Mask */
sahilmgandhi 18:6a4db94011d3 8581
sahilmgandhi 18:6a4db94011d3 8582 #define PWM_INTSTS1_BRKLSTS4_Pos (28) /*!< PWM_T::INTSTS1: BRKLSTS4 Position */
sahilmgandhi 18:6a4db94011d3 8583 #define PWM_INTSTS1_BRKLSTS4_Msk (0x1ul << PWM_INTSTS1_BRKLSTS4_Pos) /*!< PWM_T::INTSTS1: BRKLSTS4 Mask */
sahilmgandhi 18:6a4db94011d3 8584
sahilmgandhi 18:6a4db94011d3 8585 #define PWM_INTSTS1_BRKLSTS5_Pos (29) /*!< PWM_T::INTSTS1: BRKLSTS5 Position */
sahilmgandhi 18:6a4db94011d3 8586 #define PWM_INTSTS1_BRKLSTS5_Msk (0x1ul << PWM_INTSTS1_BRKLSTS5_Pos) /*!< PWM_T::INTSTS1: BRKLSTS5 Mask */
sahilmgandhi 18:6a4db94011d3 8587
sahilmgandhi 18:6a4db94011d3 8588 #define PWM_IFA_IFCNT0_1_Pos (0) /*!< PWM_T::IFA: IFCNT0_1 Position */
sahilmgandhi 18:6a4db94011d3 8589 #define PWM_IFA_IFCNT0_1_Msk (0xful << PWM_IFA_IFCNT0_1_Pos) /*!< PWM_T::IFA: IFCNT0_1 Mask */
sahilmgandhi 18:6a4db94011d3 8590
sahilmgandhi 18:6a4db94011d3 8591 #define PWM_IFA_IFSEL0_1_Pos (4) /*!< PWM_T::IFA: IFSEL0_1 Position */
sahilmgandhi 18:6a4db94011d3 8592 #define PWM_IFA_IFSEL0_1_Msk (0x7ul << PWM_IFA_IFSEL0_1_Pos) /*!< PWM_T::IFA: IFSEL0_1 Mask */
sahilmgandhi 18:6a4db94011d3 8593
sahilmgandhi 18:6a4db94011d3 8594 #define PWM_IFA_IFAEN0_1_Pos (7) /*!< PWM_T::IFA: IFAEN0_1 Position */
sahilmgandhi 18:6a4db94011d3 8595 #define PWM_IFA_IFAEN0_1_Msk (0x1ul << PWM_IFA_IFAEN0_1_Pos) /*!< PWM_T::IFA: IFAEN0_1 Mask */
sahilmgandhi 18:6a4db94011d3 8596
sahilmgandhi 18:6a4db94011d3 8597 #define PWM_IFA_IFCNT2_3_Pos (8) /*!< PWM_T::IFA: IFCNT2_3 Position */
sahilmgandhi 18:6a4db94011d3 8598 #define PWM_IFA_IFCNT2_3_Msk (0xful << PWM_IFA_IFCNT2_3_Pos) /*!< PWM_T::IFA: IFCNT2_3 Mask */
sahilmgandhi 18:6a4db94011d3 8599
sahilmgandhi 18:6a4db94011d3 8600 #define PWM_IFA_IFSEL2_3_Pos (12) /*!< PWM_T::IFA: IFSEL2_3 Position */
sahilmgandhi 18:6a4db94011d3 8601 #define PWM_IFA_IFSEL2_3_Msk (0x7ul << PWM_IFA_IFSEL2_3_Pos) /*!< PWM_T::IFA: IFSEL2_3 Mask */
sahilmgandhi 18:6a4db94011d3 8602
sahilmgandhi 18:6a4db94011d3 8603 #define PWM_IFA_IFAEN2_3_Pos (15) /*!< PWM_T::IFA: IFAEN2_3 Position */
sahilmgandhi 18:6a4db94011d3 8604 #define PWM_IFA_IFAEN2_3_Msk (0x1ul << PWM_IFA_IFAEN2_3_Pos) /*!< PWM_T::IFA: IFAEN2_3 Mask */
sahilmgandhi 18:6a4db94011d3 8605
sahilmgandhi 18:6a4db94011d3 8606 #define PWM_IFA_IFCNT4_5_Pos (16) /*!< PWM_T::IFA: IFCNT4_5 Position */
sahilmgandhi 18:6a4db94011d3 8607 #define PWM_IFA_IFCNT4_5_Msk (0xful << PWM_IFA_IFCNT4_5_Pos) /*!< PWM_T::IFA: IFCNT4_5 Mask */
sahilmgandhi 18:6a4db94011d3 8608
sahilmgandhi 18:6a4db94011d3 8609 #define PWM_IFA_IFSEL4_5_Pos (20) /*!< PWM_T::IFA: IFSEL4_5 Position */
sahilmgandhi 18:6a4db94011d3 8610 #define PWM_IFA_IFSEL4_5_Msk (0x7ul << PWM_IFA_IFSEL4_5_Pos) /*!< PWM_T::IFA: IFSEL4_5 Mask */
sahilmgandhi 18:6a4db94011d3 8611
sahilmgandhi 18:6a4db94011d3 8612 #define PWM_IFA_IFAEN4_5_Pos (23) /*!< PWM_T::IFA: IFAEN4_5 Position */
sahilmgandhi 18:6a4db94011d3 8613 #define PWM_IFA_IFAEN4_5_Msk (0x1ul << PWM_IFA_IFAEN4_5_Pos) /*!< PWM_T::IFA: IFAEN4_5 Mask */
sahilmgandhi 18:6a4db94011d3 8614
sahilmgandhi 18:6a4db94011d3 8615 #define PWM_DACTRGEN_ZTEn_Pos (0) /*!< PWM_T::DACTRGEN: ZTEn Position */
sahilmgandhi 18:6a4db94011d3 8616 #define PWM_DACTRGEN_ZTEn_Msk (0x3ful << PWM_DACTRGEN_ZTEn_Pos) /*!< PWM_T::DACTRGEN: ZTEn Mask */
sahilmgandhi 18:6a4db94011d3 8617
sahilmgandhi 18:6a4db94011d3 8618 #define PWM_DACTRGEN_ZTE0_Pos (0) /*!< PWM_T::DACTRGEN: ZTE0 Position */
sahilmgandhi 18:6a4db94011d3 8619 #define PWM_DACTRGEN_ZTE0_Msk (0x1ul << PWM_DACTRGEN_ZTE0_Pos) /*!< PWM_T::DACTRGEN: ZTE0 Mask */
sahilmgandhi 18:6a4db94011d3 8620
sahilmgandhi 18:6a4db94011d3 8621 #define PWM_DACTRGEN_ZTE1_Pos (1) /*!< PWM_T::DACTRGEN: ZTE1 Position */
sahilmgandhi 18:6a4db94011d3 8622 #define PWM_DACTRGEN_ZTE1_Msk (0x1ul << PWM_DACTRGEN_ZTE1_Pos) /*!< PWM_T::DACTRGEN: ZTE1 Mask */
sahilmgandhi 18:6a4db94011d3 8623
sahilmgandhi 18:6a4db94011d3 8624 #define PWM_DACTRGEN_ZTE2_Pos (2) /*!< PWM_T::DACTRGEN: ZTE2 Position */
sahilmgandhi 18:6a4db94011d3 8625 #define PWM_DACTRGEN_ZTE2_Msk (0x1ul << PWM_DACTRGEN_ZTE2_Pos) /*!< PWM_T::DACTRGEN: ZTE2 Mask */
sahilmgandhi 18:6a4db94011d3 8626
sahilmgandhi 18:6a4db94011d3 8627 #define PWM_DACTRGEN_ZTE3_Pos (3) /*!< PWM_T::DACTRGEN: ZTE3 Position */
sahilmgandhi 18:6a4db94011d3 8628 #define PWM_DACTRGEN_ZTE3_Msk (0x1ul << PWM_DACTRGEN_ZTE3_Pos) /*!< PWM_T::DACTRGEN: ZTE3 Mask */
sahilmgandhi 18:6a4db94011d3 8629
sahilmgandhi 18:6a4db94011d3 8630 #define PWM_DACTRGEN_ZTE4_Pos (4) /*!< PWM_T::DACTRGEN: ZTE4 Position */
sahilmgandhi 18:6a4db94011d3 8631 #define PWM_DACTRGEN_ZTE4_Msk (0x1ul << PWM_DACTRGEN_ZTE4_Pos) /*!< PWM_T::DACTRGEN: ZTE4 Mask */
sahilmgandhi 18:6a4db94011d3 8632
sahilmgandhi 18:6a4db94011d3 8633 #define PWM_DACTRGEN_ZTE5_Pos (5) /*!< PWM_T::DACTRGEN: ZTE5 Position */
sahilmgandhi 18:6a4db94011d3 8634 #define PWM_DACTRGEN_ZTE5_Msk (0x1ul << PWM_DACTRGEN_ZTE5_Pos) /*!< PWM_T::DACTRGEN: ZTE5 Mask */
sahilmgandhi 18:6a4db94011d3 8635
sahilmgandhi 18:6a4db94011d3 8636 #define PWM_DACTRGEN_PTEn_Pos (8) /*!< PWM_T::DACTRGEN: PTEn Position */
sahilmgandhi 18:6a4db94011d3 8637 #define PWM_DACTRGEN_PTEn_Msk (0x3ful << PWM_DACTRGEN_PTEn_Pos) /*!< PWM_T::DACTRGEN: PTEn Mask */
sahilmgandhi 18:6a4db94011d3 8638
sahilmgandhi 18:6a4db94011d3 8639 #define PWM_DACTRGEN_PTE0_Pos (8) /*!< PWM_T::DACTRGEN: PTE0 Position */
sahilmgandhi 18:6a4db94011d3 8640 #define PWM_DACTRGEN_PTE0_Msk (0x1ul << PWM_DACTRGEN_PTE0_Pos) /*!< PWM_T::DACTRGEN: PTE0 Mask */
sahilmgandhi 18:6a4db94011d3 8641
sahilmgandhi 18:6a4db94011d3 8642 #define PWM_DACTRGEN_PTE1_Pos (9) /*!< PWM_T::DACTRGEN: PTE1 Position */
sahilmgandhi 18:6a4db94011d3 8643 #define PWM_DACTRGEN_PTE1_Msk (0x1ul << PWM_DACTRGEN_PTE1_Pos) /*!< PWM_T::DACTRGEN: PTE1 Mask */
sahilmgandhi 18:6a4db94011d3 8644
sahilmgandhi 18:6a4db94011d3 8645 #define PWM_DACTRGEN_PTE2_Pos (10) /*!< PWM_T::DACTRGEN: PTE2 Position */
sahilmgandhi 18:6a4db94011d3 8646 #define PWM_DACTRGEN_PTE2_Msk (0x1ul << PWM_DACTRGEN_PTE2_Pos) /*!< PWM_T::DACTRGEN: PTE2 Mask */
sahilmgandhi 18:6a4db94011d3 8647
sahilmgandhi 18:6a4db94011d3 8648 #define PWM_DACTRGEN_PTE3_Pos (11) /*!< PWM_T::DACTRGEN: PTE3 Position */
sahilmgandhi 18:6a4db94011d3 8649 #define PWM_DACTRGEN_PTE3_Msk (0x1ul << PWM_DACTRGEN_PTE3_Pos) /*!< PWM_T::DACTRGEN: PTE3 Mask */
sahilmgandhi 18:6a4db94011d3 8650
sahilmgandhi 18:6a4db94011d3 8651 #define PWM_DACTRGEN_PTE4_Pos (12) /*!< PWM_T::DACTRGEN: PTE4 Position */
sahilmgandhi 18:6a4db94011d3 8652 #define PWM_DACTRGEN_PTE4_Msk (0x1ul << PWM_DACTRGEN_PTE4_Pos) /*!< PWM_T::DACTRGEN: PTE4 Mask */
sahilmgandhi 18:6a4db94011d3 8653
sahilmgandhi 18:6a4db94011d3 8654 #define PWM_DACTRGEN_PTE5_Pos (13) /*!< PWM_T::DACTRGEN: PTE5 Position */
sahilmgandhi 18:6a4db94011d3 8655 #define PWM_DACTRGEN_PTE5_Msk (0x1ul << PWM_DACTRGEN_PTE5_Pos) /*!< PWM_T::DACTRGEN: PTE5 Mask */
sahilmgandhi 18:6a4db94011d3 8656
sahilmgandhi 18:6a4db94011d3 8657 #define PWM_DACTRGEN_CUTRGEn_Pos (16) /*!< PWM_T::DACTRGEN: CUTRGEn Position */
sahilmgandhi 18:6a4db94011d3 8658 #define PWM_DACTRGEN_CUTRGEn_Msk (0x3ful << PWM_DACTRGEN_CUTRGEn_Pos) /*!< PWM_T::DACTRGEN: CUTRGEn Mask */
sahilmgandhi 18:6a4db94011d3 8659
sahilmgandhi 18:6a4db94011d3 8660 #define PWM_DACTRGEN_CUTRGE0_Pos (16) /*!< PWM_T::DACTRGEN: CUTRGE0 Position */
sahilmgandhi 18:6a4db94011d3 8661 #define PWM_DACTRGEN_CUTRGE0_Msk (0x1ul << PWM_DACTRGEN_CUTRGE0_Pos) /*!< PWM_T::DACTRGEN: CUTRGE0 Mask */
sahilmgandhi 18:6a4db94011d3 8662
sahilmgandhi 18:6a4db94011d3 8663 #define PWM_DACTRGEN_CUTRGE1_Pos (17) /*!< PWM_T::DACTRGEN: CUTRGE1 Position */
sahilmgandhi 18:6a4db94011d3 8664 #define PWM_DACTRGEN_CUTRGE1_Msk (0x1ul << PWM_DACTRGEN_CUTRGE1_Pos) /*!< PWM_T::DACTRGEN: CUTRGE1 Mask */
sahilmgandhi 18:6a4db94011d3 8665
sahilmgandhi 18:6a4db94011d3 8666 #define PWM_DACTRGEN_CUTRGE2_Pos (18) /*!< PWM_T::DACTRGEN: CUTRGE2 Position */
sahilmgandhi 18:6a4db94011d3 8667 #define PWM_DACTRGEN_CUTRGE2_Msk (0x1ul << PWM_DACTRGEN_CUTRGE2_Pos) /*!< PWM_T::DACTRGEN: CUTRGE2 Mask */
sahilmgandhi 18:6a4db94011d3 8668
sahilmgandhi 18:6a4db94011d3 8669 #define PWM_DACTRGEN_CUTRGE3_Pos (19) /*!< PWM_T::DACTRGEN: CUTRGE3 Position */
sahilmgandhi 18:6a4db94011d3 8670 #define PWM_DACTRGEN_CUTRGE3_Msk (0x1ul << PWM_DACTRGEN_CUTRGE3_Pos) /*!< PWM_T::DACTRGEN: CUTRGE3 Mask */
sahilmgandhi 18:6a4db94011d3 8671
sahilmgandhi 18:6a4db94011d3 8672 #define PWM_DACTRGEN_CUTRGE4_Pos (20) /*!< PWM_T::DACTRGEN: CUTRGE4 Position */
sahilmgandhi 18:6a4db94011d3 8673 #define PWM_DACTRGEN_CUTRGE4_Msk (0x1ul << PWM_DACTRGEN_CUTRGE4_Pos) /*!< PWM_T::DACTRGEN: CUTRGE4 Mask */
sahilmgandhi 18:6a4db94011d3 8674
sahilmgandhi 18:6a4db94011d3 8675 #define PWM_DACTRGEN_CUTRGE5_Pos (21) /*!< PWM_T::DACTRGEN: CUTRGE5 Position */
sahilmgandhi 18:6a4db94011d3 8676 #define PWM_DACTRGEN_CUTRGE5_Msk (0x1ul << PWM_DACTRGEN_CUTRGE5_Pos) /*!< PWM_T::DACTRGEN: CUTRGE5 Mask */
sahilmgandhi 18:6a4db94011d3 8677
sahilmgandhi 18:6a4db94011d3 8678 #define PWM_DACTRGEN_CDTRGEn_Pos (24) /*!< PWM_T::DACTRGEN: CDTRGEn Position */
sahilmgandhi 18:6a4db94011d3 8679 #define PWM_DACTRGEN_CDTRGEn_Msk (0x3ful << PWM_DACTRGEN_CDTRGEn_Pos) /*!< PWM_T::DACTRGEN: CDTRGEn Mask */
sahilmgandhi 18:6a4db94011d3 8680
sahilmgandhi 18:6a4db94011d3 8681 #define PWM_DACTRGEN_CDTRGE0_Pos (24) /*!< PWM_T::DACTRGEN: CDTRGE0 Position */
sahilmgandhi 18:6a4db94011d3 8682 #define PWM_DACTRGEN_CDTRGE0_Msk (0x1ul << PWM_DACTRGEN_CDTRGE0_Pos) /*!< PWM_T::DACTRGEN: CDTRGE0 Mask */
sahilmgandhi 18:6a4db94011d3 8683
sahilmgandhi 18:6a4db94011d3 8684 #define PWM_DACTRGEN_CDTRGE1_Pos (25) /*!< PWM_T::DACTRGEN: CDTRGE1 Position */
sahilmgandhi 18:6a4db94011d3 8685 #define PWM_DACTRGEN_CDTRGE1_Msk (0x1ul << PWM_DACTRGEN_CDTRGE1_Pos) /*!< PWM_T::DACTRGEN: CDTRGE1 Mask */
sahilmgandhi 18:6a4db94011d3 8686
sahilmgandhi 18:6a4db94011d3 8687 #define PWM_DACTRGEN_CDTRGE2_Pos (26) /*!< PWM_T::DACTRGEN: CDTRGE2 Position */
sahilmgandhi 18:6a4db94011d3 8688 #define PWM_DACTRGEN_CDTRGE2_Msk (0x1ul << PWM_DACTRGEN_CDTRGE2_Pos) /*!< PWM_T::DACTRGEN: CDTRGE2 Mask */
sahilmgandhi 18:6a4db94011d3 8689
sahilmgandhi 18:6a4db94011d3 8690 #define PWM_DACTRGEN_CDTRGE3_Pos (27) /*!< PWM_T::DACTRGEN: CDTRGE3 Position */
sahilmgandhi 18:6a4db94011d3 8691 #define PWM_DACTRGEN_CDTRGE3_Msk (0x1ul << PWM_DACTRGEN_CDTRGE3_Pos) /*!< PWM_T::DACTRGEN: CDTRGE3 Mask */
sahilmgandhi 18:6a4db94011d3 8692
sahilmgandhi 18:6a4db94011d3 8693 #define PWM_DACTRGEN_CDTRGE4_Pos (28) /*!< PWM_T::DACTRGEN: CDTRGE4 Position */
sahilmgandhi 18:6a4db94011d3 8694 #define PWM_DACTRGEN_CDTRGE4_Msk (0x1ul << PWM_DACTRGEN_CDTRGE4_Pos) /*!< PWM_T::DACTRGEN: CDTRGE4 Mask */
sahilmgandhi 18:6a4db94011d3 8695
sahilmgandhi 18:6a4db94011d3 8696 #define PWM_DACTRGEN_CDTRGE5_Pos (29) /*!< PWM_T::DACTRGEN: CDTRGE5 Position */
sahilmgandhi 18:6a4db94011d3 8697 #define PWM_DACTRGEN_CDTRGE5_Msk (0x1ul << PWM_DACTRGEN_CDTRGE5_Pos) /*!< PWM_T::DACTRGEN: CDTRGE5 Mask */
sahilmgandhi 18:6a4db94011d3 8698
sahilmgandhi 18:6a4db94011d3 8699 #define PWM_EADCTS0_TRGSEL0_Pos (0) /*!< PWM_T::EADCTS0: TRGSEL0 Position */
sahilmgandhi 18:6a4db94011d3 8700 #define PWM_EADCTS0_TRGSEL0_Msk (0xful << PWM_EADCTS0_TRGSEL0_Pos) /*!< PWM_T::EADCTS0: TRGSEL0 Mask */
sahilmgandhi 18:6a4db94011d3 8701
sahilmgandhi 18:6a4db94011d3 8702 #define PWM_EADCTS0_TRGEN0_Pos (7) /*!< PWM_T::EADCTS0: TRGEN0 Position */
sahilmgandhi 18:6a4db94011d3 8703 #define PWM_EADCTS0_TRGEN0_Msk (0x1ul << PWM_EADCTS0_TRGEN0_Pos) /*!< PWM_T::EADCTS0: TRGEN0 Mask */
sahilmgandhi 18:6a4db94011d3 8704
sahilmgandhi 18:6a4db94011d3 8705 #define PWM_EADCTS0_TRGSEL1_Pos (8) /*!< PWM_T::EADCTS0: TRGSEL1 Position */
sahilmgandhi 18:6a4db94011d3 8706 #define PWM_EADCTS0_TRGSEL1_Msk (0xful << PWM_EADCTS0_TRGSEL1_Pos) /*!< PWM_T::EADCTS0: TRGSEL1 Mask */
sahilmgandhi 18:6a4db94011d3 8707
sahilmgandhi 18:6a4db94011d3 8708 #define PWM_EADCTS0_TRGEN1_Pos (15) /*!< PWM_T::EADCTS0: TRGEN1 Position */
sahilmgandhi 18:6a4db94011d3 8709 #define PWM_EADCTS0_TRGEN1_Msk (0x1ul << PWM_EADCTS0_TRGEN1_Pos) /*!< PWM_T::EADCTS0: TRGEN1 Mask */
sahilmgandhi 18:6a4db94011d3 8710
sahilmgandhi 18:6a4db94011d3 8711 #define PWM_EADCTS0_TRGSEL2_Pos (16) /*!< PWM_T::EADCTS0: TRGSEL2 Position */
sahilmgandhi 18:6a4db94011d3 8712 #define PWM_EADCTS0_TRGSEL2_Msk (0xful << PWM_EADCTS0_TRGSEL2_Pos) /*!< PWM_T::EADCTS0: TRGSEL2 Mask */
sahilmgandhi 18:6a4db94011d3 8713
sahilmgandhi 18:6a4db94011d3 8714 #define PWM_EADCTS0_TRGEN2_Pos (23) /*!< PWM_T::EADCTS0: TRGEN2 Position */
sahilmgandhi 18:6a4db94011d3 8715 #define PWM_EADCTS0_TRGEN2_Msk (0x1ul << PWM_EADCTS0_TRGEN2_Pos) /*!< PWM_T::EADCTS0: TRGEN2 Mask */
sahilmgandhi 18:6a4db94011d3 8716
sahilmgandhi 18:6a4db94011d3 8717 #define PWM_EADCTS0_TRGSEL3_Pos (24) /*!< PWM_T::EADCTS0: TRGSEL3 Position */
sahilmgandhi 18:6a4db94011d3 8718 #define PWM_EADCTS0_TRGSEL3_Msk (0xful << PWM_EADCTS0_TRGSEL3_Pos) /*!< PWM_T::EADCTS0: TRGSEL3 Mask */
sahilmgandhi 18:6a4db94011d3 8719
sahilmgandhi 18:6a4db94011d3 8720 #define PWM_EADCTS0_TRGEN3_Pos (31) /*!< PWM_T::EADCTS0: TRGEN3 Position */
sahilmgandhi 18:6a4db94011d3 8721 #define PWM_EADCTS0_TRGEN3_Msk (0x1ul << PWM_EADCTS0_TRGEN3_Pos) /*!< PWM_T::EADCTS0: TRGEN3 Mask */
sahilmgandhi 18:6a4db94011d3 8722
sahilmgandhi 18:6a4db94011d3 8723 #define PWM_EADCTS1_TRGSEL4_Pos (0) /*!< PWM_T::EADCTS1: TRGSEL4 Position */
sahilmgandhi 18:6a4db94011d3 8724 #define PWM_EADCTS1_TRGSEL4_Msk (0xful << PWM_EADCTS1_TRGSEL4_Pos) /*!< PWM_T::EADCTS1: TRGSEL4 Mask */
sahilmgandhi 18:6a4db94011d3 8725
sahilmgandhi 18:6a4db94011d3 8726 #define PWM_EADCTS1_TRGEN4_Pos (7) /*!< PWM_T::EADCTS1: TRGEN4 Position */
sahilmgandhi 18:6a4db94011d3 8727 #define PWM_EADCTS1_TRGEN4_Msk (0x1ul << PWM_EADCTS1_TRGEN4_Pos) /*!< PWM_T::EADCTS1: TRGEN4 Mask */
sahilmgandhi 18:6a4db94011d3 8728
sahilmgandhi 18:6a4db94011d3 8729 #define PWM_EADCTS1_TRGSEL5_Pos (8) /*!< PWM_T::EADCTS1: TRGSEL5 Position */
sahilmgandhi 18:6a4db94011d3 8730 #define PWM_EADCTS1_TRGSEL5_Msk (0xful << PWM_EADCTS1_TRGSEL5_Pos) /*!< PWM_T::EADCTS1: TRGSEL5 Mask */
sahilmgandhi 18:6a4db94011d3 8731
sahilmgandhi 18:6a4db94011d3 8732 #define PWM_EADCTS1_TRGEN5_Pos (15) /*!< PWM_T::EADCTS1: TRGEN5 Position */
sahilmgandhi 18:6a4db94011d3 8733 #define PWM_EADCTS1_TRGEN5_Msk (0x1ul << PWM_EADCTS1_TRGEN5_Pos) /*!< PWM_T::EADCTS1: TRGEN5 Mask */
sahilmgandhi 18:6a4db94011d3 8734
sahilmgandhi 18:6a4db94011d3 8735 #define PWM_FTCMPDAT0_1_FTCMP_Pos (0) /*!< PWM_T::FTCMPDAT0_1: FTCMP Position */
sahilmgandhi 18:6a4db94011d3 8736 #define PWM_FTCMPDAT0_1_FTCMP_Msk (0xfffful << PWM_FTCMPDAT0_1_FTCMP_Pos) /*!< PWM_T::FTCMPDAT0_1: FTCMP Mask */
sahilmgandhi 18:6a4db94011d3 8737
sahilmgandhi 18:6a4db94011d3 8738 #define PWM_FTCMPDAT2_3_FTCMP_Pos (0) /*!< PWM_T::FTCMPDAT2_3: FTCMP Position */
sahilmgandhi 18:6a4db94011d3 8739 #define PWM_FTCMPDAT2_3_FTCMP_Msk (0xfffful << PWM_FTCMPDAT2_3_FTCMP_Pos) /*!< PWM_T::FTCMPDAT2_3: FTCMP Mask */
sahilmgandhi 18:6a4db94011d3 8740
sahilmgandhi 18:6a4db94011d3 8741 #define PWM_FTCMPDAT4_5_FTCMP_Pos (0) /*!< PWM_T::FTCMPDAT4_5: FTCMP Position */
sahilmgandhi 18:6a4db94011d3 8742 #define PWM_FTCMPDAT4_5_FTCMP_Msk (0xfffful << PWM_FTCMPDAT4_5_FTCMP_Pos) /*!< PWM_T::FTCMPDAT4_5: FTCMP Mask */
sahilmgandhi 18:6a4db94011d3 8743
sahilmgandhi 18:6a4db94011d3 8744 #define PWM_SSCTL_SSENn_Pos (0) /*!< PWM_T::SSCTL: SSENn Position */
sahilmgandhi 18:6a4db94011d3 8745 #define PWM_SSCTL_SSENn_Msk (0x3ful << PWM_SSCTL_SSENn_Pos) /*!< PWM_T::SSCTL: SSENn Mask */
sahilmgandhi 18:6a4db94011d3 8746
sahilmgandhi 18:6a4db94011d3 8747 #define PWM_SSCTL_SSEN0_Pos (0) /*!< PWM_T::SSCTL: SSEN0 Position */
sahilmgandhi 18:6a4db94011d3 8748 #define PWM_SSCTL_SSEN0_Msk (0x1ul << PWM_SSCTL_SSEN0_Pos) /*!< PWM_T::SSCTL: SSEN0 Mask */
sahilmgandhi 18:6a4db94011d3 8749
sahilmgandhi 18:6a4db94011d3 8750 #define PWM_SSCTL_SSEN1_Pos (1) /*!< PWM_T::SSCTL: SSEN1 Position */
sahilmgandhi 18:6a4db94011d3 8751 #define PWM_SSCTL_SSEN1_Msk (0x1ul << PWM_SSCTL_SSEN1_Pos) /*!< PWM_T::SSCTL: SSEN1 Mask */
sahilmgandhi 18:6a4db94011d3 8752
sahilmgandhi 18:6a4db94011d3 8753 #define PWM_SSCTL_SSEN2_Pos (2) /*!< PWM_T::SSCTL: SSEN2 Position */
sahilmgandhi 18:6a4db94011d3 8754 #define PWM_SSCTL_SSEN2_Msk (0x1ul << PWM_SSCTL_SSEN2_Pos) /*!< PWM_T::SSCTL: SSEN2 Mask */
sahilmgandhi 18:6a4db94011d3 8755
sahilmgandhi 18:6a4db94011d3 8756 #define PWM_SSCTL_SSEN3_Pos (3) /*!< PWM_T::SSCTL: SSEN3 Position */
sahilmgandhi 18:6a4db94011d3 8757 #define PWM_SSCTL_SSEN3_Msk (0x1ul << PWM_SSCTL_SSEN3_Pos) /*!< PWM_T::SSCTL: SSEN3 Mask */
sahilmgandhi 18:6a4db94011d3 8758
sahilmgandhi 18:6a4db94011d3 8759 #define PWM_SSCTL_SSEN4_Pos (4) /*!< PWM_T::SSCTL: SSEN4 Position */
sahilmgandhi 18:6a4db94011d3 8760 #define PWM_SSCTL_SSEN4_Msk (0x1ul << PWM_SSCTL_SSEN4_Pos) /*!< PWM_T::SSCTL: SSEN4 Mask */
sahilmgandhi 18:6a4db94011d3 8761
sahilmgandhi 18:6a4db94011d3 8762 #define PWM_SSCTL_SSEN5_Pos (5) /*!< PWM_T::SSCTL: SSEN5 Position */
sahilmgandhi 18:6a4db94011d3 8763 #define PWM_SSCTL_SSEN5_Msk (0x1ul << PWM_SSCTL_SSEN5_Pos) /*!< PWM_T::SSCTL: SSEN5 Mask */
sahilmgandhi 18:6a4db94011d3 8764
sahilmgandhi 18:6a4db94011d3 8765 #define PWM_SSTRG_CNTSEN_Pos (0) /*!< PWM_T::SSTRG: CNTSEN Position */
sahilmgandhi 18:6a4db94011d3 8766 #define PWM_SSTRG_CNTSEN_Msk (0x1ul << PWM_SSTRG_CNTSEN_Pos) /*!< PWM_T::SSTRG: CNTSEN Mask */
sahilmgandhi 18:6a4db94011d3 8767
sahilmgandhi 18:6a4db94011d3 8768 #define PWM_STATUS_CNTMAXFn_Pos (0) /*!< PWM_T::STATUS: CNTMAXFn Position */
sahilmgandhi 18:6a4db94011d3 8769 #define PWM_STATUS_CNTMAXFn_Msk (0x3ful << PWM_STATUS_CNTMAXFn_Pos) /*!< PWM_T::STATUS: CNTMAXFn Mask */
sahilmgandhi 18:6a4db94011d3 8770
sahilmgandhi 18:6a4db94011d3 8771 #define PWM_STATUS_CNTMAXF0_Pos (0) /*!< PWM_T::STATUS: CNTMAXF0 Position */
sahilmgandhi 18:6a4db94011d3 8772 #define PWM_STATUS_CNTMAXF0_Msk (0x1ul << PWM_STATUS_CNTMAXF0_Pos) /*!< PWM_T::STATUS: CNTMAXF0 Mask */
sahilmgandhi 18:6a4db94011d3 8773
sahilmgandhi 18:6a4db94011d3 8774 #define PWM_STATUS_CNTMAXF1_Pos (1) /*!< PWM_T::STATUS: CNTMAXF1 Position */
sahilmgandhi 18:6a4db94011d3 8775 #define PWM_STATUS_CNTMAXF1_Msk (0x1ul << PWM_STATUS_CNTMAXF1_Pos) /*!< PWM_T::STATUS: CNTMAXF1 Mask */
sahilmgandhi 18:6a4db94011d3 8776
sahilmgandhi 18:6a4db94011d3 8777 #define PWM_STATUS_CNTMAXF2_Pos (2) /*!< PWM_T::STATUS: CNTMAXF2 Position */
sahilmgandhi 18:6a4db94011d3 8778 #define PWM_STATUS_CNTMAXF2_Msk (0x1ul << PWM_STATUS_CNTMAXF2_Pos) /*!< PWM_T::STATUS: CNTMAXF2 Mask */
sahilmgandhi 18:6a4db94011d3 8779
sahilmgandhi 18:6a4db94011d3 8780 #define PWM_STATUS_CNTMAXF3_Pos (3) /*!< PWM_T::STATUS: CNTMAXF3 Position */
sahilmgandhi 18:6a4db94011d3 8781 #define PWM_STATUS_CNTMAXF3_Msk (0x1ul << PWM_STATUS_CNTMAXF3_Pos) /*!< PWM_T::STATUS: CNTMAXF3 Mask */
sahilmgandhi 18:6a4db94011d3 8782
sahilmgandhi 18:6a4db94011d3 8783 #define PWM_STATUS_CNTMAXF4_Pos (4) /*!< PWM_T::STATUS: CNTMAXF4 Position */
sahilmgandhi 18:6a4db94011d3 8784 #define PWM_STATUS_CNTMAXF4_Msk (0x1ul << PWM_STATUS_CNTMAXF4_Pos) /*!< PWM_T::STATUS: CNTMAXF4 Mask */
sahilmgandhi 18:6a4db94011d3 8785
sahilmgandhi 18:6a4db94011d3 8786 #define PWM_STATUS_CNTMAXF5_Pos (5) /*!< PWM_T::STATUS: CNTMAXF5 Position */
sahilmgandhi 18:6a4db94011d3 8787 #define PWM_STATUS_CNTMAXF5_Msk (0x1ul << PWM_STATUS_CNTMAXF5_Pos) /*!< PWM_T::STATUS: CNTMAXF5 Mask */
sahilmgandhi 18:6a4db94011d3 8788
sahilmgandhi 18:6a4db94011d3 8789 #define PWM_STATUS_SYNCINFn_Pos (8) /*!< PWM_T::STATUS: SYNCINFn Position */
sahilmgandhi 18:6a4db94011d3 8790 #define PWM_STATUS_SYNCINFn_Msk (0x7ul << PWM_STATUS_SYNCINFn_Pos) /*!< PWM_T::STATUS: SYNCINFn Mask */
sahilmgandhi 18:6a4db94011d3 8791
sahilmgandhi 18:6a4db94011d3 8792 #define PWM_STATUS_SYNCINF0_Pos (8) /*!< PWM_T::STATUS: SYNCINF0 Position */
sahilmgandhi 18:6a4db94011d3 8793 #define PWM_STATUS_SYNCINF0_Msk (0x1ul << PWM_STATUS_SYNCINF0_Pos) /*!< PWM_T::STATUS: SYNCINF0 Mask */
sahilmgandhi 18:6a4db94011d3 8794
sahilmgandhi 18:6a4db94011d3 8795 #define PWM_STATUS_SYNCINF2_Pos (9) /*!< PWM_T::STATUS: SYNCINF2 Position */
sahilmgandhi 18:6a4db94011d3 8796 #define PWM_STATUS_SYNCINF2_Msk (0x1ul << PWM_STATUS_SYNCINF2_Pos) /*!< PWM_T::STATUS: SYNCINF2 Mask */
sahilmgandhi 18:6a4db94011d3 8797
sahilmgandhi 18:6a4db94011d3 8798 #define PWM_STATUS_SYNCINF4_Pos (10) /*!< PWM_T::STATUS: SYNCINF4 Position */
sahilmgandhi 18:6a4db94011d3 8799 #define PWM_STATUS_SYNCINF4_Msk (0x1ul << PWM_STATUS_SYNCINF4_Pos) /*!< PWM_T::STATUS: SYNCINF4 Mask */
sahilmgandhi 18:6a4db94011d3 8800
sahilmgandhi 18:6a4db94011d3 8801 #define PWM_STATUS_ADCTRGFn_Pos (16) /*!< PWM_T::STATUS: ADCTRGFn Position */
sahilmgandhi 18:6a4db94011d3 8802 #define PWM_STATUS_ADCTRGFn_Msk (0x3ful << PWM_STATUS_ADCTRGFn_Pos) /*!< PWM_T::STATUS: ADCTRGFn Mask */
sahilmgandhi 18:6a4db94011d3 8803
sahilmgandhi 18:6a4db94011d3 8804 #define PWM_STATUS_ADCTRGF0_Pos (16) /*!< PWM_T::STATUS: ADCTRGF0 Position */
sahilmgandhi 18:6a4db94011d3 8805 #define PWM_STATUS_ADCTRGF0_Msk (0x1ul << PWM_STATUS_ADCTRGF0_Pos) /*!< PWM_T::STATUS: ADCTRGF0 Mask */
sahilmgandhi 18:6a4db94011d3 8806
sahilmgandhi 18:6a4db94011d3 8807 #define PWM_STATUS_ADCTRGF1_Pos (17) /*!< PWM_T::STATUS: ADCTRGF1 Position */
sahilmgandhi 18:6a4db94011d3 8808 #define PWM_STATUS_ADCTRGF1_Msk (0x1ul << PWM_STATUS_ADCTRGF1_Pos) /*!< PWM_T::STATUS: ADCTRGF1 Mask */
sahilmgandhi 18:6a4db94011d3 8809
sahilmgandhi 18:6a4db94011d3 8810 #define PWM_STATUS_ADCTRGF2_Pos (18) /*!< PWM_T::STATUS: ADCTRGF2 Position */
sahilmgandhi 18:6a4db94011d3 8811 #define PWM_STATUS_ADCTRGF2_Msk (0x1ul << PWM_STATUS_ADCTRGF2_Pos) /*!< PWM_T::STATUS: ADCTRGF2 Mask */
sahilmgandhi 18:6a4db94011d3 8812
sahilmgandhi 18:6a4db94011d3 8813 #define PWM_STATUS_ADCTRGF3_Pos (19) /*!< PWM_T::STATUS: ADCTRGF3 Position */
sahilmgandhi 18:6a4db94011d3 8814 #define PWM_STATUS_ADCTRGF3_Msk (0x1ul << PWM_STATUS_ADCTRGF3_Pos) /*!< PWM_T::STATUS: ADCTRGF3 Mask */
sahilmgandhi 18:6a4db94011d3 8815
sahilmgandhi 18:6a4db94011d3 8816 #define PWM_STATUS_ADCTRGF4_Pos (20) /*!< PWM_T::STATUS: ADCTRGF4 Position */
sahilmgandhi 18:6a4db94011d3 8817 #define PWM_STATUS_ADCTRGF4_Msk (0x1ul << PWM_STATUS_ADCTRGF4_Pos) /*!< PWM_T::STATUS: ADCTRGF4 Mask */
sahilmgandhi 18:6a4db94011d3 8818
sahilmgandhi 18:6a4db94011d3 8819 #define PWM_STATUS_ADCTRGF5_Pos (21) /*!< PWM_T::STATUS: ADCTRGF5 Position */
sahilmgandhi 18:6a4db94011d3 8820 #define PWM_STATUS_ADCTRGF5_Msk (0x1ul << PWM_STATUS_ADCTRGF5_Pos) /*!< PWM_T::STATUS: ADCTRGF5 Mask */
sahilmgandhi 18:6a4db94011d3 8821
sahilmgandhi 18:6a4db94011d3 8822 #define PWM_STATUS_DACTRGF_Pos (24) /*!< PWM_T::STATUS: DACTRGF Position */
sahilmgandhi 18:6a4db94011d3 8823 #define PWM_STATUS_DACTRGF_Msk (0x1ul << PWM_STATUS_DACTRGF_Pos) /*!< PWM_T::STATUS: DACTRGF Mask */
sahilmgandhi 18:6a4db94011d3 8824
sahilmgandhi 18:6a4db94011d3 8825 #define PWM_CAPINEN_CAPINENn_Pos (0) /*!< PWM_T::CAPINEN: CAPINENn Position */
sahilmgandhi 18:6a4db94011d3 8826 #define PWM_CAPINEN_CAPINENn_Msk (0x3ful << PWM_CAPINEN_CAPINENn_Pos) /*!< PWM_T::CAPINEN: CAPINENn Mask */
sahilmgandhi 18:6a4db94011d3 8827
sahilmgandhi 18:6a4db94011d3 8828 #define PWM_CAPINEN_CAPINEN0_Pos (0) /*!< PWM_T::CAPINEN: CAPINEN0 Position */
sahilmgandhi 18:6a4db94011d3 8829 #define PWM_CAPINEN_CAPINEN0_Msk (0x1ul << PWM_CAPINEN_CAPINEN0_Pos) /*!< PWM_T::CAPINEN: CAPINEN0 Mask */
sahilmgandhi 18:6a4db94011d3 8830
sahilmgandhi 18:6a4db94011d3 8831 #define PWM_CAPINEN_CAPINEN1_Pos (1) /*!< PWM_T::CAPINEN: CAPINEN1 Position */
sahilmgandhi 18:6a4db94011d3 8832 #define PWM_CAPINEN_CAPINEN1_Msk (0x1ul << PWM_CAPINEN_CAPINEN1_Pos) /*!< PWM_T::CAPINEN: CAPINEN1 Mask */
sahilmgandhi 18:6a4db94011d3 8833
sahilmgandhi 18:6a4db94011d3 8834 #define PWM_CAPINEN_CAPINEN2_Pos (2) /*!< PWM_T::CAPINEN: CAPINEN2 Position */
sahilmgandhi 18:6a4db94011d3 8835 #define PWM_CAPINEN_CAPINEN2_Msk (0x1ul << PWM_CAPINEN_CAPINEN2_Pos) /*!< PWM_T::CAPINEN: CAPINEN2 Mask */
sahilmgandhi 18:6a4db94011d3 8836
sahilmgandhi 18:6a4db94011d3 8837 #define PWM_CAPINEN_CAPINEN3_Pos (3) /*!< PWM_T::CAPINEN: CAPINEN3 Position */
sahilmgandhi 18:6a4db94011d3 8838 #define PWM_CAPINEN_CAPINEN3_Msk (0x1ul << PWM_CAPINEN_CAPINEN3_Pos) /*!< PWM_T::CAPINEN: CAPINEN3 Mask */
sahilmgandhi 18:6a4db94011d3 8839
sahilmgandhi 18:6a4db94011d3 8840 #define PWM_CAPINEN_CAPINEN4_Pos (4) /*!< PWM_T::CAPINEN: CAPINEN4 Position */
sahilmgandhi 18:6a4db94011d3 8841 #define PWM_CAPINEN_CAPINEN4_Msk (0x1ul << PWM_CAPINEN_CAPINEN4_Pos) /*!< PWM_T::CAPINEN: CAPINEN4 Mask */
sahilmgandhi 18:6a4db94011d3 8842
sahilmgandhi 18:6a4db94011d3 8843 #define PWM_CAPINEN_CAPINEN5_Pos (5) /*!< PWM_T::CAPINEN: CAPINEN5 Position */
sahilmgandhi 18:6a4db94011d3 8844 #define PWM_CAPINEN_CAPINEN5_Msk (0x1ul << PWM_CAPINEN_CAPINEN5_Pos) /*!< PWM_T::CAPINEN: CAPINEN5 Mask */
sahilmgandhi 18:6a4db94011d3 8845
sahilmgandhi 18:6a4db94011d3 8846 #define PWM_CAPCTL_CAPENn_Pos (0) /*!< PWM_T::CAPCTL: CAPENn Position */
sahilmgandhi 18:6a4db94011d3 8847 #define PWM_CAPCTL_CAPENn_Msk (0x3ful << PWM_CAPCTL_CAPENn_Pos) /*!< PWM_T::CAPCTL: CAPENn Mask */
sahilmgandhi 18:6a4db94011d3 8848
sahilmgandhi 18:6a4db94011d3 8849 #define PWM_CAPCTL_CAPEN0_Pos (0) /*!< PWM_T::CAPCTL: CAPEN0 Position */
sahilmgandhi 18:6a4db94011d3 8850 #define PWM_CAPCTL_CAPEN0_Msk (0x1ul << PWM_CAPCTL_CAPEN0_Pos) /*!< PWM_T::CAPCTL: CAPEN0 Mask */
sahilmgandhi 18:6a4db94011d3 8851
sahilmgandhi 18:6a4db94011d3 8852 #define PWM_CAPCTL_CAPEN1_Pos (1) /*!< PWM_T::CAPCTL: CAPEN1 Position */
sahilmgandhi 18:6a4db94011d3 8853 #define PWM_CAPCTL_CAPEN1_Msk (0x1ul << PWM_CAPCTL_CAPEN1_Pos) /*!< PWM_T::CAPCTL: CAPEN1 Mask */
sahilmgandhi 18:6a4db94011d3 8854
sahilmgandhi 18:6a4db94011d3 8855 #define PWM_CAPCTL_CAPEN2_Pos (2) /*!< PWM_T::CAPCTL: CAPEN2 Position */
sahilmgandhi 18:6a4db94011d3 8856 #define PWM_CAPCTL_CAPEN2_Msk (0x1ul << PWM_CAPCTL_CAPEN2_Pos) /*!< PWM_T::CAPCTL: CAPEN2 Mask */
sahilmgandhi 18:6a4db94011d3 8857
sahilmgandhi 18:6a4db94011d3 8858 #define PWM_CAPCTL_CAPEN3_Pos (3) /*!< PWM_T::CAPCTL: CAPEN3 Position */
sahilmgandhi 18:6a4db94011d3 8859 #define PWM_CAPCTL_CAPEN3_Msk (0x1ul << PWM_CAPCTL_CAPEN3_Pos) /*!< PWM_T::CAPCTL: CAPEN3 Mask */
sahilmgandhi 18:6a4db94011d3 8860
sahilmgandhi 18:6a4db94011d3 8861 #define PWM_CAPCTL_CAPEN4_Pos (4) /*!< PWM_T::CAPCTL: CAPEN4 Position */
sahilmgandhi 18:6a4db94011d3 8862 #define PWM_CAPCTL_CAPEN4_Msk (0x1ul << PWM_CAPCTL_CAPEN4_Pos) /*!< PWM_T::CAPCTL: CAPEN4 Mask */
sahilmgandhi 18:6a4db94011d3 8863
sahilmgandhi 18:6a4db94011d3 8864 #define PWM_CAPCTL_CAPEN5_Pos (5) /*!< PWM_T::CAPCTL: CAPEN5 Position */
sahilmgandhi 18:6a4db94011d3 8865 #define PWM_CAPCTL_CAPEN5_Msk (0x1ul << PWM_CAPCTL_CAPEN5_Pos) /*!< PWM_T::CAPCTL: CAPEN5 Mask */
sahilmgandhi 18:6a4db94011d3 8866
sahilmgandhi 18:6a4db94011d3 8867 #define PWM_CAPCTL_CAPINVn_Pos (8) /*!< PWM_T::CAPCTL: CAPINVn Position */
sahilmgandhi 18:6a4db94011d3 8868 #define PWM_CAPCTL_CAPINVn_Msk (0x3ful << PWM_CAPCTL_CAPINVn_Pos) /*!< PWM_T::CAPCTL: CAPINVn Mask */
sahilmgandhi 18:6a4db94011d3 8869
sahilmgandhi 18:6a4db94011d3 8870 #define PWM_CAPCTL_CAPINV0_Pos (8) /*!< PWM_T::CAPCTL: CAPINV0 Position */
sahilmgandhi 18:6a4db94011d3 8871 #define PWM_CAPCTL_CAPINV0_Msk (0x1ul << PWM_CAPCTL_CAPINV0_Pos) /*!< PWM_T::CAPCTL: CAPINV0 Mask */
sahilmgandhi 18:6a4db94011d3 8872
sahilmgandhi 18:6a4db94011d3 8873 #define PWM_CAPCTL_CAPINV1_Pos (9) /*!< PWM_T::CAPCTL: CAPINV1 Position */
sahilmgandhi 18:6a4db94011d3 8874 #define PWM_CAPCTL_CAPINV1_Msk (0x1ul << PWM_CAPCTL_CAPINV1_Pos) /*!< PWM_T::CAPCTL: CAPINV1 Mask */
sahilmgandhi 18:6a4db94011d3 8875
sahilmgandhi 18:6a4db94011d3 8876 #define PWM_CAPCTL_CAPINV2_Pos (10) /*!< PWM_T::CAPCTL: CAPINV2 Position */
sahilmgandhi 18:6a4db94011d3 8877 #define PWM_CAPCTL_CAPINV2_Msk (0x1ul << PWM_CAPCTL_CAPINV2_Pos) /*!< PWM_T::CAPCTL: CAPINV2 Mask */
sahilmgandhi 18:6a4db94011d3 8878
sahilmgandhi 18:6a4db94011d3 8879 #define PWM_CAPCTL_CAPINV3_Pos (11) /*!< PWM_T::CAPCTL: CAPINV3 Position */
sahilmgandhi 18:6a4db94011d3 8880 #define PWM_CAPCTL_CAPINV3_Msk (0x1ul << PWM_CAPCTL_CAPINV3_Pos) /*!< PWM_T::CAPCTL: CAPINV3 Mask */
sahilmgandhi 18:6a4db94011d3 8881
sahilmgandhi 18:6a4db94011d3 8882 #define PWM_CAPCTL_CAPINV4_Pos (12) /*!< PWM_T::CAPCTL: CAPINV4 Position */
sahilmgandhi 18:6a4db94011d3 8883 #define PWM_CAPCTL_CAPINV4_Msk (0x1ul << PWM_CAPCTL_CAPINV4_Pos) /*!< PWM_T::CAPCTL: CAPINV4 Mask */
sahilmgandhi 18:6a4db94011d3 8884
sahilmgandhi 18:6a4db94011d3 8885 #define PWM_CAPCTL_CAPINV5_Pos (13) /*!< PWM_T::CAPCTL: CAPINV5 Position */
sahilmgandhi 18:6a4db94011d3 8886 #define PWM_CAPCTL_CAPINV5_Msk (0x1ul << PWM_CAPCTL_CAPINV5_Pos) /*!< PWM_T::CAPCTL: CAPINV5 Mask */
sahilmgandhi 18:6a4db94011d3 8887
sahilmgandhi 18:6a4db94011d3 8888 #define PWM_CAPCTL_RCRLDENn_Pos (16) /*!< PWM_T::CAPCTL: RCRLDENn Position */
sahilmgandhi 18:6a4db94011d3 8889 #define PWM_CAPCTL_RCRLDENn_Msk (0x3ful << PWM_CAPCTL_RCRLDENn_Pos) /*!< PWM_T::CAPCTL: RCRLDENn Mask */
sahilmgandhi 18:6a4db94011d3 8890
sahilmgandhi 18:6a4db94011d3 8891 #define PWM_CAPCTL_RCRLDEN0_Pos (16) /*!< PWM_T::CAPCTL: RCRLDEN0 Position */
sahilmgandhi 18:6a4db94011d3 8892 #define PWM_CAPCTL_RCRLDEN0_Msk (0x1ul << PWM_CAPCTL_RCRLDEN0_Pos) /*!< PWM_T::CAPCTL: RCRLDEN0 Mask */
sahilmgandhi 18:6a4db94011d3 8893
sahilmgandhi 18:6a4db94011d3 8894 #define PWM_CAPCTL_RCRLDEN1_Pos (17) /*!< PWM_T::CAPCTL: RCRLDEN1 Position */
sahilmgandhi 18:6a4db94011d3 8895 #define PWM_CAPCTL_RCRLDEN1_Msk (0x1ul << PWM_CAPCTL_RCRLDEN1_Pos) /*!< PWM_T::CAPCTL: RCRLDEN1 Mask */
sahilmgandhi 18:6a4db94011d3 8896
sahilmgandhi 18:6a4db94011d3 8897 #define PWM_CAPCTL_RCRLDEN2_Pos (18) /*!< PWM_T::CAPCTL: RCRLDEN2 Position */
sahilmgandhi 18:6a4db94011d3 8898 #define PWM_CAPCTL_RCRLDEN2_Msk (0x1ul << PWM_CAPCTL_RCRLDEN2_Pos) /*!< PWM_T::CAPCTL: RCRLDEN2 Mask */
sahilmgandhi 18:6a4db94011d3 8899
sahilmgandhi 18:6a4db94011d3 8900 #define PWM_CAPCTL_RCRLDEN3_Pos (19) /*!< PWM_T::CAPCTL: RCRLDEN3 Position */
sahilmgandhi 18:6a4db94011d3 8901 #define PWM_CAPCTL_RCRLDEN3_Msk (0x1ul << PWM_CAPCTL_RCRLDEN3_Pos) /*!< PWM_T::CAPCTL: RCRLDEN3 Mask */
sahilmgandhi 18:6a4db94011d3 8902
sahilmgandhi 18:6a4db94011d3 8903 #define PWM_CAPCTL_RCRLDEN4_Pos (20) /*!< PWM_T::CAPCTL: RCRLDEN4 Position */
sahilmgandhi 18:6a4db94011d3 8904 #define PWM_CAPCTL_RCRLDEN4_Msk (0x1ul << PWM_CAPCTL_RCRLDEN4_Pos) /*!< PWM_T::CAPCTL: RCRLDEN4 Mask */
sahilmgandhi 18:6a4db94011d3 8905
sahilmgandhi 18:6a4db94011d3 8906 #define PWM_CAPCTL_RCRLDEN5_Pos (21) /*!< PWM_T::CAPCTL: RCRLDEN5 Position */
sahilmgandhi 18:6a4db94011d3 8907 #define PWM_CAPCTL_RCRLDEN5_Msk (0x1ul << PWM_CAPCTL_RCRLDEN5_Pos) /*!< PWM_T::CAPCTL: RCRLDEN5 Mask */
sahilmgandhi 18:6a4db94011d3 8908
sahilmgandhi 18:6a4db94011d3 8909 #define PWM_CAPCTL_FCRLDENn_Pos (24) /*!< PWM_T::CAPCTL: FCRLDENn Position */
sahilmgandhi 18:6a4db94011d3 8910 #define PWM_CAPCTL_FCRLDENn_Msk (0x3ful << PWM_CAPCTL_FCRLDENn_Pos) /*!< PWM_T::CAPCTL: FCRLDENn Mask */
sahilmgandhi 18:6a4db94011d3 8911
sahilmgandhi 18:6a4db94011d3 8912 #define PWM_CAPCTL_FCRLDEN0_Pos (24) /*!< PWM_T::CAPCTL: FCRLDEN0 Position */
sahilmgandhi 18:6a4db94011d3 8913 #define PWM_CAPCTL_FCRLDEN0_Msk (0x1ul << PWM_CAPCTL_FCRLDEN0_Pos) /*!< PWM_T::CAPCTL: FCRLDEN0 Mask */
sahilmgandhi 18:6a4db94011d3 8914
sahilmgandhi 18:6a4db94011d3 8915 #define PWM_CAPCTL_FCRLDEN1_Pos (25) /*!< PWM_T::CAPCTL: FCRLDEN1 Position */
sahilmgandhi 18:6a4db94011d3 8916 #define PWM_CAPCTL_FCRLDEN1_Msk (0x1ul << PWM_CAPCTL_FCRLDEN1_Pos) /*!< PWM_T::CAPCTL: FCRLDEN1 Mask */
sahilmgandhi 18:6a4db94011d3 8917
sahilmgandhi 18:6a4db94011d3 8918 #define PWM_CAPCTL_FCRLDEN2_Pos (26) /*!< PWM_T::CAPCTL: FCRLDEN2 Position */
sahilmgandhi 18:6a4db94011d3 8919 #define PWM_CAPCTL_FCRLDEN2_Msk (0x1ul << PWM_CAPCTL_FCRLDEN2_Pos) /*!< PWM_T::CAPCTL: FCRLDEN2 Mask */
sahilmgandhi 18:6a4db94011d3 8920
sahilmgandhi 18:6a4db94011d3 8921 #define PWM_CAPCTL_FCRLDEN3_Pos (27) /*!< PWM_T::CAPCTL: FCRLDEN3 Position */
sahilmgandhi 18:6a4db94011d3 8922 #define PWM_CAPCTL_FCRLDEN3_Msk (0x1ul << PWM_CAPCTL_FCRLDEN3_Pos) /*!< PWM_T::CAPCTL: FCRLDEN3 Mask */
sahilmgandhi 18:6a4db94011d3 8923
sahilmgandhi 18:6a4db94011d3 8924 #define PWM_CAPCTL_FCRLDEN4_Pos (28) /*!< PWM_T::CAPCTL: FCRLDEN4 Position */
sahilmgandhi 18:6a4db94011d3 8925 #define PWM_CAPCTL_FCRLDEN4_Msk (0x1ul << PWM_CAPCTL_FCRLDEN4_Pos) /*!< PWM_T::CAPCTL: FCRLDEN4 Mask */
sahilmgandhi 18:6a4db94011d3 8926
sahilmgandhi 18:6a4db94011d3 8927 #define PWM_CAPCTL_FCRLDEN5_Pos (29) /*!< PWM_T::CAPCTL: FCRLDEN5 Position */
sahilmgandhi 18:6a4db94011d3 8928 #define PWM_CAPCTL_FCRLDEN5_Msk (0x1ul << PWM_CAPCTL_FCRLDEN5_Pos) /*!< PWM_T::CAPCTL: FCRLDEN5 Mask */
sahilmgandhi 18:6a4db94011d3 8929
sahilmgandhi 18:6a4db94011d3 8930 #define PWM_CAPSTS_CRLIFOVn_Pos (0) /*!< PWM_T::CAPSTS: CRLIFOVn Position */
sahilmgandhi 18:6a4db94011d3 8931 #define PWM_CAPSTS_CRLIFOVn_Msk (0x3ful << PWM_CAPSTS_CRLIFOVn_Pos) /*!< PWM_T::CAPSTS: CRLIFOVn Mask */
sahilmgandhi 18:6a4db94011d3 8932
sahilmgandhi 18:6a4db94011d3 8933 #define PWM_CAPSTS_CRLIFOV0_Pos (0) /*!< PWM_T::CAPSTS: CRLIFOV0 Position */
sahilmgandhi 18:6a4db94011d3 8934 #define PWM_CAPSTS_CRLIFOV0_Msk (0x1ul << PWM_CAPSTS_CRLIFOV0_Pos) /*!< PWM_T::CAPSTS: CRLIFOV0 Mask */
sahilmgandhi 18:6a4db94011d3 8935
sahilmgandhi 18:6a4db94011d3 8936 #define PWM_CAPSTS_CRLIFOV1_Pos (1) /*!< PWM_T::CAPSTS: CRLIFOV1 Position */
sahilmgandhi 18:6a4db94011d3 8937 #define PWM_CAPSTS_CRLIFOV1_Msk (0x1ul << PWM_CAPSTS_CRLIFOV1_Pos) /*!< PWM_T::CAPSTS: CRLIFOV1 Mask */
sahilmgandhi 18:6a4db94011d3 8938
sahilmgandhi 18:6a4db94011d3 8939 #define PWM_CAPSTS_CRLIFOV2_Pos (2) /*!< PWM_T::CAPSTS: CRLIFOV2 Position */
sahilmgandhi 18:6a4db94011d3 8940 #define PWM_CAPSTS_CRLIFOV2_Msk (0x1ul << PWM_CAPSTS_CRLIFOV2_Pos) /*!< PWM_T::CAPSTS: CRLIFOV2 Mask */
sahilmgandhi 18:6a4db94011d3 8941
sahilmgandhi 18:6a4db94011d3 8942 #define PWM_CAPSTS_CRLIFOV3_Pos (3) /*!< PWM_T::CAPSTS: CRLIFOV3 Position */
sahilmgandhi 18:6a4db94011d3 8943 #define PWM_CAPSTS_CRLIFOV3_Msk (0x1ul << PWM_CAPSTS_CRLIFOV3_Pos) /*!< PWM_T::CAPSTS: CRLIFOV3 Mask */
sahilmgandhi 18:6a4db94011d3 8944
sahilmgandhi 18:6a4db94011d3 8945 #define PWM_CAPSTS_CRLIFOV4_Pos (4) /*!< PWM_T::CAPSTS: CRLIFOV4 Position */
sahilmgandhi 18:6a4db94011d3 8946 #define PWM_CAPSTS_CRLIFOV4_Msk (0x1ul << PWM_CAPSTS_CRLIFOV4_Pos) /*!< PWM_T::CAPSTS: CRLIFOV4 Mask */
sahilmgandhi 18:6a4db94011d3 8947
sahilmgandhi 18:6a4db94011d3 8948 #define PWM_CAPSTS_CRLIFOV5_Pos (5) /*!< PWM_T::CAPSTS: CRLIFOV5 Position */
sahilmgandhi 18:6a4db94011d3 8949 #define PWM_CAPSTS_CRLIFOV5_Msk (0x1ul << PWM_CAPSTS_CRLIFOV5_Pos) /*!< PWM_T::CAPSTS: CRLIFOV5 Mask */
sahilmgandhi 18:6a4db94011d3 8950
sahilmgandhi 18:6a4db94011d3 8951 #define PWM_CAPSTS_CFLIFOVn_Pos (8) /*!< PWM_T::CAPSTS: CFLIFOVn Position */
sahilmgandhi 18:6a4db94011d3 8952 #define PWM_CAPSTS_CFLIFOVn_Msk (0x3ful << PWM_CAPSTS_CFLIFOVn_Pos) /*!< PWM_T::CAPSTS: CFLIFOVn Mask */
sahilmgandhi 18:6a4db94011d3 8953
sahilmgandhi 18:6a4db94011d3 8954 #define PWM_CAPSTS_CFLIFOV0_Pos (8) /*!< PWM_T::CAPSTS: CFLIFOV0 Position */
sahilmgandhi 18:6a4db94011d3 8955 #define PWM_CAPSTS_CFLIFOV0_Msk (0x1ul << PWM_CAPSTS_CFLIFOV0_Pos) /*!< PWM_T::CAPSTS: CFLIFOV0 Mask */
sahilmgandhi 18:6a4db94011d3 8956
sahilmgandhi 18:6a4db94011d3 8957 #define PWM_CAPSTS_CFLIFOV1_Pos (9) /*!< PWM_T::CAPSTS: CFLIFOV1 Position */
sahilmgandhi 18:6a4db94011d3 8958 #define PWM_CAPSTS_CFLIFOV1_Msk (0x1ul << PWM_CAPSTS_CFLIFOV1_Pos) /*!< PWM_T::CAPSTS: CFLIFOV1 Mask */
sahilmgandhi 18:6a4db94011d3 8959
sahilmgandhi 18:6a4db94011d3 8960 #define PWM_CAPSTS_CFLIFOV2_Pos (10) /*!< PWM_T::CAPSTS: CFLIFOV2 Position */
sahilmgandhi 18:6a4db94011d3 8961 #define PWM_CAPSTS_CFLIFOV2_Msk (0x1ul << PWM_CAPSTS_CFLIFOV2_Pos) /*!< PWM_T::CAPSTS: CFLIFOV2 Mask */
sahilmgandhi 18:6a4db94011d3 8962
sahilmgandhi 18:6a4db94011d3 8963 #define PWM_CAPSTS_CFLIFOV3_Pos (11) /*!< PWM_T::CAPSTS: CFLIFOV3 Position */
sahilmgandhi 18:6a4db94011d3 8964 #define PWM_CAPSTS_CFLIFOV3_Msk (0x1ul << PWM_CAPSTS_CFLIFOV3_Pos) /*!< PWM_T::CAPSTS: CFLIFOV3 Mask */
sahilmgandhi 18:6a4db94011d3 8965
sahilmgandhi 18:6a4db94011d3 8966 #define PWM_CAPSTS_CFLIFOV4_Pos (12) /*!< PWM_T::CAPSTS: CFLIFOV4 Position */
sahilmgandhi 18:6a4db94011d3 8967 #define PWM_CAPSTS_CFLIFOV4_Msk (0x1ul << PWM_CAPSTS_CFLIFOV4_Pos) /*!< PWM_T::CAPSTS: CFLIFOV4 Mask */
sahilmgandhi 18:6a4db94011d3 8968
sahilmgandhi 18:6a4db94011d3 8969 #define PWM_CAPSTS_CFLIFOV5_Pos (13) /*!< PWM_T::CAPSTS: CFLIFOV5 Position */
sahilmgandhi 18:6a4db94011d3 8970 #define PWM_CAPSTS_CFLIFOV5_Msk (0x1ul << PWM_CAPSTS_CFLIFOV5_Pos) /*!< PWM_T::CAPSTS: CFLIFOV5 Mask */
sahilmgandhi 18:6a4db94011d3 8971
sahilmgandhi 18:6a4db94011d3 8972 #define PWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT0: RCAPDAT Position */
sahilmgandhi 18:6a4db94011d3 8973 #define PWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT0_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT0: RCAPDAT Mask */
sahilmgandhi 18:6a4db94011d3 8974
sahilmgandhi 18:6a4db94011d3 8975 #define PWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT0: FCAPDAT Position */
sahilmgandhi 18:6a4db94011d3 8976 #define PWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT0_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT0: FCAPDAT Mask */
sahilmgandhi 18:6a4db94011d3 8977
sahilmgandhi 18:6a4db94011d3 8978 #define PWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT1: RCAPDAT Position */
sahilmgandhi 18:6a4db94011d3 8979 #define PWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT1_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT1: RCAPDAT Mask */
sahilmgandhi 18:6a4db94011d3 8980
sahilmgandhi 18:6a4db94011d3 8981 #define PWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT1: FCAPDAT Position */
sahilmgandhi 18:6a4db94011d3 8982 #define PWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT1_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT1: FCAPDAT Mask */
sahilmgandhi 18:6a4db94011d3 8983
sahilmgandhi 18:6a4db94011d3 8984 #define PWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT2: RCAPDAT Position */
sahilmgandhi 18:6a4db94011d3 8985 #define PWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT2_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT2: RCAPDAT Mask */
sahilmgandhi 18:6a4db94011d3 8986
sahilmgandhi 18:6a4db94011d3 8987 #define PWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT2: FCAPDAT Position */
sahilmgandhi 18:6a4db94011d3 8988 #define PWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT2_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT2: FCAPDAT Mask */
sahilmgandhi 18:6a4db94011d3 8989
sahilmgandhi 18:6a4db94011d3 8990 #define PWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT3: RCAPDAT Position */
sahilmgandhi 18:6a4db94011d3 8991 #define PWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT3_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT3: RCAPDAT Mask */
sahilmgandhi 18:6a4db94011d3 8992
sahilmgandhi 18:6a4db94011d3 8993 #define PWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT3: FCAPDAT Position */
sahilmgandhi 18:6a4db94011d3 8994 #define PWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT3_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT3: FCAPDAT Mask */
sahilmgandhi 18:6a4db94011d3 8995
sahilmgandhi 18:6a4db94011d3 8996 #define PWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT4: RCAPDAT Position */
sahilmgandhi 18:6a4db94011d3 8997 #define PWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT4_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT4: RCAPDAT Mask */
sahilmgandhi 18:6a4db94011d3 8998
sahilmgandhi 18:6a4db94011d3 8999 #define PWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT4: FCAPDAT Position */
sahilmgandhi 18:6a4db94011d3 9000 #define PWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT4_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT4: FCAPDAT Mask */
sahilmgandhi 18:6a4db94011d3 9001
sahilmgandhi 18:6a4db94011d3 9002 #define PWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT5: RCAPDAT Position */
sahilmgandhi 18:6a4db94011d3 9003 #define PWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT5_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT5: RCAPDAT Mask */
sahilmgandhi 18:6a4db94011d3 9004
sahilmgandhi 18:6a4db94011d3 9005 #define PWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT5: FCAPDAT Position */
sahilmgandhi 18:6a4db94011d3 9006 #define PWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT5_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT5: FCAPDAT Mask */
sahilmgandhi 18:6a4db94011d3 9007
sahilmgandhi 18:6a4db94011d3 9008 #define PWM_PDMACTL_CHEN0_1_Pos (0) /*!< PWM_T::PDMACTL: CHEN0_1 Position */
sahilmgandhi 18:6a4db94011d3 9009 #define PWM_PDMACTL_CHEN0_1_Msk (0x1ul << PWM_PDMACTL_CHEN0_1_Pos) /*!< PWM_T::PDMACTL: CHEN0_1 Mask */
sahilmgandhi 18:6a4db94011d3 9010
sahilmgandhi 18:6a4db94011d3 9011 #define PWM_PDMACTL_CAPMOD0_1_Pos (1) /*!< PWM_T::PDMACTL: CAPMOD0_1 Position */
sahilmgandhi 18:6a4db94011d3 9012 #define PWM_PDMACTL_CAPMOD0_1_Msk (0x3ul << PWM_PDMACTL_CAPMOD0_1_Pos) /*!< PWM_T::PDMACTL: CAPMOD0_1 Mask */
sahilmgandhi 18:6a4db94011d3 9013
sahilmgandhi 18:6a4db94011d3 9014 #define PWM_PDMACTL_CAPORD0_1_Pos (3) /*!< PWM_T::PDMACTL: CAPORD0_1 Position */
sahilmgandhi 18:6a4db94011d3 9015 #define PWM_PDMACTL_CAPORD0_1_Msk (0x1ul << PWM_PDMACTL_CAPORD0_1_Pos) /*!< PWM_T::PDMACTL: CAPORD0_1 Mask */
sahilmgandhi 18:6a4db94011d3 9016
sahilmgandhi 18:6a4db94011d3 9017 #define PWM_PDMACTL_CHSEL0_1_Pos (4) /*!< PWM_T::PDMACTL: CHSEL0_1 Position */
sahilmgandhi 18:6a4db94011d3 9018 #define PWM_PDMACTL_CHSEL0_1_Msk (0x1ul << PWM_PDMACTL_CHSEL0_1_Pos) /*!< PWM_T::PDMACTL: CHSEL0_1 Mask */
sahilmgandhi 18:6a4db94011d3 9019
sahilmgandhi 18:6a4db94011d3 9020 #define PWM_PDMACTL_CHEN2_3_Pos (8) /*!< PWM_T::PDMACTL: CHEN2_3 Position */
sahilmgandhi 18:6a4db94011d3 9021 #define PWM_PDMACTL_CHEN2_3_Msk (0x1ul << PWM_PDMACTL_CHEN2_3_Pos) /*!< PWM_T::PDMACTL: CHEN2_3 Mask */
sahilmgandhi 18:6a4db94011d3 9022
sahilmgandhi 18:6a4db94011d3 9023 #define PWM_PDMACTL_CAPMOD2_3_Pos (9) /*!< PWM_T::PDMACTL: CAPMOD2_3 Position */
sahilmgandhi 18:6a4db94011d3 9024 #define PWM_PDMACTL_CAPMOD2_3_Msk (0x3ul << PWM_PDMACTL_CAPMOD2_3_Pos) /*!< PWM_T::PDMACTL: CAPMOD2_3 Mask */
sahilmgandhi 18:6a4db94011d3 9025
sahilmgandhi 18:6a4db94011d3 9026 #define PWM_PDMACTL_CAPORD2_3_Pos (11) /*!< PWM_T::PDMACTL: CAPORD2_3 Position */
sahilmgandhi 18:6a4db94011d3 9027 #define PWM_PDMACTL_CAPORD2_3_Msk (0x1ul << PWM_PDMACTL_CAPORD2_3_Pos) /*!< PWM_T::PDMACTL: CAPORD2_3 Mask */
sahilmgandhi 18:6a4db94011d3 9028
sahilmgandhi 18:6a4db94011d3 9029 #define PWM_PDMACTL_CHSEL2_3_Pos (12) /*!< PWM_T::PDMACTL: CHSEL2_3 Position */
sahilmgandhi 18:6a4db94011d3 9030 #define PWM_PDMACTL_CHSEL2_3_Msk (0x1ul << PWM_PDMACTL_CHSEL2_3_Pos) /*!< PWM_T::PDMACTL: CHSEL2_3 Mask */
sahilmgandhi 18:6a4db94011d3 9031
sahilmgandhi 18:6a4db94011d3 9032 #define PWM_PDMACTL_CHEN4_5_Pos (16) /*!< PWM_T::PDMACTL: CHEN4_5 Position */
sahilmgandhi 18:6a4db94011d3 9033 #define PWM_PDMACTL_CHEN4_5_Msk (0x1ul << PWM_PDMACTL_CHEN4_5_Pos) /*!< PWM_T::PDMACTL: CHEN4_5 Mask */
sahilmgandhi 18:6a4db94011d3 9034
sahilmgandhi 18:6a4db94011d3 9035 #define PWM_PDMACTL_CAPMOD4_5_Pos (17) /*!< PWM_T::PDMACTL: CAPMOD4_5 Position */
sahilmgandhi 18:6a4db94011d3 9036 #define PWM_PDMACTL_CAPMOD4_5_Msk (0x3ul << PWM_PDMACTL_CAPMOD4_5_Pos) /*!< PWM_T::PDMACTL: CAPMOD4_5 Mask */
sahilmgandhi 18:6a4db94011d3 9037
sahilmgandhi 18:6a4db94011d3 9038 #define PWM_PDMACTL_CAPORD4_5_Pos (19) /*!< PWM_T::PDMACTL: CAPORD4_5 Position */
sahilmgandhi 18:6a4db94011d3 9039 #define PWM_PDMACTL_CAPORD4_5_Msk (0x1ul << PWM_PDMACTL_CAPORD4_5_Pos) /*!< PWM_T::PDMACTL: CAPORD4_5 Mask */
sahilmgandhi 18:6a4db94011d3 9040
sahilmgandhi 18:6a4db94011d3 9041 #define PWM_PDMACTL_CHSEL4_5_Pos (20) /*!< PWM_T::PDMACTL: CHSEL4_5 Position */
sahilmgandhi 18:6a4db94011d3 9042 #define PWM_PDMACTL_CHSEL4_5_Msk (0x1ul << PWM_PDMACTL_CHSEL4_5_Pos) /*!< PWM_T::PDMACTL: CHSEL4_5 Mask */
sahilmgandhi 18:6a4db94011d3 9043
sahilmgandhi 18:6a4db94011d3 9044 #define PWM_PDMACAP0_1_CAPBUF_Pos (0) /*!< PWM_T::PDMACAP0_1: CAPBUF Position */
sahilmgandhi 18:6a4db94011d3 9045 #define PWM_PDMACAP0_1_CAPBUF_Msk (0xfffful << PWM_PDMACAP0_1_CAPBUF_Pos) /*!< PWM_T::PDMACAP0_1: CAPBUF Mask */
sahilmgandhi 18:6a4db94011d3 9046
sahilmgandhi 18:6a4db94011d3 9047 #define PWM_PDMACAP2_3_CAPBUF_Pos (0) /*!< PWM_T::PDMACAP2_3: CAPBUF Position */
sahilmgandhi 18:6a4db94011d3 9048 #define PWM_PDMACAP2_3_CAPBUF_Msk (0xfffful << PWM_PDMACAP2_3_CAPBUF_Pos) /*!< PWM_T::PDMACAP2_3: CAPBUF Mask */
sahilmgandhi 18:6a4db94011d3 9049
sahilmgandhi 18:6a4db94011d3 9050 #define PWM_PDMACAP4_5_CAPBUF_Pos (0) /*!< PWM_T::PDMACAP4_5: CAPBUF Position */
sahilmgandhi 18:6a4db94011d3 9051 #define PWM_PDMACAP4_5_CAPBUF_Msk (0xfffful << PWM_PDMACAP4_5_CAPBUF_Pos) /*!< PWM_T::PDMACAP4_5: CAPBUF Mask */
sahilmgandhi 18:6a4db94011d3 9052
sahilmgandhi 18:6a4db94011d3 9053 #define PWM_CAPIEN_CAPRIENn_Pos (0) /*!< PWM_T::CAPIEN: CAPRIENn Position */
sahilmgandhi 18:6a4db94011d3 9054 #define PWM_CAPIEN_CAPRIENn_Msk (0x3ful << PWM_CAPIEN_CAPRIENn_Pos) /*!< PWM_T::CAPIEN: CAPRIENn Mask */
sahilmgandhi 18:6a4db94011d3 9055
sahilmgandhi 18:6a4db94011d3 9056 #define PWM_CAPIEN_CAPRIEN0_Pos (0) /*!< PWM_T::CAPIEN: CAPRIEN0 Position */
sahilmgandhi 18:6a4db94011d3 9057 #define PWM_CAPIEN_CAPRIEN0_Msk (0x1ul << PWM_CAPIEN_CAPRIEN0_Pos) /*!< PWM_T::CAPIEN: CAPRIEN0 Mask */
sahilmgandhi 18:6a4db94011d3 9058
sahilmgandhi 18:6a4db94011d3 9059 #define PWM_CAPIEN_CAPRIEN1_Pos (1) /*!< PWM_T::CAPIEN: CAPRIEN1 Position */
sahilmgandhi 18:6a4db94011d3 9060 #define PWM_CAPIEN_CAPRIEN1_Msk (0x1ul << PWM_CAPIEN_CAPRIEN1_Pos) /*!< PWM_T::CAPIEN: CAPRIEN1 Mask */
sahilmgandhi 18:6a4db94011d3 9061
sahilmgandhi 18:6a4db94011d3 9062 #define PWM_CAPIEN_CAPRIEN2_Pos (2) /*!< PWM_T::CAPIEN: CAPRIEN2 Position */
sahilmgandhi 18:6a4db94011d3 9063 #define PWM_CAPIEN_CAPRIEN2_Msk (0x1ul << PWM_CAPIEN_CAPRIEN2_Pos) /*!< PWM_T::CAPIEN: CAPRIEN2 Mask */
sahilmgandhi 18:6a4db94011d3 9064
sahilmgandhi 18:6a4db94011d3 9065 #define PWM_CAPIEN_CAPRIEN3_Pos (3) /*!< PWM_T::CAPIEN: CAPRIEN3 Position */
sahilmgandhi 18:6a4db94011d3 9066 #define PWM_CAPIEN_CAPRIEN3_Msk (0x1ul << PWM_CAPIEN_CAPRIEN3_Pos) /*!< PWM_T::CAPIEN: CAPRIEN3 Mask */
sahilmgandhi 18:6a4db94011d3 9067
sahilmgandhi 18:6a4db94011d3 9068 #define PWM_CAPIEN_CAPRIEN4_Pos (4) /*!< PWM_T::CAPIEN: CAPRIEN4 Position */
sahilmgandhi 18:6a4db94011d3 9069 #define PWM_CAPIEN_CAPRIEN4_Msk (0x1ul << PWM_CAPIEN_CAPRIEN4_Pos) /*!< PWM_T::CAPIEN: CAPRIEN4 Mask */
sahilmgandhi 18:6a4db94011d3 9070
sahilmgandhi 18:6a4db94011d3 9071 #define PWM_CAPIEN_CAPRIEN5_Pos (5) /*!< PWM_T::CAPIEN: CAPRIEN5 Position */
sahilmgandhi 18:6a4db94011d3 9072 #define PWM_CAPIEN_CAPRIEN5_Msk (0x1ul << PWM_CAPIEN_CAPRIEN5_Pos) /*!< PWM_T::CAPIEN: CAPRIEN5 Mask */
sahilmgandhi 18:6a4db94011d3 9073
sahilmgandhi 18:6a4db94011d3 9074 #define PWM_CAPIEN_CAPFIENn_Pos (8) /*!< PWM_T::CAPIEN: CAPFIENn Position */
sahilmgandhi 18:6a4db94011d3 9075 #define PWM_CAPIEN_CAPFIENn_Msk (0x3ful << PWM_CAPIEN_CAPFIENn_Pos) /*!< PWM_T::CAPIEN: CAPFIENn Mask */
sahilmgandhi 18:6a4db94011d3 9076
sahilmgandhi 18:6a4db94011d3 9077 #define PWM_CAPIEN_CAPFIEN0_Pos (8) /*!< PWM_T::CAPIEN: CAPFIEN0 Position */
sahilmgandhi 18:6a4db94011d3 9078 #define PWM_CAPIEN_CAPFIEN0_Msk (0x1ul << PWM_CAPIEN_CAPFIEN0_Pos) /*!< PWM_T::CAPIEN: CAPFIEN0 Mask */
sahilmgandhi 18:6a4db94011d3 9079
sahilmgandhi 18:6a4db94011d3 9080 #define PWM_CAPIEN_CAPFIEN1_Pos (9) /*!< PWM_T::CAPIEN: CAPFIEN1 Position */
sahilmgandhi 18:6a4db94011d3 9081 #define PWM_CAPIEN_CAPFIEN1_Msk (0x1ul << PWM_CAPIEN_CAPFIEN1_Pos) /*!< PWM_T::CAPIEN: CAPFIEN1 Mask */
sahilmgandhi 18:6a4db94011d3 9082
sahilmgandhi 18:6a4db94011d3 9083 #define PWM_CAPIEN_CAPFIEN2_Pos (10) /*!< PWM_T::CAPIEN: CAPFIEN2 Position */
sahilmgandhi 18:6a4db94011d3 9084 #define PWM_CAPIEN_CAPFIEN2_Msk (0x1ul << PWM_CAPIEN_CAPFIEN2_Pos) /*!< PWM_T::CAPIEN: CAPFIEN2 Mask */
sahilmgandhi 18:6a4db94011d3 9085
sahilmgandhi 18:6a4db94011d3 9086 #define PWM_CAPIEN_CAPFIEN3_Pos (11) /*!< PWM_T::CAPIEN: CAPFIEN3 Position */
sahilmgandhi 18:6a4db94011d3 9087 #define PWM_CAPIEN_CAPFIEN3_Msk (0x1ul << PWM_CAPIEN_CAPFIEN3_Pos) /*!< PWM_T::CAPIEN: CAPFIEN3 Mask */
sahilmgandhi 18:6a4db94011d3 9088
sahilmgandhi 18:6a4db94011d3 9089 #define PWM_CAPIEN_CAPFIEN4_Pos (12) /*!< PWM_T::CAPIEN: CAPFIEN4 Position */
sahilmgandhi 18:6a4db94011d3 9090 #define PWM_CAPIEN_CAPFIEN4_Msk (0x1ul << PWM_CAPIEN_CAPFIEN4_Pos) /*!< PWM_T::CAPIEN: CAPFIEN4 Mask */
sahilmgandhi 18:6a4db94011d3 9091
sahilmgandhi 18:6a4db94011d3 9092 #define PWM_CAPIEN_CAPFIEN5_Pos (13) /*!< PWM_T::CAPIEN: CAPFIEN5 Position */
sahilmgandhi 18:6a4db94011d3 9093 #define PWM_CAPIEN_CAPFIEN5_Msk (0x1ul << PWM_CAPIEN_CAPFIEN5_Pos) /*!< PWM_T::CAPIEN: CAPFIEN5 Mask */
sahilmgandhi 18:6a4db94011d3 9094
sahilmgandhi 18:6a4db94011d3 9095 #define PWM_CAPIF_CRLIFn_Pos (0) /*!< PWM_T::CAPIF: CRLIFn Position */
sahilmgandhi 18:6a4db94011d3 9096 #define PWM_CAPIF_CRLIFn_Msk (0x3ful << PWM_CAPIF_CRLIFn_Pos) /*!< PWM_T::CAPIF: CRLIFn Mask */
sahilmgandhi 18:6a4db94011d3 9097
sahilmgandhi 18:6a4db94011d3 9098 #define PWM_CAPIF_CRLIF0_Pos (0) /*!< PWM_T::CAPIF: CRLIF0 Position */
sahilmgandhi 18:6a4db94011d3 9099 #define PWM_CAPIF_CRLIF0_Msk (0x1ul << PWM_CAPIF_CRLIF0_Pos) /*!< PWM_T::CAPIF: CRLIF0 Mask */
sahilmgandhi 18:6a4db94011d3 9100
sahilmgandhi 18:6a4db94011d3 9101 #define PWM_CAPIF_CRLIF1_Pos (1) /*!< PWM_T::CAPIF: CRLIF1 Position */
sahilmgandhi 18:6a4db94011d3 9102 #define PWM_CAPIF_CRLIF1_Msk (0x1ul << PWM_CAPIF_CRLIF1_Pos) /*!< PWM_T::CAPIF: CRLIF1 Mask */
sahilmgandhi 18:6a4db94011d3 9103
sahilmgandhi 18:6a4db94011d3 9104 #define PWM_CAPIF_CRLIF2_Pos (2) /*!< PWM_T::CAPIF: CRLIF2 Position */
sahilmgandhi 18:6a4db94011d3 9105 #define PWM_CAPIF_CRLIF2_Msk (0x1ul << PWM_CAPIF_CRLIF2_Pos) /*!< PWM_T::CAPIF: CRLIF2 Mask */
sahilmgandhi 18:6a4db94011d3 9106
sahilmgandhi 18:6a4db94011d3 9107 #define PWM_CAPIF_CRLIF3_Pos (3) /*!< PWM_T::CAPIF: CRLIF3 Position */
sahilmgandhi 18:6a4db94011d3 9108 #define PWM_CAPIF_CRLIF3_Msk (0x1ul << PWM_CAPIF_CRLIF3_Pos) /*!< PWM_T::CAPIF: CRLIF3 Mask */
sahilmgandhi 18:6a4db94011d3 9109
sahilmgandhi 18:6a4db94011d3 9110 #define PWM_CAPIF_CRLIF4_Pos (4) /*!< PWM_T::CAPIF: CRLIF4 Position */
sahilmgandhi 18:6a4db94011d3 9111 #define PWM_CAPIF_CRLIF4_Msk (0x1ul << PWM_CAPIF_CRLIF4_Pos) /*!< PWM_T::CAPIF: CRLIF4 Mask */
sahilmgandhi 18:6a4db94011d3 9112
sahilmgandhi 18:6a4db94011d3 9113 #define PWM_CAPIF_CRLIF5_Pos (5) /*!< PWM_T::CAPIF: CRLIF5 Position */
sahilmgandhi 18:6a4db94011d3 9114 #define PWM_CAPIF_CRLIF5_Msk (0x1ul << PWM_CAPIF_CRLIF5_Pos) /*!< PWM_T::CAPIF: CRLIF5 Mask */
sahilmgandhi 18:6a4db94011d3 9115
sahilmgandhi 18:6a4db94011d3 9116 #define PWM_CAPIF_CFLIFn_Pos (8) /*!< PWM_T::CAPIF: CFLIFn Position */
sahilmgandhi 18:6a4db94011d3 9117 #define PWM_CAPIF_CFLIFn_Msk (0x3ful << PWM_CAPIF_CFLIFn_Pos) /*!< PWM_T::CAPIF: CFLIFn Mask */
sahilmgandhi 18:6a4db94011d3 9118
sahilmgandhi 18:6a4db94011d3 9119 #define PWM_CAPIF_CFLIF0_Pos (8) /*!< PWM_T::CAPIF: CFLIF0 Position */
sahilmgandhi 18:6a4db94011d3 9120 #define PWM_CAPIF_CFLIF0_Msk (0x1ul << PWM_CAPIF_CFLIF0_Pos) /*!< PWM_T::CAPIF: CFLIF0 Mask */
sahilmgandhi 18:6a4db94011d3 9121
sahilmgandhi 18:6a4db94011d3 9122 #define PWM_CAPIF_CFLIF1_Pos (9) /*!< PWM_T::CAPIF: CFLIF1 Position */
sahilmgandhi 18:6a4db94011d3 9123 #define PWM_CAPIF_CFLIF1_Msk (0x1ul << PWM_CAPIF_CFLIF1_Pos) /*!< PWM_T::CAPIF: CFLIF1 Mask */
sahilmgandhi 18:6a4db94011d3 9124
sahilmgandhi 18:6a4db94011d3 9125 #define PWM_CAPIF_CFLIF2_Pos (10) /*!< PWM_T::CAPIF: CFLIF2 Position */
sahilmgandhi 18:6a4db94011d3 9126 #define PWM_CAPIF_CFLIF2_Msk (0x1ul << PWM_CAPIF_CFLIF2_Pos) /*!< PWM_T::CAPIF: CFLIF2 Mask */
sahilmgandhi 18:6a4db94011d3 9127
sahilmgandhi 18:6a4db94011d3 9128 #define PWM_CAPIF_CFLIF3_Pos (11) /*!< PWM_T::CAPIF: CFLIF3 Position */
sahilmgandhi 18:6a4db94011d3 9129 #define PWM_CAPIF_CFLIF3_Msk (0x1ul << PWM_CAPIF_CFLIF3_Pos) /*!< PWM_T::CAPIF: CFLIF3 Mask */
sahilmgandhi 18:6a4db94011d3 9130
sahilmgandhi 18:6a4db94011d3 9131 #define PWM_CAPIF_CFLIF4_Pos (12) /*!< PWM_T::CAPIF: CFLIF4 Position */
sahilmgandhi 18:6a4db94011d3 9132 #define PWM_CAPIF_CFLIF4_Msk (0x1ul << PWM_CAPIF_CFLIF4_Pos) /*!< PWM_T::CAPIF: CFLIF4 Mask */
sahilmgandhi 18:6a4db94011d3 9133
sahilmgandhi 18:6a4db94011d3 9134 #define PWM_CAPIF_CFLIF5_Pos (13) /*!< PWM_T::CAPIF: CFLIF5 Position */
sahilmgandhi 18:6a4db94011d3 9135 #define PWM_CAPIF_CFLIF5_Msk (0x1ul << PWM_CAPIF_CFLIF5_Pos) /*!< PWM_T::CAPIF: CFLIF5 Mask */
sahilmgandhi 18:6a4db94011d3 9136
sahilmgandhi 18:6a4db94011d3 9137 #define PWM_PBUF_PBUF_Pos (0) /*!< PWM_T::PBUF: PBUF Position */
sahilmgandhi 18:6a4db94011d3 9138 #define PWM_PBUF_PBUF_Msk (0xfffful << PWM_PBUF_PBUF_Pos) /*!< PWM_T::PBUF: PBUF Mask */
sahilmgandhi 18:6a4db94011d3 9139
sahilmgandhi 18:6a4db94011d3 9140 #define PWM_CMPBUF_CMPBUF_Pos (0) /*!< PWM_T::CMPBUF: CMPBUF Position */
sahilmgandhi 18:6a4db94011d3 9141 #define PWM_CMPBUF_CMPBUF_Msk (0xfffful << PWM_CMPBUF_CMPBUF_Pos) /*!< PWM_T::CMPBUF: CMPBUF Mask */
sahilmgandhi 18:6a4db94011d3 9142
sahilmgandhi 18:6a4db94011d3 9143 #define PWM_FTCBUF0_1_FTCMPBUF_Pos (0) /*!< PWM_T::FTCBUF0_1: FTCMPBUF Position */
sahilmgandhi 18:6a4db94011d3 9144 #define PWM_FTCBUF0_1_FTCMPBUF_Msk (0xfffful << PWM_FTCBUF0_1_FTCMPBUF_Pos) /*!< PWM_T::FTCBUF0_1: FTCMPBUF Mask */
sahilmgandhi 18:6a4db94011d3 9145
sahilmgandhi 18:6a4db94011d3 9146 #define PWM_FTCBUF2_3_FTCMPBUF_Pos (0) /*!< PWM_T::FTCBUF2_3: FTCMPBUF Position */
sahilmgandhi 18:6a4db94011d3 9147 #define PWM_FTCBUF2_3_FTCMPBUF_Msk (0xfffful << PWM_FTCBUF2_3_FTCMPBUF_Pos) /*!< PWM_T::FTCBUF2_3: FTCMPBUF Mask */
sahilmgandhi 18:6a4db94011d3 9148
sahilmgandhi 18:6a4db94011d3 9149 #define PWM_FTCBUF4_5_FTCMPBUF_Pos (0) /*!< PWM_T::FTCBUF4_5: FTCMPBUF Position */
sahilmgandhi 18:6a4db94011d3 9150 #define PWM_FTCBUF4_5_FTCMPBUF_Msk (0xfffful << PWM_FTCBUF4_5_FTCMPBUF_Pos) /*!< PWM_T::FTCBUF4_5: FTCMPBUF Mask */
sahilmgandhi 18:6a4db94011d3 9151
sahilmgandhi 18:6a4db94011d3 9152 #define PWM_FTCI_FTCMUn_Pos (0) /*!< PWM_T::FTCI: FTCMUn Position */
sahilmgandhi 18:6a4db94011d3 9153 #define PWM_FTCI_FTCMUn_Msk (0x7ul << PWM_FTCI_FTCMUn_Pos) /*!< PWM_T::FTCI: FTCMUn Mask */
sahilmgandhi 18:6a4db94011d3 9154
sahilmgandhi 18:6a4db94011d3 9155 #define PWM_FTCI_FTCMU0_Pos (0) /*!< PWM_T::FTCI: FTCMU0 Position */
sahilmgandhi 18:6a4db94011d3 9156 #define PWM_FTCI_FTCMU0_Msk (0x1ul << PWM_FTCI_FTCMU0_Pos) /*!< PWM_T::FTCI: FTCMU0 Mask */
sahilmgandhi 18:6a4db94011d3 9157
sahilmgandhi 18:6a4db94011d3 9158 #define PWM_FTCI_FTCMU2_Pos (1) /*!< PWM_T::FTCI: FTCMU2 Position */
sahilmgandhi 18:6a4db94011d3 9159 #define PWM_FTCI_FTCMU2_Msk (0x1ul << PWM_FTCI_FTCMU2_Pos) /*!< PWM_T::FTCI: FTCMU2 Mask */
sahilmgandhi 18:6a4db94011d3 9160
sahilmgandhi 18:6a4db94011d3 9161 #define PWM_FTCI_FTCMU4_Pos (2) /*!< PWM_T::FTCI: FTCMU4 Position */
sahilmgandhi 18:6a4db94011d3 9162 #define PWM_FTCI_FTCMU4_Msk (0x1ul << PWM_FTCI_FTCMU4_Pos) /*!< PWM_T::FTCI: FTCMU4 Mask */
sahilmgandhi 18:6a4db94011d3 9163
sahilmgandhi 18:6a4db94011d3 9164 #define PWM_FTCI_FTCMDn_Pos (8) /*!< PWM_T::FTCI: FTCMDn Position */
sahilmgandhi 18:6a4db94011d3 9165 #define PWM_FTCI_FTCMDn_Msk (0x7ul << PWM_FTCI_FTCMDn_Pos) /*!< PWM_T::FTCI: FTCMDn Mask */
sahilmgandhi 18:6a4db94011d3 9166
sahilmgandhi 18:6a4db94011d3 9167 #define PWM_FTCI_FTCMD0_Pos (8) /*!< PWM_T::FTCI: FTCMD0 Position */
sahilmgandhi 18:6a4db94011d3 9168 #define PWM_FTCI_FTCMD0_Msk (0x1ul << PWM_FTCI_FTCMD0_Pos) /*!< PWM_T::FTCI: FTCMD0 Mask */
sahilmgandhi 18:6a4db94011d3 9169
sahilmgandhi 18:6a4db94011d3 9170 #define PWM_FTCI_FTCMD2_Pos (9) /*!< PWM_T::FTCI: FTCMD2 Position */
sahilmgandhi 18:6a4db94011d3 9171 #define PWM_FTCI_FTCMD2_Msk (0x1ul << PWM_FTCI_FTCMD2_Pos) /*!< PWM_T::FTCI: FTCMD2 Mask */
sahilmgandhi 18:6a4db94011d3 9172
sahilmgandhi 18:6a4db94011d3 9173 #define PWM_FTCI_FTCMD4_Pos (10) /*!< PWM_T::FTCI: FTCMD4 Position */
sahilmgandhi 18:6a4db94011d3 9174 #define PWM_FTCI_FTCMD4_Msk (0x1ul << PWM_FTCI_FTCMD4_Pos) /*!< PWM_T::FTCI: FTCMD4 Mask */
sahilmgandhi 18:6a4db94011d3 9175
sahilmgandhi 18:6a4db94011d3 9176 /**@}*/ /* PWM_CONST */
sahilmgandhi 18:6a4db94011d3 9177 /**@}*/ /* end of PWM register group */
sahilmgandhi 18:6a4db94011d3 9178
sahilmgandhi 18:6a4db94011d3 9179
sahilmgandhi 18:6a4db94011d3 9180 /*---------------------- Real Time Clock Controller -------------------------*/
sahilmgandhi 18:6a4db94011d3 9181 /**
sahilmgandhi 18:6a4db94011d3 9182 @addtogroup RTC Real Time Clock Controller(RTC)
sahilmgandhi 18:6a4db94011d3 9183 Memory Mapped Structure for RTC Controller
sahilmgandhi 18:6a4db94011d3 9184 @{ */
sahilmgandhi 18:6a4db94011d3 9185
sahilmgandhi 18:6a4db94011d3 9186
sahilmgandhi 18:6a4db94011d3 9187 typedef struct
sahilmgandhi 18:6a4db94011d3 9188 {
sahilmgandhi 18:6a4db94011d3 9189
sahilmgandhi 18:6a4db94011d3 9190
sahilmgandhi 18:6a4db94011d3 9191
sahilmgandhi 18:6a4db94011d3 9192
sahilmgandhi 18:6a4db94011d3 9193 /**
sahilmgandhi 18:6a4db94011d3 9194 * @var RTC_T::INIT
sahilmgandhi 18:6a4db94011d3 9195 * Offset: 0x00 RTC Initiation Register
sahilmgandhi 18:6a4db94011d3 9196 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 9197 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 9198 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 9199 * |[0] |INIT[0]/ACTIVE|RTC Active Status (Read Only)
sahilmgandhi 18:6a4db94011d3 9200 * | | |0 = RTC is at reset state.
sahilmgandhi 18:6a4db94011d3 9201 * | | |1 = RTC is at normal active state.
sahilmgandhi 18:6a4db94011d3 9202 * |[31:1] |INIT[31:1]|RTC Initiation
sahilmgandhi 18:6a4db94011d3 9203 * | | |When RTC block is powered on, RTC is at reset state.
sahilmgandhi 18:6a4db94011d3 9204 * | | |User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state.
sahilmgandhi 18:6a4db94011d3 9205 * | | |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
sahilmgandhi 18:6a4db94011d3 9206 * | | |The INIT is a write-only field and read value will be always 0.
sahilmgandhi 18:6a4db94011d3 9207 * @var RTC_T::RWEN
sahilmgandhi 18:6a4db94011d3 9208 * Offset: 0x04 RTC Access Enable Register
sahilmgandhi 18:6a4db94011d3 9209 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 9210 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 9211 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 9212 * |[15:0] |RWEN |RTC Register Access Enable Password (Write Only)
sahilmgandhi 18:6a4db94011d3 9213 * | | |Writing 0xA965 to this register will enable RTC access and keep 1024 RTC clock.
sahilmgandhi 18:6a4db94011d3 9214 * |[16] |RWENF |RTC Register Access Enable Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 9215 * | | |0 = RTC register read/write Disabled.
sahilmgandhi 18:6a4db94011d3 9216 * | | |1 = RTC register read/write Enabled.
sahilmgandhi 18:6a4db94011d3 9217 * | | |This bit will be set after RTC_RWEN[15:0] register is load a 0xA965, and be cleared automatically after 1024 RTC clock.
sahilmgandhi 18:6a4db94011d3 9218 * @var RTC_T::FREQADJ
sahilmgandhi 18:6a4db94011d3 9219 * Offset: 0x08 RTC Frequency Compensation Register
sahilmgandhi 18:6a4db94011d3 9220 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 9221 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 9222 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 9223 * |[5:0] |FRACTION |Fraction Part
sahilmgandhi 18:6a4db94011d3 9224 * | | |Formula = (fraction part of detected value) x 60.
sahilmgandhi 18:6a4db94011d3 9225 * | | |Note: Digit in RTC_FREQADJ must be expressed as hexadecimal number.
sahilmgandhi 18:6a4db94011d3 9226 * |[11:8] |INTEGER |Integer Part
sahilmgandhi 18:6a4db94011d3 9227 * @var RTC_T::TIME
sahilmgandhi 18:6a4db94011d3 9228 * Offset: 0x0C Time Loading Register
sahilmgandhi 18:6a4db94011d3 9229 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 9230 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 9231 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 9232 * |[3:0] |SEC |1-Sec Time Digit (0~9)
sahilmgandhi 18:6a4db94011d3 9233 * |[6:4] |TENSEC |10-Sec Time Digit (0~5)
sahilmgandhi 18:6a4db94011d3 9234 * |[11:8] |MIN |1-Min Time Digit (0~9)
sahilmgandhi 18:6a4db94011d3 9235 * |[14:12] |TENMIN |10-Min Time Digit (0~5)
sahilmgandhi 18:6a4db94011d3 9236 * |[19:16] |HR |1-Hour Time Digit (0~9)
sahilmgandhi 18:6a4db94011d3 9237 * |[21:20] |TENHR |10-Hour Time Digit (0~2)
sahilmgandhi 18:6a4db94011d3 9238 * @var RTC_T::CAL
sahilmgandhi 18:6a4db94011d3 9239 * Offset: 0x10 RTC Calendar Loading Register
sahilmgandhi 18:6a4db94011d3 9240 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 9241 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 9242 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 9243 * |[3:0] |DAY |1-Day Calendar Digit (0~9)
sahilmgandhi 18:6a4db94011d3 9244 * |[5:4] |TENDAY |10-Day Calendar Digit (0~3)
sahilmgandhi 18:6a4db94011d3 9245 * |[11:8] |MON |1-Month Calendar Digit (0~9)
sahilmgandhi 18:6a4db94011d3 9246 * |[12] |TENMON |10-Month Calendar Digit (0~1)
sahilmgandhi 18:6a4db94011d3 9247 * |[19:16] |YEAR |1-Year Calendar Digit (0~9)
sahilmgandhi 18:6a4db94011d3 9248 * |[23:20] |TENYEAR |10-Year Calendar Digit (0~9)
sahilmgandhi 18:6a4db94011d3 9249 * @var RTC_T::CLKFMT
sahilmgandhi 18:6a4db94011d3 9250 * Offset: 0x14 Time Scale Selection Register
sahilmgandhi 18:6a4db94011d3 9251 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 9252 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 9253 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 9254 * |[0] |24HEN |24-Hour / 12-Hour Time Scale Selection
sahilmgandhi 18:6a4db94011d3 9255 * | | |Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale
sahilmgandhi 18:6a4db94011d3 9256 * | | |0 = 12-hour time scale with AM and PM indication selected.
sahilmgandhi 18:6a4db94011d3 9257 * | | |1 = 24-hour time scale selected.
sahilmgandhi 18:6a4db94011d3 9258 * @var RTC_T::WEEKDAY
sahilmgandhi 18:6a4db94011d3 9259 * Offset: 0x18 Day of the Week Register
sahilmgandhi 18:6a4db94011d3 9260 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 9261 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 9262 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 9263 * |[2:0] |WEEKDAY |Day Of The Week Register
sahilmgandhi 18:6a4db94011d3 9264 * | | |000 = Sunday.
sahilmgandhi 18:6a4db94011d3 9265 * | | |001 = Monday.
sahilmgandhi 18:6a4db94011d3 9266 * | | |010 = Tuesday.
sahilmgandhi 18:6a4db94011d3 9267 * | | |011 = Wednesday.
sahilmgandhi 18:6a4db94011d3 9268 * | | |100 = Thursday.
sahilmgandhi 18:6a4db94011d3 9269 * | | |101 = Friday.
sahilmgandhi 18:6a4db94011d3 9270 * | | |110 = Saturday.
sahilmgandhi 18:6a4db94011d3 9271 * | | |111 = Reserved.
sahilmgandhi 18:6a4db94011d3 9272 * @var RTC_T::TALM
sahilmgandhi 18:6a4db94011d3 9273 * Offset: 0x1C Time Alarm Register
sahilmgandhi 18:6a4db94011d3 9274 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 9275 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 9276 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 9277 * |[3:0] |SEC |1-Sec Time Digit of Alarm Setting (0~9)
sahilmgandhi 18:6a4db94011d3 9278 * |[6:4] |TENSEC |10-Sec Time Digit of Alarm Setting (0~5)
sahilmgandhi 18:6a4db94011d3 9279 * |[11:8] |MIN |1-Min Time Digit of Alarm Setting (0~9)
sahilmgandhi 18:6a4db94011d3 9280 * |[14:12] |TENMIN |10-Min Time Digit of Alarm Setting (0~5)
sahilmgandhi 18:6a4db94011d3 9281 * |[19:16] |HR |1-Hour Time Digit of Alarm Setting (0~9)
sahilmgandhi 18:6a4db94011d3 9282 * |[21:20] |TENHR |10-Hour Time Digit of Alarm Setting (0~2)
sahilmgandhi 18:6a4db94011d3 9283 * @var RTC_T::CALM
sahilmgandhi 18:6a4db94011d3 9284 * Offset: 0x20 Calendar Alarm Register
sahilmgandhi 18:6a4db94011d3 9285 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 9286 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 9287 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 9288 * |[3:0] |DAY |1-Day Calendar Digit of Alarm Setting (0~9)
sahilmgandhi 18:6a4db94011d3 9289 * |[5:4] |TENDAY |10-Day Calendar Digit of Alarm Setting (0~3)
sahilmgandhi 18:6a4db94011d3 9290 * |[11:8] |MON |1-Month Calendar Digit of Alarm Setting (0~9)
sahilmgandhi 18:6a4db94011d3 9291 * |[12] |TENMON |10-Month Calendar Digit of Alarm Setting (0~1)
sahilmgandhi 18:6a4db94011d3 9292 * |[19:16] |YEAR |1-Year Calendar Digit of Alarm Setting (0~9)
sahilmgandhi 18:6a4db94011d3 9293 * |[23:20] |TENYEAR |10-Year Calendar Digit of Alarm Setting (0~9)
sahilmgandhi 18:6a4db94011d3 9294 * @var RTC_T::LEAPYEAR
sahilmgandhi 18:6a4db94011d3 9295 * Offset: 0x24 RTC Leap Year Indicator Register
sahilmgandhi 18:6a4db94011d3 9296 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 9297 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 9298 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 9299 * |[0] |LEAPYEAR |Leap Year Indication Register (Read Only)
sahilmgandhi 18:6a4db94011d3 9300 * | | |0 = This year is not a leap year.
sahilmgandhi 18:6a4db94011d3 9301 * | | |1 = This year is leap year.
sahilmgandhi 18:6a4db94011d3 9302 * @var RTC_T::INTEN
sahilmgandhi 18:6a4db94011d3 9303 * Offset: 0x28 RTC Interrupt Enable Register
sahilmgandhi 18:6a4db94011d3 9304 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 9305 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 9306 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 9307 * |[0] |ALMIEN |Alarm Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 9308 * | | |0 = RTC Alarm interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 9309 * | | |1 = RTC Alarm interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 9310 * |[1] |TICKIEN |Time Tick Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 9311 * | | |0 = RTC Time Tick interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 9312 * | | |1 = RTC Time Tick interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 9313 * |[2] |SNPDIEN |Snoop Detection Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 9314 * | | |0 = Snoop detected interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 9315 * | | |1 = Snoop detected interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 9316 * @var RTC_T::INTSTS
sahilmgandhi 18:6a4db94011d3 9317 * Offset: 0x2C RTC Interrupt Indicator Register
sahilmgandhi 18:6a4db94011d3 9318 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 9319 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 9320 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 9321 * |[0] |ALMIF |RTC Alarm Interrupt Flag
sahilmgandhi 18:6a4db94011d3 9322 * | | |When RTC time counters RTC_TIME and RTC_CAL match the alarm setting time registers RTC_TALM and RTC_CALM, this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled ALMIEN (RTC_INTEN[0]) is set to 1.
sahilmgandhi 18:6a4db94011d3 9323 * | | |Chip will be waken up if RTC Alarm Interrupt is enabled when chip is at Power-down mode.
sahilmgandhi 18:6a4db94011d3 9324 * | | |0 = Alarm condition is not matched.
sahilmgandhi 18:6a4db94011d3 9325 * | | |1 = Alarm condition is matched.
sahilmgandhi 18:6a4db94011d3 9326 * | | |Note: Write 1 to clear this bit.
sahilmgandhi 18:6a4db94011d3 9327 * |[1] |TICKIF |RTC Time Tick Interrupt Flag
sahilmgandhi 18:6a4db94011d3 9328 * | | |When RTC time tick happened, this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled TICKIEN (RTC_INTEN[1]) is set to 1.
sahilmgandhi 18:6a4db94011d3 9329 * | | |Chip will also be waken up if RTC Tick Interrupt is enabled and this bit is set to 1 when chip is running at Power-down mode.
sahilmgandhi 18:6a4db94011d3 9330 * | | |0 = Tick condition does not occur.
sahilmgandhi 18:6a4db94011d3 9331 * | | |1 = Tick condition occur.
sahilmgandhi 18:6a4db94011d3 9332 * | | |Note: Write 1 to clear to clear this bit.
sahilmgandhi 18:6a4db94011d3 9333 * |[2] |SNPDIF |Snoop Detect Interrupt Flag
sahilmgandhi 18:6a4db94011d3 9334 * | | |When tamper pin transition event is detected, this bit is set to 1 and an interrupt is generated if Snoop Detection Interrupt enabled SNPDIEN (RTC_INTEN[2]) is set to1.
sahilmgandhi 18:6a4db94011d3 9335 * | | |Chip will be waken up from Power-down mode if spare register snooper detect interrupt is enabled.
sahilmgandhi 18:6a4db94011d3 9336 * | | |0 = No snoop event is detected.
sahilmgandhi 18:6a4db94011d3 9337 * | | |1 = Snoop event is detected.
sahilmgandhi 18:6a4db94011d3 9338 * | | |Note: Write 1 to clear this bit.
sahilmgandhi 18:6a4db94011d3 9339 * @var RTC_T::TICK
sahilmgandhi 18:6a4db94011d3 9340 * Offset: 0x30 RTC Time Tick Register
sahilmgandhi 18:6a4db94011d3 9341 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 9342 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 9343 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 9344 * |[2:0] |TICK |Time Tick Register
sahilmgandhi 18:6a4db94011d3 9345 * | | |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request.
sahilmgandhi 18:6a4db94011d3 9346 * | | |000 = Time tick is 1 second.
sahilmgandhi 18:6a4db94011d3 9347 * | | |001 = Time tick is 1/2 second.
sahilmgandhi 18:6a4db94011d3 9348 * | | |010 = Time tick is 1/4 second.
sahilmgandhi 18:6a4db94011d3 9349 * | | |011 = Time tick is 1/8 second.
sahilmgandhi 18:6a4db94011d3 9350 * | | |100 = Time tick is 1/16 second.
sahilmgandhi 18:6a4db94011d3 9351 * | | |101 = Time tick is 1/32 second.
sahilmgandhi 18:6a4db94011d3 9352 * | | |110 = Time tick is 1/64 second.
sahilmgandhi 18:6a4db94011d3 9353 * | | |111 = Time tick is 1/28 second.
sahilmgandhi 18:6a4db94011d3 9354 * | | |Note: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active.
sahilmgandhi 18:6a4db94011d3 9355 * @var RTC_T::TAMSK
sahilmgandhi 18:6a4db94011d3 9356 * Offset: 0x34 Time Alarm Mask Register
sahilmgandhi 18:6a4db94011d3 9357 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 9358 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 9359 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 9360 * |[0] |MSEC |Mask 1-Sec Time Digit of Alarm Setting (0~9)
sahilmgandhi 18:6a4db94011d3 9361 * |[1] |MTENSEC |Mask 10-Sec Time Digit of Alarm Setting (0~5)
sahilmgandhi 18:6a4db94011d3 9362 * |[2] |MMIN |Mask 1-Min Time Digit of Alarm Setting (0~9)
sahilmgandhi 18:6a4db94011d3 9363 * |[3] |MTENMIN |Mask 10-Min Time Digit of Alarm Setting (0~5)
sahilmgandhi 18:6a4db94011d3 9364 * |[4] |MHR |Mask 1-Hour Time Digit of Alarm Setting (0~9)
sahilmgandhi 18:6a4db94011d3 9365 * |[5] |MTENHR |Mask 10-Hour Time Digit of Alarm Setting (0~2)
sahilmgandhi 18:6a4db94011d3 9366 * @var RTC_T::CAMSK
sahilmgandhi 18:6a4db94011d3 9367 * Offset: 0x38 Calendar Alarm Mask Register
sahilmgandhi 18:6a4db94011d3 9368 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 9369 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 9370 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 9371 * |[0] |MDAY |Mask 1-Day Calendar Digit of Alarm Setting (0~9)
sahilmgandhi 18:6a4db94011d3 9372 * |[1] |MTENDAY |Mask 10-Day Calendar Digit of Alarm Setting (0~3)
sahilmgandhi 18:6a4db94011d3 9373 * |[2] |MMON |Mask 1-Month Calendar Digit of Alarm Setting (0~9)
sahilmgandhi 18:6a4db94011d3 9374 * |[3] |MTENMON |Mask 10-Month Calendar Digit of Alarm Setting (0~1)
sahilmgandhi 18:6a4db94011d3 9375 * |[4] |MYEAR |Mask 1-Year Calendar Digit of Alarm Setting (0~9)
sahilmgandhi 18:6a4db94011d3 9376 * |[5] |MTENYEAR |Mask 10-Year Calendar Digit of Alarm Setting (0~9)
sahilmgandhi 18:6a4db94011d3 9377 * @var RTC_T::SPRCTL
sahilmgandhi 18:6a4db94011d3 9378 * Offset: 0x3C RTC Spare Functional Control Register
sahilmgandhi 18:6a4db94011d3 9379 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 9380 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 9381 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 9382 * |[0] |SNPDEN |Snoop Detection Enable Bit
sahilmgandhi 18:6a4db94011d3 9383 * | | |0 = TAMPER pin detection is Disabled.
sahilmgandhi 18:6a4db94011d3 9384 * | | |1 = TAMPER pin detection is Enabled.
sahilmgandhi 18:6a4db94011d3 9385 * |[1] |SNPTYPE0 |Snoop Detection Level
sahilmgandhi 18:6a4db94011d3 9386 * | | |This bit controls TAMPER detect event is high level/rising edge or low level/falling edge.
sahilmgandhi 18:6a4db94011d3 9387 * | | |0 = Low level/Falling edge detection.
sahilmgandhi 18:6a4db94011d3 9388 * | | |1 = High level/Rising edge detection.
sahilmgandhi 18:6a4db94011d3 9389 * |[2] |SPRRWEN |Spare Register Enable Bit
sahilmgandhi 18:6a4db94011d3 9390 * | | |0 = Spare register is Disabled.
sahilmgandhi 18:6a4db94011d3 9391 * | | |1 = Spare register is Enabled.
sahilmgandhi 18:6a4db94011d3 9392 * | | |Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed.
sahilmgandhi 18:6a4db94011d3 9393 * |[3] |SNPTYPE1 |Snoop Detection Mode
sahilmgandhi 18:6a4db94011d3 9394 * | | |This bit controls TAMPER pin is edge or level detection
sahilmgandhi 18:6a4db94011d3 9395 * | | |0 = Level detection.
sahilmgandhi 18:6a4db94011d3 9396 * | | |1 = Edge detection.
sahilmgandhi 18:6a4db94011d3 9397 * |[5] |SPRCSTS |SPR Clear Flag
sahilmgandhi 18:6a4db94011d3 9398 * | | |This bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify snoop event is detected.
sahilmgandhi 18:6a4db94011d3 9399 * | | |0 = Spare register content is not cleared.
sahilmgandhi 18:6a4db94011d3 9400 * | | |1 = Spare register content is cleared.
sahilmgandhi 18:6a4db94011d3 9401 * | | |Writes 1 to clear this bit.
sahilmgandhi 18:6a4db94011d3 9402 * |[7] |SPRRWRDY |SPR Register Ready
sahilmgandhi 18:6a4db94011d3 9403 * | | |This bit indicates if the registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 are ready to be accessed.
sahilmgandhi 18:6a4db94011d3 9404 * | | |After user writing registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19, read this bit to check if these registers are updated done is necessary.
sahilmgandhi 18:6a4db94011d3 9405 * | | |0 = RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 updating is in progress.
sahilmgandhi 18:6a4db94011d3 9406 * | | |1 = RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 are updated done and ready to be accessed.
sahilmgandhi 18:6a4db94011d3 9407 * | | |Note: This bit is read only and any write to it won't take any effect.
sahilmgandhi 18:6a4db94011d3 9408 * @var RTC_T::SPR
sahilmgandhi 18:6a4db94011d3 9409 * Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19
sahilmgandhi 18:6a4db94011d3 9410 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 9411 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 9412 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 9413 * |[31:0] |SPARE |Spare Register
sahilmgandhi 18:6a4db94011d3 9414 * | | |This field is used to store back-up information defined by user.
sahilmgandhi 18:6a4db94011d3 9415 * | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
sahilmgandhi 18:6a4db94011d3 9416 * | | |Before storing back-up information in to RTC_SPRx register, user should write 0xA965 to RTC_RWEN[15:0] to make sure register read/write enable bit REWNF (RTC_RWEN[16]) is enabled.
sahilmgandhi 18:6a4db94011d3 9417 * @var RTC_T::LXTCTL
sahilmgandhi 18:6a4db94011d3 9418 * Offset: 0x100 RTC 32.768 kHz Oscillator Control Register
sahilmgandhi 18:6a4db94011d3 9419 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 9420 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 9421 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 9422 * |[0] |LXTEN |Backup Domain 32K Oscillator Enable Bit
sahilmgandhi 18:6a4db94011d3 9423 * | | |0 = Oscillator is Disabled.
sahilmgandhi 18:6a4db94011d3 9424 * | | |1 = Oscillator is Enabled.
sahilmgandhi 18:6a4db94011d3 9425 * | | |This bit controls 32 kHz oscillator on/off.
sahilmgandhi 18:6a4db94011d3 9426 * | | |User can set either LXTEN in RTC domain or system manager control register CLK_PWRCTL[1] (LXTEN) to enable 32 kHz oscillator.
sahilmgandhi 18:6a4db94011d3 9427 * | | |If this bit is set 1, X32 kHz oscillator keep running after system power is turned off, if this bit is clear to 0, oscillator is turned off when system power is turned off.
sahilmgandhi 18:6a4db94011d3 9428 * |[3:1] |GAIN |Oscillator Gain Option
sahilmgandhi 18:6a4db94011d3 9429 * | | |User can select oscillator gain according to crystal external loading and operating temperature range.
sahilmgandhi 18:6a4db94011d3 9430 * | | |The larger gain value corresponding to stronger driving capability and higher power consumption.
sahilmgandhi 18:6a4db94011d3 9431 * | | |000 = L0 mode.
sahilmgandhi 18:6a4db94011d3 9432 * | | |001 = L1 mode.
sahilmgandhi 18:6a4db94011d3 9433 * | | |010 = L2 mode.
sahilmgandhi 18:6a4db94011d3 9434 * | | |011 = L3 mode.
sahilmgandhi 18:6a4db94011d3 9435 * | | |100 = L4 mode.
sahilmgandhi 18:6a4db94011d3 9436 * | | |101 = L5 mode.
sahilmgandhi 18:6a4db94011d3 9437 * | | |110 = L6 mode.
sahilmgandhi 18:6a4db94011d3 9438 * | | |111 = L7 mode (Default).
sahilmgandhi 18:6a4db94011d3 9439 * @var RTC_T::LXTOCTL
sahilmgandhi 18:6a4db94011d3 9440 * Offset: 0x104 X32KO Pin Control Register
sahilmgandhi 18:6a4db94011d3 9441 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 9442 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 9443 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 9444 * |[1:0] |OPMODE |GPF0 Operation Mode
sahilmgandhi 18:6a4db94011d3 9445 * | | |00 = X32KO (PF.0) is input only mode, without pull-up resistor.
sahilmgandhi 18:6a4db94011d3 9446 * | | |01 = X32KO (PF.0) is output push pull mode.
sahilmgandhi 18:6a4db94011d3 9447 * | | |10 = X32KO (PF.0) is open drain mode.
sahilmgandhi 18:6a4db94011d3 9448 * | | |11 = X32KO (PF.0) is input only mode with internal pull up.
sahilmgandhi 18:6a4db94011d3 9449 * |[2] |DOUT |IO Output Data
sahilmgandhi 18:6a4db94011d3 9450 * | | |0 = X32KO (PF.0) output low.
sahilmgandhi 18:6a4db94011d3 9451 * | | |1 = X32KO (PF.0) output high.
sahilmgandhi 18:6a4db94011d3 9452 * |[3] |CTLSEL |IO Pin State Backup Selection
sahilmgandhi 18:6a4db94011d3 9453 * | | |When low speed 32 kHz oscillator is disabled, X32KO (PF.0) pin can be used as GPIO function.
sahilmgandhi 18:6a4db94011d3 9454 * | | |User can program CTLSEL bit to decide X32KO (PF.0) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTOCTL control register.
sahilmgandhi 18:6a4db94011d3 9455 * | | |0 = X32KO (PF.0) pin I/O function is controlled by GPIO module.
sahilmgandhi 18:6a4db94011d3 9456 * | | |It becomes floating when system power is turned off.
sahilmgandhi 18:6a4db94011d3 9457 * | | |1 = X32KO (PF.0) pin I/O function is controlled by VBAT power domain, X32KO (PF.0) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1.
sahilmgandhi 18:6a4db94011d3 9458 * | | |I/O pin keeps the previous state after system power is turned off.
sahilmgandhi 18:6a4db94011d3 9459 * @var RTC_T::LXTICTL
sahilmgandhi 18:6a4db94011d3 9460 * Offset: 0x108 X32KI Pin Control Register
sahilmgandhi 18:6a4db94011d3 9461 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 9462 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 9463 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 9464 * |[1:0] |OPMODE |IO Operation Mode
sahilmgandhi 18:6a4db94011d3 9465 * | | |00 = X32KI (PF.1) is input only mode, without pull-up resistor.
sahilmgandhi 18:6a4db94011d3 9466 * | | |01 = X32KI (PF.1) is output push pull mode.
sahilmgandhi 18:6a4db94011d3 9467 * | | |10 = X32KI (PF.1) is open drain mode.
sahilmgandhi 18:6a4db94011d3 9468 * | | |11 = X32KI (PF.1) is input only mode with internal pull up.
sahilmgandhi 18:6a4db94011d3 9469 * |[2] |DOUT |IO Output Data
sahilmgandhi 18:6a4db94011d3 9470 * | | |0 = X32KI (PF.1) output low.
sahilmgandhi 18:6a4db94011d3 9471 * | | |1 = X32KI (PF.1) output high.
sahilmgandhi 18:6a4db94011d3 9472 * |[3] |CTLSEL |IO Pin State Backup Selection
sahilmgandhi 18:6a4db94011d3 9473 * | | |When low speed 32 kHz oscillator is disabled, X32KI (PF.1) pin can be used as GPIO function.
sahilmgandhi 18:6a4db94011d3 9474 * | | |User can program CTLSEL bit to decide X32KI (PF.1) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTICTL control register.
sahilmgandhi 18:6a4db94011d3 9475 * | | |0 = X32KI (PF.1) pin I/O function is controlled by GPIO module.
sahilmgandhi 18:6a4db94011d3 9476 * | | |It becomes floating state when system power is turned off.
sahilmgandhi 18:6a4db94011d3 9477 * | | |1 = X32KI (PF.1) pin I/O function is controlled by VBAT power domain, X32KI (PF.1) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1.
sahilmgandhi 18:6a4db94011d3 9478 * | | |I/O pin keeps the previous state after system power is turned off.
sahilmgandhi 18:6a4db94011d3 9479 * @var RTC_T::TAMPCTL
sahilmgandhi 18:6a4db94011d3 9480 * Offset: 0x10C TAMPER Pin Control Register
sahilmgandhi 18:6a4db94011d3 9481 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 9482 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 9483 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 9484 * |[1:0] |OPMODE |IO Operation Mode
sahilmgandhi 18:6a4db94011d3 9485 * | | |00 = TAMPER (PF.2) is input only mode, without pull-up resistor.
sahilmgandhi 18:6a4db94011d3 9486 * | | |01 = TAMPER (PF.2) is output push pull mode.
sahilmgandhi 18:6a4db94011d3 9487 * | | |10 = TAMPER (PF.2) is open drain mode.
sahilmgandhi 18:6a4db94011d3 9488 * | | |11 = TAMPER (PF.2) is input only mode with internal pull up.
sahilmgandhi 18:6a4db94011d3 9489 * |[2] |DOUT |IO Output Data
sahilmgandhi 18:6a4db94011d3 9490 * | | |0 = TAMPER (PF.2) output low.
sahilmgandhi 18:6a4db94011d3 9491 * | | |1 = TAMPER (PF.2) output high.
sahilmgandhi 18:6a4db94011d3 9492 * |[3] |CTLSEL |IO Pin State Backup Selection
sahilmgandhi 18:6a4db94011d3 9493 * | | |When tamper function is disabled, TAMPER pin can be used as GPIO function.
sahilmgandhi 18:6a4db94011d3 9494 * | | |User can program CTLSEL bit to decide PF.2 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_TAMPCTL control register.
sahilmgandhi 18:6a4db94011d3 9495 * | | |0 =TAMPER (PF.2) I/O function is controlled by GPIO module.
sahilmgandhi 18:6a4db94011d3 9496 * | | |It becomes floating state when system power is turned off.
sahilmgandhi 18:6a4db94011d3 9497 * | | |1 =TAMPER (PF.2) I/O function is controlled by VBAT power domain.
sahilmgandhi 18:6a4db94011d3 9498 * | | |PF.2 function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1.
sahilmgandhi 18:6a4db94011d3 9499 * | | |I/O pin state keeps previous state after system power is turned off.
sahilmgandhi 18:6a4db94011d3 9500 */
sahilmgandhi 18:6a4db94011d3 9501
sahilmgandhi 18:6a4db94011d3 9502 __IO uint32_t INIT; /* Offset: 0x00 RTC Initiation Register */
sahilmgandhi 18:6a4db94011d3 9503 __O uint32_t RWEN; /* Offset: 0x04 RTC Access Enable Register */
sahilmgandhi 18:6a4db94011d3 9504 __IO uint32_t FREQADJ; /* Offset: 0x08 RTC Frequency Compensation Register */
sahilmgandhi 18:6a4db94011d3 9505 __IO uint32_t TIME; /* Offset: 0x0C Time Loading Register */
sahilmgandhi 18:6a4db94011d3 9506 __IO uint32_t CAL; /* Offset: 0x10 RTC Calendar Loading Register */
sahilmgandhi 18:6a4db94011d3 9507 __IO uint32_t CLKFMT; /* Offset: 0x14 Time Scale Selection Register */
sahilmgandhi 18:6a4db94011d3 9508 __IO uint32_t WEEKDAY; /* Offset: 0x18 Day of the Week Register */
sahilmgandhi 18:6a4db94011d3 9509 __IO uint32_t TALM; /* Offset: 0x1C Time Alarm Register */
sahilmgandhi 18:6a4db94011d3 9510 __IO uint32_t CALM; /* Offset: 0x20 Calendar Alarm Register */
sahilmgandhi 18:6a4db94011d3 9511 __I uint32_t LEAPYEAR; /* Offset: 0x24 RTC Leap Year Indicator Register */
sahilmgandhi 18:6a4db94011d3 9512 __IO uint32_t INTEN; /* Offset: 0x28 RTC Interrupt Enable Register */
sahilmgandhi 18:6a4db94011d3 9513 __IO uint32_t INTSTS; /* Offset: 0x2C RTC Interrupt Indicator Register */
sahilmgandhi 18:6a4db94011d3 9514 __IO uint32_t TICK; /* Offset: 0x30 RTC Time Tick Register */
sahilmgandhi 18:6a4db94011d3 9515 __IO uint32_t TAMSK; /* Offset: 0x34 Time Alarm Mask Register */
sahilmgandhi 18:6a4db94011d3 9516 __IO uint32_t CAMSK; /* Offset: 0x38 Calendar Alarm Mask Register */
sahilmgandhi 18:6a4db94011d3 9517 __IO uint32_t SPRCTL; /* Offset: 0x3C RTC Spare Functional Control Register */
sahilmgandhi 18:6a4db94011d3 9518 __IO uint32_t SPR[20]; /* Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19 */
sahilmgandhi 18:6a4db94011d3 9519 __I uint32_t RESERVE0[28];
sahilmgandhi 18:6a4db94011d3 9520 __IO uint32_t LXTCTL; /* Offset: 0x100 RTC 32.768 kHz Oscillator Control Register */
sahilmgandhi 18:6a4db94011d3 9521 __IO uint32_t LXTOCTL; /* Offset: 0x104 X32KO Pin Control Register */
sahilmgandhi 18:6a4db94011d3 9522 __IO uint32_t LXTICTL; /* Offset: 0x108 X32KI Pin Control Register */
sahilmgandhi 18:6a4db94011d3 9523 __IO uint32_t TAMPCTL; /* Offset: 0x10C TAMPER Pin Control Register */
sahilmgandhi 18:6a4db94011d3 9524
sahilmgandhi 18:6a4db94011d3 9525 } RTC_T;
sahilmgandhi 18:6a4db94011d3 9526
sahilmgandhi 18:6a4db94011d3 9527
sahilmgandhi 18:6a4db94011d3 9528
sahilmgandhi 18:6a4db94011d3 9529 /**
sahilmgandhi 18:6a4db94011d3 9530 @addtogroup RTC_CONST RTC Bit Field Definition
sahilmgandhi 18:6a4db94011d3 9531 Constant Definitions for RTC Controller
sahilmgandhi 18:6a4db94011d3 9532 @{ */
sahilmgandhi 18:6a4db94011d3 9533
sahilmgandhi 18:6a4db94011d3 9534 #define RTC_INIT_ACTIVE_Pos (0) /*!< RTC_T::INIT: ACTIVE Position */
sahilmgandhi 18:6a4db94011d3 9535 #define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos) /*!< RTC_T::INIT: ACTIVE Mask */
sahilmgandhi 18:6a4db94011d3 9536
sahilmgandhi 18:6a4db94011d3 9537 #define RTC_INIT_INIT_Pos (0) /*!< RTC_T::INIT: INIT Position */
sahilmgandhi 18:6a4db94011d3 9538 #define RTC_INIT_INIT_Msk (0xfffffffful << RTC_INIT_INIT_Pos) /*!< RTC_T::INIT: INIT Mask */
sahilmgandhi 18:6a4db94011d3 9539
sahilmgandhi 18:6a4db94011d3 9540 #define RTC_RWEN_RWEN_Pos (0) /*!< RTC_T::RWEN: RWEN Position */
sahilmgandhi 18:6a4db94011d3 9541 #define RTC_RWEN_RWEN_Msk (0xfffful << RTC_RWEN_RWEN_Pos) /*!< RTC_T::RWEN: RWEN Mask */
sahilmgandhi 18:6a4db94011d3 9542
sahilmgandhi 18:6a4db94011d3 9543 #define RTC_RWEN_RWENF_Pos (16) /*!< RTC_T::RWEN: RWENF Position */
sahilmgandhi 18:6a4db94011d3 9544 #define RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos) /*!< RTC_T::RWEN: RWENF Mask */
sahilmgandhi 18:6a4db94011d3 9545
sahilmgandhi 18:6a4db94011d3 9546 #define RTC_FREQADJ_FRACTION_Pos (0) /*!< RTC_T::FREQADJ: FRACTION Position */
sahilmgandhi 18:6a4db94011d3 9547 #define RTC_FREQADJ_FRACTION_Msk (0x3ful << RTC_FREQADJ_FRACTION_Pos) /*!< RTC_T::FREQADJ: FRACTION Mask */
sahilmgandhi 18:6a4db94011d3 9548
sahilmgandhi 18:6a4db94011d3 9549 #define RTC_FREQADJ_INTEGER_Pos (8) /*!< RTC_T::FREQADJ: INTEGER Position */
sahilmgandhi 18:6a4db94011d3 9550 #define RTC_FREQADJ_INTEGER_Msk (0xful << RTC_FREQADJ_INTEGER_Pos) /*!< RTC_T::FREQADJ: INTEGER Mask */
sahilmgandhi 18:6a4db94011d3 9551
sahilmgandhi 18:6a4db94011d3 9552 #define RTC_TIME_SEC_Pos (0) /*!< RTC_T::TIME: SEC Position */
sahilmgandhi 18:6a4db94011d3 9553 #define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /*!< RTC_T::TIME: SEC Mask */
sahilmgandhi 18:6a4db94011d3 9554
sahilmgandhi 18:6a4db94011d3 9555 #define RTC_TIME_TENSEC_Pos (4) /*!< RTC_T::TIME: TENSEC Position */
sahilmgandhi 18:6a4db94011d3 9556 #define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /*!< RTC_T::TIME: TENSEC Mask */
sahilmgandhi 18:6a4db94011d3 9557
sahilmgandhi 18:6a4db94011d3 9558 #define RTC_TIME_MIN_Pos (8) /*!< RTC_T::TIME: MIN Position */
sahilmgandhi 18:6a4db94011d3 9559 #define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /*!< RTC_T::TIME: MIN Mask */
sahilmgandhi 18:6a4db94011d3 9560
sahilmgandhi 18:6a4db94011d3 9561 #define RTC_TIME_TENMIN_Pos (12) /*!< RTC_T::TIME: TENMIN Position */
sahilmgandhi 18:6a4db94011d3 9562 #define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /*!< RTC_T::TIME: TENMIN Mask */
sahilmgandhi 18:6a4db94011d3 9563
sahilmgandhi 18:6a4db94011d3 9564 #define RTC_TIME_HR_Pos (16) /*!< RTC_T::TIME: HR Position */
sahilmgandhi 18:6a4db94011d3 9565 #define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /*!< RTC_T::TIME: HR Mask */
sahilmgandhi 18:6a4db94011d3 9566
sahilmgandhi 18:6a4db94011d3 9567 #define RTC_TIME_TENHR_Pos (20) /*!< RTC_T::TIME: TENHR Position */
sahilmgandhi 18:6a4db94011d3 9568 #define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /*!< RTC_T::TIME: TENHR Mask */
sahilmgandhi 18:6a4db94011d3 9569
sahilmgandhi 18:6a4db94011d3 9570 #define RTC_CAL_DAY_Pos (0) /*!< RTC_T::CAL: DAY Position */
sahilmgandhi 18:6a4db94011d3 9571 #define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /*!< RTC_T::CAL: DAY Mask */
sahilmgandhi 18:6a4db94011d3 9572
sahilmgandhi 18:6a4db94011d3 9573 #define RTC_CAL_TENDAY_Pos (4) /*!< RTC_T::CAL: TENDAY Position */
sahilmgandhi 18:6a4db94011d3 9574 #define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /*!< RTC_T::CAL: TENDAY Mask */
sahilmgandhi 18:6a4db94011d3 9575
sahilmgandhi 18:6a4db94011d3 9576 #define RTC_CAL_MON_Pos (8) /*!< RTC_T::CAL: MON Position */
sahilmgandhi 18:6a4db94011d3 9577 #define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /*!< RTC_T::CAL: MON Mask */
sahilmgandhi 18:6a4db94011d3 9578
sahilmgandhi 18:6a4db94011d3 9579 #define RTC_CAL_TENMON_Pos (12) /*!< RTC_T::CAL: TENMON Position */
sahilmgandhi 18:6a4db94011d3 9580 #define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /*!< RTC_T::CAL: TENMON Mask */
sahilmgandhi 18:6a4db94011d3 9581
sahilmgandhi 18:6a4db94011d3 9582 #define RTC_CAL_YEAR_Pos (16) /*!< RTC_T::CAL: YEAR Position */
sahilmgandhi 18:6a4db94011d3 9583 #define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /*!< RTC_T::CAL: YEAR Mask */
sahilmgandhi 18:6a4db94011d3 9584
sahilmgandhi 18:6a4db94011d3 9585 #define RTC_CAL_TENYEAR_Pos (20) /*!< RTC_T::CAL: TENYEAR Position */
sahilmgandhi 18:6a4db94011d3 9586 #define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /*!< RTC_T::CAL: TENYEAR Mask */
sahilmgandhi 18:6a4db94011d3 9587
sahilmgandhi 18:6a4db94011d3 9588 #define RTC_CLKFMT_24HEN_Pos (0) /*!< RTC_T::CLKFMT: 24HEN Position */
sahilmgandhi 18:6a4db94011d3 9589 #define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /*!< RTC_T::CLKFMT: 24HEN Mask */
sahilmgandhi 18:6a4db94011d3 9590
sahilmgandhi 18:6a4db94011d3 9591 #define RTC_WEEKDAY_WEEKDAY_Pos (0) /*!< RTC_T::WEEKDAY: WEEKDAY Position */
sahilmgandhi 18:6a4db94011d3 9592 #define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /*!< RTC_T::WEEKDAY: WEEKDAY Mask */
sahilmgandhi 18:6a4db94011d3 9593
sahilmgandhi 18:6a4db94011d3 9594 #define RTC_TALM_SEC_Pos (0) /*!< RTC_T::TALM: SEC Position */
sahilmgandhi 18:6a4db94011d3 9595 #define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /*!< RTC_T::TALM: SEC Mask */
sahilmgandhi 18:6a4db94011d3 9596
sahilmgandhi 18:6a4db94011d3 9597 #define RTC_TALM_TENSEC_Pos (4) /*!< RTC_T::TALM: TENSEC Position */
sahilmgandhi 18:6a4db94011d3 9598 #define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /*!< RTC_T::TALM: TENSEC Mask */
sahilmgandhi 18:6a4db94011d3 9599
sahilmgandhi 18:6a4db94011d3 9600 #define RTC_TALM_MIN_Pos (8) /*!< RTC_T::TALM: MIN Position */
sahilmgandhi 18:6a4db94011d3 9601 #define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /*!< RTC_T::TALM: MIN Mask */
sahilmgandhi 18:6a4db94011d3 9602
sahilmgandhi 18:6a4db94011d3 9603 #define RTC_TALM_TENMIN_Pos (12) /*!< RTC_T::TALM: TENMIN Position */
sahilmgandhi 18:6a4db94011d3 9604 #define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /*!< RTC_T::TALM: TENMIN Mask */
sahilmgandhi 18:6a4db94011d3 9605
sahilmgandhi 18:6a4db94011d3 9606 #define RTC_TALM_HR_Pos (16) /*!< RTC_T::TALM: HR Position */
sahilmgandhi 18:6a4db94011d3 9607 #define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /*!< RTC_T::TALM: HR Mask */
sahilmgandhi 18:6a4db94011d3 9608
sahilmgandhi 18:6a4db94011d3 9609 #define RTC_TALM_TENHR_Pos (20) /*!< RTC_T::TALM: TENHR Position */
sahilmgandhi 18:6a4db94011d3 9610 #define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /*!< RTC_T::TALM: TENHR Mask */
sahilmgandhi 18:6a4db94011d3 9611
sahilmgandhi 18:6a4db94011d3 9612 #define RTC_CALM_DAY_Pos (0) /*!< RTC_T::CALM: DAY Position */
sahilmgandhi 18:6a4db94011d3 9613 #define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /*!< RTC_T::CALM: DAY Mask */
sahilmgandhi 18:6a4db94011d3 9614
sahilmgandhi 18:6a4db94011d3 9615 #define RTC_CALM_TENDAY_Pos (4) /*!< RTC_T::CALM: TENDAY Position */
sahilmgandhi 18:6a4db94011d3 9616 #define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /*!< RTC_T::CALM: TENDAY Mask */
sahilmgandhi 18:6a4db94011d3 9617
sahilmgandhi 18:6a4db94011d3 9618 #define RTC_CALM_MON_Pos (8) /*!< RTC_T::CALM: MON Position */
sahilmgandhi 18:6a4db94011d3 9619 #define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /*!< RTC_T::CALM: MON Mask */
sahilmgandhi 18:6a4db94011d3 9620
sahilmgandhi 18:6a4db94011d3 9621 #define RTC_CALM_TENMON_Pos (12) /*!< RTC_T::CALM: TENMON Position */
sahilmgandhi 18:6a4db94011d3 9622 #define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /*!< RTC_T::CALM: TENMON Mask */
sahilmgandhi 18:6a4db94011d3 9623
sahilmgandhi 18:6a4db94011d3 9624 #define RTC_CALM_YEAR_Pos (16) /*!< RTC_T::CALM: YEAR Position */
sahilmgandhi 18:6a4db94011d3 9625 #define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /*!< RTC_T::CALM: YEAR Mask */
sahilmgandhi 18:6a4db94011d3 9626
sahilmgandhi 18:6a4db94011d3 9627 #define RTC_CALM_TENYEAR_Pos (20) /*!< RTC_T::CALM: TENYEAR Position */
sahilmgandhi 18:6a4db94011d3 9628 #define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /*!< RTC_T::CALM: TENYEAR Mask */
sahilmgandhi 18:6a4db94011d3 9629
sahilmgandhi 18:6a4db94011d3 9630 #define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /*!< RTC_T::LEAPYEAR: LEAPYEAR Position */
sahilmgandhi 18:6a4db94011d3 9631 #define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask */
sahilmgandhi 18:6a4db94011d3 9632
sahilmgandhi 18:6a4db94011d3 9633 #define RTC_INTEN_ALMIEN_Pos (0) /*!< RTC_T::INTEN: ALMIEN Position */
sahilmgandhi 18:6a4db94011d3 9634 #define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /*!< RTC_T::INTEN: ALMIEN Mask */
sahilmgandhi 18:6a4db94011d3 9635
sahilmgandhi 18:6a4db94011d3 9636 #define RTC_INTEN_TICKIEN_Pos (1) /*!< RTC_T::INTEN: TICKIEN Position */
sahilmgandhi 18:6a4db94011d3 9637 #define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /*!< RTC_T::INTEN: TICKIEN Mask */
sahilmgandhi 18:6a4db94011d3 9638
sahilmgandhi 18:6a4db94011d3 9639 #define RTC_INTEN_SNPDIEN_Pos (2) /*!< RTC_T::INTEN: SNPDIEN Position */
sahilmgandhi 18:6a4db94011d3 9640 #define RTC_INTEN_SNPDIEN_Msk (0x1ul << RTC_INTEN_SNPDIEN_Pos) /*!< RTC_T::INTEN: SNPDIEN Mask */
sahilmgandhi 18:6a4db94011d3 9641
sahilmgandhi 18:6a4db94011d3 9642 #define RTC_INTSTS_ALMIF_Pos (0) /*!< RTC_T::INTSTS: ALMIF Position */
sahilmgandhi 18:6a4db94011d3 9643 #define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /*!< RTC_T::INTSTS: ALMIF Mask */
sahilmgandhi 18:6a4db94011d3 9644
sahilmgandhi 18:6a4db94011d3 9645 #define RTC_INTSTS_TICKIF_Pos (1) /*!< RTC_T::INTSTS: TICKIF Position */
sahilmgandhi 18:6a4db94011d3 9646 #define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /*!< RTC_T::INTSTS: TICKIF Mask */
sahilmgandhi 18:6a4db94011d3 9647
sahilmgandhi 18:6a4db94011d3 9648 #define RTC_INTSTS_SNPDIF_Pos (2) /*!< RTC_T::INTSTS: SNPDIF Position */
sahilmgandhi 18:6a4db94011d3 9649 #define RTC_INTSTS_SNPDIF_Msk (0x1ul << RTC_INTSTS_SNPDIF_Pos) /*!< RTC_T::INTSTS: SNPDIF Mask */
sahilmgandhi 18:6a4db94011d3 9650
sahilmgandhi 18:6a4db94011d3 9651 #define RTC_TICK_TICK_Pos (0) /*!< RTC_T::TICK: TICK Position */
sahilmgandhi 18:6a4db94011d3 9652 #define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) /*!< RTC_T::TICK: TICK Mask */
sahilmgandhi 18:6a4db94011d3 9653
sahilmgandhi 18:6a4db94011d3 9654 #define RTC_TAMSK_MSEC_Pos (0) /*!< RTC_T::TAMSK: MSEC Position */
sahilmgandhi 18:6a4db94011d3 9655 #define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /*!< RTC_T::TAMSK: MSEC Mask */
sahilmgandhi 18:6a4db94011d3 9656
sahilmgandhi 18:6a4db94011d3 9657 #define RTC_TAMSK_MTENSEC_Pos (1) /*!< RTC_T::TAMSK: MTENSEC Position */
sahilmgandhi 18:6a4db94011d3 9658 #define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /*!< RTC_T::TAMSK: MTENSEC Mask */
sahilmgandhi 18:6a4db94011d3 9659
sahilmgandhi 18:6a4db94011d3 9660 #define RTC_TAMSK_MMIN_Pos (2) /*!< RTC_T::TAMSK: MMIN Position */
sahilmgandhi 18:6a4db94011d3 9661 #define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /*!< RTC_T::TAMSK: MMIN Mask */
sahilmgandhi 18:6a4db94011d3 9662
sahilmgandhi 18:6a4db94011d3 9663 #define RTC_TAMSK_MTENMIN_Pos (3) /*!< RTC_T::TAMSK: MTENMIN Position */
sahilmgandhi 18:6a4db94011d3 9664 #define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /*!< RTC_T::TAMSK: MTENMIN Mask */
sahilmgandhi 18:6a4db94011d3 9665
sahilmgandhi 18:6a4db94011d3 9666 #define RTC_TAMSK_MHR_Pos (4) /*!< RTC_T::TAMSK: MHR Position */
sahilmgandhi 18:6a4db94011d3 9667 #define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /*!< RTC_T::TAMSK: MHR Mask */
sahilmgandhi 18:6a4db94011d3 9668
sahilmgandhi 18:6a4db94011d3 9669 #define RTC_TAMSK_MTENHR_Pos (5) /*!< RTC_T::TAMSK: MTENHR Position */
sahilmgandhi 18:6a4db94011d3 9670 #define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /*!< RTC_T::TAMSK: MTENHR Mask */
sahilmgandhi 18:6a4db94011d3 9671
sahilmgandhi 18:6a4db94011d3 9672 #define RTC_CAMSK_MDAY_Pos (0) /*!< RTC_T::CAMSK: MDAY Position */
sahilmgandhi 18:6a4db94011d3 9673 #define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /*!< RTC_T::CAMSK: MDAY Mask */
sahilmgandhi 18:6a4db94011d3 9674
sahilmgandhi 18:6a4db94011d3 9675 #define RTC_CAMSK_MTENDAY_Pos (1) /*!< RTC_T::CAMSK: MTENDAY Position */
sahilmgandhi 18:6a4db94011d3 9676 #define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /*!< RTC_T::CAMSK: MTENDAY Mask */
sahilmgandhi 18:6a4db94011d3 9677
sahilmgandhi 18:6a4db94011d3 9678 #define RTC_CAMSK_MMON_Pos (2) /*!< RTC_T::CAMSK: MMON Position */
sahilmgandhi 18:6a4db94011d3 9679 #define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /*!< RTC_T::CAMSK: MMON Mask */
sahilmgandhi 18:6a4db94011d3 9680
sahilmgandhi 18:6a4db94011d3 9681 #define RTC_CAMSK_MTENMON_Pos (3) /*!< RTC_T::CAMSK: MTENMON Position */
sahilmgandhi 18:6a4db94011d3 9682 #define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /*!< RTC_T::CAMSK: MTENMON Mask */
sahilmgandhi 18:6a4db94011d3 9683
sahilmgandhi 18:6a4db94011d3 9684 #define RTC_CAMSK_MYEAR_Pos (4) /*!< RTC_T::CAMSK: MYEAR Position */
sahilmgandhi 18:6a4db94011d3 9685 #define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /*!< RTC_T::CAMSK: MYEAR Mask */
sahilmgandhi 18:6a4db94011d3 9686
sahilmgandhi 18:6a4db94011d3 9687 #define RTC_CAMSK_MTENYEAR_Pos (5) /*!< RTC_T::CAMSK: MTENYEAR Position */
sahilmgandhi 18:6a4db94011d3 9688 #define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /*!< RTC_T::CAMSK: MTENYEAR Mask */
sahilmgandhi 18:6a4db94011d3 9689
sahilmgandhi 18:6a4db94011d3 9690 #define RTC_SPRCTL_SNPDEN_Pos (0) /*!< RTC_T::SPRCTL: SNPDEN Position */
sahilmgandhi 18:6a4db94011d3 9691 #define RTC_SPRCTL_SNPDEN_Msk (0x1ul << RTC_SPRCTL_SNPDEN_Pos) /*!< RTC_T::SPRCTL: SNPDEN Mask */
sahilmgandhi 18:6a4db94011d3 9692
sahilmgandhi 18:6a4db94011d3 9693 #define RTC_SPRCTL_SNPTYPE0_Pos (1) /*!< RTC_T::SPRCTL: SNPTYPE0 Position */
sahilmgandhi 18:6a4db94011d3 9694 #define RTC_SPRCTL_SNPTYPE0_Msk (0x1ul << RTC_SPRCTL_SNPTYPE0_Pos) /*!< RTC_T::SPRCTL: SNPTYPE0 Mask */
sahilmgandhi 18:6a4db94011d3 9695
sahilmgandhi 18:6a4db94011d3 9696 #define RTC_SPRCTL_SPRRWEN_Pos (2) /*!< RTC_T::SPRCTL: SPRRWEN Position */
sahilmgandhi 18:6a4db94011d3 9697 #define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) /*!< RTC_T::SPRCTL: SPRRWEN Mask */
sahilmgandhi 18:6a4db94011d3 9698
sahilmgandhi 18:6a4db94011d3 9699 #define RTC_SPRCTL_SNPTYPE1_Pos (3) /*!< RTC_T::SPRCTL: SNPTYPE1 Position */
sahilmgandhi 18:6a4db94011d3 9700 #define RTC_SPRCTL_SNPTYPE1_Msk (0x1ul << RTC_SPRCTL_SNPTYPE1_Pos) /*!< RTC_T::SPRCTL: SNPTYPE1 Mask */
sahilmgandhi 18:6a4db94011d3 9701
sahilmgandhi 18:6a4db94011d3 9702 #define RTC_SPRCTL_SPRCSTS_Pos (5) /*!< RTC_T::SPRCTL: SPRCSTS Position */
sahilmgandhi 18:6a4db94011d3 9703 #define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos) /*!< RTC_T::SPRCTL: SPRCSTS Mask */
sahilmgandhi 18:6a4db94011d3 9704
sahilmgandhi 18:6a4db94011d3 9705 #define RTC_SPRCTL_SPRRWRDY_Pos (7) /*!< RTC_T::SPRCTL: SPRRWRDY Position */
sahilmgandhi 18:6a4db94011d3 9706 #define RTC_SPRCTL_SPRRWRDY_Msk (0x1ul << RTC_SPRCTL_SPRRWRDY_Pos) /*!< RTC_T::SPRCTL: SPRRWRDY Mask */
sahilmgandhi 18:6a4db94011d3 9707
sahilmgandhi 18:6a4db94011d3 9708 #define RTC_SPR_SPARE_Pos (0) /*!< RTC_T::SPR: SPARE Position */
sahilmgandhi 18:6a4db94011d3 9709 #define RTC_SPR_SPARE_Msk (0xfffffffful << RTC_SPR_SPARE_Pos) /*!< RTC_T::SPR: SPARE Mask */
sahilmgandhi 18:6a4db94011d3 9710
sahilmgandhi 18:6a4db94011d3 9711 #define RTC_LXTCTL_LXTEN_Pos (0) /*!< RTC_T::LXTCTL: LXTEN Position */
sahilmgandhi 18:6a4db94011d3 9712 #define RTC_LXTCTL_LXTEN_Msk (0x1ul << RTC_LXTCTL_LXTEN_Pos) /*!< RTC_T::LXTCTL: LXTEN Mask */
sahilmgandhi 18:6a4db94011d3 9713
sahilmgandhi 18:6a4db94011d3 9714 #define RTC_LXTCTL_GAIN_Pos (1) /*!< RTC_T::LXTCTL: GAIN Position */
sahilmgandhi 18:6a4db94011d3 9715 #define RTC_LXTCTL_GAIN_Msk (0x7ul << RTC_LXTCTL_GAIN_Pos) /*!< RTC_T::LXTCTL: GAIN Mask */
sahilmgandhi 18:6a4db94011d3 9716
sahilmgandhi 18:6a4db94011d3 9717 #define RTC_LXTOCTL_OPMODE_Pos (0) /*!< RTC_T::LXTOCTL: OPMODE Position */
sahilmgandhi 18:6a4db94011d3 9718 #define RTC_LXTOCTL_OPMODE_Msk (0x3ul << RTC_LXTOCTL_OPMODE_Pos) /*!< RTC_T::LXTOCTL: OPMODE Mask */
sahilmgandhi 18:6a4db94011d3 9719
sahilmgandhi 18:6a4db94011d3 9720 #define RTC_LXTOCTL_DOUT_Pos (2) /*!< RTC_T::LXTOCTL: DOUT Position */
sahilmgandhi 18:6a4db94011d3 9721 #define RTC_LXTOCTL_DOUT_Msk (0x1ul << RTC_LXTOCTL_DOUT_Pos) /*!< RTC_T::LXTOCTL: DOUT Mask */
sahilmgandhi 18:6a4db94011d3 9722
sahilmgandhi 18:6a4db94011d3 9723 #define RTC_LXTOCTL_CTLSEL_Pos (3) /*!< RTC_T::LXTOCTL: CTLSEL Position */
sahilmgandhi 18:6a4db94011d3 9724 #define RTC_LXTOCTL_CTLSEL_Msk (0x1ul << RTC_LXTOCTL_CTLSEL_Pos) /*!< RTC_T::LXTOCTL: CTLSEL Mask */
sahilmgandhi 18:6a4db94011d3 9725
sahilmgandhi 18:6a4db94011d3 9726 #define RTC_LXTICTL_OPMODE_Pos (0) /*!< RTC_T::LXTICTL: OPMODE Position */
sahilmgandhi 18:6a4db94011d3 9727 #define RTC_LXTICTL_OPMODE_Msk (0x3ul << RTC_LXTICTL_OPMODE_Pos) /*!< RTC_T::LXTICTL: OPMODE Mask */
sahilmgandhi 18:6a4db94011d3 9728
sahilmgandhi 18:6a4db94011d3 9729 #define RTC_LXTICTL_DOUT_Pos (2) /*!< RTC_T::LXTICTL: DOUT Position */
sahilmgandhi 18:6a4db94011d3 9730 #define RTC_LXTICTL_DOUT_Msk (0x1ul << RTC_LXTICTL_DOUT_Pos) /*!< RTC_T::LXTICTL: DOUT Mask */
sahilmgandhi 18:6a4db94011d3 9731
sahilmgandhi 18:6a4db94011d3 9732 #define RTC_LXTICTL_CTLSEL_Pos (3) /*!< RTC_T::LXTICTL: CTLSEL Position */
sahilmgandhi 18:6a4db94011d3 9733 #define RTC_LXTICTL_CTLSEL_Msk (0x1ul << RTC_LXTICTL_CTLSEL_Pos) /*!< RTC_T::LXTICTL: CTLSEL Mask */
sahilmgandhi 18:6a4db94011d3 9734
sahilmgandhi 18:6a4db94011d3 9735 #define RTC_TAMPCTL_OPMODE_Pos (0) /*!< RTC_T::TAMPCTL: OPMODE Position */
sahilmgandhi 18:6a4db94011d3 9736 #define RTC_TAMPCTL_OPMODE_Msk (0x3ul << RTC_TAMPCTL_OPMODE_Pos) /*!< RTC_T::TAMPCTL: OPMODE Mask */
sahilmgandhi 18:6a4db94011d3 9737
sahilmgandhi 18:6a4db94011d3 9738 #define RTC_TAMPCTL_DOUT_Pos (2) /*!< RTC_T::TAMPCTL: DOUT Position */
sahilmgandhi 18:6a4db94011d3 9739 #define RTC_TAMPCTL_DOUT_Msk (0x1ul << RTC_TAMPCTL_DOUT_Pos) /*!< RTC_T::TAMPCTL: DOUT Mask */
sahilmgandhi 18:6a4db94011d3 9740
sahilmgandhi 18:6a4db94011d3 9741 #define RTC_TAMPCTL_CTLSEL_Pos (3) /*!< RTC_T::TAMPCTL: CTLSEL Position */
sahilmgandhi 18:6a4db94011d3 9742 #define RTC_TAMPCTL_CTLSEL_Msk (0x1ul << RTC_TAMPCTL_CTLSEL_Pos) /*!< RTC_T::TAMPCTL: CTLSEL Mask */
sahilmgandhi 18:6a4db94011d3 9743
sahilmgandhi 18:6a4db94011d3 9744 /**@}*/ /* RTC_CONST */
sahilmgandhi 18:6a4db94011d3 9745 /**@}*/ /* end of RTC register group */
sahilmgandhi 18:6a4db94011d3 9746
sahilmgandhi 18:6a4db94011d3 9747
sahilmgandhi 18:6a4db94011d3 9748 /*---------------------- Smart Card Host Interface Controller -------------------------*/
sahilmgandhi 18:6a4db94011d3 9749 /**
sahilmgandhi 18:6a4db94011d3 9750 @addtogroup SC Smart Card Host Interface Controller(SC)
sahilmgandhi 18:6a4db94011d3 9751 Memory Mapped Structure for SC Controller
sahilmgandhi 18:6a4db94011d3 9752 @{ */
sahilmgandhi 18:6a4db94011d3 9753
sahilmgandhi 18:6a4db94011d3 9754
sahilmgandhi 18:6a4db94011d3 9755 typedef struct
sahilmgandhi 18:6a4db94011d3 9756 {
sahilmgandhi 18:6a4db94011d3 9757
sahilmgandhi 18:6a4db94011d3 9758
sahilmgandhi 18:6a4db94011d3 9759 /**
sahilmgandhi 18:6a4db94011d3 9760 * @var SC_T::DAT
sahilmgandhi 18:6a4db94011d3 9761 * Offset: 0x00 SC Receiving/Transmit Holding Buffer Register.
sahilmgandhi 18:6a4db94011d3 9762 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 9763 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 9764 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 9765 * |[7:0] |DAT |Receiving/ Transmit Holding Buffer
sahilmgandhi 18:6a4db94011d3 9766 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 9767 * | | |By writing data to DAT, the SC will send out an 8-bit data.
sahilmgandhi 18:6a4db94011d3 9768 * | | |Note: If SCEN(SC_CTL[0]) is not enabled, DAT cannot be programmed.
sahilmgandhi 18:6a4db94011d3 9769 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 9770 * | | |By reading DAT, the SC will return an 8-bit received data.
sahilmgandhi 18:6a4db94011d3 9771 * @var SC_T::CTL
sahilmgandhi 18:6a4db94011d3 9772 * Offset: 0x04 SC Control Register.
sahilmgandhi 18:6a4db94011d3 9773 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 9774 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 9775 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 9776 * |[0] |SCEN |SC Engine Enable Bit
sahilmgandhi 18:6a4db94011d3 9777 * | | |Set this bit to 1 to enable SC operation.
sahilmgandhi 18:6a4db94011d3 9778 * | | |If this bit is cleared, SC will force all transition to IDLE state.
sahilmgandhi 18:6a4db94011d3 9779 * |[1] |RXOFF |RX Transition Disable Control
sahilmgandhi 18:6a4db94011d3 9780 * | | |0 = The receiver Enabled.
sahilmgandhi 18:6a4db94011d3 9781 * | | |1 = The receiver Disabled.
sahilmgandhi 18:6a4db94011d3 9782 * | | |Note:
sahilmgandhi 18:6a4db94011d3 9783 * | | |If AUTOCEN (SC_CTL[3])is enabled, these fields must be ignored.
sahilmgandhi 18:6a4db94011d3 9784 * |[2] |TXOFF |TX Transition Disable Control
sahilmgandhi 18:6a4db94011d3 9785 * | | |0 = The transceiver Enabled.
sahilmgandhi 18:6a4db94011d3 9786 * | | |1 = The transceiver Disabled.
sahilmgandhi 18:6a4db94011d3 9787 * |[3] |AUTOCEN |Auto Convention Enable Bit
sahilmgandhi 18:6a4db94011d3 9788 * | | |0 = Auto-convention Disabled.
sahilmgandhi 18:6a4db94011d3 9789 * | | |1 = Auto-convention Enabled.
sahilmgandhi 18:6a4db94011d3 9790 * | | |When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11.
sahilmgandhi 18:6a4db94011d3 9791 * | | |If software enables auto convention function, the setting step must be done before Answer to Reset state and the first data must be 0x3B or 0x3F.
sahilmgandhi 18:6a4db94011d3 9792 * | | |After hardware received first data and stored it at buffer,
sahilmgandhi 18:6a4db94011d3 9793 * | | |hardware will decided the convention and change the CONSEL (SC_CTL[5:4]) bits automatically.
sahilmgandhi 18:6a4db94011d3 9794 * | | |If the first data is not 0x3B or 0x3F, hardware will generate an interrupt if ACERRIEN (SC_INTEN[10]) = 1 to CPU.
sahilmgandhi 18:6a4db94011d3 9795 * |[5:4] |CONSEL |Convention Selection
sahilmgandhi 18:6a4db94011d3 9796 * | | |00 = Direct convention.
sahilmgandhi 18:6a4db94011d3 9797 * | | |01 = Reserved.
sahilmgandhi 18:6a4db94011d3 9798 * | | |10 = Reserved.
sahilmgandhi 18:6a4db94011d3 9799 * | | |11 = Inverse convention.
sahilmgandhi 18:6a4db94011d3 9800 * | | |Note:
sahilmgandhi 18:6a4db94011d3 9801 * | | |If AUTOCEN(SC_CTL[3]) enabled, this fields are ignored.
sahilmgandhi 18:6a4db94011d3 9802 * |[7:6] |RXTRGLV |Rx Buffer Trigger Level
sahilmgandhi 18:6a4db94011d3 9803 * | | |When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set (if SC_INTEN [RDAIEN] is enabled, an interrupt will be generated).
sahilmgandhi 18:6a4db94011d3 9804 * | | |00 = INTR_RDA Trigger Level with 01 Bytes.
sahilmgandhi 18:6a4db94011d3 9805 * | | |01 = INTR_RDA Trigger Level with 02 Bytes.
sahilmgandhi 18:6a4db94011d3 9806 * | | |10 = INTR_RDA Trigger Level with 03 Bytes.
sahilmgandhi 18:6a4db94011d3 9807 * | | |11 = Reserved.
sahilmgandhi 18:6a4db94011d3 9808 * |[12:8] |BGT |Block Guard Time (BGT)
sahilmgandhi 18:6a4db94011d3 9809 * | | |Block guard time means the minimum bit length between the leading edges of two consecutive characters between different transfer directions.
sahilmgandhi 18:6a4db94011d3 9810 * | | |This field indicates the counter for the bit length of block guard time.
sahilmgandhi 18:6a4db94011d3 9811 * | | |According to ISO7816-3, in T = 0 mode, software must fill 15 (real block guard time = 16.5) to this field; in T = 1 mode, software must fill 21 (real block guard time = 22.5) to it.
sahilmgandhi 18:6a4db94011d3 9812 * | | |Note:
sahilmgandhi 18:6a4db94011d3 9813 * | | |The real block guard time is BGT + 1.
sahilmgandhi 18:6a4db94011d3 9814 * |[14:13] |TMRSEL |Timer Selection
sahilmgandhi 18:6a4db94011d3 9815 * | | |00 = All internal timer function Disabled.
sahilmgandhi 18:6a4db94011d3 9816 * | | |01 = Internal 24 bit timer Enabled.
sahilmgandhi 18:6a4db94011d3 9817 * | | |Software can configure it by setting SC_TMRCTL0 [23:0].
sahilmgandhi 18:6a4db94011d3 9818 * | | |SC_TMRCTL1 and SC_TMRCTL2 will be ignored in this mode.
sahilmgandhi 18:6a4db94011d3 9819 * | | |10 = internal 24 bit timer and 8 bit internal timer Enabled.
sahilmgandhi 18:6a4db94011d3 9820 * | | |Software can configure the 24 bit timer by setting SC_TMRCTL0 [23:0] and configure the 8 bit timer by setting SC_TMRCTL1[7:0].
sahilmgandhi 18:6a4db94011d3 9821 * | | |SC_TMRCTL2 will be ignored in this mode.
sahilmgandhi 18:6a4db94011d3 9822 * | | |11 = Internal 24 bit timer and two 8 bit timers Enabled.
sahilmgandhi 18:6a4db94011d3 9823 * | | |Software can configure them by setting SC_TMRCTL0 [23:0], SC_TMRCTL1 [7:0] and SC_TMRCTL2 [7:0].
sahilmgandhi 18:6a4db94011d3 9824 * |[15] |NSB |Stop Bit Length
sahilmgandhi 18:6a4db94011d3 9825 * | | |This field indicates the length of stop bit.
sahilmgandhi 18:6a4db94011d3 9826 * | | |0 = The stop bit length is 2 ETU.
sahilmgandhi 18:6a4db94011d3 9827 * | | |1= The stop bit length is 1 ETU.
sahilmgandhi 18:6a4db94011d3 9828 * | | |Note:
sahilmgandhi 18:6a4db94011d3 9829 * | | |The default stop bit length is 2. SMC and UART adopts NSB to program the stop bit length
sahilmgandhi 18:6a4db94011d3 9830 * |[18:16] |RXRTY |RX Error Retry Count Number
sahilmgandhi 18:6a4db94011d3 9831 * | | |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred
sahilmgandhi 18:6a4db94011d3 9832 * | | |Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.
sahilmgandhi 18:6a4db94011d3 9833 * | | |Note2: This field cannot be changed when RXRTYEN enabled.
sahilmgandhi 18:6a4db94011d3 9834 * | | |The change flow is to disable RXRTYEN first and then fill in new retry value.
sahilmgandhi 18:6a4db94011d3 9835 * |[19] |RXRTYEN |RX Error Retry Enable Bit
sahilmgandhi 18:6a4db94011d3 9836 * | | |This bit enables receiver retry function when parity error has occurred.
sahilmgandhi 18:6a4db94011d3 9837 * | | |0 = RX error retry function Disabled.
sahilmgandhi 18:6a4db94011d3 9838 * | | |1 = RX error retry function Enabled.
sahilmgandhi 18:6a4db94011d3 9839 * | | |Note:
sahilmgandhi 18:6a4db94011d3 9840 * | | |Software must fill in the RXRTY value before enabling this bit.
sahilmgandhi 18:6a4db94011d3 9841 * |[22:20] |TXRTY |TX Error Retry Count Number
sahilmgandhi 18:6a4db94011d3 9842 * | | |This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.
sahilmgandhi 18:6a4db94011d3 9843 * | | |Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.
sahilmgandhi 18:6a4db94011d3 9844 * | | |Note2: This field cannot be changed when TXRTYEN enabled.
sahilmgandhi 18:6a4db94011d3 9845 * | | |The change flow is to disable TXRTYEN first and then fill in new retry value.
sahilmgandhi 18:6a4db94011d3 9846 * |[23] |TXRTYEN |TX Error Retry Enable Bit
sahilmgandhi 18:6a4db94011d3 9847 * | | |This bit enables transmitter retry function when parity error has occurred.
sahilmgandhi 18:6a4db94011d3 9848 * | | |0 = TX error retry function Disabled.
sahilmgandhi 18:6a4db94011d3 9849 * | | |1 = TX error retry function Enabled.
sahilmgandhi 18:6a4db94011d3 9850 * |[25:24] |CDDBSEL |Card Detect De-Bounce Selection
sahilmgandhi 18:6a4db94011d3 9851 * | | |This field indicates the card detect de-bounce selection.
sahilmgandhi 18:6a4db94011d3 9852 * | | |00 = De-bounce sample card insert once per 384 (128 * 3) peripheral clocks and de-bounce sample card removal once per 128 peripheral clocks.
sahilmgandhi 18:6a4db94011d3 9853 * | | |01 = De-bounce sample card insert once per 192 (64 * 3) peripheral clocks and de-bounce sample card removal once per 64 peripheral clocks.
sahilmgandhi 18:6a4db94011d3 9854 * | | |10 = De-bounce sample card insert once per 96 (32 * 3) peripheral clocks and de-bounce sample card removal once per 32 peripheral clocks.
sahilmgandhi 18:6a4db94011d3 9855 * | | |11 = De-bounce sample card insert once per 48 (16 * 3) peripheral clocks and de-bounce sample card removal once per 16 peripheral clocks.
sahilmgandhi 18:6a4db94011d3 9856 * |[26] |CDLV |Card Detect Level
sahilmgandhi 18:6a4db94011d3 9857 * | | |0 = When hardware detects the card detect pin (SC_CD) from high to low, it indicates a card is detected.
sahilmgandhi 18:6a4db94011d3 9858 * | | |1 = When hardware detects the card detect pin from low to high, it indicates a card is detected.
sahilmgandhi 18:6a4db94011d3 9859 * | | |Note: Software must select card detect level before Smart Card engine enabled.
sahilmgandhi 18:6a4db94011d3 9860 * |[30] |SYNC |SYNC Flag Indicator
sahilmgandhi 18:6a4db94011d3 9861 * | | |Due to synchronization, software should check this bit before writing a new value to RXRTY and TXRTY.
sahilmgandhi 18:6a4db94011d3 9862 * | | |0 = Synchronizing is completion, user can write new data to RXRTY and TXRTY.
sahilmgandhi 18:6a4db94011d3 9863 * | | |1 = Last value is synchronizing.
sahilmgandhi 18:6a4db94011d3 9864 * | | |Note: This bit is read only.
sahilmgandhi 18:6a4db94011d3 9865 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control
sahilmgandhi 18:6a4db94011d3 9866 * | | |0 = ICE debug mode acknowledgement affects SC counting.
sahilmgandhi 18:6a4db94011d3 9867 * | | |SC internal counter will be held while CPU is held by ICE.
sahilmgandhi 18:6a4db94011d3 9868 * | | |1 = ICE debug mode acknowledgement Disabled.
sahilmgandhi 18:6a4db94011d3 9869 * | | |SC internal counter will keep going no matter CPU is held by ICE or not.
sahilmgandhi 18:6a4db94011d3 9870 * @var SC_T::ALTCTL
sahilmgandhi 18:6a4db94011d3 9871 * Offset: 0x08 SC Alternate Control Register.
sahilmgandhi 18:6a4db94011d3 9872 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 9873 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 9874 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 9875 * |[0] |TXRST |TX Software Reset
sahilmgandhi 18:6a4db94011d3 9876 * | | |When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.
sahilmgandhi 18:6a4db94011d3 9877 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 9878 * | | |1 = Reset the TX internal state machine and pointers.
sahilmgandhi 18:6a4db94011d3 9879 * | | |Note:
sahilmgandhi 18:6a4db94011d3 9880 * | | |This bit will be auto cleared after reset is complete.
sahilmgandhi 18:6a4db94011d3 9881 * |[1] |RXRST |Rx Software Reset
sahilmgandhi 18:6a4db94011d3 9882 * | | |When RXRST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.
sahilmgandhi 18:6a4db94011d3 9883 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 9884 * | | |1 = Reset the Rx internal state machine and pointers.
sahilmgandhi 18:6a4db94011d3 9885 * | | |Note:
sahilmgandhi 18:6a4db94011d3 9886 * | | |This bit will be auto cleared after reset is complete.
sahilmgandhi 18:6a4db94011d3 9887 * |[2] |DACTEN |Deactivation Sequence Generator Enable Bit
sahilmgandhi 18:6a4db94011d3 9888 * | | |This bit enables SC controller to initiate the card by deactivation sequence
sahilmgandhi 18:6a4db94011d3 9889 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 9890 * | | |1 = Deactivation sequence generator Enabled.
sahilmgandhi 18:6a4db94011d3 9891 * | | |Note1:
sahilmgandhi 18:6a4db94011d3 9892 * | | |When the deactivation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
sahilmgandhi 18:6a4db94011d3 9893 * | | |Note2:
sahilmgandhi 18:6a4db94011d3 9894 * | | |This field will be cleared by TXRST (SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
sahilmgandhi 18:6a4db94011d3 9895 * | | |So don't fill this bit, TXRST, and RXRST at the same time.
sahilmgandhi 18:6a4db94011d3 9896 * | | |Note3:
sahilmgandhi 18:6a4db94011d3 9897 * | | |If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed.
sahilmgandhi 18:6a4db94011d3 9898 * |[3] |ACTEN |Activation Sequence Generator Enable Bit
sahilmgandhi 18:6a4db94011d3 9899 * | | |This bit enables SC controller to initiate the card by activation sequence
sahilmgandhi 18:6a4db94011d3 9900 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 9901 * | | |1 = Activation sequence generator Enabled.
sahilmgandhi 18:6a4db94011d3 9902 * | | |Note1:
sahilmgandhi 18:6a4db94011d3 9903 * | | |When the activation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
sahilmgandhi 18:6a4db94011d3 9904 * | | |Note2:
sahilmgandhi 18:6a4db94011d3 9905 * | | |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
sahilmgandhi 18:6a4db94011d3 9906 * | | |Note3:
sahilmgandhi 18:6a4db94011d3 9907 * | | |If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
sahilmgandhi 18:6a4db94011d3 9908 * |[4] |WARSTEN |Warm Reset Sequence Generator Enable Bit
sahilmgandhi 18:6a4db94011d3 9909 * | | |This bit enables SC controller to initiate the card by warm reset sequence
sahilmgandhi 18:6a4db94011d3 9910 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 9911 * | | |1 = Warm reset sequence generator Enabled.
sahilmgandhi 18:6a4db94011d3 9912 * | | |Note1:
sahilmgandhi 18:6a4db94011d3 9913 * | | |When the warm reset sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
sahilmgandhi 18:6a4db94011d3 9914 * | | |Note2:
sahilmgandhi 18:6a4db94011d3 9915 * | | |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST, and RXRST at the same time.
sahilmgandhi 18:6a4db94011d3 9916 * | | |Note3:
sahilmgandhi 18:6a4db94011d3 9917 * | | |If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
sahilmgandhi 18:6a4db94011d3 9918 * |[5] |CNTEN0 |Internal Timer0 Start Enable Bit
sahilmgandhi 18:6a4db94011d3 9919 * | | |This bit enables Timer 0 to start counting.
sahilmgandhi 18:6a4db94011d3 9920 * | | |Software can fill 0 to stop it and set 1 to reload and count.
sahilmgandhi 18:6a4db94011d3 9921 * | | |0 = Stops counting.
sahilmgandhi 18:6a4db94011d3 9922 * | | |1 = Start counting.
sahilmgandhi 18:6a4db94011d3 9923 * | | |Note1:
sahilmgandhi 18:6a4db94011d3 9924 * | | |This field is used for internal 24 bit timer when TMRSEL (SC_CTL[14:13]) = 01.
sahilmgandhi 18:6a4db94011d3 9925 * | | |Note2:
sahilmgandhi 18:6a4db94011d3 9926 * | | |If the operation mode is not in auto-reload mode (SC_TMRCTL0[26] = 0), this bit will be auto-cleared by hardware.
sahilmgandhi 18:6a4db94011d3 9927 * | | |Note3:
sahilmgandhi 18:6a4db94011d3 9928 * | | |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
sahilmgandhi 18:6a4db94011d3 9929 * | | |So don't fill this bit, TXRST and RXRST at the same time.
sahilmgandhi 18:6a4db94011d3 9930 * | | |Note4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
sahilmgandhi 18:6a4db94011d3 9931 * |[6] |CNTEN1 |Internal Timer1 Start Enable Bit
sahilmgandhi 18:6a4db94011d3 9932 * | | |This bit enables Timer 1 to start counting.
sahilmgandhi 18:6a4db94011d3 9933 * | | |Software can fill 0 to stop it and set 1 to reload and count.
sahilmgandhi 18:6a4db94011d3 9934 * | | |0 = Stops counting.
sahilmgandhi 18:6a4db94011d3 9935 * | | |1 = Start counting.
sahilmgandhi 18:6a4db94011d3 9936 * | | |Note1:
sahilmgandhi 18:6a4db94011d3 9937 * | | |This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 10 or TMRSEL(SC_CTL[14:13]) = 11.
sahilmgandhi 18:6a4db94011d3 9938 * | | |Don't filled CNTEN1 when TMRSEL(SC_CTL[14:13]) = 00 or TMRSEL(SC_CTL[14:13]) = 01.
sahilmgandhi 18:6a4db94011d3 9939 * | | |Note2:
sahilmgandhi 18:6a4db94011d3 9940 * | | |If the operation mode is not in auto-reload mode (SC_TMRCTL1[26] = 0), this bit will be auto-cleared by hardware.
sahilmgandhi 18:6a4db94011d3 9941 * | | |Note3:
sahilmgandhi 18:6a4db94011d3 9942 * | | |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
sahilmgandhi 18:6a4db94011d3 9943 * | | |Note4:
sahilmgandhi 18:6a4db94011d3 9944 * | | |If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
sahilmgandhi 18:6a4db94011d3 9945 * |[7] |CNTEN2 |Internal Timer2 Start Enable Bit
sahilmgandhi 18:6a4db94011d3 9946 * | | |This bit enables Timer 2 to start counting.
sahilmgandhi 18:6a4db94011d3 9947 * | | |Software can fill 0 to stop it and set 1 to reload and count.
sahilmgandhi 18:6a4db94011d3 9948 * | | |0 = Stops counting.
sahilmgandhi 18:6a4db94011d3 9949 * | | |1 = Start counting.
sahilmgandhi 18:6a4db94011d3 9950 * | | |Note1:
sahilmgandhi 18:6a4db94011d3 9951 * | | |This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 11.
sahilmgandhi 18:6a4db94011d3 9952 * | | |Don't filled CNTEN2 when TMRSEL(SC_CTL[14:13]) = 00 or TMRSEL(SC_CTL[14:13]) = 01 or TMRSEL(SC_CTL[14:13]) = 10.
sahilmgandhi 18:6a4db94011d3 9953 * | | |Note2:
sahilmgandhi 18:6a4db94011d3 9954 * | | |If the operation mode is not in auto-reload mode (SC_TMRCTL2[26] = 0), this bit will be auto-cleared by hardware.
sahilmgandhi 18:6a4db94011d3 9955 * | | |Note3:
sahilmgandhi 18:6a4db94011d3 9956 * | | |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
sahilmgandhi 18:6a4db94011d3 9957 * | | |So don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
sahilmgandhi 18:6a4db94011d3 9958 * | | |Note4:
sahilmgandhi 18:6a4db94011d3 9959 * | | |If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
sahilmgandhi 18:6a4db94011d3 9960 * |[9:8] |INITSEL |Initial Timing Selection
sahilmgandhi 18:6a4db94011d3 9961 * | | |This fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).
sahilmgandhi 18:6a4db94011d3 9962 * | | |Unit: SC clock
sahilmgandhi 18:6a4db94011d3 9963 * | | |Activation: refer to SC Activation Sequence in Figure 6.17-4
sahilmgandhi 18:6a4db94011d3 9964 * | | |Warm-reset: refer to Warm-Reset Sequence in Figure 6.17-5
sahilmgandhi 18:6a4db94011d3 9965 * | | |Deactivation: refer to Deactivation Sequence in Figure 6.17-6
sahilmgandhi 18:6a4db94011d3 9966 * |[12] |RXBGTEN |Receiver Block Guard Time Function Enable Bit
sahilmgandhi 18:6a4db94011d3 9967 * | | |0 = Receiver block guard time function Disabled.
sahilmgandhi 18:6a4db94011d3 9968 * | | |1 = Receiver block guard time function Enabled.
sahilmgandhi 18:6a4db94011d3 9969 * |[13] |ACTSTS0 |Internal Timer0 Active State (Read Only)
sahilmgandhi 18:6a4db94011d3 9970 * | | |This bit indicates the timer counter status of timer0.
sahilmgandhi 18:6a4db94011d3 9971 * | | |0 = Timer0 is not active.
sahilmgandhi 18:6a4db94011d3 9972 * | | |1 = Timer0 is active.
sahilmgandhi 18:6a4db94011d3 9973 * |[14] |ACTSTS1 |Internal Timer1 Active State (Read Only)
sahilmgandhi 18:6a4db94011d3 9974 * | | |This bit indicates the timer counter status of timer1.
sahilmgandhi 18:6a4db94011d3 9975 * | | |0 = Timer1 is not active.
sahilmgandhi 18:6a4db94011d3 9976 * | | |1 = Timer1 is active.
sahilmgandhi 18:6a4db94011d3 9977 * |[15] |ACTSTS2 |Internal Timer2 Active State (Read Only)
sahilmgandhi 18:6a4db94011d3 9978 * | | |This bit indicates the timer counter status of timer2.
sahilmgandhi 18:6a4db94011d3 9979 * | | |0 = Timer2 is not active.
sahilmgandhi 18:6a4db94011d3 9980 * | | |1 = Timer2 is active.
sahilmgandhi 18:6a4db94011d3 9981 * @var SC_T::EGT
sahilmgandhi 18:6a4db94011d3 9982 * Offset: 0x0C SC Extend Guard Time Register.
sahilmgandhi 18:6a4db94011d3 9983 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 9984 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 9985 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 9986 * |[7:0] |EGT |Extended Guard Time
sahilmgandhi 18:6a4db94011d3 9987 * | | |This field indicates the extended guard timer value.
sahilmgandhi 18:6a4db94011d3 9988 * | | |Note:
sahilmgandhi 18:6a4db94011d3 9989 * | | |The counter is ETU base and the real extended guard time is EGT.
sahilmgandhi 18:6a4db94011d3 9990 * @var SC_T::RXTOUT
sahilmgandhi 18:6a4db94011d3 9991 * Offset: 0x10 SC Receive buffer Time-out Register.
sahilmgandhi 18:6a4db94011d3 9992 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 9993 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 9994 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 9995 * |[8:0] |RFTM |SC Receiver FIFO Time-out (ETU Base)
sahilmgandhi 18:6a4db94011d3 9996 * | | |The time-out counter resets and starts counting whenever the RX buffer received a new data word.
sahilmgandhi 18:6a4db94011d3 9997 * | | |Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SC_DAT buffer, a receiver time-out interrupt INT_RTMR will be generated(if RXTOIF(SC_INTEN[9]) = 1 ).
sahilmgandhi 18:6a4db94011d3 9998 * | | |Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5.
sahilmgandhi 18:6a4db94011d3 9999 * | | |Note2:
sahilmgandhi 18:6a4db94011d3 10000 * | | |Filling all 0 to this field indicates to disable this function.
sahilmgandhi 18:6a4db94011d3 10001 * @var SC_T::ETUCTL
sahilmgandhi 18:6a4db94011d3 10002 * Offset: 0x14 SC ETU Control Register.
sahilmgandhi 18:6a4db94011d3 10003 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 10004 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 10005 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 10006 * |[11:0] |ETURDIV |ETU Rate Divider
sahilmgandhi 18:6a4db94011d3 10007 * | | |The field indicates the clock rate divider.
sahilmgandhi 18:6a4db94011d3 10008 * | | |The real ETU is ETURDIV + 1.
sahilmgandhi 18:6a4db94011d3 10009 * | | |Note:
sahilmgandhi 18:6a4db94011d3 10010 * | | |Software can configure this field, but this field must be greater than 0x004.
sahilmgandhi 18:6a4db94011d3 10011 * |[15] |CMPEN |Compensation Mode Enable Bit
sahilmgandhi 18:6a4db94011d3 10012 * | | |This bit enables clock compensation function.
sahilmgandhi 18:6a4db94011d3 10013 * | | |When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, where n is the value to be written into the ETURDIV .
sahilmgandhi 18:6a4db94011d3 10014 * | | |0 = Compensation function Disabled.
sahilmgandhi 18:6a4db94011d3 10015 * | | |1 = Compensation function Enabled.
sahilmgandhi 18:6a4db94011d3 10016 * @var SC_T::INTEN
sahilmgandhi 18:6a4db94011d3 10017 * Offset: 0x18 SC Interrupt Enable Control Register.
sahilmgandhi 18:6a4db94011d3 10018 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 10019 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 10020 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 10021 * |[0] |RDAIEN |Receive Data Reach Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 10022 * | | |This field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt enable.
sahilmgandhi 18:6a4db94011d3 10023 * | | |0 = Receive data reach trigger level interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 10024 * | | |1 = Receive data reach trigger level interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 10025 * |[1] |TBEIEN |Transmit Buffer Empty Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 10026 * | | |This field is used for transmit buffer empty interrupt enable.
sahilmgandhi 18:6a4db94011d3 10027 * | | |0 = Transmit buffer empty interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 10028 * | | |1 = Transmit buffer empty interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 10029 * |[2] |TERRIEN |Transfer Error Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 10030 * | | |This field is used for transfer error interrupt enable.
sahilmgandhi 18:6a4db94011d3 10031 * | | |The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]), receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22]) and transmitter retry over limit error TXOVERR (SC_STATUS[30]).
sahilmgandhi 18:6a4db94011d3 10032 * | | |0 = Transfer error interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 10033 * | | |1 = Transfer error interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 10034 * |[3] |TMR0IEN |Timer0 Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 10035 * | | |This field is used to enable TMR0 interrupt enable.
sahilmgandhi 18:6a4db94011d3 10036 * | | |0 = Timer0 interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 10037 * | | |1 = Timer0 interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 10038 * |[4] |TMR1IEN |Timer1 Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 10039 * | | |This field is used to enable the TMR1 interrupt.
sahilmgandhi 18:6a4db94011d3 10040 * | | |0 = Timer1 interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 10041 * | | |1 = Timer1 interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 10042 * |[5] |TMR2IEN |Timer2 Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 10043 * | | |This field is used for TMR2 interrupt enable.
sahilmgandhi 18:6a4db94011d3 10044 * | | |0 = Timer2 interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 10045 * | | |1 = Timer2 interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 10046 * |[6] |BGTIEN |Block Guard Time Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 10047 * | | |This field is used for block guard time interrupt enable.
sahilmgandhi 18:6a4db94011d3 10048 * | | |0 = Block guard time Disabled.
sahilmgandhi 18:6a4db94011d3 10049 * | | |1 = Block guard time Enabled.
sahilmgandhi 18:6a4db94011d3 10050 * |[7] |CDIEN |Card Detect Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 10051 * | | |This field is used for card detect interrupt enable. The card detect status is CINSERT(SC_STATUS[12])
sahilmgandhi 18:6a4db94011d3 10052 * | | |0 = Card detect interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 10053 * | | |1 = Card detect interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 10054 * |[8] |INITIEN |Initial End Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 10055 * | | |This field is used for activation (ACTEN(SC_ALTCTL[3] = 1)), deactivation ((DACTEN SC_ALTCTL[2]) = 1) and warm reset (WARSTEN (SC_ALTCTL [4])) sequence interrupt enable.
sahilmgandhi 18:6a4db94011d3 10056 * | | |0 = Initial end interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 10057 * | | |1 = Initial end interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 10058 * |[9] |RXTOIF |Receiver Buffer Time-Out Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 10059 * | | |This field is used for receiver buffer time-out interrupt enable.
sahilmgandhi 18:6a4db94011d3 10060 * | | |0 = Receiver buffer time-out interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 10061 * | | |1 = Receiver buffer time-out interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 10062 * |[10] |ACERRIEN |Auto Convention Error Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 10063 * | | |This field is used for auto-convention error interrupt enable.
sahilmgandhi 18:6a4db94011d3 10064 * | | |0 = Auto-convention error interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 10065 * | | |1 = Auto-convention error interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 10066 * @var SC_T::INTSTS
sahilmgandhi 18:6a4db94011d3 10067 * Offset: 0x1C SC Interrupt Status Register.
sahilmgandhi 18:6a4db94011d3 10068 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 10069 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 10070 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 10071 * |[0] |RDAIF |Receive Data Reach Interrupt Status Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 10072 * | | |This field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.
sahilmgandhi 18:6a4db94011d3 10073 * | | |Note: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]).
sahilmgandhi 18:6a4db94011d3 10074 * | | |If software reads data from SC_DAT and receiver buffer data byte number is less than RXTRGLV (SC_CTL[7:6]), this bit will be cleared automatically.
sahilmgandhi 18:6a4db94011d3 10075 * |[1] |TBEIF |Transmit Buffer Empty Interrupt Status Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 10076 * | | |This field is used for transmit buffer empty interrupt status flag.
sahilmgandhi 18:6a4db94011d3 10077 * | | |Note: This field is the status flag of transmit buffer empty state.
sahilmgandhi 18:6a4db94011d3 10078 * | | |If software wants to clear this bit, software must write data to DAT(SC_DAT[7:0]) buffer and then this bit will be cleared automatically.
sahilmgandhi 18:6a4db94011d3 10079 * |[2] |TERRIF |Transfer Error Interrupt Status Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 10080 * | | |This field is used for transfer error interrupt status flag.
sahilmgandhi 18:6a4db94011d3 10081 * | | |The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]) and receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22]) and transmitter retry over limit error TXOVERR(SC_STATUS[30]).
sahilmgandhi 18:6a4db94011d3 10082 * | | |Note: This field is the status flag of
sahilmgandhi 18:6a4db94011d3 10083 * | | |BEF(SC_STATUS[6]), FEF(SC_STATUS[5]), PEF(SC_STATUS[4]), RXOV(SC_STATUS[0]), TXOV(SC_STATUS[8]), RXOVERR(SC_STATUS[22]) or TXOVERR(SC_STATUS[30]).
sahilmgandhi 18:6a4db94011d3 10084 * | | |So, if software wants to clear this bit, software must write 1 to each field.
sahilmgandhi 18:6a4db94011d3 10085 * |[3] |TMR0IF |Timer0 Interrupt Status Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 10086 * | | |This field is used for TMR0 interrupt status flag.
sahilmgandhi 18:6a4db94011d3 10087 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 10088 * |[4] |TMR1IF |Timer1 Interrupt Status Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 10089 * | | |This field is used for TMR1 interrupt status flag.
sahilmgandhi 18:6a4db94011d3 10090 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 10091 * |[5] |TMR2IF |Timer2 Interrupt Status Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 10092 * | | |This field is used for TMR2 interrupt status flag.
sahilmgandhi 18:6a4db94011d3 10093 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 10094 * |[6] |BGTIF |Block Guard Time Interrupt Status Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 10095 * | | |This field is used for block guard time interrupt status flag.
sahilmgandhi 18:6a4db94011d3 10096 * | | |Note1: This bit is valid when RXBGTEN (SC_ALTCTL[12]) is enabled.
sahilmgandhi 18:6a4db94011d3 10097 * | | |Note2: This bit is read only, but it can be cleared by writing "1" to it.
sahilmgandhi 18:6a4db94011d3 10098 * |[7] |CDIF |Card Detect Interrupt Status Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 10099 * | | |This field is used for card detect interrupt status flag.
sahilmgandhi 18:6a4db94011d3 10100 * | | |The card detect status is CINSERT (SC_STATUS[12]) and CREMOVE(SC_STATUS[11]).
sahilmgandhi 18:6a4db94011d3 10101 * | | |Note:
sahilmgandhi 18:6a4db94011d3 10102 * | | |This field is the status flag of CINSERT(SC_STATUS[12]) or CREMOVE(SC_STATUS[11])].
sahilmgandhi 18:6a4db94011d3 10103 * | | |So if software wants to clear this bit, software must write 1 to this field.
sahilmgandhi 18:6a4db94011d3 10104 * |[8] |INITIF |Initial End Interrupt Status Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 10105 * | | |This field is used for activation (ACTEN(SC_ALTCTL[3])), deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.
sahilmgandhi 18:6a4db94011d3 10106 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 10107 * |[9] |RBTOIF |Receiver Buffer Time-Out Interrupt Status Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 10108 * | | |This field is used for receiver buffer time-out interrupt status flag.
sahilmgandhi 18:6a4db94011d3 10109 * | | |Note: This field is the status flag of receiver buffer time-out state.
sahilmgandhi 18:6a4db94011d3 10110 * | | |If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_DAT buffer,.
sahilmgandhi 18:6a4db94011d3 10111 * |[10] |ACERRIF |Auto Convention Error Interrupt Status Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 10112 * | | |This field indicates auto convention sequence error.
sahilmgandhi 18:6a4db94011d3 10113 * | | |If the received TS at ATR state is neither 0x3B nor 0x3F, this bit will be set.
sahilmgandhi 18:6a4db94011d3 10114 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 10115 * @var SC_T::STATUS
sahilmgandhi 18:6a4db94011d3 10116 * Offset: 0x20 SC Status Register.
sahilmgandhi 18:6a4db94011d3 10117 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 10118 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 10119 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 10120 * |[0] |RXOV |RX Overflow Error Status Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 10121 * | | |This bit is set when RX buffer overflow.
sahilmgandhi 18:6a4db94011d3 10122 * | | |If the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.
sahilmgandhi 18:6a4db94011d3 10123 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 10124 * |[1] |RXEMPTY |Receiver Buffer Empty Status Flag(Read Only)
sahilmgandhi 18:6a4db94011d3 10125 * | | |This bit indicates RX buffer empty or not.
sahilmgandhi 18:6a4db94011d3 10126 * | | |When the last byte of Rx buffer has been read by CPU, hardware sets this bit high.
sahilmgandhi 18:6a4db94011d3 10127 * | | |It will be cleared when SC receives any new data.
sahilmgandhi 18:6a4db94011d3 10128 * |[2] |RXFULL |Receiver Buffer Full Status Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 10129 * | | |This bit indicates RX buffer full or not.
sahilmgandhi 18:6a4db94011d3 10130 * | | |This bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
sahilmgandhi 18:6a4db94011d3 10131 * |[4] |PEF |Receiver Parity Error Status Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 10132 * | | |This bit is set to logic 1 whenever the received character does not have a valid
sahilmgandhi 18:6a4db94011d3 10133 * | | |"parity bit".
sahilmgandhi 18:6a4db94011d3 10134 * | | |Note1:
sahilmgandhi 18:6a4db94011d3 10135 * | | |This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 10136 * | | |Note2:
sahilmgandhi 18:6a4db94011d3 10137 * | | |If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
sahilmgandhi 18:6a4db94011d3 10138 * |[5] |FEF |Receiver Frame Error Status Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 10139 * | | |This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
sahilmgandhi 18:6a4db94011d3 10140 * | | |Note1:
sahilmgandhi 18:6a4db94011d3 10141 * | | |This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 10142 * | | |Note2:
sahilmgandhi 18:6a4db94011d3 10143 * | | |If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
sahilmgandhi 18:6a4db94011d3 10144 * |[6] |BEF |Receiver Break Error Status Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 10145 * | | |This bit is set to logic 1 whenever the received data input (RX) held in the "spacing state" (logic 0) is longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits).
sahilmgandhi 18:6a4db94011d3 10146 * | | |.
sahilmgandhi 18:6a4db94011d3 10147 * | | |Note1:
sahilmgandhi 18:6a4db94011d3 10148 * | | |This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 10149 * | | |Note2:
sahilmgandhi 18:6a4db94011d3 10150 * | | |If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
sahilmgandhi 18:6a4db94011d3 10151 * |[8] |TXOV |TX Overflow Error Interrupt Status Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 10152 * | | |If TX buffer is full, an additional write to DAT(SC_DAT[7:0]) will cause this bit be set to "1" by hardware.
sahilmgandhi 18:6a4db94011d3 10153 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 10154 * |[9] |TXEMPTY |Transmit Buffer Empty Status Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 10155 * | | |This bit indicates TX buffer empty or not.
sahilmgandhi 18:6a4db94011d3 10156 * | | |When the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high.
sahilmgandhi 18:6a4db94011d3 10157 * | | |It will be cleared when writing data into DAT(SC_DAT[7:0]) (TX buffer not empty).
sahilmgandhi 18:6a4db94011d3 10158 * |[10] |TXFULL |Transmit Buffer Full Status Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 10159 * | | |This bit indicates TX buffer full or not.This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
sahilmgandhi 18:6a4db94011d3 10160 * |[11] |CREMOVE |Card Detect Removal Status Of SC_CD Pin (Read Only)
sahilmgandhi 18:6a4db94011d3 10161 * | | |This bit is set whenever card has been removal.
sahilmgandhi 18:6a4db94011d3 10162 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 10163 * | | |1 = Card removed.
sahilmgandhi 18:6a4db94011d3 10164 * | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
sahilmgandhi 18:6a4db94011d3 10165 * | | |Note2: Card detect engine will start after SCEN (SC_CTL[0])set.
sahilmgandhi 18:6a4db94011d3 10166 * |[12] |CINSERT |Card Detect Insert Status Of SC_CD Pin (Read Only)
sahilmgandhi 18:6a4db94011d3 10167 * | | |This bit is set whenever card has been inserted.
sahilmgandhi 18:6a4db94011d3 10168 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 10169 * | | |1 = Card insert.
sahilmgandhi 18:6a4db94011d3 10170 * | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
sahilmgandhi 18:6a4db94011d3 10171 * | | |Note2: The
sahilmgandhi 18:6a4db94011d3 10172 * | | |card detect engine will start after SCEN (SC_CTL[0]) set.
sahilmgandhi 18:6a4db94011d3 10173 * |[13] |CDPINSTS |Card Detect Status Of SC_CD Pin Status (Read Only)
sahilmgandhi 18:6a4db94011d3 10174 * | | |This bit is the pin status flag of SC_CD
sahilmgandhi 18:6a4db94011d3 10175 * | | |0 = The SC_CD pin state at low.
sahilmgandhi 18:6a4db94011d3 10176 * | | |1 = The SC_CD pin state at high.
sahilmgandhi 18:6a4db94011d3 10177 * |[17:16] |RXPOINT |Receiver Buffer Pointer Status Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 10178 * | | |This field indicates the RX buffer pointer status flag.
sahilmgandhi 18:6a4db94011d3 10179 * | | |When SC receives one byte from external device, RXPOINT(SC_STATUS[17:16]) increases one.
sahilmgandhi 18:6a4db94011d3 10180 * | | |When one byte of RX buffer is read by CPU, RXPOINT(SC_STATUS[17:16]) decreases one.
sahilmgandhi 18:6a4db94011d3 10181 * |[21] |RXRERR |Receiver Retry Error (Read Only)
sahilmgandhi 18:6a4db94011d3 10182 * | | |This bit is set by hardware when RX has any error and retries transfer.
sahilmgandhi 18:6a4db94011d3 10183 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 10184 * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU.
sahilmgandhi 18:6a4db94011d3 10185 * | | |Note3: If CPU enables receiver retry function by setting RXRTYEN (SC_CTL[19]) , the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
sahilmgandhi 18:6a4db94011d3 10186 * |[22] |RXOVERR |Receiver Over Retry Error (Read Only)
sahilmgandhi 18:6a4db94011d3 10187 * | | |This bit is set by hardware when RX transfer error retry over retry number limit.
sahilmgandhi 18:6a4db94011d3 10188 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 10189 * | | |Note2: If CPU enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
sahilmgandhi 18:6a4db94011d3 10190 * |[23] |RXACT |Receiver In Active Status Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 10191 * | | |This bit is set by hardware when RX transfer is in active.
sahilmgandhi 18:6a4db94011d3 10192 * | | |This bit is cleared automatically when RX transfer is finished.
sahilmgandhi 18:6a4db94011d3 10193 * |[25:24] |TXPOINT |Transmit Buffer Pointer Status Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 10194 * | | |This field indicates the TX buffer pointer status flag.
sahilmgandhi 18:6a4db94011d3 10195 * | | |When CPU writes data into SC_DAT, TXPOINT increases one.
sahilmgandhi 18:6a4db94011d3 10196 * | | |When one byte of TX Buffer is transferred to transmitter shift register, TXPOINT decreases one.
sahilmgandhi 18:6a4db94011d3 10197 * |[29] |TXRERR |Transmitter Retry Error (Read Only)
sahilmgandhi 18:6a4db94011d3 10198 * | | |This bit is set by hardware when transmitter re-transmits.
sahilmgandhi 18:6a4db94011d3 10199 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 10200 * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU.
sahilmgandhi 18:6a4db94011d3 10201 * |[30] |TXOVERR |Transmitter Over Retry Error (Read Only)
sahilmgandhi 18:6a4db94011d3 10202 * | | |This bit is set by hardware when transmitter re-transmits over retry number limitation.
sahilmgandhi 18:6a4db94011d3 10203 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 10204 * |[31] |TXACT |Transmit In Active Status Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 10205 * | | |0 = This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed.
sahilmgandhi 18:6a4db94011d3 10206 * | | |1 = This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted.
sahilmgandhi 18:6a4db94011d3 10207 * @var SC_T::PINCTL
sahilmgandhi 18:6a4db94011d3 10208 * Offset: 0x24 SC Pin Control State Register.
sahilmgandhi 18:6a4db94011d3 10209 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 10210 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 10211 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 10212 * |[0] |PWREN |SC_PWREN Pin Signal
sahilmgandhi 18:6a4db94011d3 10213 * | | |Software can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11])to decide SC_PWR pin is in high or low level.
sahilmgandhi 18:6a4db94011d3 10214 * | | |Write this field to drive SC_PWR pin
sahilmgandhi 18:6a4db94011d3 10215 * | | |Refer PWRINV (SC_PINCTL[11]) description for programming SC_PWR pin voltage level.
sahilmgandhi 18:6a4db94011d3 10216 * | | |Read this field to get SC_PWR pin status.
sahilmgandhi 18:6a4db94011d3 10217 * | | |0 = SC_PWR pin status is low.
sahilmgandhi 18:6a4db94011d3 10218 * | | |1 = SC_PWR pin status is high.
sahilmgandhi 18:6a4db94011d3 10219 * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically.
sahilmgandhi 18:6a4db94011d3 10220 * | | |So don't fill this field when operating in these modes.
sahilmgandhi 18:6a4db94011d3 10221 * |[1] |SCRST |SC_RST Pin Signal
sahilmgandhi 18:6a4db94011d3 10222 * | | |This bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.
sahilmgandhi 18:6a4db94011d3 10223 * | | |Write this field to drive SC_RST pin.
sahilmgandhi 18:6a4db94011d3 10224 * | | |0 = Drive SC_RST pin to low.
sahilmgandhi 18:6a4db94011d3 10225 * | | |1 = Drive SC_RST pin to high.
sahilmgandhi 18:6a4db94011d3 10226 * | | |Read this field to get SC_RST pin status.
sahilmgandhi 18:6a4db94011d3 10227 * | | |0 = SC_RST pin status is low.
sahilmgandhi 18:6a4db94011d3 10228 * | | |1 = SC_RST pin status is high.
sahilmgandhi 18:6a4db94011d3 10229 * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically.
sahilmgandhi 18:6a4db94011d3 10230 * | | |So don't fill this field when operating in these modes.
sahilmgandhi 18:6a4db94011d3 10231 * |[5] |CSTOPLV |SC Clock Stop Level
sahilmgandhi 18:6a4db94011d3 10232 * | | |This field indicates the clock polarity control in clock stop mode.
sahilmgandhi 18:6a4db94011d3 10233 * | | |0 = SC_CLK stopped in low level.
sahilmgandhi 18:6a4db94011d3 10234 * | | |1 = SC_CLK stopped in high level.
sahilmgandhi 18:6a4db94011d3 10235 * |[6] |CLKKEEP |SC Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 10236 * | | |0 = SC clock generation Disabled.
sahilmgandhi 18:6a4db94011d3 10237 * | | |1 = SC clock always keeps free running.
sahilmgandhi 18:6a4db94011d3 10238 * | | |Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically.
sahilmgandhi 18:6a4db94011d3 10239 * | | |So don't fill this field when operating in these modes.
sahilmgandhi 18:6a4db94011d3 10240 * |[9] |SCDOUT |SC Data Output Pin
sahilmgandhi 18:6a4db94011d3 10241 * | | |This bit is the pin status of SCDATOUT but user can drive SCDATOUT pin to high or low by setting this bit.
sahilmgandhi 18:6a4db94011d3 10242 * | | |0 = Drive SCDATOUT pin to low.
sahilmgandhi 18:6a4db94011d3 10243 * | | |1 = Drive SCDATOUT pin to high.
sahilmgandhi 18:6a4db94011d3 10244 * | | |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically.
sahilmgandhi 18:6a4db94011d3 10245 * | | |So don't fill this field when SC is in these modes.
sahilmgandhi 18:6a4db94011d3 10246 * |[11] |PWRINV |SC_POW Pin Inverse
sahilmgandhi 18:6a4db94011d3 10247 * | | |This bit is used for inverse the SC_POW pin.
sahilmgandhi 18:6a4db94011d3 10248 * | | |There are four kinds of combination for SC_POW pin setting by PWRINV(SC_PINCTL[11]) and PWREN(SC_PINCTL[0]).
sahilmgandhi 18:6a4db94011d3 10249 * | | |PWRINV (SC_PINCTL[11]) is bit 1 and PWREN(SC_PINCTL[0]) is bit 0 for SC_POW_Pin as high or low voltage selection.
sahilmgandhi 18:6a4db94011d3 10250 * | | |00 = SC_POW_ Pin is 0.
sahilmgandhi 18:6a4db94011d3 10251 * | | |01 = SC_POW _Pin is 1.
sahilmgandhi 18:6a4db94011d3 10252 * | | |10 = SC_POW _Pin is 1.
sahilmgandhi 18:6a4db94011d3 10253 * | | |11 = SC_POW_ Pin is 0.
sahilmgandhi 18:6a4db94011d3 10254 * | | |Note: Software must select PWRINV (SC_PINCTL[11]) before Smart Card is enabled by SCEN (SC_CTL[0]).
sahilmgandhi 18:6a4db94011d3 10255 * |[12] |SCDOSTS |SC Data Pin Output Status
sahilmgandhi 18:6a4db94011d3 10256 * | | |This bit is the pin status of SCDATOUT
sahilmgandhi 18:6a4db94011d3 10257 * | | |0 = SCDATOUT pin to low.
sahilmgandhi 18:6a4db94011d3 10258 * | | |1 = SCDATOUT pin to high.
sahilmgandhi 18:6a4db94011d3 10259 * | | |Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
sahilmgandhi 18:6a4db94011d3 10260 * | | |This bit is not allowed to program when SC is operated at these modes.
sahilmgandhi 18:6a4db94011d3 10261 * |[16] |DATSTS |This bit is the pin status of SC_DAT
sahilmgandhi 18:6a4db94011d3 10262 * | | |0 = The SC_DAT pin is low.
sahilmgandhi 18:6a4db94011d3 10263 * | | |1 = The SC_DAT pin is high.
sahilmgandhi 18:6a4db94011d3 10264 * |[17] |PWRSTS |SC_PWR Pin Signal
sahilmgandhi 18:6a4db94011d3 10265 * | | |This bit is the pin status of SC_PWR
sahilmgandhi 18:6a4db94011d3 10266 * | | |0 = SC_PWR pin to low.
sahilmgandhi 18:6a4db94011d3 10267 * | | |1 = SC_PWR pin to high.
sahilmgandhi 18:6a4db94011d3 10268 * | | |Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
sahilmgandhi 18:6a4db94011d3 10269 * | | |This bit is not allowed to program when SC is operated at these modes.
sahilmgandhi 18:6a4db94011d3 10270 * |[18] |RSTSTS |SCRST Pin Signals
sahilmgandhi 18:6a4db94011d3 10271 * | | |This bit is the pin status of SC_RST
sahilmgandhi 18:6a4db94011d3 10272 * | | |0 = SC_RST pin is low.
sahilmgandhi 18:6a4db94011d3 10273 * | | |1 = SC_RST pin is high.
sahilmgandhi 18:6a4db94011d3 10274 * | | |Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
sahilmgandhi 18:6a4db94011d3 10275 * | | |This bit is not allowed to program when SC is operated at these modes.
sahilmgandhi 18:6a4db94011d3 10276 * |[30] |SYNC |SYNC Flag Indicator
sahilmgandhi 18:6a4db94011d3 10277 * | | |Due to synchronization, software should check this bit when writing a new value to SC_PINCTL register.
sahilmgandhi 18:6a4db94011d3 10278 * | | |0 = Synchronizing is completion, user can write new data to SC_PINCTL register.
sahilmgandhi 18:6a4db94011d3 10279 * | | |1 = Last value is synchronizing.
sahilmgandhi 18:6a4db94011d3 10280 * | | |Note: This bit is read only.
sahilmgandhi 18:6a4db94011d3 10281 * |[31] |LOOPBK |Loop Back Test
sahilmgandhi 18:6a4db94011d3 10282 * | | |0 = loop back test Disabled.
sahilmgandhi 18:6a4db94011d3 10283 * | | |1 = Enabling loop back test and the internal SCDATOUT will connect to internal SC_DATA_I.
sahilmgandhi 18:6a4db94011d3 10284 * @var SC_T::TMRCTL0
sahilmgandhi 18:6a4db94011d3 10285 * Offset: 0x28 SC Internal Timer Control Register 0.
sahilmgandhi 18:6a4db94011d3 10286 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 10287 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 10288 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 10289 * |[23:0] |CNT |Timer 0 Counter Value (ETU Base)
sahilmgandhi 18:6a4db94011d3 10290 * | | |This field indicates the internal timer operation values.
sahilmgandhi 18:6a4db94011d3 10291 * |[27:24] |OPMODE |Timer 0 Operation Mode Selection
sahilmgandhi 18:6a4db94011d3 10292 * | | |This field indicates the internal 24-bit timer operation selection.
sahilmgandhi 18:6a4db94011d3 10293 * | | |Refer to 6.17.5.4 for programming Timer0
sahilmgandhi 18:6a4db94011d3 10294 * @var SC_T::TMRCTL1
sahilmgandhi 18:6a4db94011d3 10295 * Offset: 0x2C SC Internal Timer Control Register 1.
sahilmgandhi 18:6a4db94011d3 10296 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 10297 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 10298 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 10299 * |[7:0] |CNT |Timer 1 Counter Value (ETU Base)
sahilmgandhi 18:6a4db94011d3 10300 * | | |This field indicates the internal timer operation values.
sahilmgandhi 18:6a4db94011d3 10301 * |[27:24] |OPMODE |Timer 1 Operation Mode Selection
sahilmgandhi 18:6a4db94011d3 10302 * | | |This field indicates the internal 8-bit timer operation selection.
sahilmgandhi 18:6a4db94011d3 10303 * | | |Refer to 6.17.5.4 for programming Timer1
sahilmgandhi 18:6a4db94011d3 10304 * @var SC_T::TMRCTL2
sahilmgandhi 18:6a4db94011d3 10305 * Offset: 0x30 SC Internal Timer Control Register 2.
sahilmgandhi 18:6a4db94011d3 10306 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 10307 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 10308 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 10309 * |[7:0] |CNT |Timer 2 Counter Value (ETU Base)
sahilmgandhi 18:6a4db94011d3 10310 * | | |This field indicates the internal timer operation values.
sahilmgandhi 18:6a4db94011d3 10311 * |[27:24] |OPMODE |Timer 2 Operation Mode Selection
sahilmgandhi 18:6a4db94011d3 10312 * | | |This field indicates the internal 8-bit timer operation selection
sahilmgandhi 18:6a4db94011d3 10313 * | | |Refer to 6.17.5.4 for programming Timer2
sahilmgandhi 18:6a4db94011d3 10314 * @var SC_T::UARTCTL
sahilmgandhi 18:6a4db94011d3 10315 * Offset: 0x34 SC UART Mode Control Register.
sahilmgandhi 18:6a4db94011d3 10316 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 10317 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 10318 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 10319 * |[0] |UARTEN |UART Mode Enable Bit
sahilmgandhi 18:6a4db94011d3 10320 * | | |0 = Smart Card mode.
sahilmgandhi 18:6a4db94011d3 10321 * | | |1 = UART mode.
sahilmgandhi 18:6a4db94011d3 10322 * | | |Note1: When operating in UART mode, user must set CONSEL (SC_CTL[5:4]) = 00 and AUTOCEN(SC_CTL[3]) = 0.
sahilmgandhi 18:6a4db94011d3 10323 * | | |Note2: When operating in Smart Card mode, user must set UARTEN(SC_UARTCTL [0]) = 00.
sahilmgandhi 18:6a4db94011d3 10324 * | | |Note3: When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine.
sahilmgandhi 18:6a4db94011d3 10325 * |[5:4] |WLS10 |Word Length Selection
sahilmgandhi 18:6a4db94011d3 10326 * | | |00 = Word length is 8 bits.
sahilmgandhi 18:6a4db94011d3 10327 * | | |01 = Word length is 7 bits.
sahilmgandhi 18:6a4db94011d3 10328 * | | |10 = Word length is 6 bits.
sahilmgandhi 18:6a4db94011d3 10329 * | | |11 = Word length is 5 bits.
sahilmgandhi 18:6a4db94011d3 10330 * | | |Note: In smart card mode, this WLS must be '00'
sahilmgandhi 18:6a4db94011d3 10331 * |[6] |PBOFF |Parity Bit Disable Control
sahilmgandhi 18:6a4db94011d3 10332 * | | |0 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data.
sahilmgandhi 18:6a4db94011d3 10333 * | | |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer.
sahilmgandhi 18:6a4db94011d3 10334 * | | |Note: In smart card mode, this field must be '0' (default setting is with parity bit)
sahilmgandhi 18:6a4db94011d3 10335 * |[7] |OPE |Odd Parity Enable Bit
sahilmgandhi 18:6a4db94011d3 10336 * | | |0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
sahilmgandhi 18:6a4db94011d3 10337 * | | |1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
sahilmgandhi 18:6a4db94011d3 10338 * | | |Note: This bit has effect only when PBOFF bit is '0'.
sahilmgandhi 18:6a4db94011d3 10339 * @var SC_T::TMRDAT0
sahilmgandhi 18:6a4db94011d3 10340 * Offset: 0x38 SC Timer Current Data Register A.
sahilmgandhi 18:6a4db94011d3 10341 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 10342 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 10343 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 10344 * |[23:0] |CNT0 |Timer0 Current Data Value (Read Only)
sahilmgandhi 18:6a4db94011d3 10345 * | | |This field indicates the current count values of timer0.
sahilmgandhi 18:6a4db94011d3 10346 * @var SC_T::TMRDAT1_2
sahilmgandhi 18:6a4db94011d3 10347 * Offset: 0x3C SC Timer Current Data Register B.
sahilmgandhi 18:6a4db94011d3 10348 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 10349 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 10350 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 10351 * |[7:0] |CNT1 |Timer1 Current Data Value (Read Only)
sahilmgandhi 18:6a4db94011d3 10352 * | | |This field indicates the current count values of timer1.
sahilmgandhi 18:6a4db94011d3 10353 * |[15:8] |CNT2 |Timer2 Current Data Value (Read Only)
sahilmgandhi 18:6a4db94011d3 10354 * | | |This field indicates the current count values of timer2.
sahilmgandhi 18:6a4db94011d3 10355 */
sahilmgandhi 18:6a4db94011d3 10356
sahilmgandhi 18:6a4db94011d3 10357 __IO uint32_t DAT; /* Offset: 0x00 SC Receiving/Transmit Holding Buffer Register. */
sahilmgandhi 18:6a4db94011d3 10358 __IO uint32_t CTL; /* Offset: 0x04 SC Control Register. */
sahilmgandhi 18:6a4db94011d3 10359 __IO uint32_t ALTCTL; /* Offset: 0x08 SC Alternate Control Register. */
sahilmgandhi 18:6a4db94011d3 10360 __IO uint32_t EGT; /* Offset: 0x0C SC Extend Guard Time Register. */
sahilmgandhi 18:6a4db94011d3 10361 __IO uint32_t RXTOUT; /* Offset: 0x10 SC Receive buffer Time-out Register. */
sahilmgandhi 18:6a4db94011d3 10362 __IO uint32_t ETUCTL; /* Offset: 0x14 SC ETU Control Register. */
sahilmgandhi 18:6a4db94011d3 10363 __IO uint32_t INTEN; /* Offset: 0x18 SC Interrupt Enable Control Register. */
sahilmgandhi 18:6a4db94011d3 10364 __IO uint32_t INTSTS; /* Offset: 0x1C SC Interrupt Status Register. */
sahilmgandhi 18:6a4db94011d3 10365 __IO uint32_t STATUS; /* Offset: 0x20 SC Status Register. */
sahilmgandhi 18:6a4db94011d3 10366 __IO uint32_t PINCTL; /* Offset: 0x24 SC Pin Control State Register. */
sahilmgandhi 18:6a4db94011d3 10367 __IO uint32_t TMRCTL0; /* Offset: 0x28 SC Internal Timer Control Register 0. */
sahilmgandhi 18:6a4db94011d3 10368 __IO uint32_t TMRCTL1; /* Offset: 0x2C SC Internal Timer Control Register 1. */
sahilmgandhi 18:6a4db94011d3 10369 __IO uint32_t TMRCTL2; /* Offset: 0x30 SC Internal Timer Control Register 2. */
sahilmgandhi 18:6a4db94011d3 10370 __IO uint32_t UARTCTL; /* Offset: 0x34 SC UART Mode Control Register. */
sahilmgandhi 18:6a4db94011d3 10371 __I uint32_t TMRDAT0; /* Offset: 0x38 SC Timer Current Data Register A. */
sahilmgandhi 18:6a4db94011d3 10372 __I uint32_t TMRDAT1_2; /* Offset: 0x3C SC Timer Current Data Register B. */
sahilmgandhi 18:6a4db94011d3 10373
sahilmgandhi 18:6a4db94011d3 10374 } SC_T;
sahilmgandhi 18:6a4db94011d3 10375
sahilmgandhi 18:6a4db94011d3 10376
sahilmgandhi 18:6a4db94011d3 10377
sahilmgandhi 18:6a4db94011d3 10378 /**
sahilmgandhi 18:6a4db94011d3 10379 @addtogroup SC_CONST SC Bit Field Definition
sahilmgandhi 18:6a4db94011d3 10380 Constant Definitions for SC Controller
sahilmgandhi 18:6a4db94011d3 10381 @{ */
sahilmgandhi 18:6a4db94011d3 10382
sahilmgandhi 18:6a4db94011d3 10383 #define SC_DAT_DAT_Pos (0) /*!< SC_T::DAT: DAT Position */
sahilmgandhi 18:6a4db94011d3 10384 #define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) /*!< SC_T::DAT: DAT Mask */
sahilmgandhi 18:6a4db94011d3 10385
sahilmgandhi 18:6a4db94011d3 10386 #define SC_CTL_SCEN_Pos (0) /*!< SC_T::CTL: SCEN Position */
sahilmgandhi 18:6a4db94011d3 10387 #define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) /*!< SC_T::CTL: SCEN Mask */
sahilmgandhi 18:6a4db94011d3 10388
sahilmgandhi 18:6a4db94011d3 10389 #define SC_CTL_RXOFF_Pos (1) /*!< SC_T::CTL: RXOFF Position */
sahilmgandhi 18:6a4db94011d3 10390 #define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) /*!< SC_T::CTL: RXOFF Mask */
sahilmgandhi 18:6a4db94011d3 10391
sahilmgandhi 18:6a4db94011d3 10392 #define SC_CTL_TXOFF_Pos (2) /*!< SC_T::CTL: TXOFF Position */
sahilmgandhi 18:6a4db94011d3 10393 #define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) /*!< SC_T::CTL: TXOFF Mask */
sahilmgandhi 18:6a4db94011d3 10394
sahilmgandhi 18:6a4db94011d3 10395 #define SC_CTL_AUTOCEN_Pos (3) /*!< SC_T::CTL: AUTOCEN Position */
sahilmgandhi 18:6a4db94011d3 10396 #define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) /*!< SC_T::CTL: AUTOCEN Mask */
sahilmgandhi 18:6a4db94011d3 10397
sahilmgandhi 18:6a4db94011d3 10398 #define SC_CTL_CONSEL_Pos (4) /*!< SC_T::CTL: CONSEL Position */
sahilmgandhi 18:6a4db94011d3 10399 #define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) /*!< SC_T::CTL: CONSEL Mask */
sahilmgandhi 18:6a4db94011d3 10400
sahilmgandhi 18:6a4db94011d3 10401 #define SC_CTL_RXTRGLV_Pos (6) /*!< SC_T::CTL: RXTRGLV Position */
sahilmgandhi 18:6a4db94011d3 10402 #define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) /*!< SC_T::CTL: RXTRGLV Mask */
sahilmgandhi 18:6a4db94011d3 10403
sahilmgandhi 18:6a4db94011d3 10404 #define SC_CTL_BGT_Pos (8) /*!< SC_T::CTL: BGT Position */
sahilmgandhi 18:6a4db94011d3 10405 #define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) /*!< SC_T::CTL: BGT Mask */
sahilmgandhi 18:6a4db94011d3 10406
sahilmgandhi 18:6a4db94011d3 10407 #define SC_CTL_TMRSEL_Pos (13) /*!< SC_T::CTL: TMRSEL Position */
sahilmgandhi 18:6a4db94011d3 10408 #define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) /*!< SC_T::CTL: TMRSEL Mask */
sahilmgandhi 18:6a4db94011d3 10409
sahilmgandhi 18:6a4db94011d3 10410 #define SC_CTL_NSB_Pos (15) /*!< SC_T::CTL: NSB Position */
sahilmgandhi 18:6a4db94011d3 10411 #define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) /*!< SC_T::CTL: NSB Mask */
sahilmgandhi 18:6a4db94011d3 10412
sahilmgandhi 18:6a4db94011d3 10413 #define SC_CTL_RXRTY_Pos (16) /*!< SC_T::CTL: RXRTY Position */
sahilmgandhi 18:6a4db94011d3 10414 #define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) /*!< SC_T::CTL: RXRTY Mask */
sahilmgandhi 18:6a4db94011d3 10415
sahilmgandhi 18:6a4db94011d3 10416 #define SC_CTL_RXRTYEN_Pos (19) /*!< SC_T::CTL: RXRTYEN Position */
sahilmgandhi 18:6a4db94011d3 10417 #define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) /*!< SC_T::CTL: RXRTYEN Mask */
sahilmgandhi 18:6a4db94011d3 10418
sahilmgandhi 18:6a4db94011d3 10419 #define SC_CTL_TXRTY_Pos (20) /*!< SC_T::CTL: TXRTY Position */
sahilmgandhi 18:6a4db94011d3 10420 #define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) /*!< SC_T::CTL: TXRTY Mask */
sahilmgandhi 18:6a4db94011d3 10421
sahilmgandhi 18:6a4db94011d3 10422 #define SC_CTL_TXRTYEN_Pos (23) /*!< SC_T::CTL: TXRTYEN Position */
sahilmgandhi 18:6a4db94011d3 10423 #define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) /*!< SC_T::CTL: TXRTYEN Mask */
sahilmgandhi 18:6a4db94011d3 10424
sahilmgandhi 18:6a4db94011d3 10425 #define SC_CTL_CDDBSEL_Pos (24) /*!< SC_T::CTL: CDDBSEL Position */
sahilmgandhi 18:6a4db94011d3 10426 #define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) /*!< SC_T::CTL: CDDBSEL Mask */
sahilmgandhi 18:6a4db94011d3 10427
sahilmgandhi 18:6a4db94011d3 10428 #define SC_CTL_CDLV_Pos (26) /*!< SC_T::CTL: CDLV Position */
sahilmgandhi 18:6a4db94011d3 10429 #define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) /*!< SC_T::CTL: CDLV Mask */
sahilmgandhi 18:6a4db94011d3 10430
sahilmgandhi 18:6a4db94011d3 10431 #define SC_CTL_SYNC_Pos (30) /*!< SC_T::CTL: SYNC Position */
sahilmgandhi 18:6a4db94011d3 10432 #define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) /*!< SC_T::CTL: SYNC Mask */
sahilmgandhi 18:6a4db94011d3 10433
sahilmgandhi 18:6a4db94011d3 10434 #define SC_CTL_ICEDEBUG_Pos (31) /*!< SC_T::CTL: ICEDEBUG Position */
sahilmgandhi 18:6a4db94011d3 10435 #define SC_CTL_ICEDEBUG_Msk (0x1ul << SC_CTL_ICEDEBUG_Pos) /*!< SC_T::CTL: ICEDEBUG Mask */
sahilmgandhi 18:6a4db94011d3 10436
sahilmgandhi 18:6a4db94011d3 10437 #define SC_ALTCTL_TXRST_Pos (0) /*!< SC_T::ALTCTL: TXRST Position */
sahilmgandhi 18:6a4db94011d3 10438 #define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) /*!< SC_T::ALTCTL: TXRST Mask */
sahilmgandhi 18:6a4db94011d3 10439
sahilmgandhi 18:6a4db94011d3 10440 #define SC_ALTCTL_RXRST_Pos (1) /*!< SC_T::ALTCTL: RXRST Position */
sahilmgandhi 18:6a4db94011d3 10441 #define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) /*!< SC_T::ALTCTL: RXRST Mask */
sahilmgandhi 18:6a4db94011d3 10442
sahilmgandhi 18:6a4db94011d3 10443 #define SC_ALTCTL_DACTEN_Pos (2) /*!< SC_T::ALTCTL: DACTEN Position */
sahilmgandhi 18:6a4db94011d3 10444 #define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) /*!< SC_T::ALTCTL: DACTEN Mask */
sahilmgandhi 18:6a4db94011d3 10445
sahilmgandhi 18:6a4db94011d3 10446 #define SC_ALTCTL_ACTEN_Pos (3) /*!< SC_T::ALTCTL: ACTEN Position */
sahilmgandhi 18:6a4db94011d3 10447 #define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) /*!< SC_T::ALTCTL: ACTEN Mask */
sahilmgandhi 18:6a4db94011d3 10448
sahilmgandhi 18:6a4db94011d3 10449 #define SC_ALTCTL_WARSTEN_Pos (4) /*!< SC_T::ALTCTL: WARSTEN Position */
sahilmgandhi 18:6a4db94011d3 10450 #define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) /*!< SC_T::ALTCTL: WARSTEN Mask */
sahilmgandhi 18:6a4db94011d3 10451
sahilmgandhi 18:6a4db94011d3 10452 #define SC_ALTCTL_CNTEN0_Pos (5) /*!< SC_T::ALTCTL: CNTEN0 Position */
sahilmgandhi 18:6a4db94011d3 10453 #define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) /*!< SC_T::ALTCTL: CNTEN0 Mask */
sahilmgandhi 18:6a4db94011d3 10454
sahilmgandhi 18:6a4db94011d3 10455 #define SC_ALTCTL_CNTEN1_Pos (6) /*!< SC_T::ALTCTL: CNTEN1 Position */
sahilmgandhi 18:6a4db94011d3 10456 #define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) /*!< SC_T::ALTCTL: CNTEN1 Mask */
sahilmgandhi 18:6a4db94011d3 10457
sahilmgandhi 18:6a4db94011d3 10458 #define SC_ALTCTL_CNTEN2_Pos (7) /*!< SC_T::ALTCTL: CNTEN2 Position */
sahilmgandhi 18:6a4db94011d3 10459 #define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) /*!< SC_T::ALTCTL: CNTEN2 Mask */
sahilmgandhi 18:6a4db94011d3 10460
sahilmgandhi 18:6a4db94011d3 10461 #define SC_ALTCTL_INITSEL_Pos (8) /*!< SC_T::ALTCTL: INITSEL Position */
sahilmgandhi 18:6a4db94011d3 10462 #define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) /*!< SC_T::ALTCTL: INITSEL Mask */
sahilmgandhi 18:6a4db94011d3 10463
sahilmgandhi 18:6a4db94011d3 10464 #define SC_ALTCTL_ADACEN_Pos (11) /*!< SC_T::ALTCTL: ADACEN Position */
sahilmgandhi 18:6a4db94011d3 10465 #define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) /*!< SC_T::ALTCTL: ADACEN Mask */
sahilmgandhi 18:6a4db94011d3 10466
sahilmgandhi 18:6a4db94011d3 10467 #define SC_ALTCTL_RXBGTEN_Pos (12) /*!< SC_T::ALTCTL: RXBGTEN Position */
sahilmgandhi 18:6a4db94011d3 10468 #define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) /*!< SC_T::ALTCTL: RXBGTEN Mask */
sahilmgandhi 18:6a4db94011d3 10469
sahilmgandhi 18:6a4db94011d3 10470 #define SC_ALTCTL_ACTSTS0_Pos (13) /*!< SC_T::ALTCTL: ACTSTS0 Position */
sahilmgandhi 18:6a4db94011d3 10471 #define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) /*!< SC_T::ALTCTL: ACTSTS0 Mask */
sahilmgandhi 18:6a4db94011d3 10472
sahilmgandhi 18:6a4db94011d3 10473 #define SC_ALTCTL_ACTSTS1_Pos (14) /*!< SC_T::ALTCTL: ACTSTS1 Position */
sahilmgandhi 18:6a4db94011d3 10474 #define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) /*!< SC_T::ALTCTL: ACTSTS1 Mask */
sahilmgandhi 18:6a4db94011d3 10475
sahilmgandhi 18:6a4db94011d3 10476 #define SC_ALTCTL_ACTSTS2_Pos (15) /*!< SC_T::ALTCTL: ACTSTS2 Position */
sahilmgandhi 18:6a4db94011d3 10477 #define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) /*!< SC_T::ALTCTL: ACTSTS2 Mask */
sahilmgandhi 18:6a4db94011d3 10478
sahilmgandhi 18:6a4db94011d3 10479 #define SC_ALTCTL_OUTSEL_Pos (16) /*!< SC_T::ALTCTL: OUTSEL Position */
sahilmgandhi 18:6a4db94011d3 10480 #define SC_ALTCTL_OUTSEL_Msk (0x1ul << SC_ALTCTL_OUTSEL_Pos) /*!< SC_T::ALTCTL: OUTSEL Mask */
sahilmgandhi 18:6a4db94011d3 10481
sahilmgandhi 18:6a4db94011d3 10482 #define SC_EGT_EGT_Pos (0) /*!< SC_T::EGT: EGT Position */
sahilmgandhi 18:6a4db94011d3 10483 #define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) /*!< SC_T::EGT: EGT Mask */
sahilmgandhi 18:6a4db94011d3 10484
sahilmgandhi 18:6a4db94011d3 10485 #define SC_RXTOUT_RFTM_Pos (0) /*!< SC_T::RXTOUT: RFTM Position */
sahilmgandhi 18:6a4db94011d3 10486 #define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) /*!< SC_T::RXTOUT: RFTM Mask */
sahilmgandhi 18:6a4db94011d3 10487
sahilmgandhi 18:6a4db94011d3 10488 #define SC_ETUCTL_ETURDIV_Pos (0) /*!< SC_T::ETUCTL: ETURDIV_ Position */
sahilmgandhi 18:6a4db94011d3 10489 #define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) /*!< SC_T::ETUCTL: ETURDIV_ Mask */
sahilmgandhi 18:6a4db94011d3 10490
sahilmgandhi 18:6a4db94011d3 10491 #define SC_ETUCTL_CMPEN_Pos (15) /*!< SC_T::ETUCTL: CMPEN_ Position */
sahilmgandhi 18:6a4db94011d3 10492 #define SC_ETUCTL_CMPEN_Msk (0x1ul << SC_ETUCTL_CMPEN_Pos) /*!< SC_T::ETUCTL: CMPEN_ Mask */
sahilmgandhi 18:6a4db94011d3 10493
sahilmgandhi 18:6a4db94011d3 10494 #define SC_INTEN_RDAIEN_Pos (0) /*!< SC_T::INTEN: RDAIEN Position */
sahilmgandhi 18:6a4db94011d3 10495 #define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) /*!< SC_T::INTEN: RDAIEN Mask */
sahilmgandhi 18:6a4db94011d3 10496
sahilmgandhi 18:6a4db94011d3 10497 #define SC_INTEN_TBEIEN_Pos (1) /*!< SC_T::INTEN: TBEIEN Position */
sahilmgandhi 18:6a4db94011d3 10498 #define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) /*!< SC_T::INTEN: TBEIEN Mask */
sahilmgandhi 18:6a4db94011d3 10499
sahilmgandhi 18:6a4db94011d3 10500 #define SC_INTEN_TERRIEN_Pos (2) /*!< SC_T::INTEN: TERRIEN Position */
sahilmgandhi 18:6a4db94011d3 10501 #define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) /*!< SC_T::INTEN: TERRIEN Mask */
sahilmgandhi 18:6a4db94011d3 10502
sahilmgandhi 18:6a4db94011d3 10503 #define SC_INTEN_TMR0IEN_Pos (3) /*!< SC_T::INTEN: TMR0IEN_Position */
sahilmgandhi 18:6a4db94011d3 10504 #define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) /*!< SC_T::INTEN: TMR0IEN Mask */
sahilmgandhi 18:6a4db94011d3 10505
sahilmgandhi 18:6a4db94011d3 10506 #define SC_INTEN_TMR1IEN_Pos (4) /*!< SC_T::INTEN: TMR1IEN Position */
sahilmgandhi 18:6a4db94011d3 10507 #define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) /*!< SC_T::INTEN: TMR1IEN Mask */
sahilmgandhi 18:6a4db94011d3 10508
sahilmgandhi 18:6a4db94011d3 10509 #define SC_INTEN_TMR2IEN_Pos (5) /*!< SC_T::INTEN: TMR2IEN Position */
sahilmgandhi 18:6a4db94011d3 10510 #define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) /*!< SC_T::INTEN: TMR2IEN Mask */
sahilmgandhi 18:6a4db94011d3 10511
sahilmgandhi 18:6a4db94011d3 10512 #define SC_INTEN_BGTIEN_Pos (6) /*!< SC_T::INTEN: BGTIEN Position */
sahilmgandhi 18:6a4db94011d3 10513 #define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) /*!< SC_T::INTEN: BGTIEN Mask */
sahilmgandhi 18:6a4db94011d3 10514
sahilmgandhi 18:6a4db94011d3 10515 #define SC_INTEN_CDIEN_Pos (7) /*!< SC_T::INTEN: CDIEN Position */
sahilmgandhi 18:6a4db94011d3 10516 #define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) /*!< SC_T::INTEN: CDIEN Mask */
sahilmgandhi 18:6a4db94011d3 10517
sahilmgandhi 18:6a4db94011d3 10518 #define SC_INTEN_INITIEN_Pos (8) /*!< SC_T::INTEN: INITIEN Position */
sahilmgandhi 18:6a4db94011d3 10519 #define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) /*!< SC_T::INTEN: INITIEN Mask */
sahilmgandhi 18:6a4db94011d3 10520
sahilmgandhi 18:6a4db94011d3 10521 #define SC_INTEN_RXTOIF_Pos (9) /*!< SC_T::INTEN: RXTOIF Position */
sahilmgandhi 18:6a4db94011d3 10522 #define SC_INTEN_RXTOIF_Msk (0x1ul << SC_INTEN_RXTOIF_Pos) /*!< SC_T::INTEN: RXTOIF Mask */
sahilmgandhi 18:6a4db94011d3 10523
sahilmgandhi 18:6a4db94011d3 10524 #define SC_INTEN_ACERRIEN_Pos (10) /*!< SC_T::INTEN: ACERRIEN Position */
sahilmgandhi 18:6a4db94011d3 10525 #define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) /*!< SC_T::INTEN: ACERRIEN Mask */
sahilmgandhi 18:6a4db94011d3 10526
sahilmgandhi 18:6a4db94011d3 10527 #define SC_INTSTS_RDAIF_Pos (0) /*!< SC_T::INTSTS: RDAIF Position */
sahilmgandhi 18:6a4db94011d3 10528 #define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) /*!< SC_T::INTSTS: RDAIF Mask */
sahilmgandhi 18:6a4db94011d3 10529
sahilmgandhi 18:6a4db94011d3 10530 #define SC_INTSTS_TBEIF_Pos (1) /*!< SC_T::INTSTS: TBEIF Position */
sahilmgandhi 18:6a4db94011d3 10531 #define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) /*!< SC_T::INTSTS: TBEIF Mask */
sahilmgandhi 18:6a4db94011d3 10532
sahilmgandhi 18:6a4db94011d3 10533 #define SC_INTSTS_TERRIF_Pos (2) /*!< SC_T::INTSTS: TERRIF Position */
sahilmgandhi 18:6a4db94011d3 10534 #define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) /*!< SC_T::INTSTS: TERRIF Mask */
sahilmgandhi 18:6a4db94011d3 10535
sahilmgandhi 18:6a4db94011d3 10536 #define SC_INTSTS_TMR0IF_Pos (3) /*!< SC_T::INTSTS: TMR0IF Position */
sahilmgandhi 18:6a4db94011d3 10537 #define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) /*!< SC_T::INTSTS: TMR0IF Mask */
sahilmgandhi 18:6a4db94011d3 10538
sahilmgandhi 18:6a4db94011d3 10539 #define SC_INTSTS_TMR1IF_Pos (4) /*!< SC_T::INTSTS: TMR1IF Position */
sahilmgandhi 18:6a4db94011d3 10540 #define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) /*!< SC_T::INTSTS: TMR1IF Mask */
sahilmgandhi 18:6a4db94011d3 10541
sahilmgandhi 18:6a4db94011d3 10542 #define SC_INTSTS_TMR2IF_Pos (5) /*!< SC_T::INTSTS: TMR2IF Position */
sahilmgandhi 18:6a4db94011d3 10543 #define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) /*!< SC_T::INTSTS: TMR2IF Mask */
sahilmgandhi 18:6a4db94011d3 10544
sahilmgandhi 18:6a4db94011d3 10545 #define SC_INTSTS_BGTIF_Pos (6) /*!< SC_T::INTSTS: BGTIF Position */
sahilmgandhi 18:6a4db94011d3 10546 #define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) /*!< SC_T::INTSTS: BGTIF Mask */
sahilmgandhi 18:6a4db94011d3 10547
sahilmgandhi 18:6a4db94011d3 10548 #define SC_INTSTS_CDIF_Pos (7) /*!< SC_T::INTSTS: CDIF Position */
sahilmgandhi 18:6a4db94011d3 10549 #define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) /*!< SC_T::INTSTS: CDIF Mask */
sahilmgandhi 18:6a4db94011d3 10550
sahilmgandhi 18:6a4db94011d3 10551 #define SC_INTSTS_INITIF_Pos (8) /*!< SC_T::INTSTS: INITIF Position */
sahilmgandhi 18:6a4db94011d3 10552 #define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) /*!< SC_T::INTSTS: INITIF Mask */
sahilmgandhi 18:6a4db94011d3 10553
sahilmgandhi 18:6a4db94011d3 10554 #define SC_INTSTS_RBTOIF_Pos (9) /*!< SC_T::INTSTS: RBTOIF Position */
sahilmgandhi 18:6a4db94011d3 10555 #define SC_INTSTS_RBTOIF_Msk (0x1ul << SC_INTSTS_RBTOIF_Pos) /*!< SC_T::INTSTS: RBTOIF Mask */
sahilmgandhi 18:6a4db94011d3 10556
sahilmgandhi 18:6a4db94011d3 10557 #define SC_INTSTS_ACERRIF_Pos (10) /*!< SC_T::INTSTS: ACERRIF Position */
sahilmgandhi 18:6a4db94011d3 10558 #define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) /*!< SC_T::INTSTS: ACERRIF Mask */
sahilmgandhi 18:6a4db94011d3 10559
sahilmgandhi 18:6a4db94011d3 10560 #define SC_STATUS_RXOV_Pos (0) /*!< SC_T::STATUS: RXO Position */
sahilmgandhi 18:6a4db94011d3 10561 #define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) /*!< SC_T::STATUS: RXO Mask */
sahilmgandhi 18:6a4db94011d3 10562
sahilmgandhi 18:6a4db94011d3 10563 #define SC_STATUS_RXEMPTY_Pos (1) /*!< SC_T::STATUS: RXEMPTY Position */
sahilmgandhi 18:6a4db94011d3 10564 #define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) /*!< SC_T::STATUS: RXEMPTY Mask */
sahilmgandhi 18:6a4db94011d3 10565
sahilmgandhi 18:6a4db94011d3 10566 #define SC_STATUS_RXFULL_Pos (2) /*!< SC_T::STATUS: RXFULL Position */
sahilmgandhi 18:6a4db94011d3 10567 #define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) /*!< SC_T::STATUS: RXFULL Mask */
sahilmgandhi 18:6a4db94011d3 10568
sahilmgandhi 18:6a4db94011d3 10569 #define SC_STATUS_PEF_Pos (4) /*!< SC_T::STATUS: PEF Position */
sahilmgandhi 18:6a4db94011d3 10570 #define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) /*!< SC_T::STATUS: PEF Mask */
sahilmgandhi 18:6a4db94011d3 10571
sahilmgandhi 18:6a4db94011d3 10572 #define SC_STATUS_FEF_Pos (5) /*!< SC_T::STATUS: FEF Position */
sahilmgandhi 18:6a4db94011d3 10573 #define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) /*!< SC_T::STATUS: FEF Mask */
sahilmgandhi 18:6a4db94011d3 10574
sahilmgandhi 18:6a4db94011d3 10575 #define SC_STATUS_BEF_Pos (6) /*!< SC_T::STATUS: BEF Position */
sahilmgandhi 18:6a4db94011d3 10576 #define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) /*!< SC_T::STATUS: BEF Mask */
sahilmgandhi 18:6a4db94011d3 10577
sahilmgandhi 18:6a4db94011d3 10578 #define SC_STATUS_TXOV_Pos (8) /*!< SC_T::STATUS: TXOV Position */
sahilmgandhi 18:6a4db94011d3 10579 #define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) /*!< SC_T::STATUS: TXOV Mask */
sahilmgandhi 18:6a4db94011d3 10580
sahilmgandhi 18:6a4db94011d3 10581 #define SC_STATUS_TXEMPTY_Pos (9) /*!< SC_T::STATUS: TXEMPTY Position */
sahilmgandhi 18:6a4db94011d3 10582 #define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) /*!< SC_T::STATUS: TXEMPTY Mask */
sahilmgandhi 18:6a4db94011d3 10583
sahilmgandhi 18:6a4db94011d3 10584 #define SC_STATUS_TXFULL_Pos (10) /*!< SC_T::STATUS: TXFULL Position */
sahilmgandhi 18:6a4db94011d3 10585 #define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) /*!< SC_T::STATUS: TXFULL Mask */
sahilmgandhi 18:6a4db94011d3 10586
sahilmgandhi 18:6a4db94011d3 10587 #define SC_STATUS_CREMOVE_Pos (11) /*!< SC_T::STATUS: CREMOVE Position */
sahilmgandhi 18:6a4db94011d3 10588 #define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) /*!< SC_T::STATUS: CREMOVE Mask */
sahilmgandhi 18:6a4db94011d3 10589
sahilmgandhi 18:6a4db94011d3 10590 #define SC_STATUS_CINSERT_Pos (12) /*!< SC_T::STATUS: CINSERT Position */
sahilmgandhi 18:6a4db94011d3 10591 #define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) /*!< SC_T::STATUS: CINSERT Mask */
sahilmgandhi 18:6a4db94011d3 10592
sahilmgandhi 18:6a4db94011d3 10593 #define SC_STATUS_CDPINSTS_Pos (13) /*!< SC_T::STATUS: CDPINSTS Position */
sahilmgandhi 18:6a4db94011d3 10594 #define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) /*!< SC_T::STATUS: CDPINSTS Mask */
sahilmgandhi 18:6a4db94011d3 10595
sahilmgandhi 18:6a4db94011d3 10596 #define SC_STATUS_RXPOINT_Pos (16) /*!< SC_T::STATUS: RXPOINT Position */
sahilmgandhi 18:6a4db94011d3 10597 #define SC_STATUS_RXPOINT_Msk (0x3ul << SC_STATUS_RXPOINT_Pos) /*!< SC_T::STATUS: RXPOINT Mask */
sahilmgandhi 18:6a4db94011d3 10598
sahilmgandhi 18:6a4db94011d3 10599 #define SC_STATUS_RXRERR_Pos (21) /*!< SC_T::STATUS: RXRERR Position */
sahilmgandhi 18:6a4db94011d3 10600 #define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) /*!< SC_T::STATUS: RXRERR Mask */
sahilmgandhi 18:6a4db94011d3 10601
sahilmgandhi 18:6a4db94011d3 10602 #define SC_STATUS_RXOVERR_Pos (22) /*!< SC_T::STATUS: RXOVERR Position */
sahilmgandhi 18:6a4db94011d3 10603 #define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) /*!< SC_T::STATUS: RXOVERR Mask */
sahilmgandhi 18:6a4db94011d3 10604
sahilmgandhi 18:6a4db94011d3 10605 #define SC_STATUS_RXACT_Pos (23) /*!< SC_T::STATUS: RXACT Position */
sahilmgandhi 18:6a4db94011d3 10606 #define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) /*!< SC_T::STATUS: RXACT Msk */
sahilmgandhi 18:6a4db94011d3 10607
sahilmgandhi 18:6a4db94011d3 10608 #define SC_STATUS_TXPOINT_Pos (24) /*!< SC_T::STATUS: TXPOINT Position */
sahilmgandhi 18:6a4db94011d3 10609 #define SC_STATUS_TXPOINT_Msk (0x3ul << SC_STATUS_TXPOINT_Pos) /*!< SC_T::STATUS: TXPOINT Msk */
sahilmgandhi 18:6a4db94011d3 10610
sahilmgandhi 18:6a4db94011d3 10611 #define SC_STATUS_TXRERR_Pos (29) /*!< SC_T::STATUS: TXRERR Position */
sahilmgandhi 18:6a4db94011d3 10612 #define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) /*!< SC_T::STATUS: TXRERR Msk */
sahilmgandhi 18:6a4db94011d3 10613
sahilmgandhi 18:6a4db94011d3 10614 #define SC_STATUS_TXOVERR_Pos (30) /*!< SC_T::STATUS: TXOVERR_ Position */
sahilmgandhi 18:6a4db94011d3 10615 #define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) /*!< SC_T::STATUS: TXOVERR_ Msk */
sahilmgandhi 18:6a4db94011d3 10616
sahilmgandhi 18:6a4db94011d3 10617 #define SC_STATUS_TXACT_Pos (31) /*!< SC_T::STATUS: TXACT Position */
sahilmgandhi 18:6a4db94011d3 10618 #define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) /*!< SC_T::STATUS: TXACT Msk */
sahilmgandhi 18:6a4db94011d3 10619
sahilmgandhi 18:6a4db94011d3 10620 #define SC_PINCTL_PWREN_Pos (0) /*!< SC_T::PINCTL: PWREN Position */
sahilmgandhi 18:6a4db94011d3 10621 #define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) /*!< SC_T::PINCTL: PWREN Msk */
sahilmgandhi 18:6a4db94011d3 10622
sahilmgandhi 18:6a4db94011d3 10623 #define SC_PINCTL_SCRST_Pos (1) /*!< SC_T::PINCTL: SCRST Position */
sahilmgandhi 18:6a4db94011d3 10624 #define SC_PINCTL_SCRST_Msk (0x1ul << SC_PINCTL_SCRST_Pos) /*!< SC_T::PINCTL: SCRST Msk */
sahilmgandhi 18:6a4db94011d3 10625
sahilmgandhi 18:6a4db94011d3 10626 #define SC_PINCTL_CSTOPLV_Pos (5) /*!< SC_T::PINCTL: CSTOPLV Position */
sahilmgandhi 18:6a4db94011d3 10627 #define SC_PINCTL_CSTOPLV_Msk (0x1ul << SC_PINCTL_CSTOPLV_Pos) /*!< SC_T::PINCTL: CSTOPLV Msk */
sahilmgandhi 18:6a4db94011d3 10628
sahilmgandhi 18:6a4db94011d3 10629 #define SC_PINCTL_CLKKEEP_Pos (6) /*!< SC_T::PINCTL: CLKKEEP Position */
sahilmgandhi 18:6a4db94011d3 10630 #define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) /*!< SC_T::PINCTL: CLKKEEP Msk */
sahilmgandhi 18:6a4db94011d3 10631
sahilmgandhi 18:6a4db94011d3 10632 #define SC_PINCTL_SCDOUT_Pos (9) /*!< SC_T::PINCTL: SCDOUT Position */
sahilmgandhi 18:6a4db94011d3 10633 #define SC_PINCTL_SCDOUT_Msk (0x1ul << SC_PINCTL_SCDOUT_Pos) /*!< SC_T::PINCTL: SCDOUT Msk */
sahilmgandhi 18:6a4db94011d3 10634
sahilmgandhi 18:6a4db94011d3 10635 #define SC_PINCTL_PWRINV_Pos (11) /*!< SC_T::PINCTL: PWRINV Position */
sahilmgandhi 18:6a4db94011d3 10636 #define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) /*!< SC_T::PINCTL: PWRINV Msk */
sahilmgandhi 18:6a4db94011d3 10637
sahilmgandhi 18:6a4db94011d3 10638 #define SC_PINCTL_SCDOSTS_Pos (12) /*!< SC_T::PINCTL: SCDOSTS Position */
sahilmgandhi 18:6a4db94011d3 10639 #define SC_PINCTL_SCDOSTS_Msk (0x1ul << SC_PINCTL_SCDOSTS_Pos) /*!< SC_T::PINCTL: SCDOSTS Msk */
sahilmgandhi 18:6a4db94011d3 10640
sahilmgandhi 18:6a4db94011d3 10641 #define SC_PINCTL_DATSTS_Pos (16) /*!< SC_T::PINCTL: DATSTS Position */
sahilmgandhi 18:6a4db94011d3 10642 #define SC_PINCTL_DATSTS_Msk (0x1ul << SC_PINCTL_DATSTS_Pos) /*!< SC_T::PINCTL: DATSTS Msk */
sahilmgandhi 18:6a4db94011d3 10643
sahilmgandhi 18:6a4db94011d3 10644 #define SC_PINCTL_PWRSTS_Pos (17) /*!< SC_T::PINCTL: PWRSTS Position */
sahilmgandhi 18:6a4db94011d3 10645 #define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) /*!< SC_T::PINCTL: PWRSTS Msk */
sahilmgandhi 18:6a4db94011d3 10646
sahilmgandhi 18:6a4db94011d3 10647 #define SC_PINCTL_RSTSTS_Pos (18) /*!< SC_T::PINCTL: RSTSTS Position */
sahilmgandhi 18:6a4db94011d3 10648 #define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) /*!< SC_T::PINCTL: RSTSTS Msk */
sahilmgandhi 18:6a4db94011d3 10649
sahilmgandhi 18:6a4db94011d3 10650 #define SC_PINCTL_SYNC_Pos (30) /*!< SC_T::PINCTL: SYNC Position */
sahilmgandhi 18:6a4db94011d3 10651 #define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) /*!< SC_T::PINCTL: SYNC Msk */
sahilmgandhi 18:6a4db94011d3 10652
sahilmgandhi 18:6a4db94011d3 10653 #define SC_PINCTL_LOOPBK_Pos (31) /*!< SC_T::PINCTL: LOOPBK Position */
sahilmgandhi 18:6a4db94011d3 10654 #define SC_PINCTL_LOOPBK_Msk (0x1ul << SC_PINCTL_LOOPBK_Pos) /*!< SC_T::PINCTL: LOOPBK Msk */
sahilmgandhi 18:6a4db94011d3 10655
sahilmgandhi 18:6a4db94011d3 10656 #define SC_TMRCTL0_CNT_Pos (0) /*!< SC_T::TMRCTL0: CNT Position */
sahilmgandhi 18:6a4db94011d3 10657 #define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) /*!< SC_T::TMRCTL0: CNT Msk */
sahilmgandhi 18:6a4db94011d3 10658
sahilmgandhi 18:6a4db94011d3 10659 #define SC_TMRCTL0_OPMODE_Pos (24) /*!< SC_T::TMRCTL0: OPMODE Position */
sahilmgandhi 18:6a4db94011d3 10660 #define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) /*!< SC_T::TMRCTL0: OPMODE Msk */
sahilmgandhi 18:6a4db94011d3 10661
sahilmgandhi 18:6a4db94011d3 10662 #define SC_TMRCTL1_CNT_Pos (0) /*!< SC_T::TMRCTL1: CNT Position */
sahilmgandhi 18:6a4db94011d3 10663 #define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) /*!< SC_T::TMRCTL1: CNT Msk */
sahilmgandhi 18:6a4db94011d3 10664
sahilmgandhi 18:6a4db94011d3 10665 #define SC_TMRCTL1_OPMODE_Pos (24) /*!< SC_T::TMRCTL1: OPMODE Position */
sahilmgandhi 18:6a4db94011d3 10666 #define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) /*!< SC_T::TMRCTL1: OPMODE Msk */
sahilmgandhi 18:6a4db94011d3 10667
sahilmgandhi 18:6a4db94011d3 10668 #define SC_TMRCTL2_CNT_Pos (0) /*!< SC_T::TMRCTL2: CNT Position */
sahilmgandhi 18:6a4db94011d3 10669 #define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) /*!< SC_T::TMRCTL2: CNT Msk */
sahilmgandhi 18:6a4db94011d3 10670
sahilmgandhi 18:6a4db94011d3 10671 #define SC_TMRCTL2_OPMODE_Pos (24) /*!< SC_T::TMRCTL2: OPMODE Position */
sahilmgandhi 18:6a4db94011d3 10672 #define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) /*!< SC_T::TMRCTL2: OPMODE Msk */
sahilmgandhi 18:6a4db94011d3 10673
sahilmgandhi 18:6a4db94011d3 10674 #define SC_UARTCTL_UARTEN_Pos (0) /*!< SC_T::UARTCTL: UARTEN Position */
sahilmgandhi 18:6a4db94011d3 10675 #define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) /*!< SC_T::UARTCTL: UARTEN Msk */
sahilmgandhi 18:6a4db94011d3 10676
sahilmgandhi 18:6a4db94011d3 10677 #define SC_UARTCTL_WLS_Pos (4) /*!< SC_T::UARTCTL: WLS Position */
sahilmgandhi 18:6a4db94011d3 10678 #define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS10_Pos) /*!< SC_T::UARTCTL: WLS Msk */
sahilmgandhi 18:6a4db94011d3 10679
sahilmgandhi 18:6a4db94011d3 10680 #define SC_UARTCTL_PBOFF_Pos (6) /*!< SC_T::UARTCTL: PBOFF Position */
sahilmgandhi 18:6a4db94011d3 10681 #define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) /*!< SC_T::UARTCTL: PBOFF Msk */
sahilmgandhi 18:6a4db94011d3 10682
sahilmgandhi 18:6a4db94011d3 10683 #define SC_UARTCTL_OPE_Pos (7) /*!< SC_T::UARTCTL: OPE Position */
sahilmgandhi 18:6a4db94011d3 10684 #define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) /*!< SC_T::UARTCTL: OPE Msk */
sahilmgandhi 18:6a4db94011d3 10685
sahilmgandhi 18:6a4db94011d3 10686 #define SC_TMRDAT0_CNT0_Pos (0) /*!< SC_T::TMRDAT0: CNT0 Position */
sahilmgandhi 18:6a4db94011d3 10687 #define SC_TMRDAT0_CNT0_Msk (0xfffffful << SC_TMRDAT0_CNT0_Pos) /*!< SC_T::TMRDAT0: CNT0 Msk */
sahilmgandhi 18:6a4db94011d3 10688
sahilmgandhi 18:6a4db94011d3 10689 #define SC_TMRDAT1_2_CNT1_Pos (0) /*!< SC_T::TMRDAT1_2: CNT1 Position */
sahilmgandhi 18:6a4db94011d3 10690 #define SC_TMRDAT1_2_CNT1_Msk (0xfful << SC_TMRDAT1_2_CNT1_Pos) /*!< SC_T::TMRDAT1_2: CNT1 Msk */
sahilmgandhi 18:6a4db94011d3 10691
sahilmgandhi 18:6a4db94011d3 10692 #define SC_TMRDAT1_2_CNT2_Pos (8) /*!< SC_T::TMRDAT1_2: CNT2 Position */
sahilmgandhi 18:6a4db94011d3 10693 #define SC_TMRDAT1_2_CNT2_Msk (0xfful << SC_TMRDAT1_2_CNT2_Pos) /*!< SC_T::TMRDAT1_2: CNT2 Msk */
sahilmgandhi 18:6a4db94011d3 10694
sahilmgandhi 18:6a4db94011d3 10695 /**@}*/ /* SC_CONST */
sahilmgandhi 18:6a4db94011d3 10696 /**@}*/ /* end of SC register group */
sahilmgandhi 18:6a4db94011d3 10697
sahilmgandhi 18:6a4db94011d3 10698
sahilmgandhi 18:6a4db94011d3 10699 /*---------------------- Serial Peripheral Interface Controller -------------------------*/
sahilmgandhi 18:6a4db94011d3 10700 /**
sahilmgandhi 18:6a4db94011d3 10701 @addtogroup SPI Serial Peripheral Interface Controller(SPI)
sahilmgandhi 18:6a4db94011d3 10702 Memory Mapped Structure for SPI Controller
sahilmgandhi 18:6a4db94011d3 10703 @{ */
sahilmgandhi 18:6a4db94011d3 10704
sahilmgandhi 18:6a4db94011d3 10705
sahilmgandhi 18:6a4db94011d3 10706 typedef struct
sahilmgandhi 18:6a4db94011d3 10707 {
sahilmgandhi 18:6a4db94011d3 10708
sahilmgandhi 18:6a4db94011d3 10709
sahilmgandhi 18:6a4db94011d3 10710 /**
sahilmgandhi 18:6a4db94011d3 10711 * @var SPI_T::CTL
sahilmgandhi 18:6a4db94011d3 10712 * Offset: 0x00 Control Register
sahilmgandhi 18:6a4db94011d3 10713 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 10714 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 10715 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 10716 * |[0] |SPIEN |SPI Transfer Control Enable Bit
sahilmgandhi 18:6a4db94011d3 10717 * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this is set to 1.
sahilmgandhi 18:6a4db94011d3 10718 * | | |In Slave mode, this device is ready to receive data when this bit is set to 1.
sahilmgandhi 18:6a4db94011d3 10719 * | | |0 = Transfer control Disabled.
sahilmgandhi 18:6a4db94011d3 10720 * | | |1 = Transfer control Enabled.
sahilmgandhi 18:6a4db94011d3 10721 * | | |Note: Before changing the configurations of SPI_CTL, SPI_CLKDIV, SPI_SSCTL and SPI_FIFOCTL registers, user shall clear the SPIEN (SPI_CTL[0]) and confirm the SPIENSTS (SPI_STATUS[15]) is 0.
sahilmgandhi 18:6a4db94011d3 10722 * |[1] |RXNEG |Receive On Negative Edge
sahilmgandhi 18:6a4db94011d3 10723 * | | |0 = Received data input signal is latched on the rising edge of SPI bus clock.
sahilmgandhi 18:6a4db94011d3 10724 * | | |1 = Received data input signal is latched on the falling edge of SPI bus clock.
sahilmgandhi 18:6a4db94011d3 10725 * |[2] |TXNEG |Transmit On Negative Edge
sahilmgandhi 18:6a4db94011d3 10726 * | | |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock.
sahilmgandhi 18:6a4db94011d3 10727 * | | |1 = Transmitted data output signal is changed on the falling edge of SP bus clock.
sahilmgandhi 18:6a4db94011d3 10728 * |[3] |CLKPOL |Clock Polarity
sahilmgandhi 18:6a4db94011d3 10729 * | | |0 = SPI bus clock is idle low.
sahilmgandhi 18:6a4db94011d3 10730 * | | |1 = SPI bus clock is idle high.
sahilmgandhi 18:6a4db94011d3 10731 * |[7:4] |SUSPITV |Suspend Interval (Master Only)
sahilmgandhi 18:6a4db94011d3 10732 * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer.
sahilmgandhi 18:6a4db94011d3 10733 * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word.
sahilmgandhi 18:6a4db94011d3 10734 * | | |The default value is 0x3.
sahilmgandhi 18:6a4db94011d3 10735 * | | |The period of the suspend interval is obtained according to the following equation.
sahilmgandhi 18:6a4db94011d3 10736 * | | |(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle
sahilmgandhi 18:6a4db94011d3 10737 * | | |Example:
sahilmgandhi 18:6a4db94011d3 10738 * | | |SUSPITV = 0x0 ... 0.5 SPICLK clock cycle.
sahilmgandhi 18:6a4db94011d3 10739 * | | |SUSPITV = 0x1 ... 1.5 SPICLK clock cycle.
sahilmgandhi 18:6a4db94011d3 10740 * | | |...
sahilmgandhi 18:6a4db94011d3 10741 * | | |SUSPITV = 0xE ... 14.5 SPICLK clock cycle.
sahilmgandhi 18:6a4db94011d3 10742 * | | |SUSPITV = 0xF ... 15.5 SPICLK clock cycle.
sahilmgandhi 18:6a4db94011d3 10743 * |[12:8] |DWIDTH |Data Width
sahilmgandhi 18:6a4db94011d3 10744 * | | |This field specifies how many bits can be transmitted / received in one transaction.
sahilmgandhi 18:6a4db94011d3 10745 * | | |The minimum bit length is 8 bits and can up to 32 bits.
sahilmgandhi 18:6a4db94011d3 10746 * | | |DWIDTH = 0x08 ... 8 bits.
sahilmgandhi 18:6a4db94011d3 10747 * | | |DWIDTH = 0x09 ... 9 bits.
sahilmgandhi 18:6a4db94011d3 10748 * | | |...
sahilmgandhi 18:6a4db94011d3 10749 * | | |DWIDTH = 0x1F ... 31 bits.
sahilmgandhi 18:6a4db94011d3 10750 * | | |DWIDTH = 0x00 ... 32 bits.
sahilmgandhi 18:6a4db94011d3 10751 * |[13] |LSB |Send LSB First
sahilmgandhi 18:6a4db94011d3 10752 * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
sahilmgandhi 18:6a4db94011d3 10753 * | | |1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX).
sahilmgandhi 18:6a4db94011d3 10754 * |[16] |TWOBIT |2-Bit Transfer Mode Enable Bit (Only Supported in SPI0)
sahilmgandhi 18:6a4db94011d3 10755 * | | |0 = 2-Bit Transfer mode Disabled.
sahilmgandhi 18:6a4db94011d3 10756 * | | |1 = 2-Bit Transfer mode Enabled.
sahilmgandhi 18:6a4db94011d3 10757 * | | |Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd
sahilmgandhi 18:6a4db94011d3 10758 * | | |serial transmitted bit data is from the second FIFO buffer data.
sahilmgandhi 18:6a4db94011d3 10759 * | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
sahilmgandhi 18:6a4db94011d3 10760 * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 10761 * | | |0 = SPI unit transfer interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 10762 * | | |1 = SPI unit transfer interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 10763 * |[18] |SLAVE |Slave Mode Control
sahilmgandhi 18:6a4db94011d3 10764 * | | |0 = Master mode.
sahilmgandhi 18:6a4db94011d3 10765 * | | |1 = Slave mode.
sahilmgandhi 18:6a4db94011d3 10766 * |[19] |REORDER |Byte Reorder Function Enable Bit
sahilmgandhi 18:6a4db94011d3 10767 * | | |0 = Byte Reorder function Disabled.
sahilmgandhi 18:6a4db94011d3 10768 * | | |1 = Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte.
sahilmgandhi 18:6a4db94011d3 10769 * | | |The period of the byte suspend interval depends on the setting of SUSPITV.
sahilmgandhi 18:6a4db94011d3 10770 * | | |Note:
sahilmgandhi 18:6a4db94011d3 10771 * | | |1. Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
sahilmgandhi 18:6a4db94011d3 10772 * | | |2. Byte Reorder function is not supported when the Quad or Dual I/O mode is enabled.
sahilmgandhi 18:6a4db94011d3 10773 * |[20] |QDIODIR |Quad Or Dual I/O Mode Direction Control (Only Supported in SPI0)
sahilmgandhi 18:6a4db94011d3 10774 * | | |0 = Quad or Dual Input mode.
sahilmgandhi 18:6a4db94011d3 10775 * | | |1 = Quad or Dual Output mode.
sahilmgandhi 18:6a4db94011d3 10776 * |[21] |DUALIOEN |Dual I/O Mode Enable Bit (Only Supported in SPI0)
sahilmgandhi 18:6a4db94011d3 10777 * | | |0 = Dual I/O mode Disabled.
sahilmgandhi 18:6a4db94011d3 10778 * | | |1 = Dual I/O mode Enabled.
sahilmgandhi 18:6a4db94011d3 10779 * |[22] |QUADIOEN |Quad I/O Mode Enable Bit (Only Supported in SPI0)
sahilmgandhi 18:6a4db94011d3 10780 * | | |0 = Quad I/O mode Disabled.
sahilmgandhi 18:6a4db94011d3 10781 * | | |1 = Quad I/O mode Enabled.
sahilmgandhi 18:6a4db94011d3 10782 * @var SPI_T::CLKDIV
sahilmgandhi 18:6a4db94011d3 10783 * Offset: 0x04 Clock Divider Register
sahilmgandhi 18:6a4db94011d3 10784 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 10785 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 10786 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 10787 * |[7:0] |DIVIDER |Clock Divider
sahilmgandhi 18:6a4db94011d3 10788 * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI master.
sahilmgandhi 18:6a4db94011d3 10789 * | | |The frequency is obtained according to the following equation.
sahilmgandhi 18:6a4db94011d3 10790 * | | | fspi_eclk = fspi_clock_src / (DIVIDER + 1)
sahilmgandhi 18:6a4db94011d3 10791 * | | |where fspi_clock_src is the peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.
sahilmgandhi 18:6a4db94011d3 10792 * @var SPI_T::SSCTL
sahilmgandhi 18:6a4db94011d3 10793 * Offset: 0x08 Slave Select Control Register
sahilmgandhi 18:6a4db94011d3 10794 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 10795 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 10796 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 10797 * |[0] |SS |Slave Selection Control (Master Only)
sahilmgandhi 18:6a4db94011d3 10798 * | | |If AUTOSS bit is cleared to 0,
sahilmgandhi 18:6a4db94011d3 10799 * | | |0 = set the SPIn_SS line to inactive state.
sahilmgandhi 18:6a4db94011d3 10800 * | | |1 = set the SPIn_SS line to active state
sahilmgandhi 18:6a4db94011d3 10801 * | | |If the AUTOSS bit is set to 1,
sahilmgandhi 18:6a4db94011d3 10802 * | | |0 = Keep the SPIn_SS line at inactive state.
sahilmgandhi 18:6a4db94011d3 10803 * | | |1 = SPIn_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time.
sahilmgandhi 18:6a4db94011d3 10804 * | | |The active state of SPIn_SS is specified in SSACTPOL (SPI_SSCTL[2]).
sahilmgandhi 18:6a4db94011d3 10805 * |[2] |SSACTPOL |Slave Selection Active Polarity
sahilmgandhi 18:6a4db94011d3 10806 * | | |This bit defines the active polarity of slave selection signal (SPIn_SS).
sahilmgandhi 18:6a4db94011d3 10807 * | | |0 = The slave selection signal SPIn_SS is active low.
sahilmgandhi 18:6a4db94011d3 10808 * | | |1 = The slave selection signal SPIn_SS is active high.
sahilmgandhi 18:6a4db94011d3 10809 * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only)
sahilmgandhi 18:6a4db94011d3 10810 * | | |0 = Automatic slave selection function Disabled.
sahilmgandhi 18:6a4db94011d3 10811 * | | |Slave selection signal will be asserted/de-asserted according to SS (SPI_SSCTL[0]).
sahilmgandhi 18:6a4db94011d3 10812 * | | |1 = Automatic slave selection function Enabled.
sahilmgandhi 18:6a4db94011d3 10813 * |[4] |SLV3WIRE |Slave 3-Wire Mode Enable Bit
sahilmgandhi 18:6a4db94011d3 10814 * | | |Slave 3-wire mode is only available in SPI0.
sahilmgandhi 18:6a4db94011d3 10815 * | | |In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPI0_CLK, SPI0_MISO, and SPI0_MOSI.
sahilmgandhi 18:6a4db94011d3 10816 * | | |0 = 4-wire bi-direction interface.
sahilmgandhi 18:6a4db94011d3 10817 * | | |1 = 3-wire bi-direction interface.
sahilmgandhi 18:6a4db94011d3 10818 * |[5] |SLVTOIEN |Slave Mode Time-Out Interrupt Enable Bit (Only Supported in SPI0)
sahilmgandhi 18:6a4db94011d3 10819 * | | |0 = Slave mode time-out interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 10820 * | | |1 = Slave mode time-out interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 10821 * |[6] |SLVTORST |Slave Mode Time-Out Reset Control (Only Supported in SPI0)
sahilmgandhi 18:6a4db94011d3 10822 * | | |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset.
sahilmgandhi 18:6a4db94011d3 10823 * | | |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware.
sahilmgandhi 18:6a4db94011d3 10824 * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 10825 * | | |0 = Slave mode bit count error interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 10826 * | | |1 = Slave mode bit count error interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 10827 * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 10828 * | | |0 = Slave mode TX under run interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 10829 * | | |1 = Slave mode TX under run interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 10830 * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 10831 * | | |0 = Slave select active interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 10832 * | | |1 = Slave select active interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 10833 * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 10834 * | | |0 = Slave select inactive interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 10835 * | | |1 = Slave select inactive interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 10836 * |[31:16] |SLVTOCNT |Slave Mode Time-Out Period (Only Supported in SPI0)
sahilmgandhi 18:6a4db94011d3 10837 * | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active.
sahilmgandhi 18:6a4db94011d3 10838 * | | |The clock source of the time-out counter is Slave peripheral clock.
sahilmgandhi 18:6a4db94011d3 10839 * | | |If the value is 0, it indicates the slave mode time-out function is disabled.
sahilmgandhi 18:6a4db94011d3 10840 * @var SPI_T::PDMACTL
sahilmgandhi 18:6a4db94011d3 10841 * Offset: 0x0C SPI PDMA Control Register
sahilmgandhi 18:6a4db94011d3 10842 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 10843 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 10844 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 10845 * |[0] |TXPDMAEN |Transmit PDMA Enable Bit
sahilmgandhi 18:6a4db94011d3 10846 * | | |0 = Transmit PDMA function Disabled.
sahilmgandhi 18:6a4db94011d3 10847 * | | |1 = Transmit PDMA function Enabled.
sahilmgandhi 18:6a4db94011d3 10848 * | | |Note: In SPI master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function.
sahilmgandhi 18:6a4db94011d3 10849 * | | |User can enable TX PDMA function firstly or enable both functions simultaneously.
sahilmgandhi 18:6a4db94011d3 10850 * |[1] |RXPDMAEN |Receive PDMA Enable Bit
sahilmgandhi 18:6a4db94011d3 10851 * | | |0 = Receiver PDMA function Disabled.
sahilmgandhi 18:6a4db94011d3 10852 * | | |1 = Receiver PDMA function Enabled.
sahilmgandhi 18:6a4db94011d3 10853 * |[2] |PDMARST |PDMA Reset
sahilmgandhi 18:6a4db94011d3 10854 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 10855 * | | |1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0.
sahilmgandhi 18:6a4db94011d3 10856 * @var SPI_T::FIFOCTL
sahilmgandhi 18:6a4db94011d3 10857 * Offset: 0x10 SPI FIFO Control Register
sahilmgandhi 18:6a4db94011d3 10858 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 10859 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 10860 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 10861 * |[0] |RXRST |Receive Reset
sahilmgandhi 18:6a4db94011d3 10862 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 10863 * | | |1 = Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1.
sahilmgandhi 18:6a4db94011d3 10864 * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 3 peripheral clock cycles after it is set to 1.
sahilmgandhi 18:6a4db94011d3 10865 * | | |User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not.
sahilmgandhi 18:6a4db94011d3 10866 * | | |Note: If there is slave receive time-out event, the RXRST will be set 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
sahilmgandhi 18:6a4db94011d3 10867 * |[1] |TXRST |Transmit Reset
sahilmgandhi 18:6a4db94011d3 10868 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 10869 * | | |1 = Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1.
sahilmgandhi 18:6a4db94011d3 10870 * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 3 peripheral clock cycles after it is set to 1.
sahilmgandhi 18:6a4db94011d3 10871 * | | |User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not.
sahilmgandhi 18:6a4db94011d3 10872 * | | |Note: If there is slave receive time-out event, the TXRST will be set to 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
sahilmgandhi 18:6a4db94011d3 10873 * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 10874 * | | |0 = RX FIFO threshold interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 10875 * | | |1 = RX FIFO threshold interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 10876 * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 10877 * | | |0 = TX FIFO threshold interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 10878 * | | |1 = TX FIFO threshold interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 10879 * |[4] |RXTOIEN |Slave Receive Time-Out Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 10880 * | | |0 = Receive time-out interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 10881 * | | |1 = Receive time-out interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 10882 * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 10883 * | | |0 = Receive FIFO overrun interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 10884 * | | |1 = Receive FIFO overrun interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 10885 * |[6] |TXUFPOL |TX Underflow Data Polarity
sahilmgandhi 18:6a4db94011d3 10886 * | | |0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode.
sahilmgandhi 18:6a4db94011d3 10887 * | | |1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode.
sahilmgandhi 18:6a4db94011d3 10888 * | | |Note: The TX underflow event occurs if there is not any data in TX FIFO when the slave selection signal is active.
sahilmgandhi 18:6a4db94011d3 10889 * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 10890 * | | |In Slave mode, when TX underflow event occurs, this interrupt flag will be set to 1.
sahilmgandhi 18:6a4db94011d3 10891 * | | |0 = Slave TX underflow interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 10892 * | | |1 = Slave TX underflow interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 10893 * |[8] |RXFBCLR |Receive FIFO Buffer Clear
sahilmgandhi 18:6a4db94011d3 10894 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 10895 * | | |1 = Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1.
sahilmgandhi 18:6a4db94011d3 10896 * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
sahilmgandhi 18:6a4db94011d3 10897 * | | |Note: The RX shift register will not be cleared.
sahilmgandhi 18:6a4db94011d3 10898 * |[9] |TXFBCLR |Transmit FIFO Buffer Clear
sahilmgandhi 18:6a4db94011d3 10899 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 10900 * | | |1 = Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1.
sahilmgandhi 18:6a4db94011d3 10901 * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
sahilmgandhi 18:6a4db94011d3 10902 * | | |Note: The TX shift register will not be cleared.
sahilmgandhi 18:6a4db94011d3 10903 * |[26:24] |RXTH |Receive FIFO Threshold
sahilmgandhi 18:6a4db94011d3 10904 * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
sahilmgandhi 18:6a4db94011d3 10905 * | | |In SPI0, RXTH is a 3-bit wide configuration; in SPI1 and SPI2, 2-bit wide only (SPI_FIFOCTL[25:24]).
sahilmgandhi 18:6a4db94011d3 10906 * |[30:28] |TXTH |Transmit FIFO Threshold
sahilmgandhi 18:6a4db94011d3 10907 * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
sahilmgandhi 18:6a4db94011d3 10908 * | | |In SPI0, TXTH is a 3-bit wide configuration; in SPI1 and SPI2, 2-bit wide only (SPI_FIFOCTL[29:28]).
sahilmgandhi 18:6a4db94011d3 10909 * @var SPI_T::STATUS
sahilmgandhi 18:6a4db94011d3 10910 * Offset: 0x14 SPI Status Register
sahilmgandhi 18:6a4db94011d3 10911 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 10912 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 10913 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 10914 * |[0] |BUSY |Busy Status (Read Only)
sahilmgandhi 18:6a4db94011d3 10915 * | | |0 = SPI controller is in idle state.
sahilmgandhi 18:6a4db94011d3 10916 * | | |1 = SPI controller is in busy state.
sahilmgandhi 18:6a4db94011d3 10917 * | | |The following listing are the bus busy conditions:
sahilmgandhi 18:6a4db94011d3 10918 * | | |a. SPI_CTL[0] = 1 and the TXEMPTY = 0.
sahilmgandhi 18:6a4db94011d3 10919 * | | |b. For SPI Master mode, the TXEMPTY = 1 but the current transaction is not finished yet.
sahilmgandhi 18:6a4db94011d3 10920 * | | |c. For SPI Slave mode, the SPI_CTL[0] = 1 and there is serial clock input into the SPI core logic when slave select is active.
sahilmgandhi 18:6a4db94011d3 10921 * | | |d. For SPI Slave mode, the SPI_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
sahilmgandhi 18:6a4db94011d3 10922 * |[1] |UNITIF |Unit Transfer Interrupt Flag
sahilmgandhi 18:6a4db94011d3 10923 * | | |0 = No transaction has been finished since this bit was cleared to 0.
sahilmgandhi 18:6a4db94011d3 10924 * | | |1 = SPI controller has finished one unit transfer.
sahilmgandhi 18:6a4db94011d3 10925 * | | |Note: This bit will be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 10926 * |[2] |SSACTIF |Slave Select Active Interrupt Flag
sahilmgandhi 18:6a4db94011d3 10927 * | | |0 = Slave select active interrupt was cleared or not occurred.
sahilmgandhi 18:6a4db94011d3 10928 * | | |1 = Slave select active interrupt event occurred.
sahilmgandhi 18:6a4db94011d3 10929 * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 10930 * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag
sahilmgandhi 18:6a4db94011d3 10931 * | | |0 = Slave select inactive interrupt was cleared or not occurred.
sahilmgandhi 18:6a4db94011d3 10932 * | | |1 = Slave select inactive interrupt event occurred.
sahilmgandhi 18:6a4db94011d3 10933 * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 10934 * |[4] |SSLINE |Slave Select Line Bus Status (Read Only)
sahilmgandhi 18:6a4db94011d3 10935 * | | |0 = The slave select line status is 0.
sahilmgandhi 18:6a4db94011d3 10936 * | | |1 = The slave select line status is 1.
sahilmgandhi 18:6a4db94011d3 10937 * | | |Note: This bit is only available in Slave mode.
sahilmgandhi 18:6a4db94011d3 10938 * | | |If SSACTPOL (SPI_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
sahilmgandhi 18:6a4db94011d3 10939 * |[5] |SLVTOIF |Slave Time-Out Interrupt Flag (Only Supported in SPI0)
sahilmgandhi 18:6a4db94011d3 10940 * | | |When the Slave Select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in SPI controller logic will be started.
sahilmgandhi 18:6a4db94011d3 10941 * | | |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (SPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.
sahilmgandhi 18:6a4db94011d3 10942 * | | |0 = Slave time-out is not active.
sahilmgandhi 18:6a4db94011d3 10943 * | | |1 = Slave time-out is active.
sahilmgandhi 18:6a4db94011d3 10944 * | | |Note: This bit will be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 10945 * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag
sahilmgandhi 18:6a4db94011d3 10946 * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
sahilmgandhi 18:6a4db94011d3 10947 * | | |0 = No Slave mode bit count error event.
sahilmgandhi 18:6a4db94011d3 10948 * | | |1 = Slave mode bit count error event occurs.
sahilmgandhi 18:6a4db94011d3 10949 * | | |Note: If the slave select active but there is no any bus clock input, the SLVBCEIF also active when the slave select goes to inactive state.
sahilmgandhi 18:6a4db94011d3 10950 * | | |This bit will be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 10951 * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag
sahilmgandhi 18:6a4db94011d3 10952 * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
sahilmgandhi 18:6a4db94011d3 10953 * | | |0 = No Slave TX under run event.
sahilmgandhi 18:6a4db94011d3 10954 * | | |1 = Slave TX under run occurs.
sahilmgandhi 18:6a4db94011d3 10955 * | | |Note: This bit will be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 10956 * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
sahilmgandhi 18:6a4db94011d3 10957 * | | |0 = Receive FIFO buffer is not empty.
sahilmgandhi 18:6a4db94011d3 10958 * | | |1 = Receive FIFO buffer is empty.
sahilmgandhi 18:6a4db94011d3 10959 * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
sahilmgandhi 18:6a4db94011d3 10960 * | | |0 = Receive FIFO buffer is not full.
sahilmgandhi 18:6a4db94011d3 10961 * | | |1 = Receive FIFO buffer is full.
sahilmgandhi 18:6a4db94011d3 10962 * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 10963 * | | |0 = The valid data count within the RX FIFO buffer is smaller than or equal to the setting value of RXTH.
sahilmgandhi 18:6a4db94011d3 10964 * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
sahilmgandhi 18:6a4db94011d3 10965 * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
sahilmgandhi 18:6a4db94011d3 10966 * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
sahilmgandhi 18:6a4db94011d3 10967 * | | |0 = No FIFO is over run.
sahilmgandhi 18:6a4db94011d3 10968 * | | |1 = Receive FIFO over run.
sahilmgandhi 18:6a4db94011d3 10969 * | | |Note: This bit will be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 10970 * |[12] |RXTOIF |Receive Time-Out Interrupt Flag
sahilmgandhi 18:6a4db94011d3 10971 * | | |0 = No receive FIFO time-out event.
sahilmgandhi 18:6a4db94011d3 10972 * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode.
sahilmgandhi 18:6a4db94011d3 10973 * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
sahilmgandhi 18:6a4db94011d3 10974 * | | |Note: This bit will be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 10975 * |[15] |SPIENSTS |SPI Enable Status (Read Only)
sahilmgandhi 18:6a4db94011d3 10976 * | | |0 = The SPI controller is disabled.
sahilmgandhi 18:6a4db94011d3 10977 * | | |1 = The SPI controller is enabled.
sahilmgandhi 18:6a4db94011d3 10978 * | | |Note: The SPI peripheral clock is asynchronous with the system clock.
sahilmgandhi 18:6a4db94011d3 10979 * | | |In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
sahilmgandhi 18:6a4db94011d3 10980 * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
sahilmgandhi 18:6a4db94011d3 10981 * | | |0 = Transmit FIFO buffer is not empty.
sahilmgandhi 18:6a4db94011d3 10982 * | | |1 = Transmit FIFO buffer is empty.
sahilmgandhi 18:6a4db94011d3 10983 * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
sahilmgandhi 18:6a4db94011d3 10984 * | | |0 = Transmit FIFO buffer is not full.
sahilmgandhi 18:6a4db94011d3 10985 * | | |1 = Transmit FIFO buffer is full.
sahilmgandhi 18:6a4db94011d3 10986 * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 10987 * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
sahilmgandhi 18:6a4db94011d3 10988 * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
sahilmgandhi 18:6a4db94011d3 10989 * |[19] |TXUFIF |TX Underflow Interrupt Flag
sahilmgandhi 18:6a4db94011d3 10990 * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
sahilmgandhi 18:6a4db94011d3 10991 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 10992 * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active.
sahilmgandhi 18:6a4db94011d3 10993 * | | |Note 1: This bit will be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 10994 * | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
sahilmgandhi 18:6a4db94011d3 10995 * |[23] |TXRXRST |TX or RX Reset Status (Read Only)
sahilmgandhi 18:6a4db94011d3 10996 * | | |0 = The reset function of TXRST or RXRST is done.
sahilmgandhi 18:6a4db94011d3 10997 * | | |1 = Doing the reset function of TXRST or RXRST.
sahilmgandhi 18:6a4db94011d3 10998 * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles.
sahilmgandhi 18:6a4db94011d3 10999 * | | |User can check the status of this bit to monitor the reset function is doing or done.
sahilmgandhi 18:6a4db94011d3 11000 * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only)
sahilmgandhi 18:6a4db94011d3 11001 * | | |This bit field indicates the valid data count of receive FIFO buffer.
sahilmgandhi 18:6a4db94011d3 11002 * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only)
sahilmgandhi 18:6a4db94011d3 11003 * | | |This bit field indicates the valid data count of transmit FIFO buffer.
sahilmgandhi 18:6a4db94011d3 11004 * @var SPI_T::TX
sahilmgandhi 18:6a4db94011d3 11005 * Offset: 0x20 Data Transmit Register
sahilmgandhi 18:6a4db94011d3 11006 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11007 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11008 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11009 * |[31:0] |TX |Data Transmit Register
sahilmgandhi 18:6a4db94011d3 11010 * | | |The data transmit registers pass through the transmitted data into the 8-/4-level transmit FIFO buffer.
sahilmgandhi 18:6a4db94011d3 11011 * | | |The number of valid bits depends on the setting of DWIDTH (SPI_CTL[12:8]).
sahilmgandhi 18:6a4db94011d3 11012 * | | |For example, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted.
sahilmgandhi 18:6a4db94011d3 11013 * | | |If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.
sahilmgandhi 18:6a4db94011d3 11014 * | | |Note: In Master mode, SPI controller will start to transfer after 5 peripheral clock cycles after user writes to this register.
sahilmgandhi 18:6a4db94011d3 11015 * @var SPI_T::RX
sahilmgandhi 18:6a4db94011d3 11016 * Offset: 0x30 Data Receive Register
sahilmgandhi 18:6a4db94011d3 11017 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11018 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11019 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11020 * |[31:0] |RX |Data Receive Register
sahilmgandhi 18:6a4db94011d3 11021 * | | |There are 8-/4-level FIFO buffers in this controller.
sahilmgandhi 18:6a4db94011d3 11022 * | | |The data receive register holds the data received from SPI data input pin.
sahilmgandhi 18:6a4db94011d3 11023 * | | |If the RXEMPTY (SPI_STATUS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register.
sahilmgandhi 18:6a4db94011d3 11024 * | | |This is a read only register.
sahilmgandhi 18:6a4db94011d3 11025 * @var SPI_T::I2SCTL
sahilmgandhi 18:6a4db94011d3 11026 * Offset: 0x60 I2S Control Register
sahilmgandhi 18:6a4db94011d3 11027 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11028 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11029 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11030 * |[0] |I2SEN |I2S Controller Enable Bit
sahilmgandhi 18:6a4db94011d3 11031 * | | |0 = Disabled.
sahilmgandhi 18:6a4db94011d3 11032 * | | |1 = Enabled.
sahilmgandhi 18:6a4db94011d3 11033 * | | |Note: If enable this bit, I2Sn_BCLK will start to output in master mode.
sahilmgandhi 18:6a4db94011d3 11034 * |[1] |TXEN |Transmit Enable Bit
sahilmgandhi 18:6a4db94011d3 11035 * | | |0 = Data transmit Disabled.
sahilmgandhi 18:6a4db94011d3 11036 * | | |1 = Data transmit Enabled.
sahilmgandhi 18:6a4db94011d3 11037 * |[2] |RXEN |Receive Enable Bit
sahilmgandhi 18:6a4db94011d3 11038 * | | |0 = Data receiving Disabled.
sahilmgandhi 18:6a4db94011d3 11039 * | | |1 = Data receiving Enabled.
sahilmgandhi 18:6a4db94011d3 11040 * |[3] |MUTE |Transmit Mute Enable Bit
sahilmgandhi 18:6a4db94011d3 11041 * | | |0 = Transmit data is shifted from buffer.
sahilmgandhi 18:6a4db94011d3 11042 * | | |1= Transmit channel zero.
sahilmgandhi 18:6a4db94011d3 11043 * |[5:4] |WDWIDTH |Word Width
sahilmgandhi 18:6a4db94011d3 11044 * | | |00 = data is 8-bit.
sahilmgandhi 18:6a4db94011d3 11045 * | | |01 = data is 16-bit.
sahilmgandhi 18:6a4db94011d3 11046 * | | |10 = data is 24-bit.
sahilmgandhi 18:6a4db94011d3 11047 * | | |11 = data is 32-bit.
sahilmgandhi 18:6a4db94011d3 11048 * |[6] |MONO |Monaural Data
sahilmgandhi 18:6a4db94011d3 11049 * | | |0 = Data is stereo format.
sahilmgandhi 18:6a4db94011d3 11050 * | | |1 = Data is monaural format.
sahilmgandhi 18:6a4db94011d3 11051 * |[7] |ORDER |Stereo Data Order In FIFO
sahilmgandhi 18:6a4db94011d3 11052 * | | |0 = Left channel data at high byte.
sahilmgandhi 18:6a4db94011d3 11053 * | | |1 = Left channel data at low byte.
sahilmgandhi 18:6a4db94011d3 11054 * |[8] |SLAVE |Slave Mode
sahilmgandhi 18:6a4db94011d3 11055 * | | |I2S can operate as master or slave.
sahilmgandhi 18:6a4db94011d3 11056 * | | |For Master mode, I2Sn_BCLK and I2Sn_LRCLK pins are output mode and send bit clock from NuMicro M451 series to Audio CODEC chip.
sahilmgandhi 18:6a4db94011d3 11057 * | | |In Slave mode, I2Sn_BCLK and I2Sn_LRCLK pins are input mode and I2Sn_BCLK and I2Sn_LRCLK signals are received from outer Audio CODEC chip.
sahilmgandhi 18:6a4db94011d3 11058 * | | |0 = Master mode.
sahilmgandhi 18:6a4db94011d3 11059 * | | |1 = Slave mode.
sahilmgandhi 18:6a4db94011d3 11060 * |[15] |MCLKEN |Master Clock Enable Bit
sahilmgandhi 18:6a4db94011d3 11061 * | | |If MCLKEN is set to 1, I2S controller will generate master clock on I2Sn_MCLK pin for external audio devices.
sahilmgandhi 18:6a4db94011d3 11062 * | | |0 = Master clock Disabled.
sahilmgandhi 18:6a4db94011d3 11063 * | | |1 = Master clock Enabled.
sahilmgandhi 18:6a4db94011d3 11064 * |[16] |RZCEN |Right Channel Zero Cross Detection Enable Bit
sahilmgandhi 18:6a4db94011d3 11065 * | | |If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPI_I2SSTS register is set to 1.
sahilmgandhi 18:6a4db94011d3 11066 * | | |This function is only available in transmit operation.
sahilmgandhi 18:6a4db94011d3 11067 * | | |0 = Right channel zero cross detection Disabled.
sahilmgandhi 18:6a4db94011d3 11068 * | | |1 = Right channel zero cross detection Enabled.
sahilmgandhi 18:6a4db94011d3 11069 * |[17] |LZCEN |Left Channel Zero Cross Detection Enable Bit
sahilmgandhi 18:6a4db94011d3 11070 * | | |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPI_I2SSTS register is set to 1.
sahilmgandhi 18:6a4db94011d3 11071 * | | |This function is only available in transmit operation.
sahilmgandhi 18:6a4db94011d3 11072 * | | |0 = Left channel zero cross detection Disabled.
sahilmgandhi 18:6a4db94011d3 11073 * | | |1 = Left channel zero cross detection Enabled.
sahilmgandhi 18:6a4db94011d3 11074 * |[23] |RXLCH |Receive Left Channel Enable Bit
sahilmgandhi 18:6a4db94011d3 11075 * | | |When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1.
sahilmgandhi 18:6a4db94011d3 11076 * | | |0 = Receive right channel data in Mono mode.
sahilmgandhi 18:6a4db94011d3 11077 * | | |1 = Receive left channel data in Mono mode.
sahilmgandhi 18:6a4db94011d3 11078 * |[24] |RZCIEN |Right Channel Zero-Cross Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 11079 * | | |Interrupt occurs if this bit is set to 1 and right channel zero-cross event occurs.
sahilmgandhi 18:6a4db94011d3 11080 * | | |0 = Interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 11081 * | | |1 = Interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 11082 * |[25] |LZCIEN |Left Channel Zero-Cross Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 11083 * | | |Interrupt occurs if this bit is set to 1 and left channel zero-cross event occurs.
sahilmgandhi 18:6a4db94011d3 11084 * | | |0 = Interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 11085 * | | |1 = Interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 11086 * |[29:28] |FORMAT |Data Format Selection
sahilmgandhi 18:6a4db94011d3 11087 * | | |00 = I2S data format.
sahilmgandhi 18:6a4db94011d3 11088 * | | |01 = MSB justified data format.
sahilmgandhi 18:6a4db94011d3 11089 * | | |10 = PCM mode A.
sahilmgandhi 18:6a4db94011d3 11090 * | | |11 = PCM mode B.
sahilmgandhi 18:6a4db94011d3 11091 * @var SPI_T::I2SCLK
sahilmgandhi 18:6a4db94011d3 11092 * Offset: 0x64 I2S Clock Divider Control Register
sahilmgandhi 18:6a4db94011d3 11093 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11094 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11095 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11096 * |[5:0] |MCLKDIV |Master Clock Divider
sahilmgandhi 18:6a4db94011d3 11097 * | | |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices.
sahilmgandhi 18:6a4db94011d3 11098 * | | |The master clock rate, F_MCLK, is determined by the following expressions.
sahilmgandhi 18:6a4db94011d3 11099 * | | |If MCLKDIV >= 1, F_MCLK = F_I2SCLK/(2x(MCLKDIV)).
sahilmgandhi 18:6a4db94011d3 11100 * | | |If MCLKDIV = 0, F_MCLK = F_I2SCLK.
sahilmgandhi 18:6a4db94011d3 11101 * | | |F_I2SCLK is the frequency of I2S peripheral clock.
sahilmgandhi 18:6a4db94011d3 11102 * | | |In general, the master clock rate is 256 times sampling clock rate.
sahilmgandhi 18:6a4db94011d3 11103 * |[16:8] |BCLKDIV |Bit Clock Divider
sahilmgandhi 18:6a4db94011d3 11104 * | | |The I2S controller will generate bit clock in Master mode.
sahilmgandhi 18:6a4db94011d3 11105 * | | |The bit clock rate, F_BCLK, is determined by the following expression.
sahilmgandhi 18:6a4db94011d3 11106 * | | |F_BCLK = F_I2SCLK /(2x(BCLKDIV + 1)) , where F_I2SCLK is the frequency of I2S peripheral clock.
sahilmgandhi 18:6a4db94011d3 11107 * @var SPI_T::I2SSTS
sahilmgandhi 18:6a4db94011d3 11108 * Offset: 0x68 I2S Status Register
sahilmgandhi 18:6a4db94011d3 11109 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11110 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11111 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11112 * |[4] |RIGHT |Right Channel (Read Only)
sahilmgandhi 18:6a4db94011d3 11113 * | | |This bit indicates the current transmit data is belong to which channel.
sahilmgandhi 18:6a4db94011d3 11114 * | | |0 = Left channel.
sahilmgandhi 18:6a4db94011d3 11115 * | | |1 = Right channel.
sahilmgandhi 18:6a4db94011d3 11116 * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
sahilmgandhi 18:6a4db94011d3 11117 * | | |0 = Receive FIFO buffer is not empty.
sahilmgandhi 18:6a4db94011d3 11118 * | | |1 = Receive FIFO buffer is empty.
sahilmgandhi 18:6a4db94011d3 11119 * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
sahilmgandhi 18:6a4db94011d3 11120 * | | |0 = Receive FIFO buffer is not full.
sahilmgandhi 18:6a4db94011d3 11121 * | | |1 = Receive FIFO buffer is full.
sahilmgandhi 18:6a4db94011d3 11122 * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 11123 * | | |0 = The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RXTH.
sahilmgandhi 18:6a4db94011d3 11124 * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
sahilmgandhi 18:6a4db94011d3 11125 * | | |Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request.
sahilmgandhi 18:6a4db94011d3 11126 * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
sahilmgandhi 18:6a4db94011d3 11127 * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
sahilmgandhi 18:6a4db94011d3 11128 * | | |Note: This bit will be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 11129 * |[12] |RXTOIF |Receive Time-Out Interrupt Flag
sahilmgandhi 18:6a4db94011d3 11130 * | | |0 = No receive FIFO time-out event.
sahilmgandhi 18:6a4db94011d3 11131 * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode.
sahilmgandhi 18:6a4db94011d3 11132 * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
sahilmgandhi 18:6a4db94011d3 11133 * | | |Note: This bit will be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 11134 * |[15] |I2SENSTS |I2S Enable Status (Read Only)
sahilmgandhi 18:6a4db94011d3 11135 * | | |0 = The SPI/I2S control logic is disabled.
sahilmgandhi 18:6a4db94011d3 11136 * | | |1 = The SPI/I2S control logic is enabled.
sahilmgandhi 18:6a4db94011d3 11137 * | | |Note: The SPI peripheral clock is asynchronous with the system clock.
sahilmgandhi 18:6a4db94011d3 11138 * | | |In order to make sure the SPI/I2S controller logic is disabled, this bit indicates the real status of SPI/I2S controller logic for user.
sahilmgandhi 18:6a4db94011d3 11139 * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
sahilmgandhi 18:6a4db94011d3 11140 * | | |0 = Transmit FIFO buffer is not empty.
sahilmgandhi 18:6a4db94011d3 11141 * | | |1 = Transmit FIFO buffer is empty.
sahilmgandhi 18:6a4db94011d3 11142 * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
sahilmgandhi 18:6a4db94011d3 11143 * | | |0 = Transmit FIFO buffer is not full.
sahilmgandhi 18:6a4db94011d3 11144 * | | |1 = Transmit FIFO buffer is full.
sahilmgandhi 18:6a4db94011d3 11145 * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 11146 * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
sahilmgandhi 18:6a4db94011d3 11147 * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
sahilmgandhi 18:6a4db94011d3 11148 * | | |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI controller will generate a SPI interrupt request.
sahilmgandhi 18:6a4db94011d3 11149 * |[19] |TXUFIF |Transmit FIFO Underflow Interrupt Flag
sahilmgandhi 18:6a4db94011d3 11150 * | | |When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input,
sahilmgandhi 18:6a4db94011d3 11151 * | | | the output data depends on the setting of TXUFPOL and this bit will be set to 1.
sahilmgandhi 18:6a4db94011d3 11152 * | | |Note: This bit will be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 11153 * |[20] |RZCIF |Right Channel Zero Cross Interrupt Flag
sahilmgandhi 18:6a4db94011d3 11154 * | | |0 = No zero cross event occurred on right channel.
sahilmgandhi 18:6a4db94011d3 11155 * | | |1 = Zero cross event occurred on right channel.
sahilmgandhi 18:6a4db94011d3 11156 * |[21] |LZCIF |Left Channel Zero Cross Interrupt Flag
sahilmgandhi 18:6a4db94011d3 11157 * | | |0 = No zero cross event occurred on left channel.
sahilmgandhi 18:6a4db94011d3 11158 * | | |1 = Zero cross event occurred on left channel.
sahilmgandhi 18:6a4db94011d3 11159 * |[23] |TXRXRST |TX or RX Reset Status (Read Only)
sahilmgandhi 18:6a4db94011d3 11160 * | | |0 = The reset function of TXRST or RXRST is done.
sahilmgandhi 18:6a4db94011d3 11161 * | | |1 = Doing the reset function of TXRST or RXRST.
sahilmgandhi 18:6a4db94011d3 11162 * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 3 peripheral clock cycles.
sahilmgandhi 18:6a4db94011d3 11163 * | | |User can check the status of this bit to monitor the reset function is doing or done.
sahilmgandhi 18:6a4db94011d3 11164 * |[26:24] |RXCNT |Receive FIFO Data Count (Read Only)
sahilmgandhi 18:6a4db94011d3 11165 * | | |This bit field indicates the valid data count of receive FIFO buffer.
sahilmgandhi 18:6a4db94011d3 11166 * |[30:28] |TXCNT |Transmit FIFO Data Count (Read Only)
sahilmgandhi 18:6a4db94011d3 11167 * | | |This bit field indicates the valid data count of transmit FIFO buffer.
sahilmgandhi 18:6a4db94011d3 11168 */
sahilmgandhi 18:6a4db94011d3 11169
sahilmgandhi 18:6a4db94011d3 11170 __IO uint32_t CTL; /* Offset: 0x00 Control Register */
sahilmgandhi 18:6a4db94011d3 11171 __IO uint32_t CLKDIV; /* Offset: 0x04 Clock Divider Register */
sahilmgandhi 18:6a4db94011d3 11172 __IO uint32_t SSCTL; /* Offset: 0x08 Slave Select Control Register */
sahilmgandhi 18:6a4db94011d3 11173 __IO uint32_t PDMACTL; /* Offset: 0x0C SPI PDMA Control Register */
sahilmgandhi 18:6a4db94011d3 11174 __IO uint32_t FIFOCTL; /* Offset: 0x10 SPI FIFO Control Register */
sahilmgandhi 18:6a4db94011d3 11175 __IO uint32_t STATUS; /* Offset: 0x14 SPI Status Register */
sahilmgandhi 18:6a4db94011d3 11176 __I uint32_t RESERVE0[2];
sahilmgandhi 18:6a4db94011d3 11177 __O uint32_t TX; /* Offset: 0x20 Data Transmit Register */
sahilmgandhi 18:6a4db94011d3 11178 __I uint32_t RESERVE1[3];
sahilmgandhi 18:6a4db94011d3 11179 __I uint32_t RX; /* Offset: 0x30 Data Receive Register */
sahilmgandhi 18:6a4db94011d3 11180 __I uint32_t RESERVE2[11];
sahilmgandhi 18:6a4db94011d3 11181 __IO uint32_t I2SCTL; /* Offset: 0x60 I2S Control Register */
sahilmgandhi 18:6a4db94011d3 11182 __IO uint32_t I2SCLK; /* Offset: 0x64 I2S Clock Divider Control Register */
sahilmgandhi 18:6a4db94011d3 11183 __IO uint32_t I2SSTS; /* Offset: 0x68 I2S Status Register */
sahilmgandhi 18:6a4db94011d3 11184
sahilmgandhi 18:6a4db94011d3 11185 } SPI_T;
sahilmgandhi 18:6a4db94011d3 11186
sahilmgandhi 18:6a4db94011d3 11187
sahilmgandhi 18:6a4db94011d3 11188
sahilmgandhi 18:6a4db94011d3 11189 /**
sahilmgandhi 18:6a4db94011d3 11190 @addtogroup SPI_CONST SPI Bit Field Definition
sahilmgandhi 18:6a4db94011d3 11191 Constant Definitions for SPI Controller
sahilmgandhi 18:6a4db94011d3 11192 @{ */
sahilmgandhi 18:6a4db94011d3 11193
sahilmgandhi 18:6a4db94011d3 11194 #define SPI_CTL_SPIEN_Pos (0) /*!< SPI_T::CTL: SPIEN Position */
sahilmgandhi 18:6a4db94011d3 11195 #define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) /*!< SPI_T::CTL: SPIEN Mask */
sahilmgandhi 18:6a4db94011d3 11196
sahilmgandhi 18:6a4db94011d3 11197 #define SPI_CTL_RXNEG_Pos (1) /*!< SPI_T::CTL: RXNEG Position */
sahilmgandhi 18:6a4db94011d3 11198 #define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) /*!< SPI_T::CTL: RXNEG Mask */
sahilmgandhi 18:6a4db94011d3 11199
sahilmgandhi 18:6a4db94011d3 11200 #define SPI_CTL_TXNEG_Pos (2) /*!< SPI_T::CTL: TXNEG Position */
sahilmgandhi 18:6a4db94011d3 11201 #define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) /*!< SPI_T::CTL: TXNEG Mask */
sahilmgandhi 18:6a4db94011d3 11202
sahilmgandhi 18:6a4db94011d3 11203 #define SPI_CTL_CLKPOL_Pos (3) /*!< SPI_T::CTL: CLKPOL Position */
sahilmgandhi 18:6a4db94011d3 11204 #define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) /*!< SPI_T::CTL: CLKPOL Mask */
sahilmgandhi 18:6a4db94011d3 11205
sahilmgandhi 18:6a4db94011d3 11206 #define SPI_CTL_SUSPITV_Pos (4) /*!< SPI_T::CTL: SUSPITV Position */
sahilmgandhi 18:6a4db94011d3 11207 #define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) /*!< SPI_T::CTL: SUSPITV Mask */
sahilmgandhi 18:6a4db94011d3 11208
sahilmgandhi 18:6a4db94011d3 11209 #define SPI_CTL_DWIDTH_Pos (8) /*!< SPI_T::CTL: DWIDTH Position */
sahilmgandhi 18:6a4db94011d3 11210 #define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) /*!< SPI_T::CTL: DWIDTH Mask */
sahilmgandhi 18:6a4db94011d3 11211
sahilmgandhi 18:6a4db94011d3 11212 #define SPI_CTL_LSB_Pos (13) /*!< SPI_T::CTL: LSB Position */
sahilmgandhi 18:6a4db94011d3 11213 #define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI_T::CTL: LSB Mask */
sahilmgandhi 18:6a4db94011d3 11214
sahilmgandhi 18:6a4db94011d3 11215 #define SPI_CTL_TWOBIT_Pos (16) /*!< SPI_T::CTL: TWOBIT Position */
sahilmgandhi 18:6a4db94011d3 11216 #define SPI_CTL_TWOBIT_Msk (0x1ul << SPI_CTL_TWOBIT_Pos) /*!< SPI_T::CTL: TWOBIT Mask */
sahilmgandhi 18:6a4db94011d3 11217
sahilmgandhi 18:6a4db94011d3 11218 #define SPI_CTL_UNITIEN_Pos (17) /*!< SPI_T::CTL: UNITIEN Position */
sahilmgandhi 18:6a4db94011d3 11219 #define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) /*!< SPI_T::CTL: UNITIEN Mask */
sahilmgandhi 18:6a4db94011d3 11220
sahilmgandhi 18:6a4db94011d3 11221 #define SPI_CTL_SLAVE_Pos (18) /*!< SPI_T::CTL: SLAVE Position */
sahilmgandhi 18:6a4db94011d3 11222 #define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI_T::CTL: SLAVE Mask */
sahilmgandhi 18:6a4db94011d3 11223
sahilmgandhi 18:6a4db94011d3 11224 #define SPI_CTL_REORDER_Pos (19) /*!< SPI_T::CTL: REORDER Position */
sahilmgandhi 18:6a4db94011d3 11225 #define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI_T::CTL: REORDER Mask */
sahilmgandhi 18:6a4db94011d3 11226
sahilmgandhi 18:6a4db94011d3 11227 #define SPI_CTL_QDIODIR_Pos (20) /*!< SPI_T::CTL: QDIODIR Position */
sahilmgandhi 18:6a4db94011d3 11228 #define SPI_CTL_QDIODIR_Msk (0x1ul << SPI_CTL_QDIODIR_Pos) /*!< SPI_T::CTL: QDIODIR Mask */
sahilmgandhi 18:6a4db94011d3 11229
sahilmgandhi 18:6a4db94011d3 11230 #define SPI_CTL_DUALIOEN_Pos (21) /*!< SPI_T::CTL: DUALIOEN Position */
sahilmgandhi 18:6a4db94011d3 11231 #define SPI_CTL_DUALIOEN_Msk (0x1ul << SPI_CTL_DUALIOEN_Pos) /*!< SPI_T::CTL: DUALIOEN Mask */
sahilmgandhi 18:6a4db94011d3 11232
sahilmgandhi 18:6a4db94011d3 11233 #define SPI_CTL_QUADIOEN_Pos (22) /*!< SPI_T::CTL: QUADIOEN Position */
sahilmgandhi 18:6a4db94011d3 11234 #define SPI_CTL_QUADIOEN_Msk (0x1ul << SPI_CTL_QUADIOEN_Pos) /*!< SPI_T::CTL: QUADIOEN Mask */
sahilmgandhi 18:6a4db94011d3 11235
sahilmgandhi 18:6a4db94011d3 11236 #define SPI_CLKDIV_DIVIDER_Pos (0) /*!< SPI_T::CLKDIV: DIVIDER Position */
sahilmgandhi 18:6a4db94011d3 11237 #define SPI_CLKDIV_DIVIDER_Msk (0xfful << SPI_CLKDIV_DIVIDER_Pos) /*!< SPI_T::CLKDIV: DIVIDER Mask */
sahilmgandhi 18:6a4db94011d3 11238
sahilmgandhi 18:6a4db94011d3 11239 #define SPI_SSCTL_SS_Pos (0) /*!< SPI_T::SSCTL: SS Position */
sahilmgandhi 18:6a4db94011d3 11240 #define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos) /*!< SPI_T::SSCTL: SS Mask */
sahilmgandhi 18:6a4db94011d3 11241
sahilmgandhi 18:6a4db94011d3 11242 #define SPI_SSCTL_SSACTPOL_Pos (2) /*!< SPI_T::SSCTL: SSACTPOL Position */
sahilmgandhi 18:6a4db94011d3 11243 #define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) /*!< SPI_T::SSCTL: SSACTPOL Mask */
sahilmgandhi 18:6a4db94011d3 11244
sahilmgandhi 18:6a4db94011d3 11245 #define SPI_SSCTL_AUTOSS_Pos (3) /*!< SPI_T::SSCTL: AUTOSS Position */
sahilmgandhi 18:6a4db94011d3 11246 #define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) /*!< SPI_T::SSCTL: AUTOSS Mask */
sahilmgandhi 18:6a4db94011d3 11247
sahilmgandhi 18:6a4db94011d3 11248 #define SPI_SSCTL_SLV3WIRE_Pos (4) /*!< SPI_T::SSCTL: SLV3WIRE Position */
sahilmgandhi 18:6a4db94011d3 11249 #define SPI_SSCTL_SLV3WIRE_Msk (0x1ul << SPI_SSCTL_SLV3WIRE_Pos) /*!< SPI_T::SSCTL: SLV3WIRE Mask */
sahilmgandhi 18:6a4db94011d3 11250
sahilmgandhi 18:6a4db94011d3 11251 #define SPI_SSCTL_SLVTOIEN_Pos (5) /*!< SPI_T::SSCTL: SLVTOIEN Position */
sahilmgandhi 18:6a4db94011d3 11252 #define SPI_SSCTL_SLVTOIEN_Msk (0x1ul << SPI_SSCTL_SLVTOIEN_Pos) /*!< SPI_T::SSCTL: SLVTOIEN Mask */
sahilmgandhi 18:6a4db94011d3 11253
sahilmgandhi 18:6a4db94011d3 11254 #define SPI_SSCTL_SLVTORST_Pos (6) /*!< SPI_T::SSCTL: SLVTORST Position */
sahilmgandhi 18:6a4db94011d3 11255 #define SPI_SSCTL_SLVTORST_Msk (0x1ul << SPI_SSCTL_SLVTORST_Pos) /*!< SPI_T::SSCTL: SLVTORST Mask */
sahilmgandhi 18:6a4db94011d3 11256
sahilmgandhi 18:6a4db94011d3 11257 #define SPI_SSCTL_SLVBEIEN_Pos (8) /*!< SPI_T::SSCTL: SLVBEIEN Position */
sahilmgandhi 18:6a4db94011d3 11258 #define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) /*!< SPI_T::SSCTL: SLVBEIEN Mask */
sahilmgandhi 18:6a4db94011d3 11259
sahilmgandhi 18:6a4db94011d3 11260 #define SPI_SSCTL_SLVURIEN_Pos (9) /*!< SPI_T::SSCTL: SLVURIEN Position */
sahilmgandhi 18:6a4db94011d3 11261 #define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) /*!< SPI_T::SSCTL: SLVURIEN Mask */
sahilmgandhi 18:6a4db94011d3 11262
sahilmgandhi 18:6a4db94011d3 11263 #define SPI_SSCTL_SSACTIEN_Pos (12) /*!< SPI_T::SSCTL: SSACTIEN Position */
sahilmgandhi 18:6a4db94011d3 11264 #define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) /*!< SPI_T::SSCTL: SSACTIEN Mask */
sahilmgandhi 18:6a4db94011d3 11265
sahilmgandhi 18:6a4db94011d3 11266 #define SPI_SSCTL_SSINAIEN_Pos (13) /*!< SPI_T::SSCTL: SSINAIEN Position */
sahilmgandhi 18:6a4db94011d3 11267 #define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) /*!< SPI_T::SSCTL: SSINAIEN Mask */
sahilmgandhi 18:6a4db94011d3 11268
sahilmgandhi 18:6a4db94011d3 11269 #define SPI_SSCTL_SLVTOCNT_Pos (16) /*!< SPI_T::SSCTL: SLVTOCNT Position */
sahilmgandhi 18:6a4db94011d3 11270 #define SPI_SSCTL_SLVTOCNT_Msk (0xfffful << SPI_SSCTL_SLVTOCNT_Pos) /*!< SPI_T::SSCTL: SLVTOCNT Mask */
sahilmgandhi 18:6a4db94011d3 11271
sahilmgandhi 18:6a4db94011d3 11272 #define SPI_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI_T::PDMACTL: TXPDMAEN Position */
sahilmgandhi 18:6a4db94011d3 11273 #define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) /*!< SPI_T::PDMACTL: TXPDMAEN Mask */
sahilmgandhi 18:6a4db94011d3 11274
sahilmgandhi 18:6a4db94011d3 11275 #define SPI_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI_T::PDMACTL: RXPDMAEN Position */
sahilmgandhi 18:6a4db94011d3 11276 #define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) /*!< SPI_T::PDMACTL: RXPDMAEN Mask */
sahilmgandhi 18:6a4db94011d3 11277
sahilmgandhi 18:6a4db94011d3 11278 #define SPI_PDMACTL_PDMARST_Pos (2) /*!< SPI_T::PDMACTL: PDMARST Position */
sahilmgandhi 18:6a4db94011d3 11279 #define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) /*!< SPI_T::PDMACTL: PDMARST Mask */
sahilmgandhi 18:6a4db94011d3 11280
sahilmgandhi 18:6a4db94011d3 11281 #define SPI_FIFOCTL_RXRST_Pos (0) /*!< SPI_T::FIFOCTL: RXRST Position */
sahilmgandhi 18:6a4db94011d3 11282 #define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) /*!< SPI_T::FIFOCTL: RXRST Mask */
sahilmgandhi 18:6a4db94011d3 11283
sahilmgandhi 18:6a4db94011d3 11284 #define SPI_FIFOCTL_TXRST_Pos (1) /*!< SPI_T::FIFOCTL: TXRST Position */
sahilmgandhi 18:6a4db94011d3 11285 #define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) /*!< SPI_T::FIFOCTL: TXRST Mask */
sahilmgandhi 18:6a4db94011d3 11286
sahilmgandhi 18:6a4db94011d3 11287 #define SPI_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI_T::FIFOCTL: RXTHIEN Position */
sahilmgandhi 18:6a4db94011d3 11288 #define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) /*!< SPI_T::FIFOCTL: RXTHIEN Mask */
sahilmgandhi 18:6a4db94011d3 11289
sahilmgandhi 18:6a4db94011d3 11290 #define SPI_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI_T::FIFOCTL: TXTHIEN Position */
sahilmgandhi 18:6a4db94011d3 11291 #define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) /*!< SPI_T::FIFOCTL: TXTHIEN Mask */
sahilmgandhi 18:6a4db94011d3 11292
sahilmgandhi 18:6a4db94011d3 11293 #define SPI_FIFOCTL_RXTOIEN_Pos (4) /*!< SPI_T::FIFOCTL: RXTOIEN Position */
sahilmgandhi 18:6a4db94011d3 11294 #define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) /*!< SPI_T::FIFOCTL: RXTOIEN Mask */
sahilmgandhi 18:6a4db94011d3 11295
sahilmgandhi 18:6a4db94011d3 11296 #define SPI_FIFOCTL_RXOVIEN_Pos (5) /*!< SPI_T::FIFOCTL: RXOVIEN Position */
sahilmgandhi 18:6a4db94011d3 11297 #define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) /*!< SPI_T::FIFOCTL: RXOVIEN Mask */
sahilmgandhi 18:6a4db94011d3 11298
sahilmgandhi 18:6a4db94011d3 11299 #define SPI_FIFOCTL_TXUFPOL_Pos (6) /*!< SPI_T::FIFOCTL: TXUFPOL Position */
sahilmgandhi 18:6a4db94011d3 11300 #define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) /*!< SPI_T::FIFOCTL: TXUFPOL Mask */
sahilmgandhi 18:6a4db94011d3 11301
sahilmgandhi 18:6a4db94011d3 11302 #define SPI_FIFOCTL_TXUFIEN_Pos (7) /*!< SPI_T::FIFOCTL: TXUFIEN Position */
sahilmgandhi 18:6a4db94011d3 11303 #define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) /*!< SPI_T::FIFOCTL: TXUFIEN Mask */
sahilmgandhi 18:6a4db94011d3 11304
sahilmgandhi 18:6a4db94011d3 11305 #define SPI_FIFOCTL_RXFBCLR_Pos (8) /*!< SPI_T::FIFOCTL: RXFBCLR Position */
sahilmgandhi 18:6a4db94011d3 11306 #define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) /*!< SPI_T::FIFOCTL: RXFBCLR Mask */
sahilmgandhi 18:6a4db94011d3 11307
sahilmgandhi 18:6a4db94011d3 11308 #define SPI_FIFOCTL_TXFBCLR_Pos (9) /*!< SPI_T::FIFOCTL: TXFBCLR Position */
sahilmgandhi 18:6a4db94011d3 11309 #define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) /*!< SPI_T::FIFOCTL: TXFBCLR Mask */
sahilmgandhi 18:6a4db94011d3 11310
sahilmgandhi 18:6a4db94011d3 11311 #define SPI_FIFOCTL_RXTH_Pos (24) /*!< SPI_T::FIFOCTL: RXTH Position */
sahilmgandhi 18:6a4db94011d3 11312 #define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) /*!< SPI_T::FIFOCTL: RXTH Mask */
sahilmgandhi 18:6a4db94011d3 11313
sahilmgandhi 18:6a4db94011d3 11314 #define SPI_FIFOCTL_TXTH_Pos (28) /*!< SPI_T::FIFOCTL: TXTH Position */
sahilmgandhi 18:6a4db94011d3 11315 #define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /*!< SPI_T::FIFOCTL: TXTH Mask */
sahilmgandhi 18:6a4db94011d3 11316
sahilmgandhi 18:6a4db94011d3 11317 #define SPI_STATUS_BUSY_Pos (0) /*!< SPI_T::STATUS: BUSY Position */
sahilmgandhi 18:6a4db94011d3 11318 #define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) /*!< SPI_T::STATUS: BUSY Mask */
sahilmgandhi 18:6a4db94011d3 11319
sahilmgandhi 18:6a4db94011d3 11320 #define SPI_STATUS_UNITIF_Pos (1) /*!< SPI_T::STATUS: UNITIF Position */
sahilmgandhi 18:6a4db94011d3 11321 #define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) /*!< SPI_T::STATUS: UNITIF Mask */
sahilmgandhi 18:6a4db94011d3 11322
sahilmgandhi 18:6a4db94011d3 11323 #define SPI_STATUS_SSACTIF_Pos (2) /*!< SPI_T::STATUS: SSACTIF Position */
sahilmgandhi 18:6a4db94011d3 11324 #define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) /*!< SPI_T::STATUS: SSACTIF Mask */
sahilmgandhi 18:6a4db94011d3 11325
sahilmgandhi 18:6a4db94011d3 11326 #define SPI_STATUS_SSINAIF_Pos (3) /*!< SPI_T::STATUS: SSINAIF Position */
sahilmgandhi 18:6a4db94011d3 11327 #define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) /*!< SPI_T::STATUS: SSINAIF Mask */
sahilmgandhi 18:6a4db94011d3 11328
sahilmgandhi 18:6a4db94011d3 11329 #define SPI_STATUS_SSLINE_Pos (4) /*!< SPI_T::STATUS: SSLINE Position */
sahilmgandhi 18:6a4db94011d3 11330 #define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) /*!< SPI_T::STATUS: SSLINE Mask */
sahilmgandhi 18:6a4db94011d3 11331
sahilmgandhi 18:6a4db94011d3 11332 #define SPI_STATUS_SLVTOIF_Pos (5) /*!< SPI_T::STATUS: SLVTOIF Position */
sahilmgandhi 18:6a4db94011d3 11333 #define SPI_STATUS_SLVTOIF_Msk (0x1ul << SPI_STATUS_SLVTOIF_Pos) /*!< SPI_T::STATUS: SLVTOIF Mask */
sahilmgandhi 18:6a4db94011d3 11334
sahilmgandhi 18:6a4db94011d3 11335 #define SPI_STATUS_SLVBEIF_Pos (6) /*!< SPI_T::STATUS: SLVBEIF Position */
sahilmgandhi 18:6a4db94011d3 11336 #define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) /*!< SPI_T::STATUS: SLVBEIF Mask */
sahilmgandhi 18:6a4db94011d3 11337
sahilmgandhi 18:6a4db94011d3 11338 #define SPI_STATUS_SLVURIF_Pos (7) /*!< SPI_T::STATUS: SLVURIF Position */
sahilmgandhi 18:6a4db94011d3 11339 #define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos) /*!< SPI_T::STATUS: SLVURIF Mask */
sahilmgandhi 18:6a4db94011d3 11340
sahilmgandhi 18:6a4db94011d3 11341 #define SPI_STATUS_RXEMPTY_Pos (8) /*!< SPI_T::STATUS: RXEMPTY Position */
sahilmgandhi 18:6a4db94011d3 11342 #define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) /*!< SPI_T::STATUS: RXEMPTY Mask */
sahilmgandhi 18:6a4db94011d3 11343
sahilmgandhi 18:6a4db94011d3 11344 #define SPI_STATUS_RXFULL_Pos (9) /*!< SPI_T::STATUS: RXFULL Position */
sahilmgandhi 18:6a4db94011d3 11345 #define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) /*!< SPI_T::STATUS: RXFULL Mask */
sahilmgandhi 18:6a4db94011d3 11346
sahilmgandhi 18:6a4db94011d3 11347 #define SPI_STATUS_RXTHIF_Pos (10) /*!< SPI_T::STATUS: RXTHIF Position */
sahilmgandhi 18:6a4db94011d3 11348 #define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) /*!< SPI_T::STATUS: RXTHIF Mask */
sahilmgandhi 18:6a4db94011d3 11349
sahilmgandhi 18:6a4db94011d3 11350 #define SPI_STATUS_RXOVIF_Pos (11) /*!< SPI_T::STATUS: RXOVIF Position */
sahilmgandhi 18:6a4db94011d3 11351 #define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) /*!< SPI_T::STATUS: RXOVIF Mask */
sahilmgandhi 18:6a4db94011d3 11352
sahilmgandhi 18:6a4db94011d3 11353 #define SPI_STATUS_RXTOIF_Pos (12) /*!< SPI_T::STATUS: RXTOIF Position */
sahilmgandhi 18:6a4db94011d3 11354 #define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) /*!< SPI_T::STATUS: RXTOIF Mask */
sahilmgandhi 18:6a4db94011d3 11355
sahilmgandhi 18:6a4db94011d3 11356 #define SPI_STATUS_SPIENSTS_Pos (15) /*!< SPI_T::STATUS: SPIENSTS Position */
sahilmgandhi 18:6a4db94011d3 11357 #define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) /*!< SPI_T::STATUS: SPIENSTS Mask */
sahilmgandhi 18:6a4db94011d3 11358
sahilmgandhi 18:6a4db94011d3 11359 #define SPI_STATUS_TXEMPTY_Pos (16) /*!< SPI_T::STATUS: TXEMPTY Position */
sahilmgandhi 18:6a4db94011d3 11360 #define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) /*!< SPI_T::STATUS: TXEMPTY Mask */
sahilmgandhi 18:6a4db94011d3 11361
sahilmgandhi 18:6a4db94011d3 11362 #define SPI_STATUS_TXFULL_Pos (17) /*!< SPI_T::STATUS: TXFULL Position */
sahilmgandhi 18:6a4db94011d3 11363 #define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) /*!< SPI_T::STATUS: TXFULL Mask */
sahilmgandhi 18:6a4db94011d3 11364
sahilmgandhi 18:6a4db94011d3 11365 #define SPI_STATUS_TXTHIF_Pos (18) /*!< SPI_T::STATUS: TXTHIF Position */
sahilmgandhi 18:6a4db94011d3 11366 #define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) /*!< SPI_T::STATUS: TXTHIF Mask */
sahilmgandhi 18:6a4db94011d3 11367
sahilmgandhi 18:6a4db94011d3 11368 #define SPI_STATUS_TXUFIF_Pos (19) /*!< SPI_T::STATUS: TXUFIF Position */
sahilmgandhi 18:6a4db94011d3 11369 #define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) /*!< SPI_T::STATUS: TXUFIF Mask */
sahilmgandhi 18:6a4db94011d3 11370
sahilmgandhi 18:6a4db94011d3 11371 #define SPI_STATUS_TXRXRST_Pos (23) /*!< SPI_T::STATUS: TXRXRST Position */
sahilmgandhi 18:6a4db94011d3 11372 #define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) /*!< SPI_T::STATUS: TXRXRST Mask */
sahilmgandhi 18:6a4db94011d3 11373
sahilmgandhi 18:6a4db94011d3 11374 #define SPI_STATUS_RXCNT_Pos (24) /*!< SPI_T::STATUS: RXCNT Position */
sahilmgandhi 18:6a4db94011d3 11375 #define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) /*!< SPI_T::STATUS: RXCNT Mask */
sahilmgandhi 18:6a4db94011d3 11376
sahilmgandhi 18:6a4db94011d3 11377 #define SPI_STATUS_TXCNT_Pos (28) /*!< SPI_T::STATUS: TXCNT Position */
sahilmgandhi 18:6a4db94011d3 11378 #define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /*!< SPI_T::STATUS: TXCNT Mask */
sahilmgandhi 18:6a4db94011d3 11379
sahilmgandhi 18:6a4db94011d3 11380 #define SPI_TX_TX_Pos (0) /*!< SPI_T::TX: TX Position */
sahilmgandhi 18:6a4db94011d3 11381 #define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) /*!< SPI_T::TX: TX Mask */
sahilmgandhi 18:6a4db94011d3 11382
sahilmgandhi 18:6a4db94011d3 11383 #define SPI_RX_RX_Pos (0) /*!< SPI_T::RX: RX Position */
sahilmgandhi 18:6a4db94011d3 11384 #define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /*!< SPI_T::RX: RX Mask */
sahilmgandhi 18:6a4db94011d3 11385
sahilmgandhi 18:6a4db94011d3 11386 #define SPI_I2SCTL_I2SEN_Pos (0) /*!< SPI_T::I2SCTL: I2SEN Position */
sahilmgandhi 18:6a4db94011d3 11387 #define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos) /*!< SPI_T::I2SCTL: I2SEN Mask */
sahilmgandhi 18:6a4db94011d3 11388
sahilmgandhi 18:6a4db94011d3 11389 #define SPI_I2SCTL_TXEN_Pos (1) /*!< SPI_T::I2SCTL: TXEN Position */
sahilmgandhi 18:6a4db94011d3 11390 #define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos) /*!< SPI_T::I2SCTL: TXEN Mask */
sahilmgandhi 18:6a4db94011d3 11391
sahilmgandhi 18:6a4db94011d3 11392 #define SPI_I2SCTL_RXEN_Pos (2) /*!< SPI_T::I2SCTL: RXEN Position */
sahilmgandhi 18:6a4db94011d3 11393 #define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos) /*!< SPI_T::I2SCTL: RXEN Mask */
sahilmgandhi 18:6a4db94011d3 11394
sahilmgandhi 18:6a4db94011d3 11395 #define SPI_I2SCTL_MUTE_Pos (3) /*!< SPI_T::I2SCTL: MUTE Position */
sahilmgandhi 18:6a4db94011d3 11396 #define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos) /*!< SPI_T::I2SCTL: MUTE Mask */
sahilmgandhi 18:6a4db94011d3 11397
sahilmgandhi 18:6a4db94011d3 11398 #define SPI_I2SCTL_WDWIDTH_Pos (4) /*!< SPI_T::I2SCTL: WDWIDTH Position */
sahilmgandhi 18:6a4db94011d3 11399 #define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPI_T::I2SCTL: WDWIDTH Mask */
sahilmgandhi 18:6a4db94011d3 11400
sahilmgandhi 18:6a4db94011d3 11401 #define SPI_I2SCTL_MONO_Pos (6) /*!< SPI_T::I2SCTL: MONO Position */
sahilmgandhi 18:6a4db94011d3 11402 #define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos) /*!< SPI_T::I2SCTL: MONO Mask */
sahilmgandhi 18:6a4db94011d3 11403
sahilmgandhi 18:6a4db94011d3 11404 #define SPI_I2SCTL_ORDER_Pos (7) /*!< SPI_T::I2SCTL: ORDER Position */
sahilmgandhi 18:6a4db94011d3 11405 #define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos) /*!< SPI_T::I2SCTL: ORDER Mask */
sahilmgandhi 18:6a4db94011d3 11406
sahilmgandhi 18:6a4db94011d3 11407 #define SPI_I2SCTL_SLAVE_Pos (8) /*!< SPI_T::I2SCTL: SLAVE Position */
sahilmgandhi 18:6a4db94011d3 11408 #define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos) /*!< SPI_T::I2SCTL: SLAVE Mask */
sahilmgandhi 18:6a4db94011d3 11409
sahilmgandhi 18:6a4db94011d3 11410 #define SPI_I2SCTL_MCLKEN_Pos (15) /*!< SPI_T::I2SCTL: MCLKEN Position */
sahilmgandhi 18:6a4db94011d3 11411 #define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos) /*!< SPI_T::I2SCTL: MCLKEN Mask */
sahilmgandhi 18:6a4db94011d3 11412
sahilmgandhi 18:6a4db94011d3 11413 #define SPI_I2SCTL_RZCEN_Pos (16) /*!< SPI_T::I2SCTL: RZCEN Position */
sahilmgandhi 18:6a4db94011d3 11414 #define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos) /*!< SPI_T::I2SCTL: RZCEN Mask */
sahilmgandhi 18:6a4db94011d3 11415
sahilmgandhi 18:6a4db94011d3 11416 #define SPI_I2SCTL_LZCEN_Pos (17) /*!< SPI_T::I2SCTL: LZCEN Position */
sahilmgandhi 18:6a4db94011d3 11417 #define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos) /*!< SPI_T::I2SCTL: LZCEN Mask */
sahilmgandhi 18:6a4db94011d3 11418
sahilmgandhi 18:6a4db94011d3 11419 #define SPI_I2SCTL_RXLCH_Pos (23) /*!< SPI_T::I2SCTL: RXLCH Position */
sahilmgandhi 18:6a4db94011d3 11420 #define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos) /*!< SPI_T::I2SCTL: RXLCH Mask */
sahilmgandhi 18:6a4db94011d3 11421
sahilmgandhi 18:6a4db94011d3 11422 #define SPI_I2SCTL_RZCIEN_Pos (24) /*!< SPI_T::I2SCTL: RZCIEN Position */
sahilmgandhi 18:6a4db94011d3 11423 #define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos) /*!< SPI_T::I2SCTL: RZCIEN Mask */
sahilmgandhi 18:6a4db94011d3 11424
sahilmgandhi 18:6a4db94011d3 11425 #define SPI_I2SCTL_LZCIEN_Pos (25) /*!< SPI_T::I2SCTL: LZCIEN Position */
sahilmgandhi 18:6a4db94011d3 11426 #define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos) /*!< SPI_T::I2SCTL: LZCIEN Mask */
sahilmgandhi 18:6a4db94011d3 11427
sahilmgandhi 18:6a4db94011d3 11428 #define SPI_I2SCTL_FORMAT_Pos (28) /*!< SPI_T::I2SCTL: FORMAT Position */
sahilmgandhi 18:6a4db94011d3 11429 #define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos) /*!< SPI_T::I2SCTL: FORMAT Mask */
sahilmgandhi 18:6a4db94011d3 11430
sahilmgandhi 18:6a4db94011d3 11431 #define SPI_I2SCLK_MCLKDIV_Pos (0) /*!< SPI_T::I2SCLK: MCLKDIV Position */
sahilmgandhi 18:6a4db94011d3 11432 #define SPI_I2SCLK_MCLKDIV_Msk (0x3ful << SPI_I2SCLK_MCLKDIV_Pos) /*!< SPI_T::I2SCLK: MCLKDIV Mask */
sahilmgandhi 18:6a4db94011d3 11433
sahilmgandhi 18:6a4db94011d3 11434 #define SPI_I2SCLK_BCLKDIV_Pos (8) /*!< SPI_T::I2SCLK: BCLKDIV Position */
sahilmgandhi 18:6a4db94011d3 11435 #define SPI_I2SCLK_BCLKDIV_Msk (0x1fful << SPI_I2SCLK_BCLKDIV_Pos) /*!< SPI_T::I2SCLK: BCLKDIV Mask */
sahilmgandhi 18:6a4db94011d3 11436
sahilmgandhi 18:6a4db94011d3 11437 #define SPI_I2SSTS_RIGHT_Pos (4) /*!< SPI_T::I2SSTS: RIGHT Position */
sahilmgandhi 18:6a4db94011d3 11438 #define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos) /*!< SPI_T::I2SSTS: RIGHT Mask */
sahilmgandhi 18:6a4db94011d3 11439
sahilmgandhi 18:6a4db94011d3 11440 #define SPI_I2SSTS_RXEMPTY_Pos (8) /*!< SPI_T::I2SSTS: RXEMPTY Position */
sahilmgandhi 18:6a4db94011d3 11441 #define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos) /*!< SPI_T::I2SSTS: RXEMPTY Mask */
sahilmgandhi 18:6a4db94011d3 11442
sahilmgandhi 18:6a4db94011d3 11443 #define SPI_I2SSTS_RXFULL_Pos (9) /*!< SPI_T::I2SSTS: RXFULL Position */
sahilmgandhi 18:6a4db94011d3 11444 #define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos) /*!< SPI_T::I2SSTS: RXFULL Mask */
sahilmgandhi 18:6a4db94011d3 11445
sahilmgandhi 18:6a4db94011d3 11446 #define SPI_I2SSTS_RXTHIF_Pos (10) /*!< SPI_T::I2SSTS: RXTHIF Position */
sahilmgandhi 18:6a4db94011d3 11447 #define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos) /*!< SPI_T::I2SSTS: RXTHIF Mask */
sahilmgandhi 18:6a4db94011d3 11448
sahilmgandhi 18:6a4db94011d3 11449 #define SPI_I2SSTS_RXOVIF_Pos (11) /*!< SPI_T::I2SSTS: RXOVIF Position */
sahilmgandhi 18:6a4db94011d3 11450 #define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos) /*!< SPI_T::I2SSTS: RXOVIF Mask */
sahilmgandhi 18:6a4db94011d3 11451
sahilmgandhi 18:6a4db94011d3 11452 #define SPI_I2SSTS_RXTOIF_Pos (12) /*!< SPI_T::I2SSTS: RXTOIF Position */
sahilmgandhi 18:6a4db94011d3 11453 #define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos) /*!< SPI_T::I2SSTS: RXTOIF Mask */
sahilmgandhi 18:6a4db94011d3 11454
sahilmgandhi 18:6a4db94011d3 11455 #define SPI_I2SSTS_I2SENSTS_Pos (15) /*!< SPI_T::I2SSTS: I2SENSTS Position */
sahilmgandhi 18:6a4db94011d3 11456 #define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos) /*!< SPI_T::I2SSTS: I2SENSTS Mask */
sahilmgandhi 18:6a4db94011d3 11457
sahilmgandhi 18:6a4db94011d3 11458 #define SPI_I2SSTS_TXEMPTY_Pos (16) /*!< SPI_T::I2SSTS: TXEMPTY Position */
sahilmgandhi 18:6a4db94011d3 11459 #define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos) /*!< SPI_T::I2SSTS: TXEMPTY Mask */
sahilmgandhi 18:6a4db94011d3 11460
sahilmgandhi 18:6a4db94011d3 11461 #define SPI_I2SSTS_TXFULL_Pos (17) /*!< SPI_T::I2SSTS: TXFULL Position */
sahilmgandhi 18:6a4db94011d3 11462 #define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos) /*!< SPI_T::I2SSTS: TXFULL Mask */
sahilmgandhi 18:6a4db94011d3 11463
sahilmgandhi 18:6a4db94011d3 11464 #define SPI_I2SSTS_TXTHIF_Pos (18) /*!< SPI_T::I2SSTS: TXTHIF Position */
sahilmgandhi 18:6a4db94011d3 11465 #define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos) /*!< SPI_T::I2SSTS: TXTHIF Mask */
sahilmgandhi 18:6a4db94011d3 11466
sahilmgandhi 18:6a4db94011d3 11467 #define SPI_I2SSTS_TXUFIF_Pos (19) /*!< SPI_T::I2SSTS: TXUFIF Position */
sahilmgandhi 18:6a4db94011d3 11468 #define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos) /*!< SPI_T::I2SSTS: TXUFIF Mask */
sahilmgandhi 18:6a4db94011d3 11469
sahilmgandhi 18:6a4db94011d3 11470 #define SPI_I2SSTS_RZCIF_Pos (20) /*!< SPI_T::I2SSTS: RZCIF Position */
sahilmgandhi 18:6a4db94011d3 11471 #define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos) /*!< SPI_T::I2SSTS: RZCIF Mask */
sahilmgandhi 18:6a4db94011d3 11472
sahilmgandhi 18:6a4db94011d3 11473 #define SPI_I2SSTS_LZCIF_Pos (21) /*!< SPI_T::I2SSTS: LZCIF Position */
sahilmgandhi 18:6a4db94011d3 11474 #define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos) /*!< SPI_T::I2SSTS: LZCIF Mask */
sahilmgandhi 18:6a4db94011d3 11475
sahilmgandhi 18:6a4db94011d3 11476 #define SPI_I2SSTS_TXRXRST_Pos (23) /*!< SPI_T::I2SSTS: TXRXRST Position */
sahilmgandhi 18:6a4db94011d3 11477 #define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos) /*!< SPI_T::I2SSTS: TXRXRST Mask */
sahilmgandhi 18:6a4db94011d3 11478
sahilmgandhi 18:6a4db94011d3 11479 #define SPI_I2SSTS_RXCNT_Pos (24) /*!< SPI_T::I2SSTS: RXCNT Position */
sahilmgandhi 18:6a4db94011d3 11480 #define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos) /*!< SPI_T::I2SSTS: RXCNT Mask */
sahilmgandhi 18:6a4db94011d3 11481
sahilmgandhi 18:6a4db94011d3 11482 #define SPI_I2SSTS_TXCNT_Pos (28) /*!< SPI_T::I2SSTS: TXCNT Position */
sahilmgandhi 18:6a4db94011d3 11483 #define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) /*!< SPI_T::I2SSTS: TXCNT Mask */
sahilmgandhi 18:6a4db94011d3 11484
sahilmgandhi 18:6a4db94011d3 11485 /**@}*/ /* SPI_CONST */
sahilmgandhi 18:6a4db94011d3 11486 /**@}*/ /* end of SPI register group */
sahilmgandhi 18:6a4db94011d3 11487
sahilmgandhi 18:6a4db94011d3 11488
sahilmgandhi 18:6a4db94011d3 11489 /*---------------------- System Manger Controller -------------------------*/
sahilmgandhi 18:6a4db94011d3 11490 /**
sahilmgandhi 18:6a4db94011d3 11491 @addtogroup SYS System Manger Controller(SYS)
sahilmgandhi 18:6a4db94011d3 11492 Memory Mapped Structure for SYS Controller
sahilmgandhi 18:6a4db94011d3 11493 @{ */
sahilmgandhi 18:6a4db94011d3 11494
sahilmgandhi 18:6a4db94011d3 11495
sahilmgandhi 18:6a4db94011d3 11496 typedef struct
sahilmgandhi 18:6a4db94011d3 11497 {
sahilmgandhi 18:6a4db94011d3 11498
sahilmgandhi 18:6a4db94011d3 11499 /**
sahilmgandhi 18:6a4db94011d3 11500 * @var SYS_T::PDID
sahilmgandhi 18:6a4db94011d3 11501 * Offset: 0x00 Part Device Identification Number Register
sahilmgandhi 18:6a4db94011d3 11502 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11503 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11504 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11505 * |[31:0] |PDID |Part Device Identification Number (Read Only)
sahilmgandhi 18:6a4db94011d3 11506 * | | |This register reflects device part number code.
sahilmgandhi 18:6a4db94011d3 11507 * | | |Software can read this register to identify which device is used.
sahilmgandhi 18:6a4db94011d3 11508 * @var SYS_T::RSTSTS
sahilmgandhi 18:6a4db94011d3 11509 * Offset: 0x04 System Reset Status Register
sahilmgandhi 18:6a4db94011d3 11510 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11511 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11512 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11513 * |[0] |PORF |POR Reset Flag
sahilmgandhi 18:6a4db94011d3 11514 * | | |The POR reset flag is set by the "Reset Signal" from the Power-On Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.
sahilmgandhi 18:6a4db94011d3 11515 * | | |0 = No reset from POR or CHIPRST.
sahilmgandhi 18:6a4db94011d3 11516 * | | |1 = Power-On Reset (POR) or CHIPRST had issued the reset signal to reset the system.
sahilmgandhi 18:6a4db94011d3 11517 * | | |Note: Write 1 to clear this bit to 0.
sahilmgandhi 18:6a4db94011d3 11518 * |[1] |PINRF |nRESET Pin Reset Flag
sahilmgandhi 18:6a4db94011d3 11519 * | | |The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source.
sahilmgandhi 18:6a4db94011d3 11520 * | | |0 = No reset from nRESET pin.
sahilmgandhi 18:6a4db94011d3 11521 * | | |1 = Pin nRESET had issued the reset signal to reset the system.
sahilmgandhi 18:6a4db94011d3 11522 * | | |Note: Write 1 to clear this bit to 0.
sahilmgandhi 18:6a4db94011d3 11523 * |[2] |WDTRF |WDT Reset Flag
sahilmgandhi 18:6a4db94011d3 11524 * | | |The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.
sahilmgandhi 18:6a4db94011d3 11525 * | | |0 = No reset from watchdog timer or window watchdog timer.
sahilmgandhi 18:6a4db94011d3 11526 * | | |1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system.
sahilmgandhi 18:6a4db94011d3 11527 * | | |Note1:
sahilmgandhi 18:6a4db94011d3 11528 * | | |Write 1 to clear this bit to 0.
sahilmgandhi 18:6a4db94011d3 11529 * | | |Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset.
sahilmgandhi 18:6a4db94011d3 11530 * | | |Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
sahilmgandhi 18:6a4db94011d3 11531 * |[3] |LVRF |LVR Reset Flag
sahilmgandhi 18:6a4db94011d3 11532 * | | |The LVR reset flag is set by the "Reset Signal" from the Low-Voltage-Reset Controller to indicate the previous reset source.
sahilmgandhi 18:6a4db94011d3 11533 * | | |0 = No reset from LVR.
sahilmgandhi 18:6a4db94011d3 11534 * | | |1 = LVR controller had issued the reset signal to reset the system.
sahilmgandhi 18:6a4db94011d3 11535 * | | |Note: Write 1 to clear this bit to 0.
sahilmgandhi 18:6a4db94011d3 11536 * |[4] |BODRF |BOD Reset Flag
sahilmgandhi 18:6a4db94011d3 11537 * | | |The BOD reset flag is set by the "Reset Signal" from the Brown-Out-Detector to indicate the previous reset source.
sahilmgandhi 18:6a4db94011d3 11538 * | | |0 = No reset from BOD.
sahilmgandhi 18:6a4db94011d3 11539 * | | |1 = The BOD had issued the reset signal to reset the system.
sahilmgandhi 18:6a4db94011d3 11540 * | | |Note: Write 1 to clear this bit to 0.
sahilmgandhi 18:6a4db94011d3 11541 * |[5] |SYSRF |System Reset Flag
sahilmgandhi 18:6a4db94011d3 11542 * | | |The system reset flag is set by the "Reset Signal" from the Cortex-M4 Core to indicate the previous reset source.
sahilmgandhi 18:6a4db94011d3 11543 * | | |0 = No reset from Cortex-M4.
sahilmgandhi 18:6a4db94011d3 11544 * | | |1 = The Cortex-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M4 core.
sahilmgandhi 18:6a4db94011d3 11545 * | | |Note: Write 1 to clear this bit to 0.
sahilmgandhi 18:6a4db94011d3 11546 * |[7] |CPURF |CPU Reset Flag
sahilmgandhi 18:6a4db94011d3 11547 * | | |The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC).
sahilmgandhi 18:6a4db94011d3 11548 * | | |0 = No reset from CPU.
sahilmgandhi 18:6a4db94011d3 11549 * | | |1 = The Cortex-M4 Core and FMC are reset by software setting CPURST to 1.
sahilmgandhi 18:6a4db94011d3 11550 * | | |Note: Write 1 to clear this bit to 0.
sahilmgandhi 18:6a4db94011d3 11551 * |[8] |CPULKRF |CPU Lockup Reset Flag
sahilmgandhi 18:6a4db94011d3 11552 * | | |The CPU reset flag is set by hardware if Cortex-M4 lockup happened.
sahilmgandhi 18:6a4db94011d3 11553 * | | |0 = No reset from CPU lockup happened.
sahilmgandhi 18:6a4db94011d3 11554 * | | |1 = The Cortex-M4 lockup happened and chip is reset.
sahilmgandhi 18:6a4db94011d3 11555 * | | |Note: Write 1 to clear this bit to 0.
sahilmgandhi 18:6a4db94011d3 11556 * @var SYS_T::IPRST0
sahilmgandhi 18:6a4db94011d3 11557 * Offset: 0x08 Peripheral Reset Control Register 0
sahilmgandhi 18:6a4db94011d3 11558 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11559 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11560 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11561 * |[0] |CHIPRST |Chip One-Shot Reset (Write Protect)
sahilmgandhi 18:6a4db94011d3 11562 * | | |Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
sahilmgandhi 18:6a4db94011d3 11563 * | | |The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.
sahilmgandhi 18:6a4db94011d3 11564 * | | |About the difference between CHIPRST and SYSRESETREQ, please refer to section 5.2.2
sahilmgandhi 18:6a4db94011d3 11565 * | | |0 = Chip normal operation.
sahilmgandhi 18:6a4db94011d3 11566 * | | |1 = Chip one shot reset.
sahilmgandhi 18:6a4db94011d3 11567 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 11568 * |[1] |CPURST |Processor Core One-Shot Reset (Write Protect)
sahilmgandhi 18:6a4db94011d3 11569 * | | |Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.
sahilmgandhi 18:6a4db94011d3 11570 * | | |0 = Processor core normal operation.
sahilmgandhi 18:6a4db94011d3 11571 * | | |1 = Processor core one-shot reset.
sahilmgandhi 18:6a4db94011d3 11572 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 11573 * |[2] |PDMARST |PDMA Controller Reset (Write Protect)
sahilmgandhi 18:6a4db94011d3 11574 * | | |Setting this bit to 1 will generate a reset signal to the PDMA.
sahilmgandhi 18:6a4db94011d3 11575 * | | |User needs to set this bit to 0 to release from reset state.
sahilmgandhi 18:6a4db94011d3 11576 * | | |0 = PDMA controller normal operation.
sahilmgandhi 18:6a4db94011d3 11577 * | | |1 = PDMA controller reset.
sahilmgandhi 18:6a4db94011d3 11578 * |[3] |EBIRST |EBI Controller Reset (Write Protect)
sahilmgandhi 18:6a4db94011d3 11579 * | | |Set this bit to 1 will generate a reset signal to the EBI.
sahilmgandhi 18:6a4db94011d3 11580 * | | |User needs to set this bit to 0 to release from the reset state.
sahilmgandhi 18:6a4db94011d3 11581 * | | |0 = EBI controller normal operation.
sahilmgandhi 18:6a4db94011d3 11582 * | | |1 = EBI controller reset.
sahilmgandhi 18:6a4db94011d3 11583 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 11584 * |[4] |USBHRST |USBH Controller Reset (Write Protect)
sahilmgandhi 18:6a4db94011d3 11585 * | | |Set this bit to 1 will generate a reset signal to the USB host controller.
sahilmgandhi 18:6a4db94011d3 11586 * | | |User needs to set this bit to 0 to release from the reset state.
sahilmgandhi 18:6a4db94011d3 11587 * | | |0 = USBH controller normal operation.
sahilmgandhi 18:6a4db94011d3 11588 * | | |1 = USBH controller reset.
sahilmgandhi 18:6a4db94011d3 11589 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 11590 * |[7] |CRCRST |CRC Calculation Unit Reset (Write Protect)
sahilmgandhi 18:6a4db94011d3 11591 * | | |Set this bit to 1 will generate a reset signal to the CRC calculation module.
sahilmgandhi 18:6a4db94011d3 11592 * | | |User needs to set this bit to 0 to release from the reset state.
sahilmgandhi 18:6a4db94011d3 11593 * | | |0 = CRC Calculation unit normal operation.
sahilmgandhi 18:6a4db94011d3 11594 * | | |1 = CRC Calculation unit reset.
sahilmgandhi 18:6a4db94011d3 11595 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 11596 * @var SYS_T::IPRST1
sahilmgandhi 18:6a4db94011d3 11597 * Offset: 0x0C Peripheral Reset Control Register 1
sahilmgandhi 18:6a4db94011d3 11598 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11599 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11600 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11601 * |[1] |GPIORST |GPIO Controller Reset
sahilmgandhi 18:6a4db94011d3 11602 * | | |0 = GPIO controller normal operation.
sahilmgandhi 18:6a4db94011d3 11603 * | | |1 = GPIO controller reset.
sahilmgandhi 18:6a4db94011d3 11604 * |[2] |TMR0RST |Timer0 Controller Reset
sahilmgandhi 18:6a4db94011d3 11605 * | | |0 = Timer0 controller normal operation.
sahilmgandhi 18:6a4db94011d3 11606 * | | |1 = Timer0 controller reset.
sahilmgandhi 18:6a4db94011d3 11607 * |[3] |TMR1RST |Timer1 Controller Reset
sahilmgandhi 18:6a4db94011d3 11608 * | | |0 = Timer1 controller normal operation.
sahilmgandhi 18:6a4db94011d3 11609 * | | |1 = Timer1 controller reset.
sahilmgandhi 18:6a4db94011d3 11610 * |[4] |TMR2RST |Timer2 Controller Reset
sahilmgandhi 18:6a4db94011d3 11611 * | | |0 = Timer2 controller normal operation.
sahilmgandhi 18:6a4db94011d3 11612 * | | |1 = Timer2 controller reset.
sahilmgandhi 18:6a4db94011d3 11613 * |[5] |TMR3RST |Timer3 Controller Reset
sahilmgandhi 18:6a4db94011d3 11614 * | | |0 = Timer3 controller normal operation.
sahilmgandhi 18:6a4db94011d3 11615 * | | |1 = Timer3 controller reset.
sahilmgandhi 18:6a4db94011d3 11616 * |[7] |ACMP01RST |Analog Comparator 0/1 Controller Reset
sahilmgandhi 18:6a4db94011d3 11617 * | | |0 = Analog Comparator 0/1 controller normal operation.
sahilmgandhi 18:6a4db94011d3 11618 * | | |1 = Analog Comparator 0/1 controller reset.
sahilmgandhi 18:6a4db94011d3 11619 * |[8] |I2C0RST |I2C0 Controller Reset
sahilmgandhi 18:6a4db94011d3 11620 * | | |0 = I2C0 controller normal operation.
sahilmgandhi 18:6a4db94011d3 11621 * | | |1 = I2C0 controller reset.
sahilmgandhi 18:6a4db94011d3 11622 * |[9] |I2C1RST |I2C1 Controller Reset
sahilmgandhi 18:6a4db94011d3 11623 * | | |0 = I2C1 controller normal operation.
sahilmgandhi 18:6a4db94011d3 11624 * | | |1 = I2C1 controller reset.
sahilmgandhi 18:6a4db94011d3 11625 * |[12] |SPI0RST |SPI0 Controller Reset
sahilmgandhi 18:6a4db94011d3 11626 * | | |0 = SPI0 controller normal operation.
sahilmgandhi 18:6a4db94011d3 11627 * | | |1 = SPI0 controller reset.
sahilmgandhi 18:6a4db94011d3 11628 * |[13] |SPI1RST |SPI1 Controller Reset
sahilmgandhi 18:6a4db94011d3 11629 * | | |0 = SPI1 controller normal operation.
sahilmgandhi 18:6a4db94011d3 11630 * | | |1 = SPI1 controller reset.
sahilmgandhi 18:6a4db94011d3 11631 * |[14] |SPI2RST |SPI2 Controller Reset
sahilmgandhi 18:6a4db94011d3 11632 * | | |0 = SPI2 controller normal operation.
sahilmgandhi 18:6a4db94011d3 11633 * | | |1 = SPI2 controller reset.
sahilmgandhi 18:6a4db94011d3 11634 * |[16] |UART0RST |UART0 Controller Reset
sahilmgandhi 18:6a4db94011d3 11635 * | | |0 = UART0 controller normal operation.
sahilmgandhi 18:6a4db94011d3 11636 * | | |1 = UART0 controller reset.
sahilmgandhi 18:6a4db94011d3 11637 * |[17] |UART1RST |UART1 Controller Reset
sahilmgandhi 18:6a4db94011d3 11638 * | | |0 = UART1 controller normal operation.
sahilmgandhi 18:6a4db94011d3 11639 * | | |1 = UART1 controller reset.
sahilmgandhi 18:6a4db94011d3 11640 * |[18] |UART2RST |UART2 Controller Reset
sahilmgandhi 18:6a4db94011d3 11641 * | | |0 = UART2 controller normal operation.
sahilmgandhi 18:6a4db94011d3 11642 * | | |1 = UART2 controller reset.
sahilmgandhi 18:6a4db94011d3 11643 * |[19] |UART3RST |UART3 Controller Reset
sahilmgandhi 18:6a4db94011d3 11644 * | | |0 = UART3 controller normal operation.
sahilmgandhi 18:6a4db94011d3 11645 * | | |1 = UART3 controller reset.
sahilmgandhi 18:6a4db94011d3 11646 * |[24] |CAN0RST |CAN0 Controller Reset
sahilmgandhi 18:6a4db94011d3 11647 * | | |0 = CAN0 controller normal operation.
sahilmgandhi 18:6a4db94011d3 11648 * | | |1 = CAN0 controller reset.
sahilmgandhi 18:6a4db94011d3 11649 * |[26] |OTGRST |OTG Controller Reset
sahilmgandhi 18:6a4db94011d3 11650 * | | |0 = OTG controller normal operation.
sahilmgandhi 18:6a4db94011d3 11651 * | | |1 = OTG controller reset.
sahilmgandhi 18:6a4db94011d3 11652 * |[27] |USBDRST |USB Device Controller Reset
sahilmgandhi 18:6a4db94011d3 11653 * | | |0 = USB device controller normal operation.
sahilmgandhi 18:6a4db94011d3 11654 * | | |1 = USB device controller reset.
sahilmgandhi 18:6a4db94011d3 11655 * |[28] |EADCRST |EADC Controller Reset
sahilmgandhi 18:6a4db94011d3 11656 * | | |0 = EADC controller normal operation.
sahilmgandhi 18:6a4db94011d3 11657 * | | |1 = EADC controller reset.
sahilmgandhi 18:6a4db94011d3 11658 * @var SYS_T::IPRST2
sahilmgandhi 18:6a4db94011d3 11659 * Offset: 0x10 Peripheral Reset Control Register 2
sahilmgandhi 18:6a4db94011d3 11660 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11661 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11662 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11663 * |[0] |SC0RST |SC0 Controller Reset
sahilmgandhi 18:6a4db94011d3 11664 * | | |0 = SC0 controller normal operation.
sahilmgandhi 18:6a4db94011d3 11665 * | | |1 = SC0 controller reset.
sahilmgandhi 18:6a4db94011d3 11666 * |[12] |DACRST |DAC Controller Reset
sahilmgandhi 18:6a4db94011d3 11667 * | | |0 = DAC controller normal operation.
sahilmgandhi 18:6a4db94011d3 11668 * | | |1 = DAC controller reset.
sahilmgandhi 18:6a4db94011d3 11669 * |[16] |PWM0RST |PWM0 Controller Reset
sahilmgandhi 18:6a4db94011d3 11670 * | | |0 = PWM0 controller normal operation.
sahilmgandhi 18:6a4db94011d3 11671 * | | |1 = PWM0 controller reset.
sahilmgandhi 18:6a4db94011d3 11672 * |[17] |PWM1RST |PWM1 Controller Reset
sahilmgandhi 18:6a4db94011d3 11673 * | | |0 = PWM1 controller normal operation.
sahilmgandhi 18:6a4db94011d3 11674 * | | |1 = PWM1 controller reset.
sahilmgandhi 18:6a4db94011d3 11675 * |[25] |TKRST |Touch Key Controller Reset
sahilmgandhi 18:6a4db94011d3 11676 * | | |0 = Touch Key controller normal operation.
sahilmgandhi 18:6a4db94011d3 11677 * | | |1 = Touch Key controller reset.
sahilmgandhi 18:6a4db94011d3 11678 * @var SYS_T::BODCTL
sahilmgandhi 18:6a4db94011d3 11679 * Offset: 0x18 Brown-Out Detector Control Register
sahilmgandhi 18:6a4db94011d3 11680 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11681 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11682 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11683 * |[0] |BODEN |Brown-Out Detector Enable Bit (Write Protect)
sahilmgandhi 18:6a4db94011d3 11684 * | | |The default value is set by flash controller user configuration register CBODEN (CONFIG0 [23]).
sahilmgandhi 18:6a4db94011d3 11685 * | | |0 = Brown-out Detector function Disabled.
sahilmgandhi 18:6a4db94011d3 11686 * | | |1 = Brown-out Detector function Enabled.
sahilmgandhi 18:6a4db94011d3 11687 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 11688 * |[2:1] |BODVL |Brown-Out Detector Threshold Voltage Selection (Write Protect)
sahilmgandhi 18:6a4db94011d3 11689 * | | |The default value is set by flash controller user configuration register CBOV (CONFIG0 [22:21]).
sahilmgandhi 18:6a4db94011d3 11690 * | | |00 = Brown-Out Detector Threshold Voltage is 2.2V
sahilmgandhi 18:6a4db94011d3 11691 * | | |01 = Brown-Out Detector Threshold Voltage is 2.7V
sahilmgandhi 18:6a4db94011d3 11692 * | | |10 = Brown-Out Detector Threshold Voltage is 3.7V
sahilmgandhi 18:6a4db94011d3 11693 * | | |11 = Brown-Out Detector Threshold Voltage is 4.5V
sahilmgandhi 18:6a4db94011d3 11694 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 11695 * |[3] |BODRSTEN |Brown-Out Reset Enable Bit (Write Protect)
sahilmgandhi 18:6a4db94011d3 11696 * | | |The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit .
sahilmgandhi 18:6a4db94011d3 11697 * | | |0 = Brown-out "INTERRUPT" function Enabled.
sahilmgandhi 18:6a4db94011d3 11698 * | | |1 = Brown-out "RESET" function Enabled.
sahilmgandhi 18:6a4db94011d3 11699 * | | |Note1:
sahilmgandhi 18:6a4db94011d3 11700 * | | |While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).
sahilmgandhi 18:6a4db94011d3 11701 * | | |While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high.
sahilmgandhi 18:6a4db94011d3 11702 * | | |BOD interrupt will keep till to the BODEN set to 0.
sahilmgandhi 18:6a4db94011d3 11703 * | | |BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).
sahilmgandhi 18:6a4db94011d3 11704 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 11705 * |[4] |BODIF |Brown-Out Detector Interrupt Flag
sahilmgandhi 18:6a4db94011d3 11706 * | | |0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting.
sahilmgandhi 18:6a4db94011d3 11707 * | | |1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled.
sahilmgandhi 18:6a4db94011d3 11708 * | | |Note: Write 1 to clear this bit to 0.
sahilmgandhi 18:6a4db94011d3 11709 * |[5] |BODLPM |Brown-Out Detector Low Power Mode (Write Protect)
sahilmgandhi 18:6a4db94011d3 11710 * | | |0 = BOD operate in normal mode (default).
sahilmgandhi 18:6a4db94011d3 11711 * | | |1 = BOD Low Power mode Enabled.
sahilmgandhi 18:6a4db94011d3 11712 * | | |Note1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
sahilmgandhi 18:6a4db94011d3 11713 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 11714 * |[6] |BODOUT |Brown-Out Detector Output Status
sahilmgandhi 18:6a4db94011d3 11715 * | | |0 = Brown-out Detector output status is 0.
sahilmgandhi 18:6a4db94011d3 11716 * | | |It means the detected voltage is higher than BODVL setting or BODEN is 0.
sahilmgandhi 18:6a4db94011d3 11717 * | | |1 = Brown-out Detector output status is 1.
sahilmgandhi 18:6a4db94011d3 11718 * | | |It means the detected voltage is lower than BODVL setting.
sahilmgandhi 18:6a4db94011d3 11719 * | | |If the BODEN is 0, BOD function disabled , this bit always responds 0000.
sahilmgandhi 18:6a4db94011d3 11720 * |[7] |LVREN |Low Voltage Reset Enable Bit (Write Protect)
sahilmgandhi 18:6a4db94011d3 11721 * | | |The LVR function resets the chip when the input power voltage is lower than LVR circuit setting.
sahilmgandhi 18:6a4db94011d3 11722 * | | |LVR function is enabled by default.
sahilmgandhi 18:6a4db94011d3 11723 * | | |0 = Low Voltage Reset function Disabled.
sahilmgandhi 18:6a4db94011d3 11724 * | | |1 = Low Voltage Reset function Enabled
sahilmgandhi 18:6a4db94011d3 11725 * | | |Note1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default).
sahilmgandhi 18:6a4db94011d3 11726 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 11727 * |[10:8] |BODDGSEL |Brown-Out Detector Output De-Glitch Time Select (Write Protect)
sahilmgandhi 18:6a4db94011d3 11728 * | | |000 = BOD output is sampled by RC10K clock.
sahilmgandhi 18:6a4db94011d3 11729 * | | |001 = 4 system clock (HCLK).
sahilmgandhi 18:6a4db94011d3 11730 * | | |010 = 8 system clock (HCLK).
sahilmgandhi 18:6a4db94011d3 11731 * | | |011 = 16 system clock (HCLK).
sahilmgandhi 18:6a4db94011d3 11732 * | | |100 = 32 system clock (HCLK).
sahilmgandhi 18:6a4db94011d3 11733 * | | |101 = 64 system clock (HCLK).
sahilmgandhi 18:6a4db94011d3 11734 * | | |110 = 128 system clock (HCLK).
sahilmgandhi 18:6a4db94011d3 11735 * | | |111 = 256 system clock (HCLK).
sahilmgandhi 18:6a4db94011d3 11736 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 11737 * |[14:12] |LVRDGSEL |LVR Output De-Glitch Time Select (Write Protect)
sahilmgandhi 18:6a4db94011d3 11738 * | | |000 = Without de-glitch function.
sahilmgandhi 18:6a4db94011d3 11739 * | | |001 = 4 system clock (HCLK).
sahilmgandhi 18:6a4db94011d3 11740 * | | |010 = 8 system clock (HCLK).
sahilmgandhi 18:6a4db94011d3 11741 * | | |011 = 16 system clock (HCLK).
sahilmgandhi 18:6a4db94011d3 11742 * | | |100 = 32 system clock (HCLK).
sahilmgandhi 18:6a4db94011d3 11743 * | | |101 = 64 system clock (HCLK).
sahilmgandhi 18:6a4db94011d3 11744 * | | |110 = 128 system clock (HCLK).
sahilmgandhi 18:6a4db94011d3 11745 * | | |111 = 256 system clock (HCLK).
sahilmgandhi 18:6a4db94011d3 11746 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 11747 * @var SYS_T::IVSCTL
sahilmgandhi 18:6a4db94011d3 11748 * Offset: 0x1C Internal Voltage Source Control Register
sahilmgandhi 18:6a4db94011d3 11749 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11750 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11751 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11752 * |[0] |VTEMPEN |Temperature Sensor Enable Bit
sahilmgandhi 18:6a4db94011d3 11753 * | | |This bit is used to enable/disable temperature sensor function.
sahilmgandhi 18:6a4db94011d3 11754 * | | |0 = Temperature sensor function Disabled (default).
sahilmgandhi 18:6a4db94011d3 11755 * | | |1 = Temperature sensor function Enabled.
sahilmgandhi 18:6a4db94011d3 11756 * | | |Note: After this bit is set to 1, the value of temperature sensor output can be obtained from ADC conversion result.
sahilmgandhi 18:6a4db94011d3 11757 * | | |Please refer to ADC function chapter for details.
sahilmgandhi 18:6a4db94011d3 11758 * |[1] |VBATUGEN |VBAT Unity Gain Buffer Enable Bit
sahilmgandhi 18:6a4db94011d3 11759 * | | |This bit is used to enable/disable VBAT unity gain buffer function.
sahilmgandhi 18:6a4db94011d3 11760 * | | |0 = VBAT unity gain buffer function Disabled (default).
sahilmgandhi 18:6a4db94011d3 11761 * | | |1 = VBAT unity gain buffer function Enabled.
sahilmgandhi 18:6a4db94011d3 11762 * | | |Note: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result
sahilmgandhi 18:6a4db94011d3 11763 * @var SYS_T::PORCTL
sahilmgandhi 18:6a4db94011d3 11764 * Offset: 0x24 Power-On-Reset Controller Register
sahilmgandhi 18:6a4db94011d3 11765 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11766 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11767 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11768 * |[15:0] |POROFF |Power-On-Reset Enable Bit (Write Protect)
sahilmgandhi 18:6a4db94011d3 11769 * | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again.
sahilmgandhi 18:6a4db94011d3 11770 * | | |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
sahilmgandhi 18:6a4db94011d3 11771 * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
sahilmgandhi 18:6a4db94011d3 11772 * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function
sahilmgandhi 18:6a4db94011d3 11773 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 11774 * @var SYS_T::VREFCTL
sahilmgandhi 18:6a4db94011d3 11775 * Offset: 0x28 VREF Control Register
sahilmgandhi 18:6a4db94011d3 11776 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11777 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11778 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11779 * |[4:0] |VREFCTL |VREF Control Bits (Write Protect)
sahilmgandhi 18:6a4db94011d3 11780 * | | |00011 = VREF is internal 2.65V.
sahilmgandhi 18:6a4db94011d3 11781 * | | |00111 = VREF is internal 2.048V.
sahilmgandhi 18:6a4db94011d3 11782 * | | |01011 = VREF is internal 3.072V.
sahilmgandhi 18:6a4db94011d3 11783 * | | |01111 = VREF is internal 4.096V.
sahilmgandhi 18:6a4db94011d3 11784 * | | |Others = Reserved.
sahilmgandhi 18:6a4db94011d3 11785 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 11786 * @var SYS_T::USBPHY
sahilmgandhi 18:6a4db94011d3 11787 * Offset: 0x2C USB PHY Control Register
sahilmgandhi 18:6a4db94011d3 11788 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11789 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11790 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11791 * |[1:0] |USBROLE |USB Role Option (Write Protect)
sahilmgandhi 18:6a4db94011d3 11792 * | | |These two bits are used to select the role of USB.
sahilmgandhi 18:6a4db94011d3 11793 * | | |00 = Standard USB Device mode.
sahilmgandhi 18:6a4db94011d3 11794 * | | |01 = Standard USB Host mode.
sahilmgandhi 18:6a4db94011d3 11795 * | | |10 = ID dependent mode.
sahilmgandhi 18:6a4db94011d3 11796 * | | |11 = On-The-Go device mode.
sahilmgandhi 18:6a4db94011d3 11797 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 11798 * |[8] |LDO33EN |USB LDO33 Enable Bit (Write Protect)
sahilmgandhi 18:6a4db94011d3 11799 * | | |0 = USB LDO33 Disabled.
sahilmgandhi 18:6a4db94011d3 11800 * | | |1 = USB LDO33 Enabled.
sahilmgandhi 18:6a4db94011d3 11801 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 11802 * @var SYS_T::GPA_MFPL
sahilmgandhi 18:6a4db94011d3 11803 * Offset: 0x30 GPIOA Low Byte Multiple Function Control Register
sahilmgandhi 18:6a4db94011d3 11804 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11805 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11806 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11807 * |[3:0] |PA0MFP |PA.0 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11808 * |[7:4] |PA1MFP |PA.1 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11809 * |[11:8] |PA2MFP |PA.2 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11810 * |[15:12] |PA3MFP |PA.3 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11811 * |[19:16] |PA4MFP |PA.4 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11812 * |[23:20] |PA5MFP |PA.5 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11813 * |[27:24] |PA6MFP |PA.6 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11814 * |[31:28] |PA7MFP |PA.7 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11815 * @var SYS_T::GPA_MFPH
sahilmgandhi 18:6a4db94011d3 11816 * Offset: 0x34 GPIOA High Byte Multiple Function Control Register
sahilmgandhi 18:6a4db94011d3 11817 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11818 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11819 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11820 * |[3:0] |PA8MFP |PA.8 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11821 * |[7:4] |PA9MFP |PA.9 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11822 * |[11:8] |PA10MFP |PA.10 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11823 * |[15:12] |PA11MFP |PA.11 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11824 * |[19:16] |PA12MFP |PA.12 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11825 * |[23:20] |PA13MFP |PA.13 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11826 * |[27:24] |PA14MFP |PA.14 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11827 * |[31:28] |PA15MFP |PA.15 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11828 * @var SYS_T::GPB_MFPL
sahilmgandhi 18:6a4db94011d3 11829 * Offset: 0x38 GPIOB Low Byte Multiple Function Control Register
sahilmgandhi 18:6a4db94011d3 11830 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11831 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11832 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11833 * |[3:0] |PB0MFP |PB.0 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11834 * |[7:4] |PB1MFP |PB.1 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11835 * |[11:8] |PB2MFP |PB.2 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11836 * |[15:12] |PB3MFP |PB.3 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11837 * |[19:16] |PB4MFP |PB.4 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11838 * |[23:20] |PB5MFP |PB.5 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11839 * |[27:24] |PB6MFP |PB.6 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11840 * |[31:28] |PB7MFP |PB.7 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11841 * @var SYS_T::GPB_MFPH
sahilmgandhi 18:6a4db94011d3 11842 * Offset: 0x3C GPIOB High Byte Multiple Function Control Register
sahilmgandhi 18:6a4db94011d3 11843 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11844 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11845 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11846 * |[3:0] |PB8MFP |PB.8 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11847 * |[7:4] |PB9MFP |PB.9 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11848 * |[11:8] |PB10MFP |PB.10 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11849 * |[15:12] |PB11MFP |PB.11 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11850 * |[19:16] |PB12MFP |PB.12 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11851 * |[23:20] |PB13MFP |PB.13 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11852 * |[27:24] |PB14MFP |PB.14 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11853 * |[31:28] |PB15MFP |PB.15 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11854 * @var SYS_T::GPC_MFPL
sahilmgandhi 18:6a4db94011d3 11855 * Offset: 0x40 GPIOC Low Byte Multiple Function Control Register
sahilmgandhi 18:6a4db94011d3 11856 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11857 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11858 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11859 * |[3:0] |PC0MFP |PC.0 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11860 * |[7:4] |PC1MFP |PC.1 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11861 * |[11:8] |PC2MFP |PC.2 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11862 * |[15:12] |PC3MFP |PC.3 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11863 * |[19:16] |PC4MFP |PC.4 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11864 * |[23:20] |PC5MFP |PC.5 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11865 * |[27:24] |PC6MFP |PC.6 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11866 * |[31:28] |PC7MFP |PC.7 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11867 * @var SYS_T::GPC_MFPH
sahilmgandhi 18:6a4db94011d3 11868 * Offset: 0x44 GPIOC High Byte Multiple Function Control Register
sahilmgandhi 18:6a4db94011d3 11869 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11870 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11871 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11872 * |[3:0] |PC8MFP |PC.8 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11873 * |[7:4] |PC9MFP |PC.9 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11874 * |[11:8] |PC10MFP |PC.10 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11875 * |[15:12] |PC11MFP |PC.11 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11876 * |[19:16] |PC12MFP |PC.12 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11877 * |[23:20] |PC13MFP |PC.13 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11878 * |[27:24] |PC14MFP |PC.14 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11879 * |[31:28] |PC15MFP |PC.15 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11880 * @var SYS_T::GPD_MFPL
sahilmgandhi 18:6a4db94011d3 11881 * Offset: 0x48 GPIOD Low Byte Multiple Function Control Register
sahilmgandhi 18:6a4db94011d3 11882 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11883 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11884 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11885 * |[3:0] |PD0MFP |PD.0 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11886 * |[7:4] |PD1MFP |PD.1 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11887 * |[11:8] |PD2MFP |PD.2 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11888 * |[15:12] |PD3MFP |PD.3 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11889 * |[19:16] |PD4MFP |PD.4 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11890 * |[23:20] |PD5MFP |PD.5 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11891 * |[27:24] |PD6MFP |PD.6 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11892 * |[31:28] |PD7MFP |PD.7 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11893 * @var SYS_T::GPD_MFPH
sahilmgandhi 18:6a4db94011d3 11894 * Offset: 0x4C GPIOD High Byte Multiple Function Control Register
sahilmgandhi 18:6a4db94011d3 11895 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11896 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11897 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11898 * |[3:0] |PD8MFP |PD.8 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11899 * |[7:4] |PD9MFP |PD.9 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11900 * |[11:8] |PD10MFP |PD.10 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11901 * |[15:12] |PD11MFP |PD.11 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11902 * |[19:16] |PD12MFP |PD.12 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11903 * |[23:20] |PD13MFP |PD.13 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11904 * |[27:24] |PD14MFP |PD.14 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11905 * |[31:28] |PD15MFP |PD.15 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11906 * @var SYS_T::GPE_MFPL
sahilmgandhi 18:6a4db94011d3 11907 * Offset: 0x50 GPIOE Low Byte Multiple Function Control Register
sahilmgandhi 18:6a4db94011d3 11908 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11909 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11910 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11911 * |[3:0] |PE0MFP |PE.0 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11912 * |[7:4] |PE1MFP |PE.1 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11913 * |[11:8] |PE2MFP |PE.2 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11914 * |[15:12] |PE3MFP |PE.3 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11915 * |[19:16] |PE4MFP |PE.4 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11916 * |[23:20] |PE5MFP |PE.5 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11917 * |[27:24] |PE6MFP |PE.6 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11918 * |[31:28] |PE7MFP |PE.7 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11919 * @var SYS_T::GPE_MFPH
sahilmgandhi 18:6a4db94011d3 11920 * Offset: 0x54 GPIOE High Byte Multiple Function Control Register
sahilmgandhi 18:6a4db94011d3 11921 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11922 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11923 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11924 * |[3:0] |PE8MFP |PE.8 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11925 * |[7:4] |PE9MFP |PE.9 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11926 * |[11:8] |PE10MFP |PE.10 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11927 * |[15:12] |PE11MFP |PE.11 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11928 * |[19:16] |PE12MFP |PE.12 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11929 * |[23:20] |PE13MFP |PE.13 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11930 * |[27:24] |PE14_MFP |PE.14 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11931 * @var SYS_T::GPF_MFPL
sahilmgandhi 18:6a4db94011d3 11932 * Offset: 0x58 GPIOF Low Byte Multiple Function Control Register
sahilmgandhi 18:6a4db94011d3 11933 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11934 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11935 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11936 * |[3:0] |PF0MFP |PF.0 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11937 * |[7:4] |PF1MFP |PF.1 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11938 * |[11:8] |PF2MFP |PF.2 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11939 * |[15:12] |PF3MFP |PF.3 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11940 * |[19:16] |PF4MFP |PF.4 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11941 * |[23:20] |PF5MFP |PF.5 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11942 * |[27:24] |PF6MFP |PF.6 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11943 * |[31:28] |PF7MFP |PF.7 Multi-function Pin Selection
sahilmgandhi 18:6a4db94011d3 11944 * @var SYS_T::SRAM_INTCTL
sahilmgandhi 18:6a4db94011d3 11945 * Offset: 0xC0 System SRAM Interrupt Enable Control Register
sahilmgandhi 18:6a4db94011d3 11946 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11947 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11948 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11949 * |[0] |PERRIEN |SRAM Parity Check Error Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 11950 * | | |0 = SRAM parity check error interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 11951 * | | |1 = SRAM parity check error interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 11952 * @var SYS_T::SRAM_STATUS
sahilmgandhi 18:6a4db94011d3 11953 * Offset: 0xC4 System SRAM Parity Error Status Register
sahilmgandhi 18:6a4db94011d3 11954 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11955 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11956 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11957 * |[0] |PERRIF |SRAM Parity Check Error Flag
sahilmgandhi 18:6a4db94011d3 11958 * | | |0 = No System SRAM parity error.
sahilmgandhi 18:6a4db94011d3 11959 * | | |1 = System SRAM parity error occur.
sahilmgandhi 18:6a4db94011d3 11960 * @var SYS_T::SRAM_ERRADDR
sahilmgandhi 18:6a4db94011d3 11961 * Offset: 0xC8 System SRAM Parity Check Error Address Register
sahilmgandhi 18:6a4db94011d3 11962 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11963 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11964 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11965 * |[31:0] |ERRADDR |System SRAM Parity Error Address
sahilmgandhi 18:6a4db94011d3 11966 * | | |This register shows system SRAM parity error byte address.
sahilmgandhi 18:6a4db94011d3 11967 * @var SYS_T::SRAM_BISTCTL
sahilmgandhi 18:6a4db94011d3 11968 * Offset: 0xD0 System SRAM BIST Test Control Register
sahilmgandhi 18:6a4db94011d3 11969 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11970 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11971 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11972 * |[0] |SRBIST0 |1st
sahilmgandhi 18:6a4db94011d3 11973 * | | |SRAM BIST Enable Bit
sahilmgandhi 18:6a4db94011d3 11974 * | | |This bit enables BIST test for SRAM located in address 0x2000_0000 ~0x2000_3FFF
sahilmgandhi 18:6a4db94011d3 11975 * | | |0 = system SRAM BIST Disabled.
sahilmgandhi 18:6a4db94011d3 11976 * | | |1 = system SRAM BIST Enabled.
sahilmgandhi 18:6a4db94011d3 11977 * |[1] |SRBIST1 |2nd
sahilmgandhi 18:6a4db94011d3 11978 * | | |SRAM BIST Enable Bit
sahilmgandhi 18:6a4db94011d3 11979 * | | |This bit enables BIST test for SRAM located in address 0x2000_4000 ~0x2000_7FFF
sahilmgandhi 18:6a4db94011d3 11980 * | | |0 = system SRAM BIST Disabled.
sahilmgandhi 18:6a4db94011d3 11981 * | | |1 = system SRAM BIST Enabled.
sahilmgandhi 18:6a4db94011d3 11982 * |[2] |CRBIST |CACHE BIST Enable Bit
sahilmgandhi 18:6a4db94011d3 11983 * | | |This bit enables BIST test for CACHE RAM
sahilmgandhi 18:6a4db94011d3 11984 * | | |0 = system CACHE BIST Disabled.
sahilmgandhi 18:6a4db94011d3 11985 * | | |1 = system CACHE BIST Enabled.
sahilmgandhi 18:6a4db94011d3 11986 * |[3] |CANBIST |CAN BIST Enable Bit
sahilmgandhi 18:6a4db94011d3 11987 * | | |This bit enables BIST test for CAN RAM
sahilmgandhi 18:6a4db94011d3 11988 * | | |0 = system CAN BIST Disabled.
sahilmgandhi 18:6a4db94011d3 11989 * | | |1 = system CAN BIST Enabled.
sahilmgandhi 18:6a4db94011d3 11990 * |[4] |USBBIST |USB BIST Enable Bit
sahilmgandhi 18:6a4db94011d3 11991 * | | |This bit enables BIST test for USB RAM
sahilmgandhi 18:6a4db94011d3 11992 * | | |0 = system USB BIST Disabled.
sahilmgandhi 18:6a4db94011d3 11993 * | | |1 = system USB BIST Enabled.
sahilmgandhi 18:6a4db94011d3 11994 * @var SYS_T::SRAM_BISTSTS
sahilmgandhi 18:6a4db94011d3 11995 * Offset: 0xD4 System SRAM BIST Test Status Register
sahilmgandhi 18:6a4db94011d3 11996 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 11997 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 11998 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 11999 * |[0] |SRBISTEF0 |1st System SRAM BIST Fail Flag
sahilmgandhi 18:6a4db94011d3 12000 * | | |0 = 1st system SRAM BIST test pass.
sahilmgandhi 18:6a4db94011d3 12001 * | | |1 = 1st system SRAM BIST test fail.
sahilmgandhi 18:6a4db94011d3 12002 * |[1] |SRBISTEF1 |2nd System SRAM BIST Fail Flag
sahilmgandhi 18:6a4db94011d3 12003 * | | |0 = 2nd system SRAM BIST test pass.
sahilmgandhi 18:6a4db94011d3 12004 * | | |1 = 2nd system SRAM BIST test fail.
sahilmgandhi 18:6a4db94011d3 12005 * |[2] |CRBISTEF |CACHE SRAM BIST Fail Flag
sahilmgandhi 18:6a4db94011d3 12006 * | | |0 = System CACHE RAM BIST test pass.
sahilmgandhi 18:6a4db94011d3 12007 * | | |1 = System CACHE RAM BIST test fail.
sahilmgandhi 18:6a4db94011d3 12008 * |[3] |CANBEF |CAN SRAM BIST Fail Flag
sahilmgandhi 18:6a4db94011d3 12009 * | | |0 = CAN SRAM BIST test pass.
sahilmgandhi 18:6a4db94011d3 12010 * | | |1 = CAN SRAM BIST test fail.
sahilmgandhi 18:6a4db94011d3 12011 * |[4] |USBBEF |USB SRAM BIST Fail Flag
sahilmgandhi 18:6a4db94011d3 12012 * | | |0 = USB SRAM BIST test pass.
sahilmgandhi 18:6a4db94011d3 12013 * | | |1 = USB SRAM BIST test fail.
sahilmgandhi 18:6a4db94011d3 12014 * |[16] |SRBEND0 |1st SRAM BIST Test Finish
sahilmgandhi 18:6a4db94011d3 12015 * | | |0 = 1st system SRAM BIST active.
sahilmgandhi 18:6a4db94011d3 12016 * | | |1 = 1st system SRAM BIST finish.
sahilmgandhi 18:6a4db94011d3 12017 * |[17] |SRBEND1 |2nd SRAM BIST Test Finish
sahilmgandhi 18:6a4db94011d3 12018 * | | |0 = 2nd system SRAM BIST is active.
sahilmgandhi 18:6a4db94011d3 12019 * | | |1 = 2nd system SRAM BIST finish.
sahilmgandhi 18:6a4db94011d3 12020 * |[18] |CRBEND |CACHE SRAM BIST Test Finish
sahilmgandhi 18:6a4db94011d3 12021 * | | |0 = System CACHE RAM BIST is active.
sahilmgandhi 18:6a4db94011d3 12022 * | | |1 = System CACHE RAM BIST test finish.
sahilmgandhi 18:6a4db94011d3 12023 * |[19] |CANBEND |CAN SRAM BIST Test Finish
sahilmgandhi 18:6a4db94011d3 12024 * | | |0 = CAN SRAM BIST is active.
sahilmgandhi 18:6a4db94011d3 12025 * | | |1 = CAN SRAM BIST test finish.
sahilmgandhi 18:6a4db94011d3 12026 * |[20] |USBBEND |USB SRAM BIST Test Finish
sahilmgandhi 18:6a4db94011d3 12027 * | | |0 = USB SRAM BIST is active.
sahilmgandhi 18:6a4db94011d3 12028 * | | |1 = USB SRAM BIST test finish.
sahilmgandhi 18:6a4db94011d3 12029 * @var SYS_T::IRCTCTL
sahilmgandhi 18:6a4db94011d3 12030 * Offset: 0xF0 IRC Trim Control Register
sahilmgandhi 18:6a4db94011d3 12031 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 12032 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 12033 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 12034 * |[1:0] |FREQSEL |Trim Frequency Selection
sahilmgandhi 18:6a4db94011d3 12035 * | | |This field indicates the target frequency of internal 22.1184 MHz high-speed oscillator auto trim.
sahilmgandhi 18:6a4db94011d3 12036 * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
sahilmgandhi 18:6a4db94011d3 12037 * | | |00 = Disable HIRC auto trim function.
sahilmgandhi 18:6a4db94011d3 12038 * | | |01 = Enable HIRC auto trim function and trim HIRC to 22.1184 MHz.
sahilmgandhi 18:6a4db94011d3 12039 * | | |10 = Enable HIRC auto trim function and trim HIRC to 24 MHz.
sahilmgandhi 18:6a4db94011d3 12040 * | | |11 = Reserved.
sahilmgandhi 18:6a4db94011d3 12041 * |[5:4] |LOOPSEL |Trim Calculation Loop Selection
sahilmgandhi 18:6a4db94011d3 12042 * | | |This field defines that trim value calculation is based on how many 32.768 kHz clock.
sahilmgandhi 18:6a4db94011d3 12043 * | | |00 = Trim value calculation is based on average difference in 4 32.768 kHz clock.
sahilmgandhi 18:6a4db94011d3 12044 * | | |01 = Trim value calculation is based on average difference in 8 32.768 kHz clock.
sahilmgandhi 18:6a4db94011d3 12045 * | | |10 = Trim value calculation is based on average difference in 16 32.768 kHz clock.
sahilmgandhi 18:6a4db94011d3 12046 * | | |11 = Trim value calculation is based on average difference in 32 32.768 kHz clock.
sahilmgandhi 18:6a4db94011d3 12047 * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.
sahilmgandhi 18:6a4db94011d3 12048 * |[7:6] |RETRYCNT |Trim Value Update Limitation Count
sahilmgandhi 18:6a4db94011d3 12049 * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.
sahilmgandhi 18:6a4db94011d3 12050 * | | |Once the HIRC locked, the internal trim value update counter will be reset.
sahilmgandhi 18:6a4db94011d3 12051 * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
sahilmgandhi 18:6a4db94011d3 12052 * | | |00 = Trim retry count limitation is 64 loops.
sahilmgandhi 18:6a4db94011d3 12053 * | | |01 = Trim retry count limitation is 128 loops.
sahilmgandhi 18:6a4db94011d3 12054 * | | |10 = Trim retry count limitation is 256 loops.
sahilmgandhi 18:6a4db94011d3 12055 * | | |11 = Trim retry count limitation is 512 loops.
sahilmgandhi 18:6a4db94011d3 12056 * |[8] |CESTOPEN |Clock Error Stop Enable Bit
sahilmgandhi 18:6a4db94011d3 12057 * | | |0 = The trim operation is keep going if clock is inaccuracy.
sahilmgandhi 18:6a4db94011d3 12058 * | | |1 = The trim operation is stopped if clock is inaccuracy.
sahilmgandhi 18:6a4db94011d3 12059 * @var SYS_T::IRCTIEN
sahilmgandhi 18:6a4db94011d3 12060 * Offset: 0xF4 IRC Trim Interrupt Enable Register
sahilmgandhi 18:6a4db94011d3 12061 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 12062 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 12063 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 12064 * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 12065 * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]).
sahilmgandhi 18:6a4db94011d3 12066 * | | |If this bit is high and TFAILIF(SYS_IRCTSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
sahilmgandhi 18:6a4db94011d3 12067 * | | |0 = Disable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU.
sahilmgandhi 18:6a4db94011d3 12068 * | | |1 = Enable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU.
sahilmgandhi 18:6a4db94011d3 12069 * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 12070 * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.
sahilmgandhi 18:6a4db94011d3 12071 * | | |If this bit is set to1, and CLKERRIF(SYS_IRCTSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
sahilmgandhi 18:6a4db94011d3 12072 * | | |0 = Disable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU.
sahilmgandhi 18:6a4db94011d3 12073 * | | |1 = Enable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU.
sahilmgandhi 18:6a4db94011d3 12074 * @var SYS_T::IRCTISTS
sahilmgandhi 18:6a4db94011d3 12075 * Offset: 0xF8 IRC Trim Interrupt Status Register
sahilmgandhi 18:6a4db94011d3 12076 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 12077 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 12078 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 12079 * |[0] |FREQLOCK |HIRC Frequency Lock Status
sahilmgandhi 18:6a4db94011d3 12080 * | | |This bit indicates the internal 22.1184 MHz high-speed oscillator frequency is locked.
sahilmgandhi 18:6a4db94011d3 12081 * | | |This is a status bit and doesn't trigger any interrupt.
sahilmgandhi 18:6a4db94011d3 12082 * |[1] |TFAILIF |Trim Failure Interrupt Status
sahilmgandhi 18:6a4db94011d3 12083 * | | |This bit indicates that internal 22.1184 MHz high-speed oscillator trim value update limitation count reached and the internal 22.1184 MHz high-speed oscillator clock frequency still doesn't be locked.
sahilmgandhi 18:6a4db94011d3 12084 * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_iRCTCTL[1:0]) will be cleared to 00 by hardware automatically.
sahilmgandhi 18:6a4db94011d3 12085 * | | |If this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
sahilmgandhi 18:6a4db94011d3 12086 * | | |Write 1 to clear this to 0.
sahilmgandhi 18:6a4db94011d3 12087 * | | |0 = Trim value update limitation count does not reach.
sahilmgandhi 18:6a4db94011d3 12088 * | | |1 = Trim value update limitation count reached and internal 22.1184 MHz high-speed oscillator frequency still not locked.
sahilmgandhi 18:6a4db94011d3 12089 * |[2] |CLKERRIF |Clock Error Interrupt Status
sahilmgandhi 18:6a4db94011d3 12090 * | | |When the frequency of external 32.768 kHz low-speed crystal or internal 22.1184 MHz high-speed oscillator is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy
sahilmgandhi 18:6a4db94011d3 12091 * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1.
sahilmgandhi 18:6a4db94011d3 12092 * | | |If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy.
sahilmgandhi 18:6a4db94011d3 12093 * | | |Write 1 to clear this to 0.
sahilmgandhi 18:6a4db94011d3 12094 * | | |0 = Clock frequency is accuracy.
sahilmgandhi 18:6a4db94011d3 12095 * | | |1 = Clock frequency is inaccuracy.
sahilmgandhi 18:6a4db94011d3 12096 * @var SYS_T::REGLCTL
sahilmgandhi 18:6a4db94011d3 12097 * Offset: 0x100 Register Lock Control Register
sahilmgandhi 18:6a4db94011d3 12098 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 12099 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 12100 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 12101 * |[7:0] |REGLCTL |Register Lock Control Code
sahilmgandhi 18:6a4db94011d3 12102 * | | |Write operation:
sahilmgandhi 18:6a4db94011d3 12103 * | | |Some registers have write-protection function.
sahilmgandhi 18:6a4db94011d3 12104 * | | |Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field.
sahilmgandhi 18:6a4db94011d3 12105 * | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
sahilmgandhi 18:6a4db94011d3 12106 * | | |Read operation:
sahilmgandhi 18:6a4db94011d3 12107 * | | |0 = Write-protection Enabled for writing protected registers.
sahilmgandhi 18:6a4db94011d3 12108 * | | |Any write to the protected register is ignored.
sahilmgandhi 18:6a4db94011d3 12109 * | | |1 = Write-protection Disabled for writing protected registers.
sahilmgandhi 18:6a4db94011d3 12110 * | | |The Protected registers are:
sahilmgandhi 18:6a4db94011d3 12111 * | | |SYS_IPRST0: address 0x4000_0008
sahilmgandhi 18:6a4db94011d3 12112 * | | |SYS_BODCTL: address 0x4000_0018
sahilmgandhi 18:6a4db94011d3 12113 * | | |SYS_PORCTL: address 0x4000_0024
sahilmgandhi 18:6a4db94011d3 12114 * | | |SYS_VREFCTL: address 0x4000_0028
sahilmgandhi 18:6a4db94011d3 12115 * | | |SYS_USBPHY: address 0x4000_002C
sahilmgandhi 18:6a4db94011d3 12116 * | | |CLK_PWRCTL: address 0x4000_0200 (bit[6] is not protected for power wake-up interrupt clear)
sahilmgandhi 18:6a4db94011d3 12117 * | | |SYS_SRAM_BISTCTL: address 0x4000_00D0
sahilmgandhi 18:6a4db94011d3 12118 * | | |CLK_APBCLK0 [0]: address 0x4000_0208 (bit[0] is watchdog clock enable)
sahilmgandhi 18:6a4db94011d3 12119 * | | |CLK_CLKSEL0: address 0x4000_0210 (for HCLK and CPU STCLK clock source select)
sahilmgandhi 18:6a4db94011d3 12120 * | | |CLK_CLKSEL1 [1:0]: address 0x4000_0214 (for watchdog clock source select)
sahilmgandhi 18:6a4db94011d3 12121 * | | |CLK_CLKSEL1 [31:30]: address 0x4000_0214 (for window watchdog clock source select)
sahilmgandhi 18:6a4db94011d3 12122 * | | |CLK_CLKDSTS: address 0x4000_0274
sahilmgandhi 18:6a4db94011d3 12123 * | | |NMIEN: address 0x4000_0300
sahilmgandhi 18:6a4db94011d3 12124 * | | |FMC_ISPCTL: address 0x4000_C000 (Flash ISP Control register)
sahilmgandhi 18:6a4db94011d3 12125 * | | |FMC_ISPTRG: address 0x4000_C010 (ISP Trigger Control register)
sahilmgandhi 18:6a4db94011d3 12126 * | | |FMC_ISPSTS: address 0x4000_C040
sahilmgandhi 18:6a4db94011d3 12127 * | | |WDT_CTL: address 0x4004_0000
sahilmgandhi 18:6a4db94011d3 12128 * | | |FMC_FTCTL: address 0x4000_5018
sahilmgandhi 18:6a4db94011d3 12129 * | | |FMC_ICPCMD: address 0x4000_501C
sahilmgandhi 18:6a4db94011d3 12130 * | | |CLK_PLLCTL: address 0x40000240
sahilmgandhi 18:6a4db94011d3 12131 * | | |PWM_CTL0: address 0x4005_8000
sahilmgandhi 18:6a4db94011d3 12132 * | | |PWM_CTL0: address 0x4005_9000
sahilmgandhi 18:6a4db94011d3 12133 * | | |PWM_DTCTL0_1: address 0x4005_8070
sahilmgandhi 18:6a4db94011d3 12134 * | | |PWM_DTCTL0_1: address 0x4005_9070
sahilmgandhi 18:6a4db94011d3 12135 * | | |PWM_DTCTL2_3: address 0x4005_8074
sahilmgandhi 18:6a4db94011d3 12136 * | | |PWM_DTCTL2_3: address 0x4005_9074
sahilmgandhi 18:6a4db94011d3 12137 * | | |PWM_DTCTL4_5: address 0x4005_8078
sahilmgandhi 18:6a4db94011d3 12138 * | | |PWM_DTCTL4_5: address 0x4005_9078
sahilmgandhi 18:6a4db94011d3 12139 * | | |PWM_BRKCTL0_1: address 0x4005_80C8
sahilmgandhi 18:6a4db94011d3 12140 * | | |PWM_BRKCTL0_1: address 0x4005_90C8
sahilmgandhi 18:6a4db94011d3 12141 * | | |PWM_BRKCTL2_3: address0x4005_80CC
sahilmgandhi 18:6a4db94011d3 12142 * | | |PWM_BRKCTL2_3: address0x4005_90CC
sahilmgandhi 18:6a4db94011d3 12143 * | | |PWM_BRKCTL4_5: address0x4005_80D0
sahilmgandhi 18:6a4db94011d3 12144 * | | |PWM_BRKCTL4_5: address0x4005_90D0
sahilmgandhi 18:6a4db94011d3 12145 * | | |PWM_INTEN1: address0x4005_80E4
sahilmgandhi 18:6a4db94011d3 12146 * | | |PWM_INTEN1: address0x4005_90E4
sahilmgandhi 18:6a4db94011d3 12147 * | | |PWM_INTSTS1: address0x4005_80EC
sahilmgandhi 18:6a4db94011d3 12148 * | | |PWM_INTSTS1: address0x4005_90EC
sahilmgandhi 18:6a4db94011d3 12149 */
sahilmgandhi 18:6a4db94011d3 12150
sahilmgandhi 18:6a4db94011d3 12151 __I uint32_t PDID; /* Offset: 0x00 Part Device Identification Number Register */
sahilmgandhi 18:6a4db94011d3 12152 __IO uint32_t RSTSTS; /* Offset: 0x04 System Reset Status Register */
sahilmgandhi 18:6a4db94011d3 12153 __IO uint32_t IPRST0; /* Offset: 0x08 Peripheral Reset Control Register 0 */
sahilmgandhi 18:6a4db94011d3 12154 __IO uint32_t IPRST1; /* Offset: 0x0C Peripheral Reset Control Register 1 */
sahilmgandhi 18:6a4db94011d3 12155 __IO uint32_t IPRST2; /* Offset: 0x10 Peripheral Reset Control Register 2 */
sahilmgandhi 18:6a4db94011d3 12156 __I uint32_t RESERVE0[1];
sahilmgandhi 18:6a4db94011d3 12157 __IO uint32_t BODCTL; /* Offset: 0x18 Brown-Out Detector Control Register */
sahilmgandhi 18:6a4db94011d3 12158 __IO uint32_t IVSCTL; /* Offset: 0x1C Internal Voltage Source Control Register */
sahilmgandhi 18:6a4db94011d3 12159 __I uint32_t RESERVE1[1];
sahilmgandhi 18:6a4db94011d3 12160 __IO uint32_t PORCTL; /* Offset: 0x24 Power-On-Reset Controller Register */
sahilmgandhi 18:6a4db94011d3 12161 __IO uint32_t VREFCTL; /* Offset: 0x28 VREF Control Register */
sahilmgandhi 18:6a4db94011d3 12162 __IO uint32_t USBPHY; /* Offset: 0x2C USB PHY Control Register */
sahilmgandhi 18:6a4db94011d3 12163 __IO uint32_t GPA_MFPL; /* Offset: 0x30 GPIOA Low Byte Multiple Function Control Register */
sahilmgandhi 18:6a4db94011d3 12164 __IO uint32_t GPA_MFPH; /* Offset: 0x34 GPIOA High Byte Multiple Function Control Register */
sahilmgandhi 18:6a4db94011d3 12165 __IO uint32_t GPB_MFPL; /* Offset: 0x38 GPIOB Low Byte Multiple Function Control Register */
sahilmgandhi 18:6a4db94011d3 12166 __IO uint32_t GPB_MFPH; /* Offset: 0x3C GPIOB High Byte Multiple Function Control Register */
sahilmgandhi 18:6a4db94011d3 12167 __IO uint32_t GPC_MFPL; /* Offset: 0x40 GPIOC Low Byte Multiple Function Control Register */
sahilmgandhi 18:6a4db94011d3 12168 __IO uint32_t GPC_MFPH; /* Offset: 0x44 GPIOC High Byte Multiple Function Control Register */
sahilmgandhi 18:6a4db94011d3 12169 __IO uint32_t GPD_MFPL; /* Offset: 0x48 GPIOD Low Byte Multiple Function Control Register */
sahilmgandhi 18:6a4db94011d3 12170 __IO uint32_t GPD_MFPH; /* Offset: 0x4C GPIOD High Byte Multiple Function Control Register */
sahilmgandhi 18:6a4db94011d3 12171 __IO uint32_t GPE_MFPL; /* Offset: 0x50 GPIOE Low Byte Multiple Function Control Register */
sahilmgandhi 18:6a4db94011d3 12172 __IO uint32_t GPE_MFPH; /* Offset: 0x54 GPIOE High Byte Multiple Function Control Register */
sahilmgandhi 18:6a4db94011d3 12173 __IO uint32_t GPF_MFPL; /* Offset: 0x58 GPIOF Low Byte Multiple Function Control Register */
sahilmgandhi 18:6a4db94011d3 12174 __I uint32_t RESERVE2[25];
sahilmgandhi 18:6a4db94011d3 12175 __IO uint32_t SRAM_INTCTL; /* Offset: 0xC0 System SRAM Interrupt Enable Control Register */
sahilmgandhi 18:6a4db94011d3 12176 __I uint32_t SRAM_STATUS; /* Offset: 0xC4 System SRAM Parity Error Status Register */
sahilmgandhi 18:6a4db94011d3 12177 __I uint32_t SRAM_ERRADDR; /* Offset: 0xC8 System SRAM Parity Check Error Address Register */
sahilmgandhi 18:6a4db94011d3 12178 __I uint32_t RESERVE3[1];
sahilmgandhi 18:6a4db94011d3 12179 __IO uint32_t SRAM_BISTCTL; /* Offset: 0xD0 System SRAM BIST Test Control Register */
sahilmgandhi 18:6a4db94011d3 12180 __I uint32_t SRAM_BISTSTS; /* Offset: 0xD4 System SRAM BIST Test Status Register */
sahilmgandhi 18:6a4db94011d3 12181 __I uint32_t RESERVE4[6];
sahilmgandhi 18:6a4db94011d3 12182 __IO uint32_t IRCTCTL; /* Offset: 0xF0 IRC Trim Control Register */
sahilmgandhi 18:6a4db94011d3 12183 __IO uint32_t IRCTIEN; /* Offset: 0xF4 IRC Trim Interrupt Enable Register */
sahilmgandhi 18:6a4db94011d3 12184 __IO uint32_t IRCTISTS; /* Offset: 0xF8 IRC Trim Interrupt Status Register */
sahilmgandhi 18:6a4db94011d3 12185 __I uint32_t RESERVE5[1];
sahilmgandhi 18:6a4db94011d3 12186 __IO uint32_t REGLCTL; /* Offset: 0x100 Register Lock Control Register */
sahilmgandhi 18:6a4db94011d3 12187
sahilmgandhi 18:6a4db94011d3 12188 } SYS_T;
sahilmgandhi 18:6a4db94011d3 12189
sahilmgandhi 18:6a4db94011d3 12190
sahilmgandhi 18:6a4db94011d3 12191
sahilmgandhi 18:6a4db94011d3 12192 /**
sahilmgandhi 18:6a4db94011d3 12193 @addtogroup SYS_CONST SYS Bit Field Definition
sahilmgandhi 18:6a4db94011d3 12194 Constant Definitions for SYS Controller
sahilmgandhi 18:6a4db94011d3 12195 @{ */
sahilmgandhi 18:6a4db94011d3 12196
sahilmgandhi 18:6a4db94011d3 12197 #define SYS_PDID_PDID_Pos (0) /*!< SYS_T::PDID: PDID Position */
sahilmgandhi 18:6a4db94011d3 12198 #define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) /*!< SYS_T::PDID: PDID Mask */
sahilmgandhi 18:6a4db94011d3 12199
sahilmgandhi 18:6a4db94011d3 12200 #define SYS_RSTSTS_PORF_Pos (0) /*!< SYS_T::RSTSTS: PORF Position */
sahilmgandhi 18:6a4db94011d3 12201 #define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) /*!< SYS_T::RSTSTS: PORF Mask */
sahilmgandhi 18:6a4db94011d3 12202
sahilmgandhi 18:6a4db94011d3 12203 #define SYS_RSTSTS_PINRF_Pos (1) /*!< SYS_T::RSTSTS: PINRF Position */
sahilmgandhi 18:6a4db94011d3 12204 #define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) /*!< SYS_T::RSTSTS: PINRF Mask */
sahilmgandhi 18:6a4db94011d3 12205
sahilmgandhi 18:6a4db94011d3 12206 #define SYS_RSTSTS_WDTRF_Pos (2) /*!< SYS_T::RSTSTS: WDTRF Position */
sahilmgandhi 18:6a4db94011d3 12207 #define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) /*!< SYS_T::RSTSTS: WDTRF Mask */
sahilmgandhi 18:6a4db94011d3 12208
sahilmgandhi 18:6a4db94011d3 12209 #define SYS_RSTSTS_LVRF_Pos (3) /*!< SYS_T::RSTSTS: LVRF Position */
sahilmgandhi 18:6a4db94011d3 12210 #define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) /*!< SYS_T::RSTSTS: LVRF Mask */
sahilmgandhi 18:6a4db94011d3 12211
sahilmgandhi 18:6a4db94011d3 12212 #define SYS_RSTSTS_BODRF_Pos (4) /*!< SYS_T::RSTSTS: BODRF Position */
sahilmgandhi 18:6a4db94011d3 12213 #define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) /*!< SYS_T::RSTSTS: BODRF Mask */
sahilmgandhi 18:6a4db94011d3 12214
sahilmgandhi 18:6a4db94011d3 12215 #define SYS_RSTSTS_SYSRF_Pos (5) /*!< SYS_T::RSTSTS: SYSRF Position */
sahilmgandhi 18:6a4db94011d3 12216 #define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) /*!< SYS_T::RSTSTS: SYSRF Mask */
sahilmgandhi 18:6a4db94011d3 12217
sahilmgandhi 18:6a4db94011d3 12218 #define SYS_RSTSTS_CPURF_Pos (7) /*!< SYS_T::RSTSTS: CPURF Position */
sahilmgandhi 18:6a4db94011d3 12219 #define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) /*!< SYS_T::RSTSTS: CPURF Mask */
sahilmgandhi 18:6a4db94011d3 12220
sahilmgandhi 18:6a4db94011d3 12221 #define SYS_RSTSTS_CPULKRF_Pos (8) /*!< SYS_T::RSTSTS: CPULKRF Position */
sahilmgandhi 18:6a4db94011d3 12222 #define SYS_RSTSTS_CPULKRF_Msk (0x1ul << SYS_RSTSTS_CPULKRF_Pos) /*!< SYS_T::RSTSTS: CPULKRF Mask */
sahilmgandhi 18:6a4db94011d3 12223
sahilmgandhi 18:6a4db94011d3 12224 #define SYS_IPRST0_CHIPRST_Pos (0) /*!< SYS_T::IPRST0: CHIPRST Position */
sahilmgandhi 18:6a4db94011d3 12225 #define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) /*!< SYS_T::IPRST0: CHIPRST Mask */
sahilmgandhi 18:6a4db94011d3 12226
sahilmgandhi 18:6a4db94011d3 12227 #define SYS_IPRST0_CPURST_Pos (1) /*!< SYS_T::IPRST0: CPURST Position */
sahilmgandhi 18:6a4db94011d3 12228 #define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) /*!< SYS_T::IPRST0: CPURST Mask */
sahilmgandhi 18:6a4db94011d3 12229
sahilmgandhi 18:6a4db94011d3 12230 #define SYS_IPRST0_PDMARST_Pos (2) /*!< SYS_T::IPRST0: PDMARST Position */
sahilmgandhi 18:6a4db94011d3 12231 #define SYS_IPRST0_PDMARST_Msk (0x1ul << SYS_IPRST0_PDMARST_Pos) /*!< SYS_T::IPRST0: PDMARST Mask */
sahilmgandhi 18:6a4db94011d3 12232
sahilmgandhi 18:6a4db94011d3 12233 #define SYS_IPRST0_EBIRST_Pos (3) /*!< SYS_T::IPRST0: EBIRST Position */
sahilmgandhi 18:6a4db94011d3 12234 #define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) /*!< SYS_T::IPRST0: EBIRST Mask */
sahilmgandhi 18:6a4db94011d3 12235
sahilmgandhi 18:6a4db94011d3 12236 #define SYS_IPRST0_USBHRST_Pos (4) /*!< SYS_T::IPRST0: USBHRST Position */
sahilmgandhi 18:6a4db94011d3 12237 #define SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos) /*!< SYS_T::IPRST0: USBHRST Mask */
sahilmgandhi 18:6a4db94011d3 12238
sahilmgandhi 18:6a4db94011d3 12239 #define SYS_IPRST0_CRCRST_Pos (7) /*!< SYS_T::IPRST0: CRCRST Position */
sahilmgandhi 18:6a4db94011d3 12240 #define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) /*!< SYS_T::IPRST0: CRCRST Mask */
sahilmgandhi 18:6a4db94011d3 12241
sahilmgandhi 18:6a4db94011d3 12242 #define SYS_IPRST1_GPIORST_Pos (1) /*!< SYS_T::IPRST1: GPIORST Position */
sahilmgandhi 18:6a4db94011d3 12243 #define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) /*!< SYS_T::IPRST1: GPIORST Mask */
sahilmgandhi 18:6a4db94011d3 12244
sahilmgandhi 18:6a4db94011d3 12245 #define SYS_IPRST1_TMR0RST_Pos (2) /*!< SYS_T::IPRST1: TMR0RST Position */
sahilmgandhi 18:6a4db94011d3 12246 #define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) /*!< SYS_T::IPRST1: TMR0RST Mask */
sahilmgandhi 18:6a4db94011d3 12247
sahilmgandhi 18:6a4db94011d3 12248 #define SYS_IPRST1_TMR1RST_Pos (3) /*!< SYS_T::IPRST1: TMR1RST Position */
sahilmgandhi 18:6a4db94011d3 12249 #define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) /*!< SYS_T::IPRST1: TMR1RST Mask */
sahilmgandhi 18:6a4db94011d3 12250
sahilmgandhi 18:6a4db94011d3 12251 #define SYS_IPRST1_TMR2RST_Pos (4) /*!< SYS_T::IPRST1: TMR2RST Position */
sahilmgandhi 18:6a4db94011d3 12252 #define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) /*!< SYS_T::IPRST1: TMR2RST Mask */
sahilmgandhi 18:6a4db94011d3 12253
sahilmgandhi 18:6a4db94011d3 12254 #define SYS_IPRST1_TMR3RST_Pos (5) /*!< SYS_T::IPRST1: TMR3RST Position */
sahilmgandhi 18:6a4db94011d3 12255 #define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) /*!< SYS_T::IPRST1: TMR3RST Mask */
sahilmgandhi 18:6a4db94011d3 12256
sahilmgandhi 18:6a4db94011d3 12257 #define SYS_IPRST1_ACMP01RST_Pos (7) /*!< SYS_T::IPRST1: ACMP01RST Position */
sahilmgandhi 18:6a4db94011d3 12258 #define SYS_IPRST1_ACMP01RST_Msk (0x1ul << SYS_IPRST1_ACMP01RST_Pos) /*!< SYS_T::IPRST1: ACMP01RST Mask */
sahilmgandhi 18:6a4db94011d3 12259
sahilmgandhi 18:6a4db94011d3 12260 #define SYS_IPRST1_I2C0RST_Pos (8) /*!< SYS_T::IPRST1: I2C0RST Position */
sahilmgandhi 18:6a4db94011d3 12261 #define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) /*!< SYS_T::IPRST1: I2C0RST Mask */
sahilmgandhi 18:6a4db94011d3 12262
sahilmgandhi 18:6a4db94011d3 12263 #define SYS_IPRST1_I2C1RST_Pos (9) /*!< SYS_T::IPRST1: I2C1RST Position */
sahilmgandhi 18:6a4db94011d3 12264 #define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) /*!< SYS_T::IPRST1: I2C1RST Mask */
sahilmgandhi 18:6a4db94011d3 12265
sahilmgandhi 18:6a4db94011d3 12266 #define SYS_IPRST1_SPI0RST_Pos (12) /*!< SYS_T::IPRST1: SPI0RST Position */
sahilmgandhi 18:6a4db94011d3 12267 #define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) /*!< SYS_T::IPRST1: SPI0RST Mask */
sahilmgandhi 18:6a4db94011d3 12268
sahilmgandhi 18:6a4db94011d3 12269 #define SYS_IPRST1_SPI1RST_Pos (13) /*!< SYS_T::IPRST1: SPI1RST Position */
sahilmgandhi 18:6a4db94011d3 12270 #define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) /*!< SYS_T::IPRST1: SPI1RST Mask */
sahilmgandhi 18:6a4db94011d3 12271
sahilmgandhi 18:6a4db94011d3 12272 #define SYS_IPRST1_SPI2RST_Pos (14) /*!< SYS_T::IPRST1: SPI2RST Position */
sahilmgandhi 18:6a4db94011d3 12273 #define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) /*!< SYS_T::IPRST1: SPI2RST Mask */
sahilmgandhi 18:6a4db94011d3 12274
sahilmgandhi 18:6a4db94011d3 12275 #define SYS_IPRST1_UART0RST_Pos (16) /*!< SYS_T::IPRST1: UART0RST Position */
sahilmgandhi 18:6a4db94011d3 12276 #define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) /*!< SYS_T::IPRST1: UART0RST Mask */
sahilmgandhi 18:6a4db94011d3 12277
sahilmgandhi 18:6a4db94011d3 12278 #define SYS_IPRST1_UART1RST_Pos (17) /*!< SYS_T::IPRST1: UART1RST Position */
sahilmgandhi 18:6a4db94011d3 12279 #define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) /*!< SYS_T::IPRST1: UART1RST Mask */
sahilmgandhi 18:6a4db94011d3 12280
sahilmgandhi 18:6a4db94011d3 12281 #define SYS_IPRST1_UART2RST_Pos (18) /*!< SYS_T::IPRST1: UART2RST Position */
sahilmgandhi 18:6a4db94011d3 12282 #define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) /*!< SYS_T::IPRST1: UART2RST Mask */
sahilmgandhi 18:6a4db94011d3 12283
sahilmgandhi 18:6a4db94011d3 12284 #define SYS_IPRST1_UART3RST_Pos (19) /*!< SYS_T::IPRST1: UART3RST Position */
sahilmgandhi 18:6a4db94011d3 12285 #define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) /*!< SYS_T::IPRST1: UART3RST Mask */
sahilmgandhi 18:6a4db94011d3 12286
sahilmgandhi 18:6a4db94011d3 12287 #define SYS_IPRST1_CAN0RST_Pos (24) /*!< SYS_T::IPRST1: CAN0RST Position */
sahilmgandhi 18:6a4db94011d3 12288 #define SYS_IPRST1_CAN0RST_Msk (0x1ul << SYS_IPRST1_CAN0RST_Pos) /*!< SYS_T::IPRST1: CAN0RST Mask */
sahilmgandhi 18:6a4db94011d3 12289
sahilmgandhi 18:6a4db94011d3 12290 #define SYS_IPRST1_OTGRST_Pos (26) /*!< SYS_T::IPRST1: OTGRST Position */
sahilmgandhi 18:6a4db94011d3 12291 #define SYS_IPRST1_OTGRST_Msk (0x1ul << SYS_IPRST1_OTGRST_Pos) /*!< SYS_T::IPRST1: OTGRST Mask */
sahilmgandhi 18:6a4db94011d3 12292
sahilmgandhi 18:6a4db94011d3 12293 #define SYS_IPRST1_USBDRST_Pos (27) /*!< SYS_T::IPRST1: USBDRST Position */
sahilmgandhi 18:6a4db94011d3 12294 #define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) /*!< SYS_T::IPRST1: USBDRST Mask */
sahilmgandhi 18:6a4db94011d3 12295
sahilmgandhi 18:6a4db94011d3 12296 #define SYS_IPRST1_EADCRST_Pos (28) /*!< SYS_T::IPRST1: EADCRST Position */
sahilmgandhi 18:6a4db94011d3 12297 #define SYS_IPRST1_EADCRST_Msk (0x1ul << SYS_IPRST1_EADCRST_Pos) /*!< SYS_T::IPRST1: EADCRST Mask */
sahilmgandhi 18:6a4db94011d3 12298
sahilmgandhi 18:6a4db94011d3 12299 #define SYS_IPRST2_SC0RST_Pos (0) /*!< SYS_T::IPRST2: SC0RST Position */
sahilmgandhi 18:6a4db94011d3 12300 #define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) /*!< SYS_T::IPRST2: SC0RST Mask */
sahilmgandhi 18:6a4db94011d3 12301
sahilmgandhi 18:6a4db94011d3 12302 #define SYS_IPRST2_DACRST_Pos (12) /*!< SYS_T::IPRST2: DACRST Position */
sahilmgandhi 18:6a4db94011d3 12303 #define SYS_IPRST2_DACRST_Msk (0x1ul << SYS_IPRST2_DACRST_Pos) /*!< SYS_T::IPRST2: DACRST Mask */
sahilmgandhi 18:6a4db94011d3 12304
sahilmgandhi 18:6a4db94011d3 12305 #define SYS_IPRST2_PWM0RST_Pos (16) /*!< SYS_T::IPRST2: PWM0RST Position */
sahilmgandhi 18:6a4db94011d3 12306 #define SYS_IPRST2_PWM0RST_Msk (0x1ul << SYS_IPRST2_PWM0RST_Pos) /*!< SYS_T::IPRST2: PWM0RST Mask */
sahilmgandhi 18:6a4db94011d3 12307
sahilmgandhi 18:6a4db94011d3 12308 #define SYS_IPRST2_PWM1RST_Pos (17) /*!< SYS_T::IPRST2: PWM1RST Position */
sahilmgandhi 18:6a4db94011d3 12309 #define SYS_IPRST2_PWM1RST_Msk (0x1ul << SYS_IPRST2_PWM1RST_Pos) /*!< SYS_T::IPRST2: PWM1RST Mask */
sahilmgandhi 18:6a4db94011d3 12310
sahilmgandhi 18:6a4db94011d3 12311 #define SYS_IPRST2_TKRST_Pos (25) /*!< SYS_T::IPRST2: TKRST Position */
sahilmgandhi 18:6a4db94011d3 12312 #define SYS_IPRST2_TKRST_Msk (0x1ul << SYS_IPRST2_TKRST_Pos) /*!< SYS_T::IPRST2: TKRST Mask */
sahilmgandhi 18:6a4db94011d3 12313
sahilmgandhi 18:6a4db94011d3 12314 #define SYS_BODCTL_BODEN_Pos (0) /*!< SYS_T::BODCTL: BODEN Position */
sahilmgandhi 18:6a4db94011d3 12315 #define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) /*!< SYS_T::BODCTL: BODEN Mask */
sahilmgandhi 18:6a4db94011d3 12316
sahilmgandhi 18:6a4db94011d3 12317 #define SYS_BODCTL_BODVL_Pos (1) /*!< SYS_T::BODCTL: BODVL Position */
sahilmgandhi 18:6a4db94011d3 12318 #define SYS_BODCTL_BODVL_Msk (0x3ul << SYS_BODCTL_BODVL_Pos) /*!< SYS_T::BODCTL: BODVL Mask */
sahilmgandhi 18:6a4db94011d3 12319
sahilmgandhi 18:6a4db94011d3 12320 #define SYS_BODCTL_BODRSTEN_Pos (3) /*!< SYS_T::BODCTL: BODRSTEN Position */
sahilmgandhi 18:6a4db94011d3 12321 #define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) /*!< SYS_T::BODCTL: BODRSTEN Mask */
sahilmgandhi 18:6a4db94011d3 12322
sahilmgandhi 18:6a4db94011d3 12323 #define SYS_BODCTL_BODIF_Pos (4) /*!< SYS_T::BODCTL: BODIF Position */
sahilmgandhi 18:6a4db94011d3 12324 #define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) /*!< SYS_T::BODCTL: BODIF Mask */
sahilmgandhi 18:6a4db94011d3 12325
sahilmgandhi 18:6a4db94011d3 12326 #define SYS_BODCTL_BODLPM_Pos (5) /*!< SYS_T::BODCTL: BODLPM Position */
sahilmgandhi 18:6a4db94011d3 12327 #define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos) /*!< SYS_T::BODCTL: BODLPM Mask */
sahilmgandhi 18:6a4db94011d3 12328
sahilmgandhi 18:6a4db94011d3 12329 #define SYS_BODCTL_BODOUT_Pos (6) /*!< SYS_T::BODCTL: BODOUT Position */
sahilmgandhi 18:6a4db94011d3 12330 #define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) /*!< SYS_T::BODCTL: BODOUT Mask */
sahilmgandhi 18:6a4db94011d3 12331
sahilmgandhi 18:6a4db94011d3 12332 #define SYS_BODCTL_LVREN_Pos (7) /*!< SYS_T::BODCTL: LVREN Position */
sahilmgandhi 18:6a4db94011d3 12333 #define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) /*!< SYS_T::BODCTL: LVREN Mask */
sahilmgandhi 18:6a4db94011d3 12334
sahilmgandhi 18:6a4db94011d3 12335 #define SYS_BODCTL_BODDGSEL_Pos (8) /*!< SYS_T::BODCTL: BODDGSEL Position */
sahilmgandhi 18:6a4db94011d3 12336 #define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) /*!< SYS_T::BODCTL: BODDGSEL Mask */
sahilmgandhi 18:6a4db94011d3 12337
sahilmgandhi 18:6a4db94011d3 12338 #define SYS_BODCTL_LVRDGSEL_Pos (12) /*!< SYS_T::BODCTL: LVRDGSEL Position */
sahilmgandhi 18:6a4db94011d3 12339 #define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) /*!< SYS_T::BODCTL: LVRDGSEL Mask */
sahilmgandhi 18:6a4db94011d3 12340
sahilmgandhi 18:6a4db94011d3 12341 #define SYS_IVSCTL_VTEMPEN_Pos (0) /*!< SYS_T::IVSCTL: VTEMPEN Position */
sahilmgandhi 18:6a4db94011d3 12342 #define SYS_IVSCTL_VTEMPEN_Msk (0x1ul << SYS_IVSCTL_VTEMPEN_Pos) /*!< SYS_T::IVSCTL: VTEMPEN Mask */
sahilmgandhi 18:6a4db94011d3 12343
sahilmgandhi 18:6a4db94011d3 12344 #define SYS_IVSCTL_VBATUGEN_Pos (1) /*!< SYS_T::IVSCTL: VBATUGEN Position */
sahilmgandhi 18:6a4db94011d3 12345 #define SYS_IVSCTL_VBATUGEN_Msk (0x1ul << SYS_IVSCTL_VBATUGEN_Pos) /*!< SYS_T::IVSCTL: VBATUGEN Mask */
sahilmgandhi 18:6a4db94011d3 12346
sahilmgandhi 18:6a4db94011d3 12347 #define SYS_PORCTL_POROFF_Pos (0) /*!< SYS_T::PORCTL: POROFF Position */
sahilmgandhi 18:6a4db94011d3 12348 #define SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos) /*!< SYS_T::PORCTL: POROFF Mask */
sahilmgandhi 18:6a4db94011d3 12349
sahilmgandhi 18:6a4db94011d3 12350 #define SYS_VREFCTL_VREFCTL_Pos (0) /*!< SYS_T::VREFCTL: VREFCTL Position */
sahilmgandhi 18:6a4db94011d3 12351 #define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) /*!< SYS_T::VREFCTL: VREFCTL Mask */
sahilmgandhi 18:6a4db94011d3 12352
sahilmgandhi 18:6a4db94011d3 12353 #define SYS_USBPHY_USBROLE_Pos (0) /*!< SYS_T::USBPHY: USBROLE Position */
sahilmgandhi 18:6a4db94011d3 12354 #define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) /*!< SYS_T::USBPHY: USBROLE Mask */
sahilmgandhi 18:6a4db94011d3 12355
sahilmgandhi 18:6a4db94011d3 12356 #define SYS_USBPHY_LDO33EN_Pos (8) /*!< SYS_T::USBPHY: LDO33EN Position */
sahilmgandhi 18:6a4db94011d3 12357 #define SYS_USBPHY_LDO33EN_Msk (0x1ul << SYS_USBPHY_LDO33EN_Pos) /*!< SYS_T::USBPHY: LDO33EN Mask */
sahilmgandhi 18:6a4db94011d3 12358
sahilmgandhi 18:6a4db94011d3 12359 #define SYS_GPA_MFPL_PA0MFP_Pos (0) /*!< SYS_T::GPA_MFPL: PA0MFP Position */
sahilmgandhi 18:6a4db94011d3 12360 #define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) /*!< SYS_T::GPA_MFPL: PA0MFP Mask */
sahilmgandhi 18:6a4db94011d3 12361
sahilmgandhi 18:6a4db94011d3 12362 #define SYS_GPA_MFPL_PA1MFP_Pos (4) /*!< SYS_T::GPA_MFPL: PA1MFP Position */
sahilmgandhi 18:6a4db94011d3 12363 #define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) /*!< SYS_T::GPA_MFPL: PA1MFP Mask */
sahilmgandhi 18:6a4db94011d3 12364
sahilmgandhi 18:6a4db94011d3 12365 #define SYS_GPA_MFPL_PA2MFP_Pos (8) /*!< SYS_T::GPA_MFPL: PA2MFP Position */
sahilmgandhi 18:6a4db94011d3 12366 #define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) /*!< SYS_T::GPA_MFPL: PA2MFP Mask */
sahilmgandhi 18:6a4db94011d3 12367
sahilmgandhi 18:6a4db94011d3 12368 #define SYS_GPA_MFPL_PA3MFP_Pos (12) /*!< SYS_T::GPA_MFPL: PA3MFP Position */
sahilmgandhi 18:6a4db94011d3 12369 #define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) /*!< SYS_T::GPA_MFPL: PA3MFP Mask */
sahilmgandhi 18:6a4db94011d3 12370
sahilmgandhi 18:6a4db94011d3 12371 #define SYS_GPA_MFPL_PA4MFP_Pos (16) /*!< SYS_T::GPA_MFPL: PA4MFP Position */
sahilmgandhi 18:6a4db94011d3 12372 #define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) /*!< SYS_T::GPA_MFPL: PA4MFP Mask */
sahilmgandhi 18:6a4db94011d3 12373
sahilmgandhi 18:6a4db94011d3 12374 #define SYS_GPA_MFPL_PA5MFP_Pos (20) /*!< SYS_T::GPA_MFPL: PA5MFP Position */
sahilmgandhi 18:6a4db94011d3 12375 #define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) /*!< SYS_T::GPA_MFPL: PA5MFP Mask */
sahilmgandhi 18:6a4db94011d3 12376
sahilmgandhi 18:6a4db94011d3 12377 #define SYS_GPA_MFPL_PA6MFP_Pos (24) /*!< SYS_T::GPA_MFPL: PA6MFP Position */
sahilmgandhi 18:6a4db94011d3 12378 #define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) /*!< SYS_T::GPA_MFPL: PA6MFP Mask */
sahilmgandhi 18:6a4db94011d3 12379
sahilmgandhi 18:6a4db94011d3 12380 #define SYS_GPA_MFPL_PA7MFP_Pos (28) /*!< SYS_T::GPA_MFPL: PA7MFP Position */
sahilmgandhi 18:6a4db94011d3 12381 #define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos) /*!< SYS_T::GPA_MFPL: PA7MFP Mask */
sahilmgandhi 18:6a4db94011d3 12382
sahilmgandhi 18:6a4db94011d3 12383 #define SYS_GPA_MFPH_PA8MFP_Pos (0) /*!< SYS_T::GPA_MFPH: PA8MFP Position */
sahilmgandhi 18:6a4db94011d3 12384 #define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) /*!< SYS_T::GPA_MFPH: PA8MFP Mask */
sahilmgandhi 18:6a4db94011d3 12385
sahilmgandhi 18:6a4db94011d3 12386 #define SYS_GPA_MFPH_PA9MFP_Pos (4) /*!< SYS_T::GPA_MFPH: PA9MFP Position */
sahilmgandhi 18:6a4db94011d3 12387 #define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) /*!< SYS_T::GPA_MFPH: PA9MFP Mask */
sahilmgandhi 18:6a4db94011d3 12388
sahilmgandhi 18:6a4db94011d3 12389 #define SYS_GPA_MFPH_PA10MFP_Pos (8) /*!< SYS_T::GPA_MFPH: PA10MFP Position */
sahilmgandhi 18:6a4db94011d3 12390 #define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) /*!< SYS_T::GPA_MFPH: PA10MFP Mask */
sahilmgandhi 18:6a4db94011d3 12391
sahilmgandhi 18:6a4db94011d3 12392 #define SYS_GPA_MFPH_PA11MFP_Pos (12) /*!< SYS_T::GPA_MFPH: PA11MFP Position */
sahilmgandhi 18:6a4db94011d3 12393 #define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) /*!< SYS_T::GPA_MFPH: PA11MFP Mask */
sahilmgandhi 18:6a4db94011d3 12394
sahilmgandhi 18:6a4db94011d3 12395 #define SYS_GPA_MFPH_PA12MFP_Pos (16) /*!< SYS_T::GPA_MFPH: PA12MFP Position */
sahilmgandhi 18:6a4db94011d3 12396 #define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) /*!< SYS_T::GPA_MFPH: PA12MFP Mask */
sahilmgandhi 18:6a4db94011d3 12397
sahilmgandhi 18:6a4db94011d3 12398 #define SYS_GPA_MFPH_PA13MFP_Pos (20) /*!< SYS_T::GPA_MFPH: PA13MFP Position */
sahilmgandhi 18:6a4db94011d3 12399 #define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) /*!< SYS_T::GPA_MFPH: PA13MFP Mask */
sahilmgandhi 18:6a4db94011d3 12400
sahilmgandhi 18:6a4db94011d3 12401 #define SYS_GPA_MFPH_PA14MFP_Pos (24) /*!< SYS_T::GPA_MFPH: PA14MFP Position */
sahilmgandhi 18:6a4db94011d3 12402 #define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) /*!< SYS_T::GPA_MFPH: PA14MFP Mask */
sahilmgandhi 18:6a4db94011d3 12403
sahilmgandhi 18:6a4db94011d3 12404 #define SYS_GPA_MFPH_PA15MFP_Pos (28) /*!< SYS_T::GPA_MFPH: PA15MFP Position */
sahilmgandhi 18:6a4db94011d3 12405 #define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) /*!< SYS_T::GPA_MFPH: PA15MFP Mask */
sahilmgandhi 18:6a4db94011d3 12406
sahilmgandhi 18:6a4db94011d3 12407 #define SYS_GPB_MFPL_PB0MFP_Pos (0) /*!< SYS_T::GPB_MFPL: PB0MFP Position */
sahilmgandhi 18:6a4db94011d3 12408 #define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) /*!< SYS_T::GPB_MFPL: PB0MFP Mask */
sahilmgandhi 18:6a4db94011d3 12409
sahilmgandhi 18:6a4db94011d3 12410 #define SYS_GPB_MFPL_PB1MFP_Pos (4) /*!< SYS_T::GPB_MFPL: PB1MFP Position */
sahilmgandhi 18:6a4db94011d3 12411 #define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) /*!< SYS_T::GPB_MFPL: PB1MFP Mask */
sahilmgandhi 18:6a4db94011d3 12412
sahilmgandhi 18:6a4db94011d3 12413 #define SYS_GPB_MFPL_PB2MFP_Pos (8) /*!< SYS_T::GPB_MFPL: PB2MFP Position */
sahilmgandhi 18:6a4db94011d3 12414 #define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) /*!< SYS_T::GPB_MFPL: PB2MFP Mask */
sahilmgandhi 18:6a4db94011d3 12415
sahilmgandhi 18:6a4db94011d3 12416 #define SYS_GPB_MFPL_PB3MFP_Pos (12) /*!< SYS_T::GPB_MFPL: PB3MFP Position */
sahilmgandhi 18:6a4db94011d3 12417 #define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) /*!< SYS_T::GPB_MFPL: PB3MFP Mask */
sahilmgandhi 18:6a4db94011d3 12418
sahilmgandhi 18:6a4db94011d3 12419 #define SYS_GPB_MFPL_PB4MFP_Pos (16) /*!< SYS_T::GPB_MFPL: PB4MFP Position */
sahilmgandhi 18:6a4db94011d3 12420 #define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) /*!< SYS_T::GPB_MFPL: PB4MFP Mask */
sahilmgandhi 18:6a4db94011d3 12421
sahilmgandhi 18:6a4db94011d3 12422 #define SYS_GPB_MFPL_PB5MFP_Pos (20) /*!< SYS_T::GPB_MFPL: PB5MFP Position */
sahilmgandhi 18:6a4db94011d3 12423 #define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) /*!< SYS_T::GPB_MFPL: PB5MFP Mask */
sahilmgandhi 18:6a4db94011d3 12424
sahilmgandhi 18:6a4db94011d3 12425 #define SYS_GPB_MFPL_PB6MFP_Pos (24) /*!< SYS_T::GPB_MFPL: PB6MFP Position */
sahilmgandhi 18:6a4db94011d3 12426 #define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) /*!< SYS_T::GPB_MFPL: PB6MFP Mask */
sahilmgandhi 18:6a4db94011d3 12427
sahilmgandhi 18:6a4db94011d3 12428 #define SYS_GPB_MFPL_PB7MFP_Pos (28) /*!< SYS_T::GPB_MFPL: PB7MFP Position */
sahilmgandhi 18:6a4db94011d3 12429 #define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) /*!< SYS_T::GPB_MFPL: PB7MFP Mask */
sahilmgandhi 18:6a4db94011d3 12430
sahilmgandhi 18:6a4db94011d3 12431 #define SYS_GPB_MFPH_PB8MFP_Pos (0) /*!< SYS_T::GPB_MFPH: PB8MFP Position */
sahilmgandhi 18:6a4db94011d3 12432 #define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) /*!< SYS_T::GPB_MFPH: PB8MFP Mask */
sahilmgandhi 18:6a4db94011d3 12433
sahilmgandhi 18:6a4db94011d3 12434 #define SYS_GPB_MFPH_PB9MFP_Pos (4) /*!< SYS_T::GPB_MFPH: PB9MFP Position */
sahilmgandhi 18:6a4db94011d3 12435 #define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) /*!< SYS_T::GPB_MFPH: PB9MFP Mask */
sahilmgandhi 18:6a4db94011d3 12436
sahilmgandhi 18:6a4db94011d3 12437 #define SYS_GPB_MFPH_PB10MFP_Pos (8) /*!< SYS_T::GPB_MFPH: PB10MFP Position */
sahilmgandhi 18:6a4db94011d3 12438 #define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) /*!< SYS_T::GPB_MFPH: PB10MFP Mask */
sahilmgandhi 18:6a4db94011d3 12439
sahilmgandhi 18:6a4db94011d3 12440 #define SYS_GPB_MFPH_PB11MFP_Pos (12) /*!< SYS_T::GPB_MFPH: PB11MFP Position */
sahilmgandhi 18:6a4db94011d3 12441 #define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) /*!< SYS_T::GPB_MFPH: PB11MFP Mask */
sahilmgandhi 18:6a4db94011d3 12442
sahilmgandhi 18:6a4db94011d3 12443 #define SYS_GPB_MFPH_PB12MFP_Pos (16) /*!< SYS_T::GPB_MFPH: PB12MFP Position */
sahilmgandhi 18:6a4db94011d3 12444 #define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos) /*!< SYS_T::GPB_MFPH: PB12MFP Mask */
sahilmgandhi 18:6a4db94011d3 12445
sahilmgandhi 18:6a4db94011d3 12446 #define SYS_GPB_MFPH_PB13MFP_Pos (20) /*!< SYS_T::GPB_MFPH: PB13MFP Position */
sahilmgandhi 18:6a4db94011d3 12447 #define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) /*!< SYS_T::GPB_MFPH: PB13MFP Mask */
sahilmgandhi 18:6a4db94011d3 12448
sahilmgandhi 18:6a4db94011d3 12449 #define SYS_GPB_MFPH_PB14MFP_Pos (24) /*!< SYS_T::GPB_MFPH: PB14MFP Position */
sahilmgandhi 18:6a4db94011d3 12450 #define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) /*!< SYS_T::GPB_MFPH: PB14MFP Mask */
sahilmgandhi 18:6a4db94011d3 12451
sahilmgandhi 18:6a4db94011d3 12452 #define SYS_GPB_MFPH_PB15MFP_Pos (28) /*!< SYS_T::GPB_MFPH: PB15MFP Position */
sahilmgandhi 18:6a4db94011d3 12453 #define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) /*!< SYS_T::GPB_MFPH: PB15MFP Mask */
sahilmgandhi 18:6a4db94011d3 12454
sahilmgandhi 18:6a4db94011d3 12455 #define SYS_GPC_MFPL_PC0MFP_Pos (0) /*!< SYS_T::GPC_MFPL: PC0MFP Position */
sahilmgandhi 18:6a4db94011d3 12456 #define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) /*!< SYS_T::GPC_MFPL: PC0MFP Mask */
sahilmgandhi 18:6a4db94011d3 12457
sahilmgandhi 18:6a4db94011d3 12458 #define SYS_GPC_MFPL_PC1MFP_Pos (4) /*!< SYS_T::GPC_MFPL: PC1MFP Position */
sahilmgandhi 18:6a4db94011d3 12459 #define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) /*!< SYS_T::GPC_MFPL: PC1MFP Mask */
sahilmgandhi 18:6a4db94011d3 12460
sahilmgandhi 18:6a4db94011d3 12461 #define SYS_GPC_MFPL_PC2MFP_Pos (8) /*!< SYS_T::GPC_MFPL: PC2MFP Position */
sahilmgandhi 18:6a4db94011d3 12462 #define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) /*!< SYS_T::GPC_MFPL: PC2MFP Mask */
sahilmgandhi 18:6a4db94011d3 12463
sahilmgandhi 18:6a4db94011d3 12464 #define SYS_GPC_MFPL_PC3MFP_Pos (12) /*!< SYS_T::GPC_MFPL: PC3MFP Position */
sahilmgandhi 18:6a4db94011d3 12465 #define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) /*!< SYS_T::GPC_MFPL: PC3MFP Mask */
sahilmgandhi 18:6a4db94011d3 12466
sahilmgandhi 18:6a4db94011d3 12467 #define SYS_GPC_MFPL_PC4MFP_Pos (16) /*!< SYS_T::GPC_MFPL: PC4MFP Position */
sahilmgandhi 18:6a4db94011d3 12468 #define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos) /*!< SYS_T::GPC_MFPL: PC4MFP Mask */
sahilmgandhi 18:6a4db94011d3 12469
sahilmgandhi 18:6a4db94011d3 12470 #define SYS_GPC_MFPL_PC5MFP_Pos (20) /*!< SYS_T::GPC_MFPL: PC5MFP Position */
sahilmgandhi 18:6a4db94011d3 12471 #define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos) /*!< SYS_T::GPC_MFPL: PC5MFP Mask */
sahilmgandhi 18:6a4db94011d3 12472
sahilmgandhi 18:6a4db94011d3 12473 #define SYS_GPC_MFPL_PC6MFP_Pos (24) /*!< SYS_T::GPC_MFPL: PC6MFP Position */
sahilmgandhi 18:6a4db94011d3 12474 #define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) /*!< SYS_T::GPC_MFPL: PC6MFP Mask */
sahilmgandhi 18:6a4db94011d3 12475
sahilmgandhi 18:6a4db94011d3 12476 #define SYS_GPC_MFPL_PC7MFP_Pos (28) /*!< SYS_T::GPC_MFPL: PC7MFP Position */
sahilmgandhi 18:6a4db94011d3 12477 #define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) /*!< SYS_T::GPC_MFPL: PC7MFP Mask */
sahilmgandhi 18:6a4db94011d3 12478
sahilmgandhi 18:6a4db94011d3 12479 #define SYS_GPC_MFPH_PC8MFP_Pos (0) /*!< SYS_T::GPC_MFPH: PC8MFP Position */
sahilmgandhi 18:6a4db94011d3 12480 #define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) /*!< SYS_T::GPC_MFPH: PC8MFP Mask */
sahilmgandhi 18:6a4db94011d3 12481
sahilmgandhi 18:6a4db94011d3 12482 #define SYS_GPC_MFPH_PC9MFP_Pos (4) /*!< SYS_T::GPC_MFPH: PC9MFP Position */
sahilmgandhi 18:6a4db94011d3 12483 #define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) /*!< SYS_T::GPC_MFPH: PC9MFP Mask */
sahilmgandhi 18:6a4db94011d3 12484
sahilmgandhi 18:6a4db94011d3 12485 #define SYS_GPC_MFPH_PC10MFP_Pos (8) /*!< SYS_T::GPC_MFPH: PC10MFP Position */
sahilmgandhi 18:6a4db94011d3 12486 #define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) /*!< SYS_T::GPC_MFPH: PC10MFP Mask */
sahilmgandhi 18:6a4db94011d3 12487
sahilmgandhi 18:6a4db94011d3 12488 #define SYS_GPC_MFPH_PC11MFP_Pos (12) /*!< SYS_T::GPC_MFPH: PC11MFP Position */
sahilmgandhi 18:6a4db94011d3 12489 #define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) /*!< SYS_T::GPC_MFPH: PC11MFP Mask */
sahilmgandhi 18:6a4db94011d3 12490
sahilmgandhi 18:6a4db94011d3 12491 #define SYS_GPC_MFPH_PC12MFP_Pos (16) /*!< SYS_T::GPC_MFPH: PC12MFP Position */
sahilmgandhi 18:6a4db94011d3 12492 #define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos) /*!< SYS_T::GPC_MFPH: PC12MFP Mask */
sahilmgandhi 18:6a4db94011d3 12493
sahilmgandhi 18:6a4db94011d3 12494 #define SYS_GPC_MFPH_PC13MFP_Pos (20) /*!< SYS_T::GPC_MFPH: PC13MFP Position */
sahilmgandhi 18:6a4db94011d3 12495 #define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos) /*!< SYS_T::GPC_MFPH: PC13MFP Mask */
sahilmgandhi 18:6a4db94011d3 12496
sahilmgandhi 18:6a4db94011d3 12497 #define SYS_GPC_MFPH_PC14MFP_Pos (24) /*!< SYS_T::GPC_MFPH: PC14MFP Position */
sahilmgandhi 18:6a4db94011d3 12498 #define SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos) /*!< SYS_T::GPC_MFPH: PC14MFP Mask */
sahilmgandhi 18:6a4db94011d3 12499
sahilmgandhi 18:6a4db94011d3 12500 #define SYS_GPC_MFPH_PC15MFP_Pos (28) /*!< SYS_T::GPC_MFPH: PC15MFP Position */
sahilmgandhi 18:6a4db94011d3 12501 #define SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos) /*!< SYS_T::GPC_MFPH: PC15MFP Mask */
sahilmgandhi 18:6a4db94011d3 12502
sahilmgandhi 18:6a4db94011d3 12503 #define SYS_GPD_MFPL_PD0MFP_Pos (0) /*!< SYS_T::GPD_MFPL: PD0MFP Position */
sahilmgandhi 18:6a4db94011d3 12504 #define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos) /*!< SYS_T::GPD_MFPL: PD0MFP Mask */
sahilmgandhi 18:6a4db94011d3 12505
sahilmgandhi 18:6a4db94011d3 12506 #define SYS_GPD_MFPL_PD1MFP_Pos (4) /*!< SYS_T::GPD_MFPL: PD1MFP Position */
sahilmgandhi 18:6a4db94011d3 12507 #define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos) /*!< SYS_T::GPD_MFPL: PD1MFP Mask */
sahilmgandhi 18:6a4db94011d3 12508
sahilmgandhi 18:6a4db94011d3 12509 #define SYS_GPD_MFPL_PD2MFP_Pos (8) /*!< SYS_T::GPD_MFPL: PD2MFP Position */
sahilmgandhi 18:6a4db94011d3 12510 #define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos) /*!< SYS_T::GPD_MFPL: PD2MFP Mask */
sahilmgandhi 18:6a4db94011d3 12511
sahilmgandhi 18:6a4db94011d3 12512 #define SYS_GPD_MFPL_PD3MFP_Pos (12) /*!< SYS_T::GPD_MFPL: PD3MFP Position */
sahilmgandhi 18:6a4db94011d3 12513 #define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos) /*!< SYS_T::GPD_MFPL: PD3MFP Mask */
sahilmgandhi 18:6a4db94011d3 12514
sahilmgandhi 18:6a4db94011d3 12515 #define SYS_GPD_MFPL_PD4MFP_Pos (16) /*!< SYS_T::GPD_MFPL: PD4MFP Position */
sahilmgandhi 18:6a4db94011d3 12516 #define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos) /*!< SYS_T::GPD_MFPL: PD4MFP Mask */
sahilmgandhi 18:6a4db94011d3 12517
sahilmgandhi 18:6a4db94011d3 12518 #define SYS_GPD_MFPL_PD5MFP_Pos (20) /*!< SYS_T::GPD_MFPL: PD5MFP Position */
sahilmgandhi 18:6a4db94011d3 12519 #define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos) /*!< SYS_T::GPD_MFPL: PD5MFP Mask */
sahilmgandhi 18:6a4db94011d3 12520
sahilmgandhi 18:6a4db94011d3 12521 #define SYS_GPD_MFPL_PD6MFP_Pos (24) /*!< SYS_T::GPD_MFPL: PD6MFP Position */
sahilmgandhi 18:6a4db94011d3 12522 #define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) /*!< SYS_T::GPD_MFPL: PD6MFP Mask */
sahilmgandhi 18:6a4db94011d3 12523
sahilmgandhi 18:6a4db94011d3 12524 #define SYS_GPD_MFPL_PD7MFP_Pos (28) /*!< SYS_T::GPD_MFPL: PD7MFP Position */
sahilmgandhi 18:6a4db94011d3 12525 #define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) /*!< SYS_T::GPD_MFPL: PD7MFP Mask */
sahilmgandhi 18:6a4db94011d3 12526
sahilmgandhi 18:6a4db94011d3 12527 #define SYS_GPD_MFPH_PD8MFP_Pos (0) /*!< SYS_T::GPD_MFPH: PD8MFP Position */
sahilmgandhi 18:6a4db94011d3 12528 #define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos) /*!< SYS_T::GPD_MFPH: PD8MFP Mask */
sahilmgandhi 18:6a4db94011d3 12529
sahilmgandhi 18:6a4db94011d3 12530 #define SYS_GPD_MFPH_PD9MFP_Pos (4) /*!< SYS_T::GPD_MFPH: PD9MFP Position */
sahilmgandhi 18:6a4db94011d3 12531 #define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos) /*!< SYS_T::GPD_MFPH: PD9MFP Mask */
sahilmgandhi 18:6a4db94011d3 12532
sahilmgandhi 18:6a4db94011d3 12533 #define SYS_GPD_MFPH_PD10MFP_Pos (8) /*!< SYS_T::GPD_MFPH: PD10MFP Position */
sahilmgandhi 18:6a4db94011d3 12534 #define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos) /*!< SYS_T::GPD_MFPH: PD10MFP Mask */
sahilmgandhi 18:6a4db94011d3 12535
sahilmgandhi 18:6a4db94011d3 12536 #define SYS_GPD_MFPH_PD11MFP_Pos (12) /*!< SYS_T::GPD_MFPH: PD11MFP Position */
sahilmgandhi 18:6a4db94011d3 12537 #define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos) /*!< SYS_T::GPD_MFPH: PD11MFP Mask */
sahilmgandhi 18:6a4db94011d3 12538
sahilmgandhi 18:6a4db94011d3 12539 #define SYS_GPD_MFPH_PD12MFP_Pos (16) /*!< SYS_T::GPD_MFPH: PD12MFP Position */
sahilmgandhi 18:6a4db94011d3 12540 #define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos) /*!< SYS_T::GPD_MFPH: PD12MFP Mask */
sahilmgandhi 18:6a4db94011d3 12541
sahilmgandhi 18:6a4db94011d3 12542 #define SYS_GPD_MFPH_PD13MFP_Pos (20) /*!< SYS_T::GPD_MFPH: PD13MFP Position */
sahilmgandhi 18:6a4db94011d3 12543 #define SYS_GPD_MFPH_PD13MFP_Msk (0xful << SYS_GPD_MFPH_PD13MFP_Pos) /*!< SYS_T::GPD_MFPH: PD13MFP Mask */
sahilmgandhi 18:6a4db94011d3 12544
sahilmgandhi 18:6a4db94011d3 12545 #define SYS_GPD_MFPH_PD14MFP_Pos (24) /*!< SYS_T::GPD_MFPH: PD14MFP Position */
sahilmgandhi 18:6a4db94011d3 12546 #define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) /*!< SYS_T::GPD_MFPH: PD14MFP Mask */
sahilmgandhi 18:6a4db94011d3 12547
sahilmgandhi 18:6a4db94011d3 12548 #define SYS_GPD_MFPH_PD15MFP_Pos (28) /*!< SYS_T::GPD_MFPH: PD15MFP Position */
sahilmgandhi 18:6a4db94011d3 12549 #define SYS_GPD_MFPH_PD15MFP_Msk (0xful << SYS_GPD_MFPH_PD15MFP_Pos) /*!< SYS_T::GPD_MFPH: PD15MFP Mask */
sahilmgandhi 18:6a4db94011d3 12550
sahilmgandhi 18:6a4db94011d3 12551 #define SYS_GPE_MFPL_PE0MFP_Pos (0) /*!< SYS_T::GPE_MFPL: PE0MFP Position */
sahilmgandhi 18:6a4db94011d3 12552 #define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos) /*!< SYS_T::GPE_MFPL: PE0MFP Mask */
sahilmgandhi 18:6a4db94011d3 12553
sahilmgandhi 18:6a4db94011d3 12554 #define SYS_GPE_MFPL_PE1MFP_Pos (4) /*!< SYS_T::GPE_MFPL: PE1MFP Position */
sahilmgandhi 18:6a4db94011d3 12555 #define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos) /*!< SYS_T::GPE_MFPL: PE1MFP Mask */
sahilmgandhi 18:6a4db94011d3 12556
sahilmgandhi 18:6a4db94011d3 12557 #define SYS_GPE_MFPL_PE2MFP_Pos (8) /*!< SYS_T::GPE_MFPL: PE2MFP Position */
sahilmgandhi 18:6a4db94011d3 12558 #define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos) /*!< SYS_T::GPE_MFPL: PE2MFP Mask */
sahilmgandhi 18:6a4db94011d3 12559
sahilmgandhi 18:6a4db94011d3 12560 #define SYS_GPE_MFPL_PE3MFP_Pos (12) /*!< SYS_T::GPE_MFPL: PE3MFP Position */
sahilmgandhi 18:6a4db94011d3 12561 #define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos) /*!< SYS_T::GPE_MFPL: PE3MFP Mask */
sahilmgandhi 18:6a4db94011d3 12562
sahilmgandhi 18:6a4db94011d3 12563 #define SYS_GPE_MFPL_PE4MFP_Pos (16) /*!< SYS_T::GPE_MFPL: PE4MFP Position */
sahilmgandhi 18:6a4db94011d3 12564 #define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos) /*!< SYS_T::GPE_MFPL: PE4MFP Mask */
sahilmgandhi 18:6a4db94011d3 12565
sahilmgandhi 18:6a4db94011d3 12566 #define SYS_GPE_MFPL_PE5MFP_Pos (20) /*!< SYS_T::GPE_MFPL: PE5MFP Position */
sahilmgandhi 18:6a4db94011d3 12567 #define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) /*!< SYS_T::GPE_MFPL: PE5MFP Mask */
sahilmgandhi 18:6a4db94011d3 12568
sahilmgandhi 18:6a4db94011d3 12569 #define SYS_GPE_MFPL_PE6MFP_Pos (24) /*!< SYS_T::GPE_MFPL: PE6MFP Position */
sahilmgandhi 18:6a4db94011d3 12570 #define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos) /*!< SYS_T::GPE_MFPL: PE6MFP Mask */
sahilmgandhi 18:6a4db94011d3 12571
sahilmgandhi 18:6a4db94011d3 12572 #define SYS_GPE_MFPL_PE7MFP_Pos (28) /*!< SYS_T::GPE_MFPL: PE7MFP Position */
sahilmgandhi 18:6a4db94011d3 12573 #define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos) /*!< SYS_T::GPE_MFPL: PE7MFP Mask */
sahilmgandhi 18:6a4db94011d3 12574
sahilmgandhi 18:6a4db94011d3 12575 #define SYS_GPE_MFPH_PE8MFP_Pos (0) /*!< SYS_T::GPE_MFPH: PE8MFP Position */
sahilmgandhi 18:6a4db94011d3 12576 #define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos) /*!< SYS_T::GPE_MFPH: PE8MFP Mask */
sahilmgandhi 18:6a4db94011d3 12577
sahilmgandhi 18:6a4db94011d3 12578 #define SYS_GPE_MFPH_PE9MFP_Pos (4) /*!< SYS_T::GPE_MFPH: PE9MFP Position */
sahilmgandhi 18:6a4db94011d3 12579 #define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos) /*!< SYS_T::GPE_MFPH: PE9MFP Mask */
sahilmgandhi 18:6a4db94011d3 12580
sahilmgandhi 18:6a4db94011d3 12581 #define SYS_GPE_MFPH_PE10MFP_Pos (8) /*!< SYS_T::GPE_MFPH: PE10MFP Position */
sahilmgandhi 18:6a4db94011d3 12582 #define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos) /*!< SYS_T::GPE_MFPH: PE10MFP Mask */
sahilmgandhi 18:6a4db94011d3 12583
sahilmgandhi 18:6a4db94011d3 12584 #define SYS_GPE_MFPH_PE11MFP_Pos (12) /*!< SYS_T::GPE_MFPH: PE11MFP Position */
sahilmgandhi 18:6a4db94011d3 12585 #define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos) /*!< SYS_T::GPE_MFPH: PE11MFP Mask */
sahilmgandhi 18:6a4db94011d3 12586
sahilmgandhi 18:6a4db94011d3 12587 #define SYS_GPE_MFPH_PE12MFP_Pos (16) /*!< SYS_T::GPE_MFPH: PE12MFP Position */
sahilmgandhi 18:6a4db94011d3 12588 #define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos) /*!< SYS_T::GPE_MFPH: PE12MFP Mask */
sahilmgandhi 18:6a4db94011d3 12589
sahilmgandhi 18:6a4db94011d3 12590 #define SYS_GPE_MFPH_PE13MFP_Pos (20) /*!< SYS_T::GPE_MFPH: PE13MFP Position */
sahilmgandhi 18:6a4db94011d3 12591 #define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos) /*!< SYS_T::GPE_MFPH: PE13MFP Mask */
sahilmgandhi 18:6a4db94011d3 12592
sahilmgandhi 18:6a4db94011d3 12593 #define SYS_GPE_MFPH_PE14MFP_Pos (24) /*!< SYS_T::GPE_MFPH: PE14MFP Position */
sahilmgandhi 18:6a4db94011d3 12594 #define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos) /*!< SYS_T::GPE_MFPH: PE14MFP Mask */
sahilmgandhi 18:6a4db94011d3 12595
sahilmgandhi 18:6a4db94011d3 12596 #define SYS_GPF_MFPL_PF0MFP_Pos (0) /*!< SYS_T::GPF_MFPL: PF0MFP Position */
sahilmgandhi 18:6a4db94011d3 12597 #define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) /*!< SYS_T::GPF_MFPL: PF0MFP Mask */
sahilmgandhi 18:6a4db94011d3 12598
sahilmgandhi 18:6a4db94011d3 12599 #define SYS_GPF_MFPL_PF1MFP_Pos (4) /*!< SYS_T::GPF_MFPL: PF1MFP Position */
sahilmgandhi 18:6a4db94011d3 12600 #define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) /*!< SYS_T::GPF_MFPL: PF1MFP Mask */
sahilmgandhi 18:6a4db94011d3 12601
sahilmgandhi 18:6a4db94011d3 12602 #define SYS_GPF_MFPL_PF2MFP_Pos (8) /*!< SYS_T::GPF_MFPL: PF2MFP Position */
sahilmgandhi 18:6a4db94011d3 12603 #define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) /*!< SYS_T::GPF_MFPL: PF2MFP Mask */
sahilmgandhi 18:6a4db94011d3 12604
sahilmgandhi 18:6a4db94011d3 12605 #define SYS_GPF_MFPL_PF3MFP_Pos (12) /*!< SYS_T::GPF_MFPL: PF3MFP Position */
sahilmgandhi 18:6a4db94011d3 12606 #define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) /*!< SYS_T::GPF_MFPL: PF3MFP Mask */
sahilmgandhi 18:6a4db94011d3 12607
sahilmgandhi 18:6a4db94011d3 12608 #define SYS_GPF_MFPL_PF4MFP_Pos (16) /*!< SYS_T::GPF_MFPL: PF4MFP Position */
sahilmgandhi 18:6a4db94011d3 12609 #define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos) /*!< SYS_T::GPF_MFPL: PF4MFP Mask */
sahilmgandhi 18:6a4db94011d3 12610
sahilmgandhi 18:6a4db94011d3 12611 #define SYS_GPF_MFPL_PF5MFP_Pos (20) /*!< SYS_T::GPF_MFPL: PF5MFP Position */
sahilmgandhi 18:6a4db94011d3 12612 #define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos) /*!< SYS_T::GPF_MFPL: PF5MFP Mask */
sahilmgandhi 18:6a4db94011d3 12613
sahilmgandhi 18:6a4db94011d3 12614 #define SYS_GPF_MFPL_PF6MFP_Pos (24) /*!< SYS_T::GPF_MFPL: PF6MFP Position */
sahilmgandhi 18:6a4db94011d3 12615 #define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) /*!< SYS_T::GPF_MFPL: PF6MFP Mask */
sahilmgandhi 18:6a4db94011d3 12616
sahilmgandhi 18:6a4db94011d3 12617 #define SYS_GPF_MFPL_PF7MFP_Pos (28) /*!< SYS_T::GPF_MFPL: PF7MFP Position */
sahilmgandhi 18:6a4db94011d3 12618 #define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) /*!< SYS_T::GPF_MFPL: PF7MFP Mask */
sahilmgandhi 18:6a4db94011d3 12619
sahilmgandhi 18:6a4db94011d3 12620 #define SYS_SRAM_INTCTL_PERRIEN_Pos (0) /*!< SYS_T::SRAM_INTCTL: PERRIEN Position */
sahilmgandhi 18:6a4db94011d3 12621 #define SYS_SRAM_INTCTL_PERRIEN_Msk (0x1ul << SYS_SRAM_INTCTL_PERRIEN_Pos) /*!< SYS_T::SRAM_INTCTL: PERRIEN Mask */
sahilmgandhi 18:6a4db94011d3 12622
sahilmgandhi 18:6a4db94011d3 12623 #define SYS_SRAM_STATUS_PERRIF_Pos (0) /*!< SYS_T::SRAM_STATUS: PERRIF Position */
sahilmgandhi 18:6a4db94011d3 12624 #define SYS_SRAM_STATUS_PERRIF_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF_Pos) /*!< SYS_T::SRAM_STATUS: PERRIF Mask */
sahilmgandhi 18:6a4db94011d3 12625
sahilmgandhi 18:6a4db94011d3 12626 #define SYS_SRAM_ERRADDR_ERRADDR_Pos (0) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Position */
sahilmgandhi 18:6a4db94011d3 12627 #define SYS_SRAM_ERRADDR_ERRADDR_Msk (0xfffffffful << SYS_SRAM_ERRADDR_ERRADDR_Pos) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Mask */
sahilmgandhi 18:6a4db94011d3 12628
sahilmgandhi 18:6a4db94011d3 12629 #define SYS_SRAM_BISTCTL_SRBIST0_Pos (0) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Position */
sahilmgandhi 18:6a4db94011d3 12630 #define SYS_SRAM_BISTCTL_SRBIST0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Mask */
sahilmgandhi 18:6a4db94011d3 12631
sahilmgandhi 18:6a4db94011d3 12632 #define SYS_SRAM_BISTCTL_SRBIST1_Pos (1) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Position */
sahilmgandhi 18:6a4db94011d3 12633 #define SYS_SRAM_BISTCTL_SRBIST1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Mask */
sahilmgandhi 18:6a4db94011d3 12634
sahilmgandhi 18:6a4db94011d3 12635 #define SYS_SRAM_BISTCTL_CRBIST_Pos (2) /*!< SYS_T::SRAM_BISTCTL: CRBIST Position */
sahilmgandhi 18:6a4db94011d3 12636 #define SYS_SRAM_BISTCTL_CRBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CRBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CRBIST Mask */
sahilmgandhi 18:6a4db94011d3 12637
sahilmgandhi 18:6a4db94011d3 12638 #define SYS_SRAM_BISTCTL_CANBIST_Pos (3) /*!< SYS_T::SRAM_BISTCTL: CANBIST Position */
sahilmgandhi 18:6a4db94011d3 12639 #define SYS_SRAM_BISTCTL_CANBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CANBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CANBIST Mask */
sahilmgandhi 18:6a4db94011d3 12640
sahilmgandhi 18:6a4db94011d3 12641 #define SYS_SRAM_BISTCTL_USBBIST_Pos (4) /*!< SYS_T::SRAM_BISTCTL: USBBIST Position */
sahilmgandhi 18:6a4db94011d3 12642 #define SYS_SRAM_BISTCTL_USBBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_USBBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: USBBIST Mask */
sahilmgandhi 18:6a4db94011d3 12643
sahilmgandhi 18:6a4db94011d3 12644 #define SYS_SRAM_BISTSTS_SRBISTEF0_Pos (0) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Position */
sahilmgandhi 18:6a4db94011d3 12645 #define SYS_SRAM_BISTSTS_SRBISTEF0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Mask */
sahilmgandhi 18:6a4db94011d3 12646
sahilmgandhi 18:6a4db94011d3 12647 #define SYS_SRAM_BISTSTS_SRBISTEF1_Pos (1) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Position */
sahilmgandhi 18:6a4db94011d3 12648 #define SYS_SRAM_BISTSTS_SRBISTEF1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Mask */
sahilmgandhi 18:6a4db94011d3 12649
sahilmgandhi 18:6a4db94011d3 12650 #define SYS_SRAM_BISTSTS_CRBISTEF_Pos (2) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Position */
sahilmgandhi 18:6a4db94011d3 12651 #define SYS_SRAM_BISTSTS_CRBISTEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBISTEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Mask */
sahilmgandhi 18:6a4db94011d3 12652
sahilmgandhi 18:6a4db94011d3 12653 #define SYS_SRAM_BISTSTS_CANBEF_Pos (3) /*!< SYS_T::SRAM_BISTSTS: CANBEF Position */
sahilmgandhi 18:6a4db94011d3 12654 #define SYS_SRAM_BISTSTS_CANBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEF Mask */
sahilmgandhi 18:6a4db94011d3 12655
sahilmgandhi 18:6a4db94011d3 12656 #define SYS_SRAM_BISTSTS_USBBEF_Pos (4) /*!< SYS_T::SRAM_BISTSTS: USBBEF Position */
sahilmgandhi 18:6a4db94011d3 12657 #define SYS_SRAM_BISTSTS_USBBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEF Mask */
sahilmgandhi 18:6a4db94011d3 12658
sahilmgandhi 18:6a4db94011d3 12659 #define SYS_SRAM_BISTSTS_SRBEND0_Pos (16) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Position */
sahilmgandhi 18:6a4db94011d3 12660 #define SYS_SRAM_BISTSTS_SRBEND0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Mask */
sahilmgandhi 18:6a4db94011d3 12661
sahilmgandhi 18:6a4db94011d3 12662 #define SYS_SRAM_BISTSTS_SRBEND1_Pos (17) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Position */
sahilmgandhi 18:6a4db94011d3 12663 #define SYS_SRAM_BISTSTS_SRBEND1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Mask */
sahilmgandhi 18:6a4db94011d3 12664
sahilmgandhi 18:6a4db94011d3 12665 #define SYS_SRAM_BISTSTS_CRBEND_Pos (18) /*!< SYS_T::SRAM_BISTSTS: CRBEND Position */
sahilmgandhi 18:6a4db94011d3 12666 #define SYS_SRAM_BISTSTS_CRBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBEND Mask */
sahilmgandhi 18:6a4db94011d3 12667
sahilmgandhi 18:6a4db94011d3 12668 #define SYS_SRAM_BISTSTS_CANBEND_Pos (19) /*!< SYS_T::SRAM_BISTSTS: CANBEND Position */
sahilmgandhi 18:6a4db94011d3 12669 #define SYS_SRAM_BISTSTS_CANBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEND Mask */
sahilmgandhi 18:6a4db94011d3 12670
sahilmgandhi 18:6a4db94011d3 12671 #define SYS_SRAM_BISTSTS_USBBEND_Pos (20) /*!< SYS_T::SRAM_BISTSTS: USBBEND Position */
sahilmgandhi 18:6a4db94011d3 12672 #define SYS_SRAM_BISTSTS_USBBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEND Mask */
sahilmgandhi 18:6a4db94011d3 12673
sahilmgandhi 18:6a4db94011d3 12674 #define SYS_IRCTCTL_FREQSEL_Pos (0) /*!< SYS_T::IRCTCTL: FREQSEL Position */
sahilmgandhi 18:6a4db94011d3 12675 #define SYS_IRCTCTL_FREQSEL_Msk (0x3ul << SYS_IRCTCTL_FREQSEL_Pos) /*!< SYS_T::IRCTCTL: FREQSEL Mask */
sahilmgandhi 18:6a4db94011d3 12676
sahilmgandhi 18:6a4db94011d3 12677 #define SYS_IRCTCTL_LOOPSEL_Pos (4) /*!< SYS_T::IRCTCTL: LOOPSEL Position */
sahilmgandhi 18:6a4db94011d3 12678 #define SYS_IRCTCTL_LOOPSEL_Msk (0x3ul << SYS_IRCTCTL_LOOPSEL_Pos) /*!< SYS_T::IRCTCTL: LOOPSEL Mask */
sahilmgandhi 18:6a4db94011d3 12679
sahilmgandhi 18:6a4db94011d3 12680 #define SYS_IRCTCTL_RETRYCNT_Pos (6) /*!< SYS_T::IRCTCTL: RETRYCNT Position */
sahilmgandhi 18:6a4db94011d3 12681 #define SYS_IRCTCTL_RETRYCNT_Msk (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos) /*!< SYS_T::IRCTCTL: RETRYCNT Mask */
sahilmgandhi 18:6a4db94011d3 12682
sahilmgandhi 18:6a4db94011d3 12683 #define SYS_IRCTCTL_CESTOPEN_Pos (8) /*!< SYS_T::IRCTCTL: CESTOPEN Position */
sahilmgandhi 18:6a4db94011d3 12684 #define SYS_IRCTCTL_CESTOPEN_Msk (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos) /*!< SYS_T::IRCTCTL: CESTOPEN Mask */
sahilmgandhi 18:6a4db94011d3 12685
sahilmgandhi 18:6a4db94011d3 12686 #define SYS_IRCTIEN_TFAILIEN_Pos (1) /*!< SYS_T::IRCTIEN: TFAILIEN Position */
sahilmgandhi 18:6a4db94011d3 12687 #define SYS_IRCTIEN_TFAILIEN_Msk (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos) /*!< SYS_T::IRCTIEN: TFAILIEN Mask */
sahilmgandhi 18:6a4db94011d3 12688
sahilmgandhi 18:6a4db94011d3 12689 #define SYS_IRCTIEN_CLKEIEN_Pos (2) /*!< SYS_T::IRCTIEN: CLKEIEN Position */
sahilmgandhi 18:6a4db94011d3 12690 #define SYS_IRCTIEN_CLKEIEN_Msk (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos) /*!< SYS_T::IRCTIEN: CLKEIEN Mask */
sahilmgandhi 18:6a4db94011d3 12691
sahilmgandhi 18:6a4db94011d3 12692 #define SYS_IRCTISTS_FREQLOCK_Pos (0) /*!< SYS_T::IRCTISTS: FREQLOCK Position */
sahilmgandhi 18:6a4db94011d3 12693 #define SYS_IRCTISTS_FREQLOCK_Msk (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos) /*!< SYS_T::IRCTISTS: FREQLOCK Mask */
sahilmgandhi 18:6a4db94011d3 12694
sahilmgandhi 18:6a4db94011d3 12695 #define SYS_IRCTISTS_TFAILIF_Pos (1) /*!< SYS_T::IRCTISTS: TFAILIF Position */
sahilmgandhi 18:6a4db94011d3 12696 #define SYS_IRCTISTS_TFAILIF_Msk (0x1ul << SYS_IRCTISTS_TFAILIF_Pos) /*!< SYS_T::IRCTISTS: TFAILIF Mask */
sahilmgandhi 18:6a4db94011d3 12697
sahilmgandhi 18:6a4db94011d3 12698 #define SYS_IRCTISTS_CLKERRIF_Pos (2) /*!< SYS_T::IRCTISTS: CLKERRIF Position */
sahilmgandhi 18:6a4db94011d3 12699 #define SYS_IRCTISTS_CLKERRIF_Msk (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos) /*!< SYS_T::IRCTISTS: CLKERRIF Mask */
sahilmgandhi 18:6a4db94011d3 12700
sahilmgandhi 18:6a4db94011d3 12701 #define SYS_REGLCTL_REGLCTL_Pos (0) /*!< SYS_T::REGLCTL: REGLCTL Position */
sahilmgandhi 18:6a4db94011d3 12702 #define SYS_REGLCTL_REGLCTL_Msk (0xfful << SYS_REGLCTL_REGLCTL_Pos) /*!< SYS_T::REGLCTL: REGLCTL Mask */
sahilmgandhi 18:6a4db94011d3 12703
sahilmgandhi 18:6a4db94011d3 12704 /**@}*/ /* SYS_CONST */
sahilmgandhi 18:6a4db94011d3 12705
sahilmgandhi 18:6a4db94011d3 12706
sahilmgandhi 18:6a4db94011d3 12707 typedef struct
sahilmgandhi 18:6a4db94011d3 12708 {
sahilmgandhi 18:6a4db94011d3 12709
sahilmgandhi 18:6a4db94011d3 12710 /**
sahilmgandhi 18:6a4db94011d3 12711 * @var SYS_INT_T::NMIEN
sahilmgandhi 18:6a4db94011d3 12712 * Offset: 0x00 NMI Source Interrupt Enable Register
sahilmgandhi 18:6a4db94011d3 12713 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 12714 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 12715 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 12716 * |[0] |BODOUT |BOD NMI Source Enable (Write Protect)
sahilmgandhi 18:6a4db94011d3 12717 * | | |0 = BOD NMI source Disabled.
sahilmgandhi 18:6a4db94011d3 12718 * | | |1 = BOD NMI source Enabled.
sahilmgandhi 18:6a4db94011d3 12719 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 12720 * |[1] |IRC_INT |IRC TRIM NMI Source Enable (Write Protect)
sahilmgandhi 18:6a4db94011d3 12721 * | | |0 = IRC TRIM NMI source Disabled.
sahilmgandhi 18:6a4db94011d3 12722 * | | |1 = IRC TRIM NMI source Enabled.
sahilmgandhi 18:6a4db94011d3 12723 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 12724 * |[2] |PWRWU_INT |Power-Down Mode Wake-Up NMI Source Enable (Write Protect)
sahilmgandhi 18:6a4db94011d3 12725 * | | |0 = Power-down mode wake-up NMI source Disabled.
sahilmgandhi 18:6a4db94011d3 12726 * | | |1 = Power-down mode wake-up NMI source Enabled.
sahilmgandhi 18:6a4db94011d3 12727 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 12728 * |[3] |SRAM_PERR |SRAM ParityCheck Error NMI Source Enable (Write Protect)
sahilmgandhi 18:6a4db94011d3 12729 * | | |0 = SRAM parity check error NMI source Disabled.
sahilmgandhi 18:6a4db94011d3 12730 * | | |1 = SRAM parity check error NMI source Enabled.
sahilmgandhi 18:6a4db94011d3 12731 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 12732 * |[4] |CLKFAIL |Clock Fail Detected NMI Source Enable (Write Protect)
sahilmgandhi 18:6a4db94011d3 12733 * | | |0 = Clock fail detected interrupt NMI source Disabled.
sahilmgandhi 18:6a4db94011d3 12734 * | | |1 = Clock fail detected interrupt NMI source Enabled.
sahilmgandhi 18:6a4db94011d3 12735 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 12736 * |[6] |RTC_INT |RTC NMI Source Enable (Write Protect)
sahilmgandhi 18:6a4db94011d3 12737 * | | |0 = RTC NMI source Disabled.
sahilmgandhi 18:6a4db94011d3 12738 * | | |1 = RTC NMI source Enabled.
sahilmgandhi 18:6a4db94011d3 12739 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 12740 * |[7] |TAMPER_INT|TAMPER_INT NMI Source Enable (Write Protect)
sahilmgandhi 18:6a4db94011d3 12741 * | | |0 = Backup register tamper detected interrupt.NMI source Disabled.
sahilmgandhi 18:6a4db94011d3 12742 * | | |1 = Backup register tamper detected interrupt.NMI source Enabled.
sahilmgandhi 18:6a4db94011d3 12743 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 12744 * |[8] |EINT0 |External Interrupt From PA.0, PD.2 Or PE.4 Pin NMI Source Enable (Write Protect)
sahilmgandhi 18:6a4db94011d3 12745 * | | |0 = External interrupt from PA.0, PD.2 or PE.4 pin NMI source Disabled.
sahilmgandhi 18:6a4db94011d3 12746 * | | |1 = External interrupt from PA.0, PD.2 or PE.4 pin NMI source Enabled.
sahilmgandhi 18:6a4db94011d3 12747 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 12748 * |[9] |EINT1 |External Interrupt From PB.0, PD.3 Or PE.5 Pin NMI Source Enable (Write Protect)
sahilmgandhi 18:6a4db94011d3 12749 * | | |0 = External interrupt from PB.0, PD.3 or PE.5 pin NMI source Disabled.
sahilmgandhi 18:6a4db94011d3 12750 * | | |1 = External interrupt from PB.0, PD.3 or PE.5 pin NMI source Enabled.
sahilmgandhi 18:6a4db94011d3 12751 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 12752 * |[10] |EINT2 |External Interrupt From PC.0 Pin NMI Source Enable (Write Protect)
sahilmgandhi 18:6a4db94011d3 12753 * | | |0 = External interrupt from PC.0 pin NMI source Disabled.
sahilmgandhi 18:6a4db94011d3 12754 * | | |1 = External interrupt from PC.0 pin NMI source Enabled.
sahilmgandhi 18:6a4db94011d3 12755 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 12756 * |[11] |EINT3 |External Interrupt From PD.0 Pin NMI Source Enable (Write Protect)
sahilmgandhi 18:6a4db94011d3 12757 * | | |0 = External interrupt from PD.0 pin NMI source Disabled.
sahilmgandhi 18:6a4db94011d3 12758 * | | |1 = External interrupt from PD.0 pin NMI source Enabled.
sahilmgandhi 18:6a4db94011d3 12759 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 12760 * |[12] |EINT4 |External Interrupt From PE.0 Pin NMI Source Enable (Write Protect)
sahilmgandhi 18:6a4db94011d3 12761 * | | |0 = External interrupt from PE.0 pin NMI source Disabled.
sahilmgandhi 18:6a4db94011d3 12762 * | | |1 = External interrupt from PE.0 pin NMI source Enabled.
sahilmgandhi 18:6a4db94011d3 12763 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 12764 * |[13] |EINT5 |External Interrupt From PF.0 Pin NMI Source Enable (Write Protect)
sahilmgandhi 18:6a4db94011d3 12765 * | | |0 = External interrupt from PF.0 pin NMI source Disabled.
sahilmgandhi 18:6a4db94011d3 12766 * | | |1 = External interrupt from PF.0 pin NMI source Enabled.
sahilmgandhi 18:6a4db94011d3 12767 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 12768 * |[14] |UART0_INT |UART0 NMI Source Enable (Write Protect)
sahilmgandhi 18:6a4db94011d3 12769 * | | |0 = UART0 NMI source Disabled.
sahilmgandhi 18:6a4db94011d3 12770 * | | |1 = UART0 NMI source Enabled.
sahilmgandhi 18:6a4db94011d3 12771 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 12772 * |[15] |UART1_INT |UART1 NMI Source Enable (Write Protect)
sahilmgandhi 18:6a4db94011d3 12773 * | | |0 = UART1 NMI source Disabled.
sahilmgandhi 18:6a4db94011d3 12774 * | | |1 = UART1 NMI source Enabled.
sahilmgandhi 18:6a4db94011d3 12775 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 12776 * @var SYS_INT_T::NMISTS
sahilmgandhi 18:6a4db94011d3 12777 * Offset: 0x04 NMI source interrupt Status Register
sahilmgandhi 18:6a4db94011d3 12778 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 12779 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 12780 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 12781 * |[0] |BODOUT |BOD Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 12782 * | | |0 = BOD interrupt is deasserted.
sahilmgandhi 18:6a4db94011d3 12783 * | | |1 = BOD interrupt is asserted.
sahilmgandhi 18:6a4db94011d3 12784 * |[1] |IRC_INT |IRC TRIM Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 12785 * | | |0 = HIRC TRIM interrupt is deasserted.
sahilmgandhi 18:6a4db94011d3 12786 * | | |1 = HIRC TRIM interrupt is asserted.
sahilmgandhi 18:6a4db94011d3 12787 * |[2] |PWRWU_INT |Power-Down Mode Wake-Up Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 12788 * | | |0 = Power-down mode wake-up interrupt is deasserted.
sahilmgandhi 18:6a4db94011d3 12789 * | | |1 = Power-down mode wake-up interrupt is asserted.
sahilmgandhi 18:6a4db94011d3 12790 * |[3] |SRAM_PERR |SRAM ParityCheck Error Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 12791 * | | |0 = SRAM parity check error interrupt is deasserted.
sahilmgandhi 18:6a4db94011d3 12792 * | | |1 = SRAM parity check error interrupt is asserted.
sahilmgandhi 18:6a4db94011d3 12793 * |[4] |CLKFAIL |Clock Fail Detected Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 12794 * | | |0 = Clock fail detected interrupt is deasserted.
sahilmgandhi 18:6a4db94011d3 12795 * | | |1 = Clock fail detected interrupt is asserted.
sahilmgandhi 18:6a4db94011d3 12796 * |[6] |RTC_INT |RTC Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 12797 * | | |0 = RTC interrupt is deasserted.
sahilmgandhi 18:6a4db94011d3 12798 * | | |1 = RTC interrupt is asserted.
sahilmgandhi 18:6a4db94011d3 12799 * |[7] |TAMPER_INT|TAMPER_INT Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 12800 * | | |0 = Backup register tamper detected interrupt is deasserted.
sahilmgandhi 18:6a4db94011d3 12801 * | | |1 = Backup register tamper detected interrupt is asserted.
sahilmgandhi 18:6a4db94011d3 12802 * |[8] |EINT0 |External Interrupt From PA.0, PD.2 Or PE.4 Pin Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 12803 * | | |0 = External Interrupt from PA.0, PD.2 or PE.4 interrupt is deasserted.
sahilmgandhi 18:6a4db94011d3 12804 * | | |1 = External Interrupt from PA.0, PD.2 or PE.4 interrupt is asserted.
sahilmgandhi 18:6a4db94011d3 12805 * |[9] |EINT1 |External Interrupt From PB.0, PD.3 Or PE.5 Pin Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 12806 * | | |0 = External Interrupt from PB.0, PD.3 or PE.5 interrupt is deasserted.
sahilmgandhi 18:6a4db94011d3 12807 * | | |1 = External Interrupt from PB.0, PD.3 or PE.5 interrupt is asserted.
sahilmgandhi 18:6a4db94011d3 12808 * |[10] |EINT2 |External Interrupt From PC.0 Pin Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 12809 * | | |0 = External Interrupt from PC.0 interrupt is deasserted.
sahilmgandhi 18:6a4db94011d3 12810 * | | |1 = External Interrupt from PC.0 interrupt is asserted.
sahilmgandhi 18:6a4db94011d3 12811 * |[11] |EINT3 |External Interrupt From PD.0 Pin Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 12812 * | | |0 = External Interrupt from PD.0 interrupt is deasserted.
sahilmgandhi 18:6a4db94011d3 12813 * | | |1 = External Interrupt from PD.0 interrupt is asserted.
sahilmgandhi 18:6a4db94011d3 12814 * |[12] |EINT4 |External Interrupt From PE.0 Pin Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 12815 * | | |0 = External Interrupt from PE.0 interrupt is deasserted.
sahilmgandhi 18:6a4db94011d3 12816 * | | |1 = External Interrupt from PE.0 interrupt is asserted.
sahilmgandhi 18:6a4db94011d3 12817 * |[13] |EINT5 |External Interrupt From PF.0 Pin Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 12818 * | | |0 = External Interrupt from PF.0 interrupt is deasserted.
sahilmgandhi 18:6a4db94011d3 12819 * | | |1 = External Interrupt from PF.0 interrupt is asserted.
sahilmgandhi 18:6a4db94011d3 12820 * |[14] |UART0_INT |UART0 Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 12821 * | | |0 = UART1 interrupt is deasserted.
sahilmgandhi 18:6a4db94011d3 12822 * | | |1 = UART1 interrupt is asserted.
sahilmgandhi 18:6a4db94011d3 12823 * |[15] |UART1_INT |UART1 Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 12824 * | | |0 = UART1 interrupt is deasserted.
sahilmgandhi 18:6a4db94011d3 12825 * | | |1 = UART1 interrupt is asserted.
sahilmgandhi 18:6a4db94011d3 12826 */
sahilmgandhi 18:6a4db94011d3 12827
sahilmgandhi 18:6a4db94011d3 12828 __IO uint32_t NMIEN; /* Offset: 0x00 NMI Source Interrupt Enable Register */
sahilmgandhi 18:6a4db94011d3 12829 __I uint32_t NMISTS; /* Offset: 0x04 NMI source interrupt Status Register */
sahilmgandhi 18:6a4db94011d3 12830
sahilmgandhi 18:6a4db94011d3 12831 } SYS_INT_T;
sahilmgandhi 18:6a4db94011d3 12832
sahilmgandhi 18:6a4db94011d3 12833
sahilmgandhi 18:6a4db94011d3 12834
sahilmgandhi 18:6a4db94011d3 12835 /**
sahilmgandhi 18:6a4db94011d3 12836 @addtogroup INT_CONST INT Bit Field Definition
sahilmgandhi 18:6a4db94011d3 12837 Constant Definitions for SYS Controller
sahilmgandhi 18:6a4db94011d3 12838 @{ */
sahilmgandhi 18:6a4db94011d3 12839
sahilmgandhi 18:6a4db94011d3 12840 #define SYS_NMIEN_BODOUT_Pos (0) /*!< SYS_INT_T::NMIEN: BODOUT Position */
sahilmgandhi 18:6a4db94011d3 12841 #define SYS_NMIEN_BODOUT_Msk (0x1ul << SYS_NMIEN_BODOUT_Pos ) /*!< SYS_INT_T::NMIEN: BODOUT Mask */
sahilmgandhi 18:6a4db94011d3 12842
sahilmgandhi 18:6a4db94011d3 12843 #define SYS_NMIEN_IRC_INT_Pos (1) /*!< SYS_INT_T::NMIEN: IRC_INT Position */
sahilmgandhi 18:6a4db94011d3 12844 #define SYS_NMIEN_IRC_INT_Msk (0x1ul << SYS_NMIEN_IRC_INT_Pos ) /*!< SYS_INT_T::NMIEN: IRC_INT Mask */
sahilmgandhi 18:6a4db94011d3 12845
sahilmgandhi 18:6a4db94011d3 12846 #define SYS_NMIEN_PWRWU_INT_Pos (2) /*!< SYS_INT_T::NMIEN: PWRWU_INT Position */
sahilmgandhi 18:6a4db94011d3 12847 #define SYS_NMIEN_PWRWU_INT_Msk (0x1ul << SYS_NMIEN_PWRWU_INT_Pos ) /*!< SYS_INT_T::NMIEN: PWRWU_INT Mask */
sahilmgandhi 18:6a4db94011d3 12848
sahilmgandhi 18:6a4db94011d3 12849 #define SYS_NMIEN_SRAM_PERR_Pos (3) /*!< SYS_INT_T::NMIEN: SRAM_PERR Position */
sahilmgandhi 18:6a4db94011d3 12850 #define SYS_NMIEN_SRAM_PERR_Msk (0x1ul << SYS_NMIEN_SRAM_PERR_Pos ) /*!< SYS_INT_T::NMIEN: SRAM_PERR Mask */
sahilmgandhi 18:6a4db94011d3 12851
sahilmgandhi 18:6a4db94011d3 12852 #define SYS_NMIEN_CLKFAIL_Pos (4) /*!< SYS_INT_T::NMIEN: CLKFAIL Position */
sahilmgandhi 18:6a4db94011d3 12853 #define SYS_NMIEN_CLKFAIL_Msk (0x1ul << SYS_NMIEN_CLKFAIL_Pos ) /*!< SYS_INT_T::NMIEN: CLKFAIL Mask */
sahilmgandhi 18:6a4db94011d3 12854
sahilmgandhi 18:6a4db94011d3 12855 #define SYS_NMIEN_RTC_INT_Pos (6) /*!< SYS_INT_T::NMIEN: RTC_INT Position */
sahilmgandhi 18:6a4db94011d3 12856 #define SYS_NMIEN_RTC_INT_Msk (0x1ul << SYS_NMIEN_RTC_INT_Pos ) /*!< SYS_INT_T::NMIEN: RTC_INT Mask */
sahilmgandhi 18:6a4db94011d3 12857
sahilmgandhi 18:6a4db94011d3 12858 #define SYS_NMIEN_TAMPER_INT_Pos (7) /*!< SYS_INT_T::NMIEN: TAMPER_INT Position */
sahilmgandhi 18:6a4db94011d3 12859 #define SYS_NMIEN_TAMPER_INT_Msk (0x1ul << SYS_NMIEN_TAMPER_INT_Pos ) /*!< SYS_INT_T::NMIEN: TAMPER_INT Mask */
sahilmgandhi 18:6a4db94011d3 12860
sahilmgandhi 18:6a4db94011d3 12861 #define SYS_NMIEN_EINT0_Pos (8) /*!< SYS_INT_T::NMIEN: EINT0 Position */
sahilmgandhi 18:6a4db94011d3 12862 #define SYS_NMIEN_EINT0_Msk (0x1ul << SYS_NMIEN_EINT0_Pos ) /*!< SYS_INT_T::NMIEN: EINT0 Mask */
sahilmgandhi 18:6a4db94011d3 12863
sahilmgandhi 18:6a4db94011d3 12864 #define SYS_NMIEN_EINT1_Pos (9) /*!< SYS_INT_T::NMIEN: EINT1 Position */
sahilmgandhi 18:6a4db94011d3 12865 #define SYS_NMIEN_EINT1_Msk (0x1ul << SYS_NMIEN_EINT1_Pos ) /*!< SYS_INT_T::NMIEN: EINT1 Mask */
sahilmgandhi 18:6a4db94011d3 12866
sahilmgandhi 18:6a4db94011d3 12867 #define SYS_NMIEN_EINT2_Pos (10) /*!< SYS_INT_T::NMIEN: EINT2 Position */
sahilmgandhi 18:6a4db94011d3 12868 #define SYS_NMIEN_EINT2_Msk (0x1ul << SYS_NMIEN_EINT2_Pos ) /*!< SYS_INT_T::NMIEN: EINT2 Mask */
sahilmgandhi 18:6a4db94011d3 12869
sahilmgandhi 18:6a4db94011d3 12870 #define SYS_NMIEN_EINT3_Pos (11) /*!< SYS_INT_T::NMIEN: EINT3 Position */
sahilmgandhi 18:6a4db94011d3 12871 #define SYS_NMIEN_EINT3_Msk (0x1ul << SYS_NMIEN_EINT3_Pos ) /*!< SYS_INT_T::NMIEN: EINT3 Mask */
sahilmgandhi 18:6a4db94011d3 12872
sahilmgandhi 18:6a4db94011d3 12873 #define SYS_NMIEN_EINT4_Pos (12) /*!< SYS_INT_T::NMIEN: EINT4 Position */
sahilmgandhi 18:6a4db94011d3 12874 #define SYS_NMIEN_EINT4_Msk (0x1ul << SYS_NMIEN_EINT4_Pos ) /*!< SYS_INT_T::NMIEN: EINT4 Mask */
sahilmgandhi 18:6a4db94011d3 12875
sahilmgandhi 18:6a4db94011d3 12876 #define SYS_NMIEN_EINT5_Pos (13) /*!< SYS_INT_T::NMIEN: EINT5 Position */
sahilmgandhi 18:6a4db94011d3 12877 #define SYS_NMIEN_EINT5_Msk (0x1ul << SYS_NMIEN_EINT5_Pos ) /*!< SYS_INT_T::NMIEN: EINT5 Mask */
sahilmgandhi 18:6a4db94011d3 12878
sahilmgandhi 18:6a4db94011d3 12879 #define SYS_NMIEN_UART0_INT_Pos (14) /*!< SYS_INT_T::NMIEN: UART0_INT Position */
sahilmgandhi 18:6a4db94011d3 12880 #define SYS_NMIEN_UART0_INT_Msk (0x1ul << SYS_NMIEN_UART0_INT_Pos ) /*!< SYS_INT_T::NMIEN: UART0_INT Mask */
sahilmgandhi 18:6a4db94011d3 12881
sahilmgandhi 18:6a4db94011d3 12882 #define SYS_NMIEN_UART1_INT_Pos (15) /*!< SYS_INT_T::NMIEN: UART1_INT Position */
sahilmgandhi 18:6a4db94011d3 12883 #define SYS_NMIEN_UART1_INT_Msk (0x1ul << SYS_NMIEN_UART1_INT_Pos ) /*!< SYS_INT_T::NMIEN: UART1_INT Mask */
sahilmgandhi 18:6a4db94011d3 12884
sahilmgandhi 18:6a4db94011d3 12885 #define SYS_NMISTS_BODOUT_Pos (0) /*!< SYS_INT_T::NMISTS: BODOUT Position */
sahilmgandhi 18:6a4db94011d3 12886 #define SYS_NMISTS_BODOUT_Msk (0x1ul << SYS_NMISTS_BODOUT_Pos ) /*!< SYS_INT_T::NMISTS: BODOUT Mask */
sahilmgandhi 18:6a4db94011d3 12887
sahilmgandhi 18:6a4db94011d3 12888 #define SYS_NMISTS_IRC_INT_Pos (1) /*!< SYS_INT_T::NMISTS: IRC_INT Position */
sahilmgandhi 18:6a4db94011d3 12889 #define SYS_NMISTS_IRC_INT_Msk (0x1ul << SYS_NMISTS_IRC_INT_Pos ) /*!< SYS_INT_T::NMISTS: IRC_INT Mask */
sahilmgandhi 18:6a4db94011d3 12890
sahilmgandhi 18:6a4db94011d3 12891 #define SYS_NMISTS_PWRWU_INT_Pos (2) /*!< SYS_INT_T::NMISTS: PWRWU_INT Position */
sahilmgandhi 18:6a4db94011d3 12892 #define SYS_NMISTS_PWRWU_INT_Msk (0x1ul << SYS_NMISTS_PWRWU_INT_Pos ) /*!< SYS_INT_T::NMISTS: PWRWU_INT Mask */
sahilmgandhi 18:6a4db94011d3 12893
sahilmgandhi 18:6a4db94011d3 12894 #define SYS_NMISTS_SRAM_PERR_Pos (3) /*!< SYS_INT_T::NMISTS: SRAM_PERR Position */
sahilmgandhi 18:6a4db94011d3 12895 #define SYS_NMISTS_SRAM_PERR_Msk (0x1ul << SYS_NMISTS_SRAM_PERR_Pos ) /*!< SYS_INT_T::NMISTS: SRAM_PERR Mask */
sahilmgandhi 18:6a4db94011d3 12896
sahilmgandhi 18:6a4db94011d3 12897 #define SYS_NMISTS_CLKFAIL_Pos (4) /*!< SYS_INT_T::NMISTS: CLKFAIL Position */
sahilmgandhi 18:6a4db94011d3 12898 #define SYS_NMISTS_CLKFAIL_Msk (0x1ul << SYS_NMISTS_CLKFAIL_Pos ) /*!< SYS_INT_T::NMISTS: CLKFAIL Mask */
sahilmgandhi 18:6a4db94011d3 12899
sahilmgandhi 18:6a4db94011d3 12900 #define SYS_NMISTS_RTC_INT_Pos (6) /*!< SYS_INT_T::NMISTS: RTC_INT Position */
sahilmgandhi 18:6a4db94011d3 12901 #define SYS_NMISTS_RTC_INT_Msk (0x1ul << SYS_NMISTS_RTC_INT_Pos ) /*!< SYS_INT_T::NMISTS: RTC_INT Mask */
sahilmgandhi 18:6a4db94011d3 12902
sahilmgandhi 18:6a4db94011d3 12903 #define SYS_NMISTS_TAMPER_INT_Pos (7) /*!< SYS_INT_T::NMISTS: TAMPER_INT Position */
sahilmgandhi 18:6a4db94011d3 12904 #define SYS_NMISTS_TAMPER_INT_Msk (0x1ul << SYS_NMISTS_TAMPER_INT_Pos ) /*!< SYS_INT_T::NMISTS: TAMPER_INT Mask */
sahilmgandhi 18:6a4db94011d3 12905
sahilmgandhi 18:6a4db94011d3 12906 #define SYS_NMISTS_EINT0_Pos (8) /*!< SYS_INT_T::NMISTS: EINT0 Position */
sahilmgandhi 18:6a4db94011d3 12907 #define SYS_NMISTS_EINT0_Msk (0x1ul << SYS_NMISTS_EINT0_Pos ) /*!< SYS_INT_T::NMISTS: EINT0 Mask */
sahilmgandhi 18:6a4db94011d3 12908
sahilmgandhi 18:6a4db94011d3 12909 #define SYS_NMISTS_EINT1_Pos (9) /*!< SYS_INT_T::NMISTS: EINT1 Position */
sahilmgandhi 18:6a4db94011d3 12910 #define SYS_NMISTS_EINT1_Msk (0x1ul << SYS_NMISTS_EINT1_Pos ) /*!< SYS_INT_T::NMISTS: EINT1 Mask */
sahilmgandhi 18:6a4db94011d3 12911
sahilmgandhi 18:6a4db94011d3 12912 #define SYS_NMISTS_EINT2_Pos (10) /*!< SYS_INT_T::NMISTS: EINT2 Position */
sahilmgandhi 18:6a4db94011d3 12913 #define SYS_NMISTS_EINT2_Msk (0x1ul << SYS_NMISTS_EINT2_Pos ) /*!< SYS_INT_T::NMISTS: EINT2 Mask */
sahilmgandhi 18:6a4db94011d3 12914
sahilmgandhi 18:6a4db94011d3 12915 #define SYS_NMISTS_EINT3_Pos (11) /*!< SYS_INT_T::NMISTS: EINT3 Position */
sahilmgandhi 18:6a4db94011d3 12916 #define SYS_NMISTS_EINT3_Msk (0x1ul << SYS_NMISTS_EINT3_Pos ) /*!< SYS_INT_T::NMISTS: EINT3 Mask */
sahilmgandhi 18:6a4db94011d3 12917
sahilmgandhi 18:6a4db94011d3 12918 #define SYS_NMISTS_EINT4_Pos (12) /*!< SYS_INT_T::NMISTS: EINT4 Position */
sahilmgandhi 18:6a4db94011d3 12919 #define SYS_NMISTS_EINT4_Msk (0x1ul << SYS_NMISTS_EINT4_Pos ) /*!< SYS_INT_T::NMISTS: EINT4 Mask */
sahilmgandhi 18:6a4db94011d3 12920
sahilmgandhi 18:6a4db94011d3 12921 #define SYS_NMISTS_EINT5_Pos (13) /*!< SYS_INT_T::NMISTS: EINT5 Position */
sahilmgandhi 18:6a4db94011d3 12922 #define SYS_NMISTS_EINT5_Msk (0x1ul << SYS_NMISTS_EINT5_Pos ) /*!< SYS_INT_T::NMISTS: EINT5 Mask */
sahilmgandhi 18:6a4db94011d3 12923
sahilmgandhi 18:6a4db94011d3 12924 #define SYS_NMISTS_UART0_INT_Pos (14) /*!< SYS_INT_T::NMISTS: UART0_INT Position */
sahilmgandhi 18:6a4db94011d3 12925 #define SYS_NMISTS_UART0_INT_Msk (0x1ul << SYS_NMISTS_UART0_INT_Pos ) /*!< SYS_INT_T::NMISTS: UART0_INT Mask */
sahilmgandhi 18:6a4db94011d3 12926
sahilmgandhi 18:6a4db94011d3 12927 #define SYS_NMISTS_UART1_INT_Pos (15) /*!< SYS_INT_T::NMISTS: UART1_INT Position */
sahilmgandhi 18:6a4db94011d3 12928 #define SYS_NMISTS_UART1_INT_Msk (0x1ul << SYS_NMISTS_UART1_INT_Pos ) /*!< SYS_INT_T::NMISTS: UART1_INT Mask */
sahilmgandhi 18:6a4db94011d3 12929
sahilmgandhi 18:6a4db94011d3 12930 /**@}*/ /* INT_CONST */
sahilmgandhi 18:6a4db94011d3 12931 /**@}*/ /* end of SYS register group */
sahilmgandhi 18:6a4db94011d3 12932
sahilmgandhi 18:6a4db94011d3 12933
sahilmgandhi 18:6a4db94011d3 12934 /*---------------------- Touch Key Controller -------------------------*/
sahilmgandhi 18:6a4db94011d3 12935 /**
sahilmgandhi 18:6a4db94011d3 12936 @addtogroup TK Touch Key Controller(TK)
sahilmgandhi 18:6a4db94011d3 12937 Memory Mapped Structure for TK Controller
sahilmgandhi 18:6a4db94011d3 12938 @{ */
sahilmgandhi 18:6a4db94011d3 12939
sahilmgandhi 18:6a4db94011d3 12940
sahilmgandhi 18:6a4db94011d3 12941 typedef struct
sahilmgandhi 18:6a4db94011d3 12942 {
sahilmgandhi 18:6a4db94011d3 12943
sahilmgandhi 18:6a4db94011d3 12944
sahilmgandhi 18:6a4db94011d3 12945 /**
sahilmgandhi 18:6a4db94011d3 12946 * @var TK_T::CTL
sahilmgandhi 18:6a4db94011d3 12947 * Offset: 0x00 Touch Key Scan Control Register
sahilmgandhi 18:6a4db94011d3 12948 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 12949 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 12950 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 12951 * |[0] |TKSEN0 |TK0 Scan Enable Bit
sahilmgandhi 18:6a4db94011d3 12952 * | | |This bit is ignored if TKREN0 (TK_REFCTL[0]) is "1" except SCANALL (TK_REFCTL[23]) is "1".
sahilmgandhi 18:6a4db94011d3 12953 * | | |0 = TKDAT0 (TK_DAT0[7:0]) is invalid.
sahilmgandhi 18:6a4db94011d3 12954 * | | |1 = TK0 is always enable for Touch Key scan. TKDAT0 (TK_DAT0[7:0]) is valid.
sahilmgandhi 18:6a4db94011d3 12955 * |[1] |TKSEN1 |TK1 Scan Enable Bit
sahilmgandhi 18:6a4db94011d3 12956 * | | |This bit is ignored if TKREN1 (TK_REFCTL[1]) is "1".
sahilmgandhi 18:6a4db94011d3 12957 * | | |0 = TKDAT1 (TK_DAT0[15:8]) is invalid.
sahilmgandhi 18:6a4db94011d3 12958 * | | |1 = TK1 is always enable for Touch Key scan. TKDAT1 (TK_DAT0[15:8]) is valid.
sahilmgandhi 18:6a4db94011d3 12959 * |[2] |TKSEN2 |TK2 Scan Enable Bit
sahilmgandhi 18:6a4db94011d3 12960 * | | |This bit is ignored if TKREN2 (TK_REFCTL[2]) is "1".
sahilmgandhi 18:6a4db94011d3 12961 * | | |0 = TKDAT2 (TK_DAT0[23:16]) is invalid.
sahilmgandhi 18:6a4db94011d3 12962 * | | |1 = TK2 is always enable for Touch Key scan. TKDAT2 (TK_DAT0[23:16]) is valid.
sahilmgandhi 18:6a4db94011d3 12963 * |[3] |TKSEN3 |TK3 Scan Enable Bit
sahilmgandhi 18:6a4db94011d3 12964 * | | |0 = TKDAT3 (TK_DAT0[31:24]) is invalid.
sahilmgandhi 18:6a4db94011d3 12965 * | | |1 = TK3 is always enable for Touch Key scan. TKDAT3 (TK_DAT0[31:24]) is valid.
sahilmgandhi 18:6a4db94011d3 12966 * | | |This bit is ignored if TKREN3 (TK_REFCTL[3]) is "1".
sahilmgandhi 18:6a4db94011d3 12967 * |[4] |TKSEN4 |TK4 Scan Enable Bit
sahilmgandhi 18:6a4db94011d3 12968 * | | |This bit is ignored if TKREN4 (TK_REFCTL[4]) is "1".
sahilmgandhi 18:6a4db94011d3 12969 * | | |0 = TKDAT4 (TK_DAT1[7:0]) is invalid.
sahilmgandhi 18:6a4db94011d3 12970 * | | |1 = TK4 is always enable for Touch Key scan. TKDAT4 (TK_DAT1[7:0]) is valid.
sahilmgandhi 18:6a4db94011d3 12971 * |[5] |TKSEN5 |TK5 Scan Enable Bit
sahilmgandhi 18:6a4db94011d3 12972 * | | |This bit is ignored if TKREN5 (TK_REFCTL[5]) is "1".
sahilmgandhi 18:6a4db94011d3 12973 * | | |0 = TKDAT5 (TK_DAT1[15:8]) is invalid.
sahilmgandhi 18:6a4db94011d3 12974 * | | |1 = TK5 is always enable for Touch Key scan. TKDAT5 (TK_DAT1[15:8]) is valid.
sahilmgandhi 18:6a4db94011d3 12975 * |[6] |TKSEN6 |TK6 Scan Enable Bit
sahilmgandhi 18:6a4db94011d3 12976 * | | |This bit is ignored if TKREN6 (TK_REFCTL[6]) is "1".
sahilmgandhi 18:6a4db94011d3 12977 * | | |0 = TKDAT6 (TK_DAT1[23:16]) is invalid.
sahilmgandhi 18:6a4db94011d3 12978 * | | |1 = TK6 is always enable for Touch Key scan. TKDAT6 (TK_DAT1[23:16]) is valid.
sahilmgandhi 18:6a4db94011d3 12979 * |[7] |TKSEN7 |TK7 Scan Enable
sahilmgandhi 18:6a4db94011d3 12980 * | | |This bit is ignored if TKREN7 (TK_REFCTL[7]) is "1".
sahilmgandhi 18:6a4db94011d3 12981 * | | |0 = TKDAT7 (TK_DAT1[31:24]) is invalid.
sahilmgandhi 18:6a4db94011d3 12982 * | | |1 = TK7 is always enable for Touch Key scan. TKDAT7 (TK_DAT1[31:24]) is valid.
sahilmgandhi 18:6a4db94011d3 12983 * |[8] |TKSEN8 |TK8 Scan Enable Bit
sahilmgandhi 18:6a4db94011d3 12984 * | | |This bit is ignored if TKREN8 (TK_REFCTL[8]) is "1".
sahilmgandhi 18:6a4db94011d3 12985 * | | |0 = TKDAT8 (TK_DAT2[7:0]) is invalid.
sahilmgandhi 18:6a4db94011d3 12986 * | | |1 = TK8 is always enable for Touch Key scan. TKDAT8 (TK_DAT2[7:0]) is valid.
sahilmgandhi 18:6a4db94011d3 12987 * |[9] |TKSEN9 |TK9 Scan Enable Bit
sahilmgandhi 18:6a4db94011d3 12988 * | | |This bit is ignored if TKREN9 (TK_REFCTL[9]) is "1".
sahilmgandhi 18:6a4db94011d3 12989 * | | |0 = TKDAT9 (TK_DAT2[15:8]) is invalid.
sahilmgandhi 18:6a4db94011d3 12990 * | | |1 = TK9 is always enable for Touch Key scan. TKDAT9 (TK_DAT2[15:8]) is valid.
sahilmgandhi 18:6a4db94011d3 12991 * |[10] |TKSEN10 |TK10 Scan Enable Bit
sahilmgandhi 18:6a4db94011d3 12992 * | | |This bit is ignored if TKREN10 (TK_REFCTL[10]) is "1".
sahilmgandhi 18:6a4db94011d3 12993 * | | |0 = TKDAT10 (TK_DAT2[23:16]) is invalid.
sahilmgandhi 18:6a4db94011d3 12994 * | | |1 = TK10 is always enable for Touch Key scan. TKDAT10 (TK_DAT2[23:16]) is valid.
sahilmgandhi 18:6a4db94011d3 12995 * |[11] |TKSEN11 |TK11 Scan Enable
sahilmgandhi 18:6a4db94011d3 12996 * | | |This bit is ignored if TKREN11 (TK_REFCTL[11]) is "1".
sahilmgandhi 18:6a4db94011d3 12997 * | | |0 = TKDAT11 (TK_DAT2[31:24]) is invalid.
sahilmgandhi 18:6a4db94011d3 12998 * | | |1 = TK11 is always enable for Touch Key scan. TKDAT11 (TK_DAT2[31:24]) is valid.
sahilmgandhi 18:6a4db94011d3 12999 * |[12] |TKSEN12 |TK12 Scan Enable Bit
sahilmgandhi 18:6a4db94011d3 13000 * | | |This bit is ignored if TKREN12 (TK_REFCTL[12]) is "1".
sahilmgandhi 18:6a4db94011d3 13001 * | | |0 = TKDAT12 (TK_DAT3[7:0]) is invalid.
sahilmgandhi 18:6a4db94011d3 13002 * | | |1 = TK12 is always enable for Touch Key scan. TKDAT12 (TK_DAT3[7:0]) is valid.
sahilmgandhi 18:6a4db94011d3 13003 * |[13] |TKSEN13 |TK13 Scan Enable Bit
sahilmgandhi 18:6a4db94011d3 13004 * | | |This bit is ignored if TKREN13 (TK_REFCTL[13]) is "1".
sahilmgandhi 18:6a4db94011d3 13005 * | | |0 = TKDAT13 (TK_DAT3[15:8]) is invalid.
sahilmgandhi 18:6a4db94011d3 13006 * | | |1 = TK13 is always enable for key scan. TKDAT13 (TK_DAT3[15:8]) is valid.
sahilmgandhi 18:6a4db94011d3 13007 * |[14] |TKSEN14 |TK14 Scan Enable Bit
sahilmgandhi 18:6a4db94011d3 13008 * | | |This bit is ignored if TKREN14 (TK_REFCTL[14]) is "1".
sahilmgandhi 18:6a4db94011d3 13009 * | | |0 = TKDAT14 (TK_DAT3[23:16]) is invalid.
sahilmgandhi 18:6a4db94011d3 13010 * | | |1 = TK14 is always enabled for key scan. TKDAT14 (TK_DAT3[23:16]) is valid.
sahilmgandhi 18:6a4db94011d3 13011 * |[15] |TKSEN15 |TK15 Scan Enable Bit
sahilmgandhi 18:6a4db94011d3 13012 * | | |This bit is ignored if TKREN15 (TK_REFCTL[15]) is "1".
sahilmgandhi 18:6a4db94011d3 13013 * | | |0 = TKDAT15 (TK_DAT3[31:24]) is invalid.
sahilmgandhi 18:6a4db94011d3 13014 * | | |1 = TK15 is always enabled for key scan. TKDAT15 (TK_DAT3[31:24]) is valid.
sahilmgandhi 18:6a4db94011d3 13015 * |[16] |TKSEN16 |TK16 Scan Enable Bit
sahilmgandhi 18:6a4db94011d3 13016 * | | |This bit is ignored if TKREN16 (TK_REFCTL[16]) is "1".
sahilmgandhi 18:6a4db94011d3 13017 * | | |0 = TKDAT16 (TK_DAT4[7:0]) is invalid.
sahilmgandhi 18:6a4db94011d3 13018 * | | |1 = TK16 is always enabled for key scan. TKDAT16 (TK_DAT4[7:0]) is valid.
sahilmgandhi 18:6a4db94011d3 13019 * |[22:20] |AVCCHSEL |AVCCH Voltage Select
sahilmgandhi 18:6a4db94011d3 13020 * | | |000 = 1/16 VDD.
sahilmgandhi 18:6a4db94011d3 13021 * | | |001 = 1/8 VDD.
sahilmgandhi 18:6a4db94011d3 13022 * | | |010 = 3/16 VDD.
sahilmgandhi 18:6a4db94011d3 13023 * | | |011 = 1/4 VDD.
sahilmgandhi 18:6a4db94011d3 13024 * | | |100 = 5/16 VDD.
sahilmgandhi 18:6a4db94011d3 13025 * | | |101 = 3/8 VDD.
sahilmgandhi 18:6a4db94011d3 13026 * | | |110 = 7/16 VDD.
sahilmgandhi 18:6a4db94011d3 13027 * | | |111 = 1/2 VDD.
sahilmgandhi 18:6a4db94011d3 13028 * |[24] |SCAN |Scan
sahilmgandhi 18:6a4db94011d3 13029 * | | |Write an '1' to this bit will immediately initiate key scan on all channels which are enabled.
sahilmgandhi 18:6a4db94011d3 13030 * | | |This bit will be self-cleared after key scan started.
sahilmgandhi 18:6a4db94011d3 13031 * |[25] |TMRTRGEN |Timer Trigger Enable Bit
sahilmgandhi 18:6a4db94011d3 13032 * | | |0 = Disable timer to trigger key scan.
sahilmgandhi 18:6a4db94011d3 13033 * | | |1 = Enable timer triggers key scan periodically. Key scan will be initiated by Timer0 periodically.
sahilmgandhi 18:6a4db94011d3 13034 * |[31] |TKEN |Touch Key Scan Enable Bit
sahilmgandhi 18:6a4db94011d3 13035 * | | |0 = Disable Touch Key Function.
sahilmgandhi 18:6a4db94011d3 13036 * | | |1 = Enable Touch Key Function.
sahilmgandhi 18:6a4db94011d3 13037 * @var TK_T::REFCTL
sahilmgandhi 18:6a4db94011d3 13038 * Offset: 0x04 Touch Key Reference Control Register
sahilmgandhi 18:6a4db94011d3 13039 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 13040 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 13041 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 13042 * |[0] |TKREN0 |TK0 Reference Enable Bit
sahilmgandhi 18:6a4db94011d3 13043 * | | |0 = TK0 is not reference.
sahilmgandhi 18:6a4db94011d3 13044 * | | |1 = TK0 is set as reference, and TKDAT0 (TK_DAT0[7:0]) is invalid except SCANALL (TK_REFCTL[23]) is "1".
sahilmgandhi 18:6a4db94011d3 13045 * |[1] |TKREN1 |TK1 Reference Enable Bit
sahilmgandhi 18:6a4db94011d3 13046 * | | |0 = TK1 is not reference.
sahilmgandhi 18:6a4db94011d3 13047 * | | |1 = TK1 is set as reference, and TKDAT1 (TK_DAT0[15:8]) is invalid.
sahilmgandhi 18:6a4db94011d3 13048 * |[2] |TKREN2 |TK2 Reference Enable Bit
sahilmgandhi 18:6a4db94011d3 13049 * | | |0 = TK2 is not reference.
sahilmgandhi 18:6a4db94011d3 13050 * | | |1 = TK2 is set as reference, and TKDAT2 (TK_DAT0[23:16]) is invalid.
sahilmgandhi 18:6a4db94011d3 13051 * |[3] |TKREN3 |TK3 Reference Enable Bit
sahilmgandhi 18:6a4db94011d3 13052 * | | |0 = TK3 is not reference.
sahilmgandhi 18:6a4db94011d3 13053 * | | |1 = TK3 is set as reference, and TKDAT3 (TK_DAT0[31:24]) is invalid.
sahilmgandhi 18:6a4db94011d3 13054 * |[4] |TKREN4 |TK4 Reference Enable Bit
sahilmgandhi 18:6a4db94011d3 13055 * | | |0 = TK4 is not reference.
sahilmgandhi 18:6a4db94011d3 13056 * | | |1 = TK4 is set as reference, and TKDAT4 (TK_DAT1[7:0]) is invalid.
sahilmgandhi 18:6a4db94011d3 13057 * |[5] |TKREN5 |TK5 Reference Enable Bit
sahilmgandhi 18:6a4db94011d3 13058 * | | |0 = TK5 is not reference.
sahilmgandhi 18:6a4db94011d3 13059 * | | |1 = TK5 is set as reference, and TKDAT5 (TK_DAT1[15:8]) is invalid.
sahilmgandhi 18:6a4db94011d3 13060 * |[6] |TKREN6 |TK6 Reference Enable Bit
sahilmgandhi 18:6a4db94011d3 13061 * | | |0 = TK6 is not reference.
sahilmgandhi 18:6a4db94011d3 13062 * | | |1 = TK6 is set as reference, and TKDAT6 (TK_DAT1[23:16]) is invalid.
sahilmgandhi 18:6a4db94011d3 13063 * |[7] |TKREN7 |TK7 Reference Enable Bit
sahilmgandhi 18:6a4db94011d3 13064 * | | |0 = TK7 is not reference.
sahilmgandhi 18:6a4db94011d3 13065 * | | |1 = TK7 is set as reference, and TKDAT7 (TK_DAT1[31:24]) is invalid.
sahilmgandhi 18:6a4db94011d3 13066 * |[8] |TKREN8 |TK8 Reference Enable Bit
sahilmgandhi 18:6a4db94011d3 13067 * | | |0 = TK8 is not reference.
sahilmgandhi 18:6a4db94011d3 13068 * | | |1 = TK8 is set as reference, and TKDAT8 (TK_DAT2[7:0]) is invalid.
sahilmgandhi 18:6a4db94011d3 13069 * |[9] |TKREN9 |TK9 Reference Enable Bit
sahilmgandhi 18:6a4db94011d3 13070 * | | |0 = TK9 is not reference.
sahilmgandhi 18:6a4db94011d3 13071 * | | |1 = TK9 is set as reference, and TKDAT9 (TK_DAT2[15:8]) is invalid.
sahilmgandhi 18:6a4db94011d3 13072 * |[10] |TKREN10 |TK10 Reference Enable Bit
sahilmgandhi 18:6a4db94011d3 13073 * | | |0 = TK10 is not reference.
sahilmgandhi 18:6a4db94011d3 13074 * | | |1 = TK10 is set as reference, and TKDAT10 (TK_DAT2[23:16]) is invalid.
sahilmgandhi 18:6a4db94011d3 13075 * |[11] |TKREN11 |TK11 Reference Enable Bit
sahilmgandhi 18:6a4db94011d3 13076 * | | |0 = TK11 is not reference.
sahilmgandhi 18:6a4db94011d3 13077 * | | |1 = TK11 is set as reference, and TKDAT11 (TK_DAT2[31:24]) is invalid.
sahilmgandhi 18:6a4db94011d3 13078 * |[12] |TKREN12 |TK12 Reference Enable Bit
sahilmgandhi 18:6a4db94011d3 13079 * | | |0 = TK12 is not reference.
sahilmgandhi 18:6a4db94011d3 13080 * | | |1 = TK12 is set as reference, and TKDAT12 (TK_DAT3[7:0]) is invalid.
sahilmgandhi 18:6a4db94011d3 13081 * |[13] |TKREN13 |TK13 Reference Enable Bit
sahilmgandhi 18:6a4db94011d3 13082 * | | |0 = TK13 is not reference.
sahilmgandhi 18:6a4db94011d3 13083 * | | |1 = TK13 is set as reference, and TKDAT13 (TK_DAT3[15:8]) is invalid.
sahilmgandhi 18:6a4db94011d3 13084 * |[14] |TKREN14 |TK14 Reference Enable Bit
sahilmgandhi 18:6a4db94011d3 13085 * | | |0 = TK14 is not reference.
sahilmgandhi 18:6a4db94011d3 13086 * | | |1 = TK14 is set as reference, and TKDAT14 (TK_DAT3[23:16]) is invalid.
sahilmgandhi 18:6a4db94011d3 13087 * |[15] |TKREN15 |TK15 Reference Enable Bit
sahilmgandhi 18:6a4db94011d3 13088 * | | |0 = TK15 is not reference.
sahilmgandhi 18:6a4db94011d3 13089 * | | |1 = TK15 is set as reference, and TKDAT15 (TK_DAT3[31:24]) is invalid.
sahilmgandhi 18:6a4db94011d3 13090 * |[16] |TKREN16 |TK16 Reference Enable Bit
sahilmgandhi 18:6a4db94011d3 13091 * | | |0 = TK16 is not reference.
sahilmgandhi 18:6a4db94011d3 13092 * | | |1 = TK16 is set as reference, and TKDAT16 (TK_DAT4[7:0]) is invalid.
sahilmgandhi 18:6a4db94011d3 13093 * | | |Note: This bit is forced to "1" automatically if none is set as reference.
sahilmgandhi 18:6a4db94011d3 13094 * |[23] |SCANALL |All Key Scan Enable Bit
sahilmgandhi 18:6a4db94011d3 13095 * | | |This function is used for low power key scanning operation.
sahilmgandhi 18:6a4db94011d3 13096 * | | |TKDAT0 (TK_DAT0[7:0]) is the only one valid data when key scan is complete.
sahilmgandhi 18:6a4db94011d3 13097 * | | |0 = Disable All Keys Scan function.
sahilmgandhi 18:6a4db94011d3 13098 * | | |1 = Enable All Keys Scan function.
sahilmgandhi 18:6a4db94011d3 13099 * |[25:24] |SENTCTL |Touch Key Sensing Time Control
sahilmgandhi 18:6a4db94011d3 13100 * | | |00 = 128 x SENPTCTL.
sahilmgandhi 18:6a4db94011d3 13101 * | | |01 = 255 x SENPTCTL.
sahilmgandhi 18:6a4db94011d3 13102 * | | |10 = 511 x SENPTCTL.
sahilmgandhi 18:6a4db94011d3 13103 * | | |11 = 1023 x SENPTCTL.
sahilmgandhi 18:6a4db94011d3 13104 * |[29:28] |SENPTCTL |Touch Key Sensing Pulse Width Time Control
sahilmgandhi 18:6a4db94011d3 13105 * | | |00 = 1us.
sahilmgandhi 18:6a4db94011d3 13106 * | | |01 = 2us.
sahilmgandhi 18:6a4db94011d3 13107 * | | |10 = 4us.
sahilmgandhi 18:6a4db94011d3 13108 * | | |11 = 8us.
sahilmgandhi 18:6a4db94011d3 13109 * @var TK_T::CCBDAT0
sahilmgandhi 18:6a4db94011d3 13110 * Offset: 0x08 Touch Key Complement Capacitor Bank Data Register 0
sahilmgandhi 18:6a4db94011d3 13111 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 13112 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 13113 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 13114 * |[7:0] |CCBDAT0 |TK0 Complement CB Data
sahilmgandhi 18:6a4db94011d3 13115 * | | |This is register is used for TK0 sensitivity adjustment.
sahilmgandhi 18:6a4db94011d3 13116 * |[15:8] |CCBDAT1 |TK1 Complement CB Data
sahilmgandhi 18:6a4db94011d3 13117 * | | |This is register is used for TK1 sensitivity adjustment.
sahilmgandhi 18:6a4db94011d3 13118 * |[23:16] |CCBDAT2 |TK2 Complement CB Data
sahilmgandhi 18:6a4db94011d3 13119 * | | |This is register is used for TK2 sensitivity adjustment.
sahilmgandhi 18:6a4db94011d3 13120 * |[31:24] |CCBDAT3 |TK3 Complement CB Data
sahilmgandhi 18:6a4db94011d3 13121 * | | |This is register is used for TK3 sensitivity adjustment.
sahilmgandhi 18:6a4db94011d3 13122 * @var TK_T::CCBDAT1
sahilmgandhi 18:6a4db94011d3 13123 * Offset: 0x0C Touch Key Complement Capacitor Bank Data Register 1
sahilmgandhi 18:6a4db94011d3 13124 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 13125 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 13126 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 13127 * |[7:0] |CCBDAT4 |TK4 Complement CB Data
sahilmgandhi 18:6a4db94011d3 13128 * | | |This is register is used for TK4 sensitivity adjustment.
sahilmgandhi 18:6a4db94011d3 13129 * |[15:8] |CCBDAT5 |TK5 Complement CB Data
sahilmgandhi 18:6a4db94011d3 13130 * | | |This is register is used for TK5 sensitivity adjustment.
sahilmgandhi 18:6a4db94011d3 13131 * |[23:16] |CCBDAT6 |TK6 Complement CB Data
sahilmgandhi 18:6a4db94011d3 13132 * | | |This is register is used for TK6 sensitivity adjustment.
sahilmgandhi 18:6a4db94011d3 13133 * |[31:24] |CCBDAT7 |TK7 Complement CB Data
sahilmgandhi 18:6a4db94011d3 13134 * | | |This is register is used for TK7 sensitivity adjustment.
sahilmgandhi 18:6a4db94011d3 13135 * @var TK_T::CCBDAT2
sahilmgandhi 18:6a4db94011d3 13136 * Offset: 0x10 Touch Key Complement Capacitor Bank Data Register 2
sahilmgandhi 18:6a4db94011d3 13137 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 13138 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 13139 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 13140 * |[7:0] |CCBDAT8 |TK8 Complement CB Data
sahilmgandhi 18:6a4db94011d3 13141 * | | |This is register is used for TK8 sensitivity adjustment.
sahilmgandhi 18:6a4db94011d3 13142 * |[15:8] |CCBDAT9 |TK9 Complement CB Data
sahilmgandhi 18:6a4db94011d3 13143 * | | |This is register is used for TK9 sensitivity adjustment.
sahilmgandhi 18:6a4db94011d3 13144 * |[23:16] |CCBDAT10 |TK10 Complement CB Data
sahilmgandhi 18:6a4db94011d3 13145 * | | |This is register is used for TK10 sensitivity adjustment.
sahilmgandhi 18:6a4db94011d3 13146 * |[31:24] |CCBDAT11 |TK11 Complement CB Data
sahilmgandhi 18:6a4db94011d3 13147 * | | |This is register is used for TK11 sensitivity adjustment.
sahilmgandhi 18:6a4db94011d3 13148 * @var TK_T::CCBDAT3
sahilmgandhi 18:6a4db94011d3 13149 * Offset: 0x14 Touch Key Complement Capacitor Bank Data Register 3
sahilmgandhi 18:6a4db94011d3 13150 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 13151 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 13152 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 13153 * |[7:0] |CCBDAT12 |TK12 Complement CB Data
sahilmgandhi 18:6a4db94011d3 13154 * | | |This is register is used for TK12 sensitivity adjustment.
sahilmgandhi 18:6a4db94011d3 13155 * |[15:8] |CCBDAT13 |TK13 Complement CB Data
sahilmgandhi 18:6a4db94011d3 13156 * | | |This is register is used for TK13 sensitivity adjustment.
sahilmgandhi 18:6a4db94011d3 13157 * |[23:16] |CCBDAT14 |TK14 Complement CB Data
sahilmgandhi 18:6a4db94011d3 13158 * | | |This is register is used for TK14 sensitivity adjustment.
sahilmgandhi 18:6a4db94011d3 13159 * |[31:24] |CCBDAT15 |TK15 Complement CB Data
sahilmgandhi 18:6a4db94011d3 13160 * | | |This is register is used for TK15 sensitivity adjustment.
sahilmgandhi 18:6a4db94011d3 13161 * @var TK_T::CCBDAT4
sahilmgandhi 18:6a4db94011d3 13162 * Offset: 0x18 Touch Key Complement Capacitor Bank Data Register 4
sahilmgandhi 18:6a4db94011d3 13163 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 13164 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 13165 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 13166 * |[7:0] |CCBDAT16 |TK16 Complement CB Data
sahilmgandhi 18:6a4db94011d3 13167 * | | |This is register is used for TK16 sensitivity adjustment.
sahilmgandhi 18:6a4db94011d3 13168 * |[31:24] |REFCBDAT |Reference CB Data
sahilmgandhi 18:6a4db94011d3 13169 * @var TK_T::IDLESEL
sahilmgandhi 18:6a4db94011d3 13170 * Offset: 0x1C Touch Key Idle State Control Register
sahilmgandhi 18:6a4db94011d3 13171 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 13172 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 13173 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 13174 * |[31:0] |IDLSn |TKn Idle State Control
sahilmgandhi 18:6a4db94011d3 13175 * | | |This register is ignored if both TKSENn (TK_CTL[n]) and POLENn (TK_POLCTL[n+8]) are "0" or TKRENn (TK_REFCTL[n]) is "1".
sahilmgandhi 18:6a4db94011d3 13176 * | | |00 = TKn connected to GND.
sahilmgandhi 18:6a4db94011d3 13177 * | | |01 = TKn connected to AVCCH.
sahilmgandhi 18:6a4db94011d3 13178 * | | |10 = TKn connected to VDD.
sahilmgandhi 18:6a4db94011d3 13179 * | | |11 = TKn connected to VDD.
sahilmgandhi 18:6a4db94011d3 13180 * | | |n = 0 to 15.
sahilmgandhi 18:6a4db94011d3 13181 * @var TK_T::POLSEL
sahilmgandhi 18:6a4db94011d3 13182 * Offset: 0x20 Touch Key Polarity Select Register
sahilmgandhi 18:6a4db94011d3 13183 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 13184 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 13185 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 13186 * |[31:0] |POLSELn |TKn Polarity Select
sahilmgandhi 18:6a4db94011d3 13187 * | | |This register is ignored if POLENn (TK_POLCTL[n+8]) is "0", or either TKSENn (TK_CTL[n]) or TKRENn (TK_REFCTL[n]) is "1".
sahilmgandhi 18:6a4db94011d3 13188 * | | |00 = TKn connected to Gnd.
sahilmgandhi 18:6a4db94011d3 13189 * | | |01 = TKn connected to AVCCH.
sahilmgandhi 18:6a4db94011d3 13190 * | | |10 = TKn connected to VDD.
sahilmgandhi 18:6a4db94011d3 13191 * | | |11 = TKn connected to VDD.
sahilmgandhi 18:6a4db94011d3 13192 * @var TK_T::POLCTL
sahilmgandhi 18:6a4db94011d3 13193 * Offset: 0x24 Touch Key Polarity Control Register
sahilmgandhi 18:6a4db94011d3 13194 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 13195 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 13196 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 13197 * |[1:0] |IDLS16 |TK16 Idle State Control
sahilmgandhi 18:6a4db94011d3 13198 * | | |This register is ignored if both TKSEN16 (TK_CTL[16]) and POLEN16 (TK_POLCTL[24]) are "0" or TKREN16 (TK_REFCTL[16]) is "1".
sahilmgandhi 18:6a4db94011d3 13199 * | | |00 = TK16 connected to Gnd.
sahilmgandhi 18:6a4db94011d3 13200 * | | |01 = TK16 connected to AVCCH.
sahilmgandhi 18:6a4db94011d3 13201 * | | |10 = TK16 connected to VDD.
sahilmgandhi 18:6a4db94011d3 13202 * | | |11 = TK16 connected to VDD.
sahilmgandhi 18:6a4db94011d3 13203 * |[3:2] |POLSEL16 |TK16 Polarity Control
sahilmgandhi 18:6a4db94011d3 13204 * | | |This register is ignored if POLEN16 (TK_POLCTL[24]) is "0", or either TKSEN16 (TK_CTL[16]) or TKREN16 (TK_REFCTL[16]) is "1".
sahilmgandhi 18:6a4db94011d3 13205 * | | |00 = TK16 connected to Gnd.
sahilmgandhi 18:6a4db94011d3 13206 * | | |01 = TK16 connected to AVCCH.
sahilmgandhi 18:6a4db94011d3 13207 * | | |10 = TK16 connected to VDD.
sahilmgandhi 18:6a4db94011d3 13208 * | | |11 = TK16 connected to VDD.
sahilmgandhi 18:6a4db94011d3 13209 * |[5:4] |CBPOLSEL |Capacitor Bank Polarity Select
sahilmgandhi 18:6a4db94011d3 13210 * | | |00 = Gnd.
sahilmgandhi 18:6a4db94011d3 13211 * | | |01 = AVCCH.
sahilmgandhi 18:6a4db94011d3 13212 * | | |10 = VDD.
sahilmgandhi 18:6a4db94011d3 13213 * | | |11 = VDD.
sahilmgandhi 18:6a4db94011d3 13214 * |[8] |POLEN0 |TK0 Polarity Function Enable Control
sahilmgandhi 18:6a4db94011d3 13215 * | | |0 = Disabled.
sahilmgandhi 18:6a4db94011d3 13216 * | | |1 = Enabled.
sahilmgandhi 18:6a4db94011d3 13217 * |[9] |POLEN1 |TK1 Polarity Function Enable Control
sahilmgandhi 18:6a4db94011d3 13218 * | | |0 = Disabled.
sahilmgandhi 18:6a4db94011d3 13219 * | | |1 = Enabled.
sahilmgandhi 18:6a4db94011d3 13220 * |[10] |POLEN2 |TK2 Polarity Function Enable Control
sahilmgandhi 18:6a4db94011d3 13221 * | | |0 = Disabled.
sahilmgandhi 18:6a4db94011d3 13222 * | | |1 = Enabled.
sahilmgandhi 18:6a4db94011d3 13223 * |[11] |POLEN3 |TK3 Polarity Function Enable Control
sahilmgandhi 18:6a4db94011d3 13224 * | | |0 = Disabled.
sahilmgandhi 18:6a4db94011d3 13225 * | | |1 = Enabled.
sahilmgandhi 18:6a4db94011d3 13226 * |[12] |POLEN4 |TK4 Polarity Function Enable Control
sahilmgandhi 18:6a4db94011d3 13227 * | | |0 = Disabled.
sahilmgandhi 18:6a4db94011d3 13228 * | | |1 = Enabled.
sahilmgandhi 18:6a4db94011d3 13229 * |[13] |POLEN5 |TK5 Polarity Function Enable Control
sahilmgandhi 18:6a4db94011d3 13230 * | | |0 = Disabled.
sahilmgandhi 18:6a4db94011d3 13231 * | | |1 = Enabled.
sahilmgandhi 18:6a4db94011d3 13232 * |[14] |POLEN6 |TK6 Polarity Function Enable Control
sahilmgandhi 18:6a4db94011d3 13233 * | | |0 = Disabled.
sahilmgandhi 18:6a4db94011d3 13234 * | | |1 = Enabled.
sahilmgandhi 18:6a4db94011d3 13235 * |[15] |POLEN7 |TK7 Polarity Function Enable Control
sahilmgandhi 18:6a4db94011d3 13236 * | | |0 = Disabled.
sahilmgandhi 18:6a4db94011d3 13237 * | | |1 = Enabled.
sahilmgandhi 18:6a4db94011d3 13238 * |[16] |POLEN8 |TK8 Polarity Function Enable Control
sahilmgandhi 18:6a4db94011d3 13239 * | | |0 = Disabled.
sahilmgandhi 18:6a4db94011d3 13240 * | | |1 = Enabled.
sahilmgandhi 18:6a4db94011d3 13241 * |[17] |POLEN9 |TK9 Polarity Function Enable Control
sahilmgandhi 18:6a4db94011d3 13242 * | | |0 = Disabled.
sahilmgandhi 18:6a4db94011d3 13243 * | | |1 = Enabled.
sahilmgandhi 18:6a4db94011d3 13244 * |[18] |POLEN10 |TK10 Polarity Function Enable Control
sahilmgandhi 18:6a4db94011d3 13245 * | | |0 = Disabled.
sahilmgandhi 18:6a4db94011d3 13246 * | | |1 = Enabled.
sahilmgandhi 18:6a4db94011d3 13247 * |[19] |POLEN11 |TK11 Polarity Function Enable Control
sahilmgandhi 18:6a4db94011d3 13248 * | | |0 = Disabled.
sahilmgandhi 18:6a4db94011d3 13249 * | | |1 = Enabled.
sahilmgandhi 18:6a4db94011d3 13250 * |[20] |POLEN12 |TK12 Polarity Function Enable Control
sahilmgandhi 18:6a4db94011d3 13251 * | | |0 = Disabled.
sahilmgandhi 18:6a4db94011d3 13252 * | | |1 = Enabled.
sahilmgandhi 18:6a4db94011d3 13253 * |[21] |POLEN13 |TK13 Polarity Function Enable Control
sahilmgandhi 18:6a4db94011d3 13254 * | | |0 = Disabled.
sahilmgandhi 18:6a4db94011d3 13255 * | | |1 = Enabled.
sahilmgandhi 18:6a4db94011d3 13256 * |[22] |POLEN14 |TK14 Polarity Function Enable Control
sahilmgandhi 18:6a4db94011d3 13257 * | | |0 = Disabled.
sahilmgandhi 18:6a4db94011d3 13258 * | | |1 = Enabled.
sahilmgandhi 18:6a4db94011d3 13259 * |[23] |POLEN15 |TK15 Polarity Function Enable Control
sahilmgandhi 18:6a4db94011d3 13260 * | | |0 = Disabled.
sahilmgandhi 18:6a4db94011d3 13261 * | | |1 = Enabled.
sahilmgandhi 18:6a4db94011d3 13262 * |[24] |POLEN16 |TK16 Polarity Function Enable Control
sahilmgandhi 18:6a4db94011d3 13263 * | | |0 = Disabled.
sahilmgandhi 18:6a4db94011d3 13264 * | | |1 = Enabled.
sahilmgandhi 18:6a4db94011d3 13265 * |[31] |SPOTINIT |Touch Key Sensing Initial Potential Control
sahilmgandhi 18:6a4db94011d3 13266 * | | |0 = Key pad is connected to Gnd before sensing.
sahilmgandhi 18:6a4db94011d3 13267 * | | |1 = Key pad is connected to AVCCH before sensing.
sahilmgandhi 18:6a4db94011d3 13268 * @var TK_T::STATUS
sahilmgandhi 18:6a4db94011d3 13269 * Offset: 0x28 Touch Key Status Register
sahilmgandhi 18:6a4db94011d3 13270 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 13271 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 13272 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 13273 * |[0] |BUSY |Touch Key Busy (Read Only)
sahilmgandhi 18:6a4db94011d3 13274 * | | |0 = Key scan is complete or stopped.
sahilmgandhi 18:6a4db94011d3 13275 * | | |1 = Key scan is proceeding.
sahilmgandhi 18:6a4db94011d3 13276 * |[1] |SCIF |Touch Key Scan Complete Interrupt Flag
sahilmgandhi 18:6a4db94011d3 13277 * | | |This bit will be cleared by writing a "1" to this bit.
sahilmgandhi 18:6a4db94011d3 13278 * | | |0 = Key scan is proceeding and data is not ready for read.
sahilmgandhi 18:6a4db94011d3 13279 * | | |1 = Key scan is complete and data is ready for read in TKDATx registers.
sahilmgandhi 18:6a4db94011d3 13280 * | | |Note1: The Touch Key interrupt asserts if SCINTEN bit of TK_INTEN register is set.
sahilmgandhi 18:6a4db94011d3 13281 * | | |Note2: The Touch Key interrupt also asserts if SCTHIEN bit of TK_INTEN register is set and any channel data value is greater/less than its threshold setting
sahilmgandhi 18:6a4db94011d3 13282 * |[8] |TKIF0 |TK0 Interrupt Flag
sahilmgandhi 18:6a4db94011d3 13283 * | | |This bit will be cleared by writing a "1" to this bit.
sahilmgandhi 18:6a4db94011d3 13284 * | | |0 = No threshold control event with TK0.
sahilmgandhi 18:6a4db94011d3 13285 * | | |1 = Threshold control event occurs with TK0.
sahilmgandhi 18:6a4db94011d3 13286 * |[9] |TKIF1 |TK1 Interrupt Flag
sahilmgandhi 18:6a4db94011d3 13287 * | | |This bit will be cleared by writing a "1" to this bit.
sahilmgandhi 18:6a4db94011d3 13288 * | | |0 = No threshold control event with TK1.
sahilmgandhi 18:6a4db94011d3 13289 * | | |1 = Threshold control event occurs with TK1.
sahilmgandhi 18:6a4db94011d3 13290 * |[10] |TKIF2 |TK2 Interrupt Flag
sahilmgandhi 18:6a4db94011d3 13291 * | | |This bit will be cleared by writing a "1" to this bit.
sahilmgandhi 18:6a4db94011d3 13292 * | | |0 = No threshold control event with TK2.
sahilmgandhi 18:6a4db94011d3 13293 * | | |1 = Threshold control event occurs with TK2.
sahilmgandhi 18:6a4db94011d3 13294 * |[11] |TKIF3 |TK3 Interrupt Flag
sahilmgandhi 18:6a4db94011d3 13295 * | | |This bit will be cleared by writing a "1" to this bit.
sahilmgandhi 18:6a4db94011d3 13296 * | | |0 = No threshold control event with TK3.
sahilmgandhi 18:6a4db94011d3 13297 * | | |1 = Threshold control event occurs with TK3.
sahilmgandhi 18:6a4db94011d3 13298 * |[12] |TKIF4 |TK4 Interrupt Flag
sahilmgandhi 18:6a4db94011d3 13299 * | | |This bit will be cleared by writing a "1" to this bit.
sahilmgandhi 18:6a4db94011d3 13300 * | | |0 = No threshold control event with TK4.
sahilmgandhi 18:6a4db94011d3 13301 * | | |1 = Threshold control event occurs with TK4.
sahilmgandhi 18:6a4db94011d3 13302 * |[13] |TKIF5 |TK5 Interrupt Flag
sahilmgandhi 18:6a4db94011d3 13303 * | | |This bit will be cleared by writing a "1" to this bit.
sahilmgandhi 18:6a4db94011d3 13304 * | | |0 = No threshold control event with TK5.
sahilmgandhi 18:6a4db94011d3 13305 * | | |1 = Threshold control event occurs with TK5.
sahilmgandhi 18:6a4db94011d3 13306 * |[14] |TKIF6 |TK6 Interrupt Flag
sahilmgandhi 18:6a4db94011d3 13307 * | | |This bit will be cleared by writing a "1" to this bit.
sahilmgandhi 18:6a4db94011d3 13308 * | | |0 = No threshold control event with TK6.
sahilmgandhi 18:6a4db94011d3 13309 * | | |1 = Threshold control event occurs with TK6.
sahilmgandhi 18:6a4db94011d3 13310 * |[15] |TKIF7 |TK7 Interrupt Flag
sahilmgandhi 18:6a4db94011d3 13311 * | | |This bit will be cleared by writing a "1" to this bit.
sahilmgandhi 18:6a4db94011d3 13312 * | | |0 = No threshold control event with TK7.
sahilmgandhi 18:6a4db94011d3 13313 * | | |1 = Threshold control event occurs with TK7.
sahilmgandhi 18:6a4db94011d3 13314 * |[16] |TKIF8 |TK8 Interrupt Flag
sahilmgandhi 18:6a4db94011d3 13315 * | | |This bit will be cleared by writing a "1" to this bit.
sahilmgandhi 18:6a4db94011d3 13316 * | | |0 = No threshold control event with TK8.
sahilmgandhi 18:6a4db94011d3 13317 * | | |1 = Threshold control event occurs with TK8.
sahilmgandhi 18:6a4db94011d3 13318 * |[17] |TKIF9 |TK9 Interrupt Flag
sahilmgandhi 18:6a4db94011d3 13319 * | | |This bit will be cleared by writing a "1" to this bit.
sahilmgandhi 18:6a4db94011d3 13320 * | | |0 = No threshold control event with TK9.
sahilmgandhi 18:6a4db94011d3 13321 * | | |1 = Threshold control event occurs with TK9.
sahilmgandhi 18:6a4db94011d3 13322 * |[18] |TKIF10 |TK10 Interrupt Flag
sahilmgandhi 18:6a4db94011d3 13323 * | | |This bit will be cleared by writing a "1" to this bit.
sahilmgandhi 18:6a4db94011d3 13324 * | | |0 = No threshold control event with TK10.
sahilmgandhi 18:6a4db94011d3 13325 * | | |1 = Threshold control event occurs with TK10.
sahilmgandhi 18:6a4db94011d3 13326 * |[19] |TKIF11 |TK11 Interrupt Flag
sahilmgandhi 18:6a4db94011d3 13327 * | | |This bit will be cleared by writing a "1" to this bit.
sahilmgandhi 18:6a4db94011d3 13328 * | | |0 = No threshold control event with TK11.
sahilmgandhi 18:6a4db94011d3 13329 * | | |1 = Threshold control event occurs with TK11.
sahilmgandhi 18:6a4db94011d3 13330 * |[20] |TKIF12 |TK12 Interrupt Flag
sahilmgandhi 18:6a4db94011d3 13331 * | | |This bit will be cleared by writing a "1" to this bit.
sahilmgandhi 18:6a4db94011d3 13332 * | | |0 = No threshold control event with TK12.
sahilmgandhi 18:6a4db94011d3 13333 * | | |1 = Threshold control event occurs with TK12.
sahilmgandhi 18:6a4db94011d3 13334 * |[21] |TKIF13 |TK13 Interrupt Flag
sahilmgandhi 18:6a4db94011d3 13335 * | | |This bit will be cleared by writing a "1" to this bit.
sahilmgandhi 18:6a4db94011d3 13336 * | | |0 = No threshold control event with TK13.
sahilmgandhi 18:6a4db94011d3 13337 * | | |1 = Threshold control event occurs with TK13.
sahilmgandhi 18:6a4db94011d3 13338 * |[22] |TKIF14 |TK14 Interrupt Flag
sahilmgandhi 18:6a4db94011d3 13339 * | | |This bit will be cleared by writing a "1" to this bit.
sahilmgandhi 18:6a4db94011d3 13340 * | | |0 = No threshold control event with TK14.
sahilmgandhi 18:6a4db94011d3 13341 * | | |1 = Threshold control event occurs with TK14.
sahilmgandhi 18:6a4db94011d3 13342 * |[23] |TKIF15 |TK15 Interrupt Flag
sahilmgandhi 18:6a4db94011d3 13343 * | | |This bit will be cleared by writing a "1" to this bit.
sahilmgandhi 18:6a4db94011d3 13344 * | | |0 = No threshold control event with TK15.
sahilmgandhi 18:6a4db94011d3 13345 * | | |1 = Threshold control event occurs with TK15.
sahilmgandhi 18:6a4db94011d3 13346 * |[24] |TKIF16 |TK16 Interrupt Flag
sahilmgandhi 18:6a4db94011d3 13347 * | | |This bit will be cleared by writing a "1" to this bit.
sahilmgandhi 18:6a4db94011d3 13348 * | | |0 = No threshold control event with TK16.
sahilmgandhi 18:6a4db94011d3 13349 * | | |1 = Threshold control event occurs with TK16.
sahilmgandhi 18:6a4db94011d3 13350 * @var TK_T::DAT0
sahilmgandhi 18:6a4db94011d3 13351 * Offset: 0x2C Touch Key Data Register 0
sahilmgandhi 18:6a4db94011d3 13352 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 13353 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 13354 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 13355 * |[7:0] |TKDAT0 |TK0 Sensing Result Data (Read Only)
sahilmgandhi 18:6a4db94011d3 13356 * | | |This data is invalid if TKSEN0 (TK_CTL[0]) is "0" or TKREN0 (TK_REFCTL[0]) is "1" except SCANALL (TK_REFCTL[23]) is "1".
sahilmgandhi 18:6a4db94011d3 13357 * |[15:8] |TKDAT1 |TK1 Sensing Result Data (Read Only)
sahilmgandhi 18:6a4db94011d3 13358 * | | |This data is invalid if TKSEN1 (TK_CTL[1]) is "0" or TKREN1 (TK_REFCTL[1]) is "1".
sahilmgandhi 18:6a4db94011d3 13359 * |[23:16] |TKDAT2 |TK2 Sensing Result Data (Read Only)
sahilmgandhi 18:6a4db94011d3 13360 * | | |This data is invalid if TKSEN2 (TK_CTL[2]) is "0" or TKREN2 (TK_REFCTL[2]) is "1".
sahilmgandhi 18:6a4db94011d3 13361 * |[31:24] |TKDAT3 |TK3 Sensing Result Data (Read Only)
sahilmgandhi 18:6a4db94011d3 13362 * | | |This data is invalid if TKSEN3 (TK_CTL[3]) is "0" or TKREN3 (TK_REFCTL[3]) is "1".
sahilmgandhi 18:6a4db94011d3 13363 * @var TK_T::DAT1
sahilmgandhi 18:6a4db94011d3 13364 * Offset: 0x30 Touch Key Data Register 1
sahilmgandhi 18:6a4db94011d3 13365 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 13366 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 13367 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 13368 * |[7:0] |TKDAT4 |TK0 Sensing Result Data (Read Only)
sahilmgandhi 18:6a4db94011d3 13369 * | | |This data is invalid if TKSEN4 (TK_CTL[4]) is "0" or TKREN4 (TK_REFCTL[4]) is "1".
sahilmgandhi 18:6a4db94011d3 13370 * |[15:8] |TKDAT5 |TK5 Sensing Result Data (Read Only)
sahilmgandhi 18:6a4db94011d3 13371 * | | |This data is invalid if TKSEN5 (TK_CTL[5]) is "0" or TKREN5 (TK_REFCTL[5]) is "1".
sahilmgandhi 18:6a4db94011d3 13372 * |[23:16] |TKDAT6 |TK6 Sensing Result Data (Read Only)
sahilmgandhi 18:6a4db94011d3 13373 * | | |This data is invalid if TKSEN6 (TK_CTL[6]) is "0" or TKREN6 (TK_REFCTL[6]) is "1".
sahilmgandhi 18:6a4db94011d3 13374 * |[31:24] |TKDAT7 |TK7 Sensing Result Data (Read Only)
sahilmgandhi 18:6a4db94011d3 13375 * | | |This data is invalid if TKSEN7 (TK_CTL[7]) is "0" or TKREN7 (TK_REFCTL[7]) is "1".
sahilmgandhi 18:6a4db94011d3 13376 * @var TK_T::DAT2
sahilmgandhi 18:6a4db94011d3 13377 * Offset: 0x34 Touch Key Data Register 2
sahilmgandhi 18:6a4db94011d3 13378 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 13379 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 13380 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 13381 * |[7:0] |TKDAT8 |TK8 Sensing Result Data (Read Only)
sahilmgandhi 18:6a4db94011d3 13382 * | | |This data is invalid if TKSEN8 (TK_CTL[8]) is "0" or TKREN8 (TK_REFCTL[8]) is "1".
sahilmgandhi 18:6a4db94011d3 13383 * |[15:8] |TKDAT9 |TK9 Sensing Result Data (Read Only)
sahilmgandhi 18:6a4db94011d3 13384 * | | |This data is invalid if TKSEN9 (TK_CTL[9]) is "0" or TKREN9 (TK_REFCTL[9]) is "1".
sahilmgandhi 18:6a4db94011d3 13385 * |[23:16] |TKDAT10 |TK10 Sensing Result Data (Read Only)
sahilmgandhi 18:6a4db94011d3 13386 * | | |This data is invalid if TKSEN10 (TK_CTL[10]) is "0" or TKREN10 (TK_REFCTL[10]) is "1".
sahilmgandhi 18:6a4db94011d3 13387 * |[31:24] |TKDAT11 |TK11 Sensing Result Data (Read Only)
sahilmgandhi 18:6a4db94011d3 13388 * | | |This data is invalid if TKSEN11 (TK_CTL[11]) is "0" or TKREN11 (TK_REFCTL[11]) is "1".
sahilmgandhi 18:6a4db94011d3 13389 * @var TK_T::DAT3
sahilmgandhi 18:6a4db94011d3 13390 * Offset: 0x38 Touch Key Data Register 3
sahilmgandhi 18:6a4db94011d3 13391 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 13392 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 13393 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 13394 * |[7:0] |TKDAT12 |TK12 Sensing Result Data (Read Only)
sahilmgandhi 18:6a4db94011d3 13395 * | | |This data is invalid if TKSEN12 (TK_CTL[12]) is "0" or TKREN12 (TK_REFCTL[12]) is "1".
sahilmgandhi 18:6a4db94011d3 13396 * |[15:8] |TKDAT13 |TK13 Sensing Result Data (Read Only)
sahilmgandhi 18:6a4db94011d3 13397 * | | |This data is invalid if TKSEN13 (TK_CTL[13]) is "0" or TKREN13 (TK_REFCTL[13]) is "1".
sahilmgandhi 18:6a4db94011d3 13398 * |[23:16] |TKDAT14 |TK14 Sensing Result Data (Read Only)
sahilmgandhi 18:6a4db94011d3 13399 * | | |This data is invalid if TKSEN14 (TK_CTL[14]) is "0" or TKREN14 (TK_REFCTL[14]) is "1".
sahilmgandhi 18:6a4db94011d3 13400 * |[31:24] |TKDAT15 |TK15 Sensing Result Data (Read Only)
sahilmgandhi 18:6a4db94011d3 13401 * | | |This data is invalid if TKSEN15 (TK_CTL[15]) is "0" or TKREN15 (TK_REFCTL[15]) is "1".
sahilmgandhi 18:6a4db94011d3 13402 * @var TK_T::DAT4
sahilmgandhi 18:6a4db94011d3 13403 * Offset: 0x3C Touch Key Data Register 4
sahilmgandhi 18:6a4db94011d3 13404 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 13405 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 13406 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 13407 * |[7:0] |TKDAT16 |TK16 Sensing Result Data (Read Only)
sahilmgandhi 18:6a4db94011d3 13408 * | | |This data is invalid if TKSEN16 (TK_CTL[16]) is "0" or TKREN16 (TK_REFCTL[16]) is "1".
sahilmgandhi 18:6a4db94011d3 13409 * @var TK_T::INTEN
sahilmgandhi 18:6a4db94011d3 13410 * Offset: 0x40 Touch Key Interrupt Enable Register
sahilmgandhi 18:6a4db94011d3 13411 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 13412 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 13413 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 13414 * |[0] |SCTHIEN |Touch Key Scan Complete With High/Low Threshold Control Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 13415 * | | |0 = Key scan complete with threshold control interrupt is disable.
sahilmgandhi 18:6a4db94011d3 13416 * | | |1 = Key scan complete with threshold control interrupt is enable.
sahilmgandhi 18:6a4db94011d3 13417 * |[1] |SCINTEN |Touch Key Scan Complete Interrupt Enable
sahilmgandhi 18:6a4db94011d3 13418 * | | |Bit
sahilmgandhi 18:6a4db94011d3 13419 * | | |0 = Key scan complete without threshold control interrupt is disable.
sahilmgandhi 18:6a4db94011d3 13420 * | | |1 = Key scan complete without threshold control interrupt is enable.
sahilmgandhi 18:6a4db94011d3 13421 * |[31] |THIMOD |Touch Key Threshold Interrupt Mode Select
sahilmgandhi 18:6a4db94011d3 13422 * | | |0 = Edge trigger mode.
sahilmgandhi 18:6a4db94011d3 13423 * | | |1 = Level trigger mode.
sahilmgandhi 18:6a4db94011d3 13424 * @var TK_T::TH0_1
sahilmgandhi 18:6a4db94011d3 13425 * Offset: 0x44 Touch Key TK0/TK1 Threshold Control Register
sahilmgandhi 18:6a4db94011d3 13426 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 13427 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 13428 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 13429 * |[7:0] |LTH0 |Low Threshold Of TK0
sahilmgandhi 18:6a4db94011d3 13430 * | | |Low level for TK0 threshold control.
sahilmgandhi 18:6a4db94011d3 13431 * |[15:8] |HTH0 |High Threshold Of TK0
sahilmgandhi 18:6a4db94011d3 13432 * | | |High level for TK0 threshold control.
sahilmgandhi 18:6a4db94011d3 13433 * |[23:16] |LTH1 |Low Threshold Of TK1
sahilmgandhi 18:6a4db94011d3 13434 * | | |Low level for TK1 threshold control.
sahilmgandhi 18:6a4db94011d3 13435 * |[31:24] |HTH1 |High Threshold Of TK1
sahilmgandhi 18:6a4db94011d3 13436 * | | |High level for TK1 threshold control.
sahilmgandhi 18:6a4db94011d3 13437 * @var TK_T::TH2_3
sahilmgandhi 18:6a4db94011d3 13438 * Offset: 0x48 Touch Key TK2/TK3 Threshold Control Register
sahilmgandhi 18:6a4db94011d3 13439 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 13440 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 13441 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 13442 * |[7:0] |LTH2 |Low Threshold Of TK2
sahilmgandhi 18:6a4db94011d3 13443 * | | |Low level for TK2 threshold control.
sahilmgandhi 18:6a4db94011d3 13444 * |[15:8] |HTH2 |High Threshold Of TK2
sahilmgandhi 18:6a4db94011d3 13445 * | | |High level for TK2 threshold control.
sahilmgandhi 18:6a4db94011d3 13446 * |[23:16] |LTH3 |Low Threshold Of TK3
sahilmgandhi 18:6a4db94011d3 13447 * | | |Low level for TK3 threshold control.
sahilmgandhi 18:6a4db94011d3 13448 * |[31:24] |HTH3 |High Threshold Of TK3
sahilmgandhi 18:6a4db94011d3 13449 * | | |High level for TK3 threshold control.
sahilmgandhi 18:6a4db94011d3 13450 * @var TK_T::TH4_5
sahilmgandhi 18:6a4db94011d3 13451 * Offset: 0x4C Touch Key TK4/TK5 Threshold Control Register
sahilmgandhi 18:6a4db94011d3 13452 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 13453 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 13454 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 13455 * |[7:0] |LTH4 |Low Threshold Of TK4
sahilmgandhi 18:6a4db94011d3 13456 * | | |Low level for TK4 threshold control.
sahilmgandhi 18:6a4db94011d3 13457 * |[15:8] |HTH4 |High Threshold Of TK4
sahilmgandhi 18:6a4db94011d3 13458 * | | |High level for TK4 threshold control.
sahilmgandhi 18:6a4db94011d3 13459 * |[23:16] |LTH5 |Low Threshold Of TK5
sahilmgandhi 18:6a4db94011d3 13460 * | | |Low level for TK5 threshold control.
sahilmgandhi 18:6a4db94011d3 13461 * |[31:24] |HTH5 |High Threshold Of TK5
sahilmgandhi 18:6a4db94011d3 13462 * | | |High level for TK5 threshold control.
sahilmgandhi 18:6a4db94011d3 13463 * @var TK_T::TH6_7
sahilmgandhi 18:6a4db94011d3 13464 * Offset: 0x50 Touch Key TK6/TK7 Threshold Control Register
sahilmgandhi 18:6a4db94011d3 13465 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 13466 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 13467 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 13468 * |[7:0] |LTH6 |Low Threshold Of TK6
sahilmgandhi 18:6a4db94011d3 13469 * | | |Low level for TK6 threshold control.
sahilmgandhi 18:6a4db94011d3 13470 * |[15:8] |HTH6 |High Threshold Of TK6
sahilmgandhi 18:6a4db94011d3 13471 * | | |High level for TK6 threshold control.
sahilmgandhi 18:6a4db94011d3 13472 * |[23:16] |LTH7 |Low Threshold Of TK7
sahilmgandhi 18:6a4db94011d3 13473 * | | |Low level for TK7 threshold control.
sahilmgandhi 18:6a4db94011d3 13474 * |[31:24] |HTH7 |High Threshold Of TK7
sahilmgandhi 18:6a4db94011d3 13475 * | | |High level for TK7 threshold control.
sahilmgandhi 18:6a4db94011d3 13476 * @var TK_T::TH8_9
sahilmgandhi 18:6a4db94011d3 13477 * Offset: 0x54 Touch Key TK8/TK9 Threshold Control Register
sahilmgandhi 18:6a4db94011d3 13478 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 13479 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 13480 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 13481 * |[7:0] |LTH8 |Low Threshold Of TK8
sahilmgandhi 18:6a4db94011d3 13482 * | | |Low level for TK8 threshold control.
sahilmgandhi 18:6a4db94011d3 13483 * |[15:8] |HTH8 |High Threshold Of TK8
sahilmgandhi 18:6a4db94011d3 13484 * | | |High level for TK8 threshold control.
sahilmgandhi 18:6a4db94011d3 13485 * |[23:16] |LTH9 |Low Threshold Of TK9
sahilmgandhi 18:6a4db94011d3 13486 * | | |Low level for TK9 threshold control.
sahilmgandhi 18:6a4db94011d3 13487 * |[31:24] |HTH9 |High Threshold Of TK9
sahilmgandhi 18:6a4db94011d3 13488 * | | |High level for TK9 threshold control.
sahilmgandhi 18:6a4db94011d3 13489 * @var TK_T::TH10_11
sahilmgandhi 18:6a4db94011d3 13490 * Offset: 0x58 Touch Key TK10/TK11 Threshold Control Register
sahilmgandhi 18:6a4db94011d3 13491 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 13492 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 13493 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 13494 * |[7:0] |LTH10 |Low Threshold Of TK10
sahilmgandhi 18:6a4db94011d3 13495 * | | |Low level for TK10 threshold control.
sahilmgandhi 18:6a4db94011d3 13496 * |[15:8] |HTH10 |High Threshold Of TK10
sahilmgandhi 18:6a4db94011d3 13497 * | | |High level for TK10 threshold control.
sahilmgandhi 18:6a4db94011d3 13498 * |[23:16] |LTH11 |Low Threshold Of TK11
sahilmgandhi 18:6a4db94011d3 13499 * | | |Low level for TK11 threshold control.
sahilmgandhi 18:6a4db94011d3 13500 * |[31:24] |HTH11 |High Threshold Of TK11
sahilmgandhi 18:6a4db94011d3 13501 * | | |High level for TK11 threshold control.
sahilmgandhi 18:6a4db94011d3 13502 * @var TK_T::TH12_13
sahilmgandhi 18:6a4db94011d3 13503 * Offset: 0x5C Touch Key TK12/TK13 Threshold Control Register
sahilmgandhi 18:6a4db94011d3 13504 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 13505 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 13506 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 13507 * |[7:0] |LTH12 |Low Threshold Of TK12
sahilmgandhi 18:6a4db94011d3 13508 * | | |Low level for TK12 threshold control.
sahilmgandhi 18:6a4db94011d3 13509 * |[15:8] |HTH12 |High Threshold Of TK12
sahilmgandhi 18:6a4db94011d3 13510 * | | |High level for TK12 threshold control.
sahilmgandhi 18:6a4db94011d3 13511 * |[23:16] |LTH13 |Low Threshold Of TK13
sahilmgandhi 18:6a4db94011d3 13512 * | | |Low level for TK13 threshold control.
sahilmgandhi 18:6a4db94011d3 13513 * |[31:24] |HTH13 |High Threshold Of TK13
sahilmgandhi 18:6a4db94011d3 13514 * | | |High level for TK13 threshold control.
sahilmgandhi 18:6a4db94011d3 13515 * @var TK_T::TH14_15
sahilmgandhi 18:6a4db94011d3 13516 * Offset: 0x60 Touch Key TK14/TK15 Threshold Control Register
sahilmgandhi 18:6a4db94011d3 13517 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 13518 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 13519 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 13520 * |[7:0] |LTH14 |Low Threshold Of TK14
sahilmgandhi 18:6a4db94011d3 13521 * | | |Low level for TK14 threshold control.
sahilmgandhi 18:6a4db94011d3 13522 * |[15:8] |HTH14 |High Threshold Of TK14
sahilmgandhi 18:6a4db94011d3 13523 * | | |High level for TK14 threshold control.
sahilmgandhi 18:6a4db94011d3 13524 * |[23:16] |LTH15 |Low Threshold Of TK15
sahilmgandhi 18:6a4db94011d3 13525 * | | |Low level for TK15 threshold control.
sahilmgandhi 18:6a4db94011d3 13526 * |[31:24] |HTH15 |High Threshold Of TK15
sahilmgandhi 18:6a4db94011d3 13527 * | | |High level for TK15 threshold control.
sahilmgandhi 18:6a4db94011d3 13528 * @var TK_T::TH16
sahilmgandhi 18:6a4db94011d3 13529 * Offset: 0x64 Touch Key TK16 Threshold Control Register
sahilmgandhi 18:6a4db94011d3 13530 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 13531 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 13532 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 13533 * |[7:0] |LTH16 |Low Threshold Of TK16
sahilmgandhi 18:6a4db94011d3 13534 * | | |Low level for TK16 threshold control.
sahilmgandhi 18:6a4db94011d3 13535 * |[15:8] |HTH16 |High Threshold Of TK16
sahilmgandhi 18:6a4db94011d3 13536 * | | |High level for TK16 threshold control.
sahilmgandhi 18:6a4db94011d3 13537 */
sahilmgandhi 18:6a4db94011d3 13538
sahilmgandhi 18:6a4db94011d3 13539 __IO uint32_t CTL; /* Offset: 0x00 Touch Key Scan Control Register */
sahilmgandhi 18:6a4db94011d3 13540 __IO uint32_t REFCTL; /* Offset: 0x04 Touch Key Reference Control Register */
sahilmgandhi 18:6a4db94011d3 13541 __IO uint32_t CCBDAT0; /* Offset: 0x08 Touch Key Complement Capacitor Bank Data Register 0 */
sahilmgandhi 18:6a4db94011d3 13542 __IO uint32_t CCBDAT1; /* Offset: 0x0C Touch Key Complement Capacitor Bank Data Register 1 */
sahilmgandhi 18:6a4db94011d3 13543 __IO uint32_t CCBDAT2; /* Offset: 0x10 Touch Key Complement Capacitor Bank Data Register 2 */
sahilmgandhi 18:6a4db94011d3 13544 __IO uint32_t CCBDAT3; /* Offset: 0x14 Touch Key Complement Capacitor Bank Data Register 3 */
sahilmgandhi 18:6a4db94011d3 13545 __IO uint32_t CCBDAT4; /* Offset: 0x18 Touch Key Complement Capacitor Bank Data Register 4 */
sahilmgandhi 18:6a4db94011d3 13546 __IO uint32_t IDLESEL; /* Offset: 0x1C Touch Key Idle State Control Register */
sahilmgandhi 18:6a4db94011d3 13547 __IO uint32_t POLSEL; /* Offset: 0x20 Touch Key Polarity Select Register */
sahilmgandhi 18:6a4db94011d3 13548 __IO uint32_t POLCTL; /* Offset: 0x24 Touch Key Polarity Control Register */
sahilmgandhi 18:6a4db94011d3 13549 __IO uint32_t STATUS; /* Offset: 0x28 Touch Key Status Register */
sahilmgandhi 18:6a4db94011d3 13550 __I uint32_t DAT0; /* Offset: 0x2C Touch Key Data Register 0 */
sahilmgandhi 18:6a4db94011d3 13551 __I uint32_t DAT1; /* Offset: 0x30 Touch Key Data Register 1 */
sahilmgandhi 18:6a4db94011d3 13552 __I uint32_t DAT2; /* Offset: 0x34 Touch Key Data Register 2 */
sahilmgandhi 18:6a4db94011d3 13553 __I uint32_t DAT3; /* Offset: 0x38 Touch Key Data Register 3 */
sahilmgandhi 18:6a4db94011d3 13554 __I uint32_t DAT4; /* Offset: 0x3C Touch Key Data Register 4 */
sahilmgandhi 18:6a4db94011d3 13555 __IO uint32_t INTEN; /* Offset: 0x40 Touch Key Interrupt Enable Register */
sahilmgandhi 18:6a4db94011d3 13556 __IO uint32_t TH0_1; /* Offset: 0x44 Touch Key TK0/TK1 Threshold Control Register */
sahilmgandhi 18:6a4db94011d3 13557 __IO uint32_t TH2_3; /* Offset: 0x48 Touch Key TK2/TK3 Threshold Control Register */
sahilmgandhi 18:6a4db94011d3 13558 __IO uint32_t TH4_5; /* Offset: 0x4C Touch Key TK4/TK5 Threshold Control Register */
sahilmgandhi 18:6a4db94011d3 13559 __IO uint32_t TH6_7; /* Offset: 0x50 Touch Key TK6/TK7 Threshold Control Register */
sahilmgandhi 18:6a4db94011d3 13560 __IO uint32_t TH8_9; /* Offset: 0x54 Touch Key TK8/TK9 Threshold Control Register */
sahilmgandhi 18:6a4db94011d3 13561 __IO uint32_t TH10_11; /* Offset: 0x58 Touch Key TK10/TK11 Threshold Control Register */
sahilmgandhi 18:6a4db94011d3 13562 __IO uint32_t TH12_13; /* Offset: 0x5C Touch Key TK12/TK13 Threshold Control Register */
sahilmgandhi 18:6a4db94011d3 13563 __IO uint32_t TH14_15; /* Offset: 0x60 Touch Key TK14/TK15 Threshold Control Register */
sahilmgandhi 18:6a4db94011d3 13564 __IO uint32_t TH16; /* Offset: 0x64 Touch Key TK16 Threshold Control Register */
sahilmgandhi 18:6a4db94011d3 13565
sahilmgandhi 18:6a4db94011d3 13566 } TK_T;
sahilmgandhi 18:6a4db94011d3 13567
sahilmgandhi 18:6a4db94011d3 13568
sahilmgandhi 18:6a4db94011d3 13569
sahilmgandhi 18:6a4db94011d3 13570 /**
sahilmgandhi 18:6a4db94011d3 13571 @addtogroup TK_CONST TK Bit Field Definition
sahilmgandhi 18:6a4db94011d3 13572 Constant Definitions for TK Controller
sahilmgandhi 18:6a4db94011d3 13573 @{ */
sahilmgandhi 18:6a4db94011d3 13574
sahilmgandhi 18:6a4db94011d3 13575
sahilmgandhi 18:6a4db94011d3 13576 #define TK_CTL_TKSEN0_Pos (0) /*!< TK_T::CTL: TKSEN0 Position */
sahilmgandhi 18:6a4db94011d3 13577 #define TK_CTL_TKSEN0_Msk (0x1ul << TK_CTL_TKSEN0_Pos) /*!< TK_T::CTL: TKSEN0 Mask */
sahilmgandhi 18:6a4db94011d3 13578
sahilmgandhi 18:6a4db94011d3 13579 #define TK_CTL_TKSEN1_Pos (1) /*!< TK_T::CTL: TKSEN1 Position */
sahilmgandhi 18:6a4db94011d3 13580 #define TK_CTL_TKSEN1_Msk (0x1ul << TK_CTL_TKSEN1_Pos) /*!< TK_T::CTL: TKSEN1 Mask */
sahilmgandhi 18:6a4db94011d3 13581
sahilmgandhi 18:6a4db94011d3 13582 #define TK_CTL_TKSEN2_Pos (2) /*!< TK_T::CTL: TKSEN2 Position */
sahilmgandhi 18:6a4db94011d3 13583 #define TK_CTL_TKSEN2_Msk (0x1ul << TK_CTL_TKSEN2_Pos) /*!< TK_T::CTL: TKSEN2 Mask */
sahilmgandhi 18:6a4db94011d3 13584
sahilmgandhi 18:6a4db94011d3 13585 #define TK_CTL_TKSEN3_Pos (3) /*!< TK_T::CTL: TKSEN3 Position */
sahilmgandhi 18:6a4db94011d3 13586 #define TK_CTL_TKSEN3_Msk (0x1ul << TK_CTL_TKSEN3_Pos) /*!< TK_T::CTL: TKSEN3 Mask */
sahilmgandhi 18:6a4db94011d3 13587
sahilmgandhi 18:6a4db94011d3 13588 #define TK_CTL_TKSEN4_Pos (4) /*!< TK_T::CTL: TKSEN4 Position */
sahilmgandhi 18:6a4db94011d3 13589 #define TK_CTL_TKSEN4_Msk (0x1ul << TK_CTL_TKSEN4_Pos) /*!< TK_T::CTL: TKSEN4 Mask */
sahilmgandhi 18:6a4db94011d3 13590
sahilmgandhi 18:6a4db94011d3 13591 #define TK_CTL_TKSEN5_Pos (5) /*!< TK_T::CTL: TKSEN5 Position */
sahilmgandhi 18:6a4db94011d3 13592 #define TK_CTL_TKSEN5_Msk (0x1ul << TK_CTL_TKSEN5_Pos) /*!< TK_T::CTL: TKSEN5 Mask */
sahilmgandhi 18:6a4db94011d3 13593
sahilmgandhi 18:6a4db94011d3 13594 #define TK_CTL_TKSEN6_Pos (6) /*!< TK_T::CTL: TKSEN6 Position */
sahilmgandhi 18:6a4db94011d3 13595 #define TK_CTL_TKSEN6_Msk (0x1ul << TK_CTL_TKSEN6_Pos) /*!< TK_T::CTL: TKSEN6 Mask */
sahilmgandhi 18:6a4db94011d3 13596
sahilmgandhi 18:6a4db94011d3 13597 #define TK_CTL_TKSEN7_Pos (7) /*!< TK_T::CTL: TKSEN7 Position */
sahilmgandhi 18:6a4db94011d3 13598 #define TK_CTL_TKSEN7_Msk (0x1ul << TK_CTL_TKSEN7_Pos) /*!< TK_T::CTL: TKSEN7 Mask */
sahilmgandhi 18:6a4db94011d3 13599
sahilmgandhi 18:6a4db94011d3 13600 #define TK_CTL_TKSEN8_Pos (8) /*!< TK_T::CTL: TKSEN8 Position */
sahilmgandhi 18:6a4db94011d3 13601 #define TK_CTL_TKSEN8_Msk (0x1ul << TK_CTL_TKSEN8_Pos) /*!< TK_T::CTL: TKSEN8 Mask */
sahilmgandhi 18:6a4db94011d3 13602
sahilmgandhi 18:6a4db94011d3 13603 #define TK_CTL_TKSEN9_Pos (9) /*!< TK_T::CTL: TKSEN9 Position */
sahilmgandhi 18:6a4db94011d3 13604 #define TK_CTL_TKSEN9_Msk (0x1ul << TK_CTL_TKSEN9_Pos) /*!< TK_T::CTL: TKSEN9 Mask */
sahilmgandhi 18:6a4db94011d3 13605
sahilmgandhi 18:6a4db94011d3 13606 #define TK_CTL_TKSEN10_Pos (10) /*!< TK_T::CTL: TKSEN10 Position */
sahilmgandhi 18:6a4db94011d3 13607 #define TK_CTL_TKSEN10_Msk (0x1ul << TK_CTL_TKSEN10_Pos) /*!< TK_T::CTL: TKSEN10 Mask */
sahilmgandhi 18:6a4db94011d3 13608
sahilmgandhi 18:6a4db94011d3 13609 #define TK_CTL_TKSEN11_Pos (11) /*!< TK_T::CTL: TKSEN11 Position */
sahilmgandhi 18:6a4db94011d3 13610 #define TK_CTL_TKSEN11_Msk (0x1ul << TK_CTL_TKSEN11_Pos) /*!< TK_T::CTL: TKSEN11 Mask */
sahilmgandhi 18:6a4db94011d3 13611
sahilmgandhi 18:6a4db94011d3 13612 #define TK_CTL_TKSEN12_Pos (12) /*!< TK_T::CTL: TKSEN12 Position */
sahilmgandhi 18:6a4db94011d3 13613 #define TK_CTL_TKSEN12_Msk (0x1ul << TK_CTL_TKSEN12_Pos) /*!< TK_T::CTL: TKSEN12 Mask */
sahilmgandhi 18:6a4db94011d3 13614
sahilmgandhi 18:6a4db94011d3 13615 #define TK_CTL_TKSEN13_Pos (13) /*!< TK_T::CTL: TKSEN13 Position */
sahilmgandhi 18:6a4db94011d3 13616 #define TK_CTL_TKSEN13_Msk (0x1ul << TK_CTL_TKSEN13_Pos) /*!< TK_T::CTL: TKSEN13 Mask */
sahilmgandhi 18:6a4db94011d3 13617
sahilmgandhi 18:6a4db94011d3 13618 #define TK_CTL_TKSEN14_Pos (14) /*!< TK_T::CTL: TKSEN14 Position */
sahilmgandhi 18:6a4db94011d3 13619 #define TK_CTL_TKSEN14_Msk (0x1ul << TK_CTL_TKSEN14_Pos) /*!< TK_T::CTL: TKSEN14 Mask */
sahilmgandhi 18:6a4db94011d3 13620
sahilmgandhi 18:6a4db94011d3 13621 #define TK_CTL_TKSEN15_Pos (15) /*!< TK_T::CTL: TKSEN15 Position */
sahilmgandhi 18:6a4db94011d3 13622 #define TK_CTL_TKSEN15_Msk (0x1ul << TK_CTL_TKSEN15_Pos) /*!< TK_T::CTL: TKSEN15 Mask */
sahilmgandhi 18:6a4db94011d3 13623
sahilmgandhi 18:6a4db94011d3 13624 #define TK_CTL_TKSEN16_Pos (16) /*!< TK_T::CTL: TKSEN16 Position */
sahilmgandhi 18:6a4db94011d3 13625 #define TK_CTL_TKSEN16_Msk (0x1ul << TK_CTL_TKSEN16_Pos) /*!< TK_T::CTL: TKSEN16 Mask */
sahilmgandhi 18:6a4db94011d3 13626
sahilmgandhi 18:6a4db94011d3 13627 #define TK_CTL_AVCCHSEL_Pos (20) /*!< TK_T::CTL: AVCCHSEL Position */
sahilmgandhi 18:6a4db94011d3 13628 #define TK_CTL_AVCCHSEL_Msk (0x7ul << TK_CTL_AVCCHSEL_Pos) /*!< TK_T::CTL: AVCCHSEL Mask */
sahilmgandhi 18:6a4db94011d3 13629
sahilmgandhi 18:6a4db94011d3 13630 #define TK_CTL_SCAN_Pos (24) /*!< TK_T::CTL: SCAN Position */
sahilmgandhi 18:6a4db94011d3 13631 #define TK_CTL_SCAN_Msk (0x1ul << TK_CTL_SCAN_Pos) /*!< TK_T::CTL: SCAN Mask */
sahilmgandhi 18:6a4db94011d3 13632
sahilmgandhi 18:6a4db94011d3 13633 #define TK_CTL_TMRTRGEN_Pos (25) /*!< TK_T::CTL: TMRTRGEN Position */
sahilmgandhi 18:6a4db94011d3 13634 #define TK_CTL_TMRTRGEN_Msk (0x1ul << TK_CTL_TMRTRGEN_Pos) /*!< TK_T::CTL: TMRTRGEN Mask */
sahilmgandhi 18:6a4db94011d3 13635
sahilmgandhi 18:6a4db94011d3 13636 #define TK_CTL_TKEN_Pos (31) /*!< TK_T::CTL: TKEN Position */
sahilmgandhi 18:6a4db94011d3 13637 #define TK_CTL_TKEN_Msk (0x1ul << TK_CTL_TKEN_Pos) /*!< TK_T::CTL: TKEN Mask */
sahilmgandhi 18:6a4db94011d3 13638
sahilmgandhi 18:6a4db94011d3 13639 #define TK_REFCTL_TKREN0_Pos (0) /*!< TK_T::REFCTL: TKREN0 Position */
sahilmgandhi 18:6a4db94011d3 13640 #define TK_REFCTL_TKREN0_Msk (0x1ul << TK_REFCTL_TKREN0_Pos) /*!< TK_T::REFCTL: TKREN0 Mask */
sahilmgandhi 18:6a4db94011d3 13641
sahilmgandhi 18:6a4db94011d3 13642 #define TK_REFCTL_TKREN1_Pos (1) /*!< TK_T::REFCTL: TKREN1 Position */
sahilmgandhi 18:6a4db94011d3 13643 #define TK_REFCTL_TKREN1_Msk (0x1ul << TK_REFCTL_TKREN1_Pos) /*!< TK_T::REFCTL: TKREN1 Mask */
sahilmgandhi 18:6a4db94011d3 13644
sahilmgandhi 18:6a4db94011d3 13645 #define TK_REFCTL_TKREN2_Pos (2) /*!< TK_T::REFCTL: TKREN2 Position */
sahilmgandhi 18:6a4db94011d3 13646 #define TK_REFCTL_TKREN2_Msk (0x1ul << TK_REFCTL_TKREN2_Pos) /*!< TK_T::REFCTL: TKREN2 Mask */
sahilmgandhi 18:6a4db94011d3 13647
sahilmgandhi 18:6a4db94011d3 13648 #define TK_REFCTL_TKREN3_Pos (3) /*!< TK_T::REFCTL: TKREN3 Position */
sahilmgandhi 18:6a4db94011d3 13649 #define TK_REFCTL_TKREN3_Msk (0x1ul << TK_REFCTL_TKREN3_Pos) /*!< TK_T::REFCTL: TKREN3 Mask */
sahilmgandhi 18:6a4db94011d3 13650
sahilmgandhi 18:6a4db94011d3 13651 #define TK_REFCTL_TKREN4_Pos (4) /*!< TK_T::REFCTL: TKREN4 Position */
sahilmgandhi 18:6a4db94011d3 13652 #define TK_REFCTL_TKREN4_Msk (0x1ul << TK_REFCTL_TKREN4_Pos) /*!< TK_T::REFCTL: TKREN4 Mask */
sahilmgandhi 18:6a4db94011d3 13653
sahilmgandhi 18:6a4db94011d3 13654 #define TK_REFCTL_TKREN5_Pos (5) /*!< TK_T::REFCTL: TKREN5 Position */
sahilmgandhi 18:6a4db94011d3 13655 #define TK_REFCTL_TKREN5_Msk (0x1ul << TK_REFCTL_TKREN5_Pos) /*!< TK_T::REFCTL: TKREN5 Mask */
sahilmgandhi 18:6a4db94011d3 13656
sahilmgandhi 18:6a4db94011d3 13657 #define TK_REFCTL_TKREN6_Pos (6) /*!< TK_T::REFCTL: TKREN6 Position */
sahilmgandhi 18:6a4db94011d3 13658 #define TK_REFCTL_TKREN6_Msk (0x1ul << TK_REFCTL_TKREN6_Pos) /*!< TK_T::REFCTL: TKREN6 Mask */
sahilmgandhi 18:6a4db94011d3 13659
sahilmgandhi 18:6a4db94011d3 13660 #define TK_REFCTL_TKREN7_Pos (7) /*!< TK_T::REFCTL: TKREN7 Position */
sahilmgandhi 18:6a4db94011d3 13661 #define TK_REFCTL_TKREN7_Msk (0x1ul << TK_REFCTL_TKREN7_Pos) /*!< TK_T::REFCTL: TKREN7 Mask */
sahilmgandhi 18:6a4db94011d3 13662
sahilmgandhi 18:6a4db94011d3 13663 #define TK_REFCTL_TKREN8_Pos (8) /*!< TK_T::REFCTL: TKREN8 Position */
sahilmgandhi 18:6a4db94011d3 13664 #define TK_REFCTL_TKREN8_Msk (0x1ul << TK_REFCTL_TKREN8_Pos) /*!< TK_T::REFCTL: TKREN8 Mask */
sahilmgandhi 18:6a4db94011d3 13665
sahilmgandhi 18:6a4db94011d3 13666 #define TK_REFCTL_TKREN9_Pos (9) /*!< TK_T::REFCTL: TKREN9 Position */
sahilmgandhi 18:6a4db94011d3 13667 #define TK_REFCTL_TKREN9_Msk (0x1ul << TK_REFCTL_TKREN9_Pos) /*!< TK_T::REFCTL: TKREN9 Mask */
sahilmgandhi 18:6a4db94011d3 13668
sahilmgandhi 18:6a4db94011d3 13669 #define TK_REFCTL_TKREN10_Pos (10) /*!< TK_T::REFCTL: TKREN10 Position */
sahilmgandhi 18:6a4db94011d3 13670 #define TK_REFCTL_TKREN10_Msk (0x1ul << TK_REFCTL_TKREN10_Pos) /*!< TK_T::REFCTL: TKREN10 Mask */
sahilmgandhi 18:6a4db94011d3 13671
sahilmgandhi 18:6a4db94011d3 13672 #define TK_REFCTL_TKREN11_Pos (11) /*!< TK_T::REFCTL: TKREN11 Position */
sahilmgandhi 18:6a4db94011d3 13673 #define TK_REFCTL_TKREN11_Msk (0x1ul << TK_REFCTL_TKREN11_Pos) /*!< TK_T::REFCTL: TKREN11 Mask */
sahilmgandhi 18:6a4db94011d3 13674
sahilmgandhi 18:6a4db94011d3 13675 #define TK_REFCTL_TKREN12_Pos (12) /*!< TK_T::REFCTL: TKREN12 Position */
sahilmgandhi 18:6a4db94011d3 13676 #define TK_REFCTL_TKREN12_Msk (0x1ul << TK_REFCTL_TKREN12_Pos) /*!< TK_T::REFCTL: TKREN12 Mask */
sahilmgandhi 18:6a4db94011d3 13677
sahilmgandhi 18:6a4db94011d3 13678 #define TK_REFCTL_TKREN13_Pos (13) /*!< TK_T::REFCTL: TKREN13 Position */
sahilmgandhi 18:6a4db94011d3 13679 #define TK_REFCTL_TKREN13_Msk (0x1ul << TK_REFCTL_TKREN13_Pos) /*!< TK_T::REFCTL: TKREN13 Mask */
sahilmgandhi 18:6a4db94011d3 13680
sahilmgandhi 18:6a4db94011d3 13681 #define TK_REFCTL_TKREN14_Pos (14) /*!< TK_T::REFCTL: TKREN14 Position */
sahilmgandhi 18:6a4db94011d3 13682 #define TK_REFCTL_TKREN14_Msk (0x1ul << TK_REFCTL_TKREN14_Pos) /*!< TK_T::REFCTL: TKREN14 Mask */
sahilmgandhi 18:6a4db94011d3 13683
sahilmgandhi 18:6a4db94011d3 13684 #define TK_REFCTL_TKREN15_Pos (15) /*!< TK_T::REFCTL: TKREN15 Position */
sahilmgandhi 18:6a4db94011d3 13685 #define TK_REFCTL_TKREN15_Msk (0x1ul << TK_REFCTL_TKREN15_Pos) /*!< TK_T::REFCTL: TKREN15 Mask */
sahilmgandhi 18:6a4db94011d3 13686
sahilmgandhi 18:6a4db94011d3 13687 #define TK_REFCTL_TKREN16_Pos (16) /*!< TK_T::REFCTL: TKREN16 Position */
sahilmgandhi 18:6a4db94011d3 13688 #define TK_REFCTL_TKREN16_Msk (0x1ul << TK_REFCTL_TKREN16_Pos) /*!< TK_T::REFCTL: TKREN16 Mask */
sahilmgandhi 18:6a4db94011d3 13689
sahilmgandhi 18:6a4db94011d3 13690 #define TK_REFCTL_SCANALL_Pos (23) /*!< TK_T::REFCTL: SCANALL Position */
sahilmgandhi 18:6a4db94011d3 13691 #define TK_REFCTL_SCANALL_Msk (0x1ul << TK_REFCTL_SCANALL_Pos) /*!< TK_T::REFCTL: SCANALL Mask */
sahilmgandhi 18:6a4db94011d3 13692
sahilmgandhi 18:6a4db94011d3 13693 #define TK_REFCTL_SENTCTL_Pos (24) /*!< TK_T::REFCTL: SENTCTL Position */
sahilmgandhi 18:6a4db94011d3 13694 #define TK_REFCTL_SENTCTL_Msk (0x3ul << TK_REFCTL_SENTCTL_Pos) /*!< TK_T::REFCTL: SENTCTL Mask */
sahilmgandhi 18:6a4db94011d3 13695
sahilmgandhi 18:6a4db94011d3 13696 #define TK_REFCTL_SENPTCTL_Pos (28) /*!< TK_T::REFCTL: SENPTCTL Position */
sahilmgandhi 18:6a4db94011d3 13697 #define TK_REFCTL_SENPTCTL_Msk (0x3ul << TK_REFCTL_SENPTCTL_Pos) /*!< TK_T::REFCTL: SENPTCTL Mask */
sahilmgandhi 18:6a4db94011d3 13698
sahilmgandhi 18:6a4db94011d3 13699 #define TK_CCBDAT0_CCBDAT0_Pos (0) /*!< TK_T::CCBDAT0: CCBDAT0 Position */
sahilmgandhi 18:6a4db94011d3 13700 #define TK_CCBDAT0_CCBDAT0_Msk (0xfful << TK_CCBDAT0_CCBDAT0_Pos) /*!< TK_T::CCBDAT0: CCBDAT0 Mask */
sahilmgandhi 18:6a4db94011d3 13701
sahilmgandhi 18:6a4db94011d3 13702 #define TK_CCBDAT0_CCBDAT1_Pos (8) /*!< TK_T::CCBDAT0: CCBDAT1 Position */
sahilmgandhi 18:6a4db94011d3 13703 #define TK_CCBDAT0_CCBDAT1_Msk (0xfful << TK_CCBDAT0_CCBDAT1_Pos) /*!< TK_T::CCBDAT0: CCBDAT1 Mask */
sahilmgandhi 18:6a4db94011d3 13704
sahilmgandhi 18:6a4db94011d3 13705 #define TK_CCBDAT0_CCBDAT2_Pos (16) /*!< TK_T::CCBDAT0: CCBDAT2 Position */
sahilmgandhi 18:6a4db94011d3 13706 #define TK_CCBDAT0_CCBDAT2_Msk (0xfful << TK_CCBDAT0_CCBDAT2_Pos) /*!< TK_T::CCBDAT0: CCBDAT2 Mask */
sahilmgandhi 18:6a4db94011d3 13707
sahilmgandhi 18:6a4db94011d3 13708 #define TK_CCBDAT0_CCBDAT3_Pos (24) /*!< TK_T::CCBDAT0: CCBDAT3 Position */
sahilmgandhi 18:6a4db94011d3 13709 #define TK_CCBDAT0_CCBDAT3_Msk (0xfful << TK_CCBDAT0_CCBDAT3_Pos) /*!< TK_T::CCBDAT0: CCBDAT3 Mask */
sahilmgandhi 18:6a4db94011d3 13710
sahilmgandhi 18:6a4db94011d3 13711 #define TK_CCBDAT1_CCBDAT4_Pos (0) /*!< TK_T::CCBDAT1: CCBDAT4 Position */
sahilmgandhi 18:6a4db94011d3 13712 #define TK_CCBDAT1_CCBDAT4_Msk (0xfful << TK_CCBDAT1_CCBDAT4_Pos) /*!< TK_T::CCBDAT1: CCBDAT4 Mask */
sahilmgandhi 18:6a4db94011d3 13713
sahilmgandhi 18:6a4db94011d3 13714 #define TK_CCBDAT1_CCBDAT5_Pos (8) /*!< TK_T::CCBDAT1: CCBDAT5 Position */
sahilmgandhi 18:6a4db94011d3 13715 #define TK_CCBDAT1_CCBDAT5_Msk (0xfful << TK_CCBDAT1_CCBDAT5_Pos) /*!< TK_T::CCBDAT1: CCBDAT5 Mask */
sahilmgandhi 18:6a4db94011d3 13716
sahilmgandhi 18:6a4db94011d3 13717 #define TK_CCBDAT1_CCBDAT6_Pos (16) /*!< TK_T::CCBDAT1: CCBDAT6 Position */
sahilmgandhi 18:6a4db94011d3 13718 #define TK_CCBDAT1_CCBDAT6_Msk (0xfful << TK_CCBDAT1_CCBDAT6_Pos) /*!< TK_T::CCBDAT1: CCBDAT6 Mask */
sahilmgandhi 18:6a4db94011d3 13719
sahilmgandhi 18:6a4db94011d3 13720 #define TK_CCBDAT1_CCBDAT7_Pos (24) /*!< TK_T::CCBDAT1: CCBDAT7 Position */
sahilmgandhi 18:6a4db94011d3 13721 #define TK_CCBDAT1_CCBDAT7_Msk (0xfful << TK_CCBDAT1_CCBDAT7_Pos) /*!< TK_T::CCBDAT1: CCBDAT7 Mask */
sahilmgandhi 18:6a4db94011d3 13722
sahilmgandhi 18:6a4db94011d3 13723 #define TK_CCBDAT2_CCBDAT8_Pos (0) /*!< TK_T::CCBDAT2: CCBDAT8 Position */
sahilmgandhi 18:6a4db94011d3 13724 #define TK_CCBDAT2_CCBDAT8_Msk (0xfful << TK_CCBDAT2_CCBDAT8_Pos) /*!< TK_T::CCBDAT2: CCBDAT8 Mask */
sahilmgandhi 18:6a4db94011d3 13725
sahilmgandhi 18:6a4db94011d3 13726 #define TK_CCBDAT2_CCBDAT9_Pos (8) /*!< TK_T::CCBDAT2: CCBDAT9 Position */
sahilmgandhi 18:6a4db94011d3 13727 #define TK_CCBDAT2_CCBDAT9_Msk (0xfful << TK_CCBDAT2_CCBDAT9_Pos) /*!< TK_T::CCBDAT2: CCBDAT9 Mask */
sahilmgandhi 18:6a4db94011d3 13728
sahilmgandhi 18:6a4db94011d3 13729 #define TK_CCBDAT2_CCBDAT10_Pos (16) /*!< TK_T::CCBDAT2: CCBDAT10 Position */
sahilmgandhi 18:6a4db94011d3 13730 #define TK_CCBDAT2_CCBDAT10_Msk (0xfful << TK_CCBDAT2_CCBDAT10_Pos) /*!< TK_T::CCBDAT2: CCBDAT10 Mask */
sahilmgandhi 18:6a4db94011d3 13731
sahilmgandhi 18:6a4db94011d3 13732 #define TK_CCBDAT2_CCBDAT11_Pos (24) /*!< TK_T::CCBDAT2: CCBDAT11 Position */
sahilmgandhi 18:6a4db94011d3 13733 #define TK_CCBDAT2_CCBDAT11_Msk (0xfful << TK_CCBDAT2_CCBDAT11_Pos) /*!< TK_T::CCBDAT2: CCBDAT11 Mask */
sahilmgandhi 18:6a4db94011d3 13734
sahilmgandhi 18:6a4db94011d3 13735 #define TK_CCBDAT3_CCBDAT12_Pos (0) /*!< TK_T::CCBDAT3: CCBDAT12 Position */
sahilmgandhi 18:6a4db94011d3 13736 #define TK_CCBDAT3_CCBDAT12_Msk (0xfful << TK_CCBDAT3_CCBDAT12_Pos) /*!< TK_T::CCBDAT3: CCBDAT12 Mask */
sahilmgandhi 18:6a4db94011d3 13737
sahilmgandhi 18:6a4db94011d3 13738 #define TK_CCBDAT3_CCBDAT13_Pos (8) /*!< TK_T::CCBDAT3: CCBDAT13 Position */
sahilmgandhi 18:6a4db94011d3 13739 #define TK_CCBDAT3_CCBDAT13_Msk (0xfful << TK_CCBDAT3_CCBDAT13_Pos) /*!< TK_T::CCBDAT3: CCBDAT13 Mask */
sahilmgandhi 18:6a4db94011d3 13740
sahilmgandhi 18:6a4db94011d3 13741 #define TK_CCBDAT3_CCBDAT14_Pos (16) /*!< TK_T::CCBDAT3: CCBDAT14 Position */
sahilmgandhi 18:6a4db94011d3 13742 #define TK_CCBDAT3_CCBDAT14_Msk (0xfful << TK_CCBDAT3_CCBDAT14_Pos) /*!< TK_T::CCBDAT3: CCBDAT14 Mask */
sahilmgandhi 18:6a4db94011d3 13743
sahilmgandhi 18:6a4db94011d3 13744 #define TK_CCBDAT3_CCBDAT15_Pos (24) /*!< TK_T::CCBDAT3: CCBDAT15 Position */
sahilmgandhi 18:6a4db94011d3 13745 #define TK_CCBDAT3_CCBDAT15_Msk (0xfful << TK_CCBDAT3_CCBDAT15_Pos) /*!< TK_T::CCBDAT3: CCBDAT15 Mask */
sahilmgandhi 18:6a4db94011d3 13746
sahilmgandhi 18:6a4db94011d3 13747 #define TK_CCBDAT4_CCBDAT16_Pos (0) /*!< TK_T::CCBDAT4: CCBDAT16 Position */
sahilmgandhi 18:6a4db94011d3 13748 #define TK_CCBDAT4_CCBDAT16_Msk (0xfful << TK_CCBDAT4_CCBDAT16_Pos) /*!< TK_T::CCBDAT4: CCBDAT16 Mask */
sahilmgandhi 18:6a4db94011d3 13749
sahilmgandhi 18:6a4db94011d3 13750 #define TK_CCBDAT4_REFCBDAT_Pos (24) /*!< TK_T::CCBDAT4: REFCBDAT Position */
sahilmgandhi 18:6a4db94011d3 13751 #define TK_CCBDAT4_REFCBDAT_Msk (0xfful << TK_CCBDAT4_REFCBDAT_Pos) /*!< TK_T::CCBDAT4: REFCBDAT Mask */
sahilmgandhi 18:6a4db94011d3 13752
sahilmgandhi 18:6a4db94011d3 13753 #define TK_IDLESEL_IDLS_Pos (0) /*!< TK_T::IDLESEL: IDLS Position */
sahilmgandhi 18:6a4db94011d3 13754 #define TK_IDLESEL_IDLS_Msk (0xfffffffful << TK_IDLESEL_IDLS_Pos) /*!< TK_T::IDLESEL: IDLS Mask */
sahilmgandhi 18:6a4db94011d3 13755
sahilmgandhi 18:6a4db94011d3 13756 #define TK_IDLESEL_IDLSn_Pos (0) /*!< TK_T::IDLESEL: IDLSn Position */
sahilmgandhi 18:6a4db94011d3 13757 #define TK_IDLESEL_IDLSn_Msk (0x3ul << TK_IDLESEL_IDLSn_Pos) /*!< TK_T::IDLESEL: IDLSn Mask */
sahilmgandhi 18:6a4db94011d3 13758
sahilmgandhi 18:6a4db94011d3 13759 #define TK_POLSEL_POLSEL_Pos (0) /*!< TK_T::POLSEL: POLSEL Position */
sahilmgandhi 18:6a4db94011d3 13760 #define TK_POLSEL_POLSEL_Msk (0xfffffffful << TK_POLSEL_POLSEL_Pos) /*!< TK_T::POLSEL: POLSEL Mask */
sahilmgandhi 18:6a4db94011d3 13761
sahilmgandhi 18:6a4db94011d3 13762 #define TK_POLSEL_POLSELn_Pos (0) /*!< TK_T::POLSEL: POLSELn Position */
sahilmgandhi 18:6a4db94011d3 13763 #define TK_POLSEL_POLSELn_Msk (0x3ul << TK_POLSEL_POLSELn_Pos) /*!< TK_T::POLSEL: POLSELn Mask */
sahilmgandhi 18:6a4db94011d3 13764
sahilmgandhi 18:6a4db94011d3 13765 #define TK_POLCTL_IDLS16_Pos (0) /*!< TK_T::POLCTL: IDLS16 Position */
sahilmgandhi 18:6a4db94011d3 13766 #define TK_POLCTL_IDLS16_Msk (0x3ul << TK_POLCTL_IDLS16_Pos) /*!< TK_T::POLCTL: IDLS16 Mask */
sahilmgandhi 18:6a4db94011d3 13767
sahilmgandhi 18:6a4db94011d3 13768 #define TK_POLCTL_POLSEL16_Pos (2) /*!< TK_T::POLCTL: POLSEL16 Position */
sahilmgandhi 18:6a4db94011d3 13769 #define TK_POLCTL_POLSEL16_Msk (0x3ul << TK_POLCTL_POLSEL16_Pos) /*!< TK_T::POLCTL: POLSEL16 Mask */
sahilmgandhi 18:6a4db94011d3 13770
sahilmgandhi 18:6a4db94011d3 13771 #define TK_POLCTL_CBPOLSEL_Pos (4) /*!< TK_T::POLCTL: CBPOLSEL Position */
sahilmgandhi 18:6a4db94011d3 13772 #define TK_POLCTL_CBPOLSEL_Msk (0x3ul << TK_POLCTL_CBPOLSEL_Pos) /*!< TK_T::POLCTL: CBPOLSEL Mask */
sahilmgandhi 18:6a4db94011d3 13773
sahilmgandhi 18:6a4db94011d3 13774 #define TK_POLCTL_POLEN0_Pos (8) /*!< TK_T::POLCTL: POLEN0 Position */
sahilmgandhi 18:6a4db94011d3 13775 #define TK_POLCTL_POLEN0_Msk (0x1ul << TK_POLCTL_POLEN0_Pos) /*!< TK_T::POLCTL: POLEN0 Mask */
sahilmgandhi 18:6a4db94011d3 13776
sahilmgandhi 18:6a4db94011d3 13777 #define TK_POLCTL_POLEN1_Pos (9) /*!< TK_T::POLCTL: POLEN1 Position */
sahilmgandhi 18:6a4db94011d3 13778 #define TK_POLCTL_POLEN1_Msk (0x1ul << TK_POLCTL_POLEN1_Pos) /*!< TK_T::POLCTL: POLEN1 Mask */
sahilmgandhi 18:6a4db94011d3 13779
sahilmgandhi 18:6a4db94011d3 13780 #define TK_POLCTL_POLEN2_Pos (10) /*!< TK_T::POLCTL: POLEN2 Position */
sahilmgandhi 18:6a4db94011d3 13781 #define TK_POLCTL_POLEN2_Msk (0x1ul << TK_POLCTL_POLEN2_Pos) /*!< TK_T::POLCTL: POLEN2 Mask */
sahilmgandhi 18:6a4db94011d3 13782
sahilmgandhi 18:6a4db94011d3 13783 #define TK_POLCTL_POLEN3_Pos (11) /*!< TK_T::POLCTL: POLEN3 Position */
sahilmgandhi 18:6a4db94011d3 13784 #define TK_POLCTL_POLEN3_Msk (0x1ul << TK_POLCTL_POLEN3_Pos) /*!< TK_T::POLCTL: POLEN3 Mask */
sahilmgandhi 18:6a4db94011d3 13785
sahilmgandhi 18:6a4db94011d3 13786 #define TK_POLCTL_POLEN4_Pos (12) /*!< TK_T::POLCTL: POLEN4 Position */
sahilmgandhi 18:6a4db94011d3 13787 #define TK_POLCTL_POLEN4_Msk (0x1ul << TK_POLCTL_POLEN4_Pos) /*!< TK_T::POLCTL: POLEN4 Mask */
sahilmgandhi 18:6a4db94011d3 13788
sahilmgandhi 18:6a4db94011d3 13789 #define TK_POLCTL_POLEN5_Pos (13) /*!< TK_T::POLCTL: POLEN5 Position */
sahilmgandhi 18:6a4db94011d3 13790 #define TK_POLCTL_POLEN5_Msk (0x1ul << TK_POLCTL_POLEN5_Pos) /*!< TK_T::POLCTL: POLEN5 Mask */
sahilmgandhi 18:6a4db94011d3 13791
sahilmgandhi 18:6a4db94011d3 13792 #define TK_POLCTL_POLEN6_Pos (14) /*!< TK_T::POLCTL: POLEN6 Position */
sahilmgandhi 18:6a4db94011d3 13793 #define TK_POLCTL_POLEN6_Msk (0x1ul << TK_POLCTL_POLEN6_Pos) /*!< TK_T::POLCTL: POLEN6 Mask */
sahilmgandhi 18:6a4db94011d3 13794
sahilmgandhi 18:6a4db94011d3 13795 #define TK_POLCTL_POLEN7_Pos (15) /*!< TK_T::POLCTL: POLEN7 Position */
sahilmgandhi 18:6a4db94011d3 13796 #define TK_POLCTL_POLEN7_Msk (0x1ul << TK_POLCTL_POLEN7_Pos) /*!< TK_T::POLCTL: POLEN7 Mask */
sahilmgandhi 18:6a4db94011d3 13797
sahilmgandhi 18:6a4db94011d3 13798 #define TK_POLCTL_POLEN8_Pos (16) /*!< TK_T::POLCTL: POLEN8 Position */
sahilmgandhi 18:6a4db94011d3 13799 #define TK_POLCTL_POLEN8_Msk (0x1ul << TK_POLCTL_POLEN8_Pos) /*!< TK_T::POLCTL: POLEN8 Mask */
sahilmgandhi 18:6a4db94011d3 13800
sahilmgandhi 18:6a4db94011d3 13801 #define TK_POLCTL_POLEN9_Pos (17) /*!< TK_T::POLCTL: POLEN9 Position */
sahilmgandhi 18:6a4db94011d3 13802 #define TK_POLCTL_POLEN9_Msk (0x1ul << TK_POLCTL_POLEN9_Pos) /*!< TK_T::POLCTL: POLEN9 Mask */
sahilmgandhi 18:6a4db94011d3 13803
sahilmgandhi 18:6a4db94011d3 13804 #define TK_POLCTL_POLEN10_Pos (18) /*!< TK_T::POLCTL: POLEN10 Position */
sahilmgandhi 18:6a4db94011d3 13805 #define TK_POLCTL_POLEN10_Msk (0x1ul << TK_POLCTL_POLEN10_Pos) /*!< TK_T::POLCTL: POLEN10 Mask */
sahilmgandhi 18:6a4db94011d3 13806
sahilmgandhi 18:6a4db94011d3 13807 #define TK_POLCTL_POLEN11_Pos (19) /*!< TK_T::POLCTL: POLEN11 Position */
sahilmgandhi 18:6a4db94011d3 13808 #define TK_POLCTL_POLEN11_Msk (0x1ul << TK_POLCTL_POLEN11_Pos) /*!< TK_T::POLCTL: POLEN11 Mask */
sahilmgandhi 18:6a4db94011d3 13809
sahilmgandhi 18:6a4db94011d3 13810 #define TK_POLCTL_POLEN12_Pos (20) /*!< TK_T::POLCTL: POLEN12 Position */
sahilmgandhi 18:6a4db94011d3 13811 #define TK_POLCTL_POLEN12_Msk (0x1ul << TK_POLCTL_POLEN12_Pos) /*!< TK_T::POLCTL: POLEN12 Mask */
sahilmgandhi 18:6a4db94011d3 13812
sahilmgandhi 18:6a4db94011d3 13813 #define TK_POLCTL_POLEN13_Pos (21) /*!< TK_T::POLCTL: POLEN13 Position */
sahilmgandhi 18:6a4db94011d3 13814 #define TK_POLCTL_POLEN13_Msk (0x1ul << TK_POLCTL_POLEN13_Pos) /*!< TK_T::POLCTL: POLEN13 Mask */
sahilmgandhi 18:6a4db94011d3 13815
sahilmgandhi 18:6a4db94011d3 13816 #define TK_POLCTL_POLEN14_Pos (22) /*!< TK_T::POLCTL: POLEN14 Position */
sahilmgandhi 18:6a4db94011d3 13817 #define TK_POLCTL_POLEN14_Msk (0x1ul << TK_POLCTL_POLEN14_Pos) /*!< TK_T::POLCTL: POLEN14 Mask */
sahilmgandhi 18:6a4db94011d3 13818
sahilmgandhi 18:6a4db94011d3 13819 #define TK_POLCTL_POLEN15_Pos (23) /*!< TK_T::POLCTL: POLEN15 Position */
sahilmgandhi 18:6a4db94011d3 13820 #define TK_POLCTL_POLEN15_Msk (0x1ul << TK_POLCTL_POLEN15_Pos) /*!< TK_T::POLCTL: POLEN15 Mask */
sahilmgandhi 18:6a4db94011d3 13821
sahilmgandhi 18:6a4db94011d3 13822 #define TK_POLCTL_POLEN16_Pos (24) /*!< TK_T::POLCTL: POLEN16 Position */
sahilmgandhi 18:6a4db94011d3 13823 #define TK_POLCTL_POLEN16_Msk (0x1ul << TK_POLCTL_POLEN16_Pos) /*!< TK_T::POLCTL: POLEN16 Mask */
sahilmgandhi 18:6a4db94011d3 13824
sahilmgandhi 18:6a4db94011d3 13825 #define TK_POLCTL_SPOTINIT_Pos (31) /*!< TK_T::POLCTL: SPOTINIT Position */
sahilmgandhi 18:6a4db94011d3 13826 #define TK_POLCTL_SPOTINIT_Msk (0x1ul << TK_POLCTL_SPOTINIT_Pos) /*!< TK_T::POLCTL: SPOTINIT Mask */
sahilmgandhi 18:6a4db94011d3 13827
sahilmgandhi 18:6a4db94011d3 13828 #define TK_STATUS_BUSY_Pos (0) /*!< TK_T::STATUS: BUSY Position */
sahilmgandhi 18:6a4db94011d3 13829 #define TK_STATUS_BUSY_Msk (0x1ul << TK_STATUS_BUSY_Pos) /*!< TK_T::STATUS: BUSY Mask */
sahilmgandhi 18:6a4db94011d3 13830
sahilmgandhi 18:6a4db94011d3 13831 #define TK_STATUS_SCIF_Pos (1) /*!< TK_T::STATUS: SCIF Position */
sahilmgandhi 18:6a4db94011d3 13832 #define TK_STATUS_SCIF_Msk (0x1ul << TK_STATUS_SCIF_Pos) /*!< TK_T::STATUS: SCIF Mask */
sahilmgandhi 18:6a4db94011d3 13833
sahilmgandhi 18:6a4db94011d3 13834 #define TK_STATUS_TKIF0_Pos (8) /*!< TK_T::STATUS: TKIF0 Position */
sahilmgandhi 18:6a4db94011d3 13835 #define TK_STATUS_TKIF0_Msk (0x1ul << TK_STATUS_TKIF0_Pos) /*!< TK_T::STATUS: TKIF0 Mask */
sahilmgandhi 18:6a4db94011d3 13836
sahilmgandhi 18:6a4db94011d3 13837 #define TK_STATUS_TKIF1_Pos (9) /*!< TK_T::STATUS: TKIF1 Position */
sahilmgandhi 18:6a4db94011d3 13838 #define TK_STATUS_TKIF1_Msk (0x1ul << TK_STATUS_TKIF1_Pos) /*!< TK_T::STATUS: TKIF1 Mask */
sahilmgandhi 18:6a4db94011d3 13839
sahilmgandhi 18:6a4db94011d3 13840 #define TK_STATUS_TKIF2_Pos (10) /*!< TK_T::STATUS: TKIF2 Position */
sahilmgandhi 18:6a4db94011d3 13841 #define TK_STATUS_TKIF2_Msk (0x1ul << TK_STATUS_TKIF2_Pos) /*!< TK_T::STATUS: TKIF2 Mask */
sahilmgandhi 18:6a4db94011d3 13842
sahilmgandhi 18:6a4db94011d3 13843 #define TK_STATUS_TKIF3_Pos (11) /*!< TK_T::STATUS: TKIF3 Position */
sahilmgandhi 18:6a4db94011d3 13844 #define TK_STATUS_TKIF3_Msk (0x1ul << TK_STATUS_TKIF3_Pos) /*!< TK_T::STATUS: TKIF3 Mask */
sahilmgandhi 18:6a4db94011d3 13845
sahilmgandhi 18:6a4db94011d3 13846 #define TK_STATUS_TKIF4_Pos (12) /*!< TK_T::STATUS: TKIF4 Position */
sahilmgandhi 18:6a4db94011d3 13847 #define TK_STATUS_TKIF4_Msk (0x1ul << TK_STATUS_TKIF4_Pos) /*!< TK_T::STATUS: TKIF4 Mask */
sahilmgandhi 18:6a4db94011d3 13848
sahilmgandhi 18:6a4db94011d3 13849 #define TK_STATUS_TKIF5_Pos (13) /*!< TK_T::STATUS: TKIF5 Position */
sahilmgandhi 18:6a4db94011d3 13850 #define TK_STATUS_TKIF5_Msk (0x1ul << TK_STATUS_TKIF5_Pos) /*!< TK_T::STATUS: TKIF5 Mask */
sahilmgandhi 18:6a4db94011d3 13851
sahilmgandhi 18:6a4db94011d3 13852 #define TK_STATUS_TKIF6_Pos (14) /*!< TK_T::STATUS: TKIF6 Position */
sahilmgandhi 18:6a4db94011d3 13853 #define TK_STATUS_TKIF6_Msk (0x1ul << TK_STATUS_TKIF6_Pos) /*!< TK_T::STATUS: TKIF6 Mask */
sahilmgandhi 18:6a4db94011d3 13854
sahilmgandhi 18:6a4db94011d3 13855 #define TK_STATUS_TKIF7_Pos (15) /*!< TK_T::STATUS: TKIF7 Position */
sahilmgandhi 18:6a4db94011d3 13856 #define TK_STATUS_TKIF7_Msk (0x1ul << TK_STATUS_TKIF7_Pos) /*!< TK_T::STATUS: TKIF7 Mask */
sahilmgandhi 18:6a4db94011d3 13857
sahilmgandhi 18:6a4db94011d3 13858 #define TK_STATUS_TKIF8_Pos (16) /*!< TK_T::STATUS: TKIF8 Position */
sahilmgandhi 18:6a4db94011d3 13859 #define TK_STATUS_TKIF8_Msk (0x1ul << TK_STATUS_TKIF8_Pos) /*!< TK_T::STATUS: TKIF8 Mask */
sahilmgandhi 18:6a4db94011d3 13860
sahilmgandhi 18:6a4db94011d3 13861 #define TK_STATUS_TKIF9_Pos (17) /*!< TK_T::STATUS: TKIF9 Position */
sahilmgandhi 18:6a4db94011d3 13862 #define TK_STATUS_TKIF9_Msk (0x1ul << TK_STATUS_TKIF9_Pos) /*!< TK_T::STATUS: TKIF9 Mask */
sahilmgandhi 18:6a4db94011d3 13863
sahilmgandhi 18:6a4db94011d3 13864 #define TK_STATUS_TKIF10_Pos (18) /*!< TK_T::STATUS: TKIF10 Position */
sahilmgandhi 18:6a4db94011d3 13865 #define TK_STATUS_TKIF10_Msk (0x1ul << TK_STATUS_TKIF10_Pos) /*!< TK_T::STATUS: TKIF10 Mask */
sahilmgandhi 18:6a4db94011d3 13866
sahilmgandhi 18:6a4db94011d3 13867 #define TK_STATUS_TKIF11_Pos (19) /*!< TK_T::STATUS: TKIF11 Position */
sahilmgandhi 18:6a4db94011d3 13868 #define TK_STATUS_TKIF11_Msk (0x1ul << TK_STATUS_TKIF11_Pos) /*!< TK_T::STATUS: TKIF11 Mask */
sahilmgandhi 18:6a4db94011d3 13869
sahilmgandhi 18:6a4db94011d3 13870 #define TK_STATUS_TKIF12_Pos (20) /*!< TK_T::STATUS: TKIF12 Position */
sahilmgandhi 18:6a4db94011d3 13871 #define TK_STATUS_TKIF12_Msk (0x1ul << TK_STATUS_TKIF12_Pos) /*!< TK_T::STATUS: TKIF12 Mask */
sahilmgandhi 18:6a4db94011d3 13872
sahilmgandhi 18:6a4db94011d3 13873 #define TK_STATUS_TKIF13_Pos (21) /*!< TK_T::STATUS: TKIF13 Position */
sahilmgandhi 18:6a4db94011d3 13874 #define TK_STATUS_TKIF13_Msk (0x1ul << TK_STATUS_TKIF13_Pos) /*!< TK_T::STATUS: TKIF13 Mask */
sahilmgandhi 18:6a4db94011d3 13875
sahilmgandhi 18:6a4db94011d3 13876 #define TK_STATUS_TKIF14_Pos (22) /*!< TK_T::STATUS: TKIF14 Position */
sahilmgandhi 18:6a4db94011d3 13877 #define TK_STATUS_TKIF14_Msk (0x1ul << TK_STATUS_TKIF14_Pos) /*!< TK_T::STATUS: TKIF14 Mask */
sahilmgandhi 18:6a4db94011d3 13878
sahilmgandhi 18:6a4db94011d3 13879 #define TK_STATUS_TKIF15_Pos (23) /*!< TK_T::STATUS: TKIF15 Position */
sahilmgandhi 18:6a4db94011d3 13880 #define TK_STATUS_TKIF15_Msk (0x1ul << TK_STATUS_TKIF15_Pos) /*!< TK_T::STATUS: TKIF15 Mask */
sahilmgandhi 18:6a4db94011d3 13881
sahilmgandhi 18:6a4db94011d3 13882 #define TK_STATUS_TKIF16_Pos (24) /*!< TK_T::STATUS: TKIF16 Position */
sahilmgandhi 18:6a4db94011d3 13883 #define TK_STATUS_TKIF16_Msk (0x1ul << TK_STATUS_TKIF16_Pos) /*!< TK_T::STATUS: TKIF16 Mask */
sahilmgandhi 18:6a4db94011d3 13884
sahilmgandhi 18:6a4db94011d3 13885 #define TK_DAT0_TKDAT0_Pos (0) /*!< TK_T::DAT0: TKDAT0 Position */
sahilmgandhi 18:6a4db94011d3 13886 #define TK_DAT0_TKDAT0_Msk (0xfful << TK_DAT0_TKDAT0_Pos) /*!< TK_T::DAT0: TKDAT0 Mask */
sahilmgandhi 18:6a4db94011d3 13887
sahilmgandhi 18:6a4db94011d3 13888 #define TK_DAT0_TKDAT1_Pos (8) /*!< TK_T::DAT0: TKDAT1 Position */
sahilmgandhi 18:6a4db94011d3 13889 #define TK_DAT0_TKDAT1_Msk (0xfful << TK_DAT0_TKDAT1_Pos) /*!< TK_T::DAT0: TKDAT1 Mask */
sahilmgandhi 18:6a4db94011d3 13890
sahilmgandhi 18:6a4db94011d3 13891 #define TK_DAT0_TKDAT2_Pos (16) /*!< TK_T::DAT0: TKDAT2 Position */
sahilmgandhi 18:6a4db94011d3 13892 #define TK_DAT0_TKDAT2_Msk (0xfful << TK_DAT0_TKDAT2_Pos) /*!< TK_T::DAT0: TKDAT2 Mask */
sahilmgandhi 18:6a4db94011d3 13893
sahilmgandhi 18:6a4db94011d3 13894 #define TK_DAT0_TKDAT3_Pos (24) /*!< TK_T::DAT0: TKDAT3 Position */
sahilmgandhi 18:6a4db94011d3 13895 #define TK_DAT0_TKDAT3_Msk (0xfful << TK_DAT0_TKDAT3_Pos) /*!< TK_T::DAT0: TKDAT3 Mask */
sahilmgandhi 18:6a4db94011d3 13896
sahilmgandhi 18:6a4db94011d3 13897 #define TK_DAT1_TKDAT4_Pos (0) /*!< TK_T::DAT1: TKDAT4 Position */
sahilmgandhi 18:6a4db94011d3 13898 #define TK_DAT1_TKDAT4_Msk (0xfful << TK_DAT1_TKDAT4_Pos) /*!< TK_T::DAT1: TKDAT4 Mask */
sahilmgandhi 18:6a4db94011d3 13899
sahilmgandhi 18:6a4db94011d3 13900 #define TK_DAT1_TKDAT5_Pos (8) /*!< TK_T::DAT1: TKDAT5 Position */
sahilmgandhi 18:6a4db94011d3 13901 #define TK_DAT1_TKDAT5_Msk (0xfful << TK_DAT1_TKDAT5_Pos) /*!< TK_T::DAT1: TKDAT5 Mask */
sahilmgandhi 18:6a4db94011d3 13902
sahilmgandhi 18:6a4db94011d3 13903 #define TK_DAT1_TKDAT6_Pos (16) /*!< TK_T::DAT1: TKDAT6 Position */
sahilmgandhi 18:6a4db94011d3 13904 #define TK_DAT1_TKDAT6_Msk (0xfful << TK_DAT1_TKDAT6_Pos) /*!< TK_T::DAT1: TKDAT6 Mask */
sahilmgandhi 18:6a4db94011d3 13905
sahilmgandhi 18:6a4db94011d3 13906 #define TK_DAT1_TKDAT7_Pos (24) /*!< TK_T::DAT1: TKDAT7 Position */
sahilmgandhi 18:6a4db94011d3 13907 #define TK_DAT1_TKDAT7_Msk (0xfful << TK_DAT1_TKDAT7_Pos) /*!< TK_T::DAT1: TKDAT7 Mask */
sahilmgandhi 18:6a4db94011d3 13908
sahilmgandhi 18:6a4db94011d3 13909 #define TK_DAT2_TKDAT8_Pos (0) /*!< TK_T::DAT2: TKDAT8 Position */
sahilmgandhi 18:6a4db94011d3 13910 #define TK_DAT2_TKDAT8_Msk (0xfful << TK_DAT2_TKDAT8_Pos) /*!< TK_T::DAT2: TKDAT8 Mask */
sahilmgandhi 18:6a4db94011d3 13911
sahilmgandhi 18:6a4db94011d3 13912 #define TK_DAT2_TKDAT9_Pos (8) /*!< TK_T::DAT2: TKDAT9 Position */
sahilmgandhi 18:6a4db94011d3 13913 #define TK_DAT2_TKDAT9_Msk (0xfful << TK_DAT2_TKDAT9_Pos) /*!< TK_T::DAT2: TKDAT9 Mask */
sahilmgandhi 18:6a4db94011d3 13914
sahilmgandhi 18:6a4db94011d3 13915 #define TK_DAT2_TKDAT10_Pos (16) /*!< TK_T::DAT2: TKDAT10 Position */
sahilmgandhi 18:6a4db94011d3 13916 #define TK_DAT2_TKDAT10_Msk (0xfful << TK_DAT2_TKDAT10_Pos) /*!< TK_T::DAT2: TKDAT10 Mask */
sahilmgandhi 18:6a4db94011d3 13917
sahilmgandhi 18:6a4db94011d3 13918 #define TK_DAT2_TKDAT11_Pos (24) /*!< TK_T::DAT2: TKDAT11 Position */
sahilmgandhi 18:6a4db94011d3 13919 #define TK_DAT2_TKDAT11_Msk (0xfful << TK_DAT2_TKDAT11_Pos) /*!< TK_T::DAT2: TKDAT11 Mask */
sahilmgandhi 18:6a4db94011d3 13920
sahilmgandhi 18:6a4db94011d3 13921 #define TK_DAT3_TKDAT12_Pos (0) /*!< TK_T::DAT3: TKDAT12 Position */
sahilmgandhi 18:6a4db94011d3 13922 #define TK_DAT3_TKDAT12_Msk (0xfful << TK_DAT3_TKDAT12_Pos) /*!< TK_T::DAT3: TKDAT12 Mask */
sahilmgandhi 18:6a4db94011d3 13923
sahilmgandhi 18:6a4db94011d3 13924 #define TK_DAT3_TKDAT13_Pos (8) /*!< TK_T::DAT3: TKDAT13 Position */
sahilmgandhi 18:6a4db94011d3 13925 #define TK_DAT3_TKDAT13_Msk (0xfful << TK_DAT3_TKDAT13_Pos) /*!< TK_T::DAT3: TKDAT13 Mask */
sahilmgandhi 18:6a4db94011d3 13926
sahilmgandhi 18:6a4db94011d3 13927 #define TK_DAT3_TKDAT14_Pos (16) /*!< TK_T::DAT3: TKDAT14 Position */
sahilmgandhi 18:6a4db94011d3 13928 #define TK_DAT3_TKDAT14_Msk (0xfful << TK_DAT3_TKDAT14_Pos) /*!< TK_T::DAT3: TKDAT14 Mask */
sahilmgandhi 18:6a4db94011d3 13929
sahilmgandhi 18:6a4db94011d3 13930 #define TK_DAT3_TKDAT15_Pos (24) /*!< TK_T::DAT3: TKDAT15 Position */
sahilmgandhi 18:6a4db94011d3 13931 #define TK_DAT3_TKDAT15_Msk (0xfful << TK_DAT3_TKDAT15_Pos) /*!< TK_T::DAT3: TKDAT15 Mask */
sahilmgandhi 18:6a4db94011d3 13932
sahilmgandhi 18:6a4db94011d3 13933 #define TK_DAT4_TKDAT16_Pos (0) /*!< TK_T::DAT4: TKDAT16 Position */
sahilmgandhi 18:6a4db94011d3 13934 #define TK_DAT4_TKDAT16_Msk (0xfful << TK_DAT4_TKDAT16_Pos) /*!< TK_T::DAT4: TKDAT16 Mask */
sahilmgandhi 18:6a4db94011d3 13935
sahilmgandhi 18:6a4db94011d3 13936 #define TK_INTEN_SCTHIEN_Pos (0) /*!< TK_T::INTEN: SCTHIEN Position */
sahilmgandhi 18:6a4db94011d3 13937 #define TK_INTEN_SCTHIEN_Msk (0x1ul << TK_INTEN_SCTHIEN_Pos) /*!< TK_T::INTEN: SCTHIEN Mask */
sahilmgandhi 18:6a4db94011d3 13938
sahilmgandhi 18:6a4db94011d3 13939 #define TK_INTEN_SCINTEN_Pos (1) /*!< TK_T::INTEN: SCINTEN Position */
sahilmgandhi 18:6a4db94011d3 13940 #define TK_INTEN_SCINTEN_Msk (0x1ul << TK_INTEN_SCINTEN_Pos) /*!< TK_T::INTEN: SCINTEN Mask */
sahilmgandhi 18:6a4db94011d3 13941
sahilmgandhi 18:6a4db94011d3 13942 #define TK_INTEN_THIMOD_Pos (31) /*!< TK_T::INTEN: THIMOD Position */
sahilmgandhi 18:6a4db94011d3 13943 #define TK_INTEN_THIMOD_Msk (0x1ul << TK_INTEN_THIMOD_Pos) /*!< TK_T::INTEN: THIMOD Mask */
sahilmgandhi 18:6a4db94011d3 13944
sahilmgandhi 18:6a4db94011d3 13945 #define TK_TH0_1_LTH0_Pos (0) /*!< TK_T::TH0_1: LTH0 Position */
sahilmgandhi 18:6a4db94011d3 13946 #define TK_TH0_1_LTH0_Msk (0xfful << TK_TH0_1_LTH0_Pos) /*!< TK_T::TH0_1: LTH0 Mask */
sahilmgandhi 18:6a4db94011d3 13947
sahilmgandhi 18:6a4db94011d3 13948 #define TK_TH0_1_HTH0_Pos (8) /*!< TK_T::TH0_1: HTH0 Position */
sahilmgandhi 18:6a4db94011d3 13949 #define TK_TH0_1_HTH0_Msk (0xfful << TK_TH0_1_HTH0_Pos) /*!< TK_T::TH0_1: HTH0 Mask */
sahilmgandhi 18:6a4db94011d3 13950
sahilmgandhi 18:6a4db94011d3 13951 #define TK_TH0_1_LTH1_Pos (16) /*!< TK_T::TH0_1: LTH1 Position */
sahilmgandhi 18:6a4db94011d3 13952 #define TK_TH0_1_LTH1_Msk (0xfful << TK_TH0_1_LTH1_Pos) /*!< TK_T::TH0_1: LTH1 Mask */
sahilmgandhi 18:6a4db94011d3 13953
sahilmgandhi 18:6a4db94011d3 13954 #define TK_TH0_1_HTH1_Pos (24) /*!< TK_T::TH0_1: HTH1 Position */
sahilmgandhi 18:6a4db94011d3 13955 #define TK_TH0_1_HTH1_Msk (0xfful << TK_TH0_1_HTH1_Pos) /*!< TK_T::TH0_1: HTH1 Mask */
sahilmgandhi 18:6a4db94011d3 13956
sahilmgandhi 18:6a4db94011d3 13957 #define TK_TH2_3_LTH2_Pos (0) /*!< TK_T::TH2_3: LTH2 Position */
sahilmgandhi 18:6a4db94011d3 13958 #define TK_TH2_3_LTH2_Msk (0xfful << TK_TH2_3_LTH2_Pos) /*!< TK_T::TH2_3: LTH2 Mask */
sahilmgandhi 18:6a4db94011d3 13959
sahilmgandhi 18:6a4db94011d3 13960 #define TK_TH2_3_HTH2_Pos (8) /*!< TK_T::TH2_3: HTH2 Position */
sahilmgandhi 18:6a4db94011d3 13961 #define TK_TH2_3_HTH2_Msk (0xfful << TK_TH2_3_HTH2_Pos) /*!< TK_T::TH2_3: HTH2 Mask */
sahilmgandhi 18:6a4db94011d3 13962
sahilmgandhi 18:6a4db94011d3 13963 #define TK_TH2_3_LTH3_Pos (16) /*!< TK_T::TH2_3: LTH3 Position */
sahilmgandhi 18:6a4db94011d3 13964 #define TK_TH2_3_LTH3_Msk (0xfful << TK_TH2_3_LTH3_Pos) /*!< TK_T::TH2_3: LTH3 Mask */
sahilmgandhi 18:6a4db94011d3 13965
sahilmgandhi 18:6a4db94011d3 13966 #define TK_TH2_3_HTH3_Pos (24) /*!< TK_T::TH2_3: HTH3 Position */
sahilmgandhi 18:6a4db94011d3 13967 #define TK_TH2_3_HTH3_Msk (0xfful << TK_TH2_3_HTH3_Pos) /*!< TK_T::TH2_3: HTH3 Mask */
sahilmgandhi 18:6a4db94011d3 13968
sahilmgandhi 18:6a4db94011d3 13969 #define TK_TH4_5_LTH4_Pos (0) /*!< TK_T::TH4_5: LTH4 Position */
sahilmgandhi 18:6a4db94011d3 13970 #define TK_TH4_5_LTH4_Msk (0xfful << TK_TH4_5_LTH4_Pos) /*!< TK_T::TH4_5: LTH4 Mask */
sahilmgandhi 18:6a4db94011d3 13971
sahilmgandhi 18:6a4db94011d3 13972 #define TK_TH4_5_HTH4_Pos (8) /*!< TK_T::TH4_5: HTH4 Position */
sahilmgandhi 18:6a4db94011d3 13973 #define TK_TH4_5_HTH4_Msk (0xfful << TK_TH4_5_HTH4_Pos) /*!< TK_T::TH4_5: HTH4 Mask */
sahilmgandhi 18:6a4db94011d3 13974
sahilmgandhi 18:6a4db94011d3 13975 #define TK_TH4_5_LTH5_Pos (16) /*!< TK_T::TH4_5: LTH5 Position */
sahilmgandhi 18:6a4db94011d3 13976 #define TK_TH4_5_LTH5_Msk (0xfful << TK_TH4_5_LTH5_Pos) /*!< TK_T::TH4_5: LTH5 Mask */
sahilmgandhi 18:6a4db94011d3 13977
sahilmgandhi 18:6a4db94011d3 13978 #define TK_TH4_5_HTH5_Pos (24) /*!< TK_T::TH4_5: HTH5 Position */
sahilmgandhi 18:6a4db94011d3 13979 #define TK_TH4_5_HTH5_Msk (0xfful << TK_TH4_5_HTH5_Pos) /*!< TK_T::TH4_5: HTH5 Mask */
sahilmgandhi 18:6a4db94011d3 13980
sahilmgandhi 18:6a4db94011d3 13981 #define TK_TH6_7_LTH6_Pos (0) /*!< TK_T::TH6_7: LTH6 Position */
sahilmgandhi 18:6a4db94011d3 13982 #define TK_TH6_7_LTH6_Msk (0xfful << TK_TH6_7_LTH6_Pos) /*!< TK_T::TH6_7: LTH6 Mask */
sahilmgandhi 18:6a4db94011d3 13983
sahilmgandhi 18:6a4db94011d3 13984 #define TK_TH6_7_HTH6_Pos (8) /*!< TK_T::TH6_7: HTH6 Position */
sahilmgandhi 18:6a4db94011d3 13985 #define TK_TH6_7_HTH6_Msk (0xfful << TK_TH6_7_HTH6_Pos) /*!< TK_T::TH6_7: HTH6 Mask */
sahilmgandhi 18:6a4db94011d3 13986
sahilmgandhi 18:6a4db94011d3 13987 #define TK_TH6_7_LTH7_Pos (16) /*!< TK_T::TH6_7: LTH7 Position */
sahilmgandhi 18:6a4db94011d3 13988 #define TK_TH6_7_LTH7_Msk (0xfful << TK_TH6_7_LTH7_Pos) /*!< TK_T::TH6_7: LTH7 Mask */
sahilmgandhi 18:6a4db94011d3 13989
sahilmgandhi 18:6a4db94011d3 13990 #define TK_TH6_7_HTH7_Pos (24) /*!< TK_T::TH6_7: HTH7 Position */
sahilmgandhi 18:6a4db94011d3 13991 #define TK_TH6_7_HTH7_Msk (0xfful << TK_TH6_7_HTH7_Pos) /*!< TK_T::TH6_7: HTH7 Mask */
sahilmgandhi 18:6a4db94011d3 13992
sahilmgandhi 18:6a4db94011d3 13993 #define TK_TH8_9_LTH8_Pos (0) /*!< TK_T::TH8_9: LTH8 Position */
sahilmgandhi 18:6a4db94011d3 13994 #define TK_TH8_9_LTH8_Msk (0xfful << TK_TH8_9_LTH8_Pos) /*!< TK_T::TH8_9: LTH8 Mask */
sahilmgandhi 18:6a4db94011d3 13995
sahilmgandhi 18:6a4db94011d3 13996 #define TK_TH8_9_HTH8_Pos (8) /*!< TK_T::TH8_9: HTH8 Position */
sahilmgandhi 18:6a4db94011d3 13997 #define TK_TH8_9_HTH8_Msk (0xfful << TK_TH8_9_HTH8_Pos) /*!< TK_T::TH8_9: HTH8 Mask */
sahilmgandhi 18:6a4db94011d3 13998
sahilmgandhi 18:6a4db94011d3 13999 #define TK_TH8_9_LTH9_Pos (16) /*!< TK_T::TH8_9: LTH9 Position */
sahilmgandhi 18:6a4db94011d3 14000 #define TK_TH8_9_LTH9_Msk (0xfful << TK_TH8_9_LTH9_Pos) /*!< TK_T::TH8_9: LTH9 Mask */
sahilmgandhi 18:6a4db94011d3 14001
sahilmgandhi 18:6a4db94011d3 14002 #define TK_TH8_9_HTH9_Pos (24) /*!< TK_T::TH8_9: HTH9 Position */
sahilmgandhi 18:6a4db94011d3 14003 #define TK_TH8_9_HTH9_Msk (0xfful << TK_TH8_9_HTH9_Pos) /*!< TK_T::TH8_9: HTH9 Mask */
sahilmgandhi 18:6a4db94011d3 14004
sahilmgandhi 18:6a4db94011d3 14005 #define TK_TH10_11_LTH10_Pos (0) /*!< TK_T::TH10_11: LTH10 Position */
sahilmgandhi 18:6a4db94011d3 14006 #define TK_TH10_11_LTH10_Msk (0xfful << TK_TH10_11_LTH10_Pos) /*!< TK_T::TH10_11: LTH10 Mask */
sahilmgandhi 18:6a4db94011d3 14007
sahilmgandhi 18:6a4db94011d3 14008 #define TK_TH10_11_HTH10_Pos (8) /*!< TK_T::TH10_11: HTH10 Position */
sahilmgandhi 18:6a4db94011d3 14009 #define TK_TH10_11_HTH10_Msk (0xfful << TK_TH10_11_HTH10_Pos) /*!< TK_T::TH10_11: HTH10 Mask */
sahilmgandhi 18:6a4db94011d3 14010
sahilmgandhi 18:6a4db94011d3 14011 #define TK_TH10_11_LTH11_Pos (16) /*!< TK_T::TH10_11: LTH11 Position */
sahilmgandhi 18:6a4db94011d3 14012 #define TK_TH10_11_LTH11_Msk (0xfful << TK_TH10_11_LTH11_Pos) /*!< TK_T::TH10_11: LTH11 Mask */
sahilmgandhi 18:6a4db94011d3 14013
sahilmgandhi 18:6a4db94011d3 14014 #define TK_TH10_11_HTH11_Pos (24) /*!< TK_T::TH10_11: HTH11 Position */
sahilmgandhi 18:6a4db94011d3 14015 #define TK_TH10_11_HTH11_Msk (0xfful << TK_TH10_11_HTH11_Pos) /*!< TK_T::TH10_11: HTH11 Mask */
sahilmgandhi 18:6a4db94011d3 14016
sahilmgandhi 18:6a4db94011d3 14017 #define TK_TH12_13_LTH12_Pos (0) /*!< TK_T::TH12_13: LTH12 Position */
sahilmgandhi 18:6a4db94011d3 14018 #define TK_TH12_13_LTH12_Msk (0xfful << TK_TH12_13_LTH12_Pos) /*!< TK_T::TH12_13: LTH12 Mask */
sahilmgandhi 18:6a4db94011d3 14019
sahilmgandhi 18:6a4db94011d3 14020 #define TK_TH12_13_HTH12_Pos (8) /*!< TK_T::TH12_13: HTH12 Position */
sahilmgandhi 18:6a4db94011d3 14021 #define TK_TH12_13_HTH12_Msk (0xfful << TK_TH12_13_HTH12_Pos) /*!< TK_T::TH12_13: HTH12 Mask */
sahilmgandhi 18:6a4db94011d3 14022
sahilmgandhi 18:6a4db94011d3 14023 #define TK_TH12_13_LTH13_Pos (16) /*!< TK_T::TH12_13: LTH13 Position */
sahilmgandhi 18:6a4db94011d3 14024 #define TK_TH12_13_LTH13_Msk (0xfful << TK_TH12_13_LTH13_Pos) /*!< TK_T::TH12_13: LTH13 Mask */
sahilmgandhi 18:6a4db94011d3 14025
sahilmgandhi 18:6a4db94011d3 14026 #define TK_TH12_13_HTH13_Pos (24) /*!< TK_T::TH12_13: HTH13 Position */
sahilmgandhi 18:6a4db94011d3 14027 #define TK_TH12_13_HTH13_Msk (0xfful << TK_TH12_13_HTH13_Pos) /*!< TK_T::TH12_13: HTH13 Mask */
sahilmgandhi 18:6a4db94011d3 14028
sahilmgandhi 18:6a4db94011d3 14029 #define TK_TH14_15_LTH14_Pos (0) /*!< TK_T::TH14_15: LTH14 Position */
sahilmgandhi 18:6a4db94011d3 14030 #define TK_TH14_15_LTH14_Msk (0xfful << TK_TH14_15_LTH14_Pos) /*!< TK_T::TH14_15: LTH14 Mask */
sahilmgandhi 18:6a4db94011d3 14031
sahilmgandhi 18:6a4db94011d3 14032 #define TK_TH14_15_HTH14_Pos (8) /*!< TK_T::TH14_15: HTH14 Position */
sahilmgandhi 18:6a4db94011d3 14033 #define TK_TH14_15_HTH14_Msk (0xfful << TK_TH14_15_HTH14_Pos) /*!< TK_T::TH14_15: HTH14 Mask */
sahilmgandhi 18:6a4db94011d3 14034
sahilmgandhi 18:6a4db94011d3 14035 #define TK_TH14_15_LTH15_Pos (16) /*!< TK_T::TH14_15: LTH15 Position */
sahilmgandhi 18:6a4db94011d3 14036 #define TK_TH14_15_LTH15_Msk (0xfful << TK_TH14_15_LTH15_Pos) /*!< TK_T::TH14_15: LTH15 Mask */
sahilmgandhi 18:6a4db94011d3 14037
sahilmgandhi 18:6a4db94011d3 14038 #define TK_TH14_15_HTH15_Pos (24) /*!< TK_T::TH14_15: HTH15 Position */
sahilmgandhi 18:6a4db94011d3 14039 #define TK_TH14_15_HTH15_Msk (0xfful << TK_TH14_15_HTH15_Pos) /*!< TK_T::TH14_15: HTH15 Mask */
sahilmgandhi 18:6a4db94011d3 14040
sahilmgandhi 18:6a4db94011d3 14041 #define TK_TH16_LTH16_Pos (0) /*!< TK_T::TH16: LTH16 Position */
sahilmgandhi 18:6a4db94011d3 14042 #define TK_TH16_LTH16_Msk (0xfful << TK_TH16_LTH16_Pos) /*!< TK_T::TH16: LTH16 Mask */
sahilmgandhi 18:6a4db94011d3 14043
sahilmgandhi 18:6a4db94011d3 14044 #define TK_TH16_HTH16_Pos (8) /*!< TK_T::TH16: HTH16 Position */
sahilmgandhi 18:6a4db94011d3 14045 #define TK_TH16_HTH16_Msk (0xfful << TK_TH16_HTH16_Pos) /*!< TK_T::TH16: HTH16 Mask */
sahilmgandhi 18:6a4db94011d3 14046
sahilmgandhi 18:6a4db94011d3 14047 /**@}*/ /* TK_CONST */
sahilmgandhi 18:6a4db94011d3 14048 /**@}*/ /* end of TK register group */
sahilmgandhi 18:6a4db94011d3 14049
sahilmgandhi 18:6a4db94011d3 14050
sahilmgandhi 18:6a4db94011d3 14051 /*---------------------- Timer Controller -------------------------*/
sahilmgandhi 18:6a4db94011d3 14052 /**
sahilmgandhi 18:6a4db94011d3 14053 @addtogroup TMR Timer Controller(TMR)
sahilmgandhi 18:6a4db94011d3 14054 Memory Mapped Structure for TMR Controller
sahilmgandhi 18:6a4db94011d3 14055 @{ */
sahilmgandhi 18:6a4db94011d3 14056
sahilmgandhi 18:6a4db94011d3 14057
sahilmgandhi 18:6a4db94011d3 14058 typedef struct
sahilmgandhi 18:6a4db94011d3 14059 {
sahilmgandhi 18:6a4db94011d3 14060
sahilmgandhi 18:6a4db94011d3 14061
sahilmgandhi 18:6a4db94011d3 14062
sahilmgandhi 18:6a4db94011d3 14063
sahilmgandhi 18:6a4db94011d3 14064 /**
sahilmgandhi 18:6a4db94011d3 14065 * @var TIMER_T::CTL
sahilmgandhi 18:6a4db94011d3 14066 * Offset: 0x00 Timer Control and Status Register
sahilmgandhi 18:6a4db94011d3 14067 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 14068 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 14069 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 14070 * |[7:0] |PSC |Prescale Counter
sahilmgandhi 18:6a4db94011d3 14071 * | | |Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter.
sahilmgandhi 18:6a4db94011d3 14072 * | | |If this field is 0 (PSC = 0), then there is no scaling.
sahilmgandhi 18:6a4db94011d3 14073 * |[17] |WKTKEN |Wake-Up Touch-Key Scan Enable Bit
sahilmgandhi 18:6a4db94011d3 14074 * | | |If this bit is set to 1, timer time-out interrupt in Power-down mode can be triggered Touch-Key start scan.
sahilmgandhi 18:6a4db94011d3 14075 * | | |0 = Timer time-out interrupt signal trigger Touch-Key start scan Disabled.
sahilmgandhi 18:6a4db94011d3 14076 * | | |1 = Timer time-out interrupt signal trigger Touch-Key start scan Enabled.
sahilmgandhi 18:6a4db94011d3 14077 * | | |Note: This bit is only available in TIMER0_CTL.
sahilmgandhi 18:6a4db94011d3 14078 * |[18] |TRGSSEL |Trigger Source Select Bit
sahilmgandhi 18:6a4db94011d3 14079 * | | |This bit is used to select trigger source is form Timer time-out interrupt signal or capture interrupt signal.
sahilmgandhi 18:6a4db94011d3 14080 * | | |0 = Timer time-out interrupt signal is used to trigger PWM, EADC and DAC.
sahilmgandhi 18:6a4db94011d3 14081 * | | |1 = Capture interrupt signal is used to trigger PWM, EADC and DAC.
sahilmgandhi 18:6a4db94011d3 14082 * |[19] |TRGPWM |Trigger PWM Enable Bit
sahilmgandhi 18:6a4db94011d3 14083 * | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered PWM.
sahilmgandhi 18:6a4db94011d3 14084 * | | |0 = Timer interrupt trigger PWM Disabled.
sahilmgandhi 18:6a4db94011d3 14085 * | | |1 = Timer interrupt trigger PWM Enabled.
sahilmgandhi 18:6a4db94011d3 14086 * | | |Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger PWM.
sahilmgandhi 18:6a4db94011d3 14087 * | | |If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger PWM.
sahilmgandhi 18:6a4db94011d3 14088 * |[20] |TRGDAC |Trigger DAC Enable Bit
sahilmgandhi 18:6a4db94011d3 14089 * | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC.
sahilmgandhi 18:6a4db94011d3 14090 * | | |0 = Timer interrupt trigger DAC Disabled.
sahilmgandhi 18:6a4db94011d3 14091 * | | |1 = Timer interrupt trigger DAC Enabled.
sahilmgandhi 18:6a4db94011d3 14092 * | | |Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger DAC.
sahilmgandhi 18:6a4db94011d3 14093 * | | |If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger DAC.
sahilmgandhi 18:6a4db94011d3 14094 * |[21] |TRGEADC |Trigger EADC Enable Bit
sahilmgandhi 18:6a4db94011d3 14095 * | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered EADC.
sahilmgandhi 18:6a4db94011d3 14096 * | | |0 = Timer interrupt trigger EADC Disabled.
sahilmgandhi 18:6a4db94011d3 14097 * | | |1 = Timer interrupt trigger EADC Enabled.
sahilmgandhi 18:6a4db94011d3 14098 * | | |Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger EADC.
sahilmgandhi 18:6a4db94011d3 14099 * | | |If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger EADC.
sahilmgandhi 18:6a4db94011d3 14100 * |[22] |TGLPINSEL |Toggle-Output Pin Select
sahilmgandhi 18:6a4db94011d3 14101 * | | |0 = Toggle mode output to Tx_OUT (Timer Event Counter Pin).
sahilmgandhi 18:6a4db94011d3 14102 * | | |1 = Toggle mode output to Tx_EXT(Timer External Capture Pin).
sahilmgandhi 18:6a4db94011d3 14103 * |[23] |WKEN |Wake-Up Function Enable Bit
sahilmgandhi 18:6a4db94011d3 14104 * | | |If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
sahilmgandhi 18:6a4db94011d3 14105 * | | |0 = Wake-up function Disabled if timer interrupt signal generated.
sahilmgandhi 18:6a4db94011d3 14106 * | | |1 = Wake-up function Enabled if timer interrupt signal generated.
sahilmgandhi 18:6a4db94011d3 14107 * |[24] |EXTCNTEN |Event Counter Mode Enable Bit
sahilmgandhi 18:6a4db94011d3 14108 * | | |This bit is for external counting pin function enabled.
sahilmgandhi 18:6a4db94011d3 14109 * | | |0 = Event counter mode Disabled.
sahilmgandhi 18:6a4db94011d3 14110 * | | |1 = Event counter mode Enabled.
sahilmgandhi 18:6a4db94011d3 14111 * | | |Note: When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source.
sahilmgandhi 18:6a4db94011d3 14112 * |[25] |ACTSTS |Timer Active Status Bit (Read Only)
sahilmgandhi 18:6a4db94011d3 14113 * | | |This bit indicates the 24-bit up counter status.
sahilmgandhi 18:6a4db94011d3 14114 * | | |0 = 24-bit up counter is not active.
sahilmgandhi 18:6a4db94011d3 14115 * | | |1 = 24-bit up counter is active.
sahilmgandhi 18:6a4db94011d3 14116 * |[26] |RSTCNT |Timer Counter Reset Bit
sahilmgandhi 18:6a4db94011d3 14117 * | | |Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.
sahilmgandhi 18:6a4db94011d3 14118 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 14119 * | | |1 = Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit.
sahilmgandhi 18:6a4db94011d3 14120 * |[28:27] |OPMODE |Timer Counting Mode Select
sahilmgandhi 18:6a4db94011d3 14121 * | | |00 = The Timer controller is operated in One-shot mode.
sahilmgandhi 18:6a4db94011d3 14122 * | | |01 = The Timer controller is operated in Periodic mode.
sahilmgandhi 18:6a4db94011d3 14123 * | | |10 = The Timer controller is operated in Toggle-output mode.
sahilmgandhi 18:6a4db94011d3 14124 * | | |11 = The Timer controller is operated in Continuous Counting mode.
sahilmgandhi 18:6a4db94011d3 14125 * |[29] |INTEN |Timer Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 14126 * | | |0 = Timer Interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 14127 * | | |1 = Timer Interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 14128 * | | |Note: If this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
sahilmgandhi 18:6a4db94011d3 14129 * |[30] |CNTEN |Timer Counting Enable Bit
sahilmgandhi 18:6a4db94011d3 14130 * | | |0 = Stops/Suspends counting.
sahilmgandhi 18:6a4db94011d3 14131 * | | |1 = Starts counting.
sahilmgandhi 18:6a4db94011d3 14132 * | | |Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value.
sahilmgandhi 18:6a4db94011d3 14133 * | | |Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer interrupt flag TIF (TIMERx_INTSTS[0]) is generated.
sahilmgandhi 18:6a4db94011d3 14134 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable
sahilmgandhi 18:6a4db94011d3 14135 * | | |0 = ICE debug mode acknowledgement effects TIMER counting.
sahilmgandhi 18:6a4db94011d3 14136 * | | |TIMER counter will be held while CPU is held by ICE.
sahilmgandhi 18:6a4db94011d3 14137 * | | |1 = ICE debug mode acknowledgement Disabled.
sahilmgandhi 18:6a4db94011d3 14138 * | | |TIMER counter will keep going no matter CPU is held by ICE or not.
sahilmgandhi 18:6a4db94011d3 14139 * @var TIMER_T::CMP
sahilmgandhi 18:6a4db94011d3 14140 * Offset: 0x04 Timer Compare Register
sahilmgandhi 18:6a4db94011d3 14141 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 14142 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 14143 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 14144 * |[23:0] |CMPDAT |Timer Compared Value
sahilmgandhi 18:6a4db94011d3 14145 * | | |CMPDAT is a 24-bit compared value register.
sahilmgandhi 18:6a4db94011d3 14146 * | | |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.
sahilmgandhi 18:6a4db94011d3 14147 * | | |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT).
sahilmgandhi 18:6a4db94011d3 14148 * | | |Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.
sahilmgandhi 18:6a4db94011d3 14149 * | | |Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field.
sahilmgandhi 18:6a4db94011d3 14150 * | | |But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
sahilmgandhi 18:6a4db94011d3 14151 * @var TIMER_T::INTSTS
sahilmgandhi 18:6a4db94011d3 14152 * Offset: 0x08 Timer Interrupt Status Register
sahilmgandhi 18:6a4db94011d3 14153 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 14154 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 14155 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 14156 * |[0] |TIF |Timer Interrupt Flag
sahilmgandhi 18:6a4db94011d3 14157 * | | |This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.
sahilmgandhi 18:6a4db94011d3 14158 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 14159 * | | |1 = CNT value matches the CMPDAT value.
sahilmgandhi 18:6a4db94011d3 14160 * | | |Note: This bit is cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 14161 * |[1] |TWKF |Timer Wake-Up Flag
sahilmgandhi 18:6a4db94011d3 14162 * | | |This bit indicates the interrupt wake-up flag status of timer.
sahilmgandhi 18:6a4db94011d3 14163 * | | |0 = Timer does not cause CPU wake-up.
sahilmgandhi 18:6a4db94011d3 14164 * | | |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated.
sahilmgandhi 18:6a4db94011d3 14165 * | | |Note: This bit is cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 14166 * @var TIMER_T::CNT
sahilmgandhi 18:6a4db94011d3 14167 * Offset: 0x0C Timer Data Register
sahilmgandhi 18:6a4db94011d3 14168 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 14169 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 14170 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 14171 * |[23:0] |CNT |Timer Data Register
sahilmgandhi 18:6a4db94011d3 14172 * | | |This field can be reflected the internal 24-bit timer counter value or external event input counter value from Tx_CNT (x=0~3) pin.
sahilmgandhi 18:6a4db94011d3 14173 * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24- bit counter value .
sahilmgandhi 18:6a4db94011d3 14174 * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24- bit event input counter value.
sahilmgandhi 18:6a4db94011d3 14175 * @var TIMER_T::CAP
sahilmgandhi 18:6a4db94011d3 14176 * Offset: 0x10 Timer Capture Data Register
sahilmgandhi 18:6a4db94011d3 14177 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 14178 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 14179 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 14180 * |[23:0] |CAPDAT |Timer Capture Data Register
sahilmgandhi 18:6a4db94011d3 14181 * | | |When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
sahilmgandhi 18:6a4db94011d3 14182 * @var TIMER_T::EXTCTL
sahilmgandhi 18:6a4db94011d3 14183 * Offset: 0x14 Timer External Control Register
sahilmgandhi 18:6a4db94011d3 14184 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 14185 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 14186 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 14187 * |[0] |CNTPHASE |Timer External Count Phase
sahilmgandhi 18:6a4db94011d3 14188 * | | |This bit indicates the detection phase of external counting pin Tx_CNT (x= 0~3).
sahilmgandhi 18:6a4db94011d3 14189 * | | |0 = A Falling edge of external counting pin will be counted.
sahilmgandhi 18:6a4db94011d3 14190 * | | |1 = A Rising edge of external counting pin will be counted.
sahilmgandhi 18:6a4db94011d3 14191 * |[2:1] |CAPEDGE |Timer External Capture Pin Edge Detect
sahilmgandhi 18:6a4db94011d3 14192 * | | |00 = A Falling edge on Tx_EXT (x= 0~3) pin will be detected.
sahilmgandhi 18:6a4db94011d3 14193 * | | |01 = A Rising edge on Tx_EXT (x= 0~3) pin will be detected.
sahilmgandhi 18:6a4db94011d3 14194 * | | |10 = Either Rising or Falling edge on Tx_EXT (x= 0~3) pin will be detected.
sahilmgandhi 18:6a4db94011d3 14195 * | | |11 = Reserved.
sahilmgandhi 18:6a4db94011d3 14196 * |[3] |CAPEN |Timer External Capture Pin Enable
sahilmgandhi 18:6a4db94011d3 14197 * | | |This bit enables the Tx_EXT pin.
sahilmgandhi 18:6a4db94011d3 14198 * | | |0 =Tx_EXT (x= 0~3) pin Disabled.
sahilmgandhi 18:6a4db94011d3 14199 * | | |1 =Tx_EXT (x= 0~3) pin Enabled.
sahilmgandhi 18:6a4db94011d3 14200 * |[4] |CAPFUNCS |Capture Function Selection
sahilmgandhi 18:6a4db94011d3 14201 * | | |0 = External Capture Mode Enabled.
sahilmgandhi 18:6a4db94011d3 14202 * | | |1 = External Reset Mode Enabled.
sahilmgandhi 18:6a4db94011d3 14203 * | | |Note1: When CAPFUNCS is 0, transition on Tx_EXT (x= 0~3) pin is using to save the 24-bit timer counter value.
sahilmgandhi 18:6a4db94011d3 14204 * | | |Note2: When CAPFUNCS is 1, transition on Tx_EXT (x= 0~3) pin is using to reset the 24-bit timer counter value.
sahilmgandhi 18:6a4db94011d3 14205 * |[5] |CAPIEN |Timer External Capture Interrupt Enable
sahilmgandhi 18:6a4db94011d3 14206 * | | |0 = Tx_EXT (x= 0~3) pin detection Interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 14207 * | | |1 = Tx_EXT (x= 0~3) pin detection Interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 14208 * | | |Note: CAPIEN is used to enable timer external interrupt.
sahilmgandhi 18:6a4db94011d3 14209 * | | |If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1.
sahilmgandhi 18:6a4db94011d3 14210 * | | |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the Tx_EXT pin will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU.
sahilmgandhi 18:6a4db94011d3 14211 * |[6] |CAPDBEN |Timer External Capture Pin De-Bounce Enable
sahilmgandhi 18:6a4db94011d3 14212 * | | |0 = Tx_EXT (x= 0~3) pin de-bounce Disabled.
sahilmgandhi 18:6a4db94011d3 14213 * | | |1 = Tx_EXT (x= 0~3) pin de-bounce Enabled.
sahilmgandhi 18:6a4db94011d3 14214 * | | |Note: If this bit is enabled, the edge detection of Tx_EXT pin is detected with de-bounce circuit.
sahilmgandhi 18:6a4db94011d3 14215 * |[7] |CNTDBEN |Timer Counter Pin De-Bounce Enable
sahilmgandhi 18:6a4db94011d3 14216 * | | |0 = Tx_CNT (x= 0~3) pin de-bounce Disabled.
sahilmgandhi 18:6a4db94011d3 14217 * | | |1 = Tx_CNT (x= 0~3) pin de-bounce Enabled.
sahilmgandhi 18:6a4db94011d3 14218 * | | |Note: If this bit is enabled, the edge detection of Tx_CNT pin is detected with de-bounce circuit.
sahilmgandhi 18:6a4db94011d3 14219 * @var TIMER_T::EINTSTS
sahilmgandhi 18:6a4db94011d3 14220 * Offset: 0x18 Timer External Interrupt Status Register
sahilmgandhi 18:6a4db94011d3 14221 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 14222 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 14223 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 14224 * |[0] |CAPIF |Timer External Capture Interrupt Flag
sahilmgandhi 18:6a4db94011d3 14225 * | | |This bit indicates the timer external capture interrupt flag status.
sahilmgandhi 18:6a4db94011d3 14226 * | | |0 = Tx_EXT (x= 0~3) pin interrupt did not occur.
sahilmgandhi 18:6a4db94011d3 14227 * | | |1 = Tx_EXT (x= 0~3) pin interrupt occurred.
sahilmgandhi 18:6a4db94011d3 14228 * | | |Note1: This bit is cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 14229 * | | |Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT (x= 0~3) pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware.
sahilmgandhi 18:6a4db94011d3 14230 * | | |Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status.
sahilmgandhi 18:6a4db94011d3 14231 * | | |If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
sahilmgandhi 18:6a4db94011d3 14232 */
sahilmgandhi 18:6a4db94011d3 14233
sahilmgandhi 18:6a4db94011d3 14234 __IO uint32_t CTL; /* Offset: 0x00 Timer Control and Status Register */
sahilmgandhi 18:6a4db94011d3 14235 __IO uint32_t CMP; /* Offset: 0x04 Timer Compare Register */
sahilmgandhi 18:6a4db94011d3 14236 __IO uint32_t INTSTS; /* Offset: 0x08 Timer Interrupt Status Register */
sahilmgandhi 18:6a4db94011d3 14237 __I uint32_t CNT; /* Offset: 0x0C Timer Data Register */
sahilmgandhi 18:6a4db94011d3 14238 __I uint32_t CAP; /* Offset: 0x10 Timer Capture Data Register */
sahilmgandhi 18:6a4db94011d3 14239 __IO uint32_t EXTCTL; /* Offset: 0x14 Timer External Control Register */
sahilmgandhi 18:6a4db94011d3 14240 __IO uint32_t EINTSTS; /* Offset: 0x18 Timer External Interrupt Status Register */
sahilmgandhi 18:6a4db94011d3 14241
sahilmgandhi 18:6a4db94011d3 14242 } TIMER_T;
sahilmgandhi 18:6a4db94011d3 14243
sahilmgandhi 18:6a4db94011d3 14244
sahilmgandhi 18:6a4db94011d3 14245
sahilmgandhi 18:6a4db94011d3 14246 /**
sahilmgandhi 18:6a4db94011d3 14247 @addtogroup TMR_CONST TMR Bit Field Definition
sahilmgandhi 18:6a4db94011d3 14248 Constant Definitions for TMR Controller
sahilmgandhi 18:6a4db94011d3 14249 @{ */
sahilmgandhi 18:6a4db94011d3 14250
sahilmgandhi 18:6a4db94011d3 14251 #define TIMER_CTL_PSC_Pos (0) /*!< TIMER_T::CTL: PSC Position */
sahilmgandhi 18:6a4db94011d3 14252 #define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) /*!< TIMER_T::CTL: PSC Mask */
sahilmgandhi 18:6a4db94011d3 14253
sahilmgandhi 18:6a4db94011d3 14254 #define TIMER_CTL_WKTKEN_Pos (17) /*!< TIMER_T::CTL: WKTKEN Position */
sahilmgandhi 18:6a4db94011d3 14255 #define TIMER_CTL_WKTKEN_Msk (0x1ul << TIMER_CTL_WKTKEN_Pos) /*!< TIMER_T::CTL: WKTKEN Mask */
sahilmgandhi 18:6a4db94011d3 14256
sahilmgandhi 18:6a4db94011d3 14257 #define TIMER_CTL_TRGSSEL_Pos (18) /*!< TIMER_T::CTL: TRGSSEL Position */
sahilmgandhi 18:6a4db94011d3 14258 #define TIMER_CTL_TRGSSEL_Msk (0x1ul << TIMER_CTL_TRGSSEL_Pos) /*!< TIMER_T::CTL: TRGSSEL Mask */
sahilmgandhi 18:6a4db94011d3 14259
sahilmgandhi 18:6a4db94011d3 14260 #define TIMER_CTL_TRGPWM_Pos (19) /*!< TIMER_T::CTL: TRGPWM Position */
sahilmgandhi 18:6a4db94011d3 14261 #define TIMER_CTL_TRGPWM_Msk (0x1ul << TIMER_CTL_TRGPWM_Pos) /*!< TIMER_T::CTL: TRGPWM Mask */
sahilmgandhi 18:6a4db94011d3 14262
sahilmgandhi 18:6a4db94011d3 14263 #define TIMER_CTL_TRGDAC_Pos (20) /*!< TIMER_T::CTL: TRGDAC Position */
sahilmgandhi 18:6a4db94011d3 14264 #define TIMER_CTL_TRGDAC_Msk (0x1ul << TIMER_CTL_TRGDAC_Pos) /*!< TIMER_T::CTL: TRGDAC Mask */
sahilmgandhi 18:6a4db94011d3 14265
sahilmgandhi 18:6a4db94011d3 14266 #define TIMER_CTL_TRGEADC_Pos (21) /*!< TIMER_T::CTL: TRGEADC Position */
sahilmgandhi 18:6a4db94011d3 14267 #define TIMER_CTL_TRGEADC_Msk (0x1ul << TIMER_CTL_TRGEADC_Pos) /*!< TIMER_T::CTL: TRGEADC Mask */
sahilmgandhi 18:6a4db94011d3 14268
sahilmgandhi 18:6a4db94011d3 14269 #define TIMER_CTL_TGLPINSEL_Pos (22) /*!< TIMER_T::CTL: TGLPINSEL Position */
sahilmgandhi 18:6a4db94011d3 14270 #define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos) /*!< TIMER_T::CTL: TGLPINSEL Mask */
sahilmgandhi 18:6a4db94011d3 14271
sahilmgandhi 18:6a4db94011d3 14272 #define TIMER_CTL_WKEN_Pos (23) /*!< TIMER_T::CTL: WKEN Position */
sahilmgandhi 18:6a4db94011d3 14273 #define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) /*!< TIMER_T::CTL: WKEN Mask */
sahilmgandhi 18:6a4db94011d3 14274
sahilmgandhi 18:6a4db94011d3 14275 #define TIMER_CTL_EXTCNTEN_Pos (24) /*!< TIMER_T::CTL: EXTCNTEN Position */
sahilmgandhi 18:6a4db94011d3 14276 #define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) /*!< TIMER_T::CTL: EXTCNTEN Mask */
sahilmgandhi 18:6a4db94011d3 14277
sahilmgandhi 18:6a4db94011d3 14278 #define TIMER_CTL_ACTSTS_Pos (25) /*!< TIMER_T::CTL: ACTSTS Position */
sahilmgandhi 18:6a4db94011d3 14279 #define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) /*!< TIMER_T::CTL: ACTSTS Mask */
sahilmgandhi 18:6a4db94011d3 14280
sahilmgandhi 18:6a4db94011d3 14281 #define TIMER_CTL_RSTCNT_Pos (26) /*!< TIMER_T::CTL: RSTCNT Position */
sahilmgandhi 18:6a4db94011d3 14282 #define TIMER_CTL_RSTCNT_Msk (0x1ul << TIMER_CTL_RSTCNT_Pos) /*!< TIMER_T::CTL: RSTCNT Mask */
sahilmgandhi 18:6a4db94011d3 14283
sahilmgandhi 18:6a4db94011d3 14284 #define TIMER_CTL_OPMODE_Pos (27) /*!< TIMER_T::CTL: OPMODE Position */
sahilmgandhi 18:6a4db94011d3 14285 #define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) /*!< TIMER_T::CTL: OPMODE Mask */
sahilmgandhi 18:6a4db94011d3 14286
sahilmgandhi 18:6a4db94011d3 14287 #define TIMER_CTL_INTEN_Pos (29) /*!< TIMER_T::CTL: INTEN Position */
sahilmgandhi 18:6a4db94011d3 14288 #define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) /*!< TIMER_T::CTL: INTEN Mask */
sahilmgandhi 18:6a4db94011d3 14289
sahilmgandhi 18:6a4db94011d3 14290 #define TIMER_CTL_CNTEN_Pos (30) /*!< TIMER_T::CTL: CNTEN Position */
sahilmgandhi 18:6a4db94011d3 14291 #define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) /*!< TIMER_T::CTL: CNTEN Mask */
sahilmgandhi 18:6a4db94011d3 14292
sahilmgandhi 18:6a4db94011d3 14293 #define TIMER_CTL_ICEDEBUG_Pos (31) /*!< TIMER_T::CTL: ICEDEBUG Position */
sahilmgandhi 18:6a4db94011d3 14294 #define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) /*!< TIMER_T::CTL: ICEDEBUG Mask */
sahilmgandhi 18:6a4db94011d3 14295
sahilmgandhi 18:6a4db94011d3 14296 #define TIMER_CMP_CMPDAT_Pos (0) /*!< TIMER_T::CMP: CMPDAT Position */
sahilmgandhi 18:6a4db94011d3 14297 #define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) /*!< TIMER_T::CMP: CMPDAT Mask */
sahilmgandhi 18:6a4db94011d3 14298
sahilmgandhi 18:6a4db94011d3 14299 #define TIMER_INTSTS_TIF_Pos (0) /*!< TIMER_T::INTSTS: TIF Position */
sahilmgandhi 18:6a4db94011d3 14300 #define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) /*!< TIMER_T::INTSTS: TIF Mask */
sahilmgandhi 18:6a4db94011d3 14301
sahilmgandhi 18:6a4db94011d3 14302 #define TIMER_INTSTS_TWKF_Pos (1) /*!< TIMER_T::INTSTS: TWKF Position */
sahilmgandhi 18:6a4db94011d3 14303 #define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) /*!< TIMER_T::INTSTS: TWKF Mask */
sahilmgandhi 18:6a4db94011d3 14304
sahilmgandhi 18:6a4db94011d3 14305 #define TIMER_CNT_CNT_Pos (0) /*!< TIMER_T::CNT: CNT Position */
sahilmgandhi 18:6a4db94011d3 14306 #define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) /*!< TIMER_T::CNT: CNT Mask */
sahilmgandhi 18:6a4db94011d3 14307
sahilmgandhi 18:6a4db94011d3 14308 #define TIMER_CAP_CAPDAT_Pos (0) /*!< TIMER_T::CAP: CAPDAT Position */
sahilmgandhi 18:6a4db94011d3 14309 #define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) /*!< TIMER_T::CAP: CAPDAT Mask */
sahilmgandhi 18:6a4db94011d3 14310
sahilmgandhi 18:6a4db94011d3 14311 #define TIMER_EXTCTL_CNTPHASE_Pos (0) /*!< TIMER_T::EXTCTL: CNTPHASE Position */
sahilmgandhi 18:6a4db94011d3 14312 #define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) /*!< TIMER_T::EXTCTL: CNTPHASE Mask */
sahilmgandhi 18:6a4db94011d3 14313
sahilmgandhi 18:6a4db94011d3 14314 #define TIMER_EXTCTL_CAPEDGE_Pos (1) /*!< TIMER_T::EXTCTL: CAPEDGE Position */
sahilmgandhi 18:6a4db94011d3 14315 #define TIMER_EXTCTL_CAPEDGE_Msk (0x3ul << TIMER_EXTCTL_CAPEDGE_Pos) /*!< TIMER_T::EXTCTL: CAPEDGE Mask */
sahilmgandhi 18:6a4db94011d3 14316
sahilmgandhi 18:6a4db94011d3 14317 #define TIMER_EXTCTL_CAPEN_Pos (3) /*!< TIMER_T::EXTCTL: CAPEN Position */
sahilmgandhi 18:6a4db94011d3 14318 #define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) /*!< TIMER_T::EXTCTL: CAPEN Mask */
sahilmgandhi 18:6a4db94011d3 14319
sahilmgandhi 18:6a4db94011d3 14320 #define TIMER_EXTCTL_CAPFUNCS_Pos (4) /*!< TIMER_T::EXTCTL: CAPFUNCS Position */
sahilmgandhi 18:6a4db94011d3 14321 #define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< TIMER_T::EXTCTL: CAPFUNCS Mask */
sahilmgandhi 18:6a4db94011d3 14322
sahilmgandhi 18:6a4db94011d3 14323 #define TIMER_EXTCTL_CAPIEN_Pos (5) /*!< TIMER_T::EXTCTL: CAPIEN Position */
sahilmgandhi 18:6a4db94011d3 14324 #define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) /*!< TIMER_T::EXTCTL: CAPIEN Mask */
sahilmgandhi 18:6a4db94011d3 14325
sahilmgandhi 18:6a4db94011d3 14326 #define TIMER_EXTCTL_CAPDBEN_Pos (6) /*!< TIMER_T::EXTCTL: CAPDBEN Position */
sahilmgandhi 18:6a4db94011d3 14327 #define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) /*!< TIMER_T::EXTCTL: CAPDBEN Mask */
sahilmgandhi 18:6a4db94011d3 14328
sahilmgandhi 18:6a4db94011d3 14329 #define TIMER_EXTCTL_CNTDBEN_Pos (7) /*!< TIMER_T::EXTCTL: CNTDBEN Position */
sahilmgandhi 18:6a4db94011d3 14330 #define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos) /*!< TIMER_T::EXTCTL: CNTDBEN Mask */
sahilmgandhi 18:6a4db94011d3 14331
sahilmgandhi 18:6a4db94011d3 14332 #define TIMER_EINTSTS_CAPIF_Pos (0) /*!< TIMER_T::EINTSTS: CAPIF Position */
sahilmgandhi 18:6a4db94011d3 14333 #define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /*!< TIMER_T::EINTSTS: CAPIF Mask */
sahilmgandhi 18:6a4db94011d3 14334
sahilmgandhi 18:6a4db94011d3 14335 /**@}*/ /* TIMER_CONST */
sahilmgandhi 18:6a4db94011d3 14336 /**@}*/ /* end of TIMER register group */
sahilmgandhi 18:6a4db94011d3 14337
sahilmgandhi 18:6a4db94011d3 14338
sahilmgandhi 18:6a4db94011d3 14339 /*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/
sahilmgandhi 18:6a4db94011d3 14340 /**
sahilmgandhi 18:6a4db94011d3 14341 @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART)
sahilmgandhi 18:6a4db94011d3 14342 Memory Mapped Structure for UART Controller
sahilmgandhi 18:6a4db94011d3 14343 @{ */
sahilmgandhi 18:6a4db94011d3 14344
sahilmgandhi 18:6a4db94011d3 14345
sahilmgandhi 18:6a4db94011d3 14346 typedef struct
sahilmgandhi 18:6a4db94011d3 14347 {
sahilmgandhi 18:6a4db94011d3 14348
sahilmgandhi 18:6a4db94011d3 14349
sahilmgandhi 18:6a4db94011d3 14350
sahilmgandhi 18:6a4db94011d3 14351
sahilmgandhi 18:6a4db94011d3 14352 /**
sahilmgandhi 18:6a4db94011d3 14353 * @var UART_T::DAT
sahilmgandhi 18:6a4db94011d3 14354 * Offset: 0x00 UART Receive/Transmit Buffer Register
sahilmgandhi 18:6a4db94011d3 14355 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 14356 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 14357 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 14358 * |[7:0] |DAT |Receiving/Transmit Buffer
sahilmgandhi 18:6a4db94011d3 14359 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 14360 * | | |By writing one byte to this register, the data byte will be stored in transmitter FIFO.
sahilmgandhi 18:6a4db94011d3 14361 * | | |The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD.
sahilmgandhi 18:6a4db94011d3 14362 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 14363 * | | |By reading this register, the UART will return an 8-bit data received from receiving FIFO.
sahilmgandhi 18:6a4db94011d3 14364 * @var UART_T::INTEN
sahilmgandhi 18:6a4db94011d3 14365 * Offset: 0x04 UART Interrupt Enable Register
sahilmgandhi 18:6a4db94011d3 14366 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 14367 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 14368 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 14369 * |[0] |RDAIEN |Receive Data Available Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 14370 * | | |0 = Receive data available interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 14371 * | | |1 = Receive data available interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 14372 * |[1] |THREIEN |Transmit Holding Register Empty Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 14373 * | | |0 = Transmit holding register empty interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 14374 * | | |1 = Transmit holding register empty interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 14375 * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 14376 * | | |0 = Receive Line Status interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 14377 * | | |1 = Receive Line Status interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 14378 * |[3] |MODEMIEN |Modem Status Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 14379 * | | |0 = Modem status interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 14380 * | | |1 = Modem status interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 14381 * |[4] |RXTOIEN |RX Time-Out Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 14382 * | | |0 = RX time-out interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 14383 * | | |1 = RX time-out interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 14384 * |[5] |BUFERRIEN |Buffer Error Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 14385 * | | |0 = Buffer error interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 14386 * | | |1 = Buffer error interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 14387 * |[8] |LINIEN |LIN Bus Interrupt Enable Bit (Not Available In UART2/UART3)
sahilmgandhi 18:6a4db94011d3 14388 * | | |0 = LIN bus interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 14389 * | | |1 = LIN bus interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 14390 * | | |Note: This bit is used for LIN function mode.
sahilmgandhi 18:6a4db94011d3 14391 * |[9] |WKCTSIEN |nCTS Wake-Up Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 14392 * | | |0 = nCTS wake-up system function Disabled.
sahilmgandhi 18:6a4db94011d3 14393 * | | |1 = Wake-up system function Enabled, when the system is in Power-down mode, an external nCTS change will wake-up system from Power-down mode.
sahilmgandhi 18:6a4db94011d3 14394 * |[10] |WKDATIEN |Incoming Data Wake-Up Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 14395 * | | |0 = Incoming data wake-up system function Disabled.
sahilmgandhi 18:6a4db94011d3 14396 * | | |1 = Incoming data wake-up system function Enabled, when the system is in Power-down mode, incoming data will wake-up system from Power-down mode.
sahilmgandhi 18:6a4db94011d3 14397 * | | |Note: Hardware will clear this bit when the incoming data wake-up operation finishes and "system clock" work stable
sahilmgandhi 18:6a4db94011d3 14398 * |[11] |TOCNTEN |Time-Out Counter Enable Bit
sahilmgandhi 18:6a4db94011d3 14399 * | | |0 = Time-out counter Disabled.
sahilmgandhi 18:6a4db94011d3 14400 * | | |1 = Time-out counter Enabled.
sahilmgandhi 18:6a4db94011d3 14401 * |[12] |ATORTSEN |nRTS Auto-Flow Control Enable Bit
sahilmgandhi 18:6a4db94011d3 14402 * | | |0 = nRTS auto-flow control Disabled.
sahilmgandhi 18:6a4db94011d3 14403 * | | |1 = nRTS auto-flow control Enabled.
sahilmgandhi 18:6a4db94011d3 14404 * | | |Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
sahilmgandhi 18:6a4db94011d3 14405 * |[13] |ATOCTSEN |nCTS Auto-Flow Control Enable Bit
sahilmgandhi 18:6a4db94011d3 14406 * | | |0 = nCTS auto-flow control Disabled.
sahilmgandhi 18:6a4db94011d3 14407 * | | |1 = nCTS auto-flow control Enabled.
sahilmgandhi 18:6a4db94011d3 14408 * | | |Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
sahilmgandhi 18:6a4db94011d3 14409 * |[14] |TXPDMAEN |TX DMA Enable Bit
sahilmgandhi 18:6a4db94011d3 14410 * | | |This bit can enable or disable TX DMA service.
sahilmgandhi 18:6a4db94011d3 14411 * | | |0 = TX DMA Disabled.
sahilmgandhi 18:6a4db94011d3 14412 * | | |1 = TX DMA Enabled.
sahilmgandhi 18:6a4db94011d3 14413 * |[15] |RXPDMAEN |RX DMA Enable Bit
sahilmgandhi 18:6a4db94011d3 14414 * | | |This bit can enable or disable RX DMA service.
sahilmgandhi 18:6a4db94011d3 14415 * | | |0 = RX DMA Disabled.
sahilmgandhi 18:6a4db94011d3 14416 * | | |1 = RX DMA Enabled.
sahilmgandhi 18:6a4db94011d3 14417 * |[18] |ABRIEN |Auto-Baud Rate Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 14418 * | | |0 = Auto-baud rate interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 14419 * | | |1 = Auto-baud rate interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 14420 * @var UART_T::FIFO
sahilmgandhi 18:6a4db94011d3 14421 * Offset: 0x08 UART FIFO Control Register
sahilmgandhi 18:6a4db94011d3 14422 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 14423 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 14424 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 14425 * |[1] |RXRST |RX Field Software Reset
sahilmgandhi 18:6a4db94011d3 14426 * | | |When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.
sahilmgandhi 18:6a4db94011d3 14427 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 14428 * | | |1 = Reset the RX internal state machine and pointers.
sahilmgandhi 18:6a4db94011d3 14429 * | | |Note: This bit will automatically clear at least 3 UART peripheral clock cycles.
sahilmgandhi 18:6a4db94011d3 14430 * |[2] |TXRST |TX Field Software Reset
sahilmgandhi 18:6a4db94011d3 14431 * | | |When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
sahilmgandhi 18:6a4db94011d3 14432 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 14433 * | | |1 = Reset the TX internal state machine and pointers.
sahilmgandhi 18:6a4db94011d3 14434 * | | |Note: This bit will automatically clear at least 3 UART peripheral clock cycles.
sahilmgandhi 18:6a4db94011d3 14435 * |[7:4] |RFITL |RX FIFO Interrupt Trigger Level
sahilmgandhi 18:6a4db94011d3 14436 * | | |When the number of bytes in the receive FIFO equals the RFITL, the RDAIF will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
sahilmgandhi 18:6a4db94011d3 14437 * | | |0000 = RX FIFO Interrupt Trigger Level is 1 byte.
sahilmgandhi 18:6a4db94011d3 14438 * | | |0001 = RX FIFO Interrupt Trigger Level is 4 bytes.
sahilmgandhi 18:6a4db94011d3 14439 * | | |0010 = RX FIFO Interrupt Trigger Level is 8 bytes.
sahilmgandhi 18:6a4db94011d3 14440 * | | |0011 = RX FIFO Interrupt Trigger Level is 14 bytes.
sahilmgandhi 18:6a4db94011d3 14441 * | | |Others = Reserved.
sahilmgandhi 18:6a4db94011d3 14442 * |[8] |RXOFF |Receiver Disable
sahilmgandhi 18:6a4db94011d3 14443 * | | |The receiver is disabled or not (set 1 to disable receiver)
sahilmgandhi 18:6a4db94011d3 14444 * | | |0 = Receiver Enabled.
sahilmgandhi 18:6a4db94011d3 14445 * | | |1 = Receiver Disabled.
sahilmgandhi 18:6a4db94011d3 14446 * | | |Note: This bit is used for RS-485 Normal Multi-drop mode.
sahilmgandhi 18:6a4db94011d3 14447 * | | |It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
sahilmgandhi 18:6a4db94011d3 14448 * |[19:16] |RTSTRGLV |nRTS Trigger Level For Auto-Flow Control Use
sahilmgandhi 18:6a4db94011d3 14449 * | | |0000 = nRTS Trigger Level is 1 bytes.
sahilmgandhi 18:6a4db94011d3 14450 * | | |0001 = nRTS Trigger Level is 4bytes.
sahilmgandhi 18:6a4db94011d3 14451 * | | |0010 = nRTS Trigger Level is 8 bytes.
sahilmgandhi 18:6a4db94011d3 14452 * | | |0011 = nRTS Trigger Level is 14 bytes.
sahilmgandhi 18:6a4db94011d3 14453 * | | |Others = Reserved.
sahilmgandhi 18:6a4db94011d3 14454 * | | |Note: This field is used for auto nRTS flow control.
sahilmgandhi 18:6a4db94011d3 14455 * @var UART_T::LINE
sahilmgandhi 18:6a4db94011d3 14456 * Offset: 0x0C UART Line Control Register
sahilmgandhi 18:6a4db94011d3 14457 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 14458 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 14459 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 14460 * |[1:0] |WLS |Word Length Selection
sahilmgandhi 18:6a4db94011d3 14461 * | | |This field sets UART word length.
sahilmgandhi 18:6a4db94011d3 14462 * | | |00 = 5 bits.
sahilmgandhi 18:6a4db94011d3 14463 * | | |01 = 6 bits.
sahilmgandhi 18:6a4db94011d3 14464 * | | |10 = 7 bits.
sahilmgandhi 18:6a4db94011d3 14465 * | | |11 = 8 bits.
sahilmgandhi 18:6a4db94011d3 14466 * |[2] |NSB |Number Of "STOP Bit"
sahilmgandhi 18:6a4db94011d3 14467 * | | |0 = One "STOP bit" is generated in the transmitted data.
sahilmgandhi 18:6a4db94011d3 14468 * | | |1 = When select 5-bit word length, 1.5 "STOP bit" is generated in the transmitted data.
sahilmgandhi 18:6a4db94011d3 14469 * | | |When select 6-, 7- and 8-bit word length, 2 "STOP bit" is generated in the transmitted data.
sahilmgandhi 18:6a4db94011d3 14470 * |[3] |PBE |Parity Bit Enable Bit
sahilmgandhi 18:6a4db94011d3 14471 * | | |0 = No parity bit generated Disabled.
sahilmgandhi 18:6a4db94011d3 14472 * | | |1 = Parity bit generated Enabled.
sahilmgandhi 18:6a4db94011d3 14473 * | | |Note : Parity bit is generated on each outgoing character and is checked on each incoming data.
sahilmgandhi 18:6a4db94011d3 14474 * |[4] |EPE |Even Parity Enable Bit
sahilmgandhi 18:6a4db94011d3 14475 * | | |0 = Odd number of logic 1's is transmitted and checked in each word.
sahilmgandhi 18:6a4db94011d3 14476 * | | |1 = Even number of logic 1's is transmitted and checked in each word.
sahilmgandhi 18:6a4db94011d3 14477 * | | |Note:This bit has effect only when PBE (UART_LINE[3]) is set.
sahilmgandhi 18:6a4db94011d3 14478 * |[5] |SPE |Stick Parity Enable Bit
sahilmgandhi 18:6a4db94011d3 14479 * | | |0 = Stick parity Disabled.
sahilmgandhi 18:6a4db94011d3 14480 * | | |1 = Stick parity Enabled.
sahilmgandhi 18:6a4db94011d3 14481 * | | |Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0.
sahilmgandhi 18:6a4db94011d3 14482 * | | |If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
sahilmgandhi 18:6a4db94011d3 14483 * |[6] |BCB |Break Control Bit
sahilmgandhi 18:6a4db94011d3 14484 * | | |0 = Break Control Disabled.
sahilmgandhi 18:6a4db94011d3 14485 * | | |1 = Break Control Enabled.
sahilmgandhi 18:6a4db94011d3 14486 * | | |Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0).
sahilmgandhi 18:6a4db94011d3 14487 * | | |This bit acts only on TX line and has no effect on the transmitter logic.
sahilmgandhi 18:6a4db94011d3 14488 * @var UART_T::MODEM
sahilmgandhi 18:6a4db94011d3 14489 * Offset: 0x10 UART Modem Control Register
sahilmgandhi 18:6a4db94011d3 14490 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 14491 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 14492 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 14493 * |[1] |RTS |nRTS (Request-To-Send) Signal Control
sahilmgandhi 18:6a4db94011d3 14494 * | | |This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.
sahilmgandhi 18:6a4db94011d3 14495 * | | |0 = nRTS signal is active.
sahilmgandhi 18:6a4db94011d3 14496 * | | |1 = nRTS signal is inactive.
sahilmgandhi 18:6a4db94011d3 14497 * | | |Note1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.
sahilmgandhi 18:6a4db94011d3 14498 * | | |Note2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
sahilmgandhi 18:6a4db94011d3 14499 * |[9] |RTSACTLV |nRTS Pin Active Level
sahilmgandhi 18:6a4db94011d3 14500 * | | |This bit defines the active level state of nRTS pin output.
sahilmgandhi 18:6a4db94011d3 14501 * | | |0 =n RTS pin output is high level active.
sahilmgandhi 18:6a4db94011d3 14502 * | | |1 = nRTS pin output is low level active. (Default)
sahilmgandhi 18:6a4db94011d3 14503 * | | |Note1: Refer to Figure 6.21-10 and Figure 6.21-11 for UART function mode.
sahilmgandhi 18:6a4db94011d3 14504 * | | |Note2: Refer to Figure 6.21-21 and Figure 6.21-22 for RS-485 function mode.
sahilmgandhi 18:6a4db94011d3 14505 * |[13] |RTSSTS |nRTS Pin Status (Read Only)
sahilmgandhi 18:6a4db94011d3 14506 * | | |This bit mirror from nRTS pin output of voltage logic status.
sahilmgandhi 18:6a4db94011d3 14507 * | | |0 = nRTS pin output is low level voltage logic state.
sahilmgandhi 18:6a4db94011d3 14508 * | | |1 = nRTS pin output is high level voltage logic state.
sahilmgandhi 18:6a4db94011d3 14509 * @var UART_T::MODEMSTS
sahilmgandhi 18:6a4db94011d3 14510 * Offset: 0x14 UART Modem Status Register
sahilmgandhi 18:6a4db94011d3 14511 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 14512 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 14513 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 14514 * |[0] |CTSDETF |Detect nCTS State Change Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 14515 * | | |This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.
sahilmgandhi 18:6a4db94011d3 14516 * | | |0 = nCTS input has not change state.
sahilmgandhi 18:6a4db94011d3 14517 * | | |1 = nCTS input has change state.
sahilmgandhi 18:6a4db94011d3 14518 * | | |Note: This bit is read only, but can be cleared by writing "1" to it.
sahilmgandhi 18:6a4db94011d3 14519 * |[4] |CTSSTS |nCTS Pin Status (Read Only)
sahilmgandhi 18:6a4db94011d3 14520 * | | |This bit mirror from nCTS pin input of voltage logic status.
sahilmgandhi 18:6a4db94011d3 14521 * | | |0 = nCTS pin input is low level voltage logic state.
sahilmgandhi 18:6a4db94011d3 14522 * | | |1 = nCTS pin input is high level voltage logic state.
sahilmgandhi 18:6a4db94011d3 14523 * | | |Note: This bit echoes when UART Controller peripheral clock is enabled, and nCTS multi-function port is selected.
sahilmgandhi 18:6a4db94011d3 14524 * |[8] |CTSACTLV |nCTS Pin Active Level
sahilmgandhi 18:6a4db94011d3 14525 * | | |This bit defines the active level state of nCTS pin input.
sahilmgandhi 18:6a4db94011d3 14526 * | | |0 = nCTS pin input is high level active.
sahilmgandhi 18:6a4db94011d3 14527 * | | |1 = nCTS pin input is low level active. (Default)
sahilmgandhi 18:6a4db94011d3 14528 * @var UART_T::FIFOSTS
sahilmgandhi 18:6a4db94011d3 14529 * Offset: 0x18 UART FIFO Status Register
sahilmgandhi 18:6a4db94011d3 14530 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 14531 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 14532 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 14533 * |[0] |RXOVIF |RX Overflow Error Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 14534 * | | |This bit is set when RX FIFO overflow.
sahilmgandhi 18:6a4db94011d3 14535 * | | |If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 16 bytes this bit will be set.
sahilmgandhi 18:6a4db94011d3 14536 * | | |0 = RX FIFO is not overflow.
sahilmgandhi 18:6a4db94011d3 14537 * | | |1 = RX FIFO is overflow.
sahilmgandhi 18:6a4db94011d3 14538 * | | |Note: This bit is read only, but can be cleared by writing "1" to it.
sahilmgandhi 18:6a4db94011d3 14539 * |[1] |ABRDIF |Auto-Baud Rate Detect Interrupt (Read Only)
sahilmgandhi 18:6a4db94011d3 14540 * | | |0 = Auto-baud rate detect function is not finished.
sahilmgandhi 18:6a4db94011d3 14541 * | | |1 = Auto-baud rate detect function is finished.
sahilmgandhi 18:6a4db94011d3 14542 * | | |This bit is set to logic "1" when auto-baud rate detect function is finished.
sahilmgandhi 18:6a4db94011d3 14543 * | | |Note: This bit is read only, but can be cleared by writing "1" to it.
sahilmgandhi 18:6a4db94011d3 14544 * |[2] |ABRDTOIF |Auto-Baud Rate Time-Out Interrupt (Read Only)
sahilmgandhi 18:6a4db94011d3 14545 * | | |0 = Auto-baud rate counter is underflow.
sahilmgandhi 18:6a4db94011d3 14546 * | | |1 = Auto-baud rate counter is overflow.
sahilmgandhi 18:6a4db94011d3 14547 * | | |Note1: This bit is set to logic "1" in Auto-baud Rate Detect mode and the baud rate counter is overflow.
sahilmgandhi 18:6a4db94011d3 14548 * | | |Note2: This bit is read only, but can be cleared by writing "1" to it.
sahilmgandhi 18:6a4db94011d3 14549 * |[3] |ADDRDETF |RS-485 Address Byte Detect Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 14550 * | | |0 = Receiver detects a data that is not an address bit (bit 9 ='0').
sahilmgandhi 18:6a4db94011d3 14551 * | | |1 = Receiver detects a data that is an address bit (bit 9 ='1').
sahilmgandhi 18:6a4db94011d3 14552 * | | |Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode .
sahilmgandhi 18:6a4db94011d3 14553 * | | |Note2: This bit is read only, but can be cleared by writing '1' to it.
sahilmgandhi 18:6a4db94011d3 14554 * |[4] |PEF |Parity Error Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 14555 * | | |This bit is set to logic 1 whenever the received character does not have a valid "parity bit".
sahilmgandhi 18:6a4db94011d3 14556 * | | |0 = No parity error is generated.
sahilmgandhi 18:6a4db94011d3 14557 * | | |1 = Parity error is generated.
sahilmgandhi 18:6a4db94011d3 14558 * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
sahilmgandhi 18:6a4db94011d3 14559 * |[5] |FEF |Framing Error Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 14560 * | | |This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
sahilmgandhi 18:6a4db94011d3 14561 * | | |0 = No framing error is generated.
sahilmgandhi 18:6a4db94011d3 14562 * | | |1 = Framing error is generated.
sahilmgandhi 18:6a4db94011d3 14563 * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
sahilmgandhi 18:6a4db94011d3 14564 * |[6] |BIF |Break Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 14565 * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits).
sahilmgandhi 18:6a4db94011d3 14566 * | | |0 = No Break interrupt is generated.
sahilmgandhi 18:6a4db94011d3 14567 * | | |1 = Break interrupt is generated.
sahilmgandhi 18:6a4db94011d3 14568 * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
sahilmgandhi 18:6a4db94011d3 14569 * |[13:8] |RXPTR |RX FIFO Pointer (Read Only)
sahilmgandhi 18:6a4db94011d3 14570 * | | |This field indicates the RX FIFO Buffer Pointer.
sahilmgandhi 18:6a4db94011d3 14571 * | | |When UART receives one byte from external device, RXPTR increases one.
sahilmgandhi 18:6a4db94011d3 14572 * | | |When one byte of RX FIFO is read by CPU, RXPTR decreases one.
sahilmgandhi 18:6a4db94011d3 14573 * | | |The Maximum value shown in RXPTR is 15.
sahilmgandhi 18:6a4db94011d3 14574 * | | |When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0.
sahilmgandhi 18:6a4db94011d3 14575 * | | |As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
sahilmgandhi 18:6a4db94011d3 14576 * |[14] |RXEMPTY |Receiver FIFO Empty (Read Only)
sahilmgandhi 18:6a4db94011d3 14577 * | | |This bit initiate RX FIFO empty or not.
sahilmgandhi 18:6a4db94011d3 14578 * | | |0 = RX FIFO is not empty.
sahilmgandhi 18:6a4db94011d3 14579 * | | |1 = RX FIFO is empty.
sahilmgandhi 18:6a4db94011d3 14580 * | | |Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high.
sahilmgandhi 18:6a4db94011d3 14581 * | | |It will be cleared when UART receives any new data.
sahilmgandhi 18:6a4db94011d3 14582 * |[15] |RXFULL |Receiver FIFO Full (Read Only)
sahilmgandhi 18:6a4db94011d3 14583 * | | |This bit initiates RX FIFO full or not.
sahilmgandhi 18:6a4db94011d3 14584 * | | |0 = RX FIFO is not full.
sahilmgandhi 18:6a4db94011d3 14585 * | | |1 = RX FIFO is full.
sahilmgandhi 18:6a4db94011d3 14586 * | | |Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
sahilmgandhi 18:6a4db94011d3 14587 * |[21:16] |TXPTR |TX FIFO Pointer (Read Only)
sahilmgandhi 18:6a4db94011d3 14588 * | | |This field indicates the TX FIFO Buffer Pointer.
sahilmgandhi 18:6a4db94011d3 14589 * | | |When CPU writes one byte into UART_DAT, TXPTR increases one.
sahilmgandhi 18:6a4db94011d3 14590 * | | |When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
sahilmgandhi 18:6a4db94011d3 14591 * | | |The Maximum value shown in TXPTR is 15.
sahilmgandhi 18:6a4db94011d3 14592 * | | |When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0.
sahilmgandhi 18:6a4db94011d3 14593 * | | |As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
sahilmgandhi 18:6a4db94011d3 14594 * |[22] |TXEMPTY |Transmitter FIFO Empty (Read Only)
sahilmgandhi 18:6a4db94011d3 14595 * | | |This bit indicates TX FIFO empty or not.
sahilmgandhi 18:6a4db94011d3 14596 * | | |0 = TX FIFO is not empty.
sahilmgandhi 18:6a4db94011d3 14597 * | | |1 = TX FIFO is empty.
sahilmgandhi 18:6a4db94011d3 14598 * | | |Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high.
sahilmgandhi 18:6a4db94011d3 14599 * | | |It will be cleared when writing data into DAT (TX FIFO not empty).
sahilmgandhi 18:6a4db94011d3 14600 * |[23] |TXFULL |Transmitter FIFO Full (Read Only)
sahilmgandhi 18:6a4db94011d3 14601 * | | |This bit indicates TX FIFO full or not.
sahilmgandhi 18:6a4db94011d3 14602 * | | |0 = TX FIFO is not full.
sahilmgandhi 18:6a4db94011d3 14603 * | | |1 = TX FIFO is full.
sahilmgandhi 18:6a4db94011d3 14604 * | | |Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
sahilmgandhi 18:6a4db94011d3 14605 * |[24] |TXOVIF |TX Overflow Error Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 14606 * | | |If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.
sahilmgandhi 18:6a4db94011d3 14607 * | | |0 = TX FIFO is not overflow.
sahilmgandhi 18:6a4db94011d3 14608 * | | |1 = TX FIFO is overflow.
sahilmgandhi 18:6a4db94011d3 14609 * | | |Note: This bit is read only, but can be cleared by writing "1" to it.
sahilmgandhi 18:6a4db94011d3 14610 * |[28] |TXEMPTYF |Transmitter Empty Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 14611 * | | |This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.
sahilmgandhi 18:6a4db94011d3 14612 * | | |0 = TX FIFO is not empty.
sahilmgandhi 18:6a4db94011d3 14613 * | | |1 = TX FIFO is empty.
sahilmgandhi 18:6a4db94011d3 14614 * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
sahilmgandhi 18:6a4db94011d3 14615 * @var UART_T::INTSTS
sahilmgandhi 18:6a4db94011d3 14616 * Offset: 0x1C UART Interrupt Status Register
sahilmgandhi 18:6a4db94011d3 14617 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 14618 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 14619 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 14620 * |[0] |RDAIF |Receive Data Available Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 14621 * | | |When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set.
sahilmgandhi 18:6a4db94011d3 14622 * | | |If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.
sahilmgandhi 18:6a4db94011d3 14623 * | | |0 = No RDA interrupt flag is generated.
sahilmgandhi 18:6a4db94011d3 14624 * | | |1 = RDA interrupt flag is generated.
sahilmgandhi 18:6a4db94011d3 14625 * | | |Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4])).
sahilmgandhi 18:6a4db94011d3 14626 * |[1] |THREIF |Transmit Holding Register Empty Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 14627 * | | |This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register.
sahilmgandhi 18:6a4db94011d3 14628 * | | |If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.
sahilmgandhi 18:6a4db94011d3 14629 * | | |0 = No THRE interrupt flag is generated.
sahilmgandhi 18:6a4db94011d3 14630 * | | |1 = THRE interrupt flag is generated.
sahilmgandhi 18:6a4db94011d3 14631 * | | |Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
sahilmgandhi 18:6a4db94011d3 14632 * |[2] |RLSIF |Receive Line Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 14633 * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set).
sahilmgandhi 18:6a4db94011d3 14634 * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
sahilmgandhi 18:6a4db94011d3 14635 * | | |0 = No RLS interrupt flag is generated.
sahilmgandhi 18:6a4db94011d3 14636 * | | |1 = RLS interrupt flag is generated.
sahilmgandhi 18:6a4db94011d3 14637 * | | |Note1: In RS-485 function mode, this field is set include receiver detect and received address byte character (bit9 = '1') bit.
sahilmgandhi 18:6a4db94011d3 14638 * | | |At the same time, the bit of ADDRDETF (UART_FIFOSTS[3]) is also set.
sahilmgandhi 18:6a4db94011d3 14639 * | | |Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
sahilmgandhi 18:6a4db94011d3 14640 * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
sahilmgandhi 18:6a4db94011d3 14641 * |[3] |MODEMIF |MODEM Interrupt Flag (Read Only) Channel This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]) = 1). If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated.
sahilmgandhi 18:6a4db94011d3 14642 * | | |0 = No Modem interrupt flag is generated.
sahilmgandhi 18:6a4db94011d3 14643 * | | |1 = Modem interrupt flag is generated.
sahilmgandhi 18:6a4db94011d3 14644 * | | |Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
sahilmgandhi 18:6a4db94011d3 14645 * |[4] |RXTOIF |Time-Out Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 14646 * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC.
sahilmgandhi 18:6a4db94011d3 14647 * | | |If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.
sahilmgandhi 18:6a4db94011d3 14648 * | | |0 = No Time-out interrupt flag is generated.
sahilmgandhi 18:6a4db94011d3 14649 * | | |1 = Time-out interrupt flag is generated.
sahilmgandhi 18:6a4db94011d3 14650 * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
sahilmgandhi 18:6a4db94011d3 14651 * |[5] |BUFERRIF |Buffer Error Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 14652 * | | |This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set).
sahilmgandhi 18:6a4db94011d3 14653 * | | |When BERRIF (UART_INTSTS[5])is set, the transfer is not correct.
sahilmgandhi 18:6a4db94011d3 14654 * | | |If BFERRIEN (UART_INTEN [8]) is enabled, the buffer error interrupt will be generated.
sahilmgandhi 18:6a4db94011d3 14655 * | | |0 = No buffer error interrupt flag is generated.
sahilmgandhi 18:6a4db94011d3 14656 * | | |1 = Buffer error interrupt flag is generated.
sahilmgandhi 18:6a4db94011d3 14657 * | | |Note: This bit is read only.
sahilmgandhi 18:6a4db94011d3 14658 * | | |This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
sahilmgandhi 18:6a4db94011d3 14659 * |[6] |WKIF |UART Wake-up Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 14660 * | | |This bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.
sahilmgandhi 18:6a4db94011d3 14661 * | | |0 = No DATWKIF and CTSWKIF are generated.
sahilmgandhi 18:6a4db94011d3 14662 * | | |1 = DATWKIF or CTSWKIF.
sahilmgandhi 18:6a4db94011d3 14663 * | | |Note: This bit is read only.
sahilmgandhi 18:6a4db94011d3 14664 * | | |This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF(UART_INTSTS[16]) are cleared to 0 by writing 1 to DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[17]).
sahilmgandhi 18:6a4db94011d3 14665 * |[7] |LINIF |LIN Bus Interrupt Flag (Read Only) (Not Available in UART2/UART3 Channel)
sahilmgandhi 18:6a4db94011d3 14666 * | | |This bit is set when LIN slave header detect (SLVHDETF (UART_LINSTS[0] =1)), LIN break detect (BRKDETF(UART_LINSTS[9])=1), bit error detect (BITEF(UART_LINSTS[9])=1), LIN slave ID parity error (SLVIDPEF(UART_LINSTS[2]) = 1) or LIN slave header error detect (SLVHEF (UART_LINSTS[1])).
sahilmgandhi 18:6a4db94011d3 14667 * | | |If LIN_ IEN (UART_INTEN [8]) is enabled the LIN interrupt will be generated.
sahilmgandhi 18:6a4db94011d3 14668 * | | |0 = None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.
sahilmgandhi 18:6a4db94011d3 14669 * | | |1 = At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.
sahilmgandhi 18:6a4db94011d3 14670 * | | |Note: This bit is read only.
sahilmgandhi 18:6a4db94011d3 14671 * | | |This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]), SLVHEF(UART_LINSTS[1]) and SLVSYNCF(UART_LINSTS[3]) all are cleared.
sahilmgandhi 18:6a4db94011d3 14672 * |[8] |RDAINT |Receive Data Available Interrupt Indicator (Read Only)
sahilmgandhi 18:6a4db94011d3 14673 * | | |This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
sahilmgandhi 18:6a4db94011d3 14674 * | | |0 = No RDA interrupt is generated.
sahilmgandhi 18:6a4db94011d3 14675 * | | |1 = RDA interrupt is generated.
sahilmgandhi 18:6a4db94011d3 14676 * |[9] |THREINT |Transmit Holding Register Empty Interrupt Indicator (Read Only)
sahilmgandhi 18:6a4db94011d3 14677 * | | |This bit is set if THREIEN (UART_INTEN[1])and THREIF(UART_INTSTS[1]) are both set to 1.
sahilmgandhi 18:6a4db94011d3 14678 * | | |0 = No DATE interrupt is generated.
sahilmgandhi 18:6a4db94011d3 14679 * | | |1 = DATE interrupt is generated.
sahilmgandhi 18:6a4db94011d3 14680 * |[10] |RLSINT |Receive Line Status Interrupt Indicator (Read Only)
sahilmgandhi 18:6a4db94011d3 14681 * | | |This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
sahilmgandhi 18:6a4db94011d3 14682 * | | |0 = No RLS interrupt is generated.
sahilmgandhi 18:6a4db94011d3 14683 * | | |1 = RLS interrupt is generated.
sahilmgandhi 18:6a4db94011d3 14684 * |[11] |MODEMINT |MODEM Status Interrupt Indicator (Read Only)
sahilmgandhi 18:6a4db94011d3 14685 * | | |This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[4]) are both set to 1
sahilmgandhi 18:6a4db94011d3 14686 * | | |0 = No Modem interrupt is generated.
sahilmgandhi 18:6a4db94011d3 14687 * | | |1 = Modem interrupt is generated.
sahilmgandhi 18:6a4db94011d3 14688 * |[12] |RXTOINT |Time-Out Interrupt Indicator (Read Only)
sahilmgandhi 18:6a4db94011d3 14689 * | | |This bit is set if TOUTIEN(UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
sahilmgandhi 18:6a4db94011d3 14690 * | | |0 = No Tout interrupt is generated.
sahilmgandhi 18:6a4db94011d3 14691 * | | |1 = Tout interrupt is generated.
sahilmgandhi 18:6a4db94011d3 14692 * |[13] |BUFERRINT |Buffer Error Interrupt Indicator (Read Only)
sahilmgandhi 18:6a4db94011d3 14693 * | | |This bit is set if BFERRIEN(UART_INTEN[5]) and BERRIF(UART_INTSTS[5]) are both set to 1.
sahilmgandhi 18:6a4db94011d3 14694 * | | |0 = No buffer error interrupt is generated.
sahilmgandhi 18:6a4db94011d3 14695 * | | |1 = Buffer error interrupt is generated.
sahilmgandhi 18:6a4db94011d3 14696 * |[15] |LININT |LIN Bus Interrupt Indicator (Read Only)(Not Available in UART2/UART3 Channel)
sahilmgandhi 18:6a4db94011d3 14697 * | | |This bit is set if LINIEN (UART_INTEN[8]) and LIN IF(UART_INTSTS[7]) are both set to 1.
sahilmgandhi 18:6a4db94011d3 14698 * | | |0 = No LIN Bus interrupt is generated.
sahilmgandhi 18:6a4db94011d3 14699 * | | |1 = The LIN Bus interrupt is generated.
sahilmgandhi 18:6a4db94011d3 14700 * |[16] |CTSWKIF |nCTS Wake-Up Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 14701 * | | |0 = Chip stays in power-down state.
sahilmgandhi 18:6a4db94011d3 14702 * | | |1 = Chip wake-up from power-down state by nCTS wake-up.
sahilmgandhi 18:6a4db94011d3 14703 * | | |Note1: If WKCTSIEN (UART_INTEN[9])is enabled, the wake-up interrupt is generated.
sahilmgandhi 18:6a4db94011d3 14704 * | | |Note2: This bit is read only, but can be cleared by writing '1' to it.
sahilmgandhi 18:6a4db94011d3 14705 * |[17] |DATWKIF |Data Wake-Up Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 14706 * | | |This bit is set if chip wake-up from power-down state by data wake-up.
sahilmgandhi 18:6a4db94011d3 14707 * | | |0 = Chip stays in power-down state.
sahilmgandhi 18:6a4db94011d3 14708 * | | |1 = Chip wake-up from power-down state by data wake-up.
sahilmgandhi 18:6a4db94011d3 14709 * | | |Note1: If WKDATIEN (UART_INTEN[10]) is enabled, the wake-up interrupt is generated.
sahilmgandhi 18:6a4db94011d3 14710 * | | |Note2: This bit is read only, but can be cleared by writing '1' to it.
sahilmgandhi 18:6a4db94011d3 14711 * |[18] |HWRLSIF |In DMA Mode, Receive Line Status Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 14712 * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set).
sahilmgandhi 18:6a4db94011d3 14713 * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
sahilmgandhi 18:6a4db94011d3 14714 * | | |0 = No RLS interrupt flag is generated.
sahilmgandhi 18:6a4db94011d3 14715 * | | |1 = RLS interrupt flag is generated.
sahilmgandhi 18:6a4db94011d3 14716 * | | |Note1: In RS-485 function mode, this field include receiver detect any address byte received address byte character (bit9 = '1') bit.
sahilmgandhi 18:6a4db94011d3 14717 * | | |Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
sahilmgandhi 18:6a4db94011d3 14718 * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared
sahilmgandhi 18:6a4db94011d3 14719 * |[19] |HWMODIF |In DMA Mode, MODEM Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 14720 * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_CTSDETF[0] =1)).
sahilmgandhi 18:6a4db94011d3 14721 * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated.
sahilmgandhi 18:6a4db94011d3 14722 * | | |0 = No Modem interrupt flag is generated.
sahilmgandhi 18:6a4db94011d3 14723 * | | |1 = Modem interrupt flag is generated.
sahilmgandhi 18:6a4db94011d3 14724 * | | |Note: This bit is read only and reset to 0 when the bit UART_CTSDETF (US_MSR[0]) is cleared by writing 1 on CTSDETF (UART_CTSDETF [0]).
sahilmgandhi 18:6a4db94011d3 14725 * |[20] |HWTOIF |In DMA Mode, Time-Out Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 14726 * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]).
sahilmgandhi 18:6a4db94011d3 14727 * | | |If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.
sahilmgandhi 18:6a4db94011d3 14728 * | | |0 = No Time-out interrupt flag is generated.
sahilmgandhi 18:6a4db94011d3 14729 * | | |1 = Time-out interrupt flag is generated.
sahilmgandhi 18:6a4db94011d3 14730 * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
sahilmgandhi 18:6a4db94011d3 14731 * |[21] |HWBUFEIF |In DMA Mode, Buffer Error Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 14732 * | | |This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set).
sahilmgandhi 18:6a4db94011d3 14733 * | | |When BERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct.
sahilmgandhi 18:6a4db94011d3 14734 * | | |If BFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
sahilmgandhi 18:6a4db94011d3 14735 * | | |0 = No buffer error interrupt flag is generated.
sahilmgandhi 18:6a4db94011d3 14736 * | | |1 = Buffer error interrupt flag is generated.
sahilmgandhi 18:6a4db94011d3 14737 * | | |Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
sahilmgandhi 18:6a4db94011d3 14738 * |[26] |HWRLSINT |In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)
sahilmgandhi 18:6a4db94011d3 14739 * | | |This bit is set if RLSIEN (UART_INTEN[2])and HWRLSIF(UART_INTSTS[18]) are both set to 1.
sahilmgandhi 18:6a4db94011d3 14740 * | | |0 = No RLS interrupt is generated in DMA mode.
sahilmgandhi 18:6a4db94011d3 14741 * | | |1 = RLS interrupt is generated in DMA mode.
sahilmgandhi 18:6a4db94011d3 14742 * |[27] |HWMODINT |In DMA Mode, MODEM Status Interrupt Indicator (Read Only)
sahilmgandhi 18:6a4db94011d3 14743 * | | |This bit is set if MODEMIEN(UART_INTEN[3]) and HWMODIF(UART_INTSTS[3]) are both set to 1.
sahilmgandhi 18:6a4db94011d3 14744 * | | |0 = No Modem interrupt is generated in DMA mode.
sahilmgandhi 18:6a4db94011d3 14745 * | | |1 = Modem interrupt is generated in DMA mode.
sahilmgandhi 18:6a4db94011d3 14746 * |[28] |HWTOINT |In DMA Mode, Time-Out Interrupt Indicator (Read Only)
sahilmgandhi 18:6a4db94011d3 14747 * | | |This bit is set if TOUTIEN (UART_INTEN[4])and HWTOIF(UART_INTSTS[20]) are both set to 1.
sahilmgandhi 18:6a4db94011d3 14748 * | | |0 = No Tout interrupt is generated in DMA mode.
sahilmgandhi 18:6a4db94011d3 14749 * | | |1 = Tout interrupt is generated in DMA mode.
sahilmgandhi 18:6a4db94011d3 14750 * |[29] |HWBUFEINT |In DMA Mode, Buffer Error Interrupt Indicator (Read Only)
sahilmgandhi 18:6a4db94011d3 14751 * | | |This bit is set if BFERRIEN (UART_INTEN[5]) and HWBEIF (UART_INTSTS[5])are both set to 1.
sahilmgandhi 18:6a4db94011d3 14752 * | | |0 = No buffer error interrupt is generated in DMA mode.
sahilmgandhi 18:6a4db94011d3 14753 * | | |1 = Buffer error interrupt is generated in DMA mode.
sahilmgandhi 18:6a4db94011d3 14754 * @var UART_T::TOUT
sahilmgandhi 18:6a4db94011d3 14755 * Offset: 0x20 UART Time-out Register
sahilmgandhi 18:6a4db94011d3 14756 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 14757 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 14758 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 14759 * |[7:0] |TOIC |Time-Out Interrupt Comparator
sahilmgandhi 18:6a4db94011d3 14760 * | | |The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word.
sahilmgandhi 18:6a4db94011d3 14761 * | | |Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (UART_TOUT[7:0])), a receiver time-out interrupt (RXTOINT(UART_INTSTS[12])) is generated if RXTOIEN (UART_INTEN [4]) enabled.
sahilmgandhi 18:6a4db94011d3 14762 * | | |A new incoming data word or RX FIFO empty will clear RXTOINT(UART_INTSTS[12]).
sahilmgandhi 18:6a4db94011d3 14763 * | | |In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255.
sahilmgandhi 18:6a4db94011d3 14764 * | | |So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer.
sahilmgandhi 18:6a4db94011d3 14765 * |[15:8] |DLY |TX Delay Time Value
sahilmgandhi 18:6a4db94011d3 14766 * | | |This field is used to programming the transfer delay time between the last stop bit and next start bit.
sahilmgandhi 18:6a4db94011d3 14767 * | | |The unit is bit time.
sahilmgandhi 18:6a4db94011d3 14768 * @var UART_T::BAUD
sahilmgandhi 18:6a4db94011d3 14769 * Offset: 0x24 UART Baud Rate Divisor Register
sahilmgandhi 18:6a4db94011d3 14770 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 14771 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 14772 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 14773 * |[15:0] |BRD |Baud Rate Divider
sahilmgandhi 18:6a4db94011d3 14774 * | | |The field indicates the baud rate divider.
sahilmgandhi 18:6a4db94011d3 14775 * | | |This filed is used in baud rate calculation.
sahilmgandhi 18:6a4db94011d3 14776 * | | |The detail description is shown in Table 6.21-2.
sahilmgandhi 18:6a4db94011d3 14777 * |[27:24] |EDIVM1 |Extra Divider For BAUD Rate Mode 1
sahilmgandhi 18:6a4db94011d3 14778 * | | |This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2.
sahilmgandhi 18:6a4db94011d3 14779 * | | |The detail description is shown in Table 6.21-2.
sahilmgandhi 18:6a4db94011d3 14780 * |[28] |BAUDM0 |BAUD Rate Mode Selection Bit 0
sahilmgandhi 18:6a4db94011d3 14781 * | | |This bit is baud rate mode selection bit 0.
sahilmgandhi 18:6a4db94011d3 14782 * | | |UART provides three baud rate calculation modes.
sahilmgandhi 18:6a4db94011d3 14783 * | | |This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode.
sahilmgandhi 18:6a4db94011d3 14784 * | | |The detail description is shown in Table 6.21-2.
sahilmgandhi 18:6a4db94011d3 14785 * |[29] |BAUDM1 |BAUD Rate Mode Selection Bit 1
sahilmgandhi 18:6a4db94011d3 14786 * | | |This bit is baud rate mode selection bit 1.
sahilmgandhi 18:6a4db94011d3 14787 * | | |UART provides three baud rate calculation modes.
sahilmgandhi 18:6a4db94011d3 14788 * | | |This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode.
sahilmgandhi 18:6a4db94011d3 14789 * | | |The detail description is shown in Table 6.21-2.
sahilmgandhi 18:6a4db94011d3 14790 * | | |Note: In IrDA mode must be operated in mode 0.
sahilmgandhi 18:6a4db94011d3 14791 * @var UART_T::IRDA
sahilmgandhi 18:6a4db94011d3 14792 * Offset: 0x28 UART IrDA Control Register
sahilmgandhi 18:6a4db94011d3 14793 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 14794 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 14795 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 14796 * |[1] |TXEN |IrDA Receiver/Transmitter Selection Enable Bit
sahilmgandhi 18:6a4db94011d3 14797 * | | |0 = IrDA Transmitter Disabled and Receiver Enabled. (Default)
sahilmgandhi 18:6a4db94011d3 14798 * | | |1 = IrDA Transmitter Enabled and Receiver Disabled.
sahilmgandhi 18:6a4db94011d3 14799 * | | |Note: In IrDA function mode (FUNCSEL(UART_FUNCSEL[1:0])=10), the first received data is unreliable and it should be skipped if IrDA receiver is enabled (TXEN(UART_IRDA[1])=0) at the first time.
sahilmgandhi 18:6a4db94011d3 14800 * |[5] |TXINV |IrDA Inverse Transmitting Output Signal
sahilmgandhi 18:6a4db94011d3 14801 * | | |0 = None inverse transmitting signal. (Default)
sahilmgandhi 18:6a4db94011d3 14802 * | | |1 = Inverse transmitting output signal.
sahilmgandhi 18:6a4db94011d3 14803 * |[6] |RXINV |IrDA Inverse Receive Input Signal
sahilmgandhi 18:6a4db94011d3 14804 * | | |0 = None inverse receiving input signal.
sahilmgandhi 18:6a4db94011d3 14805 * | | |1 = Inverse receiving input signal. (Default)
sahilmgandhi 18:6a4db94011d3 14806 * @var UART_T::ALTCTL
sahilmgandhi 18:6a4db94011d3 14807 * Offset: 0x2C UART Alternate Control/Status Register
sahilmgandhi 18:6a4db94011d3 14808 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 14809 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 14810 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 14811 * |[3:0] |BRKFL |UART LIN Break Field Length (Only Available In UART0/UART1 Channel)
sahilmgandhi 18:6a4db94011d3 14812 * | | |This field indicates a 4-bit LIN TX break field count.
sahilmgandhi 18:6a4db94011d3 14813 * | | |Note1: This break field length is BRKFL + 1
sahilmgandhi 18:6a4db94011d3 14814 * | | |Note2: According to LIN spec, the reset value is 0xC (break field length = 13).
sahilmgandhi 18:6a4db94011d3 14815 * |[6] |LINRXEN |LIN RX Enable Bit (Only Available In UART0/UART1 Channel)
sahilmgandhi 18:6a4db94011d3 14816 * | | |0 = LIN RX mode Disabled.
sahilmgandhi 18:6a4db94011d3 14817 * | | |1 = LIN RX mode Enabled.
sahilmgandhi 18:6a4db94011d3 14818 * |[7] |LINTXEN |LIN TX Break Mode Enable Bit (Only Available In UART0/UART1 Channel)
sahilmgandhi 18:6a4db94011d3 14819 * | | |0 = LIN TX Break mode Disabled.
sahilmgandhi 18:6a4db94011d3 14820 * | | |1 = LIN TX Break mode Enabled.
sahilmgandhi 18:6a4db94011d3 14821 * | | |Note: When TX break field transfer operation finished, this bit will be cleared automatically.
sahilmgandhi 18:6a4db94011d3 14822 * |[8] |RS485NMM |RS-485 Normal Multi-Drop Operation Mode (NMM)
sahilmgandhi 18:6a4db94011d3 14823 * | | |0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled.
sahilmgandhi 18:6a4db94011d3 14824 * | | |1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled.
sahilmgandhi 18:6a4db94011d3 14825 * | | |Note: It cannot be active with RS-485_AAD operation mode.
sahilmgandhi 18:6a4db94011d3 14826 * |[9] |RS485AAD |RS-485 Auto Address Detection Operation Mode (AAD)
sahilmgandhi 18:6a4db94011d3 14827 * | | |0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled.
sahilmgandhi 18:6a4db94011d3 14828 * | | |1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled.
sahilmgandhi 18:6a4db94011d3 14829 * | | |Note: It cannot be active with RS-485_NMM operation mode.
sahilmgandhi 18:6a4db94011d3 14830 * |[10] |RS485AUD |RS-485 Auto Direction Function (AUD)
sahilmgandhi 18:6a4db94011d3 14831 * | | |0 = RS-485 Auto Direction Operation function (AUD) Disabled.
sahilmgandhi 18:6a4db94011d3 14832 * | | |1 = RS-485 Auto Direction Operation function (AUD) Enabled.
sahilmgandhi 18:6a4db94011d3 14833 * | | |Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
sahilmgandhi 18:6a4db94011d3 14834 * |[15] |ADDRDEN |RS-485 Address Detection Enable Bit
sahilmgandhi 18:6a4db94011d3 14835 * | | |This bit is used to enable RS-485 Address Detection mode.
sahilmgandhi 18:6a4db94011d3 14836 * | | |0 = Address detection mode Disabled.
sahilmgandhi 18:6a4db94011d3 14837 * | | |1 = Address detection mode Enabled.
sahilmgandhi 18:6a4db94011d3 14838 * | | |Note: This bit is used for RS-485 any operation mode.
sahilmgandhi 18:6a4db94011d3 14839 * |[17] |ABRIF |Auto-Baud Rate Interrupt Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 14840 * | | |This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated.
sahilmgandhi 18:6a4db94011d3 14841 * | | |Note: This bit is read only, but it can be cleared by writing "1" to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1])
sahilmgandhi 18:6a4db94011d3 14842 * |[18] |ABRDEN |Auto-Baud Rate Detect Enable Bit
sahilmgandhi 18:6a4db94011d3 14843 * | | |0 = Auto-baud rate detect function Disabled.
sahilmgandhi 18:6a4db94011d3 14844 * | | |1 = Auto-baud rate detect function Enabled.
sahilmgandhi 18:6a4db94011d3 14845 * | | |This bit is cleared automatically after auto-baud detection is finished.
sahilmgandhi 18:6a4db94011d3 14846 * |[20:19] |ABRDBITS |Auto-Baud Rate Detect Bit Length
sahilmgandhi 18:6a4db94011d3 14847 * | | |00 = 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01.
sahilmgandhi 18:6a4db94011d3 14848 * | | |01 = 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02.
sahilmgandhi 18:6a4db94011d3 14849 * | | |10 = 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08.
sahilmgandhi 18:6a4db94011d3 14850 * | | |11 = 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80.
sahilmgandhi 18:6a4db94011d3 14851 * | | |Note : The calculation of bit number includes the START bit.
sahilmgandhi 18:6a4db94011d3 14852 * |[31:24] |ADDRMV |Address Match Value
sahilmgandhi 18:6a4db94011d3 14853 * | | |This field contains the RS-485 address match values.
sahilmgandhi 18:6a4db94011d3 14854 * | | |Note: This field is used for RS-485 auto address detection mode.
sahilmgandhi 18:6a4db94011d3 14855 * @var UART_T::FUNCSEL
sahilmgandhi 18:6a4db94011d3 14856 * Offset: 0x30 UART Function Select Register
sahilmgandhi 18:6a4db94011d3 14857 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 14858 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 14859 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 14860 * |[1:0] |FUNCSEL |Function Select
sahilmgandhi 18:6a4db94011d3 14861 * | | |00 = UART function.
sahilmgandhi 18:6a4db94011d3 14862 * | | |01 = LIN function (Only Available in UART0/UART1 Channel).
sahilmgandhi 18:6a4db94011d3 14863 * | | |10 = IrDA function.
sahilmgandhi 18:6a4db94011d3 14864 * | | |11 = RS-485 function.
sahilmgandhi 18:6a4db94011d3 14865 * | | |Note: In IrDA function mode (FUNCSEL(UART_FUNCSEL[1:0])=10), the first received data is unreliable and it should be skipped if IrDA receiver is enabled (TXEN(UART_IRDA[1])=0) at the first time.
sahilmgandhi 18:6a4db94011d3 14866 * @var UART_T::LINCTL
sahilmgandhi 18:6a4db94011d3 14867 * Offset: 0x34 UART LIN Control Register
sahilmgandhi 18:6a4db94011d3 14868 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 14869 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 14870 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 14871 * |[0] |SLVEN |LIN Slave Mode Enable Bit
sahilmgandhi 18:6a4db94011d3 14872 * | | |0 = LIN slave mode Disabled.
sahilmgandhi 18:6a4db94011d3 14873 * | | |1 = LIN slave mode Enabled.
sahilmgandhi 18:6a4db94011d3 14874 * |[1] |SLVHDEN |LIN Slave Header Detection Enable Bit
sahilmgandhi 18:6a4db94011d3 14875 * | | |0 = LIN slave header detection Disabled.
sahilmgandhi 18:6a4db94011d3 14876 * | | |1 = LIN slave header detection Enabled.
sahilmgandhi 18:6a4db94011d3 14877 * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
sahilmgandhi 18:6a4db94011d3 14878 * | | |Note2: In LIN function mode, when detect header field (break + sync + frame ID), SLVHDETF (UART_LINSTS [0]) flag will be asserted.
sahilmgandhi 18:6a4db94011d3 14879 * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
sahilmgandhi 18:6a4db94011d3 14880 * |[2] |SLVAREN |LIN Slave Automatic Resynchronization Mode Enable Bit
sahilmgandhi 18:6a4db94011d3 14881 * | | |0 = LIN automatic resynchronization Disabled.
sahilmgandhi 18:6a4db94011d3 14882 * | | |1 = LIN automatic resynchronization Enabled.
sahilmgandhi 18:6a4db94011d3 14883 * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
sahilmgandhi 18:6a4db94011d3 14884 * | | |Note2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).
sahilmgandhi 18:6a4db94011d3 14885 * | | |Note3: The control and interactions of this field are explained in 6.21.5.9(Slave mode with automatic resynchronization).
sahilmgandhi 18:6a4db94011d3 14886 * |[3] |SLVDUEN |LIN Slave Divider Update Method Enable Bit
sahilmgandhi 18:6a4db94011d3 14887 * | | |0 = UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time).
sahilmgandhi 18:6a4db94011d3 14888 * | | |1 = UART_BAUD is updated at the next received character.
sahilmgandhi 18:6a4db94011d3 14889 * | | |User must set the bit before checksum reception.
sahilmgandhi 18:6a4db94011d3 14890 * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
sahilmgandhi 18:6a4db94011d3 14891 * | | |Note2: This bit used for LIN Slave Automatic Resynchronization mode.
sahilmgandhi 18:6a4db94011d3 14892 * | | |(for Non-Automatic Resynchronization mode, this bit should be kept cleared).
sahilmgandhi 18:6a4db94011d3 14893 * | | |Note3: The control and interactions of this field are explained in 6.21.5.9 (Slave mode with automatic resynchronization).
sahilmgandhi 18:6a4db94011d3 14894 * |[4] |MUTE |LIN Mute Mode Enable Bit
sahilmgandhi 18:6a4db94011d3 14895 * | | |0 = LIN mute mode Disabled.
sahilmgandhi 18:6a4db94011d3 14896 * | | |1 = LIN mute mode Enabled.
sahilmgandhi 18:6a4db94011d3 14897 * | | |Note: The exit from mute mode condition and each control and interactions of this field are explained in 6.21.5.9 (LIN slave mode).
sahilmgandhi 18:6a4db94011d3 14898 * |[8] |SENDH |LIN TX Send Header Enable Bit
sahilmgandhi 18:6a4db94011d3 14899 * | | |The LIN TX header can be "break field" or "break and sync field" or "break, sync and frame ID field", it is depend on setting HSEL (UART_LINCTL[23:22]).
sahilmgandhi 18:6a4db94011d3 14900 * | | |0 = Send LIN TX header Disabled.
sahilmgandhi 18:6a4db94011d3 14901 * | | |1 = Send LIN TX header Enabled.
sahilmgandhi 18:6a4db94011d3 14902 * | | |Note1: These registers are shadow registers of SENDH (UART_ALTCTL [7]); user can read/write it by setting SENDH (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]).
sahilmgandhi 18:6a4db94011d3 14903 * | | |Note2: When transmitter header field (it may be "break" or "break + sync" or "break + sync + frame ID" selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically.
sahilmgandhi 18:6a4db94011d3 14904 * |[9] |IDPEN |LIN ID Parity Enable Bit
sahilmgandhi 18:6a4db94011d3 14905 * | | |0 = LIN frame ID parity Disabled.
sahilmgandhi 18:6a4db94011d3 14906 * | | |1 = LIN frame ID parity Enabled.
sahilmgandhi 18:6a4db94011d3 14907 * | | |Note1: This bit can be used for LIN master to sending header field (SENDH (UART_LINCTL[8]) = 1 and HSEL (UART_LINCTL[23:22]) = 10) or be used for enable LIN slave received frame ID parity checked.
sahilmgandhi 18:6a4db94011d3 14908 * | | |Note2: This bit is only use when the operation header transmitter is in HSEL (UART_LINCTL[23:22]) = 10
sahilmgandhi 18:6a4db94011d3 14909 * |[10] |BRKDETEN |LIN Break Detection Enable Bit
sahilmgandhi 18:6a4db94011d3 14910 * | | |When detect consecutive dominant greater than 11 bits, and are followed by a delimiter character, the BRKDETF (UART_LINSTS[8]) flag is set in UART_LINSTS register at the end of break field.
sahilmgandhi 18:6a4db94011d3 14911 * | | |If the LINIEN (UART_INTEN [8])=1, an interrupt will be generated.
sahilmgandhi 18:6a4db94011d3 14912 * | | |0 = LIN break detection Disabled .
sahilmgandhi 18:6a4db94011d3 14913 * | | |1 = LIN break detection Enabled.
sahilmgandhi 18:6a4db94011d3 14914 * |[11] |RXOFF |LIN Receiver Disable Bit
sahilmgandhi 18:6a4db94011d3 14915 * | | |If the receiver is enabled (RXOFF (UART_LINCTL[11] ) = 0),
sahilmgandhi 18:6a4db94011d3 14916 * | | |all received byte data will be accepted and stored in the RX-FIFO,
sahilmgandhi 18:6a4db94011d3 14917 * | | |and if the receiver is disabled (RXOFF (UART_LINCTL[11]) = 1), all received byte data will be ignore.
sahilmgandhi 18:6a4db94011d3 14918 * | | |0 = LIN receiver Enabled.
sahilmgandhi 18:6a4db94011d3 14919 * | | |1 = LIN receiver Disabled.
sahilmgandhi 18:6a4db94011d3 14920 * | | |Note: This bit is only valid when operating in LIN function mode (FUNCSEL (UART_FUNCSEL[1:0]) = 01).
sahilmgandhi 18:6a4db94011d3 14921 * |[12] |BITERREN |Bit Error Detect Enable Bit
sahilmgandhi 18:6a4db94011d3 14922 * | | |0 = Bit error detection function Disabled.
sahilmgandhi 18:6a4db94011d3 14923 * | | |1 = Bit error detection Enabled.
sahilmgandhi 18:6a4db94011d3 14924 * | | |Note: In LIN function mode, when occur bit error, the BITEF (UART_LINSTS[9]) flag will be asserted.
sahilmgandhi 18:6a4db94011d3 14925 * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
sahilmgandhi 18:6a4db94011d3 14926 * |[19:16] |BRKFL |LIN Break Field Length
sahilmgandhi 18:6a4db94011d3 14927 * | | |This field indicates a 4-bit LIN TX break field count.
sahilmgandhi 18:6a4db94011d3 14928 * | | |Note1: These registers are shadow registers of BRKFL, User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]).
sahilmgandhi 18:6a4db94011d3 14929 * | | |Note2: This break field length is BRKFL + 1.
sahilmgandhi 18:6a4db94011d3 14930 * | | |Note3: According to LIN spec, the reset value is 12 (break field length = 13).
sahilmgandhi 18:6a4db94011d3 14931 * |[21:20] |BSL |LIN Break/Sync Delimiter Length
sahilmgandhi 18:6a4db94011d3 14932 * | | |00 = The LIN break/sync delimiter length is 1-bit time.
sahilmgandhi 18:6a4db94011d3 14933 * | | |01 = The LIN break/sync delimiter length is 2-bit time.
sahilmgandhi 18:6a4db94011d3 14934 * | | |10 = The LIN break/sync delimiter length is 3-bit time.
sahilmgandhi 18:6a4db94011d3 14935 * | | |11 = The LIN break/sync delimiter length is 4-bit time.
sahilmgandhi 18:6a4db94011d3 14936 * | | |Note: This bit used for LIN master to sending header field.
sahilmgandhi 18:6a4db94011d3 14937 * |[23:22] |HSEL |LIN Header Select
sahilmgandhi 18:6a4db94011d3 14938 * | | |00 = The LIN header includes "break field".
sahilmgandhi 18:6a4db94011d3 14939 * | | |01 = The LIN header includes "break field" and "sync field".
sahilmgandhi 18:6a4db94011d3 14940 * | | |10 = The LIN header includes "break field", "sync field" and "frame ID field".
sahilmgandhi 18:6a4db94011d3 14941 * | | |11 = Reserved.
sahilmgandhi 18:6a4db94011d3 14942 * | | |Note: This bit is used to master mode for LIN to send header field (SENDH (UART_LINCTL [8]) = 1) or used to slave to indicates exit from mute mode condition (MUTE (UART_LINCTL[4]) = 1).
sahilmgandhi 18:6a4db94011d3 14943 * |[31:24] |PID |LIN PID Bits
sahilmgandhi 18:6a4db94011d3 14944 * | | |This field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on IDPEN (UART_LINCTL[9]) = 1.
sahilmgandhi 18:6a4db94011d3 14945 * | | |If the parity generated by hardware, user fill ID0~ID5, (PID [29:24] )hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field.
sahilmgandhi 18:6a4db94011d3 14946 * | | |Note1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).
sahilmgandhi 18:6a4db94011d3 14947 * | | |Note2: This field can be used for LIN master mode or slave mode.
sahilmgandhi 18:6a4db94011d3 14948 * @var UART_T::LINSTS
sahilmgandhi 18:6a4db94011d3 14949 * Offset: 0x38 UART LIN Status Register
sahilmgandhi 18:6a4db94011d3 14950 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 14951 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 14952 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 14953 * |[0] |SLVHDETF |LIN Slave Header Detection Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 14954 * | | |This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 14955 * | | |0 = LIN header not detected.
sahilmgandhi 18:6a4db94011d3 14956 * | | |1 = LIN header detected (break + sync + frame ID).
sahilmgandhi 18:6a4db94011d3 14957 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 14958 * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enable LIN slave header detection function (SLVHDEN (UART_LINCTL [1])).
sahilmgandhi 18:6a4db94011d3 14959 * | | |Note3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header ("break + sync + frame ID"), the SLVHDETF will be set whether the frame ID correct or not.
sahilmgandhi 18:6a4db94011d3 14960 * |[1] |SLVHEF |LIN Slave Header Error Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 14961 * | | |This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 14962 * | | |The header errors include "break delimiter is too short (less than 0.5 bit time)", "frame error in sync field or Identifier field", "sync field data is not 0x55 in Non-Automatic Resynchronization mode", "sync field deviation error with Automatic Resynchronization mode", "sync field measure time-out with Automatic Resynchronization mode" and "LIN header reception time-out".
sahilmgandhi 18:6a4db94011d3 14963 * | | |0 = LIN header error not detected.
sahilmgandhi 18:6a4db94011d3 14964 * | | |1 = LIN header error detected.
sahilmgandhi 18:6a4db94011d3 14965 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 14966 * | | |Note2: This bit is only valid when UART is operated in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enables LIN slave header detection function (SLVHDEN (UART_LINCTL [1])).
sahilmgandhi 18:6a4db94011d3 14967 * |[2] |SLVIDPEF |LIN Slave ID Parity Error Flag
sahilmgandhi 18:6a4db94011d3 14968 * | | |This bit is set by hardware when receipted frame ID parity is not correct.
sahilmgandhi 18:6a4db94011d3 14969 * | | |0 = No active.
sahilmgandhi 18:6a4db94011d3 14970 * | | |1 = Receipted frame ID parity is not correct.
sahilmgandhi 18:6a4db94011d3 14971 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 14972 * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0])= 1) and enable LIN frame ID parity check function IDPEN (UART_LINCTL [9]).
sahilmgandhi 18:6a4db94011d3 14973 * |[3] |SLVSYNCF |LIN Slave Sync Field (Read Only)
sahilmgandhi 18:6a4db94011d3 14974 * | | |This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode.
sahilmgandhi 18:6a4db94011d3 14975 * | | |When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.
sahilmgandhi 18:6a4db94011d3 14976 * | | |0 = The current character is not at LIN sync state.
sahilmgandhi 18:6a4db94011d3 14977 * | | |1 = The current character is at LIN sync state.
sahilmgandhi 18:6a4db94011d3 14978 * | | |Note1: This bit is only valid when in LIN Slave mode (SLVEN(UART_LINCTL[0]) = 1).
sahilmgandhi 18:6a4db94011d3 14979 * | | |Note2: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 14980 * | | |Note3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header.
sahilmgandhi 18:6a4db94011d3 14981 * |[8] |BRKDETF |LIN Break Detection Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 14982 * | | |This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.
sahilmgandhi 18:6a4db94011d3 14983 * | | |0 = LIN break not detected.
sahilmgandhi 18:6a4db94011d3 14984 * | | |1 = LIN break detected.
sahilmgandhi 18:6a4db94011d3 14985 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 14986 * | | |Note2: This bit is only valid when LIN break detection function is enabled (BRKDETEN (UART_LINCTL[10]) =1).
sahilmgandhi 18:6a4db94011d3 14987 * |[9] |BITEF |Bit Error Detect Status Flag (Read Only)
sahilmgandhi 18:6a4db94011d3 14988 * | | |At TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BITEF (UART_LINSTS[9]) will be set.
sahilmgandhi 18:6a4db94011d3 14989 * | | |When occur bit error, if the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
sahilmgandhi 18:6a4db94011d3 14990 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 14991 * | | |Note2: This bit is only valid when enable bit error detection function (BITERREN (UART_LINCTL [12]) = 1).
sahilmgandhi 18:6a4db94011d3 14992 */
sahilmgandhi 18:6a4db94011d3 14993
sahilmgandhi 18:6a4db94011d3 14994 __IO uint32_t DAT; /* Offset: 0x00 UART Receive/Transmit Buffer Register */
sahilmgandhi 18:6a4db94011d3 14995 __IO uint32_t INTEN; /* Offset: 0x04 UART Interrupt Enable Register */
sahilmgandhi 18:6a4db94011d3 14996 __IO uint32_t FIFO; /* Offset: 0x08 UART FIFO Control Register */
sahilmgandhi 18:6a4db94011d3 14997 __IO uint32_t LINE; /* Offset: 0x0C UART Line Control Register */
sahilmgandhi 18:6a4db94011d3 14998 __IO uint32_t MODEM; /* Offset: 0x10 UART Modem Control Register */
sahilmgandhi 18:6a4db94011d3 14999 __IO uint32_t MODEMSTS; /* Offset: 0x14 UART Modem Status Register */
sahilmgandhi 18:6a4db94011d3 15000 __IO uint32_t FIFOSTS; /* Offset: 0x18 UART FIFO Status Register */
sahilmgandhi 18:6a4db94011d3 15001 __IO uint32_t INTSTS; /* Offset: 0x1C UART Interrupt Status Register */
sahilmgandhi 18:6a4db94011d3 15002 __IO uint32_t TOUT; /* Offset: 0x20 UART Time-out Register */
sahilmgandhi 18:6a4db94011d3 15003 __IO uint32_t BAUD; /* Offset: 0x24 UART Baud Rate Divisor Register */
sahilmgandhi 18:6a4db94011d3 15004 __IO uint32_t IRDA; /* Offset: 0x28 UART IrDA Control Register */
sahilmgandhi 18:6a4db94011d3 15005 __IO uint32_t ALTCTL; /* Offset: 0x2C UART Alternate Control/Status Register */
sahilmgandhi 18:6a4db94011d3 15006 __IO uint32_t FUNCSEL; /* Offset: 0x30 UART Function Select Register */
sahilmgandhi 18:6a4db94011d3 15007 __IO uint32_t LINCTL; /* Offset: 0x34 UART LIN Control Register */
sahilmgandhi 18:6a4db94011d3 15008 __IO uint32_t LINSTS; /* Offset: 0x38 UART LIN Status Register */
sahilmgandhi 18:6a4db94011d3 15009
sahilmgandhi 18:6a4db94011d3 15010 } UART_T;
sahilmgandhi 18:6a4db94011d3 15011
sahilmgandhi 18:6a4db94011d3 15012
sahilmgandhi 18:6a4db94011d3 15013
sahilmgandhi 18:6a4db94011d3 15014 /**
sahilmgandhi 18:6a4db94011d3 15015 @addtogroup UART_CONST UART Bit Field Definition
sahilmgandhi 18:6a4db94011d3 15016 Constant Definitions for UART Controller
sahilmgandhi 18:6a4db94011d3 15017 @{ */
sahilmgandhi 18:6a4db94011d3 15018
sahilmgandhi 18:6a4db94011d3 15019 #define UART_DAT_DAT_Pos (0) /*!< UART_T::DAT: DAT Position */
sahilmgandhi 18:6a4db94011d3 15020 #define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) /*!< UART_T::DAT: DAT Mask */
sahilmgandhi 18:6a4db94011d3 15021
sahilmgandhi 18:6a4db94011d3 15022 #define UART_INTEN_RDAIEN_Pos (0) /*!< UART_T::INTEN: RDAIEN Position */
sahilmgandhi 18:6a4db94011d3 15023 #define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) /*!< UART_T::INTEN: RDAIEN Mask */
sahilmgandhi 18:6a4db94011d3 15024
sahilmgandhi 18:6a4db94011d3 15025 #define UART_INTEN_THREIEN_Pos (1) /*!< UART_T::INTEN: THREIEN Position */
sahilmgandhi 18:6a4db94011d3 15026 #define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) /*!< UART_T::INTEN: THREIEN Mask */
sahilmgandhi 18:6a4db94011d3 15027
sahilmgandhi 18:6a4db94011d3 15028 #define UART_INTEN_RLSIEN_Pos (2) /*!< UART_T::INTEN: RLSIEN Position */
sahilmgandhi 18:6a4db94011d3 15029 #define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) /*!< UART_T::INTEN: RLSIEN Mask */
sahilmgandhi 18:6a4db94011d3 15030
sahilmgandhi 18:6a4db94011d3 15031 #define UART_INTEN_MODEMIEN_Pos (3) /*!< UART_T::INTEN: MODEMIEN Position */
sahilmgandhi 18:6a4db94011d3 15032 #define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) /*!< UART_T::INTEN: MODEMIEN Mask */
sahilmgandhi 18:6a4db94011d3 15033
sahilmgandhi 18:6a4db94011d3 15034 #define UART_INTEN_RXTOIEN_Pos (4) /*!< UART_T::INTEN: RXTOIEN Position */
sahilmgandhi 18:6a4db94011d3 15035 #define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) /*!< UART_T::INTEN: RXTOIEN Mask */
sahilmgandhi 18:6a4db94011d3 15036
sahilmgandhi 18:6a4db94011d3 15037 #define UART_INTEN_BUFERRIEN_Pos (5) /*!< UART_T::INTEN: BUFERRIEN Position */
sahilmgandhi 18:6a4db94011d3 15038 #define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos) /*!< UART_T::INTEN: BUFERRIEN Mask */
sahilmgandhi 18:6a4db94011d3 15039
sahilmgandhi 18:6a4db94011d3 15040 #define UART_INTEN_LINIEN_Pos (8) /*!< UART_T::INTEN: LINIEN Position */
sahilmgandhi 18:6a4db94011d3 15041 #define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos) /*!< UART_T::INTEN: LINIEN Mask */
sahilmgandhi 18:6a4db94011d3 15042
sahilmgandhi 18:6a4db94011d3 15043 #define UART_INTEN_WKCTSIEN_Pos (9) /*!< UART_T::INTEN: WKCTSIEN Position */
sahilmgandhi 18:6a4db94011d3 15044 #define UART_INTEN_WKCTSIEN_Msk (0x1ul << UART_INTEN_WKCTSIEN_Pos) /*!< UART_T::INTEN: WKCTSIEN Mask */
sahilmgandhi 18:6a4db94011d3 15045
sahilmgandhi 18:6a4db94011d3 15046 #define UART_INTEN_WKDATIEN_Pos (10) /*!< UART_T::INTEN: WKDATIEN Position */
sahilmgandhi 18:6a4db94011d3 15047 #define UART_INTEN_WKDATIEN_Msk (0x1ul << UART_INTEN_WKDATIEN_Pos) /*!< UART_T::INTEN: WKDATIEN Mask */
sahilmgandhi 18:6a4db94011d3 15048
sahilmgandhi 18:6a4db94011d3 15049 #define UART_INTEN_TOCNTEN_Pos (11) /*!< UART_T::INTEN: TOCNTEN Position */
sahilmgandhi 18:6a4db94011d3 15050 #define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos) /*!< UART_T::INTEN: TOCNTEN Mask */
sahilmgandhi 18:6a4db94011d3 15051
sahilmgandhi 18:6a4db94011d3 15052 #define UART_INTEN_ATORTSEN_Pos (12) /*!< UART_T::INTEN: ATORTSEN Position */
sahilmgandhi 18:6a4db94011d3 15053 #define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos) /*!< UART_T::INTEN: ATORTSEN Mask */
sahilmgandhi 18:6a4db94011d3 15054
sahilmgandhi 18:6a4db94011d3 15055 #define UART_INTEN_ATOCTSEN_Pos (13) /*!< UART_T::INTEN: ATOCTSEN Position */
sahilmgandhi 18:6a4db94011d3 15056 #define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos) /*!< UART_T::INTEN: ATOCTSEN Mask */
sahilmgandhi 18:6a4db94011d3 15057
sahilmgandhi 18:6a4db94011d3 15058 #define UART_INTEN_TXPDMAEN_Pos (14) /*!< UART_T::INTEN: TXPDMAEN Position */
sahilmgandhi 18:6a4db94011d3 15059 #define UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos) /*!< UART_T::INTEN: TXPDMAEN Mask */
sahilmgandhi 18:6a4db94011d3 15060
sahilmgandhi 18:6a4db94011d3 15061 #define UART_INTEN_RXPDMAEN_Pos (15) /*!< UART_T::INTEN: RXPDMAEN Position */
sahilmgandhi 18:6a4db94011d3 15062 #define UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos) /*!< UART_T::INTEN: RXPDMAEN Mask */
sahilmgandhi 18:6a4db94011d3 15063
sahilmgandhi 18:6a4db94011d3 15064 #define UART_INTEN_ABRIEN_Pos (18) /*!< UART_T::INTEN: ABRIEN Position */
sahilmgandhi 18:6a4db94011d3 15065 #define UART_INTEN_ABRIEN_Msk (0x1ul << UART_INTEN_ABRIEN_Pos) /*!< UART_T::INTEN: ABRIEN Mask */
sahilmgandhi 18:6a4db94011d3 15066
sahilmgandhi 18:6a4db94011d3 15067 #define UART_FIFO_RXRST_Pos (1) /*!< UART_T::FIFO: RXRST Position */
sahilmgandhi 18:6a4db94011d3 15068 #define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos) /*!< UART_T::FIFO: RXRST Mask */
sahilmgandhi 18:6a4db94011d3 15069
sahilmgandhi 18:6a4db94011d3 15070 #define UART_FIFO_TXRST_Pos (2) /*!< UART_T::FIFO: TXRST Position */
sahilmgandhi 18:6a4db94011d3 15071 #define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos) /*!< UART_T::FIFO: TXRST Mask */
sahilmgandhi 18:6a4db94011d3 15072
sahilmgandhi 18:6a4db94011d3 15073 #define UART_FIFO_RFITL_Pos (4) /*!< UART_T::FIFO: RFITL Position */
sahilmgandhi 18:6a4db94011d3 15074 #define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos) /*!< UART_T::FIFO: RFITL Mask */
sahilmgandhi 18:6a4db94011d3 15075
sahilmgandhi 18:6a4db94011d3 15076 #define UART_FIFO_RXOFF_Pos (8) /*!< UART_T::FIFO: RXOFF Position */
sahilmgandhi 18:6a4db94011d3 15077 #define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos) /*!< UART_T::FIFO: RXOFF Mask */
sahilmgandhi 18:6a4db94011d3 15078
sahilmgandhi 18:6a4db94011d3 15079 #define UART_FIFO_RTSTRGLV_Pos (16) /*!< UART_T::FIFO: RTSTRGLV Position */
sahilmgandhi 18:6a4db94011d3 15080 #define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos) /*!< UART_T::FIFO: RTSTRGLV Mask */
sahilmgandhi 18:6a4db94011d3 15081
sahilmgandhi 18:6a4db94011d3 15082 #define UART_LINE_WLS_Pos (0) /*!< UART_T::LINE: WLS Position */
sahilmgandhi 18:6a4db94011d3 15083 #define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) /*!< UART_T::LINE: WLS Mask */
sahilmgandhi 18:6a4db94011d3 15084
sahilmgandhi 18:6a4db94011d3 15085 #define UART_LINE_NSB_Pos (2) /*!< UART_T::LINE: NSB Position */
sahilmgandhi 18:6a4db94011d3 15086 #define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) /*!< UART_T::LINE: NSB Mask */
sahilmgandhi 18:6a4db94011d3 15087
sahilmgandhi 18:6a4db94011d3 15088 #define UART_LINE_PBE_Pos (3) /*!< UART_T::LINE: PBE Position */
sahilmgandhi 18:6a4db94011d3 15089 #define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) /*!< UART_T::LINE: PBE Mask */
sahilmgandhi 18:6a4db94011d3 15090
sahilmgandhi 18:6a4db94011d3 15091 #define UART_LINE_EPE_Pos (4) /*!< UART_T::LINE: EPE Position */
sahilmgandhi 18:6a4db94011d3 15092 #define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) /*!< UART_T::LINE: EPE Mask */
sahilmgandhi 18:6a4db94011d3 15093
sahilmgandhi 18:6a4db94011d3 15094 #define UART_LINE_SPE_Pos (5) /*!< UART_T::LINE: SPE Position */
sahilmgandhi 18:6a4db94011d3 15095 #define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) /*!< UART_T::LINE: SPE Mask */
sahilmgandhi 18:6a4db94011d3 15096
sahilmgandhi 18:6a4db94011d3 15097 #define UART_LINE_BCB_Pos (6) /*!< UART_T::LINE: BCB Position */
sahilmgandhi 18:6a4db94011d3 15098 #define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) /*!< UART_T::LINE: BCB Mask */
sahilmgandhi 18:6a4db94011d3 15099
sahilmgandhi 18:6a4db94011d3 15100 #define UART_MODEM_RTS_Pos (1) /*!< UART_T::MODEM: RTS Position */
sahilmgandhi 18:6a4db94011d3 15101 #define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos) /*!< UART_T::MODEM: RTS Mask */
sahilmgandhi 18:6a4db94011d3 15102
sahilmgandhi 18:6a4db94011d3 15103 #define UART_MODEM_RTSACTLV_Pos (9) /*!< UART_T::MODEM: RTSACTLV Position */
sahilmgandhi 18:6a4db94011d3 15104 #define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) /*!< UART_T::MODEM: RTSACTLV Mask */
sahilmgandhi 18:6a4db94011d3 15105
sahilmgandhi 18:6a4db94011d3 15106 #define UART_MODEM_RTSSTS_Pos (13) /*!< UART_T::MODEM: RTSSTS Position */
sahilmgandhi 18:6a4db94011d3 15107 #define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) /*!< UART_T::MODEM: RTSSTS Mask */
sahilmgandhi 18:6a4db94011d3 15108
sahilmgandhi 18:6a4db94011d3 15109 #define UART_MODEMSTS_CTSDETF_Pos (0) /*!< UART_T::MODEMSTS: CTSDETF Position */
sahilmgandhi 18:6a4db94011d3 15110 #define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos) /*!< UART_T::MODEMSTS: CTSDETF Mask */
sahilmgandhi 18:6a4db94011d3 15111
sahilmgandhi 18:6a4db94011d3 15112 #define UART_MODEMSTS_CTSSTS_Pos (4) /*!< UART_T::MODEMSTS: CTSSTS Position */
sahilmgandhi 18:6a4db94011d3 15113 #define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos) /*!< UART_T::MODEMSTS: CTSSTS Mask */
sahilmgandhi 18:6a4db94011d3 15114
sahilmgandhi 18:6a4db94011d3 15115 #define UART_MODEMSTS_CTSACTLV_Pos (8) /*!< UART_T::MODEMSTS: CTSACTLV Position */
sahilmgandhi 18:6a4db94011d3 15116 #define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos) /*!< UART_T::MODEMSTS: CTSACTLV Mask */
sahilmgandhi 18:6a4db94011d3 15117
sahilmgandhi 18:6a4db94011d3 15118 #define UART_FIFOSTS_RXOVIF_Pos (0) /*!< UART_T::FIFOSTS: RXOVIF Position */
sahilmgandhi 18:6a4db94011d3 15119 #define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) /*!< UART_T::FIFOSTS: RXOVIF Mask */
sahilmgandhi 18:6a4db94011d3 15120
sahilmgandhi 18:6a4db94011d3 15121 #define UART_FIFOSTS_ABRDIF_Pos (1) /*!< UART_T::FIFOSTS: ABRDIF Position */
sahilmgandhi 18:6a4db94011d3 15122 #define UART_FIFOSTS_ABRDIF_Msk (0x1ul << UART_FIFOSTS_ABRDIF_Pos) /*!< UART_T::FIFOSTS: ABRDIF Mask */
sahilmgandhi 18:6a4db94011d3 15123
sahilmgandhi 18:6a4db94011d3 15124 #define UART_FIFOSTS_ABRDTOIF_Pos (2) /*!< UART_T::FIFOSTS: ABRDTOIF Position */
sahilmgandhi 18:6a4db94011d3 15125 #define UART_FIFOSTS_ABRDTOIF_Msk (0x1ul << UART_FIFOSTS_ABRDTOIF_Pos) /*!< UART_T::FIFOSTS: ABRDTOIF Mask */
sahilmgandhi 18:6a4db94011d3 15126
sahilmgandhi 18:6a4db94011d3 15127 #define UART_FIFOSTS_ADDRDETF_Pos (3) /*!< UART_T::FIFOSTS: ADDRDETF Position */
sahilmgandhi 18:6a4db94011d3 15128 #define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos) /*!< UART_T::FIFOSTS: ADDRDETF Mask */
sahilmgandhi 18:6a4db94011d3 15129
sahilmgandhi 18:6a4db94011d3 15130 #define UART_FIFOSTS_PEF_Pos (4) /*!< UART_T::FIFOSTS: PEF Position */
sahilmgandhi 18:6a4db94011d3 15131 #define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) /*!< UART_T::FIFOSTS: PEF Mask */
sahilmgandhi 18:6a4db94011d3 15132
sahilmgandhi 18:6a4db94011d3 15133 #define UART_FIFOSTS_FEF_Pos (5) /*!< UART_T::FIFOSTS: FEF Position */
sahilmgandhi 18:6a4db94011d3 15134 #define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) /*!< UART_T::FIFOSTS: FEF Mask */
sahilmgandhi 18:6a4db94011d3 15135
sahilmgandhi 18:6a4db94011d3 15136 #define UART_FIFOSTS_BIF_Pos (6) /*!< UART_T::FIFOSTS: BIF Position */
sahilmgandhi 18:6a4db94011d3 15137 #define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) /*!< UART_T::FIFOSTS: BIF Mask */
sahilmgandhi 18:6a4db94011d3 15138
sahilmgandhi 18:6a4db94011d3 15139 #define UART_FIFOSTS_RXPTR_Pos (8) /*!< UART_T::FIFOSTS: RXPTR Position */
sahilmgandhi 18:6a4db94011d3 15140 #define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos) /*!< UART_T::FIFOSTS: RXPTR Mask */
sahilmgandhi 18:6a4db94011d3 15141
sahilmgandhi 18:6a4db94011d3 15142 #define UART_FIFOSTS_RXEMPTY_Pos (14) /*!< UART_T::FIFOSTS: RXEMPTY Position */
sahilmgandhi 18:6a4db94011d3 15143 #define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) /*!< UART_T::FIFOSTS: RXEMPTY Mask */
sahilmgandhi 18:6a4db94011d3 15144
sahilmgandhi 18:6a4db94011d3 15145 #define UART_FIFOSTS_RXFULL_Pos (15) /*!< UART_T::FIFOSTS: RXFULL Position */
sahilmgandhi 18:6a4db94011d3 15146 #define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) /*!< UART_T::FIFOSTS: RXFULL Mask */
sahilmgandhi 18:6a4db94011d3 15147
sahilmgandhi 18:6a4db94011d3 15148 #define UART_FIFOSTS_TXPTR_Pos (16) /*!< UART_T::FIFOSTS: TXPTR Position */
sahilmgandhi 18:6a4db94011d3 15149 #define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos) /*!< UART_T::FIFOSTS: TXPTR Mask */
sahilmgandhi 18:6a4db94011d3 15150
sahilmgandhi 18:6a4db94011d3 15151 #define UART_FIFOSTS_TXEMPTY_Pos (22) /*!< UART_T::FIFOSTS: TXEMPTY Position */
sahilmgandhi 18:6a4db94011d3 15152 #define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) /*!< UART_T::FIFOSTS: TXEMPTY Mask */
sahilmgandhi 18:6a4db94011d3 15153
sahilmgandhi 18:6a4db94011d3 15154 #define UART_FIFOSTS_TXFULL_Pos (23) /*!< UART_T::FIFOSTS: TXFULL Position */
sahilmgandhi 18:6a4db94011d3 15155 #define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) /*!< UART_T::FIFOSTS: TXFULL Mask */
sahilmgandhi 18:6a4db94011d3 15156
sahilmgandhi 18:6a4db94011d3 15157 #define UART_FIFOSTS_TXOVIF_Pos (24) /*!< UART_T::FIFOSTS: TXOVIF Position */
sahilmgandhi 18:6a4db94011d3 15158 #define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) /*!< UART_T::FIFOSTS: TXOVIF Mask */
sahilmgandhi 18:6a4db94011d3 15159
sahilmgandhi 18:6a4db94011d3 15160 #define UART_FIFOSTS_TXEMPTYF_Pos (28) /*!< UART_T::FIFOSTS: TXEMPTYF Position */
sahilmgandhi 18:6a4db94011d3 15161 #define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos) /*!< UART_T::FIFOSTS: TXEMPTYF Mask */
sahilmgandhi 18:6a4db94011d3 15162
sahilmgandhi 18:6a4db94011d3 15163 #define UART_INTSTS_RDAIF_Pos (0) /*!< UART_T::INTSTS: RDAIF Position */
sahilmgandhi 18:6a4db94011d3 15164 #define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) /*!< UART_T::INTSTS: RDAIF Mask */
sahilmgandhi 18:6a4db94011d3 15165
sahilmgandhi 18:6a4db94011d3 15166 #define UART_INTSTS_THREIF_Pos (1) /*!< UART_T::INTSTS: THREIF Position */
sahilmgandhi 18:6a4db94011d3 15167 #define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) /*!< UART_T::INTSTS: THREIF Mask */
sahilmgandhi 18:6a4db94011d3 15168
sahilmgandhi 18:6a4db94011d3 15169 #define UART_INTSTS_RLSIF_Pos (2) /*!< UART_T::INTSTS: RLSIF Position */
sahilmgandhi 18:6a4db94011d3 15170 #define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) /*!< UART_T::INTSTS: RLSIF Mask */
sahilmgandhi 18:6a4db94011d3 15171
sahilmgandhi 18:6a4db94011d3 15172 #define UART_INTSTS_MODEMIF_Pos (3) /*!< UART_T::INTSTS: MODEMIF Position */
sahilmgandhi 18:6a4db94011d3 15173 #define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos) /*!< UART_T::INTSTS: MODEMIF Mask */
sahilmgandhi 18:6a4db94011d3 15174
sahilmgandhi 18:6a4db94011d3 15175 #define UART_INTSTS_RXTOIF_Pos (4) /*!< UART_T::INTSTS: RXTOIF Position */
sahilmgandhi 18:6a4db94011d3 15176 #define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) /*!< UART_T::INTSTS: RXTOIF Mask */
sahilmgandhi 18:6a4db94011d3 15177
sahilmgandhi 18:6a4db94011d3 15178 #define UART_INTSTS_BUFERRIF_Pos (5) /*!< UART_T::INTSTS: BUFERRIF Position */
sahilmgandhi 18:6a4db94011d3 15179 #define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos) /*!< UART_T::INTSTS: BUFERRIF Mask */
sahilmgandhi 18:6a4db94011d3 15180
sahilmgandhi 18:6a4db94011d3 15181 #define UART_INTSTS_WKIF_Pos (6) /*!< UART_T::INTSTS: WKIF Position */
sahilmgandhi 18:6a4db94011d3 15182 #define UART_INTSTS_WKIF_Msk (0x1ul << UART_INTSTS_WKIF_Pos) /*!< UART_T::INTSTS: WKIF Mask */
sahilmgandhi 18:6a4db94011d3 15183
sahilmgandhi 18:6a4db94011d3 15184 #define UART_INTSTS_LINIF_Pos (7) /*!< UART_T::INTSTS: LINIF Position */
sahilmgandhi 18:6a4db94011d3 15185 #define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos) /*!< UART_T::INTSTS: LINIF Mask */
sahilmgandhi 18:6a4db94011d3 15186
sahilmgandhi 18:6a4db94011d3 15187 #define UART_INTSTS_RDAINT_Pos (8) /*!< UART_T::INTSTS: RDAINT Position */
sahilmgandhi 18:6a4db94011d3 15188 #define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos) /*!< UART_T::INTSTS: RDAINT Mask */
sahilmgandhi 18:6a4db94011d3 15189
sahilmgandhi 18:6a4db94011d3 15190 #define UART_INTSTS_THREINT_Pos (9) /*!< UART_T::INTSTS: THREINT Position */
sahilmgandhi 18:6a4db94011d3 15191 #define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos) /*!< UART_T::INTSTS: THREINT Mask */
sahilmgandhi 18:6a4db94011d3 15192
sahilmgandhi 18:6a4db94011d3 15193 #define UART_INTSTS_RLSINT_Pos (10) /*!< UART_T::INTSTS: RLSINT Position */
sahilmgandhi 18:6a4db94011d3 15194 #define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos) /*!< UART_T::INTSTS: RLSINT Mask */
sahilmgandhi 18:6a4db94011d3 15195
sahilmgandhi 18:6a4db94011d3 15196 #define UART_INTSTS_MODEMINT_Pos (11) /*!< UART_T::INTSTS: MODEMINT Position */
sahilmgandhi 18:6a4db94011d3 15197 #define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos) /*!< UART_T::INTSTS: MODEMINT Mask */
sahilmgandhi 18:6a4db94011d3 15198
sahilmgandhi 18:6a4db94011d3 15199 #define UART_INTSTS_RXTOINT_Pos (12) /*!< UART_T::INTSTS: RXTOINT Position */
sahilmgandhi 18:6a4db94011d3 15200 #define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos) /*!< UART_T::INTSTS: RXTOINT Mask */
sahilmgandhi 18:6a4db94011d3 15201
sahilmgandhi 18:6a4db94011d3 15202 #define UART_INTSTS_BUFERRINT_Pos (13) /*!< UART_T::INTSTS: BUFERRINT Position */
sahilmgandhi 18:6a4db94011d3 15203 #define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos) /*!< UART_T::INTSTS: BUFERRINT Mask */
sahilmgandhi 18:6a4db94011d3 15204
sahilmgandhi 18:6a4db94011d3 15205 #define UART_INTSTS_LININT_Pos (15) /*!< UART_T::INTSTS: LININT Position */
sahilmgandhi 18:6a4db94011d3 15206 #define UART_INTSTS_LININT_Msk (0x1ul << UART_INTSTS_LININT_Pos) /*!< UART_T::INTSTS: LININT Mask */
sahilmgandhi 18:6a4db94011d3 15207
sahilmgandhi 18:6a4db94011d3 15208 #define UART_INTSTS_CTSWKIF_Pos (16) /*!< UART_T::INTSTS: CTSWKIF Position */
sahilmgandhi 18:6a4db94011d3 15209 #define UART_INTSTS_CTSWKIF_Msk (0x1ul << UART_INTSTS_CTSWKIF_Pos) /*!< UART_T::INTSTS: CTSWKIF Mask */
sahilmgandhi 18:6a4db94011d3 15210
sahilmgandhi 18:6a4db94011d3 15211 #define UART_INTSTS_DATWKIF_Pos (17) /*!< UART_T::INTSTS: DATWKIF Position */
sahilmgandhi 18:6a4db94011d3 15212 #define UART_INTSTS_DATWKIF_Msk (0x1ul << UART_INTSTS_DATWKIF_Pos) /*!< UART_T::INTSTS: DATWKIF Mask */
sahilmgandhi 18:6a4db94011d3 15213
sahilmgandhi 18:6a4db94011d3 15214 #define UART_INTSTS_HWRLSIF_Pos (18) /*!< UART_T::INTSTS: HWRLSIF Position */
sahilmgandhi 18:6a4db94011d3 15215 #define UART_INTSTS_HWRLSIF_Msk (0x1ul << UART_INTSTS_HWRLSIF_Pos) /*!< UART_T::INTSTS: HWRLSIF Mask */
sahilmgandhi 18:6a4db94011d3 15216
sahilmgandhi 18:6a4db94011d3 15217 #define UART_INTSTS_HWMODIF_Pos (19) /*!< UART_T::INTSTS: HWMODIF Position */
sahilmgandhi 18:6a4db94011d3 15218 #define UART_INTSTS_HWMODIF_Msk (0x1ul << UART_INTSTS_HWMODIF_Pos) /*!< UART_T::INTSTS: HWMODIF Mask */
sahilmgandhi 18:6a4db94011d3 15219
sahilmgandhi 18:6a4db94011d3 15220 #define UART_INTSTS_HWTOIF_Pos (20) /*!< UART_T::INTSTS: HWTOIF Position */
sahilmgandhi 18:6a4db94011d3 15221 #define UART_INTSTS_HWTOIF_Msk (0x1ul << UART_INTSTS_HWTOIF_Pos) /*!< UART_T::INTSTS: HWTOIF Mask */
sahilmgandhi 18:6a4db94011d3 15222
sahilmgandhi 18:6a4db94011d3 15223 #define UART_INTSTS_HWBUFEIF_Pos (21) /*!< UART_T::INTSTS: HWBUFEIF Position */
sahilmgandhi 18:6a4db94011d3 15224 #define UART_INTSTS_HWBUFEIF_Msk (0x1ul << UART_INTSTS_HWBUFEIF_Pos) /*!< UART_T::INTSTS: HWBUFEIF Mask */
sahilmgandhi 18:6a4db94011d3 15225
sahilmgandhi 18:6a4db94011d3 15226 #define UART_INTSTS_HWRLSINT_Pos (26) /*!< UART_T::INTSTS: HWRLSINT Position */
sahilmgandhi 18:6a4db94011d3 15227 #define UART_INTSTS_HWRLSINT_Msk (0x1ul << UART_INTSTS_HWRLSINT_Pos) /*!< UART_T::INTSTS: HWRLSINT Mask */
sahilmgandhi 18:6a4db94011d3 15228
sahilmgandhi 18:6a4db94011d3 15229 #define UART_INTSTS_HWMODINT_Pos (27) /*!< UART_T::INTSTS: HWMODINT Position */
sahilmgandhi 18:6a4db94011d3 15230 #define UART_INTSTS_HWMODINT_Msk (0x1ul << UART_INTSTS_HWMODINT_Pos) /*!< UART_T::INTSTS: HWMODINT Mask */
sahilmgandhi 18:6a4db94011d3 15231
sahilmgandhi 18:6a4db94011d3 15232 #define UART_INTSTS_HWTOINT_Pos (28) /*!< UART_T::INTSTS: HWTOINT Position */
sahilmgandhi 18:6a4db94011d3 15233 #define UART_INTSTS_HWTOINT_Msk (0x1ul << UART_INTSTS_HWTOINT_Pos) /*!< UART_T::INTSTS: HWTOINT Mask */
sahilmgandhi 18:6a4db94011d3 15234
sahilmgandhi 18:6a4db94011d3 15235 #define UART_INTSTS_HWBUFEINT_Pos (29) /*!< UART_T::INTSTS: HWBUFEINT Position */
sahilmgandhi 18:6a4db94011d3 15236 #define UART_INTSTS_HWBUFEINT_Msk (0x1ul << UART_INTSTS_HWBUFEINT_Pos) /*!< UART_T::INTSTS: HWBUFEINT Mask */
sahilmgandhi 18:6a4db94011d3 15237
sahilmgandhi 18:6a4db94011d3 15238 #define UART_TOUT_TOIC_Pos (0) /*!< UART_T::TOUT: TOIC Position */
sahilmgandhi 18:6a4db94011d3 15239 #define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos) /*!< UART_T::TOUT: TOIC Mask */
sahilmgandhi 18:6a4db94011d3 15240
sahilmgandhi 18:6a4db94011d3 15241 #define UART_TOUT_DLY_Pos (8) /*!< UART_T::TOUT: DLY Position */
sahilmgandhi 18:6a4db94011d3 15242 #define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) /*!< UART_T::TOUT: DLY Mask */
sahilmgandhi 18:6a4db94011d3 15243
sahilmgandhi 18:6a4db94011d3 15244 #define UART_BAUD_BRD_Pos (0) /*!< UART_T::BAUD: BRD Position */
sahilmgandhi 18:6a4db94011d3 15245 #define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) /*!< UART_T::BAUD: BRD Mask */
sahilmgandhi 18:6a4db94011d3 15246
sahilmgandhi 18:6a4db94011d3 15247 #define UART_BAUD_EDIVM1_Pos (24) /*!< UART_T::BAUD: EDIVM1 Position */
sahilmgandhi 18:6a4db94011d3 15248 #define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos) /*!< UART_T::BAUD: EDIVM1 Mask */
sahilmgandhi 18:6a4db94011d3 15249
sahilmgandhi 18:6a4db94011d3 15250 #define UART_BAUD_BAUDM0_Pos (28) /*!< UART_T::BAUD: BAUDM0 Position */
sahilmgandhi 18:6a4db94011d3 15251 #define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos) /*!< UART_T::BAUD: BAUDM0 Mask */
sahilmgandhi 18:6a4db94011d3 15252
sahilmgandhi 18:6a4db94011d3 15253 #define UART_BAUD_BAUDM1_Pos (29) /*!< UART_T::BAUD: BAUDM1 Position */
sahilmgandhi 18:6a4db94011d3 15254 #define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos) /*!< UART_T::BAUD: BAUDM1 Mask */
sahilmgandhi 18:6a4db94011d3 15255
sahilmgandhi 18:6a4db94011d3 15256 #define UART_IRDA_TXEN_Pos (1) /*!< UART_T::IRDA: TXEN Position */
sahilmgandhi 18:6a4db94011d3 15257 #define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) /*!< UART_T::IRDA: TXEN Mask */
sahilmgandhi 18:6a4db94011d3 15258
sahilmgandhi 18:6a4db94011d3 15259 #define UART_IRDA_TXINV_Pos (5) /*!< UART_T::IRDA: TXINV Position */
sahilmgandhi 18:6a4db94011d3 15260 #define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) /*!< UART_T::IRDA: TXINV Mask */
sahilmgandhi 18:6a4db94011d3 15261
sahilmgandhi 18:6a4db94011d3 15262 #define UART_IRDA_RXINV_Pos (6) /*!< UART_T::IRDA: RXINV Position */
sahilmgandhi 18:6a4db94011d3 15263 #define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) /*!< UART_T::IRDA: RXINV Mask */
sahilmgandhi 18:6a4db94011d3 15264
sahilmgandhi 18:6a4db94011d3 15265 #define UART_ALTCTL_BRKFL_Pos (0) /*!< UART_T::ALTCTL: BRKFL Position */
sahilmgandhi 18:6a4db94011d3 15266 #define UART_ALTCTL_BRKFL_Msk (0xful << UART_ALTCTL_BRKFL_Pos) /*!< UART_T::ALTCTL: BRKFL Mask */
sahilmgandhi 18:6a4db94011d3 15267
sahilmgandhi 18:6a4db94011d3 15268 #define UART_ALTCTL_LINRXEN_Pos (6) /*!< UART_T::ALTCTL: LINRXEN Position */
sahilmgandhi 18:6a4db94011d3 15269 #define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos) /*!< UART_T::ALTCTL: LINRXEN Mask */
sahilmgandhi 18:6a4db94011d3 15270
sahilmgandhi 18:6a4db94011d3 15271 #define UART_ALTCTL_LINTXEN_Pos (7) /*!< UART_T::ALTCTL: LINTXEN Position */
sahilmgandhi 18:6a4db94011d3 15272 #define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos) /*!< UART_T::ALTCTL: LINTXEN Mask */
sahilmgandhi 18:6a4db94011d3 15273
sahilmgandhi 18:6a4db94011d3 15274 #define UART_ALTCTL_RS485NMM_Pos (8) /*!< UART_T::ALTCTL: RS485NMM Position */
sahilmgandhi 18:6a4db94011d3 15275 #define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) /*!< UART_T::ALTCTL: RS485NMM Mask */
sahilmgandhi 18:6a4db94011d3 15276
sahilmgandhi 18:6a4db94011d3 15277 #define UART_ALTCTL_RS485AAD_Pos (9) /*!< UART_T::ALTCTL: RS485AAD Position */
sahilmgandhi 18:6a4db94011d3 15278 #define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) /*!< UART_T::ALTCTL: RS485AAD Mask */
sahilmgandhi 18:6a4db94011d3 15279
sahilmgandhi 18:6a4db94011d3 15280 #define UART_ALTCTL_RS485AUD_Pos (10) /*!< UART_T::ALTCTL: RS485AUD Position */
sahilmgandhi 18:6a4db94011d3 15281 #define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) /*!< UART_T::ALTCTL: RS485AUD Mask */
sahilmgandhi 18:6a4db94011d3 15282
sahilmgandhi 18:6a4db94011d3 15283 #define UART_ALTCTL_ADDRDEN_Pos (15) /*!< UART_T::ALTCTL: ADDRDEN Position */
sahilmgandhi 18:6a4db94011d3 15284 #define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) /*!< UART_T::ALTCTL: ADDRDEN Mask */
sahilmgandhi 18:6a4db94011d3 15285
sahilmgandhi 18:6a4db94011d3 15286 #define UART_ALTCTL_ABRIF_Pos (17) /*!< UART_T::ALTCTL: ABRIF Position */
sahilmgandhi 18:6a4db94011d3 15287 #define UART_ALTCTL_ABRIF_Msk (0x1ul << UART_ALTCTL_ABRIF_Pos) /*!< UART_T::ALTCTL: ABRIF Mask */
sahilmgandhi 18:6a4db94011d3 15288
sahilmgandhi 18:6a4db94011d3 15289 #define UART_ALTCTL_ABRDEN_Pos (18) /*!< UART_T::ALTCTL: ABRDEN Position */
sahilmgandhi 18:6a4db94011d3 15290 #define UART_ALTCTL_ABRDEN_Msk (0x1ul << UART_ALTCTL_ABRDEN_Pos) /*!< UART_T::ALTCTL: ABRDEN Mask */
sahilmgandhi 18:6a4db94011d3 15291
sahilmgandhi 18:6a4db94011d3 15292 #define UART_ALTCTL_ABRDBITS_Pos (19) /*!< UART_T::ALTCTL: ABRDBITS Position */
sahilmgandhi 18:6a4db94011d3 15293 #define UART_ALTCTL_ABRDBITS_Msk (0x3ul << UART_ALTCTL_ABRDBITS_Pos) /*!< UART_T::ALTCTL: ABRDBITS Mask */
sahilmgandhi 18:6a4db94011d3 15294
sahilmgandhi 18:6a4db94011d3 15295 #define UART_ALTCTL_ADDRMV_Pos (24) /*!< UART_T::ALTCTL: ADDRMV Position */
sahilmgandhi 18:6a4db94011d3 15296 #define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos) /*!< UART_T::ALTCTL: ADDRMV Mask */
sahilmgandhi 18:6a4db94011d3 15297
sahilmgandhi 18:6a4db94011d3 15298 #define UART_FUNCSEL_FUNCSEL_Pos (0) /*!< UART_T::FUNCSEL: FUNCSEL Position */
sahilmgandhi 18:6a4db94011d3 15299 #define UART_FUNCSEL_FUNCSEL_Msk (0x3ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_T::FUNCSEL: FUNCSEL Mask */
sahilmgandhi 18:6a4db94011d3 15300
sahilmgandhi 18:6a4db94011d3 15301 #define UART_LINCTL_SLVEN_Pos (0) /*!< UART_T::LINCTL: SLVEN Position */
sahilmgandhi 18:6a4db94011d3 15302 #define UART_LINCTL_SLVEN_Msk (0x1ul << UART_LINCTL_SLVEN_Pos) /*!< UART_T::LINCTL: SLVEN Mask */
sahilmgandhi 18:6a4db94011d3 15303
sahilmgandhi 18:6a4db94011d3 15304 #define UART_LINCTL_SLVHDEN_Pos (1) /*!< UART_T::LINCTL: SLVHDEN Position */
sahilmgandhi 18:6a4db94011d3 15305 #define UART_LINCTL_SLVHDEN_Msk (0x1ul << UART_LINCTL_SLVHDEN_Pos) /*!< UART_T::LINCTL: SLVHDEN Mask */
sahilmgandhi 18:6a4db94011d3 15306
sahilmgandhi 18:6a4db94011d3 15307 #define UART_LINCTL_SLVAREN_Pos (2) /*!< UART_T::LINCTL: SLVAREN Position */
sahilmgandhi 18:6a4db94011d3 15308 #define UART_LINCTL_SLVAREN_Msk (0x1ul << UART_LINCTL_SLVAREN_Pos) /*!< UART_T::LINCTL: SLVAREN Mask */
sahilmgandhi 18:6a4db94011d3 15309
sahilmgandhi 18:6a4db94011d3 15310 #define UART_LINCTL_SLVDUEN_Pos (3) /*!< UART_T::LINCTL: SLVDUEN Position */
sahilmgandhi 18:6a4db94011d3 15311 #define UART_LINCTL_SLVDUEN_Msk (0x1ul << UART_LINCTL_SLVDUEN_Pos) /*!< UART_T::LINCTL: SLVDUEN Mask */
sahilmgandhi 18:6a4db94011d3 15312
sahilmgandhi 18:6a4db94011d3 15313 #define UART_LINCTL_MUTE_Pos (4) /*!< UART_T::LINCTL: MUTE Position */
sahilmgandhi 18:6a4db94011d3 15314 #define UART_LINCTL_MUTE_Msk (0x1ul << UART_LINCTL_MUTE_Pos) /*!< UART_T::LINCTL: MUTE Mask */
sahilmgandhi 18:6a4db94011d3 15315
sahilmgandhi 18:6a4db94011d3 15316 #define UART_LINCTL_SENDH_Pos (8) /*!< UART_T::LINCTL: SENDH Position */
sahilmgandhi 18:6a4db94011d3 15317 #define UART_LINCTL_SENDH_Msk (0x1ul << UART_LINCTL_SENDH_Pos) /*!< UART_T::LINCTL: SENDH Mask */
sahilmgandhi 18:6a4db94011d3 15318
sahilmgandhi 18:6a4db94011d3 15319 #define UART_LINCTL_IDPEN_Pos (9) /*!< UART_T::LINCTL: IDPEN Position */
sahilmgandhi 18:6a4db94011d3 15320 #define UART_LINCTL_IDPEN_Msk (0x1ul << UART_LINCTL_IDPEN_Pos) /*!< UART_T::LINCTL: IDPEN Mask */
sahilmgandhi 18:6a4db94011d3 15321
sahilmgandhi 18:6a4db94011d3 15322 #define UART_LINCTL_BRKDETEN_Pos (10) /*!< UART_T::LINCTL: BRKDETEN Position */
sahilmgandhi 18:6a4db94011d3 15323 #define UART_LINCTL_BRKDETEN_Msk (0x1ul << UART_LINCTL_BRKDETEN_Pos) /*!< UART_T::LINCTL: BRKDETEN Mask */
sahilmgandhi 18:6a4db94011d3 15324
sahilmgandhi 18:6a4db94011d3 15325 #define UART_LINCTL_RXOFF_Pos (11) /*!< UART_T::LINCTL: RXOFF Position */
sahilmgandhi 18:6a4db94011d3 15326 #define UART_LINCTL_RXOFF_Msk (0x1ul << UART_LINCTL_RXOFF_Pos) /*!< UART_T::LINCTL: RXOFF Mask */
sahilmgandhi 18:6a4db94011d3 15327
sahilmgandhi 18:6a4db94011d3 15328 #define UART_LINCTL_BITERREN_Pos (12) /*!< UART_T::LINCTL: BITERREN Position */
sahilmgandhi 18:6a4db94011d3 15329 #define UART_LINCTL_BITERREN_Msk (0x1ul << UART_LINCTL_BITERREN_Pos) /*!< UART_T::LINCTL: BITERREN Mask */
sahilmgandhi 18:6a4db94011d3 15330
sahilmgandhi 18:6a4db94011d3 15331 #define UART_LINCTL_BRKFL_Pos (16) /*!< UART_T::LINCTL: BRKFL Position */
sahilmgandhi 18:6a4db94011d3 15332 #define UART_LINCTL_BRKFL_Msk (0xful << UART_LINCTL_BRKFL_Pos) /*!< UART_T::LINCTL: BRKFL Mask */
sahilmgandhi 18:6a4db94011d3 15333
sahilmgandhi 18:6a4db94011d3 15334 #define UART_LINCTL_BSL_Pos (20) /*!< UART_T::LINCTL: BSL Position */
sahilmgandhi 18:6a4db94011d3 15335 #define UART_LINCTL_BSL_Msk (0x3ul << UART_LINCTL_BSL_Pos) /*!< UART_T::LINCTL: BSL Mask */
sahilmgandhi 18:6a4db94011d3 15336
sahilmgandhi 18:6a4db94011d3 15337 #define UART_LINCTL_HSEL_Pos (22) /*!< UART_T::LINCTL: HSEL Position */
sahilmgandhi 18:6a4db94011d3 15338 #define UART_LINCTL_HSEL_Msk (0x3ul << UART_LINCTL_HSEL_Pos) /*!< UART_T::LINCTL: HSEL Mask */
sahilmgandhi 18:6a4db94011d3 15339
sahilmgandhi 18:6a4db94011d3 15340 #define UART_LINCTL_PID_Pos (24) /*!< UART_T::LINCTL: PID Position */
sahilmgandhi 18:6a4db94011d3 15341 #define UART_LINCTL_PID_Msk (0xfful << UART_LINCTL_PID_Pos) /*!< UART_T::LINCTL: PID Mask */
sahilmgandhi 18:6a4db94011d3 15342
sahilmgandhi 18:6a4db94011d3 15343 #define UART_LINSTS_SLVHDETF_Pos (0) /*!< UART_T::LINSTS: SLVHDETF Position */
sahilmgandhi 18:6a4db94011d3 15344 #define UART_LINSTS_SLVHDETF_Msk (0x1ul << UART_LINSTS_SLVHDETF_Pos) /*!< UART_T::LINSTS: SLVHDETF Mask */
sahilmgandhi 18:6a4db94011d3 15345
sahilmgandhi 18:6a4db94011d3 15346 #define UART_LINSTS_SLVHEF_Pos (1) /*!< UART_T::LINSTS: SLVHEF Position */
sahilmgandhi 18:6a4db94011d3 15347 #define UART_LINSTS_SLVHEF_Msk (0x1ul << UART_LINSTS_SLVHEF_Pos) /*!< UART_T::LINSTS: SLVHEF Mask */
sahilmgandhi 18:6a4db94011d3 15348
sahilmgandhi 18:6a4db94011d3 15349 #define UART_LINSTS_SLVIDPEF_Pos (2) /*!< UART_T::LINSTS: SLVIDPEF Position */
sahilmgandhi 18:6a4db94011d3 15350 #define UART_LINSTS_SLVIDPEF_Msk (0x1ul << UART_LINSTS_SLVIDPEF_Pos) /*!< UART_T::LINSTS: SLVIDPEF Mask */
sahilmgandhi 18:6a4db94011d3 15351
sahilmgandhi 18:6a4db94011d3 15352 #define UART_LINSTS_SLVSYNCF_Pos (3) /*!< UART_T::LINSTS: SLVSYNCF Position */
sahilmgandhi 18:6a4db94011d3 15353 #define UART_LINSTS_SLVSYNCF_Msk (0x1ul << UART_LINSTS_SLVSYNCF_Pos) /*!< UART_T::LINSTS: SLVSYNCF Mask */
sahilmgandhi 18:6a4db94011d3 15354
sahilmgandhi 18:6a4db94011d3 15355 #define UART_LINSTS_BRKDETF_Pos (8) /*!< UART_T::LINSTS: BRKDETF Position */
sahilmgandhi 18:6a4db94011d3 15356 #define UART_LINSTS_BRKDETF_Msk (0x1ul << UART_LINSTS_BRKDETF_Pos) /*!< UART_T::LINSTS: BRKDETF Mask */
sahilmgandhi 18:6a4db94011d3 15357
sahilmgandhi 18:6a4db94011d3 15358 #define UART_LINSTS_BITEF_Pos (9) /*!< UART_T::LINSTS: BITEF Position */
sahilmgandhi 18:6a4db94011d3 15359 #define UART_LINSTS_BITEF_Msk (0x1ul << UART_LINSTS_BITEF_Pos) /*!< UART_T::LINSTS: BITEF Mask */
sahilmgandhi 18:6a4db94011d3 15360
sahilmgandhi 18:6a4db94011d3 15361
sahilmgandhi 18:6a4db94011d3 15362 /**@}*/ /* UART_CONST */
sahilmgandhi 18:6a4db94011d3 15363 /**@}*/ /* end of UART register group */
sahilmgandhi 18:6a4db94011d3 15364
sahilmgandhi 18:6a4db94011d3 15365
sahilmgandhi 18:6a4db94011d3 15366 /*---------------------- Universal Serial Bus Controller -------------------------*/
sahilmgandhi 18:6a4db94011d3 15367 /**
sahilmgandhi 18:6a4db94011d3 15368 @addtogroup USB Universal Serial Bus Controller(USB)
sahilmgandhi 18:6a4db94011d3 15369 Memory Mapped Structure for USB Controller
sahilmgandhi 18:6a4db94011d3 15370 @{ */
sahilmgandhi 18:6a4db94011d3 15371
sahilmgandhi 18:6a4db94011d3 15372 /**
sahilmgandhi 18:6a4db94011d3 15373 * @brief USBD endpoints register
sahilmgandhi 18:6a4db94011d3 15374 */
sahilmgandhi 18:6a4db94011d3 15375
sahilmgandhi 18:6a4db94011d3 15376 typedef struct
sahilmgandhi 18:6a4db94011d3 15377 {
sahilmgandhi 18:6a4db94011d3 15378
sahilmgandhi 18:6a4db94011d3 15379
sahilmgandhi 18:6a4db94011d3 15380 /**
sahilmgandhi 18:6a4db94011d3 15381 * @var USBD_EP_T::BUFSEG
sahilmgandhi 18:6a4db94011d3 15382 * Offset: 0x500/0x510/0x520/0x530/0x540/0x550/0x560/0x570 Endpoint 0~7 Buffer Segmentation Register
sahilmgandhi 18:6a4db94011d3 15383 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 15384 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 15385 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 15386 * |[8:3] |BUFSEG |Endpoint Buffer Segmentation
sahilmgandhi 18:6a4db94011d3 15387 * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is
sahilmgandhi 18:6a4db94011d3 15388 * | | |USB_SRAM address + { BUFSEG[8:3], 3'b000}
sahilmgandhi 18:6a4db94011d3 15389 * | | |Where the USB_SRAM address = USBD_BA+0x100h.
sahilmgandhi 18:6a4db94011d3 15390 * | | |Refer to the section 5.4.4.7 for the endpoint SRAM structure and its description.
sahilmgandhi 18:6a4db94011d3 15391 * @var USBD_EP_T::MXPLD
sahilmgandhi 18:6a4db94011d3 15392 * Offset: 0x504/0x514/0x524/0x534/0x544/0x554/0x564/0x574 Endpoint 0~7 Maximal Payload Register
sahilmgandhi 18:6a4db94011d3 15393 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 15394 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 15395 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 15396 * |[8:0] |MXPLD |Maximal Payload
sahilmgandhi 18:6a4db94011d3 15397 * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token).
sahilmgandhi 18:6a4db94011d3 15398 * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
sahilmgandhi 18:6a4db94011d3 15399 * | | |(1) When the register is written by CPU,
sahilmgandhi 18:6a4db94011d3 15400 * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.
sahilmgandhi 18:6a4db94011d3 15401 * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.
sahilmgandhi 18:6a4db94011d3 15402 * | | |(2) When the register is read by CPU,
sahilmgandhi 18:6a4db94011d3 15403 * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host
sahilmgandhi 18:6a4db94011d3 15404 * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host.
sahilmgandhi 18:6a4db94011d3 15405 * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
sahilmgandhi 18:6a4db94011d3 15406 * @var USBD_EP_T::CFG
sahilmgandhi 18:6a4db94011d3 15407 * Offset: 0x508/0x518/0x528/0x538/0x548/0x558/0x568/0x578 Endpoint 0~7 Configuration Register
sahilmgandhi 18:6a4db94011d3 15408 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 15409 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 15410 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 15411 * |[3:0] |EPNUM |Endpoint Number
sahilmgandhi 18:6a4db94011d3 15412 * | | |These bits are used to define the endpoint number of the current endpoint.
sahilmgandhi 18:6a4db94011d3 15413 * |[4] |ISOCH |Isochronous Endpoint
sahilmgandhi 18:6a4db94011d3 15414 * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake.
sahilmgandhi 18:6a4db94011d3 15415 * | | |0 = No Isochronous endpoint.
sahilmgandhi 18:6a4db94011d3 15416 * | | |1 = Isochronous endpoint.
sahilmgandhi 18:6a4db94011d3 15417 * |[6:5] |STATE |Endpoint STATE
sahilmgandhi 18:6a4db94011d3 15418 * | | |00 = Endpoint is Disabled.
sahilmgandhi 18:6a4db94011d3 15419 * | | |01 = Out endpoint.
sahilmgandhi 18:6a4db94011d3 15420 * | | |10 = IN endpoint.
sahilmgandhi 18:6a4db94011d3 15421 * | | |11 = Undefined.
sahilmgandhi 18:6a4db94011d3 15422 * |[7] |DSQSYNC |Data Sequence Synchronization
sahilmgandhi 18:6a4db94011d3 15423 * | | |0 = DATA0 PID.
sahilmgandhi 18:6a4db94011d3 15424 * | | |1 = DATA1 PID.
sahilmgandhi 18:6a4db94011d3 15425 * | | |Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction.
sahilmgandhi 18:6a4db94011d3 15426 * | | |Hardware will toggle automatically in IN token base on the bit.
sahilmgandhi 18:6a4db94011d3 15427 * |[9] |CSTALL |Clear STALL Response
sahilmgandhi 18:6a4db94011d3 15428 * | | |0 = Disable the device to clear the STALL handshake in setup stage.
sahilmgandhi 18:6a4db94011d3 15429 * | | |1 = Clear the device to response STALL handshake in setup stage.
sahilmgandhi 18:6a4db94011d3 15430 * @var USBD_EP_T::CFGP
sahilmgandhi 18:6a4db94011d3 15431 * Offset: 0x50C/0x51C/0x52C/0x53C/0x54C/0x55C/0x56C/0x57C Endpoint 0~7 Set Stall and Clear In/Out Ready Control Register
sahilmgandhi 18:6a4db94011d3 15432 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 15433 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 15434 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 15435 * |[0] |CLRRDY |Clear Ready
sahilmgandhi 18:6a4db94011d3 15436 * | | |When the USB_MXPLD register is set by user, it means that the endpoint is ready to transmit or receive data.
sahilmgandhi 18:6a4db94011d3 15437 * | | |If the user wants to turn off this transaction before the transaction start, users can set this bit to 1 to turn it off and it will be cleared to 0 automatically.
sahilmgandhi 18:6a4db94011d3 15438 * | | |For IN token, write 1 to clear the IN token had ready to transmit the data to USB.
sahilmgandhi 18:6a4db94011d3 15439 * | | |For OUT token, write 1 to clear the OUT token had ready to receive the data from USB.
sahilmgandhi 18:6a4db94011d3 15440 * | | |This bit is write 1 only and is always 0 when it is read back.
sahilmgandhi 18:6a4db94011d3 15441 * |[1] |SSTALL |Set STALL
sahilmgandhi 18:6a4db94011d3 15442 * | | |0 = Disable the device to response STALL.
sahilmgandhi 18:6a4db94011d3 15443 * | | |1 = Set the device to respond STALL automatically.
sahilmgandhi 18:6a4db94011d3 15444 */
sahilmgandhi 18:6a4db94011d3 15445
sahilmgandhi 18:6a4db94011d3 15446 __IO uint32_t BUFSEG; /* Offset: 0x500/0x510/0x520/0x530/0x540/0x550/0x560/0x570 Endpoint 0~7 Buffer Segmentation Register */
sahilmgandhi 18:6a4db94011d3 15447 __IO uint32_t MXPLD; /* Offset: 0x504/0x514/0x524/0x534/0x544/0x554/0x564/0x574 Endpoint 0~7 Maximal Payload Register */
sahilmgandhi 18:6a4db94011d3 15448 __IO uint32_t CFG; /* Offset: 0x508/0x518/0x528/0x538/0x548/0x558/0x568/0x578 Endpoint 0~7 Configuration Register */
sahilmgandhi 18:6a4db94011d3 15449 __IO uint32_t CFGP; /* Offset: 0x50C/0x51C/0x52C/0x53C/0x54C/0x55C/0x56C/0x57C Endpoint 0~7 Set Stall and Clear In/Out Ready Control Register */
sahilmgandhi 18:6a4db94011d3 15450
sahilmgandhi 18:6a4db94011d3 15451 } USBD_EP_T;
sahilmgandhi 18:6a4db94011d3 15452
sahilmgandhi 18:6a4db94011d3 15453
sahilmgandhi 18:6a4db94011d3 15454
sahilmgandhi 18:6a4db94011d3 15455
sahilmgandhi 18:6a4db94011d3 15456
sahilmgandhi 18:6a4db94011d3 15457 typedef struct
sahilmgandhi 18:6a4db94011d3 15458 {
sahilmgandhi 18:6a4db94011d3 15459
sahilmgandhi 18:6a4db94011d3 15460
sahilmgandhi 18:6a4db94011d3 15461 /**
sahilmgandhi 18:6a4db94011d3 15462 * @var USBD_T::INTEN
sahilmgandhi 18:6a4db94011d3 15463 * Offset: 0x00 USB Interrupt Enable Register
sahilmgandhi 18:6a4db94011d3 15464 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 15465 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 15466 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 15467 * |[0] |BUSIEN |Bus Event Interrupt Enable
sahilmgandhi 18:6a4db94011d3 15468 * | | |0 = BUS event interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 15469 * | | |1 = BUS event interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 15470 * |[1] |USBIEN |USB Event Interrupt Enable
sahilmgandhi 18:6a4db94011d3 15471 * | | |0 = USB event interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 15472 * | | |1 = USB event interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 15473 * |[2] |VBDETIEN |VBUS Detection Interrupt Enable
sahilmgandhi 18:6a4db94011d3 15474 * | | |0 = Floating detection Interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 15475 * | | |1 = Floating detection Interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 15476 * |[3] |NEVWKIEN |USB No-Event-Wake-Up Interrupt Enable
sahilmgandhi 18:6a4db94011d3 15477 * | | |0 = No-Event-Wake-up Interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 15478 * | | |1 = No-Event-Wake-up Interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 15479 * |[8] |WKEN |Wake-Up Function Enable
sahilmgandhi 18:6a4db94011d3 15480 * | | |0 = USB wake-up function Disabled.
sahilmgandhi 18:6a4db94011d3 15481 * | | |1 = USB wake-up function Enabled.
sahilmgandhi 18:6a4db94011d3 15482 * |[15] |INNAKEN |Active NAK Function And Its Status In IN Token
sahilmgandhi 18:6a4db94011d3 15483 * | | |0 = When device responds NAK after receiving IN token, IN NAK status will not be
sahilmgandhi 18:6a4db94011d3 15484 * | | | updated to USBD_EPSTS register, so that the USB interrupt event will not be asserted.
sahilmgandhi 18:6a4db94011d3 15485 * | | |1 = IN NAK status will be updated to USBD_EPSTS register and the USB interrupt event
sahilmgandhi 18:6a4db94011d3 15486 * | | | will be asserted, when the device responds NAK after receiving IN token.
sahilmgandhi 18:6a4db94011d3 15487 * @var USBD_T::INTSTS
sahilmgandhi 18:6a4db94011d3 15488 * Offset: 0x04 USB Interrupt Event Status Register
sahilmgandhi 18:6a4db94011d3 15489 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 15490 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 15491 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 15492 * |[0] |BUSIF |BUS Interrupt Status
sahilmgandhi 18:6a4db94011d3 15493 * | | |The BUS event means that there is one of the suspense or the resume function in the bus.
sahilmgandhi 18:6a4db94011d3 15494 * | | |0 = No BUS event occurred.
sahilmgandhi 18:6a4db94011d3 15495 * | | |1 = Bus event occurred; check USB_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USB_INTSTS[0].
sahilmgandhi 18:6a4db94011d3 15496 * |[1] |USBIF |USB Event Interrupt Status
sahilmgandhi 18:6a4db94011d3 15497 * | | |The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.
sahilmgandhi 18:6a4db94011d3 15498 * | | |0 = No USB event occurred.
sahilmgandhi 18:6a4db94011d3 15499 * | | |1 = USB event occurred, check EPSTS0~7 to know which kind of USB event occurred.
sahilmgandhi 18:6a4db94011d3 15500 * | | |Cleared by write 1 to USB_INTSTS[1] or EPEVT0~7 and SETUP (USB_INTSTS[31]).
sahilmgandhi 18:6a4db94011d3 15501 * |[2] |VBDETIF |VBUS Detection Interrupt Status
sahilmgandhi 18:6a4db94011d3 15502 * | | |0 = There is not attached/detached event in the USB.
sahilmgandhi 18:6a4db94011d3 15503 * | | |1 = There is attached/detached event in the USB bus and it is cleared by write 1 to USB_INTSTS[2].
sahilmgandhi 18:6a4db94011d3 15504 * |[3] |NEVWKIF |USB No-Event-Wake-Up Interrupt Status
sahilmgandhi 18:6a4db94011d3 15505 * | | |0 = No Wake-up event occurred.
sahilmgandhi 18:6a4db94011d3 15506 * | | |1 = Wake-up event occurred, cleared by write 1 to USB_INTSTS[3].
sahilmgandhi 18:6a4db94011d3 15507 * |[16] |EPEVT0 |Endpoint 0's USB Event Status
sahilmgandhi 18:6a4db94011d3 15508 * | | |0 = No event occurred on endpoint 0.
sahilmgandhi 18:6a4db94011d3 15509 * | | |1 = USB event occurred on Endpoint 0, check USB_EPSTS[10:8] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[16] or USB_INTSTS[1].
sahilmgandhi 18:6a4db94011d3 15510 * |[17] |EPEVT1 |Endpoint 1's USB Event Status
sahilmgandhi 18:6a4db94011d3 15511 * | | |0 = No event occurred on endpoint 1.
sahilmgandhi 18:6a4db94011d3 15512 * | | |1 = USB event occurred on Endpoint 1, check USB_EPSTS[13:11] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[17] or USB_INTSTS[1].
sahilmgandhi 18:6a4db94011d3 15513 * |[18] |EPEVT2 |Endpoint 2's USB Event Status
sahilmgandhi 18:6a4db94011d3 15514 * | | |0 = No event occurred on endpoint 2.
sahilmgandhi 18:6a4db94011d3 15515 * | | |1 = USB event occurred on Endpoint 2, check USB_EPSTS[16:14] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[18] or USB_INTSTS[1].
sahilmgandhi 18:6a4db94011d3 15516 * |[19] |EPEVT3 |Endpoint 3's USB Event Status
sahilmgandhi 18:6a4db94011d3 15517 * | | |0 = No event occurred on endpoint 3.
sahilmgandhi 18:6a4db94011d3 15518 * | | |1 = USB event occurred on Endpoint 3, check USB_EPSTS[19:17] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[19] or USB_INTSTS[1].
sahilmgandhi 18:6a4db94011d3 15519 * |[20] |EPEVT4 |Endpoint 4's USB Event Status
sahilmgandhi 18:6a4db94011d3 15520 * | | |0 = No event occurred on endpoint 4.
sahilmgandhi 18:6a4db94011d3 15521 * | | |1 = USB event occurred on Endpoint 4, check USB_EPSTS[22:20] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[20] or USB_INTSTS[1].
sahilmgandhi 18:6a4db94011d3 15522 * |[21] |EPEVT5 |Endpoint 5's USB Event Status
sahilmgandhi 18:6a4db94011d3 15523 * | | |0 = No event occurred on endpoint 5.
sahilmgandhi 18:6a4db94011d3 15524 * | | |1 = USB event occurred on Endpoint 5, check USB_EPSTS[25:23] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[21] or USB_INTSTS[1].
sahilmgandhi 18:6a4db94011d3 15525 * |[22] |EPEVT6 |Endpoint 6's USB Event Status
sahilmgandhi 18:6a4db94011d3 15526 * | | |0 = No event occurred on endpoint 6.
sahilmgandhi 18:6a4db94011d3 15527 * | | |1 = USB event occurred on Endpoint 6, check USB_EPSTS[28:26] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[22] or USB_INTSTS[1].
sahilmgandhi 18:6a4db94011d3 15528 * |[23] |EPEVT7 |Endpoint 7's USB Event Status
sahilmgandhi 18:6a4db94011d3 15529 * | | |0 = No event occurred on endpoint 7.
sahilmgandhi 18:6a4db94011d3 15530 * | | |1 = USB event occurred on Endpoint 7, check USB_EPSTS[31:29] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[23] or USB_INTSTS[1].
sahilmgandhi 18:6a4db94011d3 15531 * |[31] |SETUP |Setup Event Status
sahilmgandhi 18:6a4db94011d3 15532 * | | |0 = No Setup event.
sahilmgandhi 18:6a4db94011d3 15533 * | | |1 = SETUP event occurred, cleared by write 1 to USB_INTSTS[31].
sahilmgandhi 18:6a4db94011d3 15534 * @var USBD_T::FADDR
sahilmgandhi 18:6a4db94011d3 15535 * Offset: 0x08 USB Device Function Address Register
sahilmgandhi 18:6a4db94011d3 15536 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 15537 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 15538 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 15539 * |[6:0] |FADDR |USB Device Function Address
sahilmgandhi 18:6a4db94011d3 15540 * @var USBD_T::EPSTS
sahilmgandhi 18:6a4db94011d3 15541 * Offset: 0x0C USB Endpoint Status Register
sahilmgandhi 18:6a4db94011d3 15542 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 15543 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 15544 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 15545 * |[7] |OV |Overrun
sahilmgandhi 18:6a4db94011d3 15546 * | | |It indicates that the received data is over the maximum payload number or not.
sahilmgandhi 18:6a4db94011d3 15547 * | | |0 = No overrun.
sahilmgandhi 18:6a4db94011d3 15548 * | | |1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes.
sahilmgandhi 18:6a4db94011d3 15549 * |[10:8] |EPSTS0 |Endpoint 0 Bus Status
sahilmgandhi 18:6a4db94011d3 15550 * | | |These bits are used to indicate the current status of this endpoint
sahilmgandhi 18:6a4db94011d3 15551 * | | |000 = In ACK.
sahilmgandhi 18:6a4db94011d3 15552 * | | |001 = In NAK.
sahilmgandhi 18:6a4db94011d3 15553 * | | |010 = Out Packet Data0 ACK.
sahilmgandhi 18:6a4db94011d3 15554 * | | |110 = Out Packet Data1 ACK.
sahilmgandhi 18:6a4db94011d3 15555 * | | |011 = Setup ACK.
sahilmgandhi 18:6a4db94011d3 15556 * | | |111 = Isochronous transfer end.
sahilmgandhi 18:6a4db94011d3 15557 * |[13:11] |EPSTS1 |Endpoint 1 Bus Status
sahilmgandhi 18:6a4db94011d3 15558 * | | |These bits are used to indicate the current status of this endpoint
sahilmgandhi 18:6a4db94011d3 15559 * | | |000 = In ACK.
sahilmgandhi 18:6a4db94011d3 15560 * | | |001 = In NAK.
sahilmgandhi 18:6a4db94011d3 15561 * | | |010 = Out Packet Data0 ACK.
sahilmgandhi 18:6a4db94011d3 15562 * | | |110 = Out Packet Data1 ACK.
sahilmgandhi 18:6a4db94011d3 15563 * | | |011 = Setup ACK.
sahilmgandhi 18:6a4db94011d3 15564 * | | |111 = Isochronous transfer end.
sahilmgandhi 18:6a4db94011d3 15565 * |[16:14] |EPSTS2 |Endpoint 2 Bus Status
sahilmgandhi 18:6a4db94011d3 15566 * | | |These bits are used to indicate the current status of this endpoint
sahilmgandhi 18:6a4db94011d3 15567 * | | |000 = In ACK.
sahilmgandhi 18:6a4db94011d3 15568 * | | |001 = In NAK.
sahilmgandhi 18:6a4db94011d3 15569 * | | |010 = Out Packet Data0 ACK.
sahilmgandhi 18:6a4db94011d3 15570 * | | |110 = Out Packet Data1 ACK.
sahilmgandhi 18:6a4db94011d3 15571 * | | |011 = Setup ACK.
sahilmgandhi 18:6a4db94011d3 15572 * | | |111 = Isochronous transfer end.
sahilmgandhi 18:6a4db94011d3 15573 * |[19:17] |EPSTS3 |Endpoint 3 Bus Status
sahilmgandhi 18:6a4db94011d3 15574 * | | |These bits are used to indicate the current status of this endpoint
sahilmgandhi 18:6a4db94011d3 15575 * | | |000 = In ACK.
sahilmgandhi 18:6a4db94011d3 15576 * | | |001 = In NAK.
sahilmgandhi 18:6a4db94011d3 15577 * | | |010 = Out Packet Data0 ACK.
sahilmgandhi 18:6a4db94011d3 15578 * | | |110 = Out Packet Data1 ACK.
sahilmgandhi 18:6a4db94011d3 15579 * | | |011 = Setup ACK.
sahilmgandhi 18:6a4db94011d3 15580 * | | |111 = Isochronous transfer end.
sahilmgandhi 18:6a4db94011d3 15581 * |[22:20] |EPSTS4 |Endpoint 4 Bus Status
sahilmgandhi 18:6a4db94011d3 15582 * | | |These bits are used to indicate the current status of this endpoint
sahilmgandhi 18:6a4db94011d3 15583 * | | |000 = In ACK.
sahilmgandhi 18:6a4db94011d3 15584 * | | |001 = In NAK.
sahilmgandhi 18:6a4db94011d3 15585 * | | |010 = Out Packet Data0 ACK.
sahilmgandhi 18:6a4db94011d3 15586 * | | |110 = Out Packet Data1 ACK.
sahilmgandhi 18:6a4db94011d3 15587 * | | |011 = Setup ACK.
sahilmgandhi 18:6a4db94011d3 15588 * | | |111 = Isochronous transfer end.
sahilmgandhi 18:6a4db94011d3 15589 * |[25:23] |EPSTS5 |Endpoint 5 Bus Status
sahilmgandhi 18:6a4db94011d3 15590 * | | |These bits are used to indicate the current status of this endpoint
sahilmgandhi 18:6a4db94011d3 15591 * | | |000 = In ACK.
sahilmgandhi 18:6a4db94011d3 15592 * | | |001 = In NAK.
sahilmgandhi 18:6a4db94011d3 15593 * | | |010 = Out Packet Data0 ACK.
sahilmgandhi 18:6a4db94011d3 15594 * | | |110 = Out Packet Data1 ACK.
sahilmgandhi 18:6a4db94011d3 15595 * | | |011 = Setup ACK.
sahilmgandhi 18:6a4db94011d3 15596 * | | |111 = Isochronous transfer end.
sahilmgandhi 18:6a4db94011d3 15597 * |[28:26] |EPSTS6 |Endpoint 6 Bus Status
sahilmgandhi 18:6a4db94011d3 15598 * | | |These bits are used to indicate the current status of this endpoint
sahilmgandhi 18:6a4db94011d3 15599 * | | |000 = In ACK.
sahilmgandhi 18:6a4db94011d3 15600 * | | |001 = In NAK.
sahilmgandhi 18:6a4db94011d3 15601 * | | |010 = Out Packet Data0 ACK.
sahilmgandhi 18:6a4db94011d3 15602 * | | |110 = Out Packet Data1 ACK.
sahilmgandhi 18:6a4db94011d3 15603 * | | |011 = Setup ACK.
sahilmgandhi 18:6a4db94011d3 15604 * | | |111 = Isochronous transfer end.
sahilmgandhi 18:6a4db94011d3 15605 * |[31:29] |EPSTS7 |Endpoint 7 Bus Status
sahilmgandhi 18:6a4db94011d3 15606 * | | |These bits are used to indicate the current status of this endpoint
sahilmgandhi 18:6a4db94011d3 15607 * | | |000 = In ACK.
sahilmgandhi 18:6a4db94011d3 15608 * | | |001 = In NAK.
sahilmgandhi 18:6a4db94011d3 15609 * | | |010 = Out Packet Data0 ACK.
sahilmgandhi 18:6a4db94011d3 15610 * | | |110 = Out Packet Data1 ACK.
sahilmgandhi 18:6a4db94011d3 15611 * | | |011 = Setup ACK.
sahilmgandhi 18:6a4db94011d3 15612 * | | |111 = Isochronous transfer end.
sahilmgandhi 18:6a4db94011d3 15613 * @var USBD_T::ATTR
sahilmgandhi 18:6a4db94011d3 15614 * Offset: 0x10 USB Bus Status and Attribution Register
sahilmgandhi 18:6a4db94011d3 15615 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 15616 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 15617 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 15618 * |[0] |USBRST |USB Reset Status
sahilmgandhi 18:6a4db94011d3 15619 * | | |0 = Bus no reset.
sahilmgandhi 18:6a4db94011d3 15620 * | | |1 = Bus reset when SE0 (single-ended 0) is presented more than 2.5us.
sahilmgandhi 18:6a4db94011d3 15621 * | | |Note: This bit is read only.
sahilmgandhi 18:6a4db94011d3 15622 * |[1] |SUSPEND |Suspend Status
sahilmgandhi 18:6a4db94011d3 15623 * | | |0 = Bus no suspend.
sahilmgandhi 18:6a4db94011d3 15624 * | | |1 = Bus idle more than 3ms, either cable is plugged off or host is sleeping.
sahilmgandhi 18:6a4db94011d3 15625 * | | |Note: This bit is read only.
sahilmgandhi 18:6a4db94011d3 15626 * |[2] |RESUME |Resume Status
sahilmgandhi 18:6a4db94011d3 15627 * | | |0 = No bus resume.
sahilmgandhi 18:6a4db94011d3 15628 * | | |1 = Resume from suspend.
sahilmgandhi 18:6a4db94011d3 15629 * | | |Note: This bit is read only.
sahilmgandhi 18:6a4db94011d3 15630 * |[3] |TOUT |Time-Out Status
sahilmgandhi 18:6a4db94011d3 15631 * | | |0 = No time-out.
sahilmgandhi 18:6a4db94011d3 15632 * | | |1 = No Bus response more than 18 bits time.
sahilmgandhi 18:6a4db94011d3 15633 * | | |Note: This bit is read only.
sahilmgandhi 18:6a4db94011d3 15634 * |[4] |PHYEN |PHY Transceiver Function Enable
sahilmgandhi 18:6a4db94011d3 15635 * | | |0 = PHY transceiver function Disabled.
sahilmgandhi 18:6a4db94011d3 15636 * | | |1 = PHY transceiver function Enabled.
sahilmgandhi 18:6a4db94011d3 15637 * |[5] |RWAKEUP |Remote Wake-Up
sahilmgandhi 18:6a4db94011d3 15638 * | | |0 = Release the USB bus from K state.
sahilmgandhi 18:6a4db94011d3 15639 * | | |1 = Force USB bus to K (USB_D+ low, USB_D- high) state, used for remote wake-up.
sahilmgandhi 18:6a4db94011d3 15640 * |[7] |USBEN |USB Controller Enable
sahilmgandhi 18:6a4db94011d3 15641 * | | |0 = USB Controller Disabled.
sahilmgandhi 18:6a4db94011d3 15642 * | | |1 = USB Controller Enabled.
sahilmgandhi 18:6a4db94011d3 15643 * |[8] |DPPUEN |Pull-Up Resistor On USB_D+ Enable
sahilmgandhi 18:6a4db94011d3 15644 * | | |0 = Pull-up resistor in USB_D+ pin Disabled.
sahilmgandhi 18:6a4db94011d3 15645 * | | |1 = Pull-up resistor in USB_D+ pin Enabled.
sahilmgandhi 18:6a4db94011d3 15646 * |[9] |PWRDN |Power Down PHY Transceiver, Low Active (M45xD/M45xC Only)
sahilmgandhi 18:6a4db94011d3 15647 * | | |0 = Power down related circuits of PHY transceiver.
sahilmgandhi 18:6a4db94011d3 15648 * | | |1 = Turn on related circuits of PHY transceiver.
sahilmgandhi 18:6a4db94011d3 15649 * |[10] |BYTEM |CPU Access USB SRAM Size Mode Selection
sahilmgandhi 18:6a4db94011d3 15650 * | | |0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only.
sahilmgandhi 18:6a4db94011d3 15651 * | | |1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only.
sahilmgandhi 18:6a4db94011d3 15652 * @var USBD_T::VBUSDET
sahilmgandhi 18:6a4db94011d3 15653 * Offset: 0x14 USB Device VBUS Detection Register
sahilmgandhi 18:6a4db94011d3 15654 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 15655 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 15656 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 15657 * |[0] |FLDET |Device VBUS Detected
sahilmgandhi 18:6a4db94011d3 15658 * | | |0 = Controller is not attached into the USB host.
sahilmgandhi 18:6a4db94011d3 15659 * | | |1 =Controller is attached into the BUS.
sahilmgandhi 18:6a4db94011d3 15660 * @var USBD_T::STBUFSEG
sahilmgandhi 18:6a4db94011d3 15661 * Offset: 0x18 Setup Token Buffer Segmentation Register
sahilmgandhi 18:6a4db94011d3 15662 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 15663 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 15664 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 15665 * |[8:3] |STBUFSEG |Setup Token Buffer Segmentation
sahilmgandhi 18:6a4db94011d3 15666 * | | |It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is
sahilmgandhi 18:6a4db94011d3 15667 * | | |USB_SRAM address + {STBUFSEG[8:3], 3'b000}
sahilmgandhi 18:6a4db94011d3 15668 * | | |Where the USB_SRAM address = USBD_BA+0x100h.
sahilmgandhi 18:6a4db94011d3 15669 * | | |Note: It is used for SETUP token only.
sahilmgandhi 18:6a4db94011d3 15670 * @var USBD_T::SE0
sahilmgandhi 18:6a4db94011d3 15671 * Offset: 0x90 USB Drive SE0 Control Register
sahilmgandhi 18:6a4db94011d3 15672 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 15673 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 15674 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 15675 * |[0] |DRVSE0 |Drive Single Ended Zero In USB Bus
sahilmgandhi 18:6a4db94011d3 15676 * | | |The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.
sahilmgandhi 18:6a4db94011d3 15677 * | | |0 = None.
sahilmgandhi 18:6a4db94011d3 15678 * | | |1 = Force USB PHY transceiver to drive SE0.
sahilmgandhi 18:6a4db94011d3 15679 * @var USBD_T::EP
sahilmgandhi 18:6a4db94011d3 15680 * Offset: 0x500 ~ 0x57C USB End Point 0 ~ 7 Configuration Register
sahilmgandhi 18:6a4db94011d3 15681 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 15682 */
sahilmgandhi 18:6a4db94011d3 15683
sahilmgandhi 18:6a4db94011d3 15684 __IO uint32_t INTEN; /* Offset: 0x00 USB Interrupt Enable Register */
sahilmgandhi 18:6a4db94011d3 15685 __IO uint32_t INTSTS; /* Offset: 0x04 USB Interrupt Event Status Register */
sahilmgandhi 18:6a4db94011d3 15686 __IO uint32_t FADDR; /* Offset: 0x08 USB Device Function Address Register */
sahilmgandhi 18:6a4db94011d3 15687 __I uint32_t EPSTS; /* Offset: 0x0C USB Endpoint Status Register */
sahilmgandhi 18:6a4db94011d3 15688 __IO uint32_t ATTR; /* Offset: 0x10 USB Bus Status and Attribution Register */
sahilmgandhi 18:6a4db94011d3 15689 __I uint32_t VBUSDET; /* Offset: 0x14 USB Device VBUS Detection Register */
sahilmgandhi 18:6a4db94011d3 15690 __IO uint32_t STBUFSEG; /* Offset: 0x18 Setup Token Buffer Segmentation Register */
sahilmgandhi 18:6a4db94011d3 15691 __I uint32_t RESERVE0[29];
sahilmgandhi 18:6a4db94011d3 15692 __IO uint32_t SE0; /* Offset: 0x90 USB Drive SE0 Control Register */
sahilmgandhi 18:6a4db94011d3 15693 __I uint32_t RESERVE1[283];
sahilmgandhi 18:6a4db94011d3 15694 USBD_EP_T EP[8]; /* Offset: 0x500 ~ 0x57C USB End Point 0 ~ 7 Configuration Register */
sahilmgandhi 18:6a4db94011d3 15695
sahilmgandhi 18:6a4db94011d3 15696 } USBD_T;
sahilmgandhi 18:6a4db94011d3 15697
sahilmgandhi 18:6a4db94011d3 15698
sahilmgandhi 18:6a4db94011d3 15699
sahilmgandhi 18:6a4db94011d3 15700 /**
sahilmgandhi 18:6a4db94011d3 15701 @addtogroup USB_CONST USB Bit Field Definition
sahilmgandhi 18:6a4db94011d3 15702 Constant Definitions for USB Controller
sahilmgandhi 18:6a4db94011d3 15703 @{ */
sahilmgandhi 18:6a4db94011d3 15704
sahilmgandhi 18:6a4db94011d3 15705 #define USBD_INTEN_BUSIEN_Pos (0) /*!< USBD_T::INTEN: BUSIEN Position */
sahilmgandhi 18:6a4db94011d3 15706 #define USBD_INTEN_BUSIEN_Msk (0x1ul << USBD_INTEN_BUSIEN_Pos) /*!< USBD_T::INTEN: BUSIEN Mask */
sahilmgandhi 18:6a4db94011d3 15707
sahilmgandhi 18:6a4db94011d3 15708 #define USBD_INTEN_USBIEN_Pos (1) /*!< USBD_T::INTEN: USBIEN Position */
sahilmgandhi 18:6a4db94011d3 15709 #define USBD_INTEN_USBIEN_Msk (0x1ul << USBD_INTEN_USBIEN_Pos) /*!< USBD_T::INTEN: USBIEN Mask */
sahilmgandhi 18:6a4db94011d3 15710
sahilmgandhi 18:6a4db94011d3 15711 #define USBD_INTEN_VBDETIEN_Pos (2) /*!< USBD_T::INTEN: VBDETIEN Position */
sahilmgandhi 18:6a4db94011d3 15712 #define USBD_INTEN_VBDETIEN_Msk (0x1ul << USBD_INTEN_VBDETIEN_Pos) /*!< USBD_T::INTEN: VBDETIEN Mask */
sahilmgandhi 18:6a4db94011d3 15713
sahilmgandhi 18:6a4db94011d3 15714 #define USBD_INTEN_NEVWKIEN_Pos (3) /*!< USBD_T::INTEN: NEVWKIEN Position */
sahilmgandhi 18:6a4db94011d3 15715 #define USBD_INTEN_NEVWKIEN_Msk (0x1ul << USBD_INTEN_NEVWKIEN_Pos) /*!< USBD_T::INTEN: NEVWKIEN Mask */
sahilmgandhi 18:6a4db94011d3 15716
sahilmgandhi 18:6a4db94011d3 15717 #define USBD_INTEN_WKEN_Pos (8) /*!< USBD_T::INTEN: WKEN Position */
sahilmgandhi 18:6a4db94011d3 15718 #define USBD_INTEN_WKEN_Msk (0x1ul << USBD_INTEN_WKEN_Pos) /*!< USBD_T::INTEN: WKEN Mask */
sahilmgandhi 18:6a4db94011d3 15719
sahilmgandhi 18:6a4db94011d3 15720 #define USBD_INTEN_INNAKEN_Pos (15) /*!< USBD_T::INTEN: INNAKEN Position */
sahilmgandhi 18:6a4db94011d3 15721 #define USBD_INTEN_INNAKEN_Msk (0x1ul << USBD_INTEN_INNAKEN_Pos) /*!< USBD_T::INTEN: INNAKEN Mask */
sahilmgandhi 18:6a4db94011d3 15722
sahilmgandhi 18:6a4db94011d3 15723 #define USBD_INTSTS_BUSIF_Pos (0) /*!< USBD_T::INTSTS: BUSIF Position */
sahilmgandhi 18:6a4db94011d3 15724 #define USBD_INTSTS_BUSIF_Msk (0x1ul << USBD_INTSTS_BUSIF_Pos) /*!< USBD_T::INTSTS: BUSIF Mask */
sahilmgandhi 18:6a4db94011d3 15725
sahilmgandhi 18:6a4db94011d3 15726 #define USBD_INTSTS_USBIF_Pos (1) /*!< USBD_T::INTSTS: USBIF Position */
sahilmgandhi 18:6a4db94011d3 15727 #define USBD_INTSTS_USBIF_Msk (0x1ul << USBD_INTSTS_USBIF_Pos) /*!< USBD_T::INTSTS: USBIF Mask */
sahilmgandhi 18:6a4db94011d3 15728
sahilmgandhi 18:6a4db94011d3 15729 #define USBD_INTSTS_VBDETIF_Pos (2) /*!< USBD_T::INTSTS: VBDETIF Position */
sahilmgandhi 18:6a4db94011d3 15730 #define USBD_INTSTS_VBDETIF_Msk (0x1ul << USBD_INTSTS_VBDETIF_Pos) /*!< USBD_T::INTSTS: VBDETIF Mask */
sahilmgandhi 18:6a4db94011d3 15731
sahilmgandhi 18:6a4db94011d3 15732 #define USBD_INTSTS_NEVWKIF_Pos (3) /*!< USBD_T::INTSTS: NEVWKIF Position */
sahilmgandhi 18:6a4db94011d3 15733 #define USBD_INTSTS_NEVWKIF_Msk (0x1ul << USBD_INTSTS_NEVWKIF_Pos) /*!< USBD_T::INTSTS: NEVWKIF Mask */
sahilmgandhi 18:6a4db94011d3 15734
sahilmgandhi 18:6a4db94011d3 15735 #define USBD_INTSTS_EPEVT0_Pos (16) /*!< USBD_T::INTSTS: EPEVT0 Position */
sahilmgandhi 18:6a4db94011d3 15736 #define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) /*!< USBD_T::INTSTS: EPEVT0 Mask */
sahilmgandhi 18:6a4db94011d3 15737
sahilmgandhi 18:6a4db94011d3 15738 #define USBD_INTSTS_EPEVT1_Pos (17) /*!< USBD_T::INTSTS: EPEVT1 Position */
sahilmgandhi 18:6a4db94011d3 15739 #define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) /*!< USBD_T::INTSTS: EPEVT1 Mask */
sahilmgandhi 18:6a4db94011d3 15740
sahilmgandhi 18:6a4db94011d3 15741 #define USBD_INTSTS_EPEVT2_Pos (18) /*!< USBD_T::INTSTS: EPEVT2 Position */
sahilmgandhi 18:6a4db94011d3 15742 #define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) /*!< USBD_T::INTSTS: EPEVT2 Mask */
sahilmgandhi 18:6a4db94011d3 15743
sahilmgandhi 18:6a4db94011d3 15744 #define USBD_INTSTS_EPEVT3_Pos (19) /*!< USBD_T::INTSTS: EPEVT3 Position */
sahilmgandhi 18:6a4db94011d3 15745 #define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) /*!< USBD_T::INTSTS: EPEVT3 Mask */
sahilmgandhi 18:6a4db94011d3 15746
sahilmgandhi 18:6a4db94011d3 15747 #define USBD_INTSTS_EPEVT4_Pos (20) /*!< USBD_T::INTSTS: EPEVT4 Position */
sahilmgandhi 18:6a4db94011d3 15748 #define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) /*!< USBD_T::INTSTS: EPEVT4 Mask */
sahilmgandhi 18:6a4db94011d3 15749
sahilmgandhi 18:6a4db94011d3 15750 #define USBD_INTSTS_EPEVT5_Pos (21) /*!< USBD_T::INTSTS: EPEVT5 Position */
sahilmgandhi 18:6a4db94011d3 15751 #define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) /*!< USBD_T::INTSTS: EPEVT5 Mask */
sahilmgandhi 18:6a4db94011d3 15752
sahilmgandhi 18:6a4db94011d3 15753 #define USBD_INTSTS_EPEVT6_Pos (22) /*!< USBD_T::INTSTS: EPEVT6 Position */
sahilmgandhi 18:6a4db94011d3 15754 #define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos) /*!< USBD_T::INTSTS: EPEVT6 Mask */
sahilmgandhi 18:6a4db94011d3 15755
sahilmgandhi 18:6a4db94011d3 15756 #define USBD_INTSTS_EPEVT7_Pos (23) /*!< USBD_T::INTSTS: EPEVT7 Position */
sahilmgandhi 18:6a4db94011d3 15757 #define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos) /*!< USBD_T::INTSTS: EPEVT7 Mask */
sahilmgandhi 18:6a4db94011d3 15758
sahilmgandhi 18:6a4db94011d3 15759 #define USBD_INTSTS_SETUP_Pos (31) /*!< USBD_T::INTSTS: SETUP Position */
sahilmgandhi 18:6a4db94011d3 15760 #define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) /*!< USBD_T::INTSTS: SETUP Mask */
sahilmgandhi 18:6a4db94011d3 15761
sahilmgandhi 18:6a4db94011d3 15762 #define USBD_FADDR_FADDR_Pos (0) /*!< USBD_T::FADDR: FADDR Position */
sahilmgandhi 18:6a4db94011d3 15763 #define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /*!< USBD_T::FADDR: FADDR Mask */
sahilmgandhi 18:6a4db94011d3 15764
sahilmgandhi 18:6a4db94011d3 15765 #define USBD_EPSTS_OV_Pos (7) /*!< USBD_T::EPSTS: OV Position */
sahilmgandhi 18:6a4db94011d3 15766 #define USBD_EPSTS_OV_Msk (0x1ul << USBD_EPSTS_OV_Pos) /*!< USBD_T::EPSTS: OV Mask */
sahilmgandhi 18:6a4db94011d3 15767
sahilmgandhi 18:6a4db94011d3 15768 #define USBD_EPSTS_EPSTS0_Pos (8) /*!< USBD_T::EPSTS: EPSTS0 Position */
sahilmgandhi 18:6a4db94011d3 15769 #define USBD_EPSTS_EPSTS0_Msk (0x7ul << USBD_EPSTS_EPSTS0_Pos) /*!< USBD_T::EPSTS: EPSTS0 Mask */
sahilmgandhi 18:6a4db94011d3 15770
sahilmgandhi 18:6a4db94011d3 15771 #define USBD_EPSTS_EPSTS1_Pos (11) /*!< USBD_T::EPSTS: EPSTS1 Position */
sahilmgandhi 18:6a4db94011d3 15772 #define USBD_EPSTS_EPSTS1_Msk (0x7ul << USBD_EPSTS_EPSTS1_Pos) /*!< USBD_T::EPSTS: EPSTS1 Mask */
sahilmgandhi 18:6a4db94011d3 15773
sahilmgandhi 18:6a4db94011d3 15774 #define USBD_EPSTS_EPSTS2_Pos (14) /*!< USBD_T::EPSTS: EPSTS2 Position */
sahilmgandhi 18:6a4db94011d3 15775 #define USBD_EPSTS_EPSTS2_Msk (0x7ul << USBD_EPSTS_EPSTS2_Pos) /*!< USBD_T::EPSTS: EPSTS2 Mask */
sahilmgandhi 18:6a4db94011d3 15776
sahilmgandhi 18:6a4db94011d3 15777 #define USBD_EPSTS_EPSTS3_Pos (17) /*!< USBD_T::EPSTS: EPSTS3 Position */
sahilmgandhi 18:6a4db94011d3 15778 #define USBD_EPSTS_EPSTS3_Msk (0x7ul << USBD_EPSTS_EPSTS3_Pos) /*!< USBD_T::EPSTS: EPSTS3 Mask */
sahilmgandhi 18:6a4db94011d3 15779
sahilmgandhi 18:6a4db94011d3 15780 #define USBD_EPSTS_EPSTS4_Pos (20) /*!< USBD_T::EPSTS: EPSTS4 Position */
sahilmgandhi 18:6a4db94011d3 15781 #define USBD_EPSTS_EPSTS4_Msk (0x7ul << USBD_EPSTS_EPSTS4_Pos) /*!< USBD_T::EPSTS: EPSTS4 Mask */
sahilmgandhi 18:6a4db94011d3 15782
sahilmgandhi 18:6a4db94011d3 15783 #define USBD_EPSTS_EPSTS5_Pos (23) /*!< USBD_T::EPSTS: EPSTS5 Position */
sahilmgandhi 18:6a4db94011d3 15784 #define USBD_EPSTS_EPSTS5_Msk (0x7ul << USBD_EPSTS_EPSTS5_Pos) /*!< USBD_T::EPSTS: EPSTS5 Mask */
sahilmgandhi 18:6a4db94011d3 15785
sahilmgandhi 18:6a4db94011d3 15786 #define USBD_EPSTS_EPSTS6_Pos (26) /*!< USBD_T::EPSTS: EPSTS6 Position */
sahilmgandhi 18:6a4db94011d3 15787 #define USBD_EPSTS_EPSTS6_Msk (0x7ul << USBD_EPSTS_EPSTS6_Pos) /*!< USBD_T::EPSTS: EPSTS6 Mask */
sahilmgandhi 18:6a4db94011d3 15788
sahilmgandhi 18:6a4db94011d3 15789 #define USBD_EPSTS_EPSTS7_Pos (29) /*!< USBD_T::EPSTS: EPSTS7 Position */
sahilmgandhi 18:6a4db94011d3 15790 #define USBD_EPSTS_EPSTS7_Msk (0x7ul << USBD_EPSTS_EPSTS7_Pos) /*!< USBD_T::EPSTS: EPSTS7 Mask */
sahilmgandhi 18:6a4db94011d3 15791
sahilmgandhi 18:6a4db94011d3 15792 #define USBD_ATTR_USBRST_Pos (0) /*!< USBD_T::ATTR: USBRST Position */
sahilmgandhi 18:6a4db94011d3 15793 #define USBD_ATTR_USBRST_Msk (0x1ul << USBD_ATTR_USBRST_Pos) /*!< USBD_T::ATTR: USBRST Mask */
sahilmgandhi 18:6a4db94011d3 15794
sahilmgandhi 18:6a4db94011d3 15795 #define USBD_ATTR_SUSPEND_Pos (1) /*!< USBD_T::ATTR: SUSPEND Position */
sahilmgandhi 18:6a4db94011d3 15796 #define USBD_ATTR_SUSPEND_Msk (0x1ul << USBD_ATTR_SUSPEND_Pos) /*!< USBD_T::ATTR: SUSPEND Mask */
sahilmgandhi 18:6a4db94011d3 15797
sahilmgandhi 18:6a4db94011d3 15798 #define USBD_ATTR_RESUME_Pos (2) /*!< USBD_T::ATTR: RESUME Position */
sahilmgandhi 18:6a4db94011d3 15799 #define USBD_ATTR_RESUME_Msk (0x1ul << USBD_ATTR_RESUME_Pos) /*!< USBD_T::ATTR: RESUME Mask */
sahilmgandhi 18:6a4db94011d3 15800
sahilmgandhi 18:6a4db94011d3 15801 #define USBD_ATTR_TOUT_Pos (3) /*!< USBD_T::ATTR: TOUT Position */
sahilmgandhi 18:6a4db94011d3 15802 #define USBD_ATTR_TOUT_Msk (0x1ul << USBD_ATTR_TOUT_Pos) /*!< USBD_T::ATTR: TOUT Mask */
sahilmgandhi 18:6a4db94011d3 15803
sahilmgandhi 18:6a4db94011d3 15804 #define USBD_ATTR_PHYEN_Pos (4) /*!< USBD_T::ATTR: PHYEN Position */
sahilmgandhi 18:6a4db94011d3 15805 #define USBD_ATTR_PHYEN_Msk (0x1ul << USBD_ATTR_PHYEN_Pos) /*!< USBD_T::ATTR: PHYEN Mask */
sahilmgandhi 18:6a4db94011d3 15806
sahilmgandhi 18:6a4db94011d3 15807 #define USBD_ATTR_RWAKEUP_Pos (5) /*!< USBD_T::ATTR: RWAKEUP Position */
sahilmgandhi 18:6a4db94011d3 15808 #define USBD_ATTR_RWAKEUP_Msk (0x1ul << USBD_ATTR_RWAKEUP_Pos) /*!< USBD_T::ATTR: RWAKEUP Mask */
sahilmgandhi 18:6a4db94011d3 15809
sahilmgandhi 18:6a4db94011d3 15810 #define USBD_ATTR_USBEN_Pos (7) /*!< USBD_T::ATTR: USBEN Position */
sahilmgandhi 18:6a4db94011d3 15811 #define USBD_ATTR_USBEN_Msk (0x1ul << USBD_ATTR_USBEN_Pos) /*!< USBD_T::ATTR: USBEN Mask */
sahilmgandhi 18:6a4db94011d3 15812
sahilmgandhi 18:6a4db94011d3 15813 #define USBD_ATTR_DPPUEN_Pos (8) /*!< USBD_T::ATTR: DPPUEN Position */
sahilmgandhi 18:6a4db94011d3 15814 #define USBD_ATTR_DPPUEN_Msk (0x1ul << USBD_ATTR_DPPUEN_Pos) /*!< USBD_T::ATTR: DPPUEN Mask */
sahilmgandhi 18:6a4db94011d3 15815
sahilmgandhi 18:6a4db94011d3 15816 #define USBD_ATTR_PWRDN_Pos (9) /*!< USBD_T::ATTR: PWRDN Position */
sahilmgandhi 18:6a4db94011d3 15817 #define USBD_ATTR_PWRDN_Msk (0x1ul << USBD_ATTR_PWRDN_Pos) /*!< USBD_T::ATTR: PWRDN Mask */
sahilmgandhi 18:6a4db94011d3 15818
sahilmgandhi 18:6a4db94011d3 15819 #define USBD_ATTR_BYTEM_Pos (10) /*!< USBD_T::ATTR: BYTEM Position */
sahilmgandhi 18:6a4db94011d3 15820 #define USBD_ATTR_BYTEM_Msk (0x1ul << USBD_ATTR_BYTEM_Pos) /*!< USBD_T::ATTR: BYTEM Mask */
sahilmgandhi 18:6a4db94011d3 15821
sahilmgandhi 18:6a4db94011d3 15822 #define USBD_VBUSDET_VBUSDET_Pos (0) /*!< USBD_T::VBUSDET: VBUSDET Position */
sahilmgandhi 18:6a4db94011d3 15823 #define USBD_VBUSDET_VBUSDET_Msk (0x1ul << USBD_VBUSDET_VBUSDET_Pos) /*!< USBD_T::VBUSDET: VBUSDET Mask */
sahilmgandhi 18:6a4db94011d3 15824
sahilmgandhi 18:6a4db94011d3 15825 #define USBD_STBUFSEG_STBUFSEG_Pos (3) /*!< USBD_T::STBUFSEG: STBUFSEG Position */
sahilmgandhi 18:6a4db94011d3 15826 #define USBD_STBUFSEG_STBUFSEG_Msk (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos) /*!< USBD_T::STBUFSEG: STBUFSEG Mask */
sahilmgandhi 18:6a4db94011d3 15827
sahilmgandhi 18:6a4db94011d3 15828 #define USBD_SE0_SE0_Pos (0) /*!< USBD_T::SE0: SE0 Position */
sahilmgandhi 18:6a4db94011d3 15829 #define USBD_SE0_SE0_Msk (0x1ul << USBD_SE0_SE0_Pos) /*!< USBD_T::SE0: SE0 Mask */
sahilmgandhi 18:6a4db94011d3 15830
sahilmgandhi 18:6a4db94011d3 15831 #define USBD_BUFSEG_BUFSEG_Pos (3) /*!< USBD_EP_T::BUFSEG: BUFSEG Position */
sahilmgandhi 18:6a4db94011d3 15832 #define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) /*!< USBD_EP_T::BUFSEG: BUFSEG Mask */
sahilmgandhi 18:6a4db94011d3 15833
sahilmgandhi 18:6a4db94011d3 15834 #define USBD_MXPLD_MXPLD_Pos (0) /*!< USBD_EP_T::MXPLD: MXPLD Position */
sahilmgandhi 18:6a4db94011d3 15835 #define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) /*!< USBD_EP_T::MXPLD: MXPLD Mask */
sahilmgandhi 18:6a4db94011d3 15836
sahilmgandhi 18:6a4db94011d3 15837 #define USBD_CFG_EPNUM_Pos (0) /*!< USBD_EP_T::CFG: EPNUM Position */
sahilmgandhi 18:6a4db94011d3 15838 #define USBD_CFG_EPNUM_Msk (0xful << USBD_CFG_EPNUM_Pos) /*!< USBD_EP_T::CFG: EPNUM Mask */
sahilmgandhi 18:6a4db94011d3 15839
sahilmgandhi 18:6a4db94011d3 15840 #define USBD_CFG_ISOCH_Pos (4) /*!< USBD_EP_T::CFG: ISOCH Position */
sahilmgandhi 18:6a4db94011d3 15841 #define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) /*!< USBD_EP_T::CFG: ISOCH Mask */
sahilmgandhi 18:6a4db94011d3 15842
sahilmgandhi 18:6a4db94011d3 15843 #define USBD_CFG_STATE_Pos (5) /*!< USBD_EP_T::CFG: STATE Position */
sahilmgandhi 18:6a4db94011d3 15844 #define USBD_CFG_STATE_Msk (0x3ul << USBD_CFG_STATE_Pos) /*!< USBD_EP_T::CFG: STATE Mask */
sahilmgandhi 18:6a4db94011d3 15845
sahilmgandhi 18:6a4db94011d3 15846 #define USBD_CFG_DSQSYNC_Pos (7) /*!< USBD_EP_T::CFG: DSQSYNC Position */
sahilmgandhi 18:6a4db94011d3 15847 #define USBD_CFG_DSQSYNC_Msk (0x1ul << USBD_CFG_DSQSYNC_Pos) /*!< USBD_EP_T::CFG: DSQSYNC Mask */
sahilmgandhi 18:6a4db94011d3 15848
sahilmgandhi 18:6a4db94011d3 15849 #define USBD_CFG_CSTALL_Pos (9) /*!< USBD_EP_T::CFG: CSTALL Position */
sahilmgandhi 18:6a4db94011d3 15850 #define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) /*!< USBD_EP_T::CFG: CSTALL Mask */
sahilmgandhi 18:6a4db94011d3 15851
sahilmgandhi 18:6a4db94011d3 15852 #define USBD_CFGP_CLRRDY_Pos (0) /*!< USBD_EP_T::CFGP: CLRRDY Position */
sahilmgandhi 18:6a4db94011d3 15853 #define USBD_CFGP_CLRRDY_Msk (0x1ul << USBD_CFGP_CLRRDY_Pos) /*!< USBD_EP_T::CFGP: CLRRDY Mask */
sahilmgandhi 18:6a4db94011d3 15854
sahilmgandhi 18:6a4db94011d3 15855 #define USBD_CFGP_SSTALL_Pos (1) /*!< USBD_EP_T::CFGP: SSTALL Position */
sahilmgandhi 18:6a4db94011d3 15856 #define USBD_CFGP_SSTALL_Msk (0x1ul << USBD_CFGP_SSTALL_Pos) /*!< USBD_EP_T::CFGP: SSTALL Mask */
sahilmgandhi 18:6a4db94011d3 15857
sahilmgandhi 18:6a4db94011d3 15858 /**@}*/ /* USB_CONST */
sahilmgandhi 18:6a4db94011d3 15859 /**@}*/ /* end of USB register group */
sahilmgandhi 18:6a4db94011d3 15860
sahilmgandhi 18:6a4db94011d3 15861
sahilmgandhi 18:6a4db94011d3 15862 /*---------------------- USB Host Controller -------------------------*/
sahilmgandhi 18:6a4db94011d3 15863 /**
sahilmgandhi 18:6a4db94011d3 15864 @addtogroup USBH USB Host Controller(USBH)
sahilmgandhi 18:6a4db94011d3 15865 Memory Mapped Structure for USBH Controller
sahilmgandhi 18:6a4db94011d3 15866 @{ */
sahilmgandhi 18:6a4db94011d3 15867
sahilmgandhi 18:6a4db94011d3 15868
sahilmgandhi 18:6a4db94011d3 15869 typedef struct
sahilmgandhi 18:6a4db94011d3 15870 {
sahilmgandhi 18:6a4db94011d3 15871
sahilmgandhi 18:6a4db94011d3 15872
sahilmgandhi 18:6a4db94011d3 15873
sahilmgandhi 18:6a4db94011d3 15874
sahilmgandhi 18:6a4db94011d3 15875 /**
sahilmgandhi 18:6a4db94011d3 15876 * @var USBH_T::HcRevision
sahilmgandhi 18:6a4db94011d3 15877 * Offset: 0x00 Host Controller Revision Register
sahilmgandhi 18:6a4db94011d3 15878 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 15879 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 15880 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 15881 * |[7:0] |REV |Revision Number
sahilmgandhi 18:6a4db94011d3 15882 * | | |Indicates the Open HCI Specification revision number implemented by the Hardware.
sahilmgandhi 18:6a4db94011d3 15883 * | | |Host Controller supports 1.1 specification.
sahilmgandhi 18:6a4db94011d3 15884 * | | |(X.Y = XYh).
sahilmgandhi 18:6a4db94011d3 15885 * @var USBH_T::HcControl
sahilmgandhi 18:6a4db94011d3 15886 * Offset: 0x04 Host Controller Control Register
sahilmgandhi 18:6a4db94011d3 15887 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 15888 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 15889 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 15890 * |[1:0] |CBSR |Control Bulk Service Ratio
sahilmgandhi 18:6a4db94011d3 15891 * | | |This specifies the service ratio between Control and Bulk EDs.
sahilmgandhi 18:6a4db94011d3 15892 * | | |Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs.
sahilmgandhi 18:6a4db94011d3 15893 * | | |The internal count will be retained when crossing the frame boundary.
sahilmgandhi 18:6a4db94011d3 15894 * | | |In case of reset, HCD is responsible for restoring this.
sahilmgandhi 18:6a4db94011d3 15895 * | | |Value.
sahilmgandhi 18:6a4db94011d3 15896 * | | |00 = Number of Control EDs over Bulk EDs served is 1:1.
sahilmgandhi 18:6a4db94011d3 15897 * | | |01 = Number of Control EDs over Bulk EDs served is 2:1.
sahilmgandhi 18:6a4db94011d3 15898 * | | |10 = Number of Control EDs over Bulk EDs served is 3:1.
sahilmgandhi 18:6a4db94011d3 15899 * | | |11 = Number of Control EDs over Bulk EDs served is 4:1.
sahilmgandhi 18:6a4db94011d3 15900 * |[2] |PLE |Periodic List Enable Bit
sahilmgandhi 18:6a4db94011d3 15901 * | | |When set, this bit enables processing of the Periodic (interrupt and Isochronous) list.
sahilmgandhi 18:6a4db94011d3 15902 * | | |The Host Controller checks this bit prior to attempting any periodic transfers in a frame.
sahilmgandhi 18:6a4db94011d3 15903 * | | |0 = Disable the processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame).
sahilmgandhi 18:6a4db94011d3 15904 * | | |1 = Enable the processing of the Periodic (Interrupt and Isochronous) list in the next frame.
sahilmgandhi 18:6a4db94011d3 15905 * | | |Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high.
sahilmgandhi 18:6a4db94011d3 15906 * |[3] |IE |Isochronous List Enable Bit
sahilmgandhi 18:6a4db94011d3 15907 * | | |Both ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list.
sahilmgandhi 18:6a4db94011d3 15908 * | | |Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list.
sahilmgandhi 18:6a4db94011d3 15909 * | | |0 = Disable the processing of the Isochronous list after next SOF (Start-Of-Frame).
sahilmgandhi 18:6a4db94011d3 15910 * | | |1 = Enable the processing of the Isochronous list in the next frame if the PLE (HcControl[2]) is high, too.
sahilmgandhi 18:6a4db94011d3 15911 * |[4] |CLE |Control List Enable Bit
sahilmgandhi 18:6a4db94011d3 15912 * | | |0 = Disable processing of the Control list after next SOF (Start-Of-Frame).
sahilmgandhi 18:6a4db94011d3 15913 * | | |1 = Enable processing of the Control list in the next frame.
sahilmgandhi 18:6a4db94011d3 15914 * |[5] |BLE |Bulk List Enable Bit
sahilmgandhi 18:6a4db94011d3 15915 * | | |0 = Disable processing of the Bulk list after next SOF (Start-Of-Frame).
sahilmgandhi 18:6a4db94011d3 15916 * | | |1 = Enable processing of the Bulk list in the next frame.
sahilmgandhi 18:6a4db94011d3 15917 * |[7:6] |HCFS |Host Controller Functional State
sahilmgandhi 18:6a4db94011d3 15918 * | | |This field sets the Host Controller state.
sahilmgandhi 18:6a4db94011d3 15919 * | | |The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port.
sahilmgandhi 18:6a4db94011d3 15920 * | | |States are:
sahilmgandhi 18:6a4db94011d3 15921 * | | |00 = USBSUSPEND.
sahilmgandhi 18:6a4db94011d3 15922 * | | |01 = USBRESUME.
sahilmgandhi 18:6a4db94011d3 15923 * | | |10 = USBOPERATIONAL.
sahilmgandhi 18:6a4db94011d3 15924 * | | |11 = USBRESET.
sahilmgandhi 18:6a4db94011d3 15925 * @var USBH_T::HcCommandStatus
sahilmgandhi 18:6a4db94011d3 15926 * Offset: 0x08 Host Controller CMD Status Register
sahilmgandhi 18:6a4db94011d3 15927 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 15928 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 15929 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 15930 * |[0] |HCR |Host Controller Reset
sahilmgandhi 18:6a4db94011d3 15931 * | | |This bit is set to initiate the software reset of Host Controller.
sahilmgandhi 18:6a4db94011d3 15932 * | | |This bit is cleared by the Host Controller, upon completed of the reset operation.
sahilmgandhi 18:6a4db94011d3 15933 * | | |This bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports.
sahilmgandhi 18:6a4db94011d3 15934 * | | |0 = Host Controller is not in software reset state.
sahilmgandhi 18:6a4db94011d3 15935 * | | |1 = Host Controller is in software reset state.
sahilmgandhi 18:6a4db94011d3 15936 * |[1] |CLF |Control List Filled
sahilmgandhi 18:6a4db94011d3 15937 * | | |Set high to indicate there is an active TD on the Control List.
sahilmgandhi 18:6a4db94011d3 15938 * | | |It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List.
sahilmgandhi 18:6a4db94011d3 15939 * | | |0 = No active TD found or Host Controller begins to process the head of the Control list.
sahilmgandhi 18:6a4db94011d3 15940 * | | |1 = An active TD added or found on the Control list.
sahilmgandhi 18:6a4db94011d3 15941 * |[2] |BLF |Bulk List Filled
sahilmgandhi 18:6a4db94011d3 15942 * | | |Set high to indicate there is an active TD on the Bulk list.
sahilmgandhi 18:6a4db94011d3 15943 * | | |This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list.
sahilmgandhi 18:6a4db94011d3 15944 * | | |0 = No active TD found or Host Controller begins to process the head of the Bulk list.
sahilmgandhi 18:6a4db94011d3 15945 * | | |1 = An active TD added or found on the Bulk list.
sahilmgandhi 18:6a4db94011d3 15946 * |[17:16] |SOC |Schedule Overrun Count
sahilmgandhi 18:6a4db94011d3 15947 * | | |These bits are incremented on each scheduling overrun error.
sahilmgandhi 18:6a4db94011d3 15948 * | | |It is initialized to 00b and wraps around at 11b.
sahilmgandhi 18:6a4db94011d3 15949 * | | |This will be incremented when a scheduling overrun is detected even if SO (HcIntSts[0]) has already been set.
sahilmgandhi 18:6a4db94011d3 15950 * @var USBH_T::HcInterruptStatus
sahilmgandhi 18:6a4db94011d3 15951 * Offset: 0x0C Host Controller Interrupt Status Register
sahilmgandhi 18:6a4db94011d3 15952 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 15953 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 15954 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 15955 * |[0] |SO |Scheduling Overrun
sahilmgandhi 18:6a4db94011d3 15956 * | | |Set when the List Processor determines a Schedule Overrun has occurred.
sahilmgandhi 18:6a4db94011d3 15957 * | | |0 = Schedule Overrun didn't occur.
sahilmgandhi 18:6a4db94011d3 15958 * | | |1 = Schedule Overrun has occurred.
sahilmgandhi 18:6a4db94011d3 15959 * |[1] |WDH |Write Back Done Head
sahilmgandhi 18:6a4db94011d3 15960 * | | |Set after the Host Controller has written HcDoneHead to HccaDoneHead.
sahilmgandhi 18:6a4db94011d3 15961 * | | |Further updates of the HccaDoneHead will not occur until this bit has been cleared.
sahilmgandhi 18:6a4db94011d3 15962 * | | |0 =.Host Controller didn't update HccaDoneHead.
sahilmgandhi 18:6a4db94011d3 15963 * | | |1 =.Host Controller has written HcDoneHead to HccaDoneHead.
sahilmgandhi 18:6a4db94011d3 15964 * |[2] |SF |Start Of Frame
sahilmgandhi 18:6a4db94011d3 15965 * | | |Set when the Frame Management functional block signals a 'Start of Frame' event.
sahilmgandhi 18:6a4db94011d3 15966 * | | |Host Control generates a SOF token at the same time.
sahilmgandhi 18:6a4db94011d3 15967 * | | |0 =.Not the start of a frame.
sahilmgandhi 18:6a4db94011d3 15968 * | | |1 =.Indicate the start of a frame and Host Controller generates a SOF token.
sahilmgandhi 18:6a4db94011d3 15969 * |[3] |RD |Resume Detected
sahilmgandhi 18:6a4db94011d3 15970 * | | |Set when Host Controller detects resume signaling on a downstream port.
sahilmgandhi 18:6a4db94011d3 15971 * | | |0 = No resume signaling detected on a downstream port.
sahilmgandhi 18:6a4db94011d3 15972 * | | |1 = Resume signaling detected on a downstream port.
sahilmgandhi 18:6a4db94011d3 15973 * |[5] |FNO |Frame Number Overflow
sahilmgandhi 18:6a4db94011d3 15974 * | | |This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
sahilmgandhi 18:6a4db94011d3 15975 * | | |0 = The bit 15 of Frame Number didn't change.
sahilmgandhi 18:6a4db94011d3 15976 * | | |1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
sahilmgandhi 18:6a4db94011d3 15977 * |[6] |RHSC |Root Hub Status Change
sahilmgandhi 18:6a4db94011d3 15978 * | | |This bit is set when the content of HcRhSts or the content of HcRhPrt1 register has changed.
sahilmgandhi 18:6a4db94011d3 15979 * | | |0 = The content of HcRhSts and the content of HcRhPrt1 register didn't change.
sahilmgandhi 18:6a4db94011d3 15980 * | | |1 = The content of HcRhSts or the content of HcRhPrt1 register has changed.
sahilmgandhi 18:6a4db94011d3 15981 * @var USBH_T::HcInterruptEnable
sahilmgandhi 18:6a4db94011d3 15982 * Offset: 0x10 Host Controller Interrupt Enable Register
sahilmgandhi 18:6a4db94011d3 15983 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 15984 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 15985 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 15986 * |[0] |SO |Scheduling Overrun Enable Bit
sahilmgandhi 18:6a4db94011d3 15987 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 15988 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 15989 * | | |1 = Enable interrupt generation due to SO (HcIntSts[0]).
sahilmgandhi 18:6a4db94011d3 15990 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 15991 * | | |0 = Interrupt generation due to SO (HcIntSts[0]) disabled.
sahilmgandhi 18:6a4db94011d3 15992 * | | |1 = Interrupt generation due to SO (HcIntSts[0]) enabled.
sahilmgandhi 18:6a4db94011d3 15993 * |[1] |WDH |Write Back Done Head Enable Bit
sahilmgandhi 18:6a4db94011d3 15994 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 15995 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 15996 * | | |1 = Enable interrupt generation due to WDH (HcIntSts[1]).
sahilmgandhi 18:6a4db94011d3 15997 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 15998 * | | |0 = Interrupt generation due to WDH (HcIntSts[1]) disabled.
sahilmgandhi 18:6a4db94011d3 15999 * | | |1 = Interrupt generation due to WDH (HcIntSts[1]) enabled.
sahilmgandhi 18:6a4db94011d3 16000 * |[2] |SF |Start Of Frame Enable Bit
sahilmgandhi 18:6a4db94011d3 16001 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 16002 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 16003 * | | |1 = Enable interrupt generation due to SF (HcIntSts[2]).
sahilmgandhi 18:6a4db94011d3 16004 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 16005 * | | |0 = Interrupt generation due to SF (HcIntSts[2]) disabled.
sahilmgandhi 18:6a4db94011d3 16006 * | | |1 = Interrupt generation due to SF (HcIntSts[2]) enabled.
sahilmgandhi 18:6a4db94011d3 16007 * |[3] |RD |Resume Detected Enable Bit
sahilmgandhi 18:6a4db94011d3 16008 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 16009 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 16010 * | | |1 = Enable interrupt generation due to RD (HcIntSts[3]).
sahilmgandhi 18:6a4db94011d3 16011 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 16012 * | | |0 = Interrupt generation due to RD (HcIntSts[3]) disabled.
sahilmgandhi 18:6a4db94011d3 16013 * | | |1 = Interrupt generation due to RD (HcIntSts[3]) enabled.
sahilmgandhi 18:6a4db94011d3 16014 * |[5] |FNO |Frame Number Overflow Enable Bit
sahilmgandhi 18:6a4db94011d3 16015 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 16016 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 16017 * | | |1 = Enable interrupt generation due to FNO (HcIntSts[5]).
sahilmgandhi 18:6a4db94011d3 16018 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 16019 * | | |0 = Interrupt generation due to FNO (HcIntSts[5]) disabled.
sahilmgandhi 18:6a4db94011d3 16020 * | | |1 = Interrupt generation due to FNO (HcIntSts[5]) enabled.
sahilmgandhi 18:6a4db94011d3 16021 * |[6] |RHSC |Root Hub Status Change Enable Bit
sahilmgandhi 18:6a4db94011d3 16022 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 16023 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 16024 * | | |1 = Enable interrupt generation due to RHSC (HcIntSts[6]).
sahilmgandhi 18:6a4db94011d3 16025 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 16026 * | | |0 = Interrupt generation due to RHSC (HcIntSts[6]) disabled.
sahilmgandhi 18:6a4db94011d3 16027 * | | |1 = Interrupt generation due to RHSC (HcIntSts[6]) enabled.
sahilmgandhi 18:6a4db94011d3 16028 * |[31] |MIE |Master Interrupt Enable Bit
sahilmgandhi 18:6a4db94011d3 16029 * | | |This bit is a global interrupt enable.
sahilmgandhi 18:6a4db94011d3 16030 * | | |A write of '1' allows interrupts to be enabled via the specific enable bits listed above.
sahilmgandhi 18:6a4db94011d3 16031 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 16032 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 16033 * | | |1 = Enable interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) if the corresponding bit in HcIntEn is high.
sahilmgandhi 18:6a4db94011d3 16034 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 16035 * | | |0 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) disabled even if the corresponding bit in HcIntEn is high.
sahilmgandhi 18:6a4db94011d3 16036 * | | |1 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) enabled if the corresponding bit in HcIntEn is high.
sahilmgandhi 18:6a4db94011d3 16037 * @var USBH_T::HcInterruptDisable
sahilmgandhi 18:6a4db94011d3 16038 * Offset: 0x14 Host Controller Interrupt Disable Register
sahilmgandhi 18:6a4db94011d3 16039 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 16040 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 16041 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 16042 * |[0] |SO |Scheduling Overrun Disable Bit
sahilmgandhi 18:6a4db94011d3 16043 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 16044 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 16045 * | | |1 = Disable interrupt generation due to SO (HcIntSts[0]).
sahilmgandhi 18:6a4db94011d3 16046 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 16047 * | | |0 = Interrupt generation due to SO (HcIntSts[0]) disabled.
sahilmgandhi 18:6a4db94011d3 16048 * | | |1 = Interrupt generation due to SO (HcIntSts[0]) enabled.
sahilmgandhi 18:6a4db94011d3 16049 * |[1] |WDH |Write Back Done Head Disable Bit
sahilmgandhi 18:6a4db94011d3 16050 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 16051 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 16052 * | | |1 = Disable interrupt generation due to WDH (HcIntSts[1]).
sahilmgandhi 18:6a4db94011d3 16053 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 16054 * | | |0 = Interrupt generation due to WDH (HcIntSts[1]) disabled.
sahilmgandhi 18:6a4db94011d3 16055 * | | |1 = Interrupt generation due to WDH (HcIntSts[1]) enabled.
sahilmgandhi 18:6a4db94011d3 16056 * |[2] |SF |Start Of Frame Disable Bit
sahilmgandhi 18:6a4db94011d3 16057 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 16058 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 16059 * | | |1 = Disable interrupt generation due to SF (HcIntSts[2]).
sahilmgandhi 18:6a4db94011d3 16060 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 16061 * | | |0 = Interrupt generation due to SF (HcIntSts[2]) disabled.
sahilmgandhi 18:6a4db94011d3 16062 * | | |1 = Interrupt generation due to SF (HcIntSts[2]) enabled.
sahilmgandhi 18:6a4db94011d3 16063 * |[3] |RD |Resume Detected Disable Bit
sahilmgandhi 18:6a4db94011d3 16064 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 16065 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 16066 * | | |1 = Disable interrupt generation due to RD (HcIntSts[3]).
sahilmgandhi 18:6a4db94011d3 16067 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 16068 * | | |0 = Interrupt generation due to RD (HcIntSts[3]) disabled.
sahilmgandhi 18:6a4db94011d3 16069 * | | |1 = Interrupt generation due to RD (HcIntSts[3]) enabled.
sahilmgandhi 18:6a4db94011d3 16070 * |[5] |FNO |Frame Number Overflow Disable Bit
sahilmgandhi 18:6a4db94011d3 16071 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 16072 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 16073 * | | |1 = Disable interrupt generation due to FNO (HcIntSts[5]).
sahilmgandhi 18:6a4db94011d3 16074 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 16075 * | | |0 = Interrupt generation due to FNO (HcIntSts[5]) disabled.
sahilmgandhi 18:6a4db94011d3 16076 * | | |1 = Interrupt generation due to FNO (HcIntSts[5]) enabled.
sahilmgandhi 18:6a4db94011d3 16077 * |[6] |RHSC |Root Hub Status Change Disable Bit
sahilmgandhi 18:6a4db94011d3 16078 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 16079 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 16080 * | | |1 = Disable interrupt generation due to RHSC (HcIntSts[6]).
sahilmgandhi 18:6a4db94011d3 16081 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 16082 * | | |0 = Interrupt generation due to RHSC (HcIntSts[6]) disabled.
sahilmgandhi 18:6a4db94011d3 16083 * | | |1 = Interrupt generation due to RHSC (HcIntSts[6]) enabled.
sahilmgandhi 18:6a4db94011d3 16084 * |[31] |MIE |Master Interrupt Disable Bit
sahilmgandhi 18:6a4db94011d3 16085 * | | |Global interrupt disable. Writing '1' to disable all interrupts.
sahilmgandhi 18:6a4db94011d3 16086 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 16087 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 16088 * | | |1 = Disable interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) if the corresponding bit in HcIntEn is high.
sahilmgandhi 18:6a4db94011d3 16089 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 16090 * | | |0 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) disabled even if the corresponding bit in HcIntEn is high.
sahilmgandhi 18:6a4db94011d3 16091 * | | |1 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) enabled if the corresponding bit in HcIntEn is high.
sahilmgandhi 18:6a4db94011d3 16092 * @var USBH_T::HcHCCA
sahilmgandhi 18:6a4db94011d3 16093 * Offset: 0x18 Host Controller Communication Area Register
sahilmgandhi 18:6a4db94011d3 16094 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 16095 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 16096 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 16097 * |[31:8] |HCCA |Host Controller Communication Area
sahilmgandhi 18:6a4db94011d3 16098 * | | |Pointer to indicate base address of the Host Controller Communication Area (HCCA).
sahilmgandhi 18:6a4db94011d3 16099 * @var USBH_T::HcPeriodCurrentED
sahilmgandhi 18:6a4db94011d3 16100 * Offset: 0x1C Host Controller Period Current ED Register
sahilmgandhi 18:6a4db94011d3 16101 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 16102 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 16103 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 16104 * |[31:4] |PCED |Periodic Current ED
sahilmgandhi 18:6a4db94011d3 16105 * | | |Pointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor.
sahilmgandhi 18:6a4db94011d3 16106 * @var USBH_T::HcControlHeadED
sahilmgandhi 18:6a4db94011d3 16107 * Offset: 0x20 Host Controller Control Head ED Register
sahilmgandhi 18:6a4db94011d3 16108 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 16109 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 16110 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 16111 * |[31:4] |CHED |Control Head ED
sahilmgandhi 18:6a4db94011d3 16112 * | | |Pointer to indicate physical address of the first Endpoint Descriptor of the Control list.
sahilmgandhi 18:6a4db94011d3 16113 * @var USBH_T::HcControlCurrentED
sahilmgandhi 18:6a4db94011d3 16114 * Offset: 0x24 Host Controller Control Current ED Register
sahilmgandhi 18:6a4db94011d3 16115 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 16116 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 16117 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 16118 * |[31:4] |CCED |Control Current Head ED
sahilmgandhi 18:6a4db94011d3 16119 * | | |Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list.
sahilmgandhi 18:6a4db94011d3 16120 * @var USBH_T::HcBulkHeadED
sahilmgandhi 18:6a4db94011d3 16121 * Offset: 0x28 Host Controller Bulk Head ED Register
sahilmgandhi 18:6a4db94011d3 16122 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 16123 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 16124 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 16125 * |[31:4] |BHED |Bulk Head ED
sahilmgandhi 18:6a4db94011d3 16126 * | | |Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list.
sahilmgandhi 18:6a4db94011d3 16127 * @var USBH_T::HcBulkCurrentED
sahilmgandhi 18:6a4db94011d3 16128 * Offset: 0x2C Host Controller Bulk Current ED Register
sahilmgandhi 18:6a4db94011d3 16129 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 16130 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 16131 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 16132 * |[31:4] |BCED |Bulk Current Head ED
sahilmgandhi 18:6a4db94011d3 16133 * | | |Pointer to indicate the physical address of the current endpoint of the Bulk list.
sahilmgandhi 18:6a4db94011d3 16134 * @var USBH_T::HcDoneHead
sahilmgandhi 18:6a4db94011d3 16135 * Offset: 0x30 Host Controller Done Head Register
sahilmgandhi 18:6a4db94011d3 16136 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 16137 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 16138 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 16139 * |[31:4] |DH |Done Head
sahilmgandhi 18:6a4db94011d3 16140 * | | |Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue.
sahilmgandhi 18:6a4db94011d3 16141 * @var USBH_T::HcFmInterval
sahilmgandhi 18:6a4db94011d3 16142 * Offset: 0x34 Host Controller Frame Interval Register
sahilmgandhi 18:6a4db94011d3 16143 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 16144 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 16145 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 16146 * |[13:0] |FI |Frame Interval
sahilmgandhi 18:6a4db94011d3 16147 * | | |This field specifies the length of a frame as (bit times - 1).
sahilmgandhi 18:6a4db94011d3 16148 * | | |For 12,000 bit times in a frame, a value of 11,999 is stored here.
sahilmgandhi 18:6a4db94011d3 16149 * |[30:16] |FSMPS |FS Largest Data Packet
sahilmgandhi 18:6a4db94011d3 16150 * | | |This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame.
sahilmgandhi 18:6a4db94011d3 16151 * |[31] |FIT |Frame Interval Toggle
sahilmgandhi 18:6a4db94011d3 16152 * | | |This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmIntv[13:0]).
sahilmgandhi 18:6a4db94011d3 16153 * | | |0 = Host Controller Driver didn't load new value into FI (HcFmIntv[13:0]).
sahilmgandhi 18:6a4db94011d3 16154 * | | |1 = Host Controller Driver loads a new value into FI (HcFmIntv[13:0]).
sahilmgandhi 18:6a4db94011d3 16155 * @var USBH_T::HcFmRemaining
sahilmgandhi 18:6a4db94011d3 16156 * Offset: 0x38 Host Controller Frame Remaining Register
sahilmgandhi 18:6a4db94011d3 16157 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 16158 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 16159 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 16160 * |[13:0] |FR |Frame Remaining
sahilmgandhi 18:6a4db94011d3 16161 * | | |When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period.
sahilmgandhi 18:6a4db94011d3 16162 * | | |When the count reaches 0, (end of frame) the counter reloads with Frame Interval.
sahilmgandhi 18:6a4db94011d3 16163 * | | |In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL.
sahilmgandhi 18:6a4db94011d3 16164 * |[31] |FRT |Frame Remaining Toggle
sahilmgandhi 18:6a4db94011d3 16165 * | | |This bit is loaded from the FIT (HcFmIntv[31]) whenever FR (HcFmRem[13:0]) reaches 0.
sahilmgandhi 18:6a4db94011d3 16166 * @var USBH_T::HcFmNumber
sahilmgandhi 18:6a4db94011d3 16167 * Offset: 0x3C Host Controller Frame Number Register
sahilmgandhi 18:6a4db94011d3 16168 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 16169 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 16170 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 16171 * |[15:0] |FN |Frame Number
sahilmgandhi 18:6a4db94011d3 16172 * | | |This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRem[13:0]).
sahilmgandhi 18:6a4db94011d3 16173 * | | |The count rolls over from 'FFFFh' to '0h.'.
sahilmgandhi 18:6a4db94011d3 16174 * @var USBH_T::HcPeriodicStart
sahilmgandhi 18:6a4db94011d3 16175 * Offset: 0x40 Host Controller Periodic Start Register
sahilmgandhi 18:6a4db94011d3 16176 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 16177 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 16178 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 16179 * |[13:0] |PS |Periodic Start
sahilmgandhi 18:6a4db94011d3 16180 * | | |This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
sahilmgandhi 18:6a4db94011d3 16181 * @var USBH_T::HcLSThreshold
sahilmgandhi 18:6a4db94011d3 16182 * Offset: 0x44 Host Controller Low-speed Threshold Register
sahilmgandhi 18:6a4db94011d3 16183 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 16184 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 16185 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 16186 * |[11:0] |LST |Low-Speed Threshold
sahilmgandhi 18:6a4db94011d3 16187 * | | |This field contains a value which is compared to the FR (HcFmRem[13:0]) field prior to initiating a Low-speed transaction.
sahilmgandhi 18:6a4db94011d3 16188 * | | |The transaction is started only if FR (HcFmRem[13:0]) >= this field.
sahilmgandhi 18:6a4db94011d3 16189 * | | |The value is calculated by Host Controller Driver with the consideration of transmission and setup overhead.
sahilmgandhi 18:6a4db94011d3 16190 * @var USBH_T::HcRhDescriptorA
sahilmgandhi 18:6a4db94011d3 16191 * Offset: 0x48 Host Controller Root Hub Descriptor A Register
sahilmgandhi 18:6a4db94011d3 16192 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 16193 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 16194 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 16195 * |[7:0] |NDP |Number Downstream Ports
sahilmgandhi 18:6a4db94011d3 16196 * | | |USB host control supports two downstream ports and only one port is available in this series of chip.
sahilmgandhi 18:6a4db94011d3 16197 * |[8] |PSM |Power Switching Mode
sahilmgandhi 18:6a4db94011d3 16198 * | | |This bit is used to specify how the power switching of the Root Hub ports is controlled.
sahilmgandhi 18:6a4db94011d3 16199 * | | |0 = Global Switching.
sahilmgandhi 18:6a4db94011d3 16200 * | | |1 = Individual Switching.
sahilmgandhi 18:6a4db94011d3 16201 * |[11] |OCPM |Over Current Protection Mode
sahilmgandhi 18:6a4db94011d3 16202 * | | |This bit describes how the over current status for the Root Hub ports reported.
sahilmgandhi 18:6a4db94011d3 16203 * | | |This bit is only valid when NOCP (HcRhDeA[12]) is cleared.
sahilmgandhi 18:6a4db94011d3 16204 * | | |0 = Global Over current.
sahilmgandhi 18:6a4db94011d3 16205 * | | |1 = Individual Over current.
sahilmgandhi 18:6a4db94011d3 16206 * |[12] |NOCP |No Over Current Protection
sahilmgandhi 18:6a4db94011d3 16207 * | | |This bit describes how the over current status for the Root Hub ports reported.
sahilmgandhi 18:6a4db94011d3 16208 * | | |0 = Over current status is reported.
sahilmgandhi 18:6a4db94011d3 16209 * | | |1 = Over current status is not reported.
sahilmgandhi 18:6a4db94011d3 16210 * @var USBH_T::HcRhDescriptorB
sahilmgandhi 18:6a4db94011d3 16211 * Offset: 0x4C Host Controller Root Hub Descriptor B Register
sahilmgandhi 18:6a4db94011d3 16212 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 16213 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 16214 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 16215 * |[31:16] |PPCM |Port Power Control Mask
sahilmgandhi 18:6a4db94011d3 16216 * | | |Global power switching.
sahilmgandhi 18:6a4db94011d3 16217 * | | |This field is only valid if PowerSwitchingMode is set (individual port switching).
sahilmgandhi 18:6a4db94011d3 16218 * | | |When set, the port only responds to individual port power switching commands (Set/ClearPortPower).
sahilmgandhi 18:6a4db94011d3 16219 * | | |When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower).
sahilmgandhi 18:6a4db94011d3 16220 * | | |0 = Port power controlled by global power switching.
sahilmgandhi 18:6a4db94011d3 16221 * | | |1 = Port power controlled by port power switching.
sahilmgandhi 18:6a4db94011d3 16222 * | | |Note: PPCM[15:2] and PPCM[0] are reserved.
sahilmgandhi 18:6a4db94011d3 16223 * @var USBH_T::HcRhStatus
sahilmgandhi 18:6a4db94011d3 16224 * Offset: 0x50 Host Controller Root Hub Status Register
sahilmgandhi 18:6a4db94011d3 16225 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 16226 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 16227 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 16228 * |[0] |LPS |Clear Global Power
sahilmgandhi 18:6a4db94011d3 16229 * | | |In global power mode (PSM (HcRhDeA[8]) = 0), this bit is written to one to clear all ports' power.
sahilmgandhi 18:6a4db94011d3 16230 * | | |This bit always read as zero.
sahilmgandhi 18:6a4db94011d3 16231 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 16232 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 16233 * | | |1 = Clear global power.
sahilmgandhi 18:6a4db94011d3 16234 * |[1] |OCI |Over Current Indicator
sahilmgandhi 18:6a4db94011d3 16235 * | | |This bit reflects the state of the over current status pin.
sahilmgandhi 18:6a4db94011d3 16236 * | | |This field is only valid if NOCP (HcRhDesA[12]) and OCPM (HcRhDesA[11]) are cleared.
sahilmgandhi 18:6a4db94011d3 16237 * | | |0 = No over current condition.
sahilmgandhi 18:6a4db94011d3 16238 * | | |1 = Over current condition.
sahilmgandhi 18:6a4db94011d3 16239 * |[15] |DRWE |Device Remote Wakeup Enable Bit
sahilmgandhi 18:6a4db94011d3 16240 * | | |This bit controls if port's Connect Status Change as a remote wake-up event.
sahilmgandhi 18:6a4db94011d3 16241 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 16242 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 16243 * | | |1 = Enable Connect Status Change as a remote wake-up event.
sahilmgandhi 18:6a4db94011d3 16244 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 16245 * | | |0 = Connect Status Change as a remote wake-up event disabled.
sahilmgandhi 18:6a4db94011d3 16246 * | | |1 = Connect Status Change as a remote wake-up event enabled.
sahilmgandhi 18:6a4db94011d3 16247 * |[16] |LPSC |Set Global Power
sahilmgandhi 18:6a4db94011d3 16248 * | | |In global power mode (PSM (HcRhDeA[8]) = 0), this bit is written to one to enable power to all ports.
sahilmgandhi 18:6a4db94011d3 16249 * | | |This bit always read as zero.
sahilmgandhi 18:6a4db94011d3 16250 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 16251 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 16252 * | | |1 = Set global power.
sahilmgandhi 18:6a4db94011d3 16253 * |[17] |OCIC |Over Current Indicator Change
sahilmgandhi 18:6a4db94011d3 16254 * | | |This bit is set by hardware when a change has occurred in OCI (HcRhSts[1]).
sahilmgandhi 18:6a4db94011d3 16255 * | | |Write 1 to clear this bit to zero.
sahilmgandhi 18:6a4db94011d3 16256 * | | |0 = OCI (HcRhSts[1]) didn't change.
sahilmgandhi 18:6a4db94011d3 16257 * | | |1 = OCI (HcRhSts[1]) change.
sahilmgandhi 18:6a4db94011d3 16258 * |[31] |CRWE |Clear Remote Wake-up Enable Bit
sahilmgandhi 18:6a4db94011d3 16259 * | | |This bit is use to clear DRWE (HcRhSts[15]).
sahilmgandhi 18:6a4db94011d3 16260 * | | |This bit always read as zero.
sahilmgandhi 18:6a4db94011d3 16261 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 16262 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 16263 * | | |1 = Clear DRWE (HcRhSts[15]).
sahilmgandhi 18:6a4db94011d3 16264 * @var USBH_T::HcRhPortStatus
sahilmgandhi 18:6a4db94011d3 16265 * Offset: 0x54 Host Controller Root Hub Port Status [1]
sahilmgandhi 18:6a4db94011d3 16266 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 16267 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 16268 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 16269 * |[0] |CCS |CurrentConnectStatus (Read) Or ClearPortEnable Bit (Write)
sahilmgandhi 18:6a4db94011d3 16270 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 16271 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 16272 * | | |1 = Clear port enable.
sahilmgandhi 18:6a4db94011d3 16273 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 16274 * | | |0 = No device connected.
sahilmgandhi 18:6a4db94011d3 16275 * | | |1 = Device connected.
sahilmgandhi 18:6a4db94011d3 16276 * |[1] |PES |Port Enable Status
sahilmgandhi 18:6a4db94011d3 16277 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 16278 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 16279 * | | |1 = Set port enable.
sahilmgandhi 18:6a4db94011d3 16280 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 16281 * | | |0 = Port Disabled.
sahilmgandhi 18:6a4db94011d3 16282 * | | |1 = Port Enabled.
sahilmgandhi 18:6a4db94011d3 16283 * |[2] |PSS |Port Suspend Status
sahilmgandhi 18:6a4db94011d3 16284 * | | |This bit indicates the port is suspended
sahilmgandhi 18:6a4db94011d3 16285 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 16286 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 16287 * | | |1 = Set port suspend.
sahilmgandhi 18:6a4db94011d3 16288 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 16289 * | | |0 = Port is not suspended.
sahilmgandhi 18:6a4db94011d3 16290 * | | |1 = Port is selectively suspended.
sahilmgandhi 18:6a4db94011d3 16291 * |[3] |POCI |Port Over Current Indicator (Read) Or Clear Port Suspend (Write)
sahilmgandhi 18:6a4db94011d3 16292 * | | |This bit reflects the state of the over current status pin dedicated to this port.
sahilmgandhi 18:6a4db94011d3 16293 * | | |This field is only valid if NOCP (HcRhDeA[12]) is cleared and OCPM (HcRhDeA[11]) is set.
sahilmgandhi 18:6a4db94011d3 16294 * | | |This bit is also used to initiate the selective result sequence for the port.
sahilmgandhi 18:6a4db94011d3 16295 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 16296 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 16297 * | | |1 = Clear port suspend.
sahilmgandhi 18:6a4db94011d3 16298 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 16299 * | | |0 = No over current condition.
sahilmgandhi 18:6a4db94011d3 16300 * | | |1 = Over current condition.
sahilmgandhi 18:6a4db94011d3 16301 * |[4] |PRS |Port Reset Status
sahilmgandhi 18:6a4db94011d3 16302 * | | |This bit reflects the reset state of the port.
sahilmgandhi 18:6a4db94011d3 16303 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 16304 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 16305 * | | |1 = Set port reset.
sahilmgandhi 18:6a4db94011d3 16306 * | | |Read Operation
sahilmgandhi 18:6a4db94011d3 16307 * | | |0 = Port reset signal is not active.
sahilmgandhi 18:6a4db94011d3 16308 * | | |1 = Port reset signal is active.
sahilmgandhi 18:6a4db94011d3 16309 * |[8] |PPS |Port Power Status
sahilmgandhi 18:6a4db94011d3 16310 * | | |This bit reflects the power state of the port regardless of the power switching mode.
sahilmgandhi 18:6a4db94011d3 16311 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 16312 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 16313 * | | |1 = Port Power Enabled.
sahilmgandhi 18:6a4db94011d3 16314 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 16315 * | | |0 = Port power is Disabled.
sahilmgandhi 18:6a4db94011d3 16316 * | | |1 = Port power is Enabled.
sahilmgandhi 18:6a4db94011d3 16317 * |[9] |LSDA |Low Speed Device Attached (Read) Or Clear Port Power (Write)
sahilmgandhi 18:6a4db94011d3 16318 * | | |This bit defines the speed (and bud idle) of the attached device.
sahilmgandhi 18:6a4db94011d3 16319 * | | |It is only valid when CCS (HcRhPrt1[0]) is set.
sahilmgandhi 18:6a4db94011d3 16320 * | | |This bit is also used to clear port power.
sahilmgandhi 18:6a4db94011d3 16321 * | | |Write Operation:
sahilmgandhi 18:6a4db94011d3 16322 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 16323 * | | |1 = Clear PPS (HcRhPrt1[8]).
sahilmgandhi 18:6a4db94011d3 16324 * | | |Read Operation:
sahilmgandhi 18:6a4db94011d3 16325 * | | |0 = Full Speed device.
sahilmgandhi 18:6a4db94011d3 16326 * | | |1 = Low-speed device.
sahilmgandhi 18:6a4db94011d3 16327 * |[16] |CSC |Connect Status Change
sahilmgandhi 18:6a4db94011d3 16328 * | | |This bit indicates connect or disconnect event has been detected (CCS
sahilmgandhi 18:6a4db94011d3 16329 * | | |(HcRhPrt1[0]) changed).
sahilmgandhi 18:6a4db94011d3 16330 * | | |Write 1 to clear this bit to zero.
sahilmgandhi 18:6a4db94011d3 16331 * | | |0 = No connect/disconnect event (CCS (HcRhPrt1[0]) didn't change).
sahilmgandhi 18:6a4db94011d3 16332 * | | |1 = Hardware detection of connect/disconnect event (CCS
sahilmgandhi 18:6a4db94011d3 16333 * | | |(HcRhPrt1[0]) changed).
sahilmgandhi 18:6a4db94011d3 16334 * |[17] |PESC |Port Enable Status Change
sahilmgandhi 18:6a4db94011d3 16335 * | | |This bit indicates that the port has been disabled (PES (HcRhPrt1[1]) cleared) due to a hardware event.
sahilmgandhi 18:6a4db94011d3 16336 * | | |Write 1 to clear this bit to zero.
sahilmgandhi 18:6a4db94011d3 16337 * | | |0 = PES (HcRhPrt1[1]) didn't change.
sahilmgandhi 18:6a4db94011d3 16338 * | | |1 = PES (HcRhPrt1[1]) changed.
sahilmgandhi 18:6a4db94011d3 16339 * |[18] |PSSC |Port Suspend Status Change
sahilmgandhi 18:6a4db94011d3 16340 * | | |This bit indicates the completion of the selective resume sequence for the port.
sahilmgandhi 18:6a4db94011d3 16341 * | | |Write 1 to clear this bit to zero.
sahilmgandhi 18:6a4db94011d3 16342 * | | |0 = Port resume is not completed.
sahilmgandhi 18:6a4db94011d3 16343 * | | |1 = Port resume completed.
sahilmgandhi 18:6a4db94011d3 16344 * |[19] |OCIC |Port Over Current Indicator Change
sahilmgandhi 18:6a4db94011d3 16345 * | | |This bit is set when POCI (HcRhPrt1[3]) changes.
sahilmgandhi 18:6a4db94011d3 16346 * | | |Write 1 to clear this bit to zero.
sahilmgandhi 18:6a4db94011d3 16347 * | | |0 = POCI (HcRhPrt1[3]) didn't change.
sahilmgandhi 18:6a4db94011d3 16348 * | | |1 = POCI (HcRhPrt1[3]) changes.
sahilmgandhi 18:6a4db94011d3 16349 * |[20] |PRSC |Port Reset Status Change
sahilmgandhi 18:6a4db94011d3 16350 * | | |This bit indicates that the port reset signal has completed.
sahilmgandhi 18:6a4db94011d3 16351 * | | |Write 1 to clear this bit to zero.
sahilmgandhi 18:6a4db94011d3 16352 * | | |0 = Port reset is not complete.
sahilmgandhi 18:6a4db94011d3 16353 * | | |1 = Port reset is complete.
sahilmgandhi 18:6a4db94011d3 16354 * @var USBH_T::HcPhyControl
sahilmgandhi 18:6a4db94011d3 16355 * Offset: 0x200 USB Host Controller PHY Control Register
sahilmgandhi 18:6a4db94011d3 16356 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 16357 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 16358 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 16359 * |[27] |STBYEN |USB Transceiver Standby Enable Bit
sahilmgandhi 18:6a4db94011d3 16360 * | | |This bit controls if USB transceiver could enter the standby mode to reduce power consumption.
sahilmgandhi 18:6a4db94011d3 16361 * | | |0 = The USB transceiver would never enter the standby mode.
sahilmgandhi 18:6a4db94011d3 16362 * | | |1 = The USB transceiver will enter standby mode while port is in power off state (port power is inactive).
sahilmgandhi 18:6a4db94011d3 16363 * @var USBH_T::HcMiscControl
sahilmgandhi 18:6a4db94011d3 16364 * Offset: 0x204 USB Host Controller Miscellaneous Control Register
sahilmgandhi 18:6a4db94011d3 16365 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 16366 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 16367 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 16368 * |[1] |ABORT |AHB Bus ERROR Response
sahilmgandhi 18:6a4db94011d3 16369 * | | |This bit indicates there is an ERROR response received in AHB bus.
sahilmgandhi 18:6a4db94011d3 16370 * | | |0 = No ERROR response received.
sahilmgandhi 18:6a4db94011d3 16371 * | | |1 = ERROR response received.
sahilmgandhi 18:6a4db94011d3 16372 * |[3] |OCAL |Over Current Active Low
sahilmgandhi 18:6a4db94011d3 16373 * | | |This bit controls the polarity of over current flag from external power IC.
sahilmgandhi 18:6a4db94011d3 16374 * | | |0 = Over current flag is high active.
sahilmgandhi 18:6a4db94011d3 16375 * | | |1 = Over current flag is low active.
sahilmgandhi 18:6a4db94011d3 16376 * |[16] |DPRT1 |Disable Port 1
sahilmgandhi 18:6a4db94011d3 16377 * | | |This bit controls if the connection between USB host controller and transceiver of port 1 is disabled.
sahilmgandhi 18:6a4db94011d3 16378 * | | |If the connection is disabled, the USB host controller will not recognize any event of USB bus.
sahilmgandhi 18:6a4db94011d3 16379 * | | |Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is.
sahilmgandhi 18:6a4db94011d3 16380 * | | |0 = The connection between USB host controller and transceiver of port 1 is enabled.
sahilmgandhi 18:6a4db94011d3 16381 * | | |1 = The connection between USB host controller and transceiver of port 1 is disabled and the transceiver of port 1 will also be forced into the standby mode.
sahilmgandhi 18:6a4db94011d3 16382 */
sahilmgandhi 18:6a4db94011d3 16383
sahilmgandhi 18:6a4db94011d3 16384 __I uint32_t HcRevision; /* Offset: 0x00 Host Controller Revision Register */
sahilmgandhi 18:6a4db94011d3 16385 __IO uint32_t HcControl; /* Offset: 0x04 Host Controller Control Register */
sahilmgandhi 18:6a4db94011d3 16386 __IO uint32_t HcCommandStatus; /* Offset: 0x08 Host Controller CMD Status Register */
sahilmgandhi 18:6a4db94011d3 16387 __IO uint32_t HcInterruptStatus; /* Offset: 0x0C Host Controller Interrupt Status Register */
sahilmgandhi 18:6a4db94011d3 16388 __IO uint32_t HcInterruptEnable; /* Offset: 0x10 Host Controller Interrupt Enable Register */
sahilmgandhi 18:6a4db94011d3 16389 __IO uint32_t HcInterruptDisable; /* Offset: 0x14 Host Controller Interrupt Disable Register */
sahilmgandhi 18:6a4db94011d3 16390 __IO uint32_t HcHCCA; /* Offset: 0x18 Host Controller Communication Area Register */
sahilmgandhi 18:6a4db94011d3 16391 __IO uint32_t HcPeriodCurrentED; /* Offset: 0x1C Host Controller Period Current ED Register */
sahilmgandhi 18:6a4db94011d3 16392 __IO uint32_t HcControlHeadED; /* Offset: 0x20 Host Controller Control Head ED Register */
sahilmgandhi 18:6a4db94011d3 16393 __IO uint32_t HcControlCurrentED; /* Offset: 0x24 Host Controller Control Current ED Register */
sahilmgandhi 18:6a4db94011d3 16394 __IO uint32_t HcBulkHeadED; /* Offset: 0x28 Host Controller Bulk Head ED Register */
sahilmgandhi 18:6a4db94011d3 16395 __IO uint32_t HcBulkCurrentED; /* Offset: 0x2C Host Controller Bulk Current ED Register */
sahilmgandhi 18:6a4db94011d3 16396 __IO uint32_t HcDoneHead; /* Offset: 0x30 Host Controller Done Head Register */
sahilmgandhi 18:6a4db94011d3 16397 __IO uint32_t HcFmInterval; /* Offset: 0x34 Host Controller Frame Interval Register */
sahilmgandhi 18:6a4db94011d3 16398 __I uint32_t HcFmRemaining; /* Offset: 0x38 Host Controller Frame Remaining Register */
sahilmgandhi 18:6a4db94011d3 16399 __I uint32_t HcFmNumber; /* Offset: 0x3C Host Controller Frame Number Register */
sahilmgandhi 18:6a4db94011d3 16400 __IO uint32_t HcPeriodicStart; /* Offset: 0x40 Host Controller Periodic Start Register */
sahilmgandhi 18:6a4db94011d3 16401 __IO uint32_t HcLSThreshold; /* Offset: 0x44 Host Controller Low-speed Threshold Register */
sahilmgandhi 18:6a4db94011d3 16402 __IO uint32_t HcRhDescriptorA; /* Offset: 0x48 Host Controller Root Hub Descriptor A Register */
sahilmgandhi 18:6a4db94011d3 16403 __IO uint32_t HcRhDescriptorB; /* Offset: 0x4C Host Controller Root Hub Descriptor B Register */
sahilmgandhi 18:6a4db94011d3 16404 __IO uint32_t HcRhStatus; /* Offset: 0x50 Host Controller Root Hub Status Register */
sahilmgandhi 18:6a4db94011d3 16405 __IO uint32_t HcRhPortStatus[2]; /* Offset: 0x54 Host Controller Root Hub Port Status [1] */
sahilmgandhi 18:6a4db94011d3 16406 __I uint32_t RESERVE0[105];
sahilmgandhi 18:6a4db94011d3 16407 __IO uint32_t HcPhyControl; /* Offset: 0x200 USB Host Controller PHY Control Register */
sahilmgandhi 18:6a4db94011d3 16408 __IO uint32_t HcMiscControl; /* Offset: 0x204 USB Host Controller Miscellaneous Control Register */
sahilmgandhi 18:6a4db94011d3 16409
sahilmgandhi 18:6a4db94011d3 16410 } USBH_T;
sahilmgandhi 18:6a4db94011d3 16411
sahilmgandhi 18:6a4db94011d3 16412
sahilmgandhi 18:6a4db94011d3 16413
sahilmgandhi 18:6a4db94011d3 16414
sahilmgandhi 18:6a4db94011d3 16415 /**
sahilmgandhi 18:6a4db94011d3 16416 @addtogroup USBH_CONST USBH Bit Field Definition
sahilmgandhi 18:6a4db94011d3 16417 Constant Definitions for USBH Controller
sahilmgandhi 18:6a4db94011d3 16418 @{ */
sahilmgandhi 18:6a4db94011d3 16419
sahilmgandhi 18:6a4db94011d3 16420 #define USBH_HcRevision_REV_Pos (0) /*!< USBH_T::HcRevision: REV Position */
sahilmgandhi 18:6a4db94011d3 16421 #define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) /*!< USBH_T::HcRevision: REV Mask */
sahilmgandhi 18:6a4db94011d3 16422
sahilmgandhi 18:6a4db94011d3 16423 #define USBH_HcControl_CBSR_Pos (0) /*!< USBH_T::HcControl: CBSR Position */
sahilmgandhi 18:6a4db94011d3 16424 #define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) /*!< USBH_T::HcControl: CBSR Mask */
sahilmgandhi 18:6a4db94011d3 16425
sahilmgandhi 18:6a4db94011d3 16426 #define USBH_HcControl_PLE_Pos (2) /*!< USBH_T::HcControl: CBSR Position */
sahilmgandhi 18:6a4db94011d3 16427 #define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) /*!< USBH_T::HcControl: CBSR Mask */
sahilmgandhi 18:6a4db94011d3 16428
sahilmgandhi 18:6a4db94011d3 16429 #define USBH_HcControl_IE_Pos (3) /*!< USBH_T::HcControl: IE Position */
sahilmgandhi 18:6a4db94011d3 16430 #define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) /*!< USBH_T::HcControl: IE Mask */
sahilmgandhi 18:6a4db94011d3 16431
sahilmgandhi 18:6a4db94011d3 16432 #define USBH_HcControl_CLE_Pos (4) /*!< USBH_T::HcControl: CLE Position */
sahilmgandhi 18:6a4db94011d3 16433 #define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) /*!< USBH_T::HcControl: CLE Mask */
sahilmgandhi 18:6a4db94011d3 16434
sahilmgandhi 18:6a4db94011d3 16435 #define USBH_HcControl_BLE_Pos (5) /*!< USBH_T::HcControl: BLE Position */
sahilmgandhi 18:6a4db94011d3 16436 #define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) /*!< USBH_T::HcControl: BLE Mask */
sahilmgandhi 18:6a4db94011d3 16437
sahilmgandhi 18:6a4db94011d3 16438 #define USBH_HcControl_HCFS_Pos (6) /*!< USBH_T::HcControl: HCFS Position */
sahilmgandhi 18:6a4db94011d3 16439 #define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) /*!< USBH_T::HcControl: HCFS Mask */
sahilmgandhi 18:6a4db94011d3 16440
sahilmgandhi 18:6a4db94011d3 16441 #define USBH_HcCommandStatus_HCR_Pos (0) /*!< USBH_T::HcCommandStatus: HCR Position */
sahilmgandhi 18:6a4db94011d3 16442 #define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) /*!< USBH_T::HcCommandStatus: HCR Mask */
sahilmgandhi 18:6a4db94011d3 16443
sahilmgandhi 18:6a4db94011d3 16444 #define USBH_HcCommandStatus_CLF_Pos (1) /*!< USBH_T::HcCommandStatus: CLF Position */
sahilmgandhi 18:6a4db94011d3 16445 #define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) /*!< USBH_T::HcCommandStatus: CLF Mask */
sahilmgandhi 18:6a4db94011d3 16446
sahilmgandhi 18:6a4db94011d3 16447 #define USBH_HcCommandStatus_BLF_Pos (2) /*!< USBH_T::HcCommandStatus: BLF Position */
sahilmgandhi 18:6a4db94011d3 16448 #define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) /*!< USBH_T::HcCommandStatus: BLF Mask */
sahilmgandhi 18:6a4db94011d3 16449
sahilmgandhi 18:6a4db94011d3 16450 #define USBH_HcCommandStatus_SOC_Pos (16) /*!< USBH_T::HcCommandStatus: SOC Position */
sahilmgandhi 18:6a4db94011d3 16451 #define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) /*!< USBH_T::HcCommandStatus: SOC Mask */
sahilmgandhi 18:6a4db94011d3 16452
sahilmgandhi 18:6a4db94011d3 16453 #define USBH_HcInterruptStatus_SO_Pos (0) /*!< USBH_T::HcInterruptStatus: SO Position */
sahilmgandhi 18:6a4db94011d3 16454 #define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) /*!< USBH_T::HcInterruptStatus: SO Mask */
sahilmgandhi 18:6a4db94011d3 16455
sahilmgandhi 18:6a4db94011d3 16456 #define USBH_HcInterruptStatus_WDH_Pos (1) /*!< USBH_T::HcInterruptStatus: WDH Position */
sahilmgandhi 18:6a4db94011d3 16457 #define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) /*!< USBH_T::HcInterruptStatus: WDH Mask */
sahilmgandhi 18:6a4db94011d3 16458
sahilmgandhi 18:6a4db94011d3 16459 #define USBH_HcInterruptStatus_SF_Pos (2) /*!< USBH_T::HcInterruptStatus: SF Position */
sahilmgandhi 18:6a4db94011d3 16460 #define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) /*!< USBH_T::HcInterruptStatus: SF Mask */
sahilmgandhi 18:6a4db94011d3 16461
sahilmgandhi 18:6a4db94011d3 16462 #define USBH_HcInterruptStatus_RD_Pos (3) /*!< USBH_T::HcInterruptStatus: RD Position */
sahilmgandhi 18:6a4db94011d3 16463 #define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) /*!< USBH_T::HcInterruptStatus: RD Mask */
sahilmgandhi 18:6a4db94011d3 16464
sahilmgandhi 18:6a4db94011d3 16465 #define USBH_HcInterruptStatus_FNO_Pos (5) /*!< USBH_T::HcInterruptStatus: FNO Position */
sahilmgandhi 18:6a4db94011d3 16466 #define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) /*!< USBH_T::HcInterruptStatus: FNO Mask */
sahilmgandhi 18:6a4db94011d3 16467
sahilmgandhi 18:6a4db94011d3 16468 #define USBH_HcInterruptStatus_RHSC_Pos (6) /*!< USBH_T::HcInterruptStatus: RHSC Position */
sahilmgandhi 18:6a4db94011d3 16469 #define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) /*!< USBH_T::HcInterruptStatus: RHSC Mask */
sahilmgandhi 18:6a4db94011d3 16470
sahilmgandhi 18:6a4db94011d3 16471 #define USBH_HcInterruptEnable_SO_Pos (0) /*!< USBH_T::HcInterruptEnable: SO Position */
sahilmgandhi 18:6a4db94011d3 16472 #define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) /*!< USBH_T::HcInterruptEnable: SO Mask */
sahilmgandhi 18:6a4db94011d3 16473
sahilmgandhi 18:6a4db94011d3 16474 #define USBH_HcInterruptEnable_WDH_Pos (1) /*!< USBH_T::HcInterruptEnable: WDH Position */
sahilmgandhi 18:6a4db94011d3 16475 #define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) /*!< USBH_T::HcInterruptEnable: WDH Mask */
sahilmgandhi 18:6a4db94011d3 16476
sahilmgandhi 18:6a4db94011d3 16477 #define USBH_HcInterruptEnable_SF_Pos (2) /*!< USBH_T::HcInterruptEnable: SF Position */
sahilmgandhi 18:6a4db94011d3 16478 #define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) /*!< USBH_T::HcInterruptEnable: SF Mask */
sahilmgandhi 18:6a4db94011d3 16479
sahilmgandhi 18:6a4db94011d3 16480 #define USBH_HcInterruptEnable_RD_Pos (3) /*!< USBH_T::HcInterruptEnable: RD Position */
sahilmgandhi 18:6a4db94011d3 16481 #define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) /*!< USBH_T::HcInterruptEnable: RD Mask */
sahilmgandhi 18:6a4db94011d3 16482
sahilmgandhi 18:6a4db94011d3 16483 #define USBH_HcInterruptEnable_FNO_Pos (5) /*!< USBH_T::HcInterruptEnable: FNO Position */
sahilmgandhi 18:6a4db94011d3 16484 #define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) /*!< USBH_T::HcInterruptEnable: FNO Mask */
sahilmgandhi 18:6a4db94011d3 16485
sahilmgandhi 18:6a4db94011d3 16486 #define USBH_HcInterruptEnable_RHSC_Pos (6) /*!< USBH_T::HcInterruptEnable: RHSC Position */
sahilmgandhi 18:6a4db94011d3 16487 #define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) /*!< USBH_T::HcInterruptEnable: RHSC Mask */
sahilmgandhi 18:6a4db94011d3 16488
sahilmgandhi 18:6a4db94011d3 16489 #define USBH_HcInterruptEnable_MIE_Pos (31) /*!< USBH_T::HcInterruptEnable: MIE Position */
sahilmgandhi 18:6a4db94011d3 16490 #define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) /*!< USBH_T::HcInterruptEnable: MIE Mask */
sahilmgandhi 18:6a4db94011d3 16491
sahilmgandhi 18:6a4db94011d3 16492 #define USBH_HcInterruptDisable_SO_Pos (0) /*!< USBH_T::HcInterruptDisable: SO Position */
sahilmgandhi 18:6a4db94011d3 16493 #define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) /*!< USBH_T::HcInterruptDisable: SO Mask */
sahilmgandhi 18:6a4db94011d3 16494
sahilmgandhi 18:6a4db94011d3 16495 #define USBH_HcInterruptDisable_WDH_Pos (1) /*!< USBH_T::HcInterruptDisable: WDH Position */
sahilmgandhi 18:6a4db94011d3 16496 #define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) /*!< USBH_T::HcInterruptDisable: WDH Mask */
sahilmgandhi 18:6a4db94011d3 16497
sahilmgandhi 18:6a4db94011d3 16498 #define USBH_HcInterruptDisable_SF_Pos (2) /*!< USBH_T::HcInterruptDisable: SF Position */
sahilmgandhi 18:6a4db94011d3 16499 #define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) /*!< USBH_T::HcInterruptDisable: SF Mask */
sahilmgandhi 18:6a4db94011d3 16500
sahilmgandhi 18:6a4db94011d3 16501 #define USBH_HcInterruptDisable_RD_Pos (3) /*!< USBH_T::HcInterruptDisable: RD Position */
sahilmgandhi 18:6a4db94011d3 16502 #define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) /*!< USBH_T::HcInterruptDisable: RD Mask */
sahilmgandhi 18:6a4db94011d3 16503
sahilmgandhi 18:6a4db94011d3 16504 #define USBH_HcInterruptDisable_FNO_Pos (5) /*!< USBH_T::HcInterruptDisable: FNO Position */
sahilmgandhi 18:6a4db94011d3 16505 #define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) /*!< USBH_T::HcInterruptDisable: FNO Mask */
sahilmgandhi 18:6a4db94011d3 16506
sahilmgandhi 18:6a4db94011d3 16507 #define USBH_HcInterruptDisable_RHSC_Pos (6) /*!< USBH_T::HcInterruptDisable: RHSC Position */
sahilmgandhi 18:6a4db94011d3 16508 #define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) /*!< USBH_T::HcInterruptDisable: RHSC Mask */
sahilmgandhi 18:6a4db94011d3 16509
sahilmgandhi 18:6a4db94011d3 16510 #define USBH_HcInterruptDisable_MIE_Pos (31) /*!< USBH_T::HcInterruptDisable: MIE Position */
sahilmgandhi 18:6a4db94011d3 16511 #define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) /*!< USBH_T::HcInterruptDisable: MIE Mask */
sahilmgandhi 18:6a4db94011d3 16512
sahilmgandhi 18:6a4db94011d3 16513 #define USBH_HcHCCA_HCCA_Pos (8) /*!< USBH_T::HcHCCA: HCCA Position */
sahilmgandhi 18:6a4db94011d3 16514 #define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) /*!< USBH_T::HcHCCA: HCCA Mask */
sahilmgandhi 18:6a4db94011d3 16515
sahilmgandhi 18:6a4db94011d3 16516 #define USBH_HcPeriodCurrentED_PCED_Pos (4) /*!< USBH_T::HcPeriodCurrentED: PCED Position */
sahilmgandhi 18:6a4db94011d3 16517 #define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) /*!< USBH_T::HcPeriodCurrentED: PCED Mask */
sahilmgandhi 18:6a4db94011d3 16518
sahilmgandhi 18:6a4db94011d3 16519 #define USBH_HcControlHeadED_CHED_Pos (4) /*!< USBH_T::HcControlHeadED: CHED Position */
sahilmgandhi 18:6a4db94011d3 16520 #define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) /*!< USBH_T::HcControlHeadED: CHED Mask */
sahilmgandhi 18:6a4db94011d3 16521
sahilmgandhi 18:6a4db94011d3 16522 #define USBH_HcControlCurrentED_CCED_Pos (4) /*!< USBH_T::HcControlCurrentED: CCED Position */
sahilmgandhi 18:6a4db94011d3 16523 #define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /*!< USBH_T::HcControlCurrentED: CCED Mask */
sahilmgandhi 18:6a4db94011d3 16524
sahilmgandhi 18:6a4db94011d3 16525 #define USBH_HcBulkHeadED_BHED_Pos (4) /*!< USBH_T::HcBulkHeadED: BHED Position */
sahilmgandhi 18:6a4db94011d3 16526 #define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) /*!< USBH_T::HcBulkHeadED: BHED Mask */
sahilmgandhi 18:6a4db94011d3 16527
sahilmgandhi 18:6a4db94011d3 16528 #define USBH_HcBulkCurrentED_BCED_Pos (4) /*!< USBH_T::HcBulkCurrentED: BCED Position */
sahilmgandhi 18:6a4db94011d3 16529 #define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) /*!< USBH_T::HcBulkCurrentED: BCED Mask */
sahilmgandhi 18:6a4db94011d3 16530
sahilmgandhi 18:6a4db94011d3 16531 #define USBH_HcDoneHead_DH_Pos (4) /*!< USBH_T::HcDoneHead: DH Position */
sahilmgandhi 18:6a4db94011d3 16532 #define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) /*!< USBH_T::HcDoneHead: DH Mask */
sahilmgandhi 18:6a4db94011d3 16533
sahilmgandhi 18:6a4db94011d3 16534 #define USBH_HcFmInterval_FI_Pos (0) /*!< USBH_T::HcFmInterval: FI Position */
sahilmgandhi 18:6a4db94011d3 16535 #define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) /*!< USBH_T::HcFmInterval: FI Mask */
sahilmgandhi 18:6a4db94011d3 16536
sahilmgandhi 18:6a4db94011d3 16537 #define USBH_HcFmInterval_FSMPS_Pos (16) /*!< USBH_T::HcFmInterval: FSMPS Position */
sahilmgandhi 18:6a4db94011d3 16538 #define USBH_HcFmInterval_FSMPS_Msk (0x7ffful << USBH_HcFmInterval_FSMPS_Pos) /*!< USBH_T::HcFmInterval: FSMPS Mask */
sahilmgandhi 18:6a4db94011d3 16539
sahilmgandhi 18:6a4db94011d3 16540 #define USBH_HcFmInterval_FIT_Pos (31) /*!< USBH_T::HcFmInterval: FIT Position */
sahilmgandhi 18:6a4db94011d3 16541 #define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) /*!< USBH_T::HcFmInterval: FIT Mask */
sahilmgandhi 18:6a4db94011d3 16542
sahilmgandhi 18:6a4db94011d3 16543 #define USBH_HcFmRemaining_FR_Pos (0) /*!< USBH_T::HcFmRemaining: FR Position */
sahilmgandhi 18:6a4db94011d3 16544 #define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) /*!< USBH_T::HcFmRemaining: FR Mask */
sahilmgandhi 18:6a4db94011d3 16545
sahilmgandhi 18:6a4db94011d3 16546 #define USBH_HcFmRemaining_FRT_Pos (31) /*!< USBH_T::HcFmRemaining: FRT Position */
sahilmgandhi 18:6a4db94011d3 16547 #define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) /*!< USBH_T::HcFmRemaining: FRT Mask */
sahilmgandhi 18:6a4db94011d3 16548
sahilmgandhi 18:6a4db94011d3 16549 #define USBH_HcFmNumber_FN_Pos (0) /*!< USBH_T::HcFmNumber: FN Position */
sahilmgandhi 18:6a4db94011d3 16550 #define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) /*!< USBH_T::HcFmNumber: FN Mask */
sahilmgandhi 18:6a4db94011d3 16551
sahilmgandhi 18:6a4db94011d3 16552 #define USBH_HcPeriodicStart_PS_Pos (0) /*!< USBH_T::HcPeriodicStart: PS Position */
sahilmgandhi 18:6a4db94011d3 16553 #define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) /*!< USBH_T::HcPeriodicStart: PS Mask */
sahilmgandhi 18:6a4db94011d3 16554
sahilmgandhi 18:6a4db94011d3 16555 #define USBH_HcLSThreshold_LST_Pos (0) /*!< USBH_T::HcLSThreshold: LST Position */
sahilmgandhi 18:6a4db94011d3 16556 #define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) /*!< USBH_T::HcLSThreshold: LST Mask */
sahilmgandhi 18:6a4db94011d3 16557
sahilmgandhi 18:6a4db94011d3 16558 #define USBH_HcRhDescriptorA_NDP_Pos (0) /*!< USBH_T::HcRhDescriptorA: NDP Position */
sahilmgandhi 18:6a4db94011d3 16559 #define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) /*!< USBH_T::HcRhDescriptorA: NDP Mask */
sahilmgandhi 18:6a4db94011d3 16560
sahilmgandhi 18:6a4db94011d3 16561 #define USBH_HcRhDescriptorA_PSM_Pos (8) /*!< USBH_T::HcRhDescriptorA: PSM Position */
sahilmgandhi 18:6a4db94011d3 16562 #define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) /*!< USBH_T::HcRhDescriptorA: PSM Mask */
sahilmgandhi 18:6a4db94011d3 16563
sahilmgandhi 18:6a4db94011d3 16564 #define USBH_HcRhDescriptorA_OCPM_Pos (11) /*!< USBH_T::HcRhDescriptorA: OCPM Position */
sahilmgandhi 18:6a4db94011d3 16565 #define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) /*!< USBH_T::HcRhDescriptorA: OCPM Mask */
sahilmgandhi 18:6a4db94011d3 16566
sahilmgandhi 18:6a4db94011d3 16567 #define USBH_HcRhDescriptorA_NOCP_Pos (12) /*!< USBH_T::HcRhDescriptorA: NOCP Position */
sahilmgandhi 18:6a4db94011d3 16568 #define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) /*!< USBH_T::HcRhDescriptorA: NOCP Mask */
sahilmgandhi 18:6a4db94011d3 16569
sahilmgandhi 18:6a4db94011d3 16570 #define USBH_HcRhDescriptorB_PPCM_Pos (16) /*!< USBH_T::HcRhDescriptorB: PPCM Position */
sahilmgandhi 18:6a4db94011d3 16571 #define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) /*!< USBH_T::HcRhDescriptorB: PPCM Mask */
sahilmgandhi 18:6a4db94011d3 16572
sahilmgandhi 18:6a4db94011d3 16573 #define USBH_HcRhStatus_LPS_Pos (0) /*!< USBH_T::HcRhStatus: LPS Position */
sahilmgandhi 18:6a4db94011d3 16574 #define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) /*!< USBH_T::HcRhStatus: LPS Mask */
sahilmgandhi 18:6a4db94011d3 16575
sahilmgandhi 18:6a4db94011d3 16576 #define USBH_HcRhStatus_OCI_Pos (1) /*!< USBH_T::HcRhStatus: OCI Position */
sahilmgandhi 18:6a4db94011d3 16577 #define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) /*!< USBH_T::HcRhStatus: OCI Mask */
sahilmgandhi 18:6a4db94011d3 16578
sahilmgandhi 18:6a4db94011d3 16579 #define USBH_HcRhStatus_DRWE_Pos (15) /*!< USBH_T::HcRhStatus: DRWE Position */
sahilmgandhi 18:6a4db94011d3 16580 #define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) /*!< USBH_T::HcRhStatus: DRWE Mask */
sahilmgandhi 18:6a4db94011d3 16581
sahilmgandhi 18:6a4db94011d3 16582 #define USBH_HcRhStatus_LPSC_Pos (16) /*!< USBH_T::HcRhStatus: LPSC Position */
sahilmgandhi 18:6a4db94011d3 16583 #define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) /*!< USBH_T::HcRhStatus: LPSC Mask */
sahilmgandhi 18:6a4db94011d3 16584
sahilmgandhi 18:6a4db94011d3 16585 #define USBH_HcRhStatus_OCIC_Pos (17) /*!< USBH_T::HcRhStatus: OCIC Position */
sahilmgandhi 18:6a4db94011d3 16586 #define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) /*!< USBH_T::HcRhStatus: OCIC Mask */
sahilmgandhi 18:6a4db94011d3 16587
sahilmgandhi 18:6a4db94011d3 16588 #define USBH_HcRhStatus_CRWE_Pos (31) /*!< USBH_T::HcRhStatus: CRWE Position */
sahilmgandhi 18:6a4db94011d3 16589 #define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) /*!< USBH_T::HcRhStatus: CRWE Mask */
sahilmgandhi 18:6a4db94011d3 16590
sahilmgandhi 18:6a4db94011d3 16591 #define USBH_HcRhPortStatus_CCS_Pos (0) /*!< USBH_T::HcRhPortStatus: CCS Position */
sahilmgandhi 18:6a4db94011d3 16592 #define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos) /*!< USBH_T::HcRhPortStatus: CCS Mask */
sahilmgandhi 18:6a4db94011d3 16593
sahilmgandhi 18:6a4db94011d3 16594 #define USBH_HcRhPortStatus_PES_Pos (1) /*!< USBH_T::HcRhPortStatus: PES Position */
sahilmgandhi 18:6a4db94011d3 16595 #define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos) /*!< USBH_T::HcRhPortStatus: PES Mask */
sahilmgandhi 18:6a4db94011d3 16596
sahilmgandhi 18:6a4db94011d3 16597 #define USBH_HcRhPortStatus_PSS_Pos (2) /*!< USBH_T::HcRhPortStatus: PSS Position */
sahilmgandhi 18:6a4db94011d3 16598 #define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos) /*!< USBH_T::HcRhPortStatus: PSS Mask */
sahilmgandhi 18:6a4db94011d3 16599
sahilmgandhi 18:6a4db94011d3 16600 #define USBH_HcRhPortStatus_POCI_Pos (3) /*!< USBH_T::HcRhPortStatus: POCI Position */
sahilmgandhi 18:6a4db94011d3 16601 #define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos) /*!< USBH_T::HcRhPortStatus: POCI Mask */
sahilmgandhi 18:6a4db94011d3 16602
sahilmgandhi 18:6a4db94011d3 16603 #define USBH_HcRhPortStatus_PRS_Pos (4) /*!< USBH_T::HcRhPortStatus: PRS Position */
sahilmgandhi 18:6a4db94011d3 16604 #define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos) /*!< USBH_T::HcRhPortStatus: PRS Mask */
sahilmgandhi 18:6a4db94011d3 16605
sahilmgandhi 18:6a4db94011d3 16606 #define USBH_HcRhPortStatus_PPS_Pos (8) /*!< USBH_T::HcRhPortStatus: PPS Position */
sahilmgandhi 18:6a4db94011d3 16607 #define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos) /*!< USBH_T::HcRhPortStatus: PPS Mask */
sahilmgandhi 18:6a4db94011d3 16608
sahilmgandhi 18:6a4db94011d3 16609 #define USBH_HcRhPortStatus_LSDA_Pos (9) /*!< USBH_T::HcRhPortStatus: LSDA Position */
sahilmgandhi 18:6a4db94011d3 16610 #define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos) /*!< USBH_T::HcRhPortStatus: LSDA Mask */
sahilmgandhi 18:6a4db94011d3 16611
sahilmgandhi 18:6a4db94011d3 16612 #define USBH_HcRhPortStatus_CSC_Pos (16) /*!< USBH_T::HcRhPortStatus: CSC Position */
sahilmgandhi 18:6a4db94011d3 16613 #define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos) /*!< USBH_T::HcRhPortStatus: CSC Mask */
sahilmgandhi 18:6a4db94011d3 16614
sahilmgandhi 18:6a4db94011d3 16615 #define USBH_HcRhPortStatus_PESC_Pos (17) /*!< USBH_T::HcRhPortStatus: PESC Position */
sahilmgandhi 18:6a4db94011d3 16616 #define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos) /*!< USBH_T::HcRhPortStatus: PESC Mask */
sahilmgandhi 18:6a4db94011d3 16617
sahilmgandhi 18:6a4db94011d3 16618 #define USBH_HcRhPortStatus_PSSC_Pos (18) /*!< USBH_T::HcRhPortStatus: PSSC Position */
sahilmgandhi 18:6a4db94011d3 16619 #define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos) /*!< USBH_T::HcRhPortStatus: PSSC Mask */
sahilmgandhi 18:6a4db94011d3 16620
sahilmgandhi 18:6a4db94011d3 16621 #define USBH_HcRhPortStatus_OCIC_Pos (19) /*!< USBH_T::HcRhPortStatus: OCIC Position */
sahilmgandhi 18:6a4db94011d3 16622 #define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos) /*!< USBH_T::HcRhPortStatus: OCIC Mask */
sahilmgandhi 18:6a4db94011d3 16623
sahilmgandhi 18:6a4db94011d3 16624 #define USBH_HcRhPortStatus_PRSC_Pos (20) /*!< USBH_T::HcRhPortStatus: PRSC Position */
sahilmgandhi 18:6a4db94011d3 16625 #define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos) /*!< USBH_T::HcRhPortStatus: PRSC Mask */
sahilmgandhi 18:6a4db94011d3 16626
sahilmgandhi 18:6a4db94011d3 16627 #define USBH_HcPhyControl_STBYEN_Pos (27) /*!< USBH_T::HcPhyControl: STBYEN Position */
sahilmgandhi 18:6a4db94011d3 16628 #define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) /*!< USBH_T::HcPhyControl: STBYEN Mask */
sahilmgandhi 18:6a4db94011d3 16629
sahilmgandhi 18:6a4db94011d3 16630 #define USBH_HcMiscControl_ABORT_Pos (1) /*!< USBH_T::HcMiscControl: ABORT Position */
sahilmgandhi 18:6a4db94011d3 16631 #define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos) /*!< USBH_T::HcMiscControl: ABORT Mask */
sahilmgandhi 18:6a4db94011d3 16632
sahilmgandhi 18:6a4db94011d3 16633 #define USBH_HcMiscControl_OCAL_Pos (3) /*!< USBH_T::HcMiscControl: OCAL Position */
sahilmgandhi 18:6a4db94011d3 16634 #define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos) /*!< USBH_T::HcMiscControl: OCAL Mask */
sahilmgandhi 18:6a4db94011d3 16635
sahilmgandhi 18:6a4db94011d3 16636 #define USBH_HcMiscControl_DPRT1_Pos (16) /*!< USBH_T::HcMiscControl: DPRT1 Position */
sahilmgandhi 18:6a4db94011d3 16637 #define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos) /*!< USBH_T::HcMiscControl: DPRT1 Mask */
sahilmgandhi 18:6a4db94011d3 16638
sahilmgandhi 18:6a4db94011d3 16639 /**@}*/ /* USBH_CONST */
sahilmgandhi 18:6a4db94011d3 16640 /**@}*/ /* end of USBH register group */
sahilmgandhi 18:6a4db94011d3 16641
sahilmgandhi 18:6a4db94011d3 16642
sahilmgandhi 18:6a4db94011d3 16643 /*---------------------- Watch Dog Timer Controller -------------------------*/
sahilmgandhi 18:6a4db94011d3 16644 /**
sahilmgandhi 18:6a4db94011d3 16645 @addtogroup WDT Watch Dog Timer Controller(WDT)
sahilmgandhi 18:6a4db94011d3 16646 Memory Mapped Structure for WDT Controller
sahilmgandhi 18:6a4db94011d3 16647 @{ */
sahilmgandhi 18:6a4db94011d3 16648
sahilmgandhi 18:6a4db94011d3 16649
sahilmgandhi 18:6a4db94011d3 16650 typedef struct
sahilmgandhi 18:6a4db94011d3 16651 {
sahilmgandhi 18:6a4db94011d3 16652
sahilmgandhi 18:6a4db94011d3 16653
sahilmgandhi 18:6a4db94011d3 16654
sahilmgandhi 18:6a4db94011d3 16655
sahilmgandhi 18:6a4db94011d3 16656 /**
sahilmgandhi 18:6a4db94011d3 16657 * @var WDT_T::CTL
sahilmgandhi 18:6a4db94011d3 16658 * Offset: 0x00 WDT Control Register
sahilmgandhi 18:6a4db94011d3 16659 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 16660 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 16661 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 16662 * |[0] |RSTCNT |Reset WDT Up Counter (Write Protect)
sahilmgandhi 18:6a4db94011d3 16663 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 16664 * | | |1 = Reset the internal 18-bit WDT up counter value.
sahilmgandhi 18:6a4db94011d3 16665 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 16666 * | | |Note2: This bit will be automatically cleared by hardware.
sahilmgandhi 18:6a4db94011d3 16667 * |[1] |RSTEN |WDT Time-Out Reset Enable Control (Write Protect)
sahilmgandhi 18:6a4db94011d3 16668 * | | |Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.
sahilmgandhi 18:6a4db94011d3 16669 * | | |0 = WDT time-out reset function Disabled.
sahilmgandhi 18:6a4db94011d3 16670 * | | |1 = WDT time-out reset function Enabled.
sahilmgandhi 18:6a4db94011d3 16671 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 16672 * |[2] |RSTF |WDT Time-Out Reset Flag
sahilmgandhi 18:6a4db94011d3 16673 * | | |This bit indicates the system has been reset by WDT time-out reset or not.
sahilmgandhi 18:6a4db94011d3 16674 * | | |0 = WDT time-out reset did not occur.
sahilmgandhi 18:6a4db94011d3 16675 * | | |1 = WDT time-out reset occurred.
sahilmgandhi 18:6a4db94011d3 16676 * | | |Note: This bit is cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 16677 * |[3] |IF |WDT Time-Out Interrupt Flag
sahilmgandhi 18:6a4db94011d3 16678 * | | |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval
sahilmgandhi 18:6a4db94011d3 16679 * | | |0 = WDT time-out interrupt did not occur.
sahilmgandhi 18:6a4db94011d3 16680 * | | |1 = WDT time-out interrupt occurred.
sahilmgandhi 18:6a4db94011d3 16681 * | | |Note: This bit is cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 16682 * |[4] |WKEN |WDT Time-Out Wake-Up Function Control (Write Protect)
sahilmgandhi 18:6a4db94011d3 16683 * | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
sahilmgandhi 18:6a4db94011d3 16684 * | | |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated.
sahilmgandhi 18:6a4db94011d3 16685 * | | |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated.
sahilmgandhi 18:6a4db94011d3 16686 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 16687 * | | |Note2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillator.
sahilmgandhi 18:6a4db94011d3 16688 * |[5] |WKF |WDT Time-Out Wake-Up Flag
sahilmgandhi 18:6a4db94011d3 16689 * | | |This bit indicates the interrupt wake-up flag status of WDT
sahilmgandhi 18:6a4db94011d3 16690 * | | |0 = WDT does not cause chip wake-up.
sahilmgandhi 18:6a4db94011d3 16691 * | | |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated.
sahilmgandhi 18:6a4db94011d3 16692 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 16693 * | | |Note2: This bit is cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 16694 * |[6] |INTEN |WDT Time-Out Interrupt Enable Control (Write Protect)
sahilmgandhi 18:6a4db94011d3 16695 * | | |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
sahilmgandhi 18:6a4db94011d3 16696 * | | |0 = WDT time-out interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 16697 * | | |1 = WDT time-out interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 16698 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 16699 * |[7] |WDTEN |WDT Enable Control (Write Protect)
sahilmgandhi 18:6a4db94011d3 16700 * | | |0 = WDT Disabled (This action will reset the internal up counter value).
sahilmgandhi 18:6a4db94011d3 16701 * | | |1 = WDT Enabled.
sahilmgandhi 18:6a4db94011d3 16702 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 16703 * | | |Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configure to 111, this bit is forced as 1 and user cannot change this bit to 0.
sahilmgandhi 18:6a4db94011d3 16704 * |[10:8] |TOUTSEL |WDT Time-Out Interval Selection (Write Protect)
sahilmgandhi 18:6a4db94011d3 16705 * | | |These three bits select the time-out interval period for the WDT.
sahilmgandhi 18:6a4db94011d3 16706 * | | |000 = (2^4)*TWDT.
sahilmgandhi 18:6a4db94011d3 16707 * | | |001 = (2^6)*TWDT.
sahilmgandhi 18:6a4db94011d3 16708 * | | |010 = (2^8)*TWDT.
sahilmgandhi 18:6a4db94011d3 16709 * | | |011 = (2^10)*TWDT.
sahilmgandhi 18:6a4db94011d3 16710 * | | |100 = (2^12)*TWDT.
sahilmgandhi 18:6a4db94011d3 16711 * | | |101 = (2^14)*TWDT.
sahilmgandhi 18:6a4db94011d3 16712 * | | |110 = (2^16)*TWDT.
sahilmgandhi 18:6a4db94011d3 16713 * | | |111 = (2^18)*TWDT.
sahilmgandhi 18:6a4db94011d3 16714 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 16715 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect)
sahilmgandhi 18:6a4db94011d3 16716 * | | |0 = ICE debug mode acknowledgement affects WDT counting.
sahilmgandhi 18:6a4db94011d3 16717 * | | |WDT up counter will be held while CPU is held by ICE.
sahilmgandhi 18:6a4db94011d3 16718 * | | |1 = ICE debug mode acknowledgement Disabled.
sahilmgandhi 18:6a4db94011d3 16719 * | | |WDT up counter will keep going no matter CPU is held by ICE or not.
sahilmgandhi 18:6a4db94011d3 16720 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 16721 * @var WDT_T::ALTCTL
sahilmgandhi 18:6a4db94011d3 16722 * Offset: 0x04 WDT Alternative Control Register
sahilmgandhi 18:6a4db94011d3 16723 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 16724 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 16725 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 16726 * |[1:0] |RSTDSEL |WDT Reset Delay Selection (Write Protect)
sahilmgandhi 18:6a4db94011d3 16727 * | | |When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened.
sahilmgandhi 18:6a4db94011d3 16728 * | | |User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.
sahilmgandhi 18:6a4db94011d3 16729 * | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK.
sahilmgandhi 18:6a4db94011d3 16730 * | | |01 = WDT Reset Delay Period is 130 * WDT_CLK.
sahilmgandhi 18:6a4db94011d3 16731 * | | |10 = WDT Reset Delay Period is 18 * WDT_CLK.
sahilmgandhi 18:6a4db94011d3 16732 * | | |11 = WDT Reset Delay Period is 3 * WDT_CLK.
sahilmgandhi 18:6a4db94011d3 16733 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
sahilmgandhi 18:6a4db94011d3 16734 * | | |Note2: This register will be reset to 0 if WDT time-out reset happened.
sahilmgandhi 18:6a4db94011d3 16735 */
sahilmgandhi 18:6a4db94011d3 16736
sahilmgandhi 18:6a4db94011d3 16737 __IO uint32_t CTL; /* Offset: 0x00 WDT Control Register */
sahilmgandhi 18:6a4db94011d3 16738 __IO uint32_t ALTCTL; /* Offset: 0x04 WDT Alternative Control Register */
sahilmgandhi 18:6a4db94011d3 16739
sahilmgandhi 18:6a4db94011d3 16740 } WDT_T;
sahilmgandhi 18:6a4db94011d3 16741
sahilmgandhi 18:6a4db94011d3 16742
sahilmgandhi 18:6a4db94011d3 16743
sahilmgandhi 18:6a4db94011d3 16744 /**
sahilmgandhi 18:6a4db94011d3 16745 @addtogroup WDT_CONST WDT Bit Field Definition
sahilmgandhi 18:6a4db94011d3 16746 Constant Definitions for WDT Controller
sahilmgandhi 18:6a4db94011d3 16747 @{ */
sahilmgandhi 18:6a4db94011d3 16748
sahilmgandhi 18:6a4db94011d3 16749 #define WDT_CTL_RSTCNT_Pos (0) /*!< WDT_T::CTL: RSTCNT Position */
sahilmgandhi 18:6a4db94011d3 16750 #define WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos) /*!< WDT_T::CTL: RSTCNT Mask */
sahilmgandhi 18:6a4db94011d3 16751
sahilmgandhi 18:6a4db94011d3 16752 #define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */
sahilmgandhi 18:6a4db94011d3 16753 #define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */
sahilmgandhi 18:6a4db94011d3 16754
sahilmgandhi 18:6a4db94011d3 16755 #define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */
sahilmgandhi 18:6a4db94011d3 16756 #define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */
sahilmgandhi 18:6a4db94011d3 16757
sahilmgandhi 18:6a4db94011d3 16758 #define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */
sahilmgandhi 18:6a4db94011d3 16759 #define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */
sahilmgandhi 18:6a4db94011d3 16760
sahilmgandhi 18:6a4db94011d3 16761 #define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */
sahilmgandhi 18:6a4db94011d3 16762 #define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */
sahilmgandhi 18:6a4db94011d3 16763
sahilmgandhi 18:6a4db94011d3 16764 #define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */
sahilmgandhi 18:6a4db94011d3 16765 #define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */
sahilmgandhi 18:6a4db94011d3 16766
sahilmgandhi 18:6a4db94011d3 16767 #define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */
sahilmgandhi 18:6a4db94011d3 16768 #define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */
sahilmgandhi 18:6a4db94011d3 16769
sahilmgandhi 18:6a4db94011d3 16770 #define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */
sahilmgandhi 18:6a4db94011d3 16771 #define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */
sahilmgandhi 18:6a4db94011d3 16772
sahilmgandhi 18:6a4db94011d3 16773 #define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */
sahilmgandhi 18:6a4db94011d3 16774 #define WDT_CTL_TOUTSEL_Msk (0x7ul << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */
sahilmgandhi 18:6a4db94011d3 16775
sahilmgandhi 18:6a4db94011d3 16776 #define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */
sahilmgandhi 18:6a4db94011d3 16777 #define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */
sahilmgandhi 18:6a4db94011d3 16778
sahilmgandhi 18:6a4db94011d3 16779 #define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */
sahilmgandhi 18:6a4db94011d3 16780 #define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */
sahilmgandhi 18:6a4db94011d3 16781
sahilmgandhi 18:6a4db94011d3 16782 /**@}*/ /* WDT_CONST */
sahilmgandhi 18:6a4db94011d3 16783 /**@}*/ /* end of WDT register group */
sahilmgandhi 18:6a4db94011d3 16784
sahilmgandhi 18:6a4db94011d3 16785
sahilmgandhi 18:6a4db94011d3 16786 /*---------------------- Window Watchdog Timer -------------------------*/
sahilmgandhi 18:6a4db94011d3 16787 /**
sahilmgandhi 18:6a4db94011d3 16788 @addtogroup WWDT Window Watchdog Timer(WWDT)
sahilmgandhi 18:6a4db94011d3 16789 Memory Mapped Structure for WWDT Controller
sahilmgandhi 18:6a4db94011d3 16790 @{ */
sahilmgandhi 18:6a4db94011d3 16791
sahilmgandhi 18:6a4db94011d3 16792
sahilmgandhi 18:6a4db94011d3 16793 typedef struct
sahilmgandhi 18:6a4db94011d3 16794 {
sahilmgandhi 18:6a4db94011d3 16795
sahilmgandhi 18:6a4db94011d3 16796
sahilmgandhi 18:6a4db94011d3 16797
sahilmgandhi 18:6a4db94011d3 16798
sahilmgandhi 18:6a4db94011d3 16799 /**
sahilmgandhi 18:6a4db94011d3 16800 * @var WWDT_T::RLDCNT
sahilmgandhi 18:6a4db94011d3 16801 * Offset: 0x00 WWDT Reload Counter Register
sahilmgandhi 18:6a4db94011d3 16802 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 16803 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 16804 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 16805 * |[31:0] |WWDT_RLDCNT|WWDT Reload Counter Register
sahilmgandhi 18:6a4db94011d3 16806 * | | |Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
sahilmgandhi 18:6a4db94011d3 16807 * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]).
sahilmgandhi 18:6a4db94011d3 16808 * | | |If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT , WWDT reset signal will generate immediately.
sahilmgandhi 18:6a4db94011d3 16809 * @var WWDT_T::CTL
sahilmgandhi 18:6a4db94011d3 16810 * Offset: 0x04 WWDT Control Register
sahilmgandhi 18:6a4db94011d3 16811 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 16812 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 16813 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 16814 * |[0] |WWDTEN |WWDT Enable Control Bit
sahilmgandhi 18:6a4db94011d3 16815 * | | |Set this bit to enable WWDT counter counting.
sahilmgandhi 18:6a4db94011d3 16816 * | | |0 = WWDT counter is stopped.
sahilmgandhi 18:6a4db94011d3 16817 * | | |1 = WWDT counter is starting counting.
sahilmgandhi 18:6a4db94011d3 16818 * |[1] |INTEN |WWDT Interrupt Enable Control Bit
sahilmgandhi 18:6a4db94011d3 16819 * | | |If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.
sahilmgandhi 18:6a4db94011d3 16820 * | | |0 = WWDT counter compare match interrupt Disabled.
sahilmgandhi 18:6a4db94011d3 16821 * | | |1 = WWDT counter compare match interrupt Enabled.
sahilmgandhi 18:6a4db94011d3 16822 * |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection
sahilmgandhi 18:6a4db94011d3 16823 * | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * TWWDT.
sahilmgandhi 18:6a4db94011d3 16824 * | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * TWWDT.
sahilmgandhi 18:6a4db94011d3 16825 * | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * TWWDT.
sahilmgandhi 18:6a4db94011d3 16826 * | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * TWWDT.
sahilmgandhi 18:6a4db94011d3 16827 * | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * TWWDT.
sahilmgandhi 18:6a4db94011d3 16828 * | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * TWWDT.
sahilmgandhi 18:6a4db94011d3 16829 * | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * TWWDT.
sahilmgandhi 18:6a4db94011d3 16830 * | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * TWWDT.
sahilmgandhi 18:6a4db94011d3 16831 * | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * TWWDT.
sahilmgandhi 18:6a4db94011d3 16832 * | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * TWWDT.
sahilmgandhi 18:6a4db94011d3 16833 * | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * TWWDT.
sahilmgandhi 18:6a4db94011d3 16834 * | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * TWWDT.
sahilmgandhi 18:6a4db94011d3 16835 * | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * TWWDT.
sahilmgandhi 18:6a4db94011d3 16836 * | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * TWWDT.
sahilmgandhi 18:6a4db94011d3 16837 * | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * TWWDT.
sahilmgandhi 18:6a4db94011d3 16838 * | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * TWWDT.
sahilmgandhi 18:6a4db94011d3 16839 * |[21:16] |CMPDAT |WWDT Window Compare Register
sahilmgandhi 18:6a4db94011d3 16840 * | | |Set this register to adjust the valid reload window.
sahilmgandhi 18:6a4db94011d3 16841 * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.
sahilmgandhi 18:6a4db94011d3 16842 * | | |If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
sahilmgandhi 18:6a4db94011d3 16843 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control
sahilmgandhi 18:6a4db94011d3 16844 * | | |0 = ICE debug mode acknowledgement effects WWDT counting.
sahilmgandhi 18:6a4db94011d3 16845 * | | |WWDT down counter will be held while CPU is held by ICE.
sahilmgandhi 18:6a4db94011d3 16846 * | | |1 = ICE debug mode acknowledgement Disabled.
sahilmgandhi 18:6a4db94011d3 16847 * | | |WWDT down counter will keep going no matter CPU is held by ICE or not.
sahilmgandhi 18:6a4db94011d3 16848 * @var WWDT_T::STATUS
sahilmgandhi 18:6a4db94011d3 16849 * Offset: 0x08 WWDT Status Register
sahilmgandhi 18:6a4db94011d3 16850 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 16851 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 16852 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 16853 * |[0] |WWDTIF |WWDT Compare Match Interrupt Flag
sahilmgandhi 18:6a4db94011d3 16854 * | | |This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).
sahilmgandhi 18:6a4db94011d3 16855 * | | |0 = No effect.
sahilmgandhi 18:6a4db94011d3 16856 * | | |1 = WWDT counter value matches CMPDAT.
sahilmgandhi 18:6a4db94011d3 16857 * | | |Note: This bit is cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 16858 * |[1] |WWDTRF |WWDT Timer-Out Reset Flag
sahilmgandhi 18:6a4db94011d3 16859 * | | |This bit indicates the system has been reset by WWDT time-out reset or not.
sahilmgandhi 18:6a4db94011d3 16860 * | | |0 = WWDT time-out reset did not occur.
sahilmgandhi 18:6a4db94011d3 16861 * | | |1 = WWDT time-out reset occurred.
sahilmgandhi 18:6a4db94011d3 16862 * | | |Note: This bit is cleared by writing 1 to it.
sahilmgandhi 18:6a4db94011d3 16863 * @var WWDT_T::CNT
sahilmgandhi 18:6a4db94011d3 16864 * Offset: 0x0C WWDT Counter Value Register
sahilmgandhi 18:6a4db94011d3 16865 * ---------------------------------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 16866 * |Bits |Field |Descriptions
sahilmgandhi 18:6a4db94011d3 16867 * | :----: | :----: | :---- |
sahilmgandhi 18:6a4db94011d3 16868 * |[5:0] |CNTDAT |WWDT Counter Value
sahilmgandhi 18:6a4db94011d3 16869 * | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.
sahilmgandhi 18:6a4db94011d3 16870 */
sahilmgandhi 18:6a4db94011d3 16871
sahilmgandhi 18:6a4db94011d3 16872 __O uint32_t RLDCNT; /* Offset: 0x00 WWDT Reload Counter Register */
sahilmgandhi 18:6a4db94011d3 16873 __IO uint32_t CTL; /* Offset: 0x04 WWDT Control Register */
sahilmgandhi 18:6a4db94011d3 16874 __IO uint32_t STATUS; /* Offset: 0x08 WWDT Status Register */
sahilmgandhi 18:6a4db94011d3 16875 __I uint32_t CNT; /* Offset: 0x0C WWDT Counter Value Register */
sahilmgandhi 18:6a4db94011d3 16876
sahilmgandhi 18:6a4db94011d3 16877 } WWDT_T;
sahilmgandhi 18:6a4db94011d3 16878
sahilmgandhi 18:6a4db94011d3 16879
sahilmgandhi 18:6a4db94011d3 16880
sahilmgandhi 18:6a4db94011d3 16881 /**
sahilmgandhi 18:6a4db94011d3 16882 @addtogroup WWDT_CONST WWDT Bit Field Definition
sahilmgandhi 18:6a4db94011d3 16883 Constant Definitions for WWDT Controller
sahilmgandhi 18:6a4db94011d3 16884 @{ */
sahilmgandhi 18:6a4db94011d3 16885
sahilmgandhi 18:6a4db94011d3 16886 #define WWDT_RLDCNT_WWDT_RLDCNT_Pos (0) /*!< WWDT_T::RLDCNT: WWDT_RLDCNT Position */
sahilmgandhi 18:6a4db94011d3 16887 #define WWDT_RLDCNT_WWDT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_WWDT_RLDCNT_Pos) /*!< WWDT_T::RLDCNT: WWDT_RLDCNT Mask */
sahilmgandhi 18:6a4db94011d3 16888
sahilmgandhi 18:6a4db94011d3 16889 #define WWDT_CTL_WWDTEN_Pos (0) /*!< WWDT_T::CTL: WWDTEN Position */
sahilmgandhi 18:6a4db94011d3 16890 #define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /*!< WWDT_T::CTL: WWDTEN Mask */
sahilmgandhi 18:6a4db94011d3 16891
sahilmgandhi 18:6a4db94011d3 16892 #define WWDT_CTL_INTEN_Pos (1) /*!< WWDT_T::CTL: INTEN Position */
sahilmgandhi 18:6a4db94011d3 16893 #define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /*!< WWDT_T::CTL: INTEN Mask */
sahilmgandhi 18:6a4db94011d3 16894
sahilmgandhi 18:6a4db94011d3 16895 #define WWDT_CTL_PSCSEL_Pos (8) /*!< WWDT_T::CTL: PSCSEL Position */
sahilmgandhi 18:6a4db94011d3 16896 #define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /*!< WWDT_T::CTL: PSCSEL Mask */
sahilmgandhi 18:6a4db94011d3 16897
sahilmgandhi 18:6a4db94011d3 16898 #define WWDT_CTL_CMPDAT_Pos (16) /*!< WWDT_T::CTL: CMPDAT Position */
sahilmgandhi 18:6a4db94011d3 16899 #define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /*!< WWDT_T::CTL: CMPDAT Mask */
sahilmgandhi 18:6a4db94011d3 16900
sahilmgandhi 18:6a4db94011d3 16901 #define WWDT_CTL_ICEDEBUG_Pos (31) /*!< WWDT_T::CTL: ICEDEBUG Position */
sahilmgandhi 18:6a4db94011d3 16902 #define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /*!< WWDT_T::CTL: ICEDEBUG Mask */
sahilmgandhi 18:6a4db94011d3 16903
sahilmgandhi 18:6a4db94011d3 16904 #define WWDT_STATUS_WWDTIF_Pos (0) /*!< WWDT_T::STATUS: WWDTIF Position */
sahilmgandhi 18:6a4db94011d3 16905 #define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /*!< WWDT_T::STATUS: WWDTIF Mask */
sahilmgandhi 18:6a4db94011d3 16906
sahilmgandhi 18:6a4db94011d3 16907 #define WWDT_STATUS_WWDTRF_Pos (1) /*!< WWDT_T::STATUS: WWDTRF Position */
sahilmgandhi 18:6a4db94011d3 16908 #define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /*!< WWDT_T::STATUS: WWDTRF Mask */
sahilmgandhi 18:6a4db94011d3 16909
sahilmgandhi 18:6a4db94011d3 16910 #define WWDT_CNT_CNTDAT_Pos (0) /*!< WWDT_T::CNT: CNTDAT Position */
sahilmgandhi 18:6a4db94011d3 16911 #define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /*!< WWDT_T::CNT: CNTDAT Mask */
sahilmgandhi 18:6a4db94011d3 16912
sahilmgandhi 18:6a4db94011d3 16913 /**@}*/ /* WWDT_CONST */
sahilmgandhi 18:6a4db94011d3 16914 /**@}*/ /* end of WWDT register group */
sahilmgandhi 18:6a4db94011d3 16915
sahilmgandhi 18:6a4db94011d3 16916
sahilmgandhi 18:6a4db94011d3 16917 /**@}*/ /* end of REGISTER group */
sahilmgandhi 18:6a4db94011d3 16918
sahilmgandhi 18:6a4db94011d3 16919
sahilmgandhi 18:6a4db94011d3 16920 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 16921 /* Peripheral memory map */
sahilmgandhi 18:6a4db94011d3 16922 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 16923 /** @addtogroup MemoryMap Memory Mapping
sahilmgandhi 18:6a4db94011d3 16924 @{
sahilmgandhi 18:6a4db94011d3 16925 */
sahilmgandhi 18:6a4db94011d3 16926
sahilmgandhi 18:6a4db94011d3 16927 /* Peripheral and SRAM base address */
sahilmgandhi 18:6a4db94011d3 16928 #define SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
sahilmgandhi 18:6a4db94011d3 16929 #define PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
sahilmgandhi 18:6a4db94011d3 16930
sahilmgandhi 18:6a4db94011d3 16931
sahilmgandhi 18:6a4db94011d3 16932 /* Peripheral memory map */
sahilmgandhi 18:6a4db94011d3 16933 #define AHBPERIPH_BASE PERIPH_BASE
sahilmgandhi 18:6a4db94011d3 16934 #define APBPERIPH_BASE (PERIPH_BASE + 0x00040000)
sahilmgandhi 18:6a4db94011d3 16935
sahilmgandhi 18:6a4db94011d3 16936 /*!< AHB peripherals */
sahilmgandhi 18:6a4db94011d3 16937 #define GCR_BASE (AHBPERIPH_BASE + 0x00000)
sahilmgandhi 18:6a4db94011d3 16938 #define CLK_BASE (AHBPERIPH_BASE + 0x00200)
sahilmgandhi 18:6a4db94011d3 16939 #define INT_BASE (AHBPERIPH_BASE + 0x00300)
sahilmgandhi 18:6a4db94011d3 16940 #define GPIO_BASE (AHBPERIPH_BASE + 0x04000)
sahilmgandhi 18:6a4db94011d3 16941 #define GPIOA_BASE (AHBPERIPH_BASE + 0x04000)
sahilmgandhi 18:6a4db94011d3 16942 #define GPIOB_BASE (AHBPERIPH_BASE + 0x04040)
sahilmgandhi 18:6a4db94011d3 16943 #define GPIOC_BASE (AHBPERIPH_BASE + 0x04080)
sahilmgandhi 18:6a4db94011d3 16944 #define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0)
sahilmgandhi 18:6a4db94011d3 16945 #define GPIOE_BASE (AHBPERIPH_BASE + 0x04100)
sahilmgandhi 18:6a4db94011d3 16946 #define GPIOF_BASE (AHBPERIPH_BASE + 0x04140)
sahilmgandhi 18:6a4db94011d3 16947 #define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440)
sahilmgandhi 18:6a4db94011d3 16948 #define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800)
sahilmgandhi 18:6a4db94011d3 16949 #define PDMA_BASE (AHBPERIPH_BASE + 0x08000)
sahilmgandhi 18:6a4db94011d3 16950 #define USBH_BASE (AHBPERIPH_BASE + 0x09000)
sahilmgandhi 18:6a4db94011d3 16951 #define FMC_BASE (AHBPERIPH_BASE + 0x0C000)
sahilmgandhi 18:6a4db94011d3 16952 #define EBI_BASE (AHBPERIPH_BASE + 0x10000)
sahilmgandhi 18:6a4db94011d3 16953 #define CRC_BASE (AHBPERIPH_BASE + 0x31000)
sahilmgandhi 18:6a4db94011d3 16954
sahilmgandhi 18:6a4db94011d3 16955 /*!< APB0 peripherals */
sahilmgandhi 18:6a4db94011d3 16956 #define WDT_BASE (APBPERIPH_BASE + 0x00000)
sahilmgandhi 18:6a4db94011d3 16957 #define WWDT_BASE (APBPERIPH_BASE + 0x00100)
sahilmgandhi 18:6a4db94011d3 16958 #define TMR01_BASE (APBPERIPH_BASE + 0x10000)
sahilmgandhi 18:6a4db94011d3 16959 #define PWM0_BASE (APBPERIPH_BASE + 0x18000)
sahilmgandhi 18:6a4db94011d3 16960 #define SPI0_BASE (APBPERIPH_BASE + 0x20000)
sahilmgandhi 18:6a4db94011d3 16961 #define SPI2_BASE (APBPERIPH_BASE + 0x22000)
sahilmgandhi 18:6a4db94011d3 16962 #define UART0_BASE (APBPERIPH_BASE + 0x30000)
sahilmgandhi 18:6a4db94011d3 16963 #define UART2_BASE (APBPERIPH_BASE + 0x32000)
sahilmgandhi 18:6a4db94011d3 16964 #define I2C0_BASE (APBPERIPH_BASE + 0x40000)
sahilmgandhi 18:6a4db94011d3 16965 #define SC0_BASE (APBPERIPH_BASE + 0x50000)
sahilmgandhi 18:6a4db94011d3 16966 #define CAN0_BASE (APBPERIPH_BASE + 0x60000)
sahilmgandhi 18:6a4db94011d3 16967 #define USBD_BASE (APBPERIPH_BASE + 0x80000)
sahilmgandhi 18:6a4db94011d3 16968 #define TK_BASE (APBPERIPH_BASE + 0xA2000)
sahilmgandhi 18:6a4db94011d3 16969
sahilmgandhi 18:6a4db94011d3 16970 /*!< APB1 peripherals */
sahilmgandhi 18:6a4db94011d3 16971 #define RTC_BASE (APBPERIPH_BASE + 0x01000)
sahilmgandhi 18:6a4db94011d3 16972 #define EADC0_BASE (APBPERIPH_BASE + 0x03000)
sahilmgandhi 18:6a4db94011d3 16973 #define ACMP01_BASE (APBPERIPH_BASE + 0x05000)
sahilmgandhi 18:6a4db94011d3 16974 #define DAC_BASE (APBPERIPH_BASE + 0x07000)
sahilmgandhi 18:6a4db94011d3 16975 #define OTG_BASE (APBPERIPH_BASE + 0x0D000)
sahilmgandhi 18:6a4db94011d3 16976 #define TMR23_BASE (APBPERIPH_BASE + 0x11000)
sahilmgandhi 18:6a4db94011d3 16977 #define PWM1_BASE (APBPERIPH_BASE + 0x19000)
sahilmgandhi 18:6a4db94011d3 16978 #define SPI1_BASE (APBPERIPH_BASE + 0x21000)
sahilmgandhi 18:6a4db94011d3 16979 #define UART1_BASE (APBPERIPH_BASE + 0x31000)
sahilmgandhi 18:6a4db94011d3 16980 #define UART3_BASE (APBPERIPH_BASE + 0x33000)
sahilmgandhi 18:6a4db94011d3 16981 #define I2C1_BASE (APBPERIPH_BASE + 0x41000)
sahilmgandhi 18:6a4db94011d3 16982 /*@}*/ /* end of group MemoryMap */
sahilmgandhi 18:6a4db94011d3 16983
sahilmgandhi 18:6a4db94011d3 16984
sahilmgandhi 18:6a4db94011d3 16985 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 16986 /* Peripheral declaration */
sahilmgandhi 18:6a4db94011d3 16987 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 16988 /** @addtogroup PeripheralDecl Peripheral Declaration
sahilmgandhi 18:6a4db94011d3 16989 @{
sahilmgandhi 18:6a4db94011d3 16990 */
sahilmgandhi 18:6a4db94011d3 16991
sahilmgandhi 18:6a4db94011d3 16992
sahilmgandhi 18:6a4db94011d3 16993 #define SYS ((SYS_T *) GCR_BASE)
sahilmgandhi 18:6a4db94011d3 16994 #define SYSINT ((SYS_INT_T *) INT_BASE)
sahilmgandhi 18:6a4db94011d3 16995 #define CLK ((CLK_T *) CLK_BASE)
sahilmgandhi 18:6a4db94011d3 16996 #define PA ((GPIO_T *) GPIOA_BASE)
sahilmgandhi 18:6a4db94011d3 16997 #define PB ((GPIO_T *) GPIOB_BASE)
sahilmgandhi 18:6a4db94011d3 16998 #define PC ((GPIO_T *) GPIOC_BASE)
sahilmgandhi 18:6a4db94011d3 16999 #define PD ((GPIO_T *) GPIOD_BASE)
sahilmgandhi 18:6a4db94011d3 17000 #define PE ((GPIO_T *) GPIOE_BASE)
sahilmgandhi 18:6a4db94011d3 17001 #define PF ((GPIO_T *) GPIOF_BASE)
sahilmgandhi 18:6a4db94011d3 17002 #define GPIO ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE)
sahilmgandhi 18:6a4db94011d3 17003 #define PDMA ((PDMA_T *) PDMA_BASE)
sahilmgandhi 18:6a4db94011d3 17004 #define USBH ((USBH_T *) USBH_BASE)
sahilmgandhi 18:6a4db94011d3 17005 #define FMC ((FMC_T *) FMC_BASE)
sahilmgandhi 18:6a4db94011d3 17006 #define EBI ((EBI_T *) EBI_BASE)
sahilmgandhi 18:6a4db94011d3 17007 #define CRC ((CRC_T *) CRC_BASE)
sahilmgandhi 18:6a4db94011d3 17008
sahilmgandhi 18:6a4db94011d3 17009 #define WDT ((WDT_T *) WDT_BASE)
sahilmgandhi 18:6a4db94011d3 17010 #define WWDT ((WWDT_T *) WWDT_BASE)
sahilmgandhi 18:6a4db94011d3 17011 #define RTC ((RTC_T *) RTC_BASE)
sahilmgandhi 18:6a4db94011d3 17012 #define EADC ((EADC_T *) EADC0_BASE)
sahilmgandhi 18:6a4db94011d3 17013 #define ACMP01 ((ACMP_T *) ACMP01_BASE)
sahilmgandhi 18:6a4db94011d3 17014
sahilmgandhi 18:6a4db94011d3 17015 #define USBD ((USBD_T *) USBD_BASE)
sahilmgandhi 18:6a4db94011d3 17016 #define OTG ((OTG_T *) OTG_BASE)
sahilmgandhi 18:6a4db94011d3 17017 #define TIMER0 ((TIMER_T *) TMR01_BASE)
sahilmgandhi 18:6a4db94011d3 17018 #define TIMER1 ((TIMER_T *) (TMR01_BASE + 0x20))
sahilmgandhi 18:6a4db94011d3 17019 #define TIMER2 ((TIMER_T *) TMR23_BASE)
sahilmgandhi 18:6a4db94011d3 17020 #define TIMER3 ((TIMER_T *) (TMR23_BASE+ 0x20))
sahilmgandhi 18:6a4db94011d3 17021 #define PWM0 ((PWM_T *) PWM0_BASE)
sahilmgandhi 18:6a4db94011d3 17022 #define PWM1 ((PWM_T *) PWM1_BASE)
sahilmgandhi 18:6a4db94011d3 17023 #define DAC ((DAC_T *) DAC_BASE)
sahilmgandhi 18:6a4db94011d3 17024 #define SPI0 ((SPI_T *) SPI0_BASE)
sahilmgandhi 18:6a4db94011d3 17025 #define SPI1 ((SPI_T *) SPI1_BASE)
sahilmgandhi 18:6a4db94011d3 17026 #define SPI2 ((SPI_T *) SPI2_BASE)
sahilmgandhi 18:6a4db94011d3 17027 #define UART0 ((UART_T *) UART0_BASE)
sahilmgandhi 18:6a4db94011d3 17028 #define UART1 ((UART_T *) UART1_BASE)
sahilmgandhi 18:6a4db94011d3 17029 #define UART2 ((UART_T *) UART2_BASE)
sahilmgandhi 18:6a4db94011d3 17030 #define UART3 ((UART_T *) UART3_BASE)
sahilmgandhi 18:6a4db94011d3 17031 #define I2C0 ((I2C_T *) I2C0_BASE)
sahilmgandhi 18:6a4db94011d3 17032 #define I2C1 ((I2C_T *) I2C1_BASE)
sahilmgandhi 18:6a4db94011d3 17033 #define SC0 ((SC_T *) SC0_BASE)
sahilmgandhi 18:6a4db94011d3 17034 #define CAN0 ((CAN_T *) CAN0_BASE)
sahilmgandhi 18:6a4db94011d3 17035 #define TK ((TK_T *) TK_BASE)
sahilmgandhi 18:6a4db94011d3 17036
sahilmgandhi 18:6a4db94011d3 17037 /* One Bit Mask Definitions */
sahilmgandhi 18:6a4db94011d3 17038 #define BIT0 0x00000001
sahilmgandhi 18:6a4db94011d3 17039 #define BIT1 0x00000002
sahilmgandhi 18:6a4db94011d3 17040 #define BIT2 0x00000004
sahilmgandhi 18:6a4db94011d3 17041 #define BIT3 0x00000008
sahilmgandhi 18:6a4db94011d3 17042 #define BIT4 0x00000010
sahilmgandhi 18:6a4db94011d3 17043 #define BIT5 0x00000020
sahilmgandhi 18:6a4db94011d3 17044 #define BIT6 0x00000040
sahilmgandhi 18:6a4db94011d3 17045 #define BIT7 0x00000080
sahilmgandhi 18:6a4db94011d3 17046 #define BIT8 0x00000100
sahilmgandhi 18:6a4db94011d3 17047 #define BIT9 0x00000200
sahilmgandhi 18:6a4db94011d3 17048 #define BIT10 0x00000400
sahilmgandhi 18:6a4db94011d3 17049 #define BIT11 0x00000800
sahilmgandhi 18:6a4db94011d3 17050 #define BIT12 0x00001000
sahilmgandhi 18:6a4db94011d3 17051 #define BIT13 0x00002000
sahilmgandhi 18:6a4db94011d3 17052 #define BIT14 0x00004000
sahilmgandhi 18:6a4db94011d3 17053 #define BIT15 0x00008000
sahilmgandhi 18:6a4db94011d3 17054 #define BIT16 0x00010000
sahilmgandhi 18:6a4db94011d3 17055 #define BIT17 0x00020000
sahilmgandhi 18:6a4db94011d3 17056 #define BIT18 0x00040000
sahilmgandhi 18:6a4db94011d3 17057 #define BIT19 0x00080000
sahilmgandhi 18:6a4db94011d3 17058 #define BIT20 0x00100000
sahilmgandhi 18:6a4db94011d3 17059 #define BIT21 0x00200000
sahilmgandhi 18:6a4db94011d3 17060 #define BIT22 0x00400000
sahilmgandhi 18:6a4db94011d3 17061 #define BIT23 0x00800000
sahilmgandhi 18:6a4db94011d3 17062 #define BIT24 0x01000000
sahilmgandhi 18:6a4db94011d3 17063 #define BIT25 0x02000000
sahilmgandhi 18:6a4db94011d3 17064 #define BIT26 0x04000000
sahilmgandhi 18:6a4db94011d3 17065 #define BIT27 0x08000000
sahilmgandhi 18:6a4db94011d3 17066 #define BIT28 0x10000000
sahilmgandhi 18:6a4db94011d3 17067 #define BIT29 0x20000000
sahilmgandhi 18:6a4db94011d3 17068 #define BIT30 0x40000000
sahilmgandhi 18:6a4db94011d3 17069 #define BIT31 0x80000000
sahilmgandhi 18:6a4db94011d3 17070
sahilmgandhi 18:6a4db94011d3 17071 /* Byte Mask Definitions */
sahilmgandhi 18:6a4db94011d3 17072 #define BYTE0_Msk (0x000000FF)
sahilmgandhi 18:6a4db94011d3 17073 #define BYTE1_Msk (0x0000FF00)
sahilmgandhi 18:6a4db94011d3 17074 #define BYTE2_Msk (0x00FF0000)
sahilmgandhi 18:6a4db94011d3 17075 #define BYTE3_Msk (0xFF000000)
sahilmgandhi 18:6a4db94011d3 17076
sahilmgandhi 18:6a4db94011d3 17077 #define _GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */
sahilmgandhi 18:6a4db94011d3 17078 #define _GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */
sahilmgandhi 18:6a4db94011d3 17079 #define _GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
sahilmgandhi 18:6a4db94011d3 17080 #define _GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */
sahilmgandhi 18:6a4db94011d3 17081
sahilmgandhi 18:6a4db94011d3 17082 #ifndef TRUE
sahilmgandhi 18:6a4db94011d3 17083 # define TRUE 1
sahilmgandhi 18:6a4db94011d3 17084 #endif
sahilmgandhi 18:6a4db94011d3 17085 #ifndef FALSE
sahilmgandhi 18:6a4db94011d3 17086 # define FALSE 0
sahilmgandhi 18:6a4db94011d3 17087 #endif
sahilmgandhi 18:6a4db94011d3 17088
sahilmgandhi 18:6a4db94011d3 17089 #ifndef NULL
sahilmgandhi 18:6a4db94011d3 17090 #define NULL 0
sahilmgandhi 18:6a4db94011d3 17091 #endif
sahilmgandhi 18:6a4db94011d3 17092
sahilmgandhi 18:6a4db94011d3 17093 #include "m451_sys.h"
sahilmgandhi 18:6a4db94011d3 17094 #include "m451_clk.h"
sahilmgandhi 18:6a4db94011d3 17095 #include "m451_gpio.h"
sahilmgandhi 18:6a4db94011d3 17096 #include "m451_i2c.h"
sahilmgandhi 18:6a4db94011d3 17097 #include "m451_crc.h"
sahilmgandhi 18:6a4db94011d3 17098 #include "m451_ebi.h"
sahilmgandhi 18:6a4db94011d3 17099 #include "m451_rtc.h"
sahilmgandhi 18:6a4db94011d3 17100 #include "m451_timer.h"
sahilmgandhi 18:6a4db94011d3 17101 #include "m451_wdt.h"
sahilmgandhi 18:6a4db94011d3 17102 #include "m451_wwdt.h"
sahilmgandhi 18:6a4db94011d3 17103 #include "m451_spi.h"
sahilmgandhi 18:6a4db94011d3 17104 #include "m451_sc.h"
sahilmgandhi 18:6a4db94011d3 17105 #include "m451_scuart.h"
sahilmgandhi 18:6a4db94011d3 17106 #include "m451_acmp.h"
sahilmgandhi 18:6a4db94011d3 17107 #include "m451_eadc.h"
sahilmgandhi 18:6a4db94011d3 17108 #include "m451_dac.h"
sahilmgandhi 18:6a4db94011d3 17109 #include "m451_can.h"
sahilmgandhi 18:6a4db94011d3 17110 #include "m451_usbd.h"
sahilmgandhi 18:6a4db94011d3 17111 #include "m451_fmc.h"
sahilmgandhi 18:6a4db94011d3 17112 #include "m451_uart.h"
sahilmgandhi 18:6a4db94011d3 17113 #include "m451_pwm.h"
sahilmgandhi 18:6a4db94011d3 17114 #include "m451_pdma.h"
sahilmgandhi 18:6a4db94011d3 17115 #include "m451_tk.h"
sahilmgandhi 18:6a4db94011d3 17116 #include "m451_otg.h"
sahilmgandhi 18:6a4db94011d3 17117
sahilmgandhi 18:6a4db94011d3 17118 typedef volatile unsigned char vu8;
sahilmgandhi 18:6a4db94011d3 17119 typedef volatile unsigned long vu32;
sahilmgandhi 18:6a4db94011d3 17120 typedef volatile unsigned short vu16;
sahilmgandhi 18:6a4db94011d3 17121 #define M8(adr) (*((vu8 *) (adr)))
sahilmgandhi 18:6a4db94011d3 17122 #define M16(adr) (*((vu16 *) (adr)))
sahilmgandhi 18:6a4db94011d3 17123 #define M32(adr) (*((vu32 *) (adr)))
sahilmgandhi 18:6a4db94011d3 17124
sahilmgandhi 18:6a4db94011d3 17125 #define outpw(port,value) (*((volatile unsigned int *)(port))=(value))
sahilmgandhi 18:6a4db94011d3 17126 #define inpw(port) (*((volatile unsigned int *)(port)))
sahilmgandhi 18:6a4db94011d3 17127 #define outpb(port,value) (*((volatile unsigned char *)(port))=(value))
sahilmgandhi 18:6a4db94011d3 17128 #define inpb(port) (*((volatile unsigned char *)(port)))
sahilmgandhi 18:6a4db94011d3 17129 #define outps(port,value) (*((volatile unsigned short *)(port))=(value))
sahilmgandhi 18:6a4db94011d3 17130 #define inps(port) (*((volatile unsigned short *)(port)))
sahilmgandhi 18:6a4db94011d3 17131
sahilmgandhi 18:6a4db94011d3 17132 #define outp32(port,value) (*((volatile unsigned int *)(port))=(value))
sahilmgandhi 18:6a4db94011d3 17133 #define inp32(port) (*((volatile unsigned int *)(port)))
sahilmgandhi 18:6a4db94011d3 17134 #define outp8(port,value) (*((volatile unsigned char *)(port))=(value))
sahilmgandhi 18:6a4db94011d3 17135 #define inp8(port) (*((volatile unsigned char *)(port)))
sahilmgandhi 18:6a4db94011d3 17136 #define outp16(port,value) (*((volatile unsigned short *)(port))=(value))
sahilmgandhi 18:6a4db94011d3 17137 #define inp16(port) (*((volatile unsigned short *)(port)))
sahilmgandhi 18:6a4db94011d3 17138
sahilmgandhi 18:6a4db94011d3 17139 /*@}*/ /* end of group PeripheralDecl */
sahilmgandhi 18:6a4db94011d3 17140
sahilmgandhi 18:6a4db94011d3 17141 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 17142 }
sahilmgandhi 18:6a4db94011d3 17143 #endif
sahilmgandhi 18:6a4db94011d3 17144
sahilmgandhi 18:6a4db94011d3 17145 #endif /* __M451SERIES_H__ */
sahilmgandhi 18:6a4db94011d3 17146
sahilmgandhi 18:6a4db94011d3 17147 /*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
sahilmgandhi 18:6a4db94011d3 17148
sahilmgandhi 18:6a4db94011d3 17149
sahilmgandhi 18:6a4db94011d3 17150