MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sleep.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include "sleep_api.h"
sahilmgandhi 18:6a4db94011d3 17 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 18 #include "mbed_interface.h"
sahilmgandhi 18:6a4db94011d3 19 #include "softdevice_handler.h"
sahilmgandhi 18:6a4db94011d3 20 #include "nrf_soc.h"
sahilmgandhi 18:6a4db94011d3 21
sahilmgandhi 18:6a4db94011d3 22 // Mask of reserved bits of the register ICSR in the System Control Block peripheral
sahilmgandhi 18:6a4db94011d3 23 // In this case, bits which are equal to 0 are the bits reserved in this register
sahilmgandhi 18:6a4db94011d3 24 #define SCB_ICSR_RESERVED_BITS_MASK 0x9E43F03F
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 #define FPU_EXCEPTION_MASK 0x0000009F
sahilmgandhi 18:6a4db94011d3 27
sahilmgandhi 18:6a4db94011d3 28 void hal_sleep(void)
sahilmgandhi 18:6a4db94011d3 29 {
sahilmgandhi 18:6a4db94011d3 30 // ensure debug is disconnected if semihost is enabled....
sahilmgandhi 18:6a4db94011d3 31
sahilmgandhi 18:6a4db94011d3 32 // Trigger an event when an interrupt is pending. This allows to wake up
sahilmgandhi 18:6a4db94011d3 33 // the processor from disabled interrupts.
sahilmgandhi 18:6a4db94011d3 34 SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
sahilmgandhi 18:6a4db94011d3 35
sahilmgandhi 18:6a4db94011d3 36 #if defined(NRF52) || defined(NRF52840_XXAA)
sahilmgandhi 18:6a4db94011d3 37 /* Clear exceptions and PendingIRQ from the FPU unit */
sahilmgandhi 18:6a4db94011d3 38 __set_FPSCR(__get_FPSCR() & ~(FPU_EXCEPTION_MASK));
sahilmgandhi 18:6a4db94011d3 39 (void) __get_FPSCR();
sahilmgandhi 18:6a4db94011d3 40 NVIC_ClearPendingIRQ(FPU_IRQn);
sahilmgandhi 18:6a4db94011d3 41 #endif
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43 // If the SoftDevice is enabled, its API must be used to go to sleep.
sahilmgandhi 18:6a4db94011d3 44 if (softdevice_handler_is_enabled())
sahilmgandhi 18:6a4db94011d3 45 {
sahilmgandhi 18:6a4db94011d3 46 sd_power_mode_set(NRF_POWER_MODE_LOWPWR);
sahilmgandhi 18:6a4db94011d3 47 sd_app_evt_wait();
sahilmgandhi 18:6a4db94011d3 48 }
sahilmgandhi 18:6a4db94011d3 49 else
sahilmgandhi 18:6a4db94011d3 50 {
sahilmgandhi 18:6a4db94011d3 51 NRF_POWER->TASKS_LOWPWR = 1;
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 // Note: it is not sufficient to just use WFE here, since the internal
sahilmgandhi 18:6a4db94011d3 54 // event register may be already set from an event that occurred in the
sahilmgandhi 18:6a4db94011d3 55 // past (like an SVC call to the SoftDevice) and in such case WFE will
sahilmgandhi 18:6a4db94011d3 56 // just clear the register and continue execution.
sahilmgandhi 18:6a4db94011d3 57 // Therefore, the strategy here is to first clear the event register
sahilmgandhi 18:6a4db94011d3 58 // by using SEV/WFE pair, and then execute WFE again, unless there is
sahilmgandhi 18:6a4db94011d3 59 // a pending interrupt.
sahilmgandhi 18:6a4db94011d3 60
sahilmgandhi 18:6a4db94011d3 61 // Set an event and wake up whatsoever, this will clear the event
sahilmgandhi 18:6a4db94011d3 62 // register from all previous events set (SVC call included)
sahilmgandhi 18:6a4db94011d3 63 __SEV();
sahilmgandhi 18:6a4db94011d3 64 __WFE();
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66 // Test if there is an interrupt pending (mask reserved regions)
sahilmgandhi 18:6a4db94011d3 67 if (SCB->ICSR & (SCB_ICSR_RESERVED_BITS_MASK))
sahilmgandhi 18:6a4db94011d3 68 {
sahilmgandhi 18:6a4db94011d3 69 // Ok, there is an interrut pending, no need to go to sleep
sahilmgandhi 18:6a4db94011d3 70 return;
sahilmgandhi 18:6a4db94011d3 71 }
sahilmgandhi 18:6a4db94011d3 72 else
sahilmgandhi 18:6a4db94011d3 73 {
sahilmgandhi 18:6a4db94011d3 74 // next event will wakeup the CPU
sahilmgandhi 18:6a4db94011d3 75 // If an interrupt occured between the test of SCB->ICSR and this
sahilmgandhi 18:6a4db94011d3 76 // instruction, WFE will just not put the CPU to sleep
sahilmgandhi 18:6a4db94011d3 77 __WFE();
sahilmgandhi 18:6a4db94011d3 78 }
sahilmgandhi 18:6a4db94011d3 79 }
sahilmgandhi 18:6a4db94011d3 80 }
sahilmgandhi 18:6a4db94011d3 81
sahilmgandhi 18:6a4db94011d3 82 void hal_deepsleep(void)
sahilmgandhi 18:6a4db94011d3 83 {
sahilmgandhi 18:6a4db94011d3 84 hal_sleep();
sahilmgandhi 18:6a4db94011d3 85 }