MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/spi_slave/nrf_drv_spis.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /*
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2013 Nordic Semiconductor ASA
sahilmgandhi 18:6a4db94011d3 3 * All rights reserved.
sahilmgandhi 18:6a4db94011d3 4 *
sahilmgandhi 18:6a4db94011d3 5 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 6 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * 1. Redistributions of source code must retain the above copyright notice, this list
sahilmgandhi 18:6a4db94011d3 9 * of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
sahilmgandhi 18:6a4db94011d3 12 * integrated circuit in a product or a software update for such product, must reproduce
sahilmgandhi 18:6a4db94011d3 13 * the above copyright notice, this list of conditions and the following disclaimer in
sahilmgandhi 18:6a4db94011d3 14 * the documentation and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 15 *
sahilmgandhi 18:6a4db94011d3 16 * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
sahilmgandhi 18:6a4db94011d3 17 * used to endorse or promote products derived from this software without specific prior
sahilmgandhi 18:6a4db94011d3 18 * written permission.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * 4. This software, with or without modification, must only be used with a
sahilmgandhi 18:6a4db94011d3 21 * Nordic Semiconductor ASA integrated circuit.
sahilmgandhi 18:6a4db94011d3 22 *
sahilmgandhi 18:6a4db94011d3 23 * 5. Any software provided in binary or object form under this license must not be reverse
sahilmgandhi 18:6a4db94011d3 24 * engineered, decompiled, modified and/or disassembled.
sahilmgandhi 18:6a4db94011d3 25 *
sahilmgandhi 18:6a4db94011d3 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
sahilmgandhi 18:6a4db94011d3 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
sahilmgandhi 18:6a4db94011d3 28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 29 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
sahilmgandhi 18:6a4db94011d3 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
sahilmgandhi 18:6a4db94011d3 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
sahilmgandhi 18:6a4db94011d3 32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
sahilmgandhi 18:6a4db94011d3 33 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
sahilmgandhi 18:6a4db94011d3 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
sahilmgandhi 18:6a4db94011d3 35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 36 *
sahilmgandhi 18:6a4db94011d3 37 */
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39
sahilmgandhi 18:6a4db94011d3 40 #include "nrf_drv_spis.h"
sahilmgandhi 18:6a4db94011d3 41 #include <stdbool.h>
sahilmgandhi 18:6a4db94011d3 42 #include <stdio.h>
sahilmgandhi 18:6a4db94011d3 43 #include "nrf.h"
sahilmgandhi 18:6a4db94011d3 44 #include "nrf_gpio.h"
sahilmgandhi 18:6a4db94011d3 45 #include "app_error.h"
sahilmgandhi 18:6a4db94011d3 46 #include "app_util_platform.h"
sahilmgandhi 18:6a4db94011d3 47 #include "nrf_drv_config.h"
sahilmgandhi 18:6a4db94011d3 48 #include "nrf_drv_common.h"
sahilmgandhi 18:6a4db94011d3 49 #include "nordic_common.h"
sahilmgandhi 18:6a4db94011d3 50 #include "sdk_common.h"
sahilmgandhi 18:6a4db94011d3 51 #include "nrf_assert.h"
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 #if !SPIS_COUNT
sahilmgandhi 18:6a4db94011d3 54 #warning No SPIS instances enabled.
sahilmgandhi 18:6a4db94011d3 55 #else
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 /**@brief States of the SPI transaction state machine. */
sahilmgandhi 18:6a4db94011d3 58 typedef enum
sahilmgandhi 18:6a4db94011d3 59 {
sahilmgandhi 18:6a4db94011d3 60 SPIS_STATE_INIT, /**< Initialization state. In this state the module waits for a call to @ref spi_slave_buffers_set. */
sahilmgandhi 18:6a4db94011d3 61 SPIS_BUFFER_RESOURCE_REQUESTED, /**< State where the configuration of the memory buffers, which are to be used in SPI transaction, has started. */
sahilmgandhi 18:6a4db94011d3 62 SPIS_BUFFER_RESOURCE_CONFIGURED, /**< State where the configuration of the memory buffers, which are to be used in SPI transaction, has completed. */
sahilmgandhi 18:6a4db94011d3 63 SPIS_XFER_COMPLETED /**< State where SPI transaction has been completed. */
sahilmgandhi 18:6a4db94011d3 64 } nrf_drv_spis_state_t;
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66
sahilmgandhi 18:6a4db94011d3 67 #if PERIPHERAL_RESOURCE_SHARING_ENABLED
sahilmgandhi 18:6a4db94011d3 68 #define IRQ_HANDLER_NAME(n) irq_handler_for_instance_##n
sahilmgandhi 18:6a4db94011d3 69 #define IRQ_HANDLER(n) static void IRQ_HANDLER_NAME(n)(void)
sahilmgandhi 18:6a4db94011d3 70
sahilmgandhi 18:6a4db94011d3 71 #if SPIS0_ENABLED
sahilmgandhi 18:6a4db94011d3 72 IRQ_HANDLER(0);
sahilmgandhi 18:6a4db94011d3 73 #endif
sahilmgandhi 18:6a4db94011d3 74 #if SPIS1_ENABLED
sahilmgandhi 18:6a4db94011d3 75 IRQ_HANDLER(1);
sahilmgandhi 18:6a4db94011d3 76 #endif
sahilmgandhi 18:6a4db94011d3 77 #if SPIS2_ENABLED
sahilmgandhi 18:6a4db94011d3 78 IRQ_HANDLER(2);
sahilmgandhi 18:6a4db94011d3 79 #endif
sahilmgandhi 18:6a4db94011d3 80 static nrf_drv_irq_handler_t const m_irq_handlers[SPIS_COUNT] = {
sahilmgandhi 18:6a4db94011d3 81 #if SPIS0_ENABLED
sahilmgandhi 18:6a4db94011d3 82 IRQ_HANDLER_NAME(0),
sahilmgandhi 18:6a4db94011d3 83 #endif
sahilmgandhi 18:6a4db94011d3 84 #if SPIS1_ENABLED
sahilmgandhi 18:6a4db94011d3 85 IRQ_HANDLER_NAME(1),
sahilmgandhi 18:6a4db94011d3 86 #endif
sahilmgandhi 18:6a4db94011d3 87 #if SPIS2_ENABLED
sahilmgandhi 18:6a4db94011d3 88 IRQ_HANDLER_NAME(2),
sahilmgandhi 18:6a4db94011d3 89 #endif
sahilmgandhi 18:6a4db94011d3 90 };
sahilmgandhi 18:6a4db94011d3 91 #else
sahilmgandhi 18:6a4db94011d3 92 #define IRQ_HANDLER(n) void SPIS##n##_IRQ_HANDLER(void)
sahilmgandhi 18:6a4db94011d3 93 #endif // PERIPHERAL_RESOURCE_SHARING_ENABLED
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 #define SPIS_IRQHANDLER_TEMPLATE(NUM) \
sahilmgandhi 18:6a4db94011d3 96 IRQ_HANDLER(NUM) \
sahilmgandhi 18:6a4db94011d3 97 { \
sahilmgandhi 18:6a4db94011d3 98 spis_irq_handler(NRF_SPIS##NUM, &m_cb[SPIS##NUM##_INSTANCE_INDEX]); \
sahilmgandhi 18:6a4db94011d3 99 }
sahilmgandhi 18:6a4db94011d3 100
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102 /**@brief SPIS control block - driver instance local data. */
sahilmgandhi 18:6a4db94011d3 103 typedef struct
sahilmgandhi 18:6a4db94011d3 104 {
sahilmgandhi 18:6a4db94011d3 105 volatile uint32_t tx_buffer_size; //!< SPI slave TX buffer size in bytes.
sahilmgandhi 18:6a4db94011d3 106 volatile uint32_t rx_buffer_size; //!< SPI slave RX buffer size in bytes.
sahilmgandhi 18:6a4db94011d3 107 nrf_drv_spis_event_handler_t handler; //!< SPI event handler.
sahilmgandhi 18:6a4db94011d3 108 volatile const uint8_t * tx_buffer; //!< SPI slave TX buffer.
sahilmgandhi 18:6a4db94011d3 109 volatile uint8_t * rx_buffer; //!< SPI slave RX buffer.
sahilmgandhi 18:6a4db94011d3 110 nrf_drv_state_t state; //!< driver initialization state.
sahilmgandhi 18:6a4db94011d3 111 volatile nrf_drv_spis_state_t spi_state; //!< SPI slave state.
sahilmgandhi 18:6a4db94011d3 112 } spis_cb_t;
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 static spis_cb_t m_cb[SPIS_COUNT];
sahilmgandhi 18:6a4db94011d3 115
sahilmgandhi 18:6a4db94011d3 116 static nrf_drv_spis_config_t const m_default_config[SPIS_COUNT] = {
sahilmgandhi 18:6a4db94011d3 117 #if SPIS0_ENABLED
sahilmgandhi 18:6a4db94011d3 118 NRF_DRV_SPIS_DEFAULT_CONFIG(0),
sahilmgandhi 18:6a4db94011d3 119 #endif
sahilmgandhi 18:6a4db94011d3 120 #if SPIS1_ENABLED
sahilmgandhi 18:6a4db94011d3 121 NRF_DRV_SPIS_DEFAULT_CONFIG(1),
sahilmgandhi 18:6a4db94011d3 122 #endif
sahilmgandhi 18:6a4db94011d3 123 #if SPIS2_ENABLED
sahilmgandhi 18:6a4db94011d3 124 NRF_DRV_SPIS_DEFAULT_CONFIG(2),
sahilmgandhi 18:6a4db94011d3 125 #endif
sahilmgandhi 18:6a4db94011d3 126 };
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128
sahilmgandhi 18:6a4db94011d3 129 ret_code_t nrf_drv_spis_init(nrf_drv_spis_t const * const p_instance,
sahilmgandhi 18:6a4db94011d3 130 nrf_drv_spis_config_t const * p_config,
sahilmgandhi 18:6a4db94011d3 131 nrf_drv_spis_event_handler_t event_handler)
sahilmgandhi 18:6a4db94011d3 132 {
sahilmgandhi 18:6a4db94011d3 133 spis_cb_t * p_cb = &m_cb[p_instance->instance_id];
sahilmgandhi 18:6a4db94011d3 134
sahilmgandhi 18:6a4db94011d3 135 NRF_SPIS_Type * p_spis = p_instance->p_reg;
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137 if (p_cb->state != NRF_DRV_STATE_UNINITIALIZED)
sahilmgandhi 18:6a4db94011d3 138 {
sahilmgandhi 18:6a4db94011d3 139 return NRF_ERROR_INVALID_STATE;
sahilmgandhi 18:6a4db94011d3 140 }
sahilmgandhi 18:6a4db94011d3 141 if (p_config == NULL)
sahilmgandhi 18:6a4db94011d3 142 {
sahilmgandhi 18:6a4db94011d3 143 p_config = &m_default_config[p_instance->instance_id];
sahilmgandhi 18:6a4db94011d3 144 }
sahilmgandhi 18:6a4db94011d3 145 if ((uint32_t)p_config->mode > (uint32_t)NRF_DRV_SPIS_MODE_3)
sahilmgandhi 18:6a4db94011d3 146 {
sahilmgandhi 18:6a4db94011d3 147 return NRF_ERROR_INVALID_PARAM;
sahilmgandhi 18:6a4db94011d3 148 }
sahilmgandhi 18:6a4db94011d3 149 if (!event_handler)
sahilmgandhi 18:6a4db94011d3 150 {
sahilmgandhi 18:6a4db94011d3 151 return NRF_ERROR_NULL;
sahilmgandhi 18:6a4db94011d3 152 }
sahilmgandhi 18:6a4db94011d3 153 #if PERIPHERAL_RESOURCE_SHARING_ENABLED
sahilmgandhi 18:6a4db94011d3 154 if (nrf_drv_common_per_res_acquire(p_spis,
sahilmgandhi 18:6a4db94011d3 155 m_irq_handlers[p_instance->instance_id]) != NRF_SUCCESS)
sahilmgandhi 18:6a4db94011d3 156 {
sahilmgandhi 18:6a4db94011d3 157 return NRF_ERROR_BUSY;
sahilmgandhi 18:6a4db94011d3 158 }
sahilmgandhi 18:6a4db94011d3 159 #endif
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161 // Configure the SPI pins for input.
sahilmgandhi 18:6a4db94011d3 162 uint32_t mosi_pin;
sahilmgandhi 18:6a4db94011d3 163 uint32_t miso_pin;
sahilmgandhi 18:6a4db94011d3 164
sahilmgandhi 18:6a4db94011d3 165 if (p_config->miso_pin != NRF_DRV_SPIS_PIN_NOT_USED)
sahilmgandhi 18:6a4db94011d3 166 {
sahilmgandhi 18:6a4db94011d3 167 nrf_gpio_cfg(p_config->miso_pin,
sahilmgandhi 18:6a4db94011d3 168 NRF_GPIO_PIN_DIR_INPUT,
sahilmgandhi 18:6a4db94011d3 169 NRF_GPIO_PIN_INPUT_CONNECT,
sahilmgandhi 18:6a4db94011d3 170 NRF_GPIO_PIN_NOPULL,
sahilmgandhi 18:6a4db94011d3 171 p_config->miso_drive,
sahilmgandhi 18:6a4db94011d3 172 NRF_GPIO_PIN_NOSENSE);
sahilmgandhi 18:6a4db94011d3 173 miso_pin = p_config->miso_pin;
sahilmgandhi 18:6a4db94011d3 174 }
sahilmgandhi 18:6a4db94011d3 175 else
sahilmgandhi 18:6a4db94011d3 176 {
sahilmgandhi 18:6a4db94011d3 177 miso_pin = NRF_SPIS_PIN_NOT_CONNECTED;
sahilmgandhi 18:6a4db94011d3 178 }
sahilmgandhi 18:6a4db94011d3 179
sahilmgandhi 18:6a4db94011d3 180 if (p_config->mosi_pin != NRF_DRV_SPIS_PIN_NOT_USED)
sahilmgandhi 18:6a4db94011d3 181 {
sahilmgandhi 18:6a4db94011d3 182 nrf_gpio_cfg(p_config->mosi_pin,
sahilmgandhi 18:6a4db94011d3 183 NRF_GPIO_PIN_DIR_INPUT,
sahilmgandhi 18:6a4db94011d3 184 NRF_GPIO_PIN_INPUT_CONNECT,
sahilmgandhi 18:6a4db94011d3 185 NRF_GPIO_PIN_NOPULL,
sahilmgandhi 18:6a4db94011d3 186 NRF_GPIO_PIN_S0S1,
sahilmgandhi 18:6a4db94011d3 187 NRF_GPIO_PIN_NOSENSE);
sahilmgandhi 18:6a4db94011d3 188 mosi_pin = p_config->mosi_pin;
sahilmgandhi 18:6a4db94011d3 189 }
sahilmgandhi 18:6a4db94011d3 190 else
sahilmgandhi 18:6a4db94011d3 191 {
sahilmgandhi 18:6a4db94011d3 192 mosi_pin = NRF_SPIS_PIN_NOT_CONNECTED;
sahilmgandhi 18:6a4db94011d3 193 }
sahilmgandhi 18:6a4db94011d3 194
sahilmgandhi 18:6a4db94011d3 195 nrf_gpio_cfg(p_config->csn_pin,
sahilmgandhi 18:6a4db94011d3 196 NRF_GPIO_PIN_DIR_INPUT,
sahilmgandhi 18:6a4db94011d3 197 NRF_GPIO_PIN_INPUT_CONNECT,
sahilmgandhi 18:6a4db94011d3 198 p_config->csn_pullup,
sahilmgandhi 18:6a4db94011d3 199 NRF_GPIO_PIN_S0S1,
sahilmgandhi 18:6a4db94011d3 200 NRF_GPIO_PIN_NOSENSE);
sahilmgandhi 18:6a4db94011d3 201
sahilmgandhi 18:6a4db94011d3 202 nrf_gpio_cfg(p_config->sck_pin,
sahilmgandhi 18:6a4db94011d3 203 NRF_GPIO_PIN_DIR_INPUT,
sahilmgandhi 18:6a4db94011d3 204 NRF_GPIO_PIN_INPUT_CONNECT,
sahilmgandhi 18:6a4db94011d3 205 NRF_GPIO_PIN_NOPULL,
sahilmgandhi 18:6a4db94011d3 206 NRF_GPIO_PIN_S0S1,
sahilmgandhi 18:6a4db94011d3 207 NRF_GPIO_PIN_NOSENSE);
sahilmgandhi 18:6a4db94011d3 208
sahilmgandhi 18:6a4db94011d3 209 nrf_spis_pins_set(p_spis, p_config->sck_pin, mosi_pin, miso_pin, p_config->csn_pin);
sahilmgandhi 18:6a4db94011d3 210
sahilmgandhi 18:6a4db94011d3 211 nrf_spis_rx_buffer_set(p_spis, NULL, 0);
sahilmgandhi 18:6a4db94011d3 212 nrf_spis_tx_buffer_set(p_spis, NULL, 0);
sahilmgandhi 18:6a4db94011d3 213
sahilmgandhi 18:6a4db94011d3 214 // Configure SPI mode.
sahilmgandhi 18:6a4db94011d3 215 nrf_spis_configure(p_spis, (nrf_spis_mode_t) p_config->mode,
sahilmgandhi 18:6a4db94011d3 216 (nrf_spis_bit_order_t) p_config->bit_order);
sahilmgandhi 18:6a4db94011d3 217
sahilmgandhi 18:6a4db94011d3 218 // Configure DEF and ORC characters.
sahilmgandhi 18:6a4db94011d3 219 nrf_spis_def_set(p_spis, p_config->def);
sahilmgandhi 18:6a4db94011d3 220 nrf_spis_orc_set(p_spis, p_config->orc);
sahilmgandhi 18:6a4db94011d3 221
sahilmgandhi 18:6a4db94011d3 222 // Clear possible pending events.
sahilmgandhi 18:6a4db94011d3 223 nrf_spis_event_clear(p_spis, NRF_SPIS_EVENT_END);
sahilmgandhi 18:6a4db94011d3 224 nrf_spis_event_clear(p_spis, NRF_SPIS_EVENT_ACQUIRED);
sahilmgandhi 18:6a4db94011d3 225
sahilmgandhi 18:6a4db94011d3 226 // Enable END_ACQUIRE shortcut.
sahilmgandhi 18:6a4db94011d3 227 nrf_spis_shorts_enable(p_spis, NRF_SPIS_SHORT_END_ACQUIRE);
sahilmgandhi 18:6a4db94011d3 228
sahilmgandhi 18:6a4db94011d3 229 m_cb[p_instance->instance_id].spi_state = SPIS_STATE_INIT;
sahilmgandhi 18:6a4db94011d3 230 m_cb[p_instance->instance_id].handler = event_handler;
sahilmgandhi 18:6a4db94011d3 231
sahilmgandhi 18:6a4db94011d3 232
sahilmgandhi 18:6a4db94011d3 233 // Enable IRQ.
sahilmgandhi 18:6a4db94011d3 234 nrf_spis_int_enable(p_spis, NRF_SPIS_INT_ACQUIRED_MASK | NRF_SPIS_INT_END_MASK);
sahilmgandhi 18:6a4db94011d3 235 nrf_drv_common_irq_enable(p_instance->irq, p_config->irq_priority);
sahilmgandhi 18:6a4db94011d3 236
sahilmgandhi 18:6a4db94011d3 237 p_cb->state = NRF_DRV_STATE_INITIALIZED;
sahilmgandhi 18:6a4db94011d3 238
sahilmgandhi 18:6a4db94011d3 239 // Enable SPI slave device.
sahilmgandhi 18:6a4db94011d3 240 nrf_spis_enable(p_spis);
sahilmgandhi 18:6a4db94011d3 241
sahilmgandhi 18:6a4db94011d3 242 return NRF_SUCCESS;
sahilmgandhi 18:6a4db94011d3 243 }
sahilmgandhi 18:6a4db94011d3 244
sahilmgandhi 18:6a4db94011d3 245
sahilmgandhi 18:6a4db94011d3 246 void nrf_drv_spis_uninit(nrf_drv_spis_t const * const p_instance)
sahilmgandhi 18:6a4db94011d3 247 {
sahilmgandhi 18:6a4db94011d3 248 spis_cb_t * p_cb = &m_cb[p_instance->instance_id];
sahilmgandhi 18:6a4db94011d3 249 ASSERT(p_cb->state != NRF_DRV_STATE_UNINITIALIZED);
sahilmgandhi 18:6a4db94011d3 250
sahilmgandhi 18:6a4db94011d3 251 NRF_SPIS_Type * p_spis = p_instance->p_reg;
sahilmgandhi 18:6a4db94011d3 252
sahilmgandhi 18:6a4db94011d3 253 #define DISABLE_ALL 0xFFFFFFFF
sahilmgandhi 18:6a4db94011d3 254 nrf_spis_disable(p_spis);
sahilmgandhi 18:6a4db94011d3 255 nrf_drv_common_irq_disable(p_instance->irq);
sahilmgandhi 18:6a4db94011d3 256 nrf_spis_int_disable(p_spis, DISABLE_ALL);
sahilmgandhi 18:6a4db94011d3 257 #undef DISABLE_ALL
sahilmgandhi 18:6a4db94011d3 258
sahilmgandhi 18:6a4db94011d3 259 #if PERIPHERAL_RESOURCE_SHARING_ENABLED
sahilmgandhi 18:6a4db94011d3 260 nrf_drv_common_per_res_release(p_spis);
sahilmgandhi 18:6a4db94011d3 261 #endif
sahilmgandhi 18:6a4db94011d3 262
sahilmgandhi 18:6a4db94011d3 263 p_cb->state = NRF_DRV_STATE_UNINITIALIZED;
sahilmgandhi 18:6a4db94011d3 264 }
sahilmgandhi 18:6a4db94011d3 265
sahilmgandhi 18:6a4db94011d3 266
sahilmgandhi 18:6a4db94011d3 267 /**@brief Function for executing the state entry action. */
sahilmgandhi 18:6a4db94011d3 268 static void spis_state_entry_action_execute(NRF_SPIS_Type * p_spis,
sahilmgandhi 18:6a4db94011d3 269 spis_cb_t * p_cb)
sahilmgandhi 18:6a4db94011d3 270 {
sahilmgandhi 18:6a4db94011d3 271 nrf_drv_spis_event_t event;
sahilmgandhi 18:6a4db94011d3 272
sahilmgandhi 18:6a4db94011d3 273 switch (p_cb->spi_state)
sahilmgandhi 18:6a4db94011d3 274 {
sahilmgandhi 18:6a4db94011d3 275 case SPIS_BUFFER_RESOURCE_REQUESTED:
sahilmgandhi 18:6a4db94011d3 276 nrf_spis_task_trigger(p_spis, NRF_SPIS_TASK_ACQUIRE);
sahilmgandhi 18:6a4db94011d3 277 break;
sahilmgandhi 18:6a4db94011d3 278
sahilmgandhi 18:6a4db94011d3 279 case SPIS_BUFFER_RESOURCE_CONFIGURED:
sahilmgandhi 18:6a4db94011d3 280 event.evt_type = NRF_DRV_SPIS_BUFFERS_SET_DONE;
sahilmgandhi 18:6a4db94011d3 281 event.rx_amount = 0;
sahilmgandhi 18:6a4db94011d3 282 event.tx_amount = 0;
sahilmgandhi 18:6a4db94011d3 283
sahilmgandhi 18:6a4db94011d3 284 APP_ERROR_CHECK_BOOL(p_cb->handler != NULL);
sahilmgandhi 18:6a4db94011d3 285 p_cb->handler(event);
sahilmgandhi 18:6a4db94011d3 286 break;
sahilmgandhi 18:6a4db94011d3 287
sahilmgandhi 18:6a4db94011d3 288 case SPIS_XFER_COMPLETED:
sahilmgandhi 18:6a4db94011d3 289 event.evt_type = NRF_DRV_SPIS_XFER_DONE;
sahilmgandhi 18:6a4db94011d3 290 event.rx_amount = nrf_spis_rx_amount_get(p_spis);
sahilmgandhi 18:6a4db94011d3 291 event.tx_amount = nrf_spis_tx_amount_get(p_spis);
sahilmgandhi 18:6a4db94011d3 292 APP_ERROR_CHECK_BOOL(p_cb->handler != NULL);
sahilmgandhi 18:6a4db94011d3 293 p_cb->handler(event);
sahilmgandhi 18:6a4db94011d3 294 break;
sahilmgandhi 18:6a4db94011d3 295
sahilmgandhi 18:6a4db94011d3 296 default:
sahilmgandhi 18:6a4db94011d3 297 // No implementation required.
sahilmgandhi 18:6a4db94011d3 298 break;
sahilmgandhi 18:6a4db94011d3 299 }
sahilmgandhi 18:6a4db94011d3 300 }
sahilmgandhi 18:6a4db94011d3 301
sahilmgandhi 18:6a4db94011d3 302 /**@brief Function for changing the state of the SPI state machine.
sahilmgandhi 18:6a4db94011d3 303 *
sahilmgandhi 18:6a4db94011d3 304 * @param[in] p_spis SPIS instance register.
sahilmgandhi 18:6a4db94011d3 305 * @param[in] p_cb SPIS instance control block.
sahilmgandhi 18:6a4db94011d3 306 * @param[in] new_state State where the state machine transits to.
sahilmgandhi 18:6a4db94011d3 307 */
sahilmgandhi 18:6a4db94011d3 308 static void spis_state_change(NRF_SPIS_Type * p_spis,
sahilmgandhi 18:6a4db94011d3 309 spis_cb_t * p_cb,
sahilmgandhi 18:6a4db94011d3 310 nrf_drv_spis_state_t new_state)
sahilmgandhi 18:6a4db94011d3 311 {
sahilmgandhi 18:6a4db94011d3 312 p_cb->spi_state = new_state;
sahilmgandhi 18:6a4db94011d3 313 spis_state_entry_action_execute(p_spis, p_cb);
sahilmgandhi 18:6a4db94011d3 314 }
sahilmgandhi 18:6a4db94011d3 315
sahilmgandhi 18:6a4db94011d3 316
sahilmgandhi 18:6a4db94011d3 317 ret_code_t nrf_drv_spis_buffers_set(nrf_drv_spis_t const * const p_instance,
sahilmgandhi 18:6a4db94011d3 318 const uint8_t * p_tx_buffer,
sahilmgandhi 18:6a4db94011d3 319 uint8_t tx_buffer_length,
sahilmgandhi 18:6a4db94011d3 320 uint8_t * p_rx_buffer,
sahilmgandhi 18:6a4db94011d3 321 uint8_t rx_buffer_length)
sahilmgandhi 18:6a4db94011d3 322 {
sahilmgandhi 18:6a4db94011d3 323 spis_cb_t * p_cb = &m_cb[p_instance->instance_id];
sahilmgandhi 18:6a4db94011d3 324 uint32_t err_code;
sahilmgandhi 18:6a4db94011d3 325
sahilmgandhi 18:6a4db94011d3 326 VERIFY_PARAM_NOT_NULL(p_rx_buffer);
sahilmgandhi 18:6a4db94011d3 327 VERIFY_PARAM_NOT_NULL(p_tx_buffer);
sahilmgandhi 18:6a4db94011d3 328
sahilmgandhi 18:6a4db94011d3 329 // EasyDMA requires that transfer buffers are placed in Data RAM region;
sahilmgandhi 18:6a4db94011d3 330 // signal error if they are not.
sahilmgandhi 18:6a4db94011d3 331 if ((p_tx_buffer != NULL && !nrf_drv_is_in_RAM(p_tx_buffer)) ||
sahilmgandhi 18:6a4db94011d3 332 (p_rx_buffer != NULL && !nrf_drv_is_in_RAM(p_rx_buffer)))
sahilmgandhi 18:6a4db94011d3 333 {
sahilmgandhi 18:6a4db94011d3 334 return NRF_ERROR_INVALID_ADDR;
sahilmgandhi 18:6a4db94011d3 335 }
sahilmgandhi 18:6a4db94011d3 336
sahilmgandhi 18:6a4db94011d3 337 switch (p_cb->spi_state)
sahilmgandhi 18:6a4db94011d3 338 {
sahilmgandhi 18:6a4db94011d3 339 case SPIS_STATE_INIT:
sahilmgandhi 18:6a4db94011d3 340 case SPIS_XFER_COMPLETED:
sahilmgandhi 18:6a4db94011d3 341 case SPIS_BUFFER_RESOURCE_CONFIGURED:
sahilmgandhi 18:6a4db94011d3 342 p_cb->tx_buffer = p_tx_buffer;
sahilmgandhi 18:6a4db94011d3 343 p_cb->rx_buffer = p_rx_buffer;
sahilmgandhi 18:6a4db94011d3 344 p_cb->tx_buffer_size = tx_buffer_length;
sahilmgandhi 18:6a4db94011d3 345 p_cb->rx_buffer_size = rx_buffer_length;
sahilmgandhi 18:6a4db94011d3 346 err_code = NRF_SUCCESS;
sahilmgandhi 18:6a4db94011d3 347
sahilmgandhi 18:6a4db94011d3 348 spis_state_change(p_instance->p_reg, p_cb, SPIS_BUFFER_RESOURCE_REQUESTED);
sahilmgandhi 18:6a4db94011d3 349 break;
sahilmgandhi 18:6a4db94011d3 350
sahilmgandhi 18:6a4db94011d3 351 case SPIS_BUFFER_RESOURCE_REQUESTED:
sahilmgandhi 18:6a4db94011d3 352 err_code = NRF_ERROR_INVALID_STATE;
sahilmgandhi 18:6a4db94011d3 353 break;
sahilmgandhi 18:6a4db94011d3 354
sahilmgandhi 18:6a4db94011d3 355 default:
sahilmgandhi 18:6a4db94011d3 356 // @note: execution of this code path would imply internal error in the design.
sahilmgandhi 18:6a4db94011d3 357 err_code = NRF_ERROR_INTERNAL;
sahilmgandhi 18:6a4db94011d3 358 break;
sahilmgandhi 18:6a4db94011d3 359 }
sahilmgandhi 18:6a4db94011d3 360
sahilmgandhi 18:6a4db94011d3 361 return err_code;
sahilmgandhi 18:6a4db94011d3 362 }
sahilmgandhi 18:6a4db94011d3 363
sahilmgandhi 18:6a4db94011d3 364 static void spis_irq_handler(NRF_SPIS_Type * p_spis, spis_cb_t * p_cb)
sahilmgandhi 18:6a4db94011d3 365 {
sahilmgandhi 18:6a4db94011d3 366 // @note: as multiple events can be pending for processing, the correct event processing order
sahilmgandhi 18:6a4db94011d3 367 // is as follows:
sahilmgandhi 18:6a4db94011d3 368 // - SPI semaphore acquired event.
sahilmgandhi 18:6a4db94011d3 369 // - SPI transaction complete event.
sahilmgandhi 18:6a4db94011d3 370
sahilmgandhi 18:6a4db94011d3 371 // Check for SPI semaphore acquired event.
sahilmgandhi 18:6a4db94011d3 372 if (nrf_spis_event_check(p_spis, NRF_SPIS_EVENT_ACQUIRED))
sahilmgandhi 18:6a4db94011d3 373 {
sahilmgandhi 18:6a4db94011d3 374 nrf_spis_event_clear(p_spis, NRF_SPIS_EVENT_ACQUIRED);
sahilmgandhi 18:6a4db94011d3 375
sahilmgandhi 18:6a4db94011d3 376 switch (p_cb->spi_state)
sahilmgandhi 18:6a4db94011d3 377 {
sahilmgandhi 18:6a4db94011d3 378 case SPIS_BUFFER_RESOURCE_REQUESTED:
sahilmgandhi 18:6a4db94011d3 379 nrf_spis_tx_buffer_set(p_spis, (uint8_t *)p_cb->tx_buffer, p_cb->tx_buffer_size);
sahilmgandhi 18:6a4db94011d3 380 nrf_spis_rx_buffer_set(p_spis, (uint8_t *)p_cb->rx_buffer, p_cb->rx_buffer_size);
sahilmgandhi 18:6a4db94011d3 381
sahilmgandhi 18:6a4db94011d3 382 nrf_spis_task_trigger(p_spis, NRF_SPIS_TASK_RELEASE);
sahilmgandhi 18:6a4db94011d3 383
sahilmgandhi 18:6a4db94011d3 384 spis_state_change(p_spis, p_cb, SPIS_BUFFER_RESOURCE_CONFIGURED);
sahilmgandhi 18:6a4db94011d3 385 break;
sahilmgandhi 18:6a4db94011d3 386
sahilmgandhi 18:6a4db94011d3 387 default:
sahilmgandhi 18:6a4db94011d3 388 // No implementation required.
sahilmgandhi 18:6a4db94011d3 389 break;
sahilmgandhi 18:6a4db94011d3 390 }
sahilmgandhi 18:6a4db94011d3 391 }
sahilmgandhi 18:6a4db94011d3 392
sahilmgandhi 18:6a4db94011d3 393 // Check for SPI transaction complete event.
sahilmgandhi 18:6a4db94011d3 394 if (nrf_spis_event_check(p_spis, NRF_SPIS_EVENT_END))
sahilmgandhi 18:6a4db94011d3 395 {
sahilmgandhi 18:6a4db94011d3 396 nrf_spis_event_clear(p_spis, NRF_SPIS_EVENT_END);
sahilmgandhi 18:6a4db94011d3 397
sahilmgandhi 18:6a4db94011d3 398 switch (p_cb->spi_state)
sahilmgandhi 18:6a4db94011d3 399 {
sahilmgandhi 18:6a4db94011d3 400 case SPIS_BUFFER_RESOURCE_CONFIGURED:
sahilmgandhi 18:6a4db94011d3 401 spis_state_change(p_spis, p_cb, SPIS_XFER_COMPLETED);
sahilmgandhi 18:6a4db94011d3 402 break;
sahilmgandhi 18:6a4db94011d3 403
sahilmgandhi 18:6a4db94011d3 404 default:
sahilmgandhi 18:6a4db94011d3 405 // No implementation required.
sahilmgandhi 18:6a4db94011d3 406 break;
sahilmgandhi 18:6a4db94011d3 407 }
sahilmgandhi 18:6a4db94011d3 408 }
sahilmgandhi 18:6a4db94011d3 409 }
sahilmgandhi 18:6a4db94011d3 410
sahilmgandhi 18:6a4db94011d3 411 #if SPIS0_ENABLED
sahilmgandhi 18:6a4db94011d3 412 SPIS_IRQHANDLER_TEMPLATE(0)
sahilmgandhi 18:6a4db94011d3 413 #endif
sahilmgandhi 18:6a4db94011d3 414
sahilmgandhi 18:6a4db94011d3 415 #if SPIS1_ENABLED
sahilmgandhi 18:6a4db94011d3 416 SPIS_IRQHANDLER_TEMPLATE(1)
sahilmgandhi 18:6a4db94011d3 417 #endif
sahilmgandhi 18:6a4db94011d3 418
sahilmgandhi 18:6a4db94011d3 419 #if SPIS2_ENABLED
sahilmgandhi 18:6a4db94011d3 420 SPIS_IRQHANDLER_TEMPLATE(2)
sahilmgandhi 18:6a4db94011d3 421 #endif
sahilmgandhi 18:6a4db94011d3 422
sahilmgandhi 18:6a4db94011d3 423 #endif // SPI_COUNT > 0