MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf52.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1
sahilmgandhi 18:6a4db94011d3 2 /****************************************************************************************************//**
sahilmgandhi 18:6a4db94011d3 3 * @file nrf52.h
sahilmgandhi 18:6a4db94011d3 4 *
sahilmgandhi 18:6a4db94011d3 5 * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for
sahilmgandhi 18:6a4db94011d3 6 * nrf52 from Nordic Semiconductor.
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * @version V1
sahilmgandhi 18:6a4db94011d3 9 * @date 23. February 2016
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * @note Generated with SVDConv V2.81d
sahilmgandhi 18:6a4db94011d3 12 * from CMSIS SVD File 'nrf52.svd' Version 1,
sahilmgandhi 18:6a4db94011d3 13 *
sahilmgandhi 18:6a4db94011d3 14 * @par Copyright (c) 2015, Nordic Semiconductor ASA
sahilmgandhi 18:6a4db94011d3 15 * All rights reserved.
sahilmgandhi 18:6a4db94011d3 16 *
sahilmgandhi 18:6a4db94011d3 17 * Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 18 * modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * * Redistributions of source code must retain the above copyright notice, this
sahilmgandhi 18:6a4db94011d3 21 * list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 22 *
sahilmgandhi 18:6a4db94011d3 23 * * Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 24 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 25 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * * Neither the name of Nordic Semiconductor ASA nor the names of its
sahilmgandhi 18:6a4db94011d3 28 * contributors may be used to endorse or promote products derived from
sahilmgandhi 18:6a4db94011d3 29 * this software without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 30 *
sahilmgandhi 18:6a4db94011d3 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 32 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 34 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 37 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 38 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 39 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 41 *
sahilmgandhi 18:6a4db94011d3 42 *
sahilmgandhi 18:6a4db94011d3 43 *******************************************************************************************************/
sahilmgandhi 18:6a4db94011d3 44
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46
sahilmgandhi 18:6a4db94011d3 47 /** @addtogroup Nordic Semiconductor
sahilmgandhi 18:6a4db94011d3 48 * @{
sahilmgandhi 18:6a4db94011d3 49 */
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 /** @addtogroup nrf52
sahilmgandhi 18:6a4db94011d3 52 * @{
sahilmgandhi 18:6a4db94011d3 53 */
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 #ifndef NRF52_H
sahilmgandhi 18:6a4db94011d3 56 #define NRF52_H
sahilmgandhi 18:6a4db94011d3 57
sahilmgandhi 18:6a4db94011d3 58 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 59 extern "C" {
sahilmgandhi 18:6a4db94011d3 60 #endif
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 /* ------------------------- Interrupt Number Definition ------------------------ */
sahilmgandhi 18:6a4db94011d3 64
sahilmgandhi 18:6a4db94011d3 65 typedef enum {
sahilmgandhi 18:6a4db94011d3 66 /* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
sahilmgandhi 18:6a4db94011d3 67 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
sahilmgandhi 18:6a4db94011d3 68 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
sahilmgandhi 18:6a4db94011d3 69 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
sahilmgandhi 18:6a4db94011d3 70 MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
sahilmgandhi 18:6a4db94011d3 71 and No Match */
sahilmgandhi 18:6a4db94011d3 72 BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
sahilmgandhi 18:6a4db94011d3 73 related Fault */
sahilmgandhi 18:6a4db94011d3 74 UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
sahilmgandhi 18:6a4db94011d3 75 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
sahilmgandhi 18:6a4db94011d3 76 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
sahilmgandhi 18:6a4db94011d3 77 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
sahilmgandhi 18:6a4db94011d3 78 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
sahilmgandhi 18:6a4db94011d3 79 /* ---------------------- nrf52 Specific Interrupt Numbers ---------------------- */
sahilmgandhi 18:6a4db94011d3 80 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
sahilmgandhi 18:6a4db94011d3 81 RADIO_IRQn = 1, /*!< 1 RADIO */
sahilmgandhi 18:6a4db94011d3 82 UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */
sahilmgandhi 18:6a4db94011d3 83 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */
sahilmgandhi 18:6a4db94011d3 84 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */
sahilmgandhi 18:6a4db94011d3 85 NFCT_IRQn = 5, /*!< 5 NFCT */
sahilmgandhi 18:6a4db94011d3 86 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
sahilmgandhi 18:6a4db94011d3 87 SAADC_IRQn = 7, /*!< 7 SAADC */
sahilmgandhi 18:6a4db94011d3 88 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
sahilmgandhi 18:6a4db94011d3 89 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
sahilmgandhi 18:6a4db94011d3 90 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
sahilmgandhi 18:6a4db94011d3 91 RTC0_IRQn = 11, /*!< 11 RTC0 */
sahilmgandhi 18:6a4db94011d3 92 TEMP_IRQn = 12, /*!< 12 TEMP */
sahilmgandhi 18:6a4db94011d3 93 RNG_IRQn = 13, /*!< 13 RNG */
sahilmgandhi 18:6a4db94011d3 94 ECB_IRQn = 14, /*!< 14 ECB */
sahilmgandhi 18:6a4db94011d3 95 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
sahilmgandhi 18:6a4db94011d3 96 WDT_IRQn = 16, /*!< 16 WDT */
sahilmgandhi 18:6a4db94011d3 97 RTC1_IRQn = 17, /*!< 17 RTC1 */
sahilmgandhi 18:6a4db94011d3 98 QDEC_IRQn = 18, /*!< 18 QDEC */
sahilmgandhi 18:6a4db94011d3 99 COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */
sahilmgandhi 18:6a4db94011d3 100 SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */
sahilmgandhi 18:6a4db94011d3 101 SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */
sahilmgandhi 18:6a4db94011d3 102 SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */
sahilmgandhi 18:6a4db94011d3 103 SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */
sahilmgandhi 18:6a4db94011d3 104 SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */
sahilmgandhi 18:6a4db94011d3 105 SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */
sahilmgandhi 18:6a4db94011d3 106 TIMER3_IRQn = 26, /*!< 26 TIMER3 */
sahilmgandhi 18:6a4db94011d3 107 TIMER4_IRQn = 27, /*!< 27 TIMER4 */
sahilmgandhi 18:6a4db94011d3 108 PWM0_IRQn = 28, /*!< 28 PWM0 */
sahilmgandhi 18:6a4db94011d3 109 PDM_IRQn = 29, /*!< 29 PDM */
sahilmgandhi 18:6a4db94011d3 110 MWU_IRQn = 32, /*!< 32 MWU */
sahilmgandhi 18:6a4db94011d3 111 PWM1_IRQn = 33, /*!< 33 PWM1 */
sahilmgandhi 18:6a4db94011d3 112 PWM2_IRQn = 34, /*!< 34 PWM2 */
sahilmgandhi 18:6a4db94011d3 113 SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */
sahilmgandhi 18:6a4db94011d3 114 RTC2_IRQn = 36, /*!< 36 RTC2 */
sahilmgandhi 18:6a4db94011d3 115 I2S_IRQn = 37, /*!< 37 I2S */
sahilmgandhi 18:6a4db94011d3 116 FPU_IRQn = 38 /*!< 38 FPU */
sahilmgandhi 18:6a4db94011d3 117 } IRQn_Type;
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119
sahilmgandhi 18:6a4db94011d3 120 /** @addtogroup Configuration_of_CMSIS
sahilmgandhi 18:6a4db94011d3 121 * @{
sahilmgandhi 18:6a4db94011d3 122 */
sahilmgandhi 18:6a4db94011d3 123
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 126 /* ================ Processor and Core Peripheral Section ================ */
sahilmgandhi 18:6a4db94011d3 127 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 128
sahilmgandhi 18:6a4db94011d3 129 /* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */
sahilmgandhi 18:6a4db94011d3 130 #define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */
sahilmgandhi 18:6a4db94011d3 131 #define __MPU_PRESENT 1 /*!< MPU present or not */
sahilmgandhi 18:6a4db94011d3 132 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
sahilmgandhi 18:6a4db94011d3 133 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
sahilmgandhi 18:6a4db94011d3 134 #define __FPU_PRESENT 1 /*!< FPU present or not */
sahilmgandhi 18:6a4db94011d3 135 /** @} */ /* End of group Configuration_of_CMSIS */
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137 #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
sahilmgandhi 18:6a4db94011d3 138 #include "system_nrf52.h" /*!< nrf52 System */
sahilmgandhi 18:6a4db94011d3 139
sahilmgandhi 18:6a4db94011d3 140
sahilmgandhi 18:6a4db94011d3 141 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 142 /* ================ Device Specific Peripheral Section ================ */
sahilmgandhi 18:6a4db94011d3 143 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 144
sahilmgandhi 18:6a4db94011d3 145
sahilmgandhi 18:6a4db94011d3 146 /** @addtogroup Device_Peripheral_Registers
sahilmgandhi 18:6a4db94011d3 147 * @{
sahilmgandhi 18:6a4db94011d3 148 */
sahilmgandhi 18:6a4db94011d3 149
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151 /* ------------------- Start of section using anonymous unions ------------------ */
sahilmgandhi 18:6a4db94011d3 152 #if defined(__CC_ARM)
sahilmgandhi 18:6a4db94011d3 153 #pragma push
sahilmgandhi 18:6a4db94011d3 154 #pragma anon_unions
sahilmgandhi 18:6a4db94011d3 155 #elif defined(__ICCARM__)
sahilmgandhi 18:6a4db94011d3 156 #pragma language=extended
sahilmgandhi 18:6a4db94011d3 157 #elif defined(__GNUC__)
sahilmgandhi 18:6a4db94011d3 158 /* anonymous unions are enabled by default */
sahilmgandhi 18:6a4db94011d3 159 #elif defined(__TMS470__)
sahilmgandhi 18:6a4db94011d3 160 /* anonymous unions are enabled by default */
sahilmgandhi 18:6a4db94011d3 161 #elif defined(__TASKING__)
sahilmgandhi 18:6a4db94011d3 162 #pragma warning 586
sahilmgandhi 18:6a4db94011d3 163 #else
sahilmgandhi 18:6a4db94011d3 164 #warning Not supported compiler type
sahilmgandhi 18:6a4db94011d3 165 #endif
sahilmgandhi 18:6a4db94011d3 166
sahilmgandhi 18:6a4db94011d3 167
sahilmgandhi 18:6a4db94011d3 168 typedef struct {
sahilmgandhi 18:6a4db94011d3 169 __I uint32_t PART; /*!< Part code */
sahilmgandhi 18:6a4db94011d3 170 __I uint32_t VARIANT; /*!< Part Variant, Hardware version and Production configuration */
sahilmgandhi 18:6a4db94011d3 171 __I uint32_t PACKAGE; /*!< Package option */
sahilmgandhi 18:6a4db94011d3 172 __I uint32_t RAM; /*!< RAM variant */
sahilmgandhi 18:6a4db94011d3 173 __I uint32_t FLASH; /*!< Flash variant */
sahilmgandhi 18:6a4db94011d3 174 __IO uint32_t UNUSED0[3]; /*!< Description collection[0]: Unspecified */
sahilmgandhi 18:6a4db94011d3 175 } FICR_INFO_Type;
sahilmgandhi 18:6a4db94011d3 176
sahilmgandhi 18:6a4db94011d3 177 typedef struct {
sahilmgandhi 18:6a4db94011d3 178 __I uint32_t A0; /*!< Slope definition A0. */
sahilmgandhi 18:6a4db94011d3 179 __I uint32_t A1; /*!< Slope definition A1. */
sahilmgandhi 18:6a4db94011d3 180 __I uint32_t A2; /*!< Slope definition A2. */
sahilmgandhi 18:6a4db94011d3 181 __I uint32_t A3; /*!< Slope definition A3. */
sahilmgandhi 18:6a4db94011d3 182 __I uint32_t A4; /*!< Slope definition A4. */
sahilmgandhi 18:6a4db94011d3 183 __I uint32_t A5; /*!< Slope definition A5. */
sahilmgandhi 18:6a4db94011d3 184 __I uint32_t B0; /*!< y-intercept B0. */
sahilmgandhi 18:6a4db94011d3 185 __I uint32_t B1; /*!< y-intercept B1. */
sahilmgandhi 18:6a4db94011d3 186 __I uint32_t B2; /*!< y-intercept B2. */
sahilmgandhi 18:6a4db94011d3 187 __I uint32_t B3; /*!< y-intercept B3. */
sahilmgandhi 18:6a4db94011d3 188 __I uint32_t B4; /*!< y-intercept B4. */
sahilmgandhi 18:6a4db94011d3 189 __I uint32_t B5; /*!< y-intercept B5. */
sahilmgandhi 18:6a4db94011d3 190 __I uint32_t T0; /*!< Segment end T0. */
sahilmgandhi 18:6a4db94011d3 191 __I uint32_t T1; /*!< Segment end T1. */
sahilmgandhi 18:6a4db94011d3 192 __I uint32_t T2; /*!< Segment end T2. */
sahilmgandhi 18:6a4db94011d3 193 __I uint32_t T3; /*!< Segment end T3. */
sahilmgandhi 18:6a4db94011d3 194 __I uint32_t T4; /*!< Segment end T4. */
sahilmgandhi 18:6a4db94011d3 195 } FICR_TEMP_Type;
sahilmgandhi 18:6a4db94011d3 196
sahilmgandhi 18:6a4db94011d3 197 typedef struct {
sahilmgandhi 18:6a4db94011d3 198 __I uint32_t TAGHEADER0; /*!< Default header for NFC Tag. Software can read these values to
sahilmgandhi 18:6a4db94011d3 199 populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
sahilmgandhi 18:6a4db94011d3 200 __I uint32_t TAGHEADER1; /*!< Default header for NFC Tag. Software can read these values to
sahilmgandhi 18:6a4db94011d3 201 populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
sahilmgandhi 18:6a4db94011d3 202 __I uint32_t TAGHEADER2; /*!< Default header for NFC Tag. Software can read these values to
sahilmgandhi 18:6a4db94011d3 203 populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
sahilmgandhi 18:6a4db94011d3 204 __I uint32_t TAGHEADER3; /*!< Default header for NFC Tag. Software can read these values to
sahilmgandhi 18:6a4db94011d3 205 populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
sahilmgandhi 18:6a4db94011d3 206 } FICR_NFC_Type;
sahilmgandhi 18:6a4db94011d3 207
sahilmgandhi 18:6a4db94011d3 208 typedef struct {
sahilmgandhi 18:6a4db94011d3 209 __IO uint32_t POWER; /*!< Description cluster[0]: RAM0 power control register */
sahilmgandhi 18:6a4db94011d3 210 __O uint32_t POWERSET; /*!< Description cluster[0]: RAM0 power control set register */
sahilmgandhi 18:6a4db94011d3 211 __O uint32_t POWERCLR; /*!< Description cluster[0]: RAM0 power control clear register */
sahilmgandhi 18:6a4db94011d3 212 __I uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 213 } POWER_RAM_Type;
sahilmgandhi 18:6a4db94011d3 214
sahilmgandhi 18:6a4db94011d3 215 typedef struct {
sahilmgandhi 18:6a4db94011d3 216 __IO uint32_t CPU0; /*!< AHB bus master priority register for CPU0 */
sahilmgandhi 18:6a4db94011d3 217 __IO uint32_t SPIS1; /*!< AHB bus master priority register for SPIM1, SPIS1, TWIM1 and
sahilmgandhi 18:6a4db94011d3 218 TWIS1 */
sahilmgandhi 18:6a4db94011d3 219 __IO uint32_t RADIO; /*!< AHB bus master priority register for RADIO */
sahilmgandhi 18:6a4db94011d3 220 __IO uint32_t ECB; /*!< AHB bus master priority register for ECB */
sahilmgandhi 18:6a4db94011d3 221 __IO uint32_t CCM; /*!< AHB bus master priority register for CCM */
sahilmgandhi 18:6a4db94011d3 222 __IO uint32_t AAR; /*!< AHB bus master priority register for AAR */
sahilmgandhi 18:6a4db94011d3 223 __IO uint32_t SAADC; /*!< AHB bus master priority register for SAADC */
sahilmgandhi 18:6a4db94011d3 224 __IO uint32_t UARTE; /*!< AHB bus master priority register for UARTE */
sahilmgandhi 18:6a4db94011d3 225 __IO uint32_t SERIAL0; /*!< AHB bus master priority register for SPIM0, SPIS0, TWIM0 and
sahilmgandhi 18:6a4db94011d3 226 TWIS0 */
sahilmgandhi 18:6a4db94011d3 227 __IO uint32_t SERIAL2; /*!< AHB bus master priority register for SPIM2 and SPIS2 */
sahilmgandhi 18:6a4db94011d3 228 __IO uint32_t NFCT; /*!< AHB bus master priority register for NFCT */
sahilmgandhi 18:6a4db94011d3 229 __IO uint32_t I2S; /*!< AHB bus master priority register for I2S */
sahilmgandhi 18:6a4db94011d3 230 __IO uint32_t PDM; /*!< AHB bus master priority register for PDM */
sahilmgandhi 18:6a4db94011d3 231 __IO uint32_t PWM; /*!< AHB bus master priority register for PWM0, PWM1 and PWM2 */
sahilmgandhi 18:6a4db94011d3 232 } AMLI_RAMPRI_Type;
sahilmgandhi 18:6a4db94011d3 233
sahilmgandhi 18:6a4db94011d3 234 typedef struct {
sahilmgandhi 18:6a4db94011d3 235 __IO uint32_t RTS; /*!< Pin select for RTS signal */
sahilmgandhi 18:6a4db94011d3 236 __IO uint32_t TXD; /*!< Pin select for TXD signal */
sahilmgandhi 18:6a4db94011d3 237 __IO uint32_t CTS; /*!< Pin select for CTS signal */
sahilmgandhi 18:6a4db94011d3 238 __IO uint32_t RXD; /*!< Pin select for RXD signal */
sahilmgandhi 18:6a4db94011d3 239 } UARTE_PSEL_Type;
sahilmgandhi 18:6a4db94011d3 240
sahilmgandhi 18:6a4db94011d3 241 typedef struct {
sahilmgandhi 18:6a4db94011d3 242 __IO uint32_t PTR; /*!< Data pointer */
sahilmgandhi 18:6a4db94011d3 243 __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */
sahilmgandhi 18:6a4db94011d3 244 __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
sahilmgandhi 18:6a4db94011d3 245 } UARTE_RXD_Type;
sahilmgandhi 18:6a4db94011d3 246
sahilmgandhi 18:6a4db94011d3 247 typedef struct {
sahilmgandhi 18:6a4db94011d3 248 __IO uint32_t PTR; /*!< Data pointer */
sahilmgandhi 18:6a4db94011d3 249 __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */
sahilmgandhi 18:6a4db94011d3 250 __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
sahilmgandhi 18:6a4db94011d3 251 } UARTE_TXD_Type;
sahilmgandhi 18:6a4db94011d3 252
sahilmgandhi 18:6a4db94011d3 253 typedef struct {
sahilmgandhi 18:6a4db94011d3 254 __IO uint32_t SCK; /*!< Pin select for SCK */
sahilmgandhi 18:6a4db94011d3 255 __IO uint32_t MOSI; /*!< Pin select for MOSI signal */
sahilmgandhi 18:6a4db94011d3 256 __IO uint32_t MISO; /*!< Pin select for MISO signal */
sahilmgandhi 18:6a4db94011d3 257 } SPIM_PSEL_Type;
sahilmgandhi 18:6a4db94011d3 258
sahilmgandhi 18:6a4db94011d3 259 typedef struct {
sahilmgandhi 18:6a4db94011d3 260 __IO uint32_t PTR; /*!< Data pointer */
sahilmgandhi 18:6a4db94011d3 261 __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */
sahilmgandhi 18:6a4db94011d3 262 __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
sahilmgandhi 18:6a4db94011d3 263 __IO uint32_t LIST; /*!< EasyDMA list type */
sahilmgandhi 18:6a4db94011d3 264 } SPIM_RXD_Type;
sahilmgandhi 18:6a4db94011d3 265
sahilmgandhi 18:6a4db94011d3 266 typedef struct {
sahilmgandhi 18:6a4db94011d3 267 __IO uint32_t PTR; /*!< Data pointer */
sahilmgandhi 18:6a4db94011d3 268 __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */
sahilmgandhi 18:6a4db94011d3 269 __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
sahilmgandhi 18:6a4db94011d3 270 __IO uint32_t LIST; /*!< EasyDMA list type */
sahilmgandhi 18:6a4db94011d3 271 } SPIM_TXD_Type;
sahilmgandhi 18:6a4db94011d3 272
sahilmgandhi 18:6a4db94011d3 273 typedef struct {
sahilmgandhi 18:6a4db94011d3 274 __IO uint32_t SCK; /*!< Pin select for SCK */
sahilmgandhi 18:6a4db94011d3 275 __IO uint32_t MISO; /*!< Pin select for MISO signal */
sahilmgandhi 18:6a4db94011d3 276 __IO uint32_t MOSI; /*!< Pin select for MOSI signal */
sahilmgandhi 18:6a4db94011d3 277 __IO uint32_t CSN; /*!< Pin select for CSN signal */
sahilmgandhi 18:6a4db94011d3 278 } SPIS_PSEL_Type;
sahilmgandhi 18:6a4db94011d3 279
sahilmgandhi 18:6a4db94011d3 280 typedef struct {
sahilmgandhi 18:6a4db94011d3 281 __IO uint32_t PTR; /*!< RXD data pointer */
sahilmgandhi 18:6a4db94011d3 282 __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */
sahilmgandhi 18:6a4db94011d3 283 __I uint32_t AMOUNT; /*!< Number of bytes received in last granted transaction */
sahilmgandhi 18:6a4db94011d3 284 } SPIS_RXD_Type;
sahilmgandhi 18:6a4db94011d3 285
sahilmgandhi 18:6a4db94011d3 286 typedef struct {
sahilmgandhi 18:6a4db94011d3 287 __IO uint32_t PTR; /*!< TXD data pointer */
sahilmgandhi 18:6a4db94011d3 288 __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */
sahilmgandhi 18:6a4db94011d3 289 __I uint32_t AMOUNT; /*!< Number of bytes transmitted in last granted transaction */
sahilmgandhi 18:6a4db94011d3 290 } SPIS_TXD_Type;
sahilmgandhi 18:6a4db94011d3 291
sahilmgandhi 18:6a4db94011d3 292 typedef struct {
sahilmgandhi 18:6a4db94011d3 293 __IO uint32_t SCL; /*!< Pin select for SCL signal */
sahilmgandhi 18:6a4db94011d3 294 __IO uint32_t SDA; /*!< Pin select for SDA signal */
sahilmgandhi 18:6a4db94011d3 295 } TWIM_PSEL_Type;
sahilmgandhi 18:6a4db94011d3 296
sahilmgandhi 18:6a4db94011d3 297 typedef struct {
sahilmgandhi 18:6a4db94011d3 298 __IO uint32_t PTR; /*!< Data pointer */
sahilmgandhi 18:6a4db94011d3 299 __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */
sahilmgandhi 18:6a4db94011d3 300 __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
sahilmgandhi 18:6a4db94011d3 301 __IO uint32_t LIST; /*!< EasyDMA list type */
sahilmgandhi 18:6a4db94011d3 302 } TWIM_RXD_Type;
sahilmgandhi 18:6a4db94011d3 303
sahilmgandhi 18:6a4db94011d3 304 typedef struct {
sahilmgandhi 18:6a4db94011d3 305 __IO uint32_t PTR; /*!< Data pointer */
sahilmgandhi 18:6a4db94011d3 306 __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */
sahilmgandhi 18:6a4db94011d3 307 __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
sahilmgandhi 18:6a4db94011d3 308 __IO uint32_t LIST; /*!< EasyDMA list type */
sahilmgandhi 18:6a4db94011d3 309 } TWIM_TXD_Type;
sahilmgandhi 18:6a4db94011d3 310
sahilmgandhi 18:6a4db94011d3 311 typedef struct {
sahilmgandhi 18:6a4db94011d3 312 __IO uint32_t SCL; /*!< Pin select for SCL signal */
sahilmgandhi 18:6a4db94011d3 313 __IO uint32_t SDA; /*!< Pin select for SDA signal */
sahilmgandhi 18:6a4db94011d3 314 } TWIS_PSEL_Type;
sahilmgandhi 18:6a4db94011d3 315
sahilmgandhi 18:6a4db94011d3 316 typedef struct {
sahilmgandhi 18:6a4db94011d3 317 __IO uint32_t PTR; /*!< RXD Data pointer */
sahilmgandhi 18:6a4db94011d3 318 __IO uint32_t MAXCNT; /*!< Maximum number of bytes in RXD buffer */
sahilmgandhi 18:6a4db94011d3 319 __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last RXD transaction */
sahilmgandhi 18:6a4db94011d3 320 } TWIS_RXD_Type;
sahilmgandhi 18:6a4db94011d3 321
sahilmgandhi 18:6a4db94011d3 322 typedef struct {
sahilmgandhi 18:6a4db94011d3 323 __IO uint32_t PTR; /*!< TXD Data pointer */
sahilmgandhi 18:6a4db94011d3 324 __IO uint32_t MAXCNT; /*!< Maximum number of bytes in TXD buffer */
sahilmgandhi 18:6a4db94011d3 325 __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last TXD transaction */
sahilmgandhi 18:6a4db94011d3 326 } TWIS_TXD_Type;
sahilmgandhi 18:6a4db94011d3 327
sahilmgandhi 18:6a4db94011d3 328 typedef struct {
sahilmgandhi 18:6a4db94011d3 329 __IO uint32_t SCK; /*!< Pin select for SCK */
sahilmgandhi 18:6a4db94011d3 330 __IO uint32_t MOSI; /*!< Pin select for MOSI */
sahilmgandhi 18:6a4db94011d3 331 __IO uint32_t MISO; /*!< Pin select for MISO */
sahilmgandhi 18:6a4db94011d3 332 } SPI_PSEL_Type;
sahilmgandhi 18:6a4db94011d3 333
sahilmgandhi 18:6a4db94011d3 334 typedef struct {
sahilmgandhi 18:6a4db94011d3 335 __IO uint32_t RX; /*!< Result of last incoming frames */
sahilmgandhi 18:6a4db94011d3 336 } NFCT_FRAMESTATUS_Type;
sahilmgandhi 18:6a4db94011d3 337
sahilmgandhi 18:6a4db94011d3 338 typedef struct {
sahilmgandhi 18:6a4db94011d3 339 __IO uint32_t FRAMECONFIG; /*!< Configuration of outgoing frames */
sahilmgandhi 18:6a4db94011d3 340 __IO uint32_t AMOUNT; /*!< Size of outgoing frame */
sahilmgandhi 18:6a4db94011d3 341 } NFCT_TXD_Type;
sahilmgandhi 18:6a4db94011d3 342
sahilmgandhi 18:6a4db94011d3 343 typedef struct {
sahilmgandhi 18:6a4db94011d3 344 __IO uint32_t FRAMECONFIG; /*!< Configuration of incoming frames */
sahilmgandhi 18:6a4db94011d3 345 __I uint32_t AMOUNT; /*!< Size of last incoming frame */
sahilmgandhi 18:6a4db94011d3 346 } NFCT_RXD_Type;
sahilmgandhi 18:6a4db94011d3 347
sahilmgandhi 18:6a4db94011d3 348 typedef struct {
sahilmgandhi 18:6a4db94011d3 349 __IO uint32_t LIMITH; /*!< Description cluster[0]: Last results is equal or above CH[0].LIMIT.HIGH */
sahilmgandhi 18:6a4db94011d3 350 __IO uint32_t LIMITL; /*!< Description cluster[0]: Last results is equal or below CH[0].LIMIT.LOW */
sahilmgandhi 18:6a4db94011d3 351 } SAADC_EVENTS_CH_Type;
sahilmgandhi 18:6a4db94011d3 352
sahilmgandhi 18:6a4db94011d3 353 typedef struct {
sahilmgandhi 18:6a4db94011d3 354 __IO uint32_t PSELP; /*!< Description cluster[0]: Input positive pin selection for CH[0] */
sahilmgandhi 18:6a4db94011d3 355 __IO uint32_t PSELN; /*!< Description cluster[0]: Input negative pin selection for CH[0] */
sahilmgandhi 18:6a4db94011d3 356 __IO uint32_t CONFIG; /*!< Description cluster[0]: Input configuration for CH[0] */
sahilmgandhi 18:6a4db94011d3 357 __IO uint32_t LIMIT; /*!< Description cluster[0]: High/low limits for event monitoring
sahilmgandhi 18:6a4db94011d3 358 a channel */
sahilmgandhi 18:6a4db94011d3 359 } SAADC_CH_Type;
sahilmgandhi 18:6a4db94011d3 360
sahilmgandhi 18:6a4db94011d3 361 typedef struct {
sahilmgandhi 18:6a4db94011d3 362 __IO uint32_t PTR; /*!< Data pointer */
sahilmgandhi 18:6a4db94011d3 363 __IO uint32_t MAXCNT; /*!< Maximum number of buffer words to transfer */
sahilmgandhi 18:6a4db94011d3 364 __I uint32_t AMOUNT; /*!< Number of buffer words transferred since last START */
sahilmgandhi 18:6a4db94011d3 365 } SAADC_RESULT_Type;
sahilmgandhi 18:6a4db94011d3 366
sahilmgandhi 18:6a4db94011d3 367 typedef struct {
sahilmgandhi 18:6a4db94011d3 368 __IO uint32_t LED; /*!< Pin select for LED signal */
sahilmgandhi 18:6a4db94011d3 369 __IO uint32_t A; /*!< Pin select for A signal */
sahilmgandhi 18:6a4db94011d3 370 __IO uint32_t B; /*!< Pin select for B signal */
sahilmgandhi 18:6a4db94011d3 371 } QDEC_PSEL_Type;
sahilmgandhi 18:6a4db94011d3 372
sahilmgandhi 18:6a4db94011d3 373 typedef struct {
sahilmgandhi 18:6a4db94011d3 374 __IO uint32_t PTR; /*!< Description cluster[0]: Beginning address in Data RAM of sequence
sahilmgandhi 18:6a4db94011d3 375 A */
sahilmgandhi 18:6a4db94011d3 376 __IO uint32_t CNT; /*!< Description cluster[0]: Amount of values (duty cycles) in sequence
sahilmgandhi 18:6a4db94011d3 377 A */
sahilmgandhi 18:6a4db94011d3 378 __IO uint32_t REFRESH; /*!< Description cluster[0]: Amount of additional PWM periods between
sahilmgandhi 18:6a4db94011d3 379 samples loaded to compare register (load every CNT+1 PWM periods) */
sahilmgandhi 18:6a4db94011d3 380 __IO uint32_t ENDDELAY; /*!< Description cluster[0]: Time added after the sequence */
sahilmgandhi 18:6a4db94011d3 381 __I uint32_t RESERVED1[4];
sahilmgandhi 18:6a4db94011d3 382 } PWM_SEQ_Type;
sahilmgandhi 18:6a4db94011d3 383
sahilmgandhi 18:6a4db94011d3 384 typedef struct {
sahilmgandhi 18:6a4db94011d3 385 __IO uint32_t OUT[4]; /*!< Description collection[0]: Output pin select for PWM channel
sahilmgandhi 18:6a4db94011d3 386 0 */
sahilmgandhi 18:6a4db94011d3 387 } PWM_PSEL_Type;
sahilmgandhi 18:6a4db94011d3 388
sahilmgandhi 18:6a4db94011d3 389 typedef struct {
sahilmgandhi 18:6a4db94011d3 390 __IO uint32_t CLK; /*!< Pin number configuration for PDM CLK signal */
sahilmgandhi 18:6a4db94011d3 391 __IO uint32_t DIN; /*!< Pin number configuration for PDM DIN signal */
sahilmgandhi 18:6a4db94011d3 392 } PDM_PSEL_Type;
sahilmgandhi 18:6a4db94011d3 393
sahilmgandhi 18:6a4db94011d3 394 typedef struct {
sahilmgandhi 18:6a4db94011d3 395 __IO uint32_t PTR; /*!< RAM address pointer to write samples to with EasyDMA */
sahilmgandhi 18:6a4db94011d3 396 __IO uint32_t MAXCNT; /*!< Number of samples to allocate memory for in EasyDMA mode */
sahilmgandhi 18:6a4db94011d3 397 } PDM_SAMPLE_Type;
sahilmgandhi 18:6a4db94011d3 398
sahilmgandhi 18:6a4db94011d3 399 typedef struct {
sahilmgandhi 18:6a4db94011d3 400 __O uint32_t EN; /*!< Description cluster[0]: Enable channel group 0 */
sahilmgandhi 18:6a4db94011d3 401 __O uint32_t DIS; /*!< Description cluster[0]: Disable channel group 0 */
sahilmgandhi 18:6a4db94011d3 402 } PPI_TASKS_CHG_Type;
sahilmgandhi 18:6a4db94011d3 403
sahilmgandhi 18:6a4db94011d3 404 typedef struct {
sahilmgandhi 18:6a4db94011d3 405 __IO uint32_t EEP; /*!< Description cluster[0]: Channel 0 event end-point */
sahilmgandhi 18:6a4db94011d3 406 __IO uint32_t TEP; /*!< Description cluster[0]: Channel 0 task end-point */
sahilmgandhi 18:6a4db94011d3 407 } PPI_CH_Type;
sahilmgandhi 18:6a4db94011d3 408
sahilmgandhi 18:6a4db94011d3 409 typedef struct {
sahilmgandhi 18:6a4db94011d3 410 __IO uint32_t TEP; /*!< Description cluster[0]: Channel 0 task end-point */
sahilmgandhi 18:6a4db94011d3 411 } PPI_FORK_Type;
sahilmgandhi 18:6a4db94011d3 412
sahilmgandhi 18:6a4db94011d3 413 typedef struct {
sahilmgandhi 18:6a4db94011d3 414 __IO uint32_t WA; /*!< Description cluster[0]: Write access to region 0 detected */
sahilmgandhi 18:6a4db94011d3 415 __IO uint32_t RA; /*!< Description cluster[0]: Read access to region 0 detected */
sahilmgandhi 18:6a4db94011d3 416 } MWU_EVENTS_REGION_Type;
sahilmgandhi 18:6a4db94011d3 417
sahilmgandhi 18:6a4db94011d3 418 typedef struct {
sahilmgandhi 18:6a4db94011d3 419 __IO uint32_t WA; /*!< Description cluster[0]: Write access to peripheral region 0
sahilmgandhi 18:6a4db94011d3 420 detected */
sahilmgandhi 18:6a4db94011d3 421 __IO uint32_t RA; /*!< Description cluster[0]: Read access to peripheral region 0 detected */
sahilmgandhi 18:6a4db94011d3 422 } MWU_EVENTS_PREGION_Type;
sahilmgandhi 18:6a4db94011d3 423
sahilmgandhi 18:6a4db94011d3 424 typedef struct {
sahilmgandhi 18:6a4db94011d3 425 __IO uint32_t SUBSTATWA; /*!< Description cluster[0]: Source of event/interrupt in region
sahilmgandhi 18:6a4db94011d3 426 0, write access detected while corresponding subregion was enabled
sahilmgandhi 18:6a4db94011d3 427 for watching */
sahilmgandhi 18:6a4db94011d3 428 __IO uint32_t SUBSTATRA; /*!< Description cluster[0]: Source of event/interrupt in region
sahilmgandhi 18:6a4db94011d3 429 0, read access detected while corresponding subregion was enabled
sahilmgandhi 18:6a4db94011d3 430 for watching */
sahilmgandhi 18:6a4db94011d3 431 } MWU_PERREGION_Type;
sahilmgandhi 18:6a4db94011d3 432
sahilmgandhi 18:6a4db94011d3 433 typedef struct {
sahilmgandhi 18:6a4db94011d3 434 __IO uint32_t START; /*!< Description cluster[0]: Start address for region 0 */
sahilmgandhi 18:6a4db94011d3 435 __IO uint32_t END; /*!< Description cluster[0]: End address of region 0 */
sahilmgandhi 18:6a4db94011d3 436 __I uint32_t RESERVED2[2];
sahilmgandhi 18:6a4db94011d3 437 } MWU_REGION_Type;
sahilmgandhi 18:6a4db94011d3 438
sahilmgandhi 18:6a4db94011d3 439 typedef struct {
sahilmgandhi 18:6a4db94011d3 440 __I uint32_t START; /*!< Description cluster[0]: Reserved for future use */
sahilmgandhi 18:6a4db94011d3 441 __I uint32_t END; /*!< Description cluster[0]: Reserved for future use */
sahilmgandhi 18:6a4db94011d3 442 __IO uint32_t SUBS; /*!< Description cluster[0]: Subregions of region 0 */
sahilmgandhi 18:6a4db94011d3 443 __I uint32_t RESERVED3;
sahilmgandhi 18:6a4db94011d3 444 } MWU_PREGION_Type;
sahilmgandhi 18:6a4db94011d3 445
sahilmgandhi 18:6a4db94011d3 446 typedef struct {
sahilmgandhi 18:6a4db94011d3 447 __IO uint32_t MODE; /*!< I2S mode. */
sahilmgandhi 18:6a4db94011d3 448 __IO uint32_t RXEN; /*!< Reception (RX) enable. */
sahilmgandhi 18:6a4db94011d3 449 __IO uint32_t TXEN; /*!< Transmission (TX) enable. */
sahilmgandhi 18:6a4db94011d3 450 __IO uint32_t MCKEN; /*!< Master clock generator enable. */
sahilmgandhi 18:6a4db94011d3 451 __IO uint32_t MCKFREQ; /*!< Master clock generator frequency. */
sahilmgandhi 18:6a4db94011d3 452 __IO uint32_t RATIO; /*!< MCK / LRCK ratio. */
sahilmgandhi 18:6a4db94011d3 453 __IO uint32_t SWIDTH; /*!< Sample width. */
sahilmgandhi 18:6a4db94011d3 454 __IO uint32_t ALIGN; /*!< Alignment of sample within a frame. */
sahilmgandhi 18:6a4db94011d3 455 __IO uint32_t FORMAT; /*!< Frame format. */
sahilmgandhi 18:6a4db94011d3 456 __IO uint32_t CHANNELS; /*!< Enable channels. */
sahilmgandhi 18:6a4db94011d3 457 } I2S_CONFIG_Type;
sahilmgandhi 18:6a4db94011d3 458
sahilmgandhi 18:6a4db94011d3 459 typedef struct {
sahilmgandhi 18:6a4db94011d3 460 __IO uint32_t PTR; /*!< Receive buffer RAM start address. */
sahilmgandhi 18:6a4db94011d3 461 } I2S_RXD_Type;
sahilmgandhi 18:6a4db94011d3 462
sahilmgandhi 18:6a4db94011d3 463 typedef struct {
sahilmgandhi 18:6a4db94011d3 464 __IO uint32_t PTR; /*!< Transmit buffer RAM start address. */
sahilmgandhi 18:6a4db94011d3 465 } I2S_TXD_Type;
sahilmgandhi 18:6a4db94011d3 466
sahilmgandhi 18:6a4db94011d3 467 typedef struct {
sahilmgandhi 18:6a4db94011d3 468 __IO uint32_t MAXCNT; /*!< Size of RXD and TXD buffers. */
sahilmgandhi 18:6a4db94011d3 469 } I2S_RXTXD_Type;
sahilmgandhi 18:6a4db94011d3 470
sahilmgandhi 18:6a4db94011d3 471 typedef struct {
sahilmgandhi 18:6a4db94011d3 472 __IO uint32_t MCK; /*!< Pin select for MCK signal. */
sahilmgandhi 18:6a4db94011d3 473 __IO uint32_t SCK; /*!< Pin select for SCK signal. */
sahilmgandhi 18:6a4db94011d3 474 __IO uint32_t LRCK; /*!< Pin select for LRCK signal. */
sahilmgandhi 18:6a4db94011d3 475 __IO uint32_t SDIN; /*!< Pin select for SDIN signal. */
sahilmgandhi 18:6a4db94011d3 476 __IO uint32_t SDOUT; /*!< Pin select for SDOUT signal. */
sahilmgandhi 18:6a4db94011d3 477 } I2S_PSEL_Type;
sahilmgandhi 18:6a4db94011d3 478
sahilmgandhi 18:6a4db94011d3 479
sahilmgandhi 18:6a4db94011d3 480 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 481 /* ================ FICR ================ */
sahilmgandhi 18:6a4db94011d3 482 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 483
sahilmgandhi 18:6a4db94011d3 484
sahilmgandhi 18:6a4db94011d3 485 /**
sahilmgandhi 18:6a4db94011d3 486 * @brief Factory Information Configuration Registers (FICR)
sahilmgandhi 18:6a4db94011d3 487 */
sahilmgandhi 18:6a4db94011d3 488
sahilmgandhi 18:6a4db94011d3 489 typedef struct { /*!< FICR Structure */
sahilmgandhi 18:6a4db94011d3 490 __I uint32_t RESERVED0[4];
sahilmgandhi 18:6a4db94011d3 491 __I uint32_t CODEPAGESIZE; /*!< Code memory page size */
sahilmgandhi 18:6a4db94011d3 492 __I uint32_t CODESIZE; /*!< Code memory size */
sahilmgandhi 18:6a4db94011d3 493 __I uint32_t RESERVED1[18];
sahilmgandhi 18:6a4db94011d3 494 __I uint32_t DEVICEID[2]; /*!< Description collection[0]: Device identifier */
sahilmgandhi 18:6a4db94011d3 495 __I uint32_t RESERVED2[6];
sahilmgandhi 18:6a4db94011d3 496 __I uint32_t ER[4]; /*!< Description collection[0]: Encryption Root, word 0 */
sahilmgandhi 18:6a4db94011d3 497 __I uint32_t IR[4]; /*!< Description collection[0]: Identity Root, word 0 */
sahilmgandhi 18:6a4db94011d3 498 __I uint32_t DEVICEADDRTYPE; /*!< Device address type */
sahilmgandhi 18:6a4db94011d3 499 __I uint32_t DEVICEADDR[2]; /*!< Description collection[0]: Device address 0 */
sahilmgandhi 18:6a4db94011d3 500 __I uint32_t RESERVED3[21];
sahilmgandhi 18:6a4db94011d3 501 FICR_INFO_Type INFO; /*!< Device info */
sahilmgandhi 18:6a4db94011d3 502 __I uint32_t RESERVED4[185];
sahilmgandhi 18:6a4db94011d3 503 FICR_TEMP_Type TEMP; /*!< Registers storing factory TEMP module linearization coefficients */
sahilmgandhi 18:6a4db94011d3 504 __I uint32_t RESERVED5[2];
sahilmgandhi 18:6a4db94011d3 505 FICR_NFC_Type NFC; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 506 } NRF_FICR_Type;
sahilmgandhi 18:6a4db94011d3 507
sahilmgandhi 18:6a4db94011d3 508
sahilmgandhi 18:6a4db94011d3 509 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 510 /* ================ UICR ================ */
sahilmgandhi 18:6a4db94011d3 511 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 512
sahilmgandhi 18:6a4db94011d3 513
sahilmgandhi 18:6a4db94011d3 514 /**
sahilmgandhi 18:6a4db94011d3 515 * @brief User Information Configuration Registers (UICR)
sahilmgandhi 18:6a4db94011d3 516 */
sahilmgandhi 18:6a4db94011d3 517
sahilmgandhi 18:6a4db94011d3 518 typedef struct { /*!< UICR Structure */
sahilmgandhi 18:6a4db94011d3 519 __IO uint32_t UNUSED0; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 520 __IO uint32_t UNUSED1; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 521 __IO uint32_t UNUSED2; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 522 __I uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 523 __IO uint32_t UNUSED3; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 524 __IO uint32_t NRFFW[15]; /*!< Description collection[0]: Reserved for Nordic firmware design */
sahilmgandhi 18:6a4db94011d3 525 __IO uint32_t NRFHW[12]; /*!< Description collection[0]: Reserved for Nordic hardware design */
sahilmgandhi 18:6a4db94011d3 526 __IO uint32_t CUSTOMER[32]; /*!< Description collection[0]: Reserved for customer */
sahilmgandhi 18:6a4db94011d3 527 __I uint32_t RESERVED1[64];
sahilmgandhi 18:6a4db94011d3 528 __IO uint32_t PSELRESET[2]; /*!< Description collection[0]: Mapping of the nRESET function (see
sahilmgandhi 18:6a4db94011d3 529 POWER chapter for details) */
sahilmgandhi 18:6a4db94011d3 530 __IO uint32_t APPROTECT; /*!< Access Port protection */
sahilmgandhi 18:6a4db94011d3 531 __IO uint32_t NFCPINS; /*!< Setting of pins dedicated to NFC functionality: NFC antenna
sahilmgandhi 18:6a4db94011d3 532 or GPIO */
sahilmgandhi 18:6a4db94011d3 533 } NRF_UICR_Type;
sahilmgandhi 18:6a4db94011d3 534
sahilmgandhi 18:6a4db94011d3 535
sahilmgandhi 18:6a4db94011d3 536 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 537 /* ================ BPROT ================ */
sahilmgandhi 18:6a4db94011d3 538 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 539
sahilmgandhi 18:6a4db94011d3 540
sahilmgandhi 18:6a4db94011d3 541 /**
sahilmgandhi 18:6a4db94011d3 542 * @brief Block Protect (BPROT)
sahilmgandhi 18:6a4db94011d3 543 */
sahilmgandhi 18:6a4db94011d3 544
sahilmgandhi 18:6a4db94011d3 545 typedef struct { /*!< BPROT Structure */
sahilmgandhi 18:6a4db94011d3 546 __I uint32_t RESERVED0[384];
sahilmgandhi 18:6a4db94011d3 547 __IO uint32_t CONFIG0; /*!< Block protect configuration register 0 */
sahilmgandhi 18:6a4db94011d3 548 __IO uint32_t CONFIG1; /*!< Block protect configuration register 1 */
sahilmgandhi 18:6a4db94011d3 549 __IO uint32_t DISABLEINDEBUG; /*!< Disable protection mechanism in debug interface mode */
sahilmgandhi 18:6a4db94011d3 550 __IO uint32_t UNUSED0; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 551 __IO uint32_t CONFIG2; /*!< Block protect configuration register 2 */
sahilmgandhi 18:6a4db94011d3 552 __IO uint32_t CONFIG3; /*!< Block protect configuration register 3 */
sahilmgandhi 18:6a4db94011d3 553 } NRF_BPROT_Type;
sahilmgandhi 18:6a4db94011d3 554
sahilmgandhi 18:6a4db94011d3 555
sahilmgandhi 18:6a4db94011d3 556 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 557 /* ================ POWER ================ */
sahilmgandhi 18:6a4db94011d3 558 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 559
sahilmgandhi 18:6a4db94011d3 560
sahilmgandhi 18:6a4db94011d3 561 /**
sahilmgandhi 18:6a4db94011d3 562 * @brief Power control (POWER)
sahilmgandhi 18:6a4db94011d3 563 */
sahilmgandhi 18:6a4db94011d3 564
sahilmgandhi 18:6a4db94011d3 565 typedef struct { /*!< POWER Structure */
sahilmgandhi 18:6a4db94011d3 566 __I uint32_t RESERVED0[30];
sahilmgandhi 18:6a4db94011d3 567 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode */
sahilmgandhi 18:6a4db94011d3 568 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency) */
sahilmgandhi 18:6a4db94011d3 569 __I uint32_t RESERVED1[34];
sahilmgandhi 18:6a4db94011d3 570 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning */
sahilmgandhi 18:6a4db94011d3 571 __I uint32_t RESERVED2[2];
sahilmgandhi 18:6a4db94011d3 572 __IO uint32_t EVENTS_SLEEPENTER; /*!< CPU entered WFI/WFE sleep */
sahilmgandhi 18:6a4db94011d3 573 __IO uint32_t EVENTS_SLEEPEXIT; /*!< CPU exited WFI/WFE sleep */
sahilmgandhi 18:6a4db94011d3 574 __I uint32_t RESERVED3[122];
sahilmgandhi 18:6a4db94011d3 575 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 576 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 577 __I uint32_t RESERVED4[61];
sahilmgandhi 18:6a4db94011d3 578 __IO uint32_t RESETREAS; /*!< Reset reason */
sahilmgandhi 18:6a4db94011d3 579 __I uint32_t RESERVED5[9];
sahilmgandhi 18:6a4db94011d3 580 __I uint32_t RAMSTATUS; /*!< Deprecated register - RAM status register */
sahilmgandhi 18:6a4db94011d3 581 __I uint32_t RESERVED6[53];
sahilmgandhi 18:6a4db94011d3 582 __O uint32_t SYSTEMOFF; /*!< System OFF register */
sahilmgandhi 18:6a4db94011d3 583 __I uint32_t RESERVED7[3];
sahilmgandhi 18:6a4db94011d3 584 __IO uint32_t POFCON; /*!< Power failure comparator configuration */
sahilmgandhi 18:6a4db94011d3 585 __I uint32_t RESERVED8[2];
sahilmgandhi 18:6a4db94011d3 586 __IO uint32_t GPREGRET; /*!< General purpose retention register */
sahilmgandhi 18:6a4db94011d3 587 __IO uint32_t GPREGRET2; /*!< General purpose retention register */
sahilmgandhi 18:6a4db94011d3 588 __IO uint32_t RAMON; /*!< Deprecated register - RAM on/off register (this register is
sahilmgandhi 18:6a4db94011d3 589 retained) */
sahilmgandhi 18:6a4db94011d3 590 __I uint32_t RESERVED9[11];
sahilmgandhi 18:6a4db94011d3 591 __IO uint32_t RAMONB; /*!< Deprecated register - RAM on/off register (this register is
sahilmgandhi 18:6a4db94011d3 592 retained) */
sahilmgandhi 18:6a4db94011d3 593 __I uint32_t RESERVED10[8];
sahilmgandhi 18:6a4db94011d3 594 __IO uint32_t DCDCEN; /*!< DC/DC enable register */
sahilmgandhi 18:6a4db94011d3 595 __I uint32_t RESERVED11[225];
sahilmgandhi 18:6a4db94011d3 596 POWER_RAM_Type RAM[8]; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 597 } NRF_POWER_Type;
sahilmgandhi 18:6a4db94011d3 598
sahilmgandhi 18:6a4db94011d3 599
sahilmgandhi 18:6a4db94011d3 600 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 601 /* ================ CLOCK ================ */
sahilmgandhi 18:6a4db94011d3 602 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 603
sahilmgandhi 18:6a4db94011d3 604
sahilmgandhi 18:6a4db94011d3 605 /**
sahilmgandhi 18:6a4db94011d3 606 * @brief Clock control (CLOCK)
sahilmgandhi 18:6a4db94011d3 607 */
sahilmgandhi 18:6a4db94011d3 608
sahilmgandhi 18:6a4db94011d3 609 typedef struct { /*!< CLOCK Structure */
sahilmgandhi 18:6a4db94011d3 610 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK crystal oscillator */
sahilmgandhi 18:6a4db94011d3 611 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK crystal oscillator */
sahilmgandhi 18:6a4db94011d3 612 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK source */
sahilmgandhi 18:6a4db94011d3 613 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK source */
sahilmgandhi 18:6a4db94011d3 614 __O uint32_t TASKS_CAL; /*!< Start calibration of LFRC oscillator */
sahilmgandhi 18:6a4db94011d3 615 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer */
sahilmgandhi 18:6a4db94011d3 616 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer */
sahilmgandhi 18:6a4db94011d3 617 __I uint32_t RESERVED0[57];
sahilmgandhi 18:6a4db94011d3 618 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started */
sahilmgandhi 18:6a4db94011d3 619 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK started */
sahilmgandhi 18:6a4db94011d3 620 __I uint32_t RESERVED1;
sahilmgandhi 18:6a4db94011d3 621 __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator complete event */
sahilmgandhi 18:6a4db94011d3 622 __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout */
sahilmgandhi 18:6a4db94011d3 623 __I uint32_t RESERVED2[124];
sahilmgandhi 18:6a4db94011d3 624 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 625 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 626 __I uint32_t RESERVED3[63];
sahilmgandhi 18:6a4db94011d3 627 __I uint32_t HFCLKRUN; /*!< Status indicating that HFCLKSTART task has been triggered */
sahilmgandhi 18:6a4db94011d3 628 __I uint32_t HFCLKSTAT; /*!< HFCLK status */
sahilmgandhi 18:6a4db94011d3 629 __I uint32_t RESERVED4;
sahilmgandhi 18:6a4db94011d3 630 __I uint32_t LFCLKRUN; /*!< Status indicating that LFCLKSTART task has been triggered */
sahilmgandhi 18:6a4db94011d3 631 __I uint32_t LFCLKSTAT; /*!< LFCLK status */
sahilmgandhi 18:6a4db94011d3 632 __I uint32_t LFCLKSRCCOPY; /*!< Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
sahilmgandhi 18:6a4db94011d3 633 __I uint32_t RESERVED5[62];
sahilmgandhi 18:6a4db94011d3 634 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK */
sahilmgandhi 18:6a4db94011d3 635 __I uint32_t RESERVED6[7];
sahilmgandhi 18:6a4db94011d3 636 __IO uint32_t CTIV; /*!< Calibration timer interval (retained register, same reset behaviour
sahilmgandhi 18:6a4db94011d3 637 as RESETREAS) */
sahilmgandhi 18:6a4db94011d3 638 __I uint32_t RESERVED7[8];
sahilmgandhi 18:6a4db94011d3 639 __IO uint32_t TRACECONFIG; /*!< Clocking options for the Trace Port debug interface */
sahilmgandhi 18:6a4db94011d3 640 } NRF_CLOCK_Type;
sahilmgandhi 18:6a4db94011d3 641
sahilmgandhi 18:6a4db94011d3 642
sahilmgandhi 18:6a4db94011d3 643 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 644 /* ================ AMLI ================ */
sahilmgandhi 18:6a4db94011d3 645 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 646
sahilmgandhi 18:6a4db94011d3 647
sahilmgandhi 18:6a4db94011d3 648 /**
sahilmgandhi 18:6a4db94011d3 649 * @brief AHB Multi-Layer Interface (AMLI)
sahilmgandhi 18:6a4db94011d3 650 */
sahilmgandhi 18:6a4db94011d3 651
sahilmgandhi 18:6a4db94011d3 652 typedef struct { /*!< AMLI Structure */
sahilmgandhi 18:6a4db94011d3 653 __I uint32_t RESERVED0[896];
sahilmgandhi 18:6a4db94011d3 654 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure */
sahilmgandhi 18:6a4db94011d3 655 } NRF_AMLI_Type;
sahilmgandhi 18:6a4db94011d3 656
sahilmgandhi 18:6a4db94011d3 657
sahilmgandhi 18:6a4db94011d3 658 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 659 /* ================ RADIO ================ */
sahilmgandhi 18:6a4db94011d3 660 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 661
sahilmgandhi 18:6a4db94011d3 662
sahilmgandhi 18:6a4db94011d3 663 /**
sahilmgandhi 18:6a4db94011d3 664 * @brief 2.4 GHz Radio (RADIO)
sahilmgandhi 18:6a4db94011d3 665 */
sahilmgandhi 18:6a4db94011d3 666
sahilmgandhi 18:6a4db94011d3 667 typedef struct { /*!< RADIO Structure */
sahilmgandhi 18:6a4db94011d3 668 __O uint32_t TASKS_TXEN; /*!< Enable RADIO in TX mode */
sahilmgandhi 18:6a4db94011d3 669 __O uint32_t TASKS_RXEN; /*!< Enable RADIO in RX mode */
sahilmgandhi 18:6a4db94011d3 670 __O uint32_t TASKS_START; /*!< Start RADIO */
sahilmgandhi 18:6a4db94011d3 671 __O uint32_t TASKS_STOP; /*!< Stop RADIO */
sahilmgandhi 18:6a4db94011d3 672 __O uint32_t TASKS_DISABLE; /*!< Disable RADIO */
sahilmgandhi 18:6a4db94011d3 673 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one single sample of the receive signal
sahilmgandhi 18:6a4db94011d3 674 strength. */
sahilmgandhi 18:6a4db94011d3 675 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement */
sahilmgandhi 18:6a4db94011d3 676 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter */
sahilmgandhi 18:6a4db94011d3 677 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter */
sahilmgandhi 18:6a4db94011d3 678 __I uint32_t RESERVED0[55];
sahilmgandhi 18:6a4db94011d3 679 __IO uint32_t EVENTS_READY; /*!< RADIO has ramped up and is ready to be started */
sahilmgandhi 18:6a4db94011d3 680 __IO uint32_t EVENTS_ADDRESS; /*!< Address sent or received */
sahilmgandhi 18:6a4db94011d3 681 __IO uint32_t EVENTS_PAYLOAD; /*!< Packet payload sent or received */
sahilmgandhi 18:6a4db94011d3 682 __IO uint32_t EVENTS_END; /*!< Packet sent or received */
sahilmgandhi 18:6a4db94011d3 683 __IO uint32_t EVENTS_DISABLED; /*!< RADIO has been disabled */
sahilmgandhi 18:6a4db94011d3 684 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet */
sahilmgandhi 18:6a4db94011d3 685 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet */
sahilmgandhi 18:6a4db94011d3 686 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of receive signal strength complete. */
sahilmgandhi 18:6a4db94011d3 687 __I uint32_t RESERVED1[2];
sahilmgandhi 18:6a4db94011d3 688 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value. */
sahilmgandhi 18:6a4db94011d3 689 __I uint32_t RESERVED2;
sahilmgandhi 18:6a4db94011d3 690 __IO uint32_t EVENTS_CRCOK; /*!< Packet received with CRC ok */
sahilmgandhi 18:6a4db94011d3 691 __IO uint32_t EVENTS_CRCERROR; /*!< Packet received with CRC error */
sahilmgandhi 18:6a4db94011d3 692 __I uint32_t RESERVED3[50];
sahilmgandhi 18:6a4db94011d3 693 __IO uint32_t SHORTS; /*!< Shortcut register */
sahilmgandhi 18:6a4db94011d3 694 __I uint32_t RESERVED4[64];
sahilmgandhi 18:6a4db94011d3 695 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 696 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 697 __I uint32_t RESERVED5[61];
sahilmgandhi 18:6a4db94011d3 698 __I uint32_t CRCSTATUS; /*!< CRC status */
sahilmgandhi 18:6a4db94011d3 699 __I uint32_t RESERVED6;
sahilmgandhi 18:6a4db94011d3 700 __I uint32_t RXMATCH; /*!< Received address */
sahilmgandhi 18:6a4db94011d3 701 __I uint32_t RXCRC; /*!< CRC field of previously received packet */
sahilmgandhi 18:6a4db94011d3 702 __I uint32_t DAI; /*!< Device address match index */
sahilmgandhi 18:6a4db94011d3 703 __I uint32_t RESERVED7[60];
sahilmgandhi 18:6a4db94011d3 704 __IO uint32_t PACKETPTR; /*!< Packet pointer */
sahilmgandhi 18:6a4db94011d3 705 __IO uint32_t FREQUENCY; /*!< Frequency */
sahilmgandhi 18:6a4db94011d3 706 __IO uint32_t TXPOWER; /*!< Output power */
sahilmgandhi 18:6a4db94011d3 707 __IO uint32_t MODE; /*!< Data rate and modulation */
sahilmgandhi 18:6a4db94011d3 708 __IO uint32_t PCNF0; /*!< Packet configuration register 0 */
sahilmgandhi 18:6a4db94011d3 709 __IO uint32_t PCNF1; /*!< Packet configuration register 1 */
sahilmgandhi 18:6a4db94011d3 710 __IO uint32_t BASE0; /*!< Base address 0 */
sahilmgandhi 18:6a4db94011d3 711 __IO uint32_t BASE1; /*!< Base address 1 */
sahilmgandhi 18:6a4db94011d3 712 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0-3 */
sahilmgandhi 18:6a4db94011d3 713 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4-7 */
sahilmgandhi 18:6a4db94011d3 714 __IO uint32_t TXADDRESS; /*!< Transmit address select */
sahilmgandhi 18:6a4db94011d3 715 __IO uint32_t RXADDRESSES; /*!< Receive address select */
sahilmgandhi 18:6a4db94011d3 716 __IO uint32_t CRCCNF; /*!< CRC configuration */
sahilmgandhi 18:6a4db94011d3 717 __IO uint32_t CRCPOLY; /*!< CRC polynomial */
sahilmgandhi 18:6a4db94011d3 718 __IO uint32_t CRCINIT; /*!< CRC initial value */
sahilmgandhi 18:6a4db94011d3 719 __IO uint32_t UNUSED0; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 720 __IO uint32_t TIFS; /*!< Inter Frame Spacing in us */
sahilmgandhi 18:6a4db94011d3 721 __I uint32_t RSSISAMPLE; /*!< RSSI sample */
sahilmgandhi 18:6a4db94011d3 722 __I uint32_t RESERVED8;
sahilmgandhi 18:6a4db94011d3 723 __I uint32_t STATE; /*!< Current radio state */
sahilmgandhi 18:6a4db94011d3 724 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value */
sahilmgandhi 18:6a4db94011d3 725 __I uint32_t RESERVED9[2];
sahilmgandhi 18:6a4db94011d3 726 __IO uint32_t BCC; /*!< Bit counter compare */
sahilmgandhi 18:6a4db94011d3 727 __I uint32_t RESERVED10[39];
sahilmgandhi 18:6a4db94011d3 728 __IO uint32_t DAB[8]; /*!< Description collection[0]: Device address base segment 0 */
sahilmgandhi 18:6a4db94011d3 729 __IO uint32_t DAP[8]; /*!< Description collection[0]: Device address prefix 0 */
sahilmgandhi 18:6a4db94011d3 730 __IO uint32_t DACNF; /*!< Device address match configuration */
sahilmgandhi 18:6a4db94011d3 731 __I uint32_t RESERVED11[3];
sahilmgandhi 18:6a4db94011d3 732 __IO uint32_t MODECNF0; /*!< Radio mode configuration register 0 */
sahilmgandhi 18:6a4db94011d3 733 __I uint32_t RESERVED12[618];
sahilmgandhi 18:6a4db94011d3 734 __IO uint32_t POWER; /*!< Peripheral power control */
sahilmgandhi 18:6a4db94011d3 735 } NRF_RADIO_Type;
sahilmgandhi 18:6a4db94011d3 736
sahilmgandhi 18:6a4db94011d3 737
sahilmgandhi 18:6a4db94011d3 738 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 739 /* ================ UARTE ================ */
sahilmgandhi 18:6a4db94011d3 740 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 741
sahilmgandhi 18:6a4db94011d3 742
sahilmgandhi 18:6a4db94011d3 743 /**
sahilmgandhi 18:6a4db94011d3 744 * @brief UART with EasyDMA (UARTE)
sahilmgandhi 18:6a4db94011d3 745 */
sahilmgandhi 18:6a4db94011d3 746
sahilmgandhi 18:6a4db94011d3 747 typedef struct { /*!< UARTE Structure */
sahilmgandhi 18:6a4db94011d3 748 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver */
sahilmgandhi 18:6a4db94011d3 749 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver */
sahilmgandhi 18:6a4db94011d3 750 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter */
sahilmgandhi 18:6a4db94011d3 751 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter */
sahilmgandhi 18:6a4db94011d3 752 __I uint32_t RESERVED0[7];
sahilmgandhi 18:6a4db94011d3 753 __O uint32_t TASKS_FLUSHRX; /*!< Flush RX FIFO into RX buffer */
sahilmgandhi 18:6a4db94011d3 754 __I uint32_t RESERVED1[52];
sahilmgandhi 18:6a4db94011d3 755 __IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */
sahilmgandhi 18:6a4db94011d3 756 __IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */
sahilmgandhi 18:6a4db94011d3 757 __I uint32_t RESERVED2[2];
sahilmgandhi 18:6a4db94011d3 758 __IO uint32_t EVENTS_ENDRX; /*!< Receive buffer is filled up */
sahilmgandhi 18:6a4db94011d3 759 __I uint32_t RESERVED3[3];
sahilmgandhi 18:6a4db94011d3 760 __IO uint32_t EVENTS_ENDTX; /*!< Last TX byte transmitted */
sahilmgandhi 18:6a4db94011d3 761 __IO uint32_t EVENTS_ERROR; /*!< Error detected */
sahilmgandhi 18:6a4db94011d3 762 __I uint32_t RESERVED4[7];
sahilmgandhi 18:6a4db94011d3 763 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout */
sahilmgandhi 18:6a4db94011d3 764 __I uint32_t RESERVED5;
sahilmgandhi 18:6a4db94011d3 765 __IO uint32_t EVENTS_RXSTARTED; /*!< UART receiver has started */
sahilmgandhi 18:6a4db94011d3 766 __IO uint32_t EVENTS_TXSTARTED; /*!< UART transmitter has started */
sahilmgandhi 18:6a4db94011d3 767 __I uint32_t RESERVED6;
sahilmgandhi 18:6a4db94011d3 768 __IO uint32_t EVENTS_TXSTOPPED; /*!< Transmitter stopped */
sahilmgandhi 18:6a4db94011d3 769 __I uint32_t RESERVED7[41];
sahilmgandhi 18:6a4db94011d3 770 __IO uint32_t SHORTS; /*!< Shortcut register */
sahilmgandhi 18:6a4db94011d3 771 __I uint32_t RESERVED8[63];
sahilmgandhi 18:6a4db94011d3 772 __IO uint32_t INTEN; /*!< Enable or disable interrupt */
sahilmgandhi 18:6a4db94011d3 773 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 774 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 775 __I uint32_t RESERVED9[93];
sahilmgandhi 18:6a4db94011d3 776 __IO uint32_t ERRORSRC; /*!< Error source */
sahilmgandhi 18:6a4db94011d3 777 __I uint32_t RESERVED10[31];
sahilmgandhi 18:6a4db94011d3 778 __IO uint32_t ENABLE; /*!< Enable UART */
sahilmgandhi 18:6a4db94011d3 779 __I uint32_t RESERVED11;
sahilmgandhi 18:6a4db94011d3 780 UARTE_PSEL_Type PSEL; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 781 __I uint32_t RESERVED12[3];
sahilmgandhi 18:6a4db94011d3 782 __IO uint32_t BAUDRATE; /*!< Baud rate */
sahilmgandhi 18:6a4db94011d3 783 __I uint32_t RESERVED13[3];
sahilmgandhi 18:6a4db94011d3 784 UARTE_RXD_Type RXD; /*!< RXD EasyDMA channel */
sahilmgandhi 18:6a4db94011d3 785 __I uint32_t RESERVED14;
sahilmgandhi 18:6a4db94011d3 786 UARTE_TXD_Type TXD; /*!< TXD EasyDMA channel */
sahilmgandhi 18:6a4db94011d3 787 __I uint32_t RESERVED15[7];
sahilmgandhi 18:6a4db94011d3 788 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control */
sahilmgandhi 18:6a4db94011d3 789 } NRF_UARTE_Type;
sahilmgandhi 18:6a4db94011d3 790
sahilmgandhi 18:6a4db94011d3 791
sahilmgandhi 18:6a4db94011d3 792 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 793 /* ================ UART ================ */
sahilmgandhi 18:6a4db94011d3 794 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 795
sahilmgandhi 18:6a4db94011d3 796
sahilmgandhi 18:6a4db94011d3 797 /**
sahilmgandhi 18:6a4db94011d3 798 * @brief Universal Asynchronous Receiver/Transmitter (UART)
sahilmgandhi 18:6a4db94011d3 799 */
sahilmgandhi 18:6a4db94011d3 800
sahilmgandhi 18:6a4db94011d3 801 typedef struct { /*!< UART Structure */
sahilmgandhi 18:6a4db94011d3 802 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver */
sahilmgandhi 18:6a4db94011d3 803 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver */
sahilmgandhi 18:6a4db94011d3 804 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter */
sahilmgandhi 18:6a4db94011d3 805 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter */
sahilmgandhi 18:6a4db94011d3 806 __I uint32_t RESERVED0[3];
sahilmgandhi 18:6a4db94011d3 807 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART */
sahilmgandhi 18:6a4db94011d3 808 __I uint32_t RESERVED1[56];
sahilmgandhi 18:6a4db94011d3 809 __IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */
sahilmgandhi 18:6a4db94011d3 810 __IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */
sahilmgandhi 18:6a4db94011d3 811 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD */
sahilmgandhi 18:6a4db94011d3 812 __I uint32_t RESERVED2[4];
sahilmgandhi 18:6a4db94011d3 813 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD */
sahilmgandhi 18:6a4db94011d3 814 __I uint32_t RESERVED3;
sahilmgandhi 18:6a4db94011d3 815 __IO uint32_t EVENTS_ERROR; /*!< Error detected */
sahilmgandhi 18:6a4db94011d3 816 __I uint32_t RESERVED4[7];
sahilmgandhi 18:6a4db94011d3 817 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout */
sahilmgandhi 18:6a4db94011d3 818 __I uint32_t RESERVED5[46];
sahilmgandhi 18:6a4db94011d3 819 __IO uint32_t SHORTS; /*!< Shortcut register */
sahilmgandhi 18:6a4db94011d3 820 __I uint32_t RESERVED6[64];
sahilmgandhi 18:6a4db94011d3 821 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 822 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 823 __I uint32_t RESERVED7[93];
sahilmgandhi 18:6a4db94011d3 824 __IO uint32_t ERRORSRC; /*!< Error source */
sahilmgandhi 18:6a4db94011d3 825 __I uint32_t RESERVED8[31];
sahilmgandhi 18:6a4db94011d3 826 __IO uint32_t ENABLE; /*!< Enable UART */
sahilmgandhi 18:6a4db94011d3 827 __I uint32_t RESERVED9;
sahilmgandhi 18:6a4db94011d3 828 __IO uint32_t PSELRTS; /*!< Pin select for RTS */
sahilmgandhi 18:6a4db94011d3 829 __IO uint32_t PSELTXD; /*!< Pin select for TXD */
sahilmgandhi 18:6a4db94011d3 830 __IO uint32_t PSELCTS; /*!< Pin select for CTS */
sahilmgandhi 18:6a4db94011d3 831 __IO uint32_t PSELRXD; /*!< Pin select for RXD */
sahilmgandhi 18:6a4db94011d3 832 __I uint32_t RXD; /*!< RXD register */
sahilmgandhi 18:6a4db94011d3 833 __O uint32_t TXD; /*!< TXD register */
sahilmgandhi 18:6a4db94011d3 834 __I uint32_t RESERVED10;
sahilmgandhi 18:6a4db94011d3 835 __IO uint32_t BAUDRATE; /*!< Baud rate */
sahilmgandhi 18:6a4db94011d3 836 __I uint32_t RESERVED11[17];
sahilmgandhi 18:6a4db94011d3 837 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control */
sahilmgandhi 18:6a4db94011d3 838 } NRF_UART_Type;
sahilmgandhi 18:6a4db94011d3 839
sahilmgandhi 18:6a4db94011d3 840
sahilmgandhi 18:6a4db94011d3 841 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 842 /* ================ SPIM ================ */
sahilmgandhi 18:6a4db94011d3 843 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 844
sahilmgandhi 18:6a4db94011d3 845
sahilmgandhi 18:6a4db94011d3 846 /**
sahilmgandhi 18:6a4db94011d3 847 * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM)
sahilmgandhi 18:6a4db94011d3 848 */
sahilmgandhi 18:6a4db94011d3 849
sahilmgandhi 18:6a4db94011d3 850 typedef struct { /*!< SPIM Structure */
sahilmgandhi 18:6a4db94011d3 851 __I uint32_t RESERVED0[4];
sahilmgandhi 18:6a4db94011d3 852 __O uint32_t TASKS_START; /*!< Start SPI transaction */
sahilmgandhi 18:6a4db94011d3 853 __O uint32_t TASKS_STOP; /*!< Stop SPI transaction */
sahilmgandhi 18:6a4db94011d3 854 __I uint32_t RESERVED1;
sahilmgandhi 18:6a4db94011d3 855 __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction */
sahilmgandhi 18:6a4db94011d3 856 __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction */
sahilmgandhi 18:6a4db94011d3 857 __I uint32_t RESERVED2[56];
sahilmgandhi 18:6a4db94011d3 858 __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped */
sahilmgandhi 18:6a4db94011d3 859 __I uint32_t RESERVED3[2];
sahilmgandhi 18:6a4db94011d3 860 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */
sahilmgandhi 18:6a4db94011d3 861 __I uint32_t RESERVED4;
sahilmgandhi 18:6a4db94011d3 862 __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached */
sahilmgandhi 18:6a4db94011d3 863 __I uint32_t RESERVED5;
sahilmgandhi 18:6a4db94011d3 864 __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached */
sahilmgandhi 18:6a4db94011d3 865 __I uint32_t RESERVED6[10];
sahilmgandhi 18:6a4db94011d3 866 __IO uint32_t EVENTS_STARTED; /*!< Transaction started */
sahilmgandhi 18:6a4db94011d3 867 __I uint32_t RESERVED7[44];
sahilmgandhi 18:6a4db94011d3 868 __IO uint32_t SHORTS; /*!< Shortcut register */
sahilmgandhi 18:6a4db94011d3 869 __I uint32_t RESERVED8[64];
sahilmgandhi 18:6a4db94011d3 870 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 871 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 872 __I uint32_t RESERVED9[125];
sahilmgandhi 18:6a4db94011d3 873 __IO uint32_t ENABLE; /*!< Enable SPIM */
sahilmgandhi 18:6a4db94011d3 874 __I uint32_t RESERVED10;
sahilmgandhi 18:6a4db94011d3 875 SPIM_PSEL_Type PSEL; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 876 __I uint32_t RESERVED11[4];
sahilmgandhi 18:6a4db94011d3 877 __IO uint32_t FREQUENCY; /*!< SPI frequency */
sahilmgandhi 18:6a4db94011d3 878 __I uint32_t RESERVED12[3];
sahilmgandhi 18:6a4db94011d3 879 SPIM_RXD_Type RXD; /*!< RXD EasyDMA channel */
sahilmgandhi 18:6a4db94011d3 880 SPIM_TXD_Type TXD; /*!< TXD EasyDMA channel */
sahilmgandhi 18:6a4db94011d3 881 __IO uint32_t CONFIG; /*!< Configuration register */
sahilmgandhi 18:6a4db94011d3 882 __I uint32_t RESERVED13[26];
sahilmgandhi 18:6a4db94011d3 883 __IO uint32_t ORC; /*!< Over-read character. Character clocked out in case and over-read
sahilmgandhi 18:6a4db94011d3 884 of the TXD buffer. */
sahilmgandhi 18:6a4db94011d3 885 } NRF_SPIM_Type;
sahilmgandhi 18:6a4db94011d3 886
sahilmgandhi 18:6a4db94011d3 887
sahilmgandhi 18:6a4db94011d3 888 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 889 /* ================ SPIS ================ */
sahilmgandhi 18:6a4db94011d3 890 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 891
sahilmgandhi 18:6a4db94011d3 892
sahilmgandhi 18:6a4db94011d3 893 /**
sahilmgandhi 18:6a4db94011d3 894 * @brief SPI Slave 0 (SPIS)
sahilmgandhi 18:6a4db94011d3 895 */
sahilmgandhi 18:6a4db94011d3 896
sahilmgandhi 18:6a4db94011d3 897 typedef struct { /*!< SPIS Structure */
sahilmgandhi 18:6a4db94011d3 898 __I uint32_t RESERVED0[9];
sahilmgandhi 18:6a4db94011d3 899 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore */
sahilmgandhi 18:6a4db94011d3 900 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore, enabling the SPI slave to acquire it */
sahilmgandhi 18:6a4db94011d3 901 __I uint32_t RESERVED1[54];
sahilmgandhi 18:6a4db94011d3 902 __IO uint32_t EVENTS_END; /*!< Granted transaction completed */
sahilmgandhi 18:6a4db94011d3 903 __I uint32_t RESERVED2[2];
sahilmgandhi 18:6a4db94011d3 904 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */
sahilmgandhi 18:6a4db94011d3 905 __I uint32_t RESERVED3[5];
sahilmgandhi 18:6a4db94011d3 906 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired */
sahilmgandhi 18:6a4db94011d3 907 __I uint32_t RESERVED4[53];
sahilmgandhi 18:6a4db94011d3 908 __IO uint32_t SHORTS; /*!< Shortcut register */
sahilmgandhi 18:6a4db94011d3 909 __I uint32_t RESERVED5[64];
sahilmgandhi 18:6a4db94011d3 910 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 911 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 912 __I uint32_t RESERVED6[61];
sahilmgandhi 18:6a4db94011d3 913 __I uint32_t SEMSTAT; /*!< Semaphore status register */
sahilmgandhi 18:6a4db94011d3 914 __I uint32_t RESERVED7[15];
sahilmgandhi 18:6a4db94011d3 915 __IO uint32_t STATUS; /*!< Status from last transaction */
sahilmgandhi 18:6a4db94011d3 916 __I uint32_t RESERVED8[47];
sahilmgandhi 18:6a4db94011d3 917 __IO uint32_t ENABLE; /*!< Enable SPI slave */
sahilmgandhi 18:6a4db94011d3 918 __I uint32_t RESERVED9;
sahilmgandhi 18:6a4db94011d3 919 SPIS_PSEL_Type PSEL; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 920 __I uint32_t RESERVED10[7];
sahilmgandhi 18:6a4db94011d3 921 SPIS_RXD_Type RXD; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 922 __I uint32_t RESERVED11;
sahilmgandhi 18:6a4db94011d3 923 SPIS_TXD_Type TXD; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 924 __I uint32_t RESERVED12;
sahilmgandhi 18:6a4db94011d3 925 __IO uint32_t CONFIG; /*!< Configuration register */
sahilmgandhi 18:6a4db94011d3 926 __I uint32_t RESERVED13;
sahilmgandhi 18:6a4db94011d3 927 __IO uint32_t DEF; /*!< Default character. Character clocked out in case of an ignored
sahilmgandhi 18:6a4db94011d3 928 transaction. */
sahilmgandhi 18:6a4db94011d3 929 __I uint32_t RESERVED14[24];
sahilmgandhi 18:6a4db94011d3 930 __IO uint32_t ORC; /*!< Over-read character */
sahilmgandhi 18:6a4db94011d3 931 } NRF_SPIS_Type;
sahilmgandhi 18:6a4db94011d3 932
sahilmgandhi 18:6a4db94011d3 933
sahilmgandhi 18:6a4db94011d3 934 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 935 /* ================ TWIM ================ */
sahilmgandhi 18:6a4db94011d3 936 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 937
sahilmgandhi 18:6a4db94011d3 938
sahilmgandhi 18:6a4db94011d3 939 /**
sahilmgandhi 18:6a4db94011d3 940 * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM)
sahilmgandhi 18:6a4db94011d3 941 */
sahilmgandhi 18:6a4db94011d3 942
sahilmgandhi 18:6a4db94011d3 943 typedef struct { /*!< TWIM Structure */
sahilmgandhi 18:6a4db94011d3 944 __O uint32_t TASKS_STARTRX; /*!< Start TWI receive sequence */
sahilmgandhi 18:6a4db94011d3 945 __I uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 946 __O uint32_t TASKS_STARTTX; /*!< Start TWI transmit sequence */
sahilmgandhi 18:6a4db94011d3 947 __I uint32_t RESERVED1[2];
sahilmgandhi 18:6a4db94011d3 948 __O uint32_t TASKS_STOP; /*!< Stop TWI transaction. Must be issued while the TWI master is
sahilmgandhi 18:6a4db94011d3 949 not suspended. */
sahilmgandhi 18:6a4db94011d3 950 __I uint32_t RESERVED2;
sahilmgandhi 18:6a4db94011d3 951 __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */
sahilmgandhi 18:6a4db94011d3 952 __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */
sahilmgandhi 18:6a4db94011d3 953 __I uint32_t RESERVED3[56];
sahilmgandhi 18:6a4db94011d3 954 __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */
sahilmgandhi 18:6a4db94011d3 955 __I uint32_t RESERVED4[7];
sahilmgandhi 18:6a4db94011d3 956 __IO uint32_t EVENTS_ERROR; /*!< TWI error */
sahilmgandhi 18:6a4db94011d3 957 __I uint32_t RESERVED5[8];
sahilmgandhi 18:6a4db94011d3 958 __IO uint32_t EVENTS_SUSPENDED; /*!< Last byte has been sent out after the SUSPEND task has been
sahilmgandhi 18:6a4db94011d3 959 issued, TWI traffic is now suspended. */
sahilmgandhi 18:6a4db94011d3 960 __IO uint32_t EVENTS_RXSTARTED; /*!< Receive sequence started */
sahilmgandhi 18:6a4db94011d3 961 __IO uint32_t EVENTS_TXSTARTED; /*!< Transmit sequence started */
sahilmgandhi 18:6a4db94011d3 962 __I uint32_t RESERVED6[2];
sahilmgandhi 18:6a4db94011d3 963 __IO uint32_t EVENTS_LASTRX; /*!< Byte boundary, starting to receive the last byte */
sahilmgandhi 18:6a4db94011d3 964 __IO uint32_t EVENTS_LASTTX; /*!< Byte boundary, starting to transmit the last byte */
sahilmgandhi 18:6a4db94011d3 965 __I uint32_t RESERVED7[39];
sahilmgandhi 18:6a4db94011d3 966 __IO uint32_t SHORTS; /*!< Shortcut register */
sahilmgandhi 18:6a4db94011d3 967 __I uint32_t RESERVED8[63];
sahilmgandhi 18:6a4db94011d3 968 __IO uint32_t INTEN; /*!< Enable or disable interrupt */
sahilmgandhi 18:6a4db94011d3 969 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 970 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 971 __I uint32_t RESERVED9[110];
sahilmgandhi 18:6a4db94011d3 972 __IO uint32_t ERRORSRC; /*!< Error source */
sahilmgandhi 18:6a4db94011d3 973 __I uint32_t RESERVED10[14];
sahilmgandhi 18:6a4db94011d3 974 __IO uint32_t ENABLE; /*!< Enable TWIM */
sahilmgandhi 18:6a4db94011d3 975 __I uint32_t RESERVED11;
sahilmgandhi 18:6a4db94011d3 976 TWIM_PSEL_Type PSEL; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 977 __I uint32_t RESERVED12[5];
sahilmgandhi 18:6a4db94011d3 978 __IO uint32_t FREQUENCY; /*!< TWI frequency */
sahilmgandhi 18:6a4db94011d3 979 __I uint32_t RESERVED13[3];
sahilmgandhi 18:6a4db94011d3 980 TWIM_RXD_Type RXD; /*!< RXD EasyDMA channel */
sahilmgandhi 18:6a4db94011d3 981 TWIM_TXD_Type TXD; /*!< TXD EasyDMA channel */
sahilmgandhi 18:6a4db94011d3 982 __I uint32_t RESERVED14[13];
sahilmgandhi 18:6a4db94011d3 983 __IO uint32_t ADDRESS; /*!< Address used in the TWI transfer */
sahilmgandhi 18:6a4db94011d3 984 } NRF_TWIM_Type;
sahilmgandhi 18:6a4db94011d3 985
sahilmgandhi 18:6a4db94011d3 986
sahilmgandhi 18:6a4db94011d3 987 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 988 /* ================ TWIS ================ */
sahilmgandhi 18:6a4db94011d3 989 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 990
sahilmgandhi 18:6a4db94011d3 991
sahilmgandhi 18:6a4db94011d3 992 /**
sahilmgandhi 18:6a4db94011d3 993 * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS)
sahilmgandhi 18:6a4db94011d3 994 */
sahilmgandhi 18:6a4db94011d3 995
sahilmgandhi 18:6a4db94011d3 996 typedef struct { /*!< TWIS Structure */
sahilmgandhi 18:6a4db94011d3 997 __I uint32_t RESERVED0[5];
sahilmgandhi 18:6a4db94011d3 998 __O uint32_t TASKS_STOP; /*!< Stop TWI transaction */
sahilmgandhi 18:6a4db94011d3 999 __I uint32_t RESERVED1;
sahilmgandhi 18:6a4db94011d3 1000 __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */
sahilmgandhi 18:6a4db94011d3 1001 __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */
sahilmgandhi 18:6a4db94011d3 1002 __I uint32_t RESERVED2[3];
sahilmgandhi 18:6a4db94011d3 1003 __O uint32_t TASKS_PREPARERX; /*!< Prepare the TWI slave to respond to a write command */
sahilmgandhi 18:6a4db94011d3 1004 __O uint32_t TASKS_PREPARETX; /*!< Prepare the TWI slave to respond to a read command */
sahilmgandhi 18:6a4db94011d3 1005 __I uint32_t RESERVED3[51];
sahilmgandhi 18:6a4db94011d3 1006 __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */
sahilmgandhi 18:6a4db94011d3 1007 __I uint32_t RESERVED4[7];
sahilmgandhi 18:6a4db94011d3 1008 __IO uint32_t EVENTS_ERROR; /*!< TWI error */
sahilmgandhi 18:6a4db94011d3 1009 __I uint32_t RESERVED5[9];
sahilmgandhi 18:6a4db94011d3 1010 __IO uint32_t EVENTS_RXSTARTED; /*!< Receive sequence started */
sahilmgandhi 18:6a4db94011d3 1011 __IO uint32_t EVENTS_TXSTARTED; /*!< Transmit sequence started */
sahilmgandhi 18:6a4db94011d3 1012 __I uint32_t RESERVED6[4];
sahilmgandhi 18:6a4db94011d3 1013 __IO uint32_t EVENTS_WRITE; /*!< Write command received */
sahilmgandhi 18:6a4db94011d3 1014 __IO uint32_t EVENTS_READ; /*!< Read command received */
sahilmgandhi 18:6a4db94011d3 1015 __I uint32_t RESERVED7[37];
sahilmgandhi 18:6a4db94011d3 1016 __IO uint32_t SHORTS; /*!< Shortcut register */
sahilmgandhi 18:6a4db94011d3 1017 __I uint32_t RESERVED8[63];
sahilmgandhi 18:6a4db94011d3 1018 __IO uint32_t INTEN; /*!< Enable or disable interrupt */
sahilmgandhi 18:6a4db94011d3 1019 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 1020 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 1021 __I uint32_t RESERVED9[113];
sahilmgandhi 18:6a4db94011d3 1022 __IO uint32_t ERRORSRC; /*!< Error source */
sahilmgandhi 18:6a4db94011d3 1023 __I uint32_t MATCH; /*!< Status register indicating which address had a match */
sahilmgandhi 18:6a4db94011d3 1024 __I uint32_t RESERVED10[10];
sahilmgandhi 18:6a4db94011d3 1025 __IO uint32_t ENABLE; /*!< Enable TWIS */
sahilmgandhi 18:6a4db94011d3 1026 __I uint32_t RESERVED11;
sahilmgandhi 18:6a4db94011d3 1027 TWIS_PSEL_Type PSEL; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 1028 __I uint32_t RESERVED12[9];
sahilmgandhi 18:6a4db94011d3 1029 TWIS_RXD_Type RXD; /*!< RXD EasyDMA channel */
sahilmgandhi 18:6a4db94011d3 1030 __I uint32_t RESERVED13;
sahilmgandhi 18:6a4db94011d3 1031 TWIS_TXD_Type TXD; /*!< TXD EasyDMA channel */
sahilmgandhi 18:6a4db94011d3 1032 __I uint32_t RESERVED14[14];
sahilmgandhi 18:6a4db94011d3 1033 __IO uint32_t ADDRESS[2]; /*!< Description collection[0]: TWI slave address 0 */
sahilmgandhi 18:6a4db94011d3 1034 __I uint32_t RESERVED15;
sahilmgandhi 18:6a4db94011d3 1035 __IO uint32_t CONFIG; /*!< Configuration register for the address match mechanism */
sahilmgandhi 18:6a4db94011d3 1036 __I uint32_t RESERVED16[10];
sahilmgandhi 18:6a4db94011d3 1037 __IO uint32_t ORC; /*!< Over-read character. Character sent out in case of an over-read
sahilmgandhi 18:6a4db94011d3 1038 of the transmit buffer. */
sahilmgandhi 18:6a4db94011d3 1039 } NRF_TWIS_Type;
sahilmgandhi 18:6a4db94011d3 1040
sahilmgandhi 18:6a4db94011d3 1041
sahilmgandhi 18:6a4db94011d3 1042 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1043 /* ================ SPI ================ */
sahilmgandhi 18:6a4db94011d3 1044 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1045
sahilmgandhi 18:6a4db94011d3 1046
sahilmgandhi 18:6a4db94011d3 1047 /**
sahilmgandhi 18:6a4db94011d3 1048 * @brief Serial Peripheral Interface 0 (SPI)
sahilmgandhi 18:6a4db94011d3 1049 */
sahilmgandhi 18:6a4db94011d3 1050
sahilmgandhi 18:6a4db94011d3 1051 typedef struct { /*!< SPI Structure */
sahilmgandhi 18:6a4db94011d3 1052 __I uint32_t RESERVED0[66];
sahilmgandhi 18:6a4db94011d3 1053 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received */
sahilmgandhi 18:6a4db94011d3 1054 __I uint32_t RESERVED1[126];
sahilmgandhi 18:6a4db94011d3 1055 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 1056 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 1057 __I uint32_t RESERVED2[125];
sahilmgandhi 18:6a4db94011d3 1058 __IO uint32_t ENABLE; /*!< Enable SPI */
sahilmgandhi 18:6a4db94011d3 1059 __I uint32_t RESERVED3;
sahilmgandhi 18:6a4db94011d3 1060 SPI_PSEL_Type PSEL; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 1061 __I uint32_t RESERVED4;
sahilmgandhi 18:6a4db94011d3 1062 __I uint32_t RXD; /*!< RXD register */
sahilmgandhi 18:6a4db94011d3 1063 __IO uint32_t TXD; /*!< TXD register */
sahilmgandhi 18:6a4db94011d3 1064 __I uint32_t RESERVED5;
sahilmgandhi 18:6a4db94011d3 1065 __IO uint32_t FREQUENCY; /*!< SPI frequency */
sahilmgandhi 18:6a4db94011d3 1066 __I uint32_t RESERVED6[11];
sahilmgandhi 18:6a4db94011d3 1067 __IO uint32_t CONFIG; /*!< Configuration register */
sahilmgandhi 18:6a4db94011d3 1068 } NRF_SPI_Type;
sahilmgandhi 18:6a4db94011d3 1069
sahilmgandhi 18:6a4db94011d3 1070
sahilmgandhi 18:6a4db94011d3 1071 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1072 /* ================ TWI ================ */
sahilmgandhi 18:6a4db94011d3 1073 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1074
sahilmgandhi 18:6a4db94011d3 1075
sahilmgandhi 18:6a4db94011d3 1076 /**
sahilmgandhi 18:6a4db94011d3 1077 * @brief I2C compatible Two-Wire Interface 0 (TWI)
sahilmgandhi 18:6a4db94011d3 1078 */
sahilmgandhi 18:6a4db94011d3 1079
sahilmgandhi 18:6a4db94011d3 1080 typedef struct { /*!< TWI Structure */
sahilmgandhi 18:6a4db94011d3 1081 __O uint32_t TASKS_STARTRX; /*!< Start TWI receive sequence */
sahilmgandhi 18:6a4db94011d3 1082 __I uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 1083 __O uint32_t TASKS_STARTTX; /*!< Start TWI transmit sequence */
sahilmgandhi 18:6a4db94011d3 1084 __I uint32_t RESERVED1[2];
sahilmgandhi 18:6a4db94011d3 1085 __O uint32_t TASKS_STOP; /*!< Stop TWI transaction */
sahilmgandhi 18:6a4db94011d3 1086 __I uint32_t RESERVED2;
sahilmgandhi 18:6a4db94011d3 1087 __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */
sahilmgandhi 18:6a4db94011d3 1088 __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */
sahilmgandhi 18:6a4db94011d3 1089 __I uint32_t RESERVED3[56];
sahilmgandhi 18:6a4db94011d3 1090 __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */
sahilmgandhi 18:6a4db94011d3 1091 __IO uint32_t EVENTS_RXDREADY; /*!< TWI RXD byte received */
sahilmgandhi 18:6a4db94011d3 1092 __I uint32_t RESERVED4[4];
sahilmgandhi 18:6a4db94011d3 1093 __IO uint32_t EVENTS_TXDSENT; /*!< TWI TXD byte sent */
sahilmgandhi 18:6a4db94011d3 1094 __I uint32_t RESERVED5;
sahilmgandhi 18:6a4db94011d3 1095 __IO uint32_t EVENTS_ERROR; /*!< TWI error */
sahilmgandhi 18:6a4db94011d3 1096 __I uint32_t RESERVED6[4];
sahilmgandhi 18:6a4db94011d3 1097 __IO uint32_t EVENTS_BB; /*!< TWI byte boundary, generated before each byte that is sent or
sahilmgandhi 18:6a4db94011d3 1098 received */
sahilmgandhi 18:6a4db94011d3 1099 __I uint32_t RESERVED7[3];
sahilmgandhi 18:6a4db94011d3 1100 __IO uint32_t EVENTS_SUSPENDED; /*!< TWI entered the suspended state */
sahilmgandhi 18:6a4db94011d3 1101 __I uint32_t RESERVED8[45];
sahilmgandhi 18:6a4db94011d3 1102 __IO uint32_t SHORTS; /*!< Shortcut register */
sahilmgandhi 18:6a4db94011d3 1103 __I uint32_t RESERVED9[64];
sahilmgandhi 18:6a4db94011d3 1104 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 1105 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 1106 __I uint32_t RESERVED10[110];
sahilmgandhi 18:6a4db94011d3 1107 __IO uint32_t ERRORSRC; /*!< Error source */
sahilmgandhi 18:6a4db94011d3 1108 __I uint32_t RESERVED11[14];
sahilmgandhi 18:6a4db94011d3 1109 __IO uint32_t ENABLE; /*!< Enable TWI */
sahilmgandhi 18:6a4db94011d3 1110 __I uint32_t RESERVED12;
sahilmgandhi 18:6a4db94011d3 1111 __IO uint32_t PSELSCL; /*!< Pin select for SCL */
sahilmgandhi 18:6a4db94011d3 1112 __IO uint32_t PSELSDA; /*!< Pin select for SDA */
sahilmgandhi 18:6a4db94011d3 1113 __I uint32_t RESERVED13[2];
sahilmgandhi 18:6a4db94011d3 1114 __I uint32_t RXD; /*!< RXD register */
sahilmgandhi 18:6a4db94011d3 1115 __IO uint32_t TXD; /*!< TXD register */
sahilmgandhi 18:6a4db94011d3 1116 __I uint32_t RESERVED14;
sahilmgandhi 18:6a4db94011d3 1117 __IO uint32_t FREQUENCY; /*!< TWI frequency */
sahilmgandhi 18:6a4db94011d3 1118 __I uint32_t RESERVED15[24];
sahilmgandhi 18:6a4db94011d3 1119 __IO uint32_t ADDRESS; /*!< Address used in the TWI transfer */
sahilmgandhi 18:6a4db94011d3 1120 } NRF_TWI_Type;
sahilmgandhi 18:6a4db94011d3 1121
sahilmgandhi 18:6a4db94011d3 1122
sahilmgandhi 18:6a4db94011d3 1123 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1124 /* ================ NFCT ================ */
sahilmgandhi 18:6a4db94011d3 1125 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1126
sahilmgandhi 18:6a4db94011d3 1127
sahilmgandhi 18:6a4db94011d3 1128 /**
sahilmgandhi 18:6a4db94011d3 1129 * @brief NFC-A compatible radio (NFCT)
sahilmgandhi 18:6a4db94011d3 1130 */
sahilmgandhi 18:6a4db94011d3 1131
sahilmgandhi 18:6a4db94011d3 1132 typedef struct { /*!< NFCT Structure */
sahilmgandhi 18:6a4db94011d3 1133 __O uint32_t TASKS_ACTIVATE; /*!< Activate NFC peripheral for incoming and outgoing frames, change
sahilmgandhi 18:6a4db94011d3 1134 state to activated */
sahilmgandhi 18:6a4db94011d3 1135 __O uint32_t TASKS_DISABLE; /*!< Disable NFC peripheral */
sahilmgandhi 18:6a4db94011d3 1136 __O uint32_t TASKS_SENSE; /*!< Enable NFC sense field mode, change state to sense mode */
sahilmgandhi 18:6a4db94011d3 1137 __O uint32_t TASKS_STARTTX; /*!< Start transmission of a outgoing frame, change state to transmit */
sahilmgandhi 18:6a4db94011d3 1138 __I uint32_t RESERVED0[3];
sahilmgandhi 18:6a4db94011d3 1139 __O uint32_t TASKS_ENABLERXDATA; /*!< Initializes the EasyDMA for receive. */
sahilmgandhi 18:6a4db94011d3 1140 __I uint32_t RESERVED1;
sahilmgandhi 18:6a4db94011d3 1141 __O uint32_t TASKS_GOIDLE; /*!< Force state machine to IDLE state */
sahilmgandhi 18:6a4db94011d3 1142 __O uint32_t TASKS_GOSLEEP; /*!< Force state machine to SLEEP_A state */
sahilmgandhi 18:6a4db94011d3 1143 __I uint32_t RESERVED2[53];
sahilmgandhi 18:6a4db94011d3 1144 __IO uint32_t EVENTS_READY; /*!< The NFC peripheral is ready to receive and send frames */
sahilmgandhi 18:6a4db94011d3 1145 __IO uint32_t EVENTS_FIELDDETECTED; /*!< Remote NFC field detected */
sahilmgandhi 18:6a4db94011d3 1146 __IO uint32_t EVENTS_FIELDLOST; /*!< Remote NFC field lost */
sahilmgandhi 18:6a4db94011d3 1147 __IO uint32_t EVENTS_TXFRAMESTART; /*!< Marks the start of the first symbol of a transmitted frame */
sahilmgandhi 18:6a4db94011d3 1148 __IO uint32_t EVENTS_TXFRAMEEND; /*!< Marks the end of the last transmitted on-air symbol of a frame */
sahilmgandhi 18:6a4db94011d3 1149 __IO uint32_t EVENTS_RXFRAMESTART; /*!< Marks the end of the first symbol of a received frame */
sahilmgandhi 18:6a4db94011d3 1150 __IO uint32_t EVENTS_RXFRAMEEND; /*!< Received data have been checked (CRC, parity) and transferred
sahilmgandhi 18:6a4db94011d3 1151 to RAM, and EasyDMA has ended accessing the RX buffer */
sahilmgandhi 18:6a4db94011d3 1152 __IO uint32_t EVENTS_ERROR; /*!< NFC error reported. The ERRORSTATUS register contains details
sahilmgandhi 18:6a4db94011d3 1153 on the source of the error. */
sahilmgandhi 18:6a4db94011d3 1154 __I uint32_t RESERVED3[2];
sahilmgandhi 18:6a4db94011d3 1155 __IO uint32_t EVENTS_RXERROR; /*!< NFC RX frame error reported. The FRAMESTATUS.RX register contains
sahilmgandhi 18:6a4db94011d3 1156 details on the source of the error. */
sahilmgandhi 18:6a4db94011d3 1157 __IO uint32_t EVENTS_ENDRX; /*!< RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */
sahilmgandhi 18:6a4db94011d3 1158 __IO uint32_t EVENTS_ENDTX; /*!< Transmission of data in RAM has ended, and EasyDMA has ended
sahilmgandhi 18:6a4db94011d3 1159 accessing the TX buffer */
sahilmgandhi 18:6a4db94011d3 1160 __I uint32_t RESERVED4;
sahilmgandhi 18:6a4db94011d3 1161 __IO uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< Auto collision resolution process has started */
sahilmgandhi 18:6a4db94011d3 1162 __I uint32_t RESERVED5[3];
sahilmgandhi 18:6a4db94011d3 1163 __IO uint32_t EVENTS_COLLISION; /*!< NFC Auto collision resolution error reported. */
sahilmgandhi 18:6a4db94011d3 1164 __IO uint32_t EVENTS_SELECTED; /*!< NFC Auto collision resolution successfully completed */
sahilmgandhi 18:6a4db94011d3 1165 __IO uint32_t EVENTS_STARTED; /*!< EasyDMA is ready to receive or send frames. */
sahilmgandhi 18:6a4db94011d3 1166 __I uint32_t RESERVED6[43];
sahilmgandhi 18:6a4db94011d3 1167 __IO uint32_t SHORTS; /*!< Shortcut register */
sahilmgandhi 18:6a4db94011d3 1168 __I uint32_t RESERVED7[63];
sahilmgandhi 18:6a4db94011d3 1169 __IO uint32_t INTEN; /*!< Enable or disable interrupt */
sahilmgandhi 18:6a4db94011d3 1170 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 1171 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 1172 __I uint32_t RESERVED8[62];
sahilmgandhi 18:6a4db94011d3 1173 __IO uint32_t ERRORSTATUS; /*!< NFC Error Status register */
sahilmgandhi 18:6a4db94011d3 1174 __I uint32_t RESERVED9;
sahilmgandhi 18:6a4db94011d3 1175 NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 1176 __I uint32_t RESERVED10[8];
sahilmgandhi 18:6a4db94011d3 1177 __I uint32_t CURRENTLOADCTRL; /*!< Current value driven to the NFC Load Control */
sahilmgandhi 18:6a4db94011d3 1178 __I uint32_t RESERVED11[2];
sahilmgandhi 18:6a4db94011d3 1179 __I uint32_t FIELDPRESENT; /*!< Indicates the presence or not of a valid field */
sahilmgandhi 18:6a4db94011d3 1180 __I uint32_t RESERVED12[49];
sahilmgandhi 18:6a4db94011d3 1181 __IO uint32_t FRAMEDELAYMIN; /*!< Minimum frame delay */
sahilmgandhi 18:6a4db94011d3 1182 __IO uint32_t FRAMEDELAYMAX; /*!< Maximum frame delay */
sahilmgandhi 18:6a4db94011d3 1183 __IO uint32_t FRAMEDELAYMODE; /*!< Configuration register for the Frame Delay Timer */
sahilmgandhi 18:6a4db94011d3 1184 __IO uint32_t PACKETPTR; /*!< Packet pointer for TXD and RXD data storage in Data RAM */
sahilmgandhi 18:6a4db94011d3 1185 __IO uint32_t MAXLEN; /*!< Size of allocated for TXD and RXD data storage buffer in Data
sahilmgandhi 18:6a4db94011d3 1186 RAM */
sahilmgandhi 18:6a4db94011d3 1187 NFCT_TXD_Type TXD; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 1188 NFCT_RXD_Type RXD; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 1189 __I uint32_t RESERVED13[26];
sahilmgandhi 18:6a4db94011d3 1190 __IO uint32_t NFCID1_LAST; /*!< Last NFCID1 part (4, 7 or 10 bytes ID) */
sahilmgandhi 18:6a4db94011d3 1191 __IO uint32_t NFCID1_2ND_LAST; /*!< Second last NFCID1 part (7 or 10 bytes ID) */
sahilmgandhi 18:6a4db94011d3 1192 __IO uint32_t NFCID1_3RD_LAST; /*!< Third last NFCID1 part (10 bytes ID) */
sahilmgandhi 18:6a4db94011d3 1193 __I uint32_t RESERVED14;
sahilmgandhi 18:6a4db94011d3 1194 __IO uint32_t SENSRES; /*!< NFC-A SENS_RES auto-response settings */
sahilmgandhi 18:6a4db94011d3 1195 __IO uint32_t SELRES; /*!< NFC-A SEL_RES auto-response settings */
sahilmgandhi 18:6a4db94011d3 1196 } NRF_NFCT_Type;
sahilmgandhi 18:6a4db94011d3 1197
sahilmgandhi 18:6a4db94011d3 1198
sahilmgandhi 18:6a4db94011d3 1199 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1200 /* ================ GPIOTE ================ */
sahilmgandhi 18:6a4db94011d3 1201 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1202
sahilmgandhi 18:6a4db94011d3 1203
sahilmgandhi 18:6a4db94011d3 1204 /**
sahilmgandhi 18:6a4db94011d3 1205 * @brief GPIO Tasks and Events (GPIOTE)
sahilmgandhi 18:6a4db94011d3 1206 */
sahilmgandhi 18:6a4db94011d3 1207
sahilmgandhi 18:6a4db94011d3 1208 typedef struct { /*!< GPIOTE Structure */
sahilmgandhi 18:6a4db94011d3 1209 __O uint32_t TASKS_OUT[8]; /*!< Description collection[0]: Task for writing to pin specified
sahilmgandhi 18:6a4db94011d3 1210 in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. */
sahilmgandhi 18:6a4db94011d3 1211 __I uint32_t RESERVED0[4];
sahilmgandhi 18:6a4db94011d3 1212 __O uint32_t TASKS_SET[8]; /*!< Description collection[0]: Task for writing to pin specified
sahilmgandhi 18:6a4db94011d3 1213 in CONFIG[0].PSEL. Action on pin is to set it high. */
sahilmgandhi 18:6a4db94011d3 1214 __I uint32_t RESERVED1[4];
sahilmgandhi 18:6a4db94011d3 1215 __O uint32_t TASKS_CLR[8]; /*!< Description collection[0]: Task for writing to pin specified
sahilmgandhi 18:6a4db94011d3 1216 in CONFIG[0].PSEL. Action on pin is to set it low. */
sahilmgandhi 18:6a4db94011d3 1217 __I uint32_t RESERVED2[32];
sahilmgandhi 18:6a4db94011d3 1218 __IO uint32_t EVENTS_IN[8]; /*!< Description collection[0]: Event generated from pin specified
sahilmgandhi 18:6a4db94011d3 1219 in CONFIG[0].PSEL */
sahilmgandhi 18:6a4db94011d3 1220 __I uint32_t RESERVED3[23];
sahilmgandhi 18:6a4db94011d3 1221 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple input GPIO pins with SENSE mechanism
sahilmgandhi 18:6a4db94011d3 1222 enabled */
sahilmgandhi 18:6a4db94011d3 1223 __I uint32_t RESERVED4[97];
sahilmgandhi 18:6a4db94011d3 1224 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 1225 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 1226 __I uint32_t RESERVED5[129];
sahilmgandhi 18:6a4db94011d3 1227 __IO uint32_t CONFIG[8]; /*!< Description collection[0]: Configuration for OUT[n], SET[n]
sahilmgandhi 18:6a4db94011d3 1228 and CLR[n] tasks and IN[n] event */
sahilmgandhi 18:6a4db94011d3 1229 } NRF_GPIOTE_Type;
sahilmgandhi 18:6a4db94011d3 1230
sahilmgandhi 18:6a4db94011d3 1231
sahilmgandhi 18:6a4db94011d3 1232 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1233 /* ================ SAADC ================ */
sahilmgandhi 18:6a4db94011d3 1234 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1235
sahilmgandhi 18:6a4db94011d3 1236
sahilmgandhi 18:6a4db94011d3 1237 /**
sahilmgandhi 18:6a4db94011d3 1238 * @brief Analog to Digital Converter (SAADC)
sahilmgandhi 18:6a4db94011d3 1239 */
sahilmgandhi 18:6a4db94011d3 1240
sahilmgandhi 18:6a4db94011d3 1241 typedef struct { /*!< SAADC Structure */
sahilmgandhi 18:6a4db94011d3 1242 __O uint32_t TASKS_START; /*!< Start the ADC and prepare the result buffer in RAM */
sahilmgandhi 18:6a4db94011d3 1243 __O uint32_t TASKS_SAMPLE; /*!< Take one ADC sample, if scan is enabled all channels are sampled */
sahilmgandhi 18:6a4db94011d3 1244 __O uint32_t TASKS_STOP; /*!< Stop the ADC and terminate any on-going conversion */
sahilmgandhi 18:6a4db94011d3 1245 __O uint32_t TASKS_CALIBRATEOFFSET; /*!< Starts offset auto-calibration */
sahilmgandhi 18:6a4db94011d3 1246 __I uint32_t RESERVED0[60];
sahilmgandhi 18:6a4db94011d3 1247 __IO uint32_t EVENTS_STARTED; /*!< The ADC has started */
sahilmgandhi 18:6a4db94011d3 1248 __IO uint32_t EVENTS_END; /*!< The ADC has filled up the Result buffer */
sahilmgandhi 18:6a4db94011d3 1249 __IO uint32_t EVENTS_DONE; /*!< A conversion task has been completed. Depending on the mode,
sahilmgandhi 18:6a4db94011d3 1250 multiple conversions might be needed for a result to be transferred
sahilmgandhi 18:6a4db94011d3 1251 to RAM. */
sahilmgandhi 18:6a4db94011d3 1252 __IO uint32_t EVENTS_RESULTDONE; /*!< A result is ready to get transferred to RAM. */
sahilmgandhi 18:6a4db94011d3 1253 __IO uint32_t EVENTS_CALIBRATEDONE; /*!< Calibration is complete */
sahilmgandhi 18:6a4db94011d3 1254 __IO uint32_t EVENTS_STOPPED; /*!< The ADC has stopped */
sahilmgandhi 18:6a4db94011d3 1255 SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 1256 __I uint32_t RESERVED1[106];
sahilmgandhi 18:6a4db94011d3 1257 __IO uint32_t INTEN; /*!< Enable or disable interrupt */
sahilmgandhi 18:6a4db94011d3 1258 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 1259 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 1260 __I uint32_t RESERVED2[61];
sahilmgandhi 18:6a4db94011d3 1261 __I uint32_t STATUS; /*!< Status */
sahilmgandhi 18:6a4db94011d3 1262 __I uint32_t RESERVED3[63];
sahilmgandhi 18:6a4db94011d3 1263 __IO uint32_t ENABLE; /*!< Enable or disable ADC */
sahilmgandhi 18:6a4db94011d3 1264 __I uint32_t RESERVED4[3];
sahilmgandhi 18:6a4db94011d3 1265 SAADC_CH_Type CH[8]; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 1266 __I uint32_t RESERVED5[24];
sahilmgandhi 18:6a4db94011d3 1267 __IO uint32_t RESOLUTION; /*!< Resolution configuration */
sahilmgandhi 18:6a4db94011d3 1268 __IO uint32_t OVERSAMPLE; /*!< Oversampling configuration. OVERSAMPLE should not be combined
sahilmgandhi 18:6a4db94011d3 1269 with SCAN. The RESOLUTION is applied before averaging, thus
sahilmgandhi 18:6a4db94011d3 1270 for high OVERSAMPLE a higher RESOLUTION should be used. */
sahilmgandhi 18:6a4db94011d3 1271 __IO uint32_t SAMPLERATE; /*!< Controls normal or continuous sample rate */
sahilmgandhi 18:6a4db94011d3 1272 __I uint32_t RESERVED6[12];
sahilmgandhi 18:6a4db94011d3 1273 SAADC_RESULT_Type RESULT; /*!< RESULT EasyDMA channel */
sahilmgandhi 18:6a4db94011d3 1274 } NRF_SAADC_Type;
sahilmgandhi 18:6a4db94011d3 1275
sahilmgandhi 18:6a4db94011d3 1276
sahilmgandhi 18:6a4db94011d3 1277 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1278 /* ================ TIMER ================ */
sahilmgandhi 18:6a4db94011d3 1279 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1280
sahilmgandhi 18:6a4db94011d3 1281
sahilmgandhi 18:6a4db94011d3 1282 /**
sahilmgandhi 18:6a4db94011d3 1283 * @brief Timer/Counter 0 (TIMER)
sahilmgandhi 18:6a4db94011d3 1284 */
sahilmgandhi 18:6a4db94011d3 1285
sahilmgandhi 18:6a4db94011d3 1286 typedef struct { /*!< TIMER Structure */
sahilmgandhi 18:6a4db94011d3 1287 __O uint32_t TASKS_START; /*!< Start Timer */
sahilmgandhi 18:6a4db94011d3 1288 __O uint32_t TASKS_STOP; /*!< Stop Timer */
sahilmgandhi 18:6a4db94011d3 1289 __O uint32_t TASKS_COUNT; /*!< Increment Timer (Counter mode only) */
sahilmgandhi 18:6a4db94011d3 1290 __O uint32_t TASKS_CLEAR; /*!< Clear time */
sahilmgandhi 18:6a4db94011d3 1291 __O uint32_t TASKS_SHUTDOWN; /*!< Deprecated register - Shut down timer */
sahilmgandhi 18:6a4db94011d3 1292 __I uint32_t RESERVED0[11];
sahilmgandhi 18:6a4db94011d3 1293 __O uint32_t TASKS_CAPTURE[6]; /*!< Description collection[0]: Capture Timer value to CC[0] register */
sahilmgandhi 18:6a4db94011d3 1294 __I uint32_t RESERVED1[58];
sahilmgandhi 18:6a4db94011d3 1295 __IO uint32_t EVENTS_COMPARE[6]; /*!< Description collection[0]: Compare event on CC[0] match */
sahilmgandhi 18:6a4db94011d3 1296 __I uint32_t RESERVED2[42];
sahilmgandhi 18:6a4db94011d3 1297 __IO uint32_t SHORTS; /*!< Shortcut register */
sahilmgandhi 18:6a4db94011d3 1298 __I uint32_t RESERVED3[64];
sahilmgandhi 18:6a4db94011d3 1299 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 1300 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 1301 __I uint32_t RESERVED4[126];
sahilmgandhi 18:6a4db94011d3 1302 __IO uint32_t MODE; /*!< Timer mode selection */
sahilmgandhi 18:6a4db94011d3 1303 __IO uint32_t BITMODE; /*!< Configure the number of bits used by the TIMER */
sahilmgandhi 18:6a4db94011d3 1304 __I uint32_t RESERVED5;
sahilmgandhi 18:6a4db94011d3 1305 __IO uint32_t PRESCALER; /*!< Timer prescaler register */
sahilmgandhi 18:6a4db94011d3 1306 __I uint32_t RESERVED6[11];
sahilmgandhi 18:6a4db94011d3 1307 __IO uint32_t CC[6]; /*!< Description collection[0]: Capture/Compare register 0 */
sahilmgandhi 18:6a4db94011d3 1308 } NRF_TIMER_Type;
sahilmgandhi 18:6a4db94011d3 1309
sahilmgandhi 18:6a4db94011d3 1310
sahilmgandhi 18:6a4db94011d3 1311 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1312 /* ================ RTC ================ */
sahilmgandhi 18:6a4db94011d3 1313 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1314
sahilmgandhi 18:6a4db94011d3 1315
sahilmgandhi 18:6a4db94011d3 1316 /**
sahilmgandhi 18:6a4db94011d3 1317 * @brief Real time counter 0 (RTC)
sahilmgandhi 18:6a4db94011d3 1318 */
sahilmgandhi 18:6a4db94011d3 1319
sahilmgandhi 18:6a4db94011d3 1320 typedef struct { /*!< RTC Structure */
sahilmgandhi 18:6a4db94011d3 1321 __O uint32_t TASKS_START; /*!< Start RTC COUNTER */
sahilmgandhi 18:6a4db94011d3 1322 __O uint32_t TASKS_STOP; /*!< Stop RTC COUNTER */
sahilmgandhi 18:6a4db94011d3 1323 __O uint32_t TASKS_CLEAR; /*!< Clear RTC COUNTER */
sahilmgandhi 18:6a4db94011d3 1324 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFF0 */
sahilmgandhi 18:6a4db94011d3 1325 __I uint32_t RESERVED0[60];
sahilmgandhi 18:6a4db94011d3 1326 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment */
sahilmgandhi 18:6a4db94011d3 1327 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow */
sahilmgandhi 18:6a4db94011d3 1328 __I uint32_t RESERVED1[14];
sahilmgandhi 18:6a4db94011d3 1329 __IO uint32_t EVENTS_COMPARE[4]; /*!< Description collection[0]: Compare event on CC[0] match */
sahilmgandhi 18:6a4db94011d3 1330 __I uint32_t RESERVED2[109];
sahilmgandhi 18:6a4db94011d3 1331 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 1332 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 1333 __I uint32_t RESERVED3[13];
sahilmgandhi 18:6a4db94011d3 1334 __IO uint32_t EVTEN; /*!< Enable or disable event routing */
sahilmgandhi 18:6a4db94011d3 1335 __IO uint32_t EVTENSET; /*!< Enable event routing */
sahilmgandhi 18:6a4db94011d3 1336 __IO uint32_t EVTENCLR; /*!< Disable event routing */
sahilmgandhi 18:6a4db94011d3 1337 __I uint32_t RESERVED4[110];
sahilmgandhi 18:6a4db94011d3 1338 __I uint32_t COUNTER; /*!< Current COUNTER value */
sahilmgandhi 18:6a4db94011d3 1339 __IO uint32_t PRESCALER; /*!< 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must
sahilmgandhi 18:6a4db94011d3 1340 be written when RTC is stopped */
sahilmgandhi 18:6a4db94011d3 1341 __I uint32_t RESERVED5[13];
sahilmgandhi 18:6a4db94011d3 1342 __IO uint32_t CC[4]; /*!< Description collection[0]: Compare register 0 */
sahilmgandhi 18:6a4db94011d3 1343 } NRF_RTC_Type;
sahilmgandhi 18:6a4db94011d3 1344
sahilmgandhi 18:6a4db94011d3 1345
sahilmgandhi 18:6a4db94011d3 1346 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1347 /* ================ TEMP ================ */
sahilmgandhi 18:6a4db94011d3 1348 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1349
sahilmgandhi 18:6a4db94011d3 1350
sahilmgandhi 18:6a4db94011d3 1351 /**
sahilmgandhi 18:6a4db94011d3 1352 * @brief Temperature Sensor (TEMP)
sahilmgandhi 18:6a4db94011d3 1353 */
sahilmgandhi 18:6a4db94011d3 1354
sahilmgandhi 18:6a4db94011d3 1355 typedef struct { /*!< TEMP Structure */
sahilmgandhi 18:6a4db94011d3 1356 __O uint32_t TASKS_START; /*!< Start temperature measurement */
sahilmgandhi 18:6a4db94011d3 1357 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement */
sahilmgandhi 18:6a4db94011d3 1358 __I uint32_t RESERVED0[62];
sahilmgandhi 18:6a4db94011d3 1359 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready */
sahilmgandhi 18:6a4db94011d3 1360 __I uint32_t RESERVED1[128];
sahilmgandhi 18:6a4db94011d3 1361 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 1362 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 1363 __I uint32_t RESERVED2[127];
sahilmgandhi 18:6a4db94011d3 1364 __I int32_t TEMP; /*!< Temperature in degC (0.25deg steps) */
sahilmgandhi 18:6a4db94011d3 1365 __I uint32_t RESERVED3[5];
sahilmgandhi 18:6a4db94011d3 1366 __IO uint32_t A0; /*!< Slope of 1st piece wise linear function */
sahilmgandhi 18:6a4db94011d3 1367 __IO uint32_t A1; /*!< Slope of 2nd piece wise linear function */
sahilmgandhi 18:6a4db94011d3 1368 __IO uint32_t A2; /*!< Slope of 3rd piece wise linear function */
sahilmgandhi 18:6a4db94011d3 1369 __IO uint32_t A3; /*!< Slope of 4th piece wise linear function */
sahilmgandhi 18:6a4db94011d3 1370 __IO uint32_t A4; /*!< Slope of 5th piece wise linear function */
sahilmgandhi 18:6a4db94011d3 1371 __IO uint32_t A5; /*!< Slope of 6th piece wise linear function */
sahilmgandhi 18:6a4db94011d3 1372 __I uint32_t RESERVED4[2];
sahilmgandhi 18:6a4db94011d3 1373 __IO uint32_t B0; /*!< y-intercept of 1st piece wise linear function */
sahilmgandhi 18:6a4db94011d3 1374 __IO uint32_t B1; /*!< y-intercept of 2nd piece wise linear function */
sahilmgandhi 18:6a4db94011d3 1375 __IO uint32_t B2; /*!< y-intercept of 3rd piece wise linear function */
sahilmgandhi 18:6a4db94011d3 1376 __IO uint32_t B3; /*!< y-intercept of 4th piece wise linear function */
sahilmgandhi 18:6a4db94011d3 1377 __IO uint32_t B4; /*!< y-intercept of 5th piece wise linear function */
sahilmgandhi 18:6a4db94011d3 1378 __IO uint32_t B5; /*!< y-intercept of 6th piece wise linear function */
sahilmgandhi 18:6a4db94011d3 1379 __I uint32_t RESERVED5[2];
sahilmgandhi 18:6a4db94011d3 1380 __IO uint32_t T0; /*!< End point of 1st piece wise linear function */
sahilmgandhi 18:6a4db94011d3 1381 __IO uint32_t T1; /*!< End point of 2nd piece wise linear function */
sahilmgandhi 18:6a4db94011d3 1382 __IO uint32_t T2; /*!< End point of 3rd piece wise linear function */
sahilmgandhi 18:6a4db94011d3 1383 __IO uint32_t T3; /*!< End point of 4th piece wise linear function */
sahilmgandhi 18:6a4db94011d3 1384 __IO uint32_t T4; /*!< End point of 5th piece wise linear function */
sahilmgandhi 18:6a4db94011d3 1385 } NRF_TEMP_Type;
sahilmgandhi 18:6a4db94011d3 1386
sahilmgandhi 18:6a4db94011d3 1387
sahilmgandhi 18:6a4db94011d3 1388 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1389 /* ================ RNG ================ */
sahilmgandhi 18:6a4db94011d3 1390 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1391
sahilmgandhi 18:6a4db94011d3 1392
sahilmgandhi 18:6a4db94011d3 1393 /**
sahilmgandhi 18:6a4db94011d3 1394 * @brief Random Number Generator (RNG)
sahilmgandhi 18:6a4db94011d3 1395 */
sahilmgandhi 18:6a4db94011d3 1396
sahilmgandhi 18:6a4db94011d3 1397 typedef struct { /*!< RNG Structure */
sahilmgandhi 18:6a4db94011d3 1398 __O uint32_t TASKS_START; /*!< Task starting the random number generator */
sahilmgandhi 18:6a4db94011d3 1399 __O uint32_t TASKS_STOP; /*!< Task stopping the random number generator */
sahilmgandhi 18:6a4db94011d3 1400 __I uint32_t RESERVED0[62];
sahilmgandhi 18:6a4db94011d3 1401 __IO uint32_t EVENTS_VALRDY; /*!< Event being generated for every new random number written to
sahilmgandhi 18:6a4db94011d3 1402 the VALUE register */
sahilmgandhi 18:6a4db94011d3 1403 __I uint32_t RESERVED1[63];
sahilmgandhi 18:6a4db94011d3 1404 __IO uint32_t SHORTS; /*!< Shortcut register */
sahilmgandhi 18:6a4db94011d3 1405 __I uint32_t RESERVED2[64];
sahilmgandhi 18:6a4db94011d3 1406 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 1407 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 1408 __I uint32_t RESERVED3[126];
sahilmgandhi 18:6a4db94011d3 1409 __IO uint32_t CONFIG; /*!< Configuration register */
sahilmgandhi 18:6a4db94011d3 1410 __I uint32_t VALUE; /*!< Output random number */
sahilmgandhi 18:6a4db94011d3 1411 } NRF_RNG_Type;
sahilmgandhi 18:6a4db94011d3 1412
sahilmgandhi 18:6a4db94011d3 1413
sahilmgandhi 18:6a4db94011d3 1414 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1415 /* ================ ECB ================ */
sahilmgandhi 18:6a4db94011d3 1416 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1417
sahilmgandhi 18:6a4db94011d3 1418
sahilmgandhi 18:6a4db94011d3 1419 /**
sahilmgandhi 18:6a4db94011d3 1420 * @brief AES ECB Mode Encryption (ECB)
sahilmgandhi 18:6a4db94011d3 1421 */
sahilmgandhi 18:6a4db94011d3 1422
sahilmgandhi 18:6a4db94011d3 1423 typedef struct { /*!< ECB Structure */
sahilmgandhi 18:6a4db94011d3 1424 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt */
sahilmgandhi 18:6a4db94011d3 1425 __O uint32_t TASKS_STOPECB; /*!< Abort a possible executing ECB operation */
sahilmgandhi 18:6a4db94011d3 1426 __I uint32_t RESERVED0[62];
sahilmgandhi 18:6a4db94011d3 1427 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete */
sahilmgandhi 18:6a4db94011d3 1428 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted because of a STOPECB task or due to
sahilmgandhi 18:6a4db94011d3 1429 an error */
sahilmgandhi 18:6a4db94011d3 1430 __I uint32_t RESERVED1[127];
sahilmgandhi 18:6a4db94011d3 1431 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 1432 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 1433 __I uint32_t RESERVED2[126];
sahilmgandhi 18:6a4db94011d3 1434 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointers */
sahilmgandhi 18:6a4db94011d3 1435 } NRF_ECB_Type;
sahilmgandhi 18:6a4db94011d3 1436
sahilmgandhi 18:6a4db94011d3 1437
sahilmgandhi 18:6a4db94011d3 1438 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1439 /* ================ CCM ================ */
sahilmgandhi 18:6a4db94011d3 1440 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1441
sahilmgandhi 18:6a4db94011d3 1442
sahilmgandhi 18:6a4db94011d3 1443 /**
sahilmgandhi 18:6a4db94011d3 1444 * @brief AES CCM Mode Encryption (CCM)
sahilmgandhi 18:6a4db94011d3 1445 */
sahilmgandhi 18:6a4db94011d3 1446
sahilmgandhi 18:6a4db94011d3 1447 typedef struct { /*!< CCM Structure */
sahilmgandhi 18:6a4db94011d3 1448 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
sahilmgandhi 18:6a4db94011d3 1449 itself when completed. */
sahilmgandhi 18:6a4db94011d3 1450 __O uint32_t TASKS_CRYPT; /*!< Start encryption/decryption. This operation will stop by itself
sahilmgandhi 18:6a4db94011d3 1451 when completed. */
sahilmgandhi 18:6a4db94011d3 1452 __O uint32_t TASKS_STOP; /*!< Stop encryption/decryption */
sahilmgandhi 18:6a4db94011d3 1453 __I uint32_t RESERVED0[61];
sahilmgandhi 18:6a4db94011d3 1454 __IO uint32_t EVENTS_ENDKSGEN; /*!< Key-stream generation complete */
sahilmgandhi 18:6a4db94011d3 1455 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt complete */
sahilmgandhi 18:6a4db94011d3 1456 __IO uint32_t EVENTS_ERROR; /*!< CCM error event */
sahilmgandhi 18:6a4db94011d3 1457 __I uint32_t RESERVED1[61];
sahilmgandhi 18:6a4db94011d3 1458 __IO uint32_t SHORTS; /*!< Shortcut register */
sahilmgandhi 18:6a4db94011d3 1459 __I uint32_t RESERVED2[64];
sahilmgandhi 18:6a4db94011d3 1460 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 1461 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 1462 __I uint32_t RESERVED3[61];
sahilmgandhi 18:6a4db94011d3 1463 __I uint32_t MICSTATUS; /*!< MIC check result */
sahilmgandhi 18:6a4db94011d3 1464 __I uint32_t RESERVED4[63];
sahilmgandhi 18:6a4db94011d3 1465 __IO uint32_t ENABLE; /*!< Enable */
sahilmgandhi 18:6a4db94011d3 1466 __IO uint32_t MODE; /*!< Operation mode */
sahilmgandhi 18:6a4db94011d3 1467 __IO uint32_t CNFPTR; /*!< Pointer to data structure holding AES key and NONCE vector */
sahilmgandhi 18:6a4db94011d3 1468 __IO uint32_t INPTR; /*!< Input pointer */
sahilmgandhi 18:6a4db94011d3 1469 __IO uint32_t OUTPTR; /*!< Output pointer */
sahilmgandhi 18:6a4db94011d3 1470 __IO uint32_t SCRATCHPTR; /*!< Pointer to data area used for temporary storage */
sahilmgandhi 18:6a4db94011d3 1471 } NRF_CCM_Type;
sahilmgandhi 18:6a4db94011d3 1472
sahilmgandhi 18:6a4db94011d3 1473
sahilmgandhi 18:6a4db94011d3 1474 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1475 /* ================ AAR ================ */
sahilmgandhi 18:6a4db94011d3 1476 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1477
sahilmgandhi 18:6a4db94011d3 1478
sahilmgandhi 18:6a4db94011d3 1479 /**
sahilmgandhi 18:6a4db94011d3 1480 * @brief Accelerated Address Resolver (AAR)
sahilmgandhi 18:6a4db94011d3 1481 */
sahilmgandhi 18:6a4db94011d3 1482
sahilmgandhi 18:6a4db94011d3 1483 typedef struct { /*!< AAR Structure */
sahilmgandhi 18:6a4db94011d3 1484 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
sahilmgandhi 18:6a4db94011d3 1485 data structure */
sahilmgandhi 18:6a4db94011d3 1486 __I uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 1487 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses */
sahilmgandhi 18:6a4db94011d3 1488 __I uint32_t RESERVED1[61];
sahilmgandhi 18:6a4db94011d3 1489 __IO uint32_t EVENTS_END; /*!< Address resolution procedure complete */
sahilmgandhi 18:6a4db94011d3 1490 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved */
sahilmgandhi 18:6a4db94011d3 1491 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved */
sahilmgandhi 18:6a4db94011d3 1492 __I uint32_t RESERVED2[126];
sahilmgandhi 18:6a4db94011d3 1493 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 1494 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 1495 __I uint32_t RESERVED3[61];
sahilmgandhi 18:6a4db94011d3 1496 __I uint32_t STATUS; /*!< Resolution status */
sahilmgandhi 18:6a4db94011d3 1497 __I uint32_t RESERVED4[63];
sahilmgandhi 18:6a4db94011d3 1498 __IO uint32_t ENABLE; /*!< Enable AAR */
sahilmgandhi 18:6a4db94011d3 1499 __IO uint32_t NIRK; /*!< Number of IRKs */
sahilmgandhi 18:6a4db94011d3 1500 __IO uint32_t IRKPTR; /*!< Pointer to IRK data structure */
sahilmgandhi 18:6a4db94011d3 1501 __I uint32_t RESERVED5;
sahilmgandhi 18:6a4db94011d3 1502 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address */
sahilmgandhi 18:6a4db94011d3 1503 __IO uint32_t SCRATCHPTR; /*!< Pointer to data area used for temporary storage */
sahilmgandhi 18:6a4db94011d3 1504 } NRF_AAR_Type;
sahilmgandhi 18:6a4db94011d3 1505
sahilmgandhi 18:6a4db94011d3 1506
sahilmgandhi 18:6a4db94011d3 1507 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1508 /* ================ WDT ================ */
sahilmgandhi 18:6a4db94011d3 1509 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1510
sahilmgandhi 18:6a4db94011d3 1511
sahilmgandhi 18:6a4db94011d3 1512 /**
sahilmgandhi 18:6a4db94011d3 1513 * @brief Watchdog Timer (WDT)
sahilmgandhi 18:6a4db94011d3 1514 */
sahilmgandhi 18:6a4db94011d3 1515
sahilmgandhi 18:6a4db94011d3 1516 typedef struct { /*!< WDT Structure */
sahilmgandhi 18:6a4db94011d3 1517 __O uint32_t TASKS_START; /*!< Start the watchdog */
sahilmgandhi 18:6a4db94011d3 1518 __I uint32_t RESERVED0[63];
sahilmgandhi 18:6a4db94011d3 1519 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout */
sahilmgandhi 18:6a4db94011d3 1520 __I uint32_t RESERVED1[128];
sahilmgandhi 18:6a4db94011d3 1521 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 1522 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 1523 __I uint32_t RESERVED2[61];
sahilmgandhi 18:6a4db94011d3 1524 __I uint32_t RUNSTATUS; /*!< Run status */
sahilmgandhi 18:6a4db94011d3 1525 __I uint32_t REQSTATUS; /*!< Request status */
sahilmgandhi 18:6a4db94011d3 1526 __I uint32_t RESERVED3[63];
sahilmgandhi 18:6a4db94011d3 1527 __IO uint32_t CRV; /*!< Counter reload value */
sahilmgandhi 18:6a4db94011d3 1528 __IO uint32_t RREN; /*!< Enable register for reload request registers */
sahilmgandhi 18:6a4db94011d3 1529 __IO uint32_t CONFIG; /*!< Configuration register */
sahilmgandhi 18:6a4db94011d3 1530 __I uint32_t RESERVED4[60];
sahilmgandhi 18:6a4db94011d3 1531 __O uint32_t RR[8]; /*!< Description collection[0]: Reload request 0 */
sahilmgandhi 18:6a4db94011d3 1532 } NRF_WDT_Type;
sahilmgandhi 18:6a4db94011d3 1533
sahilmgandhi 18:6a4db94011d3 1534
sahilmgandhi 18:6a4db94011d3 1535 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1536 /* ================ QDEC ================ */
sahilmgandhi 18:6a4db94011d3 1537 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1538
sahilmgandhi 18:6a4db94011d3 1539
sahilmgandhi 18:6a4db94011d3 1540 /**
sahilmgandhi 18:6a4db94011d3 1541 * @brief Quadrature Decoder (QDEC)
sahilmgandhi 18:6a4db94011d3 1542 */
sahilmgandhi 18:6a4db94011d3 1543
sahilmgandhi 18:6a4db94011d3 1544 typedef struct { /*!< QDEC Structure */
sahilmgandhi 18:6a4db94011d3 1545 __O uint32_t TASKS_START; /*!< Task starting the quadrature decoder */
sahilmgandhi 18:6a4db94011d3 1546 __O uint32_t TASKS_STOP; /*!< Task stopping the quadrature decoder */
sahilmgandhi 18:6a4db94011d3 1547 __O uint32_t TASKS_READCLRACC; /*!< Read and clear ACC and ACCDBL */
sahilmgandhi 18:6a4db94011d3 1548 __O uint32_t TASKS_RDCLRACC; /*!< Read and clear ACC */
sahilmgandhi 18:6a4db94011d3 1549 __O uint32_t TASKS_RDCLRDBL; /*!< Read and clear ACCDBL */
sahilmgandhi 18:6a4db94011d3 1550 __I uint32_t RESERVED0[59];
sahilmgandhi 18:6a4db94011d3 1551 __IO uint32_t EVENTS_SAMPLERDY; /*!< Event being generated for every new sample value written to
sahilmgandhi 18:6a4db94011d3 1552 the SAMPLE register */
sahilmgandhi 18:6a4db94011d3 1553 __IO uint32_t EVENTS_REPORTRDY; /*!< Non-null report ready */
sahilmgandhi 18:6a4db94011d3 1554 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow */
sahilmgandhi 18:6a4db94011d3 1555 __IO uint32_t EVENTS_DBLRDY; /*!< Double displacement(s) detected */
sahilmgandhi 18:6a4db94011d3 1556 __IO uint32_t EVENTS_STOPPED; /*!< QDEC has been stopped */
sahilmgandhi 18:6a4db94011d3 1557 __I uint32_t RESERVED1[59];
sahilmgandhi 18:6a4db94011d3 1558 __IO uint32_t SHORTS; /*!< Shortcut register */
sahilmgandhi 18:6a4db94011d3 1559 __I uint32_t RESERVED2[64];
sahilmgandhi 18:6a4db94011d3 1560 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 1561 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 1562 __I uint32_t RESERVED3[125];
sahilmgandhi 18:6a4db94011d3 1563 __IO uint32_t ENABLE; /*!< Enable the quadrature decoder */
sahilmgandhi 18:6a4db94011d3 1564 __IO uint32_t LEDPOL; /*!< LED output pin polarity */
sahilmgandhi 18:6a4db94011d3 1565 __IO uint32_t SAMPLEPER; /*!< Sample period */
sahilmgandhi 18:6a4db94011d3 1566 __I int32_t SAMPLE; /*!< Motion sample value */
sahilmgandhi 18:6a4db94011d3 1567 __IO uint32_t REPORTPER; /*!< Number of samples to be taken before REPORTRDY and DBLRDY events
sahilmgandhi 18:6a4db94011d3 1568 can be generated */
sahilmgandhi 18:6a4db94011d3 1569 __I int32_t ACC; /*!< Register accumulating the valid transitions */
sahilmgandhi 18:6a4db94011d3 1570 __I int32_t ACCREAD; /*!< Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC
sahilmgandhi 18:6a4db94011d3 1571 task */
sahilmgandhi 18:6a4db94011d3 1572 QDEC_PSEL_Type PSEL; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 1573 __IO uint32_t DBFEN; /*!< Enable input debounce filters */
sahilmgandhi 18:6a4db94011d3 1574 __I uint32_t RESERVED4[5];
sahilmgandhi 18:6a4db94011d3 1575 __IO uint32_t LEDPRE; /*!< Time period the LED is switched ON prior to sampling */
sahilmgandhi 18:6a4db94011d3 1576 __I uint32_t ACCDBL; /*!< Register accumulating the number of detected double transitions */
sahilmgandhi 18:6a4db94011d3 1577 __I uint32_t ACCDBLREAD; /*!< Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL
sahilmgandhi 18:6a4db94011d3 1578 task */
sahilmgandhi 18:6a4db94011d3 1579 } NRF_QDEC_Type;
sahilmgandhi 18:6a4db94011d3 1580
sahilmgandhi 18:6a4db94011d3 1581
sahilmgandhi 18:6a4db94011d3 1582 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1583 /* ================ COMP ================ */
sahilmgandhi 18:6a4db94011d3 1584 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1585
sahilmgandhi 18:6a4db94011d3 1586
sahilmgandhi 18:6a4db94011d3 1587 /**
sahilmgandhi 18:6a4db94011d3 1588 * @brief Comparator (COMP)
sahilmgandhi 18:6a4db94011d3 1589 */
sahilmgandhi 18:6a4db94011d3 1590
sahilmgandhi 18:6a4db94011d3 1591 typedef struct { /*!< COMP Structure */
sahilmgandhi 18:6a4db94011d3 1592 __O uint32_t TASKS_START; /*!< Start comparator */
sahilmgandhi 18:6a4db94011d3 1593 __O uint32_t TASKS_STOP; /*!< Stop comparator */
sahilmgandhi 18:6a4db94011d3 1594 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value */
sahilmgandhi 18:6a4db94011d3 1595 __I uint32_t RESERVED0[61];
sahilmgandhi 18:6a4db94011d3 1596 __IO uint32_t EVENTS_READY; /*!< COMP is ready and output is valid */
sahilmgandhi 18:6a4db94011d3 1597 __IO uint32_t EVENTS_DOWN; /*!< Downward crossing */
sahilmgandhi 18:6a4db94011d3 1598 __IO uint32_t EVENTS_UP; /*!< Upward crossing */
sahilmgandhi 18:6a4db94011d3 1599 __IO uint32_t EVENTS_CROSS; /*!< Downward or upward crossing */
sahilmgandhi 18:6a4db94011d3 1600 __I uint32_t RESERVED1[60];
sahilmgandhi 18:6a4db94011d3 1601 __IO uint32_t SHORTS; /*!< Shortcut register */
sahilmgandhi 18:6a4db94011d3 1602 __I uint32_t RESERVED2[63];
sahilmgandhi 18:6a4db94011d3 1603 __IO uint32_t INTEN; /*!< Enable or disable interrupt */
sahilmgandhi 18:6a4db94011d3 1604 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 1605 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 1606 __I uint32_t RESERVED3[61];
sahilmgandhi 18:6a4db94011d3 1607 __I uint32_t RESULT; /*!< Compare result */
sahilmgandhi 18:6a4db94011d3 1608 __I uint32_t RESERVED4[63];
sahilmgandhi 18:6a4db94011d3 1609 __IO uint32_t ENABLE; /*!< COMP enable */
sahilmgandhi 18:6a4db94011d3 1610 __IO uint32_t PSEL; /*!< Pin select */
sahilmgandhi 18:6a4db94011d3 1611 __IO uint32_t REFSEL; /*!< Reference source select */
sahilmgandhi 18:6a4db94011d3 1612 __IO uint32_t EXTREFSEL; /*!< External reference select */
sahilmgandhi 18:6a4db94011d3 1613 __I uint32_t RESERVED5[8];
sahilmgandhi 18:6a4db94011d3 1614 __IO uint32_t TH; /*!< Threshold configuration for hysteresis unit */
sahilmgandhi 18:6a4db94011d3 1615 __IO uint32_t MODE; /*!< Mode configuration */
sahilmgandhi 18:6a4db94011d3 1616 __IO uint32_t HYST; /*!< Comparator hysteresis enable */
sahilmgandhi 18:6a4db94011d3 1617 __IO uint32_t ISOURCE; /*!< Current source select on analog input */
sahilmgandhi 18:6a4db94011d3 1618 } NRF_COMP_Type;
sahilmgandhi 18:6a4db94011d3 1619
sahilmgandhi 18:6a4db94011d3 1620
sahilmgandhi 18:6a4db94011d3 1621 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1622 /* ================ LPCOMP ================ */
sahilmgandhi 18:6a4db94011d3 1623 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1624
sahilmgandhi 18:6a4db94011d3 1625
sahilmgandhi 18:6a4db94011d3 1626 /**
sahilmgandhi 18:6a4db94011d3 1627 * @brief Low Power Comparator (LPCOMP)
sahilmgandhi 18:6a4db94011d3 1628 */
sahilmgandhi 18:6a4db94011d3 1629
sahilmgandhi 18:6a4db94011d3 1630 typedef struct { /*!< LPCOMP Structure */
sahilmgandhi 18:6a4db94011d3 1631 __O uint32_t TASKS_START; /*!< Start comparator */
sahilmgandhi 18:6a4db94011d3 1632 __O uint32_t TASKS_STOP; /*!< Stop comparator */
sahilmgandhi 18:6a4db94011d3 1633 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value */
sahilmgandhi 18:6a4db94011d3 1634 __I uint32_t RESERVED0[61];
sahilmgandhi 18:6a4db94011d3 1635 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid */
sahilmgandhi 18:6a4db94011d3 1636 __IO uint32_t EVENTS_DOWN; /*!< Downward crossing */
sahilmgandhi 18:6a4db94011d3 1637 __IO uint32_t EVENTS_UP; /*!< Upward crossing */
sahilmgandhi 18:6a4db94011d3 1638 __IO uint32_t EVENTS_CROSS; /*!< Downward or upward crossing */
sahilmgandhi 18:6a4db94011d3 1639 __I uint32_t RESERVED1[60];
sahilmgandhi 18:6a4db94011d3 1640 __IO uint32_t SHORTS; /*!< Shortcut register */
sahilmgandhi 18:6a4db94011d3 1641 __I uint32_t RESERVED2[64];
sahilmgandhi 18:6a4db94011d3 1642 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 1643 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 1644 __I uint32_t RESERVED3[61];
sahilmgandhi 18:6a4db94011d3 1645 __I uint32_t RESULT; /*!< Compare result */
sahilmgandhi 18:6a4db94011d3 1646 __I uint32_t RESERVED4[63];
sahilmgandhi 18:6a4db94011d3 1647 __IO uint32_t ENABLE; /*!< Enable LPCOMP */
sahilmgandhi 18:6a4db94011d3 1648 __IO uint32_t PSEL; /*!< Input pin select */
sahilmgandhi 18:6a4db94011d3 1649 __IO uint32_t REFSEL; /*!< Reference select */
sahilmgandhi 18:6a4db94011d3 1650 __IO uint32_t EXTREFSEL; /*!< External reference select */
sahilmgandhi 18:6a4db94011d3 1651 __I uint32_t RESERVED5[4];
sahilmgandhi 18:6a4db94011d3 1652 __IO uint32_t ANADETECT; /*!< Analog detect configuration */
sahilmgandhi 18:6a4db94011d3 1653 __I uint32_t RESERVED6[5];
sahilmgandhi 18:6a4db94011d3 1654 __IO uint32_t HYST; /*!< Comparator hysteresis enable */
sahilmgandhi 18:6a4db94011d3 1655 } NRF_LPCOMP_Type;
sahilmgandhi 18:6a4db94011d3 1656
sahilmgandhi 18:6a4db94011d3 1657
sahilmgandhi 18:6a4db94011d3 1658 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1659 /* ================ SWI ================ */
sahilmgandhi 18:6a4db94011d3 1660 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1661
sahilmgandhi 18:6a4db94011d3 1662
sahilmgandhi 18:6a4db94011d3 1663 /**
sahilmgandhi 18:6a4db94011d3 1664 * @brief Software interrupt 0 (SWI)
sahilmgandhi 18:6a4db94011d3 1665 */
sahilmgandhi 18:6a4db94011d3 1666
sahilmgandhi 18:6a4db94011d3 1667 typedef struct { /*!< SWI Structure */
sahilmgandhi 18:6a4db94011d3 1668 __I uint32_t UNUSED; /*!< Unused. */
sahilmgandhi 18:6a4db94011d3 1669 } NRF_SWI_Type;
sahilmgandhi 18:6a4db94011d3 1670
sahilmgandhi 18:6a4db94011d3 1671
sahilmgandhi 18:6a4db94011d3 1672 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1673 /* ================ EGU ================ */
sahilmgandhi 18:6a4db94011d3 1674 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1675
sahilmgandhi 18:6a4db94011d3 1676
sahilmgandhi 18:6a4db94011d3 1677 /**
sahilmgandhi 18:6a4db94011d3 1678 * @brief Event Generator Unit 0 (EGU)
sahilmgandhi 18:6a4db94011d3 1679 */
sahilmgandhi 18:6a4db94011d3 1680
sahilmgandhi 18:6a4db94011d3 1681 typedef struct { /*!< EGU Structure */
sahilmgandhi 18:6a4db94011d3 1682 __O uint32_t TASKS_TRIGGER[16]; /*!< Description collection[0]: Trigger 0 for triggering the corresponding
sahilmgandhi 18:6a4db94011d3 1683 TRIGGERED[0] event */
sahilmgandhi 18:6a4db94011d3 1684 __I uint32_t RESERVED0[48];
sahilmgandhi 18:6a4db94011d3 1685 __IO uint32_t EVENTS_TRIGGERED[16]; /*!< Description collection[0]: Event number 0 generated by triggering
sahilmgandhi 18:6a4db94011d3 1686 the corresponding TRIGGER[0] task */
sahilmgandhi 18:6a4db94011d3 1687 __I uint32_t RESERVED1[112];
sahilmgandhi 18:6a4db94011d3 1688 __IO uint32_t INTEN; /*!< Enable or disable interrupt */
sahilmgandhi 18:6a4db94011d3 1689 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 1690 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 1691 } NRF_EGU_Type;
sahilmgandhi 18:6a4db94011d3 1692
sahilmgandhi 18:6a4db94011d3 1693
sahilmgandhi 18:6a4db94011d3 1694 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1695 /* ================ PWM ================ */
sahilmgandhi 18:6a4db94011d3 1696 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1697
sahilmgandhi 18:6a4db94011d3 1698
sahilmgandhi 18:6a4db94011d3 1699 /**
sahilmgandhi 18:6a4db94011d3 1700 * @brief Pulse Width Modulation Unit 0 (PWM)
sahilmgandhi 18:6a4db94011d3 1701 */
sahilmgandhi 18:6a4db94011d3 1702
sahilmgandhi 18:6a4db94011d3 1703 typedef struct { /*!< PWM Structure */
sahilmgandhi 18:6a4db94011d3 1704 __I uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 1705 __O uint32_t TASKS_STOP; /*!< Stops PWM pulse generation on all channels at the end of current
sahilmgandhi 18:6a4db94011d3 1706 PWM period, and stops sequence playback */
sahilmgandhi 18:6a4db94011d3 1707 __O uint32_t TASKS_SEQSTART[2]; /*!< Description collection[0]: Loads the first PWM value on all
sahilmgandhi 18:6a4db94011d3 1708 enabled channels from sequence 0, and starts playing that sequence
sahilmgandhi 18:6a4db94011d3 1709 at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes
sahilmgandhi 18:6a4db94011d3 1710 PWM generation to start it was not running. */
sahilmgandhi 18:6a4db94011d3 1711 __O uint32_t TASKS_NEXTSTEP; /*!< Steps by one value in the current sequence on all enabled channels
sahilmgandhi 18:6a4db94011d3 1712 if DECODER.MODE=NextStep. Does not cause PWM generation to start
sahilmgandhi 18:6a4db94011d3 1713 it was not running. */
sahilmgandhi 18:6a4db94011d3 1714 __I uint32_t RESERVED1[60];
sahilmgandhi 18:6a4db94011d3 1715 __IO uint32_t EVENTS_STOPPED; /*!< Response to STOP task, emitted when PWM pulses are no longer
sahilmgandhi 18:6a4db94011d3 1716 generated */
sahilmgandhi 18:6a4db94011d3 1717 __IO uint32_t EVENTS_SEQSTARTED[2]; /*!< Description collection[0]: First PWM period started on sequence
sahilmgandhi 18:6a4db94011d3 1718 0 */
sahilmgandhi 18:6a4db94011d3 1719 __IO uint32_t EVENTS_SEQEND[2]; /*!< Description collection[0]: Emitted at end of every sequence
sahilmgandhi 18:6a4db94011d3 1720 0, when last value from RAM has been applied to wave counter */
sahilmgandhi 18:6a4db94011d3 1721 __IO uint32_t EVENTS_PWMPERIODEND; /*!< Emitted at the end of each PWM period */
sahilmgandhi 18:6a4db94011d3 1722 __IO uint32_t EVENTS_LOOPSDONE; /*!< Concatenated sequences have been played the amount of times
sahilmgandhi 18:6a4db94011d3 1723 defined in LOOP.CNT */
sahilmgandhi 18:6a4db94011d3 1724 __I uint32_t RESERVED2[56];
sahilmgandhi 18:6a4db94011d3 1725 __IO uint32_t SHORTS; /*!< Shortcut register */
sahilmgandhi 18:6a4db94011d3 1726 __I uint32_t RESERVED3[63];
sahilmgandhi 18:6a4db94011d3 1727 __IO uint32_t INTEN; /*!< Enable or disable interrupt */
sahilmgandhi 18:6a4db94011d3 1728 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 1729 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 1730 __I uint32_t RESERVED4[125];
sahilmgandhi 18:6a4db94011d3 1731 __IO uint32_t ENABLE; /*!< PWM module enable register */
sahilmgandhi 18:6a4db94011d3 1732 __IO uint32_t MODE; /*!< Selects operating mode of the wave counter */
sahilmgandhi 18:6a4db94011d3 1733 __IO uint32_t COUNTERTOP; /*!< Value up to which the pulse generator counter counts */
sahilmgandhi 18:6a4db94011d3 1734 __IO uint32_t PRESCALER; /*!< Configuration for PWM_CLK */
sahilmgandhi 18:6a4db94011d3 1735 __IO uint32_t DECODER; /*!< Configuration of the decoder */
sahilmgandhi 18:6a4db94011d3 1736 __IO uint32_t LOOP; /*!< Amount of playback of a loop */
sahilmgandhi 18:6a4db94011d3 1737 __I uint32_t RESERVED5[2];
sahilmgandhi 18:6a4db94011d3 1738 PWM_SEQ_Type SEQ[2]; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 1739 PWM_PSEL_Type PSEL; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 1740 } NRF_PWM_Type;
sahilmgandhi 18:6a4db94011d3 1741
sahilmgandhi 18:6a4db94011d3 1742
sahilmgandhi 18:6a4db94011d3 1743 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1744 /* ================ PDM ================ */
sahilmgandhi 18:6a4db94011d3 1745 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1746
sahilmgandhi 18:6a4db94011d3 1747
sahilmgandhi 18:6a4db94011d3 1748 /**
sahilmgandhi 18:6a4db94011d3 1749 * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM)
sahilmgandhi 18:6a4db94011d3 1750 */
sahilmgandhi 18:6a4db94011d3 1751
sahilmgandhi 18:6a4db94011d3 1752 typedef struct { /*!< PDM Structure */
sahilmgandhi 18:6a4db94011d3 1753 __O uint32_t TASKS_START; /*!< Starts continuous PDM transfer */
sahilmgandhi 18:6a4db94011d3 1754 __O uint32_t TASKS_STOP; /*!< Stops PDM transfer */
sahilmgandhi 18:6a4db94011d3 1755 __I uint32_t RESERVED0[62];
sahilmgandhi 18:6a4db94011d3 1756 __IO uint32_t EVENTS_STARTED; /*!< PDM transfer has started */
sahilmgandhi 18:6a4db94011d3 1757 __IO uint32_t EVENTS_STOPPED; /*!< PDM transfer has finished */
sahilmgandhi 18:6a4db94011d3 1758 __IO uint32_t EVENTS_END; /*!< The PDM has written the last sample specified by SAMPLE.MAXCNT
sahilmgandhi 18:6a4db94011d3 1759 (or the last sample after a STOP task has been received) to
sahilmgandhi 18:6a4db94011d3 1760 Data RAM */
sahilmgandhi 18:6a4db94011d3 1761 __I uint32_t RESERVED1[125];
sahilmgandhi 18:6a4db94011d3 1762 __IO uint32_t INTEN; /*!< Enable or disable interrupt */
sahilmgandhi 18:6a4db94011d3 1763 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 1764 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 1765 __I uint32_t RESERVED2[125];
sahilmgandhi 18:6a4db94011d3 1766 __IO uint32_t ENABLE; /*!< PDM module enable register */
sahilmgandhi 18:6a4db94011d3 1767 __IO uint32_t PDMCLKCTRL; /*!< PDM clock generator control */
sahilmgandhi 18:6a4db94011d3 1768 __IO uint32_t MODE; /*!< Defines the routing of the connected PDM microphones' signals */
sahilmgandhi 18:6a4db94011d3 1769 __I uint32_t RESERVED3[3];
sahilmgandhi 18:6a4db94011d3 1770 __IO uint32_t GAINL; /*!< Left output gain adjustment */
sahilmgandhi 18:6a4db94011d3 1771 __IO uint32_t GAINR; /*!< Right output gain adjustment */
sahilmgandhi 18:6a4db94011d3 1772 __I uint32_t RESERVED4[8];
sahilmgandhi 18:6a4db94011d3 1773 PDM_PSEL_Type PSEL; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 1774 __I uint32_t RESERVED5[6];
sahilmgandhi 18:6a4db94011d3 1775 PDM_SAMPLE_Type SAMPLE; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 1776 } NRF_PDM_Type;
sahilmgandhi 18:6a4db94011d3 1777
sahilmgandhi 18:6a4db94011d3 1778
sahilmgandhi 18:6a4db94011d3 1779 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1780 /* ================ NVMC ================ */
sahilmgandhi 18:6a4db94011d3 1781 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1782
sahilmgandhi 18:6a4db94011d3 1783
sahilmgandhi 18:6a4db94011d3 1784 /**
sahilmgandhi 18:6a4db94011d3 1785 * @brief Non Volatile Memory Controller (NVMC)
sahilmgandhi 18:6a4db94011d3 1786 */
sahilmgandhi 18:6a4db94011d3 1787
sahilmgandhi 18:6a4db94011d3 1788 typedef struct { /*!< NVMC Structure */
sahilmgandhi 18:6a4db94011d3 1789 __I uint32_t RESERVED0[256];
sahilmgandhi 18:6a4db94011d3 1790 __I uint32_t READY; /*!< Ready flag */
sahilmgandhi 18:6a4db94011d3 1791 __I uint32_t RESERVED1[64];
sahilmgandhi 18:6a4db94011d3 1792 __IO uint32_t CONFIG; /*!< Configuration register */
sahilmgandhi 18:6a4db94011d3 1793
sahilmgandhi 18:6a4db94011d3 1794 union {
sahilmgandhi 18:6a4db94011d3 1795 __IO uint32_t ERASEPCR1; /*!< Deprecated register - Register for erasing a page in Code area.
sahilmgandhi 18:6a4db94011d3 1796 Equivalent to ERASEPAGE. */
sahilmgandhi 18:6a4db94011d3 1797 __IO uint32_t ERASEPAGE; /*!< Register for erasing a page in Code area */
sahilmgandhi 18:6a4db94011d3 1798 };
sahilmgandhi 18:6a4db94011d3 1799 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory */
sahilmgandhi 18:6a4db94011d3 1800 __IO uint32_t ERASEPCR0; /*!< Deprecated register - Register for erasing a page in Code area.
sahilmgandhi 18:6a4db94011d3 1801 Equivalent to ERASEPAGE. */
sahilmgandhi 18:6a4db94011d3 1802 __IO uint32_t ERASEUICR; /*!< Register for erasing User Information Configuration Registers */
sahilmgandhi 18:6a4db94011d3 1803 __I uint32_t RESERVED2[10];
sahilmgandhi 18:6a4db94011d3 1804 __IO uint32_t ICACHECNF; /*!< I-Code cache configuration register. */
sahilmgandhi 18:6a4db94011d3 1805 __I uint32_t RESERVED3;
sahilmgandhi 18:6a4db94011d3 1806 __IO uint32_t IHIT; /*!< I-Code cache hit counter. */
sahilmgandhi 18:6a4db94011d3 1807 __IO uint32_t IMISS; /*!< I-Code cache miss counter. */
sahilmgandhi 18:6a4db94011d3 1808 } NRF_NVMC_Type;
sahilmgandhi 18:6a4db94011d3 1809
sahilmgandhi 18:6a4db94011d3 1810
sahilmgandhi 18:6a4db94011d3 1811 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1812 /* ================ PPI ================ */
sahilmgandhi 18:6a4db94011d3 1813 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1814
sahilmgandhi 18:6a4db94011d3 1815
sahilmgandhi 18:6a4db94011d3 1816 /**
sahilmgandhi 18:6a4db94011d3 1817 * @brief Programmable Peripheral Interconnect (PPI)
sahilmgandhi 18:6a4db94011d3 1818 */
sahilmgandhi 18:6a4db94011d3 1819
sahilmgandhi 18:6a4db94011d3 1820 typedef struct { /*!< PPI Structure */
sahilmgandhi 18:6a4db94011d3 1821 PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< Channel group tasks */
sahilmgandhi 18:6a4db94011d3 1822 __I uint32_t RESERVED0[308];
sahilmgandhi 18:6a4db94011d3 1823 __IO uint32_t CHEN; /*!< Channel enable register */
sahilmgandhi 18:6a4db94011d3 1824 __IO uint32_t CHENSET; /*!< Channel enable set register */
sahilmgandhi 18:6a4db94011d3 1825 __IO uint32_t CHENCLR; /*!< Channel enable clear register */
sahilmgandhi 18:6a4db94011d3 1826 __I uint32_t RESERVED1;
sahilmgandhi 18:6a4db94011d3 1827 PPI_CH_Type CH[20]; /*!< PPI Channel */
sahilmgandhi 18:6a4db94011d3 1828 __I uint32_t RESERVED2[148];
sahilmgandhi 18:6a4db94011d3 1829 __IO uint32_t CHG[6]; /*!< Description collection[0]: Channel group 0 */
sahilmgandhi 18:6a4db94011d3 1830 __I uint32_t RESERVED3[62];
sahilmgandhi 18:6a4db94011d3 1831 PPI_FORK_Type FORK[32]; /*!< Fork */
sahilmgandhi 18:6a4db94011d3 1832 } NRF_PPI_Type;
sahilmgandhi 18:6a4db94011d3 1833
sahilmgandhi 18:6a4db94011d3 1834
sahilmgandhi 18:6a4db94011d3 1835 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1836 /* ================ MWU ================ */
sahilmgandhi 18:6a4db94011d3 1837 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1838
sahilmgandhi 18:6a4db94011d3 1839
sahilmgandhi 18:6a4db94011d3 1840 /**
sahilmgandhi 18:6a4db94011d3 1841 * @brief Memory Watch Unit (MWU)
sahilmgandhi 18:6a4db94011d3 1842 */
sahilmgandhi 18:6a4db94011d3 1843
sahilmgandhi 18:6a4db94011d3 1844 typedef struct { /*!< MWU Structure */
sahilmgandhi 18:6a4db94011d3 1845 __I uint32_t RESERVED0[64];
sahilmgandhi 18:6a4db94011d3 1846 MWU_EVENTS_REGION_Type EVENTS_REGION[4]; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 1847 __I uint32_t RESERVED1[16];
sahilmgandhi 18:6a4db94011d3 1848 MWU_EVENTS_PREGION_Type EVENTS_PREGION[2]; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 1849 __I uint32_t RESERVED2[100];
sahilmgandhi 18:6a4db94011d3 1850 __IO uint32_t INTEN; /*!< Enable or disable interrupt */
sahilmgandhi 18:6a4db94011d3 1851 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 1852 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 1853 __I uint32_t RESERVED3[5];
sahilmgandhi 18:6a4db94011d3 1854 __IO uint32_t NMIEN; /*!< Enable or disable non-maskable interrupt */
sahilmgandhi 18:6a4db94011d3 1855 __IO uint32_t NMIENSET; /*!< Enable non-maskable interrupt */
sahilmgandhi 18:6a4db94011d3 1856 __IO uint32_t NMIENCLR; /*!< Disable non-maskable interrupt */
sahilmgandhi 18:6a4db94011d3 1857 __I uint32_t RESERVED4[53];
sahilmgandhi 18:6a4db94011d3 1858 MWU_PERREGION_Type PERREGION[2]; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 1859 __I uint32_t RESERVED5[64];
sahilmgandhi 18:6a4db94011d3 1860 __IO uint32_t REGIONEN; /*!< Enable/disable regions watch */
sahilmgandhi 18:6a4db94011d3 1861 __IO uint32_t REGIONENSET; /*!< Enable regions watch */
sahilmgandhi 18:6a4db94011d3 1862 __IO uint32_t REGIONENCLR; /*!< Disable regions watch */
sahilmgandhi 18:6a4db94011d3 1863 __I uint32_t RESERVED6[57];
sahilmgandhi 18:6a4db94011d3 1864 MWU_REGION_Type REGION[4]; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 1865 __I uint32_t RESERVED7[32];
sahilmgandhi 18:6a4db94011d3 1866 MWU_PREGION_Type PREGION[2]; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 1867 } NRF_MWU_Type;
sahilmgandhi 18:6a4db94011d3 1868
sahilmgandhi 18:6a4db94011d3 1869
sahilmgandhi 18:6a4db94011d3 1870 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1871 /* ================ I2S ================ */
sahilmgandhi 18:6a4db94011d3 1872 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1873
sahilmgandhi 18:6a4db94011d3 1874
sahilmgandhi 18:6a4db94011d3 1875 /**
sahilmgandhi 18:6a4db94011d3 1876 * @brief Inter-IC Sound (I2S)
sahilmgandhi 18:6a4db94011d3 1877 */
sahilmgandhi 18:6a4db94011d3 1878
sahilmgandhi 18:6a4db94011d3 1879 typedef struct { /*!< I2S Structure */
sahilmgandhi 18:6a4db94011d3 1880 __O uint32_t TASKS_START; /*!< Starts continuous I2S transfer. Also starts MCK generator when
sahilmgandhi 18:6a4db94011d3 1881 this is enabled. */
sahilmgandhi 18:6a4db94011d3 1882 __O uint32_t TASKS_STOP; /*!< Stops I2S transfer. Also stops MCK generator. Triggering this
sahilmgandhi 18:6a4db94011d3 1883 task will cause the {event:STOPPED} event to be generated. */
sahilmgandhi 18:6a4db94011d3 1884 __I uint32_t RESERVED0[63];
sahilmgandhi 18:6a4db94011d3 1885 __IO uint32_t EVENTS_RXPTRUPD; /*!< The RXD.PTR register has been copied to internal double-buffers.
sahilmgandhi 18:6a4db94011d3 1886 When the I2S module is started and RX is enabled, this event
sahilmgandhi 18:6a4db94011d3 1887 will be generated for every RXTXD.MAXCNT words that are received
sahilmgandhi 18:6a4db94011d3 1888 on the SDIN pin. */
sahilmgandhi 18:6a4db94011d3 1889 __IO uint32_t EVENTS_STOPPED; /*!< I2S transfer stopped. */
sahilmgandhi 18:6a4db94011d3 1890 __I uint32_t RESERVED1[2];
sahilmgandhi 18:6a4db94011d3 1891 __IO uint32_t EVENTS_TXPTRUPD; /*!< The TDX.PTR register has been copied to internal double-buffers.
sahilmgandhi 18:6a4db94011d3 1892 When the I2S module is started and TX is enabled, this event
sahilmgandhi 18:6a4db94011d3 1893 will be generated for every RXTXD.MAXCNT words that are sent
sahilmgandhi 18:6a4db94011d3 1894 on the SDOUT pin. */
sahilmgandhi 18:6a4db94011d3 1895 __I uint32_t RESERVED2[122];
sahilmgandhi 18:6a4db94011d3 1896 __IO uint32_t INTEN; /*!< Enable or disable interrupt */
sahilmgandhi 18:6a4db94011d3 1897 __IO uint32_t INTENSET; /*!< Enable interrupt */
sahilmgandhi 18:6a4db94011d3 1898 __IO uint32_t INTENCLR; /*!< Disable interrupt */
sahilmgandhi 18:6a4db94011d3 1899 __I uint32_t RESERVED3[125];
sahilmgandhi 18:6a4db94011d3 1900 __IO uint32_t ENABLE; /*!< Enable I2S module. */
sahilmgandhi 18:6a4db94011d3 1901 I2S_CONFIG_Type CONFIG; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 1902 __I uint32_t RESERVED4[3];
sahilmgandhi 18:6a4db94011d3 1903 I2S_RXD_Type RXD; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 1904 __I uint32_t RESERVED5;
sahilmgandhi 18:6a4db94011d3 1905 I2S_TXD_Type TXD; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 1906 __I uint32_t RESERVED6[3];
sahilmgandhi 18:6a4db94011d3 1907 I2S_RXTXD_Type RXTXD; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 1908 __I uint32_t RESERVED7[3];
sahilmgandhi 18:6a4db94011d3 1909 I2S_PSEL_Type PSEL; /*!< Unspecified */
sahilmgandhi 18:6a4db94011d3 1910 } NRF_I2S_Type;
sahilmgandhi 18:6a4db94011d3 1911
sahilmgandhi 18:6a4db94011d3 1912
sahilmgandhi 18:6a4db94011d3 1913 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1914 /* ================ FPU ================ */
sahilmgandhi 18:6a4db94011d3 1915 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1916
sahilmgandhi 18:6a4db94011d3 1917
sahilmgandhi 18:6a4db94011d3 1918 /**
sahilmgandhi 18:6a4db94011d3 1919 * @brief FPU (FPU)
sahilmgandhi 18:6a4db94011d3 1920 */
sahilmgandhi 18:6a4db94011d3 1921
sahilmgandhi 18:6a4db94011d3 1922 typedef struct { /*!< FPU Structure */
sahilmgandhi 18:6a4db94011d3 1923 __I uint32_t UNUSED; /*!< Unused. */
sahilmgandhi 18:6a4db94011d3 1924 } NRF_FPU_Type;
sahilmgandhi 18:6a4db94011d3 1925
sahilmgandhi 18:6a4db94011d3 1926
sahilmgandhi 18:6a4db94011d3 1927 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1928 /* ================ GPIO ================ */
sahilmgandhi 18:6a4db94011d3 1929 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1930
sahilmgandhi 18:6a4db94011d3 1931
sahilmgandhi 18:6a4db94011d3 1932 /**
sahilmgandhi 18:6a4db94011d3 1933 * @brief GPIO Port 1 (GPIO)
sahilmgandhi 18:6a4db94011d3 1934 */
sahilmgandhi 18:6a4db94011d3 1935
sahilmgandhi 18:6a4db94011d3 1936 typedef struct { /*!< GPIO Structure */
sahilmgandhi 18:6a4db94011d3 1937 __I uint32_t RESERVED0[321];
sahilmgandhi 18:6a4db94011d3 1938 __IO uint32_t OUT; /*!< Write GPIO port */
sahilmgandhi 18:6a4db94011d3 1939 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port */
sahilmgandhi 18:6a4db94011d3 1940 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port */
sahilmgandhi 18:6a4db94011d3 1941 __I uint32_t IN; /*!< Read GPIO port */
sahilmgandhi 18:6a4db94011d3 1942 __IO uint32_t DIR; /*!< Direction of GPIO pins */
sahilmgandhi 18:6a4db94011d3 1943 __IO uint32_t DIRSET; /*!< DIR set register */
sahilmgandhi 18:6a4db94011d3 1944 __IO uint32_t DIRCLR; /*!< DIR clear register */
sahilmgandhi 18:6a4db94011d3 1945 __IO uint32_t LATCH; /*!< Latch register indicating what GPIO pins that have met the criteria
sahilmgandhi 18:6a4db94011d3 1946 set in the PIN_CNF[n].SENSE registers */
sahilmgandhi 18:6a4db94011d3 1947 __IO uint32_t DETECTMODE; /*!< Select between default DETECT signal behaviour and LDETECT mode */
sahilmgandhi 18:6a4db94011d3 1948 __I uint32_t RESERVED1[118];
sahilmgandhi 18:6a4db94011d3 1949 __IO uint32_t PIN_CNF[32]; /*!< Description collection[0]: Configuration of GPIO pins */
sahilmgandhi 18:6a4db94011d3 1950 } NRF_GPIO_Type;
sahilmgandhi 18:6a4db94011d3 1951
sahilmgandhi 18:6a4db94011d3 1952
sahilmgandhi 18:6a4db94011d3 1953 /* -------------------- End of section using anonymous unions ------------------- */
sahilmgandhi 18:6a4db94011d3 1954 #if defined(__CC_ARM)
sahilmgandhi 18:6a4db94011d3 1955 #pragma pop
sahilmgandhi 18:6a4db94011d3 1956 #elif defined(__ICCARM__)
sahilmgandhi 18:6a4db94011d3 1957 /* leave anonymous unions enabled */
sahilmgandhi 18:6a4db94011d3 1958 #elif defined(__GNUC__)
sahilmgandhi 18:6a4db94011d3 1959 /* anonymous unions are enabled by default */
sahilmgandhi 18:6a4db94011d3 1960 #elif defined(__TMS470__)
sahilmgandhi 18:6a4db94011d3 1961 /* anonymous unions are enabled by default */
sahilmgandhi 18:6a4db94011d3 1962 #elif defined(__TASKING__)
sahilmgandhi 18:6a4db94011d3 1963 #pragma warning restore
sahilmgandhi 18:6a4db94011d3 1964 #else
sahilmgandhi 18:6a4db94011d3 1965 #warning Not supported compiler type
sahilmgandhi 18:6a4db94011d3 1966 #endif
sahilmgandhi 18:6a4db94011d3 1967
sahilmgandhi 18:6a4db94011d3 1968
sahilmgandhi 18:6a4db94011d3 1969
sahilmgandhi 18:6a4db94011d3 1970
sahilmgandhi 18:6a4db94011d3 1971 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1972 /* ================ Peripheral memory map ================ */
sahilmgandhi 18:6a4db94011d3 1973 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1974
sahilmgandhi 18:6a4db94011d3 1975 #define NRF_FICR_BASE 0x10000000UL
sahilmgandhi 18:6a4db94011d3 1976 #define NRF_UICR_BASE 0x10001000UL
sahilmgandhi 18:6a4db94011d3 1977 #define NRF_BPROT_BASE 0x40000000UL
sahilmgandhi 18:6a4db94011d3 1978 #define NRF_POWER_BASE 0x40000000UL
sahilmgandhi 18:6a4db94011d3 1979 #define NRF_CLOCK_BASE 0x40000000UL
sahilmgandhi 18:6a4db94011d3 1980 #define NRF_AMLI_BASE 0x40000000UL
sahilmgandhi 18:6a4db94011d3 1981 #define NRF_RADIO_BASE 0x40001000UL
sahilmgandhi 18:6a4db94011d3 1982 #define NRF_UARTE0_BASE 0x40002000UL
sahilmgandhi 18:6a4db94011d3 1983 #define NRF_UART0_BASE 0x40002000UL
sahilmgandhi 18:6a4db94011d3 1984 #define NRF_SPIM0_BASE 0x40003000UL
sahilmgandhi 18:6a4db94011d3 1985 #define NRF_SPIS0_BASE 0x40003000UL
sahilmgandhi 18:6a4db94011d3 1986 #define NRF_TWIM0_BASE 0x40003000UL
sahilmgandhi 18:6a4db94011d3 1987 #define NRF_TWIS0_BASE 0x40003000UL
sahilmgandhi 18:6a4db94011d3 1988 #define NRF_SPI0_BASE 0x40003000UL
sahilmgandhi 18:6a4db94011d3 1989 #define NRF_TWI0_BASE 0x40003000UL
sahilmgandhi 18:6a4db94011d3 1990 #define NRF_SPIM1_BASE 0x40004000UL
sahilmgandhi 18:6a4db94011d3 1991 #define NRF_SPIS1_BASE 0x40004000UL
sahilmgandhi 18:6a4db94011d3 1992 #define NRF_TWIM1_BASE 0x40004000UL
sahilmgandhi 18:6a4db94011d3 1993 #define NRF_TWIS1_BASE 0x40004000UL
sahilmgandhi 18:6a4db94011d3 1994 #define NRF_SPI1_BASE 0x40004000UL
sahilmgandhi 18:6a4db94011d3 1995 #define NRF_TWI1_BASE 0x40004000UL
sahilmgandhi 18:6a4db94011d3 1996 #define NRF_NFCT_BASE 0x40005000UL
sahilmgandhi 18:6a4db94011d3 1997 #define NRF_GPIOTE_BASE 0x40006000UL
sahilmgandhi 18:6a4db94011d3 1998 #define NRF_SAADC_BASE 0x40007000UL
sahilmgandhi 18:6a4db94011d3 1999 #define NRF_TIMER0_BASE 0x40008000UL
sahilmgandhi 18:6a4db94011d3 2000 #define NRF_TIMER1_BASE 0x40009000UL
sahilmgandhi 18:6a4db94011d3 2001 #define NRF_TIMER2_BASE 0x4000A000UL
sahilmgandhi 18:6a4db94011d3 2002 #define NRF_RTC0_BASE 0x4000B000UL
sahilmgandhi 18:6a4db94011d3 2003 #define NRF_TEMP_BASE 0x4000C000UL
sahilmgandhi 18:6a4db94011d3 2004 #define NRF_RNG_BASE 0x4000D000UL
sahilmgandhi 18:6a4db94011d3 2005 #define NRF_ECB_BASE 0x4000E000UL
sahilmgandhi 18:6a4db94011d3 2006 #define NRF_CCM_BASE 0x4000F000UL
sahilmgandhi 18:6a4db94011d3 2007 #define NRF_AAR_BASE 0x4000F000UL
sahilmgandhi 18:6a4db94011d3 2008 #define NRF_WDT_BASE 0x40010000UL
sahilmgandhi 18:6a4db94011d3 2009 #define NRF_RTC1_BASE 0x40011000UL
sahilmgandhi 18:6a4db94011d3 2010 #define NRF_QDEC_BASE 0x40012000UL
sahilmgandhi 18:6a4db94011d3 2011 #define NRF_COMP_BASE 0x40013000UL
sahilmgandhi 18:6a4db94011d3 2012 #define NRF_LPCOMP_BASE 0x40013000UL
sahilmgandhi 18:6a4db94011d3 2013 #define NRF_SWI0_BASE 0x40014000UL
sahilmgandhi 18:6a4db94011d3 2014 #define NRF_EGU0_BASE 0x40014000UL
sahilmgandhi 18:6a4db94011d3 2015 #define NRF_SWI1_BASE 0x40015000UL
sahilmgandhi 18:6a4db94011d3 2016 #define NRF_EGU1_BASE 0x40015000UL
sahilmgandhi 18:6a4db94011d3 2017 #define NRF_SWI2_BASE 0x40016000UL
sahilmgandhi 18:6a4db94011d3 2018 #define NRF_EGU2_BASE 0x40016000UL
sahilmgandhi 18:6a4db94011d3 2019 #define NRF_SWI3_BASE 0x40017000UL
sahilmgandhi 18:6a4db94011d3 2020 #define NRF_EGU3_BASE 0x40017000UL
sahilmgandhi 18:6a4db94011d3 2021 #define NRF_SWI4_BASE 0x40018000UL
sahilmgandhi 18:6a4db94011d3 2022 #define NRF_EGU4_BASE 0x40018000UL
sahilmgandhi 18:6a4db94011d3 2023 #define NRF_SWI5_BASE 0x40019000UL
sahilmgandhi 18:6a4db94011d3 2024 #define NRF_EGU5_BASE 0x40019000UL
sahilmgandhi 18:6a4db94011d3 2025 #define NRF_TIMER3_BASE 0x4001A000UL
sahilmgandhi 18:6a4db94011d3 2026 #define NRF_TIMER4_BASE 0x4001B000UL
sahilmgandhi 18:6a4db94011d3 2027 #define NRF_PWM0_BASE 0x4001C000UL
sahilmgandhi 18:6a4db94011d3 2028 #define NRF_PDM_BASE 0x4001D000UL
sahilmgandhi 18:6a4db94011d3 2029 #define NRF_NVMC_BASE 0x4001E000UL
sahilmgandhi 18:6a4db94011d3 2030 #define NRF_PPI_BASE 0x4001F000UL
sahilmgandhi 18:6a4db94011d3 2031 #define NRF_MWU_BASE 0x40020000UL
sahilmgandhi 18:6a4db94011d3 2032 #define NRF_PWM1_BASE 0x40021000UL
sahilmgandhi 18:6a4db94011d3 2033 #define NRF_PWM2_BASE 0x40022000UL
sahilmgandhi 18:6a4db94011d3 2034 #define NRF_SPIM2_BASE 0x40023000UL
sahilmgandhi 18:6a4db94011d3 2035 #define NRF_SPIS2_BASE 0x40023000UL
sahilmgandhi 18:6a4db94011d3 2036 #define NRF_SPI2_BASE 0x40023000UL
sahilmgandhi 18:6a4db94011d3 2037 #define NRF_RTC2_BASE 0x40024000UL
sahilmgandhi 18:6a4db94011d3 2038 #define NRF_I2S_BASE 0x40025000UL
sahilmgandhi 18:6a4db94011d3 2039 #define NRF_FPU_BASE 0x40026000UL
sahilmgandhi 18:6a4db94011d3 2040 #define NRF_P0_BASE 0x50000000UL
sahilmgandhi 18:6a4db94011d3 2041
sahilmgandhi 18:6a4db94011d3 2042
sahilmgandhi 18:6a4db94011d3 2043 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 2044 /* ================ Peripheral declaration ================ */
sahilmgandhi 18:6a4db94011d3 2045 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 2046
sahilmgandhi 18:6a4db94011d3 2047 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
sahilmgandhi 18:6a4db94011d3 2048 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
sahilmgandhi 18:6a4db94011d3 2049 #define NRF_BPROT ((NRF_BPROT_Type *) NRF_BPROT_BASE)
sahilmgandhi 18:6a4db94011d3 2050 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
sahilmgandhi 18:6a4db94011d3 2051 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
sahilmgandhi 18:6a4db94011d3 2052 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
sahilmgandhi 18:6a4db94011d3 2053 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
sahilmgandhi 18:6a4db94011d3 2054 #define NRF_UARTE0 ((NRF_UARTE_Type *) NRF_UARTE0_BASE)
sahilmgandhi 18:6a4db94011d3 2055 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
sahilmgandhi 18:6a4db94011d3 2056 #define NRF_SPIM0 ((NRF_SPIM_Type *) NRF_SPIM0_BASE)
sahilmgandhi 18:6a4db94011d3 2057 #define NRF_SPIS0 ((NRF_SPIS_Type *) NRF_SPIS0_BASE)
sahilmgandhi 18:6a4db94011d3 2058 #define NRF_TWIM0 ((NRF_TWIM_Type *) NRF_TWIM0_BASE)
sahilmgandhi 18:6a4db94011d3 2059 #define NRF_TWIS0 ((NRF_TWIS_Type *) NRF_TWIS0_BASE)
sahilmgandhi 18:6a4db94011d3 2060 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
sahilmgandhi 18:6a4db94011d3 2061 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
sahilmgandhi 18:6a4db94011d3 2062 #define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
sahilmgandhi 18:6a4db94011d3 2063 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
sahilmgandhi 18:6a4db94011d3 2064 #define NRF_TWIM1 ((NRF_TWIM_Type *) NRF_TWIM1_BASE)
sahilmgandhi 18:6a4db94011d3 2065 #define NRF_TWIS1 ((NRF_TWIS_Type *) NRF_TWIS1_BASE)
sahilmgandhi 18:6a4db94011d3 2066 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
sahilmgandhi 18:6a4db94011d3 2067 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
sahilmgandhi 18:6a4db94011d3 2068 #define NRF_NFCT ((NRF_NFCT_Type *) NRF_NFCT_BASE)
sahilmgandhi 18:6a4db94011d3 2069 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
sahilmgandhi 18:6a4db94011d3 2070 #define NRF_SAADC ((NRF_SAADC_Type *) NRF_SAADC_BASE)
sahilmgandhi 18:6a4db94011d3 2071 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
sahilmgandhi 18:6a4db94011d3 2072 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
sahilmgandhi 18:6a4db94011d3 2073 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
sahilmgandhi 18:6a4db94011d3 2074 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
sahilmgandhi 18:6a4db94011d3 2075 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
sahilmgandhi 18:6a4db94011d3 2076 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
sahilmgandhi 18:6a4db94011d3 2077 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
sahilmgandhi 18:6a4db94011d3 2078 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
sahilmgandhi 18:6a4db94011d3 2079 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
sahilmgandhi 18:6a4db94011d3 2080 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
sahilmgandhi 18:6a4db94011d3 2081 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
sahilmgandhi 18:6a4db94011d3 2082 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
sahilmgandhi 18:6a4db94011d3 2083 #define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE)
sahilmgandhi 18:6a4db94011d3 2084 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
sahilmgandhi 18:6a4db94011d3 2085 #define NRF_SWI0 ((NRF_SWI_Type *) NRF_SWI0_BASE)
sahilmgandhi 18:6a4db94011d3 2086 #define NRF_EGU0 ((NRF_EGU_Type *) NRF_EGU0_BASE)
sahilmgandhi 18:6a4db94011d3 2087 #define NRF_SWI1 ((NRF_SWI_Type *) NRF_SWI1_BASE)
sahilmgandhi 18:6a4db94011d3 2088 #define NRF_EGU1 ((NRF_EGU_Type *) NRF_EGU1_BASE)
sahilmgandhi 18:6a4db94011d3 2089 #define NRF_SWI2 ((NRF_SWI_Type *) NRF_SWI2_BASE)
sahilmgandhi 18:6a4db94011d3 2090 #define NRF_EGU2 ((NRF_EGU_Type *) NRF_EGU2_BASE)
sahilmgandhi 18:6a4db94011d3 2091 #define NRF_SWI3 ((NRF_SWI_Type *) NRF_SWI3_BASE)
sahilmgandhi 18:6a4db94011d3 2092 #define NRF_EGU3 ((NRF_EGU_Type *) NRF_EGU3_BASE)
sahilmgandhi 18:6a4db94011d3 2093 #define NRF_SWI4 ((NRF_SWI_Type *) NRF_SWI4_BASE)
sahilmgandhi 18:6a4db94011d3 2094 #define NRF_EGU4 ((NRF_EGU_Type *) NRF_EGU4_BASE)
sahilmgandhi 18:6a4db94011d3 2095 #define NRF_SWI5 ((NRF_SWI_Type *) NRF_SWI5_BASE)
sahilmgandhi 18:6a4db94011d3 2096 #define NRF_EGU5 ((NRF_EGU_Type *) NRF_EGU5_BASE)
sahilmgandhi 18:6a4db94011d3 2097 #define NRF_TIMER3 ((NRF_TIMER_Type *) NRF_TIMER3_BASE)
sahilmgandhi 18:6a4db94011d3 2098 #define NRF_TIMER4 ((NRF_TIMER_Type *) NRF_TIMER4_BASE)
sahilmgandhi 18:6a4db94011d3 2099 #define NRF_PWM0 ((NRF_PWM_Type *) NRF_PWM0_BASE)
sahilmgandhi 18:6a4db94011d3 2100 #define NRF_PDM ((NRF_PDM_Type *) NRF_PDM_BASE)
sahilmgandhi 18:6a4db94011d3 2101 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
sahilmgandhi 18:6a4db94011d3 2102 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
sahilmgandhi 18:6a4db94011d3 2103 #define NRF_MWU ((NRF_MWU_Type *) NRF_MWU_BASE)
sahilmgandhi 18:6a4db94011d3 2104 #define NRF_PWM1 ((NRF_PWM_Type *) NRF_PWM1_BASE)
sahilmgandhi 18:6a4db94011d3 2105 #define NRF_PWM2 ((NRF_PWM_Type *) NRF_PWM2_BASE)
sahilmgandhi 18:6a4db94011d3 2106 #define NRF_SPIM2 ((NRF_SPIM_Type *) NRF_SPIM2_BASE)
sahilmgandhi 18:6a4db94011d3 2107 #define NRF_SPIS2 ((NRF_SPIS_Type *) NRF_SPIS2_BASE)
sahilmgandhi 18:6a4db94011d3 2108 #define NRF_SPI2 ((NRF_SPI_Type *) NRF_SPI2_BASE)
sahilmgandhi 18:6a4db94011d3 2109 #define NRF_RTC2 ((NRF_RTC_Type *) NRF_RTC2_BASE)
sahilmgandhi 18:6a4db94011d3 2110 #define NRF_I2S ((NRF_I2S_Type *) NRF_I2S_BASE)
sahilmgandhi 18:6a4db94011d3 2111 #define NRF_FPU ((NRF_FPU_Type *) NRF_FPU_BASE)
sahilmgandhi 18:6a4db94011d3 2112 #define NRF_P0 ((NRF_GPIO_Type *) NRF_P0_BASE)
sahilmgandhi 18:6a4db94011d3 2113
sahilmgandhi 18:6a4db94011d3 2114
sahilmgandhi 18:6a4db94011d3 2115 /** @} */ /* End of group Device_Peripheral_Registers */
sahilmgandhi 18:6a4db94011d3 2116 /** @} */ /* End of group nrf52 */
sahilmgandhi 18:6a4db94011d3 2117 /** @} */ /* End of group Nordic Semiconductor */
sahilmgandhi 18:6a4db94011d3 2118
sahilmgandhi 18:6a4db94011d3 2119 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 2120 }
sahilmgandhi 18:6a4db94011d3 2121 #endif
sahilmgandhi 18:6a4db94011d3 2122
sahilmgandhi 18:6a4db94011d3 2123
sahilmgandhi 18:6a4db94011d3 2124 #endif /* nrf52_H */
sahilmgandhi 18:6a4db94011d3 2125