MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_irq_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2013 Nordic Semiconductor
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include <stddef.h>
sahilmgandhi 18:6a4db94011d3 17 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 #include "gpio_irq_api.h"
sahilmgandhi 18:6a4db94011d3 20 #include "mbed_error.h"
sahilmgandhi 18:6a4db94011d3 21
sahilmgandhi 18:6a4db94011d3 22 #define CHANNEL_NUM 31
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24 static uint32_t channel_ids[CHANNEL_NUM] = {0}; //each pin will be given an id, if id is 0 the pin can be ignored.
sahilmgandhi 18:6a4db94011d3 25 static uint8_t channel_enabled[CHANNEL_NUM] = {0};
sahilmgandhi 18:6a4db94011d3 26 static uint32_t portRISE = 0;
sahilmgandhi 18:6a4db94011d3 27 static uint32_t portFALL = 0;
sahilmgandhi 18:6a4db94011d3 28 static gpio_irq_handler irq_handler;
sahilmgandhi 18:6a4db94011d3 29
sahilmgandhi 18:6a4db94011d3 30 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 31 extern "C" {
sahilmgandhi 18:6a4db94011d3 32 #endif
sahilmgandhi 18:6a4db94011d3 33 void GPIOTE_IRQHandler(void)
sahilmgandhi 18:6a4db94011d3 34 {
sahilmgandhi 18:6a4db94011d3 35 volatile uint32_t newVal = NRF_GPIO->IN;
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37 if ((NRF_GPIOTE->EVENTS_PORT != 0) && ((NRF_GPIOTE->INTENSET & GPIOTE_INTENSET_PORT_Msk) != 0)) {
sahilmgandhi 18:6a4db94011d3 38 NRF_GPIOTE->EVENTS_PORT = 0;
sahilmgandhi 18:6a4db94011d3 39
sahilmgandhi 18:6a4db94011d3 40 for (uint8_t i = 0; i<31; i++) {
sahilmgandhi 18:6a4db94011d3 41 if (channel_ids[i]>0) {
sahilmgandhi 18:6a4db94011d3 42 if (channel_enabled[i]) {
sahilmgandhi 18:6a4db94011d3 43 if( ((newVal>>i)&1) && ( ( (NRF_GPIO->PIN_CNF[i] >>GPIO_PIN_CNF_SENSE_Pos) & GPIO_PIN_CNF_SENSE_Low) != GPIO_PIN_CNF_SENSE_Low) && ( (portRISE>>i)&1) ){
sahilmgandhi 18:6a4db94011d3 44 irq_handler(channel_ids[i], IRQ_RISE);
sahilmgandhi 18:6a4db94011d3 45 } else if ((((newVal >> i) & 1) == 0) &&
sahilmgandhi 18:6a4db94011d3 46 (((NRF_GPIO->PIN_CNF[i] >> GPIO_PIN_CNF_SENSE_Pos) & GPIO_PIN_CNF_SENSE_Low) == GPIO_PIN_CNF_SENSE_Low) &&
sahilmgandhi 18:6a4db94011d3 47 ((portFALL >> i) & 1)) {
sahilmgandhi 18:6a4db94011d3 48 irq_handler(channel_ids[i], IRQ_FALL);
sahilmgandhi 18:6a4db94011d3 49 }
sahilmgandhi 18:6a4db94011d3 50 }
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 if (NRF_GPIO->PIN_CNF[i] & GPIO_PIN_CNF_SENSE_Msk) {
sahilmgandhi 18:6a4db94011d3 53 NRF_GPIO->PIN_CNF[i] &= ~(GPIO_PIN_CNF_SENSE_Msk);
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 if (newVal >> i & 1) {
sahilmgandhi 18:6a4db94011d3 56 NRF_GPIO->PIN_CNF[i] |= (GPIO_PIN_CNF_SENSE_Low << GPIO_PIN_CNF_SENSE_Pos);
sahilmgandhi 18:6a4db94011d3 57 } else {
sahilmgandhi 18:6a4db94011d3 58 NRF_GPIO->PIN_CNF[i] |= (GPIO_PIN_CNF_SENSE_High << GPIO_PIN_CNF_SENSE_Pos);
sahilmgandhi 18:6a4db94011d3 59 }
sahilmgandhi 18:6a4db94011d3 60 }
sahilmgandhi 18:6a4db94011d3 61 }
sahilmgandhi 18:6a4db94011d3 62 }
sahilmgandhi 18:6a4db94011d3 63 }
sahilmgandhi 18:6a4db94011d3 64 }
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 67 }
sahilmgandhi 18:6a4db94011d3 68 #endif
sahilmgandhi 18:6a4db94011d3 69
sahilmgandhi 18:6a4db94011d3 70 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
sahilmgandhi 18:6a4db94011d3 71 {
sahilmgandhi 18:6a4db94011d3 72 if (pin == NC) {
sahilmgandhi 18:6a4db94011d3 73 return -1;
sahilmgandhi 18:6a4db94011d3 74 }
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76 irq_handler = handler;
sahilmgandhi 18:6a4db94011d3 77 obj->ch = pin;
sahilmgandhi 18:6a4db94011d3 78 NRF_GPIOTE->EVENTS_PORT = 0;
sahilmgandhi 18:6a4db94011d3 79 channel_ids[pin] = id;
sahilmgandhi 18:6a4db94011d3 80 channel_enabled[pin] = 1;
sahilmgandhi 18:6a4db94011d3 81 NRF_GPIOTE->INTENSET = GPIOTE_INTENSET_PORT_Set << GPIOTE_INTENSET_PORT_Pos;
sahilmgandhi 18:6a4db94011d3 82
sahilmgandhi 18:6a4db94011d3 83 NVIC_SetPriority(GPIOTE_IRQn, 3);
sahilmgandhi 18:6a4db94011d3 84 NVIC_EnableIRQ (GPIOTE_IRQn);
sahilmgandhi 18:6a4db94011d3 85 return 0;
sahilmgandhi 18:6a4db94011d3 86 }
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 void gpio_irq_free(gpio_irq_t *obj)
sahilmgandhi 18:6a4db94011d3 89 {
sahilmgandhi 18:6a4db94011d3 90 channel_ids[obj->ch] = 0;
sahilmgandhi 18:6a4db94011d3 91 }
sahilmgandhi 18:6a4db94011d3 92
sahilmgandhi 18:6a4db94011d3 93 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
sahilmgandhi 18:6a4db94011d3 94 {
sahilmgandhi 18:6a4db94011d3 95 NRF_GPIO->PIN_CNF[obj->ch] &= ~(GPIO_PIN_CNF_SENSE_Msk);
sahilmgandhi 18:6a4db94011d3 96 if (enable) {
sahilmgandhi 18:6a4db94011d3 97 if (event == IRQ_RISE) {
sahilmgandhi 18:6a4db94011d3 98 portRISE |= (1 << obj->ch);
sahilmgandhi 18:6a4db94011d3 99 } else if (event == IRQ_FALL) {
sahilmgandhi 18:6a4db94011d3 100 portFALL |= (1 << obj->ch);
sahilmgandhi 18:6a4db94011d3 101 }
sahilmgandhi 18:6a4db94011d3 102 } else {
sahilmgandhi 18:6a4db94011d3 103 if (event == IRQ_RISE) {
sahilmgandhi 18:6a4db94011d3 104 portRISE &= ~(1 << obj->ch);
sahilmgandhi 18:6a4db94011d3 105 } else if (event == IRQ_FALL) {
sahilmgandhi 18:6a4db94011d3 106 portFALL &= ~(1 << obj->ch);
sahilmgandhi 18:6a4db94011d3 107 }
sahilmgandhi 18:6a4db94011d3 108 }
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 if (((portRISE >> obj->ch) & 1) || ((portFALL >> obj->ch) & 1)) {
sahilmgandhi 18:6a4db94011d3 111 if ((NRF_GPIO->IN >> obj->ch) & 1) {
sahilmgandhi 18:6a4db94011d3 112 NRF_GPIO->PIN_CNF[obj->ch] |= (GPIO_PIN_CNF_SENSE_Low << GPIO_PIN_CNF_SENSE_Pos); // | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos);
sahilmgandhi 18:6a4db94011d3 113 } else {
sahilmgandhi 18:6a4db94011d3 114 NRF_GPIO->PIN_CNF[obj->ch] |= (GPIO_PIN_CNF_SENSE_High << GPIO_PIN_CNF_SENSE_Pos); //| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos);
sahilmgandhi 18:6a4db94011d3 115 }
sahilmgandhi 18:6a4db94011d3 116 }
sahilmgandhi 18:6a4db94011d3 117 }
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 void gpio_irq_enable(gpio_irq_t *obj)
sahilmgandhi 18:6a4db94011d3 120 {
sahilmgandhi 18:6a4db94011d3 121 channel_enabled[obj->ch] = 1;
sahilmgandhi 18:6a4db94011d3 122 }
sahilmgandhi 18:6a4db94011d3 123
sahilmgandhi 18:6a4db94011d3 124 void gpio_irq_disable(gpio_irq_t *obj)
sahilmgandhi 18:6a4db94011d3 125 {
sahilmgandhi 18:6a4db94011d3 126 channel_enabled[obj->ch] = 0;
sahilmgandhi 18:6a4db94011d3 127 }