MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Maxim/TARGET_MAX32630/PeripheralPins.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /*******************************************************************************
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Permission is hereby granted, free of charge, to any person obtaining a
sahilmgandhi 18:6a4db94011d3 5 * copy of this software and associated documentation files (the "Software"),
sahilmgandhi 18:6a4db94011d3 6 * to deal in the Software without restriction, including without limitation
sahilmgandhi 18:6a4db94011d3 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
sahilmgandhi 18:6a4db94011d3 8 * and/or sell copies of the Software, and to permit persons to whom the
sahilmgandhi 18:6a4db94011d3 9 * Software is furnished to do so, subject to the following conditions:
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * The above copyright notice and this permission notice shall be included
sahilmgandhi 18:6a4db94011d3 12 * in all copies or substantial portions of the Software.
sahilmgandhi 18:6a4db94011d3 13 *
sahilmgandhi 18:6a4db94011d3 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
sahilmgandhi 18:6a4db94011d3 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
sahilmgandhi 18:6a4db94011d3 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
sahilmgandhi 18:6a4db94011d3 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
sahilmgandhi 18:6a4db94011d3 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
sahilmgandhi 18:6a4db94011d3 20 * OTHER DEALINGS IN THE SOFTWARE.
sahilmgandhi 18:6a4db94011d3 21 *
sahilmgandhi 18:6a4db94011d3 22 * Except as contained in this notice, the name of Maxim Integrated
sahilmgandhi 18:6a4db94011d3 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
sahilmgandhi 18:6a4db94011d3 24 * Products, Inc. Branding Policy.
sahilmgandhi 18:6a4db94011d3 25 *
sahilmgandhi 18:6a4db94011d3 26 * The mere transfer of this software does not imply any licenses
sahilmgandhi 18:6a4db94011d3 27 * of trade secrets, proprietary technology, copyrights, patents,
sahilmgandhi 18:6a4db94011d3 28 * trademarks, maskwork rights, or any other form of intellectual
sahilmgandhi 18:6a4db94011d3 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
sahilmgandhi 18:6a4db94011d3 30 * ownership rights.
sahilmgandhi 18:6a4db94011d3 31 *******************************************************************************
sahilmgandhi 18:6a4db94011d3 32 */
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 #include "device.h"
sahilmgandhi 18:6a4db94011d3 35 #include "PeripheralPins.h"
sahilmgandhi 18:6a4db94011d3 36 #include "ioman_regs.h"
sahilmgandhi 18:6a4db94011d3 37 #include "ioman.h"
sahilmgandhi 18:6a4db94011d3 38 #include "adc.h"
sahilmgandhi 18:6a4db94011d3 39
sahilmgandhi 18:6a4db94011d3 40 /*
sahilmgandhi 18:6a4db94011d3 41 * To select a peripheral function on Maxim microcontrollers, multiple
sahilmgandhi 18:6a4db94011d3 42 * configurations must be made. The mbed PinMap structure only includes one
sahilmgandhi 18:6a4db94011d3 43 * data member to hold this information. To extend the configuration storage,
sahilmgandhi 18:6a4db94011d3 44 * the "function" data member is used as a pointer to a pin_function_t
sahilmgandhi 18:6a4db94011d3 45 * structure. This structure is defined in objects.h. The definitions below
sahilmgandhi 18:6a4db94011d3 46 * include the creation of the pin_function_t structures and the assignment of
sahilmgandhi 18:6a4db94011d3 47 * the pointers to the "function" data members.
sahilmgandhi 18:6a4db94011d3 48 */
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 #ifdef TOOLCHAIN_ARM_STD
sahilmgandhi 18:6a4db94011d3 51 #pragma diag_suppress 1296
sahilmgandhi 18:6a4db94011d3 52 #endif
sahilmgandhi 18:6a4db94011d3 53
sahilmgandhi 18:6a4db94011d3 54 /************I2C***************/
sahilmgandhi 18:6a4db94011d3 55 const PinMap PinMap_I2C_SDA[] = {
sahilmgandhi 18:6a4db94011d3 56 { P1_6, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK}) },
sahilmgandhi 18:6a4db94011d3 57 { P3_4, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) },
sahilmgandhi 18:6a4db94011d3 58 { P5_7, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) },
sahilmgandhi 18:6a4db94011d3 59 { P7_1, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) },
sahilmgandhi 18:6a4db94011d3 60 { P6_7, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) },
sahilmgandhi 18:6a4db94011d3 61 { P7_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) },
sahilmgandhi 18:6a4db94011d3 62 { P7_3, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) },
sahilmgandhi 18:6a4db94011d3 63 { NC, NC, 0 }
sahilmgandhi 18:6a4db94011d3 64 };
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66 const PinMap PinMap_I2C_SCL[] = {
sahilmgandhi 18:6a4db94011d3 67 { P1_7, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK}) },
sahilmgandhi 18:6a4db94011d3 68 { P3_5, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) },
sahilmgandhi 18:6a4db94011d3 69 { P6_0, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) },
sahilmgandhi 18:6a4db94011d3 70 { P7_2, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) },
sahilmgandhi 18:6a4db94011d3 71 { P7_0, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) },
sahilmgandhi 18:6a4db94011d3 72 { P8_0, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) },
sahilmgandhi 18:6a4db94011d3 73 { P7_4, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) },
sahilmgandhi 18:6a4db94011d3 74 { NC, NC, 0 }
sahilmgandhi 18:6a4db94011d3 75 };
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 /************UART***************/
sahilmgandhi 18:6a4db94011d3 78 const PinMap PinMap_UART_TX[] = {
sahilmgandhi 18:6a4db94011d3 79 { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_IO_REQ), (MXC_F_IOMAN_UART0_ACK_IO_MAP | MXC_F_IOMAN_UART0_ACK_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 80 { P2_1, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_IO_REQ), (MXC_F_IOMAN_UART1_ACK_IO_MAP | MXC_F_IOMAN_UART1_ACK_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 81 { P3_1, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_IO_REQ), (MXC_F_IOMAN_UART2_ACK_IO_MAP | MXC_F_IOMAN_UART2_ACK_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 82 { P5_4, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART3_REQ_IO_REQ), (MXC_F_IOMAN_UART3_ACK_IO_MAP | MXC_F_IOMAN_UART3_ACK_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 83 { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_IO_REQ), (MXC_F_IOMAN_UART0_ACK_IO_MAP | MXC_F_IOMAN_UART0_ACK_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 84 { P2_0, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_IO_REQ), (MXC_F_IOMAN_UART1_ACK_IO_MAP | MXC_F_IOMAN_UART1_ACK_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 85 { P3_0, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_IO_REQ), (MXC_F_IOMAN_UART2_ACK_IO_MAP | MXC_F_IOMAN_UART2_ACK_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 86 { P5_3, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART3_REQ_IO_REQ), (MXC_F_IOMAN_UART3_ACK_IO_MAP | MXC_F_IOMAN_UART3_ACK_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 87 { NC, NC, 0 }
sahilmgandhi 18:6a4db94011d3 88 };
sahilmgandhi 18:6a4db94011d3 89
sahilmgandhi 18:6a4db94011d3 90 const PinMap PinMap_UART_RX[] = {
sahilmgandhi 18:6a4db94011d3 91 { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_IO_REQ), (MXC_F_IOMAN_UART0_ACK_IO_MAP | MXC_F_IOMAN_UART0_ACK_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 92 { P2_0, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_IO_REQ), (MXC_F_IOMAN_UART1_ACK_IO_MAP | MXC_F_IOMAN_UART1_ACK_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 93 { P3_0, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_IO_REQ), (MXC_F_IOMAN_UART2_ACK_IO_MAP | MXC_F_IOMAN_UART2_ACK_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 94 { P5_3, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART3_REQ_IO_REQ), (MXC_F_IOMAN_UART3_ACK_IO_MAP | MXC_F_IOMAN_UART3_ACK_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 95 { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_IO_REQ), (MXC_F_IOMAN_UART0_ACK_IO_MAP | MXC_F_IOMAN_UART0_ACK_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 96 { P2_1, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_IO_REQ), (MXC_F_IOMAN_UART1_ACK_IO_MAP | MXC_F_IOMAN_UART1_ACK_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 97 { P3_1, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_IO_REQ), (MXC_F_IOMAN_UART2_ACK_IO_MAP | MXC_F_IOMAN_UART2_ACK_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 98 { P5_4, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART3_REQ_IO_REQ), (MXC_F_IOMAN_UART3_ACK_IO_MAP | MXC_F_IOMAN_UART3_ACK_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 99 { NC, NC, 0 }
sahilmgandhi 18:6a4db94011d3 100 };
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102 const PinMap PinMap_UART_CTS[] = {
sahilmgandhi 18:6a4db94011d3 103 { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_CTS_MAP | MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 104 { P2_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_CTS_MAP | MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 105 { P3_2, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_CTS_MAP | MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 106 { P5_5, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_CTS_MAP | MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 107 { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_CTS_MAP | MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 108 { P2_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_CTS_MAP | MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 109 { P3_3, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_CTS_MAP | MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 110 { P5_6, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_CTS_MAP | MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 111 { NC, NC, 0 }
sahilmgandhi 18:6a4db94011d3 112 };
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 const PinMap PinMap_UART_RTS[] = {
sahilmgandhi 18:6a4db94011d3 115 { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_RTS_MAP | MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 116 { P2_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_RTS_MAP | MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 117 { P3_3, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_RTS_MAP | MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 118 { P5_6, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_RTS_MAP | MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 119 { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_RTS_MAP | MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 120 { P2_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_RTS_MAP | MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 121 { P3_2, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_RTS_MAP | MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 122 { P5_5, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_RTS_MAP | MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 123 { NC, NC, 0 }
sahilmgandhi 18:6a4db94011d3 124 };
sahilmgandhi 18:6a4db94011d3 125
sahilmgandhi 18:6a4db94011d3 126 /************SPI***************/
sahilmgandhi 18:6a4db94011d3 127 const PinMap PinMap_SPI_SCLK[] = {
sahilmgandhi 18:6a4db94011d3 128 { P0_4, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK}) },
sahilmgandhi 18:6a4db94011d3 129 { P1_0, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK}) },
sahilmgandhi 18:6a4db94011d3 130 { P2_4, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 131 { P5_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 132 { P6_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 133 { NC, NC, 0 }
sahilmgandhi 18:6a4db94011d3 134 };
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 const PinMap PinMap_SPI_MOSI[] = {
sahilmgandhi 18:6a4db94011d3 137 { P0_5, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK}) },
sahilmgandhi 18:6a4db94011d3 138 { P1_1, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK}) },
sahilmgandhi 18:6a4db94011d3 139 { P2_5, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 140 { P5_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 141 { P6_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 142 { NC, NC, 0 }
sahilmgandhi 18:6a4db94011d3 143 };
sahilmgandhi 18:6a4db94011d3 144
sahilmgandhi 18:6a4db94011d3 145 const PinMap PinMap_SPI_MISO[] = {
sahilmgandhi 18:6a4db94011d3 146 { P0_6, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK}) },
sahilmgandhi 18:6a4db94011d3 147 { P1_2, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK}) },
sahilmgandhi 18:6a4db94011d3 148 { P2_6, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 149 { P5_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 150 { P6_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
sahilmgandhi 18:6a4db94011d3 151 { NC, NC, 0 }
sahilmgandhi 18:6a4db94011d3 152 };
sahilmgandhi 18:6a4db94011d3 153
sahilmgandhi 18:6a4db94011d3 154 const PinMap PinMap_SPI_SSEL[] = {
sahilmgandhi 18:6a4db94011d3 155 { P0_7, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK}) },
sahilmgandhi 18:6a4db94011d3 156 { P1_3, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK}) },
sahilmgandhi 18:6a4db94011d3 157 { P2_7, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK}) },
sahilmgandhi 18:6a4db94011d3 158 { P5_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK}) },
sahilmgandhi 18:6a4db94011d3 159 { P6_4, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK}) },
sahilmgandhi 18:6a4db94011d3 160 { NC, NC, 0 }
sahilmgandhi 18:6a4db94011d3 161 };
sahilmgandhi 18:6a4db94011d3 162
sahilmgandhi 18:6a4db94011d3 163 /************PWM***************/
sahilmgandhi 18:6a4db94011d3 164 const PinMap PinMap_PWM[] = {
sahilmgandhi 18:6a4db94011d3 165 { P0_0, PWM_0, 1 }, { P2_0, PWM_0, 1 }, { P4_0, PWM_0, 1 }, { P6_0, PWM_0, 1 }, { P8_0, PWM_0, 1 },
sahilmgandhi 18:6a4db94011d3 166 { P0_1, PWM_1, 1 }, { P2_1, PWM_1, 1 }, { P4_1, PWM_1, 1 }, { P6_1, PWM_1, 1 }, { P8_1, PWM_1, 1 },
sahilmgandhi 18:6a4db94011d3 167 { P0_2, PWM_2, 1 }, { P2_2, PWM_2, 1 }, { P4_2, PWM_2, 1 }, { P6_2, PWM_2, 1 },
sahilmgandhi 18:6a4db94011d3 168 { P0_3, PWM_3, 1 }, { P2_3, PWM_3, 1 }, { P4_3, PWM_3, 1 }, { P6_3, PWM_3, 1 },
sahilmgandhi 18:6a4db94011d3 169 { P0_4, PWM_4, 1 }, { P2_4, PWM_4, 1 }, { P4_4, PWM_4, 1 }, { P6_4, PWM_4, 1 },
sahilmgandhi 18:6a4db94011d3 170 { P0_5, PWM_5, 1 }, { P2_5, PWM_5, 1 }, { P4_5, PWM_5, 1 }, { P6_5, PWM_5, 1 },
sahilmgandhi 18:6a4db94011d3 171 { P0_6, PWM_6, 1 }, { P2_6, PWM_6, 1 }, { P4_6, PWM_6, 1 }, { P6_6, PWM_6, 1 },
sahilmgandhi 18:6a4db94011d3 172 { P0_7, PWM_7, 1 }, { P2_7, PWM_7, 1 }, { P4_7, PWM_7, 1 }, { P6_7, PWM_7, 1 },
sahilmgandhi 18:6a4db94011d3 173 { P1_0, PWM_8, 1 }, { P3_0, PWM_8, 1 }, { P5_0, PWM_8, 1 }, { P7_0, PWM_8, 1 },
sahilmgandhi 18:6a4db94011d3 174 { P1_1, PWM_9, 1 }, { P3_1, PWM_9, 1 }, { P5_1, PWM_9, 1 }, { P7_1, PWM_9, 1 },
sahilmgandhi 18:6a4db94011d3 175 { P1_2, PWM_10, 1 }, { P3_2, PWM_10, 1 }, { P5_2, PWM_10, 1 }, { P7_2, PWM_10, 1 },
sahilmgandhi 18:6a4db94011d3 176 { P1_3, PWM_11, 1 }, { P3_3, PWM_11, 1 }, { P5_3, PWM_11, 1 }, { P7_3, PWM_11, 1 },
sahilmgandhi 18:6a4db94011d3 177 { P1_4, PWM_12, 1 }, { P3_4, PWM_12, 1 }, { P5_4, PWM_12, 1 }, { P7_4, PWM_12, 1 },
sahilmgandhi 18:6a4db94011d3 178 { P1_5, PWM_13, 1 }, { P3_5, PWM_13, 1 }, { P5_5, PWM_13, 1 }, { P7_5, PWM_13, 1 },
sahilmgandhi 18:6a4db94011d3 179 { P1_6, PWM_14, 1 }, { P3_6, PWM_14, 1 }, { P5_6, PWM_14, 1 }, { P7_6, PWM_14, 1 },
sahilmgandhi 18:6a4db94011d3 180 { P1_7, PWM_15, 1 }, { P3_7, PWM_15, 1 }, { P5_7, PWM_15, 1 }, { P7_7, PWM_15, 1 },
sahilmgandhi 18:6a4db94011d3 181 { NC, NC, 0 }
sahilmgandhi 18:6a4db94011d3 182 };
sahilmgandhi 18:6a4db94011d3 183
sahilmgandhi 18:6a4db94011d3 184 /************ADC***************/
sahilmgandhi 18:6a4db94011d3 185 const PinMap PinMap_ADC[] = {
sahilmgandhi 18:6a4db94011d3 186 { AIN_0, ADC, ADC_CH_0 },
sahilmgandhi 18:6a4db94011d3 187 { AIN_1, ADC, ADC_CH_1 },
sahilmgandhi 18:6a4db94011d3 188 { AIN_2, ADC, ADC_CH_2 },
sahilmgandhi 18:6a4db94011d3 189 { AIN_3, ADC, ADC_CH_3 },
sahilmgandhi 18:6a4db94011d3 190 { AIN_4, ADC, ADC_CH_0_DIV_5 },
sahilmgandhi 18:6a4db94011d3 191 { AIN_5, ADC, ADC_CH_1_DIV_5 },
sahilmgandhi 18:6a4db94011d3 192 { AIN_6, ADC, ADC_CH_VDDB_DIV_4 },
sahilmgandhi 18:6a4db94011d3 193 { AIN_7, ADC, ADC_CH_VDD18 },
sahilmgandhi 18:6a4db94011d3 194 { AIN_8, ADC, ADC_CH_VDD12 },
sahilmgandhi 18:6a4db94011d3 195 { AIN_9, ADC, ADC_CH_VRTC_DIV_2 },
sahilmgandhi 18:6a4db94011d3 196 { NC, NC, 0 }
sahilmgandhi 18:6a4db94011d3 197 };