MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Maxim/TARGET_MAX32620/objects.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /*******************************************************************************
sahilmgandhi 18:6a4db94011d3 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Permission is hereby granted, free of charge, to any person obtaining a
sahilmgandhi 18:6a4db94011d3 5 * copy of this software and associated documentation files (the "Software"),
sahilmgandhi 18:6a4db94011d3 6 * to deal in the Software without restriction, including without limitation
sahilmgandhi 18:6a4db94011d3 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
sahilmgandhi 18:6a4db94011d3 8 * and/or sell copies of the Software, and to permit persons to whom the
sahilmgandhi 18:6a4db94011d3 9 * Software is furnished to do so, subject to the following conditions:
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * The above copyright notice and this permission notice shall be included
sahilmgandhi 18:6a4db94011d3 12 * in all copies or substantial portions of the Software.
sahilmgandhi 18:6a4db94011d3 13 *
sahilmgandhi 18:6a4db94011d3 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
sahilmgandhi 18:6a4db94011d3 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
sahilmgandhi 18:6a4db94011d3 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
sahilmgandhi 18:6a4db94011d3 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
sahilmgandhi 18:6a4db94011d3 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
sahilmgandhi 18:6a4db94011d3 20 * OTHER DEALINGS IN THE SOFTWARE.
sahilmgandhi 18:6a4db94011d3 21 *
sahilmgandhi 18:6a4db94011d3 22 * Except as contained in this notice, the name of Maxim Integrated
sahilmgandhi 18:6a4db94011d3 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
sahilmgandhi 18:6a4db94011d3 24 * Products, Inc. Branding Policy.
sahilmgandhi 18:6a4db94011d3 25 *
sahilmgandhi 18:6a4db94011d3 26 * The mere transfer of this software does not imply any licenses
sahilmgandhi 18:6a4db94011d3 27 * of trade secrets, proprietary technology, copyrights, patents,
sahilmgandhi 18:6a4db94011d3 28 * trademarks, maskwork rights, or any other form of intellectual
sahilmgandhi 18:6a4db94011d3 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
sahilmgandhi 18:6a4db94011d3 30 * ownership rights.
sahilmgandhi 18:6a4db94011d3 31 *******************************************************************************
sahilmgandhi 18:6a4db94011d3 32 */
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 #ifndef MBED_OBJECTS_H
sahilmgandhi 18:6a4db94011d3 35 #define MBED_OBJECTS_H
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 38 #include "PortNames.h"
sahilmgandhi 18:6a4db94011d3 39 #include "PeripheralNames.h"
sahilmgandhi 18:6a4db94011d3 40 #include "PinNames.h"
sahilmgandhi 18:6a4db94011d3 41 #include "gpio_object.h"
sahilmgandhi 18:6a4db94011d3 42 #include "gpio_regs.h"
sahilmgandhi 18:6a4db94011d3 43 #include "uart_regs.h"
sahilmgandhi 18:6a4db94011d3 44 #include "i2cm_regs.h"
sahilmgandhi 18:6a4db94011d3 45 #include "spi_regs.h"
sahilmgandhi 18:6a4db94011d3 46 #include "pt_regs.h"
sahilmgandhi 18:6a4db94011d3 47 #include "adc_regs.h"
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 50 extern "C" {
sahilmgandhi 18:6a4db94011d3 51 #endif
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 struct port_s {
sahilmgandhi 18:6a4db94011d3 54 PortName port;
sahilmgandhi 18:6a4db94011d3 55 uint32_t mask;
sahilmgandhi 18:6a4db94011d3 56 __IO uint32_t *reg_out;
sahilmgandhi 18:6a4db94011d3 57 __I uint32_t *reg_in;
sahilmgandhi 18:6a4db94011d3 58 };
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 struct gpio_irq_s {
sahilmgandhi 18:6a4db94011d3 61 uint8_t port;
sahilmgandhi 18:6a4db94011d3 62 uint8_t pin;
sahilmgandhi 18:6a4db94011d3 63 uint8_t rise_en;
sahilmgandhi 18:6a4db94011d3 64 uint8_t fall_en;
sahilmgandhi 18:6a4db94011d3 65 uint32_t id;
sahilmgandhi 18:6a4db94011d3 66 };
sahilmgandhi 18:6a4db94011d3 67
sahilmgandhi 18:6a4db94011d3 68 struct serial_s {
sahilmgandhi 18:6a4db94011d3 69 int index;
sahilmgandhi 18:6a4db94011d3 70 mxc_uart_regs_t *uart;
sahilmgandhi 18:6a4db94011d3 71 mxc_uart_fifo_regs_t *fifo;
sahilmgandhi 18:6a4db94011d3 72 };
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 struct i2c_s {
sahilmgandhi 18:6a4db94011d3 75 int index;
sahilmgandhi 18:6a4db94011d3 76 mxc_i2cm_regs_t *i2c;
sahilmgandhi 18:6a4db94011d3 77 mxc_i2cm_fifo_regs_t *fifos;
sahilmgandhi 18:6a4db94011d3 78 int start_pending;
sahilmgandhi 18:6a4db94011d3 79 int stop_pending;
sahilmgandhi 18:6a4db94011d3 80 };
sahilmgandhi 18:6a4db94011d3 81
sahilmgandhi 18:6a4db94011d3 82 struct spi_s {
sahilmgandhi 18:6a4db94011d3 83 int index;
sahilmgandhi 18:6a4db94011d3 84 mxc_spi_regs_t *spi;
sahilmgandhi 18:6a4db94011d3 85 mxc_spi_fifo_regs_t *fifo;
sahilmgandhi 18:6a4db94011d3 86 int bits;
sahilmgandhi 18:6a4db94011d3 87 int ssel;
sahilmgandhi 18:6a4db94011d3 88 uint32_t width; // SPI data width (number of data lines to use)
sahilmgandhi 18:6a4db94011d3 89 PinName sclk; // PinName saved to use in Quad SPI pin mapping table
sahilmgandhi 18:6a4db94011d3 90 #if DEVICE_SPI_ASYNCH
sahilmgandhi 18:6a4db94011d3 91 // Async transaction state
sahilmgandhi 18:6a4db94011d3 92 const uint8_t *tx_data; // TX buffer
sahilmgandhi 18:6a4db94011d3 93 uint8_t *rx_data; // RX buffer
sahilmgandhi 18:6a4db94011d3 94 unsigned len; // Number of bytes to send
sahilmgandhi 18:6a4db94011d3 95 unsigned read_num; // Number of bytes read
sahilmgandhi 18:6a4db94011d3 96 unsigned write_num; // Number of bytes written
sahilmgandhi 18:6a4db94011d3 97 void (*callback)(); // Callback for asynchronous request
sahilmgandhi 18:6a4db94011d3 98 unsigned head_rem; // Remaining count for current header
sahilmgandhi 18:6a4db94011d3 99 uint32_t event; // Callback response events
sahilmgandhi 18:6a4db94011d3 100 #endif
sahilmgandhi 18:6a4db94011d3 101 };
sahilmgandhi 18:6a4db94011d3 102
sahilmgandhi 18:6a4db94011d3 103 struct pwmout_s {
sahilmgandhi 18:6a4db94011d3 104 mxc_pt_regs_t *pwm;
sahilmgandhi 18:6a4db94011d3 105 int period;
sahilmgandhi 18:6a4db94011d3 106 int pulse_width;
sahilmgandhi 18:6a4db94011d3 107 };
sahilmgandhi 18:6a4db94011d3 108
sahilmgandhi 18:6a4db94011d3 109 struct analogin_s {
sahilmgandhi 18:6a4db94011d3 110 mxc_adc_regs_t *adc;
sahilmgandhi 18:6a4db94011d3 111 PinName adc_pin;
sahilmgandhi 18:6a4db94011d3 112 };
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 typedef struct {
sahilmgandhi 18:6a4db94011d3 115 volatile uint32_t *reg_req;
sahilmgandhi 18:6a4db94011d3 116 volatile uint32_t *reg_ack;
sahilmgandhi 18:6a4db94011d3 117 uint32_t req_val;
sahilmgandhi 18:6a4db94011d3 118 uint32_t ack_mask;
sahilmgandhi 18:6a4db94011d3 119 } pin_function_t;
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 122 }
sahilmgandhi 18:6a4db94011d3 123 #endif
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125 #endif