MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Maxim/TARGET_MAX32610/sleep.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /*******************************************************************************
sahilmgandhi 18:6a4db94011d3 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Permission is hereby granted, free of charge, to any person obtaining a
sahilmgandhi 18:6a4db94011d3 5 * copy of this software and associated documentation files (the "Software"),
sahilmgandhi 18:6a4db94011d3 6 * to deal in the Software without restriction, including without limitation
sahilmgandhi 18:6a4db94011d3 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
sahilmgandhi 18:6a4db94011d3 8 * and/or sell copies of the Software, and to permit persons to whom the
sahilmgandhi 18:6a4db94011d3 9 * Software is furnished to do so, subject to the following conditions:
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * The above copyright notice and this permission notice shall be included
sahilmgandhi 18:6a4db94011d3 12 * in all copies or substantial portions of the Software.
sahilmgandhi 18:6a4db94011d3 13 *
sahilmgandhi 18:6a4db94011d3 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
sahilmgandhi 18:6a4db94011d3 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
sahilmgandhi 18:6a4db94011d3 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
sahilmgandhi 18:6a4db94011d3 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
sahilmgandhi 18:6a4db94011d3 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
sahilmgandhi 18:6a4db94011d3 20 * OTHER DEALINGS IN THE SOFTWARE.
sahilmgandhi 18:6a4db94011d3 21 *
sahilmgandhi 18:6a4db94011d3 22 * Except as contained in this notice, the name of Maxim Integrated
sahilmgandhi 18:6a4db94011d3 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
sahilmgandhi 18:6a4db94011d3 24 * Products, Inc. Branding Policy.
sahilmgandhi 18:6a4db94011d3 25 *
sahilmgandhi 18:6a4db94011d3 26 * The mere transfer of this software does not imply any licenses
sahilmgandhi 18:6a4db94011d3 27 * of trade secrets, proprietary technology, copyrights, patents,
sahilmgandhi 18:6a4db94011d3 28 * trademarks, maskwork rights, or any other form of intellectual
sahilmgandhi 18:6a4db94011d3 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
sahilmgandhi 18:6a4db94011d3 30 * ownership rights.
sahilmgandhi 18:6a4db94011d3 31 *******************************************************************************
sahilmgandhi 18:6a4db94011d3 32 */
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 #include "sleep_api.h"
sahilmgandhi 18:6a4db94011d3 35 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 36 #include "pwrman_regs.h"
sahilmgandhi 18:6a4db94011d3 37 #include "pwrseq_regs.h"
sahilmgandhi 18:6a4db94011d3 38 #include "ioman_regs.h"
sahilmgandhi 18:6a4db94011d3 39 #include "rtc_regs.h"
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 static mxc_uart_regs_t *stdio_uart = (mxc_uart_regs_t*)STDIO_UART;
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43 // Normal wait mode
sahilmgandhi 18:6a4db94011d3 44 void hal_sleep(void)
sahilmgandhi 18:6a4db94011d3 45 {
sahilmgandhi 18:6a4db94011d3 46 // Normal sleep mode for ARM core
sahilmgandhi 18:6a4db94011d3 47 SCB->SCR = 0;
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 __DSB();
sahilmgandhi 18:6a4db94011d3 50 __WFI();
sahilmgandhi 18:6a4db94011d3 51 }
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 // Work-around for issue of clearing power sequencer I/O flag
sahilmgandhi 18:6a4db94011d3 54 static void clearAllGPIOWUD(void)
sahilmgandhi 18:6a4db94011d3 55 {
sahilmgandhi 18:6a4db94011d3 56 uint32_t wud_req0 = MXC_IOMAN->wud_req0;
sahilmgandhi 18:6a4db94011d3 57 uint32_t wud_req1 = MXC_IOMAN->wud_req1;
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 // I/O must be a wakeup detect to clear
sahilmgandhi 18:6a4db94011d3 60 MXC_IOMAN->wud_req0 = 0xffffffff;
sahilmgandhi 18:6a4db94011d3 61 MXC_IOMAN->wud_req1 = 0xffffffff;
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 // Clear all WUDs
sahilmgandhi 18:6a4db94011d3 64 MXC_PWRMAN->wud_ctrl = (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS) | MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL;
sahilmgandhi 18:6a4db94011d3 65 MXC_PWRMAN->wud_pulse0 = 1;
sahilmgandhi 18:6a4db94011d3 66
sahilmgandhi 18:6a4db94011d3 67 // Restore WUD requests
sahilmgandhi 18:6a4db94011d3 68 MXC_IOMAN->wud_req0 = wud_req0;
sahilmgandhi 18:6a4db94011d3 69 MXC_IOMAN->wud_req1 = wud_req1;
sahilmgandhi 18:6a4db94011d3 70 }
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72 // Low-power stop mode
sahilmgandhi 18:6a4db94011d3 73 void hal_deepsleep(void)
sahilmgandhi 18:6a4db94011d3 74 {
sahilmgandhi 18:6a4db94011d3 75 __disable_irq();
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 // Wait for all STDIO characters to be sent. The UART clock will stop.
sahilmgandhi 18:6a4db94011d3 78 while (stdio_uart->status & MXC_F_UART_STATUS_TX_BUSY);
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 // Prepare for LP1
sahilmgandhi 18:6a4db94011d3 81 uint32_t reg0 = MXC_PWRSEQ->reg0;
sahilmgandhi 18:6a4db94011d3 82 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP; // disable VDD3 SVM during sleep mode
sahilmgandhi 18:6a4db94011d3 83 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP; // disable VREG18 SVM during sleep mode
sahilmgandhi 18:6a4db94011d3 84 if (reg0 & MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN) { // if real-time clock enabled during run
sahilmgandhi 18:6a4db94011d3 85 reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP; // enable real-time clock during sleep mode
sahilmgandhi 18:6a4db94011d3 86 } else {
sahilmgandhi 18:6a4db94011d3 87 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP; // disable real-time clock during sleep mode
sahilmgandhi 18:6a4db94011d3 88 }
sahilmgandhi 18:6a4db94011d3 89 reg0 |= MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP; // enable CHZY regulator during sleep mode
sahilmgandhi 18:6a4db94011d3 90 reg0 |= MXC_F_PWRSEQ_REG0_PWR_LP1; // go into LP1
sahilmgandhi 18:6a4db94011d3 91 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT; // clear first boot flag
sahilmgandhi 18:6a4db94011d3 92 MXC_PWRSEQ->reg0 = reg0;
sahilmgandhi 18:6a4db94011d3 93
sahilmgandhi 18:6a4db94011d3 94 MXC_PWRSEQ->reg3 = (MXC_PWRSEQ->reg3 & ~MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK) | (3 << MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS);
sahilmgandhi 18:6a4db94011d3 95
sahilmgandhi 18:6a4db94011d3 96 // Deep sleep for ARM core
sahilmgandhi 18:6a4db94011d3 97 SCB->SCR = SCB_SCR_SLEEPDEEP_Msk;
sahilmgandhi 18:6a4db94011d3 98
sahilmgandhi 18:6a4db94011d3 99 // clear latches for wakeup detect
sahilmgandhi 18:6a4db94011d3 100 MXC_PWRSEQ->flags = MXC_PWRSEQ->flags;
sahilmgandhi 18:6a4db94011d3 101 if (MXC_PWRSEQ->flags & MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP) {
sahilmgandhi 18:6a4db94011d3 102 // attempt work-around for I/O flag clearing issue
sahilmgandhi 18:6a4db94011d3 103 clearAllGPIOWUD();
sahilmgandhi 18:6a4db94011d3 104 MXC_PWRSEQ->flags = MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP;
sahilmgandhi 18:6a4db94011d3 105 }
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107 // Wait for pending RTC transaction
sahilmgandhi 18:6a4db94011d3 108 while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 // Ensure that the event register is clear
sahilmgandhi 18:6a4db94011d3 111 __SEV(); // set event
sahilmgandhi 18:6a4db94011d3 112 __WFE(); // clear event
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 // Enter LP1
sahilmgandhi 18:6a4db94011d3 115 __WFE();
sahilmgandhi 18:6a4db94011d3 116 // Woke up from LP1
sahilmgandhi 18:6a4db94011d3 117
sahilmgandhi 18:6a4db94011d3 118 // The RTC timer does not update until the next tick
sahilmgandhi 18:6a4db94011d3 119 uint32_t temp = MXC_RTCTMR->timer;
sahilmgandhi 18:6a4db94011d3 120 while (MXC_RTCTMR->timer == temp);
sahilmgandhi 18:6a4db94011d3 121
sahilmgandhi 18:6a4db94011d3 122 __enable_irq();
sahilmgandhi 18:6a4db94011d3 123 }