Mouse code for the MacroRat
mbed-dev/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/dfll.h@46:b156ef445742, 2017-06-03 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sat Jun 03 00:22:44 2017 +0000
- Revision:
- 46:b156ef445742
- Parent:
- 18:6a4db94011d3
Final code for internal battlebot competition.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /** |
sahilmgandhi | 18:6a4db94011d3 | 2 | * \file |
sahilmgandhi | 18:6a4db94011d3 | 3 | * |
sahilmgandhi | 18:6a4db94011d3 | 4 | * \brief DFLL management |
sahilmgandhi | 18:6a4db94011d3 | 5 | * |
sahilmgandhi | 18:6a4db94011d3 | 6 | * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. |
sahilmgandhi | 18:6a4db94011d3 | 7 | * |
sahilmgandhi | 18:6a4db94011d3 | 8 | * \asf_license_start |
sahilmgandhi | 18:6a4db94011d3 | 9 | * |
sahilmgandhi | 18:6a4db94011d3 | 10 | * \page License |
sahilmgandhi | 18:6a4db94011d3 | 11 | * |
sahilmgandhi | 18:6a4db94011d3 | 12 | * Redistribution and use in source and binary forms, with or without |
sahilmgandhi | 18:6a4db94011d3 | 13 | * modification, are permitted provided that the following conditions are met: |
sahilmgandhi | 18:6a4db94011d3 | 14 | * |
sahilmgandhi | 18:6a4db94011d3 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 16 | * this list of conditions and the following disclaimer. |
sahilmgandhi | 18:6a4db94011d3 | 17 | * |
sahilmgandhi | 18:6a4db94011d3 | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 19 | * this list of conditions and the following disclaimer in the documentation |
sahilmgandhi | 18:6a4db94011d3 | 20 | * and/or other materials provided with the distribution. |
sahilmgandhi | 18:6a4db94011d3 | 21 | * |
sahilmgandhi | 18:6a4db94011d3 | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
sahilmgandhi | 18:6a4db94011d3 | 23 | * from this software without specific prior written permission. |
sahilmgandhi | 18:6a4db94011d3 | 24 | * |
sahilmgandhi | 18:6a4db94011d3 | 25 | * 4. This software may only be redistributed and used in connection with an |
sahilmgandhi | 18:6a4db94011d3 | 26 | * Atmel microcontroller product. |
sahilmgandhi | 18:6a4db94011d3 | 27 | * |
sahilmgandhi | 18:6a4db94011d3 | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
sahilmgandhi | 18:6a4db94011d3 | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
sahilmgandhi | 18:6a4db94011d3 | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
sahilmgandhi | 18:6a4db94011d3 | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
sahilmgandhi | 18:6a4db94011d3 | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
sahilmgandhi | 18:6a4db94011d3 | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
sahilmgandhi | 18:6a4db94011d3 | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
sahilmgandhi | 18:6a4db94011d3 | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
sahilmgandhi | 18:6a4db94011d3 | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
sahilmgandhi | 18:6a4db94011d3 | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
sahilmgandhi | 18:6a4db94011d3 | 38 | * POSSIBILITY OF SUCH DAMAGE. |
sahilmgandhi | 18:6a4db94011d3 | 39 | * |
sahilmgandhi | 18:6a4db94011d3 | 40 | * \asf_license_stop |
sahilmgandhi | 18:6a4db94011d3 | 41 | * |
sahilmgandhi | 18:6a4db94011d3 | 42 | */ |
sahilmgandhi | 18:6a4db94011d3 | 43 | /* |
sahilmgandhi | 18:6a4db94011d3 | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
sahilmgandhi | 18:6a4db94011d3 | 45 | */ |
sahilmgandhi | 18:6a4db94011d3 | 46 | #ifndef CLK_DFLL_H_INCLUDED |
sahilmgandhi | 18:6a4db94011d3 | 47 | #define CLK_DFLL_H_INCLUDED |
sahilmgandhi | 18:6a4db94011d3 | 48 | |
sahilmgandhi | 18:6a4db94011d3 | 49 | #include <parts.h> |
sahilmgandhi | 18:6a4db94011d3 | 50 | #include "conf_clock.h" |
sahilmgandhi | 18:6a4db94011d3 | 51 | |
sahilmgandhi | 18:6a4db94011d3 | 52 | #if UC3L |
sahilmgandhi | 18:6a4db94011d3 | 53 | # include "uc3l/dfll.h" |
sahilmgandhi | 18:6a4db94011d3 | 54 | #elif SAM4L |
sahilmgandhi | 18:6a4db94011d3 | 55 | # include "sam4l/dfll.h" |
sahilmgandhi | 18:6a4db94011d3 | 56 | #else |
sahilmgandhi | 18:6a4db94011d3 | 57 | # error Unsupported chip type |
sahilmgandhi | 18:6a4db94011d3 | 58 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 59 | |
sahilmgandhi | 18:6a4db94011d3 | 60 | /** |
sahilmgandhi | 18:6a4db94011d3 | 61 | * \ingroup clk_group |
sahilmgandhi | 18:6a4db94011d3 | 62 | * \defgroup dfll_group DFLL Management |
sahilmgandhi | 18:6a4db94011d3 | 63 | * |
sahilmgandhi | 18:6a4db94011d3 | 64 | * A Digital Frequency Locked Loop can be used to generate a highly |
sahilmgandhi | 18:6a4db94011d3 | 65 | * accurate frequency from a slower-running reference clock, in much the |
sahilmgandhi | 18:6a4db94011d3 | 66 | * same way as a PLL. DFLLs typically have shorter startup times and |
sahilmgandhi | 18:6a4db94011d3 | 67 | * less jitter. They can also be used in open-loop mode to generate a |
sahilmgandhi | 18:6a4db94011d3 | 68 | * less accurate frequency without the use of a reference clock. |
sahilmgandhi | 18:6a4db94011d3 | 69 | * |
sahilmgandhi | 18:6a4db94011d3 | 70 | * There may be significant variations between platforms in the support |
sahilmgandhi | 18:6a4db94011d3 | 71 | * for certain features. |
sahilmgandhi | 18:6a4db94011d3 | 72 | * |
sahilmgandhi | 18:6a4db94011d3 | 73 | * \par Example: Setting up DFLL0 with default parameters and dithering enabled |
sahilmgandhi | 18:6a4db94011d3 | 74 | * |
sahilmgandhi | 18:6a4db94011d3 | 75 | * The following example shows how to configure and enable DFLL0 in |
sahilmgandhi | 18:6a4db94011d3 | 76 | * closed-loop mode using the default parameters specified through |
sahilmgandhi | 18:6a4db94011d3 | 77 | * configuration symbols. |
sahilmgandhi | 18:6a4db94011d3 | 78 | * \code |
sahilmgandhi | 18:6a4db94011d3 | 79 | dfll_enable_config_defaults(0); \endcode |
sahilmgandhi | 18:6a4db94011d3 | 80 | * |
sahilmgandhi | 18:6a4db94011d3 | 81 | * To configure and enable DFLL0 in closed-loop mode using the default |
sahilmgandhi | 18:6a4db94011d3 | 82 | * parameters and to enable specific feature like dithering for better accuracy, |
sahilmgandhi | 18:6a4db94011d3 | 83 | * you can use this initialization process. |
sahilmgandhi | 18:6a4db94011d3 | 84 | * \code |
sahilmgandhi | 18:6a4db94011d3 | 85 | struct dfll_config dfllcfg; |
sahilmgandhi | 18:6a4db94011d3 | 86 | |
sahilmgandhi | 18:6a4db94011d3 | 87 | dfll_enable_source(CONFIG_DFLL0_SOURCE); |
sahilmgandhi | 18:6a4db94011d3 | 88 | dfll_config_defaults(&dfllcfg, 0); |
sahilmgandhi | 18:6a4db94011d3 | 89 | dfll_config_enable_dithering(&dfllcfg); |
sahilmgandhi | 18:6a4db94011d3 | 90 | dfll_enable(&dfllcfg, 0); |
sahilmgandhi | 18:6a4db94011d3 | 91 | dfll_wait_for_accurate_lock(0); \endcode |
sahilmgandhi | 18:6a4db94011d3 | 92 | * |
sahilmgandhi | 18:6a4db94011d3 | 93 | * When the last function call returns, DFLL0 is running at a frequency |
sahilmgandhi | 18:6a4db94011d3 | 94 | * which matches the default configuration as accurately as possible. |
sahilmgandhi | 18:6a4db94011d3 | 95 | * Any additional alterations to the default configuration can be added |
sahilmgandhi | 18:6a4db94011d3 | 96 | * at the same place as the call to dfll_config_enable_dithering(), but |
sahilmgandhi | 18:6a4db94011d3 | 97 | * note that the DFLL will never achieve "accurate" lock if dithering is |
sahilmgandhi | 18:6a4db94011d3 | 98 | * disabled. |
sahilmgandhi | 18:6a4db94011d3 | 99 | * |
sahilmgandhi | 18:6a4db94011d3 | 100 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 101 | */ |
sahilmgandhi | 18:6a4db94011d3 | 102 | |
sahilmgandhi | 18:6a4db94011d3 | 103 | //! \name Chip-specific DFLL characteristics |
sahilmgandhi | 18:6a4db94011d3 | 104 | //@{ |
sahilmgandhi | 18:6a4db94011d3 | 105 | /** |
sahilmgandhi | 18:6a4db94011d3 | 106 | * \def NR_DFLLS |
sahilmgandhi | 18:6a4db94011d3 | 107 | * \brief Number of on-chip DFLLs. |
sahilmgandhi | 18:6a4db94011d3 | 108 | */ |
sahilmgandhi | 18:6a4db94011d3 | 109 | /** |
sahilmgandhi | 18:6a4db94011d3 | 110 | * \def DFLL_MIN_HZ |
sahilmgandhi | 18:6a4db94011d3 | 111 | * \brief Minimum frequency that the DFLL can generate. |
sahilmgandhi | 18:6a4db94011d3 | 112 | */ |
sahilmgandhi | 18:6a4db94011d3 | 113 | /** |
sahilmgandhi | 18:6a4db94011d3 | 114 | * \def DFLL_MAX_HZ |
sahilmgandhi | 18:6a4db94011d3 | 115 | * \brief Maximum frequency that the DFLL can generate. |
sahilmgandhi | 18:6a4db94011d3 | 116 | */ |
sahilmgandhi | 18:6a4db94011d3 | 117 | //@} |
sahilmgandhi | 18:6a4db94011d3 | 118 | |
sahilmgandhi | 18:6a4db94011d3 | 119 | /** |
sahilmgandhi | 18:6a4db94011d3 | 120 | * \typedef dfll_refclk_t |
sahilmgandhi | 18:6a4db94011d3 | 121 | * \brief Type used for identifying a reference clock source for the DFLL. |
sahilmgandhi | 18:6a4db94011d3 | 122 | */ |
sahilmgandhi | 18:6a4db94011d3 | 123 | |
sahilmgandhi | 18:6a4db94011d3 | 124 | //! \name DFLL Configuration |
sahilmgandhi | 18:6a4db94011d3 | 125 | //@{ |
sahilmgandhi | 18:6a4db94011d3 | 126 | |
sahilmgandhi | 18:6a4db94011d3 | 127 | /** |
sahilmgandhi | 18:6a4db94011d3 | 128 | * \struct dfll_config |
sahilmgandhi | 18:6a4db94011d3 | 129 | * \brief Hardware-specific representation of DFLL configuration. |
sahilmgandhi | 18:6a4db94011d3 | 130 | * |
sahilmgandhi | 18:6a4db94011d3 | 131 | * This structure contains one or more device-specific values |
sahilmgandhi | 18:6a4db94011d3 | 132 | * representing the current DFLL configuration. The contents of this |
sahilmgandhi | 18:6a4db94011d3 | 133 | * structure is typically different from platform to platform, and the |
sahilmgandhi | 18:6a4db94011d3 | 134 | * user should not access any fields except through the DFLL |
sahilmgandhi | 18:6a4db94011d3 | 135 | * configuration API. |
sahilmgandhi | 18:6a4db94011d3 | 136 | */ |
sahilmgandhi | 18:6a4db94011d3 | 137 | |
sahilmgandhi | 18:6a4db94011d3 | 138 | /** |
sahilmgandhi | 18:6a4db94011d3 | 139 | * \fn void dfll_config_init_open_loop_mode(struct dfll_config *cfg) |
sahilmgandhi | 18:6a4db94011d3 | 140 | * \brief Configure the DFLL configuration \a cfg for open-loop mode. |
sahilmgandhi | 18:6a4db94011d3 | 141 | * |
sahilmgandhi | 18:6a4db94011d3 | 142 | * \param cfg The DFLL configuration to be initialized. |
sahilmgandhi | 18:6a4db94011d3 | 143 | */ |
sahilmgandhi | 18:6a4db94011d3 | 144 | /** |
sahilmgandhi | 18:6a4db94011d3 | 145 | * \fn void dfll_config_init_closed_loop_mode(struct dfll_config *cfg, |
sahilmgandhi | 18:6a4db94011d3 | 146 | * dfll_refclk_t refclk, uint16_t div, uint16_t mul) |
sahilmgandhi | 18:6a4db94011d3 | 147 | * \brief Configure the DFLL configuration \a cfg for closed-loop mode. |
sahilmgandhi | 18:6a4db94011d3 | 148 | * |
sahilmgandhi | 18:6a4db94011d3 | 149 | * \param cfg The DFLL configuration to be initialized. |
sahilmgandhi | 18:6a4db94011d3 | 150 | * \param refclk The reference clock source. |
sahilmgandhi | 18:6a4db94011d3 | 151 | * \param div Reference clock divider. |
sahilmgandhi | 18:6a4db94011d3 | 152 | * \param mul Multiplier (integer part only). |
sahilmgandhi | 18:6a4db94011d3 | 153 | */ |
sahilmgandhi | 18:6a4db94011d3 | 154 | /** |
sahilmgandhi | 18:6a4db94011d3 | 155 | * \def dfll_config_defaults(cfg, dfll_id) |
sahilmgandhi | 18:6a4db94011d3 | 156 | * \brief Initialize DFLL configuration using default parameters. |
sahilmgandhi | 18:6a4db94011d3 | 157 | * |
sahilmgandhi | 18:6a4db94011d3 | 158 | * After this function returns, \a cfg will contain a configuration |
sahilmgandhi | 18:6a4db94011d3 | 159 | * which will make the DFLL run at (CONFIG_DFLLx_MUL / CONFIG_DFLLx_DIV) |
sahilmgandhi | 18:6a4db94011d3 | 160 | * times the frequency of CONFIG_DFLLx_SOURCE. The default configuration |
sahilmgandhi | 18:6a4db94011d3 | 161 | * will always use closed-loop mode with no fractional multiplier. |
sahilmgandhi | 18:6a4db94011d3 | 162 | * |
sahilmgandhi | 18:6a4db94011d3 | 163 | * \param cfg The DFLL configuration to be initialized. |
sahilmgandhi | 18:6a4db94011d3 | 164 | * \param dfll_id Use defaults for this DFLL. |
sahilmgandhi | 18:6a4db94011d3 | 165 | */ |
sahilmgandhi | 18:6a4db94011d3 | 166 | /** |
sahilmgandhi | 18:6a4db94011d3 | 167 | * \def dfll_get_default_rate(dfll_id) |
sahilmgandhi | 18:6a4db94011d3 | 168 | * \brief Return the default rate in Hz of \a dfll_id. |
sahilmgandhi | 18:6a4db94011d3 | 169 | */ |
sahilmgandhi | 18:6a4db94011d3 | 170 | |
sahilmgandhi | 18:6a4db94011d3 | 171 | /** |
sahilmgandhi | 18:6a4db94011d3 | 172 | * \fn void dfll_config_set_fractional_multiplier(struct dfll_config *cfg, |
sahilmgandhi | 18:6a4db94011d3 | 173 | * uint16_t mul_i, uint16_t mul_f) |
sahilmgandhi | 18:6a4db94011d3 | 174 | * \brief Set a fractional multiplier. |
sahilmgandhi | 18:6a4db94011d3 | 175 | * |
sahilmgandhi | 18:6a4db94011d3 | 176 | * This function has no effect in open-loop mode, and is only available |
sahilmgandhi | 18:6a4db94011d3 | 177 | * on devices which support fractional multipliers. |
sahilmgandhi | 18:6a4db94011d3 | 178 | * |
sahilmgandhi | 18:6a4db94011d3 | 179 | * The fractional part of the multiplier is assumed to be 16 bits. The |
sahilmgandhi | 18:6a4db94011d3 | 180 | * low-level driver will make sure to shift this value to match the |
sahilmgandhi | 18:6a4db94011d3 | 181 | * hardware if necessary. |
sahilmgandhi | 18:6a4db94011d3 | 182 | * |
sahilmgandhi | 18:6a4db94011d3 | 183 | * \param cfg The DFLL configuration to be modified. |
sahilmgandhi | 18:6a4db94011d3 | 184 | * \param mul_i Integer part of multiplier. |
sahilmgandhi | 18:6a4db94011d3 | 185 | * \param mul_f Fractional part of multiplier. |
sahilmgandhi | 18:6a4db94011d3 | 186 | */ |
sahilmgandhi | 18:6a4db94011d3 | 187 | /** |
sahilmgandhi | 18:6a4db94011d3 | 188 | * \fn void dfll_config_enable_dithering(struct dfll_config *cfg) |
sahilmgandhi | 18:6a4db94011d3 | 189 | * \brief Enable dithering for more accurate frequency generation. |
sahilmgandhi | 18:6a4db94011d3 | 190 | * |
sahilmgandhi | 18:6a4db94011d3 | 191 | * The fine LSB input to the VCO is dithered to achieve fractional |
sahilmgandhi | 18:6a4db94011d3 | 192 | * approximation to the correct multiplication ratio. |
sahilmgandhi | 18:6a4db94011d3 | 193 | * |
sahilmgandhi | 18:6a4db94011d3 | 194 | * \param cfg The DFLL configuration to be modified. |
sahilmgandhi | 18:6a4db94011d3 | 195 | */ |
sahilmgandhi | 18:6a4db94011d3 | 196 | /** |
sahilmgandhi | 18:6a4db94011d3 | 197 | * \fn void dfll_config_disable_dithering(struct dfll_config *cfg) |
sahilmgandhi | 18:6a4db94011d3 | 198 | * \brief Disable dithering. |
sahilmgandhi | 18:6a4db94011d3 | 199 | * |
sahilmgandhi | 18:6a4db94011d3 | 200 | * \see dfll_config_enable_dithering() |
sahilmgandhi | 18:6a4db94011d3 | 201 | * |
sahilmgandhi | 18:6a4db94011d3 | 202 | * \param cfg The DFLL configuration to be modified. |
sahilmgandhi | 18:6a4db94011d3 | 203 | */ |
sahilmgandhi | 18:6a4db94011d3 | 204 | /** |
sahilmgandhi | 18:6a4db94011d3 | 205 | * \fn void dfll_config_set_initial_tuning(struct dfll_config *cfg, |
sahilmgandhi | 18:6a4db94011d3 | 206 | * uint16_t coarse, uint16_t fine) |
sahilmgandhi | 18:6a4db94011d3 | 207 | * \brief Set initial VCO tuning. |
sahilmgandhi | 18:6a4db94011d3 | 208 | * |
sahilmgandhi | 18:6a4db94011d3 | 209 | * In open loop mode, this will determine the frequency of the output. |
sahilmgandhi | 18:6a4db94011d3 | 210 | * |
sahilmgandhi | 18:6a4db94011d3 | 211 | * In closed loop mode, this will provide an initial estimate of the VCO |
sahilmgandhi | 18:6a4db94011d3 | 212 | * tuning. While the DFLL will automatically adjust these values to |
sahilmgandhi | 18:6a4db94011d3 | 213 | * match the desired output frequency, careful selection of initial |
sahilmgandhi | 18:6a4db94011d3 | 214 | * values might reduce the time to achieve coarse and fine lock. |
sahilmgandhi | 18:6a4db94011d3 | 215 | * |
sahilmgandhi | 18:6a4db94011d3 | 216 | * \param cfg The DFLL configuration to be modified. |
sahilmgandhi | 18:6a4db94011d3 | 217 | * \param coarse Coarse tuning of the frequency generator. |
sahilmgandhi | 18:6a4db94011d3 | 218 | * \param fine Fine tuning of the frequency generator. |
sahilmgandhi | 18:6a4db94011d3 | 219 | */ |
sahilmgandhi | 18:6a4db94011d3 | 220 | /** |
sahilmgandhi | 18:6a4db94011d3 | 221 | * \fn void dfll_config_set_max_step(struct dfll_config *cfg, |
sahilmgandhi | 18:6a4db94011d3 | 222 | * uint16_t coarse, uint16_t fine) |
sahilmgandhi | 18:6a4db94011d3 | 223 | * \brief Set the maximum VCO tuning step size. |
sahilmgandhi | 18:6a4db94011d3 | 224 | * |
sahilmgandhi | 18:6a4db94011d3 | 225 | * This function has no effect in open-loop mode. |
sahilmgandhi | 18:6a4db94011d3 | 226 | * |
sahilmgandhi | 18:6a4db94011d3 | 227 | * By default, both of these values are set to 50% of their respective |
sahilmgandhi | 18:6a4db94011d3 | 228 | * maximums. It is not recommended to set the values any higher than |
sahilmgandhi | 18:6a4db94011d3 | 229 | * this, but setting them lower might reduce the frequency overshoot at |
sahilmgandhi | 18:6a4db94011d3 | 230 | * the expense of longer time to achieve coarse and/or fine lock. |
sahilmgandhi | 18:6a4db94011d3 | 231 | * |
sahilmgandhi | 18:6a4db94011d3 | 232 | * \param cfg The DFLL configuration to be modified |
sahilmgandhi | 18:6a4db94011d3 | 233 | * \param coarse The maximum step size of the coarse VCO tuning. |
sahilmgandhi | 18:6a4db94011d3 | 234 | * \param fine The maximum step size of the fine VCO tuning. |
sahilmgandhi | 18:6a4db94011d3 | 235 | */ |
sahilmgandhi | 18:6a4db94011d3 | 236 | /** |
sahilmgandhi | 18:6a4db94011d3 | 237 | * \fn void dfll_config_enable_ssg(struct dfll_config *cfg, |
sahilmgandhi | 18:6a4db94011d3 | 238 | * uint16_t amplitude, uint16_t step_size) |
sahilmgandhi | 18:6a4db94011d3 | 239 | * \brief Enable Spread Spectrum Generator. |
sahilmgandhi | 18:6a4db94011d3 | 240 | * |
sahilmgandhi | 18:6a4db94011d3 | 241 | * \param cfg The DFLL configuration to be modified. |
sahilmgandhi | 18:6a4db94011d3 | 242 | * \param amplitude The amplitude of the spread spectrum. |
sahilmgandhi | 18:6a4db94011d3 | 243 | * \param step_size The step size of the spread spectrum. |
sahilmgandhi | 18:6a4db94011d3 | 244 | */ |
sahilmgandhi | 18:6a4db94011d3 | 245 | /** |
sahilmgandhi | 18:6a4db94011d3 | 246 | * \fn void dfll_config_disable_ssg(struct dfll_config *cfg) |
sahilmgandhi | 18:6a4db94011d3 | 247 | * \brief Disable Spread Spectrum Generator. |
sahilmgandhi | 18:6a4db94011d3 | 248 | * |
sahilmgandhi | 18:6a4db94011d3 | 249 | * \param cfg The DFLL configuration to be modified. |
sahilmgandhi | 18:6a4db94011d3 | 250 | */ |
sahilmgandhi | 18:6a4db94011d3 | 251 | //@} |
sahilmgandhi | 18:6a4db94011d3 | 252 | |
sahilmgandhi | 18:6a4db94011d3 | 253 | //! \name Interaction with the DFLL hardware |
sahilmgandhi | 18:6a4db94011d3 | 254 | //@{ |
sahilmgandhi | 18:6a4db94011d3 | 255 | /** |
sahilmgandhi | 18:6a4db94011d3 | 256 | * \fn void dfll_enable_open_loop(const struct dfll_config *cfg, |
sahilmgandhi | 18:6a4db94011d3 | 257 | * unsigned int dfll_id) |
sahilmgandhi | 18:6a4db94011d3 | 258 | * \brief Activate the configuration \a cfg and enable DFLL \a dfll_id |
sahilmgandhi | 18:6a4db94011d3 | 259 | * in open-loop mode. |
sahilmgandhi | 18:6a4db94011d3 | 260 | * |
sahilmgandhi | 18:6a4db94011d3 | 261 | * \pre The configuration in \a cfg must represent an open-loop |
sahilmgandhi | 18:6a4db94011d3 | 262 | * configuration. |
sahilmgandhi | 18:6a4db94011d3 | 263 | * |
sahilmgandhi | 18:6a4db94011d3 | 264 | * \param cfg The configuration to be activated. |
sahilmgandhi | 18:6a4db94011d3 | 265 | * \param dfll_id The ID of the DFLL to be enabled. |
sahilmgandhi | 18:6a4db94011d3 | 266 | */ |
sahilmgandhi | 18:6a4db94011d3 | 267 | /** |
sahilmgandhi | 18:6a4db94011d3 | 268 | * \fn void dfll_enable_closed_loop(const struct dfll_config *cfg, |
sahilmgandhi | 18:6a4db94011d3 | 269 | * unsigned int dfll_id) |
sahilmgandhi | 18:6a4db94011d3 | 270 | * \brief Activate the configuration \a cfg and enable DFLL \a dfll_id |
sahilmgandhi | 18:6a4db94011d3 | 271 | * in closed-loop mode. |
sahilmgandhi | 18:6a4db94011d3 | 272 | * |
sahilmgandhi | 18:6a4db94011d3 | 273 | * \pre The configuration in \a cfg must represent a closed-loop |
sahilmgandhi | 18:6a4db94011d3 | 274 | * configuration. |
sahilmgandhi | 18:6a4db94011d3 | 275 | * |
sahilmgandhi | 18:6a4db94011d3 | 276 | * \param cfg The configuration to be activated. |
sahilmgandhi | 18:6a4db94011d3 | 277 | * \param dfll_id The ID of the DFLL to be enabled. |
sahilmgandhi | 18:6a4db94011d3 | 278 | */ |
sahilmgandhi | 18:6a4db94011d3 | 279 | /** |
sahilmgandhi | 18:6a4db94011d3 | 280 | * \fn void dfll_disable_open_loop(unsigned int dfll_id) |
sahilmgandhi | 18:6a4db94011d3 | 281 | * \brief Disable the DFLL identified by \a dfll_id. |
sahilmgandhi | 18:6a4db94011d3 | 282 | * |
sahilmgandhi | 18:6a4db94011d3 | 283 | * \pre The DFLL must have been enabled in open loop mode. |
sahilmgandhi | 18:6a4db94011d3 | 284 | * |
sahilmgandhi | 18:6a4db94011d3 | 285 | * \param dfll_id The ID of the DFLL to be disabled. |
sahilmgandhi | 18:6a4db94011d3 | 286 | */ |
sahilmgandhi | 18:6a4db94011d3 | 287 | /** |
sahilmgandhi | 18:6a4db94011d3 | 288 | * \fn void dfll_disable_closed_loop(unsigned int dfll_id) |
sahilmgandhi | 18:6a4db94011d3 | 289 | * \brief Disable the DFLL identified by \a dfll_id. |
sahilmgandhi | 18:6a4db94011d3 | 290 | * |
sahilmgandhi | 18:6a4db94011d3 | 291 | * \pre The DFLL must have been enabled in closed loop mode. |
sahilmgandhi | 18:6a4db94011d3 | 292 | * |
sahilmgandhi | 18:6a4db94011d3 | 293 | * \param dfll_id The ID of the DFLL to be disabled. |
sahilmgandhi | 18:6a4db94011d3 | 294 | */ |
sahilmgandhi | 18:6a4db94011d3 | 295 | /** |
sahilmgandhi | 18:6a4db94011d3 | 296 | * \fn bool dfll_is_coarse_locked(unsigned int dfll_id) |
sahilmgandhi | 18:6a4db94011d3 | 297 | * \brief Determine whether or not a DFLL has achieved coarse lock. |
sahilmgandhi | 18:6a4db94011d3 | 298 | * |
sahilmgandhi | 18:6a4db94011d3 | 299 | * \param dfll_id The ID of the DFLL to check. |
sahilmgandhi | 18:6a4db94011d3 | 300 | * |
sahilmgandhi | 18:6a4db94011d3 | 301 | * \retval true The DFLL has determined the final value of the coarse |
sahilmgandhi | 18:6a4db94011d3 | 302 | * VCO tuning value. |
sahilmgandhi | 18:6a4db94011d3 | 303 | * \retval false The DFLL has not yet determined the coarse VCO tuning |
sahilmgandhi | 18:6a4db94011d3 | 304 | * value, or has not been enabled. |
sahilmgandhi | 18:6a4db94011d3 | 305 | */ |
sahilmgandhi | 18:6a4db94011d3 | 306 | /** |
sahilmgandhi | 18:6a4db94011d3 | 307 | * \fn bool dfll_is_fine_locked(unsigned int dfll_id) |
sahilmgandhi | 18:6a4db94011d3 | 308 | * \brief Determine whether or not a DFLL has achieved fine lock. |
sahilmgandhi | 18:6a4db94011d3 | 309 | * |
sahilmgandhi | 18:6a4db94011d3 | 310 | * \param dfll_id The ID of the DFLL to check. |
sahilmgandhi | 18:6a4db94011d3 | 311 | * |
sahilmgandhi | 18:6a4db94011d3 | 312 | * \retval true The DFLL has determined the final value of the fine VCO |
sahilmgandhi | 18:6a4db94011d3 | 313 | * tuning value. |
sahilmgandhi | 18:6a4db94011d3 | 314 | * \retval false The DFLL has not yet determined the fine VCO tuning |
sahilmgandhi | 18:6a4db94011d3 | 315 | * value, or has not been enabled. |
sahilmgandhi | 18:6a4db94011d3 | 316 | */ |
sahilmgandhi | 18:6a4db94011d3 | 317 | /** |
sahilmgandhi | 18:6a4db94011d3 | 318 | * \fn bool dfll_is_accurate_locked(unsigned int dfll_id) |
sahilmgandhi | 18:6a4db94011d3 | 319 | * \brief Determine whether or not a DFLL has achieved accurate lock. |
sahilmgandhi | 18:6a4db94011d3 | 320 | * |
sahilmgandhi | 18:6a4db94011d3 | 321 | * \param dfll_id The ID of the DFLL to check. |
sahilmgandhi | 18:6a4db94011d3 | 322 | * |
sahilmgandhi | 18:6a4db94011d3 | 323 | * \retval true The DFLL has determined the final dithering duty cycle. |
sahilmgandhi | 18:6a4db94011d3 | 324 | * \retval false The DFLL has not yet determined the dithering duty |
sahilmgandhi | 18:6a4db94011d3 | 325 | * cycle, or has not been enabled with dithering enabled. |
sahilmgandhi | 18:6a4db94011d3 | 326 | */ |
sahilmgandhi | 18:6a4db94011d3 | 327 | /** |
sahilmgandhi | 18:6a4db94011d3 | 328 | * \fn void dfll_enable_source(enum dfll_refclk_t src) |
sahilmgandhi | 18:6a4db94011d3 | 329 | * \brief Enable the source of the dfll. |
sahilmgandhi | 18:6a4db94011d3 | 330 | * The source is enabled, if the source is not already running. |
sahilmgandhi | 18:6a4db94011d3 | 331 | * |
sahilmgandhi | 18:6a4db94011d3 | 332 | * \param dfll_source src The ID of the DFLL source to enable. |
sahilmgandhi | 18:6a4db94011d3 | 333 | */ |
sahilmgandhi | 18:6a4db94011d3 | 334 | /** |
sahilmgandhi | 18:6a4db94011d3 | 335 | * \fn void dfll_enable_config_defaults(unsigned int dfll_id) |
sahilmgandhi | 18:6a4db94011d3 | 336 | * \brief Enable the dfll with the default configuration. |
sahilmgandhi | 18:6a4db94011d3 | 337 | * DFLL is enabled, if the DFLL is not already locked. |
sahilmgandhi | 18:6a4db94011d3 | 338 | * |
sahilmgandhi | 18:6a4db94011d3 | 339 | * \param dfll_id The ID of the DFLL to enable. |
sahilmgandhi | 18:6a4db94011d3 | 340 | */ |
sahilmgandhi | 18:6a4db94011d3 | 341 | |
sahilmgandhi | 18:6a4db94011d3 | 342 | /** |
sahilmgandhi | 18:6a4db94011d3 | 343 | * \brief Wait for the DFLL identified by \a dfll_id to achieve coarse |
sahilmgandhi | 18:6a4db94011d3 | 344 | * lock. |
sahilmgandhi | 18:6a4db94011d3 | 345 | * |
sahilmgandhi | 18:6a4db94011d3 | 346 | * \param dfll_id The ID of the DFLL to wait for. |
sahilmgandhi | 18:6a4db94011d3 | 347 | * |
sahilmgandhi | 18:6a4db94011d3 | 348 | * \retval STATUS_OK The DFLL has achieved coarse lock. |
sahilmgandhi | 18:6a4db94011d3 | 349 | * \retval ERR_TIMEOUT Timed out waiting for lock. |
sahilmgandhi | 18:6a4db94011d3 | 350 | */ |
sahilmgandhi | 18:6a4db94011d3 | 351 | static inline int dfll_wait_for_coarse_lock(unsigned int dfll_id) |
sahilmgandhi | 18:6a4db94011d3 | 352 | { |
sahilmgandhi | 18:6a4db94011d3 | 353 | /* TODO: Add timeout mechanism */ |
sahilmgandhi | 18:6a4db94011d3 | 354 | while (!dfll_is_coarse_locked(dfll_id)) { |
sahilmgandhi | 18:6a4db94011d3 | 355 | /* Do nothing */ |
sahilmgandhi | 18:6a4db94011d3 | 356 | } |
sahilmgandhi | 18:6a4db94011d3 | 357 | |
sahilmgandhi | 18:6a4db94011d3 | 358 | return 0; |
sahilmgandhi | 18:6a4db94011d3 | 359 | } |
sahilmgandhi | 18:6a4db94011d3 | 360 | |
sahilmgandhi | 18:6a4db94011d3 | 361 | /** |
sahilmgandhi | 18:6a4db94011d3 | 362 | * \brief Wait for the DFLL identified by \a dfll_id to achieve fine |
sahilmgandhi | 18:6a4db94011d3 | 363 | * lock. |
sahilmgandhi | 18:6a4db94011d3 | 364 | * |
sahilmgandhi | 18:6a4db94011d3 | 365 | * \param dfll_id The ID of the DFLL to wait for. |
sahilmgandhi | 18:6a4db94011d3 | 366 | * |
sahilmgandhi | 18:6a4db94011d3 | 367 | * \retval STATUS_OK The DFLL has achieved fine lock. |
sahilmgandhi | 18:6a4db94011d3 | 368 | * \retval ERR_TIMEOUT Timed out waiting for lock. |
sahilmgandhi | 18:6a4db94011d3 | 369 | */ |
sahilmgandhi | 18:6a4db94011d3 | 370 | static inline int dfll_wait_for_fine_lock(unsigned int dfll_id) |
sahilmgandhi | 18:6a4db94011d3 | 371 | { |
sahilmgandhi | 18:6a4db94011d3 | 372 | /* TODO: Add timeout mechanism */ |
sahilmgandhi | 18:6a4db94011d3 | 373 | while (!dfll_is_fine_locked(dfll_id)) { |
sahilmgandhi | 18:6a4db94011d3 | 374 | /* Do nothing */ |
sahilmgandhi | 18:6a4db94011d3 | 375 | } |
sahilmgandhi | 18:6a4db94011d3 | 376 | |
sahilmgandhi | 18:6a4db94011d3 | 377 | return 0; |
sahilmgandhi | 18:6a4db94011d3 | 378 | } |
sahilmgandhi | 18:6a4db94011d3 | 379 | |
sahilmgandhi | 18:6a4db94011d3 | 380 | /** |
sahilmgandhi | 18:6a4db94011d3 | 381 | * \brief Wait for the DFLL identified by \a dfll_id to achieve accurate |
sahilmgandhi | 18:6a4db94011d3 | 382 | * lock. |
sahilmgandhi | 18:6a4db94011d3 | 383 | * |
sahilmgandhi | 18:6a4db94011d3 | 384 | * \param dfll_id The ID of the DFLL to wait for. |
sahilmgandhi | 18:6a4db94011d3 | 385 | * |
sahilmgandhi | 18:6a4db94011d3 | 386 | * \retval STATUS_OK The DFLL has achieved accurate lock. |
sahilmgandhi | 18:6a4db94011d3 | 387 | * \retval ERR_TIMEOUT Timed out waiting for lock. |
sahilmgandhi | 18:6a4db94011d3 | 388 | */ |
sahilmgandhi | 18:6a4db94011d3 | 389 | static inline int dfll_wait_for_accurate_lock(unsigned int dfll_id) |
sahilmgandhi | 18:6a4db94011d3 | 390 | { |
sahilmgandhi | 18:6a4db94011d3 | 391 | /* TODO: Add timeout mechanism */ |
sahilmgandhi | 18:6a4db94011d3 | 392 | while (!dfll_is_accurate_locked(dfll_id)) { |
sahilmgandhi | 18:6a4db94011d3 | 393 | /* Do nothing */ |
sahilmgandhi | 18:6a4db94011d3 | 394 | } |
sahilmgandhi | 18:6a4db94011d3 | 395 | |
sahilmgandhi | 18:6a4db94011d3 | 396 | return 0; |
sahilmgandhi | 18:6a4db94011d3 | 397 | } |
sahilmgandhi | 18:6a4db94011d3 | 398 | |
sahilmgandhi | 18:6a4db94011d3 | 399 | //@} |
sahilmgandhi | 18:6a4db94011d3 | 400 | //! @} |
sahilmgandhi | 18:6a4db94011d3 | 401 | |
sahilmgandhi | 18:6a4db94011d3 | 402 | #endif /* CLK_DFLL_H_INCLUDED */ |