MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Atmel/TARGET_SAM_CortexM4/objects.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2015 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #ifndef MBED_OBJECTS_H
sahilmgandhi 18:6a4db94011d3 17 #define MBED_OBJECTS_H
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 20 #include "PortNames.h"
sahilmgandhi 18:6a4db94011d3 21 #include "PeripheralNames.h"
sahilmgandhi 18:6a4db94011d3 22 #include "gpio_object.h"
sahilmgandhi 18:6a4db94011d3 23 #include "serial_platform.h"
sahilmgandhi 18:6a4db94011d3 24 #include "adc2.h"
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 27 extern "C" {
sahilmgandhi 18:6a4db94011d3 28 #endif
sahilmgandhi 18:6a4db94011d3 29
sahilmgandhi 18:6a4db94011d3 30 struct waveconfig_t {
sahilmgandhi 18:6a4db94011d3 31 /** Internal clock signals selection. */
sahilmgandhi 18:6a4db94011d3 32 uint32_t ul_intclock;
sahilmgandhi 18:6a4db94011d3 33 /** Waveform frequency (in Hz). */
sahilmgandhi 18:6a4db94011d3 34 uint16_t us_frequency;
sahilmgandhi 18:6a4db94011d3 35 /** Duty cycle in percent (positive).*/
sahilmgandhi 18:6a4db94011d3 36 uint16_t us_dutycycle;
sahilmgandhi 18:6a4db94011d3 37 };
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 struct gpio_irq_s {
sahilmgandhi 18:6a4db94011d3 40 uint32_t pin;
sahilmgandhi 18:6a4db94011d3 41 uint32_t irqmask;
sahilmgandhi 18:6a4db94011d3 42 };
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 struct port_s {
sahilmgandhi 18:6a4db94011d3 45 PortName port;
sahilmgandhi 18:6a4db94011d3 46 uint32_t mask;
sahilmgandhi 18:6a4db94011d3 47 uint8_t mode;
sahilmgandhi 18:6a4db94011d3 48 uint8_t direction;
sahilmgandhi 18:6a4db94011d3 49 };
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 struct serial_s {
sahilmgandhi 18:6a4db94011d3 52 UARTName uart;
sahilmgandhi 18:6a4db94011d3 53 usart_serial_options_t uart_serial_options;
sahilmgandhi 18:6a4db94011d3 54 #if DEVICE_SERIAL_ASYNCH
sahilmgandhi 18:6a4db94011d3 55 uint8_t actrec;
sahilmgandhi 18:6a4db94011d3 56 uint8_t acttra;
sahilmgandhi 18:6a4db94011d3 57 uint32_t events;
sahilmgandhi 18:6a4db94011d3 58 #endif
sahilmgandhi 18:6a4db94011d3 59 };
sahilmgandhi 18:6a4db94011d3 60
sahilmgandhi 18:6a4db94011d3 61 struct analogin_s {
sahilmgandhi 18:6a4db94011d3 62 enum adc_channel_num channel;
sahilmgandhi 18:6a4db94011d3 63 };
sahilmgandhi 18:6a4db94011d3 64
sahilmgandhi 18:6a4db94011d3 65 struct pwmout_s {
sahilmgandhi 18:6a4db94011d3 66 uint32_t channel;
sahilmgandhi 18:6a4db94011d3 67 uint32_t ioline;
sahilmgandhi 18:6a4db94011d3 68 uint32_t pin;
sahilmgandhi 18:6a4db94011d3 69 uint32_t prescalarindex;
sahilmgandhi 18:6a4db94011d3 70 struct waveconfig_t waveconfig;
sahilmgandhi 18:6a4db94011d3 71 };
sahilmgandhi 18:6a4db94011d3 72
sahilmgandhi 18:6a4db94011d3 73 struct i2c_s {
sahilmgandhi 18:6a4db94011d3 74 Twi * i2c_base;
sahilmgandhi 18:6a4db94011d3 75 Flexcom * flexcom;
sahilmgandhi 18:6a4db94011d3 76 uint8_t is_slave;
sahilmgandhi 18:6a4db94011d3 77 uint8_t module_number;
sahilmgandhi 18:6a4db94011d3 78 uint32_t speed;
sahilmgandhi 18:6a4db94011d3 79 uint32_t master_clk;
sahilmgandhi 18:6a4db94011d3 80 uint32_t address;
sahilmgandhi 18:6a4db94011d3 81 #if DEVICE_I2C_ASYNCH
sahilmgandhi 18:6a4db94011d3 82 Pdc * pdc;
sahilmgandhi 18:6a4db94011d3 83 uint8_t dma_usage;
sahilmgandhi 18:6a4db94011d3 84 IRQn_Type irq_type;
sahilmgandhi 18:6a4db94011d3 85 uint32_t event;
sahilmgandhi 18:6a4db94011d3 86 uint32_t stop;
sahilmgandhi 18:6a4db94011d3 87 #endif
sahilmgandhi 18:6a4db94011d3 88 };
sahilmgandhi 18:6a4db94011d3 89 struct spi_s {
sahilmgandhi 18:6a4db94011d3 90 Spi * spi_base;
sahilmgandhi 18:6a4db94011d3 91 Flexcom * flexcom;
sahilmgandhi 18:6a4db94011d3 92 uint8_t cs;
sahilmgandhi 18:6a4db94011d3 93 uint8_t polarity;
sahilmgandhi 18:6a4db94011d3 94 uint8_t phase;
sahilmgandhi 18:6a4db94011d3 95 uint32_t transferrate;
sahilmgandhi 18:6a4db94011d3 96 uint8_t is_slave;
sahilmgandhi 18:6a4db94011d3 97 uint8_t module_number;
sahilmgandhi 18:6a4db94011d3 98 #if DEVICE_SPI_ASYNCH
sahilmgandhi 18:6a4db94011d3 99 Pdc * pdc;
sahilmgandhi 18:6a4db94011d3 100 uint8_t dma_usage;
sahilmgandhi 18:6a4db94011d3 101 IRQn_Type irq_type;
sahilmgandhi 18:6a4db94011d3 102 uint32_t event;
sahilmgandhi 18:6a4db94011d3 103 #endif
sahilmgandhi 18:6a4db94011d3 104 };
sahilmgandhi 18:6a4db94011d3 105
sahilmgandhi 18:6a4db94011d3 106 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 107 }
sahilmgandhi 18:6a4db94011d3 108 #endif
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 #endif