MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Atmel/TARGET_SAM_CortexM4/i2c_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2015 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16
sahilmgandhi 18:6a4db94011d3 17 #include "device.h"
sahilmgandhi 18:6a4db94011d3 18 #include "buffer.h"
sahilmgandhi 18:6a4db94011d3 19 #include "dma_api.h"
sahilmgandhi 18:6a4db94011d3 20 #include "i2c_api.h"
sahilmgandhi 18:6a4db94011d3 21 #include "PeripheralPins.h"
sahilmgandhi 18:6a4db94011d3 22 #include "twi.h"
sahilmgandhi 18:6a4db94011d3 23 #include "pdc.h"
sahilmgandhi 18:6a4db94011d3 24 #include "mbed_assert.h"
sahilmgandhi 18:6a4db94011d3 25 #include "ioport.h"
sahilmgandhi 18:6a4db94011d3 26
sahilmgandhi 18:6a4db94011d3 27 /**
sahilmgandhi 18:6a4db94011d3 28 * \defgroup GeneralI2C I2C Configuration Functions
sahilmgandhi 18:6a4db94011d3 29 * @{
sahilmgandhi 18:6a4db94011d3 30 */
sahilmgandhi 18:6a4db94011d3 31
sahilmgandhi 18:6a4db94011d3 32 /** TWI Bus Clock 400kHz */
sahilmgandhi 18:6a4db94011d3 33 extern uint8_t g_sys_init;
sahilmgandhi 18:6a4db94011d3 34
sahilmgandhi 18:6a4db94011d3 35 #define TWI_CLK (400000u)
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37 #define ADDR_LENGTH 0
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 #define MAX_I2C 8
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 extern uint32_t twi_mk_addr(const uint8_t *addr, int len);
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43 void pinmap_find_i2c_info(Twi *sercombase, i2c_t *obj)
sahilmgandhi 18:6a4db94011d3 44 {
sahilmgandhi 18:6a4db94011d3 45 if(sercombase==TWI0) {
sahilmgandhi 18:6a4db94011d3 46 obj->i2c.flexcom=FLEXCOM0;
sahilmgandhi 18:6a4db94011d3 47 obj->i2c.module_number=0;
sahilmgandhi 18:6a4db94011d3 48 obj->i2c.pdc =PDC_TWI0;
sahilmgandhi 18:6a4db94011d3 49 obj->i2c.irq_type=FLEXCOM0_IRQn;
sahilmgandhi 18:6a4db94011d3 50 } else if(sercombase==TWI1) {
sahilmgandhi 18:6a4db94011d3 51 obj->i2c.flexcom=FLEXCOM1;
sahilmgandhi 18:6a4db94011d3 52 obj->i2c.module_number=1;
sahilmgandhi 18:6a4db94011d3 53 obj->i2c.pdc =PDC_TWI1;
sahilmgandhi 18:6a4db94011d3 54 obj->i2c.irq_type=FLEXCOM1_IRQn;
sahilmgandhi 18:6a4db94011d3 55 } else if(sercombase==TWI2) {
sahilmgandhi 18:6a4db94011d3 56 obj->i2c.flexcom=FLEXCOM2;
sahilmgandhi 18:6a4db94011d3 57 obj->i2c.module_number=2;
sahilmgandhi 18:6a4db94011d3 58 obj->i2c.pdc =PDC_TWI2;
sahilmgandhi 18:6a4db94011d3 59 obj->i2c.irq_type=FLEXCOM2_IRQn;
sahilmgandhi 18:6a4db94011d3 60 } else if(sercombase==TWI3) {
sahilmgandhi 18:6a4db94011d3 61 obj->i2c.flexcom=FLEXCOM3;
sahilmgandhi 18:6a4db94011d3 62 obj->i2c.module_number=3;
sahilmgandhi 18:6a4db94011d3 63 obj->i2c.pdc =PDC_TWI3;
sahilmgandhi 18:6a4db94011d3 64 obj->i2c.irq_type=FLEXCOM3_IRQn;
sahilmgandhi 18:6a4db94011d3 65 } else if(sercombase==TWI4) {
sahilmgandhi 18:6a4db94011d3 66 obj->i2c.flexcom=FLEXCOM4;
sahilmgandhi 18:6a4db94011d3 67 obj->i2c.module_number=4;
sahilmgandhi 18:6a4db94011d3 68 obj->i2c.pdc =PDC_TWI4;
sahilmgandhi 18:6a4db94011d3 69 obj->i2c.irq_type=FLEXCOM4_IRQn;
sahilmgandhi 18:6a4db94011d3 70 } else if(sercombase==TWI5) {
sahilmgandhi 18:6a4db94011d3 71 obj->i2c.flexcom=FLEXCOM5;
sahilmgandhi 18:6a4db94011d3 72 obj->i2c.module_number=5;
sahilmgandhi 18:6a4db94011d3 73 obj->i2c.pdc =PDC_TWI5;
sahilmgandhi 18:6a4db94011d3 74 obj->i2c.irq_type=FLEXCOM5_IRQn;
sahilmgandhi 18:6a4db94011d3 75 } else if(sercombase==TWI6) {
sahilmgandhi 18:6a4db94011d3 76 obj->i2c.flexcom=FLEXCOM6;
sahilmgandhi 18:6a4db94011d3 77 obj->i2c.module_number=6;
sahilmgandhi 18:6a4db94011d3 78 obj->i2c.pdc =PDC_TWI6;
sahilmgandhi 18:6a4db94011d3 79 obj->i2c.irq_type=FLEXCOM6_IRQn;
sahilmgandhi 18:6a4db94011d3 80 } else if(sercombase==TWI7) {
sahilmgandhi 18:6a4db94011d3 81 obj->i2c.flexcom=FLEXCOM7;
sahilmgandhi 18:6a4db94011d3 82 obj->i2c.module_number=7;
sahilmgandhi 18:6a4db94011d3 83 obj->i2c.pdc =PDC_TWI7;
sahilmgandhi 18:6a4db94011d3 84 obj->i2c.irq_type=FLEXCOM7_IRQn;
sahilmgandhi 18:6a4db94011d3 85 } else {
sahilmgandhi 18:6a4db94011d3 86 obj->i2c.flexcom=(Flexcom *)NC;
sahilmgandhi 18:6a4db94011d3 87 obj->i2c.module_number=0;
sahilmgandhi 18:6a4db94011d3 88 obj->i2c.pdc =(Pdc *) NC;
sahilmgandhi 18:6a4db94011d3 89 }
sahilmgandhi 18:6a4db94011d3 90 }
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92
sahilmgandhi 18:6a4db94011d3 93 /** Initialize the I2C peripheral. It sets the default parameters for I2C
sahilmgandhi 18:6a4db94011d3 94 * peripheral, and configure its specifieds pins.
sahilmgandhi 18:6a4db94011d3 95 * @param obj The i2c object
sahilmgandhi 18:6a4db94011d3 96 * @param sda The sda pin
sahilmgandhi 18:6a4db94011d3 97 * @param scl The scl pin
sahilmgandhi 18:6a4db94011d3 98 */
sahilmgandhi 18:6a4db94011d3 99 void i2c_init(i2c_t *obj, PinName sda, PinName scl)
sahilmgandhi 18:6a4db94011d3 100 {
sahilmgandhi 18:6a4db94011d3 101 MBED_ASSERT(obj);
sahilmgandhi 18:6a4db94011d3 102 MBED_ASSERT(sda !=NC && scl!=NC );
sahilmgandhi 18:6a4db94011d3 103
sahilmgandhi 18:6a4db94011d3 104 if (g_sys_init == 0) {
sahilmgandhi 18:6a4db94011d3 105 sysclk_init();
sahilmgandhi 18:6a4db94011d3 106 board_init();
sahilmgandhi 18:6a4db94011d3 107 g_sys_init = 1;
sahilmgandhi 18:6a4db94011d3 108 }
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 Twi* sda_base = (Twi*)pinmap_peripheral(sda, PinMap_I2C_SDA);
sahilmgandhi 18:6a4db94011d3 112 Twi* scl_base = (Twi*)pinmap_peripheral(scl, PinMap_I2C_SCL);
sahilmgandhi 18:6a4db94011d3 113 Twi* I2cBase = (Twi*)pinmap_merge((uint32_t)sda_base, (uint32_t)scl_base);
sahilmgandhi 18:6a4db94011d3 114
sahilmgandhi 18:6a4db94011d3 115 MBED_ASSERT(I2cBase !=NC );
sahilmgandhi 18:6a4db94011d3 116
sahilmgandhi 18:6a4db94011d3 117 obj->i2c.i2c_base=I2cBase;
sahilmgandhi 18:6a4db94011d3 118 pinmap_find_i2c_info(I2cBase,obj);
sahilmgandhi 18:6a4db94011d3 119
sahilmgandhi 18:6a4db94011d3 120 /* Configure I2C pins */
sahilmgandhi 18:6a4db94011d3 121 pin_function(sda, pinmap_find_function(sda, PinMap_I2C_SDA));
sahilmgandhi 18:6a4db94011d3 122 ioport_disable_pin(sda);
sahilmgandhi 18:6a4db94011d3 123
sahilmgandhi 18:6a4db94011d3 124 pin_function(scl, pinmap_find_function(scl, PinMap_I2C_SCL));
sahilmgandhi 18:6a4db94011d3 125 ioport_disable_pin(scl);
sahilmgandhi 18:6a4db94011d3 126
sahilmgandhi 18:6a4db94011d3 127 #if (SAMG55)
sahilmgandhi 18:6a4db94011d3 128 /* Enable the peripheral and set TWI mode. */
sahilmgandhi 18:6a4db94011d3 129 MBED_ASSERT((int)obj->i2c.flexcom!=NC);
sahilmgandhi 18:6a4db94011d3 130 flexcom_enable(obj->i2c.flexcom);
sahilmgandhi 18:6a4db94011d3 131 flexcom_set_opmode(obj->i2c.flexcom, FLEXCOM_TWI);
sahilmgandhi 18:6a4db94011d3 132 #else
sahilmgandhi 18:6a4db94011d3 133 /* Enable the peripheral clock for TWI */
sahilmgandhi 18:6a4db94011d3 134 pmc_enable_periph_clk(obj->i2c.i2c_base);
sahilmgandhi 18:6a4db94011d3 135 #endif
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137 twi_options_t twi_options;
sahilmgandhi 18:6a4db94011d3 138 twi_options.master_clk=sysclk_get_cpu_hz();
sahilmgandhi 18:6a4db94011d3 139 twi_options.speed=TWI_CLK;
sahilmgandhi 18:6a4db94011d3 140 twi_options.smbus = 0;
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142 twi_master_init(obj->i2c.i2c_base,&twi_options);
sahilmgandhi 18:6a4db94011d3 143
sahilmgandhi 18:6a4db94011d3 144 obj->i2c.is_slave=false;
sahilmgandhi 18:6a4db94011d3 145 obj->i2c.speed=TWI_CLK;
sahilmgandhi 18:6a4db94011d3 146 obj->i2c.master_clk=twi_options.master_clk;
sahilmgandhi 18:6a4db94011d3 147 }
sahilmgandhi 18:6a4db94011d3 148
sahilmgandhi 18:6a4db94011d3 149 /** Configure the I2C frequency.
sahilmgandhi 18:6a4db94011d3 150 * @param obj The i2c object
sahilmgandhi 18:6a4db94011d3 151 * @param hz Frequency in Hz
sahilmgandhi 18:6a4db94011d3 152 */
sahilmgandhi 18:6a4db94011d3 153 void i2c_frequency(i2c_t *obj, int hz)
sahilmgandhi 18:6a4db94011d3 154 {
sahilmgandhi 18:6a4db94011d3 155 MBED_ASSERT(obj);
sahilmgandhi 18:6a4db94011d3 156 if(obj->i2c.is_slave)
sahilmgandhi 18:6a4db94011d3 157 twi_disable_slave_mode(obj->i2c.i2c_base);
sahilmgandhi 18:6a4db94011d3 158 else
sahilmgandhi 18:6a4db94011d3 159 twi_disable_master_mode(obj->i2c.i2c_base);
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161 twi_set_speed(obj->i2c.i2c_base,hz,obj->i2c.master_clk);
sahilmgandhi 18:6a4db94011d3 162
sahilmgandhi 18:6a4db94011d3 163 if(obj->i2c.is_slave)
sahilmgandhi 18:6a4db94011d3 164 twi_enable_slave_mode(obj->i2c.i2c_base);
sahilmgandhi 18:6a4db94011d3 165 else
sahilmgandhi 18:6a4db94011d3 166 twi_enable_master_mode(obj->i2c.i2c_base);
sahilmgandhi 18:6a4db94011d3 167 }
sahilmgandhi 18:6a4db94011d3 168
sahilmgandhi 18:6a4db94011d3 169 /** Send START command.
sahilmgandhi 18:6a4db94011d3 170 * @param obj The i2c object
sahilmgandhi 18:6a4db94011d3 171 */
sahilmgandhi 18:6a4db94011d3 172 int i2c_start(i2c_t *obj)
sahilmgandhi 18:6a4db94011d3 173 {
sahilmgandhi 18:6a4db94011d3 174 MBED_ASSERT(obj);
sahilmgandhi 18:6a4db94011d3 175 obj->i2c.i2c_base->TWI_CR = TWI_CR_START;
sahilmgandhi 18:6a4db94011d3 176 return 0;
sahilmgandhi 18:6a4db94011d3 177 }
sahilmgandhi 18:6a4db94011d3 178
sahilmgandhi 18:6a4db94011d3 179 /** Send STOP command.
sahilmgandhi 18:6a4db94011d3 180 * @param obj The i2c object
sahilmgandhi 18:6a4db94011d3 181 */
sahilmgandhi 18:6a4db94011d3 182 int i2c_stop(i2c_t *obj)
sahilmgandhi 18:6a4db94011d3 183 {
sahilmgandhi 18:6a4db94011d3 184 MBED_ASSERT(obj);
sahilmgandhi 18:6a4db94011d3 185 obj->i2c.i2c_base->TWI_CR = TWI_CR_STOP;
sahilmgandhi 18:6a4db94011d3 186 return 0;
sahilmgandhi 18:6a4db94011d3 187 }
sahilmgandhi 18:6a4db94011d3 188
sahilmgandhi 18:6a4db94011d3 189
sahilmgandhi 18:6a4db94011d3 190 uint32_t twi_master_read_no_stop(Twi *p_twi, twi_packet_t *p_packet, uint8_t stopena)
sahilmgandhi 18:6a4db94011d3 191 {
sahilmgandhi 18:6a4db94011d3 192 uint32_t status;
sahilmgandhi 18:6a4db94011d3 193 uint32_t cnt = p_packet->length;
sahilmgandhi 18:6a4db94011d3 194 uint8_t *buffer = p_packet->buffer;
sahilmgandhi 18:6a4db94011d3 195 uint8_t stop_sent = 0;
sahilmgandhi 18:6a4db94011d3 196 uint32_t timeout = TWI_TIMEOUT;;
sahilmgandhi 18:6a4db94011d3 197
sahilmgandhi 18:6a4db94011d3 198 /* Check argument */
sahilmgandhi 18:6a4db94011d3 199 if (cnt == 0) {
sahilmgandhi 18:6a4db94011d3 200 return TWI_INVALID_ARGUMENT;
sahilmgandhi 18:6a4db94011d3 201 }
sahilmgandhi 18:6a4db94011d3 202
sahilmgandhi 18:6a4db94011d3 203 /* Set read mode, slave address and 3 internal address byte lengths */
sahilmgandhi 18:6a4db94011d3 204 p_twi->TWI_MMR = 0;
sahilmgandhi 18:6a4db94011d3 205 p_twi->TWI_MMR = TWI_MMR_MREAD | TWI_MMR_DADR(p_packet->chip) |
sahilmgandhi 18:6a4db94011d3 206 ((p_packet->addr_length << TWI_MMR_IADRSZ_Pos) &
sahilmgandhi 18:6a4db94011d3 207 TWI_MMR_IADRSZ_Msk);
sahilmgandhi 18:6a4db94011d3 208
sahilmgandhi 18:6a4db94011d3 209 /* Send a START condition */
sahilmgandhi 18:6a4db94011d3 210 if ((cnt == 1) && (stopena == 1)) {
sahilmgandhi 18:6a4db94011d3 211 p_twi->TWI_CR = TWI_CR_START | TWI_CR_STOP;
sahilmgandhi 18:6a4db94011d3 212 stop_sent = 1;
sahilmgandhi 18:6a4db94011d3 213 } else {
sahilmgandhi 18:6a4db94011d3 214 p_twi->TWI_CR = TWI_CR_START;
sahilmgandhi 18:6a4db94011d3 215 stop_sent = 0;
sahilmgandhi 18:6a4db94011d3 216 }
sahilmgandhi 18:6a4db94011d3 217
sahilmgandhi 18:6a4db94011d3 218 while (cnt > 0) {
sahilmgandhi 18:6a4db94011d3 219 status = p_twi->TWI_SR;
sahilmgandhi 18:6a4db94011d3 220 if (status & TWI_SR_NACK) {
sahilmgandhi 18:6a4db94011d3 221 return TWI_RECEIVE_NACK;
sahilmgandhi 18:6a4db94011d3 222 }
sahilmgandhi 18:6a4db94011d3 223
sahilmgandhi 18:6a4db94011d3 224 if (!timeout--) {
sahilmgandhi 18:6a4db94011d3 225 return TWI_ERROR_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 226 }
sahilmgandhi 18:6a4db94011d3 227
sahilmgandhi 18:6a4db94011d3 228 /* Last byte ? */
sahilmgandhi 18:6a4db94011d3 229 if ((cnt == 1) && (!stop_sent) && (stopena == 1)) {
sahilmgandhi 18:6a4db94011d3 230 p_twi->TWI_CR = TWI_CR_STOP;
sahilmgandhi 18:6a4db94011d3 231 stop_sent = 1;
sahilmgandhi 18:6a4db94011d3 232 }
sahilmgandhi 18:6a4db94011d3 233
sahilmgandhi 18:6a4db94011d3 234 if (!(status & TWI_SR_RXRDY)) {
sahilmgandhi 18:6a4db94011d3 235 continue;
sahilmgandhi 18:6a4db94011d3 236 }
sahilmgandhi 18:6a4db94011d3 237 *buffer++ = p_twi->TWI_RHR;
sahilmgandhi 18:6a4db94011d3 238
sahilmgandhi 18:6a4db94011d3 239 cnt--;
sahilmgandhi 18:6a4db94011d3 240 timeout = TWI_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 241 }
sahilmgandhi 18:6a4db94011d3 242 if(stopena) {
sahilmgandhi 18:6a4db94011d3 243 while (!(p_twi->TWI_SR & TWI_SR_TXCOMP)) {
sahilmgandhi 18:6a4db94011d3 244 }
sahilmgandhi 18:6a4db94011d3 245 }
sahilmgandhi 18:6a4db94011d3 246
sahilmgandhi 18:6a4db94011d3 247 p_twi->TWI_SR;
sahilmgandhi 18:6a4db94011d3 248
sahilmgandhi 18:6a4db94011d3 249 return TWI_SUCCESS;
sahilmgandhi 18:6a4db94011d3 250
sahilmgandhi 18:6a4db94011d3 251 }
sahilmgandhi 18:6a4db94011d3 252
sahilmgandhi 18:6a4db94011d3 253
sahilmgandhi 18:6a4db94011d3 254
sahilmgandhi 18:6a4db94011d3 255
sahilmgandhi 18:6a4db94011d3 256
sahilmgandhi 18:6a4db94011d3 257 /** Blocking reading data.
sahilmgandhi 18:6a4db94011d3 258 * @param obj The i2c object
sahilmgandhi 18:6a4db94011d3 259 * @param address 7-bit address (last bit is 1)
sahilmgandhi 18:6a4db94011d3 260 * @param data The buffer for receiving
sahilmgandhi 18:6a4db94011d3 261 * @param length Number of bytes to read
sahilmgandhi 18:6a4db94011d3 262 * @param stop Stop to be generated after the transfer is done
sahilmgandhi 18:6a4db94011d3 263 * @return Number of read bytes
sahilmgandhi 18:6a4db94011d3 264 */
sahilmgandhi 18:6a4db94011d3 265 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
sahilmgandhi 18:6a4db94011d3 266 {
sahilmgandhi 18:6a4db94011d3 267 MBED_ASSERT(obj);
sahilmgandhi 18:6a4db94011d3 268
sahilmgandhi 18:6a4db94011d3 269 twi_packet_t packet;
sahilmgandhi 18:6a4db94011d3 270 packet.chip= (address>>1) & 0x7F;
sahilmgandhi 18:6a4db94011d3 271 packet.addr_length=ADDR_LENGTH;
sahilmgandhi 18:6a4db94011d3 272 packet.buffer=data;
sahilmgandhi 18:6a4db94011d3 273 packet.length=length;
sahilmgandhi 18:6a4db94011d3 274
sahilmgandhi 18:6a4db94011d3 275 uint8_t status;
sahilmgandhi 18:6a4db94011d3 276 status= twi_master_read_no_stop(obj->i2c.i2c_base, &packet, stop);
sahilmgandhi 18:6a4db94011d3 277
sahilmgandhi 18:6a4db94011d3 278 if(TWI_SUCCESS==status)
sahilmgandhi 18:6a4db94011d3 279 return length;
sahilmgandhi 18:6a4db94011d3 280
sahilmgandhi 18:6a4db94011d3 281 return 0;
sahilmgandhi 18:6a4db94011d3 282 }
sahilmgandhi 18:6a4db94011d3 283
sahilmgandhi 18:6a4db94011d3 284
sahilmgandhi 18:6a4db94011d3 285 uint32_t twi_master_write_no_stop(Twi *p_twi, twi_packet_t *p_packet, uint8_t stopena)
sahilmgandhi 18:6a4db94011d3 286 {
sahilmgandhi 18:6a4db94011d3 287 uint32_t status;
sahilmgandhi 18:6a4db94011d3 288 uint32_t cnt = p_packet->length;
sahilmgandhi 18:6a4db94011d3 289 uint8_t *buffer = p_packet->buffer;
sahilmgandhi 18:6a4db94011d3 290
sahilmgandhi 18:6a4db94011d3 291 /* Check argument */
sahilmgandhi 18:6a4db94011d3 292 if (cnt == 0) {
sahilmgandhi 18:6a4db94011d3 293 return TWI_INVALID_ARGUMENT;
sahilmgandhi 18:6a4db94011d3 294 }
sahilmgandhi 18:6a4db94011d3 295
sahilmgandhi 18:6a4db94011d3 296 /* Set write mode, slave address and 3 internal address byte lengths */
sahilmgandhi 18:6a4db94011d3 297 p_twi->TWI_MMR = 0;
sahilmgandhi 18:6a4db94011d3 298 p_twi->TWI_MMR = TWI_MMR_DADR(p_packet->chip) |
sahilmgandhi 18:6a4db94011d3 299 ((p_packet->addr_length << TWI_MMR_IADRSZ_Pos) &
sahilmgandhi 18:6a4db94011d3 300 TWI_MMR_IADRSZ_Msk);
sahilmgandhi 18:6a4db94011d3 301
sahilmgandhi 18:6a4db94011d3 302 /* Send a START condition */
sahilmgandhi 18:6a4db94011d3 303 if ((cnt == 1) && (stopena == 1)) {
sahilmgandhi 18:6a4db94011d3 304 p_twi->TWI_CR = TWI_CR_START | TWI_CR_STOP;
sahilmgandhi 18:6a4db94011d3 305 } else {
sahilmgandhi 18:6a4db94011d3 306 p_twi->TWI_CR = TWI_CR_START;
sahilmgandhi 18:6a4db94011d3 307 }
sahilmgandhi 18:6a4db94011d3 308
sahilmgandhi 18:6a4db94011d3 309 /* Send all bytes */
sahilmgandhi 18:6a4db94011d3 310 while (cnt > 0) {
sahilmgandhi 18:6a4db94011d3 311 status = p_twi->TWI_SR;
sahilmgandhi 18:6a4db94011d3 312 if (status & TWI_SR_NACK) {
sahilmgandhi 18:6a4db94011d3 313 return TWI_RECEIVE_NACK;
sahilmgandhi 18:6a4db94011d3 314 }
sahilmgandhi 18:6a4db94011d3 315
sahilmgandhi 18:6a4db94011d3 316 if (!(status & TWI_SR_TXRDY)) {
sahilmgandhi 18:6a4db94011d3 317 continue;
sahilmgandhi 18:6a4db94011d3 318 }
sahilmgandhi 18:6a4db94011d3 319 p_twi->TWI_THR = *buffer++;
sahilmgandhi 18:6a4db94011d3 320
sahilmgandhi 18:6a4db94011d3 321 cnt--;
sahilmgandhi 18:6a4db94011d3 322 }
sahilmgandhi 18:6a4db94011d3 323
sahilmgandhi 18:6a4db94011d3 324 while (1) {
sahilmgandhi 18:6a4db94011d3 325 status = p_twi->TWI_SR;
sahilmgandhi 18:6a4db94011d3 326 if (status & TWI_SR_NACK) {
sahilmgandhi 18:6a4db94011d3 327 return TWI_RECEIVE_NACK;
sahilmgandhi 18:6a4db94011d3 328 }
sahilmgandhi 18:6a4db94011d3 329
sahilmgandhi 18:6a4db94011d3 330 if (status & TWI_SR_TXRDY) {
sahilmgandhi 18:6a4db94011d3 331 break;
sahilmgandhi 18:6a4db94011d3 332 }
sahilmgandhi 18:6a4db94011d3 333 }
sahilmgandhi 18:6a4db94011d3 334
sahilmgandhi 18:6a4db94011d3 335 if (stopena) {
sahilmgandhi 18:6a4db94011d3 336 p_twi->TWI_CR = TWI_CR_STOP;
sahilmgandhi 18:6a4db94011d3 337 while (!(p_twi->TWI_SR & TWI_SR_TXCOMP));
sahilmgandhi 18:6a4db94011d3 338 }
sahilmgandhi 18:6a4db94011d3 339
sahilmgandhi 18:6a4db94011d3 340 return TWI_SUCCESS;
sahilmgandhi 18:6a4db94011d3 341 }
sahilmgandhi 18:6a4db94011d3 342
sahilmgandhi 18:6a4db94011d3 343
sahilmgandhi 18:6a4db94011d3 344
sahilmgandhi 18:6a4db94011d3 345 /** Blocking sending data.
sahilmgandhi 18:6a4db94011d3 346 * @param obj The i2c object
sahilmgandhi 18:6a4db94011d3 347 * @param address 7-bit address (last bit is 0)
sahilmgandhi 18:6a4db94011d3 348 * @param data The buffer for sending
sahilmgandhi 18:6a4db94011d3 349 * @param length Number of bytes to wrte
sahilmgandhi 18:6a4db94011d3 350 * @param stop Stop to be generated after the transfer is done
sahilmgandhi 18:6a4db94011d3 351 * @return Number of written bytes
sahilmgandhi 18:6a4db94011d3 352 */
sahilmgandhi 18:6a4db94011d3 353 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
sahilmgandhi 18:6a4db94011d3 354 {
sahilmgandhi 18:6a4db94011d3 355 MBED_ASSERT(obj);
sahilmgandhi 18:6a4db94011d3 356
sahilmgandhi 18:6a4db94011d3 357 twi_packet_t packet;
sahilmgandhi 18:6a4db94011d3 358 packet.chip= (address>>1) & 0x7F;
sahilmgandhi 18:6a4db94011d3 359 packet.addr_length=ADDR_LENGTH;
sahilmgandhi 18:6a4db94011d3 360 packet.buffer= (void *)data;
sahilmgandhi 18:6a4db94011d3 361 packet.length=length;
sahilmgandhi 18:6a4db94011d3 362
sahilmgandhi 18:6a4db94011d3 363 uint8_t status;
sahilmgandhi 18:6a4db94011d3 364 status= twi_master_write_no_stop(obj->i2c.i2c_base,&packet, stop);
sahilmgandhi 18:6a4db94011d3 365
sahilmgandhi 18:6a4db94011d3 366 if(TWI_SUCCESS==status)
sahilmgandhi 18:6a4db94011d3 367 return length;
sahilmgandhi 18:6a4db94011d3 368
sahilmgandhi 18:6a4db94011d3 369 return 0;
sahilmgandhi 18:6a4db94011d3 370 }
sahilmgandhi 18:6a4db94011d3 371
sahilmgandhi 18:6a4db94011d3 372 /** Reset I2C peripheral. TODO: The action here. Most of the implementation sends stop().
sahilmgandhi 18:6a4db94011d3 373 * @param obj The i2c object
sahilmgandhi 18:6a4db94011d3 374 */
sahilmgandhi 18:6a4db94011d3 375 void i2c_reset(i2c_t *obj)
sahilmgandhi 18:6a4db94011d3 376 {
sahilmgandhi 18:6a4db94011d3 377 MBED_ASSERT(obj);
sahilmgandhi 18:6a4db94011d3 378 twi_reset(obj->i2c.i2c_base);
sahilmgandhi 18:6a4db94011d3 379 }
sahilmgandhi 18:6a4db94011d3 380
sahilmgandhi 18:6a4db94011d3 381 /** Read one byte.
sahilmgandhi 18:6a4db94011d3 382 * @param obj The i2c object
sahilmgandhi 18:6a4db94011d3 383 * @param last Acknoledge
sahilmgandhi 18:6a4db94011d3 384 * @return The read byte
sahilmgandhi 18:6a4db94011d3 385 */
sahilmgandhi 18:6a4db94011d3 386 int i2c_byte_read(i2c_t *obj, int last)
sahilmgandhi 18:6a4db94011d3 387 {
sahilmgandhi 18:6a4db94011d3 388 MBED_ASSERT(obj);
sahilmgandhi 18:6a4db94011d3 389 if(!last)
sahilmgandhi 18:6a4db94011d3 390 twi_enable_slave_nack(obj->i2c.i2c_base);
sahilmgandhi 18:6a4db94011d3 391
sahilmgandhi 18:6a4db94011d3 392 return twi_read_byte(obj->i2c.i2c_base);
sahilmgandhi 18:6a4db94011d3 393 }
sahilmgandhi 18:6a4db94011d3 394
sahilmgandhi 18:6a4db94011d3 395 /** Write one byte.
sahilmgandhi 18:6a4db94011d3 396 * @param obj The i2c object
sahilmgandhi 18:6a4db94011d3 397 * @param data Byte to be written
sahilmgandhi 18:6a4db94011d3 398 * @return 1 if NAK was received, 0 if ACK was received, 2 for timeout.
sahilmgandhi 18:6a4db94011d3 399 */
sahilmgandhi 18:6a4db94011d3 400 #define ACK 0
sahilmgandhi 18:6a4db94011d3 401 #define NAK 1
sahilmgandhi 18:6a4db94011d3 402 #define TIMEOUT 2
sahilmgandhi 18:6a4db94011d3 403
sahilmgandhi 18:6a4db94011d3 404 int i2c_byte_write(i2c_t *obj, int data)
sahilmgandhi 18:6a4db94011d3 405 {
sahilmgandhi 18:6a4db94011d3 406 MBED_ASSERT(obj);
sahilmgandhi 18:6a4db94011d3 407 twi_write_byte(obj->i2c.i2c_base,data);
sahilmgandhi 18:6a4db94011d3 408
sahilmgandhi 18:6a4db94011d3 409 uint32_t timeout = TWI_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 410 while (timeout--) {
sahilmgandhi 18:6a4db94011d3 411 uint32_t status = obj->i2c.i2c_base->TWI_SR;
sahilmgandhi 18:6a4db94011d3 412 if (status & TWI_SR_NACK) {
sahilmgandhi 18:6a4db94011d3 413 return NAK;
sahilmgandhi 18:6a4db94011d3 414 }
sahilmgandhi 18:6a4db94011d3 415
sahilmgandhi 18:6a4db94011d3 416 if (status & TWI_SR_TXRDY) {
sahilmgandhi 18:6a4db94011d3 417 return ACK;
sahilmgandhi 18:6a4db94011d3 418 }
sahilmgandhi 18:6a4db94011d3 419
sahilmgandhi 18:6a4db94011d3 420 if (timeout<1) {
sahilmgandhi 18:6a4db94011d3 421 return TIMEOUT;
sahilmgandhi 18:6a4db94011d3 422 }
sahilmgandhi 18:6a4db94011d3 423 }
sahilmgandhi 18:6a4db94011d3 424
sahilmgandhi 18:6a4db94011d3 425 return ACK;
sahilmgandhi 18:6a4db94011d3 426 }
sahilmgandhi 18:6a4db94011d3 427
sahilmgandhi 18:6a4db94011d3 428 /**@}*/
sahilmgandhi 18:6a4db94011d3 429
sahilmgandhi 18:6a4db94011d3 430 #if DEVICE_I2CSLAVE
sahilmgandhi 18:6a4db94011d3 431
sahilmgandhi 18:6a4db94011d3 432 /**
sahilmgandhi 18:6a4db94011d3 433 * \defgroup SynchI2C Synchronous I2C Hardware Abstraction Layer for slave
sahilmgandhi 18:6a4db94011d3 434 * @{
sahilmgandhi 18:6a4db94011d3 435 */
sahilmgandhi 18:6a4db94011d3 436
sahilmgandhi 18:6a4db94011d3 437 /** Configure I2C as slave or master.
sahilmgandhi 18:6a4db94011d3 438 * @param obj The I2C object
sahilmgandhi 18:6a4db94011d3 439 * @return non-zero if a value is available
sahilmgandhi 18:6a4db94011d3 440 */
sahilmgandhi 18:6a4db94011d3 441 void i2c_slave_mode(i2c_t *obj, int enable_slave)
sahilmgandhi 18:6a4db94011d3 442 {
sahilmgandhi 18:6a4db94011d3 443 MBED_ASSERT(obj);
sahilmgandhi 18:6a4db94011d3 444 /* Disable TWI interrupts */
sahilmgandhi 18:6a4db94011d3 445 obj->i2c.i2c_base->TWI_IDR = ~0UL;
sahilmgandhi 18:6a4db94011d3 446 obj->i2c.i2c_base->TWI_SR;
sahilmgandhi 18:6a4db94011d3 447
sahilmgandhi 18:6a4db94011d3 448 /* Reset TWI */
sahilmgandhi 18:6a4db94011d3 449 twi_reset(obj->i2c.i2c_base);
sahilmgandhi 18:6a4db94011d3 450
sahilmgandhi 18:6a4db94011d3 451 MBED_ASSERT(obj);
sahilmgandhi 18:6a4db94011d3 452 if(enable_slave)
sahilmgandhi 18:6a4db94011d3 453 twi_enable_slave_mode(obj->i2c.i2c_base);
sahilmgandhi 18:6a4db94011d3 454 else
sahilmgandhi 18:6a4db94011d3 455 twi_enable_master_mode(obj->i2c.i2c_base);
sahilmgandhi 18:6a4db94011d3 456 }
sahilmgandhi 18:6a4db94011d3 457
sahilmgandhi 18:6a4db94011d3 458 /** Check to see if the I2C slave has been addressed.
sahilmgandhi 18:6a4db94011d3 459 * @param obj The I2C object
sahilmgandhi 18:6a4db94011d3 460 * @return The status - 1 - read addresses, 2 - write to all slaves,
sahilmgandhi 18:6a4db94011d3 461 * 3 write addressed, 0 - the slave has not been addressed
sahilmgandhi 18:6a4db94011d3 462 */
sahilmgandhi 18:6a4db94011d3 463 int i2c_slave_receive(i2c_t *obj)
sahilmgandhi 18:6a4db94011d3 464 {
sahilmgandhi 18:6a4db94011d3 465 uint32_t status = obj->i2c.i2c_base->TWI_SR;
sahilmgandhi 18:6a4db94011d3 466 if((status & TWI_SR_SVACC)) {
sahilmgandhi 18:6a4db94011d3 467 if(status & TWI_SR_SVREAD)
sahilmgandhi 18:6a4db94011d3 468 return 1;
sahilmgandhi 18:6a4db94011d3 469 else
sahilmgandhi 18:6a4db94011d3 470 return 3;
sahilmgandhi 18:6a4db94011d3 471 }
sahilmgandhi 18:6a4db94011d3 472 return 0;
sahilmgandhi 18:6a4db94011d3 473 }
sahilmgandhi 18:6a4db94011d3 474
sahilmgandhi 18:6a4db94011d3 475
sahilmgandhi 18:6a4db94011d3 476 uint32_t twi_slave_read_n(Twi *p_twi, uint8_t *p_data, int length)
sahilmgandhi 18:6a4db94011d3 477 {
sahilmgandhi 18:6a4db94011d3 478 uint32_t status, cnt = 0;
sahilmgandhi 18:6a4db94011d3 479
sahilmgandhi 18:6a4db94011d3 480 do {
sahilmgandhi 18:6a4db94011d3 481 status = p_twi->TWI_SR;
sahilmgandhi 18:6a4db94011d3 482 if (status & TWI_SR_SVACC) {
sahilmgandhi 18:6a4db94011d3 483 if (!(status & (TWI_SR_GACC| TWI_SR_SVREAD )) &&
sahilmgandhi 18:6a4db94011d3 484 (status & TWI_SR_RXRDY)
sahilmgandhi 18:6a4db94011d3 485 ) {
sahilmgandhi 18:6a4db94011d3 486 *p_data++ = (uint8_t) p_twi->TWI_RHR;
sahilmgandhi 18:6a4db94011d3 487 cnt++;
sahilmgandhi 18:6a4db94011d3 488 if(cnt>=length) break;
sahilmgandhi 18:6a4db94011d3 489 }
sahilmgandhi 18:6a4db94011d3 490 } else if ((status & (TWI_SR_EOSACC | TWI_SR_TXCOMP))
sahilmgandhi 18:6a4db94011d3 491 == (TWI_SR_EOSACC | TWI_SR_TXCOMP)) {
sahilmgandhi 18:6a4db94011d3 492 break;
sahilmgandhi 18:6a4db94011d3 493 }
sahilmgandhi 18:6a4db94011d3 494 } while (1);
sahilmgandhi 18:6a4db94011d3 495
sahilmgandhi 18:6a4db94011d3 496 return cnt;
sahilmgandhi 18:6a4db94011d3 497 }
sahilmgandhi 18:6a4db94011d3 498
sahilmgandhi 18:6a4db94011d3 499 /** Read I2C slave.
sahilmgandhi 18:6a4db94011d3 500 * @param obj The I2C object
sahilmgandhi 18:6a4db94011d3 501 * @return non-zero if a value is available
sahilmgandhi 18:6a4db94011d3 502 */
sahilmgandhi 18:6a4db94011d3 503 int i2c_slave_read(i2c_t *obj, char *data, int length)
sahilmgandhi 18:6a4db94011d3 504 {
sahilmgandhi 18:6a4db94011d3 505 MBED_ASSERT(obj);
sahilmgandhi 18:6a4db94011d3 506 int read= twi_slave_read_n(obj->i2c.i2c_base,(uint8_t *) data,length);
sahilmgandhi 18:6a4db94011d3 507 return read;
sahilmgandhi 18:6a4db94011d3 508 }
sahilmgandhi 18:6a4db94011d3 509
sahilmgandhi 18:6a4db94011d3 510
sahilmgandhi 18:6a4db94011d3 511 uint32_t twi_slave_write_n(Twi *p_twi, uint8_t *p_data, int length)
sahilmgandhi 18:6a4db94011d3 512 {
sahilmgandhi 18:6a4db94011d3 513 uint32_t status, cnt = 0;
sahilmgandhi 18:6a4db94011d3 514
sahilmgandhi 18:6a4db94011d3 515 do {
sahilmgandhi 18:6a4db94011d3 516 status = p_twi->TWI_SR;
sahilmgandhi 18:6a4db94011d3 517 if (status & TWI_SR_SVACC) {
sahilmgandhi 18:6a4db94011d3 518 if ((status & TWI_SR_SVREAD) && !(status & TWI_SR_GACC) &&
sahilmgandhi 18:6a4db94011d3 519 (status & TWI_SR_TXRDY)) {
sahilmgandhi 18:6a4db94011d3 520 p_twi->TWI_THR = *p_data++;
sahilmgandhi 18:6a4db94011d3 521 cnt++;
sahilmgandhi 18:6a4db94011d3 522 if(cnt>=length) break;
sahilmgandhi 18:6a4db94011d3 523 }
sahilmgandhi 18:6a4db94011d3 524 } else if ((status & (TWI_SR_EOSACC | TWI_SR_TXCOMP))
sahilmgandhi 18:6a4db94011d3 525 == (TWI_SR_EOSACC | TWI_SR_TXCOMP)) {
sahilmgandhi 18:6a4db94011d3 526 break;
sahilmgandhi 18:6a4db94011d3 527 }
sahilmgandhi 18:6a4db94011d3 528 } while (1);
sahilmgandhi 18:6a4db94011d3 529
sahilmgandhi 18:6a4db94011d3 530 return cnt;
sahilmgandhi 18:6a4db94011d3 531 }
sahilmgandhi 18:6a4db94011d3 532
sahilmgandhi 18:6a4db94011d3 533
sahilmgandhi 18:6a4db94011d3 534 /** Write I2C as slave.
sahilmgandhi 18:6a4db94011d3 535 * @param obj The I2C object
sahilmgandhi 18:6a4db94011d3 536 * @return non-zero if a value is available
sahilmgandhi 18:6a4db94011d3 537 */
sahilmgandhi 18:6a4db94011d3 538 int i2c_slave_write(i2c_t *obj, const char *data, int length)
sahilmgandhi 18:6a4db94011d3 539 {
sahilmgandhi 18:6a4db94011d3 540 MBED_ASSERT(obj);
sahilmgandhi 18:6a4db94011d3 541 int write= twi_slave_write_n(obj->i2c.i2c_base, (uint8_t *) data,length);
sahilmgandhi 18:6a4db94011d3 542 return write;
sahilmgandhi 18:6a4db94011d3 543 }
sahilmgandhi 18:6a4db94011d3 544
sahilmgandhi 18:6a4db94011d3 545 /** Configure I2C address.
sahilmgandhi 18:6a4db94011d3 546 * @param obj The I2C object
sahilmgandhi 18:6a4db94011d3 547 * @param idx Currently not used
sahilmgandhi 18:6a4db94011d3 548 * @param address The address to be set
sahilmgandhi 18:6a4db94011d3 549 * @param mask Currently not used
sahilmgandhi 18:6a4db94011d3 550 */
sahilmgandhi 18:6a4db94011d3 551 void i2c_slave_address(i2c_t *obj, int idx/*not used*/, uint32_t address, uint32_t mask)
sahilmgandhi 18:6a4db94011d3 552 {
sahilmgandhi 18:6a4db94011d3 553 MBED_ASSERT(obj);
sahilmgandhi 18:6a4db94011d3 554 twi_set_slave_addr(obj->i2c.i2c_base, (address>>1));
sahilmgandhi 18:6a4db94011d3 555 }
sahilmgandhi 18:6a4db94011d3 556
sahilmgandhi 18:6a4db94011d3 557 #endif
sahilmgandhi 18:6a4db94011d3 558
sahilmgandhi 18:6a4db94011d3 559 /**@}*/
sahilmgandhi 18:6a4db94011d3 560
sahilmgandhi 18:6a4db94011d3 561 #if DEVICE_I2C_ASYNCH
sahilmgandhi 18:6a4db94011d3 562
sahilmgandhi 18:6a4db94011d3 563 /**
sahilmgandhi 18:6a4db94011d3 564 * \defgroup AsynchI2C Asynchronous I2C Hardware Abstraction Layer
sahilmgandhi 18:6a4db94011d3 565 * @{
sahilmgandhi 18:6a4db94011d3 566 */
sahilmgandhi 18:6a4db94011d3 567
sahilmgandhi 18:6a4db94011d3 568 /** Start i2c asynchronous transfer.
sahilmgandhi 18:6a4db94011d3 569 * @param obj The I2C object
sahilmgandhi 18:6a4db94011d3 570 * @param tx The buffer to send
sahilmgandhi 18:6a4db94011d3 571 * @param tx_length The number of words to transmit
sahilmgandhi 18:6a4db94011d3 572 * @param rx The buffer to receive
sahilmgandhi 18:6a4db94011d3 573 * @param rx_length The number of words to receive
sahilmgandhi 18:6a4db94011d3 574 * @param address The address to be set - 7bit or 9 bit
sahilmgandhi 18:6a4db94011d3 575 * @param stop If true, stop will be generated after the transfer is done
sahilmgandhi 18:6a4db94011d3 576 * @param handler The I2C IRQ handler to be set
sahilmgandhi 18:6a4db94011d3 577 * @param hint DMA hint usage
sahilmgandhi 18:6a4db94011d3 578 */
sahilmgandhi 18:6a4db94011d3 579 #warning "Only DMA async supported by I2C master transfer"
sahilmgandhi 18:6a4db94011d3 580
sahilmgandhi 18:6a4db94011d3 581 void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint /*Not Used*/)
sahilmgandhi 18:6a4db94011d3 582 {
sahilmgandhi 18:6a4db94011d3 583 uint32_t pdcenable=0;
sahilmgandhi 18:6a4db94011d3 584
sahilmgandhi 18:6a4db94011d3 585 if(address) {
sahilmgandhi 18:6a4db94011d3 586 twi_packet_t pdc_packet;
sahilmgandhi 18:6a4db94011d3 587 pdc_packet.chip=(address>>1) & 0x7F;
sahilmgandhi 18:6a4db94011d3 588 pdc_packet.addr_length=ADDR_LENGTH;
sahilmgandhi 18:6a4db94011d3 589
sahilmgandhi 18:6a4db94011d3 590 /* Set write mode, slave address and 3 internal address byte lengths */
sahilmgandhi 18:6a4db94011d3 591 obj->i2c.i2c_base->TWI_MMR = 0;
sahilmgandhi 18:6a4db94011d3 592 obj->i2c.i2c_base->TWI_MMR = TWI_MMR_DADR(pdc_packet.chip) |
sahilmgandhi 18:6a4db94011d3 593 ((pdc_packet.addr_length << TWI_MMR_IADRSZ_Pos) &
sahilmgandhi 18:6a4db94011d3 594 TWI_MMR_IADRSZ_Msk);
sahilmgandhi 18:6a4db94011d3 595 }
sahilmgandhi 18:6a4db94011d3 596
sahilmgandhi 18:6a4db94011d3 597 if(tx) {
sahilmgandhi 18:6a4db94011d3 598 pdc_packet_t pdc_packet_tx;
sahilmgandhi 18:6a4db94011d3 599 pdc_packet_tx.ul_addr=(uint32_t)tx;
sahilmgandhi 18:6a4db94011d3 600 pdc_packet_tx.ul_size=tx_length;
sahilmgandhi 18:6a4db94011d3 601
sahilmgandhi 18:6a4db94011d3 602 pdcenable|=PERIPH_PTCR_TXTEN;
sahilmgandhi 18:6a4db94011d3 603 /* Configure PDC for data send */
sahilmgandhi 18:6a4db94011d3 604 pdc_tx_init(obj->i2c.pdc, &pdc_packet_tx, NULL);
sahilmgandhi 18:6a4db94011d3 605 }
sahilmgandhi 18:6a4db94011d3 606
sahilmgandhi 18:6a4db94011d3 607 if(rx) {
sahilmgandhi 18:6a4db94011d3 608 obj->i2c.i2c_base->TWI_MMR |= TWI_MMR_MREAD;
sahilmgandhi 18:6a4db94011d3 609 pdc_rx_clear_cnt(obj->i2c.pdc);
sahilmgandhi 18:6a4db94011d3 610 pdc_packet_t pdc_packet_rx;
sahilmgandhi 18:6a4db94011d3 611 pdc_packet_rx.ul_addr=(uint32_t)rx;
sahilmgandhi 18:6a4db94011d3 612 pdc_packet_rx.ul_size=rx_length;
sahilmgandhi 18:6a4db94011d3 613 pdcenable|=PERIPH_PTCR_RXTEN;
sahilmgandhi 18:6a4db94011d3 614
sahilmgandhi 18:6a4db94011d3 615 /* Configure PDC for data receive */
sahilmgandhi 18:6a4db94011d3 616 pdc_rx_init(obj->i2c.pdc, &pdc_packet_rx, NULL);
sahilmgandhi 18:6a4db94011d3 617 }
sahilmgandhi 18:6a4db94011d3 618
sahilmgandhi 18:6a4db94011d3 619 obj->i2c.dma_usage=hint;
sahilmgandhi 18:6a4db94011d3 620 obj->i2c.event=event;
sahilmgandhi 18:6a4db94011d3 621 obj->i2c.stop=stop;
sahilmgandhi 18:6a4db94011d3 622 obj->i2c.address=address;
sahilmgandhi 18:6a4db94011d3 623
sahilmgandhi 18:6a4db94011d3 624 NVIC_ClearPendingIRQ(obj->i2c.irq_type);
sahilmgandhi 18:6a4db94011d3 625 NVIC_DisableIRQ(obj->i2c.irq_type);
sahilmgandhi 18:6a4db94011d3 626 NVIC_SetVector(obj->i2c.irq_type,handler);
sahilmgandhi 18:6a4db94011d3 627 NVIC_EnableIRQ(obj->i2c.irq_type);
sahilmgandhi 18:6a4db94011d3 628
sahilmgandhi 18:6a4db94011d3 629 /* Enable TWI IRQ */
sahilmgandhi 18:6a4db94011d3 630 twi_enable_interrupt(obj->i2c.i2c_base, TWI_IER_RXBUFF| TWI_IER_TXBUFE | TWI_IER_UNRE | TWI_IER_OVRE | TWI_IER_PECERR);
sahilmgandhi 18:6a4db94011d3 631
sahilmgandhi 18:6a4db94011d3 632 /* Enable PDC transfers */
sahilmgandhi 18:6a4db94011d3 633 pdc_enable_transfer(obj->i2c.pdc, pdcenable );
sahilmgandhi 18:6a4db94011d3 634
sahilmgandhi 18:6a4db94011d3 635 }
sahilmgandhi 18:6a4db94011d3 636
sahilmgandhi 18:6a4db94011d3 637 /** The asynchronous IRQ handler
sahilmgandhi 18:6a4db94011d3 638 * @param obj The I2C object which holds the transfer information
sahilmgandhi 18:6a4db94011d3 639 * @return event flags if a transfer termination condition was met or 0 otherwise.
sahilmgandhi 18:6a4db94011d3 640 */
sahilmgandhi 18:6a4db94011d3 641 uint32_t i2c_irq_handler_asynch(i2c_t *obj)
sahilmgandhi 18:6a4db94011d3 642 {
sahilmgandhi 18:6a4db94011d3 643 uint32_t event=0;
sahilmgandhi 18:6a4db94011d3 644
sahilmgandhi 18:6a4db94011d3 645 if(obj->i2c.stop) {
sahilmgandhi 18:6a4db94011d3 646 i2c_stop(obj);
sahilmgandhi 18:6a4db94011d3 647 }
sahilmgandhi 18:6a4db94011d3 648
sahilmgandhi 18:6a4db94011d3 649 // Data transferred via DMA
sahilmgandhi 18:6a4db94011d3 650 if((obj->i2c.i2c_base->TWI_SR & TWI_IER_TXBUFE)) {
sahilmgandhi 18:6a4db94011d3 651 twi_disable_interrupt(obj->i2c.i2c_base, TWI_IDR_TXBUFE | TWI_IDR_UNRE | TWI_IDR_OVRE | TWI_IDR_PECERR);
sahilmgandhi 18:6a4db94011d3 652 if(obj->i2c.event | I2C_EVENT_TRANSFER_COMPLETE)
sahilmgandhi 18:6a4db94011d3 653 event |=I2C_EVENT_TRANSFER_COMPLETE;
sahilmgandhi 18:6a4db94011d3 654 }
sahilmgandhi 18:6a4db94011d3 655
sahilmgandhi 18:6a4db94011d3 656 if((obj->i2c.i2c_base->TWI_SR & TWI_IER_RXBUFF)) {
sahilmgandhi 18:6a4db94011d3 657 twi_disable_interrupt(obj->i2c.i2c_base, TWI_IDR_RXBUFF | TWI_IDR_UNRE | TWI_IDR_OVRE | TWI_IDR_PECERR);
sahilmgandhi 18:6a4db94011d3 658 if(obj->i2c.event | I2C_EVENT_TRANSFER_COMPLETE)
sahilmgandhi 18:6a4db94011d3 659 event |=I2C_EVENT_TRANSFER_COMPLETE;
sahilmgandhi 18:6a4db94011d3 660 }
sahilmgandhi 18:6a4db94011d3 661
sahilmgandhi 18:6a4db94011d3 662 if(obj->i2c.i2c_base->TWI_SR & TWI_IER_NACK) {
sahilmgandhi 18:6a4db94011d3 663 if(obj->i2c.event | I2C_EVENT_TRANSFER_EARLY_NACK)
sahilmgandhi 18:6a4db94011d3 664 event |=I2C_EVENT_TRANSFER_EARLY_NACK;
sahilmgandhi 18:6a4db94011d3 665 }
sahilmgandhi 18:6a4db94011d3 666
sahilmgandhi 18:6a4db94011d3 667
sahilmgandhi 18:6a4db94011d3 668 if((obj->i2c.i2c_base->TWI_SR & TWI_IER_UNRE) || (obj->i2c.i2c_base->TWI_SR & TWI_IER_OVRE) || (obj->i2c.i2c_base->TWI_SR & TWI_IER_PECERR) || (obj->i2c.i2c_base->TWI_SR & TWI_SR_TOUT) ) {
sahilmgandhi 18:6a4db94011d3 669 if((obj->i2c.event | I2C_EVENT_ERROR))
sahilmgandhi 18:6a4db94011d3 670 event |=I2C_EVENT_ERROR;
sahilmgandhi 18:6a4db94011d3 671
sahilmgandhi 18:6a4db94011d3 672 if(obj->i2c.address) {
sahilmgandhi 18:6a4db94011d3 673 uint8_t status= twi_probe(obj->i2c.i2c_base,obj->i2c.address);
sahilmgandhi 18:6a4db94011d3 674 if((obj->i2c.event | I2C_EVENT_ERROR_NO_SLAVE) && (status!=TWI_SUCCESS) )
sahilmgandhi 18:6a4db94011d3 675 event |=I2C_EVENT_ERROR_NO_SLAVE;
sahilmgandhi 18:6a4db94011d3 676 }
sahilmgandhi 18:6a4db94011d3 677 }
sahilmgandhi 18:6a4db94011d3 678
sahilmgandhi 18:6a4db94011d3 679 return event;
sahilmgandhi 18:6a4db94011d3 680 }
sahilmgandhi 18:6a4db94011d3 681
sahilmgandhi 18:6a4db94011d3 682 /** Attempts to determine if I2C peripheral is already in use.
sahilmgandhi 18:6a4db94011d3 683 * @param obj The I2C object
sahilmgandhi 18:6a4db94011d3 684 * @return non-zero if the I2C module is active or zero if it is not
sahilmgandhi 18:6a4db94011d3 685 */
sahilmgandhi 18:6a4db94011d3 686 uint8_t i2c_active(i2c_t *obj)
sahilmgandhi 18:6a4db94011d3 687 {
sahilmgandhi 18:6a4db94011d3 688
sahilmgandhi 18:6a4db94011d3 689 if(obj->i2c.i2c_base->TWI_SR & TWI_SR_ENDTX && obj->i2c.i2c_base->TWI_SR & TWI_SR_ENDRX)
sahilmgandhi 18:6a4db94011d3 690 return 0;
sahilmgandhi 18:6a4db94011d3 691
sahilmgandhi 18:6a4db94011d3 692 return 1;
sahilmgandhi 18:6a4db94011d3 693
sahilmgandhi 18:6a4db94011d3 694 }
sahilmgandhi 18:6a4db94011d3 695
sahilmgandhi 18:6a4db94011d3 696 /** Abort ongoing asynchronous transaction.
sahilmgandhi 18:6a4db94011d3 697 * @param obj The I2C object
sahilmgandhi 18:6a4db94011d3 698 */
sahilmgandhi 18:6a4db94011d3 699 void i2c_abort_asynch(i2c_t *obj)
sahilmgandhi 18:6a4db94011d3 700 {
sahilmgandhi 18:6a4db94011d3 701 /* Disable PDC transfers */
sahilmgandhi 18:6a4db94011d3 702 pdc_disable_transfer(obj->i2c.pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS);
sahilmgandhi 18:6a4db94011d3 703
sahilmgandhi 18:6a4db94011d3 704 /* Clear PDC buffer receive counter */
sahilmgandhi 18:6a4db94011d3 705 pdc_rx_clear_cnt(obj->i2c.pdc);
sahilmgandhi 18:6a4db94011d3 706
sahilmgandhi 18:6a4db94011d3 707 /* Disable I2C IRQ */
sahilmgandhi 18:6a4db94011d3 708 twi_disable_interrupt(obj->i2c.i2c_base, TWI_IDR_TXBUFE);
sahilmgandhi 18:6a4db94011d3 709 twi_disable_interrupt(obj->i2c.i2c_base, TWI_IDR_RXBUFF);
sahilmgandhi 18:6a4db94011d3 710
sahilmgandhi 18:6a4db94011d3 711 /* Disable I2C interrupt */
sahilmgandhi 18:6a4db94011d3 712 NVIC_DisableIRQ(obj->i2c.irq_type);
sahilmgandhi 18:6a4db94011d3 713 }
sahilmgandhi 18:6a4db94011d3 714
sahilmgandhi 18:6a4db94011d3 715 #endif