Mouse code for the MacroRat
mbed-dev/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/spi/spi_driver.h@46:b156ef445742, 2017-06-03 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sat Jun 03 00:22:44 2017 +0000
- Revision:
- 46:b156ef445742
- Parent:
- 18:6a4db94011d3
Final code for internal battlebot competition.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /** |
sahilmgandhi | 18:6a4db94011d3 | 2 | * \file |
sahilmgandhi | 18:6a4db94011d3 | 3 | * |
sahilmgandhi | 18:6a4db94011d3 | 4 | * \brief Serial Peripheral Interface (SPI) driver for SAM. |
sahilmgandhi | 18:6a4db94011d3 | 5 | * |
sahilmgandhi | 18:6a4db94011d3 | 6 | * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. |
sahilmgandhi | 18:6a4db94011d3 | 7 | * |
sahilmgandhi | 18:6a4db94011d3 | 8 | * \asf_license_start |
sahilmgandhi | 18:6a4db94011d3 | 9 | * |
sahilmgandhi | 18:6a4db94011d3 | 10 | * \page License |
sahilmgandhi | 18:6a4db94011d3 | 11 | * |
sahilmgandhi | 18:6a4db94011d3 | 12 | * Redistribution and use in source and binary forms, with or without |
sahilmgandhi | 18:6a4db94011d3 | 13 | * modification, are permitted provided that the following conditions are met: |
sahilmgandhi | 18:6a4db94011d3 | 14 | * |
sahilmgandhi | 18:6a4db94011d3 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 16 | * this list of conditions and the following disclaimer. |
sahilmgandhi | 18:6a4db94011d3 | 17 | * |
sahilmgandhi | 18:6a4db94011d3 | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 19 | * this list of conditions and the following disclaimer in the documentation |
sahilmgandhi | 18:6a4db94011d3 | 20 | * and/or other materials provided with the distribution. |
sahilmgandhi | 18:6a4db94011d3 | 21 | * |
sahilmgandhi | 18:6a4db94011d3 | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
sahilmgandhi | 18:6a4db94011d3 | 23 | * from this software without specific prior written permission. |
sahilmgandhi | 18:6a4db94011d3 | 24 | * |
sahilmgandhi | 18:6a4db94011d3 | 25 | * 4. This software may only be redistributed and used in connection with an |
sahilmgandhi | 18:6a4db94011d3 | 26 | * Atmel microcontroller product. |
sahilmgandhi | 18:6a4db94011d3 | 27 | * |
sahilmgandhi | 18:6a4db94011d3 | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
sahilmgandhi | 18:6a4db94011d3 | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
sahilmgandhi | 18:6a4db94011d3 | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
sahilmgandhi | 18:6a4db94011d3 | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
sahilmgandhi | 18:6a4db94011d3 | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
sahilmgandhi | 18:6a4db94011d3 | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
sahilmgandhi | 18:6a4db94011d3 | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
sahilmgandhi | 18:6a4db94011d3 | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
sahilmgandhi | 18:6a4db94011d3 | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
sahilmgandhi | 18:6a4db94011d3 | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
sahilmgandhi | 18:6a4db94011d3 | 38 | * POSSIBILITY OF SUCH DAMAGE. |
sahilmgandhi | 18:6a4db94011d3 | 39 | * |
sahilmgandhi | 18:6a4db94011d3 | 40 | * \asf_license_stop |
sahilmgandhi | 18:6a4db94011d3 | 41 | * |
sahilmgandhi | 18:6a4db94011d3 | 42 | */ |
sahilmgandhi | 18:6a4db94011d3 | 43 | /* |
sahilmgandhi | 18:6a4db94011d3 | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
sahilmgandhi | 18:6a4db94011d3 | 45 | */ |
sahilmgandhi | 18:6a4db94011d3 | 46 | |
sahilmgandhi | 18:6a4db94011d3 | 47 | #ifndef SPI_H_INCLUDED |
sahilmgandhi | 18:6a4db94011d3 | 48 | #define SPI_H_INCLUDED |
sahilmgandhi | 18:6a4db94011d3 | 49 | |
sahilmgandhi | 18:6a4db94011d3 | 50 | #include "compiler.h" |
sahilmgandhi | 18:6a4db94011d3 | 51 | |
sahilmgandhi | 18:6a4db94011d3 | 52 | /// @cond 0 |
sahilmgandhi | 18:6a4db94011d3 | 53 | /**INDENT-OFF**/ |
sahilmgandhi | 18:6a4db94011d3 | 54 | #ifdef __cplusplus |
sahilmgandhi | 18:6a4db94011d3 | 55 | extern "C" { |
sahilmgandhi | 18:6a4db94011d3 | 56 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 57 | /**INDENT-ON**/ |
sahilmgandhi | 18:6a4db94011d3 | 58 | /// @endcond |
sahilmgandhi | 18:6a4db94011d3 | 59 | |
sahilmgandhi | 18:6a4db94011d3 | 60 | /** Time-out value (number of attempts). */ |
sahilmgandhi | 18:6a4db94011d3 | 61 | #define SPI_TIMEOUT 15000 |
sahilmgandhi | 18:6a4db94011d3 | 62 | |
sahilmgandhi | 18:6a4db94011d3 | 63 | /** Status codes used by the SPI driver. */ |
sahilmgandhi | 18:6a4db94011d3 | 64 | typedef enum { |
sahilmgandhi | 18:6a4db94011d3 | 65 | SPI_ERROR = -1, |
sahilmgandhi | 18:6a4db94011d3 | 66 | SPI_OK = 0, |
sahilmgandhi | 18:6a4db94011d3 | 67 | SPI_ERROR_TIMEOUT = 1, |
sahilmgandhi | 18:6a4db94011d3 | 68 | SPI_ERROR_ARGUMENT, |
sahilmgandhi | 18:6a4db94011d3 | 69 | SPI_ERROR_OVERRUN, |
sahilmgandhi | 18:6a4db94011d3 | 70 | SPI_ERROR_MODE_FAULT, |
sahilmgandhi | 18:6a4db94011d3 | 71 | SPI_ERROR_OVERRUN_AND_MODE_FAULT |
sahilmgandhi | 18:6a4db94011d3 | 72 | } spi_status_t; |
sahilmgandhi | 18:6a4db94011d3 | 73 | |
sahilmgandhi | 18:6a4db94011d3 | 74 | /** SPI Chip Select behavior modes while transferring. */ |
sahilmgandhi | 18:6a4db94011d3 | 75 | typedef enum spi_cs_behavior { |
sahilmgandhi | 18:6a4db94011d3 | 76 | /** CS does not rise until a new transfer is requested on different chip select. */ |
sahilmgandhi | 18:6a4db94011d3 | 77 | SPI_CS_KEEP_LOW = SPI_CSR_CSAAT, |
sahilmgandhi | 18:6a4db94011d3 | 78 | /** CS rises if there is no more data to transfer. */ |
sahilmgandhi | 18:6a4db94011d3 | 79 | SPI_CS_RISE_NO_TX = 0, |
sahilmgandhi | 18:6a4db94011d3 | 80 | /** CS is de-asserted systematically during a time DLYBCS. */ |
sahilmgandhi | 18:6a4db94011d3 | 81 | SPI_CS_RISE_FORCED = SPI_CSR_CSNAAT |
sahilmgandhi | 18:6a4db94011d3 | 82 | } spi_cs_behavior_t; |
sahilmgandhi | 18:6a4db94011d3 | 83 | |
sahilmgandhi | 18:6a4db94011d3 | 84 | /** |
sahilmgandhi | 18:6a4db94011d3 | 85 | * \brief Generate Peripheral Chip Select Value from Chip Select ID |
sahilmgandhi | 18:6a4db94011d3 | 86 | * \note When chip select n is working, PCS bit n is set to low level. |
sahilmgandhi | 18:6a4db94011d3 | 87 | * |
sahilmgandhi | 18:6a4db94011d3 | 88 | * \param chip_sel_id The chip select number used |
sahilmgandhi | 18:6a4db94011d3 | 89 | */ |
sahilmgandhi | 18:6a4db94011d3 | 90 | #define spi_get_pcs(chip_sel_id) ((~(1u<<(chip_sel_id)))&0xF) |
sahilmgandhi | 18:6a4db94011d3 | 91 | |
sahilmgandhi | 18:6a4db94011d3 | 92 | /** |
sahilmgandhi | 18:6a4db94011d3 | 93 | * \brief Reset SPI and set it to Slave mode. |
sahilmgandhi | 18:6a4db94011d3 | 94 | * |
sahilmgandhi | 18:6a4db94011d3 | 95 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 96 | */ |
sahilmgandhi | 18:6a4db94011d3 | 97 | static inline void spi_reset(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 98 | { |
sahilmgandhi | 18:6a4db94011d3 | 99 | p_spi->SPI_CR = SPI_CR_SWRST; |
sahilmgandhi | 18:6a4db94011d3 | 100 | } |
sahilmgandhi | 18:6a4db94011d3 | 101 | |
sahilmgandhi | 18:6a4db94011d3 | 102 | /** |
sahilmgandhi | 18:6a4db94011d3 | 103 | * \brief Enable SPI. |
sahilmgandhi | 18:6a4db94011d3 | 104 | * |
sahilmgandhi | 18:6a4db94011d3 | 105 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 106 | */ |
sahilmgandhi | 18:6a4db94011d3 | 107 | static inline void spi_enable(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 108 | { |
sahilmgandhi | 18:6a4db94011d3 | 109 | p_spi->SPI_CR = SPI_CR_SPIEN; |
sahilmgandhi | 18:6a4db94011d3 | 110 | } |
sahilmgandhi | 18:6a4db94011d3 | 111 | |
sahilmgandhi | 18:6a4db94011d3 | 112 | /** |
sahilmgandhi | 18:6a4db94011d3 | 113 | * \brief Disable SPI. |
sahilmgandhi | 18:6a4db94011d3 | 114 | * |
sahilmgandhi | 18:6a4db94011d3 | 115 | * \note CS is de-asserted, which indicates that the last data is done, and user |
sahilmgandhi | 18:6a4db94011d3 | 116 | * should check TX_EMPTY before disabling SPI. |
sahilmgandhi | 18:6a4db94011d3 | 117 | * |
sahilmgandhi | 18:6a4db94011d3 | 118 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 119 | */ |
sahilmgandhi | 18:6a4db94011d3 | 120 | static inline void spi_disable(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 121 | { |
sahilmgandhi | 18:6a4db94011d3 | 122 | p_spi->SPI_CR = SPI_CR_SPIDIS; |
sahilmgandhi | 18:6a4db94011d3 | 123 | } |
sahilmgandhi | 18:6a4db94011d3 | 124 | |
sahilmgandhi | 18:6a4db94011d3 | 125 | /** |
sahilmgandhi | 18:6a4db94011d3 | 126 | * \brief Issue a LASTXFER command. |
sahilmgandhi | 18:6a4db94011d3 | 127 | * The next transfer is the last transfer and after that CS is de-asserted. |
sahilmgandhi | 18:6a4db94011d3 | 128 | * |
sahilmgandhi | 18:6a4db94011d3 | 129 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 130 | */ |
sahilmgandhi | 18:6a4db94011d3 | 131 | static inline void spi_set_lastxfer(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 132 | { |
sahilmgandhi | 18:6a4db94011d3 | 133 | p_spi->SPI_CR = SPI_CR_LASTXFER; |
sahilmgandhi | 18:6a4db94011d3 | 134 | } |
sahilmgandhi | 18:6a4db94011d3 | 135 | |
sahilmgandhi | 18:6a4db94011d3 | 136 | /** |
sahilmgandhi | 18:6a4db94011d3 | 137 | * \brief Set SPI to Master mode. |
sahilmgandhi | 18:6a4db94011d3 | 138 | * |
sahilmgandhi | 18:6a4db94011d3 | 139 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 140 | */ |
sahilmgandhi | 18:6a4db94011d3 | 141 | static inline void spi_set_master_mode(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 142 | { |
sahilmgandhi | 18:6a4db94011d3 | 143 | p_spi->SPI_MR |= SPI_MR_MSTR; |
sahilmgandhi | 18:6a4db94011d3 | 144 | } |
sahilmgandhi | 18:6a4db94011d3 | 145 | |
sahilmgandhi | 18:6a4db94011d3 | 146 | /** |
sahilmgandhi | 18:6a4db94011d3 | 147 | * \brief Set SPI to Slave mode. |
sahilmgandhi | 18:6a4db94011d3 | 148 | * |
sahilmgandhi | 18:6a4db94011d3 | 149 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 150 | */ |
sahilmgandhi | 18:6a4db94011d3 | 151 | static inline void spi_set_slave_mode(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 152 | { |
sahilmgandhi | 18:6a4db94011d3 | 153 | p_spi->SPI_MR &= (~SPI_MR_MSTR); |
sahilmgandhi | 18:6a4db94011d3 | 154 | } |
sahilmgandhi | 18:6a4db94011d3 | 155 | |
sahilmgandhi | 18:6a4db94011d3 | 156 | /** |
sahilmgandhi | 18:6a4db94011d3 | 157 | * \brief Get SPI work mode. |
sahilmgandhi | 18:6a4db94011d3 | 158 | * |
sahilmgandhi | 18:6a4db94011d3 | 159 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 160 | * |
sahilmgandhi | 18:6a4db94011d3 | 161 | * \return 1 for master mode, 0 for slave mode. |
sahilmgandhi | 18:6a4db94011d3 | 162 | */ |
sahilmgandhi | 18:6a4db94011d3 | 163 | static inline uint32_t spi_get_mode(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 164 | { |
sahilmgandhi | 18:6a4db94011d3 | 165 | if (p_spi->SPI_MR & SPI_MR_MSTR) { |
sahilmgandhi | 18:6a4db94011d3 | 166 | return 1; |
sahilmgandhi | 18:6a4db94011d3 | 167 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 168 | return 0; |
sahilmgandhi | 18:6a4db94011d3 | 169 | } |
sahilmgandhi | 18:6a4db94011d3 | 170 | } |
sahilmgandhi | 18:6a4db94011d3 | 171 | |
sahilmgandhi | 18:6a4db94011d3 | 172 | /** |
sahilmgandhi | 18:6a4db94011d3 | 173 | * \brief Set Variable Peripheral Select. |
sahilmgandhi | 18:6a4db94011d3 | 174 | * Peripheral Chip Select can be controlled by SPI_TDR. |
sahilmgandhi | 18:6a4db94011d3 | 175 | * |
sahilmgandhi | 18:6a4db94011d3 | 176 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 177 | */ |
sahilmgandhi | 18:6a4db94011d3 | 178 | static inline void spi_set_variable_peripheral_select(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 179 | { |
sahilmgandhi | 18:6a4db94011d3 | 180 | p_spi->SPI_MR |= SPI_MR_PS; |
sahilmgandhi | 18:6a4db94011d3 | 181 | } |
sahilmgandhi | 18:6a4db94011d3 | 182 | |
sahilmgandhi | 18:6a4db94011d3 | 183 | /** |
sahilmgandhi | 18:6a4db94011d3 | 184 | * \brief Set Fixed Peripheral Select. |
sahilmgandhi | 18:6a4db94011d3 | 185 | * Peripheral Chip Select is controlled by SPI_MR. |
sahilmgandhi | 18:6a4db94011d3 | 186 | * |
sahilmgandhi | 18:6a4db94011d3 | 187 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 188 | */ |
sahilmgandhi | 18:6a4db94011d3 | 189 | static inline void spi_set_fixed_peripheral_select(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 190 | { |
sahilmgandhi | 18:6a4db94011d3 | 191 | p_spi->SPI_MR &= (~SPI_MR_PS); |
sahilmgandhi | 18:6a4db94011d3 | 192 | } |
sahilmgandhi | 18:6a4db94011d3 | 193 | |
sahilmgandhi | 18:6a4db94011d3 | 194 | /** |
sahilmgandhi | 18:6a4db94011d3 | 195 | * \brief Get Peripheral Select mode. |
sahilmgandhi | 18:6a4db94011d3 | 196 | * |
sahilmgandhi | 18:6a4db94011d3 | 197 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 198 | * |
sahilmgandhi | 18:6a4db94011d3 | 199 | * \return 1 for Variable mode, 0 for fixed mode. |
sahilmgandhi | 18:6a4db94011d3 | 200 | */ |
sahilmgandhi | 18:6a4db94011d3 | 201 | static inline uint32_t spi_get_peripheral_select_mode(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 202 | { |
sahilmgandhi | 18:6a4db94011d3 | 203 | if (p_spi->SPI_MR & SPI_MR_PS) { |
sahilmgandhi | 18:6a4db94011d3 | 204 | return 1; |
sahilmgandhi | 18:6a4db94011d3 | 205 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 206 | return 0; |
sahilmgandhi | 18:6a4db94011d3 | 207 | } |
sahilmgandhi | 18:6a4db94011d3 | 208 | } |
sahilmgandhi | 18:6a4db94011d3 | 209 | |
sahilmgandhi | 18:6a4db94011d3 | 210 | /** |
sahilmgandhi | 18:6a4db94011d3 | 211 | * \brief Enable Peripheral Select Decode. |
sahilmgandhi | 18:6a4db94011d3 | 212 | * |
sahilmgandhi | 18:6a4db94011d3 | 213 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 214 | */ |
sahilmgandhi | 18:6a4db94011d3 | 215 | static inline void spi_enable_peripheral_select_decode(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 216 | { |
sahilmgandhi | 18:6a4db94011d3 | 217 | p_spi->SPI_MR |= SPI_MR_PCSDEC; |
sahilmgandhi | 18:6a4db94011d3 | 218 | } |
sahilmgandhi | 18:6a4db94011d3 | 219 | |
sahilmgandhi | 18:6a4db94011d3 | 220 | /** |
sahilmgandhi | 18:6a4db94011d3 | 221 | * \brief Disable Peripheral Select Decode. |
sahilmgandhi | 18:6a4db94011d3 | 222 | * |
sahilmgandhi | 18:6a4db94011d3 | 223 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 224 | */ |
sahilmgandhi | 18:6a4db94011d3 | 225 | static inline void spi_disable_peripheral_select_decode(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 226 | { |
sahilmgandhi | 18:6a4db94011d3 | 227 | p_spi->SPI_MR &= (~SPI_MR_PCSDEC); |
sahilmgandhi | 18:6a4db94011d3 | 228 | } |
sahilmgandhi | 18:6a4db94011d3 | 229 | |
sahilmgandhi | 18:6a4db94011d3 | 230 | /** |
sahilmgandhi | 18:6a4db94011d3 | 231 | * \brief Get Peripheral Select Decode mode. |
sahilmgandhi | 18:6a4db94011d3 | 232 | * |
sahilmgandhi | 18:6a4db94011d3 | 233 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 234 | * |
sahilmgandhi | 18:6a4db94011d3 | 235 | * \return 1 for decode mode, 0 for direct mode. |
sahilmgandhi | 18:6a4db94011d3 | 236 | */ |
sahilmgandhi | 18:6a4db94011d3 | 237 | static inline uint32_t spi_get_peripheral_select_decode_setting(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 238 | { |
sahilmgandhi | 18:6a4db94011d3 | 239 | if (p_spi->SPI_MR & SPI_MR_PCSDEC) { |
sahilmgandhi | 18:6a4db94011d3 | 240 | return 1; |
sahilmgandhi | 18:6a4db94011d3 | 241 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 242 | return 0; |
sahilmgandhi | 18:6a4db94011d3 | 243 | } |
sahilmgandhi | 18:6a4db94011d3 | 244 | } |
sahilmgandhi | 18:6a4db94011d3 | 245 | |
sahilmgandhi | 18:6a4db94011d3 | 246 | /** |
sahilmgandhi | 18:6a4db94011d3 | 247 | * \brief Enable Mode Fault Detection. |
sahilmgandhi | 18:6a4db94011d3 | 248 | * |
sahilmgandhi | 18:6a4db94011d3 | 249 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 250 | */ |
sahilmgandhi | 18:6a4db94011d3 | 251 | static inline void spi_enable_mode_fault_detect(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 252 | { |
sahilmgandhi | 18:6a4db94011d3 | 253 | p_spi->SPI_MR &= (~SPI_MR_MODFDIS); |
sahilmgandhi | 18:6a4db94011d3 | 254 | } |
sahilmgandhi | 18:6a4db94011d3 | 255 | |
sahilmgandhi | 18:6a4db94011d3 | 256 | /** |
sahilmgandhi | 18:6a4db94011d3 | 257 | * \brief Disable Mode Fault Detection. |
sahilmgandhi | 18:6a4db94011d3 | 258 | * |
sahilmgandhi | 18:6a4db94011d3 | 259 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 260 | */ |
sahilmgandhi | 18:6a4db94011d3 | 261 | static inline void spi_disable_mode_fault_detect(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 262 | { |
sahilmgandhi | 18:6a4db94011d3 | 263 | p_spi->SPI_MR |= SPI_MR_MODFDIS; |
sahilmgandhi | 18:6a4db94011d3 | 264 | } |
sahilmgandhi | 18:6a4db94011d3 | 265 | |
sahilmgandhi | 18:6a4db94011d3 | 266 | /** |
sahilmgandhi | 18:6a4db94011d3 | 267 | * \brief Check if mode fault detection is enabled. |
sahilmgandhi | 18:6a4db94011d3 | 268 | * |
sahilmgandhi | 18:6a4db94011d3 | 269 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 270 | * |
sahilmgandhi | 18:6a4db94011d3 | 271 | * \return 1 for disabled, 0 for enabled. |
sahilmgandhi | 18:6a4db94011d3 | 272 | */ |
sahilmgandhi | 18:6a4db94011d3 | 273 | static inline uint32_t spi_get_mode_fault_detect_setting(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 274 | { |
sahilmgandhi | 18:6a4db94011d3 | 275 | if (p_spi->SPI_MR & SPI_MR_MODFDIS) { |
sahilmgandhi | 18:6a4db94011d3 | 276 | return 1; |
sahilmgandhi | 18:6a4db94011d3 | 277 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 278 | return 0; |
sahilmgandhi | 18:6a4db94011d3 | 279 | } |
sahilmgandhi | 18:6a4db94011d3 | 280 | } |
sahilmgandhi | 18:6a4db94011d3 | 281 | |
sahilmgandhi | 18:6a4db94011d3 | 282 | /** |
sahilmgandhi | 18:6a4db94011d3 | 283 | * \brief Enable waiting RX_EMPTY before transfer starts. |
sahilmgandhi | 18:6a4db94011d3 | 284 | * |
sahilmgandhi | 18:6a4db94011d3 | 285 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 286 | */ |
sahilmgandhi | 18:6a4db94011d3 | 287 | static inline void spi_enable_tx_on_rx_empty(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 288 | { |
sahilmgandhi | 18:6a4db94011d3 | 289 | p_spi->SPI_MR |= SPI_MR_WDRBT; |
sahilmgandhi | 18:6a4db94011d3 | 290 | } |
sahilmgandhi | 18:6a4db94011d3 | 291 | |
sahilmgandhi | 18:6a4db94011d3 | 292 | /** |
sahilmgandhi | 18:6a4db94011d3 | 293 | * \brief Disable waiting RX_EMPTY before transfer starts. |
sahilmgandhi | 18:6a4db94011d3 | 294 | * |
sahilmgandhi | 18:6a4db94011d3 | 295 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 296 | */ |
sahilmgandhi | 18:6a4db94011d3 | 297 | static inline void spi_disable_tx_on_rx_empty(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 298 | { |
sahilmgandhi | 18:6a4db94011d3 | 299 | p_spi->SPI_MR &= (~SPI_MR_WDRBT); |
sahilmgandhi | 18:6a4db94011d3 | 300 | } |
sahilmgandhi | 18:6a4db94011d3 | 301 | |
sahilmgandhi | 18:6a4db94011d3 | 302 | /** |
sahilmgandhi | 18:6a4db94011d3 | 303 | * \brief Check if SPI waits RX_EMPTY before transfer starts. |
sahilmgandhi | 18:6a4db94011d3 | 304 | * |
sahilmgandhi | 18:6a4db94011d3 | 305 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 306 | * |
sahilmgandhi | 18:6a4db94011d3 | 307 | * \return 1 for SPI waits, 0 for no wait. |
sahilmgandhi | 18:6a4db94011d3 | 308 | */ |
sahilmgandhi | 18:6a4db94011d3 | 309 | static inline uint32_t spi_get_tx_on_rx_empty_setting(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 310 | { |
sahilmgandhi | 18:6a4db94011d3 | 311 | if (p_spi->SPI_MR & SPI_MR_WDRBT) { |
sahilmgandhi | 18:6a4db94011d3 | 312 | return 1; |
sahilmgandhi | 18:6a4db94011d3 | 313 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 314 | return 0; |
sahilmgandhi | 18:6a4db94011d3 | 315 | } |
sahilmgandhi | 18:6a4db94011d3 | 316 | } |
sahilmgandhi | 18:6a4db94011d3 | 317 | |
sahilmgandhi | 18:6a4db94011d3 | 318 | /** |
sahilmgandhi | 18:6a4db94011d3 | 319 | * \brief Enable loopback mode. |
sahilmgandhi | 18:6a4db94011d3 | 320 | * |
sahilmgandhi | 18:6a4db94011d3 | 321 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 322 | */ |
sahilmgandhi | 18:6a4db94011d3 | 323 | static inline void spi_enable_loopback(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 324 | { |
sahilmgandhi | 18:6a4db94011d3 | 325 | p_spi->SPI_MR |= SPI_MR_LLB; |
sahilmgandhi | 18:6a4db94011d3 | 326 | } |
sahilmgandhi | 18:6a4db94011d3 | 327 | |
sahilmgandhi | 18:6a4db94011d3 | 328 | /** |
sahilmgandhi | 18:6a4db94011d3 | 329 | * \brief Disable loopback mode. |
sahilmgandhi | 18:6a4db94011d3 | 330 | * |
sahilmgandhi | 18:6a4db94011d3 | 331 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 332 | */ |
sahilmgandhi | 18:6a4db94011d3 | 333 | static inline void spi_disable_loopback(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 334 | { |
sahilmgandhi | 18:6a4db94011d3 | 335 | p_spi->SPI_MR &= (~SPI_MR_LLB); |
sahilmgandhi | 18:6a4db94011d3 | 336 | } |
sahilmgandhi | 18:6a4db94011d3 | 337 | |
sahilmgandhi | 18:6a4db94011d3 | 338 | void spi_enable_clock(Spi *p_spi); |
sahilmgandhi | 18:6a4db94011d3 | 339 | void spi_disable_clock(Spi *p_spi); |
sahilmgandhi | 18:6a4db94011d3 | 340 | void spi_set_peripheral_chip_select_value(Spi *p_spi, uint32_t ul_value); |
sahilmgandhi | 18:6a4db94011d3 | 341 | void spi_set_delay_between_chip_select(Spi *p_spi, uint32_t ul_delay); |
sahilmgandhi | 18:6a4db94011d3 | 342 | spi_status_t spi_read(Spi *p_spi, uint16_t *us_data, uint8_t *p_pcs); |
sahilmgandhi | 18:6a4db94011d3 | 343 | spi_status_t spi_write(Spi *p_spi, uint16_t us_data, uint8_t uc_pcs, |
sahilmgandhi | 18:6a4db94011d3 | 344 | uint8_t uc_last); |
sahilmgandhi | 18:6a4db94011d3 | 345 | |
sahilmgandhi | 18:6a4db94011d3 | 346 | /** |
sahilmgandhi | 18:6a4db94011d3 | 347 | * \brief Read status register. |
sahilmgandhi | 18:6a4db94011d3 | 348 | * |
sahilmgandhi | 18:6a4db94011d3 | 349 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 350 | * |
sahilmgandhi | 18:6a4db94011d3 | 351 | * \return SPI status register value. |
sahilmgandhi | 18:6a4db94011d3 | 352 | */ |
sahilmgandhi | 18:6a4db94011d3 | 353 | static inline uint32_t spi_read_status(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 354 | { |
sahilmgandhi | 18:6a4db94011d3 | 355 | return p_spi->SPI_SR; |
sahilmgandhi | 18:6a4db94011d3 | 356 | } |
sahilmgandhi | 18:6a4db94011d3 | 357 | |
sahilmgandhi | 18:6a4db94011d3 | 358 | /** |
sahilmgandhi | 18:6a4db94011d3 | 359 | * \brief Test if the SPI is enabled. |
sahilmgandhi | 18:6a4db94011d3 | 360 | * |
sahilmgandhi | 18:6a4db94011d3 | 361 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 362 | * |
sahilmgandhi | 18:6a4db94011d3 | 363 | * \return 1 if the SPI is enabled, otherwise 0. |
sahilmgandhi | 18:6a4db94011d3 | 364 | */ |
sahilmgandhi | 18:6a4db94011d3 | 365 | static inline uint32_t spi_is_enabled(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 366 | { |
sahilmgandhi | 18:6a4db94011d3 | 367 | if (p_spi->SPI_SR & SPI_SR_SPIENS) { |
sahilmgandhi | 18:6a4db94011d3 | 368 | return 1; |
sahilmgandhi | 18:6a4db94011d3 | 369 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 370 | return 0; |
sahilmgandhi | 18:6a4db94011d3 | 371 | } |
sahilmgandhi | 18:6a4db94011d3 | 372 | } |
sahilmgandhi | 18:6a4db94011d3 | 373 | |
sahilmgandhi | 18:6a4db94011d3 | 374 | /** |
sahilmgandhi | 18:6a4db94011d3 | 375 | * \brief Put one data to a SPI peripheral. |
sahilmgandhi | 18:6a4db94011d3 | 376 | * |
sahilmgandhi | 18:6a4db94011d3 | 377 | * \param p_spi Base address of the SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 378 | * \param data The data byte to be loaded |
sahilmgandhi | 18:6a4db94011d3 | 379 | * |
sahilmgandhi | 18:6a4db94011d3 | 380 | */ |
sahilmgandhi | 18:6a4db94011d3 | 381 | static inline void spi_put(Spi *p_spi, uint16_t data) |
sahilmgandhi | 18:6a4db94011d3 | 382 | { |
sahilmgandhi | 18:6a4db94011d3 | 383 | p_spi->SPI_TDR = SPI_TDR_TD(data); |
sahilmgandhi | 18:6a4db94011d3 | 384 | } |
sahilmgandhi | 18:6a4db94011d3 | 385 | |
sahilmgandhi | 18:6a4db94011d3 | 386 | /** \brief Get one data to a SPI peripheral. |
sahilmgandhi | 18:6a4db94011d3 | 387 | * |
sahilmgandhi | 18:6a4db94011d3 | 388 | * \param p_spi Base address of the SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 389 | * \return The data byte |
sahilmgandhi | 18:6a4db94011d3 | 390 | * |
sahilmgandhi | 18:6a4db94011d3 | 391 | */ |
sahilmgandhi | 18:6a4db94011d3 | 392 | static inline uint16_t spi_get(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 393 | { |
sahilmgandhi | 18:6a4db94011d3 | 394 | return (p_spi->SPI_RDR & SPI_RDR_RD_Msk); |
sahilmgandhi | 18:6a4db94011d3 | 395 | } |
sahilmgandhi | 18:6a4db94011d3 | 396 | |
sahilmgandhi | 18:6a4db94011d3 | 397 | /** |
sahilmgandhi | 18:6a4db94011d3 | 398 | * \brief Check if all transmissions are complete. |
sahilmgandhi | 18:6a4db94011d3 | 399 | * |
sahilmgandhi | 18:6a4db94011d3 | 400 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 401 | * |
sahilmgandhi | 18:6a4db94011d3 | 402 | * \retval 1 if transmissions are complete. |
sahilmgandhi | 18:6a4db94011d3 | 403 | * \retval 0 if transmissions are not complete. |
sahilmgandhi | 18:6a4db94011d3 | 404 | */ |
sahilmgandhi | 18:6a4db94011d3 | 405 | static inline uint32_t spi_is_tx_empty(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 406 | { |
sahilmgandhi | 18:6a4db94011d3 | 407 | if (p_spi->SPI_SR & SPI_SR_TXEMPTY) { |
sahilmgandhi | 18:6a4db94011d3 | 408 | return 1; |
sahilmgandhi | 18:6a4db94011d3 | 409 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 410 | return 0; |
sahilmgandhi | 18:6a4db94011d3 | 411 | } |
sahilmgandhi | 18:6a4db94011d3 | 412 | } |
sahilmgandhi | 18:6a4db94011d3 | 413 | |
sahilmgandhi | 18:6a4db94011d3 | 414 | /** |
sahilmgandhi | 18:6a4db94011d3 | 415 | * \brief Check if all transmissions are ready. |
sahilmgandhi | 18:6a4db94011d3 | 416 | * |
sahilmgandhi | 18:6a4db94011d3 | 417 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 418 | * |
sahilmgandhi | 18:6a4db94011d3 | 419 | * \retval 1 if transmissions are complete. |
sahilmgandhi | 18:6a4db94011d3 | 420 | * \retval 0 if transmissions are not complete. |
sahilmgandhi | 18:6a4db94011d3 | 421 | */ |
sahilmgandhi | 18:6a4db94011d3 | 422 | static inline uint32_t spi_is_tx_ready(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 423 | { |
sahilmgandhi | 18:6a4db94011d3 | 424 | if (p_spi->SPI_SR & SPI_SR_TDRE) { |
sahilmgandhi | 18:6a4db94011d3 | 425 | return 1; |
sahilmgandhi | 18:6a4db94011d3 | 426 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 427 | return 0; |
sahilmgandhi | 18:6a4db94011d3 | 428 | } |
sahilmgandhi | 18:6a4db94011d3 | 429 | } |
sahilmgandhi | 18:6a4db94011d3 | 430 | |
sahilmgandhi | 18:6a4db94011d3 | 431 | /** |
sahilmgandhi | 18:6a4db94011d3 | 432 | * \brief Check if the SPI contains a received character. |
sahilmgandhi | 18:6a4db94011d3 | 433 | * |
sahilmgandhi | 18:6a4db94011d3 | 434 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 435 | * |
sahilmgandhi | 18:6a4db94011d3 | 436 | * \return 1 if the SPI Receive Holding Register is full, otherwise 0. |
sahilmgandhi | 18:6a4db94011d3 | 437 | */ |
sahilmgandhi | 18:6a4db94011d3 | 438 | static inline uint32_t spi_is_rx_full(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 439 | { |
sahilmgandhi | 18:6a4db94011d3 | 440 | if (p_spi->SPI_SR & SPI_SR_RDRF) { |
sahilmgandhi | 18:6a4db94011d3 | 441 | return 1; |
sahilmgandhi | 18:6a4db94011d3 | 442 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 443 | return 0; |
sahilmgandhi | 18:6a4db94011d3 | 444 | } |
sahilmgandhi | 18:6a4db94011d3 | 445 | } |
sahilmgandhi | 18:6a4db94011d3 | 446 | |
sahilmgandhi | 18:6a4db94011d3 | 447 | /** |
sahilmgandhi | 18:6a4db94011d3 | 448 | * \brief Check if all receptions are ready. |
sahilmgandhi | 18:6a4db94011d3 | 449 | * |
sahilmgandhi | 18:6a4db94011d3 | 450 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 451 | * |
sahilmgandhi | 18:6a4db94011d3 | 452 | * \return 1 if the SPI Receiver is ready, otherwise 0. |
sahilmgandhi | 18:6a4db94011d3 | 453 | */ |
sahilmgandhi | 18:6a4db94011d3 | 454 | static inline uint32_t spi_is_rx_ready(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 455 | { |
sahilmgandhi | 18:6a4db94011d3 | 456 | if ((p_spi->SPI_SR & (SPI_SR_RDRF | SPI_SR_TXEMPTY)) |
sahilmgandhi | 18:6a4db94011d3 | 457 | == (SPI_SR_RDRF | SPI_SR_TXEMPTY)) { |
sahilmgandhi | 18:6a4db94011d3 | 458 | return 1; |
sahilmgandhi | 18:6a4db94011d3 | 459 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 460 | return 0; |
sahilmgandhi | 18:6a4db94011d3 | 461 | } |
sahilmgandhi | 18:6a4db94011d3 | 462 | } |
sahilmgandhi | 18:6a4db94011d3 | 463 | |
sahilmgandhi | 18:6a4db94011d3 | 464 | /** |
sahilmgandhi | 18:6a4db94011d3 | 465 | * \brief Enable SPI interrupts. |
sahilmgandhi | 18:6a4db94011d3 | 466 | * |
sahilmgandhi | 18:6a4db94011d3 | 467 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 468 | * \param ul_sources Interrupts to be enabled. |
sahilmgandhi | 18:6a4db94011d3 | 469 | */ |
sahilmgandhi | 18:6a4db94011d3 | 470 | static inline void spi_enable_interrupt(Spi *p_spi, uint32_t ul_sources) |
sahilmgandhi | 18:6a4db94011d3 | 471 | { |
sahilmgandhi | 18:6a4db94011d3 | 472 | p_spi->SPI_IER = ul_sources; |
sahilmgandhi | 18:6a4db94011d3 | 473 | } |
sahilmgandhi | 18:6a4db94011d3 | 474 | |
sahilmgandhi | 18:6a4db94011d3 | 475 | /** |
sahilmgandhi | 18:6a4db94011d3 | 476 | * \brief Disable SPI interrupts. |
sahilmgandhi | 18:6a4db94011d3 | 477 | * |
sahilmgandhi | 18:6a4db94011d3 | 478 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 479 | * \param ul_sources Interrupts to be disabled. |
sahilmgandhi | 18:6a4db94011d3 | 480 | */ |
sahilmgandhi | 18:6a4db94011d3 | 481 | static inline void spi_disable_interrupt(Spi *p_spi, uint32_t ul_sources) |
sahilmgandhi | 18:6a4db94011d3 | 482 | { |
sahilmgandhi | 18:6a4db94011d3 | 483 | p_spi->SPI_IDR = ul_sources; |
sahilmgandhi | 18:6a4db94011d3 | 484 | } |
sahilmgandhi | 18:6a4db94011d3 | 485 | |
sahilmgandhi | 18:6a4db94011d3 | 486 | /** |
sahilmgandhi | 18:6a4db94011d3 | 487 | * \brief Read SPI interrupt mask. |
sahilmgandhi | 18:6a4db94011d3 | 488 | * |
sahilmgandhi | 18:6a4db94011d3 | 489 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 490 | * |
sahilmgandhi | 18:6a4db94011d3 | 491 | * \return The interrupt mask value. |
sahilmgandhi | 18:6a4db94011d3 | 492 | */ |
sahilmgandhi | 18:6a4db94011d3 | 493 | static inline uint32_t spi_read_interrupt_mask(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 494 | { |
sahilmgandhi | 18:6a4db94011d3 | 495 | return p_spi->SPI_IMR; |
sahilmgandhi | 18:6a4db94011d3 | 496 | } |
sahilmgandhi | 18:6a4db94011d3 | 497 | |
sahilmgandhi | 18:6a4db94011d3 | 498 | void spi_set_clock_polarity(Spi *p_spi, uint32_t ul_pcs_ch, |
sahilmgandhi | 18:6a4db94011d3 | 499 | uint32_t ul_polarity); |
sahilmgandhi | 18:6a4db94011d3 | 500 | void spi_set_clock_phase(Spi *p_spi, uint32_t ul_pcs_ch, uint32_t ul_phase); |
sahilmgandhi | 18:6a4db94011d3 | 501 | void spi_configure_cs_behavior(Spi *p_spi, uint32_t ul_pcs_ch, |
sahilmgandhi | 18:6a4db94011d3 | 502 | uint32_t ul_cs_behavior); |
sahilmgandhi | 18:6a4db94011d3 | 503 | void spi_set_bits_per_transfer(Spi *p_spi, uint32_t ul_pcs_ch, uint32_t ul_bits); |
sahilmgandhi | 18:6a4db94011d3 | 504 | int16_t spi_calc_baudrate_div(const uint32_t baudrate, uint32_t mck); |
sahilmgandhi | 18:6a4db94011d3 | 505 | void spi_set_baudrate_div(Spi *p_spi, uint32_t ul_pcs_ch, |
sahilmgandhi | 18:6a4db94011d3 | 506 | uint8_t uc_baudrate_divider); |
sahilmgandhi | 18:6a4db94011d3 | 507 | void spi_set_transfer_delay(Spi *p_spi, uint32_t ul_pcs_ch, uint8_t uc_dlybs, |
sahilmgandhi | 18:6a4db94011d3 | 508 | uint8_t uc_dlybct); |
sahilmgandhi | 18:6a4db94011d3 | 509 | |
sahilmgandhi | 18:6a4db94011d3 | 510 | #if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM) |
sahilmgandhi | 18:6a4db94011d3 | 511 | /** |
sahilmgandhi | 18:6a4db94011d3 | 512 | * \brief Get PDC registers base address. |
sahilmgandhi | 18:6a4db94011d3 | 513 | * |
sahilmgandhi | 18:6a4db94011d3 | 514 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 515 | * |
sahilmgandhi | 18:6a4db94011d3 | 516 | * \return PDC registers base for PDC driver to access. |
sahilmgandhi | 18:6a4db94011d3 | 517 | */ |
sahilmgandhi | 18:6a4db94011d3 | 518 | static inline Pdc *spi_get_pdc_base(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 519 | { |
sahilmgandhi | 18:6a4db94011d3 | 520 | return (Pdc *)&(p_spi->SPI_RPR); |
sahilmgandhi | 18:6a4db94011d3 | 521 | } |
sahilmgandhi | 18:6a4db94011d3 | 522 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 523 | |
sahilmgandhi | 18:6a4db94011d3 | 524 | #if (SAM3U || SAM3XA || SAMV71 || SAMV70 || SAME70 || SAMS70) |
sahilmgandhi | 18:6a4db94011d3 | 525 | /** |
sahilmgandhi | 18:6a4db94011d3 | 526 | * \brief Get transmit data register address for DMA operation. |
sahilmgandhi | 18:6a4db94011d3 | 527 | * |
sahilmgandhi | 18:6a4db94011d3 | 528 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 529 | * |
sahilmgandhi | 18:6a4db94011d3 | 530 | * \return Transmit address for DMA access. |
sahilmgandhi | 18:6a4db94011d3 | 531 | */ |
sahilmgandhi | 18:6a4db94011d3 | 532 | static inline void *spi_get_tx_access(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 533 | { |
sahilmgandhi | 18:6a4db94011d3 | 534 | return (void *)&(p_spi->SPI_TDR); |
sahilmgandhi | 18:6a4db94011d3 | 535 | } |
sahilmgandhi | 18:6a4db94011d3 | 536 | |
sahilmgandhi | 18:6a4db94011d3 | 537 | /** |
sahilmgandhi | 18:6a4db94011d3 | 538 | * \brief Get receive data register address for DMA operation. |
sahilmgandhi | 18:6a4db94011d3 | 539 | * |
sahilmgandhi | 18:6a4db94011d3 | 540 | * \param p_spi Pointer to an SPI instance. |
sahilmgandhi | 18:6a4db94011d3 | 541 | * |
sahilmgandhi | 18:6a4db94011d3 | 542 | * \return Receive address for DMA access. |
sahilmgandhi | 18:6a4db94011d3 | 543 | */ |
sahilmgandhi | 18:6a4db94011d3 | 544 | static inline void *spi_get_rx_access(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 545 | { |
sahilmgandhi | 18:6a4db94011d3 | 546 | return (void *)&(p_spi->SPI_RDR); |
sahilmgandhi | 18:6a4db94011d3 | 547 | } |
sahilmgandhi | 18:6a4db94011d3 | 548 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 549 | |
sahilmgandhi | 18:6a4db94011d3 | 550 | void spi_set_writeprotect(Spi *p_spi, uint32_t ul_enable); |
sahilmgandhi | 18:6a4db94011d3 | 551 | uint32_t spi_get_writeprotect_status(Spi *p_spi); |
sahilmgandhi | 18:6a4db94011d3 | 552 | |
sahilmgandhi | 18:6a4db94011d3 | 553 | /// @cond 0 |
sahilmgandhi | 18:6a4db94011d3 | 554 | /**INDENT-OFF**/ |
sahilmgandhi | 18:6a4db94011d3 | 555 | #ifdef __cplusplus |
sahilmgandhi | 18:6a4db94011d3 | 556 | } |
sahilmgandhi | 18:6a4db94011d3 | 557 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 558 | /**INDENT-ON**/ |
sahilmgandhi | 18:6a4db94011d3 | 559 | /// @endcond |
sahilmgandhi | 18:6a4db94011d3 | 560 | |
sahilmgandhi | 18:6a4db94011d3 | 561 | /** |
sahilmgandhi | 18:6a4db94011d3 | 562 | * \page sam_spi_quickstart Quickstart guide for SAM SPI driver |
sahilmgandhi | 18:6a4db94011d3 | 563 | * |
sahilmgandhi | 18:6a4db94011d3 | 564 | * This is the quickstart guide for the \ref spi_group "SAM SPI driver", |
sahilmgandhi | 18:6a4db94011d3 | 565 | * with step-by-step instructions on how to configure and use the driver in a |
sahilmgandhi | 18:6a4db94011d3 | 566 | * selection of use cases. |
sahilmgandhi | 18:6a4db94011d3 | 567 | * |
sahilmgandhi | 18:6a4db94011d3 | 568 | * The use cases contain several code fragments. The code fragments in the |
sahilmgandhi | 18:6a4db94011d3 | 569 | * steps for setup can be copied into a custom initialization function, while |
sahilmgandhi | 18:6a4db94011d3 | 570 | * the steps for usage can be copied into, e.g.the main application function. |
sahilmgandhi | 18:6a4db94011d3 | 571 | * |
sahilmgandhi | 18:6a4db94011d3 | 572 | * \section spi_basic_use_case Basic use case |
sahilmgandhi | 18:6a4db94011d3 | 573 | * In this basic use case, the SPI module are configured for: |
sahilmgandhi | 18:6a4db94011d3 | 574 | * - Master mode |
sahilmgandhi | 18:6a4db94011d3 | 575 | * - Interrupt-based handling |
sahilmgandhi | 18:6a4db94011d3 | 576 | * |
sahilmgandhi | 18:6a4db94011d3 | 577 | * \subsection sam_spi_quickstart_prereq Prerequisites |
sahilmgandhi | 18:6a4db94011d3 | 578 | * -# \ref sysclk_group "System Clock Management (Sysclock)" |
sahilmgandhi | 18:6a4db94011d3 | 579 | * |
sahilmgandhi | 18:6a4db94011d3 | 580 | * \section spi_basic_use_case_setup Setup steps |
sahilmgandhi | 18:6a4db94011d3 | 581 | * \subsection spi_basic_use_case_setup_code Example code |
sahilmgandhi | 18:6a4db94011d3 | 582 | * Add to application C-file: |
sahilmgandhi | 18:6a4db94011d3 | 583 | * \code |
sahilmgandhi | 18:6a4db94011d3 | 584 | void spi_master_init(Spi *p_spi) |
sahilmgandhi | 18:6a4db94011d3 | 585 | { |
sahilmgandhi | 18:6a4db94011d3 | 586 | spi_enable_clock(p_spi); |
sahilmgandhi | 18:6a4db94011d3 | 587 | spi_reset(p_spi); |
sahilmgandhi | 18:6a4db94011d3 | 588 | spi_set_master_mode(p_spi); |
sahilmgandhi | 18:6a4db94011d3 | 589 | spi_disable_mode_fault_detect(p_spi); |
sahilmgandhi | 18:6a4db94011d3 | 590 | spi_disable_loopback(p_spi); |
sahilmgandhi | 18:6a4db94011d3 | 591 | spi_set_peripheral_chip_select_value(p_spi, |
sahilmgandhi | 18:6a4db94011d3 | 592 | spi_get_pcs(DEFAULT_CHIP_ID)); |
sahilmgandhi | 18:6a4db94011d3 | 593 | spi_set_fixed_peripheral_select(p_spi); |
sahilmgandhi | 18:6a4db94011d3 | 594 | spi_disable_peripheral_select_decode(p_spi); |
sahilmgandhi | 18:6a4db94011d3 | 595 | spi_set_delay_between_chip_select(p_spi, CONFIG_SPI_MASTER_DELAY_BCS); |
sahilmgandhi | 18:6a4db94011d3 | 596 | } |
sahilmgandhi | 18:6a4db94011d3 | 597 | void spi_master_setup_device(Spi *p_spi, struct spi_device *device, |
sahilmgandhi | 18:6a4db94011d3 | 598 | spi_flags_t flags, uint32_t baud_rate, board_spi_select_id_t sel_id) |
sahilmgandhi | 18:6a4db94011d3 | 599 | { |
sahilmgandhi | 18:6a4db94011d3 | 600 | spi_set_transfer_delay(p_spi, device->id, CONFIG_SPI_MASTER_DELAY_BS, |
sahilmgandhi | 18:6a4db94011d3 | 601 | CONFIG_SPI_MASTER_DELAY_BCT); |
sahilmgandhi | 18:6a4db94011d3 | 602 | |
sahilmgandhi | 18:6a4db94011d3 | 603 | spi_set_bits_per_transfer(p_spi, device->id, CONFIG_SPI_MASTER_BITS_PER_TRANSFER); |
sahilmgandhi | 18:6a4db94011d3 | 604 | spi_set_baudrate_div(p_spi, device->id, |
sahilmgandhi | 18:6a4db94011d3 | 605 | spi_calc_baudrate_div(baud_rate, sysclk_get_cpu_hz())); |
sahilmgandhi | 18:6a4db94011d3 | 606 | |
sahilmgandhi | 18:6a4db94011d3 | 607 | spi_configure_cs_behavior(p_spi, device->id, SPI_CS_KEEP_LOW); |
sahilmgandhi | 18:6a4db94011d3 | 608 | |
sahilmgandhi | 18:6a4db94011d3 | 609 | spi_set_clock_polarity(p_spi, device->id, flags >> 1); |
sahilmgandhi | 18:6a4db94011d3 | 610 | spi_set_clock_phase(p_spi, device->id, ((flags & 0x1) ^ 0x1)); |
sahilmgandhi | 18:6a4db94011d3 | 611 | } |
sahilmgandhi | 18:6a4db94011d3 | 612 | \endcode |
sahilmgandhi | 18:6a4db94011d3 | 613 | * |
sahilmgandhi | 18:6a4db94011d3 | 614 | * \subsection spi_basic_use_case_setup_flow Workflow |
sahilmgandhi | 18:6a4db94011d3 | 615 | * -# Initialize the SPI in master mode: |
sahilmgandhi | 18:6a4db94011d3 | 616 | * - \code |
sahilmgandhi | 18:6a4db94011d3 | 617 | void spi_master_init(SPI_EXAMPLE); |
sahilmgandhi | 18:6a4db94011d3 | 618 | \endcode |
sahilmgandhi | 18:6a4db94011d3 | 619 | * -# Set up an SPI device: |
sahilmgandhi | 18:6a4db94011d3 | 620 | * - \code void spi_master_setup_device(SPI_EXAMPLE, &SPI_DEVICE_EXAMPLE, |
sahilmgandhi | 18:6a4db94011d3 | 621 | SPI_MODE_0, SPI_EXAMPLE_BAUDRATE, 0); \endcode |
sahilmgandhi | 18:6a4db94011d3 | 622 | * - \note The returned device descriptor structure must be passed to the driver |
sahilmgandhi | 18:6a4db94011d3 | 623 | * whenever that device should be used as current slave device. |
sahilmgandhi | 18:6a4db94011d3 | 624 | * -# Enable SPI module: |
sahilmgandhi | 18:6a4db94011d3 | 625 | * - \code spi_enable(SPI_EXAMPLE); \endcode |
sahilmgandhi | 18:6a4db94011d3 | 626 | */ |
sahilmgandhi | 18:6a4db94011d3 | 627 | #endif /* SPI_H_INCLUDED */ |