MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pmc/pmc.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 * \file
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * \brief Power Management Controller (PMC) driver for SAM.
sahilmgandhi 18:6a4db94011d3 5 *
sahilmgandhi 18:6a4db94011d3 6 * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * \asf_license_start
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * \page License
sahilmgandhi 18:6a4db94011d3 11 *
sahilmgandhi 18:6a4db94011d3 12 * Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 13 * modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 14 *
sahilmgandhi 18:6a4db94011d3 15 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 16 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 *
sahilmgandhi 18:6a4db94011d3 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 19 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 20 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 21 *
sahilmgandhi 18:6a4db94011d3 22 * 3. The name of Atmel may not be used to endorse or promote products derived
sahilmgandhi 18:6a4db94011d3 23 * from this software without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 24 *
sahilmgandhi 18:6a4db94011d3 25 * 4. This software may only be redistributed and used in connection with an
sahilmgandhi 18:6a4db94011d3 26 * Atmel microcontroller product.
sahilmgandhi 18:6a4db94011d3 27 *
sahilmgandhi 18:6a4db94011d3 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
sahilmgandhi 18:6a4db94011d3 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
sahilmgandhi 18:6a4db94011d3 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
sahilmgandhi 18:6a4db94011d3 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
sahilmgandhi 18:6a4db94011d3 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
sahilmgandhi 18:6a4db94011d3 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
sahilmgandhi 18:6a4db94011d3 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
sahilmgandhi 18:6a4db94011d3 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sahilmgandhi 18:6a4db94011d3 38 * POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 39 *
sahilmgandhi 18:6a4db94011d3 40 * \asf_license_stop
sahilmgandhi 18:6a4db94011d3 41 *
sahilmgandhi 18:6a4db94011d3 42 */
sahilmgandhi 18:6a4db94011d3 43 /*
sahilmgandhi 18:6a4db94011d3 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
sahilmgandhi 18:6a4db94011d3 45 */
sahilmgandhi 18:6a4db94011d3 46
sahilmgandhi 18:6a4db94011d3 47 #include "pmc.h"
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 #if (SAM3N)
sahilmgandhi 18:6a4db94011d3 50 # define MAX_PERIPH_ID 31
sahilmgandhi 18:6a4db94011d3 51 #elif (SAM3XA)
sahilmgandhi 18:6a4db94011d3 52 # define MAX_PERIPH_ID 44
sahilmgandhi 18:6a4db94011d3 53 #elif (SAM3U)
sahilmgandhi 18:6a4db94011d3 54 # define MAX_PERIPH_ID 29
sahilmgandhi 18:6a4db94011d3 55 #elif (SAM3S || SAM4S)
sahilmgandhi 18:6a4db94011d3 56 # define MAX_PERIPH_ID 34
sahilmgandhi 18:6a4db94011d3 57 #elif (SAM4E)
sahilmgandhi 18:6a4db94011d3 58 # define MAX_PERIPH_ID 47
sahilmgandhi 18:6a4db94011d3 59 #elif (SAMV71)
sahilmgandhi 18:6a4db94011d3 60 # define MAX_PERIPH_ID 63
sahilmgandhi 18:6a4db94011d3 61 #elif (SAMV70)
sahilmgandhi 18:6a4db94011d3 62 # define MAX_PERIPH_ID 63
sahilmgandhi 18:6a4db94011d3 63 #elif (SAME70)
sahilmgandhi 18:6a4db94011d3 64 # define MAX_PERIPH_ID 63
sahilmgandhi 18:6a4db94011d3 65 #elif (SAMS70)
sahilmgandhi 18:6a4db94011d3 66 # define MAX_PERIPH_ID 63
sahilmgandhi 18:6a4db94011d3 67 #elif (SAM4N)
sahilmgandhi 18:6a4db94011d3 68 # define MAX_PERIPH_ID 31
sahilmgandhi 18:6a4db94011d3 69 #elif (SAM4C || SAM4CM || SAM4CP)
sahilmgandhi 18:6a4db94011d3 70 # define MAX_PERIPH_ID 43
sahilmgandhi 18:6a4db94011d3 71 #elif (SAMG51)
sahilmgandhi 18:6a4db94011d3 72 # define MAX_PERIPH_ID 47
sahilmgandhi 18:6a4db94011d3 73 #elif (SAMG53)
sahilmgandhi 18:6a4db94011d3 74 # define MAX_PERIPH_ID 47
sahilmgandhi 18:6a4db94011d3 75 #elif (SAMG54)
sahilmgandhi 18:6a4db94011d3 76 # define MAX_PERIPH_ID 47
sahilmgandhi 18:6a4db94011d3 77 #elif (SAMG55)
sahilmgandhi 18:6a4db94011d3 78 # define MAX_PERIPH_ID 50
sahilmgandhi 18:6a4db94011d3 79 #endif
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 /// @cond 0
sahilmgandhi 18:6a4db94011d3 82 /**INDENT-OFF**/
sahilmgandhi 18:6a4db94011d3 83 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 84 extern "C" {
sahilmgandhi 18:6a4db94011d3 85 #endif
sahilmgandhi 18:6a4db94011d3 86 /**INDENT-ON**/
sahilmgandhi 18:6a4db94011d3 87 /// @endcond
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 /**
sahilmgandhi 18:6a4db94011d3 90 * \defgroup sam_drivers_pmc_group Power Management Controller (PMC)
sahilmgandhi 18:6a4db94011d3 91 *
sahilmgandhi 18:6a4db94011d3 92 * \par Purpose
sahilmgandhi 18:6a4db94011d3 93 *
sahilmgandhi 18:6a4db94011d3 94 * The Power Management Controller (PMC) optimizes power consumption by
sahilmgandhi 18:6a4db94011d3 95 * controlling all system and user peripheral clocks. The PMC enables/disables
sahilmgandhi 18:6a4db94011d3 96 * the clock inputs to many of the peripherals and the Cortex-M Processor.
sahilmgandhi 18:6a4db94011d3 97 *
sahilmgandhi 18:6a4db94011d3 98 * @{
sahilmgandhi 18:6a4db94011d3 99 */
sahilmgandhi 18:6a4db94011d3 100
sahilmgandhi 18:6a4db94011d3 101 /**
sahilmgandhi 18:6a4db94011d3 102 * \brief Set the prescaler of the MCK.
sahilmgandhi 18:6a4db94011d3 103 *
sahilmgandhi 18:6a4db94011d3 104 * \param ul_pres Prescaler value.
sahilmgandhi 18:6a4db94011d3 105 */
sahilmgandhi 18:6a4db94011d3 106 void pmc_mck_set_prescaler(uint32_t ul_pres)
sahilmgandhi 18:6a4db94011d3 107 {
sahilmgandhi 18:6a4db94011d3 108 PMC->PMC_MCKR =
sahilmgandhi 18:6a4db94011d3 109 (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
sahilmgandhi 18:6a4db94011d3 110 while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
sahilmgandhi 18:6a4db94011d3 111 }
sahilmgandhi 18:6a4db94011d3 112
sahilmgandhi 18:6a4db94011d3 113 #if SAMV71 || SAMV70 || SAME70 || SAMS70
sahilmgandhi 18:6a4db94011d3 114 /**
sahilmgandhi 18:6a4db94011d3 115 * \brief Set the division of the MCK.
sahilmgandhi 18:6a4db94011d3 116 *
sahilmgandhi 18:6a4db94011d3 117 * \param ul_div Division value.
sahilmgandhi 18:6a4db94011d3 118 */
sahilmgandhi 18:6a4db94011d3 119 void pmc_mck_set_division(uint32_t ul_div)
sahilmgandhi 18:6a4db94011d3 120 {
sahilmgandhi 18:6a4db94011d3 121 switch (ul_div) {
sahilmgandhi 18:6a4db94011d3 122 case 1:
sahilmgandhi 18:6a4db94011d3 123 ul_div = PMC_MCKR_MDIV_EQ_PCK;
sahilmgandhi 18:6a4db94011d3 124 break;
sahilmgandhi 18:6a4db94011d3 125 case 2:
sahilmgandhi 18:6a4db94011d3 126 ul_div = PMC_MCKR_MDIV_PCK_DIV2;
sahilmgandhi 18:6a4db94011d3 127 break;
sahilmgandhi 18:6a4db94011d3 128 case 3:
sahilmgandhi 18:6a4db94011d3 129 ul_div = PMC_MCKR_MDIV_PCK_DIV3;
sahilmgandhi 18:6a4db94011d3 130 break;
sahilmgandhi 18:6a4db94011d3 131 case 4:
sahilmgandhi 18:6a4db94011d3 132 ul_div = PMC_MCKR_MDIV_PCK_DIV4;
sahilmgandhi 18:6a4db94011d3 133 break;
sahilmgandhi 18:6a4db94011d3 134 default:
sahilmgandhi 18:6a4db94011d3 135 ul_div = PMC_MCKR_MDIV_EQ_PCK;
sahilmgandhi 18:6a4db94011d3 136 break;
sahilmgandhi 18:6a4db94011d3 137 }
sahilmgandhi 18:6a4db94011d3 138 PMC->PMC_MCKR =
sahilmgandhi 18:6a4db94011d3 139 (PMC->PMC_MCKR & (~PMC_MCKR_MDIV_Msk)) | ul_div;
sahilmgandhi 18:6a4db94011d3 140 while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
sahilmgandhi 18:6a4db94011d3 141 }
sahilmgandhi 18:6a4db94011d3 142 #endif
sahilmgandhi 18:6a4db94011d3 143
sahilmgandhi 18:6a4db94011d3 144 /**
sahilmgandhi 18:6a4db94011d3 145 * \brief Set the source of the MCK.
sahilmgandhi 18:6a4db94011d3 146 *
sahilmgandhi 18:6a4db94011d3 147 * \param ul_source Source selection value.
sahilmgandhi 18:6a4db94011d3 148 */
sahilmgandhi 18:6a4db94011d3 149 void pmc_mck_set_source(uint32_t ul_source)
sahilmgandhi 18:6a4db94011d3 150 {
sahilmgandhi 18:6a4db94011d3 151 PMC->PMC_MCKR =
sahilmgandhi 18:6a4db94011d3 152 (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | ul_source;
sahilmgandhi 18:6a4db94011d3 153 while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
sahilmgandhi 18:6a4db94011d3 154 }
sahilmgandhi 18:6a4db94011d3 155
sahilmgandhi 18:6a4db94011d3 156 /**
sahilmgandhi 18:6a4db94011d3 157 * \brief Switch master clock source selection to slow clock.
sahilmgandhi 18:6a4db94011d3 158 *
sahilmgandhi 18:6a4db94011d3 159 * \param ul_pres Processor clock prescaler.
sahilmgandhi 18:6a4db94011d3 160 *
sahilmgandhi 18:6a4db94011d3 161 * \retval 0 Success.
sahilmgandhi 18:6a4db94011d3 162 * \retval 1 Timeout error.
sahilmgandhi 18:6a4db94011d3 163 */
sahilmgandhi 18:6a4db94011d3 164 uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres)
sahilmgandhi 18:6a4db94011d3 165 {
sahilmgandhi 18:6a4db94011d3 166 uint32_t ul_timeout;
sahilmgandhi 18:6a4db94011d3 167
sahilmgandhi 18:6a4db94011d3 168 PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
sahilmgandhi 18:6a4db94011d3 169 PMC_MCKR_CSS_SLOW_CLK;
sahilmgandhi 18:6a4db94011d3 170 for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
sahilmgandhi 18:6a4db94011d3 171 --ul_timeout) {
sahilmgandhi 18:6a4db94011d3 172 if (ul_timeout == 0) {
sahilmgandhi 18:6a4db94011d3 173 return 1;
sahilmgandhi 18:6a4db94011d3 174 }
sahilmgandhi 18:6a4db94011d3 175 }
sahilmgandhi 18:6a4db94011d3 176
sahilmgandhi 18:6a4db94011d3 177 PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
sahilmgandhi 18:6a4db94011d3 178 for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
sahilmgandhi 18:6a4db94011d3 179 --ul_timeout) {
sahilmgandhi 18:6a4db94011d3 180 if (ul_timeout == 0) {
sahilmgandhi 18:6a4db94011d3 181 return 1;
sahilmgandhi 18:6a4db94011d3 182 }
sahilmgandhi 18:6a4db94011d3 183 }
sahilmgandhi 18:6a4db94011d3 184
sahilmgandhi 18:6a4db94011d3 185 return 0;
sahilmgandhi 18:6a4db94011d3 186 }
sahilmgandhi 18:6a4db94011d3 187
sahilmgandhi 18:6a4db94011d3 188 /**
sahilmgandhi 18:6a4db94011d3 189 * \brief Switch master clock source selection to main clock.
sahilmgandhi 18:6a4db94011d3 190 *
sahilmgandhi 18:6a4db94011d3 191 * \param ul_pres Processor clock prescaler.
sahilmgandhi 18:6a4db94011d3 192 *
sahilmgandhi 18:6a4db94011d3 193 * \retval 0 Success.
sahilmgandhi 18:6a4db94011d3 194 * \retval 1 Timeout error.
sahilmgandhi 18:6a4db94011d3 195 */
sahilmgandhi 18:6a4db94011d3 196 uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres)
sahilmgandhi 18:6a4db94011d3 197 {
sahilmgandhi 18:6a4db94011d3 198 uint32_t ul_timeout;
sahilmgandhi 18:6a4db94011d3 199
sahilmgandhi 18:6a4db94011d3 200 PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
sahilmgandhi 18:6a4db94011d3 201 PMC_MCKR_CSS_MAIN_CLK;
sahilmgandhi 18:6a4db94011d3 202 for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
sahilmgandhi 18:6a4db94011d3 203 --ul_timeout) {
sahilmgandhi 18:6a4db94011d3 204 if (ul_timeout == 0) {
sahilmgandhi 18:6a4db94011d3 205 return 1;
sahilmgandhi 18:6a4db94011d3 206 }
sahilmgandhi 18:6a4db94011d3 207 }
sahilmgandhi 18:6a4db94011d3 208
sahilmgandhi 18:6a4db94011d3 209 PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
sahilmgandhi 18:6a4db94011d3 210 for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
sahilmgandhi 18:6a4db94011d3 211 --ul_timeout) {
sahilmgandhi 18:6a4db94011d3 212 if (ul_timeout == 0) {
sahilmgandhi 18:6a4db94011d3 213 return 1;
sahilmgandhi 18:6a4db94011d3 214 }
sahilmgandhi 18:6a4db94011d3 215 }
sahilmgandhi 18:6a4db94011d3 216
sahilmgandhi 18:6a4db94011d3 217 return 0;
sahilmgandhi 18:6a4db94011d3 218 }
sahilmgandhi 18:6a4db94011d3 219
sahilmgandhi 18:6a4db94011d3 220 /**
sahilmgandhi 18:6a4db94011d3 221 * \brief Switch master clock source selection to PLLA clock.
sahilmgandhi 18:6a4db94011d3 222 *
sahilmgandhi 18:6a4db94011d3 223 * \param ul_pres Processor clock prescaler.
sahilmgandhi 18:6a4db94011d3 224 *
sahilmgandhi 18:6a4db94011d3 225 * \retval 0 Success.
sahilmgandhi 18:6a4db94011d3 226 * \retval 1 Timeout error.
sahilmgandhi 18:6a4db94011d3 227 */
sahilmgandhi 18:6a4db94011d3 228 uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres)
sahilmgandhi 18:6a4db94011d3 229 {
sahilmgandhi 18:6a4db94011d3 230 uint32_t ul_timeout;
sahilmgandhi 18:6a4db94011d3 231
sahilmgandhi 18:6a4db94011d3 232 PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
sahilmgandhi 18:6a4db94011d3 233 for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
sahilmgandhi 18:6a4db94011d3 234 --ul_timeout) {
sahilmgandhi 18:6a4db94011d3 235 if (ul_timeout == 0) {
sahilmgandhi 18:6a4db94011d3 236 return 1;
sahilmgandhi 18:6a4db94011d3 237 }
sahilmgandhi 18:6a4db94011d3 238 }
sahilmgandhi 18:6a4db94011d3 239
sahilmgandhi 18:6a4db94011d3 240 PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
sahilmgandhi 18:6a4db94011d3 241 PMC_MCKR_CSS_PLLA_CLK;
sahilmgandhi 18:6a4db94011d3 242
sahilmgandhi 18:6a4db94011d3 243 for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
sahilmgandhi 18:6a4db94011d3 244 --ul_timeout) {
sahilmgandhi 18:6a4db94011d3 245 if (ul_timeout == 0) {
sahilmgandhi 18:6a4db94011d3 246 return 1;
sahilmgandhi 18:6a4db94011d3 247 }
sahilmgandhi 18:6a4db94011d3 248 }
sahilmgandhi 18:6a4db94011d3 249
sahilmgandhi 18:6a4db94011d3 250 return 0;
sahilmgandhi 18:6a4db94011d3 251 }
sahilmgandhi 18:6a4db94011d3 252
sahilmgandhi 18:6a4db94011d3 253 #if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)
sahilmgandhi 18:6a4db94011d3 254 /**
sahilmgandhi 18:6a4db94011d3 255 * \brief Switch master clock source selection to PLLB clock.
sahilmgandhi 18:6a4db94011d3 256 *
sahilmgandhi 18:6a4db94011d3 257 * \param ul_pres Processor clock prescaler.
sahilmgandhi 18:6a4db94011d3 258 *
sahilmgandhi 18:6a4db94011d3 259 * \retval 0 Success.
sahilmgandhi 18:6a4db94011d3 260 * \retval 1 Timeout error.
sahilmgandhi 18:6a4db94011d3 261 */
sahilmgandhi 18:6a4db94011d3 262 uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres)
sahilmgandhi 18:6a4db94011d3 263 {
sahilmgandhi 18:6a4db94011d3 264 uint32_t ul_timeout;
sahilmgandhi 18:6a4db94011d3 265
sahilmgandhi 18:6a4db94011d3 266 PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
sahilmgandhi 18:6a4db94011d3 267 for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
sahilmgandhi 18:6a4db94011d3 268 --ul_timeout) {
sahilmgandhi 18:6a4db94011d3 269 if (ul_timeout == 0) {
sahilmgandhi 18:6a4db94011d3 270 return 1;
sahilmgandhi 18:6a4db94011d3 271 }
sahilmgandhi 18:6a4db94011d3 272 }
sahilmgandhi 18:6a4db94011d3 273
sahilmgandhi 18:6a4db94011d3 274 PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
sahilmgandhi 18:6a4db94011d3 275 PMC_MCKR_CSS_PLLB_CLK;
sahilmgandhi 18:6a4db94011d3 276 for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
sahilmgandhi 18:6a4db94011d3 277 --ul_timeout) {
sahilmgandhi 18:6a4db94011d3 278 if (ul_timeout == 0) {
sahilmgandhi 18:6a4db94011d3 279 return 1;
sahilmgandhi 18:6a4db94011d3 280 }
sahilmgandhi 18:6a4db94011d3 281 }
sahilmgandhi 18:6a4db94011d3 282
sahilmgandhi 18:6a4db94011d3 283 return 0;
sahilmgandhi 18:6a4db94011d3 284 }
sahilmgandhi 18:6a4db94011d3 285 #endif
sahilmgandhi 18:6a4db94011d3 286
sahilmgandhi 18:6a4db94011d3 287 #if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 288 /**
sahilmgandhi 18:6a4db94011d3 289 * \brief Switch master clock source selection to UPLL clock.
sahilmgandhi 18:6a4db94011d3 290 *
sahilmgandhi 18:6a4db94011d3 291 * \param ul_pres Processor clock prescaler.
sahilmgandhi 18:6a4db94011d3 292 *
sahilmgandhi 18:6a4db94011d3 293 * \retval 0 Success.
sahilmgandhi 18:6a4db94011d3 294 * \retval 1 Timeout error.
sahilmgandhi 18:6a4db94011d3 295 */
sahilmgandhi 18:6a4db94011d3 296 uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres)
sahilmgandhi 18:6a4db94011d3 297 {
sahilmgandhi 18:6a4db94011d3 298 uint32_t ul_timeout;
sahilmgandhi 18:6a4db94011d3 299
sahilmgandhi 18:6a4db94011d3 300 PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
sahilmgandhi 18:6a4db94011d3 301 for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
sahilmgandhi 18:6a4db94011d3 302 --ul_timeout) {
sahilmgandhi 18:6a4db94011d3 303 if (ul_timeout == 0) {
sahilmgandhi 18:6a4db94011d3 304 return 1;
sahilmgandhi 18:6a4db94011d3 305 }
sahilmgandhi 18:6a4db94011d3 306 }
sahilmgandhi 18:6a4db94011d3 307
sahilmgandhi 18:6a4db94011d3 308 PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
sahilmgandhi 18:6a4db94011d3 309 PMC_MCKR_CSS_UPLL_CLK;
sahilmgandhi 18:6a4db94011d3 310 for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
sahilmgandhi 18:6a4db94011d3 311 --ul_timeout) {
sahilmgandhi 18:6a4db94011d3 312 if (ul_timeout == 0) {
sahilmgandhi 18:6a4db94011d3 313 return 1;
sahilmgandhi 18:6a4db94011d3 314 }
sahilmgandhi 18:6a4db94011d3 315 }
sahilmgandhi 18:6a4db94011d3 316
sahilmgandhi 18:6a4db94011d3 317 return 0;
sahilmgandhi 18:6a4db94011d3 318 }
sahilmgandhi 18:6a4db94011d3 319 #endif
sahilmgandhi 18:6a4db94011d3 320
sahilmgandhi 18:6a4db94011d3 321 /**
sahilmgandhi 18:6a4db94011d3 322 * \brief Switch slow clock source selection to external 32k (Xtal or Bypass).
sahilmgandhi 18:6a4db94011d3 323 *
sahilmgandhi 18:6a4db94011d3 324 * \note Switching SCLK back to 32krc is only possible by shutting down the
sahilmgandhi 18:6a4db94011d3 325 * VDDIO power supply.
sahilmgandhi 18:6a4db94011d3 326 *
sahilmgandhi 18:6a4db94011d3 327 * \param ul_bypass 0 for Xtal, 1 for bypass.
sahilmgandhi 18:6a4db94011d3 328 */
sahilmgandhi 18:6a4db94011d3 329 void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass)
sahilmgandhi 18:6a4db94011d3 330 {
sahilmgandhi 18:6a4db94011d3 331 /* Set Bypass mode if required */
sahilmgandhi 18:6a4db94011d3 332 if (ul_bypass == 1) {
sahilmgandhi 18:6a4db94011d3 333 SUPC->SUPC_MR |= SUPC_MR_KEY_PASSWD |
sahilmgandhi 18:6a4db94011d3 334 SUPC_MR_OSCBYPASS;
sahilmgandhi 18:6a4db94011d3 335 }
sahilmgandhi 18:6a4db94011d3 336
sahilmgandhi 18:6a4db94011d3 337 SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL;
sahilmgandhi 18:6a4db94011d3 338 }
sahilmgandhi 18:6a4db94011d3 339
sahilmgandhi 18:6a4db94011d3 340 /**
sahilmgandhi 18:6a4db94011d3 341 * \brief Check if the external 32k Xtal is ready.
sahilmgandhi 18:6a4db94011d3 342 *
sahilmgandhi 18:6a4db94011d3 343 * \retval 1 External 32k Xtal is ready.
sahilmgandhi 18:6a4db94011d3 344 * \retval 0 External 32k Xtal is not ready.
sahilmgandhi 18:6a4db94011d3 345 */
sahilmgandhi 18:6a4db94011d3 346 uint32_t pmc_osc_is_ready_32kxtal(void)
sahilmgandhi 18:6a4db94011d3 347 {
sahilmgandhi 18:6a4db94011d3 348 return ((SUPC->SUPC_SR & SUPC_SR_OSCSEL)
sahilmgandhi 18:6a4db94011d3 349 && (PMC->PMC_SR & PMC_SR_OSCSELS));
sahilmgandhi 18:6a4db94011d3 350 }
sahilmgandhi 18:6a4db94011d3 351
sahilmgandhi 18:6a4db94011d3 352 /**
sahilmgandhi 18:6a4db94011d3 353 * \brief Switch main clock source selection to internal fast RC.
sahilmgandhi 18:6a4db94011d3 354 *
sahilmgandhi 18:6a4db94011d3 355 * \param ul_moscrcf Fast RC oscillator(4/8/12Mhz).
sahilmgandhi 18:6a4db94011d3 356 *
sahilmgandhi 18:6a4db94011d3 357 * \retval 0 Success.
sahilmgandhi 18:6a4db94011d3 358 * \retval 1 Timeout error.
sahilmgandhi 18:6a4db94011d3 359 * \retval 2 Invalid frequency.
sahilmgandhi 18:6a4db94011d3 360 */
sahilmgandhi 18:6a4db94011d3 361 void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf)
sahilmgandhi 18:6a4db94011d3 362 {
sahilmgandhi 18:6a4db94011d3 363 /* Enable Fast RC oscillator but DO NOT switch to RC now */
sahilmgandhi 18:6a4db94011d3 364 PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN);
sahilmgandhi 18:6a4db94011d3 365
sahilmgandhi 18:6a4db94011d3 366 /* Wait the Fast RC to stabilize */
sahilmgandhi 18:6a4db94011d3 367 while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
sahilmgandhi 18:6a4db94011d3 368
sahilmgandhi 18:6a4db94011d3 369 /* Change Fast RC oscillator frequency */
sahilmgandhi 18:6a4db94011d3 370 PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) |
sahilmgandhi 18:6a4db94011d3 371 CKGR_MOR_KEY_PASSWD | ul_moscrcf;
sahilmgandhi 18:6a4db94011d3 372
sahilmgandhi 18:6a4db94011d3 373 /* Wait the Fast RC to stabilize */
sahilmgandhi 18:6a4db94011d3 374 while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
sahilmgandhi 18:6a4db94011d3 375
sahilmgandhi 18:6a4db94011d3 376 /* Switch to Fast RC */
sahilmgandhi 18:6a4db94011d3 377 PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) |
sahilmgandhi 18:6a4db94011d3 378 CKGR_MOR_KEY_PASSWD;
sahilmgandhi 18:6a4db94011d3 379 }
sahilmgandhi 18:6a4db94011d3 380
sahilmgandhi 18:6a4db94011d3 381 /**
sahilmgandhi 18:6a4db94011d3 382 * \brief Enable fast RC oscillator.
sahilmgandhi 18:6a4db94011d3 383 *
sahilmgandhi 18:6a4db94011d3 384 * \param ul_rc Fast RC oscillator(4/8/12Mhz).
sahilmgandhi 18:6a4db94011d3 385 */
sahilmgandhi 18:6a4db94011d3 386 void pmc_osc_enable_fastrc(uint32_t ul_rc)
sahilmgandhi 18:6a4db94011d3 387 {
sahilmgandhi 18:6a4db94011d3 388 /* Enable Fast RC oscillator but DO NOT switch to RC */
sahilmgandhi 18:6a4db94011d3 389 PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN);
sahilmgandhi 18:6a4db94011d3 390 /* Wait the Fast RC to stabilize */
sahilmgandhi 18:6a4db94011d3 391 while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
sahilmgandhi 18:6a4db94011d3 392
sahilmgandhi 18:6a4db94011d3 393 /* Change Fast RC oscillator frequency */
sahilmgandhi 18:6a4db94011d3 394 PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) |
sahilmgandhi 18:6a4db94011d3 395 CKGR_MOR_KEY_PASSWD | ul_rc;
sahilmgandhi 18:6a4db94011d3 396 /* Wait the Fast RC to stabilize */
sahilmgandhi 18:6a4db94011d3 397 while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
sahilmgandhi 18:6a4db94011d3 398 }
sahilmgandhi 18:6a4db94011d3 399
sahilmgandhi 18:6a4db94011d3 400 /**
sahilmgandhi 18:6a4db94011d3 401 * \brief Disable the internal fast RC.
sahilmgandhi 18:6a4db94011d3 402 */
sahilmgandhi 18:6a4db94011d3 403 void pmc_osc_disable_fastrc(void)
sahilmgandhi 18:6a4db94011d3 404 {
sahilmgandhi 18:6a4db94011d3 405 /* Disable Fast RC oscillator */
sahilmgandhi 18:6a4db94011d3 406 PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN &
sahilmgandhi 18:6a4db94011d3 407 ~CKGR_MOR_MOSCRCF_Msk)
sahilmgandhi 18:6a4db94011d3 408 | CKGR_MOR_KEY_PASSWD;
sahilmgandhi 18:6a4db94011d3 409 }
sahilmgandhi 18:6a4db94011d3 410
sahilmgandhi 18:6a4db94011d3 411 /**
sahilmgandhi 18:6a4db94011d3 412 * \brief Check if the main fastrc is ready.
sahilmgandhi 18:6a4db94011d3 413 *
sahilmgandhi 18:6a4db94011d3 414 * \retval 0 Xtal is not ready, otherwise ready.
sahilmgandhi 18:6a4db94011d3 415 */
sahilmgandhi 18:6a4db94011d3 416 uint32_t pmc_osc_is_ready_fastrc(void)
sahilmgandhi 18:6a4db94011d3 417 {
sahilmgandhi 18:6a4db94011d3 418 return (PMC->PMC_SR & PMC_SR_MOSCRCS);
sahilmgandhi 18:6a4db94011d3 419 }
sahilmgandhi 18:6a4db94011d3 420
sahilmgandhi 18:6a4db94011d3 421 /**
sahilmgandhi 18:6a4db94011d3 422 * \brief Enable main XTAL oscillator.
sahilmgandhi 18:6a4db94011d3 423 *
sahilmgandhi 18:6a4db94011d3 424 * \param ul_xtal_startup_time Xtal start-up time, in number of slow clocks.
sahilmgandhi 18:6a4db94011d3 425 */
sahilmgandhi 18:6a4db94011d3 426 void pmc_osc_enable_main_xtal(uint32_t ul_xtal_startup_time)
sahilmgandhi 18:6a4db94011d3 427 {
sahilmgandhi 18:6a4db94011d3 428 uint32_t mor = PMC->CKGR_MOR;
sahilmgandhi 18:6a4db94011d3 429 mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN);
sahilmgandhi 18:6a4db94011d3 430 mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN |
sahilmgandhi 18:6a4db94011d3 431 CKGR_MOR_MOSCXTST(ul_xtal_startup_time);
sahilmgandhi 18:6a4db94011d3 432 PMC->CKGR_MOR = mor;
sahilmgandhi 18:6a4db94011d3 433 /* Wait the main Xtal to stabilize */
sahilmgandhi 18:6a4db94011d3 434 while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));
sahilmgandhi 18:6a4db94011d3 435 }
sahilmgandhi 18:6a4db94011d3 436
sahilmgandhi 18:6a4db94011d3 437 /**
sahilmgandhi 18:6a4db94011d3 438 * \brief Bypass main XTAL.
sahilmgandhi 18:6a4db94011d3 439 */
sahilmgandhi 18:6a4db94011d3 440 void pmc_osc_bypass_main_xtal(void)
sahilmgandhi 18:6a4db94011d3 441 {
sahilmgandhi 18:6a4db94011d3 442 uint32_t mor = PMC->CKGR_MOR;
sahilmgandhi 18:6a4db94011d3 443 mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN);
sahilmgandhi 18:6a4db94011d3 444 mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY;
sahilmgandhi 18:6a4db94011d3 445 /* Enable Crystal oscillator but DO NOT switch now. Keep MOSCSEL to 0 */
sahilmgandhi 18:6a4db94011d3 446 PMC->CKGR_MOR = mor;
sahilmgandhi 18:6a4db94011d3 447 /* The MOSCXTS in PMC_SR is automatically set */
sahilmgandhi 18:6a4db94011d3 448 }
sahilmgandhi 18:6a4db94011d3 449
sahilmgandhi 18:6a4db94011d3 450 /**
sahilmgandhi 18:6a4db94011d3 451 * \brief Disable the main Xtal.
sahilmgandhi 18:6a4db94011d3 452 */
sahilmgandhi 18:6a4db94011d3 453 void pmc_osc_disable_main_xtal(void)
sahilmgandhi 18:6a4db94011d3 454 {
sahilmgandhi 18:6a4db94011d3 455 uint32_t mor = PMC->CKGR_MOR;
sahilmgandhi 18:6a4db94011d3 456 mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN);
sahilmgandhi 18:6a4db94011d3 457 PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor;
sahilmgandhi 18:6a4db94011d3 458 }
sahilmgandhi 18:6a4db94011d3 459
sahilmgandhi 18:6a4db94011d3 460 /**
sahilmgandhi 18:6a4db94011d3 461 * \brief Check if the main crystal is bypassed.
sahilmgandhi 18:6a4db94011d3 462 *
sahilmgandhi 18:6a4db94011d3 463 * \retval 0 Xtal is bypassed, otherwise not.
sahilmgandhi 18:6a4db94011d3 464 */
sahilmgandhi 18:6a4db94011d3 465 uint32_t pmc_osc_is_bypassed_main_xtal(void)
sahilmgandhi 18:6a4db94011d3 466 {
sahilmgandhi 18:6a4db94011d3 467 return (PMC->CKGR_MOR & CKGR_MOR_MOSCXTBY);
sahilmgandhi 18:6a4db94011d3 468 }
sahilmgandhi 18:6a4db94011d3 469
sahilmgandhi 18:6a4db94011d3 470 /**
sahilmgandhi 18:6a4db94011d3 471 * \brief Check if the main crystal is ready.
sahilmgandhi 18:6a4db94011d3 472 *
sahilmgandhi 18:6a4db94011d3 473 * \note If main crystal is bypassed, it's always ready.
sahilmgandhi 18:6a4db94011d3 474 *
sahilmgandhi 18:6a4db94011d3 475 * \retval 0 main crystal is not ready, otherwise ready.
sahilmgandhi 18:6a4db94011d3 476 */
sahilmgandhi 18:6a4db94011d3 477 uint32_t pmc_osc_is_ready_main_xtal(void)
sahilmgandhi 18:6a4db94011d3 478 {
sahilmgandhi 18:6a4db94011d3 479 return (PMC->PMC_SR & PMC_SR_MOSCXTS);
sahilmgandhi 18:6a4db94011d3 480 }
sahilmgandhi 18:6a4db94011d3 481
sahilmgandhi 18:6a4db94011d3 482 /**
sahilmgandhi 18:6a4db94011d3 483 * \brief Switch main clock source selection to external Xtal/Bypass.
sahilmgandhi 18:6a4db94011d3 484 *
sahilmgandhi 18:6a4db94011d3 485 * \note The function may switch MCK to SCLK if MCK source is MAINCK to avoid
sahilmgandhi 18:6a4db94011d3 486 * any system crash.
sahilmgandhi 18:6a4db94011d3 487 *
sahilmgandhi 18:6a4db94011d3 488 * \note If used in Xtal mode, the Xtal is automatically enabled.
sahilmgandhi 18:6a4db94011d3 489 *
sahilmgandhi 18:6a4db94011d3 490 * \param ul_bypass 0 for Xtal, 1 for bypass.
sahilmgandhi 18:6a4db94011d3 491 *
sahilmgandhi 18:6a4db94011d3 492 * \retval 0 Success.
sahilmgandhi 18:6a4db94011d3 493 * \retval 1 Timeout error.
sahilmgandhi 18:6a4db94011d3 494 */
sahilmgandhi 18:6a4db94011d3 495 void pmc_switch_mainck_to_xtal(uint32_t ul_bypass,
sahilmgandhi 18:6a4db94011d3 496 uint32_t ul_xtal_startup_time)
sahilmgandhi 18:6a4db94011d3 497 {
sahilmgandhi 18:6a4db94011d3 498 /* Enable Main Xtal oscillator */
sahilmgandhi 18:6a4db94011d3 499 if (ul_bypass) {
sahilmgandhi 18:6a4db94011d3 500 PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |
sahilmgandhi 18:6a4db94011d3 501 CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY |
sahilmgandhi 18:6a4db94011d3 502 CKGR_MOR_MOSCSEL;
sahilmgandhi 18:6a4db94011d3 503 } else {
sahilmgandhi 18:6a4db94011d3 504 PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |
sahilmgandhi 18:6a4db94011d3 505 CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN |
sahilmgandhi 18:6a4db94011d3 506 CKGR_MOR_MOSCXTST(ul_xtal_startup_time);
sahilmgandhi 18:6a4db94011d3 507 /* Wait the Xtal to stabilize */
sahilmgandhi 18:6a4db94011d3 508 while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));
sahilmgandhi 18:6a4db94011d3 509
sahilmgandhi 18:6a4db94011d3 510 PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL;
sahilmgandhi 18:6a4db94011d3 511 }
sahilmgandhi 18:6a4db94011d3 512 }
sahilmgandhi 18:6a4db94011d3 513
sahilmgandhi 18:6a4db94011d3 514 /**
sahilmgandhi 18:6a4db94011d3 515 * \brief Disable the external Xtal.
sahilmgandhi 18:6a4db94011d3 516 *
sahilmgandhi 18:6a4db94011d3 517 * \param ul_bypass 0 for Xtal, 1 for bypass.
sahilmgandhi 18:6a4db94011d3 518 */
sahilmgandhi 18:6a4db94011d3 519 void pmc_osc_disable_xtal(uint32_t ul_bypass)
sahilmgandhi 18:6a4db94011d3 520 {
sahilmgandhi 18:6a4db94011d3 521 /* Disable xtal oscillator */
sahilmgandhi 18:6a4db94011d3 522 if (ul_bypass) {
sahilmgandhi 18:6a4db94011d3 523 PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |
sahilmgandhi 18:6a4db94011d3 524 CKGR_MOR_KEY_PASSWD;
sahilmgandhi 18:6a4db94011d3 525 } else {
sahilmgandhi 18:6a4db94011d3 526 PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |
sahilmgandhi 18:6a4db94011d3 527 CKGR_MOR_KEY_PASSWD;
sahilmgandhi 18:6a4db94011d3 528 }
sahilmgandhi 18:6a4db94011d3 529 }
sahilmgandhi 18:6a4db94011d3 530
sahilmgandhi 18:6a4db94011d3 531 /**
sahilmgandhi 18:6a4db94011d3 532 * \brief Check if the MAINCK is ready. Depending on MOSCEL, MAINCK can be one
sahilmgandhi 18:6a4db94011d3 533 * of Xtal, bypass or internal RC.
sahilmgandhi 18:6a4db94011d3 534 *
sahilmgandhi 18:6a4db94011d3 535 * \retval 1 Xtal is ready.
sahilmgandhi 18:6a4db94011d3 536 * \retval 0 Xtal is not ready.
sahilmgandhi 18:6a4db94011d3 537 */
sahilmgandhi 18:6a4db94011d3 538 uint32_t pmc_osc_is_ready_mainck(void)
sahilmgandhi 18:6a4db94011d3 539 {
sahilmgandhi 18:6a4db94011d3 540 return PMC->PMC_SR & PMC_SR_MOSCSELS;
sahilmgandhi 18:6a4db94011d3 541 }
sahilmgandhi 18:6a4db94011d3 542
sahilmgandhi 18:6a4db94011d3 543 /**
sahilmgandhi 18:6a4db94011d3 544 * \brief Select Main Crystal or internal RC as main clock source.
sahilmgandhi 18:6a4db94011d3 545 *
sahilmgandhi 18:6a4db94011d3 546 * \note This function will not enable/disable RC or Main Crystal.
sahilmgandhi 18:6a4db94011d3 547 *
sahilmgandhi 18:6a4db94011d3 548 * \param ul_xtal_rc 0 internal RC is selected, otherwise Main Crystal.
sahilmgandhi 18:6a4db94011d3 549 */
sahilmgandhi 18:6a4db94011d3 550 void pmc_mainck_osc_select(uint32_t ul_xtal_rc)
sahilmgandhi 18:6a4db94011d3 551 {
sahilmgandhi 18:6a4db94011d3 552 uint32_t mor = PMC->CKGR_MOR;
sahilmgandhi 18:6a4db94011d3 553 if (ul_xtal_rc) {
sahilmgandhi 18:6a4db94011d3 554 mor |= CKGR_MOR_MOSCSEL;
sahilmgandhi 18:6a4db94011d3 555 } else {
sahilmgandhi 18:6a4db94011d3 556 mor &= ~CKGR_MOR_MOSCSEL;
sahilmgandhi 18:6a4db94011d3 557 }
sahilmgandhi 18:6a4db94011d3 558 PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor;
sahilmgandhi 18:6a4db94011d3 559 }
sahilmgandhi 18:6a4db94011d3 560
sahilmgandhi 18:6a4db94011d3 561 /**
sahilmgandhi 18:6a4db94011d3 562 * \brief Enable PLLA clock.
sahilmgandhi 18:6a4db94011d3 563 *
sahilmgandhi 18:6a4db94011d3 564 * \param mula PLLA multiplier.
sahilmgandhi 18:6a4db94011d3 565 * \param pllacount PLLA counter.
sahilmgandhi 18:6a4db94011d3 566 * \param diva Divider.
sahilmgandhi 18:6a4db94011d3 567 */
sahilmgandhi 18:6a4db94011d3 568 void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva)
sahilmgandhi 18:6a4db94011d3 569 {
sahilmgandhi 18:6a4db94011d3 570 /* first disable the PLL to unlock the lock */
sahilmgandhi 18:6a4db94011d3 571 pmc_disable_pllack();
sahilmgandhi 18:6a4db94011d3 572
sahilmgandhi 18:6a4db94011d3 573 #if (SAM4C || SAM4CM || SAM4CP || SAMG)
sahilmgandhi 18:6a4db94011d3 574 PMC->CKGR_PLLAR = CKGR_PLLAR_PLLAEN(diva) |
sahilmgandhi 18:6a4db94011d3 575 CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula);
sahilmgandhi 18:6a4db94011d3 576 #else
sahilmgandhi 18:6a4db94011d3 577 PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_DIVA(diva) |
sahilmgandhi 18:6a4db94011d3 578 CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula);
sahilmgandhi 18:6a4db94011d3 579 #endif
sahilmgandhi 18:6a4db94011d3 580 while ((PMC->PMC_SR & PMC_SR_LOCKA) == 0);
sahilmgandhi 18:6a4db94011d3 581 }
sahilmgandhi 18:6a4db94011d3 582
sahilmgandhi 18:6a4db94011d3 583 /**
sahilmgandhi 18:6a4db94011d3 584 * \brief Disable PLLA clock.
sahilmgandhi 18:6a4db94011d3 585 */
sahilmgandhi 18:6a4db94011d3 586 void pmc_disable_pllack(void)
sahilmgandhi 18:6a4db94011d3 587 {
sahilmgandhi 18:6a4db94011d3 588 #if (SAM4C || SAM4CM || SAM4CP || SAMG)
sahilmgandhi 18:6a4db94011d3 589 PMC->CKGR_PLLAR = CKGR_PLLAR_MULA(0);
sahilmgandhi 18:6a4db94011d3 590 #else
sahilmgandhi 18:6a4db94011d3 591 PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0);
sahilmgandhi 18:6a4db94011d3 592 #endif
sahilmgandhi 18:6a4db94011d3 593 }
sahilmgandhi 18:6a4db94011d3 594
sahilmgandhi 18:6a4db94011d3 595 /**
sahilmgandhi 18:6a4db94011d3 596 * \brief Is PLLA locked?
sahilmgandhi 18:6a4db94011d3 597 *
sahilmgandhi 18:6a4db94011d3 598 * \retval 0 Not locked.
sahilmgandhi 18:6a4db94011d3 599 * \retval 1 Locked.
sahilmgandhi 18:6a4db94011d3 600 */
sahilmgandhi 18:6a4db94011d3 601 uint32_t pmc_is_locked_pllack(void)
sahilmgandhi 18:6a4db94011d3 602 {
sahilmgandhi 18:6a4db94011d3 603 return (PMC->PMC_SR & PMC_SR_LOCKA);
sahilmgandhi 18:6a4db94011d3 604 }
sahilmgandhi 18:6a4db94011d3 605
sahilmgandhi 18:6a4db94011d3 606 #if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)
sahilmgandhi 18:6a4db94011d3 607 /**
sahilmgandhi 18:6a4db94011d3 608 * \brief Enable PLLB clock.
sahilmgandhi 18:6a4db94011d3 609 *
sahilmgandhi 18:6a4db94011d3 610 * \param mulb PLLB multiplier.
sahilmgandhi 18:6a4db94011d3 611 * \param pllbcount PLLB counter.
sahilmgandhi 18:6a4db94011d3 612 * \param divb Divider.
sahilmgandhi 18:6a4db94011d3 613 */
sahilmgandhi 18:6a4db94011d3 614 void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb)
sahilmgandhi 18:6a4db94011d3 615 {
sahilmgandhi 18:6a4db94011d3 616 /* first disable the PLL to unlock the lock */
sahilmgandhi 18:6a4db94011d3 617 pmc_disable_pllbck();
sahilmgandhi 18:6a4db94011d3 618
sahilmgandhi 18:6a4db94011d3 619 #if SAMG55
sahilmgandhi 18:6a4db94011d3 620 PMC->CKGR_PLLAR = CKGR_PLLAR_PLLAEN(divb) |
sahilmgandhi 18:6a4db94011d3 621 CKGR_PLLAR_PLLACOUNT(pllbcount) | CKGR_PLLAR_MULA(mulb);
sahilmgandhi 18:6a4db94011d3 622 #else
sahilmgandhi 18:6a4db94011d3 623 PMC->CKGR_PLLBR =
sahilmgandhi 18:6a4db94011d3 624 CKGR_PLLBR_DIVB(divb) | CKGR_PLLBR_PLLBCOUNT(pllbcount)
sahilmgandhi 18:6a4db94011d3 625 | CKGR_PLLBR_MULB(mulb);
sahilmgandhi 18:6a4db94011d3 626 #endif
sahilmgandhi 18:6a4db94011d3 627 while ((PMC->PMC_SR & PMC_SR_LOCKB) == 0);
sahilmgandhi 18:6a4db94011d3 628 }
sahilmgandhi 18:6a4db94011d3 629
sahilmgandhi 18:6a4db94011d3 630 /**
sahilmgandhi 18:6a4db94011d3 631 * \brief Disable PLLB clock.
sahilmgandhi 18:6a4db94011d3 632 */
sahilmgandhi 18:6a4db94011d3 633 void pmc_disable_pllbck(void)
sahilmgandhi 18:6a4db94011d3 634 {
sahilmgandhi 18:6a4db94011d3 635 PMC->CKGR_PLLBR = CKGR_PLLBR_MULB(0);
sahilmgandhi 18:6a4db94011d3 636 }
sahilmgandhi 18:6a4db94011d3 637
sahilmgandhi 18:6a4db94011d3 638 /**
sahilmgandhi 18:6a4db94011d3 639 * \brief Is PLLB locked?
sahilmgandhi 18:6a4db94011d3 640 *
sahilmgandhi 18:6a4db94011d3 641 * \retval 0 Not locked.
sahilmgandhi 18:6a4db94011d3 642 * \retval 1 Locked.
sahilmgandhi 18:6a4db94011d3 643 */
sahilmgandhi 18:6a4db94011d3 644 uint32_t pmc_is_locked_pllbck(void)
sahilmgandhi 18:6a4db94011d3 645 {
sahilmgandhi 18:6a4db94011d3 646 return (PMC->PMC_SR & PMC_SR_LOCKB);
sahilmgandhi 18:6a4db94011d3 647 }
sahilmgandhi 18:6a4db94011d3 648 #endif
sahilmgandhi 18:6a4db94011d3 649
sahilmgandhi 18:6a4db94011d3 650 #if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 651 /**
sahilmgandhi 18:6a4db94011d3 652 * \brief Enable UPLL clock.
sahilmgandhi 18:6a4db94011d3 653 */
sahilmgandhi 18:6a4db94011d3 654 void pmc_enable_upll_clock(void)
sahilmgandhi 18:6a4db94011d3 655 {
sahilmgandhi 18:6a4db94011d3 656 PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(3) | CKGR_UCKR_UPLLEN;
sahilmgandhi 18:6a4db94011d3 657
sahilmgandhi 18:6a4db94011d3 658 /* Wait UTMI PLL Lock Status */
sahilmgandhi 18:6a4db94011d3 659 while (!(PMC->PMC_SR & PMC_SR_LOCKU));
sahilmgandhi 18:6a4db94011d3 660 }
sahilmgandhi 18:6a4db94011d3 661
sahilmgandhi 18:6a4db94011d3 662 /**
sahilmgandhi 18:6a4db94011d3 663 * \brief Disable UPLL clock.
sahilmgandhi 18:6a4db94011d3 664 */
sahilmgandhi 18:6a4db94011d3 665 void pmc_disable_upll_clock(void)
sahilmgandhi 18:6a4db94011d3 666 {
sahilmgandhi 18:6a4db94011d3 667 PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN;
sahilmgandhi 18:6a4db94011d3 668 }
sahilmgandhi 18:6a4db94011d3 669
sahilmgandhi 18:6a4db94011d3 670 /**
sahilmgandhi 18:6a4db94011d3 671 * \brief Is UPLL locked?
sahilmgandhi 18:6a4db94011d3 672 *
sahilmgandhi 18:6a4db94011d3 673 * \retval 0 Not locked.
sahilmgandhi 18:6a4db94011d3 674 * \retval 1 Locked.
sahilmgandhi 18:6a4db94011d3 675 */
sahilmgandhi 18:6a4db94011d3 676 uint32_t pmc_is_locked_upll(void)
sahilmgandhi 18:6a4db94011d3 677 {
sahilmgandhi 18:6a4db94011d3 678 return (PMC->PMC_SR & PMC_SR_LOCKU);
sahilmgandhi 18:6a4db94011d3 679 }
sahilmgandhi 18:6a4db94011d3 680 #endif
sahilmgandhi 18:6a4db94011d3 681
sahilmgandhi 18:6a4db94011d3 682 /**
sahilmgandhi 18:6a4db94011d3 683 * \brief Enable the specified peripheral clock.
sahilmgandhi 18:6a4db94011d3 684 *
sahilmgandhi 18:6a4db94011d3 685 * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
sahilmgandhi 18:6a4db94011d3 686 *
sahilmgandhi 18:6a4db94011d3 687 * \param ul_id Peripheral ID (ID_xxx).
sahilmgandhi 18:6a4db94011d3 688 *
sahilmgandhi 18:6a4db94011d3 689 * \retval 0 Success.
sahilmgandhi 18:6a4db94011d3 690 * \retval 1 Invalid parameter.
sahilmgandhi 18:6a4db94011d3 691 */
sahilmgandhi 18:6a4db94011d3 692 uint32_t pmc_enable_periph_clk(uint32_t ul_id)
sahilmgandhi 18:6a4db94011d3 693 {
sahilmgandhi 18:6a4db94011d3 694 if (ul_id > MAX_PERIPH_ID) {
sahilmgandhi 18:6a4db94011d3 695 return 1;
sahilmgandhi 18:6a4db94011d3 696 }
sahilmgandhi 18:6a4db94011d3 697
sahilmgandhi 18:6a4db94011d3 698 if (ul_id < 32) {
sahilmgandhi 18:6a4db94011d3 699 if ((PMC->PMC_PCSR0 & (1u << ul_id)) != (1u << ul_id)) {
sahilmgandhi 18:6a4db94011d3 700 PMC->PMC_PCER0 = 1 << ul_id;
sahilmgandhi 18:6a4db94011d3 701 }
sahilmgandhi 18:6a4db94011d3 702 #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 703 } else {
sahilmgandhi 18:6a4db94011d3 704 ul_id -= 32;
sahilmgandhi 18:6a4db94011d3 705 if ((PMC->PMC_PCSR1 & (1u << ul_id)) != (1u << ul_id)) {
sahilmgandhi 18:6a4db94011d3 706 PMC->PMC_PCER1 = 1 << ul_id;
sahilmgandhi 18:6a4db94011d3 707 }
sahilmgandhi 18:6a4db94011d3 708 #endif
sahilmgandhi 18:6a4db94011d3 709 }
sahilmgandhi 18:6a4db94011d3 710
sahilmgandhi 18:6a4db94011d3 711 return 0;
sahilmgandhi 18:6a4db94011d3 712 }
sahilmgandhi 18:6a4db94011d3 713
sahilmgandhi 18:6a4db94011d3 714 /**
sahilmgandhi 18:6a4db94011d3 715 * \brief Disable the specified peripheral clock.
sahilmgandhi 18:6a4db94011d3 716 *
sahilmgandhi 18:6a4db94011d3 717 * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
sahilmgandhi 18:6a4db94011d3 718 *
sahilmgandhi 18:6a4db94011d3 719 * \param ul_id Peripheral ID (ID_xxx).
sahilmgandhi 18:6a4db94011d3 720 *
sahilmgandhi 18:6a4db94011d3 721 * \retval 0 Success.
sahilmgandhi 18:6a4db94011d3 722 * \retval 1 Invalid parameter.
sahilmgandhi 18:6a4db94011d3 723 */
sahilmgandhi 18:6a4db94011d3 724 uint32_t pmc_disable_periph_clk(uint32_t ul_id)
sahilmgandhi 18:6a4db94011d3 725 {
sahilmgandhi 18:6a4db94011d3 726 if (ul_id > MAX_PERIPH_ID) {
sahilmgandhi 18:6a4db94011d3 727 return 1;
sahilmgandhi 18:6a4db94011d3 728 }
sahilmgandhi 18:6a4db94011d3 729
sahilmgandhi 18:6a4db94011d3 730 if (ul_id < 32) {
sahilmgandhi 18:6a4db94011d3 731 if ((PMC->PMC_PCSR0 & (1u << ul_id)) == (1u << ul_id)) {
sahilmgandhi 18:6a4db94011d3 732 PMC->PMC_PCDR0 = 1 << ul_id;
sahilmgandhi 18:6a4db94011d3 733 }
sahilmgandhi 18:6a4db94011d3 734 #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 \
sahilmgandhi 18:6a4db94011d3 735 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 736 } else {
sahilmgandhi 18:6a4db94011d3 737 ul_id -= 32;
sahilmgandhi 18:6a4db94011d3 738 if ((PMC->PMC_PCSR1 & (1u << ul_id)) == (1u << ul_id)) {
sahilmgandhi 18:6a4db94011d3 739 PMC->PMC_PCDR1 = 1 << ul_id;
sahilmgandhi 18:6a4db94011d3 740 }
sahilmgandhi 18:6a4db94011d3 741 #endif
sahilmgandhi 18:6a4db94011d3 742 }
sahilmgandhi 18:6a4db94011d3 743 return 0;
sahilmgandhi 18:6a4db94011d3 744 }
sahilmgandhi 18:6a4db94011d3 745
sahilmgandhi 18:6a4db94011d3 746 /**
sahilmgandhi 18:6a4db94011d3 747 * \brief Enable all peripheral clocks.
sahilmgandhi 18:6a4db94011d3 748 */
sahilmgandhi 18:6a4db94011d3 749 void pmc_enable_all_periph_clk(void)
sahilmgandhi 18:6a4db94011d3 750 {
sahilmgandhi 18:6a4db94011d3 751 PMC->PMC_PCER0 = PMC_MASK_STATUS0;
sahilmgandhi 18:6a4db94011d3 752 while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != PMC_MASK_STATUS0);
sahilmgandhi 18:6a4db94011d3 753
sahilmgandhi 18:6a4db94011d3 754 #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \
sahilmgandhi 18:6a4db94011d3 755 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 756 PMC->PMC_PCER1 = PMC_MASK_STATUS1;
sahilmgandhi 18:6a4db94011d3 757 while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != PMC_MASK_STATUS1);
sahilmgandhi 18:6a4db94011d3 758 #endif
sahilmgandhi 18:6a4db94011d3 759 }
sahilmgandhi 18:6a4db94011d3 760
sahilmgandhi 18:6a4db94011d3 761 /**
sahilmgandhi 18:6a4db94011d3 762 * \brief Disable all peripheral clocks.
sahilmgandhi 18:6a4db94011d3 763 */
sahilmgandhi 18:6a4db94011d3 764 void pmc_disable_all_periph_clk(void)
sahilmgandhi 18:6a4db94011d3 765 {
sahilmgandhi 18:6a4db94011d3 766 PMC->PMC_PCDR0 = PMC_MASK_STATUS0;
sahilmgandhi 18:6a4db94011d3 767 while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != 0);
sahilmgandhi 18:6a4db94011d3 768
sahilmgandhi 18:6a4db94011d3 769 #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \
sahilmgandhi 18:6a4db94011d3 770 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 771 PMC->PMC_PCDR1 = PMC_MASK_STATUS1;
sahilmgandhi 18:6a4db94011d3 772 while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != 0);
sahilmgandhi 18:6a4db94011d3 773 #endif
sahilmgandhi 18:6a4db94011d3 774 }
sahilmgandhi 18:6a4db94011d3 775
sahilmgandhi 18:6a4db94011d3 776 /**
sahilmgandhi 18:6a4db94011d3 777 * \brief Check if the specified peripheral clock is enabled.
sahilmgandhi 18:6a4db94011d3 778 *
sahilmgandhi 18:6a4db94011d3 779 * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
sahilmgandhi 18:6a4db94011d3 780 *
sahilmgandhi 18:6a4db94011d3 781 * \param ul_id Peripheral ID (ID_xxx).
sahilmgandhi 18:6a4db94011d3 782 *
sahilmgandhi 18:6a4db94011d3 783 * \retval 0 Peripheral clock is disabled or unknown.
sahilmgandhi 18:6a4db94011d3 784 * \retval 1 Peripheral clock is enabled.
sahilmgandhi 18:6a4db94011d3 785 */
sahilmgandhi 18:6a4db94011d3 786 uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id)
sahilmgandhi 18:6a4db94011d3 787 {
sahilmgandhi 18:6a4db94011d3 788 if (ul_id > MAX_PERIPH_ID) {
sahilmgandhi 18:6a4db94011d3 789 return 0;
sahilmgandhi 18:6a4db94011d3 790 }
sahilmgandhi 18:6a4db94011d3 791
sahilmgandhi 18:6a4db94011d3 792 #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \
sahilmgandhi 18:6a4db94011d3 793 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 794 if (ul_id < 32) {
sahilmgandhi 18:6a4db94011d3 795 #endif
sahilmgandhi 18:6a4db94011d3 796 if ((PMC->PMC_PCSR0 & (1u << ul_id))) {
sahilmgandhi 18:6a4db94011d3 797 return 1;
sahilmgandhi 18:6a4db94011d3 798 } else {
sahilmgandhi 18:6a4db94011d3 799 return 0;
sahilmgandhi 18:6a4db94011d3 800 }
sahilmgandhi 18:6a4db94011d3 801 #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \
sahilmgandhi 18:6a4db94011d3 802 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 803 } else {
sahilmgandhi 18:6a4db94011d3 804 ul_id -= 32;
sahilmgandhi 18:6a4db94011d3 805 if ((PMC->PMC_PCSR1 & (1u << ul_id))) {
sahilmgandhi 18:6a4db94011d3 806 return 1;
sahilmgandhi 18:6a4db94011d3 807 } else {
sahilmgandhi 18:6a4db94011d3 808 return 0;
sahilmgandhi 18:6a4db94011d3 809 }
sahilmgandhi 18:6a4db94011d3 810 }
sahilmgandhi 18:6a4db94011d3 811 #endif
sahilmgandhi 18:6a4db94011d3 812 }
sahilmgandhi 18:6a4db94011d3 813
sahilmgandhi 18:6a4db94011d3 814 /**
sahilmgandhi 18:6a4db94011d3 815 * \brief Set the prescaler for the specified programmable clock.
sahilmgandhi 18:6a4db94011d3 816 *
sahilmgandhi 18:6a4db94011d3 817 * \param ul_id Peripheral ID.
sahilmgandhi 18:6a4db94011d3 818 * \param ul_pres Prescaler value.
sahilmgandhi 18:6a4db94011d3 819 */
sahilmgandhi 18:6a4db94011d3 820 void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres)
sahilmgandhi 18:6a4db94011d3 821 {
sahilmgandhi 18:6a4db94011d3 822 PMC->PMC_PCK[ul_id] =
sahilmgandhi 18:6a4db94011d3 823 (PMC->PMC_PCK[ul_id] & ~PMC_PCK_PRES_Msk) | ul_pres;
sahilmgandhi 18:6a4db94011d3 824 while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id))
sahilmgandhi 18:6a4db94011d3 825 && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)));
sahilmgandhi 18:6a4db94011d3 826 }
sahilmgandhi 18:6a4db94011d3 827
sahilmgandhi 18:6a4db94011d3 828 /**
sahilmgandhi 18:6a4db94011d3 829 * \brief Set the source oscillator for the specified programmable clock.
sahilmgandhi 18:6a4db94011d3 830 *
sahilmgandhi 18:6a4db94011d3 831 * \param ul_id Peripheral ID.
sahilmgandhi 18:6a4db94011d3 832 * \param ul_source Source selection value.
sahilmgandhi 18:6a4db94011d3 833 */
sahilmgandhi 18:6a4db94011d3 834 void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source)
sahilmgandhi 18:6a4db94011d3 835 {
sahilmgandhi 18:6a4db94011d3 836 PMC->PMC_PCK[ul_id] =
sahilmgandhi 18:6a4db94011d3 837 (PMC->PMC_PCK[ul_id] & ~PMC_PCK_CSS_Msk) | ul_source;
sahilmgandhi 18:6a4db94011d3 838 while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id))
sahilmgandhi 18:6a4db94011d3 839 && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)));
sahilmgandhi 18:6a4db94011d3 840 }
sahilmgandhi 18:6a4db94011d3 841
sahilmgandhi 18:6a4db94011d3 842 /**
sahilmgandhi 18:6a4db94011d3 843 * \brief Switch programmable clock source selection to slow clock.
sahilmgandhi 18:6a4db94011d3 844 *
sahilmgandhi 18:6a4db94011d3 845 * \param ul_id Id of the programmable clock.
sahilmgandhi 18:6a4db94011d3 846 * \param ul_pres Programmable clock prescaler.
sahilmgandhi 18:6a4db94011d3 847 *
sahilmgandhi 18:6a4db94011d3 848 * \retval 0 Success.
sahilmgandhi 18:6a4db94011d3 849 * \retval 1 Timeout error.
sahilmgandhi 18:6a4db94011d3 850 */
sahilmgandhi 18:6a4db94011d3 851 uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres)
sahilmgandhi 18:6a4db94011d3 852 {
sahilmgandhi 18:6a4db94011d3 853 uint32_t ul_timeout;
sahilmgandhi 18:6a4db94011d3 854
sahilmgandhi 18:6a4db94011d3 855 PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_SLOW_CLK | ul_pres;
sahilmgandhi 18:6a4db94011d3 856 for (ul_timeout = PMC_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 857 !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
sahilmgandhi 18:6a4db94011d3 858 if (ul_timeout == 0) {
sahilmgandhi 18:6a4db94011d3 859 return 1;
sahilmgandhi 18:6a4db94011d3 860 }
sahilmgandhi 18:6a4db94011d3 861 }
sahilmgandhi 18:6a4db94011d3 862
sahilmgandhi 18:6a4db94011d3 863 return 0;
sahilmgandhi 18:6a4db94011d3 864 }
sahilmgandhi 18:6a4db94011d3 865
sahilmgandhi 18:6a4db94011d3 866 /**
sahilmgandhi 18:6a4db94011d3 867 * \brief Switch programmable clock source selection to main clock.
sahilmgandhi 18:6a4db94011d3 868 *
sahilmgandhi 18:6a4db94011d3 869 * \param ul_id Id of the programmable clock.
sahilmgandhi 18:6a4db94011d3 870 * \param ul_pres Programmable clock prescaler.
sahilmgandhi 18:6a4db94011d3 871 *
sahilmgandhi 18:6a4db94011d3 872 * \retval 0 Success.
sahilmgandhi 18:6a4db94011d3 873 * \retval 1 Timeout error.
sahilmgandhi 18:6a4db94011d3 874 */
sahilmgandhi 18:6a4db94011d3 875 uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres)
sahilmgandhi 18:6a4db94011d3 876 {
sahilmgandhi 18:6a4db94011d3 877 uint32_t ul_timeout;
sahilmgandhi 18:6a4db94011d3 878
sahilmgandhi 18:6a4db94011d3 879 PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MAIN_CLK | ul_pres;
sahilmgandhi 18:6a4db94011d3 880 for (ul_timeout = PMC_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 881 !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
sahilmgandhi 18:6a4db94011d3 882 if (ul_timeout == 0) {
sahilmgandhi 18:6a4db94011d3 883 return 1;
sahilmgandhi 18:6a4db94011d3 884 }
sahilmgandhi 18:6a4db94011d3 885 }
sahilmgandhi 18:6a4db94011d3 886
sahilmgandhi 18:6a4db94011d3 887 return 0;
sahilmgandhi 18:6a4db94011d3 888 }
sahilmgandhi 18:6a4db94011d3 889
sahilmgandhi 18:6a4db94011d3 890 /**
sahilmgandhi 18:6a4db94011d3 891 * \brief Switch programmable clock source selection to PLLA clock.
sahilmgandhi 18:6a4db94011d3 892 *
sahilmgandhi 18:6a4db94011d3 893 * \param ul_id Id of the programmable clock.
sahilmgandhi 18:6a4db94011d3 894 * \param ul_pres Programmable clock prescaler.
sahilmgandhi 18:6a4db94011d3 895 *
sahilmgandhi 18:6a4db94011d3 896 * \retval 0 Success.
sahilmgandhi 18:6a4db94011d3 897 * \retval 1 Timeout error.
sahilmgandhi 18:6a4db94011d3 898 */
sahilmgandhi 18:6a4db94011d3 899 uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres)
sahilmgandhi 18:6a4db94011d3 900 {
sahilmgandhi 18:6a4db94011d3 901 uint32_t ul_timeout;
sahilmgandhi 18:6a4db94011d3 902
sahilmgandhi 18:6a4db94011d3 903 PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLA_CLK | ul_pres;
sahilmgandhi 18:6a4db94011d3 904 for (ul_timeout = PMC_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 905 !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
sahilmgandhi 18:6a4db94011d3 906 if (ul_timeout == 0) {
sahilmgandhi 18:6a4db94011d3 907 return 1;
sahilmgandhi 18:6a4db94011d3 908 }
sahilmgandhi 18:6a4db94011d3 909 }
sahilmgandhi 18:6a4db94011d3 910
sahilmgandhi 18:6a4db94011d3 911 return 0;
sahilmgandhi 18:6a4db94011d3 912 }
sahilmgandhi 18:6a4db94011d3 913
sahilmgandhi 18:6a4db94011d3 914 #if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)
sahilmgandhi 18:6a4db94011d3 915 /**
sahilmgandhi 18:6a4db94011d3 916 * \brief Switch programmable clock source selection to PLLB clock.
sahilmgandhi 18:6a4db94011d3 917 *
sahilmgandhi 18:6a4db94011d3 918 * \param ul_id Id of the programmable clock.
sahilmgandhi 18:6a4db94011d3 919 * \param ul_pres Programmable clock prescaler.
sahilmgandhi 18:6a4db94011d3 920 *
sahilmgandhi 18:6a4db94011d3 921 * \retval 0 Success.
sahilmgandhi 18:6a4db94011d3 922 * \retval 1 Timeout error.
sahilmgandhi 18:6a4db94011d3 923 */
sahilmgandhi 18:6a4db94011d3 924 uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres)
sahilmgandhi 18:6a4db94011d3 925 {
sahilmgandhi 18:6a4db94011d3 926 uint32_t ul_timeout;
sahilmgandhi 18:6a4db94011d3 927
sahilmgandhi 18:6a4db94011d3 928 PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLB_CLK | ul_pres;
sahilmgandhi 18:6a4db94011d3 929 for (ul_timeout = PMC_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 930 !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));
sahilmgandhi 18:6a4db94011d3 931 --ul_timeout) {
sahilmgandhi 18:6a4db94011d3 932 if (ul_timeout == 0) {
sahilmgandhi 18:6a4db94011d3 933 return 1;
sahilmgandhi 18:6a4db94011d3 934 }
sahilmgandhi 18:6a4db94011d3 935 }
sahilmgandhi 18:6a4db94011d3 936
sahilmgandhi 18:6a4db94011d3 937 return 0;
sahilmgandhi 18:6a4db94011d3 938 }
sahilmgandhi 18:6a4db94011d3 939 #endif
sahilmgandhi 18:6a4db94011d3 940
sahilmgandhi 18:6a4db94011d3 941 #if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 942 /**
sahilmgandhi 18:6a4db94011d3 943 * \brief Switch programmable clock source selection to UPLL clock.
sahilmgandhi 18:6a4db94011d3 944 *
sahilmgandhi 18:6a4db94011d3 945 * \param ul_id Id of the programmable clock.
sahilmgandhi 18:6a4db94011d3 946 * \param ul_pres Programmable clock prescaler.
sahilmgandhi 18:6a4db94011d3 947 *
sahilmgandhi 18:6a4db94011d3 948 * \retval 0 Success.
sahilmgandhi 18:6a4db94011d3 949 * \retval 1 Timeout error.
sahilmgandhi 18:6a4db94011d3 950 */
sahilmgandhi 18:6a4db94011d3 951 uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres)
sahilmgandhi 18:6a4db94011d3 952 {
sahilmgandhi 18:6a4db94011d3 953 uint32_t ul_timeout;
sahilmgandhi 18:6a4db94011d3 954
sahilmgandhi 18:6a4db94011d3 955 PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_UPLL_CLK | ul_pres;
sahilmgandhi 18:6a4db94011d3 956 for (ul_timeout = PMC_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 957 !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));
sahilmgandhi 18:6a4db94011d3 958 --ul_timeout) {
sahilmgandhi 18:6a4db94011d3 959 if (ul_timeout == 0) {
sahilmgandhi 18:6a4db94011d3 960 return 1;
sahilmgandhi 18:6a4db94011d3 961 }
sahilmgandhi 18:6a4db94011d3 962 }
sahilmgandhi 18:6a4db94011d3 963
sahilmgandhi 18:6a4db94011d3 964 return 0;
sahilmgandhi 18:6a4db94011d3 965 }
sahilmgandhi 18:6a4db94011d3 966 #endif
sahilmgandhi 18:6a4db94011d3 967
sahilmgandhi 18:6a4db94011d3 968 /**
sahilmgandhi 18:6a4db94011d3 969 * \brief Switch programmable clock source selection to mck.
sahilmgandhi 18:6a4db94011d3 970 *
sahilmgandhi 18:6a4db94011d3 971 * \param ul_id Id of the programmable clock.
sahilmgandhi 18:6a4db94011d3 972 * \param ul_pres Programmable clock prescaler.
sahilmgandhi 18:6a4db94011d3 973 *
sahilmgandhi 18:6a4db94011d3 974 * \retval 0 Success.
sahilmgandhi 18:6a4db94011d3 975 * \retval 1 Timeout error.
sahilmgandhi 18:6a4db94011d3 976 */
sahilmgandhi 18:6a4db94011d3 977 uint32_t pmc_switch_pck_to_mck(uint32_t ul_id, uint32_t ul_pres)
sahilmgandhi 18:6a4db94011d3 978 {
sahilmgandhi 18:6a4db94011d3 979 uint32_t ul_timeout;
sahilmgandhi 18:6a4db94011d3 980
sahilmgandhi 18:6a4db94011d3 981 PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MCK | ul_pres;
sahilmgandhi 18:6a4db94011d3 982 for (ul_timeout = PMC_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 983 !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
sahilmgandhi 18:6a4db94011d3 984 if (ul_timeout == 0) {
sahilmgandhi 18:6a4db94011d3 985 return 1;
sahilmgandhi 18:6a4db94011d3 986 }
sahilmgandhi 18:6a4db94011d3 987 }
sahilmgandhi 18:6a4db94011d3 988
sahilmgandhi 18:6a4db94011d3 989 return 0;
sahilmgandhi 18:6a4db94011d3 990 }
sahilmgandhi 18:6a4db94011d3 991
sahilmgandhi 18:6a4db94011d3 992 /**
sahilmgandhi 18:6a4db94011d3 993 * \brief Enable the specified programmable clock.
sahilmgandhi 18:6a4db94011d3 994 *
sahilmgandhi 18:6a4db94011d3 995 * \param ul_id Id of the programmable clock.
sahilmgandhi 18:6a4db94011d3 996 */
sahilmgandhi 18:6a4db94011d3 997 void pmc_enable_pck(uint32_t ul_id)
sahilmgandhi 18:6a4db94011d3 998 {
sahilmgandhi 18:6a4db94011d3 999 PMC->PMC_SCER = PMC_SCER_PCK0 << ul_id;
sahilmgandhi 18:6a4db94011d3 1000 }
sahilmgandhi 18:6a4db94011d3 1001
sahilmgandhi 18:6a4db94011d3 1002 /**
sahilmgandhi 18:6a4db94011d3 1003 * \brief Disable the specified programmable clock.
sahilmgandhi 18:6a4db94011d3 1004 *
sahilmgandhi 18:6a4db94011d3 1005 * \param ul_id Id of the programmable clock.
sahilmgandhi 18:6a4db94011d3 1006 */
sahilmgandhi 18:6a4db94011d3 1007 void pmc_disable_pck(uint32_t ul_id)
sahilmgandhi 18:6a4db94011d3 1008 {
sahilmgandhi 18:6a4db94011d3 1009 PMC->PMC_SCDR = PMC_SCER_PCK0 << ul_id;
sahilmgandhi 18:6a4db94011d3 1010 }
sahilmgandhi 18:6a4db94011d3 1011
sahilmgandhi 18:6a4db94011d3 1012 /**
sahilmgandhi 18:6a4db94011d3 1013 * \brief Enable all programmable clocks.
sahilmgandhi 18:6a4db94011d3 1014 */
sahilmgandhi 18:6a4db94011d3 1015 void pmc_enable_all_pck(void)
sahilmgandhi 18:6a4db94011d3 1016 {
sahilmgandhi 18:6a4db94011d3 1017 PMC->PMC_SCER = PMC_SCER_PCK0 | PMC_SCER_PCK1 | PMC_SCER_PCK2;
sahilmgandhi 18:6a4db94011d3 1018 }
sahilmgandhi 18:6a4db94011d3 1019
sahilmgandhi 18:6a4db94011d3 1020 /**
sahilmgandhi 18:6a4db94011d3 1021 * \brief Disable all programmable clocks.
sahilmgandhi 18:6a4db94011d3 1022 */
sahilmgandhi 18:6a4db94011d3 1023 void pmc_disable_all_pck(void)
sahilmgandhi 18:6a4db94011d3 1024 {
sahilmgandhi 18:6a4db94011d3 1025 PMC->PMC_SCDR = PMC_SCDR_PCK0 | PMC_SCDR_PCK1 | PMC_SCDR_PCK2;
sahilmgandhi 18:6a4db94011d3 1026 }
sahilmgandhi 18:6a4db94011d3 1027
sahilmgandhi 18:6a4db94011d3 1028 /**
sahilmgandhi 18:6a4db94011d3 1029 * \brief Check if the specified programmable clock is enabled.
sahilmgandhi 18:6a4db94011d3 1030 *
sahilmgandhi 18:6a4db94011d3 1031 * \param ul_id Id of the programmable clock.
sahilmgandhi 18:6a4db94011d3 1032 *
sahilmgandhi 18:6a4db94011d3 1033 * \retval 0 Programmable clock is disabled or unknown.
sahilmgandhi 18:6a4db94011d3 1034 * \retval 1 Programmable clock is enabled.
sahilmgandhi 18:6a4db94011d3 1035 */
sahilmgandhi 18:6a4db94011d3 1036 uint32_t pmc_is_pck_enabled(uint32_t ul_id)
sahilmgandhi 18:6a4db94011d3 1037 {
sahilmgandhi 18:6a4db94011d3 1038 if (ul_id > 2) {
sahilmgandhi 18:6a4db94011d3 1039 return 0;
sahilmgandhi 18:6a4db94011d3 1040 }
sahilmgandhi 18:6a4db94011d3 1041
sahilmgandhi 18:6a4db94011d3 1042 return (PMC->PMC_SCSR & (PMC_SCSR_PCK0 << ul_id));
sahilmgandhi 18:6a4db94011d3 1043 }
sahilmgandhi 18:6a4db94011d3 1044
sahilmgandhi 18:6a4db94011d3 1045 #if (SAM4C || SAM4CM || SAM4CP)
sahilmgandhi 18:6a4db94011d3 1046 /**
sahilmgandhi 18:6a4db94011d3 1047 * \brief Enable Coprocessor Clocks.
sahilmgandhi 18:6a4db94011d3 1048 */
sahilmgandhi 18:6a4db94011d3 1049 void pmc_enable_cpck(void)
sahilmgandhi 18:6a4db94011d3 1050 {
sahilmgandhi 18:6a4db94011d3 1051 PMC->PMC_SCER = PMC_SCER_CPCK | PMC_SCER_CPKEY_PASSWD;
sahilmgandhi 18:6a4db94011d3 1052 }
sahilmgandhi 18:6a4db94011d3 1053
sahilmgandhi 18:6a4db94011d3 1054 /**
sahilmgandhi 18:6a4db94011d3 1055 * \brief Disable Coprocessor Clocks.
sahilmgandhi 18:6a4db94011d3 1056 */
sahilmgandhi 18:6a4db94011d3 1057 void pmc_disable_cpck(void)
sahilmgandhi 18:6a4db94011d3 1058 {
sahilmgandhi 18:6a4db94011d3 1059 PMC->PMC_SCDR = PMC_SCDR_CPCK | PMC_SCDR_CPKEY_PASSWD;
sahilmgandhi 18:6a4db94011d3 1060 }
sahilmgandhi 18:6a4db94011d3 1061
sahilmgandhi 18:6a4db94011d3 1062 /**
sahilmgandhi 18:6a4db94011d3 1063 * \brief Check if the Coprocessor Clocks is enabled.
sahilmgandhi 18:6a4db94011d3 1064 *
sahilmgandhi 18:6a4db94011d3 1065 * \retval 0 Coprocessor Clocks is disabled.
sahilmgandhi 18:6a4db94011d3 1066 * \retval 1 Coprocessor Clocks is enabled.
sahilmgandhi 18:6a4db94011d3 1067 */
sahilmgandhi 18:6a4db94011d3 1068 bool pmc_is_cpck_enabled(void)
sahilmgandhi 18:6a4db94011d3 1069 {
sahilmgandhi 18:6a4db94011d3 1070 if(PMC->PMC_SCSR & PMC_SCSR_CPCK) {
sahilmgandhi 18:6a4db94011d3 1071 return 1;
sahilmgandhi 18:6a4db94011d3 1072 } else {
sahilmgandhi 18:6a4db94011d3 1073 return 0;
sahilmgandhi 18:6a4db94011d3 1074 }
sahilmgandhi 18:6a4db94011d3 1075 }
sahilmgandhi 18:6a4db94011d3 1076
sahilmgandhi 18:6a4db94011d3 1077 /**
sahilmgandhi 18:6a4db94011d3 1078 * \brief Enable Coprocessor Bus Master Clocks.
sahilmgandhi 18:6a4db94011d3 1079 */
sahilmgandhi 18:6a4db94011d3 1080 void pmc_enable_cpbmck(void)
sahilmgandhi 18:6a4db94011d3 1081 {
sahilmgandhi 18:6a4db94011d3 1082 PMC->PMC_SCER = PMC_SCER_CPCK | PMC_SCER_CPKEY_PASSWD;
sahilmgandhi 18:6a4db94011d3 1083 }
sahilmgandhi 18:6a4db94011d3 1084
sahilmgandhi 18:6a4db94011d3 1085 /**
sahilmgandhi 18:6a4db94011d3 1086 * \brief Disable Coprocessor Bus Master Clocks.
sahilmgandhi 18:6a4db94011d3 1087 */
sahilmgandhi 18:6a4db94011d3 1088 void pmc_disable_cpbmck(void)
sahilmgandhi 18:6a4db94011d3 1089 {
sahilmgandhi 18:6a4db94011d3 1090 PMC->PMC_SCDR = PMC_SCDR_CPCK | PMC_SCDR_CPKEY_PASSWD;
sahilmgandhi 18:6a4db94011d3 1091 }
sahilmgandhi 18:6a4db94011d3 1092
sahilmgandhi 18:6a4db94011d3 1093 /**
sahilmgandhi 18:6a4db94011d3 1094 * \brief Check if the Coprocessor Bus Master Clocks is enabled.
sahilmgandhi 18:6a4db94011d3 1095 *
sahilmgandhi 18:6a4db94011d3 1096 * \retval 0 Coprocessor Bus Master Clocks is disabled.
sahilmgandhi 18:6a4db94011d3 1097 * \retval 1 Coprocessor Bus Master Clocks is enabled.
sahilmgandhi 18:6a4db94011d3 1098 */
sahilmgandhi 18:6a4db94011d3 1099 bool pmc_is_cpbmck_enabled(void)
sahilmgandhi 18:6a4db94011d3 1100 {
sahilmgandhi 18:6a4db94011d3 1101 if(PMC->PMC_SCSR & PMC_SCSR_CPBMCK) {
sahilmgandhi 18:6a4db94011d3 1102 return 1;
sahilmgandhi 18:6a4db94011d3 1103 } else {
sahilmgandhi 18:6a4db94011d3 1104 return 0;
sahilmgandhi 18:6a4db94011d3 1105 }
sahilmgandhi 18:6a4db94011d3 1106 }
sahilmgandhi 18:6a4db94011d3 1107
sahilmgandhi 18:6a4db94011d3 1108 /**
sahilmgandhi 18:6a4db94011d3 1109 * \brief Set the prescaler for the Coprocessor Master Clock.
sahilmgandhi 18:6a4db94011d3 1110 *
sahilmgandhi 18:6a4db94011d3 1111 * \param ul_pres Prescaler value.
sahilmgandhi 18:6a4db94011d3 1112 */
sahilmgandhi 18:6a4db94011d3 1113 void pmc_cpck_set_prescaler(uint32_t ul_pres)
sahilmgandhi 18:6a4db94011d3 1114 {
sahilmgandhi 18:6a4db94011d3 1115 PMC->PMC_MCKR =
sahilmgandhi 18:6a4db94011d3 1116 (PMC->PMC_MCKR & (~PMC_MCKR_CPPRES_Msk)) | PMC_MCKR_CPPRES(ul_pres);
sahilmgandhi 18:6a4db94011d3 1117 }
sahilmgandhi 18:6a4db94011d3 1118
sahilmgandhi 18:6a4db94011d3 1119 /**
sahilmgandhi 18:6a4db94011d3 1120 * \brief Set the source for the Coprocessor Master Clock.
sahilmgandhi 18:6a4db94011d3 1121 *
sahilmgandhi 18:6a4db94011d3 1122 * \param ul_source Source selection value.
sahilmgandhi 18:6a4db94011d3 1123 */
sahilmgandhi 18:6a4db94011d3 1124 void pmc_cpck_set_source(uint32_t ul_source)
sahilmgandhi 18:6a4db94011d3 1125 {
sahilmgandhi 18:6a4db94011d3 1126 PMC->PMC_MCKR =
sahilmgandhi 18:6a4db94011d3 1127 (PMC->PMC_MCKR & (~PMC_MCKR_CPCSS_Msk)) | ul_source;
sahilmgandhi 18:6a4db94011d3 1128 }
sahilmgandhi 18:6a4db94011d3 1129 #endif
sahilmgandhi 18:6a4db94011d3 1130
sahilmgandhi 18:6a4db94011d3 1131 #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 1132 /**
sahilmgandhi 18:6a4db94011d3 1133 * \brief Switch UDP (USB) clock source selection to PLLA clock.
sahilmgandhi 18:6a4db94011d3 1134 *
sahilmgandhi 18:6a4db94011d3 1135 * \param ul_usbdiv Clock divisor.
sahilmgandhi 18:6a4db94011d3 1136 */
sahilmgandhi 18:6a4db94011d3 1137 void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv)
sahilmgandhi 18:6a4db94011d3 1138 {
sahilmgandhi 18:6a4db94011d3 1139 PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv);
sahilmgandhi 18:6a4db94011d3 1140 }
sahilmgandhi 18:6a4db94011d3 1141 #endif
sahilmgandhi 18:6a4db94011d3 1142
sahilmgandhi 18:6a4db94011d3 1143 #if (SAM3S || SAM4S || SAMG55)
sahilmgandhi 18:6a4db94011d3 1144 /**
sahilmgandhi 18:6a4db94011d3 1145 * \brief Switch UDP (USB) clock source selection to PLLB clock.
sahilmgandhi 18:6a4db94011d3 1146 *
sahilmgandhi 18:6a4db94011d3 1147 * \param ul_usbdiv Clock divisor.
sahilmgandhi 18:6a4db94011d3 1148 */
sahilmgandhi 18:6a4db94011d3 1149 void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv)
sahilmgandhi 18:6a4db94011d3 1150 {
sahilmgandhi 18:6a4db94011d3 1151 PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS;
sahilmgandhi 18:6a4db94011d3 1152 }
sahilmgandhi 18:6a4db94011d3 1153 #endif
sahilmgandhi 18:6a4db94011d3 1154
sahilmgandhi 18:6a4db94011d3 1155 #if (SAM3XA || SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 1156 /**
sahilmgandhi 18:6a4db94011d3 1157 * \brief Switch UDP (USB) clock source selection to UPLL clock.
sahilmgandhi 18:6a4db94011d3 1158 *
sahilmgandhi 18:6a4db94011d3 1159 * \param ul_usbdiv Clock divisor.
sahilmgandhi 18:6a4db94011d3 1160 */
sahilmgandhi 18:6a4db94011d3 1161 void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv)
sahilmgandhi 18:6a4db94011d3 1162 {
sahilmgandhi 18:6a4db94011d3 1163 PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(ul_usbdiv);
sahilmgandhi 18:6a4db94011d3 1164 }
sahilmgandhi 18:6a4db94011d3 1165 #endif
sahilmgandhi 18:6a4db94011d3 1166
sahilmgandhi 18:6a4db94011d3 1167 #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 1168 /**
sahilmgandhi 18:6a4db94011d3 1169 * \brief Enable UDP (USB) clock.
sahilmgandhi 18:6a4db94011d3 1170 */
sahilmgandhi 18:6a4db94011d3 1171 void pmc_enable_udpck(void)
sahilmgandhi 18:6a4db94011d3 1172 {
sahilmgandhi 18:6a4db94011d3 1173 #if (SAM3S || SAM4S || SAM4E || SAMG55)
sahilmgandhi 18:6a4db94011d3 1174 PMC->PMC_SCER = PMC_SCER_UDP;
sahilmgandhi 18:6a4db94011d3 1175 #elif (SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 1176 PMC->PMC_SCER = PMC_SCER_USBCLK;
sahilmgandhi 18:6a4db94011d3 1177 #else
sahilmgandhi 18:6a4db94011d3 1178 PMC->PMC_SCER = PMC_SCER_UOTGCLK;
sahilmgandhi 18:6a4db94011d3 1179 # endif
sahilmgandhi 18:6a4db94011d3 1180 }
sahilmgandhi 18:6a4db94011d3 1181
sahilmgandhi 18:6a4db94011d3 1182 /**
sahilmgandhi 18:6a4db94011d3 1183 * \brief Disable UDP (USB) clock.
sahilmgandhi 18:6a4db94011d3 1184 */
sahilmgandhi 18:6a4db94011d3 1185 void pmc_disable_udpck(void)
sahilmgandhi 18:6a4db94011d3 1186 {
sahilmgandhi 18:6a4db94011d3 1187 #if (SAM3S || SAM4S || SAM4E || SAMG55)
sahilmgandhi 18:6a4db94011d3 1188 PMC->PMC_SCDR = PMC_SCDR_UDP;
sahilmgandhi 18:6a4db94011d3 1189 #elif (SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 1190 PMC->PMC_SCDR = PMC_SCDR_USBCLK;
sahilmgandhi 18:6a4db94011d3 1191 #else
sahilmgandhi 18:6a4db94011d3 1192 PMC->PMC_SCDR = PMC_SCDR_UOTGCLK;
sahilmgandhi 18:6a4db94011d3 1193 # endif
sahilmgandhi 18:6a4db94011d3 1194 }
sahilmgandhi 18:6a4db94011d3 1195 #endif
sahilmgandhi 18:6a4db94011d3 1196
sahilmgandhi 18:6a4db94011d3 1197 #if SAMG55
sahilmgandhi 18:6a4db94011d3 1198 /**
sahilmgandhi 18:6a4db94011d3 1199 * \brief Switch UHP (USB) clock source selection to PLLA clock.
sahilmgandhi 18:6a4db94011d3 1200 *
sahilmgandhi 18:6a4db94011d3 1201 * \param ul_usbdiv Clock divisor.
sahilmgandhi 18:6a4db94011d3 1202 */
sahilmgandhi 18:6a4db94011d3 1203 void pmc_switch_uhpck_to_pllack(uint32_t ul_usbdiv)
sahilmgandhi 18:6a4db94011d3 1204 {
sahilmgandhi 18:6a4db94011d3 1205 PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv);
sahilmgandhi 18:6a4db94011d3 1206 }
sahilmgandhi 18:6a4db94011d3 1207
sahilmgandhi 18:6a4db94011d3 1208 /**
sahilmgandhi 18:6a4db94011d3 1209 * \brief Switch UHP (USB) clock source selection to PLLB clock.
sahilmgandhi 18:6a4db94011d3 1210 *
sahilmgandhi 18:6a4db94011d3 1211 * \param ul_usbdiv Clock divisor.
sahilmgandhi 18:6a4db94011d3 1212 */
sahilmgandhi 18:6a4db94011d3 1213 void pmc_switch_uhpck_to_pllbck(uint32_t ul_usbdiv)
sahilmgandhi 18:6a4db94011d3 1214 {
sahilmgandhi 18:6a4db94011d3 1215 PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS;
sahilmgandhi 18:6a4db94011d3 1216 }
sahilmgandhi 18:6a4db94011d3 1217
sahilmgandhi 18:6a4db94011d3 1218 /**
sahilmgandhi 18:6a4db94011d3 1219 * \brief Enable UHP (USB) clock.
sahilmgandhi 18:6a4db94011d3 1220 */
sahilmgandhi 18:6a4db94011d3 1221 void pmc_enable_uhpck(void)
sahilmgandhi 18:6a4db94011d3 1222 {
sahilmgandhi 18:6a4db94011d3 1223 PMC->PMC_SCER = PMC_SCER_UHP;
sahilmgandhi 18:6a4db94011d3 1224 }
sahilmgandhi 18:6a4db94011d3 1225 #endif
sahilmgandhi 18:6a4db94011d3 1226
sahilmgandhi 18:6a4db94011d3 1227 /**
sahilmgandhi 18:6a4db94011d3 1228 * \brief Enable PMC interrupts.
sahilmgandhi 18:6a4db94011d3 1229 *
sahilmgandhi 18:6a4db94011d3 1230 * \param ul_sources Interrupt sources bit map.
sahilmgandhi 18:6a4db94011d3 1231 */
sahilmgandhi 18:6a4db94011d3 1232 void pmc_enable_interrupt(uint32_t ul_sources)
sahilmgandhi 18:6a4db94011d3 1233 {
sahilmgandhi 18:6a4db94011d3 1234 PMC->PMC_IER = ul_sources;
sahilmgandhi 18:6a4db94011d3 1235 }
sahilmgandhi 18:6a4db94011d3 1236
sahilmgandhi 18:6a4db94011d3 1237 /**
sahilmgandhi 18:6a4db94011d3 1238 * \brief Disable PMC interrupts.
sahilmgandhi 18:6a4db94011d3 1239 *
sahilmgandhi 18:6a4db94011d3 1240 * \param ul_sources Interrupt sources bit map.
sahilmgandhi 18:6a4db94011d3 1241 */
sahilmgandhi 18:6a4db94011d3 1242 void pmc_disable_interrupt(uint32_t ul_sources)
sahilmgandhi 18:6a4db94011d3 1243 {
sahilmgandhi 18:6a4db94011d3 1244 PMC->PMC_IDR = ul_sources;
sahilmgandhi 18:6a4db94011d3 1245 }
sahilmgandhi 18:6a4db94011d3 1246
sahilmgandhi 18:6a4db94011d3 1247 /**
sahilmgandhi 18:6a4db94011d3 1248 * \brief Get PMC interrupt mask.
sahilmgandhi 18:6a4db94011d3 1249 *
sahilmgandhi 18:6a4db94011d3 1250 * \return The interrupt mask value.
sahilmgandhi 18:6a4db94011d3 1251 */
sahilmgandhi 18:6a4db94011d3 1252 uint32_t pmc_get_interrupt_mask(void)
sahilmgandhi 18:6a4db94011d3 1253 {
sahilmgandhi 18:6a4db94011d3 1254 return PMC->PMC_IMR;
sahilmgandhi 18:6a4db94011d3 1255 }
sahilmgandhi 18:6a4db94011d3 1256
sahilmgandhi 18:6a4db94011d3 1257 /**
sahilmgandhi 18:6a4db94011d3 1258 * \brief Get current status.
sahilmgandhi 18:6a4db94011d3 1259 *
sahilmgandhi 18:6a4db94011d3 1260 * \return The current PMC status.
sahilmgandhi 18:6a4db94011d3 1261 */
sahilmgandhi 18:6a4db94011d3 1262 uint32_t pmc_get_status(void)
sahilmgandhi 18:6a4db94011d3 1263 {
sahilmgandhi 18:6a4db94011d3 1264 return PMC->PMC_SR;
sahilmgandhi 18:6a4db94011d3 1265 }
sahilmgandhi 18:6a4db94011d3 1266
sahilmgandhi 18:6a4db94011d3 1267 /**
sahilmgandhi 18:6a4db94011d3 1268 * \brief Set the wake-up inputs for fast startup mode registers
sahilmgandhi 18:6a4db94011d3 1269 * (event generation).
sahilmgandhi 18:6a4db94011d3 1270 *
sahilmgandhi 18:6a4db94011d3 1271 * \param ul_inputs Wake up inputs to enable.
sahilmgandhi 18:6a4db94011d3 1272 */
sahilmgandhi 18:6a4db94011d3 1273 void pmc_set_fast_startup_input(uint32_t ul_inputs)
sahilmgandhi 18:6a4db94011d3 1274 {
sahilmgandhi 18:6a4db94011d3 1275 ul_inputs &= PMC_FAST_STARTUP_Msk;
sahilmgandhi 18:6a4db94011d3 1276 PMC->PMC_FSMR |= ul_inputs;
sahilmgandhi 18:6a4db94011d3 1277 }
sahilmgandhi 18:6a4db94011d3 1278
sahilmgandhi 18:6a4db94011d3 1279 /**
sahilmgandhi 18:6a4db94011d3 1280 * \brief Clear the wake-up inputs for fast startup mode registers
sahilmgandhi 18:6a4db94011d3 1281 * (remove event generation).
sahilmgandhi 18:6a4db94011d3 1282 *
sahilmgandhi 18:6a4db94011d3 1283 * \param ul_inputs Wake up inputs to disable.
sahilmgandhi 18:6a4db94011d3 1284 */
sahilmgandhi 18:6a4db94011d3 1285 void pmc_clr_fast_startup_input(uint32_t ul_inputs)
sahilmgandhi 18:6a4db94011d3 1286 {
sahilmgandhi 18:6a4db94011d3 1287 ul_inputs &= PMC_FAST_STARTUP_Msk;
sahilmgandhi 18:6a4db94011d3 1288 PMC->PMC_FSMR &= ~ul_inputs;
sahilmgandhi 18:6a4db94011d3 1289 }
sahilmgandhi 18:6a4db94011d3 1290
sahilmgandhi 18:6a4db94011d3 1291 #if (SAM4C || SAM4CM || SAM4CP)
sahilmgandhi 18:6a4db94011d3 1292 /**
sahilmgandhi 18:6a4db94011d3 1293 * \brief Set the wake-up inputs of coprocessor for fast startup mode registers
sahilmgandhi 18:6a4db94011d3 1294 * (event generation).
sahilmgandhi 18:6a4db94011d3 1295 *
sahilmgandhi 18:6a4db94011d3 1296 * \param ul_inputs Wake up inputs to enable.
sahilmgandhi 18:6a4db94011d3 1297 */
sahilmgandhi 18:6a4db94011d3 1298 void pmc_cp_set_fast_startup_input(uint32_t ul_inputs)
sahilmgandhi 18:6a4db94011d3 1299 {
sahilmgandhi 18:6a4db94011d3 1300 ul_inputs &= PMC_FAST_STARTUP_Msk;
sahilmgandhi 18:6a4db94011d3 1301 PMC->PMC_CPFSMR |= ul_inputs;
sahilmgandhi 18:6a4db94011d3 1302 }
sahilmgandhi 18:6a4db94011d3 1303
sahilmgandhi 18:6a4db94011d3 1304 /**
sahilmgandhi 18:6a4db94011d3 1305 * \brief Clear the wake-up inputs of coprocessor for fast startup mode registers
sahilmgandhi 18:6a4db94011d3 1306 * (remove event generation).
sahilmgandhi 18:6a4db94011d3 1307 *
sahilmgandhi 18:6a4db94011d3 1308 * \param ul_inputs Wake up inputs to disable.
sahilmgandhi 18:6a4db94011d3 1309 */
sahilmgandhi 18:6a4db94011d3 1310 void pmc_cp_clr_fast_startup_input(uint32_t ul_inputs)
sahilmgandhi 18:6a4db94011d3 1311 {
sahilmgandhi 18:6a4db94011d3 1312 ul_inputs &= PMC_FAST_STARTUP_Msk;
sahilmgandhi 18:6a4db94011d3 1313 PMC->PMC_CPFSMR &= ~ul_inputs;
sahilmgandhi 18:6a4db94011d3 1314 }
sahilmgandhi 18:6a4db94011d3 1315 #endif
sahilmgandhi 18:6a4db94011d3 1316
sahilmgandhi 18:6a4db94011d3 1317 #if (!(SAMG51 || SAMG53 || SAMG54))
sahilmgandhi 18:6a4db94011d3 1318 /**
sahilmgandhi 18:6a4db94011d3 1319 * \brief Enable Sleep Mode.
sahilmgandhi 18:6a4db94011d3 1320 * Enter condition: (WFE or WFI) + (SLEEPDEEP bit = 0) + (LPM bit = 0)
sahilmgandhi 18:6a4db94011d3 1321 *
sahilmgandhi 18:6a4db94011d3 1322 * \param uc_type 0 for wait for interrupt, 1 for wait for event.
sahilmgandhi 18:6a4db94011d3 1323 * \note For SAM4S, SAM4C, SAM4CM, SAM4CP, SAMV71 and SAM4E series,
sahilmgandhi 18:6a4db94011d3 1324 * since only WFI is effective, uc_type = 1 will be treated as uc_type = 0.
sahilmgandhi 18:6a4db94011d3 1325 */
sahilmgandhi 18:6a4db94011d3 1326 void pmc_enable_sleepmode(uint8_t uc_type)
sahilmgandhi 18:6a4db94011d3 1327 {
sahilmgandhi 18:6a4db94011d3 1328 #if !(SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 1329 PMC->PMC_FSMR &= (uint32_t) ~ PMC_FSMR_LPM; // Enter Sleep mode
sahilmgandhi 18:6a4db94011d3 1330 #endif
sahilmgandhi 18:6a4db94011d3 1331 SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; // Deep sleep
sahilmgandhi 18:6a4db94011d3 1332
sahilmgandhi 18:6a4db94011d3 1333 #if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 1334 UNUSED(uc_type);
sahilmgandhi 18:6a4db94011d3 1335 __WFI();
sahilmgandhi 18:6a4db94011d3 1336 #else
sahilmgandhi 18:6a4db94011d3 1337 if (uc_type == 0) {
sahilmgandhi 18:6a4db94011d3 1338 __WFI();
sahilmgandhi 18:6a4db94011d3 1339 } else {
sahilmgandhi 18:6a4db94011d3 1340 __WFE();
sahilmgandhi 18:6a4db94011d3 1341 }
sahilmgandhi 18:6a4db94011d3 1342 #endif
sahilmgandhi 18:6a4db94011d3 1343 }
sahilmgandhi 18:6a4db94011d3 1344 #endif
sahilmgandhi 18:6a4db94011d3 1345
sahilmgandhi 18:6a4db94011d3 1346 #if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 1347 static uint32_t ul_flash_in_wait_mode = PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN;
sahilmgandhi 18:6a4db94011d3 1348 /**
sahilmgandhi 18:6a4db94011d3 1349 * \brief Set the embedded flash state in wait mode
sahilmgandhi 18:6a4db94011d3 1350 *
sahilmgandhi 18:6a4db94011d3 1351 * \param ul_flash_state PMC_WAIT_MODE_FLASH_STANDBY flash in standby mode,
sahilmgandhi 18:6a4db94011d3 1352 * PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN flash in deep power down mode.
sahilmgandhi 18:6a4db94011d3 1353 */
sahilmgandhi 18:6a4db94011d3 1354 void pmc_set_flash_in_wait_mode(uint32_t ul_flash_state)
sahilmgandhi 18:6a4db94011d3 1355 {
sahilmgandhi 18:6a4db94011d3 1356 ul_flash_in_wait_mode = ul_flash_state;
sahilmgandhi 18:6a4db94011d3 1357 }
sahilmgandhi 18:6a4db94011d3 1358
sahilmgandhi 18:6a4db94011d3 1359 /**
sahilmgandhi 18:6a4db94011d3 1360 * \brief Enable Wait Mode. Enter condition: (WAITMODE bit = 1) + FLPM
sahilmgandhi 18:6a4db94011d3 1361 *
sahilmgandhi 18:6a4db94011d3 1362 * \note In this function, FLPM will retain, WAITMODE bit will be set,
sahilmgandhi 18:6a4db94011d3 1363 * Generally, this function will be called by pmc_sleep() in order to
sahilmgandhi 18:6a4db94011d3 1364 * complete all sequence entering wait mode.
sahilmgandhi 18:6a4db94011d3 1365 * See \ref pmc_sleep() for entering different sleep modes.
sahilmgandhi 18:6a4db94011d3 1366 */
sahilmgandhi 18:6a4db94011d3 1367 void pmc_enable_waitmode(void)
sahilmgandhi 18:6a4db94011d3 1368 {
sahilmgandhi 18:6a4db94011d3 1369 uint32_t i;
sahilmgandhi 18:6a4db94011d3 1370
sahilmgandhi 18:6a4db94011d3 1371 /* Flash in wait mode */
sahilmgandhi 18:6a4db94011d3 1372 i = PMC->PMC_FSMR;
sahilmgandhi 18:6a4db94011d3 1373 i &= ~PMC_FSMR_FLPM_Msk;
sahilmgandhi 18:6a4db94011d3 1374 i |= ul_flash_in_wait_mode;
sahilmgandhi 18:6a4db94011d3 1375 PMC->PMC_FSMR = i;
sahilmgandhi 18:6a4db94011d3 1376
sahilmgandhi 18:6a4db94011d3 1377 /* Set the WAITMODE bit = 1 */
sahilmgandhi 18:6a4db94011d3 1378 PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_WAITMODE;
sahilmgandhi 18:6a4db94011d3 1379
sahilmgandhi 18:6a4db94011d3 1380 /* Waiting for Master Clock Ready MCKRDY = 1 */
sahilmgandhi 18:6a4db94011d3 1381 while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
sahilmgandhi 18:6a4db94011d3 1382
sahilmgandhi 18:6a4db94011d3 1383 /* Waiting for MOSCRCEN bit cleared is strongly recommended
sahilmgandhi 18:6a4db94011d3 1384 * to ensure that the core will not execute undesired instructions
sahilmgandhi 18:6a4db94011d3 1385 */
sahilmgandhi 18:6a4db94011d3 1386 for (i = 0; i < 500; i++) {
sahilmgandhi 18:6a4db94011d3 1387 __NOP();
sahilmgandhi 18:6a4db94011d3 1388 }
sahilmgandhi 18:6a4db94011d3 1389 while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN));
sahilmgandhi 18:6a4db94011d3 1390
sahilmgandhi 18:6a4db94011d3 1391 #if (!SAMG)
sahilmgandhi 18:6a4db94011d3 1392 /* Restore Flash in idle mode */
sahilmgandhi 18:6a4db94011d3 1393 i = PMC->PMC_FSMR;
sahilmgandhi 18:6a4db94011d3 1394 i &= ~PMC_FSMR_FLPM_Msk;
sahilmgandhi 18:6a4db94011d3 1395 i |= PMC_WAIT_MODE_FLASH_IDLE;
sahilmgandhi 18:6a4db94011d3 1396 PMC->PMC_FSMR = i;
sahilmgandhi 18:6a4db94011d3 1397 #endif
sahilmgandhi 18:6a4db94011d3 1398 }
sahilmgandhi 18:6a4db94011d3 1399 #else
sahilmgandhi 18:6a4db94011d3 1400 /**
sahilmgandhi 18:6a4db94011d3 1401 * \brief Enable Wait Mode. Enter condition: WFE + (SLEEPDEEP bit = 0) +
sahilmgandhi 18:6a4db94011d3 1402 * (LPM bit = 1)
sahilmgandhi 18:6a4db94011d3 1403 */
sahilmgandhi 18:6a4db94011d3 1404 void pmc_enable_waitmode(void)
sahilmgandhi 18:6a4db94011d3 1405 {
sahilmgandhi 18:6a4db94011d3 1406 uint32_t i;
sahilmgandhi 18:6a4db94011d3 1407
sahilmgandhi 18:6a4db94011d3 1408 PMC->PMC_FSMR |= PMC_FSMR_LPM; /* Enter Wait mode */
sahilmgandhi 18:6a4db94011d3 1409 SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; /* Deep sleep */
sahilmgandhi 18:6a4db94011d3 1410
sahilmgandhi 18:6a4db94011d3 1411 __WFE();
sahilmgandhi 18:6a4db94011d3 1412
sahilmgandhi 18:6a4db94011d3 1413 /* Waiting for MOSCRCEN bit cleared is strongly recommended
sahilmgandhi 18:6a4db94011d3 1414 * to ensure that the core will not execute undesired instructions
sahilmgandhi 18:6a4db94011d3 1415 */
sahilmgandhi 18:6a4db94011d3 1416 for (i = 0; i < 500; i++) {
sahilmgandhi 18:6a4db94011d3 1417 __NOP();
sahilmgandhi 18:6a4db94011d3 1418 }
sahilmgandhi 18:6a4db94011d3 1419 while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN));
sahilmgandhi 18:6a4db94011d3 1420
sahilmgandhi 18:6a4db94011d3 1421 }
sahilmgandhi 18:6a4db94011d3 1422 #endif
sahilmgandhi 18:6a4db94011d3 1423
sahilmgandhi 18:6a4db94011d3 1424 #if (!(SAMG51 || SAMG53 || SAMG54))
sahilmgandhi 18:6a4db94011d3 1425 /**
sahilmgandhi 18:6a4db94011d3 1426 * \brief Enable Backup Mode. Enter condition: WFE/(VROFF bit = 1) +
sahilmgandhi 18:6a4db94011d3 1427 * (SLEEPDEEP bit = 1)
sahilmgandhi 18:6a4db94011d3 1428 */
sahilmgandhi 18:6a4db94011d3 1429 void pmc_enable_backupmode(void)
sahilmgandhi 18:6a4db94011d3 1430 {
sahilmgandhi 18:6a4db94011d3 1431 #if (SAM4C || SAM4CM || SAM4CP)
sahilmgandhi 18:6a4db94011d3 1432 uint32_t tmp = SUPC->SUPC_MR & ~(SUPC_MR_BUPPOREN | SUPC_MR_KEY_Msk);
sahilmgandhi 18:6a4db94011d3 1433 SUPC->SUPC_MR = tmp | SUPC_MR_KEY_PASSWD;
sahilmgandhi 18:6a4db94011d3 1434 while (SUPC->SUPC_SR & SUPC_SR_BUPPORS);
sahilmgandhi 18:6a4db94011d3 1435 #endif
sahilmgandhi 18:6a4db94011d3 1436 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
sahilmgandhi 18:6a4db94011d3 1437 #if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 1438 SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_VROFF_STOP_VREG;
sahilmgandhi 18:6a4db94011d3 1439 __WFE();
sahilmgandhi 18:6a4db94011d3 1440 __WFI();
sahilmgandhi 18:6a4db94011d3 1441 #else
sahilmgandhi 18:6a4db94011d3 1442 __WFE();
sahilmgandhi 18:6a4db94011d3 1443 #endif
sahilmgandhi 18:6a4db94011d3 1444 }
sahilmgandhi 18:6a4db94011d3 1445 #endif
sahilmgandhi 18:6a4db94011d3 1446
sahilmgandhi 18:6a4db94011d3 1447 /**
sahilmgandhi 18:6a4db94011d3 1448 * \brief Enable Clock Failure Detector.
sahilmgandhi 18:6a4db94011d3 1449 */
sahilmgandhi 18:6a4db94011d3 1450 void pmc_enable_clock_failure_detector(void)
sahilmgandhi 18:6a4db94011d3 1451 {
sahilmgandhi 18:6a4db94011d3 1452 uint32_t ul_reg = PMC->CKGR_MOR;
sahilmgandhi 18:6a4db94011d3 1453
sahilmgandhi 18:6a4db94011d3 1454 PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_CFDEN | ul_reg;
sahilmgandhi 18:6a4db94011d3 1455 }
sahilmgandhi 18:6a4db94011d3 1456
sahilmgandhi 18:6a4db94011d3 1457 /**
sahilmgandhi 18:6a4db94011d3 1458 * \brief Disable Clock Failure Detector.
sahilmgandhi 18:6a4db94011d3 1459 */
sahilmgandhi 18:6a4db94011d3 1460 void pmc_disable_clock_failure_detector(void)
sahilmgandhi 18:6a4db94011d3 1461 {
sahilmgandhi 18:6a4db94011d3 1462 uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_CFDEN);
sahilmgandhi 18:6a4db94011d3 1463
sahilmgandhi 18:6a4db94011d3 1464 PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | ul_reg;
sahilmgandhi 18:6a4db94011d3 1465 }
sahilmgandhi 18:6a4db94011d3 1466
sahilmgandhi 18:6a4db94011d3 1467 #if (SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 1468 /**
sahilmgandhi 18:6a4db94011d3 1469 * \brief Enable Slow Crystal Oscillator Frequency Monitoring.
sahilmgandhi 18:6a4db94011d3 1470 */
sahilmgandhi 18:6a4db94011d3 1471 void pmc_enable_sclk_osc_freq_monitor(void)
sahilmgandhi 18:6a4db94011d3 1472 {
sahilmgandhi 18:6a4db94011d3 1473 uint32_t ul_reg = PMC->CKGR_MOR;
sahilmgandhi 18:6a4db94011d3 1474
sahilmgandhi 18:6a4db94011d3 1475 PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_XT32KFME | ul_reg;
sahilmgandhi 18:6a4db94011d3 1476 }
sahilmgandhi 18:6a4db94011d3 1477
sahilmgandhi 18:6a4db94011d3 1478 /**
sahilmgandhi 18:6a4db94011d3 1479 * \brief Disable Slow Crystal Oscillator Frequency Monitoring.
sahilmgandhi 18:6a4db94011d3 1480 */
sahilmgandhi 18:6a4db94011d3 1481 void pmc_disable_sclk_osc_freq_monitor(void)
sahilmgandhi 18:6a4db94011d3 1482 {
sahilmgandhi 18:6a4db94011d3 1483 uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_XT32KFME);
sahilmgandhi 18:6a4db94011d3 1484
sahilmgandhi 18:6a4db94011d3 1485 PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | ul_reg;
sahilmgandhi 18:6a4db94011d3 1486 }
sahilmgandhi 18:6a4db94011d3 1487 #endif
sahilmgandhi 18:6a4db94011d3 1488
sahilmgandhi 18:6a4db94011d3 1489 /**
sahilmgandhi 18:6a4db94011d3 1490 * \brief Enable or disable write protect of PMC registers.
sahilmgandhi 18:6a4db94011d3 1491 *
sahilmgandhi 18:6a4db94011d3 1492 * \param ul_enable 1 to enable, 0 to disable.
sahilmgandhi 18:6a4db94011d3 1493 */
sahilmgandhi 18:6a4db94011d3 1494 void pmc_set_writeprotect(uint32_t ul_enable)
sahilmgandhi 18:6a4db94011d3 1495 {
sahilmgandhi 18:6a4db94011d3 1496 if (ul_enable) {
sahilmgandhi 18:6a4db94011d3 1497 PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD | PMC_WPMR_WPEN;
sahilmgandhi 18:6a4db94011d3 1498 } else {
sahilmgandhi 18:6a4db94011d3 1499 PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD;
sahilmgandhi 18:6a4db94011d3 1500 }
sahilmgandhi 18:6a4db94011d3 1501 }
sahilmgandhi 18:6a4db94011d3 1502
sahilmgandhi 18:6a4db94011d3 1503 /**
sahilmgandhi 18:6a4db94011d3 1504 * \brief Return write protect status.
sahilmgandhi 18:6a4db94011d3 1505 *
sahilmgandhi 18:6a4db94011d3 1506 * \return Return write protect status.
sahilmgandhi 18:6a4db94011d3 1507 */
sahilmgandhi 18:6a4db94011d3 1508 uint32_t pmc_get_writeprotect_status(void)
sahilmgandhi 18:6a4db94011d3 1509 {
sahilmgandhi 18:6a4db94011d3 1510 return PMC->PMC_WPSR;
sahilmgandhi 18:6a4db94011d3 1511 }
sahilmgandhi 18:6a4db94011d3 1512
sahilmgandhi 18:6a4db94011d3 1513 #if (SAMG53 || SAMG54 || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 1514 /**
sahilmgandhi 18:6a4db94011d3 1515 * \brief Enable the specified peripheral clock.
sahilmgandhi 18:6a4db94011d3 1516 *
sahilmgandhi 18:6a4db94011d3 1517 * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
sahilmgandhi 18:6a4db94011d3 1518 *
sahilmgandhi 18:6a4db94011d3 1519 * \param ul_id Peripheral ID (ID_xxx).
sahilmgandhi 18:6a4db94011d3 1520 *
sahilmgandhi 18:6a4db94011d3 1521 * \retval 0 Success.
sahilmgandhi 18:6a4db94011d3 1522 * \retval 1 Fail.
sahilmgandhi 18:6a4db94011d3 1523 */
sahilmgandhi 18:6a4db94011d3 1524 uint32_t pmc_enable_sleepwalking(uint32_t ul_id)
sahilmgandhi 18:6a4db94011d3 1525 {
sahilmgandhi 18:6a4db94011d3 1526 uint32_t temp;
sahilmgandhi 18:6a4db94011d3 1527 #if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 1528 if ((7 <= ul_id) && (ul_id<= 29)) {
sahilmgandhi 18:6a4db94011d3 1529 #else
sahilmgandhi 18:6a4db94011d3 1530 if ((8 <= ul_id) && (ul_id<= 29)) {
sahilmgandhi 18:6a4db94011d3 1531 #endif
sahilmgandhi 18:6a4db94011d3 1532 temp = pmc_get_active_status0();
sahilmgandhi 18:6a4db94011d3 1533 if (temp & (1 << ul_id)) {
sahilmgandhi 18:6a4db94011d3 1534 return 1;
sahilmgandhi 18:6a4db94011d3 1535 }
sahilmgandhi 18:6a4db94011d3 1536 PMC->PMC_SLPWK_ER0 = 1 << ul_id;
sahilmgandhi 18:6a4db94011d3 1537 temp = pmc_get_active_status0();
sahilmgandhi 18:6a4db94011d3 1538 if (temp & (1 << ul_id)) {
sahilmgandhi 18:6a4db94011d3 1539 pmc_disable_sleepwalking(ul_id);
sahilmgandhi 18:6a4db94011d3 1540 return 1;
sahilmgandhi 18:6a4db94011d3 1541 }
sahilmgandhi 18:6a4db94011d3 1542 return 0;
sahilmgandhi 18:6a4db94011d3 1543 }
sahilmgandhi 18:6a4db94011d3 1544 #if (SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 1545 else if ((32 <= ul_id) && (ul_id<= 60)) {
sahilmgandhi 18:6a4db94011d3 1546 ul_id -= 32;
sahilmgandhi 18:6a4db94011d3 1547 temp = pmc_get_active_status1();
sahilmgandhi 18:6a4db94011d3 1548 if (temp & (1 << ul_id)) {
sahilmgandhi 18:6a4db94011d3 1549 return 1;
sahilmgandhi 18:6a4db94011d3 1550 }
sahilmgandhi 18:6a4db94011d3 1551 PMC->PMC_SLPWK_ER1 = 1 << ul_id;
sahilmgandhi 18:6a4db94011d3 1552 temp = pmc_get_active_status1();
sahilmgandhi 18:6a4db94011d3 1553 if (temp & (1 << ul_id)) {
sahilmgandhi 18:6a4db94011d3 1554 pmc_disable_sleepwalking(ul_id);
sahilmgandhi 18:6a4db94011d3 1555 return 1;
sahilmgandhi 18:6a4db94011d3 1556 }
sahilmgandhi 18:6a4db94011d3 1557 return 0;
sahilmgandhi 18:6a4db94011d3 1558 }
sahilmgandhi 18:6a4db94011d3 1559 #endif
sahilmgandhi 18:6a4db94011d3 1560 else {
sahilmgandhi 18:6a4db94011d3 1561 return 1;
sahilmgandhi 18:6a4db94011d3 1562 }
sahilmgandhi 18:6a4db94011d3 1563 }
sahilmgandhi 18:6a4db94011d3 1564
sahilmgandhi 18:6a4db94011d3 1565 /**
sahilmgandhi 18:6a4db94011d3 1566 * \brief Disable the sleepwalking of specified peripheral.
sahilmgandhi 18:6a4db94011d3 1567 *
sahilmgandhi 18:6a4db94011d3 1568 * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
sahilmgandhi 18:6a4db94011d3 1569 *
sahilmgandhi 18:6a4db94011d3 1570 * \param ul_id Peripheral ID (ID_xxx).
sahilmgandhi 18:6a4db94011d3 1571 *
sahilmgandhi 18:6a4db94011d3 1572 * \retval 0 Success.
sahilmgandhi 18:6a4db94011d3 1573 * \retval 1 Invalid parameter.
sahilmgandhi 18:6a4db94011d3 1574 */
sahilmgandhi 18:6a4db94011d3 1575 uint32_t pmc_disable_sleepwalking(uint32_t ul_id)
sahilmgandhi 18:6a4db94011d3 1576 {
sahilmgandhi 18:6a4db94011d3 1577 #if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 1578 if ((7 <= ul_id) && (ul_id<= 29)) {
sahilmgandhi 18:6a4db94011d3 1579 #else
sahilmgandhi 18:6a4db94011d3 1580 if ((8 <= ul_id) && (ul_id<= 29)) {
sahilmgandhi 18:6a4db94011d3 1581 #endif
sahilmgandhi 18:6a4db94011d3 1582 PMC->PMC_SLPWK_DR0 = 1 << ul_id;
sahilmgandhi 18:6a4db94011d3 1583 return 0;
sahilmgandhi 18:6a4db94011d3 1584 }
sahilmgandhi 18:6a4db94011d3 1585 #if (SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 1586 else if ((32 <= ul_id) && (ul_id<= 60)) {
sahilmgandhi 18:6a4db94011d3 1587 ul_id -= 32;
sahilmgandhi 18:6a4db94011d3 1588 PMC->PMC_SLPWK_DR1 = 1 << ul_id;
sahilmgandhi 18:6a4db94011d3 1589 return 0;
sahilmgandhi 18:6a4db94011d3 1590 }
sahilmgandhi 18:6a4db94011d3 1591 #endif
sahilmgandhi 18:6a4db94011d3 1592 else {
sahilmgandhi 18:6a4db94011d3 1593 return 1;
sahilmgandhi 18:6a4db94011d3 1594 }
sahilmgandhi 18:6a4db94011d3 1595 }
sahilmgandhi 18:6a4db94011d3 1596
sahilmgandhi 18:6a4db94011d3 1597 /**
sahilmgandhi 18:6a4db94011d3 1598 * \brief Return peripheral sleepwalking enable status.
sahilmgandhi 18:6a4db94011d3 1599 *
sahilmgandhi 18:6a4db94011d3 1600 * \return the status register value.
sahilmgandhi 18:6a4db94011d3 1601 */
sahilmgandhi 18:6a4db94011d3 1602 uint32_t pmc_get_sleepwalking_status0(void)
sahilmgandhi 18:6a4db94011d3 1603 {
sahilmgandhi 18:6a4db94011d3 1604 return PMC->PMC_SLPWK_SR0;
sahilmgandhi 18:6a4db94011d3 1605 }
sahilmgandhi 18:6a4db94011d3 1606
sahilmgandhi 18:6a4db94011d3 1607 /**
sahilmgandhi 18:6a4db94011d3 1608 * \brief Return peripheral active status.
sahilmgandhi 18:6a4db94011d3 1609 *
sahilmgandhi 18:6a4db94011d3 1610 * \return the status register value.
sahilmgandhi 18:6a4db94011d3 1611 */
sahilmgandhi 18:6a4db94011d3 1612 uint32_t pmc_get_active_status0(void)
sahilmgandhi 18:6a4db94011d3 1613 {
sahilmgandhi 18:6a4db94011d3 1614 return PMC->PMC_SLPWK_ASR0;
sahilmgandhi 18:6a4db94011d3 1615 }
sahilmgandhi 18:6a4db94011d3 1616
sahilmgandhi 18:6a4db94011d3 1617 #endif
sahilmgandhi 18:6a4db94011d3 1618
sahilmgandhi 18:6a4db94011d3 1619 #if (SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 1620 /**
sahilmgandhi 18:6a4db94011d3 1621 * \brief Return peripheral sleepwalking enable status.
sahilmgandhi 18:6a4db94011d3 1622 *
sahilmgandhi 18:6a4db94011d3 1623 * \return the status register value.
sahilmgandhi 18:6a4db94011d3 1624 */
sahilmgandhi 18:6a4db94011d3 1625 uint32_t pmc_get_sleepwalking_status1(void)
sahilmgandhi 18:6a4db94011d3 1626 {
sahilmgandhi 18:6a4db94011d3 1627 return PMC->PMC_SLPWK_SR1;
sahilmgandhi 18:6a4db94011d3 1628 }
sahilmgandhi 18:6a4db94011d3 1629
sahilmgandhi 18:6a4db94011d3 1630 /**
sahilmgandhi 18:6a4db94011d3 1631 * \brief Return peripheral active status.
sahilmgandhi 18:6a4db94011d3 1632 *
sahilmgandhi 18:6a4db94011d3 1633 * \return the status register value.
sahilmgandhi 18:6a4db94011d3 1634 */
sahilmgandhi 18:6a4db94011d3 1635 uint32_t pmc_get_active_status1(void)
sahilmgandhi 18:6a4db94011d3 1636 {
sahilmgandhi 18:6a4db94011d3 1637 return PMC->PMC_SLPWK_ASR1;
sahilmgandhi 18:6a4db94011d3 1638 }
sahilmgandhi 18:6a4db94011d3 1639 #endif
sahilmgandhi 18:6a4db94011d3 1640
sahilmgandhi 18:6a4db94011d3 1641 /// @cond 0
sahilmgandhi 18:6a4db94011d3 1642 /**INDENT-OFF**/
sahilmgandhi 18:6a4db94011d3 1643 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 1644 }
sahilmgandhi 18:6a4db94011d3 1645 #endif
sahilmgandhi 18:6a4db94011d3 1646 /**INDENT-ON**/
sahilmgandhi 18:6a4db94011d3 1647 /// @endcond