Mouse code for the MacroRat
mbed-dev/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/efc/efc.c@46:b156ef445742, 2017-06-03 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sat Jun 03 00:22:44 2017 +0000
- Revision:
- 46:b156ef445742
- Parent:
- 18:6a4db94011d3
Final code for internal battlebot competition.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /** |
sahilmgandhi | 18:6a4db94011d3 | 2 | * \file |
sahilmgandhi | 18:6a4db94011d3 | 3 | * |
sahilmgandhi | 18:6a4db94011d3 | 4 | * \brief Enhanced Embedded Flash Controller (EEFC) driver for SAM. |
sahilmgandhi | 18:6a4db94011d3 | 5 | * |
sahilmgandhi | 18:6a4db94011d3 | 6 | * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. |
sahilmgandhi | 18:6a4db94011d3 | 7 | * |
sahilmgandhi | 18:6a4db94011d3 | 8 | * \asf_license_start |
sahilmgandhi | 18:6a4db94011d3 | 9 | * |
sahilmgandhi | 18:6a4db94011d3 | 10 | * \page License |
sahilmgandhi | 18:6a4db94011d3 | 11 | * |
sahilmgandhi | 18:6a4db94011d3 | 12 | * Redistribution and use in source and binary forms, with or without |
sahilmgandhi | 18:6a4db94011d3 | 13 | * modification, are permitted provided that the following conditions are met: |
sahilmgandhi | 18:6a4db94011d3 | 14 | * |
sahilmgandhi | 18:6a4db94011d3 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 16 | * this list of conditions and the following disclaimer. |
sahilmgandhi | 18:6a4db94011d3 | 17 | * |
sahilmgandhi | 18:6a4db94011d3 | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 19 | * this list of conditions and the following disclaimer in the documentation |
sahilmgandhi | 18:6a4db94011d3 | 20 | * and/or other materials provided with the distribution. |
sahilmgandhi | 18:6a4db94011d3 | 21 | * |
sahilmgandhi | 18:6a4db94011d3 | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
sahilmgandhi | 18:6a4db94011d3 | 23 | * from this software without specific prior written permission. |
sahilmgandhi | 18:6a4db94011d3 | 24 | * |
sahilmgandhi | 18:6a4db94011d3 | 25 | * 4. This software may only be redistributed and used in connection with an |
sahilmgandhi | 18:6a4db94011d3 | 26 | * Atmel microcontroller product. |
sahilmgandhi | 18:6a4db94011d3 | 27 | * |
sahilmgandhi | 18:6a4db94011d3 | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
sahilmgandhi | 18:6a4db94011d3 | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
sahilmgandhi | 18:6a4db94011d3 | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
sahilmgandhi | 18:6a4db94011d3 | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
sahilmgandhi | 18:6a4db94011d3 | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
sahilmgandhi | 18:6a4db94011d3 | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
sahilmgandhi | 18:6a4db94011d3 | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
sahilmgandhi | 18:6a4db94011d3 | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
sahilmgandhi | 18:6a4db94011d3 | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
sahilmgandhi | 18:6a4db94011d3 | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
sahilmgandhi | 18:6a4db94011d3 | 38 | * POSSIBILITY OF SUCH DAMAGE. |
sahilmgandhi | 18:6a4db94011d3 | 39 | * |
sahilmgandhi | 18:6a4db94011d3 | 40 | * \asf_license_stop |
sahilmgandhi | 18:6a4db94011d3 | 41 | * |
sahilmgandhi | 18:6a4db94011d3 | 42 | */ |
sahilmgandhi | 18:6a4db94011d3 | 43 | /* |
sahilmgandhi | 18:6a4db94011d3 | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
sahilmgandhi | 18:6a4db94011d3 | 45 | */ |
sahilmgandhi | 18:6a4db94011d3 | 46 | |
sahilmgandhi | 18:6a4db94011d3 | 47 | #include "efc.h" |
sahilmgandhi | 18:6a4db94011d3 | 48 | |
sahilmgandhi | 18:6a4db94011d3 | 49 | /// @cond 0 |
sahilmgandhi | 18:6a4db94011d3 | 50 | /**INDENT-OFF**/ |
sahilmgandhi | 18:6a4db94011d3 | 51 | #ifdef __cplusplus |
sahilmgandhi | 18:6a4db94011d3 | 52 | extern "C" { |
sahilmgandhi | 18:6a4db94011d3 | 53 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 54 | /**INDENT-ON**/ |
sahilmgandhi | 18:6a4db94011d3 | 55 | /// @endcond |
sahilmgandhi | 18:6a4db94011d3 | 56 | |
sahilmgandhi | 18:6a4db94011d3 | 57 | /** |
sahilmgandhi | 18:6a4db94011d3 | 58 | * \defgroup sam_drivers_efc_group Enhanced Embedded Flash Controller (EEFC) |
sahilmgandhi | 18:6a4db94011d3 | 59 | * |
sahilmgandhi | 18:6a4db94011d3 | 60 | * The Enhanced Embedded Flash Controller ensures the interface of the Flash |
sahilmgandhi | 18:6a4db94011d3 | 61 | * block with the 32-bit internal bus. |
sahilmgandhi | 18:6a4db94011d3 | 62 | * |
sahilmgandhi | 18:6a4db94011d3 | 63 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 64 | */ |
sahilmgandhi | 18:6a4db94011d3 | 65 | |
sahilmgandhi | 18:6a4db94011d3 | 66 | /* Address definition for read operation */ |
sahilmgandhi | 18:6a4db94011d3 | 67 | #if (SAM3XA || SAM3U4 || SAM4SD16 || SAM4SD32) |
sahilmgandhi | 18:6a4db94011d3 | 68 | # define READ_BUFF_ADDR0 IFLASH0_ADDR |
sahilmgandhi | 18:6a4db94011d3 | 69 | # define READ_BUFF_ADDR1 IFLASH1_ADDR |
sahilmgandhi | 18:6a4db94011d3 | 70 | #elif (SAM3S || SAM3N || SAM4E || SAM4N || SAMG || SAMV71 || SAMV70 || SAMS70 || SAME70) |
sahilmgandhi | 18:6a4db94011d3 | 71 | # define READ_BUFF_ADDR IFLASH_ADDR |
sahilmgandhi | 18:6a4db94011d3 | 72 | #elif (SAM4C || SAM4CP || SAM4CM) |
sahilmgandhi | 18:6a4db94011d3 | 73 | #if SAM4C32 |
sahilmgandhi | 18:6a4db94011d3 | 74 | # define READ_BUFF_ADDR0 IFLASH0_CNC_ADDR |
sahilmgandhi | 18:6a4db94011d3 | 75 | # define READ_BUFF_ADDR1 IFLASH1_CNC_ADDR |
sahilmgandhi | 18:6a4db94011d3 | 76 | #else |
sahilmgandhi | 18:6a4db94011d3 | 77 | # define READ_BUFF_ADDR IFLASH_CNC_ADDR |
sahilmgandhi | 18:6a4db94011d3 | 78 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 79 | #elif (SAM3U || SAM4S) |
sahilmgandhi | 18:6a4db94011d3 | 80 | # define READ_BUFF_ADDR IFLASH0_ADDR |
sahilmgandhi | 18:6a4db94011d3 | 81 | #else |
sahilmgandhi | 18:6a4db94011d3 | 82 | # warning Only reading unique ID for sam3/4 is implemented. |
sahilmgandhi | 18:6a4db94011d3 | 83 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 84 | |
sahilmgandhi | 18:6a4db94011d3 | 85 | /* Flash Writing Protection Key */ |
sahilmgandhi | 18:6a4db94011d3 | 86 | #define FWP_KEY 0x5Au |
sahilmgandhi | 18:6a4db94011d3 | 87 | |
sahilmgandhi | 18:6a4db94011d3 | 88 | #if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM) |
sahilmgandhi | 18:6a4db94011d3 | 89 | #define EEFC_FCR_FCMD(value) \ |
sahilmgandhi | 18:6a4db94011d3 | 90 | ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos))) |
sahilmgandhi | 18:6a4db94011d3 | 91 | #define EEFC_ERROR_FLAGS (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE | EEFC_FSR_FLERR) |
sahilmgandhi | 18:6a4db94011d3 | 92 | #elif (SAMV71 || SAMV70 || SAMS70 || SAME70) |
sahilmgandhi | 18:6a4db94011d3 | 93 | #define EEFC_ERROR_FLAGS (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE | EEFC_FSR_FLERR \ |
sahilmgandhi | 18:6a4db94011d3 | 94 | | EEFC_FSR_UECCELSB | EEFC_FSR_MECCELSB | EEFC_FSR_UECCEMSB | EEFC_FSR_MECCEMSB) |
sahilmgandhi | 18:6a4db94011d3 | 95 | #else |
sahilmgandhi | 18:6a4db94011d3 | 96 | #define EEFC_ERROR_FLAGS (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE) |
sahilmgandhi | 18:6a4db94011d3 | 97 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 98 | |
sahilmgandhi | 18:6a4db94011d3 | 99 | #ifndef EEFC_FCR_FKEY_PASSWD |
sahilmgandhi | 18:6a4db94011d3 | 100 | #define EEFC_FCR_FKEY_PASSWD EEFC_FCR_FKEY(FWP_KEY) |
sahilmgandhi | 18:6a4db94011d3 | 101 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 102 | |
sahilmgandhi | 18:6a4db94011d3 | 103 | |
sahilmgandhi | 18:6a4db94011d3 | 104 | /* |
sahilmgandhi | 18:6a4db94011d3 | 105 | * Local function declaration. |
sahilmgandhi | 18:6a4db94011d3 | 106 | * Because they are RAM functions, they need 'extern' declaration. |
sahilmgandhi | 18:6a4db94011d3 | 107 | */ |
sahilmgandhi | 18:6a4db94011d3 | 108 | extern void efc_write_fmr(Efc *p_efc, uint32_t ul_fmr); |
sahilmgandhi | 18:6a4db94011d3 | 109 | extern uint32_t efc_perform_fcr(Efc *p_efc, uint32_t ul_fcr); |
sahilmgandhi | 18:6a4db94011d3 | 110 | |
sahilmgandhi | 18:6a4db94011d3 | 111 | /** |
sahilmgandhi | 18:6a4db94011d3 | 112 | * \brief Initialize the EFC controller. |
sahilmgandhi | 18:6a4db94011d3 | 113 | * |
sahilmgandhi | 18:6a4db94011d3 | 114 | * \param ul_access_mode 0 for 128-bit, EEFC_FMR_FAM for 64-bit. |
sahilmgandhi | 18:6a4db94011d3 | 115 | * \param ul_fws The number of wait states in cycle (no shift). |
sahilmgandhi | 18:6a4db94011d3 | 116 | * |
sahilmgandhi | 18:6a4db94011d3 | 117 | * \return 0 if successful. |
sahilmgandhi | 18:6a4db94011d3 | 118 | */ |
sahilmgandhi | 18:6a4db94011d3 | 119 | uint32_t efc_init(Efc *p_efc, uint32_t ul_access_mode, uint32_t ul_fws) |
sahilmgandhi | 18:6a4db94011d3 | 120 | { |
sahilmgandhi | 18:6a4db94011d3 | 121 | #if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \ |
sahilmgandhi | 18:6a4db94011d3 | 122 | SAMV71 || SAMV70 || SAMS70 || SAME70) |
sahilmgandhi | 18:6a4db94011d3 | 123 | efc_write_fmr(p_efc, ul_access_mode | EEFC_FMR_FWS(ul_fws) | EEFC_FMR_CLOE); |
sahilmgandhi | 18:6a4db94011d3 | 124 | #else |
sahilmgandhi | 18:6a4db94011d3 | 125 | efc_write_fmr(p_efc, ul_access_mode | EEFC_FMR_FWS(ul_fws)); |
sahilmgandhi | 18:6a4db94011d3 | 126 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 127 | return EFC_RC_OK; |
sahilmgandhi | 18:6a4db94011d3 | 128 | } |
sahilmgandhi | 18:6a4db94011d3 | 129 | |
sahilmgandhi | 18:6a4db94011d3 | 130 | #if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \ |
sahilmgandhi | 18:6a4db94011d3 | 131 | SAMV71 || SAMV70 || SAMS70 || SAME70) |
sahilmgandhi | 18:6a4db94011d3 | 132 | /** |
sahilmgandhi | 18:6a4db94011d3 | 133 | * \brief Enable code loop optimization. |
sahilmgandhi | 18:6a4db94011d3 | 134 | * |
sahilmgandhi | 18:6a4db94011d3 | 135 | * \param p_efc Pointer to an EFC instance. |
sahilmgandhi | 18:6a4db94011d3 | 136 | */ |
sahilmgandhi | 18:6a4db94011d3 | 137 | void efc_enable_cloe(Efc *p_efc) |
sahilmgandhi | 18:6a4db94011d3 | 138 | { |
sahilmgandhi | 18:6a4db94011d3 | 139 | uint32_t ul_fmr = p_efc->EEFC_FMR; |
sahilmgandhi | 18:6a4db94011d3 | 140 | efc_write_fmr(p_efc, ul_fmr | EEFC_FMR_CLOE); |
sahilmgandhi | 18:6a4db94011d3 | 141 | } |
sahilmgandhi | 18:6a4db94011d3 | 142 | |
sahilmgandhi | 18:6a4db94011d3 | 143 | /** |
sahilmgandhi | 18:6a4db94011d3 | 144 | * \brief Disable code loop optimization. |
sahilmgandhi | 18:6a4db94011d3 | 145 | * |
sahilmgandhi | 18:6a4db94011d3 | 146 | * \param p_efc Pointer to an EFC instance. |
sahilmgandhi | 18:6a4db94011d3 | 147 | */ |
sahilmgandhi | 18:6a4db94011d3 | 148 | void efc_disable_cloe(Efc *p_efc) |
sahilmgandhi | 18:6a4db94011d3 | 149 | { |
sahilmgandhi | 18:6a4db94011d3 | 150 | uint32_t ul_fmr = p_efc->EEFC_FMR; |
sahilmgandhi | 18:6a4db94011d3 | 151 | efc_write_fmr(p_efc, ul_fmr & (~EEFC_FMR_CLOE)); |
sahilmgandhi | 18:6a4db94011d3 | 152 | } |
sahilmgandhi | 18:6a4db94011d3 | 153 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 154 | |
sahilmgandhi | 18:6a4db94011d3 | 155 | |
sahilmgandhi | 18:6a4db94011d3 | 156 | |
sahilmgandhi | 18:6a4db94011d3 | 157 | /** |
sahilmgandhi | 18:6a4db94011d3 | 158 | * \brief Enable the flash ready interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 159 | * |
sahilmgandhi | 18:6a4db94011d3 | 160 | * \param p_efc Pointer to an EFC instance. |
sahilmgandhi | 18:6a4db94011d3 | 161 | */ |
sahilmgandhi | 18:6a4db94011d3 | 162 | void efc_enable_frdy_interrupt(Efc *p_efc) |
sahilmgandhi | 18:6a4db94011d3 | 163 | { |
sahilmgandhi | 18:6a4db94011d3 | 164 | uint32_t ul_fmr = p_efc->EEFC_FMR; |
sahilmgandhi | 18:6a4db94011d3 | 165 | |
sahilmgandhi | 18:6a4db94011d3 | 166 | efc_write_fmr(p_efc, ul_fmr | EEFC_FMR_FRDY); |
sahilmgandhi | 18:6a4db94011d3 | 167 | } |
sahilmgandhi | 18:6a4db94011d3 | 168 | |
sahilmgandhi | 18:6a4db94011d3 | 169 | /** |
sahilmgandhi | 18:6a4db94011d3 | 170 | * \brief Disable the flash ready interrupt. |
sahilmgandhi | 18:6a4db94011d3 | 171 | * |
sahilmgandhi | 18:6a4db94011d3 | 172 | * \param p_efc Pointer to an EFC instance. |
sahilmgandhi | 18:6a4db94011d3 | 173 | */ |
sahilmgandhi | 18:6a4db94011d3 | 174 | void efc_disable_frdy_interrupt(Efc *p_efc) |
sahilmgandhi | 18:6a4db94011d3 | 175 | { |
sahilmgandhi | 18:6a4db94011d3 | 176 | uint32_t ul_fmr = p_efc->EEFC_FMR; |
sahilmgandhi | 18:6a4db94011d3 | 177 | |
sahilmgandhi | 18:6a4db94011d3 | 178 | efc_write_fmr(p_efc, ul_fmr & (~EEFC_FMR_FRDY)); |
sahilmgandhi | 18:6a4db94011d3 | 179 | } |
sahilmgandhi | 18:6a4db94011d3 | 180 | |
sahilmgandhi | 18:6a4db94011d3 | 181 | #if (SAMV71 || SAMV70 || SAMS70 || SAME70) |
sahilmgandhi | 18:6a4db94011d3 | 182 | /** |
sahilmgandhi | 18:6a4db94011d3 | 183 | * \brief Enable the write protection. |
sahilmgandhi | 18:6a4db94011d3 | 184 | * |
sahilmgandhi | 18:6a4db94011d3 | 185 | * \param p_efc Pointer to an EFC instance. |
sahilmgandhi | 18:6a4db94011d3 | 186 | */ |
sahilmgandhi | 18:6a4db94011d3 | 187 | void efc_enable_write_protection(Efc *p_efc) |
sahilmgandhi | 18:6a4db94011d3 | 188 | { |
sahilmgandhi | 18:6a4db94011d3 | 189 | p_efc->EEFC_WPMR = EEFC_WPMR_WPKEY_PASSWD | EEFC_WPMR_WPEN; |
sahilmgandhi | 18:6a4db94011d3 | 190 | } |
sahilmgandhi | 18:6a4db94011d3 | 191 | |
sahilmgandhi | 18:6a4db94011d3 | 192 | /** |
sahilmgandhi | 18:6a4db94011d3 | 193 | * \brief Disable the write protection. |
sahilmgandhi | 18:6a4db94011d3 | 194 | * |
sahilmgandhi | 18:6a4db94011d3 | 195 | * \param p_efc Pointer to an EFC instance. |
sahilmgandhi | 18:6a4db94011d3 | 196 | */ |
sahilmgandhi | 18:6a4db94011d3 | 197 | void efc_disable_write_protection(Efc *p_efc) |
sahilmgandhi | 18:6a4db94011d3 | 198 | { |
sahilmgandhi | 18:6a4db94011d3 | 199 | p_efc->EEFC_WPMR = EEFC_WPMR_WPKEY_PASSWD; |
sahilmgandhi | 18:6a4db94011d3 | 200 | } |
sahilmgandhi | 18:6a4db94011d3 | 201 | #else |
sahilmgandhi | 18:6a4db94011d3 | 202 | /** |
sahilmgandhi | 18:6a4db94011d3 | 203 | * \brief Set flash access mode. |
sahilmgandhi | 18:6a4db94011d3 | 204 | * |
sahilmgandhi | 18:6a4db94011d3 | 205 | * \param p_efc Pointer to an EFC instance. |
sahilmgandhi | 18:6a4db94011d3 | 206 | * \param ul_mode 0 for 128-bit, EEFC_FMR_FAM for 64-bit. |
sahilmgandhi | 18:6a4db94011d3 | 207 | */ |
sahilmgandhi | 18:6a4db94011d3 | 208 | void efc_set_flash_access_mode(Efc *p_efc, uint32_t ul_mode) |
sahilmgandhi | 18:6a4db94011d3 | 209 | { |
sahilmgandhi | 18:6a4db94011d3 | 210 | uint32_t ul_fmr = p_efc->EEFC_FMR & (~EEFC_FMR_FAM); |
sahilmgandhi | 18:6a4db94011d3 | 211 | |
sahilmgandhi | 18:6a4db94011d3 | 212 | efc_write_fmr(p_efc, ul_fmr | ul_mode); |
sahilmgandhi | 18:6a4db94011d3 | 213 | } |
sahilmgandhi | 18:6a4db94011d3 | 214 | |
sahilmgandhi | 18:6a4db94011d3 | 215 | /** |
sahilmgandhi | 18:6a4db94011d3 | 216 | * \brief Get flash access mode. |
sahilmgandhi | 18:6a4db94011d3 | 217 | * |
sahilmgandhi | 18:6a4db94011d3 | 218 | * \param p_efc Pointer to an EFC instance. |
sahilmgandhi | 18:6a4db94011d3 | 219 | * |
sahilmgandhi | 18:6a4db94011d3 | 220 | * \return 0 for 128-bit or EEFC_FMR_FAM for 64-bit. |
sahilmgandhi | 18:6a4db94011d3 | 221 | */ |
sahilmgandhi | 18:6a4db94011d3 | 222 | uint32_t efc_get_flash_access_mode(Efc *p_efc) |
sahilmgandhi | 18:6a4db94011d3 | 223 | { |
sahilmgandhi | 18:6a4db94011d3 | 224 | return (p_efc->EEFC_FMR & EEFC_FMR_FAM); |
sahilmgandhi | 18:6a4db94011d3 | 225 | } |
sahilmgandhi | 18:6a4db94011d3 | 226 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 227 | |
sahilmgandhi | 18:6a4db94011d3 | 228 | /** |
sahilmgandhi | 18:6a4db94011d3 | 229 | * \brief Set flash wait state. |
sahilmgandhi | 18:6a4db94011d3 | 230 | * |
sahilmgandhi | 18:6a4db94011d3 | 231 | * \param p_efc Pointer to an EFC instance. |
sahilmgandhi | 18:6a4db94011d3 | 232 | * \param ul_fws The number of wait states in cycle (no shift). |
sahilmgandhi | 18:6a4db94011d3 | 233 | */ |
sahilmgandhi | 18:6a4db94011d3 | 234 | void efc_set_wait_state(Efc *p_efc, uint32_t ul_fws) |
sahilmgandhi | 18:6a4db94011d3 | 235 | { |
sahilmgandhi | 18:6a4db94011d3 | 236 | uint32_t ul_fmr = p_efc->EEFC_FMR & (~EEFC_FMR_FWS_Msk); |
sahilmgandhi | 18:6a4db94011d3 | 237 | |
sahilmgandhi | 18:6a4db94011d3 | 238 | efc_write_fmr(p_efc, ul_fmr | EEFC_FMR_FWS(ul_fws)); |
sahilmgandhi | 18:6a4db94011d3 | 239 | } |
sahilmgandhi | 18:6a4db94011d3 | 240 | |
sahilmgandhi | 18:6a4db94011d3 | 241 | /** |
sahilmgandhi | 18:6a4db94011d3 | 242 | * \brief Get flash wait state. |
sahilmgandhi | 18:6a4db94011d3 | 243 | * |
sahilmgandhi | 18:6a4db94011d3 | 244 | * \param p_efc Pointer to an EFC instance. |
sahilmgandhi | 18:6a4db94011d3 | 245 | * |
sahilmgandhi | 18:6a4db94011d3 | 246 | * \return The number of wait states in cycle (no shift). |
sahilmgandhi | 18:6a4db94011d3 | 247 | */ |
sahilmgandhi | 18:6a4db94011d3 | 248 | uint32_t efc_get_wait_state(Efc *p_efc) |
sahilmgandhi | 18:6a4db94011d3 | 249 | { |
sahilmgandhi | 18:6a4db94011d3 | 250 | return ((p_efc->EEFC_FMR & EEFC_FMR_FWS_Msk) >> EEFC_FMR_FWS_Pos); |
sahilmgandhi | 18:6a4db94011d3 | 251 | } |
sahilmgandhi | 18:6a4db94011d3 | 252 | |
sahilmgandhi | 18:6a4db94011d3 | 253 | /** |
sahilmgandhi | 18:6a4db94011d3 | 254 | * \brief Perform the given command and wait until its completion (or an error). |
sahilmgandhi | 18:6a4db94011d3 | 255 | * |
sahilmgandhi | 18:6a4db94011d3 | 256 | * \note Unique ID commands are not supported, use efc_perform_read_sequence. |
sahilmgandhi | 18:6a4db94011d3 | 257 | * |
sahilmgandhi | 18:6a4db94011d3 | 258 | * \param p_efc Pointer to an EFC instance. |
sahilmgandhi | 18:6a4db94011d3 | 259 | * \param ul_command Command to perform. |
sahilmgandhi | 18:6a4db94011d3 | 260 | * \param ul_argument Optional command argument. |
sahilmgandhi | 18:6a4db94011d3 | 261 | * |
sahilmgandhi | 18:6a4db94011d3 | 262 | * \note This function will automatically choose to use IAP function. |
sahilmgandhi | 18:6a4db94011d3 | 263 | * |
sahilmgandhi | 18:6a4db94011d3 | 264 | * \return 0 if successful, otherwise returns an error code. |
sahilmgandhi | 18:6a4db94011d3 | 265 | */ |
sahilmgandhi | 18:6a4db94011d3 | 266 | uint32_t efc_perform_command(Efc *p_efc, uint32_t ul_command, |
sahilmgandhi | 18:6a4db94011d3 | 267 | uint32_t ul_argument) |
sahilmgandhi | 18:6a4db94011d3 | 268 | { |
sahilmgandhi | 18:6a4db94011d3 | 269 | uint32_t result; |
sahilmgandhi | 18:6a4db94011d3 | 270 | irqflags_t flags; |
sahilmgandhi | 18:6a4db94011d3 | 271 | |
sahilmgandhi | 18:6a4db94011d3 | 272 | /* Unique ID commands are not supported. */ |
sahilmgandhi | 18:6a4db94011d3 | 273 | if (ul_command == EFC_FCMD_STUI || ul_command == EFC_FCMD_SPUI) { |
sahilmgandhi | 18:6a4db94011d3 | 274 | return EFC_RC_NOT_SUPPORT; |
sahilmgandhi | 18:6a4db94011d3 | 275 | } |
sahilmgandhi | 18:6a4db94011d3 | 276 | |
sahilmgandhi | 18:6a4db94011d3 | 277 | flags = cpu_irq_save(); |
sahilmgandhi | 18:6a4db94011d3 | 278 | /* Use RAM Function. */ |
sahilmgandhi | 18:6a4db94011d3 | 279 | result = efc_perform_fcr(p_efc, |
sahilmgandhi | 18:6a4db94011d3 | 280 | EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(ul_argument) | |
sahilmgandhi | 18:6a4db94011d3 | 281 | EEFC_FCR_FCMD(ul_command)); |
sahilmgandhi | 18:6a4db94011d3 | 282 | cpu_irq_restore(flags); |
sahilmgandhi | 18:6a4db94011d3 | 283 | return result; |
sahilmgandhi | 18:6a4db94011d3 | 284 | } |
sahilmgandhi | 18:6a4db94011d3 | 285 | |
sahilmgandhi | 18:6a4db94011d3 | 286 | /** |
sahilmgandhi | 18:6a4db94011d3 | 287 | * \brief Get the current status of the EEFC. |
sahilmgandhi | 18:6a4db94011d3 | 288 | * |
sahilmgandhi | 18:6a4db94011d3 | 289 | * \note This function clears the value of some status bits (FLOCKE, FCMDE). |
sahilmgandhi | 18:6a4db94011d3 | 290 | * |
sahilmgandhi | 18:6a4db94011d3 | 291 | * \param p_efc Pointer to an EFC instance. |
sahilmgandhi | 18:6a4db94011d3 | 292 | * |
sahilmgandhi | 18:6a4db94011d3 | 293 | * \return The current status. |
sahilmgandhi | 18:6a4db94011d3 | 294 | */ |
sahilmgandhi | 18:6a4db94011d3 | 295 | uint32_t efc_get_status(Efc *p_efc) |
sahilmgandhi | 18:6a4db94011d3 | 296 | { |
sahilmgandhi | 18:6a4db94011d3 | 297 | return p_efc->EEFC_FSR; |
sahilmgandhi | 18:6a4db94011d3 | 298 | } |
sahilmgandhi | 18:6a4db94011d3 | 299 | |
sahilmgandhi | 18:6a4db94011d3 | 300 | /** |
sahilmgandhi | 18:6a4db94011d3 | 301 | * \brief Get the result of the last executed command. |
sahilmgandhi | 18:6a4db94011d3 | 302 | * |
sahilmgandhi | 18:6a4db94011d3 | 303 | * \param p_efc Pointer to an EFC instance. |
sahilmgandhi | 18:6a4db94011d3 | 304 | * |
sahilmgandhi | 18:6a4db94011d3 | 305 | * \return The result of the last executed command. |
sahilmgandhi | 18:6a4db94011d3 | 306 | */ |
sahilmgandhi | 18:6a4db94011d3 | 307 | uint32_t efc_get_result(Efc *p_efc) |
sahilmgandhi | 18:6a4db94011d3 | 308 | { |
sahilmgandhi | 18:6a4db94011d3 | 309 | return p_efc->EEFC_FRR; |
sahilmgandhi | 18:6a4db94011d3 | 310 | } |
sahilmgandhi | 18:6a4db94011d3 | 311 | |
sahilmgandhi | 18:6a4db94011d3 | 312 | /** |
sahilmgandhi | 18:6a4db94011d3 | 313 | * \brief Perform read sequence. Supported sequences are read Unique ID and |
sahilmgandhi | 18:6a4db94011d3 | 314 | * read User Signature |
sahilmgandhi | 18:6a4db94011d3 | 315 | * |
sahilmgandhi | 18:6a4db94011d3 | 316 | * \param p_efc Pointer to an EFC instance. |
sahilmgandhi | 18:6a4db94011d3 | 317 | * \param ul_cmd_st Start command to perform. |
sahilmgandhi | 18:6a4db94011d3 | 318 | * \param ul_cmd_sp Stop command to perform. |
sahilmgandhi | 18:6a4db94011d3 | 319 | * \param p_ul_buf Pointer to an data buffer. |
sahilmgandhi | 18:6a4db94011d3 | 320 | * \param ul_size Buffer size. |
sahilmgandhi | 18:6a4db94011d3 | 321 | * |
sahilmgandhi | 18:6a4db94011d3 | 322 | * \return 0 if successful, otherwise returns an error code. |
sahilmgandhi | 18:6a4db94011d3 | 323 | */ |
sahilmgandhi | 18:6a4db94011d3 | 324 | __no_inline |
sahilmgandhi | 18:6a4db94011d3 | 325 | RAMFUNC |
sahilmgandhi | 18:6a4db94011d3 | 326 | uint32_t efc_perform_read_sequence(Efc *p_efc, |
sahilmgandhi | 18:6a4db94011d3 | 327 | uint32_t ul_cmd_st, uint32_t ul_cmd_sp, |
sahilmgandhi | 18:6a4db94011d3 | 328 | uint32_t *p_ul_buf, uint32_t ul_size) |
sahilmgandhi | 18:6a4db94011d3 | 329 | { |
sahilmgandhi | 18:6a4db94011d3 | 330 | volatile uint32_t ul_status; |
sahilmgandhi | 18:6a4db94011d3 | 331 | uint32_t ul_cnt; |
sahilmgandhi | 18:6a4db94011d3 | 332 | |
sahilmgandhi | 18:6a4db94011d3 | 333 | #if (SAM3U4 || SAM3XA || SAM4SD16 || SAM4SD32 || SAM4C32) |
sahilmgandhi | 18:6a4db94011d3 | 334 | uint32_t *p_ul_data = |
sahilmgandhi | 18:6a4db94011d3 | 335 | (uint32_t *) ((p_efc == EFC0) ? |
sahilmgandhi | 18:6a4db94011d3 | 336 | READ_BUFF_ADDR0 : READ_BUFF_ADDR1); |
sahilmgandhi | 18:6a4db94011d3 | 337 | #elif (SAM3S || SAM4S || SAM3N || SAM3U || SAM4E || SAM4N || SAM4C || SAMG || \ |
sahilmgandhi | 18:6a4db94011d3 | 338 | SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAMS70 || SAME70) |
sahilmgandhi | 18:6a4db94011d3 | 339 | uint32_t *p_ul_data = (uint32_t *) READ_BUFF_ADDR; |
sahilmgandhi | 18:6a4db94011d3 | 340 | #else |
sahilmgandhi | 18:6a4db94011d3 | 341 | return EFC_RC_NOT_SUPPORT; |
sahilmgandhi | 18:6a4db94011d3 | 342 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 343 | |
sahilmgandhi | 18:6a4db94011d3 | 344 | if (p_ul_buf == NULL) { |
sahilmgandhi | 18:6a4db94011d3 | 345 | return EFC_RC_INVALID; |
sahilmgandhi | 18:6a4db94011d3 | 346 | } |
sahilmgandhi | 18:6a4db94011d3 | 347 | |
sahilmgandhi | 18:6a4db94011d3 | 348 | p_efc->EEFC_FMR |= (0x1u << 16); |
sahilmgandhi | 18:6a4db94011d3 | 349 | |
sahilmgandhi | 18:6a4db94011d3 | 350 | /* Send the Start Read command */ |
sahilmgandhi | 18:6a4db94011d3 | 351 | #if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \ |
sahilmgandhi | 18:6a4db94011d3 | 352 | SAMV71 || SAMV70 || SAMS70 || SAME70) |
sahilmgandhi | 18:6a4db94011d3 | 353 | p_efc->EEFC_FCR = EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(0) |
sahilmgandhi | 18:6a4db94011d3 | 354 | | EEFC_FCR_FCMD(ul_cmd_st); |
sahilmgandhi | 18:6a4db94011d3 | 355 | #else |
sahilmgandhi | 18:6a4db94011d3 | 356 | p_efc->EEFC_FCR = EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(0) |
sahilmgandhi | 18:6a4db94011d3 | 357 | | EEFC_FCR_FCMD(ul_cmd_st); |
sahilmgandhi | 18:6a4db94011d3 | 358 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 359 | /* Wait for the FRDY bit in the Flash Programming Status Register |
sahilmgandhi | 18:6a4db94011d3 | 360 | * (EEFC_FSR) falls. |
sahilmgandhi | 18:6a4db94011d3 | 361 | */ |
sahilmgandhi | 18:6a4db94011d3 | 362 | do { |
sahilmgandhi | 18:6a4db94011d3 | 363 | ul_status = p_efc->EEFC_FSR; |
sahilmgandhi | 18:6a4db94011d3 | 364 | } while ((ul_status & EEFC_FSR_FRDY) == EEFC_FSR_FRDY); |
sahilmgandhi | 18:6a4db94011d3 | 365 | |
sahilmgandhi | 18:6a4db94011d3 | 366 | /* The data is located in the first address of the Flash |
sahilmgandhi | 18:6a4db94011d3 | 367 | * memory mapping. |
sahilmgandhi | 18:6a4db94011d3 | 368 | */ |
sahilmgandhi | 18:6a4db94011d3 | 369 | for (ul_cnt = 0; ul_cnt < ul_size; ul_cnt++) { |
sahilmgandhi | 18:6a4db94011d3 | 370 | p_ul_buf[ul_cnt] = p_ul_data[ul_cnt]; |
sahilmgandhi | 18:6a4db94011d3 | 371 | } |
sahilmgandhi | 18:6a4db94011d3 | 372 | |
sahilmgandhi | 18:6a4db94011d3 | 373 | /* To stop the read mode */ |
sahilmgandhi | 18:6a4db94011d3 | 374 | p_efc->EEFC_FCR = |
sahilmgandhi | 18:6a4db94011d3 | 375 | #if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \ |
sahilmgandhi | 18:6a4db94011d3 | 376 | SAMV71 || SAMV70 || SAMS70 || SAME70) |
sahilmgandhi | 18:6a4db94011d3 | 377 | EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(0) | |
sahilmgandhi | 18:6a4db94011d3 | 378 | EEFC_FCR_FCMD(ul_cmd_sp); |
sahilmgandhi | 18:6a4db94011d3 | 379 | #else |
sahilmgandhi | 18:6a4db94011d3 | 380 | EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(0) | |
sahilmgandhi | 18:6a4db94011d3 | 381 | EEFC_FCR_FCMD(ul_cmd_sp); |
sahilmgandhi | 18:6a4db94011d3 | 382 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 383 | /* Wait for the FRDY bit in the Flash Programming Status Register (EEFC_FSR) |
sahilmgandhi | 18:6a4db94011d3 | 384 | * rises. |
sahilmgandhi | 18:6a4db94011d3 | 385 | */ |
sahilmgandhi | 18:6a4db94011d3 | 386 | do { |
sahilmgandhi | 18:6a4db94011d3 | 387 | ul_status = p_efc->EEFC_FSR; |
sahilmgandhi | 18:6a4db94011d3 | 388 | } while ((ul_status & EEFC_FSR_FRDY) != EEFC_FSR_FRDY); |
sahilmgandhi | 18:6a4db94011d3 | 389 | |
sahilmgandhi | 18:6a4db94011d3 | 390 | p_efc->EEFC_FMR &= ~(0x1u << 16); |
sahilmgandhi | 18:6a4db94011d3 | 391 | |
sahilmgandhi | 18:6a4db94011d3 | 392 | return EFC_RC_OK; |
sahilmgandhi | 18:6a4db94011d3 | 393 | } |
sahilmgandhi | 18:6a4db94011d3 | 394 | |
sahilmgandhi | 18:6a4db94011d3 | 395 | /** |
sahilmgandhi | 18:6a4db94011d3 | 396 | * \brief Set mode register. |
sahilmgandhi | 18:6a4db94011d3 | 397 | * |
sahilmgandhi | 18:6a4db94011d3 | 398 | * \param p_efc Pointer to an EFC instance. |
sahilmgandhi | 18:6a4db94011d3 | 399 | * \param ul_fmr Value of mode register |
sahilmgandhi | 18:6a4db94011d3 | 400 | */ |
sahilmgandhi | 18:6a4db94011d3 | 401 | __no_inline |
sahilmgandhi | 18:6a4db94011d3 | 402 | RAMFUNC |
sahilmgandhi | 18:6a4db94011d3 | 403 | void efc_write_fmr(Efc *p_efc, uint32_t ul_fmr) |
sahilmgandhi | 18:6a4db94011d3 | 404 | { |
sahilmgandhi | 18:6a4db94011d3 | 405 | p_efc->EEFC_FMR = ul_fmr; |
sahilmgandhi | 18:6a4db94011d3 | 406 | } |
sahilmgandhi | 18:6a4db94011d3 | 407 | |
sahilmgandhi | 18:6a4db94011d3 | 408 | /** |
sahilmgandhi | 18:6a4db94011d3 | 409 | * \brief Perform command. |
sahilmgandhi | 18:6a4db94011d3 | 410 | * |
sahilmgandhi | 18:6a4db94011d3 | 411 | * \param p_efc Pointer to an EFC instance. |
sahilmgandhi | 18:6a4db94011d3 | 412 | * \param ul_fcr Flash command. |
sahilmgandhi | 18:6a4db94011d3 | 413 | * |
sahilmgandhi | 18:6a4db94011d3 | 414 | * \return The current status. |
sahilmgandhi | 18:6a4db94011d3 | 415 | */ |
sahilmgandhi | 18:6a4db94011d3 | 416 | __no_inline |
sahilmgandhi | 18:6a4db94011d3 | 417 | RAMFUNC |
sahilmgandhi | 18:6a4db94011d3 | 418 | uint32_t efc_perform_fcr(Efc *p_efc, uint32_t ul_fcr) |
sahilmgandhi | 18:6a4db94011d3 | 419 | { |
sahilmgandhi | 18:6a4db94011d3 | 420 | volatile uint32_t ul_status; |
sahilmgandhi | 18:6a4db94011d3 | 421 | |
sahilmgandhi | 18:6a4db94011d3 | 422 | p_efc->EEFC_FCR = ul_fcr; |
sahilmgandhi | 18:6a4db94011d3 | 423 | do { |
sahilmgandhi | 18:6a4db94011d3 | 424 | ul_status = p_efc->EEFC_FSR; |
sahilmgandhi | 18:6a4db94011d3 | 425 | } while ((ul_status & EEFC_FSR_FRDY) != EEFC_FSR_FRDY); |
sahilmgandhi | 18:6a4db94011d3 | 426 | |
sahilmgandhi | 18:6a4db94011d3 | 427 | return (ul_status & EEFC_ERROR_FLAGS); |
sahilmgandhi | 18:6a4db94011d3 | 428 | } |
sahilmgandhi | 18:6a4db94011d3 | 429 | |
sahilmgandhi | 18:6a4db94011d3 | 430 | //@} |
sahilmgandhi | 18:6a4db94011d3 | 431 | |
sahilmgandhi | 18:6a4db94011d3 | 432 | /// @cond 0 |
sahilmgandhi | 18:6a4db94011d3 | 433 | /**INDENT-OFF**/ |
sahilmgandhi | 18:6a4db94011d3 | 434 | #ifdef __cplusplus |
sahilmgandhi | 18:6a4db94011d3 | 435 | } |
sahilmgandhi | 18:6a4db94011d3 | 436 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 437 | /**INDENT-ON**/ |
sahilmgandhi | 18:6a4db94011d3 | 438 | /// @endcond |