Mouse code for the MacroRat
mbed-dev/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/port/port.h@46:b156ef445742, 2017-06-03 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sat Jun 03 00:22:44 2017 +0000
- Revision:
- 46:b156ef445742
- Parent:
- 18:6a4db94011d3
Final code for internal battlebot competition.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /** |
sahilmgandhi | 18:6a4db94011d3 | 2 | * \file |
sahilmgandhi | 18:6a4db94011d3 | 3 | * |
sahilmgandhi | 18:6a4db94011d3 | 4 | * \brief SAM GPIO Port Driver |
sahilmgandhi | 18:6a4db94011d3 | 5 | * |
sahilmgandhi | 18:6a4db94011d3 | 6 | * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. |
sahilmgandhi | 18:6a4db94011d3 | 7 | * |
sahilmgandhi | 18:6a4db94011d3 | 8 | * \asf_license_start |
sahilmgandhi | 18:6a4db94011d3 | 9 | * |
sahilmgandhi | 18:6a4db94011d3 | 10 | * \page License |
sahilmgandhi | 18:6a4db94011d3 | 11 | * |
sahilmgandhi | 18:6a4db94011d3 | 12 | * Redistribution and use in source and binary forms, with or without |
sahilmgandhi | 18:6a4db94011d3 | 13 | * modification, are permitted provided that the following conditions are met: |
sahilmgandhi | 18:6a4db94011d3 | 14 | * |
sahilmgandhi | 18:6a4db94011d3 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 16 | * this list of conditions and the following disclaimer. |
sahilmgandhi | 18:6a4db94011d3 | 17 | * |
sahilmgandhi | 18:6a4db94011d3 | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 19 | * this list of conditions and the following disclaimer in the documentation |
sahilmgandhi | 18:6a4db94011d3 | 20 | * and/or other materials provided with the distribution. |
sahilmgandhi | 18:6a4db94011d3 | 21 | * |
sahilmgandhi | 18:6a4db94011d3 | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
sahilmgandhi | 18:6a4db94011d3 | 23 | * from this software without specific prior written permission. |
sahilmgandhi | 18:6a4db94011d3 | 24 | * |
sahilmgandhi | 18:6a4db94011d3 | 25 | * 4. This software may only be redistributed and used in connection with an |
sahilmgandhi | 18:6a4db94011d3 | 26 | * Atmel microcontroller product. |
sahilmgandhi | 18:6a4db94011d3 | 27 | * |
sahilmgandhi | 18:6a4db94011d3 | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
sahilmgandhi | 18:6a4db94011d3 | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
sahilmgandhi | 18:6a4db94011d3 | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
sahilmgandhi | 18:6a4db94011d3 | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
sahilmgandhi | 18:6a4db94011d3 | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
sahilmgandhi | 18:6a4db94011d3 | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
sahilmgandhi | 18:6a4db94011d3 | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
sahilmgandhi | 18:6a4db94011d3 | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
sahilmgandhi | 18:6a4db94011d3 | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
sahilmgandhi | 18:6a4db94011d3 | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
sahilmgandhi | 18:6a4db94011d3 | 38 | * POSSIBILITY OF SUCH DAMAGE. |
sahilmgandhi | 18:6a4db94011d3 | 39 | * |
sahilmgandhi | 18:6a4db94011d3 | 40 | * \asf_license_stop |
sahilmgandhi | 18:6a4db94011d3 | 41 | * |
sahilmgandhi | 18:6a4db94011d3 | 42 | */ |
sahilmgandhi | 18:6a4db94011d3 | 43 | /* |
sahilmgandhi | 18:6a4db94011d3 | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
sahilmgandhi | 18:6a4db94011d3 | 45 | */ |
sahilmgandhi | 18:6a4db94011d3 | 46 | #ifndef PORT_H_INCLUDED |
sahilmgandhi | 18:6a4db94011d3 | 47 | #define PORT_H_INCLUDED |
sahilmgandhi | 18:6a4db94011d3 | 48 | |
sahilmgandhi | 18:6a4db94011d3 | 49 | /** |
sahilmgandhi | 18:6a4db94011d3 | 50 | * \defgroup asfdoc_sam0_port_group SAM Port Driver (PORT) |
sahilmgandhi | 18:6a4db94011d3 | 51 | * |
sahilmgandhi | 18:6a4db94011d3 | 52 | * This driver for Atmel® | SMART SAM devices provides an interface for the configuration |
sahilmgandhi | 18:6a4db94011d3 | 53 | * and management of the device's General Purpose Input/Output (GPIO) pin |
sahilmgandhi | 18:6a4db94011d3 | 54 | * functionality, for manual pin state reading and writing. |
sahilmgandhi | 18:6a4db94011d3 | 55 | * |
sahilmgandhi | 18:6a4db94011d3 | 56 | * The following peripherals are used by this module: |
sahilmgandhi | 18:6a4db94011d3 | 57 | * - PORT (GPIO Management) |
sahilmgandhi | 18:6a4db94011d3 | 58 | * |
sahilmgandhi | 18:6a4db94011d3 | 59 | * The following devices can use this module: |
sahilmgandhi | 18:6a4db94011d3 | 60 | * - Atmel | SMART SAM D20/D21 |
sahilmgandhi | 18:6a4db94011d3 | 61 | * - Atmel | SMART SAM R21 |
sahilmgandhi | 18:6a4db94011d3 | 62 | * - Atmel | SMART SAM D10/D11 |
sahilmgandhi | 18:6a4db94011d3 | 63 | * - Atmel | SMART SAM L21 |
sahilmgandhi | 18:6a4db94011d3 | 64 | * - Atmel | SMART SAM DAx |
sahilmgandhi | 18:6a4db94011d3 | 65 | * - Atmel | SMART SAM C20/C21 |
sahilmgandhi | 18:6a4db94011d3 | 66 | * |
sahilmgandhi | 18:6a4db94011d3 | 67 | * The outline of this documentation is as follows: |
sahilmgandhi | 18:6a4db94011d3 | 68 | * - \ref asfdoc_sam0_port_prerequisites |
sahilmgandhi | 18:6a4db94011d3 | 69 | * - \ref asfdoc_sam0_port_module_overview |
sahilmgandhi | 18:6a4db94011d3 | 70 | * - \ref asfdoc_sam0_port_special_considerations |
sahilmgandhi | 18:6a4db94011d3 | 71 | * - \ref asfdoc_sam0_port_extra_info |
sahilmgandhi | 18:6a4db94011d3 | 72 | * - \ref asfdoc_sam0_port_examples |
sahilmgandhi | 18:6a4db94011d3 | 73 | * - \ref asfdoc_sam0_port_api_overview |
sahilmgandhi | 18:6a4db94011d3 | 74 | * |
sahilmgandhi | 18:6a4db94011d3 | 75 | * |
sahilmgandhi | 18:6a4db94011d3 | 76 | * \section asfdoc_sam0_port_prerequisites Prerequisites |
sahilmgandhi | 18:6a4db94011d3 | 77 | * |
sahilmgandhi | 18:6a4db94011d3 | 78 | * There are no prerequisites for this module. |
sahilmgandhi | 18:6a4db94011d3 | 79 | * |
sahilmgandhi | 18:6a4db94011d3 | 80 | * |
sahilmgandhi | 18:6a4db94011d3 | 81 | * \section asfdoc_sam0_port_module_overview Module Overview |
sahilmgandhi | 18:6a4db94011d3 | 82 | * |
sahilmgandhi | 18:6a4db94011d3 | 83 | * The device GPIO (PORT) module provides an interface between the user |
sahilmgandhi | 18:6a4db94011d3 | 84 | * application logic and external hardware peripherals, when general pin state |
sahilmgandhi | 18:6a4db94011d3 | 85 | * manipulation is required. This driver provides an easy-to-use interface to |
sahilmgandhi | 18:6a4db94011d3 | 86 | * the physical pin input samplers and output drivers, so that pins can be read |
sahilmgandhi | 18:6a4db94011d3 | 87 | * from or written to for general purpose external hardware control. |
sahilmgandhi | 18:6a4db94011d3 | 88 | * |
sahilmgandhi | 18:6a4db94011d3 | 89 | * \subsection asfdoc_sam0_port_features Driver Feature Macro Definition |
sahilmgandhi | 18:6a4db94011d3 | 90 | * <table> |
sahilmgandhi | 18:6a4db94011d3 | 91 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 92 | * <th>Driver Feature Macro</th> |
sahilmgandhi | 18:6a4db94011d3 | 93 | * <th>Supported devices</th> |
sahilmgandhi | 18:6a4db94011d3 | 94 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 95 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 96 | * <td>FEATURE_PORT_INPUT_EVENT</td> |
sahilmgandhi | 18:6a4db94011d3 | 97 | * <td>SAML21/C20/C21</td> |
sahilmgandhi | 18:6a4db94011d3 | 98 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 99 | * </table> |
sahilmgandhi | 18:6a4db94011d3 | 100 | * \note The specific features are only available in the driver when the |
sahilmgandhi | 18:6a4db94011d3 | 101 | * selected device supports those features. |
sahilmgandhi | 18:6a4db94011d3 | 102 | * |
sahilmgandhi | 18:6a4db94011d3 | 103 | * \subsection asfdoc_sam0_port_module_overview_pin_numbering Physical and Logical GPIO Pins |
sahilmgandhi | 18:6a4db94011d3 | 104 | * SAM devices use two naming conventions for the I/O pins in the device; one |
sahilmgandhi | 18:6a4db94011d3 | 105 | * physical and one logical. Each physical pin on a device package is assigned |
sahilmgandhi | 18:6a4db94011d3 | 106 | * both a physical port and pin identifier (e.g. "PORTA.0") as well as a |
sahilmgandhi | 18:6a4db94011d3 | 107 | * monotonically incrementing logical GPIO number (e.g. "GPIO0"). While the |
sahilmgandhi | 18:6a4db94011d3 | 108 | * former is used to map physical pins to their physical internal device module |
sahilmgandhi | 18:6a4db94011d3 | 109 | * counterparts, for simplicity the design of this driver uses the logical GPIO |
sahilmgandhi | 18:6a4db94011d3 | 110 | * numbers instead. |
sahilmgandhi | 18:6a4db94011d3 | 111 | * |
sahilmgandhi | 18:6a4db94011d3 | 112 | * \subsection asfdoc_sam0_port_module_overview_physical Physical Connection |
sahilmgandhi | 18:6a4db94011d3 | 113 | * |
sahilmgandhi | 18:6a4db94011d3 | 114 | * \ref asfdoc_sam0_port_module_int_connections "The diagram below" shows how |
sahilmgandhi | 18:6a4db94011d3 | 115 | * this module is interconnected within the device. |
sahilmgandhi | 18:6a4db94011d3 | 116 | * |
sahilmgandhi | 18:6a4db94011d3 | 117 | * \anchor asfdoc_sam0_port_module_int_connections |
sahilmgandhi | 18:6a4db94011d3 | 118 | * \dot |
sahilmgandhi | 18:6a4db94011d3 | 119 | * digraph overview { |
sahilmgandhi | 18:6a4db94011d3 | 120 | * node [label="Port Pad" shape=square] pad; |
sahilmgandhi | 18:6a4db94011d3 | 121 | * |
sahilmgandhi | 18:6a4db94011d3 | 122 | * subgraph driver { |
sahilmgandhi | 18:6a4db94011d3 | 123 | * node [label="Peripheral MUX" shape=trapezium] pinmux; |
sahilmgandhi | 18:6a4db94011d3 | 124 | * node [label="GPIO Module" shape=ellipse] gpio; |
sahilmgandhi | 18:6a4db94011d3 | 125 | * node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals; |
sahilmgandhi | 18:6a4db94011d3 | 126 | * } |
sahilmgandhi | 18:6a4db94011d3 | 127 | * |
sahilmgandhi | 18:6a4db94011d3 | 128 | * pinmux -> gpio; |
sahilmgandhi | 18:6a4db94011d3 | 129 | * pad -> pinmux; |
sahilmgandhi | 18:6a4db94011d3 | 130 | * pinmux -> peripherals; |
sahilmgandhi | 18:6a4db94011d3 | 131 | * } |
sahilmgandhi | 18:6a4db94011d3 | 132 | * \enddot |
sahilmgandhi | 18:6a4db94011d3 | 133 | * |
sahilmgandhi | 18:6a4db94011d3 | 134 | * |
sahilmgandhi | 18:6a4db94011d3 | 135 | * \section asfdoc_sam0_port_special_considerations Special Considerations |
sahilmgandhi | 18:6a4db94011d3 | 136 | * |
sahilmgandhi | 18:6a4db94011d3 | 137 | * The SAM port pin input sampler can be disabled when the pin is configured |
sahilmgandhi | 18:6a4db94011d3 | 138 | * in pure output mode to save power; reading the pin state of a pin configured |
sahilmgandhi | 18:6a4db94011d3 | 139 | * in output-only mode will read the logical output state that was last set. |
sahilmgandhi | 18:6a4db94011d3 | 140 | * |
sahilmgandhi | 18:6a4db94011d3 | 141 | * \section asfdoc_sam0_port_extra_info Extra Information |
sahilmgandhi | 18:6a4db94011d3 | 142 | * |
sahilmgandhi | 18:6a4db94011d3 | 143 | * For extra information, see \ref asfdoc_sam0_port_extra. This includes: |
sahilmgandhi | 18:6a4db94011d3 | 144 | * - \ref asfdoc_sam0_port_extra_acronyms |
sahilmgandhi | 18:6a4db94011d3 | 145 | * - \ref asfdoc_sam0_port_extra_dependencies |
sahilmgandhi | 18:6a4db94011d3 | 146 | * - \ref asfdoc_sam0_port_extra_errata |
sahilmgandhi | 18:6a4db94011d3 | 147 | * - \ref asfdoc_sam0_port_extra_history |
sahilmgandhi | 18:6a4db94011d3 | 148 | * |
sahilmgandhi | 18:6a4db94011d3 | 149 | * |
sahilmgandhi | 18:6a4db94011d3 | 150 | * \section asfdoc_sam0_port_examples Examples |
sahilmgandhi | 18:6a4db94011d3 | 151 | * |
sahilmgandhi | 18:6a4db94011d3 | 152 | * For a list of examples related to this driver, see |
sahilmgandhi | 18:6a4db94011d3 | 153 | * \ref asfdoc_sam0_port_exqsg. |
sahilmgandhi | 18:6a4db94011d3 | 154 | * |
sahilmgandhi | 18:6a4db94011d3 | 155 | * |
sahilmgandhi | 18:6a4db94011d3 | 156 | * \section asfdoc_sam0_port_api_overview API Overview |
sahilmgandhi | 18:6a4db94011d3 | 157 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 158 | */ |
sahilmgandhi | 18:6a4db94011d3 | 159 | |
sahilmgandhi | 18:6a4db94011d3 | 160 | #include <compiler.h> |
sahilmgandhi | 18:6a4db94011d3 | 161 | #include <pinmux.h> |
sahilmgandhi | 18:6a4db94011d3 | 162 | |
sahilmgandhi | 18:6a4db94011d3 | 163 | #ifdef __cplusplus |
sahilmgandhi | 18:6a4db94011d3 | 164 | extern "C" { |
sahilmgandhi | 18:6a4db94011d3 | 165 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 166 | |
sahilmgandhi | 18:6a4db94011d3 | 167 | /** |
sahilmgandhi | 18:6a4db94011d3 | 168 | * \name Driver Feature Definition |
sahilmgandhi | 18:6a4db94011d3 | 169 | * Define port features set according to different device family. |
sahilmgandhi | 18:6a4db94011d3 | 170 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 171 | */ |
sahilmgandhi | 18:6a4db94011d3 | 172 | #if (SAML21) || (SAMC20) || (SAMC21) || defined(__DOXYGEN__) |
sahilmgandhi | 18:6a4db94011d3 | 173 | /** Event input control feature support for PORT group. */ |
sahilmgandhi | 18:6a4db94011d3 | 174 | # define FEATURE_PORT_INPUT_EVENT |
sahilmgandhi | 18:6a4db94011d3 | 175 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 176 | /*@}*/ |
sahilmgandhi | 18:6a4db94011d3 | 177 | |
sahilmgandhi | 18:6a4db94011d3 | 178 | /** \name PORT Alias Macros |
sahilmgandhi | 18:6a4db94011d3 | 179 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 180 | */ |
sahilmgandhi | 18:6a4db94011d3 | 181 | |
sahilmgandhi | 18:6a4db94011d3 | 182 | /** Convenience definition for GPIO module group A on the device (if |
sahilmgandhi | 18:6a4db94011d3 | 183 | * available). */ |
sahilmgandhi | 18:6a4db94011d3 | 184 | #if (PORT_GROUPS > 0) || defined(__DOXYGEN__) |
sahilmgandhi | 18:6a4db94011d3 | 185 | # define PORTA PORT->Group[0] |
sahilmgandhi | 18:6a4db94011d3 | 186 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 187 | |
sahilmgandhi | 18:6a4db94011d3 | 188 | #if (PORT_GROUPS > 1) || defined(__DOXYGEN__) |
sahilmgandhi | 18:6a4db94011d3 | 189 | /** Convenience definition for GPIO module group B on the device (if |
sahilmgandhi | 18:6a4db94011d3 | 190 | * available). */ |
sahilmgandhi | 18:6a4db94011d3 | 191 | # define PORTB PORT->Group[1] |
sahilmgandhi | 18:6a4db94011d3 | 192 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 193 | |
sahilmgandhi | 18:6a4db94011d3 | 194 | #if (PORT_GROUPS > 2) || defined(__DOXYGEN__) |
sahilmgandhi | 18:6a4db94011d3 | 195 | /** Convenience definition for GPIO module group C on the device (if |
sahilmgandhi | 18:6a4db94011d3 | 196 | * available). */ |
sahilmgandhi | 18:6a4db94011d3 | 197 | # define PORTC PORT->Group[2] |
sahilmgandhi | 18:6a4db94011d3 | 198 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 199 | |
sahilmgandhi | 18:6a4db94011d3 | 200 | #if (PORT_GROUPS > 3) || defined(__DOXYGEN__) |
sahilmgandhi | 18:6a4db94011d3 | 201 | /** Convenience definition for GPIO module group D on the device (if |
sahilmgandhi | 18:6a4db94011d3 | 202 | * available). */ |
sahilmgandhi | 18:6a4db94011d3 | 203 | # define PORTD PORT->Group[3] |
sahilmgandhi | 18:6a4db94011d3 | 204 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 205 | |
sahilmgandhi | 18:6a4db94011d3 | 206 | /** @} */ |
sahilmgandhi | 18:6a4db94011d3 | 207 | |
sahilmgandhi | 18:6a4db94011d3 | 208 | /** |
sahilmgandhi | 18:6a4db94011d3 | 209 | * \brief Port pin direction configuration enum. |
sahilmgandhi | 18:6a4db94011d3 | 210 | * |
sahilmgandhi | 18:6a4db94011d3 | 211 | * Enum for the possible pin direction settings of the port pin configuration |
sahilmgandhi | 18:6a4db94011d3 | 212 | * structure, to indicate the direction the pin should use. |
sahilmgandhi | 18:6a4db94011d3 | 213 | */ |
sahilmgandhi | 18:6a4db94011d3 | 214 | enum port_pin_dir { |
sahilmgandhi | 18:6a4db94011d3 | 215 | /** The pin's input buffer should be enabled, so that the pin state can |
sahilmgandhi | 18:6a4db94011d3 | 216 | * be read. */ |
sahilmgandhi | 18:6a4db94011d3 | 217 | PORT_PIN_DIR_INPUT = SYSTEM_PINMUX_PIN_DIR_INPUT, |
sahilmgandhi | 18:6a4db94011d3 | 218 | /** The pin's output buffer should be enabled, so that the pin state can |
sahilmgandhi | 18:6a4db94011d3 | 219 | * be set. */ |
sahilmgandhi | 18:6a4db94011d3 | 220 | PORT_PIN_DIR_OUTPUT = SYSTEM_PINMUX_PIN_DIR_OUTPUT, |
sahilmgandhi | 18:6a4db94011d3 | 221 | /** The pin's output and input buffers should be enabled, so that the pin |
sahilmgandhi | 18:6a4db94011d3 | 222 | * state can be set and read back. */ |
sahilmgandhi | 18:6a4db94011d3 | 223 | PORT_PIN_DIR_OUTPUT_WTH_READBACK = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK, |
sahilmgandhi | 18:6a4db94011d3 | 224 | }; |
sahilmgandhi | 18:6a4db94011d3 | 225 | |
sahilmgandhi | 18:6a4db94011d3 | 226 | /** |
sahilmgandhi | 18:6a4db94011d3 | 227 | * \brief Port pin input pull configuration enum. |
sahilmgandhi | 18:6a4db94011d3 | 228 | * |
sahilmgandhi | 18:6a4db94011d3 | 229 | * Enum for the possible pin pull settings of the port pin configuration |
sahilmgandhi | 18:6a4db94011d3 | 230 | * structure, to indicate the type of logic level pull the pin should use. |
sahilmgandhi | 18:6a4db94011d3 | 231 | */ |
sahilmgandhi | 18:6a4db94011d3 | 232 | enum port_pin_pull { |
sahilmgandhi | 18:6a4db94011d3 | 233 | /** No logical pull should be applied to the pin. */ |
sahilmgandhi | 18:6a4db94011d3 | 234 | PORT_PIN_PULL_NONE = SYSTEM_PINMUX_PIN_PULL_NONE, |
sahilmgandhi | 18:6a4db94011d3 | 235 | /** Pin should be pulled up when idle. */ |
sahilmgandhi | 18:6a4db94011d3 | 236 | PORT_PIN_PULL_UP = SYSTEM_PINMUX_PIN_PULL_UP, |
sahilmgandhi | 18:6a4db94011d3 | 237 | /** Pin should be pulled down when idle. */ |
sahilmgandhi | 18:6a4db94011d3 | 238 | PORT_PIN_PULL_DOWN = SYSTEM_PINMUX_PIN_PULL_DOWN, |
sahilmgandhi | 18:6a4db94011d3 | 239 | }; |
sahilmgandhi | 18:6a4db94011d3 | 240 | |
sahilmgandhi | 18:6a4db94011d3 | 241 | #ifdef FEATURE_PORT_INPUT_EVENT |
sahilmgandhi | 18:6a4db94011d3 | 242 | /** |
sahilmgandhi | 18:6a4db94011d3 | 243 | * \brief Port input event action. |
sahilmgandhi | 18:6a4db94011d3 | 244 | * |
sahilmgandhi | 18:6a4db94011d3 | 245 | * List of port input events action on pin. |
sahilmgandhi | 18:6a4db94011d3 | 246 | */ |
sahilmgandhi | 18:6a4db94011d3 | 247 | enum port_input_event_action { |
sahilmgandhi | 18:6a4db94011d3 | 248 | /** Event out to pin. */ |
sahilmgandhi | 18:6a4db94011d3 | 249 | PORT_INPUT_EVENT_ACTION_OUT = 0, |
sahilmgandhi | 18:6a4db94011d3 | 250 | /** Set output register of pin on event. */ |
sahilmgandhi | 18:6a4db94011d3 | 251 | PORT_INPUT_EVENT_ACTION_SET, |
sahilmgandhi | 18:6a4db94011d3 | 252 | /** Clear output register pin on event. */ |
sahilmgandhi | 18:6a4db94011d3 | 253 | PORT_INPUT_EVENT_ACTION_CLR, |
sahilmgandhi | 18:6a4db94011d3 | 254 | /** Toggle output register pin on event. */ |
sahilmgandhi | 18:6a4db94011d3 | 255 | PORT_INPUT_EVENT_ACTION_TGL, |
sahilmgandhi | 18:6a4db94011d3 | 256 | }; |
sahilmgandhi | 18:6a4db94011d3 | 257 | |
sahilmgandhi | 18:6a4db94011d3 | 258 | /** |
sahilmgandhi | 18:6a4db94011d3 | 259 | * \brief Port input event. |
sahilmgandhi | 18:6a4db94011d3 | 260 | * |
sahilmgandhi | 18:6a4db94011d3 | 261 | * List of port input events. |
sahilmgandhi | 18:6a4db94011d3 | 262 | */ |
sahilmgandhi | 18:6a4db94011d3 | 263 | enum port_input_event { |
sahilmgandhi | 18:6a4db94011d3 | 264 | /** Port input event 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 265 | PORT_INPUT_EVENT_0 = 0, |
sahilmgandhi | 18:6a4db94011d3 | 266 | /** Port input event 1. */ |
sahilmgandhi | 18:6a4db94011d3 | 267 | PORT_INPUT_EVENT_1 = 1, |
sahilmgandhi | 18:6a4db94011d3 | 268 | /** Port input event 2. */ |
sahilmgandhi | 18:6a4db94011d3 | 269 | PORT_INPUT_EVENT_2 = 2, |
sahilmgandhi | 18:6a4db94011d3 | 270 | /** Port input event 3. */ |
sahilmgandhi | 18:6a4db94011d3 | 271 | PORT_INPUT_EVENT_3 = 3, |
sahilmgandhi | 18:6a4db94011d3 | 272 | }; |
sahilmgandhi | 18:6a4db94011d3 | 273 | |
sahilmgandhi | 18:6a4db94011d3 | 274 | /** |
sahilmgandhi | 18:6a4db94011d3 | 275 | * \brief Port input event configuration structure. |
sahilmgandhi | 18:6a4db94011d3 | 276 | * |
sahilmgandhi | 18:6a4db94011d3 | 277 | * Configuration structure for a port input event. |
sahilmgandhi | 18:6a4db94011d3 | 278 | */ |
sahilmgandhi | 18:6a4db94011d3 | 279 | struct port_input_event_config { |
sahilmgandhi | 18:6a4db94011d3 | 280 | /** Port input event action. */ |
sahilmgandhi | 18:6a4db94011d3 | 281 | enum port_input_event_action action; |
sahilmgandhi | 18:6a4db94011d3 | 282 | /** GPIO pin. */ |
sahilmgandhi | 18:6a4db94011d3 | 283 | uint8_t gpio_pin; |
sahilmgandhi | 18:6a4db94011d3 | 284 | }; |
sahilmgandhi | 18:6a4db94011d3 | 285 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 286 | |
sahilmgandhi | 18:6a4db94011d3 | 287 | /** |
sahilmgandhi | 18:6a4db94011d3 | 288 | * \brief Port pin configuration structure. |
sahilmgandhi | 18:6a4db94011d3 | 289 | * |
sahilmgandhi | 18:6a4db94011d3 | 290 | * Configuration structure for a port pin instance. This structure should be |
sahilmgandhi | 18:6a4db94011d3 | 291 | * initialized by the \ref port_get_config_defaults() function before being |
sahilmgandhi | 18:6a4db94011d3 | 292 | * modified by the user application. |
sahilmgandhi | 18:6a4db94011d3 | 293 | */ |
sahilmgandhi | 18:6a4db94011d3 | 294 | struct port_config { |
sahilmgandhi | 18:6a4db94011d3 | 295 | /** Port buffer input/output direction. */ |
sahilmgandhi | 18:6a4db94011d3 | 296 | enum port_pin_dir direction; |
sahilmgandhi | 18:6a4db94011d3 | 297 | |
sahilmgandhi | 18:6a4db94011d3 | 298 | /** Port pull-up/pull-down for input pins. */ |
sahilmgandhi | 18:6a4db94011d3 | 299 | enum port_pin_pull input_pull; |
sahilmgandhi | 18:6a4db94011d3 | 300 | |
sahilmgandhi | 18:6a4db94011d3 | 301 | /** Enable lowest possible powerstate on the pin. |
sahilmgandhi | 18:6a4db94011d3 | 302 | * |
sahilmgandhi | 18:6a4db94011d3 | 303 | * \note All other configurations will be ignored, the pin will be disabled. |
sahilmgandhi | 18:6a4db94011d3 | 304 | */ |
sahilmgandhi | 18:6a4db94011d3 | 305 | bool powersave; |
sahilmgandhi | 18:6a4db94011d3 | 306 | }; |
sahilmgandhi | 18:6a4db94011d3 | 307 | |
sahilmgandhi | 18:6a4db94011d3 | 308 | /** \name State Reading/Writing (Physical Group Orientated) |
sahilmgandhi | 18:6a4db94011d3 | 309 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 310 | */ |
sahilmgandhi | 18:6a4db94011d3 | 311 | |
sahilmgandhi | 18:6a4db94011d3 | 312 | /** |
sahilmgandhi | 18:6a4db94011d3 | 313 | * \brief Retrieves the PORT module group instance from a given GPIO pin number. |
sahilmgandhi | 18:6a4db94011d3 | 314 | * |
sahilmgandhi | 18:6a4db94011d3 | 315 | * Retrieves the PORT module group instance associated with a given logical |
sahilmgandhi | 18:6a4db94011d3 | 316 | * GPIO pin number. |
sahilmgandhi | 18:6a4db94011d3 | 317 | * |
sahilmgandhi | 18:6a4db94011d3 | 318 | * \param[in] gpio_pin Index of the GPIO pin to convert |
sahilmgandhi | 18:6a4db94011d3 | 319 | * |
sahilmgandhi | 18:6a4db94011d3 | 320 | * \return Base address of the associated PORT module. |
sahilmgandhi | 18:6a4db94011d3 | 321 | */ |
sahilmgandhi | 18:6a4db94011d3 | 322 | static inline PortGroup* port_get_group_from_gpio_pin( |
sahilmgandhi | 18:6a4db94011d3 | 323 | const uint8_t gpio_pin) |
sahilmgandhi | 18:6a4db94011d3 | 324 | { |
sahilmgandhi | 18:6a4db94011d3 | 325 | return system_pinmux_get_group_from_gpio_pin(gpio_pin); |
sahilmgandhi | 18:6a4db94011d3 | 326 | } |
sahilmgandhi | 18:6a4db94011d3 | 327 | |
sahilmgandhi | 18:6a4db94011d3 | 328 | /** |
sahilmgandhi | 18:6a4db94011d3 | 329 | * \brief Retrieves the state of a group of port pins that are configured as inputs. |
sahilmgandhi | 18:6a4db94011d3 | 330 | * |
sahilmgandhi | 18:6a4db94011d3 | 331 | * Reads the current logic level of a port module's pins and returns the |
sahilmgandhi | 18:6a4db94011d3 | 332 | * current levels as a bitmask. |
sahilmgandhi | 18:6a4db94011d3 | 333 | * |
sahilmgandhi | 18:6a4db94011d3 | 334 | * \param[in] port Base of the PORT module to read from |
sahilmgandhi | 18:6a4db94011d3 | 335 | * \param[in] mask Mask of the port pin(s) to read |
sahilmgandhi | 18:6a4db94011d3 | 336 | * |
sahilmgandhi | 18:6a4db94011d3 | 337 | * \return Status of the port pin(s) input buffers. |
sahilmgandhi | 18:6a4db94011d3 | 338 | */ |
sahilmgandhi | 18:6a4db94011d3 | 339 | static inline uint32_t port_group_get_input_level( |
sahilmgandhi | 18:6a4db94011d3 | 340 | const PortGroup *const port, |
sahilmgandhi | 18:6a4db94011d3 | 341 | const uint32_t mask) |
sahilmgandhi | 18:6a4db94011d3 | 342 | { |
sahilmgandhi | 18:6a4db94011d3 | 343 | /* Sanity check arguments */ |
sahilmgandhi | 18:6a4db94011d3 | 344 | Assert(port); |
sahilmgandhi | 18:6a4db94011d3 | 345 | |
sahilmgandhi | 18:6a4db94011d3 | 346 | return (port->IN.reg & mask); |
sahilmgandhi | 18:6a4db94011d3 | 347 | } |
sahilmgandhi | 18:6a4db94011d3 | 348 | |
sahilmgandhi | 18:6a4db94011d3 | 349 | /** |
sahilmgandhi | 18:6a4db94011d3 | 350 | * \brief Retrieves the state of a group of port pins that are configured as outputs. |
sahilmgandhi | 18:6a4db94011d3 | 351 | * |
sahilmgandhi | 18:6a4db94011d3 | 352 | * Reads the current logical output level of a port module's pins and returns |
sahilmgandhi | 18:6a4db94011d3 | 353 | * the current levels as a bitmask. |
sahilmgandhi | 18:6a4db94011d3 | 354 | * |
sahilmgandhi | 18:6a4db94011d3 | 355 | * \param[in] port Base of the PORT module to read from |
sahilmgandhi | 18:6a4db94011d3 | 356 | * \param[in] mask Mask of the port pin(s) to read |
sahilmgandhi | 18:6a4db94011d3 | 357 | * |
sahilmgandhi | 18:6a4db94011d3 | 358 | * \return Status of the port pin(s) output buffers. |
sahilmgandhi | 18:6a4db94011d3 | 359 | */ |
sahilmgandhi | 18:6a4db94011d3 | 360 | static inline uint32_t port_group_get_output_level( |
sahilmgandhi | 18:6a4db94011d3 | 361 | const PortGroup *const port, |
sahilmgandhi | 18:6a4db94011d3 | 362 | const uint32_t mask) |
sahilmgandhi | 18:6a4db94011d3 | 363 | { |
sahilmgandhi | 18:6a4db94011d3 | 364 | /* Sanity check arguments */ |
sahilmgandhi | 18:6a4db94011d3 | 365 | Assert(port); |
sahilmgandhi | 18:6a4db94011d3 | 366 | |
sahilmgandhi | 18:6a4db94011d3 | 367 | return (port->OUT.reg & mask); |
sahilmgandhi | 18:6a4db94011d3 | 368 | } |
sahilmgandhi | 18:6a4db94011d3 | 369 | |
sahilmgandhi | 18:6a4db94011d3 | 370 | /** |
sahilmgandhi | 18:6a4db94011d3 | 371 | * \brief Sets the state of a group of port pins that are configured as outputs. |
sahilmgandhi | 18:6a4db94011d3 | 372 | * |
sahilmgandhi | 18:6a4db94011d3 | 373 | * Sets the current output level of a port module's pins to a given logic |
sahilmgandhi | 18:6a4db94011d3 | 374 | * level. |
sahilmgandhi | 18:6a4db94011d3 | 375 | * |
sahilmgandhi | 18:6a4db94011d3 | 376 | * \param[out] port Base of the PORT module to write to |
sahilmgandhi | 18:6a4db94011d3 | 377 | * \param[in] mask Mask of the port pin(s) to change |
sahilmgandhi | 18:6a4db94011d3 | 378 | * \param[in] level_mask Mask of the port level(s) to set |
sahilmgandhi | 18:6a4db94011d3 | 379 | */ |
sahilmgandhi | 18:6a4db94011d3 | 380 | static inline void port_group_set_output_level( |
sahilmgandhi | 18:6a4db94011d3 | 381 | PortGroup *const port, |
sahilmgandhi | 18:6a4db94011d3 | 382 | const uint32_t mask, |
sahilmgandhi | 18:6a4db94011d3 | 383 | const uint32_t level_mask) |
sahilmgandhi | 18:6a4db94011d3 | 384 | { |
sahilmgandhi | 18:6a4db94011d3 | 385 | /* Sanity check arguments */ |
sahilmgandhi | 18:6a4db94011d3 | 386 | Assert(port); |
sahilmgandhi | 18:6a4db94011d3 | 387 | |
sahilmgandhi | 18:6a4db94011d3 | 388 | port->OUTSET.reg = (mask & level_mask); |
sahilmgandhi | 18:6a4db94011d3 | 389 | port->OUTCLR.reg = (mask & ~level_mask); |
sahilmgandhi | 18:6a4db94011d3 | 390 | } |
sahilmgandhi | 18:6a4db94011d3 | 391 | |
sahilmgandhi | 18:6a4db94011d3 | 392 | /** |
sahilmgandhi | 18:6a4db94011d3 | 393 | * \brief Toggles the state of a group of port pins that are configured as an outputs. |
sahilmgandhi | 18:6a4db94011d3 | 394 | * |
sahilmgandhi | 18:6a4db94011d3 | 395 | * Toggles the current output levels of a port module's pins. |
sahilmgandhi | 18:6a4db94011d3 | 396 | * |
sahilmgandhi | 18:6a4db94011d3 | 397 | * \param[out] port Base of the PORT module to write to |
sahilmgandhi | 18:6a4db94011d3 | 398 | * \param[in] mask Mask of the port pin(s) to toggle |
sahilmgandhi | 18:6a4db94011d3 | 399 | */ |
sahilmgandhi | 18:6a4db94011d3 | 400 | static inline void port_group_toggle_output_level( |
sahilmgandhi | 18:6a4db94011d3 | 401 | PortGroup *const port, |
sahilmgandhi | 18:6a4db94011d3 | 402 | const uint32_t mask) |
sahilmgandhi | 18:6a4db94011d3 | 403 | { |
sahilmgandhi | 18:6a4db94011d3 | 404 | /* Sanity check arguments */ |
sahilmgandhi | 18:6a4db94011d3 | 405 | Assert(port); |
sahilmgandhi | 18:6a4db94011d3 | 406 | |
sahilmgandhi | 18:6a4db94011d3 | 407 | port->OUTTGL.reg = mask; |
sahilmgandhi | 18:6a4db94011d3 | 408 | } |
sahilmgandhi | 18:6a4db94011d3 | 409 | |
sahilmgandhi | 18:6a4db94011d3 | 410 | /** @} */ |
sahilmgandhi | 18:6a4db94011d3 | 411 | |
sahilmgandhi | 18:6a4db94011d3 | 412 | /** \name Configuration and Initialization |
sahilmgandhi | 18:6a4db94011d3 | 413 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 414 | */ |
sahilmgandhi | 18:6a4db94011d3 | 415 | |
sahilmgandhi | 18:6a4db94011d3 | 416 | /** |
sahilmgandhi | 18:6a4db94011d3 | 417 | * \brief Initializes a Port pin/group configuration structure to defaults. |
sahilmgandhi | 18:6a4db94011d3 | 418 | * |
sahilmgandhi | 18:6a4db94011d3 | 419 | * Initializes a given Port pin/group configuration structure to a set of |
sahilmgandhi | 18:6a4db94011d3 | 420 | * known default values. This function should be called on all new |
sahilmgandhi | 18:6a4db94011d3 | 421 | * instances of these configuration structures before being modified by the |
sahilmgandhi | 18:6a4db94011d3 | 422 | * user application. |
sahilmgandhi | 18:6a4db94011d3 | 423 | * |
sahilmgandhi | 18:6a4db94011d3 | 424 | * The default configuration is as follows: |
sahilmgandhi | 18:6a4db94011d3 | 425 | * \li Input mode with internal pullup enabled |
sahilmgandhi | 18:6a4db94011d3 | 426 | * |
sahilmgandhi | 18:6a4db94011d3 | 427 | * \param[out] config Configuration structure to initialize to default values |
sahilmgandhi | 18:6a4db94011d3 | 428 | */ |
sahilmgandhi | 18:6a4db94011d3 | 429 | static inline void port_get_config_defaults( |
sahilmgandhi | 18:6a4db94011d3 | 430 | struct port_config *const config) |
sahilmgandhi | 18:6a4db94011d3 | 431 | { |
sahilmgandhi | 18:6a4db94011d3 | 432 | /* Sanity check arguments */ |
sahilmgandhi | 18:6a4db94011d3 | 433 | Assert(config); |
sahilmgandhi | 18:6a4db94011d3 | 434 | |
sahilmgandhi | 18:6a4db94011d3 | 435 | /* Default configuration values */ |
sahilmgandhi | 18:6a4db94011d3 | 436 | config->direction = PORT_PIN_DIR_INPUT; |
sahilmgandhi | 18:6a4db94011d3 | 437 | config->input_pull = PORT_PIN_PULL_UP; |
sahilmgandhi | 18:6a4db94011d3 | 438 | config->powersave = false; |
sahilmgandhi | 18:6a4db94011d3 | 439 | } |
sahilmgandhi | 18:6a4db94011d3 | 440 | |
sahilmgandhi | 18:6a4db94011d3 | 441 | void port_pin_set_config( |
sahilmgandhi | 18:6a4db94011d3 | 442 | const uint8_t gpio_pin, |
sahilmgandhi | 18:6a4db94011d3 | 443 | const struct port_config *const config); |
sahilmgandhi | 18:6a4db94011d3 | 444 | |
sahilmgandhi | 18:6a4db94011d3 | 445 | void port_group_set_config( |
sahilmgandhi | 18:6a4db94011d3 | 446 | PortGroup *const port, |
sahilmgandhi | 18:6a4db94011d3 | 447 | const uint32_t mask, |
sahilmgandhi | 18:6a4db94011d3 | 448 | const struct port_config *const config); |
sahilmgandhi | 18:6a4db94011d3 | 449 | |
sahilmgandhi | 18:6a4db94011d3 | 450 | /** @} */ |
sahilmgandhi | 18:6a4db94011d3 | 451 | |
sahilmgandhi | 18:6a4db94011d3 | 452 | /** \name State Reading/Writing (Logical Pin Orientated) |
sahilmgandhi | 18:6a4db94011d3 | 453 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 454 | */ |
sahilmgandhi | 18:6a4db94011d3 | 455 | |
sahilmgandhi | 18:6a4db94011d3 | 456 | /** |
sahilmgandhi | 18:6a4db94011d3 | 457 | * \brief Retrieves the state of a port pin that is configured as an input. |
sahilmgandhi | 18:6a4db94011d3 | 458 | * |
sahilmgandhi | 18:6a4db94011d3 | 459 | * Reads the current logic level of a port pin and returns the current |
sahilmgandhi | 18:6a4db94011d3 | 460 | * level as a Boolean value. |
sahilmgandhi | 18:6a4db94011d3 | 461 | * |
sahilmgandhi | 18:6a4db94011d3 | 462 | * \param[in] gpio_pin Index of the GPIO pin to read |
sahilmgandhi | 18:6a4db94011d3 | 463 | * |
sahilmgandhi | 18:6a4db94011d3 | 464 | * \return Status of the port pin's input buffer. |
sahilmgandhi | 18:6a4db94011d3 | 465 | */ |
sahilmgandhi | 18:6a4db94011d3 | 466 | static inline bool port_pin_get_input_level( |
sahilmgandhi | 18:6a4db94011d3 | 467 | const uint8_t gpio_pin) |
sahilmgandhi | 18:6a4db94011d3 | 468 | { |
sahilmgandhi | 18:6a4db94011d3 | 469 | PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); |
sahilmgandhi | 18:6a4db94011d3 | 470 | uint32_t pin_mask = (1UL << (gpio_pin % 32)); |
sahilmgandhi | 18:6a4db94011d3 | 471 | |
sahilmgandhi | 18:6a4db94011d3 | 472 | return (port_base->IN.reg & pin_mask); |
sahilmgandhi | 18:6a4db94011d3 | 473 | } |
sahilmgandhi | 18:6a4db94011d3 | 474 | |
sahilmgandhi | 18:6a4db94011d3 | 475 | /** |
sahilmgandhi | 18:6a4db94011d3 | 476 | * \brief Retrieves the state of a port pin that is configured as an output. |
sahilmgandhi | 18:6a4db94011d3 | 477 | * |
sahilmgandhi | 18:6a4db94011d3 | 478 | * Reads the current logical output level of a port pin and returns the current |
sahilmgandhi | 18:6a4db94011d3 | 479 | * level as a Boolean value. |
sahilmgandhi | 18:6a4db94011d3 | 480 | * |
sahilmgandhi | 18:6a4db94011d3 | 481 | * \param[in] gpio_pin Index of the GPIO pin to read |
sahilmgandhi | 18:6a4db94011d3 | 482 | * |
sahilmgandhi | 18:6a4db94011d3 | 483 | * \return Status of the port pin's output buffer. |
sahilmgandhi | 18:6a4db94011d3 | 484 | */ |
sahilmgandhi | 18:6a4db94011d3 | 485 | static inline bool port_pin_get_output_level( |
sahilmgandhi | 18:6a4db94011d3 | 486 | const uint8_t gpio_pin) |
sahilmgandhi | 18:6a4db94011d3 | 487 | { |
sahilmgandhi | 18:6a4db94011d3 | 488 | PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); |
sahilmgandhi | 18:6a4db94011d3 | 489 | uint32_t pin_mask = (1UL << (gpio_pin % 32)); |
sahilmgandhi | 18:6a4db94011d3 | 490 | |
sahilmgandhi | 18:6a4db94011d3 | 491 | return (port_base->OUT.reg & pin_mask); |
sahilmgandhi | 18:6a4db94011d3 | 492 | } |
sahilmgandhi | 18:6a4db94011d3 | 493 | |
sahilmgandhi | 18:6a4db94011d3 | 494 | /** |
sahilmgandhi | 18:6a4db94011d3 | 495 | * \brief Sets the state of a port pin that is configured as an output. |
sahilmgandhi | 18:6a4db94011d3 | 496 | * |
sahilmgandhi | 18:6a4db94011d3 | 497 | * Sets the current output level of a port pin to a given logic level. |
sahilmgandhi | 18:6a4db94011d3 | 498 | * |
sahilmgandhi | 18:6a4db94011d3 | 499 | * \param[in] gpio_pin Index of the GPIO pin to write to |
sahilmgandhi | 18:6a4db94011d3 | 500 | * \param[in] level Logical level to set the given pin to |
sahilmgandhi | 18:6a4db94011d3 | 501 | */ |
sahilmgandhi | 18:6a4db94011d3 | 502 | static inline void port_pin_set_output_level( |
sahilmgandhi | 18:6a4db94011d3 | 503 | const uint8_t gpio_pin, |
sahilmgandhi | 18:6a4db94011d3 | 504 | const bool level) |
sahilmgandhi | 18:6a4db94011d3 | 505 | { |
sahilmgandhi | 18:6a4db94011d3 | 506 | PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); |
sahilmgandhi | 18:6a4db94011d3 | 507 | uint32_t pin_mask = (1UL << (gpio_pin % 32)); |
sahilmgandhi | 18:6a4db94011d3 | 508 | |
sahilmgandhi | 18:6a4db94011d3 | 509 | /* Set the pin to high or low atomically based on the requested level */ |
sahilmgandhi | 18:6a4db94011d3 | 510 | if (level) { |
sahilmgandhi | 18:6a4db94011d3 | 511 | port_base->OUTSET.reg = pin_mask; |
sahilmgandhi | 18:6a4db94011d3 | 512 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 513 | port_base->OUTCLR.reg = pin_mask; |
sahilmgandhi | 18:6a4db94011d3 | 514 | } |
sahilmgandhi | 18:6a4db94011d3 | 515 | } |
sahilmgandhi | 18:6a4db94011d3 | 516 | |
sahilmgandhi | 18:6a4db94011d3 | 517 | /** |
sahilmgandhi | 18:6a4db94011d3 | 518 | * \brief Toggles the state of a port pin that is configured as an output. |
sahilmgandhi | 18:6a4db94011d3 | 519 | * |
sahilmgandhi | 18:6a4db94011d3 | 520 | * Toggles the current output level of a port pin. |
sahilmgandhi | 18:6a4db94011d3 | 521 | * |
sahilmgandhi | 18:6a4db94011d3 | 522 | * \param[in] gpio_pin Index of the GPIO pin to toggle |
sahilmgandhi | 18:6a4db94011d3 | 523 | */ |
sahilmgandhi | 18:6a4db94011d3 | 524 | static inline void port_pin_toggle_output_level( |
sahilmgandhi | 18:6a4db94011d3 | 525 | const uint8_t gpio_pin) |
sahilmgandhi | 18:6a4db94011d3 | 526 | { |
sahilmgandhi | 18:6a4db94011d3 | 527 | PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); |
sahilmgandhi | 18:6a4db94011d3 | 528 | uint32_t pin_mask = (1UL << (gpio_pin % 32)); |
sahilmgandhi | 18:6a4db94011d3 | 529 | |
sahilmgandhi | 18:6a4db94011d3 | 530 | /* Toggle pin output level */ |
sahilmgandhi | 18:6a4db94011d3 | 531 | port_base->OUTTGL.reg = pin_mask; |
sahilmgandhi | 18:6a4db94011d3 | 532 | } |
sahilmgandhi | 18:6a4db94011d3 | 533 | |
sahilmgandhi | 18:6a4db94011d3 | 534 | /** @} */ |
sahilmgandhi | 18:6a4db94011d3 | 535 | |
sahilmgandhi | 18:6a4db94011d3 | 536 | #ifdef FEATURE_PORT_INPUT_EVENT |
sahilmgandhi | 18:6a4db94011d3 | 537 | |
sahilmgandhi | 18:6a4db94011d3 | 538 | /** \name Port Input Event |
sahilmgandhi | 18:6a4db94011d3 | 539 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 540 | */ |
sahilmgandhi | 18:6a4db94011d3 | 541 | |
sahilmgandhi | 18:6a4db94011d3 | 542 | /** |
sahilmgandhi | 18:6a4db94011d3 | 543 | * \brief Enable the port event input. |
sahilmgandhi | 18:6a4db94011d3 | 544 | * |
sahilmgandhi | 18:6a4db94011d3 | 545 | * Enable the port event input with the given pin and event. |
sahilmgandhi | 18:6a4db94011d3 | 546 | * |
sahilmgandhi | 18:6a4db94011d3 | 547 | * \param[in] gpio_pin Index of the GPIO pin |
sahilmgandhi | 18:6a4db94011d3 | 548 | * \param[in] n Port input event |
sahilmgandhi | 18:6a4db94011d3 | 549 | * |
sahilmgandhi | 18:6a4db94011d3 | 550 | * \retval STATUS_ERR_INVALID_ARG Invalid parameter |
sahilmgandhi | 18:6a4db94011d3 | 551 | * \retval STATUS_OK Successfully |
sahilmgandhi | 18:6a4db94011d3 | 552 | */ |
sahilmgandhi | 18:6a4db94011d3 | 553 | static inline enum status_code port_enable_input_event( |
sahilmgandhi | 18:6a4db94011d3 | 554 | const uint8_t gpio_pin, |
sahilmgandhi | 18:6a4db94011d3 | 555 | const enum port_input_event n) |
sahilmgandhi | 18:6a4db94011d3 | 556 | { |
sahilmgandhi | 18:6a4db94011d3 | 557 | PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); |
sahilmgandhi | 18:6a4db94011d3 | 558 | switch (n) { |
sahilmgandhi | 18:6a4db94011d3 | 559 | case PORT_INPUT_EVENT_0: |
sahilmgandhi | 18:6a4db94011d3 | 560 | port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI0; |
sahilmgandhi | 18:6a4db94011d3 | 561 | break; |
sahilmgandhi | 18:6a4db94011d3 | 562 | case PORT_INPUT_EVENT_1: |
sahilmgandhi | 18:6a4db94011d3 | 563 | port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI1; |
sahilmgandhi | 18:6a4db94011d3 | 564 | break; |
sahilmgandhi | 18:6a4db94011d3 | 565 | case PORT_INPUT_EVENT_2: |
sahilmgandhi | 18:6a4db94011d3 | 566 | port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI2; |
sahilmgandhi | 18:6a4db94011d3 | 567 | break; |
sahilmgandhi | 18:6a4db94011d3 | 568 | case PORT_INPUT_EVENT_3: |
sahilmgandhi | 18:6a4db94011d3 | 569 | port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI3; |
sahilmgandhi | 18:6a4db94011d3 | 570 | break; |
sahilmgandhi | 18:6a4db94011d3 | 571 | default: |
sahilmgandhi | 18:6a4db94011d3 | 572 | Assert(false); |
sahilmgandhi | 18:6a4db94011d3 | 573 | return STATUS_ERR_INVALID_ARG; |
sahilmgandhi | 18:6a4db94011d3 | 574 | } |
sahilmgandhi | 18:6a4db94011d3 | 575 | return STATUS_OK; |
sahilmgandhi | 18:6a4db94011d3 | 576 | } |
sahilmgandhi | 18:6a4db94011d3 | 577 | |
sahilmgandhi | 18:6a4db94011d3 | 578 | /** |
sahilmgandhi | 18:6a4db94011d3 | 579 | * \brief Disable the port event input. |
sahilmgandhi | 18:6a4db94011d3 | 580 | * |
sahilmgandhi | 18:6a4db94011d3 | 581 | * Disable the port event input with the given pin and event. |
sahilmgandhi | 18:6a4db94011d3 | 582 | * |
sahilmgandhi | 18:6a4db94011d3 | 583 | * \param[in] gpio_pin Index of the GPIO pin |
sahilmgandhi | 18:6a4db94011d3 | 584 | * \param[in] gpio_pin Port input event |
sahilmgandhi | 18:6a4db94011d3 | 585 | * |
sahilmgandhi | 18:6a4db94011d3 | 586 | * \retval STATUS_ERR_INVALID_ARG Invalid parameter |
sahilmgandhi | 18:6a4db94011d3 | 587 | * \retval STATUS_OK Successfully |
sahilmgandhi | 18:6a4db94011d3 | 588 | */ |
sahilmgandhi | 18:6a4db94011d3 | 589 | static inline enum status_code port_disable_input_event( |
sahilmgandhi | 18:6a4db94011d3 | 590 | const uint8_t gpio_pin, |
sahilmgandhi | 18:6a4db94011d3 | 591 | const enum port_input_event n) |
sahilmgandhi | 18:6a4db94011d3 | 592 | { |
sahilmgandhi | 18:6a4db94011d3 | 593 | PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); |
sahilmgandhi | 18:6a4db94011d3 | 594 | switch (n) { |
sahilmgandhi | 18:6a4db94011d3 | 595 | case PORT_INPUT_EVENT_0: |
sahilmgandhi | 18:6a4db94011d3 | 596 | port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; |
sahilmgandhi | 18:6a4db94011d3 | 597 | break; |
sahilmgandhi | 18:6a4db94011d3 | 598 | case PORT_INPUT_EVENT_1: |
sahilmgandhi | 18:6a4db94011d3 | 599 | port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; |
sahilmgandhi | 18:6a4db94011d3 | 600 | break; |
sahilmgandhi | 18:6a4db94011d3 | 601 | case PORT_INPUT_EVENT_2: |
sahilmgandhi | 18:6a4db94011d3 | 602 | port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; |
sahilmgandhi | 18:6a4db94011d3 | 603 | break; |
sahilmgandhi | 18:6a4db94011d3 | 604 | case PORT_INPUT_EVENT_3: |
sahilmgandhi | 18:6a4db94011d3 | 605 | port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; |
sahilmgandhi | 18:6a4db94011d3 | 606 | break; |
sahilmgandhi | 18:6a4db94011d3 | 607 | default: |
sahilmgandhi | 18:6a4db94011d3 | 608 | Assert(false); |
sahilmgandhi | 18:6a4db94011d3 | 609 | return STATUS_ERR_INVALID_ARG; |
sahilmgandhi | 18:6a4db94011d3 | 610 | } |
sahilmgandhi | 18:6a4db94011d3 | 611 | return STATUS_OK; |
sahilmgandhi | 18:6a4db94011d3 | 612 | } |
sahilmgandhi | 18:6a4db94011d3 | 613 | |
sahilmgandhi | 18:6a4db94011d3 | 614 | /** |
sahilmgandhi | 18:6a4db94011d3 | 615 | * \brief Retrieve the default configuration for port input event. |
sahilmgandhi | 18:6a4db94011d3 | 616 | * |
sahilmgandhi | 18:6a4db94011d3 | 617 | * Fills a configuration structure with the default configuration for port input event: |
sahilmgandhi | 18:6a4db94011d3 | 618 | * - Event output to pin |
sahilmgandhi | 18:6a4db94011d3 | 619 | * - Event action to be executed on PIN 0 |
sahilmgandhi | 18:6a4db94011d3 | 620 | * |
sahilmgandhi | 18:6a4db94011d3 | 621 | * \param[out] config Configuration structure to fill with default values |
sahilmgandhi | 18:6a4db94011d3 | 622 | */ |
sahilmgandhi | 18:6a4db94011d3 | 623 | static inline void port_input_event_get_config_defaults( |
sahilmgandhi | 18:6a4db94011d3 | 624 | struct port_input_event_config *const config) |
sahilmgandhi | 18:6a4db94011d3 | 625 | { |
sahilmgandhi | 18:6a4db94011d3 | 626 | Assert(config); |
sahilmgandhi | 18:6a4db94011d3 | 627 | config->action = PORT_INPUT_EVENT_ACTION_OUT; |
sahilmgandhi | 18:6a4db94011d3 | 628 | config->gpio_pin = 0; |
sahilmgandhi | 18:6a4db94011d3 | 629 | } |
sahilmgandhi | 18:6a4db94011d3 | 630 | |
sahilmgandhi | 18:6a4db94011d3 | 631 | /** |
sahilmgandhi | 18:6a4db94011d3 | 632 | * \brief Configure port input event. |
sahilmgandhi | 18:6a4db94011d3 | 633 | * |
sahilmgandhi | 18:6a4db94011d3 | 634 | * Configures port input event with the given configuration settings. |
sahilmgandhi | 18:6a4db94011d3 | 635 | * |
sahilmgandhi | 18:6a4db94011d3 | 636 | * \param[in] config Port input even configuration structure containing the new config |
sahilmgandhi | 18:6a4db94011d3 | 637 | * |
sahilmgandhi | 18:6a4db94011d3 | 638 | * \retval STATUS_ERR_INVALID_ARG Invalid parameter |
sahilmgandhi | 18:6a4db94011d3 | 639 | * \retval STATUS_OK Successfully |
sahilmgandhi | 18:6a4db94011d3 | 640 | */ |
sahilmgandhi | 18:6a4db94011d3 | 641 | |
sahilmgandhi | 18:6a4db94011d3 | 642 | static inline enum status_code port_input_event_set_config( |
sahilmgandhi | 18:6a4db94011d3 | 643 | const enum port_input_event n, |
sahilmgandhi | 18:6a4db94011d3 | 644 | struct port_input_event_config *const config) |
sahilmgandhi | 18:6a4db94011d3 | 645 | { |
sahilmgandhi | 18:6a4db94011d3 | 646 | Assert(config); |
sahilmgandhi | 18:6a4db94011d3 | 647 | PortGroup *const port_base = port_get_group_from_gpio_pin(config->gpio_pin); |
sahilmgandhi | 18:6a4db94011d3 | 648 | uint8_t pin_index = config->gpio_pin % 32; |
sahilmgandhi | 18:6a4db94011d3 | 649 | struct port_config pin_conf; |
sahilmgandhi | 18:6a4db94011d3 | 650 | |
sahilmgandhi | 18:6a4db94011d3 | 651 | port_get_config_defaults(&pin_conf); |
sahilmgandhi | 18:6a4db94011d3 | 652 | /* Configure the GPIO pin as outputs*/ |
sahilmgandhi | 18:6a4db94011d3 | 653 | pin_conf.direction = PORT_PIN_DIR_OUTPUT; |
sahilmgandhi | 18:6a4db94011d3 | 654 | port_pin_set_config(config->gpio_pin, &pin_conf); |
sahilmgandhi | 18:6a4db94011d3 | 655 | |
sahilmgandhi | 18:6a4db94011d3 | 656 | switch (n) { |
sahilmgandhi | 18:6a4db94011d3 | 657 | case PORT_INPUT_EVENT_0: |
sahilmgandhi | 18:6a4db94011d3 | 658 | port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT0(config->action) |
sahilmgandhi | 18:6a4db94011d3 | 659 | | PORT_EVCTRL_PID0(pin_index); |
sahilmgandhi | 18:6a4db94011d3 | 660 | break; |
sahilmgandhi | 18:6a4db94011d3 | 661 | case PORT_INPUT_EVENT_1: |
sahilmgandhi | 18:6a4db94011d3 | 662 | port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT1(config->action) |
sahilmgandhi | 18:6a4db94011d3 | 663 | | PORT_EVCTRL_PID1(pin_index); |
sahilmgandhi | 18:6a4db94011d3 | 664 | break; |
sahilmgandhi | 18:6a4db94011d3 | 665 | case PORT_INPUT_EVENT_2: |
sahilmgandhi | 18:6a4db94011d3 | 666 | port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT2(config->action) |
sahilmgandhi | 18:6a4db94011d3 | 667 | | PORT_EVCTRL_PID2(pin_index); |
sahilmgandhi | 18:6a4db94011d3 | 668 | break; |
sahilmgandhi | 18:6a4db94011d3 | 669 | case PORT_INPUT_EVENT_3: |
sahilmgandhi | 18:6a4db94011d3 | 670 | port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT3(config->action) |
sahilmgandhi | 18:6a4db94011d3 | 671 | | PORT_EVCTRL_PID3(pin_index); |
sahilmgandhi | 18:6a4db94011d3 | 672 | break; |
sahilmgandhi | 18:6a4db94011d3 | 673 | default: |
sahilmgandhi | 18:6a4db94011d3 | 674 | Assert(false); |
sahilmgandhi | 18:6a4db94011d3 | 675 | return STATUS_ERR_INVALID_ARG; |
sahilmgandhi | 18:6a4db94011d3 | 676 | } |
sahilmgandhi | 18:6a4db94011d3 | 677 | return STATUS_OK; |
sahilmgandhi | 18:6a4db94011d3 | 678 | } |
sahilmgandhi | 18:6a4db94011d3 | 679 | |
sahilmgandhi | 18:6a4db94011d3 | 680 | /** @} */ |
sahilmgandhi | 18:6a4db94011d3 | 681 | |
sahilmgandhi | 18:6a4db94011d3 | 682 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 683 | |
sahilmgandhi | 18:6a4db94011d3 | 684 | #ifdef __cplusplus |
sahilmgandhi | 18:6a4db94011d3 | 685 | } |
sahilmgandhi | 18:6a4db94011d3 | 686 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 687 | |
sahilmgandhi | 18:6a4db94011d3 | 688 | /** @} */ |
sahilmgandhi | 18:6a4db94011d3 | 689 | |
sahilmgandhi | 18:6a4db94011d3 | 690 | /** |
sahilmgandhi | 18:6a4db94011d3 | 691 | * \page asfdoc_sam0_port_extra Extra Information for PORT Driver |
sahilmgandhi | 18:6a4db94011d3 | 692 | * |
sahilmgandhi | 18:6a4db94011d3 | 693 | * \section asfdoc_sam0_port_extra_acronyms Acronyms |
sahilmgandhi | 18:6a4db94011d3 | 694 | * Below is a table listing the acronyms used in this module, along with their |
sahilmgandhi | 18:6a4db94011d3 | 695 | * intended meanings. |
sahilmgandhi | 18:6a4db94011d3 | 696 | * |
sahilmgandhi | 18:6a4db94011d3 | 697 | * <table> |
sahilmgandhi | 18:6a4db94011d3 | 698 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 699 | * <th>Acronym</th> |
sahilmgandhi | 18:6a4db94011d3 | 700 | * <th>Description</th> |
sahilmgandhi | 18:6a4db94011d3 | 701 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 702 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 703 | * <td>GPIO</td> |
sahilmgandhi | 18:6a4db94011d3 | 704 | * <td>General Purpose Input/Output</td> |
sahilmgandhi | 18:6a4db94011d3 | 705 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 706 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 707 | * <td>MUX</td> |
sahilmgandhi | 18:6a4db94011d3 | 708 | * <td>Multiplexer</td> |
sahilmgandhi | 18:6a4db94011d3 | 709 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 710 | * </table> |
sahilmgandhi | 18:6a4db94011d3 | 711 | * |
sahilmgandhi | 18:6a4db94011d3 | 712 | * |
sahilmgandhi | 18:6a4db94011d3 | 713 | * \section asfdoc_sam0_port_extra_dependencies Dependencies |
sahilmgandhi | 18:6a4db94011d3 | 714 | * This driver has the following dependencies: |
sahilmgandhi | 18:6a4db94011d3 | 715 | * |
sahilmgandhi | 18:6a4db94011d3 | 716 | * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver" |
sahilmgandhi | 18:6a4db94011d3 | 717 | * |
sahilmgandhi | 18:6a4db94011d3 | 718 | * |
sahilmgandhi | 18:6a4db94011d3 | 719 | * \section asfdoc_sam0_port_extra_errata Errata |
sahilmgandhi | 18:6a4db94011d3 | 720 | * There are no errata related to this driver. |
sahilmgandhi | 18:6a4db94011d3 | 721 | * |
sahilmgandhi | 18:6a4db94011d3 | 722 | * |
sahilmgandhi | 18:6a4db94011d3 | 723 | * \section asfdoc_sam0_port_extra_history Module History |
sahilmgandhi | 18:6a4db94011d3 | 724 | * An overview of the module history is presented in the table below, with |
sahilmgandhi | 18:6a4db94011d3 | 725 | * details on the enhancements and fixes made to the module since its first |
sahilmgandhi | 18:6a4db94011d3 | 726 | * release. The current version of this corresponds to the newest version in |
sahilmgandhi | 18:6a4db94011d3 | 727 | * the table. |
sahilmgandhi | 18:6a4db94011d3 | 728 | * |
sahilmgandhi | 18:6a4db94011d3 | 729 | * <table> |
sahilmgandhi | 18:6a4db94011d3 | 730 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 731 | * <th>Changelog</th> |
sahilmgandhi | 18:6a4db94011d3 | 732 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 733 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 734 | * <td>Added input event feature</td> |
sahilmgandhi | 18:6a4db94011d3 | 735 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 736 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 737 | * <td>Initial Release</td> |
sahilmgandhi | 18:6a4db94011d3 | 738 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 739 | * </table> |
sahilmgandhi | 18:6a4db94011d3 | 740 | */ |
sahilmgandhi | 18:6a4db94011d3 | 741 | |
sahilmgandhi | 18:6a4db94011d3 | 742 | /** |
sahilmgandhi | 18:6a4db94011d3 | 743 | * \page asfdoc_sam0_port_exqsg Examples for PORT Driver |
sahilmgandhi | 18:6a4db94011d3 | 744 | * |
sahilmgandhi | 18:6a4db94011d3 | 745 | * This is a list of the available Quick Start guides (QSGs) and example |
sahilmgandhi | 18:6a4db94011d3 | 746 | * applications for \ref asfdoc_sam0_port_group. QSGs are simple examples with |
sahilmgandhi | 18:6a4db94011d3 | 747 | * step-by-step instructions to configure and use this driver in a selection of |
sahilmgandhi | 18:6a4db94011d3 | 748 | * use cases. Note that QSGs can be compiled as a standalone application or be |
sahilmgandhi | 18:6a4db94011d3 | 749 | * added to the user application. |
sahilmgandhi | 18:6a4db94011d3 | 750 | * |
sahilmgandhi | 18:6a4db94011d3 | 751 | * - \subpage asfdoc_sam0_port_basic_use_case |
sahilmgandhi | 18:6a4db94011d3 | 752 | * |
sahilmgandhi | 18:6a4db94011d3 | 753 | * \page asfdoc_sam0_port_document_revision_history Document Revision History |
sahilmgandhi | 18:6a4db94011d3 | 754 | * |
sahilmgandhi | 18:6a4db94011d3 | 755 | * <table> |
sahilmgandhi | 18:6a4db94011d3 | 756 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 757 | * <th>Doc. Rev.</td> |
sahilmgandhi | 18:6a4db94011d3 | 758 | * <th>Date</td> |
sahilmgandhi | 18:6a4db94011d3 | 759 | * <th>Comments</td> |
sahilmgandhi | 18:6a4db94011d3 | 760 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 761 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 762 | * <td>E</td> |
sahilmgandhi | 18:6a4db94011d3 | 763 | * <td>06/2015</td> |
sahilmgandhi | 18:6a4db94011d3 | 764 | * <td>Added input event feature and support for SAML21, SAMC21, and SAMDAx.</td> |
sahilmgandhi | 18:6a4db94011d3 | 765 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 766 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 767 | * <td>D</td> |
sahilmgandhi | 18:6a4db94011d3 | 768 | * <td>12/2014</td> |
sahilmgandhi | 18:6a4db94011d3 | 769 | * <td>Added support for SAMR21 and SAMD10/D11.</td> |
sahilmgandhi | 18:6a4db94011d3 | 770 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 771 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 772 | * <td>C</td> |
sahilmgandhi | 18:6a4db94011d3 | 773 | * <td>01/2014</td> |
sahilmgandhi | 18:6a4db94011d3 | 774 | * <td>Added support for SAMD21.</td> |
sahilmgandhi | 18:6a4db94011d3 | 775 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 776 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 777 | * <td>B</td> |
sahilmgandhi | 18:6a4db94011d3 | 778 | * <td>06/2013</td> |
sahilmgandhi | 18:6a4db94011d3 | 779 | * <td>Corrected documentation typos.</td> |
sahilmgandhi | 18:6a4db94011d3 | 780 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 781 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 782 | * <td>A</td> |
sahilmgandhi | 18:6a4db94011d3 | 783 | * <td>06/2013</td> |
sahilmgandhi | 18:6a4db94011d3 | 784 | * <td>Initial release</td> |
sahilmgandhi | 18:6a4db94011d3 | 785 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 786 | * </table> |
sahilmgandhi | 18:6a4db94011d3 | 787 | */ |
sahilmgandhi | 18:6a4db94011d3 | 788 | |
sahilmgandhi | 18:6a4db94011d3 | 789 | #endif |