MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0/device/SMM_MPS2.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* MPS2 CMSIS Library
sahilmgandhi 18:6a4db94011d3 2 *
sahilmgandhi 18:6a4db94011d3 3 * Copyright (c) 2006-2016 ARM Limited
sahilmgandhi 18:6a4db94011d3 4 * All rights reserved.
sahilmgandhi 18:6a4db94011d3 5 *
sahilmgandhi 18:6a4db94011d3 6 * Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 7 * modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 10 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 11 *
sahilmgandhi 18:6a4db94011d3 12 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 13 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 14 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 15 *
sahilmgandhi 18:6a4db94011d3 16 * 3. Neither the name of the copyright holder nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 17 * may be used to endorse or promote products derived from this software without
sahilmgandhi 18:6a4db94011d3 18 * specific prior written permission.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
sahilmgandhi 18:6a4db94011d3 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
sahilmgandhi 18:6a4db94011d3 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
sahilmgandhi 18:6a4db94011d3 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
sahilmgandhi 18:6a4db94011d3 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
sahilmgandhi 18:6a4db94011d3 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
sahilmgandhi 18:6a4db94011d3 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
sahilmgandhi 18:6a4db94011d3 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sahilmgandhi 18:6a4db94011d3 30 * POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 31 *******************************************************************************
sahilmgandhi 18:6a4db94011d3 32 * File: smm_mps2.h
sahilmgandhi 18:6a4db94011d3 33 * Release: Version 1.1
sahilmgandhi 18:6a4db94011d3 34 *******************************************************************************/
sahilmgandhi 18:6a4db94011d3 35
sahilmgandhi 18:6a4db94011d3 36 #ifndef __SMM_MPS2_H
sahilmgandhi 18:6a4db94011d3 37 #define __SMM_MPS2_H
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 #include "peripherallink.h" /* device specific header file */
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 #if defined ( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 42 #pragma anon_unions
sahilmgandhi 18:6a4db94011d3 43 #endif
sahilmgandhi 18:6a4db94011d3 44
sahilmgandhi 18:6a4db94011d3 45 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 46 /* FPGA System Register declaration */
sahilmgandhi 18:6a4db94011d3 47 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 typedef struct
sahilmgandhi 18:6a4db94011d3 50 {
sahilmgandhi 18:6a4db94011d3 51 __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
sahilmgandhi 18:6a4db94011d3 52 // [31:2] : Reserved
sahilmgandhi 18:6a4db94011d3 53 // [1:0] : LEDs
sahilmgandhi 18:6a4db94011d3 54 uint32_t RESERVED1[1];
sahilmgandhi 18:6a4db94011d3 55 __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons
sahilmgandhi 18:6a4db94011d3 56 // [31:2] : Reserved
sahilmgandhi 18:6a4db94011d3 57 // [1:0] : Buttons
sahilmgandhi 18:6a4db94011d3 58 uint32_t RESERVED2[1];
sahilmgandhi 18:6a4db94011d3 59 __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter
sahilmgandhi 18:6a4db94011d3 60 __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter
sahilmgandhi 18:6a4db94011d3 61 __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter
sahilmgandhi 18:6a4db94011d3 62 // Increments when 32-bit prescale counter reach zero
sahilmgandhi 18:6a4db94011d3 63 uint32_t RESERVED3[1];
sahilmgandhi 18:6a4db94011d3 64 __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler
sahilmgandhi 18:6a4db94011d3 65 // Bit[31:0] : reload value for prescale counter
sahilmgandhi 18:6a4db94011d3 66 __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter
sahilmgandhi 18:6a4db94011d3 67 // current value of the pre-scaler counter
sahilmgandhi 18:6a4db94011d3 68 // The Cycle Up Counter increment when the prescale down counter reach 0
sahilmgandhi 18:6a4db94011d3 69 // The pre-scaler counter is reloaded with PRESCALE after reaching 0.
sahilmgandhi 18:6a4db94011d3 70 uint32_t RESERVED4[9];
sahilmgandhi 18:6a4db94011d3 71 __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */
sahilmgandhi 18:6a4db94011d3 72 // [31:10] : Reserved
sahilmgandhi 18:6a4db94011d3 73 // [9] : SHIELD_1_SPI_nCS
sahilmgandhi 18:6a4db94011d3 74 // [8] : SHIELD_0_SPI_nCS
sahilmgandhi 18:6a4db94011d3 75 // [7] : ADC_SPI_nCS
sahilmgandhi 18:6a4db94011d3 76 // [6] : CLCD_BL_CTRL
sahilmgandhi 18:6a4db94011d3 77 // [5] : CLCD_RD
sahilmgandhi 18:6a4db94011d3 78 // [4] : CLCD_RS
sahilmgandhi 18:6a4db94011d3 79 // [3] : CLCD_RESET
sahilmgandhi 18:6a4db94011d3 80 // [2] : RESERVED
sahilmgandhi 18:6a4db94011d3 81 // [1] : SPI_nSS
sahilmgandhi 18:6a4db94011d3 82 // [0] : CLCD_CS
sahilmgandhi 18:6a4db94011d3 83 } MPS2_FPGAIO_TypeDef;
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 // MISC register bit definitions
sahilmgandhi 18:6a4db94011d3 86
sahilmgandhi 18:6a4db94011d3 87 #define CLCD_CS_Pos 0
sahilmgandhi 18:6a4db94011d3 88 #define CLCD_CS_Msk (1UL<<CLCD_CS_Pos)
sahilmgandhi 18:6a4db94011d3 89 #define SPI_nSS_Pos 1
sahilmgandhi 18:6a4db94011d3 90 #define SPI_nSS_Msk (1UL<<SPI_nSS_Pos)
sahilmgandhi 18:6a4db94011d3 91 #define CLCD_RESET_Pos 3
sahilmgandhi 18:6a4db94011d3 92 #define CLCD_RESET_Msk (1UL<<CLCD_RESET_Pos)
sahilmgandhi 18:6a4db94011d3 93 #define CLCD_RS_Pos 4
sahilmgandhi 18:6a4db94011d3 94 #define CLCD_RS_Msk (1UL<<CLCD_RS_Pos)
sahilmgandhi 18:6a4db94011d3 95 #define CLCD_RD_Pos 5
sahilmgandhi 18:6a4db94011d3 96 #define CLCD_RD_Msk (1UL<<CLCD_RD_Pos)
sahilmgandhi 18:6a4db94011d3 97 #define CLCD_BL_Pos 6
sahilmgandhi 18:6a4db94011d3 98 #define CLCD_BL_Msk (1UL<<CLCD_BL_Pos)
sahilmgandhi 18:6a4db94011d3 99 #define ADC_nCS_Pos 7
sahilmgandhi 18:6a4db94011d3 100 #define ADC_nCS_Msk (1UL<<ADC_nCS_Pos)
sahilmgandhi 18:6a4db94011d3 101 #define SHIELD_0_nCS_Pos 8
sahilmgandhi 18:6a4db94011d3 102 #define SHIELD_0_nCS_Msk (1UL<<SHIELD_0_nCS_Pos)
sahilmgandhi 18:6a4db94011d3 103 #define SHIELD_1_nCS_Pos 9
sahilmgandhi 18:6a4db94011d3 104 #define SHIELD_1_nCS_Msk (1UL<<SHIELD_1_nCS_Pos)
sahilmgandhi 18:6a4db94011d3 105
sahilmgandhi 18:6a4db94011d3 106 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 107 /* SCC Register declaration */
sahilmgandhi 18:6a4db94011d3 108 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 typedef struct //
sahilmgandhi 18:6a4db94011d3 111 {
sahilmgandhi 18:6a4db94011d3 112 __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
sahilmgandhi 18:6a4db94011d3 113 // [31:1] : Reserved
sahilmgandhi 18:6a4db94011d3 114 // [0] 1 : REMAP BlockRam to ZBT
sahilmgandhi 18:6a4db94011d3 115 __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs
sahilmgandhi 18:6a4db94011d3 116 // [31:8] : Reserved
sahilmgandhi 18:6a4db94011d3 117 // [7:0] : MCC LEDs
sahilmgandhi 18:6a4db94011d3 118 uint32_t RESERVED0[1];
sahilmgandhi 18:6a4db94011d3 119 __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches
sahilmgandhi 18:6a4db94011d3 120 // [31:8] : Reserved
sahilmgandhi 18:6a4db94011d3 121 // [7:0] : These bits indicate state of the MCC switches
sahilmgandhi 18:6a4db94011d3 122 __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision
sahilmgandhi 18:6a4db94011d3 123 // [31:4] : Reserved
sahilmgandhi 18:6a4db94011d3 124 // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B
sahilmgandhi 18:6a4db94011d3 125 uint32_t RESERVED1[35];
sahilmgandhi 18:6a4db94011d3 126 __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register
sahilmgandhi 18:6a4db94011d3 127 // [31:0] : Data
sahilmgandhi 18:6a4db94011d3 128 __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register
sahilmgandhi 18:6a4db94011d3 129 // [31:0] : Data
sahilmgandhi 18:6a4db94011d3 130 __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register
sahilmgandhi 18:6a4db94011d3 131 // [31] : Start (generates interrupt on write to this bit)
sahilmgandhi 18:6a4db94011d3 132 // [30] : R/W access
sahilmgandhi 18:6a4db94011d3 133 // [29:26] : Reserved
sahilmgandhi 18:6a4db94011d3 134 // [25:20] : Function value
sahilmgandhi 18:6a4db94011d3 135 // [19:12] : Reserved
sahilmgandhi 18:6a4db94011d3 136 // [11:0] : Device (value of 0/1/2 for supported clocks)
sahilmgandhi 18:6a4db94011d3 137 __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information
sahilmgandhi 18:6a4db94011d3 138 // [31:2] : Reserved
sahilmgandhi 18:6a4db94011d3 139 // [1] : Error
sahilmgandhi 18:6a4db94011d3 140 // [0] : Complete
sahilmgandhi 18:6a4db94011d3 141 __IO uint32_t RESERVED2[20];
sahilmgandhi 18:6a4db94011d3 142 __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register
sahilmgandhi 18:6a4db94011d3 143 // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked
sahilmgandhi 18:6a4db94011d3 144 // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked
sahilmgandhi 18:6a4db94011d3 145 // [15:1] : Reserved
sahilmgandhi 18:6a4db94011d3 146 // [0] : This bit indicates if all enabled DLLs are locked
sahilmgandhi 18:6a4db94011d3 147 uint32_t RESERVED3[957];
sahilmgandhi 18:6a4db94011d3 148 __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register
sahilmgandhi 18:6a4db94011d3 149 // [31:24] : FPGA build number
sahilmgandhi 18:6a4db94011d3 150 // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1)
sahilmgandhi 18:6a4db94011d3 151 // [19:11] : Reserved
sahilmgandhi 18:6a4db94011d3 152 // [10] : if “1” SCC_SW register has been implemented
sahilmgandhi 18:6a4db94011d3 153 // [9] : if “1” SCC_LED register has been implemented
sahilmgandhi 18:6a4db94011d3 154 // [8] : if “1” DLL lock register has been implemented
sahilmgandhi 18:6a4db94011d3 155 // [7:0] : number of SCC configuration register
sahilmgandhi 18:6a4db94011d3 156 __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image
sahilmgandhi 18:6a4db94011d3 157 // [31:24] : Implementer ID: 0x41 = ARM
sahilmgandhi 18:6a4db94011d3 158 // [23:20] : Application note IP variant number
sahilmgandhi 18:6a4db94011d3 159 // [19:16] : IP Architecture: 0x4 =AHB
sahilmgandhi 18:6a4db94011d3 160 // [15:4] : Primary part number: 386 = AN386
sahilmgandhi 18:6a4db94011d3 161 // [3:0] : Application note IP revision number
sahilmgandhi 18:6a4db94011d3 162 } MPS2_SCC_TypeDef;
sahilmgandhi 18:6a4db94011d3 163
sahilmgandhi 18:6a4db94011d3 164
sahilmgandhi 18:6a4db94011d3 165 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 166 /* SSP Peripheral declaration */
sahilmgandhi 18:6a4db94011d3 167 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 168
sahilmgandhi 18:6a4db94011d3 169 typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
sahilmgandhi 18:6a4db94011d3 170 {
sahilmgandhi 18:6a4db94011d3 171 __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
sahilmgandhi 18:6a4db94011d3 172 // [31:16] : Reserved
sahilmgandhi 18:6a4db94011d3 173 // [15:8] : Serial clock rate
sahilmgandhi 18:6a4db94011d3 174 // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only
sahilmgandhi 18:6a4db94011d3 175 // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only
sahilmgandhi 18:6a4db94011d3 176 // [5:4] : Frame format
sahilmgandhi 18:6a4db94011d3 177 // [3:0] : Data Size Select
sahilmgandhi 18:6a4db94011d3 178 __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1
sahilmgandhi 18:6a4db94011d3 179 // [31:4] : Reserved
sahilmgandhi 18:6a4db94011d3 180 // [3] : Slave-mode output disable
sahilmgandhi 18:6a4db94011d3 181 // [2] : Master or slave mode select
sahilmgandhi 18:6a4db94011d3 182 // [1] : Synchronous serial port enable
sahilmgandhi 18:6a4db94011d3 183 // [0] : Loop back mode
sahilmgandhi 18:6a4db94011d3 184 __IO uint32_t DR; // Offset: 0x008 (R/W) Data register
sahilmgandhi 18:6a4db94011d3 185 // [31:16] : Reserved
sahilmgandhi 18:6a4db94011d3 186 // [15:0] : Transmit/Receive FIFO
sahilmgandhi 18:6a4db94011d3 187 __I uint32_t SR; // Offset: 0x00C (R/ ) Status register
sahilmgandhi 18:6a4db94011d3 188 // [31:5] : Reserved
sahilmgandhi 18:6a4db94011d3 189 // [4] : PrimeCell SSP busy flag
sahilmgandhi 18:6a4db94011d3 190 // [3] : Receive FIFO full
sahilmgandhi 18:6a4db94011d3 191 // [2] : Receive FIFO not empty
sahilmgandhi 18:6a4db94011d3 192 // [1] : Transmit FIFO not full
sahilmgandhi 18:6a4db94011d3 193 // [0] : Transmit FIFO empty
sahilmgandhi 18:6a4db94011d3 194 __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register
sahilmgandhi 18:6a4db94011d3 195 // [31:8] : Reserved
sahilmgandhi 18:6a4db94011d3 196 // [8:0] : Clock prescale divisor
sahilmgandhi 18:6a4db94011d3 197 __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register
sahilmgandhi 18:6a4db94011d3 198 // [31:4] : Reserved
sahilmgandhi 18:6a4db94011d3 199 // [3] : Transmit FIFO interrupt mask
sahilmgandhi 18:6a4db94011d3 200 // [2] : Receive FIFO interrupt mask
sahilmgandhi 18:6a4db94011d3 201 // [1] : Receive timeout interrupt mask
sahilmgandhi 18:6a4db94011d3 202 // [0] : Receive overrun interrupt mask
sahilmgandhi 18:6a4db94011d3 203 __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register
sahilmgandhi 18:6a4db94011d3 204 // [31:4] : Reserved
sahilmgandhi 18:6a4db94011d3 205 // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt
sahilmgandhi 18:6a4db94011d3 206 // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt
sahilmgandhi 18:6a4db94011d3 207 // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt
sahilmgandhi 18:6a4db94011d3 208 // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt
sahilmgandhi 18:6a4db94011d3 209 __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register
sahilmgandhi 18:6a4db94011d3 210 // [31:4] : Reserved
sahilmgandhi 18:6a4db94011d3 211 // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
sahilmgandhi 18:6a4db94011d3 212 // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
sahilmgandhi 18:6a4db94011d3 213 // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
sahilmgandhi 18:6a4db94011d3 214 // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
sahilmgandhi 18:6a4db94011d3 215 __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register
sahilmgandhi 18:6a4db94011d3 216 // [31:2] : Reserved
sahilmgandhi 18:6a4db94011d3 217 // [1] : Clears the SSPRTINTR interrupt
sahilmgandhi 18:6a4db94011d3 218 // [0] : Clears the SSPRORINTR interrupt
sahilmgandhi 18:6a4db94011d3 219 __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register
sahilmgandhi 18:6a4db94011d3 220 // [31:2] : Reserved
sahilmgandhi 18:6a4db94011d3 221 // [1] : Transmit DMA Enable
sahilmgandhi 18:6a4db94011d3 222 // [0] : Receive DMA Enable
sahilmgandhi 18:6a4db94011d3 223 } MPS2_SSP_TypeDef;
sahilmgandhi 18:6a4db94011d3 224
sahilmgandhi 18:6a4db94011d3 225
sahilmgandhi 18:6a4db94011d3 226 // SSP_CR0 Control register 0
sahilmgandhi 18:6a4db94011d3 227 #define SSP_CR0_DSS_Pos 0 // Data Size Select
sahilmgandhi 18:6a4db94011d3 228 #define SSP_CR0_DSS_Msk (0xF<<SSP_CR0_DSS_Pos)
sahilmgandhi 18:6a4db94011d3 229 #define SSP_CR0_FRF_Pos 4 // Frame Format Select
sahilmgandhi 18:6a4db94011d3 230 #define SSP_CR0_FRF_Msk (3UL<<SSP_CR0_FRM_Pos)
sahilmgandhi 18:6a4db94011d3 231 #define SSP_CR0_SPO_Pos 6 // SSPCLKOUT polarity
sahilmgandhi 18:6a4db94011d3 232 #define SSP_CR0_SPO_Msk (1UL<<SSP_CR0_SPO_Pos)
sahilmgandhi 18:6a4db94011d3 233 #define SSP_CR0_SPH_Pos 7 // SSPCLKOUT phase
sahilmgandhi 18:6a4db94011d3 234 #define SSP_CR0_SPH_Msk (1UL<<SSP_CR0_SPH_Pos)
sahilmgandhi 18:6a4db94011d3 235 #define SSP_CR0_SCR_Pos 8 // Serial Clock Rate (divide)
sahilmgandhi 18:6a4db94011d3 236 #define SSP_CR0_SCR_Msk (0xFF<<SSP_CR0_SCR_Pos)
sahilmgandhi 18:6a4db94011d3 237
sahilmgandhi 18:6a4db94011d3 238 #define SSP_CR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3
sahilmgandhi 18:6a4db94011d3 239 #define SSP_CR0_FRF_MOT 0x0000 // Frame format, Motorola
sahilmgandhi 18:6a4db94011d3 240 #define SSP_CR0_DSS_8 0x0007 // Data packet size, 8bits
sahilmgandhi 18:6a4db94011d3 241 #define SSP_CR0_DSS_16 0x000F // Data packet size, 16bits
sahilmgandhi 18:6a4db94011d3 242
sahilmgandhi 18:6a4db94011d3 243 // SSP_CR1 Control register 1
sahilmgandhi 18:6a4db94011d3 244 #define SSP_CR1_LBM_Pos 0 // Loop Back Mode
sahilmgandhi 18:6a4db94011d3 245 #define SSP_CR1_LBM_Msk (1UL<<SSP_CR1_LBM_Pos)
sahilmgandhi 18:6a4db94011d3 246 #define SSP_CR1_SSE_Pos 1 // Serial port enable
sahilmgandhi 18:6a4db94011d3 247 #define SSP_CR1_SSE_Msk (1UL<<SSP_CR1_SSE_Pos)
sahilmgandhi 18:6a4db94011d3 248 #define SSP_CR1_MS_Pos 2 // Master or Slave mode
sahilmgandhi 18:6a4db94011d3 249 #define SSP_CR1_MS_Msk (1UL<<SSP_CR1_MS_Pos)
sahilmgandhi 18:6a4db94011d3 250 #define SSP_CR1_SOD_Pos 3 // Slave Output mode Disable
sahilmgandhi 18:6a4db94011d3 251 #define SSP_CR1_SOD_Msk (1UL<<SSP_CR1_SOD_Pos)
sahilmgandhi 18:6a4db94011d3 252
sahilmgandhi 18:6a4db94011d3 253 // SSP_SR Status register
sahilmgandhi 18:6a4db94011d3 254 #define SSP_SR_TFE_Pos 0 // Transmit FIFO empty
sahilmgandhi 18:6a4db94011d3 255 #define SSP_SR_TFE_Msk (1UL<<SSP_SR_TFE_Pos)
sahilmgandhi 18:6a4db94011d3 256 #define SSP_SR_TNF_Pos 1 // Transmit FIFO not full
sahilmgandhi 18:6a4db94011d3 257 #define SSP_SR_TNF_Msk (1UL<<SSP_SR_TNF_Pos)
sahilmgandhi 18:6a4db94011d3 258 #define SSP_SR_RNE_Pos 2 // Receive FIFO not empty
sahilmgandhi 18:6a4db94011d3 259 #define SSP_SR_RNE_Msk (1UL<<SSP_SR_RNE_Pos)
sahilmgandhi 18:6a4db94011d3 260 #define SSP_SR_RFF_Pos 3 // Receive FIFO full
sahilmgandhi 18:6a4db94011d3 261 #define SSP_SR_RFF_Msk (1UL<<SSP_SR_RFF_Pos)
sahilmgandhi 18:6a4db94011d3 262 #define SSP_SR_BSY_Pos 4 // Busy
sahilmgandhi 18:6a4db94011d3 263 #define SSP_SR_BSY_Msk (1UL<<SSP_SR_BSY_Pos)
sahilmgandhi 18:6a4db94011d3 264
sahilmgandhi 18:6a4db94011d3 265 // SSP_CPSR Clock prescale register
sahilmgandhi 18:6a4db94011d3 266 #define SSP_CPSR_CPD_Pos 0 // Clock prescale divisor
sahilmgandhi 18:6a4db94011d3 267 #define SSP_CPSR_CPD_Msk (0xFF<<SSP_CPSR_CDP_Pos)
sahilmgandhi 18:6a4db94011d3 268
sahilmgandhi 18:6a4db94011d3 269 #define SSP_CPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8
sahilmgandhi 18:6a4db94011d3 270
sahilmgandhi 18:6a4db94011d3 271 // SSPIMSC Interrupt mask set and clear register
sahilmgandhi 18:6a4db94011d3 272 #define SSP_IMSC_RORIM_Pos 0 // Receive overrun not Masked
sahilmgandhi 18:6a4db94011d3 273 #define SSP_IMSC_RORIM_Msk (1UL<<SSP_IMSC_RORIM_Pos)
sahilmgandhi 18:6a4db94011d3 274 #define SSP_IMSC_RTIM_Pos 1 // Receive timeout not Masked
sahilmgandhi 18:6a4db94011d3 275 #define SSP_IMSC_RTIM_Msk (1UL<<SSP_IMSC_RTIM_Pos)
sahilmgandhi 18:6a4db94011d3 276 #define SSP_IMSC_RXIM_Pos 2 // Receive FIFO not Masked
sahilmgandhi 18:6a4db94011d3 277 #define SSP_IMSC_RXIM_Msk (1UL<<SSP_IMSC_RXIM_Pos)
sahilmgandhi 18:6a4db94011d3 278 #define SSP_IMSC_TXIM_Pos 3 // Transmit FIFO not Masked
sahilmgandhi 18:6a4db94011d3 279 #define SSP_IMSC_TXIM_Msk (1UL<<SSP_IMSC_TXIM_Pos)
sahilmgandhi 18:6a4db94011d3 280
sahilmgandhi 18:6a4db94011d3 281 // SSPRIS Raw interrupt status register
sahilmgandhi 18:6a4db94011d3 282 #define SSP_RIS_RORRIS_Pos 0 // Raw Overrun interrupt flag
sahilmgandhi 18:6a4db94011d3 283 #define SSP_RIS_RORRIS_Msk (1UL<<SSP_RIS_RORRIS_Pos)
sahilmgandhi 18:6a4db94011d3 284 #define SSP_RIS_RTRIS_Pos 1 // Raw Timemout interrupt flag
sahilmgandhi 18:6a4db94011d3 285 #define SSP_RIS_RTRIS_Msk (1UL<<SSP_RIS_RTRIS_Pos)
sahilmgandhi 18:6a4db94011d3 286 #define SSP_RIS_RXRIS_Pos 2 // Raw Receive interrupt flag
sahilmgandhi 18:6a4db94011d3 287 #define SSP_RIS_RXRIS_Msk (1UL<<SSP_RIS_RXRIS_Pos)
sahilmgandhi 18:6a4db94011d3 288 #define SSP_RIS_TXRIS_Pos 3 // Raw Transmit interrupt flag
sahilmgandhi 18:6a4db94011d3 289 #define SSP_RIS_TXRIS_Msk (1UL<<SSP_RIS_TXRIS_Pos)
sahilmgandhi 18:6a4db94011d3 290
sahilmgandhi 18:6a4db94011d3 291 // SSPMIS Masked interrupt status register
sahilmgandhi 18:6a4db94011d3 292 #define SSP_MIS_RORMIS_Pos 0 // Masked Overrun interrupt flag
sahilmgandhi 18:6a4db94011d3 293 #define SSP_MIS_RORMIS_Msk (1UL<<SSP_MIS_RORMIS_Pos)
sahilmgandhi 18:6a4db94011d3 294 #define SSP_MIS_RTMIS_Pos 1 // Masked Timemout interrupt flag
sahilmgandhi 18:6a4db94011d3 295 #define SSP_MIS_RTMIS_Msk (1UL<<SSP_MIS_RTMIS_Pos)
sahilmgandhi 18:6a4db94011d3 296 #define SSP_MIS_RXMIS_Pos 2 // Masked Receive interrupt flag
sahilmgandhi 18:6a4db94011d3 297 #define SSP_MIS_RXMIS_Msk (1UL<<SSP_MIS_RXMIS_Pos)
sahilmgandhi 18:6a4db94011d3 298 #define SSP_MIS_TXMIS_Pos 3 // Masked Transmit interrupt flag
sahilmgandhi 18:6a4db94011d3 299 #define SSP_MIS_TXMIS_Msk (1UL<<SSP_MIS_TXMIS_Pos)
sahilmgandhi 18:6a4db94011d3 300
sahilmgandhi 18:6a4db94011d3 301 // SSPICR Interrupt clear register
sahilmgandhi 18:6a4db94011d3 302 #define SSP_ICR_RORIC_Pos 0 // Clears Overrun interrupt flag
sahilmgandhi 18:6a4db94011d3 303 #define SSP_ICR_RORIC_Msk (1UL<<SSP_ICR_RORIC_Pos)
sahilmgandhi 18:6a4db94011d3 304 #define SSP_ICR_RTIC_Pos 1 // Clears Timemout interrupt flag
sahilmgandhi 18:6a4db94011d3 305 #define SSP_ICR_RTIC_Msk (1UL<<SSP_ICR_RTIC_Pos)
sahilmgandhi 18:6a4db94011d3 306
sahilmgandhi 18:6a4db94011d3 307 // SSPDMACR DMA control register
sahilmgandhi 18:6a4db94011d3 308 #define SSP_DMACR_RXDMAE_Pos 0 // Enable Receive FIFO DMA
sahilmgandhi 18:6a4db94011d3 309 #define SSP_DMACR_RXDMAE_Msk (1UL<<SSP_DMACR_RXDMAE_Pos)
sahilmgandhi 18:6a4db94011d3 310 #define SSP_DMACR_TXDMAE_Pos 1 // Enable Transmit FIFO DMA
sahilmgandhi 18:6a4db94011d3 311 #define SSP_DMACR_TXDMAE_Msk (1UL<<SSP_DMACR_TXDMAE_Pos)
sahilmgandhi 18:6a4db94011d3 312
sahilmgandhi 18:6a4db94011d3 313 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 314 /* Audio and Touch Screen (I2C) Peripheral declaration */
sahilmgandhi 18:6a4db94011d3 315 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 316
sahilmgandhi 18:6a4db94011d3 317 typedef struct
sahilmgandhi 18:6a4db94011d3 318 {
sahilmgandhi 18:6a4db94011d3 319 union {
sahilmgandhi 18:6a4db94011d3 320 __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
sahilmgandhi 18:6a4db94011d3 321 __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
sahilmgandhi 18:6a4db94011d3 322 };
sahilmgandhi 18:6a4db94011d3 323 __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
sahilmgandhi 18:6a4db94011d3 324 } MPS2_I2C_TypeDef;
sahilmgandhi 18:6a4db94011d3 325
sahilmgandhi 18:6a4db94011d3 326 #define SDA 1 << 1
sahilmgandhi 18:6a4db94011d3 327 #define SCL 1 << 0
sahilmgandhi 18:6a4db94011d3 328
sahilmgandhi 18:6a4db94011d3 329
sahilmgandhi 18:6a4db94011d3 330 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 331 /* Audio I2S Peripheral declaration */
sahilmgandhi 18:6a4db94011d3 332 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 333
sahilmgandhi 18:6a4db94011d3 334 typedef struct
sahilmgandhi 18:6a4db94011d3 335 {
sahilmgandhi 18:6a4db94011d3 336 /*!< Offset: 0x000 CONTROL Register (R/W) */
sahilmgandhi 18:6a4db94011d3 337 __IO uint32_t CONTROL; // <h> CONTROL </h>
sahilmgandhi 18:6a4db94011d3 338 // <o.0> TX Enable
sahilmgandhi 18:6a4db94011d3 339 // <0=> TX disabled
sahilmgandhi 18:6a4db94011d3 340 // <1=> TX enabled
sahilmgandhi 18:6a4db94011d3 341 // <o.1> TX IRQ Enable
sahilmgandhi 18:6a4db94011d3 342 // <0=> TX IRQ disabled
sahilmgandhi 18:6a4db94011d3 343 // <1=> TX IRQ enabled
sahilmgandhi 18:6a4db94011d3 344 // <o.2> RX Enable
sahilmgandhi 18:6a4db94011d3 345 // <0=> RX disabled
sahilmgandhi 18:6a4db94011d3 346 // <1=> RX enabled
sahilmgandhi 18:6a4db94011d3 347 // <o.3> RX IRQ Enable
sahilmgandhi 18:6a4db94011d3 348 // <0=> RX IRQ disabled
sahilmgandhi 18:6a4db94011d3 349 // <1=> RX IRQ enabled
sahilmgandhi 18:6a4db94011d3 350 // <o.10..8> TX Buffer Water Level
sahilmgandhi 18:6a4db94011d3 351 // <0=> / IRQ triggers when any space available
sahilmgandhi 18:6a4db94011d3 352 // <1=> / IRQ triggers when more than 1 space available
sahilmgandhi 18:6a4db94011d3 353 // <2=> / IRQ triggers when more than 2 space available
sahilmgandhi 18:6a4db94011d3 354 // <3=> / IRQ triggers when more than 3 space available
sahilmgandhi 18:6a4db94011d3 355 // <4=> Undefined!
sahilmgandhi 18:6a4db94011d3 356 // <5=> Undefined!
sahilmgandhi 18:6a4db94011d3 357 // <6=> Undefined!
sahilmgandhi 18:6a4db94011d3 358 // <7=> Undefined!
sahilmgandhi 18:6a4db94011d3 359 // <o.14..12> RX Buffer Water Level
sahilmgandhi 18:6a4db94011d3 360 // <0=> Undefined!
sahilmgandhi 18:6a4db94011d3 361 // <1=> / IRQ triggers when less than 1 space available
sahilmgandhi 18:6a4db94011d3 362 // <2=> / IRQ triggers when less than 2 space available
sahilmgandhi 18:6a4db94011d3 363 // <3=> / IRQ triggers when less than 3 space available
sahilmgandhi 18:6a4db94011d3 364 // <4=> / IRQ triggers when less than 4 space available
sahilmgandhi 18:6a4db94011d3 365 // <5=> Undefined!
sahilmgandhi 18:6a4db94011d3 366 // <6=> Undefined!
sahilmgandhi 18:6a4db94011d3 367 // <7=> Undefined!
sahilmgandhi 18:6a4db94011d3 368 // <o.16> FIFO reset
sahilmgandhi 18:6a4db94011d3 369 // <0=> Normal operation
sahilmgandhi 18:6a4db94011d3 370 // <1=> FIFO reset
sahilmgandhi 18:6a4db94011d3 371 // <o.17> Audio Codec reset
sahilmgandhi 18:6a4db94011d3 372 // <0=> Normal operation
sahilmgandhi 18:6a4db94011d3 373 // <1=> Assert audio Codec reset
sahilmgandhi 18:6a4db94011d3 374 /*!< Offset: 0x004 STATUS Register (R/ ) */
sahilmgandhi 18:6a4db94011d3 375 __I uint32_t STATUS; // <h> STATUS </h>
sahilmgandhi 18:6a4db94011d3 376 // <o.0> TX Buffer alert
sahilmgandhi 18:6a4db94011d3 377 // <0=> TX buffer don't need service yet
sahilmgandhi 18:6a4db94011d3 378 // <1=> TX buffer need service
sahilmgandhi 18:6a4db94011d3 379 // <o.1> RX Buffer alert
sahilmgandhi 18:6a4db94011d3 380 // <0=> RX buffer don't need service yet
sahilmgandhi 18:6a4db94011d3 381 // <1=> RX buffer need service
sahilmgandhi 18:6a4db94011d3 382 // <o.2> TX Buffer Empty
sahilmgandhi 18:6a4db94011d3 383 // <0=> TX buffer have data
sahilmgandhi 18:6a4db94011d3 384 // <1=> TX buffer empty
sahilmgandhi 18:6a4db94011d3 385 // <o.3> TX Buffer Full
sahilmgandhi 18:6a4db94011d3 386 // <0=> TX buffer not full
sahilmgandhi 18:6a4db94011d3 387 // <1=> TX buffer full
sahilmgandhi 18:6a4db94011d3 388 // <o.4> RX Buffer Empty
sahilmgandhi 18:6a4db94011d3 389 // <0=> RX buffer have data
sahilmgandhi 18:6a4db94011d3 390 // <1=> RX buffer empty
sahilmgandhi 18:6a4db94011d3 391 // <o.5> RX Buffer Full
sahilmgandhi 18:6a4db94011d3 392 // <0=> RX buffer not full
sahilmgandhi 18:6a4db94011d3 393 // <1=> RX buffer full
sahilmgandhi 18:6a4db94011d3 394 union {
sahilmgandhi 18:6a4db94011d3 395 /*!< Offset: 0x008 Error Status Register (R/ ) */
sahilmgandhi 18:6a4db94011d3 396 __I uint32_t ERROR; // <h> ERROR </h>
sahilmgandhi 18:6a4db94011d3 397 // <o.0> TX error
sahilmgandhi 18:6a4db94011d3 398 // <0=> Okay
sahilmgandhi 18:6a4db94011d3 399 // <1=> TX overrun/underrun
sahilmgandhi 18:6a4db94011d3 400 // <o.1> RX error
sahilmgandhi 18:6a4db94011d3 401 // <0=> Okay
sahilmgandhi 18:6a4db94011d3 402 // <1=> RX overrun/underrun
sahilmgandhi 18:6a4db94011d3 403 /*!< Offset: 0x008 Error Clear Register ( /W) */
sahilmgandhi 18:6a4db94011d3 404 __O uint32_t ERRORCLR; // <h> ERRORCLR </h>
sahilmgandhi 18:6a4db94011d3 405 // <o.0> TX error
sahilmgandhi 18:6a4db94011d3 406 // <0=> Okay
sahilmgandhi 18:6a4db94011d3 407 // <1=> Clear TX error
sahilmgandhi 18:6a4db94011d3 408 // <o.1> RX error
sahilmgandhi 18:6a4db94011d3 409 // <0=> Okay
sahilmgandhi 18:6a4db94011d3 410 // <1=> Clear RX error
sahilmgandhi 18:6a4db94011d3 411 };
sahilmgandhi 18:6a4db94011d3 412 /*!< Offset: 0x00C Divide ratio Register (R/W) */
sahilmgandhi 18:6a4db94011d3 413 __IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
sahilmgandhi 18:6a4db94011d3 414 // <o.9..0> TX error (default 0x80)
sahilmgandhi 18:6a4db94011d3 415 /*!< Offset: 0x010 Transmit Buffer ( /W) */
sahilmgandhi 18:6a4db94011d3 416 __O uint32_t TXBUF; // <h> Transmit buffer </h>
sahilmgandhi 18:6a4db94011d3 417 // <o.15..0> Right channel
sahilmgandhi 18:6a4db94011d3 418 // <o.31..16> Left channel
sahilmgandhi 18:6a4db94011d3 419 /*!< Offset: 0x014 Receive Buffer (R/ ) */
sahilmgandhi 18:6a4db94011d3 420 __I uint32_t RXBUF; // <h> Receive buffer </h>
sahilmgandhi 18:6a4db94011d3 421 // <o.15..0> Right channel
sahilmgandhi 18:6a4db94011d3 422 // <o.31..16> Left channel
sahilmgandhi 18:6a4db94011d3 423 uint32_t RESERVED1[186];
sahilmgandhi 18:6a4db94011d3 424 __IO uint32_t ITCR; // <h> Integration Test Control Register </h>
sahilmgandhi 18:6a4db94011d3 425 // <o.0> ITEN
sahilmgandhi 18:6a4db94011d3 426 // <0=> Normal operation
sahilmgandhi 18:6a4db94011d3 427 // <1=> Integration Test mode enable
sahilmgandhi 18:6a4db94011d3 428 __O uint32_t ITIP1; // <h> Integration Test Input Register 1</h>
sahilmgandhi 18:6a4db94011d3 429 // <o.0> SDIN
sahilmgandhi 18:6a4db94011d3 430 __O uint32_t ITOP1; // <h> Integration Test Output Register 1</h>
sahilmgandhi 18:6a4db94011d3 431 // <o.0> SDOUT
sahilmgandhi 18:6a4db94011d3 432 // <o.1> SCLK
sahilmgandhi 18:6a4db94011d3 433 // <o.2> LRCK
sahilmgandhi 18:6a4db94011d3 434 // <o.3> IRQOUT
sahilmgandhi 18:6a4db94011d3 435 } MPS2_I2S_TypeDef;
sahilmgandhi 18:6a4db94011d3 436
sahilmgandhi 18:6a4db94011d3 437 #define I2S_CONTROL_TXEN_Pos 0
sahilmgandhi 18:6a4db94011d3 438 #define I2S_CONTROL_TXEN_Msk (1UL<<I2S_CONTROL_TXEN_Pos)
sahilmgandhi 18:6a4db94011d3 439
sahilmgandhi 18:6a4db94011d3 440 #define I2S_CONTROL_TXIRQEN_Pos 1
sahilmgandhi 18:6a4db94011d3 441 #define I2S_CONTROL_TXIRQEN_Msk (1UL<<I2S_CONTROL_TXIRQEN_Pos)
sahilmgandhi 18:6a4db94011d3 442
sahilmgandhi 18:6a4db94011d3 443 #define I2S_CONTROL_RXEN_Pos 2
sahilmgandhi 18:6a4db94011d3 444 #define I2S_CONTROL_RXEN_Msk (1UL<<I2S_CONTROL_RXEN_Pos)
sahilmgandhi 18:6a4db94011d3 445
sahilmgandhi 18:6a4db94011d3 446 #define I2S_CONTROL_RXIRQEN_Pos 3
sahilmgandhi 18:6a4db94011d3 447 #define I2S_CONTROL_RXIRQEN_Msk (1UL<<I2S_CONTROL_RXIRQEN_Pos)
sahilmgandhi 18:6a4db94011d3 448
sahilmgandhi 18:6a4db94011d3 449 #define I2S_CONTROL_TXWLVL_Pos 8
sahilmgandhi 18:6a4db94011d3 450 #define I2S_CONTROL_TXWLVL_Msk (7UL<<I2S_CONTROL_TXWLVL_Pos)
sahilmgandhi 18:6a4db94011d3 451
sahilmgandhi 18:6a4db94011d3 452 #define I2S_CONTROL_RXWLVL_Pos 12
sahilmgandhi 18:6a4db94011d3 453 #define I2S_CONTROL_RXWLVL_Msk (7UL<<I2S_CONTROL_RXWLVL_Pos)
sahilmgandhi 18:6a4db94011d3 454 /* FIFO reset*/
sahilmgandhi 18:6a4db94011d3 455 #define I2S_CONTROL_FIFORST_Pos 16
sahilmgandhi 18:6a4db94011d3 456 #define I2S_CONTROL_FIFORST_Msk (1UL<<I2S_CONTROL_FIFORST_Pos)
sahilmgandhi 18:6a4db94011d3 457 /* Codec reset*/
sahilmgandhi 18:6a4db94011d3 458 #define I2S_CONTROL_CODECRST_Pos 17
sahilmgandhi 18:6a4db94011d3 459 #define I2S_CONTROL_CODECRST_Msk (1UL<<I2S_CONTROL_CODECRST_Pos)
sahilmgandhi 18:6a4db94011d3 460
sahilmgandhi 18:6a4db94011d3 461 #define I2S_STATUS_TXIRQ_Pos 0
sahilmgandhi 18:6a4db94011d3 462 #define I2S_STATUS_TXIRQ_Msk (1UL<<I2S_STATUS_TXIRQ_Pos)
sahilmgandhi 18:6a4db94011d3 463
sahilmgandhi 18:6a4db94011d3 464 #define I2S_STATUS_RXIRQ_Pos 1
sahilmgandhi 18:6a4db94011d3 465 #define I2S_STATUS_RXIRQ_Msk (1UL<<I2S_STATUS_RXIRQ_Pos)
sahilmgandhi 18:6a4db94011d3 466
sahilmgandhi 18:6a4db94011d3 467 #define I2S_STATUS_TXEmpty_Pos 2
sahilmgandhi 18:6a4db94011d3 468 #define I2S_STATUS_TXEmpty_Msk (1UL<<I2S_STATUS_TXEmpty_Pos)
sahilmgandhi 18:6a4db94011d3 469
sahilmgandhi 18:6a4db94011d3 470 #define I2S_STATUS_TXFull_Pos 3
sahilmgandhi 18:6a4db94011d3 471 #define I2S_STATUS_TXFull_Msk (1UL<<I2S_STATUS_TXFull_Pos)
sahilmgandhi 18:6a4db94011d3 472
sahilmgandhi 18:6a4db94011d3 473 #define I2S_STATUS_RXEmpty_Pos 4
sahilmgandhi 18:6a4db94011d3 474 #define I2S_STATUS_RXEmpty_Msk (1UL<<I2S_STATUS_RXEmpty_Pos)
sahilmgandhi 18:6a4db94011d3 475
sahilmgandhi 18:6a4db94011d3 476 #define I2S_STATUS_RXFull_Pos 5
sahilmgandhi 18:6a4db94011d3 477 #define I2S_STATUS_RXFull_Msk (1UL<<I2S_STATUS_RXFull_Pos)
sahilmgandhi 18:6a4db94011d3 478
sahilmgandhi 18:6a4db94011d3 479 #define I2S_ERROR_TXERR_Pos 0
sahilmgandhi 18:6a4db94011d3 480 #define I2S_ERROR_TXERR_Msk (1UL<<I2S_ERROR_TXERR_Pos)
sahilmgandhi 18:6a4db94011d3 481
sahilmgandhi 18:6a4db94011d3 482 #define I2S_ERROR_RXERR_Pos 1
sahilmgandhi 18:6a4db94011d3 483 #define I2S_ERROR_RXERR_Msk (1UL<<I2S_ERROR_RXERR_Pos)
sahilmgandhi 18:6a4db94011d3 484
sahilmgandhi 18:6a4db94011d3 485 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 486 /* SMSC9220 Register Definitions */
sahilmgandhi 18:6a4db94011d3 487 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 488
sahilmgandhi 18:6a4db94011d3 489 typedef struct // SMSC LAN9220
sahilmgandhi 18:6a4db94011d3 490 {
sahilmgandhi 18:6a4db94011d3 491 __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
sahilmgandhi 18:6a4db94011d3 492 uint32_t RESERVED1[0x7];
sahilmgandhi 18:6a4db94011d3 493 __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)
sahilmgandhi 18:6a4db94011d3 494 uint32_t RESERVED2[0x7];
sahilmgandhi 18:6a4db94011d3 495
sahilmgandhi 18:6a4db94011d3 496 __I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40)
sahilmgandhi 18:6a4db94011d3 497 __I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44)
sahilmgandhi 18:6a4db94011d3 498 __I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48)
sahilmgandhi 18:6a4db94011d3 499 __I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C)
sahilmgandhi 18:6a4db94011d3 500
sahilmgandhi 18:6a4db94011d3 501 __I uint32_t ID_REV; // Chip ID and Revision (offset 0x50)
sahilmgandhi 18:6a4db94011d3 502 __IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54)
sahilmgandhi 18:6a4db94011d3 503 __IO uint32_t INT_STS; // Interrupt Status (offset 0x58)
sahilmgandhi 18:6a4db94011d3 504 __IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C)
sahilmgandhi 18:6a4db94011d3 505 uint32_t RESERVED3; // Reserved for future use (offset 0x60)
sahilmgandhi 18:6a4db94011d3 506 __I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64)
sahilmgandhi 18:6a4db94011d3 507 __IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68)
sahilmgandhi 18:6a4db94011d3 508 __IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C)
sahilmgandhi 18:6a4db94011d3 509 __IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70)
sahilmgandhi 18:6a4db94011d3 510 __IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74)
sahilmgandhi 18:6a4db94011d3 511 __IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78)
sahilmgandhi 18:6a4db94011d3 512 __I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C)
sahilmgandhi 18:6a4db94011d3 513 __I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80)
sahilmgandhi 18:6a4db94011d3 514 __IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84)
sahilmgandhi 18:6a4db94011d3 515 __IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88)
sahilmgandhi 18:6a4db94011d3 516 __IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C)
sahilmgandhi 18:6a4db94011d3 517 __I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90)
sahilmgandhi 18:6a4db94011d3 518 uint32_t RESERVED4; // Reserved for future use (offset 0x94)
sahilmgandhi 18:6a4db94011d3 519 __IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98)
sahilmgandhi 18:6a4db94011d3 520 __I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C)
sahilmgandhi 18:6a4db94011d3 521 __I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0)
sahilmgandhi 18:6a4db94011d3 522 __IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4)
sahilmgandhi 18:6a4db94011d3 523 __IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8)
sahilmgandhi 18:6a4db94011d3 524 __IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC)
sahilmgandhi 18:6a4db94011d3 525 __IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0)
sahilmgandhi 18:6a4db94011d3 526 __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
sahilmgandhi 18:6a4db94011d3 527
sahilmgandhi 18:6a4db94011d3 528 } SMSC9220_TypeDef;
sahilmgandhi 18:6a4db94011d3 529
sahilmgandhi 18:6a4db94011d3 530 // SMSC9220 MAC Registers Indices
sahilmgandhi 18:6a4db94011d3 531 #define SMSC9220_MAC_CR 0x1
sahilmgandhi 18:6a4db94011d3 532 #define SMSC9220_MAC_ADDRH 0x2
sahilmgandhi 18:6a4db94011d3 533 #define SMSC9220_MAC_ADDRL 0x3
sahilmgandhi 18:6a4db94011d3 534 #define SMSC9220_MAC_HASHH 0x4
sahilmgandhi 18:6a4db94011d3 535 #define SMSC9220_MAC_HASHL 0x5
sahilmgandhi 18:6a4db94011d3 536 #define SMSC9220_MAC_MII_ACC 0x6
sahilmgandhi 18:6a4db94011d3 537 #define SMSC9220_MAC_MII_DATA 0x7
sahilmgandhi 18:6a4db94011d3 538 #define SMSC9220_MAC_FLOW 0x8
sahilmgandhi 18:6a4db94011d3 539 #define SMSC9220_MAC_VLAN1 0x9
sahilmgandhi 18:6a4db94011d3 540 #define SMSC9220_MAC_VLAN2 0xA
sahilmgandhi 18:6a4db94011d3 541 #define SMSC9220_MAC_WUFF 0xB
sahilmgandhi 18:6a4db94011d3 542 #define SMSC9220_MAC_WUCSR 0xC
sahilmgandhi 18:6a4db94011d3 543
sahilmgandhi 18:6a4db94011d3 544 // SMSC9220 PHY Registers Indices
sahilmgandhi 18:6a4db94011d3 545 #define SMSC9220_PHY_BCONTROL 0x0
sahilmgandhi 18:6a4db94011d3 546 #define SMSC9220_PHY_BSTATUS 0x1
sahilmgandhi 18:6a4db94011d3 547 #define SMSC9220_PHY_ID1 0x2
sahilmgandhi 18:6a4db94011d3 548 #define SMSC9220_PHY_ID2 0x3
sahilmgandhi 18:6a4db94011d3 549 #define SMSC9220_PHY_ANEG_ADV 0x4
sahilmgandhi 18:6a4db94011d3 550 #define SMSC9220_PHY_ANEG_LPA 0x5
sahilmgandhi 18:6a4db94011d3 551 #define SMSC9220_PHY_ANEG_EXP 0x6
sahilmgandhi 18:6a4db94011d3 552 #define SMSC9220_PHY_MCONTROL 0x17
sahilmgandhi 18:6a4db94011d3 553 #define SMSC9220_PHY_MSTATUS 0x18
sahilmgandhi 18:6a4db94011d3 554 #define SMSC9220_PHY_CSINDICATE 0x27
sahilmgandhi 18:6a4db94011d3 555 #define SMSC9220_PHY_INTSRC 0x29
sahilmgandhi 18:6a4db94011d3 556 #define SMSC9220_PHY_INTMASK 0x30
sahilmgandhi 18:6a4db94011d3 557 #define SMSC9220_PHY_CS 0x31
sahilmgandhi 18:6a4db94011d3 558
sahilmgandhi 18:6a4db94011d3 559 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 560 /* Peripheral memory map */
sahilmgandhi 18:6a4db94011d3 561 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 562
sahilmgandhi 18:6a4db94011d3 563 #define MPS2_SSP1_BASE (0x40020000ul) /* User SSP Base Address */
sahilmgandhi 18:6a4db94011d3 564 #define MPS2_SSP0_BASE (0x40021000ul) /* CLCD SSP Base Address */
sahilmgandhi 18:6a4db94011d3 565 #define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */
sahilmgandhi 18:6a4db94011d3 566 #define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */
sahilmgandhi 18:6a4db94011d3 567 #define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */
sahilmgandhi 18:6a4db94011d3 568 #define MPS2_SSP2_BASE (0x40025000ul) /* adc SSP Base Address */
sahilmgandhi 18:6a4db94011d3 569 #define MPS2_SSP3_BASE (0x40026000ul) /* Shield 0 SSP Base Address */
sahilmgandhi 18:6a4db94011d3 570 #define MPS2_SSP4_BASE (0x40027000ul) /* Shield 1 SSP Base Address */
sahilmgandhi 18:6a4db94011d3 571 #define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */
sahilmgandhi 18:6a4db94011d3 572 #define MPS2_SHIELD0_I2C_BASE (0x40029000ul) /* Shield 0 I2C Base Address */
sahilmgandhi 18:6a4db94011d3 573 #define MPS2_SHIELD1_I2C_BASE (0x4002A000ul) /* Shield 1 I2C Base Address */
sahilmgandhi 18:6a4db94011d3 574 #define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */
sahilmgandhi 18:6a4db94011d3 575
sahilmgandhi 18:6a4db94011d3 576 #ifdef CORTEX_M7
sahilmgandhi 18:6a4db94011d3 577 #define SMSC9220_BASE (0xA0000000ul) /* Ethernet SMSC9220 Base Address */
sahilmgandhi 18:6a4db94011d3 578 #else
sahilmgandhi 18:6a4db94011d3 579 #define SMSC9220_BASE (0x40200000ul) /* Ethernet SMSC9220 Base Address */
sahilmgandhi 18:6a4db94011d3 580 #endif
sahilmgandhi 18:6a4db94011d3 581
sahilmgandhi 18:6a4db94011d3 582 #define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */
sahilmgandhi 18:6a4db94011d3 583 #define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
sahilmgandhi 18:6a4db94011d3 584
sahilmgandhi 18:6a4db94011d3 585 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 586 /* Peripheral declaration */
sahilmgandhi 18:6a4db94011d3 587 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 588
sahilmgandhi 18:6a4db94011d3 589 #define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE )
sahilmgandhi 18:6a4db94011d3 590 #define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE )
sahilmgandhi 18:6a4db94011d3 591 #define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE )
sahilmgandhi 18:6a4db94011d3 592 #define MPS2_SHIELD0_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD0_I2C_BASE )
sahilmgandhi 18:6a4db94011d3 593 #define MPS2_SHIELD1_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD1_I2C_BASE )
sahilmgandhi 18:6a4db94011d3 594 #define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE )
sahilmgandhi 18:6a4db94011d3 595 #define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE )
sahilmgandhi 18:6a4db94011d3 596 #define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE )
sahilmgandhi 18:6a4db94011d3 597 #define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE )
sahilmgandhi 18:6a4db94011d3 598 #define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE )
sahilmgandhi 18:6a4db94011d3 599 #define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE )
sahilmgandhi 18:6a4db94011d3 600 #define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE )
sahilmgandhi 18:6a4db94011d3 601 #define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE )
sahilmgandhi 18:6a4db94011d3 602
sahilmgandhi 18:6a4db94011d3 603 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 604 /* General Function Definitions */
sahilmgandhi 18:6a4db94011d3 605 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 606
sahilmgandhi 18:6a4db94011d3 607
sahilmgandhi 18:6a4db94011d3 608 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 609 /* General MACRO Definitions */
sahilmgandhi 18:6a4db94011d3 610 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 611
sahilmgandhi 18:6a4db94011d3 612
sahilmgandhi 18:6a4db94011d3 613
sahilmgandhi 18:6a4db94011d3 614 #endif /* __SMM_MPS2_H */