Mouse code for the MacroRat
mbed-dev/targets/TARGET_ARM_SSG/TARGET_IOTSS/TARGET_IOTSS_BEID/device/CMSDK_BEID.h@46:b156ef445742, 2017-06-03 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sat Jun 03 00:22:44 2017 +0000
- Revision:
- 46:b156ef445742
- Parent:
- 18:6a4db94011d3
Final code for internal battlebot competition.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /* MPS2 CMSIS Library |
sahilmgandhi | 18:6a4db94011d3 | 2 | * |
sahilmgandhi | 18:6a4db94011d3 | 3 | * Copyright (c) 2006-2016 ARM Limited |
sahilmgandhi | 18:6a4db94011d3 | 4 | * All rights reserved. |
sahilmgandhi | 18:6a4db94011d3 | 5 | * |
sahilmgandhi | 18:6a4db94011d3 | 6 | * Redistribution and use in source and binary forms, with or without |
sahilmgandhi | 18:6a4db94011d3 | 7 | * modification, are permitted provided that the following conditions are met: |
sahilmgandhi | 18:6a4db94011d3 | 8 | * |
sahilmgandhi | 18:6a4db94011d3 | 9 | * 1. Redistributions of source code must retain the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 10 | * this list of conditions and the following disclaimer. |
sahilmgandhi | 18:6a4db94011d3 | 11 | * |
sahilmgandhi | 18:6a4db94011d3 | 12 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 13 | * this list of conditions and the following disclaimer in the documentation |
sahilmgandhi | 18:6a4db94011d3 | 14 | * and/or other materials provided with the distribution. |
sahilmgandhi | 18:6a4db94011d3 | 15 | * |
sahilmgandhi | 18:6a4db94011d3 | 16 | * 3. Neither the name of the copyright holder nor the names of its contributors |
sahilmgandhi | 18:6a4db94011d3 | 17 | * may be used to endorse or promote products derived from this software without |
sahilmgandhi | 18:6a4db94011d3 | 18 | * specific prior written permission. |
sahilmgandhi | 18:6a4db94011d3 | 19 | * |
sahilmgandhi | 18:6a4db94011d3 | 20 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
sahilmgandhi | 18:6a4db94011d3 | 21 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
sahilmgandhi | 18:6a4db94011d3 | 22 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
sahilmgandhi | 18:6a4db94011d3 | 23 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
sahilmgandhi | 18:6a4db94011d3 | 24 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
sahilmgandhi | 18:6a4db94011d3 | 25 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
sahilmgandhi | 18:6a4db94011d3 | 26 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
sahilmgandhi | 18:6a4db94011d3 | 27 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
sahilmgandhi | 18:6a4db94011d3 | 28 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
sahilmgandhi | 18:6a4db94011d3 | 29 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
sahilmgandhi | 18:6a4db94011d3 | 30 | * POSSIBILITY OF SUCH DAMAGE. |
sahilmgandhi | 18:6a4db94011d3 | 31 | ******************************************************************************* |
sahilmgandhi | 18:6a4db94011d3 | 32 | * @file CMSDK_BEID.h |
sahilmgandhi | 18:6a4db94011d3 | 33 | * @brief CMSIS Core Peripheral Access Layer Header File for |
sahilmgandhi | 18:6a4db94011d3 | 34 | * CMSDK_BEID Device |
sahilmgandhi | 18:6a4db94011d3 | 35 | * |
sahilmgandhi | 18:6a4db94011d3 | 36 | *******************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 37 | |
sahilmgandhi | 18:6a4db94011d3 | 38 | |
sahilmgandhi | 18:6a4db94011d3 | 39 | #ifndef CMSDK_BEID_H |
sahilmgandhi | 18:6a4db94011d3 | 40 | #define CMSDK_BEID_H |
sahilmgandhi | 18:6a4db94011d3 | 41 | |
sahilmgandhi | 18:6a4db94011d3 | 42 | #ifdef __cplusplus |
sahilmgandhi | 18:6a4db94011d3 | 43 | extern "C" { |
sahilmgandhi | 18:6a4db94011d3 | 44 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 45 | |
sahilmgandhi | 18:6a4db94011d3 | 46 | |
sahilmgandhi | 18:6a4db94011d3 | 47 | /* ------------------------- Interrupt Number Definition ------------------------ */ |
sahilmgandhi | 18:6a4db94011d3 | 48 | |
sahilmgandhi | 18:6a4db94011d3 | 49 | typedef enum IRQn |
sahilmgandhi | 18:6a4db94011d3 | 50 | { |
sahilmgandhi | 18:6a4db94011d3 | 51 | /* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */ |
sahilmgandhi | 18:6a4db94011d3 | 52 | NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 53 | HardFault_IRQn = -13, /* 3 HardFault Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 54 | MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 55 | BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 56 | UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 57 | SVCall_IRQn = -5, /* 11 SV Call Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 58 | DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 59 | PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 60 | SysTick_IRQn = -1, /* 15 System Tick Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 61 | |
sahilmgandhi | 18:6a4db94011d3 | 62 | /* ---------------------- CMSDK_CM3 Specific Interrupt Numbers ------------------ */ |
sahilmgandhi | 18:6a4db94011d3 | 63 | UART0_IRQn = 0, /* UART 0 RX and TX Combined Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 64 | Spare_IRQn = 1, /* Undefined */ |
sahilmgandhi | 18:6a4db94011d3 | 65 | UART1_IRQn = 2, /* UART 1 RX and TX Combined Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 66 | I2C0_IRQn = 3, /* I2C 0 Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 67 | I2C1_IRQn = 4, /* I2C 1 Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 68 | RTC_IRQn = 5, /* RTC Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 69 | PORT0_ALL_IRQn = 6, /* GPIO Port 0 combined Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 70 | PORT1_ALL_IRQn = 7, /* GPIO Port 1 combined Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 71 | TIMER0_IRQn = 8, /* TIMER 0 Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 72 | TIMER1_IRQn = 9, /* TIMER 1 Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 73 | DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 74 | SPI0_IRQn = 11, /* SPI 0 Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 75 | UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 76 | SPI1_IRQn = 13, /* SPI 1 Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 77 | RESERVED0_IRQn = 14, /* Reserved */ |
sahilmgandhi | 18:6a4db94011d3 | 78 | TSC_IRQn = 15, /* Touch Screen Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 79 | PORT01_0_IRQn = 16, /* GPIO Port 0 pin 0 Handler */ |
sahilmgandhi | 18:6a4db94011d3 | 80 | PORT01_1_IRQn = 17, /* GPIO Port 0 pin 1 Handler */ |
sahilmgandhi | 18:6a4db94011d3 | 81 | PORT01_2_IRQn = 18, /* GPIO Port 0 pin 2 Handler */ |
sahilmgandhi | 18:6a4db94011d3 | 82 | PORT01_3_IRQn = 19, /* GPIO Port 0 pin 3 Handler */ |
sahilmgandhi | 18:6a4db94011d3 | 83 | PORT01_4_IRQn = 20, /* GPIO Port 0 pin 4 Handler */ |
sahilmgandhi | 18:6a4db94011d3 | 84 | PORT01_5_IRQn = 21, /* GPIO Port 0 pin 5 Handler */ |
sahilmgandhi | 18:6a4db94011d3 | 85 | PORT01_6_IRQn = 22, /* GPIO Port 0 pin 6 Handler */ |
sahilmgandhi | 18:6a4db94011d3 | 86 | PORT01_7_IRQn = 23, /* GPIO Port 0 pin 7 Handler */ |
sahilmgandhi | 18:6a4db94011d3 | 87 | PORT01_8_IRQn = 24, /* GPIO Port 0 pin 8 Handler */ |
sahilmgandhi | 18:6a4db94011d3 | 88 | PORT01_9_IRQn = 25, /* GPIO Port 0 pin 9 Handler */ |
sahilmgandhi | 18:6a4db94011d3 | 89 | PORT01_10_IRQn = 26, /* GPIO Port 0 pin 10 Handler */ |
sahilmgandhi | 18:6a4db94011d3 | 90 | PORT01_11_IRQn = 27, /* GPIO Port 0 pin 11 Handler */ |
sahilmgandhi | 18:6a4db94011d3 | 91 | PORT01_12_IRQn = 28, /* GPIO Port 0 pin 12 Handler */ |
sahilmgandhi | 18:6a4db94011d3 | 92 | PORT01_13_IRQn = 29, /* GPIO Port 0 pin 13 Handler */ |
sahilmgandhi | 18:6a4db94011d3 | 93 | PORT01_14_IRQn = 30, /* GPIO Port 0 pin 14 Handler */ |
sahilmgandhi | 18:6a4db94011d3 | 94 | PORT01_15_IRQn = 31, /* GPIO Port 0 pin 15 Handler */ |
sahilmgandhi | 18:6a4db94011d3 | 95 | SYSERROR_IRQn = 32, /* System Error Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 96 | EFLASH_IRQn = 33, /* Embedded Flash Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 97 | RESERVED1_IRQn = 34, /* Reserved */ |
sahilmgandhi | 18:6a4db94011d3 | 98 | RESERVED2_IRQn = 35, /* Reserved */ |
sahilmgandhi | 18:6a4db94011d3 | 99 | RESERVED3_IRQn = 36, /* Reserved */ |
sahilmgandhi | 18:6a4db94011d3 | 100 | RESERVED4_IRQn = 37, /* Reserved */ |
sahilmgandhi | 18:6a4db94011d3 | 101 | RESERVED5_IRQn = 38, /* Reserved */ |
sahilmgandhi | 18:6a4db94011d3 | 102 | RESERVED6_IRQn = 39, /* Reserved */ |
sahilmgandhi | 18:6a4db94011d3 | 103 | RESERVED7_IRQn = 40, /* Reserved */ |
sahilmgandhi | 18:6a4db94011d3 | 104 | RESERVED8_IRQn = 41, /* Reserved */ |
sahilmgandhi | 18:6a4db94011d3 | 105 | PORT2_ALL_IRQn = 42, /* GPIO Port 2 combined Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 106 | PORT3_ALL_IRQn = 43, /* GPIO Port 3 combined Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 107 | TRNG_IRQn = 44, /* Random number generator Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 108 | UART2_IRQn = 45, /* UART 2 RX and TX Combined Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 109 | UART3_IRQn = 46, /* UART 3 RX and TX Combined Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 110 | ETHERNET_IRQn = 47, /* Ethernet interrupt t.b.a. */ |
sahilmgandhi | 18:6a4db94011d3 | 111 | I2S_IRQn = 48, /* I2S Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 112 | MPS2_SPI0_IRQn = 49, /* SPI Interrupt (spi header) */ |
sahilmgandhi | 18:6a4db94011d3 | 113 | MPS2_SPI1_IRQn = 50, /* SPI Interrupt (clcd) */ |
sahilmgandhi | 18:6a4db94011d3 | 114 | MPS2_SPI2_IRQn = 51, /* SPI Interrupt (spi 1 ADC replacement) */ |
sahilmgandhi | 18:6a4db94011d3 | 115 | MPS2_SPI3_IRQn = 52, /* SPI Interrupt (spi 0 shield 0 replacement) */ |
sahilmgandhi | 18:6a4db94011d3 | 116 | MPS2_SPI4_IRQn = 53 /* SPI Interrupt (shield 1) */ |
sahilmgandhi | 18:6a4db94011d3 | 117 | } IRQn_Type; |
sahilmgandhi | 18:6a4db94011d3 | 118 | |
sahilmgandhi | 18:6a4db94011d3 | 119 | |
sahilmgandhi | 18:6a4db94011d3 | 120 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 121 | /* ================ Processor and Core Peripheral Section ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 122 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 123 | |
sahilmgandhi | 18:6a4db94011d3 | 124 | /* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */ |
sahilmgandhi | 18:6a4db94011d3 | 125 | #define __BEID_REV 0x0201 /* Core revision r2p1 */ |
sahilmgandhi | 18:6a4db94011d3 | 126 | #define __MPU_PRESENT 1 /* MPU present or not */ |
sahilmgandhi | 18:6a4db94011d3 | 127 | #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */ |
sahilmgandhi | 18:6a4db94011d3 | 128 | #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ |
sahilmgandhi | 18:6a4db94011d3 | 129 | |
sahilmgandhi | 18:6a4db94011d3 | 130 | #include <core_cm3.h> /* Processor and core peripherals */ |
sahilmgandhi | 18:6a4db94011d3 | 131 | #include "system_CMSDK_BEID.h" /* System Header */ |
sahilmgandhi | 18:6a4db94011d3 | 132 | |
sahilmgandhi | 18:6a4db94011d3 | 133 | |
sahilmgandhi | 18:6a4db94011d3 | 134 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 135 | /* ================ Device Specific Peripheral Section ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 136 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 137 | |
sahilmgandhi | 18:6a4db94011d3 | 138 | /* ------------------- Start of section using anonymous unions ------------------ */ |
sahilmgandhi | 18:6a4db94011d3 | 139 | #if defined ( __CC_ARM ) |
sahilmgandhi | 18:6a4db94011d3 | 140 | #pragma push |
sahilmgandhi | 18:6a4db94011d3 | 141 | #pragma anon_unions |
sahilmgandhi | 18:6a4db94011d3 | 142 | #elif defined(__ICCARM__) |
sahilmgandhi | 18:6a4db94011d3 | 143 | #pragma language=extended |
sahilmgandhi | 18:6a4db94011d3 | 144 | #elif defined(__GNUC__) |
sahilmgandhi | 18:6a4db94011d3 | 145 | /* anonymous unions are enabled by default */ |
sahilmgandhi | 18:6a4db94011d3 | 146 | #elif defined(__TMS470__) |
sahilmgandhi | 18:6a4db94011d3 | 147 | /* anonymous unions are enabled by default */ |
sahilmgandhi | 18:6a4db94011d3 | 148 | #elif defined(__TASKING__) |
sahilmgandhi | 18:6a4db94011d3 | 149 | #pragma warning 586 |
sahilmgandhi | 18:6a4db94011d3 | 150 | #else |
sahilmgandhi | 18:6a4db94011d3 | 151 | #warning Not supported compiler type |
sahilmgandhi | 18:6a4db94011d3 | 152 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 153 | |
sahilmgandhi | 18:6a4db94011d3 | 154 | /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ |
sahilmgandhi | 18:6a4db94011d3 | 155 | typedef struct |
sahilmgandhi | 18:6a4db94011d3 | 156 | { |
sahilmgandhi | 18:6a4db94011d3 | 157 | __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ |
sahilmgandhi | 18:6a4db94011d3 | 158 | __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ |
sahilmgandhi | 18:6a4db94011d3 | 159 | __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ |
sahilmgandhi | 18:6a4db94011d3 | 160 | union { |
sahilmgandhi | 18:6a4db94011d3 | 161 | __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ |
sahilmgandhi | 18:6a4db94011d3 | 162 | __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ |
sahilmgandhi | 18:6a4db94011d3 | 163 | }; |
sahilmgandhi | 18:6a4db94011d3 | 164 | __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ |
sahilmgandhi | 18:6a4db94011d3 | 165 | |
sahilmgandhi | 18:6a4db94011d3 | 166 | } CMSDK_UART_TypeDef; |
sahilmgandhi | 18:6a4db94011d3 | 167 | |
sahilmgandhi | 18:6a4db94011d3 | 168 | /* CMSDK_UART DATA Register Definitions */ |
sahilmgandhi | 18:6a4db94011d3 | 169 | |
sahilmgandhi | 18:6a4db94011d3 | 170 | #define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */ |
sahilmgandhi | 18:6a4db94011d3 | 171 | #define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 172 | |
sahilmgandhi | 18:6a4db94011d3 | 173 | #define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */ |
sahilmgandhi | 18:6a4db94011d3 | 174 | #define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 175 | |
sahilmgandhi | 18:6a4db94011d3 | 176 | #define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */ |
sahilmgandhi | 18:6a4db94011d3 | 177 | #define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 178 | |
sahilmgandhi | 18:6a4db94011d3 | 179 | #define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */ |
sahilmgandhi | 18:6a4db94011d3 | 180 | #define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 181 | |
sahilmgandhi | 18:6a4db94011d3 | 182 | #define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */ |
sahilmgandhi | 18:6a4db94011d3 | 183 | #define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 184 | |
sahilmgandhi | 18:6a4db94011d3 | 185 | #define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */ |
sahilmgandhi | 18:6a4db94011d3 | 186 | #define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 187 | |
sahilmgandhi | 18:6a4db94011d3 | 188 | #define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */ |
sahilmgandhi | 18:6a4db94011d3 | 189 | #define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 190 | |
sahilmgandhi | 18:6a4db94011d3 | 191 | #define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */ |
sahilmgandhi | 18:6a4db94011d3 | 192 | #define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 193 | |
sahilmgandhi | 18:6a4db94011d3 | 194 | #define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */ |
sahilmgandhi | 18:6a4db94011d3 | 195 | #define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 196 | |
sahilmgandhi | 18:6a4db94011d3 | 197 | #define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */ |
sahilmgandhi | 18:6a4db94011d3 | 198 | #define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 199 | |
sahilmgandhi | 18:6a4db94011d3 | 200 | #define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */ |
sahilmgandhi | 18:6a4db94011d3 | 201 | #define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 202 | |
sahilmgandhi | 18:6a4db94011d3 | 203 | #define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */ |
sahilmgandhi | 18:6a4db94011d3 | 204 | #define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 205 | |
sahilmgandhi | 18:6a4db94011d3 | 206 | #define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */ |
sahilmgandhi | 18:6a4db94011d3 | 207 | #define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 208 | |
sahilmgandhi | 18:6a4db94011d3 | 209 | #define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */ |
sahilmgandhi | 18:6a4db94011d3 | 210 | #define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 211 | |
sahilmgandhi | 18:6a4db94011d3 | 212 | #define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */ |
sahilmgandhi | 18:6a4db94011d3 | 213 | #define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 214 | |
sahilmgandhi | 18:6a4db94011d3 | 215 | #define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */ |
sahilmgandhi | 18:6a4db94011d3 | 216 | #define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 217 | |
sahilmgandhi | 18:6a4db94011d3 | 218 | #define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */ |
sahilmgandhi | 18:6a4db94011d3 | 219 | #define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 220 | |
sahilmgandhi | 18:6a4db94011d3 | 221 | |
sahilmgandhi | 18:6a4db94011d3 | 222 | /*----------------------------- Timer (TIMER) -------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 223 | typedef struct |
sahilmgandhi | 18:6a4db94011d3 | 224 | { |
sahilmgandhi | 18:6a4db94011d3 | 225 | __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ |
sahilmgandhi | 18:6a4db94011d3 | 226 | __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ |
sahilmgandhi | 18:6a4db94011d3 | 227 | __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ |
sahilmgandhi | 18:6a4db94011d3 | 228 | union { |
sahilmgandhi | 18:6a4db94011d3 | 229 | __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ |
sahilmgandhi | 18:6a4db94011d3 | 230 | __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ |
sahilmgandhi | 18:6a4db94011d3 | 231 | }; |
sahilmgandhi | 18:6a4db94011d3 | 232 | |
sahilmgandhi | 18:6a4db94011d3 | 233 | } CMSDK_TIMER_TypeDef; |
sahilmgandhi | 18:6a4db94011d3 | 234 | |
sahilmgandhi | 18:6a4db94011d3 | 235 | /* CMSDK_TIMER CTRL Register Definitions */ |
sahilmgandhi | 18:6a4db94011d3 | 236 | |
sahilmgandhi | 18:6a4db94011d3 | 237 | #define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */ |
sahilmgandhi | 18:6a4db94011d3 | 238 | #define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 239 | |
sahilmgandhi | 18:6a4db94011d3 | 240 | #define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */ |
sahilmgandhi | 18:6a4db94011d3 | 241 | #define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 242 | |
sahilmgandhi | 18:6a4db94011d3 | 243 | #define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */ |
sahilmgandhi | 18:6a4db94011d3 | 244 | #define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 245 | |
sahilmgandhi | 18:6a4db94011d3 | 246 | #define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */ |
sahilmgandhi | 18:6a4db94011d3 | 247 | #define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 248 | |
sahilmgandhi | 18:6a4db94011d3 | 249 | #define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */ |
sahilmgandhi | 18:6a4db94011d3 | 250 | #define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 251 | |
sahilmgandhi | 18:6a4db94011d3 | 252 | #define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */ |
sahilmgandhi | 18:6a4db94011d3 | 253 | #define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 254 | |
sahilmgandhi | 18:6a4db94011d3 | 255 | #define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */ |
sahilmgandhi | 18:6a4db94011d3 | 256 | #define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */ |
sahilmgandhi | 18:6a4db94011d3 | 257 | |
sahilmgandhi | 18:6a4db94011d3 | 258 | #define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */ |
sahilmgandhi | 18:6a4db94011d3 | 259 | #define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 260 | |
sahilmgandhi | 18:6a4db94011d3 | 261 | |
sahilmgandhi | 18:6a4db94011d3 | 262 | /*------------- Timer (TIM) --------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 263 | typedef struct |
sahilmgandhi | 18:6a4db94011d3 | 264 | { |
sahilmgandhi | 18:6a4db94011d3 | 265 | __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ |
sahilmgandhi | 18:6a4db94011d3 | 266 | __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ |
sahilmgandhi | 18:6a4db94011d3 | 267 | __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ |
sahilmgandhi | 18:6a4db94011d3 | 268 | __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ |
sahilmgandhi | 18:6a4db94011d3 | 269 | __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ |
sahilmgandhi | 18:6a4db94011d3 | 270 | __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ |
sahilmgandhi | 18:6a4db94011d3 | 271 | __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ |
sahilmgandhi | 18:6a4db94011d3 | 272 | uint32_t RESERVED0; |
sahilmgandhi | 18:6a4db94011d3 | 273 | __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ |
sahilmgandhi | 18:6a4db94011d3 | 274 | __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ |
sahilmgandhi | 18:6a4db94011d3 | 275 | __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ |
sahilmgandhi | 18:6a4db94011d3 | 276 | __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ |
sahilmgandhi | 18:6a4db94011d3 | 277 | __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ |
sahilmgandhi | 18:6a4db94011d3 | 278 | __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ |
sahilmgandhi | 18:6a4db94011d3 | 279 | __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ |
sahilmgandhi | 18:6a4db94011d3 | 280 | uint32_t RESERVED1[945]; |
sahilmgandhi | 18:6a4db94011d3 | 281 | __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ |
sahilmgandhi | 18:6a4db94011d3 | 282 | __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */ |
sahilmgandhi | 18:6a4db94011d3 | 283 | } CMSDK_DUALTIMER_BOTH_TypeDef; |
sahilmgandhi | 18:6a4db94011d3 | 284 | |
sahilmgandhi | 18:6a4db94011d3 | 285 | #define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */ |
sahilmgandhi | 18:6a4db94011d3 | 286 | #define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 287 | |
sahilmgandhi | 18:6a4db94011d3 | 288 | #define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */ |
sahilmgandhi | 18:6a4db94011d3 | 289 | #define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 290 | |
sahilmgandhi | 18:6a4db94011d3 | 291 | #define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */ |
sahilmgandhi | 18:6a4db94011d3 | 292 | #define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 293 | |
sahilmgandhi | 18:6a4db94011d3 | 294 | #define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */ |
sahilmgandhi | 18:6a4db94011d3 | 295 | #define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 296 | |
sahilmgandhi | 18:6a4db94011d3 | 297 | #define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */ |
sahilmgandhi | 18:6a4db94011d3 | 298 | #define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 299 | |
sahilmgandhi | 18:6a4db94011d3 | 300 | #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */ |
sahilmgandhi | 18:6a4db94011d3 | 301 | #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 302 | |
sahilmgandhi | 18:6a4db94011d3 | 303 | #define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */ |
sahilmgandhi | 18:6a4db94011d3 | 304 | #define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 305 | |
sahilmgandhi | 18:6a4db94011d3 | 306 | #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */ |
sahilmgandhi | 18:6a4db94011d3 | 307 | #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 308 | |
sahilmgandhi | 18:6a4db94011d3 | 309 | #define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */ |
sahilmgandhi | 18:6a4db94011d3 | 310 | #define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 311 | |
sahilmgandhi | 18:6a4db94011d3 | 312 | #define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */ |
sahilmgandhi | 18:6a4db94011d3 | 313 | #define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 314 | |
sahilmgandhi | 18:6a4db94011d3 | 315 | #define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */ |
sahilmgandhi | 18:6a4db94011d3 | 316 | #define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 317 | |
sahilmgandhi | 18:6a4db94011d3 | 318 | #define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */ |
sahilmgandhi | 18:6a4db94011d3 | 319 | #define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 320 | |
sahilmgandhi | 18:6a4db94011d3 | 321 | #define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */ |
sahilmgandhi | 18:6a4db94011d3 | 322 | #define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 323 | |
sahilmgandhi | 18:6a4db94011d3 | 324 | #define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */ |
sahilmgandhi | 18:6a4db94011d3 | 325 | #define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 326 | |
sahilmgandhi | 18:6a4db94011d3 | 327 | #define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */ |
sahilmgandhi | 18:6a4db94011d3 | 328 | #define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 329 | |
sahilmgandhi | 18:6a4db94011d3 | 330 | #define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */ |
sahilmgandhi | 18:6a4db94011d3 | 331 | #define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 332 | |
sahilmgandhi | 18:6a4db94011d3 | 333 | #define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */ |
sahilmgandhi | 18:6a4db94011d3 | 334 | #define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 335 | |
sahilmgandhi | 18:6a4db94011d3 | 336 | #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */ |
sahilmgandhi | 18:6a4db94011d3 | 337 | #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 338 | |
sahilmgandhi | 18:6a4db94011d3 | 339 | #define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */ |
sahilmgandhi | 18:6a4db94011d3 | 340 | #define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 341 | |
sahilmgandhi | 18:6a4db94011d3 | 342 | #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */ |
sahilmgandhi | 18:6a4db94011d3 | 343 | #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 344 | |
sahilmgandhi | 18:6a4db94011d3 | 345 | #define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */ |
sahilmgandhi | 18:6a4db94011d3 | 346 | #define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 347 | |
sahilmgandhi | 18:6a4db94011d3 | 348 | #define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */ |
sahilmgandhi | 18:6a4db94011d3 | 349 | #define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 350 | |
sahilmgandhi | 18:6a4db94011d3 | 351 | #define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */ |
sahilmgandhi | 18:6a4db94011d3 | 352 | #define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 353 | |
sahilmgandhi | 18:6a4db94011d3 | 354 | #define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */ |
sahilmgandhi | 18:6a4db94011d3 | 355 | #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 356 | |
sahilmgandhi | 18:6a4db94011d3 | 357 | |
sahilmgandhi | 18:6a4db94011d3 | 358 | typedef struct |
sahilmgandhi | 18:6a4db94011d3 | 359 | { |
sahilmgandhi | 18:6a4db94011d3 | 360 | __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ |
sahilmgandhi | 18:6a4db94011d3 | 361 | __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ |
sahilmgandhi | 18:6a4db94011d3 | 362 | __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ |
sahilmgandhi | 18:6a4db94011d3 | 363 | __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ |
sahilmgandhi | 18:6a4db94011d3 | 364 | __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ |
sahilmgandhi | 18:6a4db94011d3 | 365 | __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ |
sahilmgandhi | 18:6a4db94011d3 | 366 | __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */ |
sahilmgandhi | 18:6a4db94011d3 | 367 | } CMSDK_DUALTIMER_SINGLE_TypeDef; |
sahilmgandhi | 18:6a4db94011d3 | 368 | |
sahilmgandhi | 18:6a4db94011d3 | 369 | #define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */ |
sahilmgandhi | 18:6a4db94011d3 | 370 | #define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 371 | |
sahilmgandhi | 18:6a4db94011d3 | 372 | #define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */ |
sahilmgandhi | 18:6a4db94011d3 | 373 | #define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 374 | |
sahilmgandhi | 18:6a4db94011d3 | 375 | #define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */ |
sahilmgandhi | 18:6a4db94011d3 | 376 | #define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 377 | |
sahilmgandhi | 18:6a4db94011d3 | 378 | #define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */ |
sahilmgandhi | 18:6a4db94011d3 | 379 | #define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 380 | |
sahilmgandhi | 18:6a4db94011d3 | 381 | #define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */ |
sahilmgandhi | 18:6a4db94011d3 | 382 | #define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 383 | |
sahilmgandhi | 18:6a4db94011d3 | 384 | #define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */ |
sahilmgandhi | 18:6a4db94011d3 | 385 | #define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 386 | |
sahilmgandhi | 18:6a4db94011d3 | 387 | #define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */ |
sahilmgandhi | 18:6a4db94011d3 | 388 | #define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 389 | |
sahilmgandhi | 18:6a4db94011d3 | 390 | #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */ |
sahilmgandhi | 18:6a4db94011d3 | 391 | #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 392 | |
sahilmgandhi | 18:6a4db94011d3 | 393 | #define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */ |
sahilmgandhi | 18:6a4db94011d3 | 394 | #define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 395 | |
sahilmgandhi | 18:6a4db94011d3 | 396 | #define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */ |
sahilmgandhi | 18:6a4db94011d3 | 397 | #define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 398 | |
sahilmgandhi | 18:6a4db94011d3 | 399 | #define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */ |
sahilmgandhi | 18:6a4db94011d3 | 400 | #define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 401 | |
sahilmgandhi | 18:6a4db94011d3 | 402 | #define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */ |
sahilmgandhi | 18:6a4db94011d3 | 403 | #define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 404 | |
sahilmgandhi | 18:6a4db94011d3 | 405 | |
sahilmgandhi | 18:6a4db94011d3 | 406 | /*-------------------- General Purpose Input Output (GPIO) -------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 407 | typedef struct |
sahilmgandhi | 18:6a4db94011d3 | 408 | { |
sahilmgandhi | 18:6a4db94011d3 | 409 | __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ |
sahilmgandhi | 18:6a4db94011d3 | 410 | __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ |
sahilmgandhi | 18:6a4db94011d3 | 411 | uint32_t RESERVED0[2]; |
sahilmgandhi | 18:6a4db94011d3 | 412 | __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ |
sahilmgandhi | 18:6a4db94011d3 | 413 | __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ |
sahilmgandhi | 18:6a4db94011d3 | 414 | __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ |
sahilmgandhi | 18:6a4db94011d3 | 415 | __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ |
sahilmgandhi | 18:6a4db94011d3 | 416 | __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ |
sahilmgandhi | 18:6a4db94011d3 | 417 | __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ |
sahilmgandhi | 18:6a4db94011d3 | 418 | __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ |
sahilmgandhi | 18:6a4db94011d3 | 419 | __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ |
sahilmgandhi | 18:6a4db94011d3 | 420 | __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ |
sahilmgandhi | 18:6a4db94011d3 | 421 | __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ |
sahilmgandhi | 18:6a4db94011d3 | 422 | union { |
sahilmgandhi | 18:6a4db94011d3 | 423 | __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ |
sahilmgandhi | 18:6a4db94011d3 | 424 | __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */ |
sahilmgandhi | 18:6a4db94011d3 | 425 | }; |
sahilmgandhi | 18:6a4db94011d3 | 426 | uint32_t RESERVED1[241]; |
sahilmgandhi | 18:6a4db94011d3 | 427 | __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ |
sahilmgandhi | 18:6a4db94011d3 | 428 | __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ |
sahilmgandhi | 18:6a4db94011d3 | 429 | } CMSDK_GPIO_TypeDef; |
sahilmgandhi | 18:6a4db94011d3 | 430 | |
sahilmgandhi | 18:6a4db94011d3 | 431 | #define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */ |
sahilmgandhi | 18:6a4db94011d3 | 432 | #define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 433 | |
sahilmgandhi | 18:6a4db94011d3 | 434 | #define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */ |
sahilmgandhi | 18:6a4db94011d3 | 435 | #define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 436 | |
sahilmgandhi | 18:6a4db94011d3 | 437 | #define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ |
sahilmgandhi | 18:6a4db94011d3 | 438 | #define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 439 | |
sahilmgandhi | 18:6a4db94011d3 | 440 | #define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ |
sahilmgandhi | 18:6a4db94011d3 | 441 | #define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 442 | |
sahilmgandhi | 18:6a4db94011d3 | 443 | #define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ |
sahilmgandhi | 18:6a4db94011d3 | 444 | #define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 445 | |
sahilmgandhi | 18:6a4db94011d3 | 446 | #define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ |
sahilmgandhi | 18:6a4db94011d3 | 447 | #define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 448 | |
sahilmgandhi | 18:6a4db94011d3 | 449 | #define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ |
sahilmgandhi | 18:6a4db94011d3 | 450 | #define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 451 | |
sahilmgandhi | 18:6a4db94011d3 | 452 | #define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ |
sahilmgandhi | 18:6a4db94011d3 | 453 | #define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 454 | |
sahilmgandhi | 18:6a4db94011d3 | 455 | #define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ |
sahilmgandhi | 18:6a4db94011d3 | 456 | #define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 457 | |
sahilmgandhi | 18:6a4db94011d3 | 458 | #define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ |
sahilmgandhi | 18:6a4db94011d3 | 459 | #define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 460 | |
sahilmgandhi | 18:6a4db94011d3 | 461 | #define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ |
sahilmgandhi | 18:6a4db94011d3 | 462 | #define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 463 | |
sahilmgandhi | 18:6a4db94011d3 | 464 | #define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ |
sahilmgandhi | 18:6a4db94011d3 | 465 | #define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 466 | |
sahilmgandhi | 18:6a4db94011d3 | 467 | #define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */ |
sahilmgandhi | 18:6a4db94011d3 | 468 | #define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 469 | |
sahilmgandhi | 18:6a4db94011d3 | 470 | #define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */ |
sahilmgandhi | 18:6a4db94011d3 | 471 | #define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 472 | |
sahilmgandhi | 18:6a4db94011d3 | 473 | #define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */ |
sahilmgandhi | 18:6a4db94011d3 | 474 | #define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 475 | |
sahilmgandhi | 18:6a4db94011d3 | 476 | #define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */ |
sahilmgandhi | 18:6a4db94011d3 | 477 | #define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 478 | |
sahilmgandhi | 18:6a4db94011d3 | 479 | |
sahilmgandhi | 18:6a4db94011d3 | 480 | /*------------- System Control (SYSCON) --------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 481 | typedef struct |
sahilmgandhi | 18:6a4db94011d3 | 482 | { |
sahilmgandhi | 18:6a4db94011d3 | 483 | __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ |
sahilmgandhi | 18:6a4db94011d3 | 484 | __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ |
sahilmgandhi | 18:6a4db94011d3 | 485 | __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ |
sahilmgandhi | 18:6a4db94011d3 | 486 | __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ |
sahilmgandhi | 18:6a4db94011d3 | 487 | __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */ |
sahilmgandhi | 18:6a4db94011d3 | 488 | uint32_t RESERVED0[3]; |
sahilmgandhi | 18:6a4db94011d3 | 489 | __IO uint32_t AHBPER0SET; /* Offset: 0x020 (R/W)AHB peripheral access control set */ |
sahilmgandhi | 18:6a4db94011d3 | 490 | __IO uint32_t AHBPER0CLR; /* Offset: 0x024 (R/W)AHB peripheral access control clear */ |
sahilmgandhi | 18:6a4db94011d3 | 491 | uint32_t RESERVED1[2]; |
sahilmgandhi | 18:6a4db94011d3 | 492 | __IO uint32_t APBPER0SET; /* Offset: 0x030 (R/W)APB peripheral access control set */ |
sahilmgandhi | 18:6a4db94011d3 | 493 | __IO uint32_t APBPER0CLR; /* Offset: 0x034 (R/W)APB peripheral access control clear */ |
sahilmgandhi | 18:6a4db94011d3 | 494 | uint32_t RESERVED2[2]; |
sahilmgandhi | 18:6a4db94011d3 | 495 | __IO uint32_t MAINCLK; /* Offset: 0x040 (R/W) Main Clock Control Register */ |
sahilmgandhi | 18:6a4db94011d3 | 496 | __IO uint32_t AUXCLK; /* Offset: 0x044 (R/W) Auxiliary / RTC Control Register */ |
sahilmgandhi | 18:6a4db94011d3 | 497 | __IO uint32_t PLLCTRL; /* Offset: 0x048 (R/W) PLL Control Register */ |
sahilmgandhi | 18:6a4db94011d3 | 498 | __IO uint32_t PLLSTATUS; /* Offset: 0x04C (R/W) PLL Status Register */ |
sahilmgandhi | 18:6a4db94011d3 | 499 | __IO uint32_t SLEEPCFG; /* Offset: 0x050 (R/W) Sleep Control Register */ |
sahilmgandhi | 18:6a4db94011d3 | 500 | __IO uint32_t FLASHAUXCFG; /* Offset: 0x054 (R/W) Flash auxiliary settings Control Register */ |
sahilmgandhi | 18:6a4db94011d3 | 501 | uint32_t RESERVED3[10]; |
sahilmgandhi | 18:6a4db94011d3 | 502 | __IO uint32_t AHBCLKCFG0SET; /* Offset: 0x080 (R/W) AHB Peripheral Clock set in Active state */ |
sahilmgandhi | 18:6a4db94011d3 | 503 | __IO uint32_t AHBCLKCFG0CLR; /* Offset: 0x084 (R/W) AHB Peripheral Clock clear in Active state */ |
sahilmgandhi | 18:6a4db94011d3 | 504 | __IO uint32_t AHBCLKCFG1SET; /* Offset: 0x088 (R/W) AHB Peripheral Clock set in Sleep state */ |
sahilmgandhi | 18:6a4db94011d3 | 505 | __IO uint32_t AHBCLKCFG1CLR; /* Offset: 0x08C (R/W) AHB Peripheral Clock clear in Sleep state */ |
sahilmgandhi | 18:6a4db94011d3 | 506 | __IO uint32_t AHBCLKCFG2SET; /* Offset: 0x090 (R/W) AHB Peripheral Clock set in Deep Sleep state */ |
sahilmgandhi | 18:6a4db94011d3 | 507 | __IO uint32_t AHBCLKCFG2CLR; /* Offset: 0x094 (R/W) AHB Peripheral Clock clear in Deep Sleep state */ |
sahilmgandhi | 18:6a4db94011d3 | 508 | uint32_t RESERVED4[2]; |
sahilmgandhi | 18:6a4db94011d3 | 509 | __IO uint32_t APBCLKCFG0SET; /* Offset: 0x0A0 (R/W) APB Peripheral Clock set in Active state */ |
sahilmgandhi | 18:6a4db94011d3 | 510 | __IO uint32_t APBCLKCFG0CLR; /* Offset: 0x0A4 (R/W) APB Peripheral Clock clear in Active state */ |
sahilmgandhi | 18:6a4db94011d3 | 511 | __IO uint32_t APBCLKCFG1SET; /* Offset: 0x0A8 (R/W) APB Peripheral Clock set in Sleep state */ |
sahilmgandhi | 18:6a4db94011d3 | 512 | __IO uint32_t APBCLKCFG1CLR; /* Offset: 0x0AC (R/W) APB Peripheral Clock clear in Sleep state */ |
sahilmgandhi | 18:6a4db94011d3 | 513 | __IO uint32_t APBCLKCFG2SET; /* Offset: 0x0B0 (R/W) APB Peripheral Clock set in Deep Sleep state */ |
sahilmgandhi | 18:6a4db94011d3 | 514 | __IO uint32_t APBCLKCFG2CLR; /* Offset: 0x0B4 (R/W) APB Peripheral Clock clear in Deep Sleep state */ |
sahilmgandhi | 18:6a4db94011d3 | 515 | uint32_t RESERVED5[2]; |
sahilmgandhi | 18:6a4db94011d3 | 516 | __IO uint32_t AHBPRST0SET; /* Offset: 0x0C0 (R/W) AHB Peripheral reset select set */ |
sahilmgandhi | 18:6a4db94011d3 | 517 | __IO uint32_t AHBPRST0CLR; /* Offset: 0x0C4 (R/W) AHB Peripheral reset select clear */ |
sahilmgandhi | 18:6a4db94011d3 | 518 | __IO uint32_t APBPRST0SET; /* Offset: 0x0C8 (R/W) APB Peripheral reset select set */ |
sahilmgandhi | 18:6a4db94011d3 | 519 | __IO uint32_t APBPRST0CLR; /* Offset: 0x0CC (R/W) APB Peripheral reset select clear */ |
sahilmgandhi | 18:6a4db94011d3 | 520 | __IO uint32_t PWRDNCFG0SET; /* Offset: 0x0D0 (R/W) AHB Power down sleep wakeup source set */ |
sahilmgandhi | 18:6a4db94011d3 | 521 | __IO uint32_t PWRDNCFG0CLR; /* Offset: 0x0D4 (R/W) AHB Power down sleep wakeup source clear */ |
sahilmgandhi | 18:6a4db94011d3 | 522 | __IO uint32_t PWRDNCFG1SET; /* Offset: 0x0D8 (R/W) APB Power down sleep wakeup source set */ |
sahilmgandhi | 18:6a4db94011d3 | 523 | __IO uint32_t PWRDNCFG1CLR; /* Offset: 0x0DC (R/W) APB Power down sleep wakeup source clear */ |
sahilmgandhi | 18:6a4db94011d3 | 524 | __O uint32_t RTCRESET; /* Offset: 0x0E0 ( /W) RTC reset */ |
sahilmgandhi | 18:6a4db94011d3 | 525 | __IO uint32_t EVENTCFG; /* Offset: 0x0E4 (R/W) Event interface Control Register */ |
sahilmgandhi | 18:6a4db94011d3 | 526 | uint32_t RESERVED6[2]; |
sahilmgandhi | 18:6a4db94011d3 | 527 | __IO uint32_t PWROVRIDE0; /* Offset: 0x0F0 (R/W) SRAM Power control overide */ |
sahilmgandhi | 18:6a4db94011d3 | 528 | __IO uint32_t PWROVRIDE1; /* Offset: 0x0F4 (R/W) Embedded Flash Power control overide */ |
sahilmgandhi | 18:6a4db94011d3 | 529 | __I uint32_t MEMORYSTATUS; /* Offset: 0x0F8 (R/ ) Memory Status Register */ |
sahilmgandhi | 18:6a4db94011d3 | 530 | uint32_t RESERVED7[1]; |
sahilmgandhi | 18:6a4db94011d3 | 531 | __IO uint32_t GPIOPADCFG0; /* Offset: 0x100 (R/W) IO pad settings */ |
sahilmgandhi | 18:6a4db94011d3 | 532 | __IO uint32_t GPIOPADCFG1; /* Offset: 0x104 (R/W) IO pad settings */ |
sahilmgandhi | 18:6a4db94011d3 | 533 | __IO uint32_t TESTMODECFG; /* Offset: 0x108 (R/W) Testmode boot bypass */ |
sahilmgandhi | 18:6a4db94011d3 | 534 | } CMSDK_SYSCON_TypeDef; |
sahilmgandhi | 18:6a4db94011d3 | 535 | |
sahilmgandhi | 18:6a4db94011d3 | 536 | #define CMSDK_SYSCON_REMAP_Pos 0 |
sahilmgandhi | 18:6a4db94011d3 | 537 | #define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 538 | |
sahilmgandhi | 18:6a4db94011d3 | 539 | #define CMSDK_SYSCON_PMUCTRL_EN_Pos 0 |
sahilmgandhi | 18:6a4db94011d3 | 540 | #define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 541 | |
sahilmgandhi | 18:6a4db94011d3 | 542 | #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0 |
sahilmgandhi | 18:6a4db94011d3 | 543 | #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 544 | |
sahilmgandhi | 18:6a4db94011d3 | 545 | #define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24 |
sahilmgandhi | 18:6a4db94011d3 | 546 | #define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 547 | |
sahilmgandhi | 18:6a4db94011d3 | 548 | #define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16 |
sahilmgandhi | 18:6a4db94011d3 | 549 | #define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 550 | |
sahilmgandhi | 18:6a4db94011d3 | 551 | #define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8 |
sahilmgandhi | 18:6a4db94011d3 | 552 | #define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 553 | |
sahilmgandhi | 18:6a4db94011d3 | 554 | #define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0 |
sahilmgandhi | 18:6a4db94011d3 | 555 | #define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 556 | |
sahilmgandhi | 18:6a4db94011d3 | 557 | #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0 |
sahilmgandhi | 18:6a4db94011d3 | 558 | #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 559 | |
sahilmgandhi | 18:6a4db94011d3 | 560 | #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1 |
sahilmgandhi | 18:6a4db94011d3 | 561 | #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 562 | |
sahilmgandhi | 18:6a4db94011d3 | 563 | #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2 |
sahilmgandhi | 18:6a4db94011d3 | 564 | #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 565 | |
sahilmgandhi | 18:6a4db94011d3 | 566 | |
sahilmgandhi | 18:6a4db94011d3 | 567 | /*------------- PL230 uDMA (PL230) --------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 568 | typedef struct |
sahilmgandhi | 18:6a4db94011d3 | 569 | { |
sahilmgandhi | 18:6a4db94011d3 | 570 | __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ |
sahilmgandhi | 18:6a4db94011d3 | 571 | __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ |
sahilmgandhi | 18:6a4db94011d3 | 572 | __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ |
sahilmgandhi | 18:6a4db94011d3 | 573 | __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ |
sahilmgandhi | 18:6a4db94011d3 | 574 | __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ |
sahilmgandhi | 18:6a4db94011d3 | 575 | __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ |
sahilmgandhi | 18:6a4db94011d3 | 576 | __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ |
sahilmgandhi | 18:6a4db94011d3 | 577 | __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ |
sahilmgandhi | 18:6a4db94011d3 | 578 | __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ |
sahilmgandhi | 18:6a4db94011d3 | 579 | __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ |
sahilmgandhi | 18:6a4db94011d3 | 580 | __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ |
sahilmgandhi | 18:6a4db94011d3 | 581 | __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ |
sahilmgandhi | 18:6a4db94011d3 | 582 | __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ |
sahilmgandhi | 18:6a4db94011d3 | 583 | __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ |
sahilmgandhi | 18:6a4db94011d3 | 584 | __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ |
sahilmgandhi | 18:6a4db94011d3 | 585 | __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ |
sahilmgandhi | 18:6a4db94011d3 | 586 | uint32_t RESERVED0[3]; |
sahilmgandhi | 18:6a4db94011d3 | 587 | __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */ |
sahilmgandhi | 18:6a4db94011d3 | 588 | |
sahilmgandhi | 18:6a4db94011d3 | 589 | } CMSDK_PL230_TypeDef; |
sahilmgandhi | 18:6a4db94011d3 | 590 | |
sahilmgandhi | 18:6a4db94011d3 | 591 | #define PL230_DMA_CHNL_BITS 0 |
sahilmgandhi | 18:6a4db94011d3 | 592 | |
sahilmgandhi | 18:6a4db94011d3 | 593 | #define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */ |
sahilmgandhi | 18:6a4db94011d3 | 594 | #define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 595 | |
sahilmgandhi | 18:6a4db94011d3 | 596 | #define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */ |
sahilmgandhi | 18:6a4db94011d3 | 597 | #define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 598 | |
sahilmgandhi | 18:6a4db94011d3 | 599 | #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */ |
sahilmgandhi | 18:6a4db94011d3 | 600 | #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 601 | |
sahilmgandhi | 18:6a4db94011d3 | 602 | #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */ |
sahilmgandhi | 18:6a4db94011d3 | 603 | #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 604 | |
sahilmgandhi | 18:6a4db94011d3 | 605 | #define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */ |
sahilmgandhi | 18:6a4db94011d3 | 606 | #define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 607 | |
sahilmgandhi | 18:6a4db94011d3 | 608 | #define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */ |
sahilmgandhi | 18:6a4db94011d3 | 609 | #define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 610 | |
sahilmgandhi | 18:6a4db94011d3 | 611 | #define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */ |
sahilmgandhi | 18:6a4db94011d3 | 612 | #define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 613 | |
sahilmgandhi | 18:6a4db94011d3 | 614 | #define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */ |
sahilmgandhi | 18:6a4db94011d3 | 615 | #define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 616 | |
sahilmgandhi | 18:6a4db94011d3 | 617 | #define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */ |
sahilmgandhi | 18:6a4db94011d3 | 618 | #define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 619 | |
sahilmgandhi | 18:6a4db94011d3 | 620 | #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */ |
sahilmgandhi | 18:6a4db94011d3 | 621 | #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 622 | |
sahilmgandhi | 18:6a4db94011d3 | 623 | #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */ |
sahilmgandhi | 18:6a4db94011d3 | 624 | #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 625 | |
sahilmgandhi | 18:6a4db94011d3 | 626 | #define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */ |
sahilmgandhi | 18:6a4db94011d3 | 627 | #define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 628 | |
sahilmgandhi | 18:6a4db94011d3 | 629 | #define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */ |
sahilmgandhi | 18:6a4db94011d3 | 630 | #define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 631 | |
sahilmgandhi | 18:6a4db94011d3 | 632 | #define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */ |
sahilmgandhi | 18:6a4db94011d3 | 633 | #define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 634 | |
sahilmgandhi | 18:6a4db94011d3 | 635 | #define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */ |
sahilmgandhi | 18:6a4db94011d3 | 636 | #define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 637 | |
sahilmgandhi | 18:6a4db94011d3 | 638 | #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */ |
sahilmgandhi | 18:6a4db94011d3 | 639 | #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 640 | |
sahilmgandhi | 18:6a4db94011d3 | 641 | #define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */ |
sahilmgandhi | 18:6a4db94011d3 | 642 | #define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 643 | |
sahilmgandhi | 18:6a4db94011d3 | 644 | #define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */ |
sahilmgandhi | 18:6a4db94011d3 | 645 | #define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 646 | |
sahilmgandhi | 18:6a4db94011d3 | 647 | #define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */ |
sahilmgandhi | 18:6a4db94011d3 | 648 | #define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 649 | |
sahilmgandhi | 18:6a4db94011d3 | 650 | #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */ |
sahilmgandhi | 18:6a4db94011d3 | 651 | #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 652 | |
sahilmgandhi | 18:6a4db94011d3 | 653 | #define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */ |
sahilmgandhi | 18:6a4db94011d3 | 654 | #define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 655 | |
sahilmgandhi | 18:6a4db94011d3 | 656 | #define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */ |
sahilmgandhi | 18:6a4db94011d3 | 657 | #define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 658 | |
sahilmgandhi | 18:6a4db94011d3 | 659 | #define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */ |
sahilmgandhi | 18:6a4db94011d3 | 660 | #define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 661 | |
sahilmgandhi | 18:6a4db94011d3 | 662 | |
sahilmgandhi | 18:6a4db94011d3 | 663 | /*------------------- Watchdog ----------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 664 | typedef struct |
sahilmgandhi | 18:6a4db94011d3 | 665 | { |
sahilmgandhi | 18:6a4db94011d3 | 666 | |
sahilmgandhi | 18:6a4db94011d3 | 667 | __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ |
sahilmgandhi | 18:6a4db94011d3 | 668 | __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ |
sahilmgandhi | 18:6a4db94011d3 | 669 | __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ |
sahilmgandhi | 18:6a4db94011d3 | 670 | __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ |
sahilmgandhi | 18:6a4db94011d3 | 671 | __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ |
sahilmgandhi | 18:6a4db94011d3 | 672 | __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ |
sahilmgandhi | 18:6a4db94011d3 | 673 | uint32_t RESERVED0[762]; |
sahilmgandhi | 18:6a4db94011d3 | 674 | __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ |
sahilmgandhi | 18:6a4db94011d3 | 675 | uint32_t RESERVED1[191]; |
sahilmgandhi | 18:6a4db94011d3 | 676 | __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ |
sahilmgandhi | 18:6a4db94011d3 | 677 | __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ |
sahilmgandhi | 18:6a4db94011d3 | 678 | }CMSDK_WATCHDOG_TypeDef; |
sahilmgandhi | 18:6a4db94011d3 | 679 | |
sahilmgandhi | 18:6a4db94011d3 | 680 | #define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */ |
sahilmgandhi | 18:6a4db94011d3 | 681 | #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 682 | |
sahilmgandhi | 18:6a4db94011d3 | 683 | #define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */ |
sahilmgandhi | 18:6a4db94011d3 | 684 | #define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 685 | |
sahilmgandhi | 18:6a4db94011d3 | 686 | #define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */ |
sahilmgandhi | 18:6a4db94011d3 | 687 | #define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 688 | |
sahilmgandhi | 18:6a4db94011d3 | 689 | #define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */ |
sahilmgandhi | 18:6a4db94011d3 | 690 | #define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 691 | |
sahilmgandhi | 18:6a4db94011d3 | 692 | #define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */ |
sahilmgandhi | 18:6a4db94011d3 | 693 | #define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 694 | |
sahilmgandhi | 18:6a4db94011d3 | 695 | #define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */ |
sahilmgandhi | 18:6a4db94011d3 | 696 | #define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 697 | |
sahilmgandhi | 18:6a4db94011d3 | 698 | #define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */ |
sahilmgandhi | 18:6a4db94011d3 | 699 | #define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 700 | |
sahilmgandhi | 18:6a4db94011d3 | 701 | #define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */ |
sahilmgandhi | 18:6a4db94011d3 | 702 | #define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 703 | |
sahilmgandhi | 18:6a4db94011d3 | 704 | #define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */ |
sahilmgandhi | 18:6a4db94011d3 | 705 | #define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 706 | |
sahilmgandhi | 18:6a4db94011d3 | 707 | #define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */ |
sahilmgandhi | 18:6a4db94011d3 | 708 | #define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */ |
sahilmgandhi | 18:6a4db94011d3 | 709 | |
sahilmgandhi | 18:6a4db94011d3 | 710 | |
sahilmgandhi | 18:6a4db94011d3 | 711 | |
sahilmgandhi | 18:6a4db94011d3 | 712 | /* -------------------- End of section using anonymous unions ------------------- */ |
sahilmgandhi | 18:6a4db94011d3 | 713 | #if defined ( __CC_ARM ) |
sahilmgandhi | 18:6a4db94011d3 | 714 | #pragma pop |
sahilmgandhi | 18:6a4db94011d3 | 715 | #elif defined(__ICCARM__) |
sahilmgandhi | 18:6a4db94011d3 | 716 | /* leave anonymous unions enabled */ |
sahilmgandhi | 18:6a4db94011d3 | 717 | #elif defined(__GNUC__) |
sahilmgandhi | 18:6a4db94011d3 | 718 | /* anonymous unions are enabled by default */ |
sahilmgandhi | 18:6a4db94011d3 | 719 | #elif defined(__TMS470__) |
sahilmgandhi | 18:6a4db94011d3 | 720 | /* anonymous unions are enabled by default */ |
sahilmgandhi | 18:6a4db94011d3 | 721 | #elif defined(__TASKING__) |
sahilmgandhi | 18:6a4db94011d3 | 722 | #pragma warning restore |
sahilmgandhi | 18:6a4db94011d3 | 723 | #else |
sahilmgandhi | 18:6a4db94011d3 | 724 | #warning Not supported compiler type |
sahilmgandhi | 18:6a4db94011d3 | 725 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 726 | |
sahilmgandhi | 18:6a4db94011d3 | 727 | |
sahilmgandhi | 18:6a4db94011d3 | 728 | |
sahilmgandhi | 18:6a4db94011d3 | 729 | |
sahilmgandhi | 18:6a4db94011d3 | 730 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 731 | /* ================ Peripheral memory map ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 732 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 733 | |
sahilmgandhi | 18:6a4db94011d3 | 734 | /* Peripheral and SRAM base address */ |
sahilmgandhi | 18:6a4db94011d3 | 735 | #define CMSDK_FLASH_BASE (0x00000000UL) |
sahilmgandhi | 18:6a4db94011d3 | 736 | #define CMSDK_SRAM_BASE (0x20000000UL) |
sahilmgandhi | 18:6a4db94011d3 | 737 | #define CMSDK_PERIPH_BASE (0x40000000UL) |
sahilmgandhi | 18:6a4db94011d3 | 738 | |
sahilmgandhi | 18:6a4db94011d3 | 739 | #define CMSDK_RAM_BASE (0x20000000UL) |
sahilmgandhi | 18:6a4db94011d3 | 740 | #define CMSDK_APB_BASE (0x40000000UL) |
sahilmgandhi | 18:6a4db94011d3 | 741 | #define CMSDK_AHB_BASE (0x40010000UL) |
sahilmgandhi | 18:6a4db94011d3 | 742 | |
sahilmgandhi | 18:6a4db94011d3 | 743 | /* APB peripherals */ |
sahilmgandhi | 18:6a4db94011d3 | 744 | #define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL) |
sahilmgandhi | 18:6a4db94011d3 | 745 | #define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL) |
sahilmgandhi | 18:6a4db94011d3 | 746 | #define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL) |
sahilmgandhi | 18:6a4db94011d3 | 747 | #define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE) |
sahilmgandhi | 18:6a4db94011d3 | 748 | #define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL) |
sahilmgandhi | 18:6a4db94011d3 | 749 | #define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL) |
sahilmgandhi | 18:6a4db94011d3 | 750 | #define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL) |
sahilmgandhi | 18:6a4db94011d3 | 751 | #define CMSDK_UART2_BASE (0x4002C000UL) |
sahilmgandhi | 18:6a4db94011d3 | 752 | #define CMSDK_UART3_BASE (0x4002D000UL) |
sahilmgandhi | 18:6a4db94011d3 | 753 | #define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL) |
sahilmgandhi | 18:6a4db94011d3 | 754 | |
sahilmgandhi | 18:6a4db94011d3 | 755 | /* AHB peripherals */ |
sahilmgandhi | 18:6a4db94011d3 | 756 | #define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL) |
sahilmgandhi | 18:6a4db94011d3 | 757 | #define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL) |
sahilmgandhi | 18:6a4db94011d3 | 758 | #define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL) |
sahilmgandhi | 18:6a4db94011d3 | 759 | #define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL) |
sahilmgandhi | 18:6a4db94011d3 | 760 | #define CMSDK_GPIO4_BASE (0x40030000UL) |
sahilmgandhi | 18:6a4db94011d3 | 761 | #define CMSDK_GPIO5_BASE (0x40031000UL) |
sahilmgandhi | 18:6a4db94011d3 | 762 | #define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL) |
sahilmgandhi | 18:6a4db94011d3 | 763 | |
sahilmgandhi | 18:6a4db94011d3 | 764 | |
sahilmgandhi | 18:6a4db94011d3 | 765 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 766 | /* ================ Peripheral declaration ================ */ |
sahilmgandhi | 18:6a4db94011d3 | 767 | /* ================================================================================ */ |
sahilmgandhi | 18:6a4db94011d3 | 768 | |
sahilmgandhi | 18:6a4db94011d3 | 769 | #define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE ) |
sahilmgandhi | 18:6a4db94011d3 | 770 | #define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE ) |
sahilmgandhi | 18:6a4db94011d3 | 771 | #define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE ) |
sahilmgandhi | 18:6a4db94011d3 | 772 | #define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE ) |
sahilmgandhi | 18:6a4db94011d3 | 773 | #define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE ) |
sahilmgandhi | 18:6a4db94011d3 | 774 | #define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE ) |
sahilmgandhi | 18:6a4db94011d3 | 775 | #define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE ) |
sahilmgandhi | 18:6a4db94011d3 | 776 | #define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE ) |
sahilmgandhi | 18:6a4db94011d3 | 777 | #define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE ) |
sahilmgandhi | 18:6a4db94011d3 | 778 | #define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE ) |
sahilmgandhi | 18:6a4db94011d3 | 779 | //#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE ) |
sahilmgandhi | 18:6a4db94011d3 | 780 | #define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE ) |
sahilmgandhi | 18:6a4db94011d3 | 781 | #define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE ) |
sahilmgandhi | 18:6a4db94011d3 | 782 | #define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE ) |
sahilmgandhi | 18:6a4db94011d3 | 783 | #define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE ) |
sahilmgandhi | 18:6a4db94011d3 | 784 | #define CMSDK_GPIO4 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO4_BASE ) |
sahilmgandhi | 18:6a4db94011d3 | 785 | #define CMSDK_GPIO5 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO5_BASE ) |
sahilmgandhi | 18:6a4db94011d3 | 786 | #define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE ) |
sahilmgandhi | 18:6a4db94011d3 | 787 | |
sahilmgandhi | 18:6a4db94011d3 | 788 | |
sahilmgandhi | 18:6a4db94011d3 | 789 | #ifdef __cplusplus |
sahilmgandhi | 18:6a4db94011d3 | 790 | } |
sahilmgandhi | 18:6a4db94011d3 | 791 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 792 | |
sahilmgandhi | 18:6a4db94011d3 | 793 | #endif /* CMSDK_BEID_H */ |