MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* MPS2 Peripheral Library
sahilmgandhi 18:6a4db94011d3 2 *
sahilmgandhi 18:6a4db94011d3 3 * Copyright (c) 2006-2015 ARM Limited
sahilmgandhi 18:6a4db94011d3 4 * All rights reserved.
sahilmgandhi 18:6a4db94011d3 5 *
sahilmgandhi 18:6a4db94011d3 6 * Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 7 * modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 10 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 11 *
sahilmgandhi 18:6a4db94011d3 12 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 13 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 14 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 15 *
sahilmgandhi 18:6a4db94011d3 16 * 3. Neither the name of the copyright holder nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 17 * may be used to endorse or promote products derived from this software without
sahilmgandhi 18:6a4db94011d3 18 * specific prior written permission.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
sahilmgandhi 18:6a4db94011d3 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
sahilmgandhi 18:6a4db94011d3 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
sahilmgandhi 18:6a4db94011d3 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
sahilmgandhi 18:6a4db94011d3 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
sahilmgandhi 18:6a4db94011d3 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
sahilmgandhi 18:6a4db94011d3 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
sahilmgandhi 18:6a4db94011d3 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sahilmgandhi 18:6a4db94011d3 30 * POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 31 */
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 /*
sahilmgandhi 18:6a4db94011d3 34 * Code implementation file for the LAN Ethernet interface.
sahilmgandhi 18:6a4db94011d3 35 */
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37 #include <stdio.h>
sahilmgandhi 18:6a4db94011d3 38 #include "mbed_wait_api.h"
sahilmgandhi 18:6a4db94011d3 39 #include "ETH_MPS2.h"
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 // SMSC9220 low-level operations
sahilmgandhi 18:6a4db94011d3 42 unsigned int smsc9220_mac_regread(unsigned char regoffset, unsigned int *data)
sahilmgandhi 18:6a4db94011d3 43 {
sahilmgandhi 18:6a4db94011d3 44 unsigned int val, maccmd;
sahilmgandhi 18:6a4db94011d3 45 int timedout;
sahilmgandhi 18:6a4db94011d3 46 int error;
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 error = 0;
sahilmgandhi 18:6a4db94011d3 49 val = SMSC9220->MAC_CSR_CMD;
sahilmgandhi 18:6a4db94011d3 50 if(!(val & ((unsigned int)1 << 31))) { // Make sure there's no pending operation
sahilmgandhi 18:6a4db94011d3 51 maccmd = 0;
sahilmgandhi 18:6a4db94011d3 52 maccmd |= regoffset;
sahilmgandhi 18:6a4db94011d3 53 maccmd |= ((unsigned int)1 << 30); // Indicates read
sahilmgandhi 18:6a4db94011d3 54 maccmd |= ((unsigned int)1 << 31); // Start bit
sahilmgandhi 18:6a4db94011d3 55 SMSC9220->MAC_CSR_CMD = maccmd; // Start operation
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 timedout = 50;
sahilmgandhi 18:6a4db94011d3 58 do {
sahilmgandhi 18:6a4db94011d3 59 val = SMSC9220->BYTE_TEST; // A no-op read.
sahilmgandhi 18:6a4db94011d3 60 wait_ms(1); //Sleepms(1);
sahilmgandhi 18:6a4db94011d3 61 timedout--;
sahilmgandhi 18:6a4db94011d3 62 } while(timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31)));
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 if(!timedout) {
sahilmgandhi 18:6a4db94011d3 65 error = 1;
sahilmgandhi 18:6a4db94011d3 66 }
sahilmgandhi 18:6a4db94011d3 67 else
sahilmgandhi 18:6a4db94011d3 68 *data = SMSC9220->MAC_CSR_DATA;
sahilmgandhi 18:6a4db94011d3 69 } else {
sahilmgandhi 18:6a4db94011d3 70 *data = 0;
sahilmgandhi 18:6a4db94011d3 71 }
sahilmgandhi 18:6a4db94011d3 72 return error;
sahilmgandhi 18:6a4db94011d3 73 }
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 unsigned int smsc9220_mac_regwrite(unsigned char regoffset, unsigned int data)
sahilmgandhi 18:6a4db94011d3 76 {
sahilmgandhi 18:6a4db94011d3 77 unsigned int read, maccmd;
sahilmgandhi 18:6a4db94011d3 78 int timedout;
sahilmgandhi 18:6a4db94011d3 79 int error;
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 error = 0;
sahilmgandhi 18:6a4db94011d3 82 read = SMSC9220->MAC_CSR_CMD;
sahilmgandhi 18:6a4db94011d3 83 if(!(read & ((unsigned int)1 << 31))) { // Make sure there's no pending operation
sahilmgandhi 18:6a4db94011d3 84 SMSC9220->MAC_CSR_DATA = data; // Store data.
sahilmgandhi 18:6a4db94011d3 85 maccmd = 0;
sahilmgandhi 18:6a4db94011d3 86 maccmd |= regoffset;
sahilmgandhi 18:6a4db94011d3 87 maccmd &= ~((unsigned int)1 << 30); // Clear indicates write
sahilmgandhi 18:6a4db94011d3 88 maccmd |= ((unsigned int)1 << 31); // Indicate start of operation
sahilmgandhi 18:6a4db94011d3 89 SMSC9220->MAC_CSR_CMD = maccmd;
sahilmgandhi 18:6a4db94011d3 90
sahilmgandhi 18:6a4db94011d3 91 timedout = 50;
sahilmgandhi 18:6a4db94011d3 92 do {
sahilmgandhi 18:6a4db94011d3 93 read = SMSC9220->BYTE_TEST; // A no-op read.
sahilmgandhi 18:6a4db94011d3 94 wait_ms(1); //Sleepms(1);
sahilmgandhi 18:6a4db94011d3 95 timedout--;
sahilmgandhi 18:6a4db94011d3 96 } while(timedout && (SMSC9220->MAC_CSR_CMD & ((unsigned int)1 << 31)));
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 if(!timedout) {
sahilmgandhi 18:6a4db94011d3 99 error = 1;
sahilmgandhi 18:6a4db94011d3 100 }
sahilmgandhi 18:6a4db94011d3 101 } else {
sahilmgandhi 18:6a4db94011d3 102 printf("Warning: SMSC9220 MAC CSR is busy. No data written.\n");
sahilmgandhi 18:6a4db94011d3 103 }
sahilmgandhi 18:6a4db94011d3 104 return error;
sahilmgandhi 18:6a4db94011d3 105 }
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107 unsigned int smsc9220_phy_regread(unsigned char regoffset, unsigned short *data)
sahilmgandhi 18:6a4db94011d3 108 {
sahilmgandhi 18:6a4db94011d3 109 unsigned int val, phycmd; int error;
sahilmgandhi 18:6a4db94011d3 110 int timedout;
sahilmgandhi 18:6a4db94011d3 111
sahilmgandhi 18:6a4db94011d3 112 error = 0;
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val);
sahilmgandhi 18:6a4db94011d3 115
sahilmgandhi 18:6a4db94011d3 116 if(!(val & 1)) { // Not busy
sahilmgandhi 18:6a4db94011d3 117 phycmd = 0;
sahilmgandhi 18:6a4db94011d3 118 phycmd |= (1 << 11); // 1 to [15:11]
sahilmgandhi 18:6a4db94011d3 119 phycmd |= ((regoffset & 0x1F) << 6); // Put regoffset to [10:6]
sahilmgandhi 18:6a4db94011d3 120 phycmd &= ~(1 << 1); // Clear [1] indicates read.
sahilmgandhi 18:6a4db94011d3 121 phycmd |= (1 << 0); // Set [0] indicates operation start
sahilmgandhi 18:6a4db94011d3 122
sahilmgandhi 18:6a4db94011d3 123 smsc9220_mac_regwrite(SMSC9220_MAC_MII_ACC, phycmd);
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125 val = 0;
sahilmgandhi 18:6a4db94011d3 126 timedout = 50;
sahilmgandhi 18:6a4db94011d3 127 do {
sahilmgandhi 18:6a4db94011d3 128 wait_ms(1); //Sleepms(1);
sahilmgandhi 18:6a4db94011d3 129 timedout--;
sahilmgandhi 18:6a4db94011d3 130 smsc9220_mac_regread(SMSC9220_MAC_MII_ACC,&val);
sahilmgandhi 18:6a4db94011d3 131 } while(timedout && (val & ((unsigned int)1 << 0)));
sahilmgandhi 18:6a4db94011d3 132
sahilmgandhi 18:6a4db94011d3 133 if(!timedout) {
sahilmgandhi 18:6a4db94011d3 134 error = 1;
sahilmgandhi 18:6a4db94011d3 135 }
sahilmgandhi 18:6a4db94011d3 136 else
sahilmgandhi 18:6a4db94011d3 137 smsc9220_mac_regread(SMSC9220_MAC_MII_DATA, (unsigned int *)data);
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139 } else {
sahilmgandhi 18:6a4db94011d3 140 *data = 0;
sahilmgandhi 18:6a4db94011d3 141 }
sahilmgandhi 18:6a4db94011d3 142 return error;
sahilmgandhi 18:6a4db94011d3 143 }
sahilmgandhi 18:6a4db94011d3 144
sahilmgandhi 18:6a4db94011d3 145 unsigned int smsc9220_phy_regwrite(unsigned char regoffset, unsigned short data)
sahilmgandhi 18:6a4db94011d3 146 {
sahilmgandhi 18:6a4db94011d3 147 unsigned int val, phycmd; int error;
sahilmgandhi 18:6a4db94011d3 148 int timedout;
sahilmgandhi 18:6a4db94011d3 149
sahilmgandhi 18:6a4db94011d3 150 error = 0;
sahilmgandhi 18:6a4db94011d3 151
sahilmgandhi 18:6a4db94011d3 152 smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &val);
sahilmgandhi 18:6a4db94011d3 153
sahilmgandhi 18:6a4db94011d3 154 if(!(val & 1)) { // Not busy
sahilmgandhi 18:6a4db94011d3 155 smsc9220_mac_regwrite(SMSC9220_MAC_MII_DATA, (data & 0xFFFF)); // Load the data
sahilmgandhi 18:6a4db94011d3 156 phycmd = 0;
sahilmgandhi 18:6a4db94011d3 157 phycmd |= (1 << 11); // 1 to [15:11]
sahilmgandhi 18:6a4db94011d3 158 phycmd |= ((regoffset & 0x1F) << 6); // Put regoffset to [10:6]
sahilmgandhi 18:6a4db94011d3 159 phycmd |= (1 << 1); // Set [1] indicates write.
sahilmgandhi 18:6a4db94011d3 160 phycmd |= (1 << 0); // Set [0] indicates operation start
sahilmgandhi 18:6a4db94011d3 161 smsc9220_mac_regwrite(SMSC9220_MAC_MII_ACC, phycmd); // Start operation
sahilmgandhi 18:6a4db94011d3 162
sahilmgandhi 18:6a4db94011d3 163 phycmd = 0;
sahilmgandhi 18:6a4db94011d3 164 timedout = 50;
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 do {
sahilmgandhi 18:6a4db94011d3 167
sahilmgandhi 18:6a4db94011d3 168 wait_ms(1); //Sleepms(1);
sahilmgandhi 18:6a4db94011d3 169 timedout--;
sahilmgandhi 18:6a4db94011d3 170 smsc9220_mac_regread(SMSC9220_MAC_MII_ACC, &phycmd);
sahilmgandhi 18:6a4db94011d3 171 } while(timedout && (phycmd & (1 << 0)));
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 if(!timedout) {
sahilmgandhi 18:6a4db94011d3 174 error = 1;
sahilmgandhi 18:6a4db94011d3 175 }
sahilmgandhi 18:6a4db94011d3 176
sahilmgandhi 18:6a4db94011d3 177 } else {
sahilmgandhi 18:6a4db94011d3 178 printf("Warning: SMSC9220 MAC MII is busy. No data written.\n");
sahilmgandhi 18:6a4db94011d3 179 }
sahilmgandhi 18:6a4db94011d3 180 return error;
sahilmgandhi 18:6a4db94011d3 181 }
sahilmgandhi 18:6a4db94011d3 182
sahilmgandhi 18:6a4db94011d3 183 // Returns smsc9220 id.
sahilmgandhi 18:6a4db94011d3 184 unsigned int smsc9220_read_id(void)
sahilmgandhi 18:6a4db94011d3 185 {
sahilmgandhi 18:6a4db94011d3 186 return SMSC9220->ID_REV;
sahilmgandhi 18:6a4db94011d3 187 }
sahilmgandhi 18:6a4db94011d3 188
sahilmgandhi 18:6a4db94011d3 189 // Initiates a soft reset, returns failure or success.
sahilmgandhi 18:6a4db94011d3 190 unsigned int smsc9220_soft_reset(void)
sahilmgandhi 18:6a4db94011d3 191 {
sahilmgandhi 18:6a4db94011d3 192 int timedout;
sahilmgandhi 18:6a4db94011d3 193
sahilmgandhi 18:6a4db94011d3 194 timedout = 10;
sahilmgandhi 18:6a4db94011d3 195 // Soft reset
sahilmgandhi 18:6a4db94011d3 196 SMSC9220->HW_CFG |= 1;
sahilmgandhi 18:6a4db94011d3 197
sahilmgandhi 18:6a4db94011d3 198 do {
sahilmgandhi 18:6a4db94011d3 199 wait_ms(1); //Sleepms(1);
sahilmgandhi 18:6a4db94011d3 200 timedout--;
sahilmgandhi 18:6a4db94011d3 201 } while(timedout && (SMSC9220->HW_CFG & 1));
sahilmgandhi 18:6a4db94011d3 202
sahilmgandhi 18:6a4db94011d3 203 if(!timedout)
sahilmgandhi 18:6a4db94011d3 204 return 1;
sahilmgandhi 18:6a4db94011d3 205
sahilmgandhi 18:6a4db94011d3 206 return 0;
sahilmgandhi 18:6a4db94011d3 207 }
sahilmgandhi 18:6a4db94011d3 208
sahilmgandhi 18:6a4db94011d3 209 void smsc9220_set_txfifo(unsigned int val)
sahilmgandhi 18:6a4db94011d3 210 {
sahilmgandhi 18:6a4db94011d3 211 // 2kb minimum, 14kb maximum
sahilmgandhi 18:6a4db94011d3 212 if(val < 2 || val > 14)
sahilmgandhi 18:6a4db94011d3 213 return;
sahilmgandhi 18:6a4db94011d3 214
sahilmgandhi 18:6a4db94011d3 215 SMSC9220->HW_CFG = val << 16;
sahilmgandhi 18:6a4db94011d3 216 }
sahilmgandhi 18:6a4db94011d3 217
sahilmgandhi 18:6a4db94011d3 218
sahilmgandhi 18:6a4db94011d3 219 unsigned int smsc9220_wait_eeprom(void)
sahilmgandhi 18:6a4db94011d3 220 {
sahilmgandhi 18:6a4db94011d3 221 int timedout;
sahilmgandhi 18:6a4db94011d3 222
sahilmgandhi 18:6a4db94011d3 223 timedout = 50;
sahilmgandhi 18:6a4db94011d3 224
sahilmgandhi 18:6a4db94011d3 225 do {
sahilmgandhi 18:6a4db94011d3 226 wait_ms(1); //Sleepms(1);
sahilmgandhi 18:6a4db94011d3 227 timedout--;
sahilmgandhi 18:6a4db94011d3 228
sahilmgandhi 18:6a4db94011d3 229 } while(timedout && (SMSC9220->E2P_CMD & ((unsigned int) 1 << 31)));
sahilmgandhi 18:6a4db94011d3 230
sahilmgandhi 18:6a4db94011d3 231 if(!timedout)
sahilmgandhi 18:6a4db94011d3 232 return 1;
sahilmgandhi 18:6a4db94011d3 233
sahilmgandhi 18:6a4db94011d3 234 return 0;
sahilmgandhi 18:6a4db94011d3 235 }
sahilmgandhi 18:6a4db94011d3 236
sahilmgandhi 18:6a4db94011d3 237 /* initialise irqs */
sahilmgandhi 18:6a4db94011d3 238 void smsc9220_init_irqs(void)
sahilmgandhi 18:6a4db94011d3 239 {
sahilmgandhi 18:6a4db94011d3 240 SMSC9220->INT_EN = 0x0;
sahilmgandhi 18:6a4db94011d3 241 SMSC9220->INT_STS = 0xFFFFFFFF; // clear all interrupts
sahilmgandhi 18:6a4db94011d3 242 SMSC9220->IRQ_CFG = 0x22000100; // irq deassertion at 220 usecs and master IRQ enable.
sahilmgandhi 18:6a4db94011d3 243 }
sahilmgandhi 18:6a4db94011d3 244
sahilmgandhi 18:6a4db94011d3 245 unsigned int smsc9220_check_phy(void)
sahilmgandhi 18:6a4db94011d3 246 {
sahilmgandhi 18:6a4db94011d3 247 unsigned short phyid1, phyid2;
sahilmgandhi 18:6a4db94011d3 248
sahilmgandhi 18:6a4db94011d3 249 smsc9220_phy_regread(SMSC9220_PHY_ID1,&phyid1);
sahilmgandhi 18:6a4db94011d3 250 smsc9220_phy_regread(SMSC9220_PHY_ID2,&phyid2);
sahilmgandhi 18:6a4db94011d3 251 return ((phyid1 == 0xFFFF && phyid2 == 0xFFFF) ||
sahilmgandhi 18:6a4db94011d3 252 (phyid1 == 0x0 && phyid2 == 0x0));
sahilmgandhi 18:6a4db94011d3 253 }
sahilmgandhi 18:6a4db94011d3 254
sahilmgandhi 18:6a4db94011d3 255 unsigned int smsc9220_reset_phy(void)
sahilmgandhi 18:6a4db94011d3 256 {
sahilmgandhi 18:6a4db94011d3 257 unsigned short read;
sahilmgandhi 18:6a4db94011d3 258 int error;
sahilmgandhi 18:6a4db94011d3 259
sahilmgandhi 18:6a4db94011d3 260 error = 0;
sahilmgandhi 18:6a4db94011d3 261 if(smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &read)) {
sahilmgandhi 18:6a4db94011d3 262 error = 1;
sahilmgandhi 18:6a4db94011d3 263 return error;
sahilmgandhi 18:6a4db94011d3 264 }
sahilmgandhi 18:6a4db94011d3 265
sahilmgandhi 18:6a4db94011d3 266 read |= (1 << 15);
sahilmgandhi 18:6a4db94011d3 267 if(smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, read)) {
sahilmgandhi 18:6a4db94011d3 268 error = 1;
sahilmgandhi 18:6a4db94011d3 269 return error;
sahilmgandhi 18:6a4db94011d3 270 }
sahilmgandhi 18:6a4db94011d3 271 return 0;
sahilmgandhi 18:6a4db94011d3 272 }
sahilmgandhi 18:6a4db94011d3 273
sahilmgandhi 18:6a4db94011d3 274 /* Advertise all speeds and pause capabilities */
sahilmgandhi 18:6a4db94011d3 275 void smsc9220_advertise_cap(void)
sahilmgandhi 18:6a4db94011d3 276 {
sahilmgandhi 18:6a4db94011d3 277 unsigned short aneg_adv;
sahilmgandhi 18:6a4db94011d3 278 aneg_adv = 0;
sahilmgandhi 18:6a4db94011d3 279
sahilmgandhi 18:6a4db94011d3 280
sahilmgandhi 18:6a4db94011d3 281 smsc9220_phy_regread(SMSC9220_PHY_ANEG_ADV, &aneg_adv);
sahilmgandhi 18:6a4db94011d3 282 aneg_adv |= 0xDE0;
sahilmgandhi 18:6a4db94011d3 283
sahilmgandhi 18:6a4db94011d3 284 smsc9220_phy_regwrite(SMSC9220_PHY_ANEG_ADV, aneg_adv);
sahilmgandhi 18:6a4db94011d3 285 smsc9220_phy_regread(SMSC9220_PHY_ANEG_ADV, &aneg_adv);
sahilmgandhi 18:6a4db94011d3 286 return;
sahilmgandhi 18:6a4db94011d3 287 }
sahilmgandhi 18:6a4db94011d3 288
sahilmgandhi 18:6a4db94011d3 289 void smsc9220_establish_link(void)
sahilmgandhi 18:6a4db94011d3 290 {
sahilmgandhi 18:6a4db94011d3 291 unsigned short bcr;
sahilmgandhi 18:6a4db94011d3 292
sahilmgandhi 18:6a4db94011d3 293 smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &bcr);
sahilmgandhi 18:6a4db94011d3 294 bcr |= (1 << 12) | (1 << 9);
sahilmgandhi 18:6a4db94011d3 295 smsc9220_phy_regwrite(SMSC9220_PHY_BCONTROL, bcr);
sahilmgandhi 18:6a4db94011d3 296 smsc9220_phy_regread(SMSC9220_PHY_BCONTROL, &bcr);
sahilmgandhi 18:6a4db94011d3 297
sahilmgandhi 18:6a4db94011d3 298 {
sahilmgandhi 18:6a4db94011d3 299 unsigned int hw_cfg;
sahilmgandhi 18:6a4db94011d3 300
sahilmgandhi 18:6a4db94011d3 301 hw_cfg = 0;
sahilmgandhi 18:6a4db94011d3 302 hw_cfg = SMSC9220->HW_CFG;
sahilmgandhi 18:6a4db94011d3 303
sahilmgandhi 18:6a4db94011d3 304 hw_cfg &= 0xF0000;
sahilmgandhi 18:6a4db94011d3 305 hw_cfg |= (1 << 20);
sahilmgandhi 18:6a4db94011d3 306 SMSC9220->HW_CFG = hw_cfg;
sahilmgandhi 18:6a4db94011d3 307 }
sahilmgandhi 18:6a4db94011d3 308
sahilmgandhi 18:6a4db94011d3 309 return;
sahilmgandhi 18:6a4db94011d3 310 }
sahilmgandhi 18:6a4db94011d3 311
sahilmgandhi 18:6a4db94011d3 312 void smsc9220_enable_xmit(void)
sahilmgandhi 18:6a4db94011d3 313 {
sahilmgandhi 18:6a4db94011d3 314 SMSC9220->TX_CFG = 0x2; // Enable trasmission
sahilmgandhi 18:6a4db94011d3 315 return;
sahilmgandhi 18:6a4db94011d3 316 }
sahilmgandhi 18:6a4db94011d3 317
sahilmgandhi 18:6a4db94011d3 318 void smsc9220_enable_mac_xmit(void)
sahilmgandhi 18:6a4db94011d3 319 {
sahilmgandhi 18:6a4db94011d3 320 unsigned int mac_cr;
sahilmgandhi 18:6a4db94011d3 321
sahilmgandhi 18:6a4db94011d3 322 mac_cr = 0;
sahilmgandhi 18:6a4db94011d3 323 smsc9220_mac_regread(SMSC9220_MAC_CR, &mac_cr);
sahilmgandhi 18:6a4db94011d3 324
sahilmgandhi 18:6a4db94011d3 325 mac_cr |= (1 << 3); // xmit enable
sahilmgandhi 18:6a4db94011d3 326 mac_cr |= (1 << 28); // Heartbeat disable
sahilmgandhi 18:6a4db94011d3 327
sahilmgandhi 18:6a4db94011d3 328 smsc9220_mac_regwrite(SMSC9220_MAC_CR, mac_cr);
sahilmgandhi 18:6a4db94011d3 329 return;
sahilmgandhi 18:6a4db94011d3 330 }
sahilmgandhi 18:6a4db94011d3 331
sahilmgandhi 18:6a4db94011d3 332 void smsc9220_enable_mac_recv(void)
sahilmgandhi 18:6a4db94011d3 333 {
sahilmgandhi 18:6a4db94011d3 334 unsigned int mac_cr;
sahilmgandhi 18:6a4db94011d3 335
sahilmgandhi 18:6a4db94011d3 336 mac_cr = 0;
sahilmgandhi 18:6a4db94011d3 337 smsc9220_mac_regread(SMSC9220_MAC_CR, &mac_cr);
sahilmgandhi 18:6a4db94011d3 338 mac_cr |= (1 << 2); // Recv enable
sahilmgandhi 18:6a4db94011d3 339 smsc9220_mac_regwrite(SMSC9220_MAC_CR, mac_cr);
sahilmgandhi 18:6a4db94011d3 340
sahilmgandhi 18:6a4db94011d3 341 return;
sahilmgandhi 18:6a4db94011d3 342 }
sahilmgandhi 18:6a4db94011d3 343
sahilmgandhi 18:6a4db94011d3 344
sahilmgandhi 18:6a4db94011d3 345 unsigned int smsc9220_check_ready(void)
sahilmgandhi 18:6a4db94011d3 346 {
sahilmgandhi 18:6a4db94011d3 347 return !(SMSC9220->PMT_CTRL & 1);
sahilmgandhi 18:6a4db94011d3 348 }
sahilmgandhi 18:6a4db94011d3 349
sahilmgandhi 18:6a4db94011d3 350 /* Generate a soft irq */
sahilmgandhi 18:6a4db94011d3 351 void smsc9220_set_soft_int(void)
sahilmgandhi 18:6a4db94011d3 352 {
sahilmgandhi 18:6a4db94011d3 353 SMSC9220->INT_EN |= 0x80000000;
sahilmgandhi 18:6a4db94011d3 354 }
sahilmgandhi 18:6a4db94011d3 355
sahilmgandhi 18:6a4db94011d3 356 /* clear soft irq */
sahilmgandhi 18:6a4db94011d3 357 void smsc9220_clear_soft_int(void)
sahilmgandhi 18:6a4db94011d3 358 {
sahilmgandhi 18:6a4db94011d3 359 SMSC9220->INT_STS |= 0x80000000;
sahilmgandhi 18:6a4db94011d3 360 }
sahilmgandhi 18:6a4db94011d3 361
sahilmgandhi 18:6a4db94011d3 362
sahilmgandhi 18:6a4db94011d3 363 unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index)
sahilmgandhi 18:6a4db94011d3 364 {
sahilmgandhi 18:6a4db94011d3 365 unsigned int rxfifo_inf; // Tells us the status of rx payload and status fifos.
sahilmgandhi 18:6a4db94011d3 366 unsigned int rxfifo_stat;
sahilmgandhi 18:6a4db94011d3 367
sahilmgandhi 18:6a4db94011d3 368 unsigned int pktsize;
sahilmgandhi 18:6a4db94011d3 369 unsigned int dwords_to_read;
sahilmgandhi 18:6a4db94011d3 370
sahilmgandhi 18:6a4db94011d3 371 rxfifo_inf = SMSC9220->RX_FIFO_INF;
sahilmgandhi 18:6a4db94011d3 372
sahilmgandhi 18:6a4db94011d3 373 if(rxfifo_inf & 0xFFFF) { // If there's data
sahilmgandhi 18:6a4db94011d3 374 rxfifo_stat = SMSC9220->RX_STAT_PORT;
sahilmgandhi 18:6a4db94011d3 375 if(rxfifo_stat != 0) { // Fetch status of this packet
sahilmgandhi 18:6a4db94011d3 376 pktsize = ((rxfifo_stat >> 16) & 0x3FFF);
sahilmgandhi 18:6a4db94011d3 377 if(rxfifo_stat & (1 << 15)) {
sahilmgandhi 18:6a4db94011d3 378 printf("Error occured during receiving of packets on the bus.\n");
sahilmgandhi 18:6a4db94011d3 379 return 1;
sahilmgandhi 18:6a4db94011d3 380 } else {
sahilmgandhi 18:6a4db94011d3 381 /* Below formula (recommended by SMSC9220 code)
sahilmgandhi 18:6a4db94011d3 382 * gives 1 more than required. This is perhaps because
sahilmgandhi 18:6a4db94011d3 383 * a last word is needed for not word aligned packets.
sahilmgandhi 18:6a4db94011d3 384 */
sahilmgandhi 18:6a4db94011d3 385 dwords_to_read = (pktsize + 3) >> 2;
sahilmgandhi 18:6a4db94011d3 386 // PIO copy of data received:
sahilmgandhi 18:6a4db94011d3 387 while(dwords_to_read > 0) {
sahilmgandhi 18:6a4db94011d3 388 recvbuf[*index] = SMSC9220->RX_DATA_PORT;
sahilmgandhi 18:6a4db94011d3 389 (*index)++;
sahilmgandhi 18:6a4db94011d3 390 dwords_to_read--;
sahilmgandhi 18:6a4db94011d3 391 }
sahilmgandhi 18:6a4db94011d3 392 }
sahilmgandhi 18:6a4db94011d3 393 } else {
sahilmgandhi 18:6a4db94011d3 394 return 1;
sahilmgandhi 18:6a4db94011d3 395 }
sahilmgandhi 18:6a4db94011d3 396 } else {
sahilmgandhi 18:6a4db94011d3 397 return 1;
sahilmgandhi 18:6a4db94011d3 398 }
sahilmgandhi 18:6a4db94011d3 399
sahilmgandhi 18:6a4db94011d3 400 rxfifo_stat = SMSC9220->RX_STAT_PORT;
sahilmgandhi 18:6a4db94011d3 401 rxfifo_inf = SMSC9220->RX_FIFO_INF;
sahilmgandhi 18:6a4db94011d3 402
sahilmgandhi 18:6a4db94011d3 403 return 0;
sahilmgandhi 18:6a4db94011d3 404 }
sahilmgandhi 18:6a4db94011d3 405
sahilmgandhi 18:6a4db94011d3 406
sahilmgandhi 18:6a4db94011d3 407 // Does the actual transfer of data to FIFO, note it does no
sahilmgandhi 18:6a4db94011d3 408 // fifo availability checking. This should be done by caller.
sahilmgandhi 18:6a4db94011d3 409 // Assumes the whole frame is transferred at once as a single segment
sahilmgandhi 18:6a4db94011d3 410 void smsc9220_xmit_packet(unsigned char * pkt, unsigned int length)
sahilmgandhi 18:6a4db94011d3 411 {
sahilmgandhi 18:6a4db94011d3 412 unsigned int txcmd_a, txcmd_b;
sahilmgandhi 18:6a4db94011d3 413 unsigned int dwords_to_write;
sahilmgandhi 18:6a4db94011d3 414 volatile unsigned int dwritten;
sahilmgandhi 18:6a4db94011d3 415 unsigned int *pktptr;
sahilmgandhi 18:6a4db94011d3 416 volatile unsigned int xmit_stat, xmit_stat2, xmit_inf;
sahilmgandhi 18:6a4db94011d3 417 int i;
sahilmgandhi 18:6a4db94011d3 418
sahilmgandhi 18:6a4db94011d3 419 pktptr = (unsigned int *) pkt;
sahilmgandhi 18:6a4db94011d3 420 txcmd_a = 0;
sahilmgandhi 18:6a4db94011d3 421 txcmd_b = 0;
sahilmgandhi 18:6a4db94011d3 422
sahilmgandhi 18:6a4db94011d3 423 txcmd_a |= (1 << 12) | (1 << 13); // First and last segments
sahilmgandhi 18:6a4db94011d3 424 txcmd_a |= length & 0x7FF; // [10:0] contains length
sahilmgandhi 18:6a4db94011d3 425
sahilmgandhi 18:6a4db94011d3 426 txcmd_b |= ((length & 0xFFFF) << 16); // [31:16] contains length
sahilmgandhi 18:6a4db94011d3 427 txcmd_b |= length & 0x7FF; // [10:0] also contains length
sahilmgandhi 18:6a4db94011d3 428
sahilmgandhi 18:6a4db94011d3 429
sahilmgandhi 18:6a4db94011d3 430 SMSC9220->TX_DATA_PORT = txcmd_a;
sahilmgandhi 18:6a4db94011d3 431 SMSC9220->TX_DATA_PORT = txcmd_b;
sahilmgandhi 18:6a4db94011d3 432 dwritten = dwords_to_write = (length + 3) >> 2;
sahilmgandhi 18:6a4db94011d3 433
sahilmgandhi 18:6a4db94011d3 434 // PIO Copy to FIFO. Could replace this with DMA.
sahilmgandhi 18:6a4db94011d3 435 while(dwords_to_write > 0) {
sahilmgandhi 18:6a4db94011d3 436 SMSC9220->TX_DATA_PORT = *pktptr;
sahilmgandhi 18:6a4db94011d3 437 pktptr++;
sahilmgandhi 18:6a4db94011d3 438 dwords_to_write--;
sahilmgandhi 18:6a4db94011d3 439 }
sahilmgandhi 18:6a4db94011d3 440
sahilmgandhi 18:6a4db94011d3 441 xmit_stat = SMSC9220->TX_STAT_PORT;
sahilmgandhi 18:6a4db94011d3 442 xmit_stat2 = SMSC9220->TX_STAT_PORT;
sahilmgandhi 18:6a4db94011d3 443 xmit_inf = SMSC9220->TX_FIFO_INF;
sahilmgandhi 18:6a4db94011d3 444
sahilmgandhi 18:6a4db94011d3 445 if(xmit_stat2 != 0 ) {
sahilmgandhi 18:6a4db94011d3 446 for(i = 0; i < 6; i++) {
sahilmgandhi 18:6a4db94011d3 447 xmit_stat2 = SMSC9220->TX_STAT_PORT;
sahilmgandhi 18:6a4db94011d3 448 }
sahilmgandhi 18:6a4db94011d3 449 }
sahilmgandhi 18:6a4db94011d3 450 }