MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/fcache_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2015 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16
sahilmgandhi 18:6a4db94011d3 17 #include "fcache_api.h"
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 static unsigned int enabled;
sahilmgandhi 18:6a4db94011d3 20 static unsigned int fcache_mode;
sahilmgandhi 18:6a4db94011d3 21 /* Functions */
sahilmgandhi 18:6a4db94011d3 22
sahilmgandhi 18:6a4db94011d3 23 /*
sahilmgandhi 18:6a4db94011d3 24 * FCache_DriverInitialize: flash cache driver initialize funtion
sahilmgandhi 18:6a4db94011d3 25 */
sahilmgandhi 18:6a4db94011d3 26 void FCache_DriverInitialize()
sahilmgandhi 18:6a4db94011d3 27 {
sahilmgandhi 18:6a4db94011d3 28 unsigned int irqstat;
sahilmgandhi 18:6a4db94011d3 29
sahilmgandhi 18:6a4db94011d3 30 /* Clear interrupt status register */
sahilmgandhi 18:6a4db94011d3 31 irqstat = FCache_Readl(SYS_FCACHE_IRQSTAT) & (FCACHE_POW_ERR | FCACHE_MAN_INV_ERR);
sahilmgandhi 18:6a4db94011d3 32 FCache_Writel(SYS_FCACHE_IRQSTAT, irqstat);
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 /* Cache Disabled: Set enabled to 0 */
sahilmgandhi 18:6a4db94011d3 35 enabled = 0;
sahilmgandhi 18:6a4db94011d3 36 }
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 /*
sahilmgandhi 18:6a4db94011d3 39 * FCache_Enable: Enables the flash cache mode
sahilmgandhi 18:6a4db94011d3 40 * mode: supported modes:
sahilmgandhi 18:6a4db94011d3 41 * 0 - auto-power auto-invalidate
sahilmgandhi 18:6a4db94011d3 42 * 1 - manual-power, manual-invalidate
sahilmgandhi 18:6a4db94011d3 43 */
sahilmgandhi 18:6a4db94011d3 44 void FCache_Enable(int mode)
sahilmgandhi 18:6a4db94011d3 45 {
sahilmgandhi 18:6a4db94011d3 46 /* Save Enable Mode */
sahilmgandhi 18:6a4db94011d3 47 fcache_mode = mode;
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 /* Enable the FCache */
sahilmgandhi 18:6a4db94011d3 50 switch (fcache_mode) {
sahilmgandhi 18:6a4db94011d3 51 case 0:
sahilmgandhi 18:6a4db94011d3 52 /* Statistic counters enabled, Cache enable,
sahilmgandhi 18:6a4db94011d3 53 * auto-inval, auto-power control
sahilmgandhi 18:6a4db94011d3 54 */
sahilmgandhi 18:6a4db94011d3 55 FCache_Writel(SYS_FCACHE_CCR, (FCACHE_EN | FCACHE_STATISTIC_EN));
sahilmgandhi 18:6a4db94011d3 56 /* Wait until the cache is enabled */
sahilmgandhi 18:6a4db94011d3 57 while ((FCache_Readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_ENABLED);
sahilmgandhi 18:6a4db94011d3 58 /* Cache Enabled: Set enabled to 1 */
sahilmgandhi 18:6a4db94011d3 59 enabled = 1;
sahilmgandhi 18:6a4db94011d3 60 break;
sahilmgandhi 18:6a4db94011d3 61 case 1:
sahilmgandhi 18:6a4db94011d3 62 /*
sahilmgandhi 18:6a4db94011d3 63 * Statistic counters enabled, Cache disabled,
sahilmgandhi 18:6a4db94011d3 64 * Manual power request (Setting: Power CTRL:
sahilmgandhi 18:6a4db94011d3 65 * Manual, Invalidate: Manual)
sahilmgandhi 18:6a4db94011d3 66 */
sahilmgandhi 18:6a4db94011d3 67 FCache_Writel(SYS_FCACHE_CCR, (FCACHE_POW_REQ
sahilmgandhi 18:6a4db94011d3 68 | FCACHE_SET_MAN_POW
sahilmgandhi 18:6a4db94011d3 69 | FCACHE_SET_MAN_INV
sahilmgandhi 18:6a4db94011d3 70 | FCACHE_STATISTIC_EN));
sahilmgandhi 18:6a4db94011d3 71 /* Wait until the cache rams are powered */
sahilmgandhi 18:6a4db94011d3 72 while ((FCache_Readl(SYS_FCACHE_SR) & FCACHE_POW_STAT) != FCACHE_POW_STAT);
sahilmgandhi 18:6a4db94011d3 73 /* Statistic counters enabled, Cache enabled
sahilmgandhi 18:6a4db94011d3 74 * Manual invalidate request (Setting: Power CTRL:
sahilmgandhi 18:6a4db94011d3 75 * Manual, Invalidate: Manual)
sahilmgandhi 18:6a4db94011d3 76 */
sahilmgandhi 18:6a4db94011d3 77 FCache_Writel(SYS_FCACHE_CCR, (FCACHE_INV_REQ
sahilmgandhi 18:6a4db94011d3 78 | FCACHE_POW_REQ
sahilmgandhi 18:6a4db94011d3 79 | FCACHE_SET_MAN_POW
sahilmgandhi 18:6a4db94011d3 80 | FCACHE_SET_MAN_INV
sahilmgandhi 18:6a4db94011d3 81 | FCACHE_STATISTIC_EN));
sahilmgandhi 18:6a4db94011d3 82 /* Wait until the cache is invalidated */
sahilmgandhi 18:6a4db94011d3 83 while ((FCache_Readl(SYS_FCACHE_SR) & FCACHE_INV_STAT) == FCACHE_INV_STAT);
sahilmgandhi 18:6a4db94011d3 84 /* Statistic counters enabled, Cache enable,
sahilmgandhi 18:6a4db94011d3 85 * manual-inval, manual-power control
sahilmgandhi 18:6a4db94011d3 86 */
sahilmgandhi 18:6a4db94011d3 87 FCache_Writel(SYS_FCACHE_CCR, (FCACHE_EN
sahilmgandhi 18:6a4db94011d3 88 | FCACHE_POW_REQ
sahilmgandhi 18:6a4db94011d3 89 | FCACHE_SET_MAN_POW
sahilmgandhi 18:6a4db94011d3 90 | FCACHE_SET_MAN_INV
sahilmgandhi 18:6a4db94011d3 91 | FCACHE_STATISTIC_EN));
sahilmgandhi 18:6a4db94011d3 92 /* Wait until the cache is enabled */
sahilmgandhi 18:6a4db94011d3 93 while ((FCache_Readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_ENABLED);
sahilmgandhi 18:6a4db94011d3 94 /* Cache Enabled: Set enabled to 1 */
sahilmgandhi 18:6a4db94011d3 95 enabled = 1;
sahilmgandhi 18:6a4db94011d3 96 break;
sahilmgandhi 18:6a4db94011d3 97 default:
sahilmgandhi 18:6a4db94011d3 98 break;
sahilmgandhi 18:6a4db94011d3 99 }
sahilmgandhi 18:6a4db94011d3 100 }
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102 /*
sahilmgandhi 18:6a4db94011d3 103 * FCache_Disable: Disables the flash cache mode previously enabled
sahilmgandhi 18:6a4db94011d3 104 */
sahilmgandhi 18:6a4db94011d3 105 void FCache_Disable()
sahilmgandhi 18:6a4db94011d3 106 {
sahilmgandhi 18:6a4db94011d3 107 /* Disable the FCache */
sahilmgandhi 18:6a4db94011d3 108 switch (fcache_mode) {
sahilmgandhi 18:6a4db94011d3 109 case 0:
sahilmgandhi 18:6a4db94011d3 110 /* Statistic counters enabled, Cache disable,
sahilmgandhi 18:6a4db94011d3 111 * auto-inval, auto-power control
sahilmgandhi 18:6a4db94011d3 112 */
sahilmgandhi 18:6a4db94011d3 113 FCache_Writel(SYS_FCACHE_CCR, FCACHE_STATISTIC_EN);
sahilmgandhi 18:6a4db94011d3 114 /* Wait until the cache is disabled */
sahilmgandhi 18:6a4db94011d3 115 while ((FCache_Readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_DISABLED);
sahilmgandhi 18:6a4db94011d3 116 /* Cache Enabled: Set enabled to 0 */
sahilmgandhi 18:6a4db94011d3 117 enabled = 0;
sahilmgandhi 18:6a4db94011d3 118 break;
sahilmgandhi 18:6a4db94011d3 119 case 1:
sahilmgandhi 18:6a4db94011d3 120 /* Statistic counters enabled, Cache disable,
sahilmgandhi 18:6a4db94011d3 121 * manual-inval, manual-power control
sahilmgandhi 18:6a4db94011d3 122 */
sahilmgandhi 18:6a4db94011d3 123 FCache_Writel(SYS_FCACHE_CCR, (FCACHE_POW_REQ
sahilmgandhi 18:6a4db94011d3 124 | FCACHE_SET_MAN_POW
sahilmgandhi 18:6a4db94011d3 125 | FCACHE_SET_MAN_INV
sahilmgandhi 18:6a4db94011d3 126 | FCACHE_STATISTIC_EN));
sahilmgandhi 18:6a4db94011d3 127 /* Wait until the cache is disabled */
sahilmgandhi 18:6a4db94011d3 128 while ((FCache_Readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_DISABLED);
sahilmgandhi 18:6a4db94011d3 129 /* Cache Enabled: Set enabled to 0 */
sahilmgandhi 18:6a4db94011d3 130 enabled = 0;
sahilmgandhi 18:6a4db94011d3 131 break;
sahilmgandhi 18:6a4db94011d3 132 default:
sahilmgandhi 18:6a4db94011d3 133 break;
sahilmgandhi 18:6a4db94011d3 134 }
sahilmgandhi 18:6a4db94011d3 135 }
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137 /*
sahilmgandhi 18:6a4db94011d3 138 * FCache_Invalidate: to be invalidated the cache needs to be disabled.
sahilmgandhi 18:6a4db94011d3 139 * return -1: flash cannot be disabled
sahilmgandhi 18:6a4db94011d3 140 * -2: flash cannot be enabled
sahilmgandhi 18:6a4db94011d3 141 */
sahilmgandhi 18:6a4db94011d3 142 int FCache_Invalidate()
sahilmgandhi 18:6a4db94011d3 143 {
sahilmgandhi 18:6a4db94011d3 144 /* Manual cache invalidate */
sahilmgandhi 18:6a4db94011d3 145 if (fcache_mode == 1)
sahilmgandhi 18:6a4db94011d3 146 {
sahilmgandhi 18:6a4db94011d3 147 /* Disable Flash Cache */
sahilmgandhi 18:6a4db94011d3 148 if (enabled == 1)
sahilmgandhi 18:6a4db94011d3 149 FCache_Disable();
sahilmgandhi 18:6a4db94011d3 150 else
sahilmgandhi 18:6a4db94011d3 151 goto error;
sahilmgandhi 18:6a4db94011d3 152
sahilmgandhi 18:6a4db94011d3 153 /* Trigger INV_REQ */
sahilmgandhi 18:6a4db94011d3 154 FCache_Writel(SYS_FCACHE_CCR, (FCACHE_INV_REQ
sahilmgandhi 18:6a4db94011d3 155 | FCACHE_POW_REQ
sahilmgandhi 18:6a4db94011d3 156 | FCACHE_SET_MAN_POW
sahilmgandhi 18:6a4db94011d3 157 | FCACHE_SET_MAN_INV
sahilmgandhi 18:6a4db94011d3 158 | FCACHE_STATISTIC_EN));
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 /* Wait until INV_REQ is finished */
sahilmgandhi 18:6a4db94011d3 161 while ((FCache_Readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_DISABLED);
sahilmgandhi 18:6a4db94011d3 162
sahilmgandhi 18:6a4db94011d3 163 /* Clear Stats */
sahilmgandhi 18:6a4db94011d3 164 FCache_Writel(SYS_FCACHE_CSHR, 0);
sahilmgandhi 18:6a4db94011d3 165 FCache_Writel(SYS_FCACHE_CSMR, 0);
sahilmgandhi 18:6a4db94011d3 166
sahilmgandhi 18:6a4db94011d3 167 /* Enable Flash Cache */
sahilmgandhi 18:6a4db94011d3 168 if (enabled == 0)
sahilmgandhi 18:6a4db94011d3 169 FCache_Enable(1);
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 error:
sahilmgandhi 18:6a4db94011d3 172 if (enabled == 0)
sahilmgandhi 18:6a4db94011d3 173 return -1;
sahilmgandhi 18:6a4db94011d3 174 else
sahilmgandhi 18:6a4db94011d3 175 return -2;
sahilmgandhi 18:6a4db94011d3 176 }
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178 return 0;
sahilmgandhi 18:6a4db94011d3 179 }
sahilmgandhi 18:6a4db94011d3 180
sahilmgandhi 18:6a4db94011d3 181 unsigned int * FCache_GetStats()
sahilmgandhi 18:6a4db94011d3 182 {
sahilmgandhi 18:6a4db94011d3 183 static unsigned int stats[2];
sahilmgandhi 18:6a4db94011d3 184
sahilmgandhi 18:6a4db94011d3 185 /* Cache Statistics HIT Register */
sahilmgandhi 18:6a4db94011d3 186 stats[0] = FCache_Readl(SYS_FCACHE_CSHR);
sahilmgandhi 18:6a4db94011d3 187 /* Cache Statistics MISS Register */
sahilmgandhi 18:6a4db94011d3 188 stats[1] = FCache_Readl(SYS_FCACHE_CSMR);
sahilmgandhi 18:6a4db94011d3 189
sahilmgandhi 18:6a4db94011d3 190 return stats;
sahilmgandhi 18:6a4db94011d3 191 }
sahilmgandhi 18:6a4db94011d3 192
sahilmgandhi 18:6a4db94011d3 193 /*
sahilmgandhi 18:6a4db94011d3 194 * FCache_isEnabled: returns 1 if FCache is enabled
sahilmgandhi 18:6a4db94011d3 195 */
sahilmgandhi 18:6a4db94011d3 196 unsigned int FCache_isEnabled()
sahilmgandhi 18:6a4db94011d3 197 {
sahilmgandhi 18:6a4db94011d3 198 return enabled;
sahilmgandhi 18:6a4db94011d3 199 }