MouseCode - Mouse code for the MacroRat

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Mouse code for the MacroRat

Dependencies: ITG3200 QEI

mbed-dev/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/CMSDK_BEETLE.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:: sahilmgandhi
Date:: Sat Jun 03 00:22:44 2017 +0000
Revision:: 46:b156ef445742
Parent:: 18:6a4db94011d3

Final code for internal battlebot competition.

Who changed what in which revision?

User	Revision	Line number	New contents of line
sahilmgandhi	18:6a4db94011d3	1	/*
sahilmgandhi	18:6a4db94011d3	2	* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
sahilmgandhi	18:6a4db94011d3	3	*
sahilmgandhi	18:6a4db94011d3	4	* SPDX-License-Identifier: Apache-2.0
sahilmgandhi	18:6a4db94011d3	5	*
sahilmgandhi	18:6a4db94011d3	6	* Licensed under the Apache License, Version 2.0 (the License); you may
sahilmgandhi	18:6a4db94011d3	7	* not use this file except in compliance with the License.
sahilmgandhi	18:6a4db94011d3	8	* You may obtain a copy of the License at
sahilmgandhi	18:6a4db94011d3	9	*
sahilmgandhi	18:6a4db94011d3	10	* http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi	18:6a4db94011d3	11	*
sahilmgandhi	18:6a4db94011d3	12	* Unless required by applicable law or agreed to in writing, software
sahilmgandhi	18:6a4db94011d3	13	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
sahilmgandhi	18:6a4db94011d3	14	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi	18:6a4db94011d3	15	* See the License for the specific language governing permissions and
sahilmgandhi	18:6a4db94011d3	16	* limitations under the License.
sahilmgandhi	18:6a4db94011d3	17	*/
sahilmgandhi	18:6a4db94011d3	18	/*
sahilmgandhi	18:6a4db94011d3	19	* This file is derivative of CMSIS V5.00 ARMCM3.h
sahilmgandhi	18:6a4db94011d3	20	*/
sahilmgandhi	18:6a4db94011d3	21
sahilmgandhi	18:6a4db94011d3	22
sahilmgandhi	18:6a4db94011d3	23	#ifndef CMSDK_BEETLE_H
sahilmgandhi	18:6a4db94011d3	24	#define CMSDK_BEETLE_H
sahilmgandhi	18:6a4db94011d3	25
sahilmgandhi	18:6a4db94011d3	26	#ifdef __cplusplus
sahilmgandhi	18:6a4db94011d3	27	extern "C" {
sahilmgandhi	18:6a4db94011d3	28	#endif
sahilmgandhi	18:6a4db94011d3	29
sahilmgandhi	18:6a4db94011d3	30
sahilmgandhi	18:6a4db94011d3	31	/* ------------------------- Interrupt Number Definition ------------------------ */
sahilmgandhi	18:6a4db94011d3	32
sahilmgandhi	18:6a4db94011d3	33	typedef enum IRQn
sahilmgandhi	18:6a4db94011d3	34	{
sahilmgandhi	18:6a4db94011d3	35	/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
sahilmgandhi	18:6a4db94011d3	36	NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
sahilmgandhi	18:6a4db94011d3	37	HardFault_IRQn = -13, /* 3 HardFault Interrupt */
sahilmgandhi	18:6a4db94011d3	38	MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
sahilmgandhi	18:6a4db94011d3	39	BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
sahilmgandhi	18:6a4db94011d3	40	UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
sahilmgandhi	18:6a4db94011d3	41	SVCall_IRQn = -5, /* 11 SV Call Interrupt */
sahilmgandhi	18:6a4db94011d3	42	DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
sahilmgandhi	18:6a4db94011d3	43	PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
sahilmgandhi	18:6a4db94011d3	44	SysTick_IRQn = -1, /* 15 System Tick Interrupt */
sahilmgandhi	18:6a4db94011d3	45
sahilmgandhi	18:6a4db94011d3	46	/* --------------------- CMSDK_BEETLE Specific Interrupt Numbers ---------------- */
sahilmgandhi	18:6a4db94011d3	47	UART0_IRQn = 0, /* UART 0 RX and TX Combined Interrupt */
sahilmgandhi	18:6a4db94011d3	48	Spare_IRQn = 1, /* Undefined */
sahilmgandhi	18:6a4db94011d3	49	UART1_IRQn = 2, /* UART 1 RX and TX Combined Interrupt */
sahilmgandhi	18:6a4db94011d3	50	I2C0_IRQn = 3, /* I2C 0 Interrupt */
sahilmgandhi	18:6a4db94011d3	51	I2C1_IRQn = 4, /* I2C 1 Interrupt */
sahilmgandhi	18:6a4db94011d3	52	RTC_IRQn = 5, /* RTC Interrupt */
sahilmgandhi	18:6a4db94011d3	53	PORT0_ALL_IRQn = 6, /* GPIO Port 0 combined Interrupt */
sahilmgandhi	18:6a4db94011d3	54	PORT1_ALL_IRQn = 7, /* GPIO Port 1 combined Interrupt */
sahilmgandhi	18:6a4db94011d3	55	TIMER0_IRQn = 8, /* TIMER 0 Interrupt */
sahilmgandhi	18:6a4db94011d3	56	TIMER1_IRQn = 9, /* TIMER 1 Interrupt */
sahilmgandhi	18:6a4db94011d3	57	DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */
sahilmgandhi	18:6a4db94011d3	58	SPI0_IRQn = 11, /* SPI 0 Interrupt */
sahilmgandhi	18:6a4db94011d3	59	UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */
sahilmgandhi	18:6a4db94011d3	60	SPI1_IRQn = 13, /* SPI 1 Interrupt */
sahilmgandhi	18:6a4db94011d3	61	QSPI_IRQn = 14, /* QUAD SPI Interrupt */
sahilmgandhi	18:6a4db94011d3	62	DMA_IRQn = 15, /* Reserved for DMA Interrup */
sahilmgandhi	18:6a4db94011d3	63	PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */
sahilmgandhi	18:6a4db94011d3	64	PORT0_1_IRQn = 17, /* There are 16 pins in total */
sahilmgandhi	18:6a4db94011d3	65	PORT0_2_IRQn = 18,
sahilmgandhi	18:6a4db94011d3	66	PORT0_3_IRQn = 19,
sahilmgandhi	18:6a4db94011d3	67	PORT0_4_IRQn = 20,
sahilmgandhi	18:6a4db94011d3	68	PORT0_5_IRQn = 21,
sahilmgandhi	18:6a4db94011d3	69	PORT0_6_IRQn = 22,
sahilmgandhi	18:6a4db94011d3	70	PORT0_7_IRQn = 23,
sahilmgandhi	18:6a4db94011d3	71	PORT0_8_IRQn = 24,
sahilmgandhi	18:6a4db94011d3	72	PORT0_9_IRQn = 25,
sahilmgandhi	18:6a4db94011d3	73	PORT0_10_IRQn = 26,
sahilmgandhi	18:6a4db94011d3	74	PORT0_11_IRQn = 27,
sahilmgandhi	18:6a4db94011d3	75	PORT0_12_IRQn = 28,
sahilmgandhi	18:6a4db94011d3	76	PORT0_13_IRQn = 29,
sahilmgandhi	18:6a4db94011d3	77	PORT0_14_IRQn = 30,
sahilmgandhi	18:6a4db94011d3	78	PORT0_15_IRQn = 31,
sahilmgandhi	18:6a4db94011d3	79	SYSERROR_IRQn = 32, /* System Error Interrupt */
sahilmgandhi	18:6a4db94011d3	80	EFLASH_IRQn = 33, /* Embedded Flash Interrupt */
sahilmgandhi	18:6a4db94011d3	81	LLCC_TXCMD_EMPTY_IRQn = 34, /* t.b.a */
sahilmgandhi	18:6a4db94011d3	82	LLCC_TXEVT_EMPTY_IRQn = 35, /* t.b.a */
sahilmgandhi	18:6a4db94011d3	83	LLCC_TXDMAH_DONE_IRQn = 36, /* t.b.a */
sahilmgandhi	18:6a4db94011d3	84	LLCC_TXDMAL_DONE_IRQn = 37, /* t.b.a */
sahilmgandhi	18:6a4db94011d3	85	LLCC_RXCMD_VALID_IRQn = 38, /* t.b.a */
sahilmgandhi	18:6a4db94011d3	86	LLCC_RXEVT_VALID_IRQn = 39, /* t.b.a */
sahilmgandhi	18:6a4db94011d3	87	LLCC_RXDMAH_DONE_IRQn = 40, /* t.b.a */
sahilmgandhi	18:6a4db94011d3	88	LLCC_RXDMAL_DONE_IRQn = 41, /* t.b.a */
sahilmgandhi	18:6a4db94011d3	89	PORT2_ALL_IRQn = 42, /* GPIO Port 2 combined Interrupt */
sahilmgandhi	18:6a4db94011d3	90	PORT3_ALL_IRQn = 43, /* GPIO Port 3 combined Interrupt */
sahilmgandhi	18:6a4db94011d3	91	TRNG_IRQn = 44, /* Random number generator Interrupt */
sahilmgandhi	18:6a4db94011d3	92	} IRQn_Type;
sahilmgandhi	18:6a4db94011d3	93
sahilmgandhi	18:6a4db94011d3	94
sahilmgandhi	18:6a4db94011d3	95	/* ================================================================================ */
sahilmgandhi	18:6a4db94011d3	96	/* ================ Processor and Core Peripheral Section ================ */
sahilmgandhi	18:6a4db94011d3	97	/* ================================================================================ */
sahilmgandhi	18:6a4db94011d3	98
sahilmgandhi	18:6a4db94011d3	99	/* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */
sahilmgandhi	18:6a4db94011d3	100	#define __CM3_REV 0x0201U /* Core revision r2p1 */
sahilmgandhi	18:6a4db94011d3	101	#define __MPU_PRESENT 1 /* MPU present */
sahilmgandhi	18:6a4db94011d3	102	#define __VTOR_PRESENT 1 /* VTOR present or not */
sahilmgandhi	18:6a4db94011d3	103	#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
sahilmgandhi	18:6a4db94011d3	104	#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
sahilmgandhi	18:6a4db94011d3	105
sahilmgandhi	18:6a4db94011d3	106	#include <core_cm3.h> /* Processor and core peripherals */
sahilmgandhi	18:6a4db94011d3	107	#include "system_CMSDK_BEETLE.h" /* System Header */
sahilmgandhi	18:6a4db94011d3	108
sahilmgandhi	18:6a4db94011d3	109
sahilmgandhi	18:6a4db94011d3	110	/* ================================================================================ */
sahilmgandhi	18:6a4db94011d3	111	/* ================ Device Specific Peripheral Section ================ */
sahilmgandhi	18:6a4db94011d3	112	/* ================================================================================ */
sahilmgandhi	18:6a4db94011d3	113
sahilmgandhi	18:6a4db94011d3	114	/* ------------------- Start of section using anonymous unions ------------------ */
sahilmgandhi	18:6a4db94011d3	115	#if defined ( __CC_ARM )
sahilmgandhi	18:6a4db94011d3	116	#pragma push
sahilmgandhi	18:6a4db94011d3	117	#pragma anon_unions
sahilmgandhi	18:6a4db94011d3	118	#elif defined(__ICCARM__)
sahilmgandhi	18:6a4db94011d3	119	#pragma language=extended
sahilmgandhi	18:6a4db94011d3	120	#elif defined(__GNUC__)
sahilmgandhi	18:6a4db94011d3	121	/* anonymous unions are enabled by default */
sahilmgandhi	18:6a4db94011d3	122	#elif defined(__TMS470__)
sahilmgandhi	18:6a4db94011d3	123	/* anonymous unions are enabled by default */
sahilmgandhi	18:6a4db94011d3	124	#elif defined(__TASKING__)
sahilmgandhi	18:6a4db94011d3	125	#pragma warning 586
sahilmgandhi	18:6a4db94011d3	126	#else
sahilmgandhi	18:6a4db94011d3	127	#warning Not supported compiler type
sahilmgandhi	18:6a4db94011d3	128	#endif
sahilmgandhi	18:6a4db94011d3	129
sahilmgandhi	18:6a4db94011d3	130	/* ======================================================================== */
sahilmgandhi	18:6a4db94011d3	131	/* ============ LLCC/DMAC v1 ============ */
sahilmgandhi	18:6a4db94011d3	132	/* ======================================================================== */
sahilmgandhi	18:6a4db94011d3	133
sahilmgandhi	18:6a4db94011d3	134	typedef struct
sahilmgandhi	18:6a4db94011d3	135	{
sahilmgandhi	18:6a4db94011d3	136	__IO uint32_t BUF_STATE; // +0x00
sahilmgandhi	18:6a4db94011d3	137	__I uint32_t STATUS; // +0x00
sahilmgandhi	18:6a4db94011d3	138	__IO uint32_t PTR_ADDR; // +0x08
sahilmgandhi	18:6a4db94011d3	139	__IO uint32_t PTR_CTRL; // +0x0c
sahilmgandhi	18:6a4db94011d3	140	__O uint32_t NXT_ADDR; // +0x10
sahilmgandhi	18:6a4db94011d3	141	__O uint32_t NXT_CTRL; // +0x14
sahilmgandhi	18:6a4db94011d3	142	__I uint32_t rsvd_18[2]; // +0x18
sahilmgandhi	18:6a4db94011d3	143	__IO uint32_t BUF0_ADDR; // +0x20
sahilmgandhi	18:6a4db94011d3	144	__IO uint32_t BUF0_CTRL; // +0x24
sahilmgandhi	18:6a4db94011d3	145	__I uint32_t rsvd_28[2]; // +0x28
sahilmgandhi	18:6a4db94011d3	146	__IO uint32_t BUF1_ADDR; // +0x30
sahilmgandhi	18:6a4db94011d3	147	__IO uint32_t BUF1_CTRL; // +0x34
sahilmgandhi	18:6a4db94011d3	148	__IO uint32_t INTEN; // +0x38
sahilmgandhi	18:6a4db94011d3	149	__IO uint32_t IRQSTATUS; // +0x3c
sahilmgandhi	18:6a4db94011d3	150	} DMAC_CHAN_TypeDef;
sahilmgandhi	18:6a4db94011d3	151
sahilmgandhi	18:6a4db94011d3	152	// DMA buffer control state machine
sahilmgandhi	18:6a4db94011d3	153	#define DMAC_BUFSTATE_MT 0
sahilmgandhi	18:6a4db94011d3	154	#define DMAC_BUFSTATE_A 1
sahilmgandhi	18:6a4db94011d3	155	#define DMAC_BUFSTATE_AB 5
sahilmgandhi	18:6a4db94011d3	156	#define DMAC_BUFSTATE_B 2
sahilmgandhi	18:6a4db94011d3	157	#define DMAC_BUFSTATE_BA 6
sahilmgandhi	18:6a4db94011d3	158	#define DMAC_BUFSTATE_FULL_IDX 2
sahilmgandhi	18:6a4db94011d3	159
sahilmgandhi	18:6a4db94011d3	160	// DMA Control structure MASKs
sahilmgandhi	18:6a4db94011d3	161	#define DMAC_CHAN_ADDR_MASK 0xfffffffc
sahilmgandhi	18:6a4db94011d3	162	#define DMAC_CHAN_COUNT_MASK 0x0000ffff
sahilmgandhi	18:6a4db94011d3	163	#define DMAC_CHAN_SIZE_MASK 0x00030000
sahilmgandhi	18:6a4db94011d3	164	#define DMAC_CHAN_AFIX_MASK 0x00040000
sahilmgandhi	18:6a4db94011d3	165	#define DMAC_CHAN_LOOP_MASK 0x00080000
sahilmgandhi	18:6a4db94011d3	166	#define DMAC_CHAN_ATTR_MASK 0xfff00000
sahilmgandhi	18:6a4db94011d3	167	#define DMAC_CHAN_COUNT_IDX_LO 0
sahilmgandhi	18:6a4db94011d3	168	#define DMAC_CHAN_COUNT_IDX_HI 15
sahilmgandhi	18:6a4db94011d3	169	#define DMAC_CHAN_SIZE_IDX_LO 16
sahilmgandhi	18:6a4db94011d3	170	#define DMAC_CHAN_SIZE_IDX_HI 17
sahilmgandhi	18:6a4db94011d3	171	#define DMAC_CHAN_AFIX_IDX 18
sahilmgandhi	18:6a4db94011d3	172	#define DMAC_CHAN_LOOP_IDX 19
sahilmgandhi	18:6a4db94011d3	173	#define DMAC_CHAN_TRIG_IDX_LO 20
sahilmgandhi	18:6a4db94011d3	174	#define DMAC_CHAN_TRIG_IDX_HI 23
sahilmgandhi	18:6a4db94011d3	175	#define DMAC_CHAN_ATTR_IDX_LO 24
sahilmgandhi	18:6a4db94011d3	176	#define DMAC_CHAN_ATTR_IDX_HI 31
sahilmgandhi	18:6a4db94011d3	177	#define DMAC_CHAN_IRQ_IDX 0
sahilmgandhi	18:6a4db94011d3	178	#define DMAC_CHAN_ERR_IDX 1
sahilmgandhi	18:6a4db94011d3	179
sahilmgandhi	18:6a4db94011d3	180	typedef struct
sahilmgandhi	18:6a4db94011d3	181	{
sahilmgandhi	18:6a4db94011d3	182	__I uint32_t ID_MAIN; // +0x0000
sahilmgandhi	18:6a4db94011d3	183	__I uint32_t ID_REV; // +0x0004
sahilmgandhi	18:6a4db94011d3	184	__I uint32_t rsvd_0008[30]; // +0x0008
sahilmgandhi	18:6a4db94011d3	185	__IO uint32_t STANDBY_CTRL; // +0x0080
sahilmgandhi	18:6a4db94011d3	186	} LLCC_CTL_TypeDef;
sahilmgandhi	18:6a4db94011d3	187
sahilmgandhi	18:6a4db94011d3	188	typedef struct
sahilmgandhi	18:6a4db94011d3	189	{
sahilmgandhi	18:6a4db94011d3	190	__I uint32_t CMD_DATA0; // +0x2000
sahilmgandhi	18:6a4db94011d3	191	__I uint32_t CMD_DATA1; // +0x2004
sahilmgandhi	18:6a4db94011d3	192	__I uint32_t rsvd_008[14]; // +0x2008
sahilmgandhi	18:6a4db94011d3	193	__I uint32_t DMAH_DATA0; // +0x2040
sahilmgandhi	18:6a4db94011d3	194	__I uint32_t DMAH_DATA1; // +0x2044
sahilmgandhi	18:6a4db94011d3	195	__I uint32_t rsvd_048[6]; // +0x2048
sahilmgandhi	18:6a4db94011d3	196	__I uint32_t DMAL_DATA0; // +0x2060
sahilmgandhi	18:6a4db94011d3	197	__I uint32_t DMAL_DATA1; // +0x2064
sahilmgandhi	18:6a4db94011d3	198	__I uint32_t rsvd_068[6]; // +0x2068
sahilmgandhi	18:6a4db94011d3	199	__I uint32_t EVT_DATA0; // +0x2080
sahilmgandhi	18:6a4db94011d3	200	__I uint32_t EVT_DATA1; // +0x2084
sahilmgandhi	18:6a4db94011d3	201	__I uint32_t rsvd_088[14]; // +0x2088
sahilmgandhi	18:6a4db94011d3	202	__I uint32_t INTERRUPT; // +0x20c0
sahilmgandhi	18:6a4db94011d3	203	__IO uint32_t INTENMASK; // +0x20c4
sahilmgandhi	18:6a4db94011d3	204	__IO uint32_t INTENMASK_SET; // +0x20c8
sahilmgandhi	18:6a4db94011d3	205	__IO uint32_t INTENMASK_CLR; // +0x20cc
sahilmgandhi	18:6a4db94011d3	206	__I uint32_t REQUEST; // +0x20d0
sahilmgandhi	18:6a4db94011d3	207	__I uint32_t rsvd_0d4[3]; // +0x20d4
sahilmgandhi	18:6a4db94011d3	208	__I uint32_t XFERREQ; // +0x20e0
sahilmgandhi	18:6a4db94011d3	209	__I uint32_t XFERACK; // +0x20e4
sahilmgandhi	18:6a4db94011d3	210	__I uint32_t rsvd_0e8[6]; // +0x20e8
sahilmgandhi	18:6a4db94011d3	211	} LLCC_RXD_TypeDef;
sahilmgandhi	18:6a4db94011d3	212
sahilmgandhi	18:6a4db94011d3	213	typedef struct
sahilmgandhi	18:6a4db94011d3	214	{
sahilmgandhi	18:6a4db94011d3	215	__IO uint32_t CMD_DATA0; // +0x3000
sahilmgandhi	18:6a4db94011d3	216	__IO uint32_t CMD_DATA1; // +0x3004
sahilmgandhi	18:6a4db94011d3	217	__I uint32_t rsvd_008[14]; // +0x3008
sahilmgandhi	18:6a4db94011d3	218	__IO uint32_t DMAH_DATA0; // +0x3040
sahilmgandhi	18:6a4db94011d3	219	__IO uint32_t DMAH_DATA1; // +0x3044
sahilmgandhi	18:6a4db94011d3	220	__I uint32_t rsvd_048[6]; // +0x3048
sahilmgandhi	18:6a4db94011d3	221	__IO uint32_t DMAL_DATA0; // +0x3060
sahilmgandhi	18:6a4db94011d3	222	__IO uint32_t DMAL_DATA1; // +0x3064
sahilmgandhi	18:6a4db94011d3	223	__I uint32_t rsvd_068[6]; // +0x3068
sahilmgandhi	18:6a4db94011d3	224	__IO uint32_t EVT_DATA0; // +0x3080
sahilmgandhi	18:6a4db94011d3	225	__IO uint32_t EVT_DATA1; // +0x3084
sahilmgandhi	18:6a4db94011d3	226	__I uint32_t rsvd_088[14]; // +0x3088
sahilmgandhi	18:6a4db94011d3	227	__I uint32_t INTERRUPT; // +0x30c0
sahilmgandhi	18:6a4db94011d3	228	__IO uint32_t INTENMASK; // +0x30c4
sahilmgandhi	18:6a4db94011d3	229	__IO uint32_t INTENMASK_SET; // +0x30c8
sahilmgandhi	18:6a4db94011d3	230	__IO uint32_t INTENMASK_CLR; // +0x30cc
sahilmgandhi	18:6a4db94011d3	231	__I uint32_t REQUEST; // +0x30d0
sahilmgandhi	18:6a4db94011d3	232	__I uint32_t ACTIVE; // +0x30d4
sahilmgandhi	18:6a4db94011d3	233	__I uint32_t VCREADY; // +0x30d8
sahilmgandhi	18:6a4db94011d3	234	__I uint32_t rsvd_0dc; // +0x30dc
sahilmgandhi	18:6a4db94011d3	235	__IO uint32_t XFERREQ; // +0x30e0
sahilmgandhi	18:6a4db94011d3	236	__I uint32_t XFERACK; // +0x30e4
sahilmgandhi	18:6a4db94011d3	237	__I uint32_t rsvd_0e8[6]; // +0x30e8
sahilmgandhi	18:6a4db94011d3	238	} LLCC_TXD_TypeDef;
sahilmgandhi	18:6a4db94011d3	239
sahilmgandhi	18:6a4db94011d3	240	// TX?RX buffer handshake/interrupt fields
sahilmgandhi	18:6a4db94011d3	241	#define LLCC_CMD0_MASK 0x01
sahilmgandhi	18:6a4db94011d3	242	#define LLCC_CMD1_MASK 0x02
sahilmgandhi	18:6a4db94011d3	243	#define LLCC_CMD_MASK 0x03
sahilmgandhi	18:6a4db94011d3	244	#define LLCC_CMD_IRQ_MASK LLCC_CMD_MASK
sahilmgandhi	18:6a4db94011d3	245	#define LLCC_DMAH1_MASK 0x04
sahilmgandhi	18:6a4db94011d3	246	#define LLCC_DMAH2_MASK 0x08
sahilmgandhi	18:6a4db94011d3	247	#define LLCC_DMAH_MASK 0x0c
sahilmgandhi	18:6a4db94011d3	248	#define LLCC_DMAL1_MASK 0x10
sahilmgandhi	18:6a4db94011d3	249	#define LLCC_DMAL2_MASK 0x20
sahilmgandhi	18:6a4db94011d3	250	#define LLCC_DMAL_MASK 0x30
sahilmgandhi	18:6a4db94011d3	251	#define LLCC_EVT0_MASK 0x40
sahilmgandhi	18:6a4db94011d3	252	#define LLCC_EVT1_MASK 0x80
sahilmgandhi	18:6a4db94011d3	253	#define LLCC_EVT_IRQ_MASK LLCC_EVT1_MASK
sahilmgandhi	18:6a4db94011d3	254	#define LLCC_EVT_MASK 0xc0
sahilmgandhi	18:6a4db94011d3	255	#define LLCC_CMD0_IDX 0
sahilmgandhi	18:6a4db94011d3	256	#define LLCC_CMD1_IDX 1
sahilmgandhi	18:6a4db94011d3	257	#define LLCC_CMD_IDX LLCC_CMD1_IDX
sahilmgandhi	18:6a4db94011d3	258	#define LLCC_CMD_IRQ_IDX 1
sahilmgandhi	18:6a4db94011d3	259	#define LLCC_DMAH1_IDX 2
sahilmgandhi	18:6a4db94011d3	260	#define LLCC_DMAH2_IDX 3
sahilmgandhi	18:6a4db94011d3	261	#define LLCC_DMAL1_IDX 4
sahilmgandhi	18:6a4db94011d3	262	#define LLCC_DMAL2_IDX 5
sahilmgandhi	18:6a4db94011d3	263	#define LLCC_EVT0_IDX 6
sahilmgandhi	18:6a4db94011d3	264	#define LLCC_EVT1_IDX 7
sahilmgandhi	18:6a4db94011d3	265	#define LLCC_EVT_IDX LLCC_EVT1_IDX
sahilmgandhi	18:6a4db94011d3	266
sahilmgandhi	18:6a4db94011d3	267	/------------- Universal Asynchronous Receiver Transmitter (UART) -----------/
sahilmgandhi	18:6a4db94011d3	268	typedef struct
sahilmgandhi	18:6a4db94011d3	269	{
sahilmgandhi	18:6a4db94011d3	270	__IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
sahilmgandhi	18:6a4db94011d3	271	__IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
sahilmgandhi	18:6a4db94011d3	272	__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
sahilmgandhi	18:6a4db94011d3	273	union {
sahilmgandhi	18:6a4db94011d3	274	__I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
sahilmgandhi	18:6a4db94011d3	275	__O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
sahilmgandhi	18:6a4db94011d3	276	};
sahilmgandhi	18:6a4db94011d3	277	__IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
sahilmgandhi	18:6a4db94011d3	278
sahilmgandhi	18:6a4db94011d3	279	} CMSDK_UART_TypeDef;
sahilmgandhi	18:6a4db94011d3	280
sahilmgandhi	18:6a4db94011d3	281	/* CMSDK_UART DATA Register Definitions */
sahilmgandhi	18:6a4db94011d3	282
sahilmgandhi	18:6a4db94011d3	283	#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */
sahilmgandhi	18:6a4db94011d3	284	#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */
sahilmgandhi	18:6a4db94011d3	285
sahilmgandhi	18:6a4db94011d3	286	#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */
sahilmgandhi	18:6a4db94011d3	287	#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */
sahilmgandhi	18:6a4db94011d3	288
sahilmgandhi	18:6a4db94011d3	289	#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */
sahilmgandhi	18:6a4db94011d3	290	#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */
sahilmgandhi	18:6a4db94011d3	291
sahilmgandhi	18:6a4db94011d3	292	#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */
sahilmgandhi	18:6a4db94011d3	293	#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */
sahilmgandhi	18:6a4db94011d3	294
sahilmgandhi	18:6a4db94011d3	295	#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */
sahilmgandhi	18:6a4db94011d3	296	#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */
sahilmgandhi	18:6a4db94011d3	297
sahilmgandhi	18:6a4db94011d3	298	#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */
sahilmgandhi	18:6a4db94011d3	299	#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */
sahilmgandhi	18:6a4db94011d3	300
sahilmgandhi	18:6a4db94011d3	301	#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */
sahilmgandhi	18:6a4db94011d3	302	#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */
sahilmgandhi	18:6a4db94011d3	303
sahilmgandhi	18:6a4db94011d3	304	#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */
sahilmgandhi	18:6a4db94011d3	305	#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */
sahilmgandhi	18:6a4db94011d3	306
sahilmgandhi	18:6a4db94011d3	307	#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */
sahilmgandhi	18:6a4db94011d3	308	#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */
sahilmgandhi	18:6a4db94011d3	309
sahilmgandhi	18:6a4db94011d3	310	#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */
sahilmgandhi	18:6a4db94011d3	311	#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */
sahilmgandhi	18:6a4db94011d3	312
sahilmgandhi	18:6a4db94011d3	313	#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */
sahilmgandhi	18:6a4db94011d3	314	#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */
sahilmgandhi	18:6a4db94011d3	315
sahilmgandhi	18:6a4db94011d3	316	#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */
sahilmgandhi	18:6a4db94011d3	317	#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */
sahilmgandhi	18:6a4db94011d3	318
sahilmgandhi	18:6a4db94011d3	319	#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */
sahilmgandhi	18:6a4db94011d3	320	#define CMSDK_UART_INTSTATUS_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */
sahilmgandhi	18:6a4db94011d3	321
sahilmgandhi	18:6a4db94011d3	322	#define CMSDK_UART_INTSTATUS_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */
sahilmgandhi	18:6a4db94011d3	323	#define CMSDK_UART_INTSTATUS_TXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */
sahilmgandhi	18:6a4db94011d3	324
sahilmgandhi	18:6a4db94011d3	325	#define CMSDK_UART_INTSTATUS_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */
sahilmgandhi	18:6a4db94011d3	326	#define CMSDK_UART_INTSTATUS_RXIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */
sahilmgandhi	18:6a4db94011d3	327
sahilmgandhi	18:6a4db94011d3	328	#define CMSDK_UART_INTSTATUS_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */
sahilmgandhi	18:6a4db94011d3	329	#define CMSDK_UART_INTSTATUS_TXIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */
sahilmgandhi	18:6a4db94011d3	330
sahilmgandhi	18:6a4db94011d3	331	#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */
sahilmgandhi	18:6a4db94011d3	332	#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */
sahilmgandhi	18:6a4db94011d3	333
sahilmgandhi	18:6a4db94011d3	334
sahilmgandhi	18:6a4db94011d3	335	/----------------------------- Timer (TIMER) -------------------------------/
sahilmgandhi	18:6a4db94011d3	336	typedef struct
sahilmgandhi	18:6a4db94011d3	337	{
sahilmgandhi	18:6a4db94011d3	338	__IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
sahilmgandhi	18:6a4db94011d3	339	__IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
sahilmgandhi	18:6a4db94011d3	340	__IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
sahilmgandhi	18:6a4db94011d3	341	union {
sahilmgandhi	18:6a4db94011d3	342	__I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
sahilmgandhi	18:6a4db94011d3	343	__O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
sahilmgandhi	18:6a4db94011d3	344	};
sahilmgandhi	18:6a4db94011d3	345
sahilmgandhi	18:6a4db94011d3	346	} CMSDK_TIMER_TypeDef;
sahilmgandhi	18:6a4db94011d3	347
sahilmgandhi	18:6a4db94011d3	348	/* CMSDK_TIMER CTRL Register Definitions */
sahilmgandhi	18:6a4db94011d3	349
sahilmgandhi	18:6a4db94011d3	350	#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */
sahilmgandhi	18:6a4db94011d3	351	#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */
sahilmgandhi	18:6a4db94011d3	352
sahilmgandhi	18:6a4db94011d3	353	#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */
sahilmgandhi	18:6a4db94011d3	354	#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */
sahilmgandhi	18:6a4db94011d3	355
sahilmgandhi	18:6a4db94011d3	356	#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */
sahilmgandhi	18:6a4db94011d3	357	#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */
sahilmgandhi	18:6a4db94011d3	358
sahilmgandhi	18:6a4db94011d3	359	#define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */
sahilmgandhi	18:6a4db94011d3	360	#define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */
sahilmgandhi	18:6a4db94011d3	361
sahilmgandhi	18:6a4db94011d3	362	#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */
sahilmgandhi	18:6a4db94011d3	363	#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */
sahilmgandhi	18:6a4db94011d3	364
sahilmgandhi	18:6a4db94011d3	365	#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */
sahilmgandhi	18:6a4db94011d3	366	#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */
sahilmgandhi	18:6a4db94011d3	367
sahilmgandhi	18:6a4db94011d3	368	#define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
sahilmgandhi	18:6a4db94011d3	369	#define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */
sahilmgandhi	18:6a4db94011d3	370
sahilmgandhi	18:6a4db94011d3	371	#define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */
sahilmgandhi	18:6a4db94011d3	372	#define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
sahilmgandhi	18:6a4db94011d3	373
sahilmgandhi	18:6a4db94011d3	374
sahilmgandhi	18:6a4db94011d3	375	/------------- Timer (TIM) --------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	376	typedef struct
sahilmgandhi	18:6a4db94011d3	377	{
sahilmgandhi	18:6a4db94011d3	378	__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
sahilmgandhi	18:6a4db94011d3	379	__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
sahilmgandhi	18:6a4db94011d3	380	__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
sahilmgandhi	18:6a4db94011d3	381	__O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
sahilmgandhi	18:6a4db94011d3	382	__I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
sahilmgandhi	18:6a4db94011d3	383	__I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
sahilmgandhi	18:6a4db94011d3	384	__IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
sahilmgandhi	18:6a4db94011d3	385	uint32_t RESERVED0;
sahilmgandhi	18:6a4db94011d3	386	__IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
sahilmgandhi	18:6a4db94011d3	387	__I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
sahilmgandhi	18:6a4db94011d3	388	__IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
sahilmgandhi	18:6a4db94011d3	389	__O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
sahilmgandhi	18:6a4db94011d3	390	__I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
sahilmgandhi	18:6a4db94011d3	391	__I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
sahilmgandhi	18:6a4db94011d3	392	__IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
sahilmgandhi	18:6a4db94011d3	393	uint32_t RESERVED1[945];
sahilmgandhi	18:6a4db94011d3	394	__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
sahilmgandhi	18:6a4db94011d3	395	__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
sahilmgandhi	18:6a4db94011d3	396	} CMSDK_DUALTIMER_BOTH_TypeDef;
sahilmgandhi	18:6a4db94011d3	397
sahilmgandhi	18:6a4db94011d3	398	#define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */
sahilmgandhi	18:6a4db94011d3	399	#define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */
sahilmgandhi	18:6a4db94011d3	400
sahilmgandhi	18:6a4db94011d3	401	#define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */
sahilmgandhi	18:6a4db94011d3	402	#define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */
sahilmgandhi	18:6a4db94011d3	403
sahilmgandhi	18:6a4db94011d3	404	#define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */
sahilmgandhi	18:6a4db94011d3	405	#define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */
sahilmgandhi	18:6a4db94011d3	406
sahilmgandhi	18:6a4db94011d3	407	#define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */
sahilmgandhi	18:6a4db94011d3	408	#define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */
sahilmgandhi	18:6a4db94011d3	409
sahilmgandhi	18:6a4db94011d3	410	#define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */
sahilmgandhi	18:6a4db94011d3	411	#define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */
sahilmgandhi	18:6a4db94011d3	412
sahilmgandhi	18:6a4db94011d3	413	#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */
sahilmgandhi	18:6a4db94011d3	414	#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */
sahilmgandhi	18:6a4db94011d3	415
sahilmgandhi	18:6a4db94011d3	416	#define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */
sahilmgandhi	18:6a4db94011d3	417	#define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */
sahilmgandhi	18:6a4db94011d3	418
sahilmgandhi	18:6a4db94011d3	419	#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */
sahilmgandhi	18:6a4db94011d3	420	#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
sahilmgandhi	18:6a4db94011d3	421
sahilmgandhi	18:6a4db94011d3	422	#define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */
sahilmgandhi	18:6a4db94011d3	423	#define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */
sahilmgandhi	18:6a4db94011d3	424
sahilmgandhi	18:6a4db94011d3	425	#define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */
sahilmgandhi	18:6a4db94011d3	426	#define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */
sahilmgandhi	18:6a4db94011d3	427
sahilmgandhi	18:6a4db94011d3	428	#define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */
sahilmgandhi	18:6a4db94011d3	429	#define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */
sahilmgandhi	18:6a4db94011d3	430
sahilmgandhi	18:6a4db94011d3	431	#define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */
sahilmgandhi	18:6a4db94011d3	432	#define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */
sahilmgandhi	18:6a4db94011d3	433
sahilmgandhi	18:6a4db94011d3	434	#define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */
sahilmgandhi	18:6a4db94011d3	435	#define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */
sahilmgandhi	18:6a4db94011d3	436
sahilmgandhi	18:6a4db94011d3	437	#define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */
sahilmgandhi	18:6a4db94011d3	438	#define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */
sahilmgandhi	18:6a4db94011d3	439
sahilmgandhi	18:6a4db94011d3	440	#define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */
sahilmgandhi	18:6a4db94011d3	441	#define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */
sahilmgandhi	18:6a4db94011d3	442
sahilmgandhi	18:6a4db94011d3	443	#define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */
sahilmgandhi	18:6a4db94011d3	444	#define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */
sahilmgandhi	18:6a4db94011d3	445
sahilmgandhi	18:6a4db94011d3	446	#define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */
sahilmgandhi	18:6a4db94011d3	447	#define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */
sahilmgandhi	18:6a4db94011d3	448
sahilmgandhi	18:6a4db94011d3	449	#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */
sahilmgandhi	18:6a4db94011d3	450	#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */
sahilmgandhi	18:6a4db94011d3	451
sahilmgandhi	18:6a4db94011d3	452	#define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */
sahilmgandhi	18:6a4db94011d3	453	#define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */
sahilmgandhi	18:6a4db94011d3	454
sahilmgandhi	18:6a4db94011d3	455	#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */
sahilmgandhi	18:6a4db94011d3	456	#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
sahilmgandhi	18:6a4db94011d3	457
sahilmgandhi	18:6a4db94011d3	458	#define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */
sahilmgandhi	18:6a4db94011d3	459	#define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */
sahilmgandhi	18:6a4db94011d3	460
sahilmgandhi	18:6a4db94011d3	461	#define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */
sahilmgandhi	18:6a4db94011d3	462	#define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */
sahilmgandhi	18:6a4db94011d3	463
sahilmgandhi	18:6a4db94011d3	464	#define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */
sahilmgandhi	18:6a4db94011d3	465	#define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */
sahilmgandhi	18:6a4db94011d3	466
sahilmgandhi	18:6a4db94011d3	467	#define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */
sahilmgandhi	18:6a4db94011d3	468	#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
sahilmgandhi	18:6a4db94011d3	469
sahilmgandhi	18:6a4db94011d3	470
sahilmgandhi	18:6a4db94011d3	471	typedef struct
sahilmgandhi	18:6a4db94011d3	472	{
sahilmgandhi	18:6a4db94011d3	473	__IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
sahilmgandhi	18:6a4db94011d3	474	__I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
sahilmgandhi	18:6a4db94011d3	475	__IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
sahilmgandhi	18:6a4db94011d3	476	__O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
sahilmgandhi	18:6a4db94011d3	477	__I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
sahilmgandhi	18:6a4db94011d3	478	__I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
sahilmgandhi	18:6a4db94011d3	479	__IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
sahilmgandhi	18:6a4db94011d3	480	} CMSDK_DUALTIMER_SINGLE_TypeDef;
sahilmgandhi	18:6a4db94011d3	481
sahilmgandhi	18:6a4db94011d3	482	#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */
sahilmgandhi	18:6a4db94011d3	483	#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */
sahilmgandhi	18:6a4db94011d3	484
sahilmgandhi	18:6a4db94011d3	485	#define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */
sahilmgandhi	18:6a4db94011d3	486	#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */
sahilmgandhi	18:6a4db94011d3	487
sahilmgandhi	18:6a4db94011d3	488	#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
sahilmgandhi	18:6a4db94011d3	489	#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
sahilmgandhi	18:6a4db94011d3	490
sahilmgandhi	18:6a4db94011d3	491	#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
sahilmgandhi	18:6a4db94011d3	492	#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
sahilmgandhi	18:6a4db94011d3	493
sahilmgandhi	18:6a4db94011d3	494	#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
sahilmgandhi	18:6a4db94011d3	495	#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
sahilmgandhi	18:6a4db94011d3	496
sahilmgandhi	18:6a4db94011d3	497	#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
sahilmgandhi	18:6a4db94011d3	498	#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
sahilmgandhi	18:6a4db94011d3	499
sahilmgandhi	18:6a4db94011d3	500	#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
sahilmgandhi	18:6a4db94011d3	501	#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
sahilmgandhi	18:6a4db94011d3	502
sahilmgandhi	18:6a4db94011d3	503	#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
sahilmgandhi	18:6a4db94011d3	504	#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
sahilmgandhi	18:6a4db94011d3	505
sahilmgandhi	18:6a4db94011d3	506	#define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */
sahilmgandhi	18:6a4db94011d3	507	#define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */
sahilmgandhi	18:6a4db94011d3	508
sahilmgandhi	18:6a4db94011d3	509	#define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
sahilmgandhi	18:6a4db94011d3	510	#define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
sahilmgandhi	18:6a4db94011d3	511
sahilmgandhi	18:6a4db94011d3	512	#define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
sahilmgandhi	18:6a4db94011d3	513	#define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
sahilmgandhi	18:6a4db94011d3	514
sahilmgandhi	18:6a4db94011d3	515	#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */
sahilmgandhi	18:6a4db94011d3	516	#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */
sahilmgandhi	18:6a4db94011d3	517
sahilmgandhi	18:6a4db94011d3	518
sahilmgandhi	18:6a4db94011d3	519	/-------------------- General Purpose Input Output (GPIO) -------------------/
sahilmgandhi	18:6a4db94011d3	520	typedef struct
sahilmgandhi	18:6a4db94011d3	521	{
sahilmgandhi	18:6a4db94011d3	522	__IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
sahilmgandhi	18:6a4db94011d3	523	__IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
sahilmgandhi	18:6a4db94011d3	524	uint32_t RESERVED0[2];
sahilmgandhi	18:6a4db94011d3	525	__IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
sahilmgandhi	18:6a4db94011d3	526	__IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
sahilmgandhi	18:6a4db94011d3	527	__IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
sahilmgandhi	18:6a4db94011d3	528	__IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
sahilmgandhi	18:6a4db94011d3	529	__IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
sahilmgandhi	18:6a4db94011d3	530	__IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
sahilmgandhi	18:6a4db94011d3	531	__IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
sahilmgandhi	18:6a4db94011d3	532	__IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
sahilmgandhi	18:6a4db94011d3	533	__IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
sahilmgandhi	18:6a4db94011d3	534	__IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
sahilmgandhi	18:6a4db94011d3	535	union {
sahilmgandhi	18:6a4db94011d3	536	__I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
sahilmgandhi	18:6a4db94011d3	537	__O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
sahilmgandhi	18:6a4db94011d3	538	};
sahilmgandhi	18:6a4db94011d3	539	uint32_t RESERVED1[241];
sahilmgandhi	18:6a4db94011d3	540	__IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
sahilmgandhi	18:6a4db94011d3	541	__IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
sahilmgandhi	18:6a4db94011d3	542	} CMSDK_GPIO_TypeDef;
sahilmgandhi	18:6a4db94011d3	543
sahilmgandhi	18:6a4db94011d3	544	#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */
sahilmgandhi	18:6a4db94011d3	545	#define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */
sahilmgandhi	18:6a4db94011d3	546
sahilmgandhi	18:6a4db94011d3	547	#define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */
sahilmgandhi	18:6a4db94011d3	548	#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */
sahilmgandhi	18:6a4db94011d3	549
sahilmgandhi	18:6a4db94011d3	550	#define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
sahilmgandhi	18:6a4db94011d3	551	#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
sahilmgandhi	18:6a4db94011d3	552
sahilmgandhi	18:6a4db94011d3	553	#define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
sahilmgandhi	18:6a4db94011d3	554	#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
sahilmgandhi	18:6a4db94011d3	555
sahilmgandhi	18:6a4db94011d3	556	#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
sahilmgandhi	18:6a4db94011d3	557	#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
sahilmgandhi	18:6a4db94011d3	558
sahilmgandhi	18:6a4db94011d3	559	#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
sahilmgandhi	18:6a4db94011d3	560	#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
sahilmgandhi	18:6a4db94011d3	561
sahilmgandhi	18:6a4db94011d3	562	#define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
sahilmgandhi	18:6a4db94011d3	563	#define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
sahilmgandhi	18:6a4db94011d3	564
sahilmgandhi	18:6a4db94011d3	565	#define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
sahilmgandhi	18:6a4db94011d3	566	#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
sahilmgandhi	18:6a4db94011d3	567
sahilmgandhi	18:6a4db94011d3	568	#define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
sahilmgandhi	18:6a4db94011d3	569	#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
sahilmgandhi	18:6a4db94011d3	570
sahilmgandhi	18:6a4db94011d3	571	#define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
sahilmgandhi	18:6a4db94011d3	572	#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
sahilmgandhi	18:6a4db94011d3	573
sahilmgandhi	18:6a4db94011d3	574	#define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
sahilmgandhi	18:6a4db94011d3	575	#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
sahilmgandhi	18:6a4db94011d3	576
sahilmgandhi	18:6a4db94011d3	577	#define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
sahilmgandhi	18:6a4db94011d3	578	#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
sahilmgandhi	18:6a4db94011d3	579
sahilmgandhi	18:6a4db94011d3	580	#define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */
sahilmgandhi	18:6a4db94011d3	581	#define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
sahilmgandhi	18:6a4db94011d3	582
sahilmgandhi	18:6a4db94011d3	583	#define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */
sahilmgandhi	18:6a4db94011d3	584	#define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
sahilmgandhi	18:6a4db94011d3	585
sahilmgandhi	18:6a4db94011d3	586	#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
sahilmgandhi	18:6a4db94011d3	587	#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
sahilmgandhi	18:6a4db94011d3	588
sahilmgandhi	18:6a4db94011d3	589	#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
sahilmgandhi	18:6a4db94011d3	590	#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
sahilmgandhi	18:6a4db94011d3	591
sahilmgandhi	18:6a4db94011d3	592
sahilmgandhi	18:6a4db94011d3	593	/------------- System Control (SYSCON) --------------------------------------/
sahilmgandhi	18:6a4db94011d3	594	typedef struct
sahilmgandhi	18:6a4db94011d3	595	{
sahilmgandhi	18:6a4db94011d3	596	__IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
sahilmgandhi	18:6a4db94011d3	597	__IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
sahilmgandhi	18:6a4db94011d3	598	__IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
sahilmgandhi	18:6a4db94011d3	599	__IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
sahilmgandhi	18:6a4db94011d3	600	__IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
sahilmgandhi	18:6a4db94011d3	601	uint32_t RESERVED0[3];
sahilmgandhi	18:6a4db94011d3	602	__IO uint32_t AHBPER0SET; /* Offset: 0x020 (R/W)AHB peripheral access control set */
sahilmgandhi	18:6a4db94011d3	603	__IO uint32_t AHBPER0CLR; /* Offset: 0x024 (R/W)AHB peripheral access control clear */
sahilmgandhi	18:6a4db94011d3	604	uint32_t RESERVED1[2];
sahilmgandhi	18:6a4db94011d3	605	__IO uint32_t APBPER0SET; /* Offset: 0x030 (R/W)APB peripheral access control set */
sahilmgandhi	18:6a4db94011d3	606	__IO uint32_t APBPER0CLR; /* Offset: 0x034 (R/W)APB peripheral access control clear */
sahilmgandhi	18:6a4db94011d3	607	uint32_t RESERVED2[2];
sahilmgandhi	18:6a4db94011d3	608	__IO uint32_t MAINCLK; /* Offset: 0x040 (R/W) Main Clock Control Register */
sahilmgandhi	18:6a4db94011d3	609	__IO uint32_t AUXCLK; /* Offset: 0x044 (R/W) Auxiliary / RTC Control Register */
sahilmgandhi	18:6a4db94011d3	610	__IO uint32_t PLLCTRL; /* Offset: 0x048 (R/W) PLL Control Register */
sahilmgandhi	18:6a4db94011d3	611	__IO uint32_t PLLSTATUS; /* Offset: 0x04C (R/W) PLL Status Register */
sahilmgandhi	18:6a4db94011d3	612	__IO uint32_t SLEEPCFG; /* Offset: 0x050 (R/W) Sleep Control Register */
sahilmgandhi	18:6a4db94011d3	613	__IO uint32_t FLASHAUXCFG; /* Offset: 0x054 (R/W) Flash auxiliary settings Control Register */
sahilmgandhi	18:6a4db94011d3	614	uint32_t RESERVED3[10];
sahilmgandhi	18:6a4db94011d3	615	__IO uint32_t AHBCLKCFG0SET; /* Offset: 0x080 (R/W) AHB Peripheral Clock set in Active state */
sahilmgandhi	18:6a4db94011d3	616	__IO uint32_t AHBCLKCFG0CLR; /* Offset: 0x084 (R/W) AHB Peripheral Clock clear in Active state */
sahilmgandhi	18:6a4db94011d3	617	__IO uint32_t AHBCLKCFG1SET; /* Offset: 0x088 (R/W) AHB Peripheral Clock set in Sleep state */
sahilmgandhi	18:6a4db94011d3	618	__IO uint32_t AHBCLKCFG1CLR; /* Offset: 0x08C (R/W) AHB Peripheral Clock clear in Sleep state */
sahilmgandhi	18:6a4db94011d3	619	__IO uint32_t AHBCLKCFG2SET; /* Offset: 0x090 (R/W) AHB Peripheral Clock set in Deep Sleep state */
sahilmgandhi	18:6a4db94011d3	620	__IO uint32_t AHBCLKCFG2CLR; /* Offset: 0x094 (R/W) AHB Peripheral Clock clear in Deep Sleep state */
sahilmgandhi	18:6a4db94011d3	621	uint32_t RESERVED4[2];
sahilmgandhi	18:6a4db94011d3	622	__IO uint32_t APBCLKCFG0SET; /* Offset: 0x0A0 (R/W) APB Peripheral Clock set in Active state */
sahilmgandhi	18:6a4db94011d3	623	__IO uint32_t APBCLKCFG0CLR; /* Offset: 0x0A4 (R/W) APB Peripheral Clock clear in Active state */
sahilmgandhi	18:6a4db94011d3	624	__IO uint32_t APBCLKCFG1SET; /* Offset: 0x0A8 (R/W) APB Peripheral Clock set in Sleep state */
sahilmgandhi	18:6a4db94011d3	625	__IO uint32_t APBCLKCFG1CLR; /* Offset: 0x0AC (R/W) APB Peripheral Clock clear in Sleep state */
sahilmgandhi	18:6a4db94011d3	626	__IO uint32_t APBCLKCFG2SET; /* Offset: 0x0B0 (R/W) APB Peripheral Clock set in Deep Sleep state */
sahilmgandhi	18:6a4db94011d3	627	__IO uint32_t APBCLKCFG2CLR; /* Offset: 0x0B4 (R/W) APB Peripheral Clock clear in Deep Sleep state */
sahilmgandhi	18:6a4db94011d3	628	uint32_t RESERVED5[2];
sahilmgandhi	18:6a4db94011d3	629	__IO uint32_t AHBPRST0SET; /* Offset: 0x0C0 (R/W) AHB Peripheral reset select set */
sahilmgandhi	18:6a4db94011d3	630	__IO uint32_t AHBPRST0CLR; /* Offset: 0x0C4 (R/W) AHB Peripheral reset select clear */
sahilmgandhi	18:6a4db94011d3	631	__IO uint32_t APBPRST0SET; /* Offset: 0x0C8 (R/W) APB Peripheral reset select set */
sahilmgandhi	18:6a4db94011d3	632	__IO uint32_t APBPRST0CLR; /* Offset: 0x0CC (R/W) APB Peripheral reset select clear */
sahilmgandhi	18:6a4db94011d3	633	__IO uint32_t PWRDNCFG0SET; /* Offset: 0x0D0 (R/W) AHB Power down sleep wakeup source set */
sahilmgandhi	18:6a4db94011d3	634	__IO uint32_t PWRDNCFG0CLR; /* Offset: 0x0D4 (R/W) AHB Power down sleep wakeup source clear */
sahilmgandhi	18:6a4db94011d3	635	__IO uint32_t PWRDNCFG1SET; /* Offset: 0x0D8 (R/W) APB Power down sleep wakeup source set */
sahilmgandhi	18:6a4db94011d3	636	__IO uint32_t PWRDNCFG1CLR; /* Offset: 0x0DC (R/W) APB Power down sleep wakeup source clear */
sahilmgandhi	18:6a4db94011d3	637	__O uint32_t RTCRESET; /* Offset: 0x0E0 ( /W) RTC reset */
sahilmgandhi	18:6a4db94011d3	638	__IO uint32_t EVENTCFG; /* Offset: 0x0E4 (R/W) Event interface Control Register */
sahilmgandhi	18:6a4db94011d3	639	uint32_t RESERVED6[2];
sahilmgandhi	18:6a4db94011d3	640	__IO uint32_t PWROVRIDE0; /* Offset: 0x0F0 (R/W) SRAM Power control overide */
sahilmgandhi	18:6a4db94011d3	641	__IO uint32_t PWROVRIDE1; /* Offset: 0x0F4 (R/W) Embedded Flash Power control overide */
sahilmgandhi	18:6a4db94011d3	642	__I uint32_t MEMORYSTATUS; /* Offset: 0x0F8 (R/ ) Memory Status Register */
sahilmgandhi	18:6a4db94011d3	643	uint32_t RESERVED7[1];
sahilmgandhi	18:6a4db94011d3	644	__IO uint32_t GPIOPADCFG0; /* Offset: 0x100 (R/W) IO pad settings */
sahilmgandhi	18:6a4db94011d3	645	__IO uint32_t GPIOPADCFG1; /* Offset: 0x104 (R/W) IO pad settings */
sahilmgandhi	18:6a4db94011d3	646	__IO uint32_t TESTMODECFG; /* Offset: 0x108 (R/W) Testmode boot bypass */
sahilmgandhi	18:6a4db94011d3	647	} CMSDK_SYSCON_TypeDef;
sahilmgandhi	18:6a4db94011d3	648
sahilmgandhi	18:6a4db94011d3	649	#define CMSDK_SYSCON_REMAP_Pos 0
sahilmgandhi	18:6a4db94011d3	650	#define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */
sahilmgandhi	18:6a4db94011d3	651
sahilmgandhi	18:6a4db94011d3	652	#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
sahilmgandhi	18:6a4db94011d3	653	#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
sahilmgandhi	18:6a4db94011d3	654
sahilmgandhi	18:6a4db94011d3	655	#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
sahilmgandhi	18:6a4db94011d3	656	#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
sahilmgandhi	18:6a4db94011d3	657
sahilmgandhi	18:6a4db94011d3	658	#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
sahilmgandhi	18:6a4db94011d3	659	#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */
sahilmgandhi	18:6a4db94011d3	660
sahilmgandhi	18:6a4db94011d3	661	#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
sahilmgandhi	18:6a4db94011d3	662	#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
sahilmgandhi	18:6a4db94011d3	663
sahilmgandhi	18:6a4db94011d3	664	#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
sahilmgandhi	18:6a4db94011d3	665	#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
sahilmgandhi	18:6a4db94011d3	666
sahilmgandhi	18:6a4db94011d3	667	#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
sahilmgandhi	18:6a4db94011d3	668	#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */
sahilmgandhi	18:6a4db94011d3	669
sahilmgandhi	18:6a4db94011d3	670	#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
sahilmgandhi	18:6a4db94011d3	671	#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
sahilmgandhi	18:6a4db94011d3	672
sahilmgandhi	18:6a4db94011d3	673	#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
sahilmgandhi	18:6a4db94011d3	674	#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
sahilmgandhi	18:6a4db94011d3	675
sahilmgandhi	18:6a4db94011d3	676	#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
sahilmgandhi	18:6a4db94011d3	677	#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
sahilmgandhi	18:6a4db94011d3	678
sahilmgandhi	18:6a4db94011d3	679
sahilmgandhi	18:6a4db94011d3	680	/------------- PL230 uDMA (PL230) --------------------------------------/
sahilmgandhi	18:6a4db94011d3	681	typedef struct
sahilmgandhi	18:6a4db94011d3	682	{
sahilmgandhi	18:6a4db94011d3	683	__I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
sahilmgandhi	18:6a4db94011d3	684	__O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
sahilmgandhi	18:6a4db94011d3	685	__IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
sahilmgandhi	18:6a4db94011d3	686	__I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
sahilmgandhi	18:6a4db94011d3	687	__I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
sahilmgandhi	18:6a4db94011d3	688	__O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
sahilmgandhi	18:6a4db94011d3	689	__IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
sahilmgandhi	18:6a4db94011d3	690	__O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
sahilmgandhi	18:6a4db94011d3	691	__IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
sahilmgandhi	18:6a4db94011d3	692	__O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
sahilmgandhi	18:6a4db94011d3	693	__IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
sahilmgandhi	18:6a4db94011d3	694	__O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
sahilmgandhi	18:6a4db94011d3	695	__IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
sahilmgandhi	18:6a4db94011d3	696	__O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
sahilmgandhi	18:6a4db94011d3	697	__IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
sahilmgandhi	18:6a4db94011d3	698	__O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
sahilmgandhi	18:6a4db94011d3	699	uint32_t RESERVED0[3];
sahilmgandhi	18:6a4db94011d3	700	__IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
sahilmgandhi	18:6a4db94011d3	701
sahilmgandhi	18:6a4db94011d3	702	} CMSDK_PL230_TypeDef;
sahilmgandhi	18:6a4db94011d3	703
sahilmgandhi	18:6a4db94011d3	704	#define PL230_DMA_CHNL_BITS 0
sahilmgandhi	18:6a4db94011d3	705
sahilmgandhi	18:6a4db94011d3	706	#define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */
sahilmgandhi	18:6a4db94011d3	707	#define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */
sahilmgandhi	18:6a4db94011d3	708
sahilmgandhi	18:6a4db94011d3	709	#define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */
sahilmgandhi	18:6a4db94011d3	710	#define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */
sahilmgandhi	18:6a4db94011d3	711
sahilmgandhi	18:6a4db94011d3	712	#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */
sahilmgandhi	18:6a4db94011d3	713	#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */
sahilmgandhi	18:6a4db94011d3	714
sahilmgandhi	18:6a4db94011d3	715	#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */
sahilmgandhi	18:6a4db94011d3	716	#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */
sahilmgandhi	18:6a4db94011d3	717
sahilmgandhi	18:6a4db94011d3	718	#define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */
sahilmgandhi	18:6a4db94011d3	719	#define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */
sahilmgandhi	18:6a4db94011d3	720
sahilmgandhi	18:6a4db94011d3	721	#define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */
sahilmgandhi	18:6a4db94011d3	722	#define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */
sahilmgandhi	18:6a4db94011d3	723
sahilmgandhi	18:6a4db94011d3	724	#define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */
sahilmgandhi	18:6a4db94011d3	725	#define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */
sahilmgandhi	18:6a4db94011d3	726
sahilmgandhi	18:6a4db94011d3	727	#define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */
sahilmgandhi	18:6a4db94011d3	728	#define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */
sahilmgandhi	18:6a4db94011d3	729
sahilmgandhi	18:6a4db94011d3	730	#define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */
sahilmgandhi	18:6a4db94011d3	731	#define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */
sahilmgandhi	18:6a4db94011d3	732
sahilmgandhi	18:6a4db94011d3	733	#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */
sahilmgandhi	18:6a4db94011d3	734	#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */
sahilmgandhi	18:6a4db94011d3	735
sahilmgandhi	18:6a4db94011d3	736	#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */
sahilmgandhi	18:6a4db94011d3	737	#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */
sahilmgandhi	18:6a4db94011d3	738
sahilmgandhi	18:6a4db94011d3	739	#define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */
sahilmgandhi	18:6a4db94011d3	740	#define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */
sahilmgandhi	18:6a4db94011d3	741
sahilmgandhi	18:6a4db94011d3	742	#define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */
sahilmgandhi	18:6a4db94011d3	743	#define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */
sahilmgandhi	18:6a4db94011d3	744
sahilmgandhi	18:6a4db94011d3	745	#define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */
sahilmgandhi	18:6a4db94011d3	746	#define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */
sahilmgandhi	18:6a4db94011d3	747
sahilmgandhi	18:6a4db94011d3	748	#define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */
sahilmgandhi	18:6a4db94011d3	749	#define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */
sahilmgandhi	18:6a4db94011d3	750
sahilmgandhi	18:6a4db94011d3	751	#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */
sahilmgandhi	18:6a4db94011d3	752	#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */
sahilmgandhi	18:6a4db94011d3	753
sahilmgandhi	18:6a4db94011d3	754	#define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */
sahilmgandhi	18:6a4db94011d3	755	#define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */
sahilmgandhi	18:6a4db94011d3	756
sahilmgandhi	18:6a4db94011d3	757	#define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */
sahilmgandhi	18:6a4db94011d3	758	#define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */
sahilmgandhi	18:6a4db94011d3	759
sahilmgandhi	18:6a4db94011d3	760	#define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */
sahilmgandhi	18:6a4db94011d3	761	#define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */
sahilmgandhi	18:6a4db94011d3	762
sahilmgandhi	18:6a4db94011d3	763	#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */
sahilmgandhi	18:6a4db94011d3	764	#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */
sahilmgandhi	18:6a4db94011d3	765
sahilmgandhi	18:6a4db94011d3	766	#define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */
sahilmgandhi	18:6a4db94011d3	767	#define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */
sahilmgandhi	18:6a4db94011d3	768
sahilmgandhi	18:6a4db94011d3	769	#define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */
sahilmgandhi	18:6a4db94011d3	770	#define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */
sahilmgandhi	18:6a4db94011d3	771
sahilmgandhi	18:6a4db94011d3	772	#define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */
sahilmgandhi	18:6a4db94011d3	773	#define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */
sahilmgandhi	18:6a4db94011d3	774
sahilmgandhi	18:6a4db94011d3	775
sahilmgandhi	18:6a4db94011d3	776	/------------------- Watchdog ----------------------------------------------/
sahilmgandhi	18:6a4db94011d3	777	typedef struct
sahilmgandhi	18:6a4db94011d3	778	{
sahilmgandhi	18:6a4db94011d3	779
sahilmgandhi	18:6a4db94011d3	780	__IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
sahilmgandhi	18:6a4db94011d3	781	__I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
sahilmgandhi	18:6a4db94011d3	782	__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
sahilmgandhi	18:6a4db94011d3	783	__O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
sahilmgandhi	18:6a4db94011d3	784	__I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
sahilmgandhi	18:6a4db94011d3	785	__I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
sahilmgandhi	18:6a4db94011d3	786	uint32_t RESERVED0[762];
sahilmgandhi	18:6a4db94011d3	787	__IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
sahilmgandhi	18:6a4db94011d3	788	uint32_t RESERVED1[191];
sahilmgandhi	18:6a4db94011d3	789	__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
sahilmgandhi	18:6a4db94011d3	790	__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
sahilmgandhi	18:6a4db94011d3	791	}CMSDK_WATCHDOG_TypeDef;
sahilmgandhi	18:6a4db94011d3	792
sahilmgandhi	18:6a4db94011d3	793	#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
sahilmgandhi	18:6a4db94011d3	794	#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
sahilmgandhi	18:6a4db94011d3	795
sahilmgandhi	18:6a4db94011d3	796	#define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */
sahilmgandhi	18:6a4db94011d3	797	#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */
sahilmgandhi	18:6a4db94011d3	798
sahilmgandhi	18:6a4db94011d3	799	#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
sahilmgandhi	18:6a4db94011d3	800	#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
sahilmgandhi	18:6a4db94011d3	801
sahilmgandhi	18:6a4db94011d3	802	#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
sahilmgandhi	18:6a4db94011d3	803	#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
sahilmgandhi	18:6a4db94011d3	804
sahilmgandhi	18:6a4db94011d3	805	#define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */
sahilmgandhi	18:6a4db94011d3	806	#define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */
sahilmgandhi	18:6a4db94011d3	807
sahilmgandhi	18:6a4db94011d3	808	#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
sahilmgandhi	18:6a4db94011d3	809	#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
sahilmgandhi	18:6a4db94011d3	810
sahilmgandhi	18:6a4db94011d3	811	#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
sahilmgandhi	18:6a4db94011d3	812	#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
sahilmgandhi	18:6a4db94011d3	813
sahilmgandhi	18:6a4db94011d3	814	#define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */
sahilmgandhi	18:6a4db94011d3	815	#define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */
sahilmgandhi	18:6a4db94011d3	816
sahilmgandhi	18:6a4db94011d3	817	#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
sahilmgandhi	18:6a4db94011d3	818	#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
sahilmgandhi	18:6a4db94011d3	819
sahilmgandhi	18:6a4db94011d3	820	#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
sahilmgandhi	18:6a4db94011d3	821	#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
sahilmgandhi	18:6a4db94011d3	822
sahilmgandhi	18:6a4db94011d3	823
sahilmgandhi	18:6a4db94011d3	824
sahilmgandhi	18:6a4db94011d3	825	/* -------------------- End of section using anonymous unions ------------------- */
sahilmgandhi	18:6a4db94011d3	826	#if defined ( __CC_ARM )
sahilmgandhi	18:6a4db94011d3	827	#pragma pop
sahilmgandhi	18:6a4db94011d3	828	#elif defined(__ICCARM__)
sahilmgandhi	18:6a4db94011d3	829	/* leave anonymous unions enabled */
sahilmgandhi	18:6a4db94011d3	830	#elif defined(__GNUC__)
sahilmgandhi	18:6a4db94011d3	831	/* anonymous unions are enabled by default */
sahilmgandhi	18:6a4db94011d3	832	#elif defined(__TMS470__)
sahilmgandhi	18:6a4db94011d3	833	/* anonymous unions are enabled by default */
sahilmgandhi	18:6a4db94011d3	834	#elif defined(__TASKING__)
sahilmgandhi	18:6a4db94011d3	835	#pragma warning restore
sahilmgandhi	18:6a4db94011d3	836	#else
sahilmgandhi	18:6a4db94011d3	837	#warning Not supported compiler type
sahilmgandhi	18:6a4db94011d3	838	#endif
sahilmgandhi	18:6a4db94011d3	839
sahilmgandhi	18:6a4db94011d3	840
sahilmgandhi	18:6a4db94011d3	841
sahilmgandhi	18:6a4db94011d3	842
sahilmgandhi	18:6a4db94011d3	843	/* ================================================================================ */
sahilmgandhi	18:6a4db94011d3	844	/* ================ Peripheral memory map ================ */
sahilmgandhi	18:6a4db94011d3	845	/* ================================================================================ */
sahilmgandhi	18:6a4db94011d3	846
sahilmgandhi	18:6a4db94011d3	847	/* Peripheral and SRAM base address */
sahilmgandhi	18:6a4db94011d3	848	#define CMSDK_FLASH_BASE (0x00000000UL)
sahilmgandhi	18:6a4db94011d3	849	#define CMSDK_SRAM_BASE (0x20000000UL)
sahilmgandhi	18:6a4db94011d3	850	#define CMSDK_PERIPH_BASE (0x40000000UL)
sahilmgandhi	18:6a4db94011d3	851
sahilmgandhi	18:6a4db94011d3	852	#define CMSDK_RAM_BASE (0x20000000UL)
sahilmgandhi	18:6a4db94011d3	853	#define CMSDK_APB_BASE (0x40000000UL)
sahilmgandhi	18:6a4db94011d3	854	#define CMSDK_AHB_BASE (0x40010000UL)
sahilmgandhi	18:6a4db94011d3	855
sahilmgandhi	18:6a4db94011d3	856	#define LLCC_CONT_BASE (0xA0000000UL)
sahilmgandhi	18:6a4db94011d3	857	#define LLCC_CTRL_BASE (LLCC_CONT_BASE)
sahilmgandhi	18:6a4db94011d3	858	#define LLCC_RXD_BASE (LLCC_CONT_BASE+0x2000)
sahilmgandhi	18:6a4db94011d3	859	#define LLCC_TXD_BASE (LLCC_CONT_BASE+0x3000)
sahilmgandhi	18:6a4db94011d3	860
sahilmgandhi	18:6a4db94011d3	861	#define DMAC_CONT_BASE (0xA0001000UL)
sahilmgandhi	18:6a4db94011d3	862	#define DMAC_DMARH_BASE (DMAC_CONT_BASE+0x00)
sahilmgandhi	18:6a4db94011d3	863	#define DMAC_DMARL_BASE (DMAC_CONT_BASE+0x40)
sahilmgandhi	18:6a4db94011d3	864	#define DMAC_DMAWH_BASE (DMAC_CONT_BASE+0x80)
sahilmgandhi	18:6a4db94011d3	865	#define DMAC_DMAWL_BASE (DMAC_CONT_BASE+0xC0)
sahilmgandhi	18:6a4db94011d3	866	#define DMAC_HCIR_BASE DMAC_DMARL_BASE
sahilmgandhi	18:6a4db94011d3	867	#define DMAC_HCIW_BASE DMAC_DMAWL_BASE
sahilmgandhi	18:6a4db94011d3	868	#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
sahilmgandhi	18:6a4db94011d3	869	#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
sahilmgandhi	18:6a4db94011d3	870	#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
sahilmgandhi	18:6a4db94011d3	871	#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
sahilmgandhi	18:6a4db94011d3	872	#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
sahilmgandhi	18:6a4db94011d3	873	#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
sahilmgandhi	18:6a4db94011d3	874	#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
sahilmgandhi	18:6a4db94011d3	875	#define CMSDK_RTC_BASE (CMSDK_APB_BASE + 0x6000UL)
sahilmgandhi	18:6a4db94011d3	876	#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
sahilmgandhi	18:6a4db94011d3	877
sahilmgandhi	18:6a4db94011d3	878	/* AHB peripherals */
sahilmgandhi	18:6a4db94011d3	879	#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
sahilmgandhi	18:6a4db94011d3	880	#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
sahilmgandhi	18:6a4db94011d3	881	#define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL)
sahilmgandhi	18:6a4db94011d3	882	#define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL)
sahilmgandhi	18:6a4db94011d3	883	#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
sahilmgandhi	18:6a4db94011d3	884
sahilmgandhi	18:6a4db94011d3	885
sahilmgandhi	18:6a4db94011d3	886	/* ================================================================================ */
sahilmgandhi	18:6a4db94011d3	887	/* ================ Peripheral declaration ================ */
sahilmgandhi	18:6a4db94011d3	888	/* ================================================================================ */
sahilmgandhi	18:6a4db94011d3	889
sahilmgandhi	18:6a4db94011d3	890	#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
sahilmgandhi	18:6a4db94011d3	891	#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
sahilmgandhi	18:6a4db94011d3	892	#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
sahilmgandhi	18:6a4db94011d3	893	#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
sahilmgandhi	18:6a4db94011d3	894	#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
sahilmgandhi	18:6a4db94011d3	895	#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
sahilmgandhi	18:6a4db94011d3	896	#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
sahilmgandhi	18:6a4db94011d3	897	#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
sahilmgandhi	18:6a4db94011d3	898	#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE )
sahilmgandhi	18:6a4db94011d3	899	#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
sahilmgandhi	18:6a4db94011d3	900	#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
sahilmgandhi	18:6a4db94011d3	901	#define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE )
sahilmgandhi	18:6a4db94011d3	902	#define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE )
sahilmgandhi	18:6a4db94011d3	903	#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
sahilmgandhi	18:6a4db94011d3	904
sahilmgandhi	18:6a4db94011d3	905	#define LLCC_CTL ((LLCC_CTL_TypeDef *) LLCC_CTRL_BASE)
sahilmgandhi	18:6a4db94011d3	906	#define LLCC_RXD ((LLCC_RXD_TypeDef *) LLCC_RXD_BASE)
sahilmgandhi	18:6a4db94011d3	907	#define LLCC_TXD ((LLCC_TXD_TypeDef *) LLCC_TXD_BASE)
sahilmgandhi	18:6a4db94011d3	908	#define DMAC_DMARH ((DMAC_CHAN_TypeDef *) DMAC_DMARH_BASE)
sahilmgandhi	18:6a4db94011d3	909	#define DMAC_DMARL ((DMAC_CHAN_TypeDef *) DMAC_DMARL_BASE)
sahilmgandhi	18:6a4db94011d3	910	#define DMAC_DMAWH ((DMAC_CHAN_TypeDef *) DMAC_DMAWH_BASE)
sahilmgandhi	18:6a4db94011d3	911	#define DMAC_DMAWL ((DMAC_CHAN_TypeDef *) DMAC_DMAWL_BASE)
sahilmgandhi	18:6a4db94011d3	912	#define DMAC_HCIR DMAC_DMAWL
sahilmgandhi	18:6a4db94011d3	913	#define DMAC_HCIW DMAC_DMARL
sahilmgandhi	18:6a4db94011d3	914
sahilmgandhi	18:6a4db94011d3	915	/*********************************************************************
sahilmgandhi	18:6a4db94011d3	916	* GPIO 2 / 3 BIT FEILD POS, OUTPUTS
sahilmgandhi	18:6a4db94011d3	917	*************************************************************************/
sahilmgandhi	18:6a4db94011d3	918	/* GPIO 2 */
sahilmgandhi	18:6a4db94011d3	919	#define CORDIO_LLCCTRL_RESETX_BIT (1<<0)
sahilmgandhi	18:6a4db94011d3	920	#define CORDIO_LLCCTRL_SYSTEM_RESET_BIT (1<<1)
sahilmgandhi	18:6a4db94011d3	921	#define CORDIO_LLCCTRL_LLC_RESET_BIT (1<<2)
sahilmgandhi	18:6a4db94011d3	922	#define CORDIO_LLCCTRL_WAKE_REQ_BIT (1<<3)
sahilmgandhi	18:6a4db94011d3	923	#define CORDIO_LLCCTRL_SLEEP_REQ_BIT (1<<4)
sahilmgandhi	18:6a4db94011d3	924	#define CORDIO_LLCCTRL_SWITCHING_REGULATOR_REQUEST_BIT (1<<5)
sahilmgandhi	18:6a4db94011d3	925	#define CORDIO_LLCCTRL_BATTERY_STATUS_REQUEST_BIT (1<<6)
sahilmgandhi	18:6a4db94011d3	926	#define CORDIO_LLCCTRL_32M_XTAL_REQUEST_BIT (1<<7)
sahilmgandhi	18:6a4db94011d3	927
sahilmgandhi	18:6a4db94011d3	928	/* GPIO 3 */
sahilmgandhi	18:6a4db94011d3	929	#define CORDIO_LLCCTRL_VMEM_ON_BIT ((1<<10) \| (1 << 11))
sahilmgandhi	18:6a4db94011d3	930
sahilmgandhi	18:6a4db94011d3	931	/*********************************************************************
sahilmgandhi	18:6a4db94011d3	932	* GPIO 2 / 3 BIT FEILD POS, INPUTS
sahilmgandhi	18:6a4db94011d3	933	*************************************************************************/
sahilmgandhi	18:6a4db94011d3	934
sahilmgandhi	18:6a4db94011d3	935	#define CORDIO_LLCCTRL_RESET_SYNDROME_MSK (3<<0)
sahilmgandhi	18:6a4db94011d3	936
sahilmgandhi	18:6a4db94011d3	937	#define CORDIO_LLCCTRL_STATUS_ACTIVE_32KXTAL_BIT (1<<2)
sahilmgandhi	18:6a4db94011d3	938	#define CORDIO_LLCCTRL_STATUS_ACTIVE_32MXTAL_BIT (1<<3)
sahilmgandhi	18:6a4db94011d3	939
sahilmgandhi	18:6a4db94011d3	940	#define CORDIO_LLCCTRL_STATUS_BATTERY_DET3V_BIT (1<<4)
sahilmgandhi	18:6a4db94011d3	941	#define CORDIO_LLCCTRL_STATUS_BATTERY_STATUS_BIT (1<<5)
sahilmgandhi	18:6a4db94011d3	942	#define CORDIO_LLCCTRL_STATUS_V1V_ON_STATUS_BIT (1<<6)
sahilmgandhi	18:6a4db94011d3	943	#define CORDIO_LLCCTRL_STATUS_AWAKE_BIT (1<<7)
sahilmgandhi	18:6a4db94011d3	944
sahilmgandhi	18:6a4db94011d3	945	/**************************************************************/
sahilmgandhi	18:6a4db94011d3	946	// RESET LOW
sahilmgandhi	18:6a4db94011d3	947	#define CORDIO_LLCCTRL_RESETX_ASSERT() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_RESETX_BIT)
sahilmgandhi	18:6a4db94011d3	948	#define CORDIO_LLCCTRL_RESETX_NEGATE() (CMSDK_GPIO2->DATAOUT \|= CORDIO_LLCCTRL_RESETX_BIT)
sahilmgandhi	18:6a4db94011d3	949	// RESET HIGH
sahilmgandhi	18:6a4db94011d3	950	#define CORDIO_LLCCTRL_SYSTEM_RESET_ASSERT() (CMSDK_GPIO2->DATAOUT \|=CORDIO_LLCCTRL_SYSTEM_RESET_BIT)
sahilmgandhi	18:6a4db94011d3	951	#define CORDIO_LLCCTRL_SYSTEM_RESET_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_SYSTEM_RESET_BIT)
sahilmgandhi	18:6a4db94011d3	952
sahilmgandhi	18:6a4db94011d3	953	// RESET HIGH
sahilmgandhi	18:6a4db94011d3	954	#define CORDIO_LLCCTRL_LLC_RESET_ASSERT() (CMSDK_GPIO2->DATAOUT \|=CORDIO_LLCCTRL_LLC_RESET_BIT)
sahilmgandhi	18:6a4db94011d3	955	#define CORDIO_LLCCTRL_LLC_RESET_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_LLC_RESET_BIT)
sahilmgandhi	18:6a4db94011d3	956
sahilmgandhi	18:6a4db94011d3	957	// ACTIVE HIGH
sahilmgandhi	18:6a4db94011d3	958	#define CORDIO_LLCCTRL_WAKE_REQ_ASSERT() (CMSDK_GPIO2->DATAOUT \|=CORDIO_LLCCTRL_WAKE_REQ_BIT)
sahilmgandhi	18:6a4db94011d3	959	#define CORDIO_LLCCTRL_WAKE_REQ_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_WAKE_REQ_BIT)
sahilmgandhi	18:6a4db94011d3	960
sahilmgandhi	18:6a4db94011d3	961	// ACTIVE HIGH
sahilmgandhi	18:6a4db94011d3	962	#define CORDIO_LLCCTRL_SLEEP_REQ_ASSERT() (CMSDK_GPIO2->DATAOUT \|=CORDIO_LLCCTRL_SLEEP_REQ_BIT)
sahilmgandhi	18:6a4db94011d3	963	#define CORDIO_LLCCTRL_SLEEP_REQ_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_SLEEP_REQ_BIT)
sahilmgandhi	18:6a4db94011d3	964
sahilmgandhi	18:6a4db94011d3	965	// ACTIVE HIGH
sahilmgandhi	18:6a4db94011d3	966	#define CORDIO_LLCCTRL_SWITCHING_REGULATOR_REQUEST_ASSERT() (CMSDK_GPIO2->DATAOUT \|=CORDIO_LLCCTRL_SWITCHING_REGULATOR_REQUEST_BIT)
sahilmgandhi	18:6a4db94011d3	967	#define CORDIO_LLCCTRL_SWITCHING_REGULATOR_REQUEST_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_SWITCHING_REGULATOR_REQUEST_BIT)
sahilmgandhi	18:6a4db94011d3	968	// ACTIVE HIGH
sahilmgandhi	18:6a4db94011d3	969	#define CORDIO_LLCCTRL_BATTERY_STATUS_REQUEST_ASSERT() (CMSDK_GPIO2->DATAOUT \|=CORDIO_LLCCTRL_BATTERY_STATUS_REQUEST_BIT)
sahilmgandhi	18:6a4db94011d3	970	#define CORDIO_LLCCTRL_BATTERY_STATUS_REQUEST_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_BATTERY_STATUS_REQUEST_BIT)
sahilmgandhi	18:6a4db94011d3	971
sahilmgandhi	18:6a4db94011d3	972	// ACTIVE HIGH
sahilmgandhi	18:6a4db94011d3	973	#define CORDIO_LLCCTRL_32M_XTAL_REQUEST_ASSERT() (CMSDK_GPIO2->DATAOUT \|=CORDIO_LLCCTRL_32M_XTAL_REQUEST_BIT)
sahilmgandhi	18:6a4db94011d3	974	#define CORDIO_LLCCTRL_32M_XTAL_REQUEST_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_32M_XTAL_REQUEST_BIT)
sahilmgandhi	18:6a4db94011d3	975	// ASSERTS HIGH
sahilmgandhi	18:6a4db94011d3	976	#define CORDIO_LLCCTRL_VMEM_ON_ASSERT() (CMSDK_GPIO3->DATAOUT \|=CORDIO_LLCCTRL_VMEM_ON_BIT)
sahilmgandhi	18:6a4db94011d3	977	#define CORDIO_LLCCTRL_VMEM_ON_NEGATE() (CMSDK_GPIO3->DATAOUT &=~CORDIO_LLCCTRL_VMEM_ON_BIT)
sahilmgandhi	18:6a4db94011d3	978
sahilmgandhi	18:6a4db94011d3	979
sahilmgandhi	18:6a4db94011d3	980	/********** READ STATUS ******************/
sahilmgandhi	18:6a4db94011d3	981
sahilmgandhi	18:6a4db94011d3	982	// ACTIVE HIGH, BIT INDEPANDENT
sahilmgandhi	18:6a4db94011d3	983	#define CORDIO_LLCCTRL_RESET_SYNDROME_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_RESET_SYNDROME_MSK)
sahilmgandhi	18:6a4db94011d3	984	// ACTIVE HIGH
sahilmgandhi	18:6a4db94011d3	985	#define CORDIO_LLCCTRL_STATUS_ACTIVE_32KXTAL_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_STATUS_ACTIVE_32KXTAL_BIT)
sahilmgandhi	18:6a4db94011d3	986	// ACTIVE HIGH
sahilmgandhi	18:6a4db94011d3	987	#define CORDIO_LLCCTRL_STATUS_ACTIVE_32MXTAL_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_STATUS_ACTIVE_32MXTAL_BIT)
sahilmgandhi	18:6a4db94011d3	988	// ACTIVE HIGH
sahilmgandhi	18:6a4db94011d3	989	#define CORDIO_LLCCTRL_STATUS_BATTERY_DET3V_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_STATUS_BATTERY_DET3V_BIT)
sahilmgandhi	18:6a4db94011d3	990	// ACTIVE HIGH
sahilmgandhi	18:6a4db94011d3	991	#define CORDIO_LLCCTRL_STATUS_BATTERY_STATUS_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_STATUS_BATTERY_STATUS_BIT)
sahilmgandhi	18:6a4db94011d3	992	// ACTIVE HIGH
sahilmgandhi	18:6a4db94011d3	993	#define CORDIO_LLCCTRL_STATUS_V1V_ON_STATUS_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_STATUS_V1V_ON_STATUS_BIT)
sahilmgandhi	18:6a4db94011d3	994	// ACTIVE HIGH
sahilmgandhi	18:6a4db94011d3	995	#define CORDIO_LLCCTRL_STATUS_AWAKE_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_STATUS_AWAKE_BIT)
sahilmgandhi	18:6a4db94011d3	996
sahilmgandhi	18:6a4db94011d3	997
sahilmgandhi	18:6a4db94011d3	998	/* ---- DEBUG MASK & VALUE BITs used for diagnosis ---- */
sahilmgandhi	18:6a4db94011d3	999	#define INSTALL_DEBUG__GPIO_TOGGLES
sahilmgandhi	18:6a4db94011d3	1000
sahilmgandhi	18:6a4db94011d3	1001	#ifdef INSTALL_DEBUG__GPIO_TOGGLES
sahilmgandhi	18:6a4db94011d3	1002
sahilmgandhi	18:6a4db94011d3	1003	#define GPIO_TOGGLES_MSK (0xFC)
sahilmgandhi	18:6a4db94011d3	1004
sahilmgandhi	18:6a4db94011d3	1005	#define BIT_0 (1<<0)
sahilmgandhi	18:6a4db94011d3	1006	#define BIT_1 (1<<1)
sahilmgandhi	18:6a4db94011d3	1007	#define BIT_2 (1<<2)
sahilmgandhi	18:6a4db94011d3	1008	#define BIT_3 (1<<3)
sahilmgandhi	18:6a4db94011d3	1009	#define BIT_4 (1<<4)
sahilmgandhi	18:6a4db94011d3	1010	#define BIT_5 (1<<5)
sahilmgandhi	18:6a4db94011d3	1011	#define BIT_6 (1<<6)
sahilmgandhi	18:6a4db94011d3	1012	#define BIT_7 (1<<7)
sahilmgandhi	18:6a4db94011d3	1013
sahilmgandhi	18:6a4db94011d3	1014	#define BIT_SET(B) (CMSDK_GPIO0->DATAOUT \|= ((B) & (GPIO_TOGGLES_MSK)))
sahilmgandhi	18:6a4db94011d3	1015
sahilmgandhi	18:6a4db94011d3	1016	#define BIT_CLR(B) (CMSDK_GPIO0->DATAOUT &= ~((B) & (GPIO_TOGGLES_MSK)))
sahilmgandhi	18:6a4db94011d3	1017
sahilmgandhi	18:6a4db94011d3	1018	/* BIT TOGGLE, XOR */
sahilmgandhi	18:6a4db94011d3	1019	#define BIT_TGL(B) (CMSDK_GPIO0->DATAOUT ^= ((B) & (GPIO_TOGGLES_MSK)))
sahilmgandhi	18:6a4db94011d3	1020
sahilmgandhi	18:6a4db94011d3	1021	#endif
sahilmgandhi	18:6a4db94011d3	1022
sahilmgandhi	18:6a4db94011d3	1023	#ifdef __cplusplus
sahilmgandhi	18:6a4db94011d3	1024	}
sahilmgandhi	18:6a4db94011d3	1025	#endif
sahilmgandhi	18:6a4db94011d3	1026
sahilmgandhi	18:6a4db94011d3	1027	#endif /* CMSDK_BEETLE_H */

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Type:	Program
Created:	25 Apr 2017
Imports:	29
Forks:	0
Commits:	47
Dependents:	0
Dependencies:	2
Followers:	5

The code in this repository is Apache licensed.

mbed-dev/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/CMSDK_BEETLE.h@46:b156ef445742, 2017-06-03 (annotated)

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