MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/hal/spi_api.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1
sahilmgandhi 18:6a4db94011d3 2 /** \addtogroup hal */
sahilmgandhi 18:6a4db94011d3 3 /** @{*/
sahilmgandhi 18:6a4db94011d3 4 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 5 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 6 *
sahilmgandhi 18:6a4db94011d3 7 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 8 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 9 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 12 *
sahilmgandhi 18:6a4db94011d3 13 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 14 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 16 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 17 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 18 */
sahilmgandhi 18:6a4db94011d3 19 #ifndef MBED_SPI_API_H
sahilmgandhi 18:6a4db94011d3 20 #define MBED_SPI_API_H
sahilmgandhi 18:6a4db94011d3 21
sahilmgandhi 18:6a4db94011d3 22 #include "device.h"
sahilmgandhi 18:6a4db94011d3 23 #include "hal/dma_api.h"
sahilmgandhi 18:6a4db94011d3 24 #include "hal/buffer.h"
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 #if DEVICE_SPI
sahilmgandhi 18:6a4db94011d3 27
sahilmgandhi 18:6a4db94011d3 28 #define SPI_EVENT_ERROR (1 << 1)
sahilmgandhi 18:6a4db94011d3 29 #define SPI_EVENT_COMPLETE (1 << 2)
sahilmgandhi 18:6a4db94011d3 30 #define SPI_EVENT_RX_OVERFLOW (1 << 3)
sahilmgandhi 18:6a4db94011d3 31 #define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 #define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // Internal flag to report that an event occurred
sahilmgandhi 18:6a4db94011d3 34
sahilmgandhi 18:6a4db94011d3 35 #define SPI_FILL_WORD (0xFFFF)
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37 #if DEVICE_SPI_ASYNCH
sahilmgandhi 18:6a4db94011d3 38 /** Asynch SPI HAL structure
sahilmgandhi 18:6a4db94011d3 39 */
sahilmgandhi 18:6a4db94011d3 40 typedef struct {
sahilmgandhi 18:6a4db94011d3 41 struct spi_s spi; /**< Target specific SPI structure */
sahilmgandhi 18:6a4db94011d3 42 struct buffer_s tx_buff; /**< Tx buffer */
sahilmgandhi 18:6a4db94011d3 43 struct buffer_s rx_buff; /**< Rx buffer */
sahilmgandhi 18:6a4db94011d3 44 } spi_t;
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 #else
sahilmgandhi 18:6a4db94011d3 47 /** Non-asynch SPI HAL structure
sahilmgandhi 18:6a4db94011d3 48 */
sahilmgandhi 18:6a4db94011d3 49 typedef struct spi_s spi_t;
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 #endif
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 54 extern "C" {
sahilmgandhi 18:6a4db94011d3 55 #endif
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 /**
sahilmgandhi 18:6a4db94011d3 58 * \defgroup hal_GeneralSPI SPI Configuration Functions
sahilmgandhi 18:6a4db94011d3 59 * @{
sahilmgandhi 18:6a4db94011d3 60 */
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62 /** Initialize the SPI peripheral
sahilmgandhi 18:6a4db94011d3 63 *
sahilmgandhi 18:6a4db94011d3 64 * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
sahilmgandhi 18:6a4db94011d3 65 * @param[out] obj The SPI object to initialize
sahilmgandhi 18:6a4db94011d3 66 * @param[in] mosi The pin to use for MOSI
sahilmgandhi 18:6a4db94011d3 67 * @param[in] miso The pin to use for MISO
sahilmgandhi 18:6a4db94011d3 68 * @param[in] sclk The pin to use for SCLK
sahilmgandhi 18:6a4db94011d3 69 * @param[in] ssel The pin to use for SSEL
sahilmgandhi 18:6a4db94011d3 70 */
sahilmgandhi 18:6a4db94011d3 71 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
sahilmgandhi 18:6a4db94011d3 72
sahilmgandhi 18:6a4db94011d3 73 /** Release a SPI object
sahilmgandhi 18:6a4db94011d3 74 *
sahilmgandhi 18:6a4db94011d3 75 * TODO: spi_free is currently unimplemented
sahilmgandhi 18:6a4db94011d3 76 * This will require reference counting at the C++ level to be safe
sahilmgandhi 18:6a4db94011d3 77 *
sahilmgandhi 18:6a4db94011d3 78 * Return the pins owned by the SPI object to their reset state
sahilmgandhi 18:6a4db94011d3 79 * Disable the SPI peripheral
sahilmgandhi 18:6a4db94011d3 80 * Disable the SPI clock
sahilmgandhi 18:6a4db94011d3 81 * @param[in] obj The SPI object to deinitialize
sahilmgandhi 18:6a4db94011d3 82 */
sahilmgandhi 18:6a4db94011d3 83 void spi_free(spi_t *obj);
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 /** Configure the SPI format
sahilmgandhi 18:6a4db94011d3 86 *
sahilmgandhi 18:6a4db94011d3 87 * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode.
sahilmgandhi 18:6a4db94011d3 88 * The default bit order is MSB.
sahilmgandhi 18:6a4db94011d3 89 * @param[in,out] obj The SPI object to configure
sahilmgandhi 18:6a4db94011d3 90 * @param[in] bits The number of bits per frame
sahilmgandhi 18:6a4db94011d3 91 * @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
sahilmgandhi 18:6a4db94011d3 92 * @param[in] slave Zero for master mode or non-zero for slave mode
sahilmgandhi 18:6a4db94011d3 93 */
sahilmgandhi 18:6a4db94011d3 94 void spi_format(spi_t *obj, int bits, int mode, int slave);
sahilmgandhi 18:6a4db94011d3 95
sahilmgandhi 18:6a4db94011d3 96 /** Set the SPI baud rate
sahilmgandhi 18:6a4db94011d3 97 *
sahilmgandhi 18:6a4db94011d3 98 * Actual frequency may differ from the desired frequency due to available dividers and bus clock
sahilmgandhi 18:6a4db94011d3 99 * Configures the SPI peripheral's baud rate
sahilmgandhi 18:6a4db94011d3 100 * @param[in,out] obj The SPI object to configure
sahilmgandhi 18:6a4db94011d3 101 * @param[in] hz The baud rate in Hz
sahilmgandhi 18:6a4db94011d3 102 */
sahilmgandhi 18:6a4db94011d3 103 void spi_frequency(spi_t *obj, int hz);
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105 /**@}*/
sahilmgandhi 18:6a4db94011d3 106 /**
sahilmgandhi 18:6a4db94011d3 107 * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
sahilmgandhi 18:6a4db94011d3 108 * @{
sahilmgandhi 18:6a4db94011d3 109 */
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 /** Write a byte out in master mode and receive a value
sahilmgandhi 18:6a4db94011d3 112 *
sahilmgandhi 18:6a4db94011d3 113 * @param[in] obj The SPI peripheral to use for sending
sahilmgandhi 18:6a4db94011d3 114 * @param[in] value The value to send
sahilmgandhi 18:6a4db94011d3 115 * @return Returns the value received during send
sahilmgandhi 18:6a4db94011d3 116 */
sahilmgandhi 18:6a4db94011d3 117 int spi_master_write(spi_t *obj, int value);
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 /** Check if a value is available to read
sahilmgandhi 18:6a4db94011d3 120 *
sahilmgandhi 18:6a4db94011d3 121 * @param[in] obj The SPI peripheral to check
sahilmgandhi 18:6a4db94011d3 122 * @return non-zero if a value is available
sahilmgandhi 18:6a4db94011d3 123 */
sahilmgandhi 18:6a4db94011d3 124 int spi_slave_receive(spi_t *obj);
sahilmgandhi 18:6a4db94011d3 125
sahilmgandhi 18:6a4db94011d3 126 /** Get a received value out of the SPI receive buffer in slave mode
sahilmgandhi 18:6a4db94011d3 127 *
sahilmgandhi 18:6a4db94011d3 128 * Blocks until a value is available
sahilmgandhi 18:6a4db94011d3 129 * @param[in] obj The SPI peripheral to read
sahilmgandhi 18:6a4db94011d3 130 * @return The value received
sahilmgandhi 18:6a4db94011d3 131 */
sahilmgandhi 18:6a4db94011d3 132 int spi_slave_read(spi_t *obj);
sahilmgandhi 18:6a4db94011d3 133
sahilmgandhi 18:6a4db94011d3 134 /** Write a value to the SPI peripheral in slave mode
sahilmgandhi 18:6a4db94011d3 135 *
sahilmgandhi 18:6a4db94011d3 136 * Blocks until the SPI peripheral can be written to
sahilmgandhi 18:6a4db94011d3 137 * @param[in] obj The SPI peripheral to write
sahilmgandhi 18:6a4db94011d3 138 * @param[in] value The value to write
sahilmgandhi 18:6a4db94011d3 139 */
sahilmgandhi 18:6a4db94011d3 140 void spi_slave_write(spi_t *obj, int value);
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142 /** Checks if the specified SPI peripheral is in use
sahilmgandhi 18:6a4db94011d3 143 *
sahilmgandhi 18:6a4db94011d3 144 * @param[in] obj The SPI peripheral to check
sahilmgandhi 18:6a4db94011d3 145 * @return non-zero if the peripheral is currently transmitting
sahilmgandhi 18:6a4db94011d3 146 */
sahilmgandhi 18:6a4db94011d3 147 int spi_busy(spi_t *obj);
sahilmgandhi 18:6a4db94011d3 148
sahilmgandhi 18:6a4db94011d3 149 /** Get the module number
sahilmgandhi 18:6a4db94011d3 150 *
sahilmgandhi 18:6a4db94011d3 151 * @param[in] obj The SPI peripheral to check
sahilmgandhi 18:6a4db94011d3 152 * @return The module number
sahilmgandhi 18:6a4db94011d3 153 */
sahilmgandhi 18:6a4db94011d3 154 uint8_t spi_get_module(spi_t *obj);
sahilmgandhi 18:6a4db94011d3 155
sahilmgandhi 18:6a4db94011d3 156 /**@}*/
sahilmgandhi 18:6a4db94011d3 157
sahilmgandhi 18:6a4db94011d3 158 #if DEVICE_SPI_ASYNCH
sahilmgandhi 18:6a4db94011d3 159 /**
sahilmgandhi 18:6a4db94011d3 160 * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
sahilmgandhi 18:6a4db94011d3 161 * @{
sahilmgandhi 18:6a4db94011d3 162 */
sahilmgandhi 18:6a4db94011d3 163
sahilmgandhi 18:6a4db94011d3 164 /** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
sahilmgandhi 18:6a4db94011d3 165 *
sahilmgandhi 18:6a4db94011d3 166 * @param[in] obj The SPI object that holds the transfer information
sahilmgandhi 18:6a4db94011d3 167 * @param[in] tx The transmit buffer
sahilmgandhi 18:6a4db94011d3 168 * @param[in] tx_length The number of bytes to transmit
sahilmgandhi 18:6a4db94011d3 169 * @param[in] rx The receive buffer
sahilmgandhi 18:6a4db94011d3 170 * @param[in] rx_length The number of bytes to receive
sahilmgandhi 18:6a4db94011d3 171 * @param[in] bit_width The bit width of buffer words
sahilmgandhi 18:6a4db94011d3 172 * @param[in] event The logical OR of events to be registered
sahilmgandhi 18:6a4db94011d3 173 * @param[in] handler SPI interrupt handler
sahilmgandhi 18:6a4db94011d3 174 * @param[in] hint A suggestion for how to use DMA with this transfer
sahilmgandhi 18:6a4db94011d3 175 */
sahilmgandhi 18:6a4db94011d3 176 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178 /** The asynchronous IRQ handler
sahilmgandhi 18:6a4db94011d3 179 *
sahilmgandhi 18:6a4db94011d3 180 * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
sahilmgandhi 18:6a4db94011d3 181 * conditions, such as buffer overflows or transfer complete.
sahilmgandhi 18:6a4db94011d3 182 * @param[in] obj The SPI object that holds the transfer information
sahilmgandhi 18:6a4db94011d3 183 * @return Event flags if a transfer termination condition was met; otherwise 0.
sahilmgandhi 18:6a4db94011d3 184 */
sahilmgandhi 18:6a4db94011d3 185 uint32_t spi_irq_handler_asynch(spi_t *obj);
sahilmgandhi 18:6a4db94011d3 186
sahilmgandhi 18:6a4db94011d3 187 /** Attempts to determine if the SPI peripheral is already in use
sahilmgandhi 18:6a4db94011d3 188 *
sahilmgandhi 18:6a4db94011d3 189 * If a temporary DMA channel has been allocated, peripheral is in use.
sahilmgandhi 18:6a4db94011d3 190 * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
sahilmgandhi 18:6a4db94011d3 191 * channel were allocated.
sahilmgandhi 18:6a4db94011d3 192 * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
sahilmgandhi 18:6a4db94011d3 193 * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
sahilmgandhi 18:6a4db94011d3 194 * there are any bytes in the FIFOs.
sahilmgandhi 18:6a4db94011d3 195 * @param[in] obj The SPI object to check for activity
sahilmgandhi 18:6a4db94011d3 196 * @return Non-zero if the SPI port is active or zero if it is not.
sahilmgandhi 18:6a4db94011d3 197 */
sahilmgandhi 18:6a4db94011d3 198 uint8_t spi_active(spi_t *obj);
sahilmgandhi 18:6a4db94011d3 199
sahilmgandhi 18:6a4db94011d3 200 /** Abort an SPI transfer
sahilmgandhi 18:6a4db94011d3 201 *
sahilmgandhi 18:6a4db94011d3 202 * @param obj The SPI peripheral to stop
sahilmgandhi 18:6a4db94011d3 203 */
sahilmgandhi 18:6a4db94011d3 204 void spi_abort_asynch(spi_t *obj);
sahilmgandhi 18:6a4db94011d3 205
sahilmgandhi 18:6a4db94011d3 206
sahilmgandhi 18:6a4db94011d3 207 #endif
sahilmgandhi 18:6a4db94011d3 208
sahilmgandhi 18:6a4db94011d3 209 /**@}*/
sahilmgandhi 18:6a4db94011d3 210
sahilmgandhi 18:6a4db94011d3 211 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 212 }
sahilmgandhi 18:6a4db94011d3 213 #endif // __cplusplus
sahilmgandhi 18:6a4db94011d3 214
sahilmgandhi 18:6a4db94011d3 215 #endif // SPI_DEVICE
sahilmgandhi 18:6a4db94011d3 216
sahilmgandhi 18:6a4db94011d3 217 #endif // MBED_SPI_API_H
sahilmgandhi 18:6a4db94011d3 218
sahilmgandhi 18:6a4db94011d3 219 /** @}*/