MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/drivers/SPI.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2015 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #ifndef MBED_SPI_H
sahilmgandhi 18:6a4db94011d3 17 #define MBED_SPI_H
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 #include "platform/platform.h"
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21 #if DEVICE_SPI
sahilmgandhi 18:6a4db94011d3 22
sahilmgandhi 18:6a4db94011d3 23 #include "platform/PlatformMutex.h"
sahilmgandhi 18:6a4db94011d3 24 #include "hal/spi_api.h"
sahilmgandhi 18:6a4db94011d3 25 #include "platform/SingletonPtr.h"
sahilmgandhi 18:6a4db94011d3 26
sahilmgandhi 18:6a4db94011d3 27 #if DEVICE_SPI_ASYNCH
sahilmgandhi 18:6a4db94011d3 28 #include "platform/CThunk.h"
sahilmgandhi 18:6a4db94011d3 29 #include "hal/dma_api.h"
sahilmgandhi 18:6a4db94011d3 30 #include "platform/CircularBuffer.h"
sahilmgandhi 18:6a4db94011d3 31 #include "platform/FunctionPointer.h"
sahilmgandhi 18:6a4db94011d3 32 #include "platform/Transaction.h"
sahilmgandhi 18:6a4db94011d3 33 #endif
sahilmgandhi 18:6a4db94011d3 34
sahilmgandhi 18:6a4db94011d3 35 namespace mbed {
sahilmgandhi 18:6a4db94011d3 36 /** \addtogroup drivers */
sahilmgandhi 18:6a4db94011d3 37 /** @{*/
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 /** A SPI Master, used for communicating with SPI slave devices
sahilmgandhi 18:6a4db94011d3 40 *
sahilmgandhi 18:6a4db94011d3 41 * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
sahilmgandhi 18:6a4db94011d3 42 *
sahilmgandhi 18:6a4db94011d3 43 * Most SPI devices will also require Chip Select and Reset signals. These
sahilmgandhi 18:6a4db94011d3 44 * can be controlled using <DigitalOut> pins
sahilmgandhi 18:6a4db94011d3 45 *
sahilmgandhi 18:6a4db94011d3 46 * @Note Synchronization level: Thread safe
sahilmgandhi 18:6a4db94011d3 47 *
sahilmgandhi 18:6a4db94011d3 48 * Example:
sahilmgandhi 18:6a4db94011d3 49 * @code
sahilmgandhi 18:6a4db94011d3 50 * // Send a byte to a SPI slave, and record the response
sahilmgandhi 18:6a4db94011d3 51 *
sahilmgandhi 18:6a4db94011d3 52 * #include "mbed.h"
sahilmgandhi 18:6a4db94011d3 53 *
sahilmgandhi 18:6a4db94011d3 54 * // hardware ssel (where applicable)
sahilmgandhi 18:6a4db94011d3 55 * //SPI device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
sahilmgandhi 18:6a4db94011d3 56 *
sahilmgandhi 18:6a4db94011d3 57 * // software ssel
sahilmgandhi 18:6a4db94011d3 58 * SPI device(p5, p6, p7); // mosi, miso, sclk
sahilmgandhi 18:6a4db94011d3 59 * DigitalOut cs(p8); // ssel
sahilmgandhi 18:6a4db94011d3 60 *
sahilmgandhi 18:6a4db94011d3 61 * int main() {
sahilmgandhi 18:6a4db94011d3 62 * // hardware ssel (where applicable)
sahilmgandhi 18:6a4db94011d3 63 * //int response = device.write(0xFF);
sahilmgandhi 18:6a4db94011d3 64 *
sahilmgandhi 18:6a4db94011d3 65 * device.lock();
sahilmgandhi 18:6a4db94011d3 66 * // software ssel
sahilmgandhi 18:6a4db94011d3 67 * cs = 0;
sahilmgandhi 18:6a4db94011d3 68 * int response = device.write(0xFF);
sahilmgandhi 18:6a4db94011d3 69 * cs = 1;
sahilmgandhi 18:6a4db94011d3 70 * device.unlock();
sahilmgandhi 18:6a4db94011d3 71 *
sahilmgandhi 18:6a4db94011d3 72 * }
sahilmgandhi 18:6a4db94011d3 73 * @endcode
sahilmgandhi 18:6a4db94011d3 74 */
sahilmgandhi 18:6a4db94011d3 75 class SPI {
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 public:
sahilmgandhi 18:6a4db94011d3 78
sahilmgandhi 18:6a4db94011d3 79 /** Create a SPI master connected to the specified pins
sahilmgandhi 18:6a4db94011d3 80 *
sahilmgandhi 18:6a4db94011d3 81 * mosi or miso can be specfied as NC if not used
sahilmgandhi 18:6a4db94011d3 82 *
sahilmgandhi 18:6a4db94011d3 83 * @param mosi SPI Master Out, Slave In pin
sahilmgandhi 18:6a4db94011d3 84 * @param miso SPI Master In, Slave Out pin
sahilmgandhi 18:6a4db94011d3 85 * @param sclk SPI Clock pin
sahilmgandhi 18:6a4db94011d3 86 * @param ssel SPI chip select pin
sahilmgandhi 18:6a4db94011d3 87 */
sahilmgandhi 18:6a4db94011d3 88 SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel=NC);
sahilmgandhi 18:6a4db94011d3 89
sahilmgandhi 18:6a4db94011d3 90 /** Configure the data transmission format
sahilmgandhi 18:6a4db94011d3 91 *
sahilmgandhi 18:6a4db94011d3 92 * @param bits Number of bits per SPI frame (4 - 16)
sahilmgandhi 18:6a4db94011d3 93 * @param mode Clock polarity and phase mode (0 - 3)
sahilmgandhi 18:6a4db94011d3 94 *
sahilmgandhi 18:6a4db94011d3 95 * @code
sahilmgandhi 18:6a4db94011d3 96 * mode | POL PHA
sahilmgandhi 18:6a4db94011d3 97 * -----+--------
sahilmgandhi 18:6a4db94011d3 98 * 0 | 0 0
sahilmgandhi 18:6a4db94011d3 99 * 1 | 0 1
sahilmgandhi 18:6a4db94011d3 100 * 2 | 1 0
sahilmgandhi 18:6a4db94011d3 101 * 3 | 1 1
sahilmgandhi 18:6a4db94011d3 102 * @endcode
sahilmgandhi 18:6a4db94011d3 103 */
sahilmgandhi 18:6a4db94011d3 104 void format(int bits, int mode = 0);
sahilmgandhi 18:6a4db94011d3 105
sahilmgandhi 18:6a4db94011d3 106 /** Set the spi bus clock frequency
sahilmgandhi 18:6a4db94011d3 107 *
sahilmgandhi 18:6a4db94011d3 108 * @param hz SCLK frequency in hz (default = 1MHz)
sahilmgandhi 18:6a4db94011d3 109 */
sahilmgandhi 18:6a4db94011d3 110 void frequency(int hz = 1000000);
sahilmgandhi 18:6a4db94011d3 111
sahilmgandhi 18:6a4db94011d3 112 /** Write to the SPI Slave and return the response
sahilmgandhi 18:6a4db94011d3 113 *
sahilmgandhi 18:6a4db94011d3 114 * @param value Data to be sent to the SPI slave
sahilmgandhi 18:6a4db94011d3 115 *
sahilmgandhi 18:6a4db94011d3 116 * @returns
sahilmgandhi 18:6a4db94011d3 117 * Response from the SPI slave
sahilmgandhi 18:6a4db94011d3 118 */
sahilmgandhi 18:6a4db94011d3 119 virtual int write(int value);
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 /** Acquire exclusive access to this SPI bus
sahilmgandhi 18:6a4db94011d3 122 */
sahilmgandhi 18:6a4db94011d3 123 virtual void lock(void);
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125 /** Release exclusive access to this SPI bus
sahilmgandhi 18:6a4db94011d3 126 */
sahilmgandhi 18:6a4db94011d3 127 virtual void unlock(void);
sahilmgandhi 18:6a4db94011d3 128
sahilmgandhi 18:6a4db94011d3 129 #if DEVICE_SPI_ASYNCH
sahilmgandhi 18:6a4db94011d3 130
sahilmgandhi 18:6a4db94011d3 131 /** Start non-blocking SPI transfer using 8bit buffers.
sahilmgandhi 18:6a4db94011d3 132 *
sahilmgandhi 18:6a4db94011d3 133 * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
sahilmgandhi 18:6a4db94011d3 134 * the default SPI value is sent
sahilmgandhi 18:6a4db94011d3 135 * @param tx_length The length of TX buffer in bytes
sahilmgandhi 18:6a4db94011d3 136 * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
sahilmgandhi 18:6a4db94011d3 137 * received data are ignored
sahilmgandhi 18:6a4db94011d3 138 * @param rx_length The length of RX buffer in bytes
sahilmgandhi 18:6a4db94011d3 139 * @param callback The event callback function
sahilmgandhi 18:6a4db94011d3 140 * @param event The logical OR of events to modify. Look at spi hal header file for SPI events.
sahilmgandhi 18:6a4db94011d3 141 * @return Zero if the transfer has started, or -1 if SPI peripheral is busy
sahilmgandhi 18:6a4db94011d3 142 */
sahilmgandhi 18:6a4db94011d3 143 template<typename Type>
sahilmgandhi 18:6a4db94011d3 144 int transfer(const Type *tx_buffer, int tx_length, Type *rx_buffer, int rx_length, const event_callback_t& callback, int event = SPI_EVENT_COMPLETE) {
sahilmgandhi 18:6a4db94011d3 145 if (spi_active(&_spi)) {
sahilmgandhi 18:6a4db94011d3 146 return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event);
sahilmgandhi 18:6a4db94011d3 147 }
sahilmgandhi 18:6a4db94011d3 148 start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event);
sahilmgandhi 18:6a4db94011d3 149 return 0;
sahilmgandhi 18:6a4db94011d3 150 }
sahilmgandhi 18:6a4db94011d3 151
sahilmgandhi 18:6a4db94011d3 152 /** Abort the on-going SPI transfer, and continue with transfer's in the queue if any.
sahilmgandhi 18:6a4db94011d3 153 */
sahilmgandhi 18:6a4db94011d3 154 void abort_transfer();
sahilmgandhi 18:6a4db94011d3 155
sahilmgandhi 18:6a4db94011d3 156 /** Clear the transaction buffer
sahilmgandhi 18:6a4db94011d3 157 */
sahilmgandhi 18:6a4db94011d3 158 void clear_transfer_buffer();
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 /** Clear the transaction buffer and abort on-going transfer.
sahilmgandhi 18:6a4db94011d3 161 */
sahilmgandhi 18:6a4db94011d3 162 void abort_all_transfers();
sahilmgandhi 18:6a4db94011d3 163
sahilmgandhi 18:6a4db94011d3 164 /** Configure DMA usage suggestion for non-blocking transfers
sahilmgandhi 18:6a4db94011d3 165 *
sahilmgandhi 18:6a4db94011d3 166 * @param usage The usage DMA hint for peripheral
sahilmgandhi 18:6a4db94011d3 167 * @return Zero if the usage was set, -1 if a transaction is on-going
sahilmgandhi 18:6a4db94011d3 168 */
sahilmgandhi 18:6a4db94011d3 169 int set_dma_usage(DMAUsage usage);
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 protected:
sahilmgandhi 18:6a4db94011d3 172 /** SPI IRQ handler
sahilmgandhi 18:6a4db94011d3 173 *
sahilmgandhi 18:6a4db94011d3 174 */
sahilmgandhi 18:6a4db94011d3 175 void irq_handler_asynch(void);
sahilmgandhi 18:6a4db94011d3 176
sahilmgandhi 18:6a4db94011d3 177 /** Common transfer method
sahilmgandhi 18:6a4db94011d3 178 *
sahilmgandhi 18:6a4db94011d3 179 * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
sahilmgandhi 18:6a4db94011d3 180 * the default SPI value is sent
sahilmgandhi 18:6a4db94011d3 181 * @param tx_length The length of TX buffer in bytes
sahilmgandhi 18:6a4db94011d3 182 * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
sahilmgandhi 18:6a4db94011d3 183 * received data are ignored
sahilmgandhi 18:6a4db94011d3 184 * @param rx_length The length of RX buffer in bytes
sahilmgandhi 18:6a4db94011d3 185 * @param bit_width The buffers element width
sahilmgandhi 18:6a4db94011d3 186 * @param callback The event callback function
sahilmgandhi 18:6a4db94011d3 187 * @param event The logical OR of events to modify
sahilmgandhi 18:6a4db94011d3 188 * @return Zero if the transfer has started or was added to the queue, or -1 if SPI peripheral is busy/buffer is full
sahilmgandhi 18:6a4db94011d3 189 */
sahilmgandhi 18:6a4db94011d3 190 int transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
sahilmgandhi 18:6a4db94011d3 191
sahilmgandhi 18:6a4db94011d3 192 /**
sahilmgandhi 18:6a4db94011d3 193 *
sahilmgandhi 18:6a4db94011d3 194 * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
sahilmgandhi 18:6a4db94011d3 195 * the default SPI value is sent
sahilmgandhi 18:6a4db94011d3 196 * @param tx_length The length of TX buffer in bytes
sahilmgandhi 18:6a4db94011d3 197 * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
sahilmgandhi 18:6a4db94011d3 198 * received data are ignored
sahilmgandhi 18:6a4db94011d3 199 * @param rx_length The length of RX buffer in bytes
sahilmgandhi 18:6a4db94011d3 200 * @param bit_width The buffers element width
sahilmgandhi 18:6a4db94011d3 201 * @param callback The event callback function
sahilmgandhi 18:6a4db94011d3 202 * @param event The logical OR of events to modify
sahilmgandhi 18:6a4db94011d3 203 * @return Zero if a transfer was added to the queue, or -1 if the queue is full
sahilmgandhi 18:6a4db94011d3 204 */
sahilmgandhi 18:6a4db94011d3 205 int queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
sahilmgandhi 18:6a4db94011d3 206
sahilmgandhi 18:6a4db94011d3 207 /** Configures a callback, spi peripheral and initiate a new transfer
sahilmgandhi 18:6a4db94011d3 208 *
sahilmgandhi 18:6a4db94011d3 209 * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
sahilmgandhi 18:6a4db94011d3 210 * the default SPI value is sent
sahilmgandhi 18:6a4db94011d3 211 * @param tx_length The length of TX buffer in bytes
sahilmgandhi 18:6a4db94011d3 212 * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
sahilmgandhi 18:6a4db94011d3 213 * received data are ignored
sahilmgandhi 18:6a4db94011d3 214 * @param rx_length The length of RX buffer in bytes
sahilmgandhi 18:6a4db94011d3 215 * @param bit_width The buffers element width
sahilmgandhi 18:6a4db94011d3 216 * @param callback The event callback function
sahilmgandhi 18:6a4db94011d3 217 * @param event The logical OR of events to modify
sahilmgandhi 18:6a4db94011d3 218 */
sahilmgandhi 18:6a4db94011d3 219 void start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
sahilmgandhi 18:6a4db94011d3 220
sahilmgandhi 18:6a4db94011d3 221 #if TRANSACTION_QUEUE_SIZE_SPI
sahilmgandhi 18:6a4db94011d3 222
sahilmgandhi 18:6a4db94011d3 223 /** Start a new transaction
sahilmgandhi 18:6a4db94011d3 224 *
sahilmgandhi 18:6a4db94011d3 225 * @param data Transaction data
sahilmgandhi 18:6a4db94011d3 226 */
sahilmgandhi 18:6a4db94011d3 227 void start_transaction(transaction_t *data);
sahilmgandhi 18:6a4db94011d3 228
sahilmgandhi 18:6a4db94011d3 229 /** Dequeue a transaction
sahilmgandhi 18:6a4db94011d3 230 *
sahilmgandhi 18:6a4db94011d3 231 */
sahilmgandhi 18:6a4db94011d3 232 void dequeue_transaction();
sahilmgandhi 18:6a4db94011d3 233 static CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> _transaction_buffer;
sahilmgandhi 18:6a4db94011d3 234 #endif
sahilmgandhi 18:6a4db94011d3 235
sahilmgandhi 18:6a4db94011d3 236 #endif
sahilmgandhi 18:6a4db94011d3 237
sahilmgandhi 18:6a4db94011d3 238 public:
sahilmgandhi 18:6a4db94011d3 239 virtual ~SPI() {
sahilmgandhi 18:6a4db94011d3 240 }
sahilmgandhi 18:6a4db94011d3 241
sahilmgandhi 18:6a4db94011d3 242 protected:
sahilmgandhi 18:6a4db94011d3 243 spi_t _spi;
sahilmgandhi 18:6a4db94011d3 244
sahilmgandhi 18:6a4db94011d3 245 #if DEVICE_SPI_ASYNCH
sahilmgandhi 18:6a4db94011d3 246 CThunk<SPI> _irq;
sahilmgandhi 18:6a4db94011d3 247 event_callback_t _callback;
sahilmgandhi 18:6a4db94011d3 248 DMAUsage _usage;
sahilmgandhi 18:6a4db94011d3 249 #endif
sahilmgandhi 18:6a4db94011d3 250
sahilmgandhi 18:6a4db94011d3 251 void aquire(void);
sahilmgandhi 18:6a4db94011d3 252 static SPI *_owner;
sahilmgandhi 18:6a4db94011d3 253 static SingletonPtr<PlatformMutex> _mutex;
sahilmgandhi 18:6a4db94011d3 254 int _bits;
sahilmgandhi 18:6a4db94011d3 255 int _mode;
sahilmgandhi 18:6a4db94011d3 256 int _hz;
sahilmgandhi 18:6a4db94011d3 257 };
sahilmgandhi 18:6a4db94011d3 258
sahilmgandhi 18:6a4db94011d3 259 } // namespace mbed
sahilmgandhi 18:6a4db94011d3 260
sahilmgandhi 18:6a4db94011d3 261 #endif
sahilmgandhi 18:6a4db94011d3 262
sahilmgandhi 18:6a4db94011d3 263 #endif
sahilmgandhi 18:6a4db94011d3 264
sahilmgandhi 18:6a4db94011d3 265 /** @}*/