MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/cmsis/core_cmInstr.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file core_cmInstr.h
sahilmgandhi 18:6a4db94011d3 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
sahilmgandhi 18:6a4db94011d3 4 * @version V4.10
sahilmgandhi 18:6a4db94011d3 5 * @date 18. March 2015
sahilmgandhi 18:6a4db94011d3 6 *
sahilmgandhi 18:6a4db94011d3 7 * @note
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
sahilmgandhi 18:6a4db94011d3 11
sahilmgandhi 18:6a4db94011d3 12 All rights reserved.
sahilmgandhi 18:6a4db94011d3 13 Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 14 modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 15 - Redistributions of source code must retain the above copyright
sahilmgandhi 18:6a4db94011d3 16 notice, this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 - Redistributions in binary form must reproduce the above copyright
sahilmgandhi 18:6a4db94011d3 18 notice, this list of conditions and the following disclaimer in the
sahilmgandhi 18:6a4db94011d3 19 documentation and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 20 - Neither the name of ARM nor the names of its contributors may be used
sahilmgandhi 18:6a4db94011d3 21 to endorse or promote products derived from this software without
sahilmgandhi 18:6a4db94011d3 22 specific prior written permission.
sahilmgandhi 18:6a4db94011d3 23 *
sahilmgandhi 18:6a4db94011d3 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
sahilmgandhi 18:6a4db94011d3 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
sahilmgandhi 18:6a4db94011d3 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
sahilmgandhi 18:6a4db94011d3 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
sahilmgandhi 18:6a4db94011d3 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
sahilmgandhi 18:6a4db94011d3 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
sahilmgandhi 18:6a4db94011d3 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
sahilmgandhi 18:6a4db94011d3 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sahilmgandhi 18:6a4db94011d3 34 POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 35 ---------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 #ifndef __CORE_CMINSTR_H
sahilmgandhi 18:6a4db94011d3 39 #define __CORE_CMINSTR_H
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 /* ########################## Core Instruction Access ######################### */
sahilmgandhi 18:6a4db94011d3 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
sahilmgandhi 18:6a4db94011d3 44 Access to dedicated instructions
sahilmgandhi 18:6a4db94011d3 45 @{
sahilmgandhi 18:6a4db94011d3 46 */
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
sahilmgandhi 18:6a4db94011d3 49 /* ARM armcc specific functions */
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 #if (__ARMCC_VERSION < 400677)
sahilmgandhi 18:6a4db94011d3 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
sahilmgandhi 18:6a4db94011d3 53 #endif
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55
sahilmgandhi 18:6a4db94011d3 56 /** \brief No Operation
sahilmgandhi 18:6a4db94011d3 57
sahilmgandhi 18:6a4db94011d3 58 No Operation does nothing. This instruction can be used for code alignment purposes.
sahilmgandhi 18:6a4db94011d3 59 */
sahilmgandhi 18:6a4db94011d3 60 #define __NOP __nop
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 /** \brief Wait For Interrupt
sahilmgandhi 18:6a4db94011d3 64
sahilmgandhi 18:6a4db94011d3 65 Wait For Interrupt is a hint instruction that suspends execution
sahilmgandhi 18:6a4db94011d3 66 until one of a number of events occurs.
sahilmgandhi 18:6a4db94011d3 67 */
sahilmgandhi 18:6a4db94011d3 68 #define __WFI __wfi
sahilmgandhi 18:6a4db94011d3 69
sahilmgandhi 18:6a4db94011d3 70
sahilmgandhi 18:6a4db94011d3 71 /** \brief Wait For Event
sahilmgandhi 18:6a4db94011d3 72
sahilmgandhi 18:6a4db94011d3 73 Wait For Event is a hint instruction that permits the processor to enter
sahilmgandhi 18:6a4db94011d3 74 a low-power state until one of a number of events occurs.
sahilmgandhi 18:6a4db94011d3 75 */
sahilmgandhi 18:6a4db94011d3 76 #define __WFE __wfe
sahilmgandhi 18:6a4db94011d3 77
sahilmgandhi 18:6a4db94011d3 78
sahilmgandhi 18:6a4db94011d3 79 /** \brief Send Event
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
sahilmgandhi 18:6a4db94011d3 82 */
sahilmgandhi 18:6a4db94011d3 83 #define __SEV __sev
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 /** \brief Instruction Synchronization Barrier
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
sahilmgandhi 18:6a4db94011d3 89 so that all instructions following the ISB are fetched from cache or
sahilmgandhi 18:6a4db94011d3 90 memory, after the instruction has been completed.
sahilmgandhi 18:6a4db94011d3 91 */
sahilmgandhi 18:6a4db94011d3 92 #define __ISB() do {\
sahilmgandhi 18:6a4db94011d3 93 __schedule_barrier();\
sahilmgandhi 18:6a4db94011d3 94 __isb(0xF);\
sahilmgandhi 18:6a4db94011d3 95 __schedule_barrier();\
sahilmgandhi 18:6a4db94011d3 96 } while (0)
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 /** \brief Data Synchronization Barrier
sahilmgandhi 18:6a4db94011d3 99
sahilmgandhi 18:6a4db94011d3 100 This function acts as a special kind of Data Memory Barrier.
sahilmgandhi 18:6a4db94011d3 101 It completes when all explicit memory accesses before this instruction complete.
sahilmgandhi 18:6a4db94011d3 102 */
sahilmgandhi 18:6a4db94011d3 103 #define __DSB() do {\
sahilmgandhi 18:6a4db94011d3 104 __schedule_barrier();\
sahilmgandhi 18:6a4db94011d3 105 __dsb(0xF);\
sahilmgandhi 18:6a4db94011d3 106 __schedule_barrier();\
sahilmgandhi 18:6a4db94011d3 107 } while (0)
sahilmgandhi 18:6a4db94011d3 108
sahilmgandhi 18:6a4db94011d3 109 /** \brief Data Memory Barrier
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 This function ensures the apparent order of the explicit memory operations before
sahilmgandhi 18:6a4db94011d3 112 and after the instruction, without ensuring their completion.
sahilmgandhi 18:6a4db94011d3 113 */
sahilmgandhi 18:6a4db94011d3 114 #define __DMB() do {\
sahilmgandhi 18:6a4db94011d3 115 __schedule_barrier();\
sahilmgandhi 18:6a4db94011d3 116 __dmb(0xF);\
sahilmgandhi 18:6a4db94011d3 117 __schedule_barrier();\
sahilmgandhi 18:6a4db94011d3 118 } while (0)
sahilmgandhi 18:6a4db94011d3 119
sahilmgandhi 18:6a4db94011d3 120 /** \brief Reverse byte order (32 bit)
sahilmgandhi 18:6a4db94011d3 121
sahilmgandhi 18:6a4db94011d3 122 This function reverses the byte order in integer value.
sahilmgandhi 18:6a4db94011d3 123
sahilmgandhi 18:6a4db94011d3 124 \param [in] value Value to reverse
sahilmgandhi 18:6a4db94011d3 125 \return Reversed value
sahilmgandhi 18:6a4db94011d3 126 */
sahilmgandhi 18:6a4db94011d3 127 #define __REV __rev
sahilmgandhi 18:6a4db94011d3 128
sahilmgandhi 18:6a4db94011d3 129
sahilmgandhi 18:6a4db94011d3 130 /** \brief Reverse byte order (16 bit)
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132 This function reverses the byte order in two unsigned short values.
sahilmgandhi 18:6a4db94011d3 133
sahilmgandhi 18:6a4db94011d3 134 \param [in] value Value to reverse
sahilmgandhi 18:6a4db94011d3 135 \return Reversed value
sahilmgandhi 18:6a4db94011d3 136 */
sahilmgandhi 18:6a4db94011d3 137 #ifndef __NO_EMBEDDED_ASM
sahilmgandhi 18:6a4db94011d3 138 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
sahilmgandhi 18:6a4db94011d3 139 {
sahilmgandhi 18:6a4db94011d3 140 rev16 r0, r0
sahilmgandhi 18:6a4db94011d3 141 bx lr
sahilmgandhi 18:6a4db94011d3 142 }
sahilmgandhi 18:6a4db94011d3 143 #endif
sahilmgandhi 18:6a4db94011d3 144
sahilmgandhi 18:6a4db94011d3 145 /** \brief Reverse byte order in signed short value
sahilmgandhi 18:6a4db94011d3 146
sahilmgandhi 18:6a4db94011d3 147 This function reverses the byte order in a signed short value with sign extension to integer.
sahilmgandhi 18:6a4db94011d3 148
sahilmgandhi 18:6a4db94011d3 149 \param [in] value Value to reverse
sahilmgandhi 18:6a4db94011d3 150 \return Reversed value
sahilmgandhi 18:6a4db94011d3 151 */
sahilmgandhi 18:6a4db94011d3 152 #ifndef __NO_EMBEDDED_ASM
sahilmgandhi 18:6a4db94011d3 153 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
sahilmgandhi 18:6a4db94011d3 154 {
sahilmgandhi 18:6a4db94011d3 155 revsh r0, r0
sahilmgandhi 18:6a4db94011d3 156 bx lr
sahilmgandhi 18:6a4db94011d3 157 }
sahilmgandhi 18:6a4db94011d3 158 #endif
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161 /** \brief Rotate Right in unsigned value (32 bit)
sahilmgandhi 18:6a4db94011d3 162
sahilmgandhi 18:6a4db94011d3 163 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
sahilmgandhi 18:6a4db94011d3 164
sahilmgandhi 18:6a4db94011d3 165 \param [in] value Value to rotate
sahilmgandhi 18:6a4db94011d3 166 \param [in] value Number of Bits to rotate
sahilmgandhi 18:6a4db94011d3 167 \return Rotated value
sahilmgandhi 18:6a4db94011d3 168 */
sahilmgandhi 18:6a4db94011d3 169 #define __ROR __ror
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171
sahilmgandhi 18:6a4db94011d3 172 /** \brief Breakpoint
sahilmgandhi 18:6a4db94011d3 173
sahilmgandhi 18:6a4db94011d3 174 This function causes the processor to enter Debug state.
sahilmgandhi 18:6a4db94011d3 175 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
sahilmgandhi 18:6a4db94011d3 176
sahilmgandhi 18:6a4db94011d3 177 \param [in] value is ignored by the processor.
sahilmgandhi 18:6a4db94011d3 178 If required, a debugger can use it to store additional information about the breakpoint.
sahilmgandhi 18:6a4db94011d3 179 */
sahilmgandhi 18:6a4db94011d3 180 #define __BKPT(value) __breakpoint(value)
sahilmgandhi 18:6a4db94011d3 181
sahilmgandhi 18:6a4db94011d3 182
sahilmgandhi 18:6a4db94011d3 183 /** \brief Reverse bit order of value
sahilmgandhi 18:6a4db94011d3 184
sahilmgandhi 18:6a4db94011d3 185 This function reverses the bit order of the given value.
sahilmgandhi 18:6a4db94011d3 186
sahilmgandhi 18:6a4db94011d3 187 \param [in] value Value to reverse
sahilmgandhi 18:6a4db94011d3 188 \return Reversed value
sahilmgandhi 18:6a4db94011d3 189 */
sahilmgandhi 18:6a4db94011d3 190 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
sahilmgandhi 18:6a4db94011d3 191 #define __RBIT __rbit
sahilmgandhi 18:6a4db94011d3 192 #else
sahilmgandhi 18:6a4db94011d3 193 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
sahilmgandhi 18:6a4db94011d3 194 {
sahilmgandhi 18:6a4db94011d3 195 uint32_t result;
sahilmgandhi 18:6a4db94011d3 196 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
sahilmgandhi 18:6a4db94011d3 197
sahilmgandhi 18:6a4db94011d3 198 result = value; // r will be reversed bits of v; first get LSB of v
sahilmgandhi 18:6a4db94011d3 199 for (value >>= 1; value; value >>= 1)
sahilmgandhi 18:6a4db94011d3 200 {
sahilmgandhi 18:6a4db94011d3 201 result <<= 1;
sahilmgandhi 18:6a4db94011d3 202 result |= value & 1;
sahilmgandhi 18:6a4db94011d3 203 s--;
sahilmgandhi 18:6a4db94011d3 204 }
sahilmgandhi 18:6a4db94011d3 205 result <<= s; // shift when v's highest bits are zero
sahilmgandhi 18:6a4db94011d3 206 return(result);
sahilmgandhi 18:6a4db94011d3 207 }
sahilmgandhi 18:6a4db94011d3 208 #endif
sahilmgandhi 18:6a4db94011d3 209
sahilmgandhi 18:6a4db94011d3 210
sahilmgandhi 18:6a4db94011d3 211 /** \brief Count leading zeros
sahilmgandhi 18:6a4db94011d3 212
sahilmgandhi 18:6a4db94011d3 213 This function counts the number of leading zeros of a data value.
sahilmgandhi 18:6a4db94011d3 214
sahilmgandhi 18:6a4db94011d3 215 \param [in] value Value to count the leading zeros
sahilmgandhi 18:6a4db94011d3 216 \return number of leading zeros in value
sahilmgandhi 18:6a4db94011d3 217 */
sahilmgandhi 18:6a4db94011d3 218 #define __CLZ __clz
sahilmgandhi 18:6a4db94011d3 219
sahilmgandhi 18:6a4db94011d3 220
sahilmgandhi 18:6a4db94011d3 221 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
sahilmgandhi 18:6a4db94011d3 222
sahilmgandhi 18:6a4db94011d3 223 /** \brief LDR Exclusive (8 bit)
sahilmgandhi 18:6a4db94011d3 224
sahilmgandhi 18:6a4db94011d3 225 This function executes a exclusive LDR instruction for 8 bit value.
sahilmgandhi 18:6a4db94011d3 226
sahilmgandhi 18:6a4db94011d3 227 \param [in] ptr Pointer to data
sahilmgandhi 18:6a4db94011d3 228 \return value of type uint8_t at (*ptr)
sahilmgandhi 18:6a4db94011d3 229 */
sahilmgandhi 18:6a4db94011d3 230 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
sahilmgandhi 18:6a4db94011d3 231
sahilmgandhi 18:6a4db94011d3 232
sahilmgandhi 18:6a4db94011d3 233 /** \brief LDR Exclusive (16 bit)
sahilmgandhi 18:6a4db94011d3 234
sahilmgandhi 18:6a4db94011d3 235 This function executes a exclusive LDR instruction for 16 bit values.
sahilmgandhi 18:6a4db94011d3 236
sahilmgandhi 18:6a4db94011d3 237 \param [in] ptr Pointer to data
sahilmgandhi 18:6a4db94011d3 238 \return value of type uint16_t at (*ptr)
sahilmgandhi 18:6a4db94011d3 239 */
sahilmgandhi 18:6a4db94011d3 240 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
sahilmgandhi 18:6a4db94011d3 241
sahilmgandhi 18:6a4db94011d3 242
sahilmgandhi 18:6a4db94011d3 243 /** \brief LDR Exclusive (32 bit)
sahilmgandhi 18:6a4db94011d3 244
sahilmgandhi 18:6a4db94011d3 245 This function executes a exclusive LDR instruction for 32 bit values.
sahilmgandhi 18:6a4db94011d3 246
sahilmgandhi 18:6a4db94011d3 247 \param [in] ptr Pointer to data
sahilmgandhi 18:6a4db94011d3 248 \return value of type uint32_t at (*ptr)
sahilmgandhi 18:6a4db94011d3 249 */
sahilmgandhi 18:6a4db94011d3 250 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
sahilmgandhi 18:6a4db94011d3 251
sahilmgandhi 18:6a4db94011d3 252
sahilmgandhi 18:6a4db94011d3 253 /** \brief STR Exclusive (8 bit)
sahilmgandhi 18:6a4db94011d3 254
sahilmgandhi 18:6a4db94011d3 255 This function executes a exclusive STR instruction for 8 bit values.
sahilmgandhi 18:6a4db94011d3 256
sahilmgandhi 18:6a4db94011d3 257 \param [in] value Value to store
sahilmgandhi 18:6a4db94011d3 258 \param [in] ptr Pointer to location
sahilmgandhi 18:6a4db94011d3 259 \return 0 Function succeeded
sahilmgandhi 18:6a4db94011d3 260 \return 1 Function failed
sahilmgandhi 18:6a4db94011d3 261 */
sahilmgandhi 18:6a4db94011d3 262 #define __STREXB(value, ptr) __strex(value, ptr)
sahilmgandhi 18:6a4db94011d3 263
sahilmgandhi 18:6a4db94011d3 264
sahilmgandhi 18:6a4db94011d3 265 /** \brief STR Exclusive (16 bit)
sahilmgandhi 18:6a4db94011d3 266
sahilmgandhi 18:6a4db94011d3 267 This function executes a exclusive STR instruction for 16 bit values.
sahilmgandhi 18:6a4db94011d3 268
sahilmgandhi 18:6a4db94011d3 269 \param [in] value Value to store
sahilmgandhi 18:6a4db94011d3 270 \param [in] ptr Pointer to location
sahilmgandhi 18:6a4db94011d3 271 \return 0 Function succeeded
sahilmgandhi 18:6a4db94011d3 272 \return 1 Function failed
sahilmgandhi 18:6a4db94011d3 273 */
sahilmgandhi 18:6a4db94011d3 274 #define __STREXH(value, ptr) __strex(value, ptr)
sahilmgandhi 18:6a4db94011d3 275
sahilmgandhi 18:6a4db94011d3 276
sahilmgandhi 18:6a4db94011d3 277 /** \brief STR Exclusive (32 bit)
sahilmgandhi 18:6a4db94011d3 278
sahilmgandhi 18:6a4db94011d3 279 This function executes a exclusive STR instruction for 32 bit values.
sahilmgandhi 18:6a4db94011d3 280
sahilmgandhi 18:6a4db94011d3 281 \param [in] value Value to store
sahilmgandhi 18:6a4db94011d3 282 \param [in] ptr Pointer to location
sahilmgandhi 18:6a4db94011d3 283 \return 0 Function succeeded
sahilmgandhi 18:6a4db94011d3 284 \return 1 Function failed
sahilmgandhi 18:6a4db94011d3 285 */
sahilmgandhi 18:6a4db94011d3 286 #define __STREXW(value, ptr) __strex(value, ptr)
sahilmgandhi 18:6a4db94011d3 287
sahilmgandhi 18:6a4db94011d3 288
sahilmgandhi 18:6a4db94011d3 289 /** \brief Remove the exclusive lock
sahilmgandhi 18:6a4db94011d3 290
sahilmgandhi 18:6a4db94011d3 291 This function removes the exclusive lock which is created by LDREX.
sahilmgandhi 18:6a4db94011d3 292
sahilmgandhi 18:6a4db94011d3 293 */
sahilmgandhi 18:6a4db94011d3 294 #define __CLREX __clrex
sahilmgandhi 18:6a4db94011d3 295
sahilmgandhi 18:6a4db94011d3 296
sahilmgandhi 18:6a4db94011d3 297 /** \brief Signed Saturate
sahilmgandhi 18:6a4db94011d3 298
sahilmgandhi 18:6a4db94011d3 299 This function saturates a signed value.
sahilmgandhi 18:6a4db94011d3 300
sahilmgandhi 18:6a4db94011d3 301 \param [in] value Value to be saturated
sahilmgandhi 18:6a4db94011d3 302 \param [in] sat Bit position to saturate to (1..32)
sahilmgandhi 18:6a4db94011d3 303 \return Saturated value
sahilmgandhi 18:6a4db94011d3 304 */
sahilmgandhi 18:6a4db94011d3 305 #define __SSAT __ssat
sahilmgandhi 18:6a4db94011d3 306
sahilmgandhi 18:6a4db94011d3 307
sahilmgandhi 18:6a4db94011d3 308 /** \brief Unsigned Saturate
sahilmgandhi 18:6a4db94011d3 309
sahilmgandhi 18:6a4db94011d3 310 This function saturates an unsigned value.
sahilmgandhi 18:6a4db94011d3 311
sahilmgandhi 18:6a4db94011d3 312 \param [in] value Value to be saturated
sahilmgandhi 18:6a4db94011d3 313 \param [in] sat Bit position to saturate to (0..31)
sahilmgandhi 18:6a4db94011d3 314 \return Saturated value
sahilmgandhi 18:6a4db94011d3 315 */
sahilmgandhi 18:6a4db94011d3 316 #define __USAT __usat
sahilmgandhi 18:6a4db94011d3 317
sahilmgandhi 18:6a4db94011d3 318
sahilmgandhi 18:6a4db94011d3 319 /** \brief Rotate Right with Extend (32 bit)
sahilmgandhi 18:6a4db94011d3 320
sahilmgandhi 18:6a4db94011d3 321 This function moves each bit of a bitstring right by one bit.
sahilmgandhi 18:6a4db94011d3 322 The carry input is shifted in at the left end of the bitstring.
sahilmgandhi 18:6a4db94011d3 323
sahilmgandhi 18:6a4db94011d3 324 \param [in] value Value to rotate
sahilmgandhi 18:6a4db94011d3 325 \return Rotated value
sahilmgandhi 18:6a4db94011d3 326 */
sahilmgandhi 18:6a4db94011d3 327 #ifndef __NO_EMBEDDED_ASM
sahilmgandhi 18:6a4db94011d3 328 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
sahilmgandhi 18:6a4db94011d3 329 {
sahilmgandhi 18:6a4db94011d3 330 rrx r0, r0
sahilmgandhi 18:6a4db94011d3 331 bx lr
sahilmgandhi 18:6a4db94011d3 332 }
sahilmgandhi 18:6a4db94011d3 333 #endif
sahilmgandhi 18:6a4db94011d3 334
sahilmgandhi 18:6a4db94011d3 335
sahilmgandhi 18:6a4db94011d3 336 /** \brief LDRT Unprivileged (8 bit)
sahilmgandhi 18:6a4db94011d3 337
sahilmgandhi 18:6a4db94011d3 338 This function executes a Unprivileged LDRT instruction for 8 bit value.
sahilmgandhi 18:6a4db94011d3 339
sahilmgandhi 18:6a4db94011d3 340 \param [in] ptr Pointer to data
sahilmgandhi 18:6a4db94011d3 341 \return value of type uint8_t at (*ptr)
sahilmgandhi 18:6a4db94011d3 342 */
sahilmgandhi 18:6a4db94011d3 343 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
sahilmgandhi 18:6a4db94011d3 344
sahilmgandhi 18:6a4db94011d3 345
sahilmgandhi 18:6a4db94011d3 346 /** \brief LDRT Unprivileged (16 bit)
sahilmgandhi 18:6a4db94011d3 347
sahilmgandhi 18:6a4db94011d3 348 This function executes a Unprivileged LDRT instruction for 16 bit values.
sahilmgandhi 18:6a4db94011d3 349
sahilmgandhi 18:6a4db94011d3 350 \param [in] ptr Pointer to data
sahilmgandhi 18:6a4db94011d3 351 \return value of type uint16_t at (*ptr)
sahilmgandhi 18:6a4db94011d3 352 */
sahilmgandhi 18:6a4db94011d3 353 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
sahilmgandhi 18:6a4db94011d3 354
sahilmgandhi 18:6a4db94011d3 355
sahilmgandhi 18:6a4db94011d3 356 /** \brief LDRT Unprivileged (32 bit)
sahilmgandhi 18:6a4db94011d3 357
sahilmgandhi 18:6a4db94011d3 358 This function executes a Unprivileged LDRT instruction for 32 bit values.
sahilmgandhi 18:6a4db94011d3 359
sahilmgandhi 18:6a4db94011d3 360 \param [in] ptr Pointer to data
sahilmgandhi 18:6a4db94011d3 361 \return value of type uint32_t at (*ptr)
sahilmgandhi 18:6a4db94011d3 362 */
sahilmgandhi 18:6a4db94011d3 363 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
sahilmgandhi 18:6a4db94011d3 364
sahilmgandhi 18:6a4db94011d3 365
sahilmgandhi 18:6a4db94011d3 366 /** \brief STRT Unprivileged (8 bit)
sahilmgandhi 18:6a4db94011d3 367
sahilmgandhi 18:6a4db94011d3 368 This function executes a Unprivileged STRT instruction for 8 bit values.
sahilmgandhi 18:6a4db94011d3 369
sahilmgandhi 18:6a4db94011d3 370 \param [in] value Value to store
sahilmgandhi 18:6a4db94011d3 371 \param [in] ptr Pointer to location
sahilmgandhi 18:6a4db94011d3 372 */
sahilmgandhi 18:6a4db94011d3 373 #define __STRBT(value, ptr) __strt(value, ptr)
sahilmgandhi 18:6a4db94011d3 374
sahilmgandhi 18:6a4db94011d3 375
sahilmgandhi 18:6a4db94011d3 376 /** \brief STRT Unprivileged (16 bit)
sahilmgandhi 18:6a4db94011d3 377
sahilmgandhi 18:6a4db94011d3 378 This function executes a Unprivileged STRT instruction for 16 bit values.
sahilmgandhi 18:6a4db94011d3 379
sahilmgandhi 18:6a4db94011d3 380 \param [in] value Value to store
sahilmgandhi 18:6a4db94011d3 381 \param [in] ptr Pointer to location
sahilmgandhi 18:6a4db94011d3 382 */
sahilmgandhi 18:6a4db94011d3 383 #define __STRHT(value, ptr) __strt(value, ptr)
sahilmgandhi 18:6a4db94011d3 384
sahilmgandhi 18:6a4db94011d3 385
sahilmgandhi 18:6a4db94011d3 386 /** \brief STRT Unprivileged (32 bit)
sahilmgandhi 18:6a4db94011d3 387
sahilmgandhi 18:6a4db94011d3 388 This function executes a Unprivileged STRT instruction for 32 bit values.
sahilmgandhi 18:6a4db94011d3 389
sahilmgandhi 18:6a4db94011d3 390 \param [in] value Value to store
sahilmgandhi 18:6a4db94011d3 391 \param [in] ptr Pointer to location
sahilmgandhi 18:6a4db94011d3 392 */
sahilmgandhi 18:6a4db94011d3 393 #define __STRT(value, ptr) __strt(value, ptr)
sahilmgandhi 18:6a4db94011d3 394
sahilmgandhi 18:6a4db94011d3 395 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
sahilmgandhi 18:6a4db94011d3 396
sahilmgandhi 18:6a4db94011d3 397
sahilmgandhi 18:6a4db94011d3 398 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
sahilmgandhi 18:6a4db94011d3 399 /* GNU gcc specific functions */
sahilmgandhi 18:6a4db94011d3 400
sahilmgandhi 18:6a4db94011d3 401 /* Define macros for porting to both thumb1 and thumb2.
sahilmgandhi 18:6a4db94011d3 402 * For thumb1, use low register (r0-r7), specified by constrant "l"
sahilmgandhi 18:6a4db94011d3 403 * Otherwise, use general registers, specified by constrant "r" */
sahilmgandhi 18:6a4db94011d3 404 #if defined (__thumb__) && !defined (__thumb2__)
sahilmgandhi 18:6a4db94011d3 405 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
sahilmgandhi 18:6a4db94011d3 406 #define __CMSIS_GCC_USE_REG(r) "l" (r)
sahilmgandhi 18:6a4db94011d3 407 #else
sahilmgandhi 18:6a4db94011d3 408 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
sahilmgandhi 18:6a4db94011d3 409 #define __CMSIS_GCC_USE_REG(r) "r" (r)
sahilmgandhi 18:6a4db94011d3 410 #endif
sahilmgandhi 18:6a4db94011d3 411
sahilmgandhi 18:6a4db94011d3 412 /** \brief No Operation
sahilmgandhi 18:6a4db94011d3 413
sahilmgandhi 18:6a4db94011d3 414 No Operation does nothing. This instruction can be used for code alignment purposes.
sahilmgandhi 18:6a4db94011d3 415 */
sahilmgandhi 18:6a4db94011d3 416 __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
sahilmgandhi 18:6a4db94011d3 417 {
sahilmgandhi 18:6a4db94011d3 418 __ASM volatile ("nop");
sahilmgandhi 18:6a4db94011d3 419 }
sahilmgandhi 18:6a4db94011d3 420
sahilmgandhi 18:6a4db94011d3 421
sahilmgandhi 18:6a4db94011d3 422 /** \brief Wait For Interrupt
sahilmgandhi 18:6a4db94011d3 423
sahilmgandhi 18:6a4db94011d3 424 Wait For Interrupt is a hint instruction that suspends execution
sahilmgandhi 18:6a4db94011d3 425 until one of a number of events occurs.
sahilmgandhi 18:6a4db94011d3 426 */
sahilmgandhi 18:6a4db94011d3 427 __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
sahilmgandhi 18:6a4db94011d3 428 {
sahilmgandhi 18:6a4db94011d3 429 __ASM volatile ("wfi");
sahilmgandhi 18:6a4db94011d3 430 }
sahilmgandhi 18:6a4db94011d3 431
sahilmgandhi 18:6a4db94011d3 432
sahilmgandhi 18:6a4db94011d3 433 /** \brief Wait For Event
sahilmgandhi 18:6a4db94011d3 434
sahilmgandhi 18:6a4db94011d3 435 Wait For Event is a hint instruction that permits the processor to enter
sahilmgandhi 18:6a4db94011d3 436 a low-power state until one of a number of events occurs.
sahilmgandhi 18:6a4db94011d3 437 */
sahilmgandhi 18:6a4db94011d3 438 __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
sahilmgandhi 18:6a4db94011d3 439 {
sahilmgandhi 18:6a4db94011d3 440 __ASM volatile ("wfe");
sahilmgandhi 18:6a4db94011d3 441 }
sahilmgandhi 18:6a4db94011d3 442
sahilmgandhi 18:6a4db94011d3 443
sahilmgandhi 18:6a4db94011d3 444 /** \brief Send Event
sahilmgandhi 18:6a4db94011d3 445
sahilmgandhi 18:6a4db94011d3 446 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
sahilmgandhi 18:6a4db94011d3 447 */
sahilmgandhi 18:6a4db94011d3 448 __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
sahilmgandhi 18:6a4db94011d3 449 {
sahilmgandhi 18:6a4db94011d3 450 __ASM volatile ("sev");
sahilmgandhi 18:6a4db94011d3 451 }
sahilmgandhi 18:6a4db94011d3 452
sahilmgandhi 18:6a4db94011d3 453
sahilmgandhi 18:6a4db94011d3 454 /** \brief Instruction Synchronization Barrier
sahilmgandhi 18:6a4db94011d3 455
sahilmgandhi 18:6a4db94011d3 456 Instruction Synchronization Barrier flushes the pipeline in the processor,
sahilmgandhi 18:6a4db94011d3 457 so that all instructions following the ISB are fetched from cache or
sahilmgandhi 18:6a4db94011d3 458 memory, after the instruction has been completed.
sahilmgandhi 18:6a4db94011d3 459 */
sahilmgandhi 18:6a4db94011d3 460 __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
sahilmgandhi 18:6a4db94011d3 461 {
sahilmgandhi 18:6a4db94011d3 462 __ASM volatile ("isb 0xF":::"memory");
sahilmgandhi 18:6a4db94011d3 463 }
sahilmgandhi 18:6a4db94011d3 464
sahilmgandhi 18:6a4db94011d3 465
sahilmgandhi 18:6a4db94011d3 466 /** \brief Data Synchronization Barrier
sahilmgandhi 18:6a4db94011d3 467
sahilmgandhi 18:6a4db94011d3 468 This function acts as a special kind of Data Memory Barrier.
sahilmgandhi 18:6a4db94011d3 469 It completes when all explicit memory accesses before this instruction complete.
sahilmgandhi 18:6a4db94011d3 470 */
sahilmgandhi 18:6a4db94011d3 471 __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
sahilmgandhi 18:6a4db94011d3 472 {
sahilmgandhi 18:6a4db94011d3 473 __ASM volatile ("dsb 0xF":::"memory");
sahilmgandhi 18:6a4db94011d3 474 }
sahilmgandhi 18:6a4db94011d3 475
sahilmgandhi 18:6a4db94011d3 476
sahilmgandhi 18:6a4db94011d3 477 /** \brief Data Memory Barrier
sahilmgandhi 18:6a4db94011d3 478
sahilmgandhi 18:6a4db94011d3 479 This function ensures the apparent order of the explicit memory operations before
sahilmgandhi 18:6a4db94011d3 480 and after the instruction, without ensuring their completion.
sahilmgandhi 18:6a4db94011d3 481 */
sahilmgandhi 18:6a4db94011d3 482 __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
sahilmgandhi 18:6a4db94011d3 483 {
sahilmgandhi 18:6a4db94011d3 484 __ASM volatile ("dmb 0xF":::"memory");
sahilmgandhi 18:6a4db94011d3 485 }
sahilmgandhi 18:6a4db94011d3 486
sahilmgandhi 18:6a4db94011d3 487
sahilmgandhi 18:6a4db94011d3 488 /** \brief Reverse byte order (32 bit)
sahilmgandhi 18:6a4db94011d3 489
sahilmgandhi 18:6a4db94011d3 490 This function reverses the byte order in integer value.
sahilmgandhi 18:6a4db94011d3 491
sahilmgandhi 18:6a4db94011d3 492 \param [in] value Value to reverse
sahilmgandhi 18:6a4db94011d3 493 \return Reversed value
sahilmgandhi 18:6a4db94011d3 494 */
sahilmgandhi 18:6a4db94011d3 495 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
sahilmgandhi 18:6a4db94011d3 496 {
sahilmgandhi 18:6a4db94011d3 497 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
sahilmgandhi 18:6a4db94011d3 498 return __builtin_bswap32(value);
sahilmgandhi 18:6a4db94011d3 499 #else
sahilmgandhi 18:6a4db94011d3 500 uint32_t result;
sahilmgandhi 18:6a4db94011d3 501
sahilmgandhi 18:6a4db94011d3 502 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
sahilmgandhi 18:6a4db94011d3 503 return(result);
sahilmgandhi 18:6a4db94011d3 504 #endif
sahilmgandhi 18:6a4db94011d3 505 }
sahilmgandhi 18:6a4db94011d3 506
sahilmgandhi 18:6a4db94011d3 507
sahilmgandhi 18:6a4db94011d3 508 /** \brief Reverse byte order (16 bit)
sahilmgandhi 18:6a4db94011d3 509
sahilmgandhi 18:6a4db94011d3 510 This function reverses the byte order in two unsigned short values.
sahilmgandhi 18:6a4db94011d3 511
sahilmgandhi 18:6a4db94011d3 512 \param [in] value Value to reverse
sahilmgandhi 18:6a4db94011d3 513 \return Reversed value
sahilmgandhi 18:6a4db94011d3 514 */
sahilmgandhi 18:6a4db94011d3 515 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
sahilmgandhi 18:6a4db94011d3 516 {
sahilmgandhi 18:6a4db94011d3 517 uint32_t result;
sahilmgandhi 18:6a4db94011d3 518
sahilmgandhi 18:6a4db94011d3 519 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
sahilmgandhi 18:6a4db94011d3 520 return(result);
sahilmgandhi 18:6a4db94011d3 521 }
sahilmgandhi 18:6a4db94011d3 522
sahilmgandhi 18:6a4db94011d3 523
sahilmgandhi 18:6a4db94011d3 524 /** \brief Reverse byte order in signed short value
sahilmgandhi 18:6a4db94011d3 525
sahilmgandhi 18:6a4db94011d3 526 This function reverses the byte order in a signed short value with sign extension to integer.
sahilmgandhi 18:6a4db94011d3 527
sahilmgandhi 18:6a4db94011d3 528 \param [in] value Value to reverse
sahilmgandhi 18:6a4db94011d3 529 \return Reversed value
sahilmgandhi 18:6a4db94011d3 530 */
sahilmgandhi 18:6a4db94011d3 531 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
sahilmgandhi 18:6a4db94011d3 532 {
sahilmgandhi 18:6a4db94011d3 533 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
sahilmgandhi 18:6a4db94011d3 534 return (short)__builtin_bswap16(value);
sahilmgandhi 18:6a4db94011d3 535 #else
sahilmgandhi 18:6a4db94011d3 536 uint32_t result;
sahilmgandhi 18:6a4db94011d3 537
sahilmgandhi 18:6a4db94011d3 538 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
sahilmgandhi 18:6a4db94011d3 539 return(result);
sahilmgandhi 18:6a4db94011d3 540 #endif
sahilmgandhi 18:6a4db94011d3 541 }
sahilmgandhi 18:6a4db94011d3 542
sahilmgandhi 18:6a4db94011d3 543
sahilmgandhi 18:6a4db94011d3 544 /** \brief Rotate Right in unsigned value (32 bit)
sahilmgandhi 18:6a4db94011d3 545
sahilmgandhi 18:6a4db94011d3 546 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
sahilmgandhi 18:6a4db94011d3 547
sahilmgandhi 18:6a4db94011d3 548 \param [in] value Value to rotate
sahilmgandhi 18:6a4db94011d3 549 \param [in] value Number of Bits to rotate
sahilmgandhi 18:6a4db94011d3 550 \return Rotated value
sahilmgandhi 18:6a4db94011d3 551 */
sahilmgandhi 18:6a4db94011d3 552 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 553 {
sahilmgandhi 18:6a4db94011d3 554 return (op1 >> op2) | (op1 << (32 - op2));
sahilmgandhi 18:6a4db94011d3 555 }
sahilmgandhi 18:6a4db94011d3 556
sahilmgandhi 18:6a4db94011d3 557
sahilmgandhi 18:6a4db94011d3 558 /** \brief Breakpoint
sahilmgandhi 18:6a4db94011d3 559
sahilmgandhi 18:6a4db94011d3 560 This function causes the processor to enter Debug state.
sahilmgandhi 18:6a4db94011d3 561 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
sahilmgandhi 18:6a4db94011d3 562
sahilmgandhi 18:6a4db94011d3 563 \param [in] value is ignored by the processor.
sahilmgandhi 18:6a4db94011d3 564 If required, a debugger can use it to store additional information about the breakpoint.
sahilmgandhi 18:6a4db94011d3 565 */
sahilmgandhi 18:6a4db94011d3 566 #define __BKPT(value) __ASM volatile ("bkpt "#value)
sahilmgandhi 18:6a4db94011d3 567
sahilmgandhi 18:6a4db94011d3 568
sahilmgandhi 18:6a4db94011d3 569 /** \brief Reverse bit order of value
sahilmgandhi 18:6a4db94011d3 570
sahilmgandhi 18:6a4db94011d3 571 This function reverses the bit order of the given value.
sahilmgandhi 18:6a4db94011d3 572
sahilmgandhi 18:6a4db94011d3 573 \param [in] value Value to reverse
sahilmgandhi 18:6a4db94011d3 574 \return Reversed value
sahilmgandhi 18:6a4db94011d3 575 */
sahilmgandhi 18:6a4db94011d3 576 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
sahilmgandhi 18:6a4db94011d3 577 {
sahilmgandhi 18:6a4db94011d3 578 uint32_t result;
sahilmgandhi 18:6a4db94011d3 579
sahilmgandhi 18:6a4db94011d3 580 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
sahilmgandhi 18:6a4db94011d3 581 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
sahilmgandhi 18:6a4db94011d3 582 #else
sahilmgandhi 18:6a4db94011d3 583 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
sahilmgandhi 18:6a4db94011d3 584
sahilmgandhi 18:6a4db94011d3 585 result = value; // r will be reversed bits of v; first get LSB of v
sahilmgandhi 18:6a4db94011d3 586 for (value >>= 1; value; value >>= 1)
sahilmgandhi 18:6a4db94011d3 587 {
sahilmgandhi 18:6a4db94011d3 588 result <<= 1;
sahilmgandhi 18:6a4db94011d3 589 result |= value & 1;
sahilmgandhi 18:6a4db94011d3 590 s--;
sahilmgandhi 18:6a4db94011d3 591 }
sahilmgandhi 18:6a4db94011d3 592 result <<= s; // shift when v's highest bits are zero
sahilmgandhi 18:6a4db94011d3 593 #endif
sahilmgandhi 18:6a4db94011d3 594 return(result);
sahilmgandhi 18:6a4db94011d3 595 }
sahilmgandhi 18:6a4db94011d3 596
sahilmgandhi 18:6a4db94011d3 597
sahilmgandhi 18:6a4db94011d3 598 /** \brief Count leading zeros
sahilmgandhi 18:6a4db94011d3 599
sahilmgandhi 18:6a4db94011d3 600 This function counts the number of leading zeros of a data value.
sahilmgandhi 18:6a4db94011d3 601
sahilmgandhi 18:6a4db94011d3 602 \param [in] value Value to count the leading zeros
sahilmgandhi 18:6a4db94011d3 603 \return number of leading zeros in value
sahilmgandhi 18:6a4db94011d3 604 */
sahilmgandhi 18:6a4db94011d3 605 #define __CLZ __builtin_clz
sahilmgandhi 18:6a4db94011d3 606
sahilmgandhi 18:6a4db94011d3 607
sahilmgandhi 18:6a4db94011d3 608 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
sahilmgandhi 18:6a4db94011d3 609
sahilmgandhi 18:6a4db94011d3 610 /** \brief LDR Exclusive (8 bit)
sahilmgandhi 18:6a4db94011d3 611
sahilmgandhi 18:6a4db94011d3 612 This function executes a exclusive LDR instruction for 8 bit value.
sahilmgandhi 18:6a4db94011d3 613
sahilmgandhi 18:6a4db94011d3 614 \param [in] ptr Pointer to data
sahilmgandhi 18:6a4db94011d3 615 \return value of type uint8_t at (*ptr)
sahilmgandhi 18:6a4db94011d3 616 */
sahilmgandhi 18:6a4db94011d3 617 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
sahilmgandhi 18:6a4db94011d3 618 {
sahilmgandhi 18:6a4db94011d3 619 uint32_t result;
sahilmgandhi 18:6a4db94011d3 620
sahilmgandhi 18:6a4db94011d3 621 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
sahilmgandhi 18:6a4db94011d3 622 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
sahilmgandhi 18:6a4db94011d3 623 #else
sahilmgandhi 18:6a4db94011d3 624 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
sahilmgandhi 18:6a4db94011d3 625 accepted by assembler. So has to use following less efficient pattern.
sahilmgandhi 18:6a4db94011d3 626 */
sahilmgandhi 18:6a4db94011d3 627 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
sahilmgandhi 18:6a4db94011d3 628 #endif
sahilmgandhi 18:6a4db94011d3 629 return ((uint8_t) result); /* Add explicit type cast here */
sahilmgandhi 18:6a4db94011d3 630 }
sahilmgandhi 18:6a4db94011d3 631
sahilmgandhi 18:6a4db94011d3 632
sahilmgandhi 18:6a4db94011d3 633 /** \brief LDR Exclusive (16 bit)
sahilmgandhi 18:6a4db94011d3 634
sahilmgandhi 18:6a4db94011d3 635 This function executes a exclusive LDR instruction for 16 bit values.
sahilmgandhi 18:6a4db94011d3 636
sahilmgandhi 18:6a4db94011d3 637 \param [in] ptr Pointer to data
sahilmgandhi 18:6a4db94011d3 638 \return value of type uint16_t at (*ptr)
sahilmgandhi 18:6a4db94011d3 639 */
sahilmgandhi 18:6a4db94011d3 640 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
sahilmgandhi 18:6a4db94011d3 641 {
sahilmgandhi 18:6a4db94011d3 642 uint32_t result;
sahilmgandhi 18:6a4db94011d3 643
sahilmgandhi 18:6a4db94011d3 644 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
sahilmgandhi 18:6a4db94011d3 645 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
sahilmgandhi 18:6a4db94011d3 646 #else
sahilmgandhi 18:6a4db94011d3 647 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
sahilmgandhi 18:6a4db94011d3 648 accepted by assembler. So has to use following less efficient pattern.
sahilmgandhi 18:6a4db94011d3 649 */
sahilmgandhi 18:6a4db94011d3 650 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
sahilmgandhi 18:6a4db94011d3 651 #endif
sahilmgandhi 18:6a4db94011d3 652 return ((uint16_t) result); /* Add explicit type cast here */
sahilmgandhi 18:6a4db94011d3 653 }
sahilmgandhi 18:6a4db94011d3 654
sahilmgandhi 18:6a4db94011d3 655
sahilmgandhi 18:6a4db94011d3 656 /** \brief LDR Exclusive (32 bit)
sahilmgandhi 18:6a4db94011d3 657
sahilmgandhi 18:6a4db94011d3 658 This function executes a exclusive LDR instruction for 32 bit values.
sahilmgandhi 18:6a4db94011d3 659
sahilmgandhi 18:6a4db94011d3 660 \param [in] ptr Pointer to data
sahilmgandhi 18:6a4db94011d3 661 \return value of type uint32_t at (*ptr)
sahilmgandhi 18:6a4db94011d3 662 */
sahilmgandhi 18:6a4db94011d3 663 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
sahilmgandhi 18:6a4db94011d3 664 {
sahilmgandhi 18:6a4db94011d3 665 uint32_t result;
sahilmgandhi 18:6a4db94011d3 666
sahilmgandhi 18:6a4db94011d3 667 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
sahilmgandhi 18:6a4db94011d3 668 return(result);
sahilmgandhi 18:6a4db94011d3 669 }
sahilmgandhi 18:6a4db94011d3 670
sahilmgandhi 18:6a4db94011d3 671
sahilmgandhi 18:6a4db94011d3 672 /** \brief STR Exclusive (8 bit)
sahilmgandhi 18:6a4db94011d3 673
sahilmgandhi 18:6a4db94011d3 674 This function executes a exclusive STR instruction for 8 bit values.
sahilmgandhi 18:6a4db94011d3 675
sahilmgandhi 18:6a4db94011d3 676 \param [in] value Value to store
sahilmgandhi 18:6a4db94011d3 677 \param [in] ptr Pointer to location
sahilmgandhi 18:6a4db94011d3 678 \return 0 Function succeeded
sahilmgandhi 18:6a4db94011d3 679 \return 1 Function failed
sahilmgandhi 18:6a4db94011d3 680 */
sahilmgandhi 18:6a4db94011d3 681 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
sahilmgandhi 18:6a4db94011d3 682 {
sahilmgandhi 18:6a4db94011d3 683 uint32_t result;
sahilmgandhi 18:6a4db94011d3 684
sahilmgandhi 18:6a4db94011d3 685 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
sahilmgandhi 18:6a4db94011d3 686 return(result);
sahilmgandhi 18:6a4db94011d3 687 }
sahilmgandhi 18:6a4db94011d3 688
sahilmgandhi 18:6a4db94011d3 689
sahilmgandhi 18:6a4db94011d3 690 /** \brief STR Exclusive (16 bit)
sahilmgandhi 18:6a4db94011d3 691
sahilmgandhi 18:6a4db94011d3 692 This function executes a exclusive STR instruction for 16 bit values.
sahilmgandhi 18:6a4db94011d3 693
sahilmgandhi 18:6a4db94011d3 694 \param [in] value Value to store
sahilmgandhi 18:6a4db94011d3 695 \param [in] ptr Pointer to location
sahilmgandhi 18:6a4db94011d3 696 \return 0 Function succeeded
sahilmgandhi 18:6a4db94011d3 697 \return 1 Function failed
sahilmgandhi 18:6a4db94011d3 698 */
sahilmgandhi 18:6a4db94011d3 699 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
sahilmgandhi 18:6a4db94011d3 700 {
sahilmgandhi 18:6a4db94011d3 701 uint32_t result;
sahilmgandhi 18:6a4db94011d3 702
sahilmgandhi 18:6a4db94011d3 703 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
sahilmgandhi 18:6a4db94011d3 704 return(result);
sahilmgandhi 18:6a4db94011d3 705 }
sahilmgandhi 18:6a4db94011d3 706
sahilmgandhi 18:6a4db94011d3 707
sahilmgandhi 18:6a4db94011d3 708 /** \brief STR Exclusive (32 bit)
sahilmgandhi 18:6a4db94011d3 709
sahilmgandhi 18:6a4db94011d3 710 This function executes a exclusive STR instruction for 32 bit values.
sahilmgandhi 18:6a4db94011d3 711
sahilmgandhi 18:6a4db94011d3 712 \param [in] value Value to store
sahilmgandhi 18:6a4db94011d3 713 \param [in] ptr Pointer to location
sahilmgandhi 18:6a4db94011d3 714 \return 0 Function succeeded
sahilmgandhi 18:6a4db94011d3 715 \return 1 Function failed
sahilmgandhi 18:6a4db94011d3 716 */
sahilmgandhi 18:6a4db94011d3 717 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
sahilmgandhi 18:6a4db94011d3 718 {
sahilmgandhi 18:6a4db94011d3 719 uint32_t result;
sahilmgandhi 18:6a4db94011d3 720
sahilmgandhi 18:6a4db94011d3 721 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
sahilmgandhi 18:6a4db94011d3 722 return(result);
sahilmgandhi 18:6a4db94011d3 723 }
sahilmgandhi 18:6a4db94011d3 724
sahilmgandhi 18:6a4db94011d3 725
sahilmgandhi 18:6a4db94011d3 726 /** \brief Remove the exclusive lock
sahilmgandhi 18:6a4db94011d3 727
sahilmgandhi 18:6a4db94011d3 728 This function removes the exclusive lock which is created by LDREX.
sahilmgandhi 18:6a4db94011d3 729
sahilmgandhi 18:6a4db94011d3 730 */
sahilmgandhi 18:6a4db94011d3 731 __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
sahilmgandhi 18:6a4db94011d3 732 {
sahilmgandhi 18:6a4db94011d3 733 __ASM volatile ("clrex" ::: "memory");
sahilmgandhi 18:6a4db94011d3 734 }
sahilmgandhi 18:6a4db94011d3 735
sahilmgandhi 18:6a4db94011d3 736
sahilmgandhi 18:6a4db94011d3 737 /** \brief Signed Saturate
sahilmgandhi 18:6a4db94011d3 738
sahilmgandhi 18:6a4db94011d3 739 This function saturates a signed value.
sahilmgandhi 18:6a4db94011d3 740
sahilmgandhi 18:6a4db94011d3 741 \param [in] value Value to be saturated
sahilmgandhi 18:6a4db94011d3 742 \param [in] sat Bit position to saturate to (1..32)
sahilmgandhi 18:6a4db94011d3 743 \return Saturated value
sahilmgandhi 18:6a4db94011d3 744 */
sahilmgandhi 18:6a4db94011d3 745 #define __SSAT(ARG1,ARG2) \
sahilmgandhi 18:6a4db94011d3 746 ({ \
sahilmgandhi 18:6a4db94011d3 747 uint32_t __RES, __ARG1 = (ARG1); \
sahilmgandhi 18:6a4db94011d3 748 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
sahilmgandhi 18:6a4db94011d3 749 __RES; \
sahilmgandhi 18:6a4db94011d3 750 })
sahilmgandhi 18:6a4db94011d3 751
sahilmgandhi 18:6a4db94011d3 752
sahilmgandhi 18:6a4db94011d3 753 /** \brief Unsigned Saturate
sahilmgandhi 18:6a4db94011d3 754
sahilmgandhi 18:6a4db94011d3 755 This function saturates an unsigned value.
sahilmgandhi 18:6a4db94011d3 756
sahilmgandhi 18:6a4db94011d3 757 \param [in] value Value to be saturated
sahilmgandhi 18:6a4db94011d3 758 \param [in] sat Bit position to saturate to (0..31)
sahilmgandhi 18:6a4db94011d3 759 \return Saturated value
sahilmgandhi 18:6a4db94011d3 760 */
sahilmgandhi 18:6a4db94011d3 761 #define __USAT(ARG1,ARG2) \
sahilmgandhi 18:6a4db94011d3 762 ({ \
sahilmgandhi 18:6a4db94011d3 763 uint32_t __RES, __ARG1 = (ARG1); \
sahilmgandhi 18:6a4db94011d3 764 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
sahilmgandhi 18:6a4db94011d3 765 __RES; \
sahilmgandhi 18:6a4db94011d3 766 })
sahilmgandhi 18:6a4db94011d3 767
sahilmgandhi 18:6a4db94011d3 768
sahilmgandhi 18:6a4db94011d3 769 /** \brief Rotate Right with Extend (32 bit)
sahilmgandhi 18:6a4db94011d3 770
sahilmgandhi 18:6a4db94011d3 771 This function moves each bit of a bitstring right by one bit.
sahilmgandhi 18:6a4db94011d3 772 The carry input is shifted in at the left end of the bitstring.
sahilmgandhi 18:6a4db94011d3 773
sahilmgandhi 18:6a4db94011d3 774 \param [in] value Value to rotate
sahilmgandhi 18:6a4db94011d3 775 \return Rotated value
sahilmgandhi 18:6a4db94011d3 776 */
sahilmgandhi 18:6a4db94011d3 777 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
sahilmgandhi 18:6a4db94011d3 778 {
sahilmgandhi 18:6a4db94011d3 779 uint32_t result;
sahilmgandhi 18:6a4db94011d3 780
sahilmgandhi 18:6a4db94011d3 781 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
sahilmgandhi 18:6a4db94011d3 782 return(result);
sahilmgandhi 18:6a4db94011d3 783 }
sahilmgandhi 18:6a4db94011d3 784
sahilmgandhi 18:6a4db94011d3 785
sahilmgandhi 18:6a4db94011d3 786 /** \brief LDRT Unprivileged (8 bit)
sahilmgandhi 18:6a4db94011d3 787
sahilmgandhi 18:6a4db94011d3 788 This function executes a Unprivileged LDRT instruction for 8 bit value.
sahilmgandhi 18:6a4db94011d3 789
sahilmgandhi 18:6a4db94011d3 790 \param [in] ptr Pointer to data
sahilmgandhi 18:6a4db94011d3 791 \return value of type uint8_t at (*ptr)
sahilmgandhi 18:6a4db94011d3 792 */
sahilmgandhi 18:6a4db94011d3 793 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
sahilmgandhi 18:6a4db94011d3 794 {
sahilmgandhi 18:6a4db94011d3 795 uint32_t result;
sahilmgandhi 18:6a4db94011d3 796
sahilmgandhi 18:6a4db94011d3 797 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
sahilmgandhi 18:6a4db94011d3 798 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
sahilmgandhi 18:6a4db94011d3 799 #else
sahilmgandhi 18:6a4db94011d3 800 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
sahilmgandhi 18:6a4db94011d3 801 accepted by assembler. So has to use following less efficient pattern.
sahilmgandhi 18:6a4db94011d3 802 */
sahilmgandhi 18:6a4db94011d3 803 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
sahilmgandhi 18:6a4db94011d3 804 #endif
sahilmgandhi 18:6a4db94011d3 805 return ((uint8_t) result); /* Add explicit type cast here */
sahilmgandhi 18:6a4db94011d3 806 }
sahilmgandhi 18:6a4db94011d3 807
sahilmgandhi 18:6a4db94011d3 808
sahilmgandhi 18:6a4db94011d3 809 /** \brief LDRT Unprivileged (16 bit)
sahilmgandhi 18:6a4db94011d3 810
sahilmgandhi 18:6a4db94011d3 811 This function executes a Unprivileged LDRT instruction for 16 bit values.
sahilmgandhi 18:6a4db94011d3 812
sahilmgandhi 18:6a4db94011d3 813 \param [in] ptr Pointer to data
sahilmgandhi 18:6a4db94011d3 814 \return value of type uint16_t at (*ptr)
sahilmgandhi 18:6a4db94011d3 815 */
sahilmgandhi 18:6a4db94011d3 816 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
sahilmgandhi 18:6a4db94011d3 817 {
sahilmgandhi 18:6a4db94011d3 818 uint32_t result;
sahilmgandhi 18:6a4db94011d3 819
sahilmgandhi 18:6a4db94011d3 820 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
sahilmgandhi 18:6a4db94011d3 821 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
sahilmgandhi 18:6a4db94011d3 822 #else
sahilmgandhi 18:6a4db94011d3 823 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
sahilmgandhi 18:6a4db94011d3 824 accepted by assembler. So has to use following less efficient pattern.
sahilmgandhi 18:6a4db94011d3 825 */
sahilmgandhi 18:6a4db94011d3 826 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
sahilmgandhi 18:6a4db94011d3 827 #endif
sahilmgandhi 18:6a4db94011d3 828 return ((uint16_t) result); /* Add explicit type cast here */
sahilmgandhi 18:6a4db94011d3 829 }
sahilmgandhi 18:6a4db94011d3 830
sahilmgandhi 18:6a4db94011d3 831
sahilmgandhi 18:6a4db94011d3 832 /** \brief LDRT Unprivileged (32 bit)
sahilmgandhi 18:6a4db94011d3 833
sahilmgandhi 18:6a4db94011d3 834 This function executes a Unprivileged LDRT instruction for 32 bit values.
sahilmgandhi 18:6a4db94011d3 835
sahilmgandhi 18:6a4db94011d3 836 \param [in] ptr Pointer to data
sahilmgandhi 18:6a4db94011d3 837 \return value of type uint32_t at (*ptr)
sahilmgandhi 18:6a4db94011d3 838 */
sahilmgandhi 18:6a4db94011d3 839 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
sahilmgandhi 18:6a4db94011d3 840 {
sahilmgandhi 18:6a4db94011d3 841 uint32_t result;
sahilmgandhi 18:6a4db94011d3 842
sahilmgandhi 18:6a4db94011d3 843 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
sahilmgandhi 18:6a4db94011d3 844 return(result);
sahilmgandhi 18:6a4db94011d3 845 }
sahilmgandhi 18:6a4db94011d3 846
sahilmgandhi 18:6a4db94011d3 847
sahilmgandhi 18:6a4db94011d3 848 /** \brief STRT Unprivileged (8 bit)
sahilmgandhi 18:6a4db94011d3 849
sahilmgandhi 18:6a4db94011d3 850 This function executes a Unprivileged STRT instruction for 8 bit values.
sahilmgandhi 18:6a4db94011d3 851
sahilmgandhi 18:6a4db94011d3 852 \param [in] value Value to store
sahilmgandhi 18:6a4db94011d3 853 \param [in] ptr Pointer to location
sahilmgandhi 18:6a4db94011d3 854 */
sahilmgandhi 18:6a4db94011d3 855 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
sahilmgandhi 18:6a4db94011d3 856 {
sahilmgandhi 18:6a4db94011d3 857 __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
sahilmgandhi 18:6a4db94011d3 858 }
sahilmgandhi 18:6a4db94011d3 859
sahilmgandhi 18:6a4db94011d3 860
sahilmgandhi 18:6a4db94011d3 861 /** \brief STRT Unprivileged (16 bit)
sahilmgandhi 18:6a4db94011d3 862
sahilmgandhi 18:6a4db94011d3 863 This function executes a Unprivileged STRT instruction for 16 bit values.
sahilmgandhi 18:6a4db94011d3 864
sahilmgandhi 18:6a4db94011d3 865 \param [in] value Value to store
sahilmgandhi 18:6a4db94011d3 866 \param [in] ptr Pointer to location
sahilmgandhi 18:6a4db94011d3 867 */
sahilmgandhi 18:6a4db94011d3 868 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
sahilmgandhi 18:6a4db94011d3 869 {
sahilmgandhi 18:6a4db94011d3 870 __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
sahilmgandhi 18:6a4db94011d3 871 }
sahilmgandhi 18:6a4db94011d3 872
sahilmgandhi 18:6a4db94011d3 873
sahilmgandhi 18:6a4db94011d3 874 /** \brief STRT Unprivileged (32 bit)
sahilmgandhi 18:6a4db94011d3 875
sahilmgandhi 18:6a4db94011d3 876 This function executes a Unprivileged STRT instruction for 32 bit values.
sahilmgandhi 18:6a4db94011d3 877
sahilmgandhi 18:6a4db94011d3 878 \param [in] value Value to store
sahilmgandhi 18:6a4db94011d3 879 \param [in] ptr Pointer to location
sahilmgandhi 18:6a4db94011d3 880 */
sahilmgandhi 18:6a4db94011d3 881 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
sahilmgandhi 18:6a4db94011d3 882 {
sahilmgandhi 18:6a4db94011d3 883 __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
sahilmgandhi 18:6a4db94011d3 884 }
sahilmgandhi 18:6a4db94011d3 885
sahilmgandhi 18:6a4db94011d3 886 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
sahilmgandhi 18:6a4db94011d3 887
sahilmgandhi 18:6a4db94011d3 888
sahilmgandhi 18:6a4db94011d3 889 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
sahilmgandhi 18:6a4db94011d3 890 /* IAR iccarm specific functions */
sahilmgandhi 18:6a4db94011d3 891 #include <cmsis_iar.h>
sahilmgandhi 18:6a4db94011d3 892
sahilmgandhi 18:6a4db94011d3 893
sahilmgandhi 18:6a4db94011d3 894 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
sahilmgandhi 18:6a4db94011d3 895 /* TI CCS specific functions */
sahilmgandhi 18:6a4db94011d3 896 #include <cmsis_ccs.h>
sahilmgandhi 18:6a4db94011d3 897
sahilmgandhi 18:6a4db94011d3 898
sahilmgandhi 18:6a4db94011d3 899 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
sahilmgandhi 18:6a4db94011d3 900 /* TASKING carm specific functions */
sahilmgandhi 18:6a4db94011d3 901 /*
sahilmgandhi 18:6a4db94011d3 902 * The CMSIS functions have been implemented as intrinsics in the compiler.
sahilmgandhi 18:6a4db94011d3 903 * Please use "carm -?i" to get an up to date list of all intrinsics,
sahilmgandhi 18:6a4db94011d3 904 * Including the CMSIS ones.
sahilmgandhi 18:6a4db94011d3 905 */
sahilmgandhi 18:6a4db94011d3 906
sahilmgandhi 18:6a4db94011d3 907
sahilmgandhi 18:6a4db94011d3 908 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
sahilmgandhi 18:6a4db94011d3 909 /* Cosmic specific functions */
sahilmgandhi 18:6a4db94011d3 910 #include <cmsis_csm.h>
sahilmgandhi 18:6a4db94011d3 911
sahilmgandhi 18:6a4db94011d3 912 #endif
sahilmgandhi 18:6a4db94011d3 913
sahilmgandhi 18:6a4db94011d3 914 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
sahilmgandhi 18:6a4db94011d3 915
sahilmgandhi 18:6a4db94011d3 916 #endif /* __CORE_CMINSTR_H */