MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/cmsis/core_cmFunc.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file core_cmFunc.h
sahilmgandhi 18:6a4db94011d3 3 * @brief CMSIS Cortex-M Core Function Access Header File
sahilmgandhi 18:6a4db94011d3 4 * @version V4.10
sahilmgandhi 18:6a4db94011d3 5 * @date 18. March 2015
sahilmgandhi 18:6a4db94011d3 6 *
sahilmgandhi 18:6a4db94011d3 7 * @note
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
sahilmgandhi 18:6a4db94011d3 11
sahilmgandhi 18:6a4db94011d3 12 All rights reserved.
sahilmgandhi 18:6a4db94011d3 13 Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 14 modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 15 - Redistributions of source code must retain the above copyright
sahilmgandhi 18:6a4db94011d3 16 notice, this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 - Redistributions in binary form must reproduce the above copyright
sahilmgandhi 18:6a4db94011d3 18 notice, this list of conditions and the following disclaimer in the
sahilmgandhi 18:6a4db94011d3 19 documentation and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 20 - Neither the name of ARM nor the names of its contributors may be used
sahilmgandhi 18:6a4db94011d3 21 to endorse or promote products derived from this software without
sahilmgandhi 18:6a4db94011d3 22 specific prior written permission.
sahilmgandhi 18:6a4db94011d3 23 *
sahilmgandhi 18:6a4db94011d3 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
sahilmgandhi 18:6a4db94011d3 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
sahilmgandhi 18:6a4db94011d3 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
sahilmgandhi 18:6a4db94011d3 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
sahilmgandhi 18:6a4db94011d3 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
sahilmgandhi 18:6a4db94011d3 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
sahilmgandhi 18:6a4db94011d3 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
sahilmgandhi 18:6a4db94011d3 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sahilmgandhi 18:6a4db94011d3 34 POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 35 ---------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 #ifndef __CORE_CMFUNC_H
sahilmgandhi 18:6a4db94011d3 39 #define __CORE_CMFUNC_H
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 /* ########################### Core Function Access ########################### */
sahilmgandhi 18:6a4db94011d3 43 /** \ingroup CMSIS_Core_FunctionInterface
sahilmgandhi 18:6a4db94011d3 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
sahilmgandhi 18:6a4db94011d3 45 @{
sahilmgandhi 18:6a4db94011d3 46 */
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
sahilmgandhi 18:6a4db94011d3 49 /* ARM armcc specific functions */
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 #if (__ARMCC_VERSION < 400677)
sahilmgandhi 18:6a4db94011d3 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
sahilmgandhi 18:6a4db94011d3 53 #endif
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 /* intrinsic void __enable_irq(); */
sahilmgandhi 18:6a4db94011d3 56 /* intrinsic void __disable_irq(); */
sahilmgandhi 18:6a4db94011d3 57
sahilmgandhi 18:6a4db94011d3 58 /** \brief Get Control Register
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 This function returns the content of the Control Register.
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62 \return Control Register value
sahilmgandhi 18:6a4db94011d3 63 */
sahilmgandhi 18:6a4db94011d3 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
sahilmgandhi 18:6a4db94011d3 65 {
sahilmgandhi 18:6a4db94011d3 66 register uint32_t __regControl __ASM("control");
sahilmgandhi 18:6a4db94011d3 67 return(__regControl);
sahilmgandhi 18:6a4db94011d3 68 }
sahilmgandhi 18:6a4db94011d3 69
sahilmgandhi 18:6a4db94011d3 70
sahilmgandhi 18:6a4db94011d3 71 /** \brief Set Control Register
sahilmgandhi 18:6a4db94011d3 72
sahilmgandhi 18:6a4db94011d3 73 This function writes the given value to the Control Register.
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 \param [in] control Control Register value to set
sahilmgandhi 18:6a4db94011d3 76 */
sahilmgandhi 18:6a4db94011d3 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
sahilmgandhi 18:6a4db94011d3 78 {
sahilmgandhi 18:6a4db94011d3 79 register uint32_t __regControl __ASM("control");
sahilmgandhi 18:6a4db94011d3 80 __regControl = control;
sahilmgandhi 18:6a4db94011d3 81 }
sahilmgandhi 18:6a4db94011d3 82
sahilmgandhi 18:6a4db94011d3 83
sahilmgandhi 18:6a4db94011d3 84 /** \brief Get IPSR Register
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 This function returns the content of the IPSR Register.
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 \return IPSR Register value
sahilmgandhi 18:6a4db94011d3 89 */
sahilmgandhi 18:6a4db94011d3 90 __STATIC_INLINE uint32_t __get_IPSR(void)
sahilmgandhi 18:6a4db94011d3 91 {
sahilmgandhi 18:6a4db94011d3 92 register uint32_t __regIPSR __ASM("ipsr");
sahilmgandhi 18:6a4db94011d3 93 return(__regIPSR);
sahilmgandhi 18:6a4db94011d3 94 }
sahilmgandhi 18:6a4db94011d3 95
sahilmgandhi 18:6a4db94011d3 96
sahilmgandhi 18:6a4db94011d3 97 /** \brief Get APSR Register
sahilmgandhi 18:6a4db94011d3 98
sahilmgandhi 18:6a4db94011d3 99 This function returns the content of the APSR Register.
sahilmgandhi 18:6a4db94011d3 100
sahilmgandhi 18:6a4db94011d3 101 \return APSR Register value
sahilmgandhi 18:6a4db94011d3 102 */
sahilmgandhi 18:6a4db94011d3 103 __STATIC_INLINE uint32_t __get_APSR(void)
sahilmgandhi 18:6a4db94011d3 104 {
sahilmgandhi 18:6a4db94011d3 105 register uint32_t __regAPSR __ASM("apsr");
sahilmgandhi 18:6a4db94011d3 106 return(__regAPSR);
sahilmgandhi 18:6a4db94011d3 107 }
sahilmgandhi 18:6a4db94011d3 108
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 /** \brief Get xPSR Register
sahilmgandhi 18:6a4db94011d3 111
sahilmgandhi 18:6a4db94011d3 112 This function returns the content of the xPSR Register.
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 \return xPSR Register value
sahilmgandhi 18:6a4db94011d3 115 */
sahilmgandhi 18:6a4db94011d3 116 __STATIC_INLINE uint32_t __get_xPSR(void)
sahilmgandhi 18:6a4db94011d3 117 {
sahilmgandhi 18:6a4db94011d3 118 register uint32_t __regXPSR __ASM("xpsr");
sahilmgandhi 18:6a4db94011d3 119 return(__regXPSR);
sahilmgandhi 18:6a4db94011d3 120 }
sahilmgandhi 18:6a4db94011d3 121
sahilmgandhi 18:6a4db94011d3 122
sahilmgandhi 18:6a4db94011d3 123 /** \brief Get Process Stack Pointer
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125 This function returns the current value of the Process Stack Pointer (PSP).
sahilmgandhi 18:6a4db94011d3 126
sahilmgandhi 18:6a4db94011d3 127 \return PSP Register value
sahilmgandhi 18:6a4db94011d3 128 */
sahilmgandhi 18:6a4db94011d3 129 __STATIC_INLINE uint32_t __get_PSP(void)
sahilmgandhi 18:6a4db94011d3 130 {
sahilmgandhi 18:6a4db94011d3 131 register uint32_t __regProcessStackPointer __ASM("psp");
sahilmgandhi 18:6a4db94011d3 132 return(__regProcessStackPointer);
sahilmgandhi 18:6a4db94011d3 133 }
sahilmgandhi 18:6a4db94011d3 134
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 /** \brief Set Process Stack Pointer
sahilmgandhi 18:6a4db94011d3 137
sahilmgandhi 18:6a4db94011d3 138 This function assigns the given value to the Process Stack Pointer (PSP).
sahilmgandhi 18:6a4db94011d3 139
sahilmgandhi 18:6a4db94011d3 140 \param [in] topOfProcStack Process Stack Pointer value to set
sahilmgandhi 18:6a4db94011d3 141 */
sahilmgandhi 18:6a4db94011d3 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
sahilmgandhi 18:6a4db94011d3 143 {
sahilmgandhi 18:6a4db94011d3 144 register uint32_t __regProcessStackPointer __ASM("psp");
sahilmgandhi 18:6a4db94011d3 145 __regProcessStackPointer = topOfProcStack;
sahilmgandhi 18:6a4db94011d3 146 }
sahilmgandhi 18:6a4db94011d3 147
sahilmgandhi 18:6a4db94011d3 148
sahilmgandhi 18:6a4db94011d3 149 /** \brief Get Main Stack Pointer
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151 This function returns the current value of the Main Stack Pointer (MSP).
sahilmgandhi 18:6a4db94011d3 152
sahilmgandhi 18:6a4db94011d3 153 \return MSP Register value
sahilmgandhi 18:6a4db94011d3 154 */
sahilmgandhi 18:6a4db94011d3 155 __STATIC_INLINE uint32_t __get_MSP(void)
sahilmgandhi 18:6a4db94011d3 156 {
sahilmgandhi 18:6a4db94011d3 157 register uint32_t __regMainStackPointer __ASM("msp");
sahilmgandhi 18:6a4db94011d3 158 return(__regMainStackPointer);
sahilmgandhi 18:6a4db94011d3 159 }
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161
sahilmgandhi 18:6a4db94011d3 162 /** \brief Set Main Stack Pointer
sahilmgandhi 18:6a4db94011d3 163
sahilmgandhi 18:6a4db94011d3 164 This function assigns the given value to the Main Stack Pointer (MSP).
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 \param [in] topOfMainStack Main Stack Pointer value to set
sahilmgandhi 18:6a4db94011d3 167 */
sahilmgandhi 18:6a4db94011d3 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
sahilmgandhi 18:6a4db94011d3 169 {
sahilmgandhi 18:6a4db94011d3 170 register uint32_t __regMainStackPointer __ASM("msp");
sahilmgandhi 18:6a4db94011d3 171 __regMainStackPointer = topOfMainStack;
sahilmgandhi 18:6a4db94011d3 172 }
sahilmgandhi 18:6a4db94011d3 173
sahilmgandhi 18:6a4db94011d3 174
sahilmgandhi 18:6a4db94011d3 175 /** \brief Get Priority Mask
sahilmgandhi 18:6a4db94011d3 176
sahilmgandhi 18:6a4db94011d3 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
sahilmgandhi 18:6a4db94011d3 178
sahilmgandhi 18:6a4db94011d3 179 \return Priority Mask value
sahilmgandhi 18:6a4db94011d3 180 */
sahilmgandhi 18:6a4db94011d3 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
sahilmgandhi 18:6a4db94011d3 182 {
sahilmgandhi 18:6a4db94011d3 183 register uint32_t __regPriMask __ASM("primask");
sahilmgandhi 18:6a4db94011d3 184 return(__regPriMask);
sahilmgandhi 18:6a4db94011d3 185 }
sahilmgandhi 18:6a4db94011d3 186
sahilmgandhi 18:6a4db94011d3 187
sahilmgandhi 18:6a4db94011d3 188 /** \brief Set Priority Mask
sahilmgandhi 18:6a4db94011d3 189
sahilmgandhi 18:6a4db94011d3 190 This function assigns the given value to the Priority Mask Register.
sahilmgandhi 18:6a4db94011d3 191
sahilmgandhi 18:6a4db94011d3 192 \param [in] priMask Priority Mask
sahilmgandhi 18:6a4db94011d3 193 */
sahilmgandhi 18:6a4db94011d3 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
sahilmgandhi 18:6a4db94011d3 195 {
sahilmgandhi 18:6a4db94011d3 196 register uint32_t __regPriMask __ASM("primask");
sahilmgandhi 18:6a4db94011d3 197 __regPriMask = (priMask);
sahilmgandhi 18:6a4db94011d3 198 }
sahilmgandhi 18:6a4db94011d3 199
sahilmgandhi 18:6a4db94011d3 200
sahilmgandhi 18:6a4db94011d3 201 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
sahilmgandhi 18:6a4db94011d3 202
sahilmgandhi 18:6a4db94011d3 203 /** \brief Enable FIQ
sahilmgandhi 18:6a4db94011d3 204
sahilmgandhi 18:6a4db94011d3 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
sahilmgandhi 18:6a4db94011d3 206 Can only be executed in Privileged modes.
sahilmgandhi 18:6a4db94011d3 207 */
sahilmgandhi 18:6a4db94011d3 208 #define __enable_fault_irq __enable_fiq
sahilmgandhi 18:6a4db94011d3 209
sahilmgandhi 18:6a4db94011d3 210
sahilmgandhi 18:6a4db94011d3 211 /** \brief Disable FIQ
sahilmgandhi 18:6a4db94011d3 212
sahilmgandhi 18:6a4db94011d3 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
sahilmgandhi 18:6a4db94011d3 214 Can only be executed in Privileged modes.
sahilmgandhi 18:6a4db94011d3 215 */
sahilmgandhi 18:6a4db94011d3 216 #define __disable_fault_irq __disable_fiq
sahilmgandhi 18:6a4db94011d3 217
sahilmgandhi 18:6a4db94011d3 218
sahilmgandhi 18:6a4db94011d3 219 /** \brief Get Base Priority
sahilmgandhi 18:6a4db94011d3 220
sahilmgandhi 18:6a4db94011d3 221 This function returns the current value of the Base Priority register.
sahilmgandhi 18:6a4db94011d3 222
sahilmgandhi 18:6a4db94011d3 223 \return Base Priority register value
sahilmgandhi 18:6a4db94011d3 224 */
sahilmgandhi 18:6a4db94011d3 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
sahilmgandhi 18:6a4db94011d3 226 {
sahilmgandhi 18:6a4db94011d3 227 register uint32_t __regBasePri __ASM("basepri");
sahilmgandhi 18:6a4db94011d3 228 return(__regBasePri);
sahilmgandhi 18:6a4db94011d3 229 }
sahilmgandhi 18:6a4db94011d3 230
sahilmgandhi 18:6a4db94011d3 231
sahilmgandhi 18:6a4db94011d3 232 /** \brief Set Base Priority
sahilmgandhi 18:6a4db94011d3 233
sahilmgandhi 18:6a4db94011d3 234 This function assigns the given value to the Base Priority register.
sahilmgandhi 18:6a4db94011d3 235
sahilmgandhi 18:6a4db94011d3 236 \param [in] basePri Base Priority value to set
sahilmgandhi 18:6a4db94011d3 237 */
sahilmgandhi 18:6a4db94011d3 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
sahilmgandhi 18:6a4db94011d3 239 {
sahilmgandhi 18:6a4db94011d3 240 register uint32_t __regBasePri __ASM("basepri");
sahilmgandhi 18:6a4db94011d3 241 __regBasePri = (basePri & 0xff);
sahilmgandhi 18:6a4db94011d3 242 }
sahilmgandhi 18:6a4db94011d3 243
sahilmgandhi 18:6a4db94011d3 244
sahilmgandhi 18:6a4db94011d3 245 /** \brief Set Base Priority with condition
sahilmgandhi 18:6a4db94011d3 246
sahilmgandhi 18:6a4db94011d3 247 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
sahilmgandhi 18:6a4db94011d3 248 or the new value increases the BASEPRI priority level.
sahilmgandhi 18:6a4db94011d3 249
sahilmgandhi 18:6a4db94011d3 250 \param [in] basePri Base Priority value to set
sahilmgandhi 18:6a4db94011d3 251 */
sahilmgandhi 18:6a4db94011d3 252 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
sahilmgandhi 18:6a4db94011d3 253 {
sahilmgandhi 18:6a4db94011d3 254 register uint32_t __regBasePriMax __ASM("basepri_max");
sahilmgandhi 18:6a4db94011d3 255 __regBasePriMax = (basePri & 0xff);
sahilmgandhi 18:6a4db94011d3 256 }
sahilmgandhi 18:6a4db94011d3 257
sahilmgandhi 18:6a4db94011d3 258
sahilmgandhi 18:6a4db94011d3 259 /** \brief Get Fault Mask
sahilmgandhi 18:6a4db94011d3 260
sahilmgandhi 18:6a4db94011d3 261 This function returns the current value of the Fault Mask register.
sahilmgandhi 18:6a4db94011d3 262
sahilmgandhi 18:6a4db94011d3 263 \return Fault Mask register value
sahilmgandhi 18:6a4db94011d3 264 */
sahilmgandhi 18:6a4db94011d3 265 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
sahilmgandhi 18:6a4db94011d3 266 {
sahilmgandhi 18:6a4db94011d3 267 register uint32_t __regFaultMask __ASM("faultmask");
sahilmgandhi 18:6a4db94011d3 268 return(__regFaultMask);
sahilmgandhi 18:6a4db94011d3 269 }
sahilmgandhi 18:6a4db94011d3 270
sahilmgandhi 18:6a4db94011d3 271
sahilmgandhi 18:6a4db94011d3 272 /** \brief Set Fault Mask
sahilmgandhi 18:6a4db94011d3 273
sahilmgandhi 18:6a4db94011d3 274 This function assigns the given value to the Fault Mask register.
sahilmgandhi 18:6a4db94011d3 275
sahilmgandhi 18:6a4db94011d3 276 \param [in] faultMask Fault Mask value to set
sahilmgandhi 18:6a4db94011d3 277 */
sahilmgandhi 18:6a4db94011d3 278 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
sahilmgandhi 18:6a4db94011d3 279 {
sahilmgandhi 18:6a4db94011d3 280 register uint32_t __regFaultMask __ASM("faultmask");
sahilmgandhi 18:6a4db94011d3 281 __regFaultMask = (faultMask & (uint32_t)1);
sahilmgandhi 18:6a4db94011d3 282 }
sahilmgandhi 18:6a4db94011d3 283
sahilmgandhi 18:6a4db94011d3 284 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
sahilmgandhi 18:6a4db94011d3 285
sahilmgandhi 18:6a4db94011d3 286
sahilmgandhi 18:6a4db94011d3 287 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
sahilmgandhi 18:6a4db94011d3 288
sahilmgandhi 18:6a4db94011d3 289 /** \brief Get FPSCR
sahilmgandhi 18:6a4db94011d3 290
sahilmgandhi 18:6a4db94011d3 291 This function returns the current value of the Floating Point Status/Control register.
sahilmgandhi 18:6a4db94011d3 292
sahilmgandhi 18:6a4db94011d3 293 \return Floating Point Status/Control register value
sahilmgandhi 18:6a4db94011d3 294 */
sahilmgandhi 18:6a4db94011d3 295 __STATIC_INLINE uint32_t __get_FPSCR(void)
sahilmgandhi 18:6a4db94011d3 296 {
sahilmgandhi 18:6a4db94011d3 297 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
sahilmgandhi 18:6a4db94011d3 298 register uint32_t __regfpscr __ASM("fpscr");
sahilmgandhi 18:6a4db94011d3 299 return(__regfpscr);
sahilmgandhi 18:6a4db94011d3 300 #else
sahilmgandhi 18:6a4db94011d3 301 return(0);
sahilmgandhi 18:6a4db94011d3 302 #endif
sahilmgandhi 18:6a4db94011d3 303 }
sahilmgandhi 18:6a4db94011d3 304
sahilmgandhi 18:6a4db94011d3 305
sahilmgandhi 18:6a4db94011d3 306 /** \brief Set FPSCR
sahilmgandhi 18:6a4db94011d3 307
sahilmgandhi 18:6a4db94011d3 308 This function assigns the given value to the Floating Point Status/Control register.
sahilmgandhi 18:6a4db94011d3 309
sahilmgandhi 18:6a4db94011d3 310 \param [in] fpscr Floating Point Status/Control value to set
sahilmgandhi 18:6a4db94011d3 311 */
sahilmgandhi 18:6a4db94011d3 312 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
sahilmgandhi 18:6a4db94011d3 313 {
sahilmgandhi 18:6a4db94011d3 314 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
sahilmgandhi 18:6a4db94011d3 315 register uint32_t __regfpscr __ASM("fpscr");
sahilmgandhi 18:6a4db94011d3 316 __regfpscr = (fpscr);
sahilmgandhi 18:6a4db94011d3 317 #endif
sahilmgandhi 18:6a4db94011d3 318 }
sahilmgandhi 18:6a4db94011d3 319
sahilmgandhi 18:6a4db94011d3 320 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
sahilmgandhi 18:6a4db94011d3 321
sahilmgandhi 18:6a4db94011d3 322
sahilmgandhi 18:6a4db94011d3 323 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
sahilmgandhi 18:6a4db94011d3 324 /* GNU gcc specific functions */
sahilmgandhi 18:6a4db94011d3 325
sahilmgandhi 18:6a4db94011d3 326 /** \brief Enable IRQ Interrupts
sahilmgandhi 18:6a4db94011d3 327
sahilmgandhi 18:6a4db94011d3 328 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
sahilmgandhi 18:6a4db94011d3 329 Can only be executed in Privileged modes.
sahilmgandhi 18:6a4db94011d3 330 */
sahilmgandhi 18:6a4db94011d3 331 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
sahilmgandhi 18:6a4db94011d3 332 {
sahilmgandhi 18:6a4db94011d3 333 __ASM volatile ("cpsie i" : : : "memory");
sahilmgandhi 18:6a4db94011d3 334 }
sahilmgandhi 18:6a4db94011d3 335
sahilmgandhi 18:6a4db94011d3 336
sahilmgandhi 18:6a4db94011d3 337 /** \brief Disable IRQ Interrupts
sahilmgandhi 18:6a4db94011d3 338
sahilmgandhi 18:6a4db94011d3 339 This function disables IRQ interrupts by setting the I-bit in the CPSR.
sahilmgandhi 18:6a4db94011d3 340 Can only be executed in Privileged modes.
sahilmgandhi 18:6a4db94011d3 341 */
sahilmgandhi 18:6a4db94011d3 342 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
sahilmgandhi 18:6a4db94011d3 343 {
sahilmgandhi 18:6a4db94011d3 344 __ASM volatile ("cpsid i" : : : "memory");
sahilmgandhi 18:6a4db94011d3 345 }
sahilmgandhi 18:6a4db94011d3 346
sahilmgandhi 18:6a4db94011d3 347
sahilmgandhi 18:6a4db94011d3 348 /** \brief Get Control Register
sahilmgandhi 18:6a4db94011d3 349
sahilmgandhi 18:6a4db94011d3 350 This function returns the content of the Control Register.
sahilmgandhi 18:6a4db94011d3 351
sahilmgandhi 18:6a4db94011d3 352 \return Control Register value
sahilmgandhi 18:6a4db94011d3 353 */
sahilmgandhi 18:6a4db94011d3 354 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
sahilmgandhi 18:6a4db94011d3 355 {
sahilmgandhi 18:6a4db94011d3 356 uint32_t result;
sahilmgandhi 18:6a4db94011d3 357
sahilmgandhi 18:6a4db94011d3 358 __ASM volatile ("MRS %0, control" : "=r" (result) );
sahilmgandhi 18:6a4db94011d3 359 return(result);
sahilmgandhi 18:6a4db94011d3 360 }
sahilmgandhi 18:6a4db94011d3 361
sahilmgandhi 18:6a4db94011d3 362
sahilmgandhi 18:6a4db94011d3 363 /** \brief Set Control Register
sahilmgandhi 18:6a4db94011d3 364
sahilmgandhi 18:6a4db94011d3 365 This function writes the given value to the Control Register.
sahilmgandhi 18:6a4db94011d3 366
sahilmgandhi 18:6a4db94011d3 367 \param [in] control Control Register value to set
sahilmgandhi 18:6a4db94011d3 368 */
sahilmgandhi 18:6a4db94011d3 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
sahilmgandhi 18:6a4db94011d3 370 {
sahilmgandhi 18:6a4db94011d3 371 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
sahilmgandhi 18:6a4db94011d3 372 }
sahilmgandhi 18:6a4db94011d3 373
sahilmgandhi 18:6a4db94011d3 374
sahilmgandhi 18:6a4db94011d3 375 /** \brief Get IPSR Register
sahilmgandhi 18:6a4db94011d3 376
sahilmgandhi 18:6a4db94011d3 377 This function returns the content of the IPSR Register.
sahilmgandhi 18:6a4db94011d3 378
sahilmgandhi 18:6a4db94011d3 379 \return IPSR Register value
sahilmgandhi 18:6a4db94011d3 380 */
sahilmgandhi 18:6a4db94011d3 381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
sahilmgandhi 18:6a4db94011d3 382 {
sahilmgandhi 18:6a4db94011d3 383 uint32_t result;
sahilmgandhi 18:6a4db94011d3 384
sahilmgandhi 18:6a4db94011d3 385 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
sahilmgandhi 18:6a4db94011d3 386 return(result);
sahilmgandhi 18:6a4db94011d3 387 }
sahilmgandhi 18:6a4db94011d3 388
sahilmgandhi 18:6a4db94011d3 389
sahilmgandhi 18:6a4db94011d3 390 /** \brief Get APSR Register
sahilmgandhi 18:6a4db94011d3 391
sahilmgandhi 18:6a4db94011d3 392 This function returns the content of the APSR Register.
sahilmgandhi 18:6a4db94011d3 393
sahilmgandhi 18:6a4db94011d3 394 \return APSR Register value
sahilmgandhi 18:6a4db94011d3 395 */
sahilmgandhi 18:6a4db94011d3 396 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
sahilmgandhi 18:6a4db94011d3 397 {
sahilmgandhi 18:6a4db94011d3 398 uint32_t result;
sahilmgandhi 18:6a4db94011d3 399
sahilmgandhi 18:6a4db94011d3 400 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
sahilmgandhi 18:6a4db94011d3 401 return(result);
sahilmgandhi 18:6a4db94011d3 402 }
sahilmgandhi 18:6a4db94011d3 403
sahilmgandhi 18:6a4db94011d3 404
sahilmgandhi 18:6a4db94011d3 405 /** \brief Get xPSR Register
sahilmgandhi 18:6a4db94011d3 406
sahilmgandhi 18:6a4db94011d3 407 This function returns the content of the xPSR Register.
sahilmgandhi 18:6a4db94011d3 408
sahilmgandhi 18:6a4db94011d3 409 \return xPSR Register value
sahilmgandhi 18:6a4db94011d3 410 */
sahilmgandhi 18:6a4db94011d3 411 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
sahilmgandhi 18:6a4db94011d3 412 {
sahilmgandhi 18:6a4db94011d3 413 uint32_t result;
sahilmgandhi 18:6a4db94011d3 414
sahilmgandhi 18:6a4db94011d3 415 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
sahilmgandhi 18:6a4db94011d3 416 return(result);
sahilmgandhi 18:6a4db94011d3 417 }
sahilmgandhi 18:6a4db94011d3 418
sahilmgandhi 18:6a4db94011d3 419
sahilmgandhi 18:6a4db94011d3 420 /** \brief Get Process Stack Pointer
sahilmgandhi 18:6a4db94011d3 421
sahilmgandhi 18:6a4db94011d3 422 This function returns the current value of the Process Stack Pointer (PSP).
sahilmgandhi 18:6a4db94011d3 423
sahilmgandhi 18:6a4db94011d3 424 \return PSP Register value
sahilmgandhi 18:6a4db94011d3 425 */
sahilmgandhi 18:6a4db94011d3 426 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
sahilmgandhi 18:6a4db94011d3 427 {
sahilmgandhi 18:6a4db94011d3 428 register uint32_t result;
sahilmgandhi 18:6a4db94011d3 429
sahilmgandhi 18:6a4db94011d3 430 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
sahilmgandhi 18:6a4db94011d3 431 return(result);
sahilmgandhi 18:6a4db94011d3 432 }
sahilmgandhi 18:6a4db94011d3 433
sahilmgandhi 18:6a4db94011d3 434
sahilmgandhi 18:6a4db94011d3 435 /** \brief Set Process Stack Pointer
sahilmgandhi 18:6a4db94011d3 436
sahilmgandhi 18:6a4db94011d3 437 This function assigns the given value to the Process Stack Pointer (PSP).
sahilmgandhi 18:6a4db94011d3 438
sahilmgandhi 18:6a4db94011d3 439 \param [in] topOfProcStack Process Stack Pointer value to set
sahilmgandhi 18:6a4db94011d3 440 */
sahilmgandhi 18:6a4db94011d3 441 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
sahilmgandhi 18:6a4db94011d3 442 {
sahilmgandhi 18:6a4db94011d3 443 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
sahilmgandhi 18:6a4db94011d3 444 }
sahilmgandhi 18:6a4db94011d3 445
sahilmgandhi 18:6a4db94011d3 446
sahilmgandhi 18:6a4db94011d3 447 /** \brief Get Main Stack Pointer
sahilmgandhi 18:6a4db94011d3 448
sahilmgandhi 18:6a4db94011d3 449 This function returns the current value of the Main Stack Pointer (MSP).
sahilmgandhi 18:6a4db94011d3 450
sahilmgandhi 18:6a4db94011d3 451 \return MSP Register value
sahilmgandhi 18:6a4db94011d3 452 */
sahilmgandhi 18:6a4db94011d3 453 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
sahilmgandhi 18:6a4db94011d3 454 {
sahilmgandhi 18:6a4db94011d3 455 register uint32_t result;
sahilmgandhi 18:6a4db94011d3 456
sahilmgandhi 18:6a4db94011d3 457 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
sahilmgandhi 18:6a4db94011d3 458 return(result);
sahilmgandhi 18:6a4db94011d3 459 }
sahilmgandhi 18:6a4db94011d3 460
sahilmgandhi 18:6a4db94011d3 461
sahilmgandhi 18:6a4db94011d3 462 /** \brief Set Main Stack Pointer
sahilmgandhi 18:6a4db94011d3 463
sahilmgandhi 18:6a4db94011d3 464 This function assigns the given value to the Main Stack Pointer (MSP).
sahilmgandhi 18:6a4db94011d3 465
sahilmgandhi 18:6a4db94011d3 466 \param [in] topOfMainStack Main Stack Pointer value to set
sahilmgandhi 18:6a4db94011d3 467 */
sahilmgandhi 18:6a4db94011d3 468 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
sahilmgandhi 18:6a4db94011d3 469 {
sahilmgandhi 18:6a4db94011d3 470 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
sahilmgandhi 18:6a4db94011d3 471 }
sahilmgandhi 18:6a4db94011d3 472
sahilmgandhi 18:6a4db94011d3 473
sahilmgandhi 18:6a4db94011d3 474 /** \brief Get Priority Mask
sahilmgandhi 18:6a4db94011d3 475
sahilmgandhi 18:6a4db94011d3 476 This function returns the current state of the priority mask bit from the Priority Mask Register.
sahilmgandhi 18:6a4db94011d3 477
sahilmgandhi 18:6a4db94011d3 478 \return Priority Mask value
sahilmgandhi 18:6a4db94011d3 479 */
sahilmgandhi 18:6a4db94011d3 480 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
sahilmgandhi 18:6a4db94011d3 481 {
sahilmgandhi 18:6a4db94011d3 482 uint32_t result;
sahilmgandhi 18:6a4db94011d3 483
sahilmgandhi 18:6a4db94011d3 484 __ASM volatile ("MRS %0, primask" : "=r" (result) );
sahilmgandhi 18:6a4db94011d3 485 return(result);
sahilmgandhi 18:6a4db94011d3 486 }
sahilmgandhi 18:6a4db94011d3 487
sahilmgandhi 18:6a4db94011d3 488
sahilmgandhi 18:6a4db94011d3 489 /** \brief Set Priority Mask
sahilmgandhi 18:6a4db94011d3 490
sahilmgandhi 18:6a4db94011d3 491 This function assigns the given value to the Priority Mask Register.
sahilmgandhi 18:6a4db94011d3 492
sahilmgandhi 18:6a4db94011d3 493 \param [in] priMask Priority Mask
sahilmgandhi 18:6a4db94011d3 494 */
sahilmgandhi 18:6a4db94011d3 495 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
sahilmgandhi 18:6a4db94011d3 496 {
sahilmgandhi 18:6a4db94011d3 497 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
sahilmgandhi 18:6a4db94011d3 498 }
sahilmgandhi 18:6a4db94011d3 499
sahilmgandhi 18:6a4db94011d3 500
sahilmgandhi 18:6a4db94011d3 501 #if (__CORTEX_M >= 0x03)
sahilmgandhi 18:6a4db94011d3 502
sahilmgandhi 18:6a4db94011d3 503 /** \brief Enable FIQ
sahilmgandhi 18:6a4db94011d3 504
sahilmgandhi 18:6a4db94011d3 505 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
sahilmgandhi 18:6a4db94011d3 506 Can only be executed in Privileged modes.
sahilmgandhi 18:6a4db94011d3 507 */
sahilmgandhi 18:6a4db94011d3 508 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
sahilmgandhi 18:6a4db94011d3 509 {
sahilmgandhi 18:6a4db94011d3 510 __ASM volatile ("cpsie f" : : : "memory");
sahilmgandhi 18:6a4db94011d3 511 }
sahilmgandhi 18:6a4db94011d3 512
sahilmgandhi 18:6a4db94011d3 513
sahilmgandhi 18:6a4db94011d3 514 /** \brief Disable FIQ
sahilmgandhi 18:6a4db94011d3 515
sahilmgandhi 18:6a4db94011d3 516 This function disables FIQ interrupts by setting the F-bit in the CPSR.
sahilmgandhi 18:6a4db94011d3 517 Can only be executed in Privileged modes.
sahilmgandhi 18:6a4db94011d3 518 */
sahilmgandhi 18:6a4db94011d3 519 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
sahilmgandhi 18:6a4db94011d3 520 {
sahilmgandhi 18:6a4db94011d3 521 __ASM volatile ("cpsid f" : : : "memory");
sahilmgandhi 18:6a4db94011d3 522 }
sahilmgandhi 18:6a4db94011d3 523
sahilmgandhi 18:6a4db94011d3 524
sahilmgandhi 18:6a4db94011d3 525 /** \brief Get Base Priority
sahilmgandhi 18:6a4db94011d3 526
sahilmgandhi 18:6a4db94011d3 527 This function returns the current value of the Base Priority register.
sahilmgandhi 18:6a4db94011d3 528
sahilmgandhi 18:6a4db94011d3 529 \return Base Priority register value
sahilmgandhi 18:6a4db94011d3 530 */
sahilmgandhi 18:6a4db94011d3 531 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
sahilmgandhi 18:6a4db94011d3 532 {
sahilmgandhi 18:6a4db94011d3 533 uint32_t result;
sahilmgandhi 18:6a4db94011d3 534
sahilmgandhi 18:6a4db94011d3 535 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
sahilmgandhi 18:6a4db94011d3 536 return(result);
sahilmgandhi 18:6a4db94011d3 537 }
sahilmgandhi 18:6a4db94011d3 538
sahilmgandhi 18:6a4db94011d3 539
sahilmgandhi 18:6a4db94011d3 540 /** \brief Set Base Priority
sahilmgandhi 18:6a4db94011d3 541
sahilmgandhi 18:6a4db94011d3 542 This function assigns the given value to the Base Priority register.
sahilmgandhi 18:6a4db94011d3 543
sahilmgandhi 18:6a4db94011d3 544 \param [in] basePri Base Priority value to set
sahilmgandhi 18:6a4db94011d3 545 */
sahilmgandhi 18:6a4db94011d3 546 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
sahilmgandhi 18:6a4db94011d3 547 {
sahilmgandhi 18:6a4db94011d3 548 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
sahilmgandhi 18:6a4db94011d3 549 }
sahilmgandhi 18:6a4db94011d3 550
sahilmgandhi 18:6a4db94011d3 551
sahilmgandhi 18:6a4db94011d3 552 /** \brief Set Base Priority with condition
sahilmgandhi 18:6a4db94011d3 553
sahilmgandhi 18:6a4db94011d3 554 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
sahilmgandhi 18:6a4db94011d3 555 or the new value increases the BASEPRI priority level.
sahilmgandhi 18:6a4db94011d3 556
sahilmgandhi 18:6a4db94011d3 557 \param [in] basePri Base Priority value to set
sahilmgandhi 18:6a4db94011d3 558 */
sahilmgandhi 18:6a4db94011d3 559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
sahilmgandhi 18:6a4db94011d3 560 {
sahilmgandhi 18:6a4db94011d3 561 __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
sahilmgandhi 18:6a4db94011d3 562 }
sahilmgandhi 18:6a4db94011d3 563
sahilmgandhi 18:6a4db94011d3 564
sahilmgandhi 18:6a4db94011d3 565 /** \brief Get Fault Mask
sahilmgandhi 18:6a4db94011d3 566
sahilmgandhi 18:6a4db94011d3 567 This function returns the current value of the Fault Mask register.
sahilmgandhi 18:6a4db94011d3 568
sahilmgandhi 18:6a4db94011d3 569 \return Fault Mask register value
sahilmgandhi 18:6a4db94011d3 570 */
sahilmgandhi 18:6a4db94011d3 571 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
sahilmgandhi 18:6a4db94011d3 572 {
sahilmgandhi 18:6a4db94011d3 573 uint32_t result;
sahilmgandhi 18:6a4db94011d3 574
sahilmgandhi 18:6a4db94011d3 575 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
sahilmgandhi 18:6a4db94011d3 576 return(result);
sahilmgandhi 18:6a4db94011d3 577 }
sahilmgandhi 18:6a4db94011d3 578
sahilmgandhi 18:6a4db94011d3 579
sahilmgandhi 18:6a4db94011d3 580 /** \brief Set Fault Mask
sahilmgandhi 18:6a4db94011d3 581
sahilmgandhi 18:6a4db94011d3 582 This function assigns the given value to the Fault Mask register.
sahilmgandhi 18:6a4db94011d3 583
sahilmgandhi 18:6a4db94011d3 584 \param [in] faultMask Fault Mask value to set
sahilmgandhi 18:6a4db94011d3 585 */
sahilmgandhi 18:6a4db94011d3 586 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
sahilmgandhi 18:6a4db94011d3 587 {
sahilmgandhi 18:6a4db94011d3 588 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
sahilmgandhi 18:6a4db94011d3 589 }
sahilmgandhi 18:6a4db94011d3 590
sahilmgandhi 18:6a4db94011d3 591 #endif /* (__CORTEX_M >= 0x03) */
sahilmgandhi 18:6a4db94011d3 592
sahilmgandhi 18:6a4db94011d3 593
sahilmgandhi 18:6a4db94011d3 594 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
sahilmgandhi 18:6a4db94011d3 595
sahilmgandhi 18:6a4db94011d3 596 /** \brief Get FPSCR
sahilmgandhi 18:6a4db94011d3 597
sahilmgandhi 18:6a4db94011d3 598 This function returns the current value of the Floating Point Status/Control register.
sahilmgandhi 18:6a4db94011d3 599
sahilmgandhi 18:6a4db94011d3 600 \return Floating Point Status/Control register value
sahilmgandhi 18:6a4db94011d3 601 */
sahilmgandhi 18:6a4db94011d3 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
sahilmgandhi 18:6a4db94011d3 603 {
sahilmgandhi 18:6a4db94011d3 604 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
sahilmgandhi 18:6a4db94011d3 605 uint32_t result;
sahilmgandhi 18:6a4db94011d3 606
sahilmgandhi 18:6a4db94011d3 607 /* Empty asm statement works as a scheduling barrier */
sahilmgandhi 18:6a4db94011d3 608 __ASM volatile ("");
sahilmgandhi 18:6a4db94011d3 609 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
sahilmgandhi 18:6a4db94011d3 610 __ASM volatile ("");
sahilmgandhi 18:6a4db94011d3 611 return(result);
sahilmgandhi 18:6a4db94011d3 612 #else
sahilmgandhi 18:6a4db94011d3 613 return(0);
sahilmgandhi 18:6a4db94011d3 614 #endif
sahilmgandhi 18:6a4db94011d3 615 }
sahilmgandhi 18:6a4db94011d3 616
sahilmgandhi 18:6a4db94011d3 617
sahilmgandhi 18:6a4db94011d3 618 /** \brief Set FPSCR
sahilmgandhi 18:6a4db94011d3 619
sahilmgandhi 18:6a4db94011d3 620 This function assigns the given value to the Floating Point Status/Control register.
sahilmgandhi 18:6a4db94011d3 621
sahilmgandhi 18:6a4db94011d3 622 \param [in] fpscr Floating Point Status/Control value to set
sahilmgandhi 18:6a4db94011d3 623 */
sahilmgandhi 18:6a4db94011d3 624 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
sahilmgandhi 18:6a4db94011d3 625 {
sahilmgandhi 18:6a4db94011d3 626 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
sahilmgandhi 18:6a4db94011d3 627 /* Empty asm statement works as a scheduling barrier */
sahilmgandhi 18:6a4db94011d3 628 __ASM volatile ("");
sahilmgandhi 18:6a4db94011d3 629 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
sahilmgandhi 18:6a4db94011d3 630 __ASM volatile ("");
sahilmgandhi 18:6a4db94011d3 631 #endif
sahilmgandhi 18:6a4db94011d3 632 }
sahilmgandhi 18:6a4db94011d3 633
sahilmgandhi 18:6a4db94011d3 634 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
sahilmgandhi 18:6a4db94011d3 635
sahilmgandhi 18:6a4db94011d3 636
sahilmgandhi 18:6a4db94011d3 637 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
sahilmgandhi 18:6a4db94011d3 638 /* IAR iccarm specific functions */
sahilmgandhi 18:6a4db94011d3 639 #include <cmsis_iar.h>
sahilmgandhi 18:6a4db94011d3 640
sahilmgandhi 18:6a4db94011d3 641
sahilmgandhi 18:6a4db94011d3 642 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
sahilmgandhi 18:6a4db94011d3 643 /* TI CCS specific functions */
sahilmgandhi 18:6a4db94011d3 644 #include <cmsis_ccs.h>
sahilmgandhi 18:6a4db94011d3 645
sahilmgandhi 18:6a4db94011d3 646
sahilmgandhi 18:6a4db94011d3 647 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
sahilmgandhi 18:6a4db94011d3 648 /* TASKING carm specific functions */
sahilmgandhi 18:6a4db94011d3 649 /*
sahilmgandhi 18:6a4db94011d3 650 * The CMSIS functions have been implemented as intrinsics in the compiler.
sahilmgandhi 18:6a4db94011d3 651 * Please use "carm -?i" to get an up to date list of all intrinsics,
sahilmgandhi 18:6a4db94011d3 652 * Including the CMSIS ones.
sahilmgandhi 18:6a4db94011d3 653 */
sahilmgandhi 18:6a4db94011d3 654
sahilmgandhi 18:6a4db94011d3 655
sahilmgandhi 18:6a4db94011d3 656 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
sahilmgandhi 18:6a4db94011d3 657 /* Cosmic specific functions */
sahilmgandhi 18:6a4db94011d3 658 #include <cmsis_csm.h>
sahilmgandhi 18:6a4db94011d3 659
sahilmgandhi 18:6a4db94011d3 660 #endif
sahilmgandhi 18:6a4db94011d3 661
sahilmgandhi 18:6a4db94011d3 662 /*@} end of CMSIS_Core_RegAccFunctions */
sahilmgandhi 18:6a4db94011d3 663
sahilmgandhi 18:6a4db94011d3 664 #endif /* __CORE_CMFUNC_H */