MouseCode - Mouse code for the MacroRat

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Mouse code for the MacroRat

Dependencies: ITG3200 QEI

mbed-dev/cmsis/core_cm7.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:: sahilmgandhi
Date:: Sat Jun 03 00:22:44 2017 +0000
Revision:: 46:b156ef445742
Parent:: 18:6a4db94011d3

Final code for internal battlebot competition.

Who changed what in which revision?

User	Revision	Line number	New contents of line
sahilmgandhi	18:6a4db94011d3	1	/************************************************************************//
sahilmgandhi	18:6a4db94011d3	2	* @file core_cm7.h
sahilmgandhi	18:6a4db94011d3	3	* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
sahilmgandhi	18:6a4db94011d3	4	* @version V4.10
sahilmgandhi	18:6a4db94011d3	5	* @date 18. March 2015
sahilmgandhi	18:6a4db94011d3	6	*
sahilmgandhi	18:6a4db94011d3	7	* @note
sahilmgandhi	18:6a4db94011d3	8	*
sahilmgandhi	18:6a4db94011d3	9	******************************************************************************/
sahilmgandhi	18:6a4db94011d3	10	/* Copyright (c) 2009 - 2015 ARM LIMITED
sahilmgandhi	18:6a4db94011d3	11
sahilmgandhi	18:6a4db94011d3	12	All rights reserved.
sahilmgandhi	18:6a4db94011d3	13	Redistribution and use in source and binary forms, with or without
sahilmgandhi	18:6a4db94011d3	14	modification, are permitted provided that the following conditions are met:
sahilmgandhi	18:6a4db94011d3	15	- Redistributions of source code must retain the above copyright
sahilmgandhi	18:6a4db94011d3	16	notice, this list of conditions and the following disclaimer.
sahilmgandhi	18:6a4db94011d3	17	- Redistributions in binary form must reproduce the above copyright
sahilmgandhi	18:6a4db94011d3	18	notice, this list of conditions and the following disclaimer in the
sahilmgandhi	18:6a4db94011d3	19	documentation and/or other materials provided with the distribution.
sahilmgandhi	18:6a4db94011d3	20	- Neither the name of ARM nor the names of its contributors may be used
sahilmgandhi	18:6a4db94011d3	21	to endorse or promote products derived from this software without
sahilmgandhi	18:6a4db94011d3	22	specific prior written permission.
sahilmgandhi	18:6a4db94011d3	23	*
sahilmgandhi	18:6a4db94011d3	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi	18:6a4db94011d3	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi	18:6a4db94011d3	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
sahilmgandhi	18:6a4db94011d3	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
sahilmgandhi	18:6a4db94011d3	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
sahilmgandhi	18:6a4db94011d3	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
sahilmgandhi	18:6a4db94011d3	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
sahilmgandhi	18:6a4db94011d3	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
sahilmgandhi	18:6a4db94011d3	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
sahilmgandhi	18:6a4db94011d3	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sahilmgandhi	18:6a4db94011d3	34	POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi	18:6a4db94011d3	35	---------------------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	36
sahilmgandhi	18:6a4db94011d3	37
sahilmgandhi	18:6a4db94011d3	38	#if defined ( __ICCARM__ )
sahilmgandhi	18:6a4db94011d3	39	#pragma system_include /* treat file as system include file for MISRA check */
sahilmgandhi	18:6a4db94011d3	40	#endif
sahilmgandhi	18:6a4db94011d3	41
sahilmgandhi	18:6a4db94011d3	42	#ifndef __CORE_CM7_H_GENERIC
sahilmgandhi	18:6a4db94011d3	43	#define __CORE_CM7_H_GENERIC
sahilmgandhi	18:6a4db94011d3	44
sahilmgandhi	18:6a4db94011d3	45	#ifdef __cplusplus
sahilmgandhi	18:6a4db94011d3	46	extern "C" {
sahilmgandhi	18:6a4db94011d3	47	#endif
sahilmgandhi	18:6a4db94011d3	48
sahilmgandhi	18:6a4db94011d3	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
sahilmgandhi	18:6a4db94011d3	50	CMSIS violates the following MISRA-C:2004 rules:
sahilmgandhi	18:6a4db94011d3	51
sahilmgandhi	18:6a4db94011d3	52	\li Required Rule 8.5, object/function definition in header file.<br>
sahilmgandhi	18:6a4db94011d3	53	Function definitions in header files are used to allow 'inlining'.
sahilmgandhi	18:6a4db94011d3	54
sahilmgandhi	18:6a4db94011d3	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
sahilmgandhi	18:6a4db94011d3	56	Unions are used for effective representation of core registers.
sahilmgandhi	18:6a4db94011d3	57
sahilmgandhi	18:6a4db94011d3	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
sahilmgandhi	18:6a4db94011d3	59	Function-like macros are used to allow more efficient code.
sahilmgandhi	18:6a4db94011d3	60	*/
sahilmgandhi	18:6a4db94011d3	61
sahilmgandhi	18:6a4db94011d3	62
sahilmgandhi	18:6a4db94011d3	63	/*******************************************************************************
sahilmgandhi	18:6a4db94011d3	64	* CMSIS definitions
sahilmgandhi	18:6a4db94011d3	65	******************************************************************************/
sahilmgandhi	18:6a4db94011d3	66	/** \ingroup Cortex_M7
sahilmgandhi	18:6a4db94011d3	67	@{
sahilmgandhi	18:6a4db94011d3	68	*/
sahilmgandhi	18:6a4db94011d3	69
sahilmgandhi	18:6a4db94011d3	70	/* CMSIS CM7 definitions */
sahilmgandhi	18:6a4db94011d3	71	#define __CM7_CMSIS_VERSION_MAIN (0x04) /!< [31:16] CMSIS HAL main version /
sahilmgandhi	18:6a4db94011d3	72	#define __CM7_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
sahilmgandhi	18:6a4db94011d3	73	#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) \| \
sahilmgandhi	18:6a4db94011d3	74	__CM7_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
sahilmgandhi	18:6a4db94011d3	75
sahilmgandhi	18:6a4db94011d3	76	#define __CORTEX_M (0x07) /!< Cortex-M Core /
sahilmgandhi	18:6a4db94011d3	77
sahilmgandhi	18:6a4db94011d3	78
sahilmgandhi	18:6a4db94011d3	79	#if defined ( __CC_ARM )
sahilmgandhi	18:6a4db94011d3	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
sahilmgandhi	18:6a4db94011d3	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
sahilmgandhi	18:6a4db94011d3	82	#define __STATIC_INLINE static __inline
sahilmgandhi	18:6a4db94011d3	83
sahilmgandhi	18:6a4db94011d3	84	#elif defined ( __GNUC__ )
sahilmgandhi	18:6a4db94011d3	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
sahilmgandhi	18:6a4db94011d3	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
sahilmgandhi	18:6a4db94011d3	87	#define __STATIC_INLINE static inline
sahilmgandhi	18:6a4db94011d3	88
sahilmgandhi	18:6a4db94011d3	89	#elif defined ( __ICCARM__ )
sahilmgandhi	18:6a4db94011d3	90	#define __ASM __asm /!< asm keyword for IAR Compiler /
sahilmgandhi	18:6a4db94011d3	91	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
sahilmgandhi	18:6a4db94011d3	92	#define __STATIC_INLINE static inline
sahilmgandhi	18:6a4db94011d3	93
sahilmgandhi	18:6a4db94011d3	94	#elif defined ( __TMS470__ )
sahilmgandhi	18:6a4db94011d3	95	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
sahilmgandhi	18:6a4db94011d3	96	#define __STATIC_INLINE static inline
sahilmgandhi	18:6a4db94011d3	97
sahilmgandhi	18:6a4db94011d3	98	#elif defined ( __TASKING__ )
sahilmgandhi	18:6a4db94011d3	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
sahilmgandhi	18:6a4db94011d3	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
sahilmgandhi	18:6a4db94011d3	101	#define __STATIC_INLINE static inline
sahilmgandhi	18:6a4db94011d3	102
sahilmgandhi	18:6a4db94011d3	103	#elif defined ( __CSMC__ )
sahilmgandhi	18:6a4db94011d3	104	#define __packed
sahilmgandhi	18:6a4db94011d3	105	#define __ASM _asm /!< asm keyword for COSMIC Compiler /
sahilmgandhi	18:6a4db94011d3	106	#define __INLINE inline /use -pc99 on compile line !< inline keyword for COSMIC Compiler /
sahilmgandhi	18:6a4db94011d3	107	#define __STATIC_INLINE static inline
sahilmgandhi	18:6a4db94011d3	108
sahilmgandhi	18:6a4db94011d3	109	#endif
sahilmgandhi	18:6a4db94011d3	110
sahilmgandhi	18:6a4db94011d3	111	/** __FPU_USED indicates whether an FPU is used or not.
sahilmgandhi	18:6a4db94011d3	112	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
sahilmgandhi	18:6a4db94011d3	113	*/
sahilmgandhi	18:6a4db94011d3	114	#if defined ( __CC_ARM )
sahilmgandhi	18:6a4db94011d3	115	#if defined __TARGET_FPU_VFP
sahilmgandhi	18:6a4db94011d3	116	#if (__FPU_PRESENT == 1)
sahilmgandhi	18:6a4db94011d3	117	#define __FPU_USED 1
sahilmgandhi	18:6a4db94011d3	118	#else
sahilmgandhi	18:6a4db94011d3	119	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sahilmgandhi	18:6a4db94011d3	120	#define __FPU_USED 0
sahilmgandhi	18:6a4db94011d3	121	#endif
sahilmgandhi	18:6a4db94011d3	122	#else
sahilmgandhi	18:6a4db94011d3	123	#define __FPU_USED 0
sahilmgandhi	18:6a4db94011d3	124	#endif
sahilmgandhi	18:6a4db94011d3	125
sahilmgandhi	18:6a4db94011d3	126	#elif defined ( __GNUC__ )
sahilmgandhi	18:6a4db94011d3	127	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
sahilmgandhi	18:6a4db94011d3	128	#if (__FPU_PRESENT == 1)
sahilmgandhi	18:6a4db94011d3	129	#define __FPU_USED 1
sahilmgandhi	18:6a4db94011d3	130	#else
sahilmgandhi	18:6a4db94011d3	131	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sahilmgandhi	18:6a4db94011d3	132	#define __FPU_USED 0
sahilmgandhi	18:6a4db94011d3	133	#endif
sahilmgandhi	18:6a4db94011d3	134	#else
sahilmgandhi	18:6a4db94011d3	135	#define __FPU_USED 0
sahilmgandhi	18:6a4db94011d3	136	#endif
sahilmgandhi	18:6a4db94011d3	137
sahilmgandhi	18:6a4db94011d3	138	#elif defined ( __ICCARM__ )
sahilmgandhi	18:6a4db94011d3	139	#if defined __ARMVFP__
sahilmgandhi	18:6a4db94011d3	140	#if (__FPU_PRESENT == 1)
sahilmgandhi	18:6a4db94011d3	141	#define __FPU_USED 1
sahilmgandhi	18:6a4db94011d3	142	#else
sahilmgandhi	18:6a4db94011d3	143	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sahilmgandhi	18:6a4db94011d3	144	#define __FPU_USED 0
sahilmgandhi	18:6a4db94011d3	145	#endif
sahilmgandhi	18:6a4db94011d3	146	#else
sahilmgandhi	18:6a4db94011d3	147	#define __FPU_USED 0
sahilmgandhi	18:6a4db94011d3	148	#endif
sahilmgandhi	18:6a4db94011d3	149
sahilmgandhi	18:6a4db94011d3	150	#elif defined ( __TMS470__ )
sahilmgandhi	18:6a4db94011d3	151	#if defined __TI_VFP_SUPPORT__
sahilmgandhi	18:6a4db94011d3	152	#if (__FPU_PRESENT == 1)
sahilmgandhi	18:6a4db94011d3	153	#define __FPU_USED 1
sahilmgandhi	18:6a4db94011d3	154	#else
sahilmgandhi	18:6a4db94011d3	155	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sahilmgandhi	18:6a4db94011d3	156	#define __FPU_USED 0
sahilmgandhi	18:6a4db94011d3	157	#endif
sahilmgandhi	18:6a4db94011d3	158	#else
sahilmgandhi	18:6a4db94011d3	159	#define __FPU_USED 0
sahilmgandhi	18:6a4db94011d3	160	#endif
sahilmgandhi	18:6a4db94011d3	161
sahilmgandhi	18:6a4db94011d3	162	#elif defined ( __TASKING__ )
sahilmgandhi	18:6a4db94011d3	163	#if defined __FPU_VFP__
sahilmgandhi	18:6a4db94011d3	164	#if (__FPU_PRESENT == 1)
sahilmgandhi	18:6a4db94011d3	165	#define __FPU_USED 1
sahilmgandhi	18:6a4db94011d3	166	#else
sahilmgandhi	18:6a4db94011d3	167	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sahilmgandhi	18:6a4db94011d3	168	#define __FPU_USED 0
sahilmgandhi	18:6a4db94011d3	169	#endif
sahilmgandhi	18:6a4db94011d3	170	#else
sahilmgandhi	18:6a4db94011d3	171	#define __FPU_USED 0
sahilmgandhi	18:6a4db94011d3	172	#endif
sahilmgandhi	18:6a4db94011d3	173
sahilmgandhi	18:6a4db94011d3	174	#elif defined ( __CSMC__ ) /* Cosmic */
sahilmgandhi	18:6a4db94011d3	175	#if ( __CSMC__ & 0x400) // FPU present for parser
sahilmgandhi	18:6a4db94011d3	176	#if (__FPU_PRESENT == 1)
sahilmgandhi	18:6a4db94011d3	177	#define __FPU_USED 1
sahilmgandhi	18:6a4db94011d3	178	#else
sahilmgandhi	18:6a4db94011d3	179	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sahilmgandhi	18:6a4db94011d3	180	#define __FPU_USED 0
sahilmgandhi	18:6a4db94011d3	181	#endif
sahilmgandhi	18:6a4db94011d3	182	#else
sahilmgandhi	18:6a4db94011d3	183	#define __FPU_USED 0
sahilmgandhi	18:6a4db94011d3	184	#endif
sahilmgandhi	18:6a4db94011d3	185	#endif
sahilmgandhi	18:6a4db94011d3	186
sahilmgandhi	18:6a4db94011d3	187	#include <stdint.h> /* standard types definitions */
sahilmgandhi	18:6a4db94011d3	188	#include <core_cmInstr.h> /* Core Instruction Access */
sahilmgandhi	18:6a4db94011d3	189	#include <core_cmFunc.h> /* Core Function Access */
sahilmgandhi	18:6a4db94011d3	190	#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
sahilmgandhi	18:6a4db94011d3	191
sahilmgandhi	18:6a4db94011d3	192	#ifdef __cplusplus
sahilmgandhi	18:6a4db94011d3	193	}
sahilmgandhi	18:6a4db94011d3	194	#endif
sahilmgandhi	18:6a4db94011d3	195
sahilmgandhi	18:6a4db94011d3	196	#endif /* __CORE_CM7_H_GENERIC */
sahilmgandhi	18:6a4db94011d3	197
sahilmgandhi	18:6a4db94011d3	198	#ifndef __CMSIS_GENERIC
sahilmgandhi	18:6a4db94011d3	199
sahilmgandhi	18:6a4db94011d3	200	#ifndef __CORE_CM7_H_DEPENDANT
sahilmgandhi	18:6a4db94011d3	201	#define __CORE_CM7_H_DEPENDANT
sahilmgandhi	18:6a4db94011d3	202
sahilmgandhi	18:6a4db94011d3	203	#ifdef __cplusplus
sahilmgandhi	18:6a4db94011d3	204	extern "C" {
sahilmgandhi	18:6a4db94011d3	205	#endif
sahilmgandhi	18:6a4db94011d3	206
sahilmgandhi	18:6a4db94011d3	207	/* check device defines and use defaults */
sahilmgandhi	18:6a4db94011d3	208	#if defined __CHECK_DEVICE_DEFINES
sahilmgandhi	18:6a4db94011d3	209	#ifndef __CM7_REV
sahilmgandhi	18:6a4db94011d3	210	#define __CM7_REV 0x0000
sahilmgandhi	18:6a4db94011d3	211	#warning "__CM7_REV not defined in device header file; using default!"
sahilmgandhi	18:6a4db94011d3	212	#endif
sahilmgandhi	18:6a4db94011d3	213
sahilmgandhi	18:6a4db94011d3	214	#ifndef __FPU_PRESENT
sahilmgandhi	18:6a4db94011d3	215	#define __FPU_PRESENT 0
sahilmgandhi	18:6a4db94011d3	216	#warning "__FPU_PRESENT not defined in device header file; using default!"
sahilmgandhi	18:6a4db94011d3	217	#endif
sahilmgandhi	18:6a4db94011d3	218
sahilmgandhi	18:6a4db94011d3	219	#ifndef __MPU_PRESENT
sahilmgandhi	18:6a4db94011d3	220	#define __MPU_PRESENT 0
sahilmgandhi	18:6a4db94011d3	221	#warning "__MPU_PRESENT not defined in device header file; using default!"
sahilmgandhi	18:6a4db94011d3	222	#endif
sahilmgandhi	18:6a4db94011d3	223
sahilmgandhi	18:6a4db94011d3	224	#ifndef __ICACHE_PRESENT
sahilmgandhi	18:6a4db94011d3	225	#define __ICACHE_PRESENT 0
sahilmgandhi	18:6a4db94011d3	226	#warning "__ICACHE_PRESENT not defined in device header file; using default!"
sahilmgandhi	18:6a4db94011d3	227	#endif
sahilmgandhi	18:6a4db94011d3	228
sahilmgandhi	18:6a4db94011d3	229	#ifndef __DCACHE_PRESENT
sahilmgandhi	18:6a4db94011d3	230	#define __DCACHE_PRESENT 0
sahilmgandhi	18:6a4db94011d3	231	#warning "__DCACHE_PRESENT not defined in device header file; using default!"
sahilmgandhi	18:6a4db94011d3	232	#endif
sahilmgandhi	18:6a4db94011d3	233
sahilmgandhi	18:6a4db94011d3	234	#ifndef __DTCM_PRESENT
sahilmgandhi	18:6a4db94011d3	235	#define __DTCM_PRESENT 0
sahilmgandhi	18:6a4db94011d3	236	#warning "__DTCM_PRESENT not defined in device header file; using default!"
sahilmgandhi	18:6a4db94011d3	237	#endif
sahilmgandhi	18:6a4db94011d3	238
sahilmgandhi	18:6a4db94011d3	239	#ifndef __NVIC_PRIO_BITS
sahilmgandhi	18:6a4db94011d3	240	#define __NVIC_PRIO_BITS 3
sahilmgandhi	18:6a4db94011d3	241	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
sahilmgandhi	18:6a4db94011d3	242	#endif
sahilmgandhi	18:6a4db94011d3	243
sahilmgandhi	18:6a4db94011d3	244	#ifndef __Vendor_SysTickConfig
sahilmgandhi	18:6a4db94011d3	245	#define __Vendor_SysTickConfig 0
sahilmgandhi	18:6a4db94011d3	246	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
sahilmgandhi	18:6a4db94011d3	247	#endif
sahilmgandhi	18:6a4db94011d3	248	#endif
sahilmgandhi	18:6a4db94011d3	249
sahilmgandhi	18:6a4db94011d3	250	/* IO definitions (access restrictions to peripheral registers) */
sahilmgandhi	18:6a4db94011d3	251	/**
sahilmgandhi	18:6a4db94011d3	252	\defgroup CMSIS_glob_defs CMSIS Global Defines
sahilmgandhi	18:6a4db94011d3	253
sahilmgandhi	18:6a4db94011d3	254	<strong>IO Type Qualifiers</strong> are used
sahilmgandhi	18:6a4db94011d3	255	\li to specify the access to peripheral variables.
sahilmgandhi	18:6a4db94011d3	256	\li for automatic generation of peripheral register debug information.
sahilmgandhi	18:6a4db94011d3	257	*/
sahilmgandhi	18:6a4db94011d3	258	#ifdef __cplusplus
sahilmgandhi	18:6a4db94011d3	259	#define __I volatile /!< Defines 'read only' permissions /
sahilmgandhi	18:6a4db94011d3	260	#else
sahilmgandhi	18:6a4db94011d3	261	#define __I volatile const /!< Defines 'read only' permissions /
sahilmgandhi	18:6a4db94011d3	262	#endif
sahilmgandhi	18:6a4db94011d3	263	#define __O volatile /!< Defines 'write only' permissions /
sahilmgandhi	18:6a4db94011d3	264	#define __IO volatile /!< Defines 'read / write' permissions /
sahilmgandhi	18:6a4db94011d3	265
sahilmgandhi	18:6a4db94011d3	266	#ifdef __cplusplus
sahilmgandhi	18:6a4db94011d3	267	#define __IM volatile /!< Defines 'read only' permissions /
sahilmgandhi	18:6a4db94011d3	268	#else
sahilmgandhi	18:6a4db94011d3	269	#define __IM volatile const /!< Defines 'read only' permissions /
sahilmgandhi	18:6a4db94011d3	270	#endif
sahilmgandhi	18:6a4db94011d3	271	#define __OM volatile /!< Defines 'write only' permissions /
sahilmgandhi	18:6a4db94011d3	272	#define __IOM volatile /!< Defines 'read / write' permissions /
sahilmgandhi	18:6a4db94011d3	273
sahilmgandhi	18:6a4db94011d3	274	/@} end of group Cortex_M7 /
sahilmgandhi	18:6a4db94011d3	275
sahilmgandhi	18:6a4db94011d3	276
sahilmgandhi	18:6a4db94011d3	277
sahilmgandhi	18:6a4db94011d3	278	/*******************************************************************************
sahilmgandhi	18:6a4db94011d3	279	* Register Abstraction
sahilmgandhi	18:6a4db94011d3	280	Core Register contain:
sahilmgandhi	18:6a4db94011d3	281	- Core Register
sahilmgandhi	18:6a4db94011d3	282	- Core NVIC Register
sahilmgandhi	18:6a4db94011d3	283	- Core SCB Register
sahilmgandhi	18:6a4db94011d3	284	- Core SysTick Register
sahilmgandhi	18:6a4db94011d3	285	- Core Debug Register
sahilmgandhi	18:6a4db94011d3	286	- Core MPU Register
sahilmgandhi	18:6a4db94011d3	287	- Core FPU Register
sahilmgandhi	18:6a4db94011d3	288	******************************************************************************/
sahilmgandhi	18:6a4db94011d3	289	/** \defgroup CMSIS_core_register Defines and Type Definitions
sahilmgandhi	18:6a4db94011d3	290	\brief Type definitions and defines for Cortex-M processor based devices.
sahilmgandhi	18:6a4db94011d3	291	*/
sahilmgandhi	18:6a4db94011d3	292
sahilmgandhi	18:6a4db94011d3	293	/** \ingroup CMSIS_core_register
sahilmgandhi	18:6a4db94011d3	294	\defgroup CMSIS_CORE Status and Control Registers
sahilmgandhi	18:6a4db94011d3	295	\brief Core Register type definitions.
sahilmgandhi	18:6a4db94011d3	296	@{
sahilmgandhi	18:6a4db94011d3	297	*/
sahilmgandhi	18:6a4db94011d3	298
sahilmgandhi	18:6a4db94011d3	299	/** \brief Union type to access the Application Program Status Register (APSR).
sahilmgandhi	18:6a4db94011d3	300	*/
sahilmgandhi	18:6a4db94011d3	301	typedef union
sahilmgandhi	18:6a4db94011d3	302	{
sahilmgandhi	18:6a4db94011d3	303	struct
sahilmgandhi	18:6a4db94011d3	304	{
sahilmgandhi	18:6a4db94011d3	305	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
sahilmgandhi	18:6a4db94011d3	306	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
sahilmgandhi	18:6a4db94011d3	307	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
sahilmgandhi	18:6a4db94011d3	308	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
sahilmgandhi	18:6a4db94011d3	309	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
sahilmgandhi	18:6a4db94011d3	310	uint32_t C:1; /!< bit: 29 Carry condition code flag /
sahilmgandhi	18:6a4db94011d3	311	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
sahilmgandhi	18:6a4db94011d3	312	uint32_t N:1; /!< bit: 31 Negative condition code flag /
sahilmgandhi	18:6a4db94011d3	313	} b; /!< Structure used for bit access /
sahilmgandhi	18:6a4db94011d3	314	uint32_t w; /!< Type used for word access /
sahilmgandhi	18:6a4db94011d3	315	} APSR_Type;
sahilmgandhi	18:6a4db94011d3	316
sahilmgandhi	18:6a4db94011d3	317	/* APSR Register Definitions */
sahilmgandhi	18:6a4db94011d3	318	#define APSR_N_Pos 31 /!< APSR: N Position /
sahilmgandhi	18:6a4db94011d3	319	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
sahilmgandhi	18:6a4db94011d3	320
sahilmgandhi	18:6a4db94011d3	321	#define APSR_Z_Pos 30 /!< APSR: Z Position /
sahilmgandhi	18:6a4db94011d3	322	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
sahilmgandhi	18:6a4db94011d3	323
sahilmgandhi	18:6a4db94011d3	324	#define APSR_C_Pos 29 /!< APSR: C Position /
sahilmgandhi	18:6a4db94011d3	325	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
sahilmgandhi	18:6a4db94011d3	326
sahilmgandhi	18:6a4db94011d3	327	#define APSR_V_Pos 28 /!< APSR: V Position /
sahilmgandhi	18:6a4db94011d3	328	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
sahilmgandhi	18:6a4db94011d3	329
sahilmgandhi	18:6a4db94011d3	330	#define APSR_Q_Pos 27 /!< APSR: Q Position /
sahilmgandhi	18:6a4db94011d3	331	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
sahilmgandhi	18:6a4db94011d3	332
sahilmgandhi	18:6a4db94011d3	333	#define APSR_GE_Pos 16 /!< APSR: GE Position /
sahilmgandhi	18:6a4db94011d3	334	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
sahilmgandhi	18:6a4db94011d3	335
sahilmgandhi	18:6a4db94011d3	336
sahilmgandhi	18:6a4db94011d3	337	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
sahilmgandhi	18:6a4db94011d3	338	*/
sahilmgandhi	18:6a4db94011d3	339	typedef union
sahilmgandhi	18:6a4db94011d3	340	{
sahilmgandhi	18:6a4db94011d3	341	struct
sahilmgandhi	18:6a4db94011d3	342	{
sahilmgandhi	18:6a4db94011d3	343	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
sahilmgandhi	18:6a4db94011d3	344	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
sahilmgandhi	18:6a4db94011d3	345	} b; /!< Structure used for bit access /
sahilmgandhi	18:6a4db94011d3	346	uint32_t w; /!< Type used for word access /
sahilmgandhi	18:6a4db94011d3	347	} IPSR_Type;
sahilmgandhi	18:6a4db94011d3	348
sahilmgandhi	18:6a4db94011d3	349	/* IPSR Register Definitions */
sahilmgandhi	18:6a4db94011d3	350	#define IPSR_ISR_Pos 0 /!< IPSR: ISR Position /
sahilmgandhi	18:6a4db94011d3	351	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
sahilmgandhi	18:6a4db94011d3	352
sahilmgandhi	18:6a4db94011d3	353
sahilmgandhi	18:6a4db94011d3	354	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
sahilmgandhi	18:6a4db94011d3	355	*/
sahilmgandhi	18:6a4db94011d3	356	typedef union
sahilmgandhi	18:6a4db94011d3	357	{
sahilmgandhi	18:6a4db94011d3	358	struct
sahilmgandhi	18:6a4db94011d3	359	{
sahilmgandhi	18:6a4db94011d3	360	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
sahilmgandhi	18:6a4db94011d3	361	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
sahilmgandhi	18:6a4db94011d3	362	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
sahilmgandhi	18:6a4db94011d3	363	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
sahilmgandhi	18:6a4db94011d3	364	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
sahilmgandhi	18:6a4db94011d3	365	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
sahilmgandhi	18:6a4db94011d3	366	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
sahilmgandhi	18:6a4db94011d3	367	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
sahilmgandhi	18:6a4db94011d3	368	uint32_t C:1; /!< bit: 29 Carry condition code flag /
sahilmgandhi	18:6a4db94011d3	369	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
sahilmgandhi	18:6a4db94011d3	370	uint32_t N:1; /!< bit: 31 Negative condition code flag /
sahilmgandhi	18:6a4db94011d3	371	} b; /!< Structure used for bit access /
sahilmgandhi	18:6a4db94011d3	372	uint32_t w; /!< Type used for word access /
sahilmgandhi	18:6a4db94011d3	373	} xPSR_Type;
sahilmgandhi	18:6a4db94011d3	374
sahilmgandhi	18:6a4db94011d3	375	/* xPSR Register Definitions */
sahilmgandhi	18:6a4db94011d3	376	#define xPSR_N_Pos 31 /!< xPSR: N Position /
sahilmgandhi	18:6a4db94011d3	377	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
sahilmgandhi	18:6a4db94011d3	378
sahilmgandhi	18:6a4db94011d3	379	#define xPSR_Z_Pos 30 /!< xPSR: Z Position /
sahilmgandhi	18:6a4db94011d3	380	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
sahilmgandhi	18:6a4db94011d3	381
sahilmgandhi	18:6a4db94011d3	382	#define xPSR_C_Pos 29 /!< xPSR: C Position /
sahilmgandhi	18:6a4db94011d3	383	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
sahilmgandhi	18:6a4db94011d3	384
sahilmgandhi	18:6a4db94011d3	385	#define xPSR_V_Pos 28 /!< xPSR: V Position /
sahilmgandhi	18:6a4db94011d3	386	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
sahilmgandhi	18:6a4db94011d3	387
sahilmgandhi	18:6a4db94011d3	388	#define xPSR_Q_Pos 27 /!< xPSR: Q Position /
sahilmgandhi	18:6a4db94011d3	389	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
sahilmgandhi	18:6a4db94011d3	390
sahilmgandhi	18:6a4db94011d3	391	#define xPSR_IT_Pos 25 /!< xPSR: IT Position /
sahilmgandhi	18:6a4db94011d3	392	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
sahilmgandhi	18:6a4db94011d3	393
sahilmgandhi	18:6a4db94011d3	394	#define xPSR_T_Pos 24 /!< xPSR: T Position /
sahilmgandhi	18:6a4db94011d3	395	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
sahilmgandhi	18:6a4db94011d3	396
sahilmgandhi	18:6a4db94011d3	397	#define xPSR_GE_Pos 16 /!< xPSR: GE Position /
sahilmgandhi	18:6a4db94011d3	398	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
sahilmgandhi	18:6a4db94011d3	399
sahilmgandhi	18:6a4db94011d3	400	#define xPSR_ISR_Pos 0 /!< xPSR: ISR Position /
sahilmgandhi	18:6a4db94011d3	401	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
sahilmgandhi	18:6a4db94011d3	402
sahilmgandhi	18:6a4db94011d3	403
sahilmgandhi	18:6a4db94011d3	404	/** \brief Union type to access the Control Registers (CONTROL).
sahilmgandhi	18:6a4db94011d3	405	*/
sahilmgandhi	18:6a4db94011d3	406	typedef union
sahilmgandhi	18:6a4db94011d3	407	{
sahilmgandhi	18:6a4db94011d3	408	struct
sahilmgandhi	18:6a4db94011d3	409	{
sahilmgandhi	18:6a4db94011d3	410	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
sahilmgandhi	18:6a4db94011d3	411	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
sahilmgandhi	18:6a4db94011d3	412	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
sahilmgandhi	18:6a4db94011d3	413	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
sahilmgandhi	18:6a4db94011d3	414	} b; /!< Structure used for bit access /
sahilmgandhi	18:6a4db94011d3	415	uint32_t w; /!< Type used for word access /
sahilmgandhi	18:6a4db94011d3	416	} CONTROL_Type;
sahilmgandhi	18:6a4db94011d3	417
sahilmgandhi	18:6a4db94011d3	418	/* CONTROL Register Definitions */
sahilmgandhi	18:6a4db94011d3	419	#define CONTROL_FPCA_Pos 2 /!< CONTROL: FPCA Position /
sahilmgandhi	18:6a4db94011d3	420	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
sahilmgandhi	18:6a4db94011d3	421
sahilmgandhi	18:6a4db94011d3	422	#define CONTROL_SPSEL_Pos 1 /!< CONTROL: SPSEL Position /
sahilmgandhi	18:6a4db94011d3	423	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
sahilmgandhi	18:6a4db94011d3	424
sahilmgandhi	18:6a4db94011d3	425	#define CONTROL_nPRIV_Pos 0 /!< CONTROL: nPRIV Position /
sahilmgandhi	18:6a4db94011d3	426	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
sahilmgandhi	18:6a4db94011d3	427
sahilmgandhi	18:6a4db94011d3	428	/@} end of group CMSIS_CORE /
sahilmgandhi	18:6a4db94011d3	429
sahilmgandhi	18:6a4db94011d3	430
sahilmgandhi	18:6a4db94011d3	431	/** \ingroup CMSIS_core_register
sahilmgandhi	18:6a4db94011d3	432	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
sahilmgandhi	18:6a4db94011d3	433	\brief Type definitions for the NVIC Registers
sahilmgandhi	18:6a4db94011d3	434	@{
sahilmgandhi	18:6a4db94011d3	435	*/
sahilmgandhi	18:6a4db94011d3	436
sahilmgandhi	18:6a4db94011d3	437	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
sahilmgandhi	18:6a4db94011d3	438	*/
sahilmgandhi	18:6a4db94011d3	439	typedef struct
sahilmgandhi	18:6a4db94011d3	440	{
sahilmgandhi	18:6a4db94011d3	441	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
sahilmgandhi	18:6a4db94011d3	442	uint32_t RESERVED0[24];
sahilmgandhi	18:6a4db94011d3	443	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
sahilmgandhi	18:6a4db94011d3	444	uint32_t RSERVED1[24];
sahilmgandhi	18:6a4db94011d3	445	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
sahilmgandhi	18:6a4db94011d3	446	uint32_t RESERVED2[24];
sahilmgandhi	18:6a4db94011d3	447	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
sahilmgandhi	18:6a4db94011d3	448	uint32_t RESERVED3[24];
sahilmgandhi	18:6a4db94011d3	449	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
sahilmgandhi	18:6a4db94011d3	450	uint32_t RESERVED4[56];
sahilmgandhi	18:6a4db94011d3	451	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
sahilmgandhi	18:6a4db94011d3	452	uint32_t RESERVED5[644];
sahilmgandhi	18:6a4db94011d3	453	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
sahilmgandhi	18:6a4db94011d3	454	} NVIC_Type;
sahilmgandhi	18:6a4db94011d3	455
sahilmgandhi	18:6a4db94011d3	456	/* Software Triggered Interrupt Register Definitions */
sahilmgandhi	18:6a4db94011d3	457	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
sahilmgandhi	18:6a4db94011d3	458	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
sahilmgandhi	18:6a4db94011d3	459
sahilmgandhi	18:6a4db94011d3	460	/@} end of group CMSIS_NVIC /
sahilmgandhi	18:6a4db94011d3	461
sahilmgandhi	18:6a4db94011d3	462
sahilmgandhi	18:6a4db94011d3	463	/** \ingroup CMSIS_core_register
sahilmgandhi	18:6a4db94011d3	464	\defgroup CMSIS_SCB System Control Block (SCB)
sahilmgandhi	18:6a4db94011d3	465	\brief Type definitions for the System Control Block Registers
sahilmgandhi	18:6a4db94011d3	466	@{
sahilmgandhi	18:6a4db94011d3	467	*/
sahilmgandhi	18:6a4db94011d3	468
sahilmgandhi	18:6a4db94011d3	469	/** \brief Structure type to access the System Control Block (SCB).
sahilmgandhi	18:6a4db94011d3	470	*/
sahilmgandhi	18:6a4db94011d3	471	typedef struct
sahilmgandhi	18:6a4db94011d3	472	{
sahilmgandhi	18:6a4db94011d3	473	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
sahilmgandhi	18:6a4db94011d3	474	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
sahilmgandhi	18:6a4db94011d3	475	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
sahilmgandhi	18:6a4db94011d3	476	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
sahilmgandhi	18:6a4db94011d3	477	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
sahilmgandhi	18:6a4db94011d3	478	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
sahilmgandhi	18:6a4db94011d3	479	__IO uint8_t SHPR[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
sahilmgandhi	18:6a4db94011d3	480	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
sahilmgandhi	18:6a4db94011d3	481	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
sahilmgandhi	18:6a4db94011d3	482	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
sahilmgandhi	18:6a4db94011d3	483	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
sahilmgandhi	18:6a4db94011d3	484	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
sahilmgandhi	18:6a4db94011d3	485	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
sahilmgandhi	18:6a4db94011d3	486	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
sahilmgandhi	18:6a4db94011d3	487	__I uint32_t ID_PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
sahilmgandhi	18:6a4db94011d3	488	__I uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
sahilmgandhi	18:6a4db94011d3	489	__I uint32_t ID_AFR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
sahilmgandhi	18:6a4db94011d3	490	__I uint32_t ID_MFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
sahilmgandhi	18:6a4db94011d3	491	__I uint32_t ID_ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
sahilmgandhi	18:6a4db94011d3	492	uint32_t RESERVED0[1];
sahilmgandhi	18:6a4db94011d3	493	__I uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
sahilmgandhi	18:6a4db94011d3	494	__I uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
sahilmgandhi	18:6a4db94011d3	495	__I uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
sahilmgandhi	18:6a4db94011d3	496	__IO uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
sahilmgandhi	18:6a4db94011d3	497	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
sahilmgandhi	18:6a4db94011d3	498	uint32_t RESERVED3[93];
sahilmgandhi	18:6a4db94011d3	499	__O uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
sahilmgandhi	18:6a4db94011d3	500	uint32_t RESERVED4[15];
sahilmgandhi	18:6a4db94011d3	501	__I uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
sahilmgandhi	18:6a4db94011d3	502	__I uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
sahilmgandhi	18:6a4db94011d3	503	__I uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 /
sahilmgandhi	18:6a4db94011d3	504	uint32_t RESERVED5[1];
sahilmgandhi	18:6a4db94011d3	505	__O uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
sahilmgandhi	18:6a4db94011d3	506	uint32_t RESERVED6[1];
sahilmgandhi	18:6a4db94011d3	507	__O uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
sahilmgandhi	18:6a4db94011d3	508	__O uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
sahilmgandhi	18:6a4db94011d3	509	__O uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
sahilmgandhi	18:6a4db94011d3	510	__O uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
sahilmgandhi	18:6a4db94011d3	511	__O uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
sahilmgandhi	18:6a4db94011d3	512	__O uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
sahilmgandhi	18:6a4db94011d3	513	__O uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
sahilmgandhi	18:6a4db94011d3	514	__O uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
sahilmgandhi	18:6a4db94011d3	515	uint32_t RESERVED7[6];
sahilmgandhi	18:6a4db94011d3	516	__IO uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
sahilmgandhi	18:6a4db94011d3	517	__IO uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
sahilmgandhi	18:6a4db94011d3	518	__IO uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
sahilmgandhi	18:6a4db94011d3	519	__IO uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
sahilmgandhi	18:6a4db94011d3	520	__IO uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
sahilmgandhi	18:6a4db94011d3	521	uint32_t RESERVED8[1];
sahilmgandhi	18:6a4db94011d3	522	__IO uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
sahilmgandhi	18:6a4db94011d3	523	} SCB_Type;
sahilmgandhi	18:6a4db94011d3	524
sahilmgandhi	18:6a4db94011d3	525	/* SCB CPUID Register Definitions */
sahilmgandhi	18:6a4db94011d3	526	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
sahilmgandhi	18:6a4db94011d3	527	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
sahilmgandhi	18:6a4db94011d3	528
sahilmgandhi	18:6a4db94011d3	529	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
sahilmgandhi	18:6a4db94011d3	530	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
sahilmgandhi	18:6a4db94011d3	531
sahilmgandhi	18:6a4db94011d3	532	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
sahilmgandhi	18:6a4db94011d3	533	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
sahilmgandhi	18:6a4db94011d3	534
sahilmgandhi	18:6a4db94011d3	535	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
sahilmgandhi	18:6a4db94011d3	536	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
sahilmgandhi	18:6a4db94011d3	537
sahilmgandhi	18:6a4db94011d3	538	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
sahilmgandhi	18:6a4db94011d3	539	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
sahilmgandhi	18:6a4db94011d3	540
sahilmgandhi	18:6a4db94011d3	541	/* SCB Interrupt Control State Register Definitions */
sahilmgandhi	18:6a4db94011d3	542	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
sahilmgandhi	18:6a4db94011d3	543	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
sahilmgandhi	18:6a4db94011d3	544
sahilmgandhi	18:6a4db94011d3	545	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
sahilmgandhi	18:6a4db94011d3	546	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
sahilmgandhi	18:6a4db94011d3	547
sahilmgandhi	18:6a4db94011d3	548	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
sahilmgandhi	18:6a4db94011d3	549	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
sahilmgandhi	18:6a4db94011d3	550
sahilmgandhi	18:6a4db94011d3	551	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
sahilmgandhi	18:6a4db94011d3	552	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
sahilmgandhi	18:6a4db94011d3	553
sahilmgandhi	18:6a4db94011d3	554	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
sahilmgandhi	18:6a4db94011d3	555	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
sahilmgandhi	18:6a4db94011d3	556
sahilmgandhi	18:6a4db94011d3	557	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
sahilmgandhi	18:6a4db94011d3	558	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
sahilmgandhi	18:6a4db94011d3	559
sahilmgandhi	18:6a4db94011d3	560	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
sahilmgandhi	18:6a4db94011d3	561	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
sahilmgandhi	18:6a4db94011d3	562
sahilmgandhi	18:6a4db94011d3	563	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
sahilmgandhi	18:6a4db94011d3	564	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
sahilmgandhi	18:6a4db94011d3	565
sahilmgandhi	18:6a4db94011d3	566	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
sahilmgandhi	18:6a4db94011d3	567	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
sahilmgandhi	18:6a4db94011d3	568
sahilmgandhi	18:6a4db94011d3	569	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
sahilmgandhi	18:6a4db94011d3	570	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
sahilmgandhi	18:6a4db94011d3	571
sahilmgandhi	18:6a4db94011d3	572	/* SCB Vector Table Offset Register Definitions */
sahilmgandhi	18:6a4db94011d3	573	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
sahilmgandhi	18:6a4db94011d3	574	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
sahilmgandhi	18:6a4db94011d3	575
sahilmgandhi	18:6a4db94011d3	576	/* SCB Application Interrupt and Reset Control Register Definitions */
sahilmgandhi	18:6a4db94011d3	577	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
sahilmgandhi	18:6a4db94011d3	578	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
sahilmgandhi	18:6a4db94011d3	579
sahilmgandhi	18:6a4db94011d3	580	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
sahilmgandhi	18:6a4db94011d3	581	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
sahilmgandhi	18:6a4db94011d3	582
sahilmgandhi	18:6a4db94011d3	583	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
sahilmgandhi	18:6a4db94011d3	584	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
sahilmgandhi	18:6a4db94011d3	585
sahilmgandhi	18:6a4db94011d3	586	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
sahilmgandhi	18:6a4db94011d3	587	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
sahilmgandhi	18:6a4db94011d3	588
sahilmgandhi	18:6a4db94011d3	589	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
sahilmgandhi	18:6a4db94011d3	590	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
sahilmgandhi	18:6a4db94011d3	591
sahilmgandhi	18:6a4db94011d3	592	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
sahilmgandhi	18:6a4db94011d3	593	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
sahilmgandhi	18:6a4db94011d3	594
sahilmgandhi	18:6a4db94011d3	595	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
sahilmgandhi	18:6a4db94011d3	596	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
sahilmgandhi	18:6a4db94011d3	597
sahilmgandhi	18:6a4db94011d3	598	/* SCB System Control Register Definitions */
sahilmgandhi	18:6a4db94011d3	599	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
sahilmgandhi	18:6a4db94011d3	600	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
sahilmgandhi	18:6a4db94011d3	601
sahilmgandhi	18:6a4db94011d3	602	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
sahilmgandhi	18:6a4db94011d3	603	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
sahilmgandhi	18:6a4db94011d3	604
sahilmgandhi	18:6a4db94011d3	605	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
sahilmgandhi	18:6a4db94011d3	606	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
sahilmgandhi	18:6a4db94011d3	607
sahilmgandhi	18:6a4db94011d3	608	/* SCB Configuration Control Register Definitions */
sahilmgandhi	18:6a4db94011d3	609	#define SCB_CCR_BP_Pos 18 /!< SCB CCR: Branch prediction enable bit Position /
sahilmgandhi	18:6a4db94011d3	610	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: Branch prediction enable bit Mask /
sahilmgandhi	18:6a4db94011d3	611
sahilmgandhi	18:6a4db94011d3	612	#define SCB_CCR_IC_Pos 17 /!< SCB CCR: Instruction cache enable bit Position /
sahilmgandhi	18:6a4db94011d3	613	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: Instruction cache enable bit Mask /
sahilmgandhi	18:6a4db94011d3	614
sahilmgandhi	18:6a4db94011d3	615	#define SCB_CCR_DC_Pos 16 /!< SCB CCR: Cache enable bit Position /
sahilmgandhi	18:6a4db94011d3	616	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: Cache enable bit Mask /
sahilmgandhi	18:6a4db94011d3	617
sahilmgandhi	18:6a4db94011d3	618	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
sahilmgandhi	18:6a4db94011d3	619	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
sahilmgandhi	18:6a4db94011d3	620
sahilmgandhi	18:6a4db94011d3	621	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
sahilmgandhi	18:6a4db94011d3	622	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
sahilmgandhi	18:6a4db94011d3	623
sahilmgandhi	18:6a4db94011d3	624	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
sahilmgandhi	18:6a4db94011d3	625	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
sahilmgandhi	18:6a4db94011d3	626
sahilmgandhi	18:6a4db94011d3	627	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
sahilmgandhi	18:6a4db94011d3	628	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
sahilmgandhi	18:6a4db94011d3	629
sahilmgandhi	18:6a4db94011d3	630	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
sahilmgandhi	18:6a4db94011d3	631	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
sahilmgandhi	18:6a4db94011d3	632
sahilmgandhi	18:6a4db94011d3	633	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
sahilmgandhi	18:6a4db94011d3	634	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
sahilmgandhi	18:6a4db94011d3	635
sahilmgandhi	18:6a4db94011d3	636	/* SCB System Handler Control and State Register Definitions */
sahilmgandhi	18:6a4db94011d3	637	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
sahilmgandhi	18:6a4db94011d3	638	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
sahilmgandhi	18:6a4db94011d3	639
sahilmgandhi	18:6a4db94011d3	640	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
sahilmgandhi	18:6a4db94011d3	641	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
sahilmgandhi	18:6a4db94011d3	642
sahilmgandhi	18:6a4db94011d3	643	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
sahilmgandhi	18:6a4db94011d3	644	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
sahilmgandhi	18:6a4db94011d3	645
sahilmgandhi	18:6a4db94011d3	646	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
sahilmgandhi	18:6a4db94011d3	647	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
sahilmgandhi	18:6a4db94011d3	648
sahilmgandhi	18:6a4db94011d3	649	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
sahilmgandhi	18:6a4db94011d3	650	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
sahilmgandhi	18:6a4db94011d3	651
sahilmgandhi	18:6a4db94011d3	652	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
sahilmgandhi	18:6a4db94011d3	653	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
sahilmgandhi	18:6a4db94011d3	654
sahilmgandhi	18:6a4db94011d3	655	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
sahilmgandhi	18:6a4db94011d3	656	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
sahilmgandhi	18:6a4db94011d3	657
sahilmgandhi	18:6a4db94011d3	658	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
sahilmgandhi	18:6a4db94011d3	659	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
sahilmgandhi	18:6a4db94011d3	660
sahilmgandhi	18:6a4db94011d3	661	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
sahilmgandhi	18:6a4db94011d3	662	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
sahilmgandhi	18:6a4db94011d3	663
sahilmgandhi	18:6a4db94011d3	664	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
sahilmgandhi	18:6a4db94011d3	665	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
sahilmgandhi	18:6a4db94011d3	666
sahilmgandhi	18:6a4db94011d3	667	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
sahilmgandhi	18:6a4db94011d3	668	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
sahilmgandhi	18:6a4db94011d3	669
sahilmgandhi	18:6a4db94011d3	670	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
sahilmgandhi	18:6a4db94011d3	671	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
sahilmgandhi	18:6a4db94011d3	672
sahilmgandhi	18:6a4db94011d3	673	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
sahilmgandhi	18:6a4db94011d3	674	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
sahilmgandhi	18:6a4db94011d3	675
sahilmgandhi	18:6a4db94011d3	676	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
sahilmgandhi	18:6a4db94011d3	677	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
sahilmgandhi	18:6a4db94011d3	678
sahilmgandhi	18:6a4db94011d3	679	/* SCB Configurable Fault Status Registers Definitions */
sahilmgandhi	18:6a4db94011d3	680	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
sahilmgandhi	18:6a4db94011d3	681	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
sahilmgandhi	18:6a4db94011d3	682
sahilmgandhi	18:6a4db94011d3	683	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
sahilmgandhi	18:6a4db94011d3	684	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
sahilmgandhi	18:6a4db94011d3	685
sahilmgandhi	18:6a4db94011d3	686	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
sahilmgandhi	18:6a4db94011d3	687	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
sahilmgandhi	18:6a4db94011d3	688
sahilmgandhi	18:6a4db94011d3	689	/* SCB Hard Fault Status Registers Definitions */
sahilmgandhi	18:6a4db94011d3	690	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
sahilmgandhi	18:6a4db94011d3	691	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
sahilmgandhi	18:6a4db94011d3	692
sahilmgandhi	18:6a4db94011d3	693	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
sahilmgandhi	18:6a4db94011d3	694	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
sahilmgandhi	18:6a4db94011d3	695
sahilmgandhi	18:6a4db94011d3	696	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
sahilmgandhi	18:6a4db94011d3	697	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
sahilmgandhi	18:6a4db94011d3	698
sahilmgandhi	18:6a4db94011d3	699	/* SCB Debug Fault Status Register Definitions */
sahilmgandhi	18:6a4db94011d3	700	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
sahilmgandhi	18:6a4db94011d3	701	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
sahilmgandhi	18:6a4db94011d3	702
sahilmgandhi	18:6a4db94011d3	703	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
sahilmgandhi	18:6a4db94011d3	704	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
sahilmgandhi	18:6a4db94011d3	705
sahilmgandhi	18:6a4db94011d3	706	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
sahilmgandhi	18:6a4db94011d3	707	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
sahilmgandhi	18:6a4db94011d3	708
sahilmgandhi	18:6a4db94011d3	709	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
sahilmgandhi	18:6a4db94011d3	710	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
sahilmgandhi	18:6a4db94011d3	711
sahilmgandhi	18:6a4db94011d3	712	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
sahilmgandhi	18:6a4db94011d3	713	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
sahilmgandhi	18:6a4db94011d3	714
sahilmgandhi	18:6a4db94011d3	715	/* Cache Level ID register */
sahilmgandhi	18:6a4db94011d3	716	#define SCB_CLIDR_LOUU_Pos 27 /!< SCB CLIDR: LoUU Position /
sahilmgandhi	18:6a4db94011d3	717	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
sahilmgandhi	18:6a4db94011d3	718
sahilmgandhi	18:6a4db94011d3	719	#define SCB_CLIDR_LOC_Pos 24 /!< SCB CLIDR: LoC Position /
sahilmgandhi	18:6a4db94011d3	720	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /!< SCB CLIDR: LoC Mask /
sahilmgandhi	18:6a4db94011d3	721
sahilmgandhi	18:6a4db94011d3	722	/* Cache Type register */
sahilmgandhi	18:6a4db94011d3	723	#define SCB_CTR_FORMAT_Pos 29 /!< SCB CTR: Format Position /
sahilmgandhi	18:6a4db94011d3	724	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
sahilmgandhi	18:6a4db94011d3	725
sahilmgandhi	18:6a4db94011d3	726	#define SCB_CTR_CWG_Pos 24 /!< SCB CTR: CWG Position /
sahilmgandhi	18:6a4db94011d3	727	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
sahilmgandhi	18:6a4db94011d3	728
sahilmgandhi	18:6a4db94011d3	729	#define SCB_CTR_ERG_Pos 20 /!< SCB CTR: ERG Position /
sahilmgandhi	18:6a4db94011d3	730	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
sahilmgandhi	18:6a4db94011d3	731
sahilmgandhi	18:6a4db94011d3	732	#define SCB_CTR_DMINLINE_Pos 16 /!< SCB CTR: DminLine Position /
sahilmgandhi	18:6a4db94011d3	733	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
sahilmgandhi	18:6a4db94011d3	734
sahilmgandhi	18:6a4db94011d3	735	#define SCB_CTR_IMINLINE_Pos 0 /!< SCB CTR: ImInLine Position /
sahilmgandhi	18:6a4db94011d3	736	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
sahilmgandhi	18:6a4db94011d3	737
sahilmgandhi	18:6a4db94011d3	738	/* Cache Size ID Register */
sahilmgandhi	18:6a4db94011d3	739	#define SCB_CCSIDR_WT_Pos 31 /!< SCB CCSIDR: WT Position /
sahilmgandhi	18:6a4db94011d3	740	#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
sahilmgandhi	18:6a4db94011d3	741
sahilmgandhi	18:6a4db94011d3	742	#define SCB_CCSIDR_WB_Pos 30 /!< SCB CCSIDR: WB Position /
sahilmgandhi	18:6a4db94011d3	743	#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
sahilmgandhi	18:6a4db94011d3	744
sahilmgandhi	18:6a4db94011d3	745	#define SCB_CCSIDR_RA_Pos 29 /!< SCB CCSIDR: RA Position /
sahilmgandhi	18:6a4db94011d3	746	#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
sahilmgandhi	18:6a4db94011d3	747
sahilmgandhi	18:6a4db94011d3	748	#define SCB_CCSIDR_WA_Pos 28 /!< SCB CCSIDR: WA Position /
sahilmgandhi	18:6a4db94011d3	749	#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
sahilmgandhi	18:6a4db94011d3	750
sahilmgandhi	18:6a4db94011d3	751	#define SCB_CCSIDR_NUMSETS_Pos 13 /!< SCB CCSIDR: NumSets Position /
sahilmgandhi	18:6a4db94011d3	752	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
sahilmgandhi	18:6a4db94011d3	753
sahilmgandhi	18:6a4db94011d3	754	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /!< SCB CCSIDR: Associativity Position /
sahilmgandhi	18:6a4db94011d3	755	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
sahilmgandhi	18:6a4db94011d3	756
sahilmgandhi	18:6a4db94011d3	757	#define SCB_CCSIDR_LINESIZE_Pos 0 /!< SCB CCSIDR: LineSize Position /
sahilmgandhi	18:6a4db94011d3	758	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
sahilmgandhi	18:6a4db94011d3	759
sahilmgandhi	18:6a4db94011d3	760	/* Cache Size Selection Register */
sahilmgandhi	18:6a4db94011d3	761	#define SCB_CSSELR_LEVEL_Pos 1 /!< SCB CSSELR: Level Position /
sahilmgandhi	18:6a4db94011d3	762	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
sahilmgandhi	18:6a4db94011d3	763
sahilmgandhi	18:6a4db94011d3	764	#define SCB_CSSELR_IND_Pos 0 /!< SCB CSSELR: InD Position /
sahilmgandhi	18:6a4db94011d3	765	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
sahilmgandhi	18:6a4db94011d3	766
sahilmgandhi	18:6a4db94011d3	767	/* SCB Software Triggered Interrupt Register */
sahilmgandhi	18:6a4db94011d3	768	#define SCB_STIR_INTID_Pos 0 /!< SCB STIR: INTID Position /
sahilmgandhi	18:6a4db94011d3	769	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
sahilmgandhi	18:6a4db94011d3	770
sahilmgandhi	18:6a4db94011d3	771	/* Instruction Tightly-Coupled Memory Control Register*/
sahilmgandhi	18:6a4db94011d3	772	#define SCB_ITCMCR_SZ_Pos 3 /!< SCB ITCMCR: SZ Position /
sahilmgandhi	18:6a4db94011d3	773	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
sahilmgandhi	18:6a4db94011d3	774
sahilmgandhi	18:6a4db94011d3	775	#define SCB_ITCMCR_RETEN_Pos 2 /!< SCB ITCMCR: RETEN Position /
sahilmgandhi	18:6a4db94011d3	776	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
sahilmgandhi	18:6a4db94011d3	777
sahilmgandhi	18:6a4db94011d3	778	#define SCB_ITCMCR_RMW_Pos 1 /!< SCB ITCMCR: RMW Position /
sahilmgandhi	18:6a4db94011d3	779	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
sahilmgandhi	18:6a4db94011d3	780
sahilmgandhi	18:6a4db94011d3	781	#define SCB_ITCMCR_EN_Pos 0 /!< SCB ITCMCR: EN Position /
sahilmgandhi	18:6a4db94011d3	782	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
sahilmgandhi	18:6a4db94011d3	783
sahilmgandhi	18:6a4db94011d3	784	/* Data Tightly-Coupled Memory Control Registers */
sahilmgandhi	18:6a4db94011d3	785	#define SCB_DTCMCR_SZ_Pos 3 /!< SCB DTCMCR: SZ Position /
sahilmgandhi	18:6a4db94011d3	786	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
sahilmgandhi	18:6a4db94011d3	787
sahilmgandhi	18:6a4db94011d3	788	#define SCB_DTCMCR_RETEN_Pos 2 /!< SCB DTCMCR: RETEN Position /
sahilmgandhi	18:6a4db94011d3	789	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
sahilmgandhi	18:6a4db94011d3	790
sahilmgandhi	18:6a4db94011d3	791	#define SCB_DTCMCR_RMW_Pos 1 /!< SCB DTCMCR: RMW Position /
sahilmgandhi	18:6a4db94011d3	792	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
sahilmgandhi	18:6a4db94011d3	793
sahilmgandhi	18:6a4db94011d3	794	#define SCB_DTCMCR_EN_Pos 0 /!< SCB DTCMCR: EN Position /
sahilmgandhi	18:6a4db94011d3	795	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
sahilmgandhi	18:6a4db94011d3	796
sahilmgandhi	18:6a4db94011d3	797	/* AHBP Control Register */
sahilmgandhi	18:6a4db94011d3	798	#define SCB_AHBPCR_SZ_Pos 1 /!< SCB AHBPCR: SZ Position /
sahilmgandhi	18:6a4db94011d3	799	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
sahilmgandhi	18:6a4db94011d3	800
sahilmgandhi	18:6a4db94011d3	801	#define SCB_AHBPCR_EN_Pos 0 /!< SCB AHBPCR: EN Position /
sahilmgandhi	18:6a4db94011d3	802	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
sahilmgandhi	18:6a4db94011d3	803
sahilmgandhi	18:6a4db94011d3	804	/* L1 Cache Control Register */
sahilmgandhi	18:6a4db94011d3	805	#define SCB_CACR_FORCEWT_Pos 2 /!< SCB CACR: FORCEWT Position /
sahilmgandhi	18:6a4db94011d3	806	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
sahilmgandhi	18:6a4db94011d3	807
sahilmgandhi	18:6a4db94011d3	808	#define SCB_CACR_ECCEN_Pos 1 /!< SCB CACR: ECCEN Position /
sahilmgandhi	18:6a4db94011d3	809	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
sahilmgandhi	18:6a4db94011d3	810
sahilmgandhi	18:6a4db94011d3	811	#define SCB_CACR_SIWT_Pos 0 /!< SCB CACR: SIWT Position /
sahilmgandhi	18:6a4db94011d3	812	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
sahilmgandhi	18:6a4db94011d3	813
sahilmgandhi	18:6a4db94011d3	814	/* AHBS control register */
sahilmgandhi	18:6a4db94011d3	815	#define SCB_AHBSCR_INITCOUNT_Pos 11 /!< SCB AHBSCR: INITCOUNT Position /
sahilmgandhi	18:6a4db94011d3	816	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
sahilmgandhi	18:6a4db94011d3	817
sahilmgandhi	18:6a4db94011d3	818	#define SCB_AHBSCR_TPRI_Pos 2 /!< SCB AHBSCR: TPRI Position /
sahilmgandhi	18:6a4db94011d3	819	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
sahilmgandhi	18:6a4db94011d3	820
sahilmgandhi	18:6a4db94011d3	821	#define SCB_AHBSCR_CTL_Pos 0 /!< SCB AHBSCR: CTL Position/
sahilmgandhi	18:6a4db94011d3	822	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
sahilmgandhi	18:6a4db94011d3	823
sahilmgandhi	18:6a4db94011d3	824	/* Auxiliary Bus Fault Status Register */
sahilmgandhi	18:6a4db94011d3	825	#define SCB_ABFSR_AXIMTYPE_Pos 8 /!< SCB ABFSR: AXIMTYPE Position/
sahilmgandhi	18:6a4db94011d3	826	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
sahilmgandhi	18:6a4db94011d3	827
sahilmgandhi	18:6a4db94011d3	828	#define SCB_ABFSR_EPPB_Pos 4 /!< SCB ABFSR: EPPB Position/
sahilmgandhi	18:6a4db94011d3	829	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
sahilmgandhi	18:6a4db94011d3	830
sahilmgandhi	18:6a4db94011d3	831	#define SCB_ABFSR_AXIM_Pos 3 /!< SCB ABFSR: AXIM Position/
sahilmgandhi	18:6a4db94011d3	832	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
sahilmgandhi	18:6a4db94011d3	833
sahilmgandhi	18:6a4db94011d3	834	#define SCB_ABFSR_AHBP_Pos 2 /!< SCB ABFSR: AHBP Position/
sahilmgandhi	18:6a4db94011d3	835	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
sahilmgandhi	18:6a4db94011d3	836
sahilmgandhi	18:6a4db94011d3	837	#define SCB_ABFSR_DTCM_Pos 1 /!< SCB ABFSR: DTCM Position/
sahilmgandhi	18:6a4db94011d3	838	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
sahilmgandhi	18:6a4db94011d3	839
sahilmgandhi	18:6a4db94011d3	840	#define SCB_ABFSR_ITCM_Pos 0 /!< SCB ABFSR: ITCM Position/
sahilmgandhi	18:6a4db94011d3	841	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
sahilmgandhi	18:6a4db94011d3	842
sahilmgandhi	18:6a4db94011d3	843	/@} end of group CMSIS_SCB /
sahilmgandhi	18:6a4db94011d3	844
sahilmgandhi	18:6a4db94011d3	845
sahilmgandhi	18:6a4db94011d3	846	/** \ingroup CMSIS_core_register
sahilmgandhi	18:6a4db94011d3	847	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
sahilmgandhi	18:6a4db94011d3	848	\brief Type definitions for the System Control and ID Register not in the SCB
sahilmgandhi	18:6a4db94011d3	849	@{
sahilmgandhi	18:6a4db94011d3	850	*/
sahilmgandhi	18:6a4db94011d3	851
sahilmgandhi	18:6a4db94011d3	852	/** \brief Structure type to access the System Control and ID Register not in the SCB.
sahilmgandhi	18:6a4db94011d3	853	*/
sahilmgandhi	18:6a4db94011d3	854	typedef struct
sahilmgandhi	18:6a4db94011d3	855	{
sahilmgandhi	18:6a4db94011d3	856	uint32_t RESERVED0[1];
sahilmgandhi	18:6a4db94011d3	857	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
sahilmgandhi	18:6a4db94011d3	858	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
sahilmgandhi	18:6a4db94011d3	859	} SCnSCB_Type;
sahilmgandhi	18:6a4db94011d3	860
sahilmgandhi	18:6a4db94011d3	861	/* Interrupt Controller Type Register Definitions */
sahilmgandhi	18:6a4db94011d3	862	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
sahilmgandhi	18:6a4db94011d3	863	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
sahilmgandhi	18:6a4db94011d3	864
sahilmgandhi	18:6a4db94011d3	865	/* Auxiliary Control Register Definitions */
sahilmgandhi	18:6a4db94011d3	866	#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /!< ACTLR: DISITMATBFLUSH Position /
sahilmgandhi	18:6a4db94011d3	867	#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /!< ACTLR: DISITMATBFLUSH Mask /
sahilmgandhi	18:6a4db94011d3	868
sahilmgandhi	18:6a4db94011d3	869	#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /!< ACTLR: DISRAMODE Position /
sahilmgandhi	18:6a4db94011d3	870	#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /!< ACTLR: DISRAMODE Mask /
sahilmgandhi	18:6a4db94011d3	871
sahilmgandhi	18:6a4db94011d3	872	#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /!< ACTLR: FPEXCODIS Position /
sahilmgandhi	18:6a4db94011d3	873	#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /!< ACTLR: FPEXCODIS Mask /
sahilmgandhi	18:6a4db94011d3	874
sahilmgandhi	18:6a4db94011d3	875	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
sahilmgandhi	18:6a4db94011d3	876	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
sahilmgandhi	18:6a4db94011d3	877
sahilmgandhi	18:6a4db94011d3	878	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
sahilmgandhi	18:6a4db94011d3	879	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
sahilmgandhi	18:6a4db94011d3	880
sahilmgandhi	18:6a4db94011d3	881	/@} end of group CMSIS_SCnotSCB /
sahilmgandhi	18:6a4db94011d3	882
sahilmgandhi	18:6a4db94011d3	883
sahilmgandhi	18:6a4db94011d3	884	/** \ingroup CMSIS_core_register
sahilmgandhi	18:6a4db94011d3	885	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
sahilmgandhi	18:6a4db94011d3	886	\brief Type definitions for the System Timer Registers.
sahilmgandhi	18:6a4db94011d3	887	@{
sahilmgandhi	18:6a4db94011d3	888	*/
sahilmgandhi	18:6a4db94011d3	889
sahilmgandhi	18:6a4db94011d3	890	/** \brief Structure type to access the System Timer (SysTick).
sahilmgandhi	18:6a4db94011d3	891	*/
sahilmgandhi	18:6a4db94011d3	892	typedef struct
sahilmgandhi	18:6a4db94011d3	893	{
sahilmgandhi	18:6a4db94011d3	894	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
sahilmgandhi	18:6a4db94011d3	895	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
sahilmgandhi	18:6a4db94011d3	896	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
sahilmgandhi	18:6a4db94011d3	897	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
sahilmgandhi	18:6a4db94011d3	898	} SysTick_Type;
sahilmgandhi	18:6a4db94011d3	899
sahilmgandhi	18:6a4db94011d3	900	/* SysTick Control / Status Register Definitions */
sahilmgandhi	18:6a4db94011d3	901	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
sahilmgandhi	18:6a4db94011d3	902	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
sahilmgandhi	18:6a4db94011d3	903
sahilmgandhi	18:6a4db94011d3	904	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
sahilmgandhi	18:6a4db94011d3	905	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
sahilmgandhi	18:6a4db94011d3	906
sahilmgandhi	18:6a4db94011d3	907	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
sahilmgandhi	18:6a4db94011d3	908	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
sahilmgandhi	18:6a4db94011d3	909
sahilmgandhi	18:6a4db94011d3	910	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
sahilmgandhi	18:6a4db94011d3	911	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
sahilmgandhi	18:6a4db94011d3	912
sahilmgandhi	18:6a4db94011d3	913	/* SysTick Reload Register Definitions */
sahilmgandhi	18:6a4db94011d3	914	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
sahilmgandhi	18:6a4db94011d3	915	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
sahilmgandhi	18:6a4db94011d3	916
sahilmgandhi	18:6a4db94011d3	917	/* SysTick Current Register Definitions */
sahilmgandhi	18:6a4db94011d3	918	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
sahilmgandhi	18:6a4db94011d3	919	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
sahilmgandhi	18:6a4db94011d3	920
sahilmgandhi	18:6a4db94011d3	921	/* SysTick Calibration Register Definitions */
sahilmgandhi	18:6a4db94011d3	922	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
sahilmgandhi	18:6a4db94011d3	923	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
sahilmgandhi	18:6a4db94011d3	924
sahilmgandhi	18:6a4db94011d3	925	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
sahilmgandhi	18:6a4db94011d3	926	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
sahilmgandhi	18:6a4db94011d3	927
sahilmgandhi	18:6a4db94011d3	928	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
sahilmgandhi	18:6a4db94011d3	929	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
sahilmgandhi	18:6a4db94011d3	930
sahilmgandhi	18:6a4db94011d3	931	/@} end of group CMSIS_SysTick /
sahilmgandhi	18:6a4db94011d3	932
sahilmgandhi	18:6a4db94011d3	933
sahilmgandhi	18:6a4db94011d3	934	/** \ingroup CMSIS_core_register
sahilmgandhi	18:6a4db94011d3	935	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
sahilmgandhi	18:6a4db94011d3	936	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
sahilmgandhi	18:6a4db94011d3	937	@{
sahilmgandhi	18:6a4db94011d3	938	*/
sahilmgandhi	18:6a4db94011d3	939
sahilmgandhi	18:6a4db94011d3	940	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
sahilmgandhi	18:6a4db94011d3	941	*/
sahilmgandhi	18:6a4db94011d3	942	typedef struct
sahilmgandhi	18:6a4db94011d3	943	{
sahilmgandhi	18:6a4db94011d3	944	__O union
sahilmgandhi	18:6a4db94011d3	945	{
sahilmgandhi	18:6a4db94011d3	946	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
sahilmgandhi	18:6a4db94011d3	947	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
sahilmgandhi	18:6a4db94011d3	948	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
sahilmgandhi	18:6a4db94011d3	949	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
sahilmgandhi	18:6a4db94011d3	950	uint32_t RESERVED0[864];
sahilmgandhi	18:6a4db94011d3	951	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
sahilmgandhi	18:6a4db94011d3	952	uint32_t RESERVED1[15];
sahilmgandhi	18:6a4db94011d3	953	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
sahilmgandhi	18:6a4db94011d3	954	uint32_t RESERVED2[15];
sahilmgandhi	18:6a4db94011d3	955	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
sahilmgandhi	18:6a4db94011d3	956	uint32_t RESERVED3[29];
sahilmgandhi	18:6a4db94011d3	957	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
sahilmgandhi	18:6a4db94011d3	958	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
sahilmgandhi	18:6a4db94011d3	959	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
sahilmgandhi	18:6a4db94011d3	960	uint32_t RESERVED4[43];
sahilmgandhi	18:6a4db94011d3	961	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
sahilmgandhi	18:6a4db94011d3	962	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
sahilmgandhi	18:6a4db94011d3	963	uint32_t RESERVED5[6];
sahilmgandhi	18:6a4db94011d3	964	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
sahilmgandhi	18:6a4db94011d3	965	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
sahilmgandhi	18:6a4db94011d3	966	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
sahilmgandhi	18:6a4db94011d3	967	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
sahilmgandhi	18:6a4db94011d3	968	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
sahilmgandhi	18:6a4db94011d3	969	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
sahilmgandhi	18:6a4db94011d3	970	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
sahilmgandhi	18:6a4db94011d3	971	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
sahilmgandhi	18:6a4db94011d3	972	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
sahilmgandhi	18:6a4db94011d3	973	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
sahilmgandhi	18:6a4db94011d3	974	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
sahilmgandhi	18:6a4db94011d3	975	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
sahilmgandhi	18:6a4db94011d3	976	} ITM_Type;
sahilmgandhi	18:6a4db94011d3	977
sahilmgandhi	18:6a4db94011d3	978	/* ITM Trace Privilege Register Definitions */
sahilmgandhi	18:6a4db94011d3	979	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
sahilmgandhi	18:6a4db94011d3	980	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
sahilmgandhi	18:6a4db94011d3	981
sahilmgandhi	18:6a4db94011d3	982	/* ITM Trace Control Register Definitions */
sahilmgandhi	18:6a4db94011d3	983	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
sahilmgandhi	18:6a4db94011d3	984	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
sahilmgandhi	18:6a4db94011d3	985
sahilmgandhi	18:6a4db94011d3	986	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
sahilmgandhi	18:6a4db94011d3	987	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
sahilmgandhi	18:6a4db94011d3	988
sahilmgandhi	18:6a4db94011d3	989	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
sahilmgandhi	18:6a4db94011d3	990	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
sahilmgandhi	18:6a4db94011d3	991
sahilmgandhi	18:6a4db94011d3	992	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
sahilmgandhi	18:6a4db94011d3	993	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
sahilmgandhi	18:6a4db94011d3	994
sahilmgandhi	18:6a4db94011d3	995	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
sahilmgandhi	18:6a4db94011d3	996	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
sahilmgandhi	18:6a4db94011d3	997
sahilmgandhi	18:6a4db94011d3	998	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
sahilmgandhi	18:6a4db94011d3	999	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
sahilmgandhi	18:6a4db94011d3	1000
sahilmgandhi	18:6a4db94011d3	1001	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
sahilmgandhi	18:6a4db94011d3	1002	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
sahilmgandhi	18:6a4db94011d3	1003
sahilmgandhi	18:6a4db94011d3	1004	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
sahilmgandhi	18:6a4db94011d3	1005	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
sahilmgandhi	18:6a4db94011d3	1006
sahilmgandhi	18:6a4db94011d3	1007	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
sahilmgandhi	18:6a4db94011d3	1008	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
sahilmgandhi	18:6a4db94011d3	1009
sahilmgandhi	18:6a4db94011d3	1010	/* ITM Integration Write Register Definitions */
sahilmgandhi	18:6a4db94011d3	1011	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
sahilmgandhi	18:6a4db94011d3	1012	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
sahilmgandhi	18:6a4db94011d3	1013
sahilmgandhi	18:6a4db94011d3	1014	/* ITM Integration Read Register Definitions */
sahilmgandhi	18:6a4db94011d3	1015	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
sahilmgandhi	18:6a4db94011d3	1016	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
sahilmgandhi	18:6a4db94011d3	1017
sahilmgandhi	18:6a4db94011d3	1018	/* ITM Integration Mode Control Register Definitions */
sahilmgandhi	18:6a4db94011d3	1019	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
sahilmgandhi	18:6a4db94011d3	1020	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
sahilmgandhi	18:6a4db94011d3	1021
sahilmgandhi	18:6a4db94011d3	1022	/* ITM Lock Status Register Definitions */
sahilmgandhi	18:6a4db94011d3	1023	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
sahilmgandhi	18:6a4db94011d3	1024	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
sahilmgandhi	18:6a4db94011d3	1025
sahilmgandhi	18:6a4db94011d3	1026	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
sahilmgandhi	18:6a4db94011d3	1027	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
sahilmgandhi	18:6a4db94011d3	1028
sahilmgandhi	18:6a4db94011d3	1029	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
sahilmgandhi	18:6a4db94011d3	1030	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
sahilmgandhi	18:6a4db94011d3	1031
sahilmgandhi	18:6a4db94011d3	1032	/@}/ /* end of group CMSIS_ITM */
sahilmgandhi	18:6a4db94011d3	1033
sahilmgandhi	18:6a4db94011d3	1034
sahilmgandhi	18:6a4db94011d3	1035	/** \ingroup CMSIS_core_register
sahilmgandhi	18:6a4db94011d3	1036	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
sahilmgandhi	18:6a4db94011d3	1037	\brief Type definitions for the Data Watchpoint and Trace (DWT)
sahilmgandhi	18:6a4db94011d3	1038	@{
sahilmgandhi	18:6a4db94011d3	1039	*/
sahilmgandhi	18:6a4db94011d3	1040
sahilmgandhi	18:6a4db94011d3	1041	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
sahilmgandhi	18:6a4db94011d3	1042	*/
sahilmgandhi	18:6a4db94011d3	1043	typedef struct
sahilmgandhi	18:6a4db94011d3	1044	{
sahilmgandhi	18:6a4db94011d3	1045	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
sahilmgandhi	18:6a4db94011d3	1046	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
sahilmgandhi	18:6a4db94011d3	1047	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
sahilmgandhi	18:6a4db94011d3	1048	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
sahilmgandhi	18:6a4db94011d3	1049	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
sahilmgandhi	18:6a4db94011d3	1050	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
sahilmgandhi	18:6a4db94011d3	1051	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
sahilmgandhi	18:6a4db94011d3	1052	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
sahilmgandhi	18:6a4db94011d3	1053	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
sahilmgandhi	18:6a4db94011d3	1054	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
sahilmgandhi	18:6a4db94011d3	1055	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
sahilmgandhi	18:6a4db94011d3	1056	uint32_t RESERVED0[1];
sahilmgandhi	18:6a4db94011d3	1057	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
sahilmgandhi	18:6a4db94011d3	1058	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
sahilmgandhi	18:6a4db94011d3	1059	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
sahilmgandhi	18:6a4db94011d3	1060	uint32_t RESERVED1[1];
sahilmgandhi	18:6a4db94011d3	1061	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
sahilmgandhi	18:6a4db94011d3	1062	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
sahilmgandhi	18:6a4db94011d3	1063	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
sahilmgandhi	18:6a4db94011d3	1064	uint32_t RESERVED2[1];
sahilmgandhi	18:6a4db94011d3	1065	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
sahilmgandhi	18:6a4db94011d3	1066	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
sahilmgandhi	18:6a4db94011d3	1067	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
sahilmgandhi	18:6a4db94011d3	1068	uint32_t RESERVED3[981];
sahilmgandhi	18:6a4db94011d3	1069	__O uint32_t LAR; /!< Offset: 0xFB0 ( W) Lock Access Register /
sahilmgandhi	18:6a4db94011d3	1070	__I uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
sahilmgandhi	18:6a4db94011d3	1071	} DWT_Type;
sahilmgandhi	18:6a4db94011d3	1072
sahilmgandhi	18:6a4db94011d3	1073	/* DWT Control Register Definitions */
sahilmgandhi	18:6a4db94011d3	1074	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
sahilmgandhi	18:6a4db94011d3	1075	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
sahilmgandhi	18:6a4db94011d3	1076
sahilmgandhi	18:6a4db94011d3	1077	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
sahilmgandhi	18:6a4db94011d3	1078	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
sahilmgandhi	18:6a4db94011d3	1079
sahilmgandhi	18:6a4db94011d3	1080	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
sahilmgandhi	18:6a4db94011d3	1081	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
sahilmgandhi	18:6a4db94011d3	1082
sahilmgandhi	18:6a4db94011d3	1083	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
sahilmgandhi	18:6a4db94011d3	1084	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
sahilmgandhi	18:6a4db94011d3	1085
sahilmgandhi	18:6a4db94011d3	1086	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
sahilmgandhi	18:6a4db94011d3	1087	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
sahilmgandhi	18:6a4db94011d3	1088
sahilmgandhi	18:6a4db94011d3	1089	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
sahilmgandhi	18:6a4db94011d3	1090	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
sahilmgandhi	18:6a4db94011d3	1091
sahilmgandhi	18:6a4db94011d3	1092	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
sahilmgandhi	18:6a4db94011d3	1093	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
sahilmgandhi	18:6a4db94011d3	1094
sahilmgandhi	18:6a4db94011d3	1095	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
sahilmgandhi	18:6a4db94011d3	1096	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
sahilmgandhi	18:6a4db94011d3	1097
sahilmgandhi	18:6a4db94011d3	1098	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
sahilmgandhi	18:6a4db94011d3	1099	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
sahilmgandhi	18:6a4db94011d3	1100
sahilmgandhi	18:6a4db94011d3	1101	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
sahilmgandhi	18:6a4db94011d3	1102	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
sahilmgandhi	18:6a4db94011d3	1103
sahilmgandhi	18:6a4db94011d3	1104	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
sahilmgandhi	18:6a4db94011d3	1105	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
sahilmgandhi	18:6a4db94011d3	1106
sahilmgandhi	18:6a4db94011d3	1107	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
sahilmgandhi	18:6a4db94011d3	1108	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
sahilmgandhi	18:6a4db94011d3	1109
sahilmgandhi	18:6a4db94011d3	1110	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
sahilmgandhi	18:6a4db94011d3	1111	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
sahilmgandhi	18:6a4db94011d3	1112
sahilmgandhi	18:6a4db94011d3	1113	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
sahilmgandhi	18:6a4db94011d3	1114	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
sahilmgandhi	18:6a4db94011d3	1115
sahilmgandhi	18:6a4db94011d3	1116	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
sahilmgandhi	18:6a4db94011d3	1117	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
sahilmgandhi	18:6a4db94011d3	1118
sahilmgandhi	18:6a4db94011d3	1119	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
sahilmgandhi	18:6a4db94011d3	1120	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
sahilmgandhi	18:6a4db94011d3	1121
sahilmgandhi	18:6a4db94011d3	1122	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
sahilmgandhi	18:6a4db94011d3	1123	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
sahilmgandhi	18:6a4db94011d3	1124
sahilmgandhi	18:6a4db94011d3	1125	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
sahilmgandhi	18:6a4db94011d3	1126	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
sahilmgandhi	18:6a4db94011d3	1127
sahilmgandhi	18:6a4db94011d3	1128	/* DWT CPI Count Register Definitions */
sahilmgandhi	18:6a4db94011d3	1129	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
sahilmgandhi	18:6a4db94011d3	1130	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
sahilmgandhi	18:6a4db94011d3	1131
sahilmgandhi	18:6a4db94011d3	1132	/* DWT Exception Overhead Count Register Definitions */
sahilmgandhi	18:6a4db94011d3	1133	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
sahilmgandhi	18:6a4db94011d3	1134	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
sahilmgandhi	18:6a4db94011d3	1135
sahilmgandhi	18:6a4db94011d3	1136	/* DWT Sleep Count Register Definitions */
sahilmgandhi	18:6a4db94011d3	1137	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
sahilmgandhi	18:6a4db94011d3	1138	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
sahilmgandhi	18:6a4db94011d3	1139
sahilmgandhi	18:6a4db94011d3	1140	/* DWT LSU Count Register Definitions */
sahilmgandhi	18:6a4db94011d3	1141	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
sahilmgandhi	18:6a4db94011d3	1142	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
sahilmgandhi	18:6a4db94011d3	1143
sahilmgandhi	18:6a4db94011d3	1144	/* DWT Folded-instruction Count Register Definitions */
sahilmgandhi	18:6a4db94011d3	1145	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
sahilmgandhi	18:6a4db94011d3	1146	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
sahilmgandhi	18:6a4db94011d3	1147
sahilmgandhi	18:6a4db94011d3	1148	/* DWT Comparator Mask Register Definitions */
sahilmgandhi	18:6a4db94011d3	1149	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
sahilmgandhi	18:6a4db94011d3	1150	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
sahilmgandhi	18:6a4db94011d3	1151
sahilmgandhi	18:6a4db94011d3	1152	/* DWT Comparator Function Register Definitions */
sahilmgandhi	18:6a4db94011d3	1153	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
sahilmgandhi	18:6a4db94011d3	1154	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
sahilmgandhi	18:6a4db94011d3	1155
sahilmgandhi	18:6a4db94011d3	1156	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
sahilmgandhi	18:6a4db94011d3	1157	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
sahilmgandhi	18:6a4db94011d3	1158
sahilmgandhi	18:6a4db94011d3	1159	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
sahilmgandhi	18:6a4db94011d3	1160	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
sahilmgandhi	18:6a4db94011d3	1161
sahilmgandhi	18:6a4db94011d3	1162	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
sahilmgandhi	18:6a4db94011d3	1163	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
sahilmgandhi	18:6a4db94011d3	1164
sahilmgandhi	18:6a4db94011d3	1165	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
sahilmgandhi	18:6a4db94011d3	1166	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
sahilmgandhi	18:6a4db94011d3	1167
sahilmgandhi	18:6a4db94011d3	1168	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
sahilmgandhi	18:6a4db94011d3	1169	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
sahilmgandhi	18:6a4db94011d3	1170
sahilmgandhi	18:6a4db94011d3	1171	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
sahilmgandhi	18:6a4db94011d3	1172	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
sahilmgandhi	18:6a4db94011d3	1173
sahilmgandhi	18:6a4db94011d3	1174	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
sahilmgandhi	18:6a4db94011d3	1175	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
sahilmgandhi	18:6a4db94011d3	1176
sahilmgandhi	18:6a4db94011d3	1177	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
sahilmgandhi	18:6a4db94011d3	1178	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
sahilmgandhi	18:6a4db94011d3	1179
sahilmgandhi	18:6a4db94011d3	1180	/@}/ /* end of group CMSIS_DWT */
sahilmgandhi	18:6a4db94011d3	1181
sahilmgandhi	18:6a4db94011d3	1182
sahilmgandhi	18:6a4db94011d3	1183	/** \ingroup CMSIS_core_register
sahilmgandhi	18:6a4db94011d3	1184	\defgroup CMSIS_TPI Trace Port Interface (TPI)
sahilmgandhi	18:6a4db94011d3	1185	\brief Type definitions for the Trace Port Interface (TPI)
sahilmgandhi	18:6a4db94011d3	1186	@{
sahilmgandhi	18:6a4db94011d3	1187	*/
sahilmgandhi	18:6a4db94011d3	1188
sahilmgandhi	18:6a4db94011d3	1189	/** \brief Structure type to access the Trace Port Interface Register (TPI).
sahilmgandhi	18:6a4db94011d3	1190	*/
sahilmgandhi	18:6a4db94011d3	1191	typedef struct
sahilmgandhi	18:6a4db94011d3	1192	{
sahilmgandhi	18:6a4db94011d3	1193	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
sahilmgandhi	18:6a4db94011d3	1194	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
sahilmgandhi	18:6a4db94011d3	1195	uint32_t RESERVED0[2];
sahilmgandhi	18:6a4db94011d3	1196	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
sahilmgandhi	18:6a4db94011d3	1197	uint32_t RESERVED1[55];
sahilmgandhi	18:6a4db94011d3	1198	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
sahilmgandhi	18:6a4db94011d3	1199	uint32_t RESERVED2[131];
sahilmgandhi	18:6a4db94011d3	1200	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
sahilmgandhi	18:6a4db94011d3	1201	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
sahilmgandhi	18:6a4db94011d3	1202	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
sahilmgandhi	18:6a4db94011d3	1203	uint32_t RESERVED3[759];
sahilmgandhi	18:6a4db94011d3	1204	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
sahilmgandhi	18:6a4db94011d3	1205	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
sahilmgandhi	18:6a4db94011d3	1206	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
sahilmgandhi	18:6a4db94011d3	1207	uint32_t RESERVED4[1];
sahilmgandhi	18:6a4db94011d3	1208	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
sahilmgandhi	18:6a4db94011d3	1209	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
sahilmgandhi	18:6a4db94011d3	1210	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
sahilmgandhi	18:6a4db94011d3	1211	uint32_t RESERVED5[39];
sahilmgandhi	18:6a4db94011d3	1212	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
sahilmgandhi	18:6a4db94011d3	1213	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
sahilmgandhi	18:6a4db94011d3	1214	uint32_t RESERVED7[8];
sahilmgandhi	18:6a4db94011d3	1215	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
sahilmgandhi	18:6a4db94011d3	1216	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
sahilmgandhi	18:6a4db94011d3	1217	} TPI_Type;
sahilmgandhi	18:6a4db94011d3	1218
sahilmgandhi	18:6a4db94011d3	1219	/* TPI Asynchronous Clock Prescaler Register Definitions */
sahilmgandhi	18:6a4db94011d3	1220	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
sahilmgandhi	18:6a4db94011d3	1221	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
sahilmgandhi	18:6a4db94011d3	1222
sahilmgandhi	18:6a4db94011d3	1223	/* TPI Selected Pin Protocol Register Definitions */
sahilmgandhi	18:6a4db94011d3	1224	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
sahilmgandhi	18:6a4db94011d3	1225	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
sahilmgandhi	18:6a4db94011d3	1226
sahilmgandhi	18:6a4db94011d3	1227	/* TPI Formatter and Flush Status Register Definitions */
sahilmgandhi	18:6a4db94011d3	1228	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
sahilmgandhi	18:6a4db94011d3	1229	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
sahilmgandhi	18:6a4db94011d3	1230
sahilmgandhi	18:6a4db94011d3	1231	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
sahilmgandhi	18:6a4db94011d3	1232	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
sahilmgandhi	18:6a4db94011d3	1233
sahilmgandhi	18:6a4db94011d3	1234	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
sahilmgandhi	18:6a4db94011d3	1235	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
sahilmgandhi	18:6a4db94011d3	1236
sahilmgandhi	18:6a4db94011d3	1237	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
sahilmgandhi	18:6a4db94011d3	1238	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
sahilmgandhi	18:6a4db94011d3	1239
sahilmgandhi	18:6a4db94011d3	1240	/* TPI Formatter and Flush Control Register Definitions */
sahilmgandhi	18:6a4db94011d3	1241	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
sahilmgandhi	18:6a4db94011d3	1242	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
sahilmgandhi	18:6a4db94011d3	1243
sahilmgandhi	18:6a4db94011d3	1244	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
sahilmgandhi	18:6a4db94011d3	1245	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
sahilmgandhi	18:6a4db94011d3	1246
sahilmgandhi	18:6a4db94011d3	1247	/* TPI TRIGGER Register Definitions */
sahilmgandhi	18:6a4db94011d3	1248	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
sahilmgandhi	18:6a4db94011d3	1249	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
sahilmgandhi	18:6a4db94011d3	1250
sahilmgandhi	18:6a4db94011d3	1251	/* TPI Integration ETM Data Register Definitions (FIFO0) */
sahilmgandhi	18:6a4db94011d3	1252	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
sahilmgandhi	18:6a4db94011d3	1253	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
sahilmgandhi	18:6a4db94011d3	1254
sahilmgandhi	18:6a4db94011d3	1255	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
sahilmgandhi	18:6a4db94011d3	1256	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
sahilmgandhi	18:6a4db94011d3	1257
sahilmgandhi	18:6a4db94011d3	1258	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
sahilmgandhi	18:6a4db94011d3	1259	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
sahilmgandhi	18:6a4db94011d3	1260
sahilmgandhi	18:6a4db94011d3	1261	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
sahilmgandhi	18:6a4db94011d3	1262	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
sahilmgandhi	18:6a4db94011d3	1263
sahilmgandhi	18:6a4db94011d3	1264	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
sahilmgandhi	18:6a4db94011d3	1265	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
sahilmgandhi	18:6a4db94011d3	1266
sahilmgandhi	18:6a4db94011d3	1267	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
sahilmgandhi	18:6a4db94011d3	1268	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
sahilmgandhi	18:6a4db94011d3	1269
sahilmgandhi	18:6a4db94011d3	1270	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
sahilmgandhi	18:6a4db94011d3	1271	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
sahilmgandhi	18:6a4db94011d3	1272
sahilmgandhi	18:6a4db94011d3	1273	/* TPI ITATBCTR2 Register Definitions */
sahilmgandhi	18:6a4db94011d3	1274	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
sahilmgandhi	18:6a4db94011d3	1275	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
sahilmgandhi	18:6a4db94011d3	1276
sahilmgandhi	18:6a4db94011d3	1277	/* TPI Integration ITM Data Register Definitions (FIFO1) */
sahilmgandhi	18:6a4db94011d3	1278	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
sahilmgandhi	18:6a4db94011d3	1279	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
sahilmgandhi	18:6a4db94011d3	1280
sahilmgandhi	18:6a4db94011d3	1281	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
sahilmgandhi	18:6a4db94011d3	1282	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
sahilmgandhi	18:6a4db94011d3	1283
sahilmgandhi	18:6a4db94011d3	1284	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
sahilmgandhi	18:6a4db94011d3	1285	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
sahilmgandhi	18:6a4db94011d3	1286
sahilmgandhi	18:6a4db94011d3	1287	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
sahilmgandhi	18:6a4db94011d3	1288	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
sahilmgandhi	18:6a4db94011d3	1289
sahilmgandhi	18:6a4db94011d3	1290	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
sahilmgandhi	18:6a4db94011d3	1291	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
sahilmgandhi	18:6a4db94011d3	1292
sahilmgandhi	18:6a4db94011d3	1293	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
sahilmgandhi	18:6a4db94011d3	1294	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
sahilmgandhi	18:6a4db94011d3	1295
sahilmgandhi	18:6a4db94011d3	1296	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
sahilmgandhi	18:6a4db94011d3	1297	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
sahilmgandhi	18:6a4db94011d3	1298
sahilmgandhi	18:6a4db94011d3	1299	/* TPI ITATBCTR0 Register Definitions */
sahilmgandhi	18:6a4db94011d3	1300	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
sahilmgandhi	18:6a4db94011d3	1301	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
sahilmgandhi	18:6a4db94011d3	1302
sahilmgandhi	18:6a4db94011d3	1303	/* TPI Integration Mode Control Register Definitions */
sahilmgandhi	18:6a4db94011d3	1304	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
sahilmgandhi	18:6a4db94011d3	1305	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
sahilmgandhi	18:6a4db94011d3	1306
sahilmgandhi	18:6a4db94011d3	1307	/* TPI DEVID Register Definitions */
sahilmgandhi	18:6a4db94011d3	1308	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
sahilmgandhi	18:6a4db94011d3	1309	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
sahilmgandhi	18:6a4db94011d3	1310
sahilmgandhi	18:6a4db94011d3	1311	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
sahilmgandhi	18:6a4db94011d3	1312	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
sahilmgandhi	18:6a4db94011d3	1313
sahilmgandhi	18:6a4db94011d3	1314	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
sahilmgandhi	18:6a4db94011d3	1315	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
sahilmgandhi	18:6a4db94011d3	1316
sahilmgandhi	18:6a4db94011d3	1317	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
sahilmgandhi	18:6a4db94011d3	1318	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
sahilmgandhi	18:6a4db94011d3	1319
sahilmgandhi	18:6a4db94011d3	1320	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
sahilmgandhi	18:6a4db94011d3	1321	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
sahilmgandhi	18:6a4db94011d3	1322
sahilmgandhi	18:6a4db94011d3	1323	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
sahilmgandhi	18:6a4db94011d3	1324	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
sahilmgandhi	18:6a4db94011d3	1325
sahilmgandhi	18:6a4db94011d3	1326	/* TPI DEVTYPE Register Definitions */
sahilmgandhi	18:6a4db94011d3	1327	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
sahilmgandhi	18:6a4db94011d3	1328	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
sahilmgandhi	18:6a4db94011d3	1329
sahilmgandhi	18:6a4db94011d3	1330	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
sahilmgandhi	18:6a4db94011d3	1331	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
sahilmgandhi	18:6a4db94011d3	1332
sahilmgandhi	18:6a4db94011d3	1333	/@}/ /* end of group CMSIS_TPI */
sahilmgandhi	18:6a4db94011d3	1334
sahilmgandhi	18:6a4db94011d3	1335
sahilmgandhi	18:6a4db94011d3	1336	#if (__MPU_PRESENT == 1)
sahilmgandhi	18:6a4db94011d3	1337	/** \ingroup CMSIS_core_register
sahilmgandhi	18:6a4db94011d3	1338	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
sahilmgandhi	18:6a4db94011d3	1339	\brief Type definitions for the Memory Protection Unit (MPU)
sahilmgandhi	18:6a4db94011d3	1340	@{
sahilmgandhi	18:6a4db94011d3	1341	*/
sahilmgandhi	18:6a4db94011d3	1342
sahilmgandhi	18:6a4db94011d3	1343	/** \brief Structure type to access the Memory Protection Unit (MPU).
sahilmgandhi	18:6a4db94011d3	1344	*/
sahilmgandhi	18:6a4db94011d3	1345	typedef struct
sahilmgandhi	18:6a4db94011d3	1346	{
sahilmgandhi	18:6a4db94011d3	1347	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
sahilmgandhi	18:6a4db94011d3	1348	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
sahilmgandhi	18:6a4db94011d3	1349	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
sahilmgandhi	18:6a4db94011d3	1350	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
sahilmgandhi	18:6a4db94011d3	1351	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
sahilmgandhi	18:6a4db94011d3	1352	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
sahilmgandhi	18:6a4db94011d3	1353	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
sahilmgandhi	18:6a4db94011d3	1354	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
sahilmgandhi	18:6a4db94011d3	1355	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
sahilmgandhi	18:6a4db94011d3	1356	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
sahilmgandhi	18:6a4db94011d3	1357	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
sahilmgandhi	18:6a4db94011d3	1358	} MPU_Type;
sahilmgandhi	18:6a4db94011d3	1359
sahilmgandhi	18:6a4db94011d3	1360	/* MPU Type Register */
sahilmgandhi	18:6a4db94011d3	1361	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
sahilmgandhi	18:6a4db94011d3	1362	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
sahilmgandhi	18:6a4db94011d3	1363
sahilmgandhi	18:6a4db94011d3	1364	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
sahilmgandhi	18:6a4db94011d3	1365	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
sahilmgandhi	18:6a4db94011d3	1366
sahilmgandhi	18:6a4db94011d3	1367	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
sahilmgandhi	18:6a4db94011d3	1368	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
sahilmgandhi	18:6a4db94011d3	1369
sahilmgandhi	18:6a4db94011d3	1370	/* MPU Control Register */
sahilmgandhi	18:6a4db94011d3	1371	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
sahilmgandhi	18:6a4db94011d3	1372	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
sahilmgandhi	18:6a4db94011d3	1373
sahilmgandhi	18:6a4db94011d3	1374	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
sahilmgandhi	18:6a4db94011d3	1375	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
sahilmgandhi	18:6a4db94011d3	1376
sahilmgandhi	18:6a4db94011d3	1377	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
sahilmgandhi	18:6a4db94011d3	1378	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
sahilmgandhi	18:6a4db94011d3	1379
sahilmgandhi	18:6a4db94011d3	1380	/* MPU Region Number Register */
sahilmgandhi	18:6a4db94011d3	1381	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
sahilmgandhi	18:6a4db94011d3	1382	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
sahilmgandhi	18:6a4db94011d3	1383
sahilmgandhi	18:6a4db94011d3	1384	/* MPU Region Base Address Register */
sahilmgandhi	18:6a4db94011d3	1385	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
sahilmgandhi	18:6a4db94011d3	1386	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
sahilmgandhi	18:6a4db94011d3	1387
sahilmgandhi	18:6a4db94011d3	1388	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
sahilmgandhi	18:6a4db94011d3	1389	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
sahilmgandhi	18:6a4db94011d3	1390
sahilmgandhi	18:6a4db94011d3	1391	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
sahilmgandhi	18:6a4db94011d3	1392	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
sahilmgandhi	18:6a4db94011d3	1393
sahilmgandhi	18:6a4db94011d3	1394	/* MPU Region Attribute and Size Register */
sahilmgandhi	18:6a4db94011d3	1395	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
sahilmgandhi	18:6a4db94011d3	1396	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
sahilmgandhi	18:6a4db94011d3	1397
sahilmgandhi	18:6a4db94011d3	1398	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
sahilmgandhi	18:6a4db94011d3	1399	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
sahilmgandhi	18:6a4db94011d3	1400
sahilmgandhi	18:6a4db94011d3	1401	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
sahilmgandhi	18:6a4db94011d3	1402	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
sahilmgandhi	18:6a4db94011d3	1403
sahilmgandhi	18:6a4db94011d3	1404	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
sahilmgandhi	18:6a4db94011d3	1405	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
sahilmgandhi	18:6a4db94011d3	1406
sahilmgandhi	18:6a4db94011d3	1407	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
sahilmgandhi	18:6a4db94011d3	1408	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
sahilmgandhi	18:6a4db94011d3	1409
sahilmgandhi	18:6a4db94011d3	1410	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
sahilmgandhi	18:6a4db94011d3	1411	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
sahilmgandhi	18:6a4db94011d3	1412
sahilmgandhi	18:6a4db94011d3	1413	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
sahilmgandhi	18:6a4db94011d3	1414	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
sahilmgandhi	18:6a4db94011d3	1415
sahilmgandhi	18:6a4db94011d3	1416	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
sahilmgandhi	18:6a4db94011d3	1417	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
sahilmgandhi	18:6a4db94011d3	1418
sahilmgandhi	18:6a4db94011d3	1419	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
sahilmgandhi	18:6a4db94011d3	1420	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
sahilmgandhi	18:6a4db94011d3	1421
sahilmgandhi	18:6a4db94011d3	1422	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
sahilmgandhi	18:6a4db94011d3	1423	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
sahilmgandhi	18:6a4db94011d3	1424
sahilmgandhi	18:6a4db94011d3	1425	/@} end of group CMSIS_MPU /
sahilmgandhi	18:6a4db94011d3	1426	#endif
sahilmgandhi	18:6a4db94011d3	1427
sahilmgandhi	18:6a4db94011d3	1428
sahilmgandhi	18:6a4db94011d3	1429	#if (__FPU_PRESENT == 1)
sahilmgandhi	18:6a4db94011d3	1430	/** \ingroup CMSIS_core_register
sahilmgandhi	18:6a4db94011d3	1431	\defgroup CMSIS_FPU Floating Point Unit (FPU)
sahilmgandhi	18:6a4db94011d3	1432	\brief Type definitions for the Floating Point Unit (FPU)
sahilmgandhi	18:6a4db94011d3	1433	@{
sahilmgandhi	18:6a4db94011d3	1434	*/
sahilmgandhi	18:6a4db94011d3	1435
sahilmgandhi	18:6a4db94011d3	1436	/** \brief Structure type to access the Floating Point Unit (FPU).
sahilmgandhi	18:6a4db94011d3	1437	*/
sahilmgandhi	18:6a4db94011d3	1438	typedef struct
sahilmgandhi	18:6a4db94011d3	1439	{
sahilmgandhi	18:6a4db94011d3	1440	uint32_t RESERVED0[1];
sahilmgandhi	18:6a4db94011d3	1441	__IO uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
sahilmgandhi	18:6a4db94011d3	1442	__IO uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
sahilmgandhi	18:6a4db94011d3	1443	__IO uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
sahilmgandhi	18:6a4db94011d3	1444	__I uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
sahilmgandhi	18:6a4db94011d3	1445	__I uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
sahilmgandhi	18:6a4db94011d3	1446	__I uint32_t MVFR2; /!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 /
sahilmgandhi	18:6a4db94011d3	1447	} FPU_Type;
sahilmgandhi	18:6a4db94011d3	1448
sahilmgandhi	18:6a4db94011d3	1449	/* Floating-Point Context Control Register */
sahilmgandhi	18:6a4db94011d3	1450	#define FPU_FPCCR_ASPEN_Pos 31 /!< FPCCR: ASPEN bit Position /
sahilmgandhi	18:6a4db94011d3	1451	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
sahilmgandhi	18:6a4db94011d3	1452
sahilmgandhi	18:6a4db94011d3	1453	#define FPU_FPCCR_LSPEN_Pos 30 /!< FPCCR: LSPEN Position /
sahilmgandhi	18:6a4db94011d3	1454	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
sahilmgandhi	18:6a4db94011d3	1455
sahilmgandhi	18:6a4db94011d3	1456	#define FPU_FPCCR_MONRDY_Pos 8 /!< FPCCR: MONRDY Position /
sahilmgandhi	18:6a4db94011d3	1457	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
sahilmgandhi	18:6a4db94011d3	1458
sahilmgandhi	18:6a4db94011d3	1459	#define FPU_FPCCR_BFRDY_Pos 6 /!< FPCCR: BFRDY Position /
sahilmgandhi	18:6a4db94011d3	1460	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
sahilmgandhi	18:6a4db94011d3	1461
sahilmgandhi	18:6a4db94011d3	1462	#define FPU_FPCCR_MMRDY_Pos 5 /!< FPCCR: MMRDY Position /
sahilmgandhi	18:6a4db94011d3	1463	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
sahilmgandhi	18:6a4db94011d3	1464
sahilmgandhi	18:6a4db94011d3	1465	#define FPU_FPCCR_HFRDY_Pos 4 /!< FPCCR: HFRDY Position /
sahilmgandhi	18:6a4db94011d3	1466	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
sahilmgandhi	18:6a4db94011d3	1467
sahilmgandhi	18:6a4db94011d3	1468	#define FPU_FPCCR_THREAD_Pos 3 /!< FPCCR: processor mode bit Position /
sahilmgandhi	18:6a4db94011d3	1469	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
sahilmgandhi	18:6a4db94011d3	1470
sahilmgandhi	18:6a4db94011d3	1471	#define FPU_FPCCR_USER_Pos 1 /!< FPCCR: privilege level bit Position /
sahilmgandhi	18:6a4db94011d3	1472	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
sahilmgandhi	18:6a4db94011d3	1473
sahilmgandhi	18:6a4db94011d3	1474	#define FPU_FPCCR_LSPACT_Pos 0 /!< FPCCR: Lazy state preservation active bit Position /
sahilmgandhi	18:6a4db94011d3	1475	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
sahilmgandhi	18:6a4db94011d3	1476
sahilmgandhi	18:6a4db94011d3	1477	/* Floating-Point Context Address Register */
sahilmgandhi	18:6a4db94011d3	1478	#define FPU_FPCAR_ADDRESS_Pos 3 /!< FPCAR: ADDRESS bit Position /
sahilmgandhi	18:6a4db94011d3	1479	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
sahilmgandhi	18:6a4db94011d3	1480
sahilmgandhi	18:6a4db94011d3	1481	/* Floating-Point Default Status Control Register */
sahilmgandhi	18:6a4db94011d3	1482	#define FPU_FPDSCR_AHP_Pos 26 /!< FPDSCR: AHP bit Position /
sahilmgandhi	18:6a4db94011d3	1483	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
sahilmgandhi	18:6a4db94011d3	1484
sahilmgandhi	18:6a4db94011d3	1485	#define FPU_FPDSCR_DN_Pos 25 /!< FPDSCR: DN bit Position /
sahilmgandhi	18:6a4db94011d3	1486	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
sahilmgandhi	18:6a4db94011d3	1487
sahilmgandhi	18:6a4db94011d3	1488	#define FPU_FPDSCR_FZ_Pos 24 /!< FPDSCR: FZ bit Position /
sahilmgandhi	18:6a4db94011d3	1489	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
sahilmgandhi	18:6a4db94011d3	1490
sahilmgandhi	18:6a4db94011d3	1491	#define FPU_FPDSCR_RMode_Pos 22 /!< FPDSCR: RMode bit Position /
sahilmgandhi	18:6a4db94011d3	1492	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
sahilmgandhi	18:6a4db94011d3	1493
sahilmgandhi	18:6a4db94011d3	1494	/* Media and FP Feature Register 0 */
sahilmgandhi	18:6a4db94011d3	1495	#define FPU_MVFR0_FP_rounding_modes_Pos 28 /!< MVFR0: FP rounding modes bits Position /
sahilmgandhi	18:6a4db94011d3	1496	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
sahilmgandhi	18:6a4db94011d3	1497
sahilmgandhi	18:6a4db94011d3	1498	#define FPU_MVFR0_Short_vectors_Pos 24 /!< MVFR0: Short vectors bits Position /
sahilmgandhi	18:6a4db94011d3	1499	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
sahilmgandhi	18:6a4db94011d3	1500
sahilmgandhi	18:6a4db94011d3	1501	#define FPU_MVFR0_Square_root_Pos 20 /!< MVFR0: Square root bits Position /
sahilmgandhi	18:6a4db94011d3	1502	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
sahilmgandhi	18:6a4db94011d3	1503
sahilmgandhi	18:6a4db94011d3	1504	#define FPU_MVFR0_Divide_Pos 16 /!< MVFR0: Divide bits Position /
sahilmgandhi	18:6a4db94011d3	1505	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
sahilmgandhi	18:6a4db94011d3	1506
sahilmgandhi	18:6a4db94011d3	1507	#define FPU_MVFR0_FP_excep_trapping_Pos 12 /!< MVFR0: FP exception trapping bits Position /
sahilmgandhi	18:6a4db94011d3	1508	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
sahilmgandhi	18:6a4db94011d3	1509
sahilmgandhi	18:6a4db94011d3	1510	#define FPU_MVFR0_Double_precision_Pos 8 /!< MVFR0: Double-precision bits Position /
sahilmgandhi	18:6a4db94011d3	1511	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
sahilmgandhi	18:6a4db94011d3	1512
sahilmgandhi	18:6a4db94011d3	1513	#define FPU_MVFR0_Single_precision_Pos 4 /!< MVFR0: Single-precision bits Position /
sahilmgandhi	18:6a4db94011d3	1514	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
sahilmgandhi	18:6a4db94011d3	1515
sahilmgandhi	18:6a4db94011d3	1516	#define FPU_MVFR0_A_SIMD_registers_Pos 0 /!< MVFR0: A_SIMD registers bits Position /
sahilmgandhi	18:6a4db94011d3	1517	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
sahilmgandhi	18:6a4db94011d3	1518
sahilmgandhi	18:6a4db94011d3	1519	/* Media and FP Feature Register 1 */
sahilmgandhi	18:6a4db94011d3	1520	#define FPU_MVFR1_FP_fused_MAC_Pos 28 /!< MVFR1: FP fused MAC bits Position /
sahilmgandhi	18:6a4db94011d3	1521	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
sahilmgandhi	18:6a4db94011d3	1522
sahilmgandhi	18:6a4db94011d3	1523	#define FPU_MVFR1_FP_HPFP_Pos 24 /!< MVFR1: FP HPFP bits Position /
sahilmgandhi	18:6a4db94011d3	1524	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
sahilmgandhi	18:6a4db94011d3	1525
sahilmgandhi	18:6a4db94011d3	1526	#define FPU_MVFR1_D_NaN_mode_Pos 4 /!< MVFR1: D_NaN mode bits Position /
sahilmgandhi	18:6a4db94011d3	1527	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
sahilmgandhi	18:6a4db94011d3	1528
sahilmgandhi	18:6a4db94011d3	1529	#define FPU_MVFR1_FtZ_mode_Pos 0 /!< MVFR1: FtZ mode bits Position /
sahilmgandhi	18:6a4db94011d3	1530	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
sahilmgandhi	18:6a4db94011d3	1531
sahilmgandhi	18:6a4db94011d3	1532	/* Media and FP Feature Register 2 */
sahilmgandhi	18:6a4db94011d3	1533
sahilmgandhi	18:6a4db94011d3	1534	/@} end of group CMSIS_FPU /
sahilmgandhi	18:6a4db94011d3	1535	#endif
sahilmgandhi	18:6a4db94011d3	1536
sahilmgandhi	18:6a4db94011d3	1537
sahilmgandhi	18:6a4db94011d3	1538	/** \ingroup CMSIS_core_register
sahilmgandhi	18:6a4db94011d3	1539	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
sahilmgandhi	18:6a4db94011d3	1540	\brief Type definitions for the Core Debug Registers
sahilmgandhi	18:6a4db94011d3	1541	@{
sahilmgandhi	18:6a4db94011d3	1542	*/
sahilmgandhi	18:6a4db94011d3	1543
sahilmgandhi	18:6a4db94011d3	1544	/** \brief Structure type to access the Core Debug Register (CoreDebug).
sahilmgandhi	18:6a4db94011d3	1545	*/
sahilmgandhi	18:6a4db94011d3	1546	typedef struct
sahilmgandhi	18:6a4db94011d3	1547	{
sahilmgandhi	18:6a4db94011d3	1548	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
sahilmgandhi	18:6a4db94011d3	1549	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
sahilmgandhi	18:6a4db94011d3	1550	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
sahilmgandhi	18:6a4db94011d3	1551	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
sahilmgandhi	18:6a4db94011d3	1552	} CoreDebug_Type;
sahilmgandhi	18:6a4db94011d3	1553
sahilmgandhi	18:6a4db94011d3	1554	/* Debug Halting Control and Status Register */
sahilmgandhi	18:6a4db94011d3	1555	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
sahilmgandhi	18:6a4db94011d3	1556	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
sahilmgandhi	18:6a4db94011d3	1557
sahilmgandhi	18:6a4db94011d3	1558	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
sahilmgandhi	18:6a4db94011d3	1559	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
sahilmgandhi	18:6a4db94011d3	1560
sahilmgandhi	18:6a4db94011d3	1561	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
sahilmgandhi	18:6a4db94011d3	1562	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
sahilmgandhi	18:6a4db94011d3	1563
sahilmgandhi	18:6a4db94011d3	1564	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
sahilmgandhi	18:6a4db94011d3	1565	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
sahilmgandhi	18:6a4db94011d3	1566
sahilmgandhi	18:6a4db94011d3	1567	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
sahilmgandhi	18:6a4db94011d3	1568	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
sahilmgandhi	18:6a4db94011d3	1569
sahilmgandhi	18:6a4db94011d3	1570	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
sahilmgandhi	18:6a4db94011d3	1571	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
sahilmgandhi	18:6a4db94011d3	1572
sahilmgandhi	18:6a4db94011d3	1573	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
sahilmgandhi	18:6a4db94011d3	1574	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
sahilmgandhi	18:6a4db94011d3	1575
sahilmgandhi	18:6a4db94011d3	1576	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
sahilmgandhi	18:6a4db94011d3	1577	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
sahilmgandhi	18:6a4db94011d3	1578
sahilmgandhi	18:6a4db94011d3	1579	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
sahilmgandhi	18:6a4db94011d3	1580	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
sahilmgandhi	18:6a4db94011d3	1581
sahilmgandhi	18:6a4db94011d3	1582	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
sahilmgandhi	18:6a4db94011d3	1583	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
sahilmgandhi	18:6a4db94011d3	1584
sahilmgandhi	18:6a4db94011d3	1585	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
sahilmgandhi	18:6a4db94011d3	1586	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
sahilmgandhi	18:6a4db94011d3	1587
sahilmgandhi	18:6a4db94011d3	1588	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
sahilmgandhi	18:6a4db94011d3	1589	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
sahilmgandhi	18:6a4db94011d3	1590
sahilmgandhi	18:6a4db94011d3	1591	/* Debug Core Register Selector Register */
sahilmgandhi	18:6a4db94011d3	1592	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
sahilmgandhi	18:6a4db94011d3	1593	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
sahilmgandhi	18:6a4db94011d3	1594
sahilmgandhi	18:6a4db94011d3	1595	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
sahilmgandhi	18:6a4db94011d3	1596	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
sahilmgandhi	18:6a4db94011d3	1597
sahilmgandhi	18:6a4db94011d3	1598	/* Debug Exception and Monitor Control Register */
sahilmgandhi	18:6a4db94011d3	1599	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
sahilmgandhi	18:6a4db94011d3	1600	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
sahilmgandhi	18:6a4db94011d3	1601
sahilmgandhi	18:6a4db94011d3	1602	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
sahilmgandhi	18:6a4db94011d3	1603	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
sahilmgandhi	18:6a4db94011d3	1604
sahilmgandhi	18:6a4db94011d3	1605	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
sahilmgandhi	18:6a4db94011d3	1606	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
sahilmgandhi	18:6a4db94011d3	1607
sahilmgandhi	18:6a4db94011d3	1608	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
sahilmgandhi	18:6a4db94011d3	1609	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
sahilmgandhi	18:6a4db94011d3	1610
sahilmgandhi	18:6a4db94011d3	1611	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
sahilmgandhi	18:6a4db94011d3	1612	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
sahilmgandhi	18:6a4db94011d3	1613
sahilmgandhi	18:6a4db94011d3	1614	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
sahilmgandhi	18:6a4db94011d3	1615	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
sahilmgandhi	18:6a4db94011d3	1616
sahilmgandhi	18:6a4db94011d3	1617	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
sahilmgandhi	18:6a4db94011d3	1618	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
sahilmgandhi	18:6a4db94011d3	1619
sahilmgandhi	18:6a4db94011d3	1620	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
sahilmgandhi	18:6a4db94011d3	1621	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
sahilmgandhi	18:6a4db94011d3	1622
sahilmgandhi	18:6a4db94011d3	1623	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
sahilmgandhi	18:6a4db94011d3	1624	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
sahilmgandhi	18:6a4db94011d3	1625
sahilmgandhi	18:6a4db94011d3	1626	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
sahilmgandhi	18:6a4db94011d3	1627	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
sahilmgandhi	18:6a4db94011d3	1628
sahilmgandhi	18:6a4db94011d3	1629	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
sahilmgandhi	18:6a4db94011d3	1630	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
sahilmgandhi	18:6a4db94011d3	1631
sahilmgandhi	18:6a4db94011d3	1632	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
sahilmgandhi	18:6a4db94011d3	1633	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
sahilmgandhi	18:6a4db94011d3	1634
sahilmgandhi	18:6a4db94011d3	1635	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
sahilmgandhi	18:6a4db94011d3	1636	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
sahilmgandhi	18:6a4db94011d3	1637
sahilmgandhi	18:6a4db94011d3	1638	/@} end of group CMSIS_CoreDebug /
sahilmgandhi	18:6a4db94011d3	1639
sahilmgandhi	18:6a4db94011d3	1640
sahilmgandhi	18:6a4db94011d3	1641	/** \ingroup CMSIS_core_register
sahilmgandhi	18:6a4db94011d3	1642	\defgroup CMSIS_core_base Core Definitions
sahilmgandhi	18:6a4db94011d3	1643	\brief Definitions for base addresses, unions, and structures.
sahilmgandhi	18:6a4db94011d3	1644	@{
sahilmgandhi	18:6a4db94011d3	1645	*/
sahilmgandhi	18:6a4db94011d3	1646
sahilmgandhi	18:6a4db94011d3	1647	/* Memory mapping of Cortex-M4 Hardware */
sahilmgandhi	18:6a4db94011d3	1648	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
sahilmgandhi	18:6a4db94011d3	1649	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
sahilmgandhi	18:6a4db94011d3	1650	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
sahilmgandhi	18:6a4db94011d3	1651	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
sahilmgandhi	18:6a4db94011d3	1652	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
sahilmgandhi	18:6a4db94011d3	1653	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
sahilmgandhi	18:6a4db94011d3	1654	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
sahilmgandhi	18:6a4db94011d3	1655	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
sahilmgandhi	18:6a4db94011d3	1656
sahilmgandhi	18:6a4db94011d3	1657	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
sahilmgandhi	18:6a4db94011d3	1658	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
sahilmgandhi	18:6a4db94011d3	1659	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
sahilmgandhi	18:6a4db94011d3	1660	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
sahilmgandhi	18:6a4db94011d3	1661	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
sahilmgandhi	18:6a4db94011d3	1662	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
sahilmgandhi	18:6a4db94011d3	1663	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
sahilmgandhi	18:6a4db94011d3	1664	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
sahilmgandhi	18:6a4db94011d3	1665
sahilmgandhi	18:6a4db94011d3	1666	#if (__MPU_PRESENT == 1)
sahilmgandhi	18:6a4db94011d3	1667	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
sahilmgandhi	18:6a4db94011d3	1668	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
sahilmgandhi	18:6a4db94011d3	1669	#endif
sahilmgandhi	18:6a4db94011d3	1670
sahilmgandhi	18:6a4db94011d3	1671	#if (__FPU_PRESENT == 1)
sahilmgandhi	18:6a4db94011d3	1672	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
sahilmgandhi	18:6a4db94011d3	1673	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
sahilmgandhi	18:6a4db94011d3	1674	#endif
sahilmgandhi	18:6a4db94011d3	1675
sahilmgandhi	18:6a4db94011d3	1676	/@} /
sahilmgandhi	18:6a4db94011d3	1677
sahilmgandhi	18:6a4db94011d3	1678
sahilmgandhi	18:6a4db94011d3	1679
sahilmgandhi	18:6a4db94011d3	1680	/*******************************************************************************
sahilmgandhi	18:6a4db94011d3	1681	* Hardware Abstraction Layer
sahilmgandhi	18:6a4db94011d3	1682	Core Function Interface contains:
sahilmgandhi	18:6a4db94011d3	1683	- Core NVIC Functions
sahilmgandhi	18:6a4db94011d3	1684	- Core SysTick Functions
sahilmgandhi	18:6a4db94011d3	1685	- Core Debug Functions
sahilmgandhi	18:6a4db94011d3	1686	- Core Register Access Functions
sahilmgandhi	18:6a4db94011d3	1687	******************************************************************************/
sahilmgandhi	18:6a4db94011d3	1688	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
sahilmgandhi	18:6a4db94011d3	1689	*/
sahilmgandhi	18:6a4db94011d3	1690
sahilmgandhi	18:6a4db94011d3	1691
sahilmgandhi	18:6a4db94011d3	1692
sahilmgandhi	18:6a4db94011d3	1693	/* ########################## NVIC functions #################################### */
sahilmgandhi	18:6a4db94011d3	1694	/** \ingroup CMSIS_Core_FunctionInterface
sahilmgandhi	18:6a4db94011d3	1695	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
sahilmgandhi	18:6a4db94011d3	1696	\brief Functions that manage interrupts and exceptions via the NVIC.
sahilmgandhi	18:6a4db94011d3	1697	@{
sahilmgandhi	18:6a4db94011d3	1698	*/
sahilmgandhi	18:6a4db94011d3	1699
sahilmgandhi	18:6a4db94011d3	1700	/** \brief Set Priority Grouping
sahilmgandhi	18:6a4db94011d3	1701
sahilmgandhi	18:6a4db94011d3	1702	The function sets the priority grouping field using the required unlock sequence.
sahilmgandhi	18:6a4db94011d3	1703	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
sahilmgandhi	18:6a4db94011d3	1704	Only values from 0..7 are used.
sahilmgandhi	18:6a4db94011d3	1705	In case of a conflict between priority grouping and available
sahilmgandhi	18:6a4db94011d3	1706	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
sahilmgandhi	18:6a4db94011d3	1707
sahilmgandhi	18:6a4db94011d3	1708	\param [in] PriorityGroup Priority grouping field.
sahilmgandhi	18:6a4db94011d3	1709	*/
sahilmgandhi	18:6a4db94011d3	1710	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
sahilmgandhi	18:6a4db94011d3	1711	{
sahilmgandhi	18:6a4db94011d3	1712	uint32_t reg_value;
sahilmgandhi	18:6a4db94011d3	1713	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
sahilmgandhi	18:6a4db94011d3	1714
sahilmgandhi	18:6a4db94011d3	1715	reg_value = SCB->AIRCR; /* read old register configuration */
sahilmgandhi	18:6a4db94011d3	1716	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
sahilmgandhi	18:6a4db94011d3	1717	reg_value = (reg_value \|
sahilmgandhi	18:6a4db94011d3	1718	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
sahilmgandhi	18:6a4db94011d3	1719	(PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
sahilmgandhi	18:6a4db94011d3	1720	SCB->AIRCR = reg_value;
sahilmgandhi	18:6a4db94011d3	1721	}
sahilmgandhi	18:6a4db94011d3	1722
sahilmgandhi	18:6a4db94011d3	1723
sahilmgandhi	18:6a4db94011d3	1724	/** \brief Get Priority Grouping
sahilmgandhi	18:6a4db94011d3	1725
sahilmgandhi	18:6a4db94011d3	1726	The function reads the priority grouping field from the NVIC Interrupt Controller.
sahilmgandhi	18:6a4db94011d3	1727
sahilmgandhi	18:6a4db94011d3	1728	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
sahilmgandhi	18:6a4db94011d3	1729	*/
sahilmgandhi	18:6a4db94011d3	1730	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
sahilmgandhi	18:6a4db94011d3	1731	{
sahilmgandhi	18:6a4db94011d3	1732	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
sahilmgandhi	18:6a4db94011d3	1733	}
sahilmgandhi	18:6a4db94011d3	1734
sahilmgandhi	18:6a4db94011d3	1735
sahilmgandhi	18:6a4db94011d3	1736	/** \brief Enable External Interrupt
sahilmgandhi	18:6a4db94011d3	1737
sahilmgandhi	18:6a4db94011d3	1738	The function enables a device-specific interrupt in the NVIC interrupt controller.
sahilmgandhi	18:6a4db94011d3	1739
sahilmgandhi	18:6a4db94011d3	1740	\param [in] IRQn External interrupt number. Value cannot be negative.
sahilmgandhi	18:6a4db94011d3	1741	*/
sahilmgandhi	18:6a4db94011d3	1742	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
sahilmgandhi	18:6a4db94011d3	1743	{
sahilmgandhi	18:6a4db94011d3	1744	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
sahilmgandhi	18:6a4db94011d3	1745	}
sahilmgandhi	18:6a4db94011d3	1746
sahilmgandhi	18:6a4db94011d3	1747
sahilmgandhi	18:6a4db94011d3	1748	/** \brief Disable External Interrupt
sahilmgandhi	18:6a4db94011d3	1749
sahilmgandhi	18:6a4db94011d3	1750	The function disables a device-specific interrupt in the NVIC interrupt controller.
sahilmgandhi	18:6a4db94011d3	1751
sahilmgandhi	18:6a4db94011d3	1752	\param [in] IRQn External interrupt number. Value cannot be negative.
sahilmgandhi	18:6a4db94011d3	1753	*/
sahilmgandhi	18:6a4db94011d3	1754	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
sahilmgandhi	18:6a4db94011d3	1755	{
sahilmgandhi	18:6a4db94011d3	1756	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
sahilmgandhi	18:6a4db94011d3	1757	__DSB();
sahilmgandhi	18:6a4db94011d3	1758	__ISB();
sahilmgandhi	18:6a4db94011d3	1759	}
sahilmgandhi	18:6a4db94011d3	1760
sahilmgandhi	18:6a4db94011d3	1761
sahilmgandhi	18:6a4db94011d3	1762	/** \brief Get Pending Interrupt
sahilmgandhi	18:6a4db94011d3	1763
sahilmgandhi	18:6a4db94011d3	1764	The function reads the pending register in the NVIC and returns the pending bit
sahilmgandhi	18:6a4db94011d3	1765	for the specified interrupt.
sahilmgandhi	18:6a4db94011d3	1766
sahilmgandhi	18:6a4db94011d3	1767	\param [in] IRQn Interrupt number.
sahilmgandhi	18:6a4db94011d3	1768
sahilmgandhi	18:6a4db94011d3	1769	\return 0 Interrupt status is not pending.
sahilmgandhi	18:6a4db94011d3	1770	\return 1 Interrupt status is pending.
sahilmgandhi	18:6a4db94011d3	1771	*/
sahilmgandhi	18:6a4db94011d3	1772	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
sahilmgandhi	18:6a4db94011d3	1773	{
sahilmgandhi	18:6a4db94011d3	1774	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
sahilmgandhi	18:6a4db94011d3	1775	}
sahilmgandhi	18:6a4db94011d3	1776
sahilmgandhi	18:6a4db94011d3	1777
sahilmgandhi	18:6a4db94011d3	1778	/** \brief Set Pending Interrupt
sahilmgandhi	18:6a4db94011d3	1779
sahilmgandhi	18:6a4db94011d3	1780	The function sets the pending bit of an external interrupt.
sahilmgandhi	18:6a4db94011d3	1781
sahilmgandhi	18:6a4db94011d3	1782	\param [in] IRQn Interrupt number. Value cannot be negative.
sahilmgandhi	18:6a4db94011d3	1783	*/
sahilmgandhi	18:6a4db94011d3	1784	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
sahilmgandhi	18:6a4db94011d3	1785	{
sahilmgandhi	18:6a4db94011d3	1786	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
sahilmgandhi	18:6a4db94011d3	1787	}
sahilmgandhi	18:6a4db94011d3	1788
sahilmgandhi	18:6a4db94011d3	1789
sahilmgandhi	18:6a4db94011d3	1790	/** \brief Clear Pending Interrupt
sahilmgandhi	18:6a4db94011d3	1791
sahilmgandhi	18:6a4db94011d3	1792	The function clears the pending bit of an external interrupt.
sahilmgandhi	18:6a4db94011d3	1793
sahilmgandhi	18:6a4db94011d3	1794	\param [in] IRQn External interrupt number. Value cannot be negative.
sahilmgandhi	18:6a4db94011d3	1795	*/
sahilmgandhi	18:6a4db94011d3	1796	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
sahilmgandhi	18:6a4db94011d3	1797	{
sahilmgandhi	18:6a4db94011d3	1798	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
sahilmgandhi	18:6a4db94011d3	1799	}
sahilmgandhi	18:6a4db94011d3	1800
sahilmgandhi	18:6a4db94011d3	1801
sahilmgandhi	18:6a4db94011d3	1802	/** \brief Get Active Interrupt
sahilmgandhi	18:6a4db94011d3	1803
sahilmgandhi	18:6a4db94011d3	1804	The function reads the active register in NVIC and returns the active bit.
sahilmgandhi	18:6a4db94011d3	1805
sahilmgandhi	18:6a4db94011d3	1806	\param [in] IRQn Interrupt number.
sahilmgandhi	18:6a4db94011d3	1807
sahilmgandhi	18:6a4db94011d3	1808	\return 0 Interrupt status is not active.
sahilmgandhi	18:6a4db94011d3	1809	\return 1 Interrupt status is active.
sahilmgandhi	18:6a4db94011d3	1810	*/
sahilmgandhi	18:6a4db94011d3	1811	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
sahilmgandhi	18:6a4db94011d3	1812	{
sahilmgandhi	18:6a4db94011d3	1813	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
sahilmgandhi	18:6a4db94011d3	1814	}
sahilmgandhi	18:6a4db94011d3	1815
sahilmgandhi	18:6a4db94011d3	1816
sahilmgandhi	18:6a4db94011d3	1817	/** \brief Set Interrupt Priority
sahilmgandhi	18:6a4db94011d3	1818
sahilmgandhi	18:6a4db94011d3	1819	The function sets the priority of an interrupt.
sahilmgandhi	18:6a4db94011d3	1820
sahilmgandhi	18:6a4db94011d3	1821	\note The priority cannot be set for every core interrupt.
sahilmgandhi	18:6a4db94011d3	1822
sahilmgandhi	18:6a4db94011d3	1823	\param [in] IRQn Interrupt number.
sahilmgandhi	18:6a4db94011d3	1824	\param [in] priority Priority to set.
sahilmgandhi	18:6a4db94011d3	1825	*/
sahilmgandhi	18:6a4db94011d3	1826	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
sahilmgandhi	18:6a4db94011d3	1827	{
sahilmgandhi	18:6a4db94011d3	1828	if((int32_t)IRQn < 0) {
sahilmgandhi	18:6a4db94011d3	1829	SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
sahilmgandhi	18:6a4db94011d3	1830	}
sahilmgandhi	18:6a4db94011d3	1831	else {
sahilmgandhi	18:6a4db94011d3	1832	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
sahilmgandhi	18:6a4db94011d3	1833	}
sahilmgandhi	18:6a4db94011d3	1834	}
sahilmgandhi	18:6a4db94011d3	1835
sahilmgandhi	18:6a4db94011d3	1836
sahilmgandhi	18:6a4db94011d3	1837	/** \brief Get Interrupt Priority
sahilmgandhi	18:6a4db94011d3	1838
sahilmgandhi	18:6a4db94011d3	1839	The function reads the priority of an interrupt. The interrupt
sahilmgandhi	18:6a4db94011d3	1840	number can be positive to specify an external (device specific)
sahilmgandhi	18:6a4db94011d3	1841	interrupt, or negative to specify an internal (core) interrupt.
sahilmgandhi	18:6a4db94011d3	1842
sahilmgandhi	18:6a4db94011d3	1843
sahilmgandhi	18:6a4db94011d3	1844	\param [in] IRQn Interrupt number.
sahilmgandhi	18:6a4db94011d3	1845	\return Interrupt Priority. Value is aligned automatically to the implemented
sahilmgandhi	18:6a4db94011d3	1846	priority bits of the microcontroller.
sahilmgandhi	18:6a4db94011d3	1847	*/
sahilmgandhi	18:6a4db94011d3	1848	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
sahilmgandhi	18:6a4db94011d3	1849	{
sahilmgandhi	18:6a4db94011d3	1850
sahilmgandhi	18:6a4db94011d3	1851	if((int32_t)IRQn < 0) {
sahilmgandhi	18:6a4db94011d3	1852	return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
sahilmgandhi	18:6a4db94011d3	1853	}
sahilmgandhi	18:6a4db94011d3	1854	else {
sahilmgandhi	18:6a4db94011d3	1855	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
sahilmgandhi	18:6a4db94011d3	1856	}
sahilmgandhi	18:6a4db94011d3	1857	}
sahilmgandhi	18:6a4db94011d3	1858
sahilmgandhi	18:6a4db94011d3	1859
sahilmgandhi	18:6a4db94011d3	1860	/** \brief Encode Priority
sahilmgandhi	18:6a4db94011d3	1861
sahilmgandhi	18:6a4db94011d3	1862	The function encodes the priority for an interrupt with the given priority group,
sahilmgandhi	18:6a4db94011d3	1863	preemptive priority value, and subpriority value.
sahilmgandhi	18:6a4db94011d3	1864	In case of a conflict between priority grouping and available
sahilmgandhi	18:6a4db94011d3	1865	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
sahilmgandhi	18:6a4db94011d3	1866
sahilmgandhi	18:6a4db94011d3	1867	\param [in] PriorityGroup Used priority group.
sahilmgandhi	18:6a4db94011d3	1868	\param [in] PreemptPriority Preemptive priority value (starting from 0).
sahilmgandhi	18:6a4db94011d3	1869	\param [in] SubPriority Subpriority value (starting from 0).
sahilmgandhi	18:6a4db94011d3	1870	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
sahilmgandhi	18:6a4db94011d3	1871	*/
sahilmgandhi	18:6a4db94011d3	1872	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
sahilmgandhi	18:6a4db94011d3	1873	{
sahilmgandhi	18:6a4db94011d3	1874	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
sahilmgandhi	18:6a4db94011d3	1875	uint32_t PreemptPriorityBits;
sahilmgandhi	18:6a4db94011d3	1876	uint32_t SubPriorityBits;
sahilmgandhi	18:6a4db94011d3	1877
sahilmgandhi	18:6a4db94011d3	1878	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
sahilmgandhi	18:6a4db94011d3	1879	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
sahilmgandhi	18:6a4db94011d3	1880
sahilmgandhi	18:6a4db94011d3	1881	return (
sahilmgandhi	18:6a4db94011d3	1882	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
sahilmgandhi	18:6a4db94011d3	1883	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
sahilmgandhi	18:6a4db94011d3	1884	);
sahilmgandhi	18:6a4db94011d3	1885	}
sahilmgandhi	18:6a4db94011d3	1886
sahilmgandhi	18:6a4db94011d3	1887
sahilmgandhi	18:6a4db94011d3	1888	/** \brief Decode Priority
sahilmgandhi	18:6a4db94011d3	1889
sahilmgandhi	18:6a4db94011d3	1890	The function decodes an interrupt priority value with a given priority group to
sahilmgandhi	18:6a4db94011d3	1891	preemptive priority value and subpriority value.
sahilmgandhi	18:6a4db94011d3	1892	In case of a conflict between priority grouping and available
sahilmgandhi	18:6a4db94011d3	1893	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
sahilmgandhi	18:6a4db94011d3	1894
sahilmgandhi	18:6a4db94011d3	1895	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
sahilmgandhi	18:6a4db94011d3	1896	\param [in] PriorityGroup Used priority group.
sahilmgandhi	18:6a4db94011d3	1897	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
sahilmgandhi	18:6a4db94011d3	1898	\param [out] pSubPriority Subpriority value (starting from 0).
sahilmgandhi	18:6a4db94011d3	1899	*/
sahilmgandhi	18:6a4db94011d3	1900	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
sahilmgandhi	18:6a4db94011d3	1901	{
sahilmgandhi	18:6a4db94011d3	1902	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
sahilmgandhi	18:6a4db94011d3	1903	uint32_t PreemptPriorityBits;
sahilmgandhi	18:6a4db94011d3	1904	uint32_t SubPriorityBits;
sahilmgandhi	18:6a4db94011d3	1905
sahilmgandhi	18:6a4db94011d3	1906	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
sahilmgandhi	18:6a4db94011d3	1907	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
sahilmgandhi	18:6a4db94011d3	1908
sahilmgandhi	18:6a4db94011d3	1909	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
sahilmgandhi	18:6a4db94011d3	1910	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
sahilmgandhi	18:6a4db94011d3	1911	}
sahilmgandhi	18:6a4db94011d3	1912
sahilmgandhi	18:6a4db94011d3	1913
sahilmgandhi	18:6a4db94011d3	1914	/** \brief System Reset
sahilmgandhi	18:6a4db94011d3	1915
sahilmgandhi	18:6a4db94011d3	1916	The function initiates a system reset request to reset the MCU.
sahilmgandhi	18:6a4db94011d3	1917	*/
sahilmgandhi	18:6a4db94011d3	1918	__STATIC_INLINE void NVIC_SystemReset(void)
sahilmgandhi	18:6a4db94011d3	1919	{
sahilmgandhi	18:6a4db94011d3	1920	__DSB(); /* Ensure all outstanding memory accesses included
sahilmgandhi	18:6a4db94011d3	1921	buffered write are completed before reset */
sahilmgandhi	18:6a4db94011d3	1922	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
sahilmgandhi	18:6a4db94011d3	1923	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
sahilmgandhi	18:6a4db94011d3	1924	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
sahilmgandhi	18:6a4db94011d3	1925	__DSB(); /* Ensure completion of memory access */
sahilmgandhi	18:6a4db94011d3	1926	while(1) { __NOP(); } /* wait until reset */
sahilmgandhi	18:6a4db94011d3	1927	}
sahilmgandhi	18:6a4db94011d3	1928
sahilmgandhi	18:6a4db94011d3	1929	/@} end of CMSIS_Core_NVICFunctions /
sahilmgandhi	18:6a4db94011d3	1930
sahilmgandhi	18:6a4db94011d3	1931
sahilmgandhi	18:6a4db94011d3	1932	/* ########################## FPU functions #################################### */
sahilmgandhi	18:6a4db94011d3	1933	/** \ingroup CMSIS_Core_FunctionInterface
sahilmgandhi	18:6a4db94011d3	1934	\defgroup CMSIS_Core_FpuFunctions FPU Functions
sahilmgandhi	18:6a4db94011d3	1935	\brief Function that provides FPU type.
sahilmgandhi	18:6a4db94011d3	1936	@{
sahilmgandhi	18:6a4db94011d3	1937	*/
sahilmgandhi	18:6a4db94011d3	1938
sahilmgandhi	18:6a4db94011d3	1939	/**
sahilmgandhi	18:6a4db94011d3	1940	\fn uint32_t SCB_GetFPUType(void)
sahilmgandhi	18:6a4db94011d3	1941	\brief get FPU type
sahilmgandhi	18:6a4db94011d3	1942	\returns
sahilmgandhi	18:6a4db94011d3	1943	- \b 0: No FPU
sahilmgandhi	18:6a4db94011d3	1944	- \b 1: Single precision FPU
sahilmgandhi	18:6a4db94011d3	1945	- \b 2: Double + Single precision FPU
sahilmgandhi	18:6a4db94011d3	1946	*/
sahilmgandhi	18:6a4db94011d3	1947	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
sahilmgandhi	18:6a4db94011d3	1948	{
sahilmgandhi	18:6a4db94011d3	1949	uint32_t mvfr0;
sahilmgandhi	18:6a4db94011d3	1950
sahilmgandhi	18:6a4db94011d3	1951	mvfr0 = SCB->MVFR0;
sahilmgandhi	18:6a4db94011d3	1952	if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
sahilmgandhi	18:6a4db94011d3	1953	return 2UL; // Double + Single precision FPU
sahilmgandhi	18:6a4db94011d3	1954	} else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
sahilmgandhi	18:6a4db94011d3	1955	return 1UL; // Single precision FPU
sahilmgandhi	18:6a4db94011d3	1956	} else {
sahilmgandhi	18:6a4db94011d3	1957	return 0UL; // No FPU
sahilmgandhi	18:6a4db94011d3	1958	}
sahilmgandhi	18:6a4db94011d3	1959	}
sahilmgandhi	18:6a4db94011d3	1960
sahilmgandhi	18:6a4db94011d3	1961
sahilmgandhi	18:6a4db94011d3	1962	/@} end of CMSIS_Core_FpuFunctions /
sahilmgandhi	18:6a4db94011d3	1963
sahilmgandhi	18:6a4db94011d3	1964
sahilmgandhi	18:6a4db94011d3	1965
sahilmgandhi	18:6a4db94011d3	1966	/* ########################## Cache functions #################################### */
sahilmgandhi	18:6a4db94011d3	1967	/** \ingroup CMSIS_Core_FunctionInterface
sahilmgandhi	18:6a4db94011d3	1968	\defgroup CMSIS_Core_CacheFunctions Cache Functions
sahilmgandhi	18:6a4db94011d3	1969	\brief Functions that configure Instruction and Data cache.
sahilmgandhi	18:6a4db94011d3	1970	@{
sahilmgandhi	18:6a4db94011d3	1971	*/
sahilmgandhi	18:6a4db94011d3	1972
sahilmgandhi	18:6a4db94011d3	1973	/* Cache Size ID Register Macros */
sahilmgandhi	18:6a4db94011d3	1974	#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
sahilmgandhi	18:6a4db94011d3	1975	#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
sahilmgandhi	18:6a4db94011d3	1976	#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) />> SCB_CCSIDR_LINESIZE_Pos/ )
sahilmgandhi	18:6a4db94011d3	1977
sahilmgandhi	18:6a4db94011d3	1978
sahilmgandhi	18:6a4db94011d3	1979	/** \brief Enable I-Cache
sahilmgandhi	18:6a4db94011d3	1980
sahilmgandhi	18:6a4db94011d3	1981	The function turns on I-Cache
sahilmgandhi	18:6a4db94011d3	1982	*/
sahilmgandhi	18:6a4db94011d3	1983	__STATIC_INLINE void SCB_EnableICache (void)
sahilmgandhi	18:6a4db94011d3	1984	{
sahilmgandhi	18:6a4db94011d3	1985	#if (__ICACHE_PRESENT == 1)
sahilmgandhi	18:6a4db94011d3	1986	__DSB();
sahilmgandhi	18:6a4db94011d3	1987	__ISB();
sahilmgandhi	18:6a4db94011d3	1988	SCB->ICIALLU = 0UL; // invalidate I-Cache
sahilmgandhi	18:6a4db94011d3	1989	SCB->CCR \|= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache
sahilmgandhi	18:6a4db94011d3	1990	__DSB();
sahilmgandhi	18:6a4db94011d3	1991	__ISB();
sahilmgandhi	18:6a4db94011d3	1992	#endif
sahilmgandhi	18:6a4db94011d3	1993	}
sahilmgandhi	18:6a4db94011d3	1994
sahilmgandhi	18:6a4db94011d3	1995
sahilmgandhi	18:6a4db94011d3	1996	/** \brief Disable I-Cache
sahilmgandhi	18:6a4db94011d3	1997
sahilmgandhi	18:6a4db94011d3	1998	The function turns off I-Cache
sahilmgandhi	18:6a4db94011d3	1999	*/
sahilmgandhi	18:6a4db94011d3	2000	__STATIC_INLINE void SCB_DisableICache (void)
sahilmgandhi	18:6a4db94011d3	2001	{
sahilmgandhi	18:6a4db94011d3	2002	#if (__ICACHE_PRESENT == 1)
sahilmgandhi	18:6a4db94011d3	2003	__DSB();
sahilmgandhi	18:6a4db94011d3	2004	__ISB();
sahilmgandhi	18:6a4db94011d3	2005	SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache
sahilmgandhi	18:6a4db94011d3	2006	SCB->ICIALLU = 0UL; // invalidate I-Cache
sahilmgandhi	18:6a4db94011d3	2007	__DSB();
sahilmgandhi	18:6a4db94011d3	2008	__ISB();
sahilmgandhi	18:6a4db94011d3	2009	#endif
sahilmgandhi	18:6a4db94011d3	2010	}
sahilmgandhi	18:6a4db94011d3	2011
sahilmgandhi	18:6a4db94011d3	2012
sahilmgandhi	18:6a4db94011d3	2013	/** \brief Invalidate I-Cache
sahilmgandhi	18:6a4db94011d3	2014
sahilmgandhi	18:6a4db94011d3	2015	The function invalidates I-Cache
sahilmgandhi	18:6a4db94011d3	2016	*/
sahilmgandhi	18:6a4db94011d3	2017	__STATIC_INLINE void SCB_InvalidateICache (void)
sahilmgandhi	18:6a4db94011d3	2018	{
sahilmgandhi	18:6a4db94011d3	2019	#if (__ICACHE_PRESENT == 1)
sahilmgandhi	18:6a4db94011d3	2020	__DSB();
sahilmgandhi	18:6a4db94011d3	2021	__ISB();
sahilmgandhi	18:6a4db94011d3	2022	SCB->ICIALLU = 0UL;
sahilmgandhi	18:6a4db94011d3	2023	__DSB();
sahilmgandhi	18:6a4db94011d3	2024	__ISB();
sahilmgandhi	18:6a4db94011d3	2025	#endif
sahilmgandhi	18:6a4db94011d3	2026	}
sahilmgandhi	18:6a4db94011d3	2027
sahilmgandhi	18:6a4db94011d3	2028
sahilmgandhi	18:6a4db94011d3	2029	/** \brief Enable D-Cache
sahilmgandhi	18:6a4db94011d3	2030
sahilmgandhi	18:6a4db94011d3	2031	The function turns on D-Cache
sahilmgandhi	18:6a4db94011d3	2032	*/
sahilmgandhi	18:6a4db94011d3	2033	__STATIC_INLINE void SCB_EnableDCache (void)
sahilmgandhi	18:6a4db94011d3	2034	{
sahilmgandhi	18:6a4db94011d3	2035	#if (__DCACHE_PRESENT == 1)
sahilmgandhi	18:6a4db94011d3	2036	uint32_t ccsidr, sshift, wshift, sw;
sahilmgandhi	18:6a4db94011d3	2037	uint32_t sets, ways;
sahilmgandhi	18:6a4db94011d3	2038
sahilmgandhi	18:6a4db94011d3	2039	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
sahilmgandhi	18:6a4db94011d3	2040	ccsidr = SCB->CCSIDR;
sahilmgandhi	18:6a4db94011d3	2041	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
sahilmgandhi	18:6a4db94011d3	2042	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
sahilmgandhi	18:6a4db94011d3	2043	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
sahilmgandhi	18:6a4db94011d3	2044	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
sahilmgandhi	18:6a4db94011d3	2045
sahilmgandhi	18:6a4db94011d3	2046	__DSB();
sahilmgandhi	18:6a4db94011d3	2047
sahilmgandhi	18:6a4db94011d3	2048	do { // invalidate D-Cache
sahilmgandhi	18:6a4db94011d3	2049	uint32_t tmpways = ways;
sahilmgandhi	18:6a4db94011d3	2050	do {
sahilmgandhi	18:6a4db94011d3	2051	sw = ((tmpways << wshift) \| (sets << sshift));
sahilmgandhi	18:6a4db94011d3	2052	SCB->DCISW = sw;
sahilmgandhi	18:6a4db94011d3	2053	} while(tmpways--);
sahilmgandhi	18:6a4db94011d3	2054	} while(sets--);
sahilmgandhi	18:6a4db94011d3	2055	__DSB();
sahilmgandhi	18:6a4db94011d3	2056
sahilmgandhi	18:6a4db94011d3	2057	SCB->CCR \|= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache
sahilmgandhi	18:6a4db94011d3	2058
sahilmgandhi	18:6a4db94011d3	2059	__DSB();
sahilmgandhi	18:6a4db94011d3	2060	__ISB();
sahilmgandhi	18:6a4db94011d3	2061	#endif
sahilmgandhi	18:6a4db94011d3	2062	}
sahilmgandhi	18:6a4db94011d3	2063
sahilmgandhi	18:6a4db94011d3	2064
sahilmgandhi	18:6a4db94011d3	2065	/** \brief Disable D-Cache
sahilmgandhi	18:6a4db94011d3	2066
sahilmgandhi	18:6a4db94011d3	2067	The function turns off D-Cache
sahilmgandhi	18:6a4db94011d3	2068	*/
sahilmgandhi	18:6a4db94011d3	2069	__STATIC_INLINE void SCB_DisableDCache (void)
sahilmgandhi	18:6a4db94011d3	2070	{
sahilmgandhi	18:6a4db94011d3	2071	#if (__DCACHE_PRESENT == 1)
sahilmgandhi	18:6a4db94011d3	2072	uint32_t ccsidr, sshift, wshift, sw;
sahilmgandhi	18:6a4db94011d3	2073	uint32_t sets, ways;
sahilmgandhi	18:6a4db94011d3	2074
sahilmgandhi	18:6a4db94011d3	2075	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
sahilmgandhi	18:6a4db94011d3	2076	ccsidr = SCB->CCSIDR;
sahilmgandhi	18:6a4db94011d3	2077	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
sahilmgandhi	18:6a4db94011d3	2078	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
sahilmgandhi	18:6a4db94011d3	2079	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
sahilmgandhi	18:6a4db94011d3	2080	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
sahilmgandhi	18:6a4db94011d3	2081
sahilmgandhi	18:6a4db94011d3	2082	__DSB();
sahilmgandhi	18:6a4db94011d3	2083
sahilmgandhi	18:6a4db94011d3	2084	SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache
sahilmgandhi	18:6a4db94011d3	2085
sahilmgandhi	18:6a4db94011d3	2086	do { // clean & invalidate D-Cache
sahilmgandhi	18:6a4db94011d3	2087	uint32_t tmpways = ways;
sahilmgandhi	18:6a4db94011d3	2088	do {
sahilmgandhi	18:6a4db94011d3	2089	sw = ((tmpways << wshift) \| (sets << sshift));
sahilmgandhi	18:6a4db94011d3	2090	SCB->DCCISW = sw;
sahilmgandhi	18:6a4db94011d3	2091	} while(tmpways--);
sahilmgandhi	18:6a4db94011d3	2092	} while(sets--);
sahilmgandhi	18:6a4db94011d3	2093
sahilmgandhi	18:6a4db94011d3	2094
sahilmgandhi	18:6a4db94011d3	2095	__DSB();
sahilmgandhi	18:6a4db94011d3	2096	__ISB();
sahilmgandhi	18:6a4db94011d3	2097	#endif
sahilmgandhi	18:6a4db94011d3	2098	}
sahilmgandhi	18:6a4db94011d3	2099
sahilmgandhi	18:6a4db94011d3	2100
sahilmgandhi	18:6a4db94011d3	2101	/** \brief Invalidate D-Cache
sahilmgandhi	18:6a4db94011d3	2102
sahilmgandhi	18:6a4db94011d3	2103	The function invalidates D-Cache
sahilmgandhi	18:6a4db94011d3	2104	*/
sahilmgandhi	18:6a4db94011d3	2105	__STATIC_INLINE void SCB_InvalidateDCache (void)
sahilmgandhi	18:6a4db94011d3	2106	{
sahilmgandhi	18:6a4db94011d3	2107	#if (__DCACHE_PRESENT == 1)
sahilmgandhi	18:6a4db94011d3	2108	uint32_t ccsidr, sshift, wshift, sw;
sahilmgandhi	18:6a4db94011d3	2109	uint32_t sets, ways;
sahilmgandhi	18:6a4db94011d3	2110
sahilmgandhi	18:6a4db94011d3	2111	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
sahilmgandhi	18:6a4db94011d3	2112	ccsidr = SCB->CCSIDR;
sahilmgandhi	18:6a4db94011d3	2113	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
sahilmgandhi	18:6a4db94011d3	2114	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
sahilmgandhi	18:6a4db94011d3	2115	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
sahilmgandhi	18:6a4db94011d3	2116	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
sahilmgandhi	18:6a4db94011d3	2117
sahilmgandhi	18:6a4db94011d3	2118	__DSB();
sahilmgandhi	18:6a4db94011d3	2119
sahilmgandhi	18:6a4db94011d3	2120	do { // invalidate D-Cache
sahilmgandhi	18:6a4db94011d3	2121	uint32_t tmpways = ways;
sahilmgandhi	18:6a4db94011d3	2122	do {
sahilmgandhi	18:6a4db94011d3	2123	sw = ((tmpways << wshift) \| (sets << sshift));
sahilmgandhi	18:6a4db94011d3	2124	SCB->DCISW = sw;
sahilmgandhi	18:6a4db94011d3	2125	} while(tmpways--);
sahilmgandhi	18:6a4db94011d3	2126	} while(sets--);
sahilmgandhi	18:6a4db94011d3	2127
sahilmgandhi	18:6a4db94011d3	2128	__DSB();
sahilmgandhi	18:6a4db94011d3	2129	__ISB();
sahilmgandhi	18:6a4db94011d3	2130	#endif
sahilmgandhi	18:6a4db94011d3	2131	}
sahilmgandhi	18:6a4db94011d3	2132
sahilmgandhi	18:6a4db94011d3	2133
sahilmgandhi	18:6a4db94011d3	2134	/** \brief Clean D-Cache
sahilmgandhi	18:6a4db94011d3	2135
sahilmgandhi	18:6a4db94011d3	2136	The function cleans D-Cache
sahilmgandhi	18:6a4db94011d3	2137	*/
sahilmgandhi	18:6a4db94011d3	2138	__STATIC_INLINE void SCB_CleanDCache (void)
sahilmgandhi	18:6a4db94011d3	2139	{
sahilmgandhi	18:6a4db94011d3	2140	#if (__DCACHE_PRESENT == 1)
sahilmgandhi	18:6a4db94011d3	2141	uint32_t ccsidr, sshift, wshift, sw;
sahilmgandhi	18:6a4db94011d3	2142	uint32_t sets, ways;
sahilmgandhi	18:6a4db94011d3	2143
sahilmgandhi	18:6a4db94011d3	2144	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
sahilmgandhi	18:6a4db94011d3	2145	ccsidr = SCB->CCSIDR;
sahilmgandhi	18:6a4db94011d3	2146	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
sahilmgandhi	18:6a4db94011d3	2147	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
sahilmgandhi	18:6a4db94011d3	2148	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
sahilmgandhi	18:6a4db94011d3	2149	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
sahilmgandhi	18:6a4db94011d3	2150
sahilmgandhi	18:6a4db94011d3	2151	__DSB();
sahilmgandhi	18:6a4db94011d3	2152
sahilmgandhi	18:6a4db94011d3	2153	do { // clean D-Cache
sahilmgandhi	18:6a4db94011d3	2154	uint32_t tmpways = ways;
sahilmgandhi	18:6a4db94011d3	2155	do {
sahilmgandhi	18:6a4db94011d3	2156	sw = ((tmpways << wshift) \| (sets << sshift));
sahilmgandhi	18:6a4db94011d3	2157	SCB->DCCSW = sw;
sahilmgandhi	18:6a4db94011d3	2158	} while(tmpways--);
sahilmgandhi	18:6a4db94011d3	2159	} while(sets--);
sahilmgandhi	18:6a4db94011d3	2160
sahilmgandhi	18:6a4db94011d3	2161	__DSB();
sahilmgandhi	18:6a4db94011d3	2162	__ISB();
sahilmgandhi	18:6a4db94011d3	2163	#endif
sahilmgandhi	18:6a4db94011d3	2164	}
sahilmgandhi	18:6a4db94011d3	2165
sahilmgandhi	18:6a4db94011d3	2166
sahilmgandhi	18:6a4db94011d3	2167	/** \brief Clean & Invalidate D-Cache
sahilmgandhi	18:6a4db94011d3	2168
sahilmgandhi	18:6a4db94011d3	2169	The function cleans and Invalidates D-Cache
sahilmgandhi	18:6a4db94011d3	2170	*/
sahilmgandhi	18:6a4db94011d3	2171	__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
sahilmgandhi	18:6a4db94011d3	2172	{
sahilmgandhi	18:6a4db94011d3	2173	#if (__DCACHE_PRESENT == 1)
sahilmgandhi	18:6a4db94011d3	2174	uint32_t ccsidr, sshift, wshift, sw;
sahilmgandhi	18:6a4db94011d3	2175	uint32_t sets, ways;
sahilmgandhi	18:6a4db94011d3	2176
sahilmgandhi	18:6a4db94011d3	2177	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
sahilmgandhi	18:6a4db94011d3	2178	ccsidr = SCB->CCSIDR;
sahilmgandhi	18:6a4db94011d3	2179	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
sahilmgandhi	18:6a4db94011d3	2180	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
sahilmgandhi	18:6a4db94011d3	2181	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
sahilmgandhi	18:6a4db94011d3	2182	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
sahilmgandhi	18:6a4db94011d3	2183
sahilmgandhi	18:6a4db94011d3	2184	__DSB();
sahilmgandhi	18:6a4db94011d3	2185
sahilmgandhi	18:6a4db94011d3	2186	do { // clean & invalidate D-Cache
sahilmgandhi	18:6a4db94011d3	2187	uint32_t tmpways = ways;
sahilmgandhi	18:6a4db94011d3	2188	do {
sahilmgandhi	18:6a4db94011d3	2189	sw = ((tmpways << wshift) \| (sets << sshift));
sahilmgandhi	18:6a4db94011d3	2190	SCB->DCCISW = sw;
sahilmgandhi	18:6a4db94011d3	2191	} while(tmpways--);
sahilmgandhi	18:6a4db94011d3	2192	} while(sets--);
sahilmgandhi	18:6a4db94011d3	2193
sahilmgandhi	18:6a4db94011d3	2194	__DSB();
sahilmgandhi	18:6a4db94011d3	2195	__ISB();
sahilmgandhi	18:6a4db94011d3	2196	#endif
sahilmgandhi	18:6a4db94011d3	2197	}
sahilmgandhi	18:6a4db94011d3	2198
sahilmgandhi	18:6a4db94011d3	2199
sahilmgandhi	18:6a4db94011d3	2200	/**
sahilmgandhi	18:6a4db94011d3	2201	\fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
sahilmgandhi	18:6a4db94011d3	2202	\brief D-Cache Invalidate by address
sahilmgandhi	18:6a4db94011d3	2203	\param[in] addr address (aligned to 32-byte boundary)
sahilmgandhi	18:6a4db94011d3	2204	\param[in] dsize size of memory block (in number of bytes)
sahilmgandhi	18:6a4db94011d3	2205	*/
sahilmgandhi	18:6a4db94011d3	2206	__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
sahilmgandhi	18:6a4db94011d3	2207	{
sahilmgandhi	18:6a4db94011d3	2208	#if (__DCACHE_PRESENT == 1)
sahilmgandhi	18:6a4db94011d3	2209	int32_t op_size = dsize;
sahilmgandhi	18:6a4db94011d3	2210	uint32_t op_addr = (uint32_t)addr;
sahilmgandhi	18:6a4db94011d3	2211	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
sahilmgandhi	18:6a4db94011d3	2212
sahilmgandhi	18:6a4db94011d3	2213	__DSB();
sahilmgandhi	18:6a4db94011d3	2214
sahilmgandhi	18:6a4db94011d3	2215	while (op_size > 0) {
sahilmgandhi	18:6a4db94011d3	2216	SCB->DCIMVAC = op_addr;
sahilmgandhi	18:6a4db94011d3	2217	op_addr += linesize;
sahilmgandhi	18:6a4db94011d3	2218	op_size -= (int32_t)linesize;
sahilmgandhi	18:6a4db94011d3	2219	}
sahilmgandhi	18:6a4db94011d3	2220
sahilmgandhi	18:6a4db94011d3	2221	__DSB();
sahilmgandhi	18:6a4db94011d3	2222	__ISB();
sahilmgandhi	18:6a4db94011d3	2223	#endif
sahilmgandhi	18:6a4db94011d3	2224	}
sahilmgandhi	18:6a4db94011d3	2225
sahilmgandhi	18:6a4db94011d3	2226
sahilmgandhi	18:6a4db94011d3	2227	/**
sahilmgandhi	18:6a4db94011d3	2228	\fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
sahilmgandhi	18:6a4db94011d3	2229	\brief D-Cache Clean by address
sahilmgandhi	18:6a4db94011d3	2230	\param[in] addr address (aligned to 32-byte boundary)
sahilmgandhi	18:6a4db94011d3	2231	\param[in] dsize size of memory block (in number of bytes)
sahilmgandhi	18:6a4db94011d3	2232	*/
sahilmgandhi	18:6a4db94011d3	2233	__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
sahilmgandhi	18:6a4db94011d3	2234	{
sahilmgandhi	18:6a4db94011d3	2235	#if (__DCACHE_PRESENT == 1)
sahilmgandhi	18:6a4db94011d3	2236	int32_t op_size = dsize;
sahilmgandhi	18:6a4db94011d3	2237	uint32_t op_addr = (uint32_t) addr;
sahilmgandhi	18:6a4db94011d3	2238	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
sahilmgandhi	18:6a4db94011d3	2239
sahilmgandhi	18:6a4db94011d3	2240	__DSB();
sahilmgandhi	18:6a4db94011d3	2241
sahilmgandhi	18:6a4db94011d3	2242	while (op_size > 0) {
sahilmgandhi	18:6a4db94011d3	2243	SCB->DCCMVAC = op_addr;
sahilmgandhi	18:6a4db94011d3	2244	op_addr += linesize;
sahilmgandhi	18:6a4db94011d3	2245	op_size -= (int32_t)linesize;
sahilmgandhi	18:6a4db94011d3	2246	}
sahilmgandhi	18:6a4db94011d3	2247
sahilmgandhi	18:6a4db94011d3	2248	__DSB();
sahilmgandhi	18:6a4db94011d3	2249	__ISB();
sahilmgandhi	18:6a4db94011d3	2250	#endif
sahilmgandhi	18:6a4db94011d3	2251	}
sahilmgandhi	18:6a4db94011d3	2252
sahilmgandhi	18:6a4db94011d3	2253
sahilmgandhi	18:6a4db94011d3	2254	/**
sahilmgandhi	18:6a4db94011d3	2255	\fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
sahilmgandhi	18:6a4db94011d3	2256	\brief D-Cache Clean and Invalidate by address
sahilmgandhi	18:6a4db94011d3	2257	\param[in] addr address (aligned to 32-byte boundary)
sahilmgandhi	18:6a4db94011d3	2258	\param[in] dsize size of memory block (in number of bytes)
sahilmgandhi	18:6a4db94011d3	2259	*/
sahilmgandhi	18:6a4db94011d3	2260	__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
sahilmgandhi	18:6a4db94011d3	2261	{
sahilmgandhi	18:6a4db94011d3	2262	#if (__DCACHE_PRESENT == 1)
sahilmgandhi	18:6a4db94011d3	2263	int32_t op_size = dsize;
sahilmgandhi	18:6a4db94011d3	2264	uint32_t op_addr = (uint32_t) addr;
sahilmgandhi	18:6a4db94011d3	2265	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
sahilmgandhi	18:6a4db94011d3	2266
sahilmgandhi	18:6a4db94011d3	2267	__DSB();
sahilmgandhi	18:6a4db94011d3	2268
sahilmgandhi	18:6a4db94011d3	2269	while (op_size > 0) {
sahilmgandhi	18:6a4db94011d3	2270	SCB->DCCIMVAC = op_addr;
sahilmgandhi	18:6a4db94011d3	2271	op_addr += linesize;
sahilmgandhi	18:6a4db94011d3	2272	op_size -= (int32_t)linesize;
sahilmgandhi	18:6a4db94011d3	2273	}
sahilmgandhi	18:6a4db94011d3	2274
sahilmgandhi	18:6a4db94011d3	2275	__DSB();
sahilmgandhi	18:6a4db94011d3	2276	__ISB();
sahilmgandhi	18:6a4db94011d3	2277	#endif
sahilmgandhi	18:6a4db94011d3	2278	}
sahilmgandhi	18:6a4db94011d3	2279
sahilmgandhi	18:6a4db94011d3	2280
sahilmgandhi	18:6a4db94011d3	2281	/@} end of CMSIS_Core_CacheFunctions /
sahilmgandhi	18:6a4db94011d3	2282
sahilmgandhi	18:6a4db94011d3	2283
sahilmgandhi	18:6a4db94011d3	2284
sahilmgandhi	18:6a4db94011d3	2285	/* ################################## SysTick function ############################################ */
sahilmgandhi	18:6a4db94011d3	2286	/** \ingroup CMSIS_Core_FunctionInterface
sahilmgandhi	18:6a4db94011d3	2287	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
sahilmgandhi	18:6a4db94011d3	2288	\brief Functions that configure the System.
sahilmgandhi	18:6a4db94011d3	2289	@{
sahilmgandhi	18:6a4db94011d3	2290	*/
sahilmgandhi	18:6a4db94011d3	2291
sahilmgandhi	18:6a4db94011d3	2292	#if (__Vendor_SysTickConfig == 0)
sahilmgandhi	18:6a4db94011d3	2293
sahilmgandhi	18:6a4db94011d3	2294	/** \brief System Tick Configuration
sahilmgandhi	18:6a4db94011d3	2295
sahilmgandhi	18:6a4db94011d3	2296	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
sahilmgandhi	18:6a4db94011d3	2297	Counter is in free running mode to generate periodic interrupts.
sahilmgandhi	18:6a4db94011d3	2298
sahilmgandhi	18:6a4db94011d3	2299	\param [in] ticks Number of ticks between two interrupts.
sahilmgandhi	18:6a4db94011d3	2300
sahilmgandhi	18:6a4db94011d3	2301	\return 0 Function succeeded.
sahilmgandhi	18:6a4db94011d3	2302	\return 1 Function failed.
sahilmgandhi	18:6a4db94011d3	2303
sahilmgandhi	18:6a4db94011d3	2304	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
sahilmgandhi	18:6a4db94011d3	2305	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
sahilmgandhi	18:6a4db94011d3	2306	must contain a vendor-specific implementation of this function.
sahilmgandhi	18:6a4db94011d3	2307
sahilmgandhi	18:6a4db94011d3	2308	*/
sahilmgandhi	18:6a4db94011d3	2309	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
sahilmgandhi	18:6a4db94011d3	2310	{
sahilmgandhi	18:6a4db94011d3	2311	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
sahilmgandhi	18:6a4db94011d3	2312
sahilmgandhi	18:6a4db94011d3	2313	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
sahilmgandhi	18:6a4db94011d3	2314	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
sahilmgandhi	18:6a4db94011d3	2315	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
sahilmgandhi	18:6a4db94011d3	2316	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
sahilmgandhi	18:6a4db94011d3	2317	SysTick_CTRL_TICKINT_Msk \|
sahilmgandhi	18:6a4db94011d3	2318	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
sahilmgandhi	18:6a4db94011d3	2319	return (0UL); /* Function successful */
sahilmgandhi	18:6a4db94011d3	2320	}
sahilmgandhi	18:6a4db94011d3	2321
sahilmgandhi	18:6a4db94011d3	2322	#endif
sahilmgandhi	18:6a4db94011d3	2323
sahilmgandhi	18:6a4db94011d3	2324	/@} end of CMSIS_Core_SysTickFunctions /
sahilmgandhi	18:6a4db94011d3	2325
sahilmgandhi	18:6a4db94011d3	2326
sahilmgandhi	18:6a4db94011d3	2327
sahilmgandhi	18:6a4db94011d3	2328	/* ##################################### Debug In/Output function ########################################### */
sahilmgandhi	18:6a4db94011d3	2329	/** \ingroup CMSIS_Core_FunctionInterface
sahilmgandhi	18:6a4db94011d3	2330	\defgroup CMSIS_core_DebugFunctions ITM Functions
sahilmgandhi	18:6a4db94011d3	2331	\brief Functions that access the ITM debug interface.
sahilmgandhi	18:6a4db94011d3	2332	@{
sahilmgandhi	18:6a4db94011d3	2333	*/
sahilmgandhi	18:6a4db94011d3	2334
sahilmgandhi	18:6a4db94011d3	2335	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
sahilmgandhi	18:6a4db94011d3	2336	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
sahilmgandhi	18:6a4db94011d3	2337
sahilmgandhi	18:6a4db94011d3	2338
sahilmgandhi	18:6a4db94011d3	2339	/** \brief ITM Send Character
sahilmgandhi	18:6a4db94011d3	2340
sahilmgandhi	18:6a4db94011d3	2341	The function transmits a character via the ITM channel 0, and
sahilmgandhi	18:6a4db94011d3	2342	\li Just returns when no debugger is connected that has booked the output.
sahilmgandhi	18:6a4db94011d3	2343	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
sahilmgandhi	18:6a4db94011d3	2344
sahilmgandhi	18:6a4db94011d3	2345	\param [in] ch Character to transmit.
sahilmgandhi	18:6a4db94011d3	2346
sahilmgandhi	18:6a4db94011d3	2347	\returns Character to transmit.
sahilmgandhi	18:6a4db94011d3	2348	*/
sahilmgandhi	18:6a4db94011d3	2349	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
sahilmgandhi	18:6a4db94011d3	2350	{
sahilmgandhi	18:6a4db94011d3	2351	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
sahilmgandhi	18:6a4db94011d3	2352	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
sahilmgandhi	18:6a4db94011d3	2353	{
sahilmgandhi	18:6a4db94011d3	2354	while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
sahilmgandhi	18:6a4db94011d3	2355	ITM->PORT[0].u8 = (uint8_t)ch;
sahilmgandhi	18:6a4db94011d3	2356	}
sahilmgandhi	18:6a4db94011d3	2357	return (ch);
sahilmgandhi	18:6a4db94011d3	2358	}
sahilmgandhi	18:6a4db94011d3	2359
sahilmgandhi	18:6a4db94011d3	2360
sahilmgandhi	18:6a4db94011d3	2361	/** \brief ITM Receive Character
sahilmgandhi	18:6a4db94011d3	2362
sahilmgandhi	18:6a4db94011d3	2363	The function inputs a character via the external variable \ref ITM_RxBuffer.
sahilmgandhi	18:6a4db94011d3	2364
sahilmgandhi	18:6a4db94011d3	2365	\return Received character.
sahilmgandhi	18:6a4db94011d3	2366	\return -1 No character pending.
sahilmgandhi	18:6a4db94011d3	2367	*/
sahilmgandhi	18:6a4db94011d3	2368	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
sahilmgandhi	18:6a4db94011d3	2369	int32_t ch = -1; /* no character available */
sahilmgandhi	18:6a4db94011d3	2370
sahilmgandhi	18:6a4db94011d3	2371	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
sahilmgandhi	18:6a4db94011d3	2372	ch = ITM_RxBuffer;
sahilmgandhi	18:6a4db94011d3	2373	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
sahilmgandhi	18:6a4db94011d3	2374	}
sahilmgandhi	18:6a4db94011d3	2375
sahilmgandhi	18:6a4db94011d3	2376	return (ch);
sahilmgandhi	18:6a4db94011d3	2377	}
sahilmgandhi	18:6a4db94011d3	2378
sahilmgandhi	18:6a4db94011d3	2379
sahilmgandhi	18:6a4db94011d3	2380	/** \brief ITM Check Character
sahilmgandhi	18:6a4db94011d3	2381
sahilmgandhi	18:6a4db94011d3	2382	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
sahilmgandhi	18:6a4db94011d3	2383
sahilmgandhi	18:6a4db94011d3	2384	\return 0 No character available.
sahilmgandhi	18:6a4db94011d3	2385	\return 1 Character available.
sahilmgandhi	18:6a4db94011d3	2386	*/
sahilmgandhi	18:6a4db94011d3	2387	__STATIC_INLINE int32_t ITM_CheckChar (void) {
sahilmgandhi	18:6a4db94011d3	2388
sahilmgandhi	18:6a4db94011d3	2389	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
sahilmgandhi	18:6a4db94011d3	2390	return (0); /* no character available */
sahilmgandhi	18:6a4db94011d3	2391	} else {
sahilmgandhi	18:6a4db94011d3	2392	return (1); /* character available */
sahilmgandhi	18:6a4db94011d3	2393	}
sahilmgandhi	18:6a4db94011d3	2394	}
sahilmgandhi	18:6a4db94011d3	2395
sahilmgandhi	18:6a4db94011d3	2396	/@} end of CMSIS_core_DebugFunctions /
sahilmgandhi	18:6a4db94011d3	2397
sahilmgandhi	18:6a4db94011d3	2398
sahilmgandhi	18:6a4db94011d3	2399
sahilmgandhi	18:6a4db94011d3	2400
sahilmgandhi	18:6a4db94011d3	2401	#ifdef __cplusplus
sahilmgandhi	18:6a4db94011d3	2402	}
sahilmgandhi	18:6a4db94011d3	2403	#endif
sahilmgandhi	18:6a4db94011d3	2404
sahilmgandhi	18:6a4db94011d3	2405	#endif /* __CORE_CM7_H_DEPENDANT */
sahilmgandhi	18:6a4db94011d3	2406
sahilmgandhi	18:6a4db94011d3	2407	#endif /* __CMSIS_GENERIC */

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Type:	Program
Created:	25 Apr 2017
Imports:	29
Forks:	0
Commits:	47
Dependents:	0
Dependencies:	2
Followers:	5

The code in this repository is Apache licensed.

mbed-dev/cmsis/core_cm7.h@46:b156ef445742, 2017-06-03 (annotated)

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