MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/cmsis/core_ca_mmu.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 ;/**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 ; * @file core_ca_mmu.h
sahilmgandhi 18:6a4db94011d3 3 ; * @brief MMU Startup File for A9_MP Device Series
sahilmgandhi 18:6a4db94011d3 4 ; * @version V1.01
sahilmgandhi 18:6a4db94011d3 5 ; * @date 10 Sept 2014
sahilmgandhi 18:6a4db94011d3 6 ; *
sahilmgandhi 18:6a4db94011d3 7 ; * @note
sahilmgandhi 18:6a4db94011d3 8 ; *
sahilmgandhi 18:6a4db94011d3 9 ; ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 10 ;/* Copyright (c) 2012-2014 ARM LIMITED
sahilmgandhi 18:6a4db94011d3 11 ;
sahilmgandhi 18:6a4db94011d3 12 ; All rights reserved.
sahilmgandhi 18:6a4db94011d3 13 ; Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 14 ; modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 15 ; - Redistributions of source code must retain the above copyright
sahilmgandhi 18:6a4db94011d3 16 ; notice, this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 ; - Redistributions in binary form must reproduce the above copyright
sahilmgandhi 18:6a4db94011d3 18 ; notice, this list of conditions and the following disclaimer in the
sahilmgandhi 18:6a4db94011d3 19 ; documentation and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 20 ; - Neither the name of ARM nor the names of its contributors may be used
sahilmgandhi 18:6a4db94011d3 21 ; to endorse or promote products derived from this software without
sahilmgandhi 18:6a4db94011d3 22 ; specific prior written permission.
sahilmgandhi 18:6a4db94011d3 23 ; *
sahilmgandhi 18:6a4db94011d3 24 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 25 ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 26 ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
sahilmgandhi 18:6a4db94011d3 27 ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
sahilmgandhi 18:6a4db94011d3 28 ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
sahilmgandhi 18:6a4db94011d3 29 ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
sahilmgandhi 18:6a4db94011d3 30 ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
sahilmgandhi 18:6a4db94011d3 31 ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
sahilmgandhi 18:6a4db94011d3 32 ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
sahilmgandhi 18:6a4db94011d3 33 ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sahilmgandhi 18:6a4db94011d3 34 ; POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 35 ; ---------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 38 extern "C" {
sahilmgandhi 18:6a4db94011d3 39 #endif
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 #ifndef _MMU_FUNC_H
sahilmgandhi 18:6a4db94011d3 42 #define _MMU_FUNC_H
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 #define SECTION_DESCRIPTOR (0x2)
sahilmgandhi 18:6a4db94011d3 45 #define SECTION_MASK (0xFFFFFFFC)
sahilmgandhi 18:6a4db94011d3 46
sahilmgandhi 18:6a4db94011d3 47 #define SECTION_TEXCB_MASK (0xFFFF8FF3)
sahilmgandhi 18:6a4db94011d3 48 #define SECTION_B_SHIFT (2)
sahilmgandhi 18:6a4db94011d3 49 #define SECTION_C_SHIFT (3)
sahilmgandhi 18:6a4db94011d3 50 #define SECTION_TEX0_SHIFT (12)
sahilmgandhi 18:6a4db94011d3 51 #define SECTION_TEX1_SHIFT (13)
sahilmgandhi 18:6a4db94011d3 52 #define SECTION_TEX2_SHIFT (14)
sahilmgandhi 18:6a4db94011d3 53
sahilmgandhi 18:6a4db94011d3 54 #define SECTION_XN_MASK (0xFFFFFFEF)
sahilmgandhi 18:6a4db94011d3 55 #define SECTION_XN_SHIFT (4)
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 #define SECTION_DOMAIN_MASK (0xFFFFFE1F)
sahilmgandhi 18:6a4db94011d3 58 #define SECTION_DOMAIN_SHIFT (5)
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 #define SECTION_P_MASK (0xFFFFFDFF)
sahilmgandhi 18:6a4db94011d3 61 #define SECTION_P_SHIFT (9)
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 #define SECTION_AP_MASK (0xFFFF73FF)
sahilmgandhi 18:6a4db94011d3 64 #define SECTION_AP_SHIFT (10)
sahilmgandhi 18:6a4db94011d3 65 #define SECTION_AP2_SHIFT (15)
sahilmgandhi 18:6a4db94011d3 66
sahilmgandhi 18:6a4db94011d3 67 #define SECTION_S_MASK (0xFFFEFFFF)
sahilmgandhi 18:6a4db94011d3 68 #define SECTION_S_SHIFT (16)
sahilmgandhi 18:6a4db94011d3 69
sahilmgandhi 18:6a4db94011d3 70 #define SECTION_NG_MASK (0xFFFDFFFF)
sahilmgandhi 18:6a4db94011d3 71 #define SECTION_NG_SHIFT (17)
sahilmgandhi 18:6a4db94011d3 72
sahilmgandhi 18:6a4db94011d3 73 #define SECTION_NS_MASK (0xFFF7FFFF)
sahilmgandhi 18:6a4db94011d3 74 #define SECTION_NS_SHIFT (19)
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 #define PAGE_L1_DESCRIPTOR (0x1)
sahilmgandhi 18:6a4db94011d3 78 #define PAGE_L1_MASK (0xFFFFFFFC)
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 #define PAGE_L2_4K_DESC (0x2)
sahilmgandhi 18:6a4db94011d3 81 #define PAGE_L2_4K_MASK (0xFFFFFFFD)
sahilmgandhi 18:6a4db94011d3 82
sahilmgandhi 18:6a4db94011d3 83 #define PAGE_L2_64K_DESC (0x1)
sahilmgandhi 18:6a4db94011d3 84 #define PAGE_L2_64K_MASK (0xFFFFFFFC)
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 #define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
sahilmgandhi 18:6a4db94011d3 87 #define PAGE_4K_B_SHIFT (2)
sahilmgandhi 18:6a4db94011d3 88 #define PAGE_4K_C_SHIFT (3)
sahilmgandhi 18:6a4db94011d3 89 #define PAGE_4K_TEX0_SHIFT (6)
sahilmgandhi 18:6a4db94011d3 90 #define PAGE_4K_TEX1_SHIFT (7)
sahilmgandhi 18:6a4db94011d3 91 #define PAGE_4K_TEX2_SHIFT (8)
sahilmgandhi 18:6a4db94011d3 92
sahilmgandhi 18:6a4db94011d3 93 #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
sahilmgandhi 18:6a4db94011d3 94 #define PAGE_64K_B_SHIFT (2)
sahilmgandhi 18:6a4db94011d3 95 #define PAGE_64K_C_SHIFT (3)
sahilmgandhi 18:6a4db94011d3 96 #define PAGE_64K_TEX0_SHIFT (12)
sahilmgandhi 18:6a4db94011d3 97 #define PAGE_64K_TEX1_SHIFT (13)
sahilmgandhi 18:6a4db94011d3 98 #define PAGE_64K_TEX2_SHIFT (14)
sahilmgandhi 18:6a4db94011d3 99
sahilmgandhi 18:6a4db94011d3 100 #define PAGE_TEXCB_MASK (0xFFFF8FF3)
sahilmgandhi 18:6a4db94011d3 101 #define PAGE_B_SHIFT (2)
sahilmgandhi 18:6a4db94011d3 102 #define PAGE_C_SHIFT (3)
sahilmgandhi 18:6a4db94011d3 103 #define PAGE_TEX_SHIFT (12)
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105 #define PAGE_XN_4K_MASK (0xFFFFFFFE)
sahilmgandhi 18:6a4db94011d3 106 #define PAGE_XN_4K_SHIFT (0)
sahilmgandhi 18:6a4db94011d3 107 #define PAGE_XN_64K_MASK (0xFFFF7FFF)
sahilmgandhi 18:6a4db94011d3 108 #define PAGE_XN_64K_SHIFT (15)
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 #define PAGE_DOMAIN_MASK (0xFFFFFE1F)
sahilmgandhi 18:6a4db94011d3 112 #define PAGE_DOMAIN_SHIFT (5)
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 #define PAGE_P_MASK (0xFFFFFDFF)
sahilmgandhi 18:6a4db94011d3 115 #define PAGE_P_SHIFT (9)
sahilmgandhi 18:6a4db94011d3 116
sahilmgandhi 18:6a4db94011d3 117 #define PAGE_AP_MASK (0xFFFFFDCF)
sahilmgandhi 18:6a4db94011d3 118 #define PAGE_AP_SHIFT (4)
sahilmgandhi 18:6a4db94011d3 119 #define PAGE_AP2_SHIFT (9)
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 #define PAGE_S_MASK (0xFFFFFBFF)
sahilmgandhi 18:6a4db94011d3 122 #define PAGE_S_SHIFT (10)
sahilmgandhi 18:6a4db94011d3 123
sahilmgandhi 18:6a4db94011d3 124 #define PAGE_NG_MASK (0xFFFFF7FF)
sahilmgandhi 18:6a4db94011d3 125 #define PAGE_NG_SHIFT (11)
sahilmgandhi 18:6a4db94011d3 126
sahilmgandhi 18:6a4db94011d3 127 #define PAGE_NS_MASK (0xFFFFFFF7)
sahilmgandhi 18:6a4db94011d3 128 #define PAGE_NS_SHIFT (3)
sahilmgandhi 18:6a4db94011d3 129
sahilmgandhi 18:6a4db94011d3 130 #define OFFSET_1M (0x00100000)
sahilmgandhi 18:6a4db94011d3 131 #define OFFSET_64K (0x00010000)
sahilmgandhi 18:6a4db94011d3 132 #define OFFSET_4K (0x00001000)
sahilmgandhi 18:6a4db94011d3 133
sahilmgandhi 18:6a4db94011d3 134 #define DESCRIPTOR_FAULT (0x00000000)
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 /* ########################### MMU Function Access ########################### */
sahilmgandhi 18:6a4db94011d3 137 /** \ingroup MMU_FunctionInterface
sahilmgandhi 18:6a4db94011d3 138 \defgroup MMU_Functions MMU Functions Interface
sahilmgandhi 18:6a4db94011d3 139 @{
sahilmgandhi 18:6a4db94011d3 140 */
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142 /* Attributes enumerations */
sahilmgandhi 18:6a4db94011d3 143
sahilmgandhi 18:6a4db94011d3 144 /* Region size attributes */
sahilmgandhi 18:6a4db94011d3 145 typedef enum
sahilmgandhi 18:6a4db94011d3 146 {
sahilmgandhi 18:6a4db94011d3 147 SECTION,
sahilmgandhi 18:6a4db94011d3 148 PAGE_4k,
sahilmgandhi 18:6a4db94011d3 149 PAGE_64k,
sahilmgandhi 18:6a4db94011d3 150 } mmu_region_size_Type;
sahilmgandhi 18:6a4db94011d3 151
sahilmgandhi 18:6a4db94011d3 152 /* Region type attributes */
sahilmgandhi 18:6a4db94011d3 153 typedef enum
sahilmgandhi 18:6a4db94011d3 154 {
sahilmgandhi 18:6a4db94011d3 155 NORMAL,
sahilmgandhi 18:6a4db94011d3 156 DEVICE,
sahilmgandhi 18:6a4db94011d3 157 SHARED_DEVICE,
sahilmgandhi 18:6a4db94011d3 158 NON_SHARED_DEVICE,
sahilmgandhi 18:6a4db94011d3 159 STRONGLY_ORDERED
sahilmgandhi 18:6a4db94011d3 160 } mmu_memory_Type;
sahilmgandhi 18:6a4db94011d3 161
sahilmgandhi 18:6a4db94011d3 162 /* Region cacheability attributes */
sahilmgandhi 18:6a4db94011d3 163 typedef enum
sahilmgandhi 18:6a4db94011d3 164 {
sahilmgandhi 18:6a4db94011d3 165 NON_CACHEABLE,
sahilmgandhi 18:6a4db94011d3 166 WB_WA,
sahilmgandhi 18:6a4db94011d3 167 WT,
sahilmgandhi 18:6a4db94011d3 168 WB_NO_WA,
sahilmgandhi 18:6a4db94011d3 169 } mmu_cacheability_Type;
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 /* Region parity check attributes */
sahilmgandhi 18:6a4db94011d3 172 typedef enum
sahilmgandhi 18:6a4db94011d3 173 {
sahilmgandhi 18:6a4db94011d3 174 ECC_DISABLED,
sahilmgandhi 18:6a4db94011d3 175 ECC_ENABLED,
sahilmgandhi 18:6a4db94011d3 176 } mmu_ecc_check_Type;
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178 /* Region execution attributes */
sahilmgandhi 18:6a4db94011d3 179 typedef enum
sahilmgandhi 18:6a4db94011d3 180 {
sahilmgandhi 18:6a4db94011d3 181 EXECUTE,
sahilmgandhi 18:6a4db94011d3 182 NON_EXECUTE,
sahilmgandhi 18:6a4db94011d3 183 } mmu_execute_Type;
sahilmgandhi 18:6a4db94011d3 184
sahilmgandhi 18:6a4db94011d3 185 /* Region global attributes */
sahilmgandhi 18:6a4db94011d3 186 typedef enum
sahilmgandhi 18:6a4db94011d3 187 {
sahilmgandhi 18:6a4db94011d3 188 GLOBAL,
sahilmgandhi 18:6a4db94011d3 189 NON_GLOBAL,
sahilmgandhi 18:6a4db94011d3 190 } mmu_global_Type;
sahilmgandhi 18:6a4db94011d3 191
sahilmgandhi 18:6a4db94011d3 192 /* Region shareability attributes */
sahilmgandhi 18:6a4db94011d3 193 typedef enum
sahilmgandhi 18:6a4db94011d3 194 {
sahilmgandhi 18:6a4db94011d3 195 NON_SHARED,
sahilmgandhi 18:6a4db94011d3 196 SHARED,
sahilmgandhi 18:6a4db94011d3 197 } mmu_shared_Type;
sahilmgandhi 18:6a4db94011d3 198
sahilmgandhi 18:6a4db94011d3 199 /* Region security attributes */
sahilmgandhi 18:6a4db94011d3 200 typedef enum
sahilmgandhi 18:6a4db94011d3 201 {
sahilmgandhi 18:6a4db94011d3 202 SECURE,
sahilmgandhi 18:6a4db94011d3 203 NON_SECURE,
sahilmgandhi 18:6a4db94011d3 204 } mmu_secure_Type;
sahilmgandhi 18:6a4db94011d3 205
sahilmgandhi 18:6a4db94011d3 206 /* Region access attributes */
sahilmgandhi 18:6a4db94011d3 207 typedef enum
sahilmgandhi 18:6a4db94011d3 208 {
sahilmgandhi 18:6a4db94011d3 209 NO_ACCESS,
sahilmgandhi 18:6a4db94011d3 210 RW,
sahilmgandhi 18:6a4db94011d3 211 READ,
sahilmgandhi 18:6a4db94011d3 212 } mmu_access_Type;
sahilmgandhi 18:6a4db94011d3 213
sahilmgandhi 18:6a4db94011d3 214 /* Memory Region definition */
sahilmgandhi 18:6a4db94011d3 215 typedef struct RegionStruct {
sahilmgandhi 18:6a4db94011d3 216 mmu_region_size_Type rg_t;
sahilmgandhi 18:6a4db94011d3 217 mmu_memory_Type mem_t;
sahilmgandhi 18:6a4db94011d3 218 uint8_t domain;
sahilmgandhi 18:6a4db94011d3 219 mmu_cacheability_Type inner_norm_t;
sahilmgandhi 18:6a4db94011d3 220 mmu_cacheability_Type outer_norm_t;
sahilmgandhi 18:6a4db94011d3 221 mmu_ecc_check_Type e_t;
sahilmgandhi 18:6a4db94011d3 222 mmu_execute_Type xn_t;
sahilmgandhi 18:6a4db94011d3 223 mmu_global_Type g_t;
sahilmgandhi 18:6a4db94011d3 224 mmu_secure_Type sec_t;
sahilmgandhi 18:6a4db94011d3 225 mmu_access_Type priv_t;
sahilmgandhi 18:6a4db94011d3 226 mmu_access_Type user_t;
sahilmgandhi 18:6a4db94011d3 227 mmu_shared_Type sh_t;
sahilmgandhi 18:6a4db94011d3 228
sahilmgandhi 18:6a4db94011d3 229 } mmu_region_attributes_Type;
sahilmgandhi 18:6a4db94011d3 230
sahilmgandhi 18:6a4db94011d3 231 /** \brief Set section execution-never attribute
sahilmgandhi 18:6a4db94011d3 232
sahilmgandhi 18:6a4db94011d3 233 The function sets section execution-never attribute
sahilmgandhi 18:6a4db94011d3 234
sahilmgandhi 18:6a4db94011d3 235 \param [out] descriptor_l1 L1 descriptor.
sahilmgandhi 18:6a4db94011d3 236 \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
sahilmgandhi 18:6a4db94011d3 237
sahilmgandhi 18:6a4db94011d3 238 \return 0
sahilmgandhi 18:6a4db94011d3 239 */
sahilmgandhi 18:6a4db94011d3 240 __STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
sahilmgandhi 18:6a4db94011d3 241 {
sahilmgandhi 18:6a4db94011d3 242 *descriptor_l1 &= SECTION_XN_MASK;
sahilmgandhi 18:6a4db94011d3 243 *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
sahilmgandhi 18:6a4db94011d3 244 return 0;
sahilmgandhi 18:6a4db94011d3 245 }
sahilmgandhi 18:6a4db94011d3 246
sahilmgandhi 18:6a4db94011d3 247 /** \brief Set section domain
sahilmgandhi 18:6a4db94011d3 248
sahilmgandhi 18:6a4db94011d3 249 The function sets section domain
sahilmgandhi 18:6a4db94011d3 250
sahilmgandhi 18:6a4db94011d3 251 \param [out] descriptor_l1 L1 descriptor.
sahilmgandhi 18:6a4db94011d3 252 \param [in] domain Section domain
sahilmgandhi 18:6a4db94011d3 253
sahilmgandhi 18:6a4db94011d3 254 \return 0
sahilmgandhi 18:6a4db94011d3 255 */
sahilmgandhi 18:6a4db94011d3 256 __STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
sahilmgandhi 18:6a4db94011d3 257 {
sahilmgandhi 18:6a4db94011d3 258 *descriptor_l1 &= SECTION_DOMAIN_MASK;
sahilmgandhi 18:6a4db94011d3 259 *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
sahilmgandhi 18:6a4db94011d3 260 return 0;
sahilmgandhi 18:6a4db94011d3 261 }
sahilmgandhi 18:6a4db94011d3 262
sahilmgandhi 18:6a4db94011d3 263 /** \brief Set section parity check
sahilmgandhi 18:6a4db94011d3 264
sahilmgandhi 18:6a4db94011d3 265 The function sets section parity check
sahilmgandhi 18:6a4db94011d3 266
sahilmgandhi 18:6a4db94011d3 267 \param [out] descriptor_l1 L1 descriptor.
sahilmgandhi 18:6a4db94011d3 268 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
sahilmgandhi 18:6a4db94011d3 269
sahilmgandhi 18:6a4db94011d3 270 \return 0
sahilmgandhi 18:6a4db94011d3 271 */
sahilmgandhi 18:6a4db94011d3 272 __STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
sahilmgandhi 18:6a4db94011d3 273 {
sahilmgandhi 18:6a4db94011d3 274 *descriptor_l1 &= SECTION_P_MASK;
sahilmgandhi 18:6a4db94011d3 275 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
sahilmgandhi 18:6a4db94011d3 276 return 0;
sahilmgandhi 18:6a4db94011d3 277 }
sahilmgandhi 18:6a4db94011d3 278
sahilmgandhi 18:6a4db94011d3 279 /** \brief Set section access privileges
sahilmgandhi 18:6a4db94011d3 280
sahilmgandhi 18:6a4db94011d3 281 The function sets section access privileges
sahilmgandhi 18:6a4db94011d3 282
sahilmgandhi 18:6a4db94011d3 283 \param [out] descriptor_l1 L1 descriptor.
sahilmgandhi 18:6a4db94011d3 284 \param [in] user User Level Access: NO_ACCESS, RW, READ
sahilmgandhi 18:6a4db94011d3 285 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
sahilmgandhi 18:6a4db94011d3 286 \param [in] afe Access flag enable
sahilmgandhi 18:6a4db94011d3 287
sahilmgandhi 18:6a4db94011d3 288 \return 0
sahilmgandhi 18:6a4db94011d3 289 */
sahilmgandhi 18:6a4db94011d3 290 __STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
sahilmgandhi 18:6a4db94011d3 291 {
sahilmgandhi 18:6a4db94011d3 292 uint32_t ap = 0;
sahilmgandhi 18:6a4db94011d3 293
sahilmgandhi 18:6a4db94011d3 294 if (afe == 0) { //full access
sahilmgandhi 18:6a4db94011d3 295 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
sahilmgandhi 18:6a4db94011d3 296 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
sahilmgandhi 18:6a4db94011d3 297 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
sahilmgandhi 18:6a4db94011d3 298 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
sahilmgandhi 18:6a4db94011d3 299 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
sahilmgandhi 18:6a4db94011d3 300 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
sahilmgandhi 18:6a4db94011d3 301 }
sahilmgandhi 18:6a4db94011d3 302
sahilmgandhi 18:6a4db94011d3 303 else { //Simplified access
sahilmgandhi 18:6a4db94011d3 304 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
sahilmgandhi 18:6a4db94011d3 305 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
sahilmgandhi 18:6a4db94011d3 306 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
sahilmgandhi 18:6a4db94011d3 307 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
sahilmgandhi 18:6a4db94011d3 308 }
sahilmgandhi 18:6a4db94011d3 309
sahilmgandhi 18:6a4db94011d3 310 *descriptor_l1 &= SECTION_AP_MASK;
sahilmgandhi 18:6a4db94011d3 311 *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
sahilmgandhi 18:6a4db94011d3 312 *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
sahilmgandhi 18:6a4db94011d3 313
sahilmgandhi 18:6a4db94011d3 314 return 0;
sahilmgandhi 18:6a4db94011d3 315 }
sahilmgandhi 18:6a4db94011d3 316
sahilmgandhi 18:6a4db94011d3 317 /** \brief Set section shareability
sahilmgandhi 18:6a4db94011d3 318
sahilmgandhi 18:6a4db94011d3 319 The function sets section shareability
sahilmgandhi 18:6a4db94011d3 320
sahilmgandhi 18:6a4db94011d3 321 \param [out] descriptor_l1 L1 descriptor.
sahilmgandhi 18:6a4db94011d3 322 \param [in] s_bit Section shareability: NON_SHARED, SHARED
sahilmgandhi 18:6a4db94011d3 323
sahilmgandhi 18:6a4db94011d3 324 \return 0
sahilmgandhi 18:6a4db94011d3 325 */
sahilmgandhi 18:6a4db94011d3 326 __STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
sahilmgandhi 18:6a4db94011d3 327 {
sahilmgandhi 18:6a4db94011d3 328 *descriptor_l1 &= SECTION_S_MASK;
sahilmgandhi 18:6a4db94011d3 329 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
sahilmgandhi 18:6a4db94011d3 330 return 0;
sahilmgandhi 18:6a4db94011d3 331 }
sahilmgandhi 18:6a4db94011d3 332
sahilmgandhi 18:6a4db94011d3 333 /** \brief Set section Global attribute
sahilmgandhi 18:6a4db94011d3 334
sahilmgandhi 18:6a4db94011d3 335 The function sets section Global attribute
sahilmgandhi 18:6a4db94011d3 336
sahilmgandhi 18:6a4db94011d3 337 \param [out] descriptor_l1 L1 descriptor.
sahilmgandhi 18:6a4db94011d3 338 \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
sahilmgandhi 18:6a4db94011d3 339
sahilmgandhi 18:6a4db94011d3 340 \return 0
sahilmgandhi 18:6a4db94011d3 341 */
sahilmgandhi 18:6a4db94011d3 342 __STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
sahilmgandhi 18:6a4db94011d3 343 {
sahilmgandhi 18:6a4db94011d3 344 *descriptor_l1 &= SECTION_NG_MASK;
sahilmgandhi 18:6a4db94011d3 345 *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
sahilmgandhi 18:6a4db94011d3 346 return 0;
sahilmgandhi 18:6a4db94011d3 347 }
sahilmgandhi 18:6a4db94011d3 348
sahilmgandhi 18:6a4db94011d3 349 /** \brief Set section Security attribute
sahilmgandhi 18:6a4db94011d3 350
sahilmgandhi 18:6a4db94011d3 351 The function sets section Global attribute
sahilmgandhi 18:6a4db94011d3 352
sahilmgandhi 18:6a4db94011d3 353 \param [out] descriptor_l1 L1 descriptor.
sahilmgandhi 18:6a4db94011d3 354 \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
sahilmgandhi 18:6a4db94011d3 355
sahilmgandhi 18:6a4db94011d3 356 \return 0
sahilmgandhi 18:6a4db94011d3 357 */
sahilmgandhi 18:6a4db94011d3 358 __STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
sahilmgandhi 18:6a4db94011d3 359 {
sahilmgandhi 18:6a4db94011d3 360 *descriptor_l1 &= SECTION_NS_MASK;
sahilmgandhi 18:6a4db94011d3 361 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
sahilmgandhi 18:6a4db94011d3 362 return 0;
sahilmgandhi 18:6a4db94011d3 363 }
sahilmgandhi 18:6a4db94011d3 364
sahilmgandhi 18:6a4db94011d3 365 /* Page 4k or 64k */
sahilmgandhi 18:6a4db94011d3 366 /** \brief Set 4k/64k page execution-never attribute
sahilmgandhi 18:6a4db94011d3 367
sahilmgandhi 18:6a4db94011d3 368 The function sets 4k/64k page execution-never attribute
sahilmgandhi 18:6a4db94011d3 369
sahilmgandhi 18:6a4db94011d3 370 \param [out] descriptor_l2 L2 descriptor.
sahilmgandhi 18:6a4db94011d3 371 \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
sahilmgandhi 18:6a4db94011d3 372 \param [in] page Page size: PAGE_4k, PAGE_64k,
sahilmgandhi 18:6a4db94011d3 373
sahilmgandhi 18:6a4db94011d3 374 \return 0
sahilmgandhi 18:6a4db94011d3 375 */
sahilmgandhi 18:6a4db94011d3 376 __STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
sahilmgandhi 18:6a4db94011d3 377 {
sahilmgandhi 18:6a4db94011d3 378 if (page == PAGE_4k)
sahilmgandhi 18:6a4db94011d3 379 {
sahilmgandhi 18:6a4db94011d3 380 *descriptor_l2 &= PAGE_XN_4K_MASK;
sahilmgandhi 18:6a4db94011d3 381 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
sahilmgandhi 18:6a4db94011d3 382 }
sahilmgandhi 18:6a4db94011d3 383 else
sahilmgandhi 18:6a4db94011d3 384 {
sahilmgandhi 18:6a4db94011d3 385 *descriptor_l2 &= PAGE_XN_64K_MASK;
sahilmgandhi 18:6a4db94011d3 386 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
sahilmgandhi 18:6a4db94011d3 387 }
sahilmgandhi 18:6a4db94011d3 388 return 0;
sahilmgandhi 18:6a4db94011d3 389 }
sahilmgandhi 18:6a4db94011d3 390
sahilmgandhi 18:6a4db94011d3 391 /** \brief Set 4k/64k page domain
sahilmgandhi 18:6a4db94011d3 392
sahilmgandhi 18:6a4db94011d3 393 The function sets 4k/64k page domain
sahilmgandhi 18:6a4db94011d3 394
sahilmgandhi 18:6a4db94011d3 395 \param [out] descriptor_l1 L1 descriptor.
sahilmgandhi 18:6a4db94011d3 396 \param [in] domain Page domain
sahilmgandhi 18:6a4db94011d3 397
sahilmgandhi 18:6a4db94011d3 398 \return 0
sahilmgandhi 18:6a4db94011d3 399 */
sahilmgandhi 18:6a4db94011d3 400 __STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
sahilmgandhi 18:6a4db94011d3 401 {
sahilmgandhi 18:6a4db94011d3 402 *descriptor_l1 &= PAGE_DOMAIN_MASK;
sahilmgandhi 18:6a4db94011d3 403 *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
sahilmgandhi 18:6a4db94011d3 404 return 0;
sahilmgandhi 18:6a4db94011d3 405 }
sahilmgandhi 18:6a4db94011d3 406
sahilmgandhi 18:6a4db94011d3 407 /** \brief Set 4k/64k page parity check
sahilmgandhi 18:6a4db94011d3 408
sahilmgandhi 18:6a4db94011d3 409 The function sets 4k/64k page parity check
sahilmgandhi 18:6a4db94011d3 410
sahilmgandhi 18:6a4db94011d3 411 \param [out] descriptor_l1 L1 descriptor.
sahilmgandhi 18:6a4db94011d3 412 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
sahilmgandhi 18:6a4db94011d3 413
sahilmgandhi 18:6a4db94011d3 414 \return 0
sahilmgandhi 18:6a4db94011d3 415 */
sahilmgandhi 18:6a4db94011d3 416 __STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
sahilmgandhi 18:6a4db94011d3 417 {
sahilmgandhi 18:6a4db94011d3 418 *descriptor_l1 &= SECTION_P_MASK;
sahilmgandhi 18:6a4db94011d3 419 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
sahilmgandhi 18:6a4db94011d3 420 return 0;
sahilmgandhi 18:6a4db94011d3 421 }
sahilmgandhi 18:6a4db94011d3 422
sahilmgandhi 18:6a4db94011d3 423 /** \brief Set 4k/64k page access privileges
sahilmgandhi 18:6a4db94011d3 424
sahilmgandhi 18:6a4db94011d3 425 The function sets 4k/64k page access privileges
sahilmgandhi 18:6a4db94011d3 426
sahilmgandhi 18:6a4db94011d3 427 \param [out] descriptor_l2 L2 descriptor.
sahilmgandhi 18:6a4db94011d3 428 \param [in] user User Level Access: NO_ACCESS, RW, READ
sahilmgandhi 18:6a4db94011d3 429 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
sahilmgandhi 18:6a4db94011d3 430 \param [in] afe Access flag enable
sahilmgandhi 18:6a4db94011d3 431
sahilmgandhi 18:6a4db94011d3 432 \return 0
sahilmgandhi 18:6a4db94011d3 433 */
sahilmgandhi 18:6a4db94011d3 434 __STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
sahilmgandhi 18:6a4db94011d3 435 {
sahilmgandhi 18:6a4db94011d3 436 uint32_t ap = 0;
sahilmgandhi 18:6a4db94011d3 437
sahilmgandhi 18:6a4db94011d3 438 if (afe == 0) { //full access
sahilmgandhi 18:6a4db94011d3 439 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
sahilmgandhi 18:6a4db94011d3 440 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
sahilmgandhi 18:6a4db94011d3 441 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
sahilmgandhi 18:6a4db94011d3 442 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
sahilmgandhi 18:6a4db94011d3 443 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
sahilmgandhi 18:6a4db94011d3 444 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
sahilmgandhi 18:6a4db94011d3 445 }
sahilmgandhi 18:6a4db94011d3 446
sahilmgandhi 18:6a4db94011d3 447 else { //Simplified access
sahilmgandhi 18:6a4db94011d3 448 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
sahilmgandhi 18:6a4db94011d3 449 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
sahilmgandhi 18:6a4db94011d3 450 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
sahilmgandhi 18:6a4db94011d3 451 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
sahilmgandhi 18:6a4db94011d3 452 }
sahilmgandhi 18:6a4db94011d3 453
sahilmgandhi 18:6a4db94011d3 454 *descriptor_l2 &= PAGE_AP_MASK;
sahilmgandhi 18:6a4db94011d3 455 *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
sahilmgandhi 18:6a4db94011d3 456 *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
sahilmgandhi 18:6a4db94011d3 457
sahilmgandhi 18:6a4db94011d3 458 return 0;
sahilmgandhi 18:6a4db94011d3 459 }
sahilmgandhi 18:6a4db94011d3 460
sahilmgandhi 18:6a4db94011d3 461 /** \brief Set 4k/64k page shareability
sahilmgandhi 18:6a4db94011d3 462
sahilmgandhi 18:6a4db94011d3 463 The function sets 4k/64k page shareability
sahilmgandhi 18:6a4db94011d3 464
sahilmgandhi 18:6a4db94011d3 465 \param [out] descriptor_l2 L2 descriptor.
sahilmgandhi 18:6a4db94011d3 466 \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
sahilmgandhi 18:6a4db94011d3 467
sahilmgandhi 18:6a4db94011d3 468 \return 0
sahilmgandhi 18:6a4db94011d3 469 */
sahilmgandhi 18:6a4db94011d3 470 __STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
sahilmgandhi 18:6a4db94011d3 471 {
sahilmgandhi 18:6a4db94011d3 472 *descriptor_l2 &= PAGE_S_MASK;
sahilmgandhi 18:6a4db94011d3 473 *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
sahilmgandhi 18:6a4db94011d3 474 return 0;
sahilmgandhi 18:6a4db94011d3 475 }
sahilmgandhi 18:6a4db94011d3 476
sahilmgandhi 18:6a4db94011d3 477 /** \brief Set 4k/64k page Global attribute
sahilmgandhi 18:6a4db94011d3 478
sahilmgandhi 18:6a4db94011d3 479 The function sets 4k/64k page Global attribute
sahilmgandhi 18:6a4db94011d3 480
sahilmgandhi 18:6a4db94011d3 481 \param [out] descriptor_l2 L2 descriptor.
sahilmgandhi 18:6a4db94011d3 482 \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
sahilmgandhi 18:6a4db94011d3 483
sahilmgandhi 18:6a4db94011d3 484 \return 0
sahilmgandhi 18:6a4db94011d3 485 */
sahilmgandhi 18:6a4db94011d3 486 __STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
sahilmgandhi 18:6a4db94011d3 487 {
sahilmgandhi 18:6a4db94011d3 488 *descriptor_l2 &= PAGE_NG_MASK;
sahilmgandhi 18:6a4db94011d3 489 *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
sahilmgandhi 18:6a4db94011d3 490 return 0;
sahilmgandhi 18:6a4db94011d3 491 }
sahilmgandhi 18:6a4db94011d3 492
sahilmgandhi 18:6a4db94011d3 493 /** \brief Set 4k/64k page Security attribute
sahilmgandhi 18:6a4db94011d3 494
sahilmgandhi 18:6a4db94011d3 495 The function sets 4k/64k page Global attribute
sahilmgandhi 18:6a4db94011d3 496
sahilmgandhi 18:6a4db94011d3 497 \param [out] descriptor_l1 L1 descriptor.
sahilmgandhi 18:6a4db94011d3 498 \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
sahilmgandhi 18:6a4db94011d3 499
sahilmgandhi 18:6a4db94011d3 500 \return 0
sahilmgandhi 18:6a4db94011d3 501 */
sahilmgandhi 18:6a4db94011d3 502 __STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
sahilmgandhi 18:6a4db94011d3 503 {
sahilmgandhi 18:6a4db94011d3 504 *descriptor_l1 &= PAGE_NS_MASK;
sahilmgandhi 18:6a4db94011d3 505 *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
sahilmgandhi 18:6a4db94011d3 506 return 0;
sahilmgandhi 18:6a4db94011d3 507 }
sahilmgandhi 18:6a4db94011d3 508
sahilmgandhi 18:6a4db94011d3 509
sahilmgandhi 18:6a4db94011d3 510 /** \brief Set Section memory attributes
sahilmgandhi 18:6a4db94011d3 511
sahilmgandhi 18:6a4db94011d3 512 The function sets section memory attributes
sahilmgandhi 18:6a4db94011d3 513
sahilmgandhi 18:6a4db94011d3 514 \param [out] descriptor_l1 L1 descriptor.
sahilmgandhi 18:6a4db94011d3 515 \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
sahilmgandhi 18:6a4db94011d3 516 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
sahilmgandhi 18:6a4db94011d3 517 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
sahilmgandhi 18:6a4db94011d3 518
sahilmgandhi 18:6a4db94011d3 519 \return 0
sahilmgandhi 18:6a4db94011d3 520 */
sahilmgandhi 18:6a4db94011d3 521 __STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
sahilmgandhi 18:6a4db94011d3 522 {
sahilmgandhi 18:6a4db94011d3 523 *descriptor_l1 &= SECTION_TEXCB_MASK;
sahilmgandhi 18:6a4db94011d3 524
sahilmgandhi 18:6a4db94011d3 525 if (STRONGLY_ORDERED == mem)
sahilmgandhi 18:6a4db94011d3 526 {
sahilmgandhi 18:6a4db94011d3 527 return 0;
sahilmgandhi 18:6a4db94011d3 528 }
sahilmgandhi 18:6a4db94011d3 529 else if (SHARED_DEVICE == mem)
sahilmgandhi 18:6a4db94011d3 530 {
sahilmgandhi 18:6a4db94011d3 531 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
sahilmgandhi 18:6a4db94011d3 532 }
sahilmgandhi 18:6a4db94011d3 533 else if (NON_SHARED_DEVICE == mem)
sahilmgandhi 18:6a4db94011d3 534 {
sahilmgandhi 18:6a4db94011d3 535 *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
sahilmgandhi 18:6a4db94011d3 536 }
sahilmgandhi 18:6a4db94011d3 537 else if (NORMAL == mem)
sahilmgandhi 18:6a4db94011d3 538 {
sahilmgandhi 18:6a4db94011d3 539 *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
sahilmgandhi 18:6a4db94011d3 540 switch(inner)
sahilmgandhi 18:6a4db94011d3 541 {
sahilmgandhi 18:6a4db94011d3 542 case NON_CACHEABLE:
sahilmgandhi 18:6a4db94011d3 543 break;
sahilmgandhi 18:6a4db94011d3 544 case WB_WA:
sahilmgandhi 18:6a4db94011d3 545 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
sahilmgandhi 18:6a4db94011d3 546 break;
sahilmgandhi 18:6a4db94011d3 547 case WT:
sahilmgandhi 18:6a4db94011d3 548 *descriptor_l1 |= 1 << SECTION_C_SHIFT;
sahilmgandhi 18:6a4db94011d3 549 break;
sahilmgandhi 18:6a4db94011d3 550 case WB_NO_WA:
sahilmgandhi 18:6a4db94011d3 551 *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
sahilmgandhi 18:6a4db94011d3 552 break;
sahilmgandhi 18:6a4db94011d3 553 }
sahilmgandhi 18:6a4db94011d3 554 switch(outer)
sahilmgandhi 18:6a4db94011d3 555 {
sahilmgandhi 18:6a4db94011d3 556 case NON_CACHEABLE:
sahilmgandhi 18:6a4db94011d3 557 break;
sahilmgandhi 18:6a4db94011d3 558 case WB_WA:
sahilmgandhi 18:6a4db94011d3 559 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
sahilmgandhi 18:6a4db94011d3 560 break;
sahilmgandhi 18:6a4db94011d3 561 case WT:
sahilmgandhi 18:6a4db94011d3 562 *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
sahilmgandhi 18:6a4db94011d3 563 break;
sahilmgandhi 18:6a4db94011d3 564 case WB_NO_WA:
sahilmgandhi 18:6a4db94011d3 565 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
sahilmgandhi 18:6a4db94011d3 566 break;
sahilmgandhi 18:6a4db94011d3 567 }
sahilmgandhi 18:6a4db94011d3 568 }
sahilmgandhi 18:6a4db94011d3 569
sahilmgandhi 18:6a4db94011d3 570 return 0;
sahilmgandhi 18:6a4db94011d3 571 }
sahilmgandhi 18:6a4db94011d3 572
sahilmgandhi 18:6a4db94011d3 573 /** \brief Set 4k/64k page memory attributes
sahilmgandhi 18:6a4db94011d3 574
sahilmgandhi 18:6a4db94011d3 575 The function sets 4k/64k page memory attributes
sahilmgandhi 18:6a4db94011d3 576
sahilmgandhi 18:6a4db94011d3 577 \param [out] descriptor_l2 L2 descriptor.
sahilmgandhi 18:6a4db94011d3 578 \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
sahilmgandhi 18:6a4db94011d3 579 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
sahilmgandhi 18:6a4db94011d3 580 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
sahilmgandhi 18:6a4db94011d3 581
sahilmgandhi 18:6a4db94011d3 582 \return 0
sahilmgandhi 18:6a4db94011d3 583 */
sahilmgandhi 18:6a4db94011d3 584 __STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
sahilmgandhi 18:6a4db94011d3 585 {
sahilmgandhi 18:6a4db94011d3 586 *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
sahilmgandhi 18:6a4db94011d3 587
sahilmgandhi 18:6a4db94011d3 588 if (page == PAGE_64k)
sahilmgandhi 18:6a4db94011d3 589 {
sahilmgandhi 18:6a4db94011d3 590 //same as section
sahilmgandhi 18:6a4db94011d3 591 __memory_section(descriptor_l2, mem, outer, inner);
sahilmgandhi 18:6a4db94011d3 592 }
sahilmgandhi 18:6a4db94011d3 593 else
sahilmgandhi 18:6a4db94011d3 594 {
sahilmgandhi 18:6a4db94011d3 595 if (STRONGLY_ORDERED == mem)
sahilmgandhi 18:6a4db94011d3 596 {
sahilmgandhi 18:6a4db94011d3 597 return 0;
sahilmgandhi 18:6a4db94011d3 598 }
sahilmgandhi 18:6a4db94011d3 599 else if (SHARED_DEVICE == mem)
sahilmgandhi 18:6a4db94011d3 600 {
sahilmgandhi 18:6a4db94011d3 601 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
sahilmgandhi 18:6a4db94011d3 602 }
sahilmgandhi 18:6a4db94011d3 603 else if (NON_SHARED_DEVICE == mem)
sahilmgandhi 18:6a4db94011d3 604 {
sahilmgandhi 18:6a4db94011d3 605 *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
sahilmgandhi 18:6a4db94011d3 606 }
sahilmgandhi 18:6a4db94011d3 607 else if (NORMAL == mem)
sahilmgandhi 18:6a4db94011d3 608 {
sahilmgandhi 18:6a4db94011d3 609 *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
sahilmgandhi 18:6a4db94011d3 610 switch(inner)
sahilmgandhi 18:6a4db94011d3 611 {
sahilmgandhi 18:6a4db94011d3 612 case NON_CACHEABLE:
sahilmgandhi 18:6a4db94011d3 613 break;
sahilmgandhi 18:6a4db94011d3 614 case WB_WA:
sahilmgandhi 18:6a4db94011d3 615 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
sahilmgandhi 18:6a4db94011d3 616 break;
sahilmgandhi 18:6a4db94011d3 617 case WT:
sahilmgandhi 18:6a4db94011d3 618 *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
sahilmgandhi 18:6a4db94011d3 619 break;
sahilmgandhi 18:6a4db94011d3 620 case WB_NO_WA:
sahilmgandhi 18:6a4db94011d3 621 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
sahilmgandhi 18:6a4db94011d3 622 break;
sahilmgandhi 18:6a4db94011d3 623 }
sahilmgandhi 18:6a4db94011d3 624 switch(outer)
sahilmgandhi 18:6a4db94011d3 625 {
sahilmgandhi 18:6a4db94011d3 626 case NON_CACHEABLE:
sahilmgandhi 18:6a4db94011d3 627 break;
sahilmgandhi 18:6a4db94011d3 628 case WB_WA:
sahilmgandhi 18:6a4db94011d3 629 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
sahilmgandhi 18:6a4db94011d3 630 break;
sahilmgandhi 18:6a4db94011d3 631 case WT:
sahilmgandhi 18:6a4db94011d3 632 *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
sahilmgandhi 18:6a4db94011d3 633 break;
sahilmgandhi 18:6a4db94011d3 634 case WB_NO_WA:
sahilmgandhi 18:6a4db94011d3 635 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
sahilmgandhi 18:6a4db94011d3 636 break;
sahilmgandhi 18:6a4db94011d3 637 }
sahilmgandhi 18:6a4db94011d3 638 }
sahilmgandhi 18:6a4db94011d3 639 }
sahilmgandhi 18:6a4db94011d3 640
sahilmgandhi 18:6a4db94011d3 641 return 0;
sahilmgandhi 18:6a4db94011d3 642 }
sahilmgandhi 18:6a4db94011d3 643
sahilmgandhi 18:6a4db94011d3 644 /** \brief Create a L1 section descriptor
sahilmgandhi 18:6a4db94011d3 645
sahilmgandhi 18:6a4db94011d3 646 The function creates a section descriptor.
sahilmgandhi 18:6a4db94011d3 647
sahilmgandhi 18:6a4db94011d3 648 Assumptions:
sahilmgandhi 18:6a4db94011d3 649 - 16MB super sections not supported
sahilmgandhi 18:6a4db94011d3 650 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
sahilmgandhi 18:6a4db94011d3 651 - Functions always return 0
sahilmgandhi 18:6a4db94011d3 652
sahilmgandhi 18:6a4db94011d3 653 \param [out] descriptor L1 descriptor
sahilmgandhi 18:6a4db94011d3 654 \param [out] descriptor2 L2 descriptor
sahilmgandhi 18:6a4db94011d3 655 \param [in] reg Section attributes
sahilmgandhi 18:6a4db94011d3 656
sahilmgandhi 18:6a4db94011d3 657 \return 0
sahilmgandhi 18:6a4db94011d3 658 */
sahilmgandhi 18:6a4db94011d3 659 __STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
sahilmgandhi 18:6a4db94011d3 660 {
sahilmgandhi 18:6a4db94011d3 661 *descriptor = 0;
sahilmgandhi 18:6a4db94011d3 662
sahilmgandhi 18:6a4db94011d3 663 __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
sahilmgandhi 18:6a4db94011d3 664 __xn_section(descriptor,reg.xn_t);
sahilmgandhi 18:6a4db94011d3 665 __domain_section(descriptor, reg.domain);
sahilmgandhi 18:6a4db94011d3 666 __p_section(descriptor, reg.e_t);
sahilmgandhi 18:6a4db94011d3 667 __ap_section(descriptor, reg.priv_t, reg.user_t, 1);
sahilmgandhi 18:6a4db94011d3 668 __shared_section(descriptor,reg.sh_t);
sahilmgandhi 18:6a4db94011d3 669 __global_section(descriptor,reg.g_t);
sahilmgandhi 18:6a4db94011d3 670 __secure_section(descriptor,reg.sec_t);
sahilmgandhi 18:6a4db94011d3 671 *descriptor &= SECTION_MASK;
sahilmgandhi 18:6a4db94011d3 672 *descriptor |= SECTION_DESCRIPTOR;
sahilmgandhi 18:6a4db94011d3 673
sahilmgandhi 18:6a4db94011d3 674 return 0;
sahilmgandhi 18:6a4db94011d3 675
sahilmgandhi 18:6a4db94011d3 676 }
sahilmgandhi 18:6a4db94011d3 677
sahilmgandhi 18:6a4db94011d3 678
sahilmgandhi 18:6a4db94011d3 679 /** \brief Create a L1 and L2 4k/64k page descriptor
sahilmgandhi 18:6a4db94011d3 680
sahilmgandhi 18:6a4db94011d3 681 The function creates a 4k/64k page descriptor.
sahilmgandhi 18:6a4db94011d3 682 Assumptions:
sahilmgandhi 18:6a4db94011d3 683 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
sahilmgandhi 18:6a4db94011d3 684 - Functions always return 0
sahilmgandhi 18:6a4db94011d3 685
sahilmgandhi 18:6a4db94011d3 686 \param [out] descriptor L1 descriptor
sahilmgandhi 18:6a4db94011d3 687 \param [out] descriptor2 L2 descriptor
sahilmgandhi 18:6a4db94011d3 688 \param [in] reg 4k/64k page attributes
sahilmgandhi 18:6a4db94011d3 689
sahilmgandhi 18:6a4db94011d3 690 \return 0
sahilmgandhi 18:6a4db94011d3 691 */
sahilmgandhi 18:6a4db94011d3 692 __STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
sahilmgandhi 18:6a4db94011d3 693 {
sahilmgandhi 18:6a4db94011d3 694 *descriptor = 0;
sahilmgandhi 18:6a4db94011d3 695 *descriptor2 = 0;
sahilmgandhi 18:6a4db94011d3 696
sahilmgandhi 18:6a4db94011d3 697 switch (reg.rg_t)
sahilmgandhi 18:6a4db94011d3 698 {
sahilmgandhi 18:6a4db94011d3 699 case PAGE_4k:
sahilmgandhi 18:6a4db94011d3 700 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
sahilmgandhi 18:6a4db94011d3 701 __xn_page(descriptor2, reg.xn_t, PAGE_4k);
sahilmgandhi 18:6a4db94011d3 702 __domain_page(descriptor, reg.domain);
sahilmgandhi 18:6a4db94011d3 703 __p_page(descriptor, reg.e_t);
sahilmgandhi 18:6a4db94011d3 704 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
sahilmgandhi 18:6a4db94011d3 705 __shared_page(descriptor2,reg.sh_t);
sahilmgandhi 18:6a4db94011d3 706 __global_page(descriptor2,reg.g_t);
sahilmgandhi 18:6a4db94011d3 707 __secure_page(descriptor,reg.sec_t);
sahilmgandhi 18:6a4db94011d3 708 *descriptor &= PAGE_L1_MASK;
sahilmgandhi 18:6a4db94011d3 709 *descriptor |= PAGE_L1_DESCRIPTOR;
sahilmgandhi 18:6a4db94011d3 710 *descriptor2 &= PAGE_L2_4K_MASK;
sahilmgandhi 18:6a4db94011d3 711 *descriptor2 |= PAGE_L2_4K_DESC;
sahilmgandhi 18:6a4db94011d3 712 break;
sahilmgandhi 18:6a4db94011d3 713
sahilmgandhi 18:6a4db94011d3 714 case PAGE_64k:
sahilmgandhi 18:6a4db94011d3 715 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
sahilmgandhi 18:6a4db94011d3 716 __xn_page(descriptor2, reg.xn_t, PAGE_64k);
sahilmgandhi 18:6a4db94011d3 717 __domain_page(descriptor, reg.domain);
sahilmgandhi 18:6a4db94011d3 718 __p_page(descriptor, reg.e_t);
sahilmgandhi 18:6a4db94011d3 719 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
sahilmgandhi 18:6a4db94011d3 720 __shared_page(descriptor2,reg.sh_t);
sahilmgandhi 18:6a4db94011d3 721 __global_page(descriptor2,reg.g_t);
sahilmgandhi 18:6a4db94011d3 722 __secure_page(descriptor,reg.sec_t);
sahilmgandhi 18:6a4db94011d3 723 *descriptor &= PAGE_L1_MASK;
sahilmgandhi 18:6a4db94011d3 724 *descriptor |= PAGE_L1_DESCRIPTOR;
sahilmgandhi 18:6a4db94011d3 725 *descriptor2 &= PAGE_L2_64K_MASK;
sahilmgandhi 18:6a4db94011d3 726 *descriptor2 |= PAGE_L2_64K_DESC;
sahilmgandhi 18:6a4db94011d3 727 break;
sahilmgandhi 18:6a4db94011d3 728
sahilmgandhi 18:6a4db94011d3 729 case SECTION:
sahilmgandhi 18:6a4db94011d3 730 //error
sahilmgandhi 18:6a4db94011d3 731 break;
sahilmgandhi 18:6a4db94011d3 732
sahilmgandhi 18:6a4db94011d3 733 }
sahilmgandhi 18:6a4db94011d3 734
sahilmgandhi 18:6a4db94011d3 735 return 0;
sahilmgandhi 18:6a4db94011d3 736
sahilmgandhi 18:6a4db94011d3 737 }
sahilmgandhi 18:6a4db94011d3 738
sahilmgandhi 18:6a4db94011d3 739 /** \brief Create a 1MB Section
sahilmgandhi 18:6a4db94011d3 740
sahilmgandhi 18:6a4db94011d3 741 \param [in] ttb Translation table base address
sahilmgandhi 18:6a4db94011d3 742 \param [in] base_address Section base address
sahilmgandhi 18:6a4db94011d3 743 \param [in] count Number of sections to create
sahilmgandhi 18:6a4db94011d3 744 \param [in] descriptor_l1 L1 descriptor (region attributes)
sahilmgandhi 18:6a4db94011d3 745
sahilmgandhi 18:6a4db94011d3 746 */
sahilmgandhi 18:6a4db94011d3 747 __STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
sahilmgandhi 18:6a4db94011d3 748 {
sahilmgandhi 18:6a4db94011d3 749 uint32_t offset;
sahilmgandhi 18:6a4db94011d3 750 uint32_t entry;
sahilmgandhi 18:6a4db94011d3 751 uint32_t i;
sahilmgandhi 18:6a4db94011d3 752
sahilmgandhi 18:6a4db94011d3 753 offset = base_address >> 20;
sahilmgandhi 18:6a4db94011d3 754 entry = (base_address & 0xFFF00000) | descriptor_l1;
sahilmgandhi 18:6a4db94011d3 755
sahilmgandhi 18:6a4db94011d3 756 //4 bytes aligned
sahilmgandhi 18:6a4db94011d3 757 ttb = ttb + offset;
sahilmgandhi 18:6a4db94011d3 758
sahilmgandhi 18:6a4db94011d3 759 for (i = 0; i < count; i++ )
sahilmgandhi 18:6a4db94011d3 760 {
sahilmgandhi 18:6a4db94011d3 761 //4 bytes aligned
sahilmgandhi 18:6a4db94011d3 762 *ttb++ = entry;
sahilmgandhi 18:6a4db94011d3 763 entry += OFFSET_1M;
sahilmgandhi 18:6a4db94011d3 764 }
sahilmgandhi 18:6a4db94011d3 765 }
sahilmgandhi 18:6a4db94011d3 766
sahilmgandhi 18:6a4db94011d3 767 /** \brief Create a 4k page entry
sahilmgandhi 18:6a4db94011d3 768
sahilmgandhi 18:6a4db94011d3 769 \param [in] ttb L1 table base address
sahilmgandhi 18:6a4db94011d3 770 \param [in] base_address 4k base address
sahilmgandhi 18:6a4db94011d3 771 \param [in] count Number of 4k pages to create
sahilmgandhi 18:6a4db94011d3 772 \param [in] descriptor_l1 L1 descriptor (region attributes)
sahilmgandhi 18:6a4db94011d3 773 \param [in] ttb_l2 L2 table base address
sahilmgandhi 18:6a4db94011d3 774 \param [in] descriptor_l2 L2 descriptor (region attributes)
sahilmgandhi 18:6a4db94011d3 775
sahilmgandhi 18:6a4db94011d3 776 */
sahilmgandhi 18:6a4db94011d3 777 __STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
sahilmgandhi 18:6a4db94011d3 778 {
sahilmgandhi 18:6a4db94011d3 779
sahilmgandhi 18:6a4db94011d3 780 uint32_t offset, offset2;
sahilmgandhi 18:6a4db94011d3 781 uint32_t entry, entry2;
sahilmgandhi 18:6a4db94011d3 782 uint32_t i;
sahilmgandhi 18:6a4db94011d3 783
sahilmgandhi 18:6a4db94011d3 784
sahilmgandhi 18:6a4db94011d3 785 offset = base_address >> 20;
sahilmgandhi 18:6a4db94011d3 786 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
sahilmgandhi 18:6a4db94011d3 787
sahilmgandhi 18:6a4db94011d3 788 //4 bytes aligned
sahilmgandhi 18:6a4db94011d3 789 ttb += offset;
sahilmgandhi 18:6a4db94011d3 790 //create l1_entry
sahilmgandhi 18:6a4db94011d3 791 *ttb = entry;
sahilmgandhi 18:6a4db94011d3 792
sahilmgandhi 18:6a4db94011d3 793 offset2 = (base_address & 0xff000) >> 12;
sahilmgandhi 18:6a4db94011d3 794 ttb_l2 += offset2;
sahilmgandhi 18:6a4db94011d3 795 entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
sahilmgandhi 18:6a4db94011d3 796 for (i = 0; i < count; i++ )
sahilmgandhi 18:6a4db94011d3 797 {
sahilmgandhi 18:6a4db94011d3 798 //4 bytes aligned
sahilmgandhi 18:6a4db94011d3 799 *ttb_l2++ = entry2;
sahilmgandhi 18:6a4db94011d3 800 entry2 += OFFSET_4K;
sahilmgandhi 18:6a4db94011d3 801 }
sahilmgandhi 18:6a4db94011d3 802 }
sahilmgandhi 18:6a4db94011d3 803
sahilmgandhi 18:6a4db94011d3 804 /** \brief Create a 64k page entry
sahilmgandhi 18:6a4db94011d3 805
sahilmgandhi 18:6a4db94011d3 806 \param [in] ttb L1 table base address
sahilmgandhi 18:6a4db94011d3 807 \param [in] base_address 64k base address
sahilmgandhi 18:6a4db94011d3 808 \param [in] count Number of 64k pages to create
sahilmgandhi 18:6a4db94011d3 809 \param [in] descriptor_l1 L1 descriptor (region attributes)
sahilmgandhi 18:6a4db94011d3 810 \param [in] ttb_l2 L2 table base address
sahilmgandhi 18:6a4db94011d3 811 \param [in] descriptor_l2 L2 descriptor (region attributes)
sahilmgandhi 18:6a4db94011d3 812
sahilmgandhi 18:6a4db94011d3 813 */
sahilmgandhi 18:6a4db94011d3 814 __STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
sahilmgandhi 18:6a4db94011d3 815 {
sahilmgandhi 18:6a4db94011d3 816 uint32_t offset, offset2;
sahilmgandhi 18:6a4db94011d3 817 uint32_t entry, entry2;
sahilmgandhi 18:6a4db94011d3 818 uint32_t i,j;
sahilmgandhi 18:6a4db94011d3 819
sahilmgandhi 18:6a4db94011d3 820
sahilmgandhi 18:6a4db94011d3 821 offset = base_address >> 20;
sahilmgandhi 18:6a4db94011d3 822 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
sahilmgandhi 18:6a4db94011d3 823
sahilmgandhi 18:6a4db94011d3 824 //4 bytes aligned
sahilmgandhi 18:6a4db94011d3 825 ttb += offset;
sahilmgandhi 18:6a4db94011d3 826 //create l1_entry
sahilmgandhi 18:6a4db94011d3 827 *ttb = entry;
sahilmgandhi 18:6a4db94011d3 828
sahilmgandhi 18:6a4db94011d3 829 offset2 = (base_address & 0xff000) >> 12;
sahilmgandhi 18:6a4db94011d3 830 ttb_l2 += offset2;
sahilmgandhi 18:6a4db94011d3 831 entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
sahilmgandhi 18:6a4db94011d3 832 for (i = 0; i < count; i++ )
sahilmgandhi 18:6a4db94011d3 833 {
sahilmgandhi 18:6a4db94011d3 834 //create 16 entries
sahilmgandhi 18:6a4db94011d3 835 for (j = 0; j < 16; j++)
sahilmgandhi 18:6a4db94011d3 836 //4 bytes aligned
sahilmgandhi 18:6a4db94011d3 837 *ttb_l2++ = entry2;
sahilmgandhi 18:6a4db94011d3 838 entry2 += OFFSET_64K;
sahilmgandhi 18:6a4db94011d3 839 }
sahilmgandhi 18:6a4db94011d3 840 }
sahilmgandhi 18:6a4db94011d3 841
sahilmgandhi 18:6a4db94011d3 842 /*@} end of MMU_Functions */
sahilmgandhi 18:6a4db94011d3 843 #endif
sahilmgandhi 18:6a4db94011d3 844
sahilmgandhi 18:6a4db94011d3 845 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 846 }
sahilmgandhi 18:6a4db94011d3 847 #endif