MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/cmsis/core_caFunc.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file core_caFunc.h
sahilmgandhi 18:6a4db94011d3 3 * @brief CMSIS Cortex-A Core Function Access Header File
sahilmgandhi 18:6a4db94011d3 4 * @version V3.10
sahilmgandhi 18:6a4db94011d3 5 * @date 30 Oct 2013
sahilmgandhi 18:6a4db94011d3 6 *
sahilmgandhi 18:6a4db94011d3 7 * @note
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
sahilmgandhi 18:6a4db94011d3 11
sahilmgandhi 18:6a4db94011d3 12 All rights reserved.
sahilmgandhi 18:6a4db94011d3 13 Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 14 modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 15 - Redistributions of source code must retain the above copyright
sahilmgandhi 18:6a4db94011d3 16 notice, this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 - Redistributions in binary form must reproduce the above copyright
sahilmgandhi 18:6a4db94011d3 18 notice, this list of conditions and the following disclaimer in the
sahilmgandhi 18:6a4db94011d3 19 documentation and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 20 - Neither the name of ARM nor the names of its contributors may be used
sahilmgandhi 18:6a4db94011d3 21 to endorse or promote products derived from this software without
sahilmgandhi 18:6a4db94011d3 22 specific prior written permission.
sahilmgandhi 18:6a4db94011d3 23 *
sahilmgandhi 18:6a4db94011d3 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
sahilmgandhi 18:6a4db94011d3 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
sahilmgandhi 18:6a4db94011d3 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
sahilmgandhi 18:6a4db94011d3 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
sahilmgandhi 18:6a4db94011d3 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
sahilmgandhi 18:6a4db94011d3 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
sahilmgandhi 18:6a4db94011d3 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
sahilmgandhi 18:6a4db94011d3 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sahilmgandhi 18:6a4db94011d3 34 POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 35 ---------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 #ifndef __CORE_CAFUNC_H__
sahilmgandhi 18:6a4db94011d3 39 #define __CORE_CAFUNC_H__
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 /* ########################### Core Function Access ########################### */
sahilmgandhi 18:6a4db94011d3 43 /** \ingroup CMSIS_Core_FunctionInterface
sahilmgandhi 18:6a4db94011d3 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
sahilmgandhi 18:6a4db94011d3 45 @{
sahilmgandhi 18:6a4db94011d3 46 */
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
sahilmgandhi 18:6a4db94011d3 49 /* ARM armcc specific functions */
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 #if (__ARMCC_VERSION < 400677)
sahilmgandhi 18:6a4db94011d3 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
sahilmgandhi 18:6a4db94011d3 53 #endif
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 #define MODE_USR 0x10
sahilmgandhi 18:6a4db94011d3 56 #define MODE_FIQ 0x11
sahilmgandhi 18:6a4db94011d3 57 #define MODE_IRQ 0x12
sahilmgandhi 18:6a4db94011d3 58 #define MODE_SVC 0x13
sahilmgandhi 18:6a4db94011d3 59 #define MODE_MON 0x16
sahilmgandhi 18:6a4db94011d3 60 #define MODE_ABT 0x17
sahilmgandhi 18:6a4db94011d3 61 #define MODE_HYP 0x1A
sahilmgandhi 18:6a4db94011d3 62 #define MODE_UND 0x1B
sahilmgandhi 18:6a4db94011d3 63 #define MODE_SYS 0x1F
sahilmgandhi 18:6a4db94011d3 64
sahilmgandhi 18:6a4db94011d3 65 /** \brief Get APSR Register
sahilmgandhi 18:6a4db94011d3 66
sahilmgandhi 18:6a4db94011d3 67 This function returns the content of the APSR Register.
sahilmgandhi 18:6a4db94011d3 68
sahilmgandhi 18:6a4db94011d3 69 \return APSR Register value
sahilmgandhi 18:6a4db94011d3 70 */
sahilmgandhi 18:6a4db94011d3 71 __STATIC_INLINE uint32_t __get_APSR(void)
sahilmgandhi 18:6a4db94011d3 72 {
sahilmgandhi 18:6a4db94011d3 73 register uint32_t __regAPSR __ASM("apsr");
sahilmgandhi 18:6a4db94011d3 74 return(__regAPSR);
sahilmgandhi 18:6a4db94011d3 75 }
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77
sahilmgandhi 18:6a4db94011d3 78 /** \brief Get CPSR Register
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 This function returns the content of the CPSR Register.
sahilmgandhi 18:6a4db94011d3 81
sahilmgandhi 18:6a4db94011d3 82 \return CPSR Register value
sahilmgandhi 18:6a4db94011d3 83 */
sahilmgandhi 18:6a4db94011d3 84 __STATIC_INLINE uint32_t __get_CPSR(void)
sahilmgandhi 18:6a4db94011d3 85 {
sahilmgandhi 18:6a4db94011d3 86 register uint32_t __regCPSR __ASM("cpsr");
sahilmgandhi 18:6a4db94011d3 87 return(__regCPSR);
sahilmgandhi 18:6a4db94011d3 88 }
sahilmgandhi 18:6a4db94011d3 89
sahilmgandhi 18:6a4db94011d3 90 /** \brief Set Stack Pointer
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92 This function assigns the given value to the current stack pointer.
sahilmgandhi 18:6a4db94011d3 93
sahilmgandhi 18:6a4db94011d3 94 \param [in] topOfStack Stack Pointer value to set
sahilmgandhi 18:6a4db94011d3 95 */
sahilmgandhi 18:6a4db94011d3 96 register uint32_t __regSP __ASM("sp");
sahilmgandhi 18:6a4db94011d3 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
sahilmgandhi 18:6a4db94011d3 98 {
sahilmgandhi 18:6a4db94011d3 99 __regSP = topOfStack;
sahilmgandhi 18:6a4db94011d3 100 }
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102
sahilmgandhi 18:6a4db94011d3 103 /** \brief Get link register
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105 This function returns the value of the link register
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107 \return Value of link register
sahilmgandhi 18:6a4db94011d3 108 */
sahilmgandhi 18:6a4db94011d3 109 register uint32_t __reglr __ASM("lr");
sahilmgandhi 18:6a4db94011d3 110 __STATIC_INLINE uint32_t __get_LR(void)
sahilmgandhi 18:6a4db94011d3 111 {
sahilmgandhi 18:6a4db94011d3 112 return(__reglr);
sahilmgandhi 18:6a4db94011d3 113 }
sahilmgandhi 18:6a4db94011d3 114
sahilmgandhi 18:6a4db94011d3 115 /** \brief Set link register
sahilmgandhi 18:6a4db94011d3 116
sahilmgandhi 18:6a4db94011d3 117 This function sets the value of the link register
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 \param [in] lr LR value to set
sahilmgandhi 18:6a4db94011d3 120 */
sahilmgandhi 18:6a4db94011d3 121 __STATIC_INLINE void __set_LR(uint32_t lr)
sahilmgandhi 18:6a4db94011d3 122 {
sahilmgandhi 18:6a4db94011d3 123 __reglr = lr;
sahilmgandhi 18:6a4db94011d3 124 }
sahilmgandhi 18:6a4db94011d3 125
sahilmgandhi 18:6a4db94011d3 126 /** \brief Set Process Stack Pointer
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
sahilmgandhi 18:6a4db94011d3 129
sahilmgandhi 18:6a4db94011d3 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
sahilmgandhi 18:6a4db94011d3 131 */
sahilmgandhi 18:6a4db94011d3 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
sahilmgandhi 18:6a4db94011d3 133 {
sahilmgandhi 18:6a4db94011d3 134 ARM
sahilmgandhi 18:6a4db94011d3 135 PRESERVE8
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
sahilmgandhi 18:6a4db94011d3 138 MRS R1, CPSR
sahilmgandhi 18:6a4db94011d3 139 CPS #MODE_SYS ;no effect in USR mode
sahilmgandhi 18:6a4db94011d3 140 MOV SP, R0
sahilmgandhi 18:6a4db94011d3 141 MSR CPSR_c, R1 ;no effect in USR mode
sahilmgandhi 18:6a4db94011d3 142 ISB
sahilmgandhi 18:6a4db94011d3 143 BX LR
sahilmgandhi 18:6a4db94011d3 144
sahilmgandhi 18:6a4db94011d3 145 }
sahilmgandhi 18:6a4db94011d3 146
sahilmgandhi 18:6a4db94011d3 147 /** \brief Set User Mode
sahilmgandhi 18:6a4db94011d3 148
sahilmgandhi 18:6a4db94011d3 149 This function changes the processor state to User Mode
sahilmgandhi 18:6a4db94011d3 150 */
sahilmgandhi 18:6a4db94011d3 151 __STATIC_ASM void __set_CPS_USR(void)
sahilmgandhi 18:6a4db94011d3 152 {
sahilmgandhi 18:6a4db94011d3 153 ARM
sahilmgandhi 18:6a4db94011d3 154
sahilmgandhi 18:6a4db94011d3 155 CPS #MODE_USR
sahilmgandhi 18:6a4db94011d3 156 BX LR
sahilmgandhi 18:6a4db94011d3 157 }
sahilmgandhi 18:6a4db94011d3 158
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 /** \brief Enable FIQ
sahilmgandhi 18:6a4db94011d3 161
sahilmgandhi 18:6a4db94011d3 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
sahilmgandhi 18:6a4db94011d3 163 Can only be executed in Privileged modes.
sahilmgandhi 18:6a4db94011d3 164 */
sahilmgandhi 18:6a4db94011d3 165 #define __enable_fault_irq __enable_fiq
sahilmgandhi 18:6a4db94011d3 166
sahilmgandhi 18:6a4db94011d3 167
sahilmgandhi 18:6a4db94011d3 168 /** \brief Disable FIQ
sahilmgandhi 18:6a4db94011d3 169
sahilmgandhi 18:6a4db94011d3 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
sahilmgandhi 18:6a4db94011d3 171 Can only be executed in Privileged modes.
sahilmgandhi 18:6a4db94011d3 172 */
sahilmgandhi 18:6a4db94011d3 173 #define __disable_fault_irq __disable_fiq
sahilmgandhi 18:6a4db94011d3 174
sahilmgandhi 18:6a4db94011d3 175
sahilmgandhi 18:6a4db94011d3 176 /** \brief Get FPSCR
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178 This function returns the current value of the Floating Point Status/Control register.
sahilmgandhi 18:6a4db94011d3 179
sahilmgandhi 18:6a4db94011d3 180 \return Floating Point Status/Control register value
sahilmgandhi 18:6a4db94011d3 181 */
sahilmgandhi 18:6a4db94011d3 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
sahilmgandhi 18:6a4db94011d3 183 {
sahilmgandhi 18:6a4db94011d3 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
sahilmgandhi 18:6a4db94011d3 185 register uint32_t __regfpscr __ASM("fpscr");
sahilmgandhi 18:6a4db94011d3 186 return(__regfpscr);
sahilmgandhi 18:6a4db94011d3 187 #else
sahilmgandhi 18:6a4db94011d3 188 return(0);
sahilmgandhi 18:6a4db94011d3 189 #endif
sahilmgandhi 18:6a4db94011d3 190 }
sahilmgandhi 18:6a4db94011d3 191
sahilmgandhi 18:6a4db94011d3 192
sahilmgandhi 18:6a4db94011d3 193 /** \brief Set FPSCR
sahilmgandhi 18:6a4db94011d3 194
sahilmgandhi 18:6a4db94011d3 195 This function assigns the given value to the Floating Point Status/Control register.
sahilmgandhi 18:6a4db94011d3 196
sahilmgandhi 18:6a4db94011d3 197 \param [in] fpscr Floating Point Status/Control value to set
sahilmgandhi 18:6a4db94011d3 198 */
sahilmgandhi 18:6a4db94011d3 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
sahilmgandhi 18:6a4db94011d3 200 {
sahilmgandhi 18:6a4db94011d3 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
sahilmgandhi 18:6a4db94011d3 202 register uint32_t __regfpscr __ASM("fpscr");
sahilmgandhi 18:6a4db94011d3 203 __regfpscr = (fpscr);
sahilmgandhi 18:6a4db94011d3 204 #endif
sahilmgandhi 18:6a4db94011d3 205 }
sahilmgandhi 18:6a4db94011d3 206
sahilmgandhi 18:6a4db94011d3 207 /** \brief Get FPEXC
sahilmgandhi 18:6a4db94011d3 208
sahilmgandhi 18:6a4db94011d3 209 This function returns the current value of the Floating Point Exception Control register.
sahilmgandhi 18:6a4db94011d3 210
sahilmgandhi 18:6a4db94011d3 211 \return Floating Point Exception Control register value
sahilmgandhi 18:6a4db94011d3 212 */
sahilmgandhi 18:6a4db94011d3 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
sahilmgandhi 18:6a4db94011d3 214 {
sahilmgandhi 18:6a4db94011d3 215 #if (__FPU_PRESENT == 1)
sahilmgandhi 18:6a4db94011d3 216 register uint32_t __regfpexc __ASM("fpexc");
sahilmgandhi 18:6a4db94011d3 217 return(__regfpexc);
sahilmgandhi 18:6a4db94011d3 218 #else
sahilmgandhi 18:6a4db94011d3 219 return(0);
sahilmgandhi 18:6a4db94011d3 220 #endif
sahilmgandhi 18:6a4db94011d3 221 }
sahilmgandhi 18:6a4db94011d3 222
sahilmgandhi 18:6a4db94011d3 223
sahilmgandhi 18:6a4db94011d3 224 /** \brief Set FPEXC
sahilmgandhi 18:6a4db94011d3 225
sahilmgandhi 18:6a4db94011d3 226 This function assigns the given value to the Floating Point Exception Control register.
sahilmgandhi 18:6a4db94011d3 227
sahilmgandhi 18:6a4db94011d3 228 \param [in] fpscr Floating Point Exception Control value to set
sahilmgandhi 18:6a4db94011d3 229 */
sahilmgandhi 18:6a4db94011d3 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
sahilmgandhi 18:6a4db94011d3 231 {
sahilmgandhi 18:6a4db94011d3 232 #if (__FPU_PRESENT == 1)
sahilmgandhi 18:6a4db94011d3 233 register uint32_t __regfpexc __ASM("fpexc");
sahilmgandhi 18:6a4db94011d3 234 __regfpexc = (fpexc);
sahilmgandhi 18:6a4db94011d3 235 #endif
sahilmgandhi 18:6a4db94011d3 236 }
sahilmgandhi 18:6a4db94011d3 237
sahilmgandhi 18:6a4db94011d3 238 /** \brief Get CPACR
sahilmgandhi 18:6a4db94011d3 239
sahilmgandhi 18:6a4db94011d3 240 This function returns the current value of the Coprocessor Access Control register.
sahilmgandhi 18:6a4db94011d3 241
sahilmgandhi 18:6a4db94011d3 242 \return Coprocessor Access Control register value
sahilmgandhi 18:6a4db94011d3 243 */
sahilmgandhi 18:6a4db94011d3 244 __STATIC_INLINE uint32_t __get_CPACR(void)
sahilmgandhi 18:6a4db94011d3 245 {
sahilmgandhi 18:6a4db94011d3 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
sahilmgandhi 18:6a4db94011d3 247 return __regCPACR;
sahilmgandhi 18:6a4db94011d3 248 }
sahilmgandhi 18:6a4db94011d3 249
sahilmgandhi 18:6a4db94011d3 250 /** \brief Set CPACR
sahilmgandhi 18:6a4db94011d3 251
sahilmgandhi 18:6a4db94011d3 252 This function assigns the given value to the Coprocessor Access Control register.
sahilmgandhi 18:6a4db94011d3 253
sahilmgandhi 18:6a4db94011d3 254 \param [in] cpacr Coprocessor Acccess Control value to set
sahilmgandhi 18:6a4db94011d3 255 */
sahilmgandhi 18:6a4db94011d3 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
sahilmgandhi 18:6a4db94011d3 257 {
sahilmgandhi 18:6a4db94011d3 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
sahilmgandhi 18:6a4db94011d3 259 __regCPACR = cpacr;
sahilmgandhi 18:6a4db94011d3 260 __ISB();
sahilmgandhi 18:6a4db94011d3 261 }
sahilmgandhi 18:6a4db94011d3 262
sahilmgandhi 18:6a4db94011d3 263 /** \brief Get CBAR
sahilmgandhi 18:6a4db94011d3 264
sahilmgandhi 18:6a4db94011d3 265 This function returns the value of the Configuration Base Address register.
sahilmgandhi 18:6a4db94011d3 266
sahilmgandhi 18:6a4db94011d3 267 \return Configuration Base Address register value
sahilmgandhi 18:6a4db94011d3 268 */
sahilmgandhi 18:6a4db94011d3 269 __STATIC_INLINE uint32_t __get_CBAR() {
sahilmgandhi 18:6a4db94011d3 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
sahilmgandhi 18:6a4db94011d3 271 return(__regCBAR);
sahilmgandhi 18:6a4db94011d3 272 }
sahilmgandhi 18:6a4db94011d3 273
sahilmgandhi 18:6a4db94011d3 274 /** \brief Get TTBR0
sahilmgandhi 18:6a4db94011d3 275
sahilmgandhi 18:6a4db94011d3 276 This function returns the value of the Translation Table Base Register 0.
sahilmgandhi 18:6a4db94011d3 277
sahilmgandhi 18:6a4db94011d3 278 \return Translation Table Base Register 0 value
sahilmgandhi 18:6a4db94011d3 279 */
sahilmgandhi 18:6a4db94011d3 280 __STATIC_INLINE uint32_t __get_TTBR0() {
sahilmgandhi 18:6a4db94011d3 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
sahilmgandhi 18:6a4db94011d3 282 return(__regTTBR0);
sahilmgandhi 18:6a4db94011d3 283 }
sahilmgandhi 18:6a4db94011d3 284
sahilmgandhi 18:6a4db94011d3 285 /** \brief Set TTBR0
sahilmgandhi 18:6a4db94011d3 286
sahilmgandhi 18:6a4db94011d3 287 This function assigns the given value to the Translation Table Base Register 0.
sahilmgandhi 18:6a4db94011d3 288
sahilmgandhi 18:6a4db94011d3 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
sahilmgandhi 18:6a4db94011d3 290 */
sahilmgandhi 18:6a4db94011d3 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
sahilmgandhi 18:6a4db94011d3 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
sahilmgandhi 18:6a4db94011d3 293 __regTTBR0 = ttbr0;
sahilmgandhi 18:6a4db94011d3 294 __ISB();
sahilmgandhi 18:6a4db94011d3 295 }
sahilmgandhi 18:6a4db94011d3 296
sahilmgandhi 18:6a4db94011d3 297 /** \brief Get DACR
sahilmgandhi 18:6a4db94011d3 298
sahilmgandhi 18:6a4db94011d3 299 This function returns the value of the Domain Access Control Register.
sahilmgandhi 18:6a4db94011d3 300
sahilmgandhi 18:6a4db94011d3 301 \return Domain Access Control Register value
sahilmgandhi 18:6a4db94011d3 302 */
sahilmgandhi 18:6a4db94011d3 303 __STATIC_INLINE uint32_t __get_DACR() {
sahilmgandhi 18:6a4db94011d3 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
sahilmgandhi 18:6a4db94011d3 305 return(__regDACR);
sahilmgandhi 18:6a4db94011d3 306 }
sahilmgandhi 18:6a4db94011d3 307
sahilmgandhi 18:6a4db94011d3 308 /** \brief Set DACR
sahilmgandhi 18:6a4db94011d3 309
sahilmgandhi 18:6a4db94011d3 310 This function assigns the given value to the Domain Access Control Register.
sahilmgandhi 18:6a4db94011d3 311
sahilmgandhi 18:6a4db94011d3 312 \param [in] dacr Domain Access Control Register value to set
sahilmgandhi 18:6a4db94011d3 313 */
sahilmgandhi 18:6a4db94011d3 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
sahilmgandhi 18:6a4db94011d3 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
sahilmgandhi 18:6a4db94011d3 316 __regDACR = dacr;
sahilmgandhi 18:6a4db94011d3 317 __ISB();
sahilmgandhi 18:6a4db94011d3 318 }
sahilmgandhi 18:6a4db94011d3 319
sahilmgandhi 18:6a4db94011d3 320 /******************************** Cache and BTAC enable ****************************************************/
sahilmgandhi 18:6a4db94011d3 321
sahilmgandhi 18:6a4db94011d3 322 /** \brief Set SCTLR
sahilmgandhi 18:6a4db94011d3 323
sahilmgandhi 18:6a4db94011d3 324 This function assigns the given value to the System Control Register.
sahilmgandhi 18:6a4db94011d3 325
sahilmgandhi 18:6a4db94011d3 326 \param [in] sctlr System Control Register value to set
sahilmgandhi 18:6a4db94011d3 327 */
sahilmgandhi 18:6a4db94011d3 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
sahilmgandhi 18:6a4db94011d3 329 {
sahilmgandhi 18:6a4db94011d3 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
sahilmgandhi 18:6a4db94011d3 331 __regSCTLR = sctlr;
sahilmgandhi 18:6a4db94011d3 332 }
sahilmgandhi 18:6a4db94011d3 333
sahilmgandhi 18:6a4db94011d3 334 /** \brief Get SCTLR
sahilmgandhi 18:6a4db94011d3 335
sahilmgandhi 18:6a4db94011d3 336 This function returns the value of the System Control Register.
sahilmgandhi 18:6a4db94011d3 337
sahilmgandhi 18:6a4db94011d3 338 \return System Control Register value
sahilmgandhi 18:6a4db94011d3 339 */
sahilmgandhi 18:6a4db94011d3 340 __STATIC_INLINE uint32_t __get_SCTLR() {
sahilmgandhi 18:6a4db94011d3 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
sahilmgandhi 18:6a4db94011d3 342 return(__regSCTLR);
sahilmgandhi 18:6a4db94011d3 343 }
sahilmgandhi 18:6a4db94011d3 344
sahilmgandhi 18:6a4db94011d3 345 /** \brief Enable Caches
sahilmgandhi 18:6a4db94011d3 346
sahilmgandhi 18:6a4db94011d3 347 Enable Caches
sahilmgandhi 18:6a4db94011d3 348 */
sahilmgandhi 18:6a4db94011d3 349 __STATIC_INLINE void __enable_caches(void) {
sahilmgandhi 18:6a4db94011d3 350 // Set I bit 12 to enable I Cache
sahilmgandhi 18:6a4db94011d3 351 // Set C bit 2 to enable D Cache
sahilmgandhi 18:6a4db94011d3 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
sahilmgandhi 18:6a4db94011d3 353 }
sahilmgandhi 18:6a4db94011d3 354
sahilmgandhi 18:6a4db94011d3 355 /** \brief Disable Caches
sahilmgandhi 18:6a4db94011d3 356
sahilmgandhi 18:6a4db94011d3 357 Disable Caches
sahilmgandhi 18:6a4db94011d3 358 */
sahilmgandhi 18:6a4db94011d3 359 __STATIC_INLINE void __disable_caches(void) {
sahilmgandhi 18:6a4db94011d3 360 // Clear I bit 12 to disable I Cache
sahilmgandhi 18:6a4db94011d3 361 // Clear C bit 2 to disable D Cache
sahilmgandhi 18:6a4db94011d3 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
sahilmgandhi 18:6a4db94011d3 363 __ISB();
sahilmgandhi 18:6a4db94011d3 364 }
sahilmgandhi 18:6a4db94011d3 365
sahilmgandhi 18:6a4db94011d3 366 /** \brief Enable BTAC
sahilmgandhi 18:6a4db94011d3 367
sahilmgandhi 18:6a4db94011d3 368 Enable BTAC
sahilmgandhi 18:6a4db94011d3 369 */
sahilmgandhi 18:6a4db94011d3 370 __STATIC_INLINE void __enable_btac(void) {
sahilmgandhi 18:6a4db94011d3 371 // Set Z bit 11 to enable branch prediction
sahilmgandhi 18:6a4db94011d3 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
sahilmgandhi 18:6a4db94011d3 373 __ISB();
sahilmgandhi 18:6a4db94011d3 374 }
sahilmgandhi 18:6a4db94011d3 375
sahilmgandhi 18:6a4db94011d3 376 /** \brief Disable BTAC
sahilmgandhi 18:6a4db94011d3 377
sahilmgandhi 18:6a4db94011d3 378 Disable BTAC
sahilmgandhi 18:6a4db94011d3 379 */
sahilmgandhi 18:6a4db94011d3 380 __STATIC_INLINE void __disable_btac(void) {
sahilmgandhi 18:6a4db94011d3 381 // Clear Z bit 11 to disable branch prediction
sahilmgandhi 18:6a4db94011d3 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
sahilmgandhi 18:6a4db94011d3 383 }
sahilmgandhi 18:6a4db94011d3 384
sahilmgandhi 18:6a4db94011d3 385
sahilmgandhi 18:6a4db94011d3 386 /** \brief Enable MMU
sahilmgandhi 18:6a4db94011d3 387
sahilmgandhi 18:6a4db94011d3 388 Enable MMU
sahilmgandhi 18:6a4db94011d3 389 */
sahilmgandhi 18:6a4db94011d3 390 __STATIC_INLINE void __enable_mmu(void) {
sahilmgandhi 18:6a4db94011d3 391 // Set M bit 0 to enable the MMU
sahilmgandhi 18:6a4db94011d3 392 // Set AFE bit to enable simplified access permissions model
sahilmgandhi 18:6a4db94011d3 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
sahilmgandhi 18:6a4db94011d3 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
sahilmgandhi 18:6a4db94011d3 395 __ISB();
sahilmgandhi 18:6a4db94011d3 396 }
sahilmgandhi 18:6a4db94011d3 397
sahilmgandhi 18:6a4db94011d3 398 /** \brief Disable MMU
sahilmgandhi 18:6a4db94011d3 399
sahilmgandhi 18:6a4db94011d3 400 Disable MMU
sahilmgandhi 18:6a4db94011d3 401 */
sahilmgandhi 18:6a4db94011d3 402 __STATIC_INLINE void __disable_mmu(void) {
sahilmgandhi 18:6a4db94011d3 403 // Clear M bit 0 to disable the MMU
sahilmgandhi 18:6a4db94011d3 404 __set_SCTLR( __get_SCTLR() & ~1);
sahilmgandhi 18:6a4db94011d3 405 __ISB();
sahilmgandhi 18:6a4db94011d3 406 }
sahilmgandhi 18:6a4db94011d3 407
sahilmgandhi 18:6a4db94011d3 408 /******************************** TLB maintenance operations ************************************************/
sahilmgandhi 18:6a4db94011d3 409 /** \brief Invalidate the whole tlb
sahilmgandhi 18:6a4db94011d3 410
sahilmgandhi 18:6a4db94011d3 411 TLBIALL. Invalidate the whole tlb
sahilmgandhi 18:6a4db94011d3 412 */
sahilmgandhi 18:6a4db94011d3 413
sahilmgandhi 18:6a4db94011d3 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
sahilmgandhi 18:6a4db94011d3 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
sahilmgandhi 18:6a4db94011d3 416 __TLBIALL = 0;
sahilmgandhi 18:6a4db94011d3 417 __DSB();
sahilmgandhi 18:6a4db94011d3 418 __ISB();
sahilmgandhi 18:6a4db94011d3 419 }
sahilmgandhi 18:6a4db94011d3 420
sahilmgandhi 18:6a4db94011d3 421 /******************************** BTB maintenance operations ************************************************/
sahilmgandhi 18:6a4db94011d3 422 /** \brief Invalidate entire branch predictor array
sahilmgandhi 18:6a4db94011d3 423
sahilmgandhi 18:6a4db94011d3 424 BPIALL. Branch Predictor Invalidate All.
sahilmgandhi 18:6a4db94011d3 425 */
sahilmgandhi 18:6a4db94011d3 426
sahilmgandhi 18:6a4db94011d3 427 __STATIC_INLINE void __v7_inv_btac(void) {
sahilmgandhi 18:6a4db94011d3 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
sahilmgandhi 18:6a4db94011d3 429 __BPIALL = 0;
sahilmgandhi 18:6a4db94011d3 430 __DSB(); //ensure completion of the invalidation
sahilmgandhi 18:6a4db94011d3 431 __ISB(); //ensure instruction fetch path sees new state
sahilmgandhi 18:6a4db94011d3 432 }
sahilmgandhi 18:6a4db94011d3 433
sahilmgandhi 18:6a4db94011d3 434
sahilmgandhi 18:6a4db94011d3 435 /******************************** L1 cache operations ******************************************************/
sahilmgandhi 18:6a4db94011d3 436
sahilmgandhi 18:6a4db94011d3 437 /** \brief Invalidate the whole I$
sahilmgandhi 18:6a4db94011d3 438
sahilmgandhi 18:6a4db94011d3 439 ICIALLU. Instruction Cache Invalidate All to PoU
sahilmgandhi 18:6a4db94011d3 440 */
sahilmgandhi 18:6a4db94011d3 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
sahilmgandhi 18:6a4db94011d3 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
sahilmgandhi 18:6a4db94011d3 443 __ICIALLU = 0;
sahilmgandhi 18:6a4db94011d3 444 __DSB(); //ensure completion of the invalidation
sahilmgandhi 18:6a4db94011d3 445 __ISB(); //ensure instruction fetch path sees new I cache state
sahilmgandhi 18:6a4db94011d3 446 }
sahilmgandhi 18:6a4db94011d3 447
sahilmgandhi 18:6a4db94011d3 448 /** \brief Clean D$ by MVA
sahilmgandhi 18:6a4db94011d3 449
sahilmgandhi 18:6a4db94011d3 450 DCCMVAC. Data cache clean by MVA to PoC
sahilmgandhi 18:6a4db94011d3 451 */
sahilmgandhi 18:6a4db94011d3 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
sahilmgandhi 18:6a4db94011d3 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
sahilmgandhi 18:6a4db94011d3 454 __DCCMVAC = (uint32_t)va;
sahilmgandhi 18:6a4db94011d3 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
sahilmgandhi 18:6a4db94011d3 456 }
sahilmgandhi 18:6a4db94011d3 457
sahilmgandhi 18:6a4db94011d3 458 /** \brief Invalidate D$ by MVA
sahilmgandhi 18:6a4db94011d3 459
sahilmgandhi 18:6a4db94011d3 460 DCIMVAC. Data cache invalidate by MVA to PoC
sahilmgandhi 18:6a4db94011d3 461 */
sahilmgandhi 18:6a4db94011d3 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
sahilmgandhi 18:6a4db94011d3 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
sahilmgandhi 18:6a4db94011d3 464 __DCIMVAC = (uint32_t)va;
sahilmgandhi 18:6a4db94011d3 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
sahilmgandhi 18:6a4db94011d3 466 }
sahilmgandhi 18:6a4db94011d3 467
sahilmgandhi 18:6a4db94011d3 468 /** \brief Clean and Invalidate D$ by MVA
sahilmgandhi 18:6a4db94011d3 469
sahilmgandhi 18:6a4db94011d3 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
sahilmgandhi 18:6a4db94011d3 471 */
sahilmgandhi 18:6a4db94011d3 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
sahilmgandhi 18:6a4db94011d3 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
sahilmgandhi 18:6a4db94011d3 474 __DCCIMVAC = (uint32_t)va;
sahilmgandhi 18:6a4db94011d3 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
sahilmgandhi 18:6a4db94011d3 476 }
sahilmgandhi 18:6a4db94011d3 477
sahilmgandhi 18:6a4db94011d3 478 /** \brief Clean and Invalidate the entire data or unified cache
sahilmgandhi 18:6a4db94011d3 479
sahilmgandhi 18:6a4db94011d3 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
sahilmgandhi 18:6a4db94011d3 481 */
sahilmgandhi 18:6a4db94011d3 482 #pragma push
sahilmgandhi 18:6a4db94011d3 483 #pragma arm
sahilmgandhi 18:6a4db94011d3 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
sahilmgandhi 18:6a4db94011d3 485 ARM
sahilmgandhi 18:6a4db94011d3 486
sahilmgandhi 18:6a4db94011d3 487 PUSH {R4-R11}
sahilmgandhi 18:6a4db94011d3 488
sahilmgandhi 18:6a4db94011d3 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
sahilmgandhi 18:6a4db94011d3 490 ANDS R3, R6, #0x07000000 // Extract coherency level
sahilmgandhi 18:6a4db94011d3 491 MOV R3, R3, LSR #23 // Total cache levels << 1
sahilmgandhi 18:6a4db94011d3 492 BEQ Finished // If 0, no need to clean
sahilmgandhi 18:6a4db94011d3 493
sahilmgandhi 18:6a4db94011d3 494 MOV R10, #0 // R10 holds current cache level << 1
sahilmgandhi 18:6a4db94011d3 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
sahilmgandhi 18:6a4db94011d3 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
sahilmgandhi 18:6a4db94011d3 497 AND R1, R1, #7 // Isolate those lower 3 bits
sahilmgandhi 18:6a4db94011d3 498 CMP R1, #2
sahilmgandhi 18:6a4db94011d3 499 BLT Skip // No cache or only instruction cache at this level
sahilmgandhi 18:6a4db94011d3 500
sahilmgandhi 18:6a4db94011d3 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
sahilmgandhi 18:6a4db94011d3 502 ISB // ISB to sync the change to the CacheSizeID reg
sahilmgandhi 18:6a4db94011d3 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
sahilmgandhi 18:6a4db94011d3 504 AND R2, R1, #7 // Extract the line length field
sahilmgandhi 18:6a4db94011d3 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
sahilmgandhi 18:6a4db94011d3 506 LDR R4, =0x3FF
sahilmgandhi 18:6a4db94011d3 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
sahilmgandhi 18:6a4db94011d3 508 CLZ R5, R4 // R5 is the bit position of the way size increment
sahilmgandhi 18:6a4db94011d3 509 LDR R7, =0x7FFF
sahilmgandhi 18:6a4db94011d3 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
sahilmgandhi 18:6a4db94011d3 511
sahilmgandhi 18:6a4db94011d3 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
sahilmgandhi 18:6a4db94011d3 513
sahilmgandhi 18:6a4db94011d3 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
sahilmgandhi 18:6a4db94011d3 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
sahilmgandhi 18:6a4db94011d3 516 CMP R0, #0
sahilmgandhi 18:6a4db94011d3 517 BNE Dccsw
sahilmgandhi 18:6a4db94011d3 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
sahilmgandhi 18:6a4db94011d3 519 B cont
sahilmgandhi 18:6a4db94011d3 520 Dccsw CMP R0, #1
sahilmgandhi 18:6a4db94011d3 521 BNE Dccisw
sahilmgandhi 18:6a4db94011d3 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
sahilmgandhi 18:6a4db94011d3 523 B cont
sahilmgandhi 18:6a4db94011d3 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
sahilmgandhi 18:6a4db94011d3 525 cont SUBS R9, R9, #1 // Decrement the Way number
sahilmgandhi 18:6a4db94011d3 526 BGE Loop3
sahilmgandhi 18:6a4db94011d3 527 SUBS R7, R7, #1 // Decrement the Set number
sahilmgandhi 18:6a4db94011d3 528 BGE Loop2
sahilmgandhi 18:6a4db94011d3 529 Skip ADD R10, R10, #2 // Increment the cache number
sahilmgandhi 18:6a4db94011d3 530 CMP R3, R10
sahilmgandhi 18:6a4db94011d3 531 BGT Loop1
sahilmgandhi 18:6a4db94011d3 532
sahilmgandhi 18:6a4db94011d3 533 Finished
sahilmgandhi 18:6a4db94011d3 534 DSB
sahilmgandhi 18:6a4db94011d3 535 POP {R4-R11}
sahilmgandhi 18:6a4db94011d3 536 BX lr
sahilmgandhi 18:6a4db94011d3 537
sahilmgandhi 18:6a4db94011d3 538 }
sahilmgandhi 18:6a4db94011d3 539 #pragma pop
sahilmgandhi 18:6a4db94011d3 540
sahilmgandhi 18:6a4db94011d3 541
sahilmgandhi 18:6a4db94011d3 542 /** \brief Invalidate the whole D$
sahilmgandhi 18:6a4db94011d3 543
sahilmgandhi 18:6a4db94011d3 544 DCISW. Invalidate by Set/Way
sahilmgandhi 18:6a4db94011d3 545 */
sahilmgandhi 18:6a4db94011d3 546
sahilmgandhi 18:6a4db94011d3 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
sahilmgandhi 18:6a4db94011d3 548 __v7_all_cache(0);
sahilmgandhi 18:6a4db94011d3 549 }
sahilmgandhi 18:6a4db94011d3 550
sahilmgandhi 18:6a4db94011d3 551 /** \brief Clean the whole D$
sahilmgandhi 18:6a4db94011d3 552
sahilmgandhi 18:6a4db94011d3 553 DCCSW. Clean by Set/Way
sahilmgandhi 18:6a4db94011d3 554 */
sahilmgandhi 18:6a4db94011d3 555
sahilmgandhi 18:6a4db94011d3 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
sahilmgandhi 18:6a4db94011d3 557 __v7_all_cache(1);
sahilmgandhi 18:6a4db94011d3 558 }
sahilmgandhi 18:6a4db94011d3 559
sahilmgandhi 18:6a4db94011d3 560 /** \brief Clean and invalidate the whole D$
sahilmgandhi 18:6a4db94011d3 561
sahilmgandhi 18:6a4db94011d3 562 DCCISW. Clean and Invalidate by Set/Way
sahilmgandhi 18:6a4db94011d3 563 */
sahilmgandhi 18:6a4db94011d3 564
sahilmgandhi 18:6a4db94011d3 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
sahilmgandhi 18:6a4db94011d3 566 __v7_all_cache(2);
sahilmgandhi 18:6a4db94011d3 567 }
sahilmgandhi 18:6a4db94011d3 568
sahilmgandhi 18:6a4db94011d3 569 #include "core_ca_mmu.h"
sahilmgandhi 18:6a4db94011d3 570
sahilmgandhi 18:6a4db94011d3 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
sahilmgandhi 18:6a4db94011d3 572
sahilmgandhi 18:6a4db94011d3 573 #define __inline inline
sahilmgandhi 18:6a4db94011d3 574
sahilmgandhi 18:6a4db94011d3 575 inline static uint32_t __disable_irq_iar() {
sahilmgandhi 18:6a4db94011d3 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
sahilmgandhi 18:6a4db94011d3 577 __disable_irq();
sahilmgandhi 18:6a4db94011d3 578 return irq_dis;
sahilmgandhi 18:6a4db94011d3 579 }
sahilmgandhi 18:6a4db94011d3 580
sahilmgandhi 18:6a4db94011d3 581 #define MODE_USR 0x10
sahilmgandhi 18:6a4db94011d3 582 #define MODE_FIQ 0x11
sahilmgandhi 18:6a4db94011d3 583 #define MODE_IRQ 0x12
sahilmgandhi 18:6a4db94011d3 584 #define MODE_SVC 0x13
sahilmgandhi 18:6a4db94011d3 585 #define MODE_MON 0x16
sahilmgandhi 18:6a4db94011d3 586 #define MODE_ABT 0x17
sahilmgandhi 18:6a4db94011d3 587 #define MODE_HYP 0x1A
sahilmgandhi 18:6a4db94011d3 588 #define MODE_UND 0x1B
sahilmgandhi 18:6a4db94011d3 589 #define MODE_SYS 0x1F
sahilmgandhi 18:6a4db94011d3 590
sahilmgandhi 18:6a4db94011d3 591 /** \brief Set Process Stack Pointer
sahilmgandhi 18:6a4db94011d3 592
sahilmgandhi 18:6a4db94011d3 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
sahilmgandhi 18:6a4db94011d3 594
sahilmgandhi 18:6a4db94011d3 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
sahilmgandhi 18:6a4db94011d3 596 */
sahilmgandhi 18:6a4db94011d3 597 // from rt_CMSIS.c
sahilmgandhi 18:6a4db94011d3 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
sahilmgandhi 18:6a4db94011d3 599 __asm(
sahilmgandhi 18:6a4db94011d3 600 " ARM\n"
sahilmgandhi 18:6a4db94011d3 601 // " PRESERVE8\n"
sahilmgandhi 18:6a4db94011d3 602
sahilmgandhi 18:6a4db94011d3 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
sahilmgandhi 18:6a4db94011d3 604 " MRS R1, CPSR \n"
sahilmgandhi 18:6a4db94011d3 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
sahilmgandhi 18:6a4db94011d3 606 " MOV SP, R0 \n"
sahilmgandhi 18:6a4db94011d3 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
sahilmgandhi 18:6a4db94011d3 608 " ISB \n"
sahilmgandhi 18:6a4db94011d3 609 " BX LR \n");
sahilmgandhi 18:6a4db94011d3 610 }
sahilmgandhi 18:6a4db94011d3 611
sahilmgandhi 18:6a4db94011d3 612 /** \brief Set User Mode
sahilmgandhi 18:6a4db94011d3 613
sahilmgandhi 18:6a4db94011d3 614 This function changes the processor state to User Mode
sahilmgandhi 18:6a4db94011d3 615 */
sahilmgandhi 18:6a4db94011d3 616 // from rt_CMSIS.c
sahilmgandhi 18:6a4db94011d3 617 __arm static inline void __set_CPS_USR(void) {
sahilmgandhi 18:6a4db94011d3 618 __asm(
sahilmgandhi 18:6a4db94011d3 619 " ARM \n"
sahilmgandhi 18:6a4db94011d3 620
sahilmgandhi 18:6a4db94011d3 621 " CPS #0x10 \n" // MODE_USR
sahilmgandhi 18:6a4db94011d3 622 " BX LR\n");
sahilmgandhi 18:6a4db94011d3 623 }
sahilmgandhi 18:6a4db94011d3 624
sahilmgandhi 18:6a4db94011d3 625 /** \brief Set TTBR0
sahilmgandhi 18:6a4db94011d3 626
sahilmgandhi 18:6a4db94011d3 627 This function assigns the given value to the Translation Table Base Register 0.
sahilmgandhi 18:6a4db94011d3 628
sahilmgandhi 18:6a4db94011d3 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
sahilmgandhi 18:6a4db94011d3 630 */
sahilmgandhi 18:6a4db94011d3 631 // from mmu_Renesas_RZ_A1.c
sahilmgandhi 18:6a4db94011d3 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
sahilmgandhi 18:6a4db94011d3 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
sahilmgandhi 18:6a4db94011d3 634 __ISB();
sahilmgandhi 18:6a4db94011d3 635 }
sahilmgandhi 18:6a4db94011d3 636
sahilmgandhi 18:6a4db94011d3 637 /** \brief Set DACR
sahilmgandhi 18:6a4db94011d3 638
sahilmgandhi 18:6a4db94011d3 639 This function assigns the given value to the Domain Access Control Register.
sahilmgandhi 18:6a4db94011d3 640
sahilmgandhi 18:6a4db94011d3 641 \param [in] dacr Domain Access Control Register value to set
sahilmgandhi 18:6a4db94011d3 642 */
sahilmgandhi 18:6a4db94011d3 643 // from mmu_Renesas_RZ_A1.c
sahilmgandhi 18:6a4db94011d3 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
sahilmgandhi 18:6a4db94011d3 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
sahilmgandhi 18:6a4db94011d3 646 __ISB();
sahilmgandhi 18:6a4db94011d3 647 }
sahilmgandhi 18:6a4db94011d3 648
sahilmgandhi 18:6a4db94011d3 649
sahilmgandhi 18:6a4db94011d3 650 /******************************** Cache and BTAC enable ****************************************************/
sahilmgandhi 18:6a4db94011d3 651 /** \brief Set SCTLR
sahilmgandhi 18:6a4db94011d3 652
sahilmgandhi 18:6a4db94011d3 653 This function assigns the given value to the System Control Register.
sahilmgandhi 18:6a4db94011d3 654
sahilmgandhi 18:6a4db94011d3 655 \param [in] sctlr System Control Register value to set
sahilmgandhi 18:6a4db94011d3 656 */
sahilmgandhi 18:6a4db94011d3 657 // from __enable_mmu()
sahilmgandhi 18:6a4db94011d3 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
sahilmgandhi 18:6a4db94011d3 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
sahilmgandhi 18:6a4db94011d3 660 }
sahilmgandhi 18:6a4db94011d3 661
sahilmgandhi 18:6a4db94011d3 662 /** \brief Get SCTLR
sahilmgandhi 18:6a4db94011d3 663
sahilmgandhi 18:6a4db94011d3 664 This function returns the value of the System Control Register.
sahilmgandhi 18:6a4db94011d3 665
sahilmgandhi 18:6a4db94011d3 666 \return System Control Register value
sahilmgandhi 18:6a4db94011d3 667 */
sahilmgandhi 18:6a4db94011d3 668 // from __enable_mmu()
sahilmgandhi 18:6a4db94011d3 669 __STATIC_INLINE uint32_t __get_SCTLR() {
sahilmgandhi 18:6a4db94011d3 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
sahilmgandhi 18:6a4db94011d3 671 return __regSCTLR;
sahilmgandhi 18:6a4db94011d3 672 }
sahilmgandhi 18:6a4db94011d3 673
sahilmgandhi 18:6a4db94011d3 674 /** \brief Enable Caches
sahilmgandhi 18:6a4db94011d3 675
sahilmgandhi 18:6a4db94011d3 676 Enable Caches
sahilmgandhi 18:6a4db94011d3 677 */
sahilmgandhi 18:6a4db94011d3 678 // from system_Renesas_RZ_A1.c
sahilmgandhi 18:6a4db94011d3 679 __STATIC_INLINE void __enable_caches(void) {
sahilmgandhi 18:6a4db94011d3 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
sahilmgandhi 18:6a4db94011d3 681 }
sahilmgandhi 18:6a4db94011d3 682
sahilmgandhi 18:6a4db94011d3 683 /** \brief Enable BTAC
sahilmgandhi 18:6a4db94011d3 684
sahilmgandhi 18:6a4db94011d3 685 Enable BTAC
sahilmgandhi 18:6a4db94011d3 686 */
sahilmgandhi 18:6a4db94011d3 687 // from system_Renesas_RZ_A1.c
sahilmgandhi 18:6a4db94011d3 688 __STATIC_INLINE void __enable_btac(void) {
sahilmgandhi 18:6a4db94011d3 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
sahilmgandhi 18:6a4db94011d3 690 __ISB();
sahilmgandhi 18:6a4db94011d3 691 }
sahilmgandhi 18:6a4db94011d3 692
sahilmgandhi 18:6a4db94011d3 693 /** \brief Enable MMU
sahilmgandhi 18:6a4db94011d3 694
sahilmgandhi 18:6a4db94011d3 695 Enable MMU
sahilmgandhi 18:6a4db94011d3 696 */
sahilmgandhi 18:6a4db94011d3 697 // from system_Renesas_RZ_A1.c
sahilmgandhi 18:6a4db94011d3 698 __STATIC_INLINE void __enable_mmu(void) {
sahilmgandhi 18:6a4db94011d3 699 // Set M bit 0 to enable the MMU
sahilmgandhi 18:6a4db94011d3 700 // Set AFE bit to enable simplified access permissions model
sahilmgandhi 18:6a4db94011d3 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
sahilmgandhi 18:6a4db94011d3 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
sahilmgandhi 18:6a4db94011d3 703 __ISB();
sahilmgandhi 18:6a4db94011d3 704 }
sahilmgandhi 18:6a4db94011d3 705
sahilmgandhi 18:6a4db94011d3 706 /******************************** TLB maintenance operations ************************************************/
sahilmgandhi 18:6a4db94011d3 707 /** \brief Invalidate the whole tlb
sahilmgandhi 18:6a4db94011d3 708
sahilmgandhi 18:6a4db94011d3 709 TLBIALL. Invalidate the whole tlb
sahilmgandhi 18:6a4db94011d3 710 */
sahilmgandhi 18:6a4db94011d3 711 // from system_Renesas_RZ_A1.c
sahilmgandhi 18:6a4db94011d3 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
sahilmgandhi 18:6a4db94011d3 713 uint32_t val = 0;
sahilmgandhi 18:6a4db94011d3 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
sahilmgandhi 18:6a4db94011d3 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
sahilmgandhi 18:6a4db94011d3 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
sahilmgandhi 18:6a4db94011d3 717 __DSB();
sahilmgandhi 18:6a4db94011d3 718 __ISB();
sahilmgandhi 18:6a4db94011d3 719 }
sahilmgandhi 18:6a4db94011d3 720
sahilmgandhi 18:6a4db94011d3 721 /******************************** BTB maintenance operations ************************************************/
sahilmgandhi 18:6a4db94011d3 722 /** \brief Invalidate entire branch predictor array
sahilmgandhi 18:6a4db94011d3 723
sahilmgandhi 18:6a4db94011d3 724 BPIALL. Branch Predictor Invalidate All.
sahilmgandhi 18:6a4db94011d3 725 */
sahilmgandhi 18:6a4db94011d3 726 // from system_Renesas_RZ_A1.c
sahilmgandhi 18:6a4db94011d3 727 __STATIC_INLINE void __v7_inv_btac(void) {
sahilmgandhi 18:6a4db94011d3 728 uint32_t val = 0;
sahilmgandhi 18:6a4db94011d3 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
sahilmgandhi 18:6a4db94011d3 730 __DSB(); //ensure completion of the invalidation
sahilmgandhi 18:6a4db94011d3 731 __ISB(); //ensure instruction fetch path sees new state
sahilmgandhi 18:6a4db94011d3 732 }
sahilmgandhi 18:6a4db94011d3 733
sahilmgandhi 18:6a4db94011d3 734
sahilmgandhi 18:6a4db94011d3 735 /******************************** L1 cache operations ******************************************************/
sahilmgandhi 18:6a4db94011d3 736
sahilmgandhi 18:6a4db94011d3 737 /** \brief Invalidate the whole I$
sahilmgandhi 18:6a4db94011d3 738
sahilmgandhi 18:6a4db94011d3 739 ICIALLU. Instruction Cache Invalidate All to PoU
sahilmgandhi 18:6a4db94011d3 740 */
sahilmgandhi 18:6a4db94011d3 741 // from system_Renesas_RZ_A1.c
sahilmgandhi 18:6a4db94011d3 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
sahilmgandhi 18:6a4db94011d3 743 uint32_t val = 0;
sahilmgandhi 18:6a4db94011d3 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
sahilmgandhi 18:6a4db94011d3 745 __DSB(); //ensure completion of the invalidation
sahilmgandhi 18:6a4db94011d3 746 __ISB(); //ensure instruction fetch path sees new I cache state
sahilmgandhi 18:6a4db94011d3 747 }
sahilmgandhi 18:6a4db94011d3 748
sahilmgandhi 18:6a4db94011d3 749 // from __v7_inv_dcache_all()
sahilmgandhi 18:6a4db94011d3 750 __arm static inline void __v7_all_cache(uint32_t op) {
sahilmgandhi 18:6a4db94011d3 751 __asm(
sahilmgandhi 18:6a4db94011d3 752 " ARM \n"
sahilmgandhi 18:6a4db94011d3 753
sahilmgandhi 18:6a4db94011d3 754 " PUSH {R4-R11} \n"
sahilmgandhi 18:6a4db94011d3 755
sahilmgandhi 18:6a4db94011d3 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
sahilmgandhi 18:6a4db94011d3 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
sahilmgandhi 18:6a4db94011d3 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
sahilmgandhi 18:6a4db94011d3 759 " BEQ Finished\n" // If 0, no need to clean
sahilmgandhi 18:6a4db94011d3 760
sahilmgandhi 18:6a4db94011d3 761 " MOV R10, #0\n" // R10 holds current cache level << 1
sahilmgandhi 18:6a4db94011d3 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
sahilmgandhi 18:6a4db94011d3 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
sahilmgandhi 18:6a4db94011d3 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
sahilmgandhi 18:6a4db94011d3 765 " CMP R1, #2 \n"
sahilmgandhi 18:6a4db94011d3 766 " BLT Skip \n" // No cache or only instruction cache at this level
sahilmgandhi 18:6a4db94011d3 767
sahilmgandhi 18:6a4db94011d3 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
sahilmgandhi 18:6a4db94011d3 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
sahilmgandhi 18:6a4db94011d3 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
sahilmgandhi 18:6a4db94011d3 771 " AND R2, R1, #7 \n" // Extract the line length field
sahilmgandhi 18:6a4db94011d3 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
sahilmgandhi 18:6a4db94011d3 773 " movw R4, #0x3FF \n"
sahilmgandhi 18:6a4db94011d3 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
sahilmgandhi 18:6a4db94011d3 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
sahilmgandhi 18:6a4db94011d3 776 " movw R7, #0x7FFF \n"
sahilmgandhi 18:6a4db94011d3 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
sahilmgandhi 18:6a4db94011d3 778
sahilmgandhi 18:6a4db94011d3 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
sahilmgandhi 18:6a4db94011d3 780
sahilmgandhi 18:6a4db94011d3 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
sahilmgandhi 18:6a4db94011d3 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
sahilmgandhi 18:6a4db94011d3 783 " CMP R0, #0 \n"
sahilmgandhi 18:6a4db94011d3 784 " BNE Dccsw \n"
sahilmgandhi 18:6a4db94011d3 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
sahilmgandhi 18:6a4db94011d3 786 " B cont \n"
sahilmgandhi 18:6a4db94011d3 787 "Dccsw: CMP R0, #1 \n"
sahilmgandhi 18:6a4db94011d3 788 " BNE Dccisw \n"
sahilmgandhi 18:6a4db94011d3 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
sahilmgandhi 18:6a4db94011d3 790 " B cont \n"
sahilmgandhi 18:6a4db94011d3 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
sahilmgandhi 18:6a4db94011d3 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
sahilmgandhi 18:6a4db94011d3 793 " BGE Loop3 \n"
sahilmgandhi 18:6a4db94011d3 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
sahilmgandhi 18:6a4db94011d3 795 " BGE Loop2 \n"
sahilmgandhi 18:6a4db94011d3 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
sahilmgandhi 18:6a4db94011d3 797 " CMP R3, R10 \n"
sahilmgandhi 18:6a4db94011d3 798 " BGT Loop1 \n"
sahilmgandhi 18:6a4db94011d3 799
sahilmgandhi 18:6a4db94011d3 800 "Finished: \n"
sahilmgandhi 18:6a4db94011d3 801 " DSB \n"
sahilmgandhi 18:6a4db94011d3 802 " POP {R4-R11} \n"
sahilmgandhi 18:6a4db94011d3 803 " BX lr \n" );
sahilmgandhi 18:6a4db94011d3 804 }
sahilmgandhi 18:6a4db94011d3 805
sahilmgandhi 18:6a4db94011d3 806 /** \brief Invalidate the whole D$
sahilmgandhi 18:6a4db94011d3 807
sahilmgandhi 18:6a4db94011d3 808 DCISW. Invalidate by Set/Way
sahilmgandhi 18:6a4db94011d3 809 */
sahilmgandhi 18:6a4db94011d3 810 // from system_Renesas_RZ_A1.c
sahilmgandhi 18:6a4db94011d3 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
sahilmgandhi 18:6a4db94011d3 812 __v7_all_cache(0);
sahilmgandhi 18:6a4db94011d3 813 }
sahilmgandhi 18:6a4db94011d3 814 /** \brief Clean the whole D$
sahilmgandhi 18:6a4db94011d3 815
sahilmgandhi 18:6a4db94011d3 816 DCCSW. Clean by Set/Way
sahilmgandhi 18:6a4db94011d3 817 */
sahilmgandhi 18:6a4db94011d3 818
sahilmgandhi 18:6a4db94011d3 819 __STATIC_INLINE void __v7_clean_dcache_all(void) {
sahilmgandhi 18:6a4db94011d3 820 __v7_all_cache(1);
sahilmgandhi 18:6a4db94011d3 821 }
sahilmgandhi 18:6a4db94011d3 822
sahilmgandhi 18:6a4db94011d3 823 /** \brief Clean and invalidate the whole D$
sahilmgandhi 18:6a4db94011d3 824
sahilmgandhi 18:6a4db94011d3 825 DCCISW. Clean and Invalidate by Set/Way
sahilmgandhi 18:6a4db94011d3 826 */
sahilmgandhi 18:6a4db94011d3 827
sahilmgandhi 18:6a4db94011d3 828 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
sahilmgandhi 18:6a4db94011d3 829 __v7_all_cache(2);
sahilmgandhi 18:6a4db94011d3 830 }
sahilmgandhi 18:6a4db94011d3 831 /** \brief Clean and Invalidate D$ by MVA
sahilmgandhi 18:6a4db94011d3 832
sahilmgandhi 18:6a4db94011d3 833 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
sahilmgandhi 18:6a4db94011d3 834 */
sahilmgandhi 18:6a4db94011d3 835 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
sahilmgandhi 18:6a4db94011d3 836 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
sahilmgandhi 18:6a4db94011d3 837 __DMB();
sahilmgandhi 18:6a4db94011d3 838 }
sahilmgandhi 18:6a4db94011d3 839
sahilmgandhi 18:6a4db94011d3 840 #include "core_ca_mmu.h"
sahilmgandhi 18:6a4db94011d3 841
sahilmgandhi 18:6a4db94011d3 842 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
sahilmgandhi 18:6a4db94011d3 843 /* GNU gcc specific functions */
sahilmgandhi 18:6a4db94011d3 844
sahilmgandhi 18:6a4db94011d3 845 #define MODE_USR 0x10
sahilmgandhi 18:6a4db94011d3 846 #define MODE_FIQ 0x11
sahilmgandhi 18:6a4db94011d3 847 #define MODE_IRQ 0x12
sahilmgandhi 18:6a4db94011d3 848 #define MODE_SVC 0x13
sahilmgandhi 18:6a4db94011d3 849 #define MODE_MON 0x16
sahilmgandhi 18:6a4db94011d3 850 #define MODE_ABT 0x17
sahilmgandhi 18:6a4db94011d3 851 #define MODE_HYP 0x1A
sahilmgandhi 18:6a4db94011d3 852 #define MODE_UND 0x1B
sahilmgandhi 18:6a4db94011d3 853 #define MODE_SYS 0x1F
sahilmgandhi 18:6a4db94011d3 854
sahilmgandhi 18:6a4db94011d3 855
sahilmgandhi 18:6a4db94011d3 856 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
sahilmgandhi 18:6a4db94011d3 857 {
sahilmgandhi 18:6a4db94011d3 858 __ASM volatile ("cpsie i");
sahilmgandhi 18:6a4db94011d3 859 }
sahilmgandhi 18:6a4db94011d3 860
sahilmgandhi 18:6a4db94011d3 861 /** \brief Disable IRQ Interrupts
sahilmgandhi 18:6a4db94011d3 862
sahilmgandhi 18:6a4db94011d3 863 This function disables IRQ interrupts by setting the I-bit in the CPSR.
sahilmgandhi 18:6a4db94011d3 864 Can only be executed in Privileged modes.
sahilmgandhi 18:6a4db94011d3 865 */
sahilmgandhi 18:6a4db94011d3 866 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
sahilmgandhi 18:6a4db94011d3 867 {
sahilmgandhi 18:6a4db94011d3 868 uint32_t result;
sahilmgandhi 18:6a4db94011d3 869
sahilmgandhi 18:6a4db94011d3 870 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
sahilmgandhi 18:6a4db94011d3 871 __ASM volatile ("cpsid i");
sahilmgandhi 18:6a4db94011d3 872 return(result & 0x80);
sahilmgandhi 18:6a4db94011d3 873 }
sahilmgandhi 18:6a4db94011d3 874
sahilmgandhi 18:6a4db94011d3 875
sahilmgandhi 18:6a4db94011d3 876 /** \brief Get APSR Register
sahilmgandhi 18:6a4db94011d3 877
sahilmgandhi 18:6a4db94011d3 878 This function returns the content of the APSR Register.
sahilmgandhi 18:6a4db94011d3 879
sahilmgandhi 18:6a4db94011d3 880 \return APSR Register value
sahilmgandhi 18:6a4db94011d3 881 */
sahilmgandhi 18:6a4db94011d3 882 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
sahilmgandhi 18:6a4db94011d3 883 {
sahilmgandhi 18:6a4db94011d3 884 #if 1
sahilmgandhi 18:6a4db94011d3 885 register uint32_t __regAPSR;
sahilmgandhi 18:6a4db94011d3 886 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
sahilmgandhi 18:6a4db94011d3 887 #else
sahilmgandhi 18:6a4db94011d3 888 register uint32_t __regAPSR __ASM("apsr");
sahilmgandhi 18:6a4db94011d3 889 #endif
sahilmgandhi 18:6a4db94011d3 890 return(__regAPSR);
sahilmgandhi 18:6a4db94011d3 891 }
sahilmgandhi 18:6a4db94011d3 892
sahilmgandhi 18:6a4db94011d3 893
sahilmgandhi 18:6a4db94011d3 894 /** \brief Get CPSR Register
sahilmgandhi 18:6a4db94011d3 895
sahilmgandhi 18:6a4db94011d3 896 This function returns the content of the CPSR Register.
sahilmgandhi 18:6a4db94011d3 897
sahilmgandhi 18:6a4db94011d3 898 \return CPSR Register value
sahilmgandhi 18:6a4db94011d3 899 */
sahilmgandhi 18:6a4db94011d3 900 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
sahilmgandhi 18:6a4db94011d3 901 {
sahilmgandhi 18:6a4db94011d3 902 #if 1
sahilmgandhi 18:6a4db94011d3 903 register uint32_t __regCPSR;
sahilmgandhi 18:6a4db94011d3 904 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
sahilmgandhi 18:6a4db94011d3 905 #else
sahilmgandhi 18:6a4db94011d3 906 register uint32_t __regCPSR __ASM("cpsr");
sahilmgandhi 18:6a4db94011d3 907 #endif
sahilmgandhi 18:6a4db94011d3 908 return(__regCPSR);
sahilmgandhi 18:6a4db94011d3 909 }
sahilmgandhi 18:6a4db94011d3 910
sahilmgandhi 18:6a4db94011d3 911 #if 0
sahilmgandhi 18:6a4db94011d3 912 /** \brief Set Stack Pointer
sahilmgandhi 18:6a4db94011d3 913
sahilmgandhi 18:6a4db94011d3 914 This function assigns the given value to the current stack pointer.
sahilmgandhi 18:6a4db94011d3 915
sahilmgandhi 18:6a4db94011d3 916 \param [in] topOfStack Stack Pointer value to set
sahilmgandhi 18:6a4db94011d3 917 */
sahilmgandhi 18:6a4db94011d3 918 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
sahilmgandhi 18:6a4db94011d3 919 {
sahilmgandhi 18:6a4db94011d3 920 register uint32_t __regSP __ASM("sp");
sahilmgandhi 18:6a4db94011d3 921 __regSP = topOfStack;
sahilmgandhi 18:6a4db94011d3 922 }
sahilmgandhi 18:6a4db94011d3 923 #endif
sahilmgandhi 18:6a4db94011d3 924
sahilmgandhi 18:6a4db94011d3 925 /** \brief Get link register
sahilmgandhi 18:6a4db94011d3 926
sahilmgandhi 18:6a4db94011d3 927 This function returns the value of the link register
sahilmgandhi 18:6a4db94011d3 928
sahilmgandhi 18:6a4db94011d3 929 \return Value of link register
sahilmgandhi 18:6a4db94011d3 930 */
sahilmgandhi 18:6a4db94011d3 931 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
sahilmgandhi 18:6a4db94011d3 932 {
sahilmgandhi 18:6a4db94011d3 933 register uint32_t __reglr __ASM("lr");
sahilmgandhi 18:6a4db94011d3 934 return(__reglr);
sahilmgandhi 18:6a4db94011d3 935 }
sahilmgandhi 18:6a4db94011d3 936
sahilmgandhi 18:6a4db94011d3 937 #if 0
sahilmgandhi 18:6a4db94011d3 938 /** \brief Set link register
sahilmgandhi 18:6a4db94011d3 939
sahilmgandhi 18:6a4db94011d3 940 This function sets the value of the link register
sahilmgandhi 18:6a4db94011d3 941
sahilmgandhi 18:6a4db94011d3 942 \param [in] lr LR value to set
sahilmgandhi 18:6a4db94011d3 943 */
sahilmgandhi 18:6a4db94011d3 944 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
sahilmgandhi 18:6a4db94011d3 945 {
sahilmgandhi 18:6a4db94011d3 946 register uint32_t __reglr __ASM("lr");
sahilmgandhi 18:6a4db94011d3 947 __reglr = lr;
sahilmgandhi 18:6a4db94011d3 948 }
sahilmgandhi 18:6a4db94011d3 949 #endif
sahilmgandhi 18:6a4db94011d3 950
sahilmgandhi 18:6a4db94011d3 951 /** \brief Set Process Stack Pointer
sahilmgandhi 18:6a4db94011d3 952
sahilmgandhi 18:6a4db94011d3 953 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
sahilmgandhi 18:6a4db94011d3 954
sahilmgandhi 18:6a4db94011d3 955 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
sahilmgandhi 18:6a4db94011d3 956 */
sahilmgandhi 18:6a4db94011d3 957 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
sahilmgandhi 18:6a4db94011d3 958 {
sahilmgandhi 18:6a4db94011d3 959 __asm__ volatile (
sahilmgandhi 18:6a4db94011d3 960 ".ARM;"
sahilmgandhi 18:6a4db94011d3 961 ".eabi_attribute Tag_ABI_align8_preserved,1;"
sahilmgandhi 18:6a4db94011d3 962
sahilmgandhi 18:6a4db94011d3 963 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
sahilmgandhi 18:6a4db94011d3 964 "MRS R1, CPSR;"
sahilmgandhi 18:6a4db94011d3 965 "CPS %0;" /* ;no effect in USR mode */
sahilmgandhi 18:6a4db94011d3 966 "MOV SP, R0;"
sahilmgandhi 18:6a4db94011d3 967 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
sahilmgandhi 18:6a4db94011d3 968 "ISB;"
sahilmgandhi 18:6a4db94011d3 969 //"BX LR;"
sahilmgandhi 18:6a4db94011d3 970 :
sahilmgandhi 18:6a4db94011d3 971 : "i"(MODE_SYS)
sahilmgandhi 18:6a4db94011d3 972 : "r0", "r1");
sahilmgandhi 18:6a4db94011d3 973 return;
sahilmgandhi 18:6a4db94011d3 974 }
sahilmgandhi 18:6a4db94011d3 975
sahilmgandhi 18:6a4db94011d3 976 /** \brief Set User Mode
sahilmgandhi 18:6a4db94011d3 977
sahilmgandhi 18:6a4db94011d3 978 This function changes the processor state to User Mode
sahilmgandhi 18:6a4db94011d3 979 */
sahilmgandhi 18:6a4db94011d3 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
sahilmgandhi 18:6a4db94011d3 981 {
sahilmgandhi 18:6a4db94011d3 982 __asm__ volatile (
sahilmgandhi 18:6a4db94011d3 983 ".ARM;"
sahilmgandhi 18:6a4db94011d3 984
sahilmgandhi 18:6a4db94011d3 985 "CPS %0;"
sahilmgandhi 18:6a4db94011d3 986 //"BX LR;"
sahilmgandhi 18:6a4db94011d3 987 :
sahilmgandhi 18:6a4db94011d3 988 : "i"(MODE_USR)
sahilmgandhi 18:6a4db94011d3 989 : );
sahilmgandhi 18:6a4db94011d3 990 return;
sahilmgandhi 18:6a4db94011d3 991 }
sahilmgandhi 18:6a4db94011d3 992
sahilmgandhi 18:6a4db94011d3 993
sahilmgandhi 18:6a4db94011d3 994 /** \brief Enable FIQ
sahilmgandhi 18:6a4db94011d3 995
sahilmgandhi 18:6a4db94011d3 996 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
sahilmgandhi 18:6a4db94011d3 997 Can only be executed in Privileged modes.
sahilmgandhi 18:6a4db94011d3 998 */
sahilmgandhi 18:6a4db94011d3 999 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
sahilmgandhi 18:6a4db94011d3 1000
sahilmgandhi 18:6a4db94011d3 1001
sahilmgandhi 18:6a4db94011d3 1002 /** \brief Disable FIQ
sahilmgandhi 18:6a4db94011d3 1003
sahilmgandhi 18:6a4db94011d3 1004 This function disables FIQ interrupts by setting the F-bit in the CPSR.
sahilmgandhi 18:6a4db94011d3 1005 Can only be executed in Privileged modes.
sahilmgandhi 18:6a4db94011d3 1006 */
sahilmgandhi 18:6a4db94011d3 1007 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
sahilmgandhi 18:6a4db94011d3 1008
sahilmgandhi 18:6a4db94011d3 1009
sahilmgandhi 18:6a4db94011d3 1010 /** \brief Get FPSCR
sahilmgandhi 18:6a4db94011d3 1011
sahilmgandhi 18:6a4db94011d3 1012 This function returns the current value of the Floating Point Status/Control register.
sahilmgandhi 18:6a4db94011d3 1013
sahilmgandhi 18:6a4db94011d3 1014 \return Floating Point Status/Control register value
sahilmgandhi 18:6a4db94011d3 1015 */
sahilmgandhi 18:6a4db94011d3 1016 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
sahilmgandhi 18:6a4db94011d3 1017 {
sahilmgandhi 18:6a4db94011d3 1018 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
sahilmgandhi 18:6a4db94011d3 1019 #if 1
sahilmgandhi 18:6a4db94011d3 1020 uint32_t result;
sahilmgandhi 18:6a4db94011d3 1021
sahilmgandhi 18:6a4db94011d3 1022 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
sahilmgandhi 18:6a4db94011d3 1023 return (result);
sahilmgandhi 18:6a4db94011d3 1024 #else
sahilmgandhi 18:6a4db94011d3 1025 register uint32_t __regfpscr __ASM("fpscr");
sahilmgandhi 18:6a4db94011d3 1026 return(__regfpscr);
sahilmgandhi 18:6a4db94011d3 1027 #endif
sahilmgandhi 18:6a4db94011d3 1028 #else
sahilmgandhi 18:6a4db94011d3 1029 return(0);
sahilmgandhi 18:6a4db94011d3 1030 #endif
sahilmgandhi 18:6a4db94011d3 1031 }
sahilmgandhi 18:6a4db94011d3 1032
sahilmgandhi 18:6a4db94011d3 1033
sahilmgandhi 18:6a4db94011d3 1034 /** \brief Set FPSCR
sahilmgandhi 18:6a4db94011d3 1035
sahilmgandhi 18:6a4db94011d3 1036 This function assigns the given value to the Floating Point Status/Control register.
sahilmgandhi 18:6a4db94011d3 1037
sahilmgandhi 18:6a4db94011d3 1038 \param [in] fpscr Floating Point Status/Control value to set
sahilmgandhi 18:6a4db94011d3 1039 */
sahilmgandhi 18:6a4db94011d3 1040 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
sahilmgandhi 18:6a4db94011d3 1041 {
sahilmgandhi 18:6a4db94011d3 1042 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
sahilmgandhi 18:6a4db94011d3 1043 #if 1
sahilmgandhi 18:6a4db94011d3 1044 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
sahilmgandhi 18:6a4db94011d3 1045 #else
sahilmgandhi 18:6a4db94011d3 1046 register uint32_t __regfpscr __ASM("fpscr");
sahilmgandhi 18:6a4db94011d3 1047 __regfpscr = (fpscr);
sahilmgandhi 18:6a4db94011d3 1048 #endif
sahilmgandhi 18:6a4db94011d3 1049 #endif
sahilmgandhi 18:6a4db94011d3 1050 }
sahilmgandhi 18:6a4db94011d3 1051
sahilmgandhi 18:6a4db94011d3 1052 /** \brief Get FPEXC
sahilmgandhi 18:6a4db94011d3 1053
sahilmgandhi 18:6a4db94011d3 1054 This function returns the current value of the Floating Point Exception Control register.
sahilmgandhi 18:6a4db94011d3 1055
sahilmgandhi 18:6a4db94011d3 1056 \return Floating Point Exception Control register value
sahilmgandhi 18:6a4db94011d3 1057 */
sahilmgandhi 18:6a4db94011d3 1058 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
sahilmgandhi 18:6a4db94011d3 1059 {
sahilmgandhi 18:6a4db94011d3 1060 #if (__FPU_PRESENT == 1)
sahilmgandhi 18:6a4db94011d3 1061 #if 1
sahilmgandhi 18:6a4db94011d3 1062 uint32_t result;
sahilmgandhi 18:6a4db94011d3 1063
sahilmgandhi 18:6a4db94011d3 1064 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
sahilmgandhi 18:6a4db94011d3 1065 return (result);
sahilmgandhi 18:6a4db94011d3 1066 #else
sahilmgandhi 18:6a4db94011d3 1067 register uint32_t __regfpexc __ASM("fpexc");
sahilmgandhi 18:6a4db94011d3 1068 return(__regfpexc);
sahilmgandhi 18:6a4db94011d3 1069 #endif
sahilmgandhi 18:6a4db94011d3 1070 #else
sahilmgandhi 18:6a4db94011d3 1071 return(0);
sahilmgandhi 18:6a4db94011d3 1072 #endif
sahilmgandhi 18:6a4db94011d3 1073 }
sahilmgandhi 18:6a4db94011d3 1074
sahilmgandhi 18:6a4db94011d3 1075
sahilmgandhi 18:6a4db94011d3 1076 /** \brief Set FPEXC
sahilmgandhi 18:6a4db94011d3 1077
sahilmgandhi 18:6a4db94011d3 1078 This function assigns the given value to the Floating Point Exception Control register.
sahilmgandhi 18:6a4db94011d3 1079
sahilmgandhi 18:6a4db94011d3 1080 \param [in] fpscr Floating Point Exception Control value to set
sahilmgandhi 18:6a4db94011d3 1081 */
sahilmgandhi 18:6a4db94011d3 1082 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
sahilmgandhi 18:6a4db94011d3 1083 {
sahilmgandhi 18:6a4db94011d3 1084 #if (__FPU_PRESENT == 1)
sahilmgandhi 18:6a4db94011d3 1085 #if 1
sahilmgandhi 18:6a4db94011d3 1086 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
sahilmgandhi 18:6a4db94011d3 1087 #else
sahilmgandhi 18:6a4db94011d3 1088 register uint32_t __regfpexc __ASM("fpexc");
sahilmgandhi 18:6a4db94011d3 1089 __regfpexc = (fpexc);
sahilmgandhi 18:6a4db94011d3 1090 #endif
sahilmgandhi 18:6a4db94011d3 1091 #endif
sahilmgandhi 18:6a4db94011d3 1092 }
sahilmgandhi 18:6a4db94011d3 1093
sahilmgandhi 18:6a4db94011d3 1094 /** \brief Get CPACR
sahilmgandhi 18:6a4db94011d3 1095
sahilmgandhi 18:6a4db94011d3 1096 This function returns the current value of the Coprocessor Access Control register.
sahilmgandhi 18:6a4db94011d3 1097
sahilmgandhi 18:6a4db94011d3 1098 \return Coprocessor Access Control register value
sahilmgandhi 18:6a4db94011d3 1099 */
sahilmgandhi 18:6a4db94011d3 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
sahilmgandhi 18:6a4db94011d3 1101 {
sahilmgandhi 18:6a4db94011d3 1102 #if 1
sahilmgandhi 18:6a4db94011d3 1103 register uint32_t __regCPACR;
sahilmgandhi 18:6a4db94011d3 1104 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
sahilmgandhi 18:6a4db94011d3 1105 #else
sahilmgandhi 18:6a4db94011d3 1106 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
sahilmgandhi 18:6a4db94011d3 1107 #endif
sahilmgandhi 18:6a4db94011d3 1108 return __regCPACR;
sahilmgandhi 18:6a4db94011d3 1109 }
sahilmgandhi 18:6a4db94011d3 1110
sahilmgandhi 18:6a4db94011d3 1111 /** \brief Set CPACR
sahilmgandhi 18:6a4db94011d3 1112
sahilmgandhi 18:6a4db94011d3 1113 This function assigns the given value to the Coprocessor Access Control register.
sahilmgandhi 18:6a4db94011d3 1114
sahilmgandhi 18:6a4db94011d3 1115 \param [in] cpacr Coprocessor Acccess Control value to set
sahilmgandhi 18:6a4db94011d3 1116 */
sahilmgandhi 18:6a4db94011d3 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
sahilmgandhi 18:6a4db94011d3 1118 {
sahilmgandhi 18:6a4db94011d3 1119 #if 1
sahilmgandhi 18:6a4db94011d3 1120 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
sahilmgandhi 18:6a4db94011d3 1121 #else
sahilmgandhi 18:6a4db94011d3 1122 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
sahilmgandhi 18:6a4db94011d3 1123 __regCPACR = cpacr;
sahilmgandhi 18:6a4db94011d3 1124 #endif
sahilmgandhi 18:6a4db94011d3 1125 __ISB();
sahilmgandhi 18:6a4db94011d3 1126 }
sahilmgandhi 18:6a4db94011d3 1127
sahilmgandhi 18:6a4db94011d3 1128 /** \brief Get CBAR
sahilmgandhi 18:6a4db94011d3 1129
sahilmgandhi 18:6a4db94011d3 1130 This function returns the value of the Configuration Base Address register.
sahilmgandhi 18:6a4db94011d3 1131
sahilmgandhi 18:6a4db94011d3 1132 \return Configuration Base Address register value
sahilmgandhi 18:6a4db94011d3 1133 */
sahilmgandhi 18:6a4db94011d3 1134 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
sahilmgandhi 18:6a4db94011d3 1135 #if 1
sahilmgandhi 18:6a4db94011d3 1136 register uint32_t __regCBAR;
sahilmgandhi 18:6a4db94011d3 1137 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
sahilmgandhi 18:6a4db94011d3 1138 #else
sahilmgandhi 18:6a4db94011d3 1139 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
sahilmgandhi 18:6a4db94011d3 1140 #endif
sahilmgandhi 18:6a4db94011d3 1141 return(__regCBAR);
sahilmgandhi 18:6a4db94011d3 1142 }
sahilmgandhi 18:6a4db94011d3 1143
sahilmgandhi 18:6a4db94011d3 1144 /** \brief Get TTBR0
sahilmgandhi 18:6a4db94011d3 1145
sahilmgandhi 18:6a4db94011d3 1146 This function returns the value of the Translation Table Base Register 0.
sahilmgandhi 18:6a4db94011d3 1147
sahilmgandhi 18:6a4db94011d3 1148 \return Translation Table Base Register 0 value
sahilmgandhi 18:6a4db94011d3 1149 */
sahilmgandhi 18:6a4db94011d3 1150 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
sahilmgandhi 18:6a4db94011d3 1151 #if 1
sahilmgandhi 18:6a4db94011d3 1152 register uint32_t __regTTBR0;
sahilmgandhi 18:6a4db94011d3 1153 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
sahilmgandhi 18:6a4db94011d3 1154 #else
sahilmgandhi 18:6a4db94011d3 1155 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
sahilmgandhi 18:6a4db94011d3 1156 #endif
sahilmgandhi 18:6a4db94011d3 1157 return(__regTTBR0);
sahilmgandhi 18:6a4db94011d3 1158 }
sahilmgandhi 18:6a4db94011d3 1159
sahilmgandhi 18:6a4db94011d3 1160 /** \brief Set TTBR0
sahilmgandhi 18:6a4db94011d3 1161
sahilmgandhi 18:6a4db94011d3 1162 This function assigns the given value to the Translation Table Base Register 0.
sahilmgandhi 18:6a4db94011d3 1163
sahilmgandhi 18:6a4db94011d3 1164 \param [in] ttbr0 Translation Table Base Register 0 value to set
sahilmgandhi 18:6a4db94011d3 1165 */
sahilmgandhi 18:6a4db94011d3 1166 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
sahilmgandhi 18:6a4db94011d3 1167 #if 1
sahilmgandhi 18:6a4db94011d3 1168 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
sahilmgandhi 18:6a4db94011d3 1169 #else
sahilmgandhi 18:6a4db94011d3 1170 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
sahilmgandhi 18:6a4db94011d3 1171 __regTTBR0 = ttbr0;
sahilmgandhi 18:6a4db94011d3 1172 #endif
sahilmgandhi 18:6a4db94011d3 1173 __ISB();
sahilmgandhi 18:6a4db94011d3 1174 }
sahilmgandhi 18:6a4db94011d3 1175
sahilmgandhi 18:6a4db94011d3 1176 /** \brief Get DACR
sahilmgandhi 18:6a4db94011d3 1177
sahilmgandhi 18:6a4db94011d3 1178 This function returns the value of the Domain Access Control Register.
sahilmgandhi 18:6a4db94011d3 1179
sahilmgandhi 18:6a4db94011d3 1180 \return Domain Access Control Register value
sahilmgandhi 18:6a4db94011d3 1181 */
sahilmgandhi 18:6a4db94011d3 1182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
sahilmgandhi 18:6a4db94011d3 1183 #if 1
sahilmgandhi 18:6a4db94011d3 1184 register uint32_t __regDACR;
sahilmgandhi 18:6a4db94011d3 1185 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
sahilmgandhi 18:6a4db94011d3 1186 #else
sahilmgandhi 18:6a4db94011d3 1187 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
sahilmgandhi 18:6a4db94011d3 1188 #endif
sahilmgandhi 18:6a4db94011d3 1189 return(__regDACR);
sahilmgandhi 18:6a4db94011d3 1190 }
sahilmgandhi 18:6a4db94011d3 1191
sahilmgandhi 18:6a4db94011d3 1192 /** \brief Set DACR
sahilmgandhi 18:6a4db94011d3 1193
sahilmgandhi 18:6a4db94011d3 1194 This function assigns the given value to the Domain Access Control Register.
sahilmgandhi 18:6a4db94011d3 1195
sahilmgandhi 18:6a4db94011d3 1196 \param [in] dacr Domain Access Control Register value to set
sahilmgandhi 18:6a4db94011d3 1197 */
sahilmgandhi 18:6a4db94011d3 1198 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
sahilmgandhi 18:6a4db94011d3 1199 #if 1
sahilmgandhi 18:6a4db94011d3 1200 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
sahilmgandhi 18:6a4db94011d3 1201 #else
sahilmgandhi 18:6a4db94011d3 1202 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
sahilmgandhi 18:6a4db94011d3 1203 __regDACR = dacr;
sahilmgandhi 18:6a4db94011d3 1204 #endif
sahilmgandhi 18:6a4db94011d3 1205 __ISB();
sahilmgandhi 18:6a4db94011d3 1206 }
sahilmgandhi 18:6a4db94011d3 1207
sahilmgandhi 18:6a4db94011d3 1208 /******************************** Cache and BTAC enable ****************************************************/
sahilmgandhi 18:6a4db94011d3 1209
sahilmgandhi 18:6a4db94011d3 1210 /** \brief Set SCTLR
sahilmgandhi 18:6a4db94011d3 1211
sahilmgandhi 18:6a4db94011d3 1212 This function assigns the given value to the System Control Register.
sahilmgandhi 18:6a4db94011d3 1213
sahilmgandhi 18:6a4db94011d3 1214 \param [in] sctlr System Control Register value to set
sahilmgandhi 18:6a4db94011d3 1215 */
sahilmgandhi 18:6a4db94011d3 1216 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
sahilmgandhi 18:6a4db94011d3 1217 {
sahilmgandhi 18:6a4db94011d3 1218 #if 1
sahilmgandhi 18:6a4db94011d3 1219 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
sahilmgandhi 18:6a4db94011d3 1220 #else
sahilmgandhi 18:6a4db94011d3 1221 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
sahilmgandhi 18:6a4db94011d3 1222 __regSCTLR = sctlr;
sahilmgandhi 18:6a4db94011d3 1223 #endif
sahilmgandhi 18:6a4db94011d3 1224 }
sahilmgandhi 18:6a4db94011d3 1225
sahilmgandhi 18:6a4db94011d3 1226 /** \brief Get SCTLR
sahilmgandhi 18:6a4db94011d3 1227
sahilmgandhi 18:6a4db94011d3 1228 This function returns the value of the System Control Register.
sahilmgandhi 18:6a4db94011d3 1229
sahilmgandhi 18:6a4db94011d3 1230 \return System Control Register value
sahilmgandhi 18:6a4db94011d3 1231 */
sahilmgandhi 18:6a4db94011d3 1232 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
sahilmgandhi 18:6a4db94011d3 1233 #if 1
sahilmgandhi 18:6a4db94011d3 1234 register uint32_t __regSCTLR;
sahilmgandhi 18:6a4db94011d3 1235 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
sahilmgandhi 18:6a4db94011d3 1236 #else
sahilmgandhi 18:6a4db94011d3 1237 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
sahilmgandhi 18:6a4db94011d3 1238 #endif
sahilmgandhi 18:6a4db94011d3 1239 return(__regSCTLR);
sahilmgandhi 18:6a4db94011d3 1240 }
sahilmgandhi 18:6a4db94011d3 1241
sahilmgandhi 18:6a4db94011d3 1242 /** \brief Enable Caches
sahilmgandhi 18:6a4db94011d3 1243
sahilmgandhi 18:6a4db94011d3 1244 Enable Caches
sahilmgandhi 18:6a4db94011d3 1245 */
sahilmgandhi 18:6a4db94011d3 1246 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
sahilmgandhi 18:6a4db94011d3 1247 // Set I bit 12 to enable I Cache
sahilmgandhi 18:6a4db94011d3 1248 // Set C bit 2 to enable D Cache
sahilmgandhi 18:6a4db94011d3 1249 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
sahilmgandhi 18:6a4db94011d3 1250 }
sahilmgandhi 18:6a4db94011d3 1251
sahilmgandhi 18:6a4db94011d3 1252 /** \brief Disable Caches
sahilmgandhi 18:6a4db94011d3 1253
sahilmgandhi 18:6a4db94011d3 1254 Disable Caches
sahilmgandhi 18:6a4db94011d3 1255 */
sahilmgandhi 18:6a4db94011d3 1256 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
sahilmgandhi 18:6a4db94011d3 1257 // Clear I bit 12 to disable I Cache
sahilmgandhi 18:6a4db94011d3 1258 // Clear C bit 2 to disable D Cache
sahilmgandhi 18:6a4db94011d3 1259 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
sahilmgandhi 18:6a4db94011d3 1260 __ISB();
sahilmgandhi 18:6a4db94011d3 1261 }
sahilmgandhi 18:6a4db94011d3 1262
sahilmgandhi 18:6a4db94011d3 1263 /** \brief Enable BTAC
sahilmgandhi 18:6a4db94011d3 1264
sahilmgandhi 18:6a4db94011d3 1265 Enable BTAC
sahilmgandhi 18:6a4db94011d3 1266 */
sahilmgandhi 18:6a4db94011d3 1267 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
sahilmgandhi 18:6a4db94011d3 1268 // Set Z bit 11 to enable branch prediction
sahilmgandhi 18:6a4db94011d3 1269 __set_SCTLR( __get_SCTLR() | (1 << 11));
sahilmgandhi 18:6a4db94011d3 1270 __ISB();
sahilmgandhi 18:6a4db94011d3 1271 }
sahilmgandhi 18:6a4db94011d3 1272
sahilmgandhi 18:6a4db94011d3 1273 /** \brief Disable BTAC
sahilmgandhi 18:6a4db94011d3 1274
sahilmgandhi 18:6a4db94011d3 1275 Disable BTAC
sahilmgandhi 18:6a4db94011d3 1276 */
sahilmgandhi 18:6a4db94011d3 1277 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
sahilmgandhi 18:6a4db94011d3 1278 // Clear Z bit 11 to disable branch prediction
sahilmgandhi 18:6a4db94011d3 1279 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
sahilmgandhi 18:6a4db94011d3 1280 }
sahilmgandhi 18:6a4db94011d3 1281
sahilmgandhi 18:6a4db94011d3 1282
sahilmgandhi 18:6a4db94011d3 1283 /** \brief Enable MMU
sahilmgandhi 18:6a4db94011d3 1284
sahilmgandhi 18:6a4db94011d3 1285 Enable MMU
sahilmgandhi 18:6a4db94011d3 1286 */
sahilmgandhi 18:6a4db94011d3 1287 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
sahilmgandhi 18:6a4db94011d3 1288 // Set M bit 0 to enable the MMU
sahilmgandhi 18:6a4db94011d3 1289 // Set AFE bit to enable simplified access permissions model
sahilmgandhi 18:6a4db94011d3 1290 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
sahilmgandhi 18:6a4db94011d3 1291 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
sahilmgandhi 18:6a4db94011d3 1292 __ISB();
sahilmgandhi 18:6a4db94011d3 1293 }
sahilmgandhi 18:6a4db94011d3 1294
sahilmgandhi 18:6a4db94011d3 1295 /** \brief Disable MMU
sahilmgandhi 18:6a4db94011d3 1296
sahilmgandhi 18:6a4db94011d3 1297 Disable MMU
sahilmgandhi 18:6a4db94011d3 1298 */
sahilmgandhi 18:6a4db94011d3 1299 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
sahilmgandhi 18:6a4db94011d3 1300 // Clear M bit 0 to disable the MMU
sahilmgandhi 18:6a4db94011d3 1301 __set_SCTLR( __get_SCTLR() & ~1);
sahilmgandhi 18:6a4db94011d3 1302 __ISB();
sahilmgandhi 18:6a4db94011d3 1303 }
sahilmgandhi 18:6a4db94011d3 1304
sahilmgandhi 18:6a4db94011d3 1305 /******************************** TLB maintenance operations ************************************************/
sahilmgandhi 18:6a4db94011d3 1306 /** \brief Invalidate the whole tlb
sahilmgandhi 18:6a4db94011d3 1307
sahilmgandhi 18:6a4db94011d3 1308 TLBIALL. Invalidate the whole tlb
sahilmgandhi 18:6a4db94011d3 1309 */
sahilmgandhi 18:6a4db94011d3 1310
sahilmgandhi 18:6a4db94011d3 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
sahilmgandhi 18:6a4db94011d3 1312 #if 1
sahilmgandhi 18:6a4db94011d3 1313 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
sahilmgandhi 18:6a4db94011d3 1314 #else
sahilmgandhi 18:6a4db94011d3 1315 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
sahilmgandhi 18:6a4db94011d3 1316 __TLBIALL = 0;
sahilmgandhi 18:6a4db94011d3 1317 #endif
sahilmgandhi 18:6a4db94011d3 1318 __DSB();
sahilmgandhi 18:6a4db94011d3 1319 __ISB();
sahilmgandhi 18:6a4db94011d3 1320 }
sahilmgandhi 18:6a4db94011d3 1321
sahilmgandhi 18:6a4db94011d3 1322 /******************************** BTB maintenance operations ************************************************/
sahilmgandhi 18:6a4db94011d3 1323 /** \brief Invalidate entire branch predictor array
sahilmgandhi 18:6a4db94011d3 1324
sahilmgandhi 18:6a4db94011d3 1325 BPIALL. Branch Predictor Invalidate All.
sahilmgandhi 18:6a4db94011d3 1326 */
sahilmgandhi 18:6a4db94011d3 1327
sahilmgandhi 18:6a4db94011d3 1328 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
sahilmgandhi 18:6a4db94011d3 1329 #if 1
sahilmgandhi 18:6a4db94011d3 1330 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
sahilmgandhi 18:6a4db94011d3 1331 #else
sahilmgandhi 18:6a4db94011d3 1332 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
sahilmgandhi 18:6a4db94011d3 1333 __BPIALL = 0;
sahilmgandhi 18:6a4db94011d3 1334 #endif
sahilmgandhi 18:6a4db94011d3 1335 __DSB(); //ensure completion of the invalidation
sahilmgandhi 18:6a4db94011d3 1336 __ISB(); //ensure instruction fetch path sees new state
sahilmgandhi 18:6a4db94011d3 1337 }
sahilmgandhi 18:6a4db94011d3 1338
sahilmgandhi 18:6a4db94011d3 1339
sahilmgandhi 18:6a4db94011d3 1340 /******************************** L1 cache operations ******************************************************/
sahilmgandhi 18:6a4db94011d3 1341
sahilmgandhi 18:6a4db94011d3 1342 /** \brief Invalidate the whole I$
sahilmgandhi 18:6a4db94011d3 1343
sahilmgandhi 18:6a4db94011d3 1344 ICIALLU. Instruction Cache Invalidate All to PoU
sahilmgandhi 18:6a4db94011d3 1345 */
sahilmgandhi 18:6a4db94011d3 1346 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
sahilmgandhi 18:6a4db94011d3 1347 #if 1
sahilmgandhi 18:6a4db94011d3 1348 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
sahilmgandhi 18:6a4db94011d3 1349 #else
sahilmgandhi 18:6a4db94011d3 1350 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
sahilmgandhi 18:6a4db94011d3 1351 __ICIALLU = 0;
sahilmgandhi 18:6a4db94011d3 1352 #endif
sahilmgandhi 18:6a4db94011d3 1353 __DSB(); //ensure completion of the invalidation
sahilmgandhi 18:6a4db94011d3 1354 __ISB(); //ensure instruction fetch path sees new I cache state
sahilmgandhi 18:6a4db94011d3 1355 }
sahilmgandhi 18:6a4db94011d3 1356
sahilmgandhi 18:6a4db94011d3 1357 /** \brief Clean D$ by MVA
sahilmgandhi 18:6a4db94011d3 1358
sahilmgandhi 18:6a4db94011d3 1359 DCCMVAC. Data cache clean by MVA to PoC
sahilmgandhi 18:6a4db94011d3 1360 */
sahilmgandhi 18:6a4db94011d3 1361 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
sahilmgandhi 18:6a4db94011d3 1362 #if 1
sahilmgandhi 18:6a4db94011d3 1363 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
sahilmgandhi 18:6a4db94011d3 1364 #else
sahilmgandhi 18:6a4db94011d3 1365 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
sahilmgandhi 18:6a4db94011d3 1366 __DCCMVAC = (uint32_t)va;
sahilmgandhi 18:6a4db94011d3 1367 #endif
sahilmgandhi 18:6a4db94011d3 1368 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
sahilmgandhi 18:6a4db94011d3 1369 }
sahilmgandhi 18:6a4db94011d3 1370
sahilmgandhi 18:6a4db94011d3 1371 /** \brief Invalidate D$ by MVA
sahilmgandhi 18:6a4db94011d3 1372
sahilmgandhi 18:6a4db94011d3 1373 DCIMVAC. Data cache invalidate by MVA to PoC
sahilmgandhi 18:6a4db94011d3 1374 */
sahilmgandhi 18:6a4db94011d3 1375 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
sahilmgandhi 18:6a4db94011d3 1376 #if 1
sahilmgandhi 18:6a4db94011d3 1377 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
sahilmgandhi 18:6a4db94011d3 1378 #else
sahilmgandhi 18:6a4db94011d3 1379 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
sahilmgandhi 18:6a4db94011d3 1380 __DCIMVAC = (uint32_t)va;
sahilmgandhi 18:6a4db94011d3 1381 #endif
sahilmgandhi 18:6a4db94011d3 1382 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
sahilmgandhi 18:6a4db94011d3 1383 }
sahilmgandhi 18:6a4db94011d3 1384
sahilmgandhi 18:6a4db94011d3 1385 /** \brief Clean and Invalidate D$ by MVA
sahilmgandhi 18:6a4db94011d3 1386
sahilmgandhi 18:6a4db94011d3 1387 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
sahilmgandhi 18:6a4db94011d3 1388 */
sahilmgandhi 18:6a4db94011d3 1389 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
sahilmgandhi 18:6a4db94011d3 1390 #if 1
sahilmgandhi 18:6a4db94011d3 1391 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
sahilmgandhi 18:6a4db94011d3 1392 #else
sahilmgandhi 18:6a4db94011d3 1393 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
sahilmgandhi 18:6a4db94011d3 1394 __DCCIMVAC = (uint32_t)va;
sahilmgandhi 18:6a4db94011d3 1395 #endif
sahilmgandhi 18:6a4db94011d3 1396 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
sahilmgandhi 18:6a4db94011d3 1397 }
sahilmgandhi 18:6a4db94011d3 1398
sahilmgandhi 18:6a4db94011d3 1399 /** \brief Clean and Invalidate the entire data or unified cache
sahilmgandhi 18:6a4db94011d3 1400
sahilmgandhi 18:6a4db94011d3 1401 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
sahilmgandhi 18:6a4db94011d3 1402 */
sahilmgandhi 18:6a4db94011d3 1403 extern void __v7_all_cache(uint32_t op);
sahilmgandhi 18:6a4db94011d3 1404
sahilmgandhi 18:6a4db94011d3 1405
sahilmgandhi 18:6a4db94011d3 1406 /** \brief Invalidate the whole D$
sahilmgandhi 18:6a4db94011d3 1407
sahilmgandhi 18:6a4db94011d3 1408 DCISW. Invalidate by Set/Way
sahilmgandhi 18:6a4db94011d3 1409 */
sahilmgandhi 18:6a4db94011d3 1410
sahilmgandhi 18:6a4db94011d3 1411 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
sahilmgandhi 18:6a4db94011d3 1412 __v7_all_cache(0);
sahilmgandhi 18:6a4db94011d3 1413 }
sahilmgandhi 18:6a4db94011d3 1414
sahilmgandhi 18:6a4db94011d3 1415 /** \brief Clean the whole D$
sahilmgandhi 18:6a4db94011d3 1416
sahilmgandhi 18:6a4db94011d3 1417 DCCSW. Clean by Set/Way
sahilmgandhi 18:6a4db94011d3 1418 */
sahilmgandhi 18:6a4db94011d3 1419
sahilmgandhi 18:6a4db94011d3 1420 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
sahilmgandhi 18:6a4db94011d3 1421 __v7_all_cache(1);
sahilmgandhi 18:6a4db94011d3 1422 }
sahilmgandhi 18:6a4db94011d3 1423
sahilmgandhi 18:6a4db94011d3 1424 /** \brief Clean and invalidate the whole D$
sahilmgandhi 18:6a4db94011d3 1425
sahilmgandhi 18:6a4db94011d3 1426 DCCISW. Clean and Invalidate by Set/Way
sahilmgandhi 18:6a4db94011d3 1427 */
sahilmgandhi 18:6a4db94011d3 1428
sahilmgandhi 18:6a4db94011d3 1429 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
sahilmgandhi 18:6a4db94011d3 1430 __v7_all_cache(2);
sahilmgandhi 18:6a4db94011d3 1431 }
sahilmgandhi 18:6a4db94011d3 1432
sahilmgandhi 18:6a4db94011d3 1433 #include "core_ca_mmu.h"
sahilmgandhi 18:6a4db94011d3 1434
sahilmgandhi 18:6a4db94011d3 1435 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
sahilmgandhi 18:6a4db94011d3 1436
sahilmgandhi 18:6a4db94011d3 1437 #error TASKING Compiler support not implemented for Cortex-A
sahilmgandhi 18:6a4db94011d3 1438
sahilmgandhi 18:6a4db94011d3 1439 #endif
sahilmgandhi 18:6a4db94011d3 1440
sahilmgandhi 18:6a4db94011d3 1441 /*@} end of CMSIS_Core_RegAccFunctions */
sahilmgandhi 18:6a4db94011d3 1442
sahilmgandhi 18:6a4db94011d3 1443
sahilmgandhi 18:6a4db94011d3 1444 #endif /* __CORE_CAFUNC_H__ */