MacroRat
Mouse code for the MacroRat
mbed-dev/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_idac.h@18:6a4db94011d3, 2017-05-14 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sun May 14 23:18:57 2017 +0000
- Revision:
- 18:6a4db94011d3
Publishing again
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| sahilmgandhi | 18:6a4db94011d3 | 1 | /**************************************************************************//** |
| sahilmgandhi | 18:6a4db94011d3 | 2 | * @file efr32mg1p_idac.h |
| sahilmgandhi | 18:6a4db94011d3 | 3 | * @brief EFR32MG1P_IDAC register and bit field definitions |
| sahilmgandhi | 18:6a4db94011d3 | 4 | * @version 5.1.2 |
| sahilmgandhi | 18:6a4db94011d3 | 5 | ****************************************************************************** |
| sahilmgandhi | 18:6a4db94011d3 | 6 | * @section License |
| sahilmgandhi | 18:6a4db94011d3 | 7 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| sahilmgandhi | 18:6a4db94011d3 | 8 | ****************************************************************************** |
| sahilmgandhi | 18:6a4db94011d3 | 9 | * |
| sahilmgandhi | 18:6a4db94011d3 | 10 | * Permission is granted to anyone to use this software for any purpose, |
| sahilmgandhi | 18:6a4db94011d3 | 11 | * including commercial applications, and to alter it and redistribute it |
| sahilmgandhi | 18:6a4db94011d3 | 12 | * freely, subject to the following restrictions: |
| sahilmgandhi | 18:6a4db94011d3 | 13 | * |
| sahilmgandhi | 18:6a4db94011d3 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| sahilmgandhi | 18:6a4db94011d3 | 15 | * claim that you wrote the original software.@n |
| sahilmgandhi | 18:6a4db94011d3 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| sahilmgandhi | 18:6a4db94011d3 | 17 | * misrepresented as being the original software.@n |
| sahilmgandhi | 18:6a4db94011d3 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| sahilmgandhi | 18:6a4db94011d3 | 19 | * |
| sahilmgandhi | 18:6a4db94011d3 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| sahilmgandhi | 18:6a4db94011d3 | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| sahilmgandhi | 18:6a4db94011d3 | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| sahilmgandhi | 18:6a4db94011d3 | 23 | * kind, including, but not limited to, any implied warranties of |
| sahilmgandhi | 18:6a4db94011d3 | 24 | * merchantability or fitness for any particular purpose or warranties against |
| sahilmgandhi | 18:6a4db94011d3 | 25 | * infringement of any proprietary rights of a third party. |
| sahilmgandhi | 18:6a4db94011d3 | 26 | * |
| sahilmgandhi | 18:6a4db94011d3 | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| sahilmgandhi | 18:6a4db94011d3 | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| sahilmgandhi | 18:6a4db94011d3 | 29 | * any third party, arising from your use of this Software. |
| sahilmgandhi | 18:6a4db94011d3 | 30 | * |
| sahilmgandhi | 18:6a4db94011d3 | 31 | *****************************************************************************/ |
| sahilmgandhi | 18:6a4db94011d3 | 32 | /**************************************************************************//** |
| sahilmgandhi | 18:6a4db94011d3 | 33 | * @addtogroup Parts |
| sahilmgandhi | 18:6a4db94011d3 | 34 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 35 | ******************************************************************************/ |
| sahilmgandhi | 18:6a4db94011d3 | 36 | /**************************************************************************//** |
| sahilmgandhi | 18:6a4db94011d3 | 37 | * @defgroup EFR32MG1P_IDAC |
| sahilmgandhi | 18:6a4db94011d3 | 38 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 39 | * @brief EFR32MG1P_IDAC Register Declaration |
| sahilmgandhi | 18:6a4db94011d3 | 40 | *****************************************************************************/ |
| sahilmgandhi | 18:6a4db94011d3 | 41 | typedef struct |
| sahilmgandhi | 18:6a4db94011d3 | 42 | { |
| sahilmgandhi | 18:6a4db94011d3 | 43 | __IOM uint32_t CTRL; /**< Control Register */ |
| sahilmgandhi | 18:6a4db94011d3 | 44 | __IOM uint32_t CURPROG; /**< Current Programming Register */ |
| sahilmgandhi | 18:6a4db94011d3 | 45 | uint32_t RESERVED0[1]; /**< Reserved for future use **/ |
| sahilmgandhi | 18:6a4db94011d3 | 46 | __IOM uint32_t DUTYCONFIG; /**< Duty Cycle Configuration Register */ |
| sahilmgandhi | 18:6a4db94011d3 | 47 | |
| sahilmgandhi | 18:6a4db94011d3 | 48 | uint32_t RESERVED1[2]; /**< Reserved for future use **/ |
| sahilmgandhi | 18:6a4db94011d3 | 49 | __IM uint32_t STATUS; /**< Status Register */ |
| sahilmgandhi | 18:6a4db94011d3 | 50 | uint32_t RESERVED2[1]; /**< Reserved for future use **/ |
| sahilmgandhi | 18:6a4db94011d3 | 51 | __IM uint32_t IF; /**< Interrupt Flag Register */ |
| sahilmgandhi | 18:6a4db94011d3 | 52 | __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ |
| sahilmgandhi | 18:6a4db94011d3 | 53 | __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| sahilmgandhi | 18:6a4db94011d3 | 54 | __IOM uint32_t IEN; /**< Interrupt Enable Register */ |
| sahilmgandhi | 18:6a4db94011d3 | 55 | uint32_t RESERVED3[1]; /**< Reserved for future use **/ |
| sahilmgandhi | 18:6a4db94011d3 | 56 | __IM uint32_t APORTREQ; /**< APORT Request Status Register */ |
| sahilmgandhi | 18:6a4db94011d3 | 57 | __IM uint32_t APORTCONFLICT; /**< APORT Request Status Register */ |
| sahilmgandhi | 18:6a4db94011d3 | 58 | } IDAC_TypeDef; /** @} */ |
| sahilmgandhi | 18:6a4db94011d3 | 59 | |
| sahilmgandhi | 18:6a4db94011d3 | 60 | /**************************************************************************//** |
| sahilmgandhi | 18:6a4db94011d3 | 61 | * @defgroup EFR32MG1P_IDAC_BitFields |
| sahilmgandhi | 18:6a4db94011d3 | 62 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 63 | *****************************************************************************/ |
| sahilmgandhi | 18:6a4db94011d3 | 64 | |
| sahilmgandhi | 18:6a4db94011d3 | 65 | /* Bit fields for IDAC CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 66 | #define _IDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 67 | #define _IDAC_CTRL_MASK 0x00F17FFFUL /**< Mask for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 68 | #define IDAC_CTRL_EN (0x1UL << 0) /**< Current DAC Enable */ |
| sahilmgandhi | 18:6a4db94011d3 | 69 | #define _IDAC_CTRL_EN_SHIFT 0 /**< Shift value for IDAC_EN */ |
| sahilmgandhi | 18:6a4db94011d3 | 70 | #define _IDAC_CTRL_EN_MASK 0x1UL /**< Bit mask for IDAC_EN */ |
| sahilmgandhi | 18:6a4db94011d3 | 71 | #define _IDAC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 72 | #define IDAC_CTRL_EN_DEFAULT (_IDAC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 73 | #define IDAC_CTRL_CURSINK (0x1UL << 1) /**< Current Sink Enable */ |
| sahilmgandhi | 18:6a4db94011d3 | 74 | #define _IDAC_CTRL_CURSINK_SHIFT 1 /**< Shift value for IDAC_CURSINK */ |
| sahilmgandhi | 18:6a4db94011d3 | 75 | #define _IDAC_CTRL_CURSINK_MASK 0x2UL /**< Bit mask for IDAC_CURSINK */ |
| sahilmgandhi | 18:6a4db94011d3 | 76 | #define _IDAC_CTRL_CURSINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 77 | #define IDAC_CTRL_CURSINK_DEFAULT (_IDAC_CTRL_CURSINK_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 78 | #define IDAC_CTRL_MINOUTTRANS (0x1UL << 2) /**< Minimum Output Transition Enable */ |
| sahilmgandhi | 18:6a4db94011d3 | 79 | #define _IDAC_CTRL_MINOUTTRANS_SHIFT 2 /**< Shift value for IDAC_MINOUTTRANS */ |
| sahilmgandhi | 18:6a4db94011d3 | 80 | #define _IDAC_CTRL_MINOUTTRANS_MASK 0x4UL /**< Bit mask for IDAC_MINOUTTRANS */ |
| sahilmgandhi | 18:6a4db94011d3 | 81 | #define _IDAC_CTRL_MINOUTTRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 82 | #define IDAC_CTRL_MINOUTTRANS_DEFAULT (_IDAC_CTRL_MINOUTTRANS_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 83 | #define IDAC_CTRL_APORTOUTEN (0x1UL << 3) /**< APORT Output Enable */ |
| sahilmgandhi | 18:6a4db94011d3 | 84 | #define _IDAC_CTRL_APORTOUTEN_SHIFT 3 /**< Shift value for IDAC_APORTOUTEN */ |
| sahilmgandhi | 18:6a4db94011d3 | 85 | #define _IDAC_CTRL_APORTOUTEN_MASK 0x8UL /**< Bit mask for IDAC_APORTOUTEN */ |
| sahilmgandhi | 18:6a4db94011d3 | 86 | #define _IDAC_CTRL_APORTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 87 | #define IDAC_CTRL_APORTOUTEN_DEFAULT (_IDAC_CTRL_APORTOUTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 88 | #define _IDAC_CTRL_APORTOUTSEL_SHIFT 4 /**< Shift value for IDAC_APORTOUTSEL */ |
| sahilmgandhi | 18:6a4db94011d3 | 89 | #define _IDAC_CTRL_APORTOUTSEL_MASK 0xFF0UL /**< Bit mask for IDAC_APORTOUTSEL */ |
| sahilmgandhi | 18:6a4db94011d3 | 90 | #define _IDAC_CTRL_APORTOUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 91 | #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 92 | #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 93 | #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 94 | #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 95 | #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 96 | #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 97 | #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 98 | #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 99 | #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 100 | #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 101 | #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 102 | #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 103 | #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 104 | #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 105 | #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 106 | #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 107 | #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 108 | #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 109 | #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 110 | #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 111 | #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 112 | #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 113 | #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 114 | #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 115 | #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 116 | #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 117 | #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 118 | #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 119 | #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 120 | #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 121 | #define _IDAC_CTRL_APORTOUTSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 122 | #define _IDAC_CTRL_APORTOUTSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 123 | #define IDAC_CTRL_APORTOUTSEL_DEFAULT (_IDAC_CTRL_APORTOUTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 124 | #define IDAC_CTRL_APORTOUTSEL_APORT1XCH0 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH0 << 4) /**< Shifted mode APORT1XCH0 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 125 | #define IDAC_CTRL_APORTOUTSEL_APORT1YCH1 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH1 << 4) /**< Shifted mode APORT1YCH1 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 126 | #define IDAC_CTRL_APORTOUTSEL_APORT1XCH2 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH2 << 4) /**< Shifted mode APORT1XCH2 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 127 | #define IDAC_CTRL_APORTOUTSEL_APORT1YCH3 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH3 << 4) /**< Shifted mode APORT1YCH3 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 128 | #define IDAC_CTRL_APORTOUTSEL_APORT1XCH4 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH4 << 4) /**< Shifted mode APORT1XCH4 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 129 | #define IDAC_CTRL_APORTOUTSEL_APORT1YCH5 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH5 << 4) /**< Shifted mode APORT1YCH5 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 130 | #define IDAC_CTRL_APORTOUTSEL_APORT1XCH6 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH6 << 4) /**< Shifted mode APORT1XCH6 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 131 | #define IDAC_CTRL_APORTOUTSEL_APORT1YCH7 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH7 << 4) /**< Shifted mode APORT1YCH7 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 132 | #define IDAC_CTRL_APORTOUTSEL_APORT1XCH8 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH8 << 4) /**< Shifted mode APORT1XCH8 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 133 | #define IDAC_CTRL_APORTOUTSEL_APORT1YCH9 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH9 << 4) /**< Shifted mode APORT1YCH9 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 134 | #define IDAC_CTRL_APORTOUTSEL_APORT1XCH10 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH10 << 4) /**< Shifted mode APORT1XCH10 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 135 | #define IDAC_CTRL_APORTOUTSEL_APORT1YCH11 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH11 << 4) /**< Shifted mode APORT1YCH11 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 136 | #define IDAC_CTRL_APORTOUTSEL_APORT1XCH12 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH12 << 4) /**< Shifted mode APORT1XCH12 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 137 | #define IDAC_CTRL_APORTOUTSEL_APORT1YCH13 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH13 << 4) /**< Shifted mode APORT1YCH13 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 138 | #define IDAC_CTRL_APORTOUTSEL_APORT1XCH14 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH14 << 4) /**< Shifted mode APORT1XCH14 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 139 | #define IDAC_CTRL_APORTOUTSEL_APORT1YCH15 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH15 << 4) /**< Shifted mode APORT1YCH15 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 140 | #define IDAC_CTRL_APORTOUTSEL_APORT1XCH16 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH16 << 4) /**< Shifted mode APORT1XCH16 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 141 | #define IDAC_CTRL_APORTOUTSEL_APORT1YCH17 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH17 << 4) /**< Shifted mode APORT1YCH17 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 142 | #define IDAC_CTRL_APORTOUTSEL_APORT1XCH18 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH18 << 4) /**< Shifted mode APORT1XCH18 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 143 | #define IDAC_CTRL_APORTOUTSEL_APORT1YCH19 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH19 << 4) /**< Shifted mode APORT1YCH19 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 144 | #define IDAC_CTRL_APORTOUTSEL_APORT1XCH20 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH20 << 4) /**< Shifted mode APORT1XCH20 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 145 | #define IDAC_CTRL_APORTOUTSEL_APORT1YCH21 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH21 << 4) /**< Shifted mode APORT1YCH21 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 146 | #define IDAC_CTRL_APORTOUTSEL_APORT1XCH22 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH22 << 4) /**< Shifted mode APORT1XCH22 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 147 | #define IDAC_CTRL_APORTOUTSEL_APORT1YCH23 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH23 << 4) /**< Shifted mode APORT1YCH23 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 148 | #define IDAC_CTRL_APORTOUTSEL_APORT1XCH24 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH24 << 4) /**< Shifted mode APORT1XCH24 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 149 | #define IDAC_CTRL_APORTOUTSEL_APORT1YCH25 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH25 << 4) /**< Shifted mode APORT1YCH25 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 150 | #define IDAC_CTRL_APORTOUTSEL_APORT1XCH26 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH26 << 4) /**< Shifted mode APORT1XCH26 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 151 | #define IDAC_CTRL_APORTOUTSEL_APORT1YCH27 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH27 << 4) /**< Shifted mode APORT1YCH27 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 152 | #define IDAC_CTRL_APORTOUTSEL_APORT1XCH28 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH28 << 4) /**< Shifted mode APORT1XCH28 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 153 | #define IDAC_CTRL_APORTOUTSEL_APORT1YCH29 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH29 << 4) /**< Shifted mode APORT1YCH29 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 154 | #define IDAC_CTRL_APORTOUTSEL_APORT1XCH30 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH30 << 4) /**< Shifted mode APORT1XCH30 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 155 | #define IDAC_CTRL_APORTOUTSEL_APORT1YCH31 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH31 << 4) /**< Shifted mode APORT1YCH31 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 156 | #define IDAC_CTRL_PWRSEL (0x1UL << 12) /**< Power Select */ |
| sahilmgandhi | 18:6a4db94011d3 | 157 | #define _IDAC_CTRL_PWRSEL_SHIFT 12 /**< Shift value for IDAC_PWRSEL */ |
| sahilmgandhi | 18:6a4db94011d3 | 158 | #define _IDAC_CTRL_PWRSEL_MASK 0x1000UL /**< Bit mask for IDAC_PWRSEL */ |
| sahilmgandhi | 18:6a4db94011d3 | 159 | #define _IDAC_CTRL_PWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 160 | #define _IDAC_CTRL_PWRSEL_ANA 0x00000000UL /**< Mode ANA for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 161 | #define _IDAC_CTRL_PWRSEL_IO 0x00000001UL /**< Mode IO for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 162 | #define IDAC_CTRL_PWRSEL_DEFAULT (_IDAC_CTRL_PWRSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 163 | #define IDAC_CTRL_PWRSEL_ANA (_IDAC_CTRL_PWRSEL_ANA << 12) /**< Shifted mode ANA for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 164 | #define IDAC_CTRL_PWRSEL_IO (_IDAC_CTRL_PWRSEL_IO << 12) /**< Shifted mode IO for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 165 | #define IDAC_CTRL_EM2DELAY (0x1UL << 13) /**< EM2 Delay */ |
| sahilmgandhi | 18:6a4db94011d3 | 166 | #define _IDAC_CTRL_EM2DELAY_SHIFT 13 /**< Shift value for IDAC_EM2DELAY */ |
| sahilmgandhi | 18:6a4db94011d3 | 167 | #define _IDAC_CTRL_EM2DELAY_MASK 0x2000UL /**< Bit mask for IDAC_EM2DELAY */ |
| sahilmgandhi | 18:6a4db94011d3 | 168 | #define _IDAC_CTRL_EM2DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 169 | #define IDAC_CTRL_EM2DELAY_DEFAULT (_IDAC_CTRL_EM2DELAY_DEFAULT << 13) /**< Shifted mode DEFAULT for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 170 | #define IDAC_CTRL_APORTMASTERDIS (0x1UL << 14) /**< APORT Bus Master Disable */ |
| sahilmgandhi | 18:6a4db94011d3 | 171 | #define _IDAC_CTRL_APORTMASTERDIS_SHIFT 14 /**< Shift value for IDAC_APORTMASTERDIS */ |
| sahilmgandhi | 18:6a4db94011d3 | 172 | #define _IDAC_CTRL_APORTMASTERDIS_MASK 0x4000UL /**< Bit mask for IDAC_APORTMASTERDIS */ |
| sahilmgandhi | 18:6a4db94011d3 | 173 | #define _IDAC_CTRL_APORTMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 174 | #define IDAC_CTRL_APORTMASTERDIS_DEFAULT (_IDAC_CTRL_APORTMASTERDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 175 | #define IDAC_CTRL_APORTOUTENPRS (0x1UL << 16) /**< PRS Controlled APORT Output Enable */ |
| sahilmgandhi | 18:6a4db94011d3 | 176 | #define _IDAC_CTRL_APORTOUTENPRS_SHIFT 16 /**< Shift value for IDAC_APORTOUTENPRS */ |
| sahilmgandhi | 18:6a4db94011d3 | 177 | #define _IDAC_CTRL_APORTOUTENPRS_MASK 0x10000UL /**< Bit mask for IDAC_APORTOUTENPRS */ |
| sahilmgandhi | 18:6a4db94011d3 | 178 | #define _IDAC_CTRL_APORTOUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 179 | #define IDAC_CTRL_APORTOUTENPRS_DEFAULT (_IDAC_CTRL_APORTOUTENPRS_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 180 | #define _IDAC_CTRL_PRSSEL_SHIFT 20 /**< Shift value for IDAC_PRSSEL */ |
| sahilmgandhi | 18:6a4db94011d3 | 181 | #define _IDAC_CTRL_PRSSEL_MASK 0xF00000UL /**< Bit mask for IDAC_PRSSEL */ |
| sahilmgandhi | 18:6a4db94011d3 | 182 | #define _IDAC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 183 | #define _IDAC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 184 | #define _IDAC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 185 | #define _IDAC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 186 | #define _IDAC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 187 | #define _IDAC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 188 | #define _IDAC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 189 | #define _IDAC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 190 | #define _IDAC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 191 | #define _IDAC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 192 | #define _IDAC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 193 | #define _IDAC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 194 | #define _IDAC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 195 | #define IDAC_CTRL_PRSSEL_DEFAULT (_IDAC_CTRL_PRSSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 196 | #define IDAC_CTRL_PRSSEL_PRSCH0 (_IDAC_CTRL_PRSSEL_PRSCH0 << 20) /**< Shifted mode PRSCH0 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 197 | #define IDAC_CTRL_PRSSEL_PRSCH1 (_IDAC_CTRL_PRSSEL_PRSCH1 << 20) /**< Shifted mode PRSCH1 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 198 | #define IDAC_CTRL_PRSSEL_PRSCH2 (_IDAC_CTRL_PRSSEL_PRSCH2 << 20) /**< Shifted mode PRSCH2 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 199 | #define IDAC_CTRL_PRSSEL_PRSCH3 (_IDAC_CTRL_PRSSEL_PRSCH3 << 20) /**< Shifted mode PRSCH3 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 200 | #define IDAC_CTRL_PRSSEL_PRSCH4 (_IDAC_CTRL_PRSSEL_PRSCH4 << 20) /**< Shifted mode PRSCH4 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 201 | #define IDAC_CTRL_PRSSEL_PRSCH5 (_IDAC_CTRL_PRSSEL_PRSCH5 << 20) /**< Shifted mode PRSCH5 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 202 | #define IDAC_CTRL_PRSSEL_PRSCH6 (_IDAC_CTRL_PRSSEL_PRSCH6 << 20) /**< Shifted mode PRSCH6 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 203 | #define IDAC_CTRL_PRSSEL_PRSCH7 (_IDAC_CTRL_PRSSEL_PRSCH7 << 20) /**< Shifted mode PRSCH7 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 204 | #define IDAC_CTRL_PRSSEL_PRSCH8 (_IDAC_CTRL_PRSSEL_PRSCH8 << 20) /**< Shifted mode PRSCH8 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 205 | #define IDAC_CTRL_PRSSEL_PRSCH9 (_IDAC_CTRL_PRSSEL_PRSCH9 << 20) /**< Shifted mode PRSCH9 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 206 | #define IDAC_CTRL_PRSSEL_PRSCH10 (_IDAC_CTRL_PRSSEL_PRSCH10 << 20) /**< Shifted mode PRSCH10 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 207 | #define IDAC_CTRL_PRSSEL_PRSCH11 (_IDAC_CTRL_PRSSEL_PRSCH11 << 20) /**< Shifted mode PRSCH11 for IDAC_CTRL */ |
| sahilmgandhi | 18:6a4db94011d3 | 208 | |
| sahilmgandhi | 18:6a4db94011d3 | 209 | /* Bit fields for IDAC CURPROG */ |
| sahilmgandhi | 18:6a4db94011d3 | 210 | #define _IDAC_CURPROG_RESETVALUE 0x009B0000UL /**< Default value for IDAC_CURPROG */ |
| sahilmgandhi | 18:6a4db94011d3 | 211 | #define _IDAC_CURPROG_MASK 0x00FF1F03UL /**< Mask for IDAC_CURPROG */ |
| sahilmgandhi | 18:6a4db94011d3 | 212 | #define _IDAC_CURPROG_RANGESEL_SHIFT 0 /**< Shift value for IDAC_RANGESEL */ |
| sahilmgandhi | 18:6a4db94011d3 | 213 | #define _IDAC_CURPROG_RANGESEL_MASK 0x3UL /**< Bit mask for IDAC_RANGESEL */ |
| sahilmgandhi | 18:6a4db94011d3 | 214 | #define _IDAC_CURPROG_RANGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */ |
| sahilmgandhi | 18:6a4db94011d3 | 215 | #define _IDAC_CURPROG_RANGESEL_RANGE0 0x00000000UL /**< Mode RANGE0 for IDAC_CURPROG */ |
| sahilmgandhi | 18:6a4db94011d3 | 216 | #define _IDAC_CURPROG_RANGESEL_RANGE1 0x00000001UL /**< Mode RANGE1 for IDAC_CURPROG */ |
| sahilmgandhi | 18:6a4db94011d3 | 217 | #define _IDAC_CURPROG_RANGESEL_RANGE2 0x00000002UL /**< Mode RANGE2 for IDAC_CURPROG */ |
| sahilmgandhi | 18:6a4db94011d3 | 218 | #define _IDAC_CURPROG_RANGESEL_RANGE3 0x00000003UL /**< Mode RANGE3 for IDAC_CURPROG */ |
| sahilmgandhi | 18:6a4db94011d3 | 219 | #define IDAC_CURPROG_RANGESEL_DEFAULT (_IDAC_CURPROG_RANGESEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CURPROG */ |
| sahilmgandhi | 18:6a4db94011d3 | 220 | #define IDAC_CURPROG_RANGESEL_RANGE0 (_IDAC_CURPROG_RANGESEL_RANGE0 << 0) /**< Shifted mode RANGE0 for IDAC_CURPROG */ |
| sahilmgandhi | 18:6a4db94011d3 | 221 | #define IDAC_CURPROG_RANGESEL_RANGE1 (_IDAC_CURPROG_RANGESEL_RANGE1 << 0) /**< Shifted mode RANGE1 for IDAC_CURPROG */ |
| sahilmgandhi | 18:6a4db94011d3 | 222 | #define IDAC_CURPROG_RANGESEL_RANGE2 (_IDAC_CURPROG_RANGESEL_RANGE2 << 0) /**< Shifted mode RANGE2 for IDAC_CURPROG */ |
| sahilmgandhi | 18:6a4db94011d3 | 223 | #define IDAC_CURPROG_RANGESEL_RANGE3 (_IDAC_CURPROG_RANGESEL_RANGE3 << 0) /**< Shifted mode RANGE3 for IDAC_CURPROG */ |
| sahilmgandhi | 18:6a4db94011d3 | 224 | #define _IDAC_CURPROG_STEPSEL_SHIFT 8 /**< Shift value for IDAC_STEPSEL */ |
| sahilmgandhi | 18:6a4db94011d3 | 225 | #define _IDAC_CURPROG_STEPSEL_MASK 0x1F00UL /**< Bit mask for IDAC_STEPSEL */ |
| sahilmgandhi | 18:6a4db94011d3 | 226 | #define _IDAC_CURPROG_STEPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */ |
| sahilmgandhi | 18:6a4db94011d3 | 227 | #define IDAC_CURPROG_STEPSEL_DEFAULT (_IDAC_CURPROG_STEPSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IDAC_CURPROG */ |
| sahilmgandhi | 18:6a4db94011d3 | 228 | #define _IDAC_CURPROG_TUNING_SHIFT 16 /**< Shift value for IDAC_TUNING */ |
| sahilmgandhi | 18:6a4db94011d3 | 229 | #define _IDAC_CURPROG_TUNING_MASK 0xFF0000UL /**< Bit mask for IDAC_TUNING */ |
| sahilmgandhi | 18:6a4db94011d3 | 230 | #define _IDAC_CURPROG_TUNING_DEFAULT 0x0000009BUL /**< Mode DEFAULT for IDAC_CURPROG */ |
| sahilmgandhi | 18:6a4db94011d3 | 231 | #define IDAC_CURPROG_TUNING_DEFAULT (_IDAC_CURPROG_TUNING_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CURPROG */ |
| sahilmgandhi | 18:6a4db94011d3 | 232 | |
| sahilmgandhi | 18:6a4db94011d3 | 233 | /* Bit fields for IDAC DUTYCONFIG */ |
| sahilmgandhi | 18:6a4db94011d3 | 234 | #define _IDAC_DUTYCONFIG_RESETVALUE 0x00000000UL /**< Default value for IDAC_DUTYCONFIG */ |
| sahilmgandhi | 18:6a4db94011d3 | 235 | #define _IDAC_DUTYCONFIG_MASK 0x00000002UL /**< Mask for IDAC_DUTYCONFIG */ |
| sahilmgandhi | 18:6a4db94011d3 | 236 | #define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS (0x1UL << 1) /**< Duty Cycle Enable. */ |
| sahilmgandhi | 18:6a4db94011d3 | 237 | #define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_SHIFT 1 /**< Shift value for IDAC_EM2DUTYCYCLEDIS */ |
| sahilmgandhi | 18:6a4db94011d3 | 238 | #define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_MASK 0x2UL /**< Bit mask for IDAC_EM2DUTYCYCLEDIS */ |
| sahilmgandhi | 18:6a4db94011d3 | 239 | #define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_DUTYCONFIG */ |
| sahilmgandhi | 18:6a4db94011d3 | 240 | #define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT (_IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_DUTYCONFIG */ |
| sahilmgandhi | 18:6a4db94011d3 | 241 | |
| sahilmgandhi | 18:6a4db94011d3 | 242 | /* Bit fields for IDAC STATUS */ |
| sahilmgandhi | 18:6a4db94011d3 | 243 | #define _IDAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IDAC_STATUS */ |
| sahilmgandhi | 18:6a4db94011d3 | 244 | #define _IDAC_STATUS_MASK 0x00000002UL /**< Mask for IDAC_STATUS */ |
| sahilmgandhi | 18:6a4db94011d3 | 245 | #define IDAC_STATUS_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Output */ |
| sahilmgandhi | 18:6a4db94011d3 | 246 | #define _IDAC_STATUS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ |
| sahilmgandhi | 18:6a4db94011d3 | 247 | #define _IDAC_STATUS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ |
| sahilmgandhi | 18:6a4db94011d3 | 248 | #define _IDAC_STATUS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_STATUS */ |
| sahilmgandhi | 18:6a4db94011d3 | 249 | #define IDAC_STATUS_APORTCONFLICT_DEFAULT (_IDAC_STATUS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_STATUS */ |
| sahilmgandhi | 18:6a4db94011d3 | 250 | |
| sahilmgandhi | 18:6a4db94011d3 | 251 | /* Bit fields for IDAC IF */ |
| sahilmgandhi | 18:6a4db94011d3 | 252 | #define _IDAC_IF_RESETVALUE 0x00000000UL /**< Default value for IDAC_IF */ |
| sahilmgandhi | 18:6a4db94011d3 | 253 | #define _IDAC_IF_MASK 0x00000002UL /**< Mask for IDAC_IF */ |
| sahilmgandhi | 18:6a4db94011d3 | 254 | #define IDAC_IF_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Interrupt Flag */ |
| sahilmgandhi | 18:6a4db94011d3 | 255 | #define _IDAC_IF_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ |
| sahilmgandhi | 18:6a4db94011d3 | 256 | #define _IDAC_IF_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ |
| sahilmgandhi | 18:6a4db94011d3 | 257 | #define _IDAC_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IF */ |
| sahilmgandhi | 18:6a4db94011d3 | 258 | #define IDAC_IF_APORTCONFLICT_DEFAULT (_IDAC_IF_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IF */ |
| sahilmgandhi | 18:6a4db94011d3 | 259 | |
| sahilmgandhi | 18:6a4db94011d3 | 260 | /* Bit fields for IDAC IFS */ |
| sahilmgandhi | 18:6a4db94011d3 | 261 | #define _IDAC_IFS_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFS */ |
| sahilmgandhi | 18:6a4db94011d3 | 262 | #define _IDAC_IFS_MASK 0x00000002UL /**< Mask for IDAC_IFS */ |
| sahilmgandhi | 18:6a4db94011d3 | 263 | #define IDAC_IFS_APORTCONFLICT (0x1UL << 1) /**< Set APORTCONFLICT Interrupt Flag */ |
| sahilmgandhi | 18:6a4db94011d3 | 264 | #define _IDAC_IFS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ |
| sahilmgandhi | 18:6a4db94011d3 | 265 | #define _IDAC_IFS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ |
| sahilmgandhi | 18:6a4db94011d3 | 266 | #define _IDAC_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */ |
| sahilmgandhi | 18:6a4db94011d3 | 267 | #define IDAC_IFS_APORTCONFLICT_DEFAULT (_IDAC_IFS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFS */ |
| sahilmgandhi | 18:6a4db94011d3 | 268 | |
| sahilmgandhi | 18:6a4db94011d3 | 269 | /* Bit fields for IDAC IFC */ |
| sahilmgandhi | 18:6a4db94011d3 | 270 | #define _IDAC_IFC_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFC */ |
| sahilmgandhi | 18:6a4db94011d3 | 271 | #define _IDAC_IFC_MASK 0x00000002UL /**< Mask for IDAC_IFC */ |
| sahilmgandhi | 18:6a4db94011d3 | 272 | #define IDAC_IFC_APORTCONFLICT (0x1UL << 1) /**< Clear APORTCONFLICT Interrupt Flag */ |
| sahilmgandhi | 18:6a4db94011d3 | 273 | #define _IDAC_IFC_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ |
| sahilmgandhi | 18:6a4db94011d3 | 274 | #define _IDAC_IFC_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ |
| sahilmgandhi | 18:6a4db94011d3 | 275 | #define _IDAC_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */ |
| sahilmgandhi | 18:6a4db94011d3 | 276 | #define IDAC_IFC_APORTCONFLICT_DEFAULT (_IDAC_IFC_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFC */ |
| sahilmgandhi | 18:6a4db94011d3 | 277 | |
| sahilmgandhi | 18:6a4db94011d3 | 278 | /* Bit fields for IDAC IEN */ |
| sahilmgandhi | 18:6a4db94011d3 | 279 | #define _IDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for IDAC_IEN */ |
| sahilmgandhi | 18:6a4db94011d3 | 280 | #define _IDAC_IEN_MASK 0x00000002UL /**< Mask for IDAC_IEN */ |
| sahilmgandhi | 18:6a4db94011d3 | 281 | #define IDAC_IEN_APORTCONFLICT (0x1UL << 1) /**< APORTCONFLICT Interrupt Enable */ |
| sahilmgandhi | 18:6a4db94011d3 | 282 | #define _IDAC_IEN_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ |
| sahilmgandhi | 18:6a4db94011d3 | 283 | #define _IDAC_IEN_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ |
| sahilmgandhi | 18:6a4db94011d3 | 284 | #define _IDAC_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */ |
| sahilmgandhi | 18:6a4db94011d3 | 285 | #define IDAC_IEN_APORTCONFLICT_DEFAULT (_IDAC_IEN_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IEN */ |
| sahilmgandhi | 18:6a4db94011d3 | 286 | |
| sahilmgandhi | 18:6a4db94011d3 | 287 | /* Bit fields for IDAC APORTREQ */ |
| sahilmgandhi | 18:6a4db94011d3 | 288 | #define _IDAC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTREQ */ |
| sahilmgandhi | 18:6a4db94011d3 | 289 | #define _IDAC_APORTREQ_MASK 0x0000000CUL /**< Mask for IDAC_APORTREQ */ |
| sahilmgandhi | 18:6a4db94011d3 | 290 | #define IDAC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the APORT bus connected to APORT1X is requested */ |
| sahilmgandhi | 18:6a4db94011d3 | 291 | #define _IDAC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for IDAC_APORT1XREQ */ |
| sahilmgandhi | 18:6a4db94011d3 | 292 | #define _IDAC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for IDAC_APORT1XREQ */ |
| sahilmgandhi | 18:6a4db94011d3 | 293 | #define _IDAC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */ |
| sahilmgandhi | 18:6a4db94011d3 | 294 | #define IDAC_APORTREQ_APORT1XREQ_DEFAULT (_IDAC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTREQ */ |
| sahilmgandhi | 18:6a4db94011d3 | 295 | #define IDAC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is requested */ |
| sahilmgandhi | 18:6a4db94011d3 | 296 | #define _IDAC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for IDAC_APORT1YREQ */ |
| sahilmgandhi | 18:6a4db94011d3 | 297 | #define _IDAC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for IDAC_APORT1YREQ */ |
| sahilmgandhi | 18:6a4db94011d3 | 298 | #define _IDAC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */ |
| sahilmgandhi | 18:6a4db94011d3 | 299 | #define IDAC_APORTREQ_APORT1YREQ_DEFAULT (_IDAC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTREQ */ |
| sahilmgandhi | 18:6a4db94011d3 | 300 | |
| sahilmgandhi | 18:6a4db94011d3 | 301 | /* Bit fields for IDAC APORTCONFLICT */ |
| sahilmgandhi | 18:6a4db94011d3 | 302 | #define _IDAC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTCONFLICT */ |
| sahilmgandhi | 18:6a4db94011d3 | 303 | #define _IDAC_APORTCONFLICT_MASK 0x0000000CUL /**< Mask for IDAC_APORTCONFLICT */ |
| sahilmgandhi | 18:6a4db94011d3 | 304 | #define IDAC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ |
| sahilmgandhi | 18:6a4db94011d3 | 305 | #define _IDAC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for IDAC_APORT1XCONFLICT */ |
| sahilmgandhi | 18:6a4db94011d3 | 306 | #define _IDAC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for IDAC_APORT1XCONFLICT */ |
| sahilmgandhi | 18:6a4db94011d3 | 307 | #define _IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */ |
| sahilmgandhi | 18:6a4db94011d3 | 308 | #define IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */ |
| sahilmgandhi | 18:6a4db94011d3 | 309 | #define IDAC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is in conflict with another peripheral */ |
| sahilmgandhi | 18:6a4db94011d3 | 310 | #define _IDAC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for IDAC_APORT1YCONFLICT */ |
| sahilmgandhi | 18:6a4db94011d3 | 311 | #define _IDAC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for IDAC_APORT1YCONFLICT */ |
| sahilmgandhi | 18:6a4db94011d3 | 312 | #define _IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */ |
| sahilmgandhi | 18:6a4db94011d3 | 313 | #define IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */ |
| sahilmgandhi | 18:6a4db94011d3 | 314 | |
| sahilmgandhi | 18:6a4db94011d3 | 315 | /** @} End of group EFR32MG1P_IDAC */ |
| sahilmgandhi | 18:6a4db94011d3 | 316 | /** @} End of group Parts */ |
| sahilmgandhi | 18:6a4db94011d3 | 317 |