MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_i2c.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

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sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file efr32mg1p_i2c.h
sahilmgandhi 18:6a4db94011d3 3 * @brief EFR32MG1P_I2C register and bit field definitions
sahilmgandhi 18:6a4db94011d3 4 * @version 5.1.2
sahilmgandhi 18:6a4db94011d3 5 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 6 * @section License
sahilmgandhi 18:6a4db94011d3 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
sahilmgandhi 18:6a4db94011d3 8 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Permission is granted to anyone to use this software for any purpose,
sahilmgandhi 18:6a4db94011d3 11 * including commercial applications, and to alter it and redistribute it
sahilmgandhi 18:6a4db94011d3 12 * freely, subject to the following restrictions:
sahilmgandhi 18:6a4db94011d3 13 *
sahilmgandhi 18:6a4db94011d3 14 * 1. The origin of this software must not be misrepresented; you must not
sahilmgandhi 18:6a4db94011d3 15 * claim that you wrote the original software.@n
sahilmgandhi 18:6a4db94011d3 16 * 2. Altered source versions must be plainly marked as such, and must not be
sahilmgandhi 18:6a4db94011d3 17 * misrepresented as being the original software.@n
sahilmgandhi 18:6a4db94011d3 18 * 3. This notice may not be removed or altered from any source distribution.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
sahilmgandhi 18:6a4db94011d3 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
sahilmgandhi 18:6a4db94011d3 22 * providing the Software "AS IS", with no express or implied warranties of any
sahilmgandhi 18:6a4db94011d3 23 * kind, including, but not limited to, any implied warranties of
sahilmgandhi 18:6a4db94011d3 24 * merchantability or fitness for any particular purpose or warranties against
sahilmgandhi 18:6a4db94011d3 25 * infringement of any proprietary rights of a third party.
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
sahilmgandhi 18:6a4db94011d3 28 * incidental, or special damages, or any other relief, or for any claim by
sahilmgandhi 18:6a4db94011d3 29 * any third party, arising from your use of this Software.
sahilmgandhi 18:6a4db94011d3 30 *
sahilmgandhi 18:6a4db94011d3 31 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 32 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 33 * @addtogroup Parts
sahilmgandhi 18:6a4db94011d3 34 * @{
sahilmgandhi 18:6a4db94011d3 35 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 36 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 37 * @defgroup EFR32MG1P_I2C
sahilmgandhi 18:6a4db94011d3 38 * @{
sahilmgandhi 18:6a4db94011d3 39 * @brief EFR32MG1P_I2C Register Declaration
sahilmgandhi 18:6a4db94011d3 40 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 41 typedef struct
sahilmgandhi 18:6a4db94011d3 42 {
sahilmgandhi 18:6a4db94011d3 43 __IOM uint32_t CTRL; /**< Control Register */
sahilmgandhi 18:6a4db94011d3 44 __IOM uint32_t CMD; /**< Command Register */
sahilmgandhi 18:6a4db94011d3 45 __IM uint32_t STATE; /**< State Register */
sahilmgandhi 18:6a4db94011d3 46 __IM uint32_t STATUS; /**< Status Register */
sahilmgandhi 18:6a4db94011d3 47 __IOM uint32_t CLKDIV; /**< Clock Division Register */
sahilmgandhi 18:6a4db94011d3 48 __IOM uint32_t SADDR; /**< Slave Address Register */
sahilmgandhi 18:6a4db94011d3 49 __IOM uint32_t SADDRMASK; /**< Slave Address Mask Register */
sahilmgandhi 18:6a4db94011d3 50 __IM uint32_t RXDATA; /**< Receive Buffer Data Register */
sahilmgandhi 18:6a4db94011d3 51 __IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */
sahilmgandhi 18:6a4db94011d3 52 __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */
sahilmgandhi 18:6a4db94011d3 53 __IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */
sahilmgandhi 18:6a4db94011d3 54 __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */
sahilmgandhi 18:6a4db94011d3 55 __IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */
sahilmgandhi 18:6a4db94011d3 56 __IM uint32_t IF; /**< Interrupt Flag Register */
sahilmgandhi 18:6a4db94011d3 57 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
sahilmgandhi 18:6a4db94011d3 58 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
sahilmgandhi 18:6a4db94011d3 59 __IOM uint32_t IEN; /**< Interrupt Enable Register */
sahilmgandhi 18:6a4db94011d3 60 __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
sahilmgandhi 18:6a4db94011d3 61 __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
sahilmgandhi 18:6a4db94011d3 62 } I2C_TypeDef; /** @} */
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 65 * @defgroup EFR32MG1P_I2C_BitFields
sahilmgandhi 18:6a4db94011d3 66 * @{
sahilmgandhi 18:6a4db94011d3 67 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 68
sahilmgandhi 18:6a4db94011d3 69 /* Bit fields for I2C CTRL */
sahilmgandhi 18:6a4db94011d3 70 #define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 71 #define _I2C_CTRL_MASK 0x0007B3FFUL /**< Mask for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 72 #define I2C_CTRL_EN (0x1UL << 0) /**< I2C Enable */
sahilmgandhi 18:6a4db94011d3 73 #define _I2C_CTRL_EN_SHIFT 0 /**< Shift value for I2C_EN */
sahilmgandhi 18:6a4db94011d3 74 #define _I2C_CTRL_EN_MASK 0x1UL /**< Bit mask for I2C_EN */
sahilmgandhi 18:6a4db94011d3 75 #define _I2C_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 76 #define I2C_CTRL_EN_DEFAULT (_I2C_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 77 #define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Slave */
sahilmgandhi 18:6a4db94011d3 78 #define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */
sahilmgandhi 18:6a4db94011d3 79 #define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */
sahilmgandhi 18:6a4db94011d3 80 #define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 81 #define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 82 #define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */
sahilmgandhi 18:6a4db94011d3 83 #define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */
sahilmgandhi 18:6a4db94011d3 84 #define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */
sahilmgandhi 18:6a4db94011d3 85 #define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 86 #define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 87 #define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */
sahilmgandhi 18:6a4db94011d3 88 #define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */
sahilmgandhi 18:6a4db94011d3 89 #define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */
sahilmgandhi 18:6a4db94011d3 90 #define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 91 #define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 92 #define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */
sahilmgandhi 18:6a4db94011d3 93 #define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */
sahilmgandhi 18:6a4db94011d3 94 #define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */
sahilmgandhi 18:6a4db94011d3 95 #define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 96 #define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 97 #define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */
sahilmgandhi 18:6a4db94011d3 98 #define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */
sahilmgandhi 18:6a4db94011d3 99 #define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */
sahilmgandhi 18:6a4db94011d3 100 #define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 101 #define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 102 #define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */
sahilmgandhi 18:6a4db94011d3 103 #define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */
sahilmgandhi 18:6a4db94011d3 104 #define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */
sahilmgandhi 18:6a4db94011d3 105 #define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 106 #define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 107 #define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */
sahilmgandhi 18:6a4db94011d3 108 #define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */
sahilmgandhi 18:6a4db94011d3 109 #define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */
sahilmgandhi 18:6a4db94011d3 110 #define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 111 #define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 112 #define _I2C_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 113 #define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 114 #define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 115 #define I2C_CTRL_TXBIL_HALFFULL (_I2C_CTRL_TXBIL_HALFFULL << 7) /**< Shifted mode HALFFULL for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 116 #define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */
sahilmgandhi 18:6a4db94011d3 117 #define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */
sahilmgandhi 18:6a4db94011d3 118 #define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 119 #define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 120 #define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 121 #define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 122 #define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 123 #define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 124 #define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 125 #define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 126 #define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */
sahilmgandhi 18:6a4db94011d3 127 #define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */
sahilmgandhi 18:6a4db94011d3 128 #define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 129 #define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 130 #define _I2C_CTRL_BITO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 131 #define _I2C_CTRL_BITO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 132 #define _I2C_CTRL_BITO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 133 #define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 134 #define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 135 #define I2C_CTRL_BITO_40PCC (_I2C_CTRL_BITO_40PCC << 12) /**< Shifted mode 40PCC for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 136 #define I2C_CTRL_BITO_80PCC (_I2C_CTRL_BITO_80PCC << 12) /**< Shifted mode 80PCC for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 137 #define I2C_CTRL_BITO_160PCC (_I2C_CTRL_BITO_160PCC << 12) /**< Shifted mode 160PCC for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 138 #define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */
sahilmgandhi 18:6a4db94011d3 139 #define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */
sahilmgandhi 18:6a4db94011d3 140 #define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */
sahilmgandhi 18:6a4db94011d3 141 #define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 142 #define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 143 #define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */
sahilmgandhi 18:6a4db94011d3 144 #define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */
sahilmgandhi 18:6a4db94011d3 145 #define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 146 #define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 147 #define _I2C_CTRL_CLTO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 148 #define _I2C_CTRL_CLTO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 149 #define _I2C_CTRL_CLTO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 150 #define _I2C_CTRL_CLTO_320PCC 0x00000004UL /**< Mode 320PCC for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 151 #define _I2C_CTRL_CLTO_1024PCC 0x00000005UL /**< Mode 1024PCC for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 152 #define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 153 #define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 154 #define I2C_CTRL_CLTO_40PCC (_I2C_CTRL_CLTO_40PCC << 16) /**< Shifted mode 40PCC for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 155 #define I2C_CTRL_CLTO_80PCC (_I2C_CTRL_CLTO_80PCC << 16) /**< Shifted mode 80PCC for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 156 #define I2C_CTRL_CLTO_160PCC (_I2C_CTRL_CLTO_160PCC << 16) /**< Shifted mode 160PCC for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 157 #define I2C_CTRL_CLTO_320PCC (_I2C_CTRL_CLTO_320PCC << 16) /**< Shifted mode 320PCC for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 158 #define I2C_CTRL_CLTO_1024PCC (_I2C_CTRL_CLTO_1024PCC << 16) /**< Shifted mode 1024PCC for I2C_CTRL */
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 /* Bit fields for I2C CMD */
sahilmgandhi 18:6a4db94011d3 161 #define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */
sahilmgandhi 18:6a4db94011d3 162 #define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */
sahilmgandhi 18:6a4db94011d3 163 #define I2C_CMD_START (0x1UL << 0) /**< Send start condition */
sahilmgandhi 18:6a4db94011d3 164 #define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */
sahilmgandhi 18:6a4db94011d3 165 #define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */
sahilmgandhi 18:6a4db94011d3 166 #define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
sahilmgandhi 18:6a4db94011d3 167 #define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */
sahilmgandhi 18:6a4db94011d3 168 #define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */
sahilmgandhi 18:6a4db94011d3 169 #define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */
sahilmgandhi 18:6a4db94011d3 170 #define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */
sahilmgandhi 18:6a4db94011d3 171 #define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
sahilmgandhi 18:6a4db94011d3 172 #define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */
sahilmgandhi 18:6a4db94011d3 173 #define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */
sahilmgandhi 18:6a4db94011d3 174 #define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */
sahilmgandhi 18:6a4db94011d3 175 #define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */
sahilmgandhi 18:6a4db94011d3 176 #define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
sahilmgandhi 18:6a4db94011d3 177 #define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */
sahilmgandhi 18:6a4db94011d3 178 #define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */
sahilmgandhi 18:6a4db94011d3 179 #define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */
sahilmgandhi 18:6a4db94011d3 180 #define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */
sahilmgandhi 18:6a4db94011d3 181 #define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
sahilmgandhi 18:6a4db94011d3 182 #define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */
sahilmgandhi 18:6a4db94011d3 183 #define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */
sahilmgandhi 18:6a4db94011d3 184 #define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */
sahilmgandhi 18:6a4db94011d3 185 #define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */
sahilmgandhi 18:6a4db94011d3 186 #define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
sahilmgandhi 18:6a4db94011d3 187 #define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */
sahilmgandhi 18:6a4db94011d3 188 #define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */
sahilmgandhi 18:6a4db94011d3 189 #define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */
sahilmgandhi 18:6a4db94011d3 190 #define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */
sahilmgandhi 18:6a4db94011d3 191 #define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
sahilmgandhi 18:6a4db94011d3 192 #define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */
sahilmgandhi 18:6a4db94011d3 193 #define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */
sahilmgandhi 18:6a4db94011d3 194 #define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */
sahilmgandhi 18:6a4db94011d3 195 #define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */
sahilmgandhi 18:6a4db94011d3 196 #define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
sahilmgandhi 18:6a4db94011d3 197 #define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */
sahilmgandhi 18:6a4db94011d3 198 #define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */
sahilmgandhi 18:6a4db94011d3 199 #define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */
sahilmgandhi 18:6a4db94011d3 200 #define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */
sahilmgandhi 18:6a4db94011d3 201 #define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
sahilmgandhi 18:6a4db94011d3 202 #define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */
sahilmgandhi 18:6a4db94011d3 203
sahilmgandhi 18:6a4db94011d3 204 /* Bit fields for I2C STATE */
sahilmgandhi 18:6a4db94011d3 205 #define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 206 #define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 207 #define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */
sahilmgandhi 18:6a4db94011d3 208 #define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */
sahilmgandhi 18:6a4db94011d3 209 #define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */
sahilmgandhi 18:6a4db94011d3 210 #define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 211 #define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 212 #define I2C_STATE_MASTER (0x1UL << 1) /**< Master */
sahilmgandhi 18:6a4db94011d3 213 #define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */
sahilmgandhi 18:6a4db94011d3 214 #define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */
sahilmgandhi 18:6a4db94011d3 215 #define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 216 #define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 217 #define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */
sahilmgandhi 18:6a4db94011d3 218 #define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */
sahilmgandhi 18:6a4db94011d3 219 #define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */
sahilmgandhi 18:6a4db94011d3 220 #define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 221 #define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 222 #define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */
sahilmgandhi 18:6a4db94011d3 223 #define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */
sahilmgandhi 18:6a4db94011d3 224 #define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */
sahilmgandhi 18:6a4db94011d3 225 #define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 226 #define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 227 #define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */
sahilmgandhi 18:6a4db94011d3 228 #define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */
sahilmgandhi 18:6a4db94011d3 229 #define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */
sahilmgandhi 18:6a4db94011d3 230 #define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 231 #define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 232 #define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 233 #define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 234 #define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 235 #define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 236 #define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 237 #define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 238 #define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 239 #define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 240 #define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 241 #define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 242 #define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 243 #define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 244 #define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 245 #define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 246 #define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 247 #define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 248 #define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 249 #define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */
sahilmgandhi 18:6a4db94011d3 250
sahilmgandhi 18:6a4db94011d3 251 /* Bit fields for I2C STATUS */
sahilmgandhi 18:6a4db94011d3 252 #define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */
sahilmgandhi 18:6a4db94011d3 253 #define _I2C_STATUS_MASK 0x000003FFUL /**< Mask for I2C_STATUS */
sahilmgandhi 18:6a4db94011d3 254 #define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */
sahilmgandhi 18:6a4db94011d3 255 #define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */
sahilmgandhi 18:6a4db94011d3 256 #define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */
sahilmgandhi 18:6a4db94011d3 257 #define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
sahilmgandhi 18:6a4db94011d3 258 #define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */
sahilmgandhi 18:6a4db94011d3 259 #define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */
sahilmgandhi 18:6a4db94011d3 260 #define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */
sahilmgandhi 18:6a4db94011d3 261 #define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */
sahilmgandhi 18:6a4db94011d3 262 #define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
sahilmgandhi 18:6a4db94011d3 263 #define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */
sahilmgandhi 18:6a4db94011d3 264 #define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */
sahilmgandhi 18:6a4db94011d3 265 #define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */
sahilmgandhi 18:6a4db94011d3 266 #define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */
sahilmgandhi 18:6a4db94011d3 267 #define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
sahilmgandhi 18:6a4db94011d3 268 #define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */
sahilmgandhi 18:6a4db94011d3 269 #define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */
sahilmgandhi 18:6a4db94011d3 270 #define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */
sahilmgandhi 18:6a4db94011d3 271 #define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */
sahilmgandhi 18:6a4db94011d3 272 #define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
sahilmgandhi 18:6a4db94011d3 273 #define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */
sahilmgandhi 18:6a4db94011d3 274 #define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */
sahilmgandhi 18:6a4db94011d3 275 #define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */
sahilmgandhi 18:6a4db94011d3 276 #define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */
sahilmgandhi 18:6a4db94011d3 277 #define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
sahilmgandhi 18:6a4db94011d3 278 #define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */
sahilmgandhi 18:6a4db94011d3 279 #define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */
sahilmgandhi 18:6a4db94011d3 280 #define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */
sahilmgandhi 18:6a4db94011d3 281 #define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */
sahilmgandhi 18:6a4db94011d3 282 #define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
sahilmgandhi 18:6a4db94011d3 283 #define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */
sahilmgandhi 18:6a4db94011d3 284 #define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */
sahilmgandhi 18:6a4db94011d3 285 #define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */
sahilmgandhi 18:6a4db94011d3 286 #define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */
sahilmgandhi 18:6a4db94011d3 287 #define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
sahilmgandhi 18:6a4db94011d3 288 #define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */
sahilmgandhi 18:6a4db94011d3 289 #define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */
sahilmgandhi 18:6a4db94011d3 290 #define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */
sahilmgandhi 18:6a4db94011d3 291 #define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */
sahilmgandhi 18:6a4db94011d3 292 #define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */
sahilmgandhi 18:6a4db94011d3 293 #define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */
sahilmgandhi 18:6a4db94011d3 294 #define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */
sahilmgandhi 18:6a4db94011d3 295 #define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */
sahilmgandhi 18:6a4db94011d3 296 #define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */
sahilmgandhi 18:6a4db94011d3 297 #define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
sahilmgandhi 18:6a4db94011d3 298 #define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */
sahilmgandhi 18:6a4db94011d3 299 #define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */
sahilmgandhi 18:6a4db94011d3 300 #define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */
sahilmgandhi 18:6a4db94011d3 301 #define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */
sahilmgandhi 18:6a4db94011d3 302 #define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
sahilmgandhi 18:6a4db94011d3 303 #define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */
sahilmgandhi 18:6a4db94011d3 304
sahilmgandhi 18:6a4db94011d3 305 /* Bit fields for I2C CLKDIV */
sahilmgandhi 18:6a4db94011d3 306 #define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */
sahilmgandhi 18:6a4db94011d3 307 #define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */
sahilmgandhi 18:6a4db94011d3 308 #define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */
sahilmgandhi 18:6a4db94011d3 309 #define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */
sahilmgandhi 18:6a4db94011d3 310 #define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */
sahilmgandhi 18:6a4db94011d3 311 #define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */
sahilmgandhi 18:6a4db94011d3 312
sahilmgandhi 18:6a4db94011d3 313 /* Bit fields for I2C SADDR */
sahilmgandhi 18:6a4db94011d3 314 #define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */
sahilmgandhi 18:6a4db94011d3 315 #define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */
sahilmgandhi 18:6a4db94011d3 316 #define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */
sahilmgandhi 18:6a4db94011d3 317 #define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */
sahilmgandhi 18:6a4db94011d3 318 #define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */
sahilmgandhi 18:6a4db94011d3 319 #define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */
sahilmgandhi 18:6a4db94011d3 320
sahilmgandhi 18:6a4db94011d3 321 /* Bit fields for I2C SADDRMASK */
sahilmgandhi 18:6a4db94011d3 322 #define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */
sahilmgandhi 18:6a4db94011d3 323 #define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */
sahilmgandhi 18:6a4db94011d3 324 #define _I2C_SADDRMASK_MASK_SHIFT 1 /**< Shift value for I2C_MASK */
sahilmgandhi 18:6a4db94011d3 325 #define _I2C_SADDRMASK_MASK_MASK 0xFEUL /**< Bit mask for I2C_MASK */
sahilmgandhi 18:6a4db94011d3 326 #define _I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */
sahilmgandhi 18:6a4db94011d3 327 #define I2C_SADDRMASK_MASK_DEFAULT (_I2C_SADDRMASK_MASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */
sahilmgandhi 18:6a4db94011d3 328
sahilmgandhi 18:6a4db94011d3 329 /* Bit fields for I2C RXDATA */
sahilmgandhi 18:6a4db94011d3 330 #define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */
sahilmgandhi 18:6a4db94011d3 331 #define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */
sahilmgandhi 18:6a4db94011d3 332 #define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */
sahilmgandhi 18:6a4db94011d3 333 #define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */
sahilmgandhi 18:6a4db94011d3 334 #define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */
sahilmgandhi 18:6a4db94011d3 335 #define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */
sahilmgandhi 18:6a4db94011d3 336
sahilmgandhi 18:6a4db94011d3 337 /* Bit fields for I2C RXDOUBLE */
sahilmgandhi 18:6a4db94011d3 338 #define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */
sahilmgandhi 18:6a4db94011d3 339 #define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */
sahilmgandhi 18:6a4db94011d3 340 #define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */
sahilmgandhi 18:6a4db94011d3 341 #define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */
sahilmgandhi 18:6a4db94011d3 342 #define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */
sahilmgandhi 18:6a4db94011d3 343 #define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */
sahilmgandhi 18:6a4db94011d3 344 #define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */
sahilmgandhi 18:6a4db94011d3 345 #define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */
sahilmgandhi 18:6a4db94011d3 346 #define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */
sahilmgandhi 18:6a4db94011d3 347 #define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */
sahilmgandhi 18:6a4db94011d3 348
sahilmgandhi 18:6a4db94011d3 349 /* Bit fields for I2C RXDATAP */
sahilmgandhi 18:6a4db94011d3 350 #define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */
sahilmgandhi 18:6a4db94011d3 351 #define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */
sahilmgandhi 18:6a4db94011d3 352 #define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */
sahilmgandhi 18:6a4db94011d3 353 #define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */
sahilmgandhi 18:6a4db94011d3 354 #define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */
sahilmgandhi 18:6a4db94011d3 355 #define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */
sahilmgandhi 18:6a4db94011d3 356
sahilmgandhi 18:6a4db94011d3 357 /* Bit fields for I2C RXDOUBLEP */
sahilmgandhi 18:6a4db94011d3 358 #define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */
sahilmgandhi 18:6a4db94011d3 359 #define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */
sahilmgandhi 18:6a4db94011d3 360 #define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */
sahilmgandhi 18:6a4db94011d3 361 #define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */
sahilmgandhi 18:6a4db94011d3 362 #define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */
sahilmgandhi 18:6a4db94011d3 363 #define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */
sahilmgandhi 18:6a4db94011d3 364 #define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */
sahilmgandhi 18:6a4db94011d3 365 #define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */
sahilmgandhi 18:6a4db94011d3 366 #define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */
sahilmgandhi 18:6a4db94011d3 367 #define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */
sahilmgandhi 18:6a4db94011d3 368
sahilmgandhi 18:6a4db94011d3 369 /* Bit fields for I2C TXDATA */
sahilmgandhi 18:6a4db94011d3 370 #define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */
sahilmgandhi 18:6a4db94011d3 371 #define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */
sahilmgandhi 18:6a4db94011d3 372 #define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */
sahilmgandhi 18:6a4db94011d3 373 #define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */
sahilmgandhi 18:6a4db94011d3 374 #define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */
sahilmgandhi 18:6a4db94011d3 375 #define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */
sahilmgandhi 18:6a4db94011d3 376
sahilmgandhi 18:6a4db94011d3 377 /* Bit fields for I2C TXDOUBLE */
sahilmgandhi 18:6a4db94011d3 378 #define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */
sahilmgandhi 18:6a4db94011d3 379 #define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */
sahilmgandhi 18:6a4db94011d3 380 #define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */
sahilmgandhi 18:6a4db94011d3 381 #define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */
sahilmgandhi 18:6a4db94011d3 382 #define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */
sahilmgandhi 18:6a4db94011d3 383 #define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */
sahilmgandhi 18:6a4db94011d3 384 #define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */
sahilmgandhi 18:6a4db94011d3 385 #define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */
sahilmgandhi 18:6a4db94011d3 386 #define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */
sahilmgandhi 18:6a4db94011d3 387 #define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */
sahilmgandhi 18:6a4db94011d3 388
sahilmgandhi 18:6a4db94011d3 389 /* Bit fields for I2C IF */
sahilmgandhi 18:6a4db94011d3 390 #define _I2C_IF_RESETVALUE 0x00000010UL /**< Default value for I2C_IF */
sahilmgandhi 18:6a4db94011d3 391 #define _I2C_IF_MASK 0x0007FFFFUL /**< Mask for I2C_IF */
sahilmgandhi 18:6a4db94011d3 392 #define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 393 #define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */
sahilmgandhi 18:6a4db94011d3 394 #define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */
sahilmgandhi 18:6a4db94011d3 395 #define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 396 #define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 397 #define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 398 #define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
sahilmgandhi 18:6a4db94011d3 399 #define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
sahilmgandhi 18:6a4db94011d3 400 #define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 401 #define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 402 #define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 403 #define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
sahilmgandhi 18:6a4db94011d3 404 #define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
sahilmgandhi 18:6a4db94011d3 405 #define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 406 #define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 407 #define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 408 #define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
sahilmgandhi 18:6a4db94011d3 409 #define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
sahilmgandhi 18:6a4db94011d3 410 #define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 411 #define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 412 #define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 413 #define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
sahilmgandhi 18:6a4db94011d3 414 #define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
sahilmgandhi 18:6a4db94011d3 415 #define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 416 #define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 417 #define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 418 #define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
sahilmgandhi 18:6a4db94011d3 419 #define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
sahilmgandhi 18:6a4db94011d3 420 #define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 421 #define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 422 #define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 423 #define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
sahilmgandhi 18:6a4db94011d3 424 #define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
sahilmgandhi 18:6a4db94011d3 425 #define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 426 #define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 427 #define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 428 #define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
sahilmgandhi 18:6a4db94011d3 429 #define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
sahilmgandhi 18:6a4db94011d3 430 #define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 431 #define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 432 #define I2C_IF_MSTOP (0x1UL << 8) /**< Master STOP Condition Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 433 #define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
sahilmgandhi 18:6a4db94011d3 434 #define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
sahilmgandhi 18:6a4db94011d3 435 #define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 436 #define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 437 #define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 438 #define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
sahilmgandhi 18:6a4db94011d3 439 #define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
sahilmgandhi 18:6a4db94011d3 440 #define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 441 #define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 442 #define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 443 #define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
sahilmgandhi 18:6a4db94011d3 444 #define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
sahilmgandhi 18:6a4db94011d3 445 #define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 446 #define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 447 #define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 448 #define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
sahilmgandhi 18:6a4db94011d3 449 #define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
sahilmgandhi 18:6a4db94011d3 450 #define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 451 #define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 452 #define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 453 #define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
sahilmgandhi 18:6a4db94011d3 454 #define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
sahilmgandhi 18:6a4db94011d3 455 #define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 456 #define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 457 #define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 458 #define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
sahilmgandhi 18:6a4db94011d3 459 #define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
sahilmgandhi 18:6a4db94011d3 460 #define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 461 #define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 462 #define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 463 #define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
sahilmgandhi 18:6a4db94011d3 464 #define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
sahilmgandhi 18:6a4db94011d3 465 #define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 466 #define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 467 #define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 468 #define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
sahilmgandhi 18:6a4db94011d3 469 #define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
sahilmgandhi 18:6a4db94011d3 470 #define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 471 #define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 472 #define I2C_IF_SSTOP (0x1UL << 16) /**< Slave STOP condition Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 473 #define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
sahilmgandhi 18:6a4db94011d3 474 #define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
sahilmgandhi 18:6a4db94011d3 475 #define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 476 #define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 477 #define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 478 #define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
sahilmgandhi 18:6a4db94011d3 479 #define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
sahilmgandhi 18:6a4db94011d3 480 #define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 481 #define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 482 #define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 483 #define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
sahilmgandhi 18:6a4db94011d3 484 #define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
sahilmgandhi 18:6a4db94011d3 485 #define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 486 #define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */
sahilmgandhi 18:6a4db94011d3 487
sahilmgandhi 18:6a4db94011d3 488 /* Bit fields for I2C IFS */
sahilmgandhi 18:6a4db94011d3 489 #define _I2C_IFS_RESETVALUE 0x00000000UL /**< Default value for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 490 #define _I2C_IFS_MASK 0x0007FFCFUL /**< Mask for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 491 #define I2C_IFS_START (0x1UL << 0) /**< Set START Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 492 #define _I2C_IFS_START_SHIFT 0 /**< Shift value for I2C_START */
sahilmgandhi 18:6a4db94011d3 493 #define _I2C_IFS_START_MASK 0x1UL /**< Bit mask for I2C_START */
sahilmgandhi 18:6a4db94011d3 494 #define _I2C_IFS_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 495 #define I2C_IFS_START_DEFAULT (_I2C_IFS_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 496 #define I2C_IFS_RSTART (0x1UL << 1) /**< Set RSTART Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 497 #define _I2C_IFS_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
sahilmgandhi 18:6a4db94011d3 498 #define _I2C_IFS_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
sahilmgandhi 18:6a4db94011d3 499 #define _I2C_IFS_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 500 #define I2C_IFS_RSTART_DEFAULT (_I2C_IFS_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 501 #define I2C_IFS_ADDR (0x1UL << 2) /**< Set ADDR Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 502 #define _I2C_IFS_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
sahilmgandhi 18:6a4db94011d3 503 #define _I2C_IFS_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
sahilmgandhi 18:6a4db94011d3 504 #define _I2C_IFS_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 505 #define I2C_IFS_ADDR_DEFAULT (_I2C_IFS_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 506 #define I2C_IFS_TXC (0x1UL << 3) /**< Set TXC Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 507 #define _I2C_IFS_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
sahilmgandhi 18:6a4db94011d3 508 #define _I2C_IFS_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
sahilmgandhi 18:6a4db94011d3 509 #define _I2C_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 510 #define I2C_IFS_TXC_DEFAULT (_I2C_IFS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 511 #define I2C_IFS_ACK (0x1UL << 6) /**< Set ACK Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 512 #define _I2C_IFS_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
sahilmgandhi 18:6a4db94011d3 513 #define _I2C_IFS_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
sahilmgandhi 18:6a4db94011d3 514 #define _I2C_IFS_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 515 #define I2C_IFS_ACK_DEFAULT (_I2C_IFS_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 516 #define I2C_IFS_NACK (0x1UL << 7) /**< Set NACK Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 517 #define _I2C_IFS_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
sahilmgandhi 18:6a4db94011d3 518 #define _I2C_IFS_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
sahilmgandhi 18:6a4db94011d3 519 #define _I2C_IFS_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 520 #define I2C_IFS_NACK_DEFAULT (_I2C_IFS_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 521 #define I2C_IFS_MSTOP (0x1UL << 8) /**< Set MSTOP Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 522 #define _I2C_IFS_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
sahilmgandhi 18:6a4db94011d3 523 #define _I2C_IFS_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
sahilmgandhi 18:6a4db94011d3 524 #define _I2C_IFS_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 525 #define I2C_IFS_MSTOP_DEFAULT (_I2C_IFS_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 526 #define I2C_IFS_ARBLOST (0x1UL << 9) /**< Set ARBLOST Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 527 #define _I2C_IFS_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
sahilmgandhi 18:6a4db94011d3 528 #define _I2C_IFS_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
sahilmgandhi 18:6a4db94011d3 529 #define _I2C_IFS_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 530 #define I2C_IFS_ARBLOST_DEFAULT (_I2C_IFS_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 531 #define I2C_IFS_BUSERR (0x1UL << 10) /**< Set BUSERR Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 532 #define _I2C_IFS_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
sahilmgandhi 18:6a4db94011d3 533 #define _I2C_IFS_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
sahilmgandhi 18:6a4db94011d3 534 #define _I2C_IFS_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 535 #define I2C_IFS_BUSERR_DEFAULT (_I2C_IFS_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 536 #define I2C_IFS_BUSHOLD (0x1UL << 11) /**< Set BUSHOLD Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 537 #define _I2C_IFS_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
sahilmgandhi 18:6a4db94011d3 538 #define _I2C_IFS_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
sahilmgandhi 18:6a4db94011d3 539 #define _I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 540 #define I2C_IFS_BUSHOLD_DEFAULT (_I2C_IFS_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 541 #define I2C_IFS_TXOF (0x1UL << 12) /**< Set TXOF Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 542 #define _I2C_IFS_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
sahilmgandhi 18:6a4db94011d3 543 #define _I2C_IFS_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
sahilmgandhi 18:6a4db94011d3 544 #define _I2C_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 545 #define I2C_IFS_TXOF_DEFAULT (_I2C_IFS_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 546 #define I2C_IFS_RXUF (0x1UL << 13) /**< Set RXUF Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 547 #define _I2C_IFS_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
sahilmgandhi 18:6a4db94011d3 548 #define _I2C_IFS_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
sahilmgandhi 18:6a4db94011d3 549 #define _I2C_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 550 #define I2C_IFS_RXUF_DEFAULT (_I2C_IFS_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 551 #define I2C_IFS_BITO (0x1UL << 14) /**< Set BITO Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 552 #define _I2C_IFS_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
sahilmgandhi 18:6a4db94011d3 553 #define _I2C_IFS_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
sahilmgandhi 18:6a4db94011d3 554 #define _I2C_IFS_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 555 #define I2C_IFS_BITO_DEFAULT (_I2C_IFS_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 556 #define I2C_IFS_CLTO (0x1UL << 15) /**< Set CLTO Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 557 #define _I2C_IFS_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
sahilmgandhi 18:6a4db94011d3 558 #define _I2C_IFS_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
sahilmgandhi 18:6a4db94011d3 559 #define _I2C_IFS_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 560 #define I2C_IFS_CLTO_DEFAULT (_I2C_IFS_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 561 #define I2C_IFS_SSTOP (0x1UL << 16) /**< Set SSTOP Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 562 #define _I2C_IFS_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
sahilmgandhi 18:6a4db94011d3 563 #define _I2C_IFS_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
sahilmgandhi 18:6a4db94011d3 564 #define _I2C_IFS_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 565 #define I2C_IFS_SSTOP_DEFAULT (_I2C_IFS_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 566 #define I2C_IFS_RXFULL (0x1UL << 17) /**< Set RXFULL Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 567 #define _I2C_IFS_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
sahilmgandhi 18:6a4db94011d3 568 #define _I2C_IFS_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
sahilmgandhi 18:6a4db94011d3 569 #define _I2C_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 570 #define I2C_IFS_RXFULL_DEFAULT (_I2C_IFS_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 571 #define I2C_IFS_CLERR (0x1UL << 18) /**< Set CLERR Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 572 #define _I2C_IFS_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
sahilmgandhi 18:6a4db94011d3 573 #define _I2C_IFS_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
sahilmgandhi 18:6a4db94011d3 574 #define _I2C_IFS_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 575 #define I2C_IFS_CLERR_DEFAULT (_I2C_IFS_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFS */
sahilmgandhi 18:6a4db94011d3 576
sahilmgandhi 18:6a4db94011d3 577 /* Bit fields for I2C IFC */
sahilmgandhi 18:6a4db94011d3 578 #define _I2C_IFC_RESETVALUE 0x00000000UL /**< Default value for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 579 #define _I2C_IFC_MASK 0x0007FFCFUL /**< Mask for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 580 #define I2C_IFC_START (0x1UL << 0) /**< Clear START Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 581 #define _I2C_IFC_START_SHIFT 0 /**< Shift value for I2C_START */
sahilmgandhi 18:6a4db94011d3 582 #define _I2C_IFC_START_MASK 0x1UL /**< Bit mask for I2C_START */
sahilmgandhi 18:6a4db94011d3 583 #define _I2C_IFC_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 584 #define I2C_IFC_START_DEFAULT (_I2C_IFC_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 585 #define I2C_IFC_RSTART (0x1UL << 1) /**< Clear RSTART Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 586 #define _I2C_IFC_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
sahilmgandhi 18:6a4db94011d3 587 #define _I2C_IFC_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
sahilmgandhi 18:6a4db94011d3 588 #define _I2C_IFC_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 589 #define I2C_IFC_RSTART_DEFAULT (_I2C_IFC_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 590 #define I2C_IFC_ADDR (0x1UL << 2) /**< Clear ADDR Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 591 #define _I2C_IFC_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
sahilmgandhi 18:6a4db94011d3 592 #define _I2C_IFC_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
sahilmgandhi 18:6a4db94011d3 593 #define _I2C_IFC_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 594 #define I2C_IFC_ADDR_DEFAULT (_I2C_IFC_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 595 #define I2C_IFC_TXC (0x1UL << 3) /**< Clear TXC Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 596 #define _I2C_IFC_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
sahilmgandhi 18:6a4db94011d3 597 #define _I2C_IFC_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
sahilmgandhi 18:6a4db94011d3 598 #define _I2C_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 599 #define I2C_IFC_TXC_DEFAULT (_I2C_IFC_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 600 #define I2C_IFC_ACK (0x1UL << 6) /**< Clear ACK Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 601 #define _I2C_IFC_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
sahilmgandhi 18:6a4db94011d3 602 #define _I2C_IFC_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
sahilmgandhi 18:6a4db94011d3 603 #define _I2C_IFC_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 604 #define I2C_IFC_ACK_DEFAULT (_I2C_IFC_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 605 #define I2C_IFC_NACK (0x1UL << 7) /**< Clear NACK Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 606 #define _I2C_IFC_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
sahilmgandhi 18:6a4db94011d3 607 #define _I2C_IFC_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
sahilmgandhi 18:6a4db94011d3 608 #define _I2C_IFC_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 609 #define I2C_IFC_NACK_DEFAULT (_I2C_IFC_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 610 #define I2C_IFC_MSTOP (0x1UL << 8) /**< Clear MSTOP Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 611 #define _I2C_IFC_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
sahilmgandhi 18:6a4db94011d3 612 #define _I2C_IFC_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
sahilmgandhi 18:6a4db94011d3 613 #define _I2C_IFC_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 614 #define I2C_IFC_MSTOP_DEFAULT (_I2C_IFC_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 615 #define I2C_IFC_ARBLOST (0x1UL << 9) /**< Clear ARBLOST Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 616 #define _I2C_IFC_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
sahilmgandhi 18:6a4db94011d3 617 #define _I2C_IFC_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
sahilmgandhi 18:6a4db94011d3 618 #define _I2C_IFC_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 619 #define I2C_IFC_ARBLOST_DEFAULT (_I2C_IFC_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 620 #define I2C_IFC_BUSERR (0x1UL << 10) /**< Clear BUSERR Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 621 #define _I2C_IFC_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
sahilmgandhi 18:6a4db94011d3 622 #define _I2C_IFC_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
sahilmgandhi 18:6a4db94011d3 623 #define _I2C_IFC_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 624 #define I2C_IFC_BUSERR_DEFAULT (_I2C_IFC_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 625 #define I2C_IFC_BUSHOLD (0x1UL << 11) /**< Clear BUSHOLD Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 626 #define _I2C_IFC_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
sahilmgandhi 18:6a4db94011d3 627 #define _I2C_IFC_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
sahilmgandhi 18:6a4db94011d3 628 #define _I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 629 #define I2C_IFC_BUSHOLD_DEFAULT (_I2C_IFC_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 630 #define I2C_IFC_TXOF (0x1UL << 12) /**< Clear TXOF Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 631 #define _I2C_IFC_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
sahilmgandhi 18:6a4db94011d3 632 #define _I2C_IFC_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
sahilmgandhi 18:6a4db94011d3 633 #define _I2C_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 634 #define I2C_IFC_TXOF_DEFAULT (_I2C_IFC_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 635 #define I2C_IFC_RXUF (0x1UL << 13) /**< Clear RXUF Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 636 #define _I2C_IFC_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
sahilmgandhi 18:6a4db94011d3 637 #define _I2C_IFC_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
sahilmgandhi 18:6a4db94011d3 638 #define _I2C_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 639 #define I2C_IFC_RXUF_DEFAULT (_I2C_IFC_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 640 #define I2C_IFC_BITO (0x1UL << 14) /**< Clear BITO Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 641 #define _I2C_IFC_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
sahilmgandhi 18:6a4db94011d3 642 #define _I2C_IFC_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
sahilmgandhi 18:6a4db94011d3 643 #define _I2C_IFC_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 644 #define I2C_IFC_BITO_DEFAULT (_I2C_IFC_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 645 #define I2C_IFC_CLTO (0x1UL << 15) /**< Clear CLTO Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 646 #define _I2C_IFC_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
sahilmgandhi 18:6a4db94011d3 647 #define _I2C_IFC_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
sahilmgandhi 18:6a4db94011d3 648 #define _I2C_IFC_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 649 #define I2C_IFC_CLTO_DEFAULT (_I2C_IFC_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 650 #define I2C_IFC_SSTOP (0x1UL << 16) /**< Clear SSTOP Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 651 #define _I2C_IFC_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
sahilmgandhi 18:6a4db94011d3 652 #define _I2C_IFC_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
sahilmgandhi 18:6a4db94011d3 653 #define _I2C_IFC_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 654 #define I2C_IFC_SSTOP_DEFAULT (_I2C_IFC_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 655 #define I2C_IFC_RXFULL (0x1UL << 17) /**< Clear RXFULL Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 656 #define _I2C_IFC_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
sahilmgandhi 18:6a4db94011d3 657 #define _I2C_IFC_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
sahilmgandhi 18:6a4db94011d3 658 #define _I2C_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 659 #define I2C_IFC_RXFULL_DEFAULT (_I2C_IFC_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 660 #define I2C_IFC_CLERR (0x1UL << 18) /**< Clear CLERR Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 661 #define _I2C_IFC_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
sahilmgandhi 18:6a4db94011d3 662 #define _I2C_IFC_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
sahilmgandhi 18:6a4db94011d3 663 #define _I2C_IFC_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 664 #define I2C_IFC_CLERR_DEFAULT (_I2C_IFC_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFC */
sahilmgandhi 18:6a4db94011d3 665
sahilmgandhi 18:6a4db94011d3 666 /* Bit fields for I2C IEN */
sahilmgandhi 18:6a4db94011d3 667 #define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 668 #define _I2C_IEN_MASK 0x0007FFFFUL /**< Mask for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 669 #define I2C_IEN_START (0x1UL << 0) /**< START Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 670 #define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */
sahilmgandhi 18:6a4db94011d3 671 #define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */
sahilmgandhi 18:6a4db94011d3 672 #define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 673 #define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 674 #define I2C_IEN_RSTART (0x1UL << 1) /**< RSTART Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 675 #define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
sahilmgandhi 18:6a4db94011d3 676 #define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
sahilmgandhi 18:6a4db94011d3 677 #define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 678 #define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 679 #define I2C_IEN_ADDR (0x1UL << 2) /**< ADDR Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 680 #define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
sahilmgandhi 18:6a4db94011d3 681 #define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
sahilmgandhi 18:6a4db94011d3 682 #define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 683 #define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 684 #define I2C_IEN_TXC (0x1UL << 3) /**< TXC Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 685 #define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
sahilmgandhi 18:6a4db94011d3 686 #define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
sahilmgandhi 18:6a4db94011d3 687 #define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 688 #define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 689 #define I2C_IEN_TXBL (0x1UL << 4) /**< TXBL Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 690 #define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
sahilmgandhi 18:6a4db94011d3 691 #define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
sahilmgandhi 18:6a4db94011d3 692 #define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 693 #define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 694 #define I2C_IEN_RXDATAV (0x1UL << 5) /**< RXDATAV Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 695 #define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
sahilmgandhi 18:6a4db94011d3 696 #define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
sahilmgandhi 18:6a4db94011d3 697 #define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 698 #define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 699 #define I2C_IEN_ACK (0x1UL << 6) /**< ACK Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 700 #define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
sahilmgandhi 18:6a4db94011d3 701 #define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
sahilmgandhi 18:6a4db94011d3 702 #define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 703 #define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 704 #define I2C_IEN_NACK (0x1UL << 7) /**< NACK Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 705 #define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
sahilmgandhi 18:6a4db94011d3 706 #define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
sahilmgandhi 18:6a4db94011d3 707 #define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 708 #define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 709 #define I2C_IEN_MSTOP (0x1UL << 8) /**< MSTOP Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 710 #define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
sahilmgandhi 18:6a4db94011d3 711 #define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
sahilmgandhi 18:6a4db94011d3 712 #define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 713 #define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 714 #define I2C_IEN_ARBLOST (0x1UL << 9) /**< ARBLOST Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 715 #define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
sahilmgandhi 18:6a4db94011d3 716 #define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
sahilmgandhi 18:6a4db94011d3 717 #define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 718 #define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 719 #define I2C_IEN_BUSERR (0x1UL << 10) /**< BUSERR Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 720 #define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
sahilmgandhi 18:6a4db94011d3 721 #define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
sahilmgandhi 18:6a4db94011d3 722 #define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 723 #define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 724 #define I2C_IEN_BUSHOLD (0x1UL << 11) /**< BUSHOLD Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 725 #define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
sahilmgandhi 18:6a4db94011d3 726 #define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
sahilmgandhi 18:6a4db94011d3 727 #define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 728 #define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 729 #define I2C_IEN_TXOF (0x1UL << 12) /**< TXOF Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 730 #define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
sahilmgandhi 18:6a4db94011d3 731 #define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
sahilmgandhi 18:6a4db94011d3 732 #define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 733 #define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 734 #define I2C_IEN_RXUF (0x1UL << 13) /**< RXUF Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 735 #define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
sahilmgandhi 18:6a4db94011d3 736 #define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
sahilmgandhi 18:6a4db94011d3 737 #define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 738 #define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 739 #define I2C_IEN_BITO (0x1UL << 14) /**< BITO Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 740 #define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
sahilmgandhi 18:6a4db94011d3 741 #define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
sahilmgandhi 18:6a4db94011d3 742 #define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 743 #define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 744 #define I2C_IEN_CLTO (0x1UL << 15) /**< CLTO Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 745 #define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
sahilmgandhi 18:6a4db94011d3 746 #define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
sahilmgandhi 18:6a4db94011d3 747 #define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 748 #define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 749 #define I2C_IEN_SSTOP (0x1UL << 16) /**< SSTOP Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 750 #define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
sahilmgandhi 18:6a4db94011d3 751 #define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
sahilmgandhi 18:6a4db94011d3 752 #define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 753 #define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 754 #define I2C_IEN_RXFULL (0x1UL << 17) /**< RXFULL Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 755 #define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
sahilmgandhi 18:6a4db94011d3 756 #define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
sahilmgandhi 18:6a4db94011d3 757 #define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 758 #define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 759 #define I2C_IEN_CLERR (0x1UL << 18) /**< CLERR Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 760 #define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
sahilmgandhi 18:6a4db94011d3 761 #define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
sahilmgandhi 18:6a4db94011d3 762 #define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 763 #define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */
sahilmgandhi 18:6a4db94011d3 764
sahilmgandhi 18:6a4db94011d3 765 /* Bit fields for I2C ROUTEPEN */
sahilmgandhi 18:6a4db94011d3 766 #define _I2C_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTEPEN */
sahilmgandhi 18:6a4db94011d3 767 #define _I2C_ROUTEPEN_MASK 0x00000003UL /**< Mask for I2C_ROUTEPEN */
sahilmgandhi 18:6a4db94011d3 768 #define I2C_ROUTEPEN_SDAPEN (0x1UL << 0) /**< SDA Pin Enable */
sahilmgandhi 18:6a4db94011d3 769 #define _I2C_ROUTEPEN_SDAPEN_SHIFT 0 /**< Shift value for I2C_SDAPEN */
sahilmgandhi 18:6a4db94011d3 770 #define _I2C_ROUTEPEN_SDAPEN_MASK 0x1UL /**< Bit mask for I2C_SDAPEN */
sahilmgandhi 18:6a4db94011d3 771 #define _I2C_ROUTEPEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */
sahilmgandhi 18:6a4db94011d3 772 #define I2C_ROUTEPEN_SDAPEN_DEFAULT (_I2C_ROUTEPEN_SDAPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */
sahilmgandhi 18:6a4db94011d3 773 #define I2C_ROUTEPEN_SCLPEN (0x1UL << 1) /**< SCL Pin Enable */
sahilmgandhi 18:6a4db94011d3 774 #define _I2C_ROUTEPEN_SCLPEN_SHIFT 1 /**< Shift value for I2C_SCLPEN */
sahilmgandhi 18:6a4db94011d3 775 #define _I2C_ROUTEPEN_SCLPEN_MASK 0x2UL /**< Bit mask for I2C_SCLPEN */
sahilmgandhi 18:6a4db94011d3 776 #define _I2C_ROUTEPEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */
sahilmgandhi 18:6a4db94011d3 777 #define I2C_ROUTEPEN_SCLPEN_DEFAULT (_I2C_ROUTEPEN_SCLPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */
sahilmgandhi 18:6a4db94011d3 778
sahilmgandhi 18:6a4db94011d3 779 /* Bit fields for I2C ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 780 #define _I2C_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 781 #define _I2C_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 782 #define _I2C_ROUTELOC0_SDALOC_SHIFT 0 /**< Shift value for I2C_SDALOC */
sahilmgandhi 18:6a4db94011d3 783 #define _I2C_ROUTELOC0_SDALOC_MASK 0x1FUL /**< Bit mask for I2C_SDALOC */
sahilmgandhi 18:6a4db94011d3 784 #define _I2C_ROUTELOC0_SDALOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 785 #define _I2C_ROUTELOC0_SDALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 786 #define _I2C_ROUTELOC0_SDALOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 787 #define _I2C_ROUTELOC0_SDALOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 788 #define _I2C_ROUTELOC0_SDALOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 789 #define _I2C_ROUTELOC0_SDALOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 790 #define _I2C_ROUTELOC0_SDALOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 791 #define _I2C_ROUTELOC0_SDALOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 792 #define _I2C_ROUTELOC0_SDALOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 793 #define _I2C_ROUTELOC0_SDALOC_LOC8 0x00000008UL /**< Mode LOC8 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 794 #define _I2C_ROUTELOC0_SDALOC_LOC9 0x00000009UL /**< Mode LOC9 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 795 #define _I2C_ROUTELOC0_SDALOC_LOC10 0x0000000AUL /**< Mode LOC10 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 796 #define _I2C_ROUTELOC0_SDALOC_LOC11 0x0000000BUL /**< Mode LOC11 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 797 #define _I2C_ROUTELOC0_SDALOC_LOC12 0x0000000CUL /**< Mode LOC12 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 798 #define _I2C_ROUTELOC0_SDALOC_LOC13 0x0000000DUL /**< Mode LOC13 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 799 #define _I2C_ROUTELOC0_SDALOC_LOC14 0x0000000EUL /**< Mode LOC14 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 800 #define _I2C_ROUTELOC0_SDALOC_LOC15 0x0000000FUL /**< Mode LOC15 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 801 #define _I2C_ROUTELOC0_SDALOC_LOC16 0x00000010UL /**< Mode LOC16 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 802 #define _I2C_ROUTELOC0_SDALOC_LOC17 0x00000011UL /**< Mode LOC17 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 803 #define _I2C_ROUTELOC0_SDALOC_LOC18 0x00000012UL /**< Mode LOC18 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 804 #define _I2C_ROUTELOC0_SDALOC_LOC19 0x00000013UL /**< Mode LOC19 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 805 #define _I2C_ROUTELOC0_SDALOC_LOC20 0x00000014UL /**< Mode LOC20 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 806 #define _I2C_ROUTELOC0_SDALOC_LOC21 0x00000015UL /**< Mode LOC21 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 807 #define _I2C_ROUTELOC0_SDALOC_LOC22 0x00000016UL /**< Mode LOC22 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 808 #define _I2C_ROUTELOC0_SDALOC_LOC23 0x00000017UL /**< Mode LOC23 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 809 #define _I2C_ROUTELOC0_SDALOC_LOC24 0x00000018UL /**< Mode LOC24 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 810 #define _I2C_ROUTELOC0_SDALOC_LOC25 0x00000019UL /**< Mode LOC25 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 811 #define _I2C_ROUTELOC0_SDALOC_LOC26 0x0000001AUL /**< Mode LOC26 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 812 #define _I2C_ROUTELOC0_SDALOC_LOC27 0x0000001BUL /**< Mode LOC27 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 813 #define _I2C_ROUTELOC0_SDALOC_LOC28 0x0000001CUL /**< Mode LOC28 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 814 #define _I2C_ROUTELOC0_SDALOC_LOC29 0x0000001DUL /**< Mode LOC29 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 815 #define _I2C_ROUTELOC0_SDALOC_LOC30 0x0000001EUL /**< Mode LOC30 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 816 #define _I2C_ROUTELOC0_SDALOC_LOC31 0x0000001FUL /**< Mode LOC31 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 817 #define I2C_ROUTELOC0_SDALOC_LOC0 (_I2C_ROUTELOC0_SDALOC_LOC0 << 0) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 818 #define I2C_ROUTELOC0_SDALOC_DEFAULT (_I2C_ROUTELOC0_SDALOC_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 819 #define I2C_ROUTELOC0_SDALOC_LOC1 (_I2C_ROUTELOC0_SDALOC_LOC1 << 0) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 820 #define I2C_ROUTELOC0_SDALOC_LOC2 (_I2C_ROUTELOC0_SDALOC_LOC2 << 0) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 821 #define I2C_ROUTELOC0_SDALOC_LOC3 (_I2C_ROUTELOC0_SDALOC_LOC3 << 0) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 822 #define I2C_ROUTELOC0_SDALOC_LOC4 (_I2C_ROUTELOC0_SDALOC_LOC4 << 0) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 823 #define I2C_ROUTELOC0_SDALOC_LOC5 (_I2C_ROUTELOC0_SDALOC_LOC5 << 0) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 824 #define I2C_ROUTELOC0_SDALOC_LOC6 (_I2C_ROUTELOC0_SDALOC_LOC6 << 0) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 825 #define I2C_ROUTELOC0_SDALOC_LOC7 (_I2C_ROUTELOC0_SDALOC_LOC7 << 0) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 826 #define I2C_ROUTELOC0_SDALOC_LOC8 (_I2C_ROUTELOC0_SDALOC_LOC8 << 0) /**< Shifted mode LOC8 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 827 #define I2C_ROUTELOC0_SDALOC_LOC9 (_I2C_ROUTELOC0_SDALOC_LOC9 << 0) /**< Shifted mode LOC9 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 828 #define I2C_ROUTELOC0_SDALOC_LOC10 (_I2C_ROUTELOC0_SDALOC_LOC10 << 0) /**< Shifted mode LOC10 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 829 #define I2C_ROUTELOC0_SDALOC_LOC11 (_I2C_ROUTELOC0_SDALOC_LOC11 << 0) /**< Shifted mode LOC11 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 830 #define I2C_ROUTELOC0_SDALOC_LOC12 (_I2C_ROUTELOC0_SDALOC_LOC12 << 0) /**< Shifted mode LOC12 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 831 #define I2C_ROUTELOC0_SDALOC_LOC13 (_I2C_ROUTELOC0_SDALOC_LOC13 << 0) /**< Shifted mode LOC13 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 832 #define I2C_ROUTELOC0_SDALOC_LOC14 (_I2C_ROUTELOC0_SDALOC_LOC14 << 0) /**< Shifted mode LOC14 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 833 #define I2C_ROUTELOC0_SDALOC_LOC15 (_I2C_ROUTELOC0_SDALOC_LOC15 << 0) /**< Shifted mode LOC15 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 834 #define I2C_ROUTELOC0_SDALOC_LOC16 (_I2C_ROUTELOC0_SDALOC_LOC16 << 0) /**< Shifted mode LOC16 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 835 #define I2C_ROUTELOC0_SDALOC_LOC17 (_I2C_ROUTELOC0_SDALOC_LOC17 << 0) /**< Shifted mode LOC17 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 836 #define I2C_ROUTELOC0_SDALOC_LOC18 (_I2C_ROUTELOC0_SDALOC_LOC18 << 0) /**< Shifted mode LOC18 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 837 #define I2C_ROUTELOC0_SDALOC_LOC19 (_I2C_ROUTELOC0_SDALOC_LOC19 << 0) /**< Shifted mode LOC19 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 838 #define I2C_ROUTELOC0_SDALOC_LOC20 (_I2C_ROUTELOC0_SDALOC_LOC20 << 0) /**< Shifted mode LOC20 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 839 #define I2C_ROUTELOC0_SDALOC_LOC21 (_I2C_ROUTELOC0_SDALOC_LOC21 << 0) /**< Shifted mode LOC21 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 840 #define I2C_ROUTELOC0_SDALOC_LOC22 (_I2C_ROUTELOC0_SDALOC_LOC22 << 0) /**< Shifted mode LOC22 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 841 #define I2C_ROUTELOC0_SDALOC_LOC23 (_I2C_ROUTELOC0_SDALOC_LOC23 << 0) /**< Shifted mode LOC23 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 842 #define I2C_ROUTELOC0_SDALOC_LOC24 (_I2C_ROUTELOC0_SDALOC_LOC24 << 0) /**< Shifted mode LOC24 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 843 #define I2C_ROUTELOC0_SDALOC_LOC25 (_I2C_ROUTELOC0_SDALOC_LOC25 << 0) /**< Shifted mode LOC25 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 844 #define I2C_ROUTELOC0_SDALOC_LOC26 (_I2C_ROUTELOC0_SDALOC_LOC26 << 0) /**< Shifted mode LOC26 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 845 #define I2C_ROUTELOC0_SDALOC_LOC27 (_I2C_ROUTELOC0_SDALOC_LOC27 << 0) /**< Shifted mode LOC27 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 846 #define I2C_ROUTELOC0_SDALOC_LOC28 (_I2C_ROUTELOC0_SDALOC_LOC28 << 0) /**< Shifted mode LOC28 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 847 #define I2C_ROUTELOC0_SDALOC_LOC29 (_I2C_ROUTELOC0_SDALOC_LOC29 << 0) /**< Shifted mode LOC29 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 848 #define I2C_ROUTELOC0_SDALOC_LOC30 (_I2C_ROUTELOC0_SDALOC_LOC30 << 0) /**< Shifted mode LOC30 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 849 #define I2C_ROUTELOC0_SDALOC_LOC31 (_I2C_ROUTELOC0_SDALOC_LOC31 << 0) /**< Shifted mode LOC31 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 850 #define _I2C_ROUTELOC0_SCLLOC_SHIFT 8 /**< Shift value for I2C_SCLLOC */
sahilmgandhi 18:6a4db94011d3 851 #define _I2C_ROUTELOC0_SCLLOC_MASK 0x1F00UL /**< Bit mask for I2C_SCLLOC */
sahilmgandhi 18:6a4db94011d3 852 #define _I2C_ROUTELOC0_SCLLOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 853 #define _I2C_ROUTELOC0_SCLLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 854 #define _I2C_ROUTELOC0_SCLLOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 855 #define _I2C_ROUTELOC0_SCLLOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 856 #define _I2C_ROUTELOC0_SCLLOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 857 #define _I2C_ROUTELOC0_SCLLOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 858 #define _I2C_ROUTELOC0_SCLLOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 859 #define _I2C_ROUTELOC0_SCLLOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 860 #define _I2C_ROUTELOC0_SCLLOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 861 #define _I2C_ROUTELOC0_SCLLOC_LOC8 0x00000008UL /**< Mode LOC8 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 862 #define _I2C_ROUTELOC0_SCLLOC_LOC9 0x00000009UL /**< Mode LOC9 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 863 #define _I2C_ROUTELOC0_SCLLOC_LOC10 0x0000000AUL /**< Mode LOC10 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 864 #define _I2C_ROUTELOC0_SCLLOC_LOC11 0x0000000BUL /**< Mode LOC11 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 865 #define _I2C_ROUTELOC0_SCLLOC_LOC12 0x0000000CUL /**< Mode LOC12 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 866 #define _I2C_ROUTELOC0_SCLLOC_LOC13 0x0000000DUL /**< Mode LOC13 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 867 #define _I2C_ROUTELOC0_SCLLOC_LOC14 0x0000000EUL /**< Mode LOC14 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 868 #define _I2C_ROUTELOC0_SCLLOC_LOC15 0x0000000FUL /**< Mode LOC15 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 869 #define _I2C_ROUTELOC0_SCLLOC_LOC16 0x00000010UL /**< Mode LOC16 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 870 #define _I2C_ROUTELOC0_SCLLOC_LOC17 0x00000011UL /**< Mode LOC17 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 871 #define _I2C_ROUTELOC0_SCLLOC_LOC18 0x00000012UL /**< Mode LOC18 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 872 #define _I2C_ROUTELOC0_SCLLOC_LOC19 0x00000013UL /**< Mode LOC19 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 873 #define _I2C_ROUTELOC0_SCLLOC_LOC20 0x00000014UL /**< Mode LOC20 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 874 #define _I2C_ROUTELOC0_SCLLOC_LOC21 0x00000015UL /**< Mode LOC21 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 875 #define _I2C_ROUTELOC0_SCLLOC_LOC22 0x00000016UL /**< Mode LOC22 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 876 #define _I2C_ROUTELOC0_SCLLOC_LOC23 0x00000017UL /**< Mode LOC23 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 877 #define _I2C_ROUTELOC0_SCLLOC_LOC24 0x00000018UL /**< Mode LOC24 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 878 #define _I2C_ROUTELOC0_SCLLOC_LOC25 0x00000019UL /**< Mode LOC25 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 879 #define _I2C_ROUTELOC0_SCLLOC_LOC26 0x0000001AUL /**< Mode LOC26 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 880 #define _I2C_ROUTELOC0_SCLLOC_LOC27 0x0000001BUL /**< Mode LOC27 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 881 #define _I2C_ROUTELOC0_SCLLOC_LOC28 0x0000001CUL /**< Mode LOC28 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 882 #define _I2C_ROUTELOC0_SCLLOC_LOC29 0x0000001DUL /**< Mode LOC29 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 883 #define _I2C_ROUTELOC0_SCLLOC_LOC30 0x0000001EUL /**< Mode LOC30 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 884 #define _I2C_ROUTELOC0_SCLLOC_LOC31 0x0000001FUL /**< Mode LOC31 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 885 #define I2C_ROUTELOC0_SCLLOC_LOC0 (_I2C_ROUTELOC0_SCLLOC_LOC0 << 8) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 886 #define I2C_ROUTELOC0_SCLLOC_DEFAULT (_I2C_ROUTELOC0_SCLLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 887 #define I2C_ROUTELOC0_SCLLOC_LOC1 (_I2C_ROUTELOC0_SCLLOC_LOC1 << 8) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 888 #define I2C_ROUTELOC0_SCLLOC_LOC2 (_I2C_ROUTELOC0_SCLLOC_LOC2 << 8) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 889 #define I2C_ROUTELOC0_SCLLOC_LOC3 (_I2C_ROUTELOC0_SCLLOC_LOC3 << 8) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 890 #define I2C_ROUTELOC0_SCLLOC_LOC4 (_I2C_ROUTELOC0_SCLLOC_LOC4 << 8) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 891 #define I2C_ROUTELOC0_SCLLOC_LOC5 (_I2C_ROUTELOC0_SCLLOC_LOC5 << 8) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 892 #define I2C_ROUTELOC0_SCLLOC_LOC6 (_I2C_ROUTELOC0_SCLLOC_LOC6 << 8) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 893 #define I2C_ROUTELOC0_SCLLOC_LOC7 (_I2C_ROUTELOC0_SCLLOC_LOC7 << 8) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 894 #define I2C_ROUTELOC0_SCLLOC_LOC8 (_I2C_ROUTELOC0_SCLLOC_LOC8 << 8) /**< Shifted mode LOC8 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 895 #define I2C_ROUTELOC0_SCLLOC_LOC9 (_I2C_ROUTELOC0_SCLLOC_LOC9 << 8) /**< Shifted mode LOC9 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 896 #define I2C_ROUTELOC0_SCLLOC_LOC10 (_I2C_ROUTELOC0_SCLLOC_LOC10 << 8) /**< Shifted mode LOC10 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 897 #define I2C_ROUTELOC0_SCLLOC_LOC11 (_I2C_ROUTELOC0_SCLLOC_LOC11 << 8) /**< Shifted mode LOC11 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 898 #define I2C_ROUTELOC0_SCLLOC_LOC12 (_I2C_ROUTELOC0_SCLLOC_LOC12 << 8) /**< Shifted mode LOC12 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 899 #define I2C_ROUTELOC0_SCLLOC_LOC13 (_I2C_ROUTELOC0_SCLLOC_LOC13 << 8) /**< Shifted mode LOC13 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 900 #define I2C_ROUTELOC0_SCLLOC_LOC14 (_I2C_ROUTELOC0_SCLLOC_LOC14 << 8) /**< Shifted mode LOC14 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 901 #define I2C_ROUTELOC0_SCLLOC_LOC15 (_I2C_ROUTELOC0_SCLLOC_LOC15 << 8) /**< Shifted mode LOC15 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 902 #define I2C_ROUTELOC0_SCLLOC_LOC16 (_I2C_ROUTELOC0_SCLLOC_LOC16 << 8) /**< Shifted mode LOC16 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 903 #define I2C_ROUTELOC0_SCLLOC_LOC17 (_I2C_ROUTELOC0_SCLLOC_LOC17 << 8) /**< Shifted mode LOC17 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 904 #define I2C_ROUTELOC0_SCLLOC_LOC18 (_I2C_ROUTELOC0_SCLLOC_LOC18 << 8) /**< Shifted mode LOC18 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 905 #define I2C_ROUTELOC0_SCLLOC_LOC19 (_I2C_ROUTELOC0_SCLLOC_LOC19 << 8) /**< Shifted mode LOC19 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 906 #define I2C_ROUTELOC0_SCLLOC_LOC20 (_I2C_ROUTELOC0_SCLLOC_LOC20 << 8) /**< Shifted mode LOC20 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 907 #define I2C_ROUTELOC0_SCLLOC_LOC21 (_I2C_ROUTELOC0_SCLLOC_LOC21 << 8) /**< Shifted mode LOC21 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 908 #define I2C_ROUTELOC0_SCLLOC_LOC22 (_I2C_ROUTELOC0_SCLLOC_LOC22 << 8) /**< Shifted mode LOC22 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 909 #define I2C_ROUTELOC0_SCLLOC_LOC23 (_I2C_ROUTELOC0_SCLLOC_LOC23 << 8) /**< Shifted mode LOC23 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 910 #define I2C_ROUTELOC0_SCLLOC_LOC24 (_I2C_ROUTELOC0_SCLLOC_LOC24 << 8) /**< Shifted mode LOC24 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 911 #define I2C_ROUTELOC0_SCLLOC_LOC25 (_I2C_ROUTELOC0_SCLLOC_LOC25 << 8) /**< Shifted mode LOC25 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 912 #define I2C_ROUTELOC0_SCLLOC_LOC26 (_I2C_ROUTELOC0_SCLLOC_LOC26 << 8) /**< Shifted mode LOC26 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 913 #define I2C_ROUTELOC0_SCLLOC_LOC27 (_I2C_ROUTELOC0_SCLLOC_LOC27 << 8) /**< Shifted mode LOC27 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 914 #define I2C_ROUTELOC0_SCLLOC_LOC28 (_I2C_ROUTELOC0_SCLLOC_LOC28 << 8) /**< Shifted mode LOC28 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 915 #define I2C_ROUTELOC0_SCLLOC_LOC29 (_I2C_ROUTELOC0_SCLLOC_LOC29 << 8) /**< Shifted mode LOC29 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 916 #define I2C_ROUTELOC0_SCLLOC_LOC30 (_I2C_ROUTELOC0_SCLLOC_LOC30 << 8) /**< Shifted mode LOC30 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 917 #define I2C_ROUTELOC0_SCLLOC_LOC31 (_I2C_ROUTELOC0_SCLLOC_LOC31 << 8) /**< Shifted mode LOC31 for I2C_ROUTELOC0 */
sahilmgandhi 18:6a4db94011d3 918
sahilmgandhi 18:6a4db94011d3 919 /** @} End of group EFR32MG1P_I2C */
sahilmgandhi 18:6a4db94011d3 920 /** @} End of group Parts */
sahilmgandhi 18:6a4db94011d3 921