MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_fpueh.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

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sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file efr32mg1p_fpueh.h
sahilmgandhi 18:6a4db94011d3 3 * @brief EFR32MG1P_FPUEH register and bit field definitions
sahilmgandhi 18:6a4db94011d3 4 * @version 5.1.2
sahilmgandhi 18:6a4db94011d3 5 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 6 * @section License
sahilmgandhi 18:6a4db94011d3 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
sahilmgandhi 18:6a4db94011d3 8 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Permission is granted to anyone to use this software for any purpose,
sahilmgandhi 18:6a4db94011d3 11 * including commercial applications, and to alter it and redistribute it
sahilmgandhi 18:6a4db94011d3 12 * freely, subject to the following restrictions:
sahilmgandhi 18:6a4db94011d3 13 *
sahilmgandhi 18:6a4db94011d3 14 * 1. The origin of this software must not be misrepresented; you must not
sahilmgandhi 18:6a4db94011d3 15 * claim that you wrote the original software.@n
sahilmgandhi 18:6a4db94011d3 16 * 2. Altered source versions must be plainly marked as such, and must not be
sahilmgandhi 18:6a4db94011d3 17 * misrepresented as being the original software.@n
sahilmgandhi 18:6a4db94011d3 18 * 3. This notice may not be removed or altered from any source distribution.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
sahilmgandhi 18:6a4db94011d3 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
sahilmgandhi 18:6a4db94011d3 22 * providing the Software "AS IS", with no express or implied warranties of any
sahilmgandhi 18:6a4db94011d3 23 * kind, including, but not limited to, any implied warranties of
sahilmgandhi 18:6a4db94011d3 24 * merchantability or fitness for any particular purpose or warranties against
sahilmgandhi 18:6a4db94011d3 25 * infringement of any proprietary rights of a third party.
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
sahilmgandhi 18:6a4db94011d3 28 * incidental, or special damages, or any other relief, or for any claim by
sahilmgandhi 18:6a4db94011d3 29 * any third party, arising from your use of this Software.
sahilmgandhi 18:6a4db94011d3 30 *
sahilmgandhi 18:6a4db94011d3 31 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 32 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 33 * @addtogroup Parts
sahilmgandhi 18:6a4db94011d3 34 * @{
sahilmgandhi 18:6a4db94011d3 35 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 36 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 37 * @defgroup EFR32MG1P_FPUEH
sahilmgandhi 18:6a4db94011d3 38 * @{
sahilmgandhi 18:6a4db94011d3 39 * @brief EFR32MG1P_FPUEH Register Declaration
sahilmgandhi 18:6a4db94011d3 40 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 41 typedef struct
sahilmgandhi 18:6a4db94011d3 42 {
sahilmgandhi 18:6a4db94011d3 43 __IM uint32_t IF; /**< Interrupt Flag Register */
sahilmgandhi 18:6a4db94011d3 44 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
sahilmgandhi 18:6a4db94011d3 45 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
sahilmgandhi 18:6a4db94011d3 46 __IOM uint32_t IEN; /**< Interrupt Enable Register */
sahilmgandhi 18:6a4db94011d3 47 } FPUEH_TypeDef; /** @} */
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 50 * @defgroup EFR32MG1P_FPUEH_BitFields
sahilmgandhi 18:6a4db94011d3 51 * @{
sahilmgandhi 18:6a4db94011d3 52 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 53
sahilmgandhi 18:6a4db94011d3 54 /* Bit fields for FPUEH IF */
sahilmgandhi 18:6a4db94011d3 55 #define _FPUEH_IF_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IF */
sahilmgandhi 18:6a4db94011d3 56 #define _FPUEH_IF_MASK 0x0000003FUL /**< Mask for FPUEH_IF */
sahilmgandhi 18:6a4db94011d3 57 #define FPUEH_IF_FPIOC (0x1UL << 0) /**< FPU invalid operation */
sahilmgandhi 18:6a4db94011d3 58 #define _FPUEH_IF_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
sahilmgandhi 18:6a4db94011d3 59 #define _FPUEH_IF_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
sahilmgandhi 18:6a4db94011d3 60 #define _FPUEH_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
sahilmgandhi 18:6a4db94011d3 61 #define FPUEH_IF_FPIOC_DEFAULT (_FPUEH_IF_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IF */
sahilmgandhi 18:6a4db94011d3 62 #define FPUEH_IF_FPDZC (0x1UL << 1) /**< FPU divide-by-zero exception */
sahilmgandhi 18:6a4db94011d3 63 #define _FPUEH_IF_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
sahilmgandhi 18:6a4db94011d3 64 #define _FPUEH_IF_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
sahilmgandhi 18:6a4db94011d3 65 #define _FPUEH_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
sahilmgandhi 18:6a4db94011d3 66 #define FPUEH_IF_FPDZC_DEFAULT (_FPUEH_IF_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IF */
sahilmgandhi 18:6a4db94011d3 67 #define FPUEH_IF_FPUFC (0x1UL << 2) /**< FPU underflow exception */
sahilmgandhi 18:6a4db94011d3 68 #define _FPUEH_IF_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
sahilmgandhi 18:6a4db94011d3 69 #define _FPUEH_IF_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
sahilmgandhi 18:6a4db94011d3 70 #define _FPUEH_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
sahilmgandhi 18:6a4db94011d3 71 #define FPUEH_IF_FPUFC_DEFAULT (_FPUEH_IF_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IF */
sahilmgandhi 18:6a4db94011d3 72 #define FPUEH_IF_FPOFC (0x1UL << 3) /**< FPU overflow exception */
sahilmgandhi 18:6a4db94011d3 73 #define _FPUEH_IF_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
sahilmgandhi 18:6a4db94011d3 74 #define _FPUEH_IF_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
sahilmgandhi 18:6a4db94011d3 75 #define _FPUEH_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
sahilmgandhi 18:6a4db94011d3 76 #define FPUEH_IF_FPOFC_DEFAULT (_FPUEH_IF_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IF */
sahilmgandhi 18:6a4db94011d3 77 #define FPUEH_IF_FPIDC (0x1UL << 4) /**< FPU input denormal exception */
sahilmgandhi 18:6a4db94011d3 78 #define _FPUEH_IF_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
sahilmgandhi 18:6a4db94011d3 79 #define _FPUEH_IF_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
sahilmgandhi 18:6a4db94011d3 80 #define _FPUEH_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
sahilmgandhi 18:6a4db94011d3 81 #define FPUEH_IF_FPIDC_DEFAULT (_FPUEH_IF_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IF */
sahilmgandhi 18:6a4db94011d3 82 #define FPUEH_IF_FPIXC (0x1UL << 5) /**< FPU inexact exception */
sahilmgandhi 18:6a4db94011d3 83 #define _FPUEH_IF_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
sahilmgandhi 18:6a4db94011d3 84 #define _FPUEH_IF_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
sahilmgandhi 18:6a4db94011d3 85 #define _FPUEH_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
sahilmgandhi 18:6a4db94011d3 86 #define FPUEH_IF_FPIXC_DEFAULT (_FPUEH_IF_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IF */
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 /* Bit fields for FPUEH IFS */
sahilmgandhi 18:6a4db94011d3 89 #define _FPUEH_IFS_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFS */
sahilmgandhi 18:6a4db94011d3 90 #define _FPUEH_IFS_MASK 0x0000003FUL /**< Mask for FPUEH_IFS */
sahilmgandhi 18:6a4db94011d3 91 #define FPUEH_IFS_FPIOC (0x1UL << 0) /**< Set FPIOC Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 92 #define _FPUEH_IFS_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
sahilmgandhi 18:6a4db94011d3 93 #define _FPUEH_IFS_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
sahilmgandhi 18:6a4db94011d3 94 #define _FPUEH_IFS_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
sahilmgandhi 18:6a4db94011d3 95 #define FPUEH_IFS_FPIOC_DEFAULT (_FPUEH_IFS_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFS */
sahilmgandhi 18:6a4db94011d3 96 #define FPUEH_IFS_FPDZC (0x1UL << 1) /**< Set FPDZC Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 97 #define _FPUEH_IFS_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
sahilmgandhi 18:6a4db94011d3 98 #define _FPUEH_IFS_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
sahilmgandhi 18:6a4db94011d3 99 #define _FPUEH_IFS_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
sahilmgandhi 18:6a4db94011d3 100 #define FPUEH_IFS_FPDZC_DEFAULT (_FPUEH_IFS_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFS */
sahilmgandhi 18:6a4db94011d3 101 #define FPUEH_IFS_FPUFC (0x1UL << 2) /**< Set FPUFC Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 102 #define _FPUEH_IFS_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
sahilmgandhi 18:6a4db94011d3 103 #define _FPUEH_IFS_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
sahilmgandhi 18:6a4db94011d3 104 #define _FPUEH_IFS_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
sahilmgandhi 18:6a4db94011d3 105 #define FPUEH_IFS_FPUFC_DEFAULT (_FPUEH_IFS_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFS */
sahilmgandhi 18:6a4db94011d3 106 #define FPUEH_IFS_FPOFC (0x1UL << 3) /**< Set FPOFC Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 107 #define _FPUEH_IFS_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
sahilmgandhi 18:6a4db94011d3 108 #define _FPUEH_IFS_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
sahilmgandhi 18:6a4db94011d3 109 #define _FPUEH_IFS_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
sahilmgandhi 18:6a4db94011d3 110 #define FPUEH_IFS_FPOFC_DEFAULT (_FPUEH_IFS_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFS */
sahilmgandhi 18:6a4db94011d3 111 #define FPUEH_IFS_FPIDC (0x1UL << 4) /**< Set FPIDC Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 112 #define _FPUEH_IFS_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
sahilmgandhi 18:6a4db94011d3 113 #define _FPUEH_IFS_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
sahilmgandhi 18:6a4db94011d3 114 #define _FPUEH_IFS_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
sahilmgandhi 18:6a4db94011d3 115 #define FPUEH_IFS_FPIDC_DEFAULT (_FPUEH_IFS_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFS */
sahilmgandhi 18:6a4db94011d3 116 #define FPUEH_IFS_FPIXC (0x1UL << 5) /**< Set FPIXC Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 117 #define _FPUEH_IFS_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
sahilmgandhi 18:6a4db94011d3 118 #define _FPUEH_IFS_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
sahilmgandhi 18:6a4db94011d3 119 #define _FPUEH_IFS_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
sahilmgandhi 18:6a4db94011d3 120 #define FPUEH_IFS_FPIXC_DEFAULT (_FPUEH_IFS_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFS */
sahilmgandhi 18:6a4db94011d3 121
sahilmgandhi 18:6a4db94011d3 122 /* Bit fields for FPUEH IFC */
sahilmgandhi 18:6a4db94011d3 123 #define _FPUEH_IFC_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFC */
sahilmgandhi 18:6a4db94011d3 124 #define _FPUEH_IFC_MASK 0x0000003FUL /**< Mask for FPUEH_IFC */
sahilmgandhi 18:6a4db94011d3 125 #define FPUEH_IFC_FPIOC (0x1UL << 0) /**< Clear FPIOC Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 126 #define _FPUEH_IFC_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
sahilmgandhi 18:6a4db94011d3 127 #define _FPUEH_IFC_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
sahilmgandhi 18:6a4db94011d3 128 #define _FPUEH_IFC_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
sahilmgandhi 18:6a4db94011d3 129 #define FPUEH_IFC_FPIOC_DEFAULT (_FPUEH_IFC_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFC */
sahilmgandhi 18:6a4db94011d3 130 #define FPUEH_IFC_FPDZC (0x1UL << 1) /**< Clear FPDZC Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 131 #define _FPUEH_IFC_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
sahilmgandhi 18:6a4db94011d3 132 #define _FPUEH_IFC_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
sahilmgandhi 18:6a4db94011d3 133 #define _FPUEH_IFC_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
sahilmgandhi 18:6a4db94011d3 134 #define FPUEH_IFC_FPDZC_DEFAULT (_FPUEH_IFC_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFC */
sahilmgandhi 18:6a4db94011d3 135 #define FPUEH_IFC_FPUFC (0x1UL << 2) /**< Clear FPUFC Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 136 #define _FPUEH_IFC_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
sahilmgandhi 18:6a4db94011d3 137 #define _FPUEH_IFC_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
sahilmgandhi 18:6a4db94011d3 138 #define _FPUEH_IFC_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
sahilmgandhi 18:6a4db94011d3 139 #define FPUEH_IFC_FPUFC_DEFAULT (_FPUEH_IFC_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFC */
sahilmgandhi 18:6a4db94011d3 140 #define FPUEH_IFC_FPOFC (0x1UL << 3) /**< Clear FPOFC Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 141 #define _FPUEH_IFC_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
sahilmgandhi 18:6a4db94011d3 142 #define _FPUEH_IFC_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
sahilmgandhi 18:6a4db94011d3 143 #define _FPUEH_IFC_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
sahilmgandhi 18:6a4db94011d3 144 #define FPUEH_IFC_FPOFC_DEFAULT (_FPUEH_IFC_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFC */
sahilmgandhi 18:6a4db94011d3 145 #define FPUEH_IFC_FPIDC (0x1UL << 4) /**< Clear FPIDC Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 146 #define _FPUEH_IFC_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
sahilmgandhi 18:6a4db94011d3 147 #define _FPUEH_IFC_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
sahilmgandhi 18:6a4db94011d3 148 #define _FPUEH_IFC_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
sahilmgandhi 18:6a4db94011d3 149 #define FPUEH_IFC_FPIDC_DEFAULT (_FPUEH_IFC_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFC */
sahilmgandhi 18:6a4db94011d3 150 #define FPUEH_IFC_FPIXC (0x1UL << 5) /**< Clear FPIXC Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 151 #define _FPUEH_IFC_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
sahilmgandhi 18:6a4db94011d3 152 #define _FPUEH_IFC_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
sahilmgandhi 18:6a4db94011d3 153 #define _FPUEH_IFC_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
sahilmgandhi 18:6a4db94011d3 154 #define FPUEH_IFC_FPIXC_DEFAULT (_FPUEH_IFC_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFC */
sahilmgandhi 18:6a4db94011d3 155
sahilmgandhi 18:6a4db94011d3 156 /* Bit fields for FPUEH IEN */
sahilmgandhi 18:6a4db94011d3 157 #define _FPUEH_IEN_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IEN */
sahilmgandhi 18:6a4db94011d3 158 #define _FPUEH_IEN_MASK 0x0000003FUL /**< Mask for FPUEH_IEN */
sahilmgandhi 18:6a4db94011d3 159 #define FPUEH_IEN_FPIOC (0x1UL << 0) /**< FPIOC Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 160 #define _FPUEH_IEN_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
sahilmgandhi 18:6a4db94011d3 161 #define _FPUEH_IEN_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
sahilmgandhi 18:6a4db94011d3 162 #define _FPUEH_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
sahilmgandhi 18:6a4db94011d3 163 #define FPUEH_IEN_FPIOC_DEFAULT (_FPUEH_IEN_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IEN */
sahilmgandhi 18:6a4db94011d3 164 #define FPUEH_IEN_FPDZC (0x1UL << 1) /**< FPDZC Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 165 #define _FPUEH_IEN_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
sahilmgandhi 18:6a4db94011d3 166 #define _FPUEH_IEN_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
sahilmgandhi 18:6a4db94011d3 167 #define _FPUEH_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
sahilmgandhi 18:6a4db94011d3 168 #define FPUEH_IEN_FPDZC_DEFAULT (_FPUEH_IEN_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IEN */
sahilmgandhi 18:6a4db94011d3 169 #define FPUEH_IEN_FPUFC (0x1UL << 2) /**< FPUFC Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 170 #define _FPUEH_IEN_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
sahilmgandhi 18:6a4db94011d3 171 #define _FPUEH_IEN_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
sahilmgandhi 18:6a4db94011d3 172 #define _FPUEH_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
sahilmgandhi 18:6a4db94011d3 173 #define FPUEH_IEN_FPUFC_DEFAULT (_FPUEH_IEN_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IEN */
sahilmgandhi 18:6a4db94011d3 174 #define FPUEH_IEN_FPOFC (0x1UL << 3) /**< FPOFC Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 175 #define _FPUEH_IEN_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
sahilmgandhi 18:6a4db94011d3 176 #define _FPUEH_IEN_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
sahilmgandhi 18:6a4db94011d3 177 #define _FPUEH_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
sahilmgandhi 18:6a4db94011d3 178 #define FPUEH_IEN_FPOFC_DEFAULT (_FPUEH_IEN_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IEN */
sahilmgandhi 18:6a4db94011d3 179 #define FPUEH_IEN_FPIDC (0x1UL << 4) /**< FPIDC Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 180 #define _FPUEH_IEN_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
sahilmgandhi 18:6a4db94011d3 181 #define _FPUEH_IEN_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
sahilmgandhi 18:6a4db94011d3 182 #define _FPUEH_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
sahilmgandhi 18:6a4db94011d3 183 #define FPUEH_IEN_FPIDC_DEFAULT (_FPUEH_IEN_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IEN */
sahilmgandhi 18:6a4db94011d3 184 #define FPUEH_IEN_FPIXC (0x1UL << 5) /**< FPIXC Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 185 #define _FPUEH_IEN_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
sahilmgandhi 18:6a4db94011d3 186 #define _FPUEH_IEN_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
sahilmgandhi 18:6a4db94011d3 187 #define _FPUEH_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
sahilmgandhi 18:6a4db94011d3 188 #define FPUEH_IEN_FPIXC_DEFAULT (_FPUEH_IEN_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IEN */
sahilmgandhi 18:6a4db94011d3 189
sahilmgandhi 18:6a4db94011d3 190 /** @} End of group EFR32MG1P_FPUEH */
sahilmgandhi 18:6a4db94011d3 191 /** @} End of group Parts */
sahilmgandhi 18:6a4db94011d3 192