Mouse code for the MacroRat
mbed-dev/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/TOOLCHAIN_GCC_ARM/startup_efr32mg1p.S@18:6a4db94011d3, 2017-05-14 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sun May 14 23:18:57 2017 +0000
- Revision:
- 18:6a4db94011d3
Publishing again
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /* @file startup_efr32mg1p.S |
sahilmgandhi | 18:6a4db94011d3 | 2 | * @brief startup file for Silicon Labs EFR32MG1P devices. |
sahilmgandhi | 18:6a4db94011d3 | 3 | * For use with GCC for ARM Embedded Processors |
sahilmgandhi | 18:6a4db94011d3 | 4 | * @version 4.3.0 |
sahilmgandhi | 18:6a4db94011d3 | 5 | * Date: 12 June 2014 |
sahilmgandhi | 18:6a4db94011d3 | 6 | * |
sahilmgandhi | 18:6a4db94011d3 | 7 | */ |
sahilmgandhi | 18:6a4db94011d3 | 8 | /* Copyright (c) 2011 - 2014 ARM LIMITED |
sahilmgandhi | 18:6a4db94011d3 | 9 | |
sahilmgandhi | 18:6a4db94011d3 | 10 | All rights reserved. |
sahilmgandhi | 18:6a4db94011d3 | 11 | Redistribution and use in source and binary forms, with or without |
sahilmgandhi | 18:6a4db94011d3 | 12 | modification, are permitted provided that the following conditions are met: |
sahilmgandhi | 18:6a4db94011d3 | 13 | - Redistributions of source code must retain the above copyright |
sahilmgandhi | 18:6a4db94011d3 | 14 | notice, this list of conditions and the following disclaimer. |
sahilmgandhi | 18:6a4db94011d3 | 15 | - Redistributions in binary form must reproduce the above copyright |
sahilmgandhi | 18:6a4db94011d3 | 16 | notice, this list of conditions and the following disclaimer in the |
sahilmgandhi | 18:6a4db94011d3 | 17 | documentation and/or other materials provided with the distribution. |
sahilmgandhi | 18:6a4db94011d3 | 18 | - Neither the name of ARM nor the names of its contributors may be used |
sahilmgandhi | 18:6a4db94011d3 | 19 | to endorse or promote products derived from this software without |
sahilmgandhi | 18:6a4db94011d3 | 20 | specific prior written permission. |
sahilmgandhi | 18:6a4db94011d3 | 21 | * |
sahilmgandhi | 18:6a4db94011d3 | 22 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
sahilmgandhi | 18:6a4db94011d3 | 23 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
sahilmgandhi | 18:6a4db94011d3 | 24 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
sahilmgandhi | 18:6a4db94011d3 | 25 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
sahilmgandhi | 18:6a4db94011d3 | 26 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
sahilmgandhi | 18:6a4db94011d3 | 27 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
sahilmgandhi | 18:6a4db94011d3 | 28 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
sahilmgandhi | 18:6a4db94011d3 | 29 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
sahilmgandhi | 18:6a4db94011d3 | 30 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
sahilmgandhi | 18:6a4db94011d3 | 31 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
sahilmgandhi | 18:6a4db94011d3 | 32 | POSSIBILITY OF SUCH DAMAGE. |
sahilmgandhi | 18:6a4db94011d3 | 33 | ---------------------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 34 | |
sahilmgandhi | 18:6a4db94011d3 | 35 | .syntax unified |
sahilmgandhi | 18:6a4db94011d3 | 36 | .arch armv7-m |
sahilmgandhi | 18:6a4db94011d3 | 37 | .section .stack |
sahilmgandhi | 18:6a4db94011d3 | 38 | .align 3 |
sahilmgandhi | 18:6a4db94011d3 | 39 | #ifdef __STACK_SIZE |
sahilmgandhi | 18:6a4db94011d3 | 40 | .equ Stack_Size, __STACK_SIZE |
sahilmgandhi | 18:6a4db94011d3 | 41 | #else |
sahilmgandhi | 18:6a4db94011d3 | 42 | .equ Stack_Size, 0x00000400 |
sahilmgandhi | 18:6a4db94011d3 | 43 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 44 | .globl __StackTop |
sahilmgandhi | 18:6a4db94011d3 | 45 | .globl __StackLimit |
sahilmgandhi | 18:6a4db94011d3 | 46 | __StackLimit: |
sahilmgandhi | 18:6a4db94011d3 | 47 | .space Stack_Size |
sahilmgandhi | 18:6a4db94011d3 | 48 | .size __StackLimit, . - __StackLimit |
sahilmgandhi | 18:6a4db94011d3 | 49 | __StackTop: |
sahilmgandhi | 18:6a4db94011d3 | 50 | .size __StackTop, . - __StackTop |
sahilmgandhi | 18:6a4db94011d3 | 51 | |
sahilmgandhi | 18:6a4db94011d3 | 52 | .section .heap |
sahilmgandhi | 18:6a4db94011d3 | 53 | .align 3 |
sahilmgandhi | 18:6a4db94011d3 | 54 | #ifdef __HEAP_SIZE |
sahilmgandhi | 18:6a4db94011d3 | 55 | .equ Heap_Size, __HEAP_SIZE |
sahilmgandhi | 18:6a4db94011d3 | 56 | #else |
sahilmgandhi | 18:6a4db94011d3 | 57 | .equ Heap_Size, 0x00000F00 |
sahilmgandhi | 18:6a4db94011d3 | 58 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 59 | .globl __HeapBase |
sahilmgandhi | 18:6a4db94011d3 | 60 | .globl __HeapLimit |
sahilmgandhi | 18:6a4db94011d3 | 61 | __HeapBase: |
sahilmgandhi | 18:6a4db94011d3 | 62 | .if Heap_Size |
sahilmgandhi | 18:6a4db94011d3 | 63 | .space Heap_Size |
sahilmgandhi | 18:6a4db94011d3 | 64 | .endif |
sahilmgandhi | 18:6a4db94011d3 | 65 | .size __HeapBase, . - __HeapBase |
sahilmgandhi | 18:6a4db94011d3 | 66 | __HeapLimit: |
sahilmgandhi | 18:6a4db94011d3 | 67 | .size __HeapLimit, . - __HeapLimit |
sahilmgandhi | 18:6a4db94011d3 | 68 | |
sahilmgandhi | 18:6a4db94011d3 | 69 | .section .vectors |
sahilmgandhi | 18:6a4db94011d3 | 70 | .align 2 |
sahilmgandhi | 18:6a4db94011d3 | 71 | .globl __Vectors |
sahilmgandhi | 18:6a4db94011d3 | 72 | __Vectors: |
sahilmgandhi | 18:6a4db94011d3 | 73 | .long __StackTop /* Top of Stack */ |
sahilmgandhi | 18:6a4db94011d3 | 74 | .long Reset_Handler /* Reset Handler */ |
sahilmgandhi | 18:6a4db94011d3 | 75 | .long NMI_Handler /* NMI Handler */ |
sahilmgandhi | 18:6a4db94011d3 | 76 | .long HardFault_Handler /* Hard Fault Handler */ |
sahilmgandhi | 18:6a4db94011d3 | 77 | .long MemManage_Handler /* MPU Fault Handler */ |
sahilmgandhi | 18:6a4db94011d3 | 78 | .long BusFault_Handler /* Bus Fault Handler */ |
sahilmgandhi | 18:6a4db94011d3 | 79 | .long UsageFault_Handler /* Usage Fault Handler */ |
sahilmgandhi | 18:6a4db94011d3 | 80 | .long Default_Handler /* Reserved */ |
sahilmgandhi | 18:6a4db94011d3 | 81 | .long Default_Handler /* Reserved */ |
sahilmgandhi | 18:6a4db94011d3 | 82 | .long Default_Handler /* Reserved */ |
sahilmgandhi | 18:6a4db94011d3 | 83 | .long Default_Handler /* Reserved */ |
sahilmgandhi | 18:6a4db94011d3 | 84 | .long SVC_Handler /* SVCall Handler */ |
sahilmgandhi | 18:6a4db94011d3 | 85 | .long DebugMon_Handler /* Debug Monitor Handler */ |
sahilmgandhi | 18:6a4db94011d3 | 86 | .long Default_Handler /* Reserved */ |
sahilmgandhi | 18:6a4db94011d3 | 87 | .long PendSV_Handler /* PendSV Handler */ |
sahilmgandhi | 18:6a4db94011d3 | 88 | .long SysTick_Handler /* SysTick Handler */ |
sahilmgandhi | 18:6a4db94011d3 | 89 | |
sahilmgandhi | 18:6a4db94011d3 | 90 | /* External interrupts */ |
sahilmgandhi | 18:6a4db94011d3 | 91 | .long EMU_IRQHandler /* 0 - EMU */ |
sahilmgandhi | 18:6a4db94011d3 | 92 | .long FRC_PRI_IRQHandler /* 1 - FRC_PRI */ |
sahilmgandhi | 18:6a4db94011d3 | 93 | .long WDOG0_IRQHandler /* 2 - WDOG0 */ |
sahilmgandhi | 18:6a4db94011d3 | 94 | .long FRC_IRQHandler /* 3 - FRC */ |
sahilmgandhi | 18:6a4db94011d3 | 95 | .long MODEM_IRQHandler /* 4 - MODEM */ |
sahilmgandhi | 18:6a4db94011d3 | 96 | .long RAC_SEQ_IRQHandler /* 5 - RAC_SEQ */ |
sahilmgandhi | 18:6a4db94011d3 | 97 | .long RAC_RSM_IRQHandler /* 6 - RAC_RSM */ |
sahilmgandhi | 18:6a4db94011d3 | 98 | .long BUFC_IRQHandler /* 7 - BUFC */ |
sahilmgandhi | 18:6a4db94011d3 | 99 | .long LDMA_IRQHandler /* 8 - LDMA */ |
sahilmgandhi | 18:6a4db94011d3 | 100 | .long GPIO_EVEN_IRQHandler /* 9 - GPIO_EVEN */ |
sahilmgandhi | 18:6a4db94011d3 | 101 | .long TIMER0_IRQHandler /* 10 - TIMER0 */ |
sahilmgandhi | 18:6a4db94011d3 | 102 | .long USART0_RX_IRQHandler /* 11 - USART0_RX */ |
sahilmgandhi | 18:6a4db94011d3 | 103 | .long USART0_TX_IRQHandler /* 12 - USART0_TX */ |
sahilmgandhi | 18:6a4db94011d3 | 104 | .long ACMP0_IRQHandler /* 13 - ACMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 105 | .long ADC0_IRQHandler /* 14 - ADC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 106 | .long IDAC0_IRQHandler /* 15 - IDAC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 107 | .long I2C0_IRQHandler /* 16 - I2C0 */ |
sahilmgandhi | 18:6a4db94011d3 | 108 | .long GPIO_ODD_IRQHandler /* 17 - GPIO_ODD */ |
sahilmgandhi | 18:6a4db94011d3 | 109 | .long TIMER1_IRQHandler /* 18 - TIMER1 */ |
sahilmgandhi | 18:6a4db94011d3 | 110 | .long USART1_RX_IRQHandler /* 19 - USART1_RX */ |
sahilmgandhi | 18:6a4db94011d3 | 111 | .long USART1_TX_IRQHandler /* 20 - USART1_TX */ |
sahilmgandhi | 18:6a4db94011d3 | 112 | .long LEUART0_IRQHandler /* 21 - LEUART0 */ |
sahilmgandhi | 18:6a4db94011d3 | 113 | .long PCNT0_IRQHandler /* 22 - PCNT0 */ |
sahilmgandhi | 18:6a4db94011d3 | 114 | .long CMU_IRQHandler /* 23 - CMU */ |
sahilmgandhi | 18:6a4db94011d3 | 115 | .long MSC_IRQHandler /* 24 - MSC */ |
sahilmgandhi | 18:6a4db94011d3 | 116 | .long CRYPTO_IRQHandler /* 25 - CRYPTO */ |
sahilmgandhi | 18:6a4db94011d3 | 117 | .long LETIMER0_IRQHandler /* 26 - LETIMER0 */ |
sahilmgandhi | 18:6a4db94011d3 | 118 | .long AGC_IRQHandler /* 27 - AGC */ |
sahilmgandhi | 18:6a4db94011d3 | 119 | .long PROTIMER_IRQHandler /* 28 - PROTIMER */ |
sahilmgandhi | 18:6a4db94011d3 | 120 | .long RTCC_IRQHandler /* 29 - RTCC */ |
sahilmgandhi | 18:6a4db94011d3 | 121 | .long SYNTH_IRQHandler /* 30 - SYNTH */ |
sahilmgandhi | 18:6a4db94011d3 | 122 | .long CRYOTIMER_IRQHandler /* 31 - CRYOTIMER */ |
sahilmgandhi | 18:6a4db94011d3 | 123 | .long RFSENSE_IRQHandler /* 32 - RFSENSE */ |
sahilmgandhi | 18:6a4db94011d3 | 124 | .long FPUEH_IRQHandler /* 33 - FPUEH */ |
sahilmgandhi | 18:6a4db94011d3 | 125 | |
sahilmgandhi | 18:6a4db94011d3 | 126 | |
sahilmgandhi | 18:6a4db94011d3 | 127 | .size __Vectors, . - __Vectors |
sahilmgandhi | 18:6a4db94011d3 | 128 | |
sahilmgandhi | 18:6a4db94011d3 | 129 | .text |
sahilmgandhi | 18:6a4db94011d3 | 130 | .thumb |
sahilmgandhi | 18:6a4db94011d3 | 131 | .thumb_func |
sahilmgandhi | 18:6a4db94011d3 | 132 | .align 2 |
sahilmgandhi | 18:6a4db94011d3 | 133 | .globl Reset_Handler |
sahilmgandhi | 18:6a4db94011d3 | 134 | .type Reset_Handler, %function |
sahilmgandhi | 18:6a4db94011d3 | 135 | Reset_Handler: |
sahilmgandhi | 18:6a4db94011d3 | 136 | #ifndef __NO_SYSTEM_INIT |
sahilmgandhi | 18:6a4db94011d3 | 137 | ldr r0, =SystemInit |
sahilmgandhi | 18:6a4db94011d3 | 138 | blx r0 |
sahilmgandhi | 18:6a4db94011d3 | 139 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 140 | |
sahilmgandhi | 18:6a4db94011d3 | 141 | /* Firstly it copies data from read only memory to RAM. There are two schemes |
sahilmgandhi | 18:6a4db94011d3 | 142 | * to copy. One can copy more than one sections. Another can only copy |
sahilmgandhi | 18:6a4db94011d3 | 143 | * one section. The former scheme needs more instructions and read-only |
sahilmgandhi | 18:6a4db94011d3 | 144 | * data to implement than the latter. |
sahilmgandhi | 18:6a4db94011d3 | 145 | * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ |
sahilmgandhi | 18:6a4db94011d3 | 146 | |
sahilmgandhi | 18:6a4db94011d3 | 147 | #ifdef __STARTUP_COPY_MULTIPLE |
sahilmgandhi | 18:6a4db94011d3 | 148 | /* Multiple sections scheme. |
sahilmgandhi | 18:6a4db94011d3 | 149 | * |
sahilmgandhi | 18:6a4db94011d3 | 150 | * Between symbol address __copy_table_start__ and __copy_table_end__, |
sahilmgandhi | 18:6a4db94011d3 | 151 | * there are array of triplets, each of which specify: |
sahilmgandhi | 18:6a4db94011d3 | 152 | * offset 0: LMA of start of a section to copy from |
sahilmgandhi | 18:6a4db94011d3 | 153 | * offset 4: VMA of start of a section to copy to |
sahilmgandhi | 18:6a4db94011d3 | 154 | * offset 8: size of the section to copy. Must be multiply of 4 |
sahilmgandhi | 18:6a4db94011d3 | 155 | * |
sahilmgandhi | 18:6a4db94011d3 | 156 | * All addresses must be aligned to 4 bytes boundary. |
sahilmgandhi | 18:6a4db94011d3 | 157 | */ |
sahilmgandhi | 18:6a4db94011d3 | 158 | ldr r4, =__copy_table_start__ |
sahilmgandhi | 18:6a4db94011d3 | 159 | ldr r5, =__copy_table_end__ |
sahilmgandhi | 18:6a4db94011d3 | 160 | |
sahilmgandhi | 18:6a4db94011d3 | 161 | .L_loop0: |
sahilmgandhi | 18:6a4db94011d3 | 162 | cmp r4, r5 |
sahilmgandhi | 18:6a4db94011d3 | 163 | bge .L_loop0_done |
sahilmgandhi | 18:6a4db94011d3 | 164 | ldr r1, [r4] |
sahilmgandhi | 18:6a4db94011d3 | 165 | ldr r2, [r4, #4] |
sahilmgandhi | 18:6a4db94011d3 | 166 | ldr r3, [r4, #8] |
sahilmgandhi | 18:6a4db94011d3 | 167 | |
sahilmgandhi | 18:6a4db94011d3 | 168 | .L_loop0_0: |
sahilmgandhi | 18:6a4db94011d3 | 169 | subs r3, #4 |
sahilmgandhi | 18:6a4db94011d3 | 170 | ittt ge |
sahilmgandhi | 18:6a4db94011d3 | 171 | ldrge r0, [r1, r3] |
sahilmgandhi | 18:6a4db94011d3 | 172 | strge r0, [r2, r3] |
sahilmgandhi | 18:6a4db94011d3 | 173 | bge .L_loop0_0 |
sahilmgandhi | 18:6a4db94011d3 | 174 | |
sahilmgandhi | 18:6a4db94011d3 | 175 | adds r4, #12 |
sahilmgandhi | 18:6a4db94011d3 | 176 | b .L_loop0 |
sahilmgandhi | 18:6a4db94011d3 | 177 | |
sahilmgandhi | 18:6a4db94011d3 | 178 | .L_loop0_done: |
sahilmgandhi | 18:6a4db94011d3 | 179 | #else |
sahilmgandhi | 18:6a4db94011d3 | 180 | /* Single section scheme. |
sahilmgandhi | 18:6a4db94011d3 | 181 | * |
sahilmgandhi | 18:6a4db94011d3 | 182 | * The ranges of copy from/to are specified by following symbols |
sahilmgandhi | 18:6a4db94011d3 | 183 | * __etext: LMA of start of the section to copy from. Usually end of text |
sahilmgandhi | 18:6a4db94011d3 | 184 | * __data_start__: VMA of start of the section to copy to |
sahilmgandhi | 18:6a4db94011d3 | 185 | * __data_end__: VMA of end of the section to copy to |
sahilmgandhi | 18:6a4db94011d3 | 186 | * |
sahilmgandhi | 18:6a4db94011d3 | 187 | * All addresses must be aligned to 4 bytes boundary. |
sahilmgandhi | 18:6a4db94011d3 | 188 | */ |
sahilmgandhi | 18:6a4db94011d3 | 189 | ldr r1, =__etext |
sahilmgandhi | 18:6a4db94011d3 | 190 | ldr r2, =__data_start__ |
sahilmgandhi | 18:6a4db94011d3 | 191 | ldr r3, =__data_end__ |
sahilmgandhi | 18:6a4db94011d3 | 192 | |
sahilmgandhi | 18:6a4db94011d3 | 193 | .L_loop1: |
sahilmgandhi | 18:6a4db94011d3 | 194 | cmp r2, r3 |
sahilmgandhi | 18:6a4db94011d3 | 195 | ittt lt |
sahilmgandhi | 18:6a4db94011d3 | 196 | ldrlt r0, [r1], #4 |
sahilmgandhi | 18:6a4db94011d3 | 197 | strlt r0, [r2], #4 |
sahilmgandhi | 18:6a4db94011d3 | 198 | blt .L_loop1 |
sahilmgandhi | 18:6a4db94011d3 | 199 | #endif /*__STARTUP_COPY_MULTIPLE */ |
sahilmgandhi | 18:6a4db94011d3 | 200 | |
sahilmgandhi | 18:6a4db94011d3 | 201 | /* This part of work usually is done in C library startup code. Otherwise, |
sahilmgandhi | 18:6a4db94011d3 | 202 | * define this macro to enable it in this startup. |
sahilmgandhi | 18:6a4db94011d3 | 203 | * |
sahilmgandhi | 18:6a4db94011d3 | 204 | * There are two schemes too. One can clear multiple BSS sections. Another |
sahilmgandhi | 18:6a4db94011d3 | 205 | * can only clear one section. The former is more size expensive than the |
sahilmgandhi | 18:6a4db94011d3 | 206 | * latter. |
sahilmgandhi | 18:6a4db94011d3 | 207 | * |
sahilmgandhi | 18:6a4db94011d3 | 208 | * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. |
sahilmgandhi | 18:6a4db94011d3 | 209 | * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. |
sahilmgandhi | 18:6a4db94011d3 | 210 | */ |
sahilmgandhi | 18:6a4db94011d3 | 211 | #ifdef __STARTUP_CLEAR_BSS_MULTIPLE |
sahilmgandhi | 18:6a4db94011d3 | 212 | /* Multiple sections scheme. |
sahilmgandhi | 18:6a4db94011d3 | 213 | * |
sahilmgandhi | 18:6a4db94011d3 | 214 | * Between symbol address __copy_table_start__ and __copy_table_end__, |
sahilmgandhi | 18:6a4db94011d3 | 215 | * there are array of tuples specifying: |
sahilmgandhi | 18:6a4db94011d3 | 216 | * offset 0: Start of a BSS section |
sahilmgandhi | 18:6a4db94011d3 | 217 | * offset 4: Size of this BSS section. Must be multiply of 4 |
sahilmgandhi | 18:6a4db94011d3 | 218 | */ |
sahilmgandhi | 18:6a4db94011d3 | 219 | ldr r3, =__zero_table_start__ |
sahilmgandhi | 18:6a4db94011d3 | 220 | ldr r4, =__zero_table_end__ |
sahilmgandhi | 18:6a4db94011d3 | 221 | |
sahilmgandhi | 18:6a4db94011d3 | 222 | .L_loop2: |
sahilmgandhi | 18:6a4db94011d3 | 223 | cmp r3, r4 |
sahilmgandhi | 18:6a4db94011d3 | 224 | bge .L_loop2_done |
sahilmgandhi | 18:6a4db94011d3 | 225 | ldr r1, [r3] |
sahilmgandhi | 18:6a4db94011d3 | 226 | ldr r2, [r3, #4] |
sahilmgandhi | 18:6a4db94011d3 | 227 | movs r0, 0 |
sahilmgandhi | 18:6a4db94011d3 | 228 | |
sahilmgandhi | 18:6a4db94011d3 | 229 | .L_loop2_0: |
sahilmgandhi | 18:6a4db94011d3 | 230 | subs r2, #4 |
sahilmgandhi | 18:6a4db94011d3 | 231 | itt ge |
sahilmgandhi | 18:6a4db94011d3 | 232 | strge r0, [r1, r2] |
sahilmgandhi | 18:6a4db94011d3 | 233 | bge .L_loop2_0 |
sahilmgandhi | 18:6a4db94011d3 | 234 | adds r3, #8 |
sahilmgandhi | 18:6a4db94011d3 | 235 | b .L_loop2 |
sahilmgandhi | 18:6a4db94011d3 | 236 | .L_loop2_done: |
sahilmgandhi | 18:6a4db94011d3 | 237 | #elif defined (__STARTUP_CLEAR_BSS) |
sahilmgandhi | 18:6a4db94011d3 | 238 | /* Single BSS section scheme. |
sahilmgandhi | 18:6a4db94011d3 | 239 | * |
sahilmgandhi | 18:6a4db94011d3 | 240 | * The BSS section is specified by following symbols |
sahilmgandhi | 18:6a4db94011d3 | 241 | * __bss_start__: start of the BSS section. |
sahilmgandhi | 18:6a4db94011d3 | 242 | * __bss_end__: end of the BSS section. |
sahilmgandhi | 18:6a4db94011d3 | 243 | * |
sahilmgandhi | 18:6a4db94011d3 | 244 | * Both addresses must be aligned to 4 bytes boundary. |
sahilmgandhi | 18:6a4db94011d3 | 245 | */ |
sahilmgandhi | 18:6a4db94011d3 | 246 | ldr r1, =__bss_start__ |
sahilmgandhi | 18:6a4db94011d3 | 247 | ldr r2, =__bss_end__ |
sahilmgandhi | 18:6a4db94011d3 | 248 | |
sahilmgandhi | 18:6a4db94011d3 | 249 | movs r0, 0 |
sahilmgandhi | 18:6a4db94011d3 | 250 | .L_loop3: |
sahilmgandhi | 18:6a4db94011d3 | 251 | cmp r1, r2 |
sahilmgandhi | 18:6a4db94011d3 | 252 | itt lt |
sahilmgandhi | 18:6a4db94011d3 | 253 | strlt r0, [r1], #4 |
sahilmgandhi | 18:6a4db94011d3 | 254 | blt .L_loop3 |
sahilmgandhi | 18:6a4db94011d3 | 255 | #endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ |
sahilmgandhi | 18:6a4db94011d3 | 256 | |
sahilmgandhi | 18:6a4db94011d3 | 257 | #ifndef __START |
sahilmgandhi | 18:6a4db94011d3 | 258 | #define __START _start |
sahilmgandhi | 18:6a4db94011d3 | 259 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 260 | bl __START |
sahilmgandhi | 18:6a4db94011d3 | 261 | |
sahilmgandhi | 18:6a4db94011d3 | 262 | .pool |
sahilmgandhi | 18:6a4db94011d3 | 263 | .size Reset_Handler, . - Reset_Handler |
sahilmgandhi | 18:6a4db94011d3 | 264 | |
sahilmgandhi | 18:6a4db94011d3 | 265 | .align 1 |
sahilmgandhi | 18:6a4db94011d3 | 266 | .thumb_func |
sahilmgandhi | 18:6a4db94011d3 | 267 | .weak Default_Handler |
sahilmgandhi | 18:6a4db94011d3 | 268 | .type Default_Handler, %function |
sahilmgandhi | 18:6a4db94011d3 | 269 | Default_Handler: |
sahilmgandhi | 18:6a4db94011d3 | 270 | b . |
sahilmgandhi | 18:6a4db94011d3 | 271 | .size Default_Handler, . - Default_Handler |
sahilmgandhi | 18:6a4db94011d3 | 272 | |
sahilmgandhi | 18:6a4db94011d3 | 273 | /* Macro to define default handlers. Default handler |
sahilmgandhi | 18:6a4db94011d3 | 274 | * will be weak symbol and just dead loops. They can be |
sahilmgandhi | 18:6a4db94011d3 | 275 | * overwritten by other handlers */ |
sahilmgandhi | 18:6a4db94011d3 | 276 | .macro def_irq_handler handler_name |
sahilmgandhi | 18:6a4db94011d3 | 277 | .weak \handler_name |
sahilmgandhi | 18:6a4db94011d3 | 278 | .set \handler_name, Default_Handler |
sahilmgandhi | 18:6a4db94011d3 | 279 | .endm |
sahilmgandhi | 18:6a4db94011d3 | 280 | |
sahilmgandhi | 18:6a4db94011d3 | 281 | def_irq_handler NMI_Handler |
sahilmgandhi | 18:6a4db94011d3 | 282 | def_irq_handler HardFault_Handler |
sahilmgandhi | 18:6a4db94011d3 | 283 | def_irq_handler MemManage_Handler |
sahilmgandhi | 18:6a4db94011d3 | 284 | def_irq_handler BusFault_Handler |
sahilmgandhi | 18:6a4db94011d3 | 285 | def_irq_handler UsageFault_Handler |
sahilmgandhi | 18:6a4db94011d3 | 286 | def_irq_handler SVC_Handler |
sahilmgandhi | 18:6a4db94011d3 | 287 | def_irq_handler DebugMon_Handler |
sahilmgandhi | 18:6a4db94011d3 | 288 | def_irq_handler PendSV_Handler |
sahilmgandhi | 18:6a4db94011d3 | 289 | def_irq_handler SysTick_Handler |
sahilmgandhi | 18:6a4db94011d3 | 290 | |
sahilmgandhi | 18:6a4db94011d3 | 291 | |
sahilmgandhi | 18:6a4db94011d3 | 292 | def_irq_handler EMU_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 293 | def_irq_handler FRC_PRI_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 294 | def_irq_handler WDOG0_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 295 | def_irq_handler FRC_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 296 | def_irq_handler MODEM_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 297 | def_irq_handler RAC_SEQ_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 298 | def_irq_handler RAC_RSM_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 299 | def_irq_handler BUFC_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 300 | def_irq_handler LDMA_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 301 | def_irq_handler GPIO_EVEN_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 302 | def_irq_handler TIMER0_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 303 | def_irq_handler USART0_RX_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 304 | def_irq_handler USART0_TX_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 305 | def_irq_handler ACMP0_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 306 | def_irq_handler ADC0_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 307 | def_irq_handler IDAC0_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 308 | def_irq_handler I2C0_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 309 | def_irq_handler GPIO_ODD_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 310 | def_irq_handler TIMER1_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 311 | def_irq_handler USART1_RX_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 312 | def_irq_handler USART1_TX_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 313 | def_irq_handler LEUART0_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 314 | def_irq_handler PCNT0_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 315 | def_irq_handler CMU_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 316 | def_irq_handler MSC_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 317 | def_irq_handler CRYPTO_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 318 | def_irq_handler LETIMER0_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 319 | def_irq_handler AGC_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 320 | def_irq_handler PROTIMER_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 321 | def_irq_handler RTCC_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 322 | def_irq_handler SYNTH_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 323 | def_irq_handler CRYOTIMER_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 324 | def_irq_handler RFSENSE_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 325 | def_irq_handler FPUEH_IRQHandler |
sahilmgandhi | 18:6a4db94011d3 | 326 | |
sahilmgandhi | 18:6a4db94011d3 | 327 | .end |