MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/i2c_api.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 *******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * Copyright (c) 2015, STMicroelectronics
sahilmgandhi 18:6a4db94011d3 4 * All rights reserved.
sahilmgandhi 18:6a4db94011d3 5 *
sahilmgandhi 18:6a4db94011d3 6 * Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 7 * modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 10 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 12 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 13 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 15 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 16 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 17 *
sahilmgandhi 18:6a4db94011d3 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 28 *******************************************************************************
sahilmgandhi 18:6a4db94011d3 29 */
sahilmgandhi 18:6a4db94011d3 30
sahilmgandhi 18:6a4db94011d3 31
sahilmgandhi 18:6a4db94011d3 32 #include "mbed_assert.h"
sahilmgandhi 18:6a4db94011d3 33 #include "i2c_api.h"
sahilmgandhi 18:6a4db94011d3 34 #include "platform/mbed_wait_api.h"
sahilmgandhi 18:6a4db94011d3 35
sahilmgandhi 18:6a4db94011d3 36 #if DEVICE_I2C
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 39 #include "pinmap.h"
sahilmgandhi 18:6a4db94011d3 40 #include "PeripheralPins.h"
sahilmgandhi 18:6a4db94011d3 41 #include "i2c_device.h" // family specific defines
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43 #ifndef DEBUG_STDIO
sahilmgandhi 18:6a4db94011d3 44 # define DEBUG_STDIO 0
sahilmgandhi 18:6a4db94011d3 45 #endif
sahilmgandhi 18:6a4db94011d3 46
sahilmgandhi 18:6a4db94011d3 47 #if DEBUG_STDIO
sahilmgandhi 18:6a4db94011d3 48 # include <stdio.h>
sahilmgandhi 18:6a4db94011d3 49 # define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0)
sahilmgandhi 18:6a4db94011d3 50 #else
sahilmgandhi 18:6a4db94011d3 51 # define DEBUG_PRINTF(...) {}
sahilmgandhi 18:6a4db94011d3 52 #endif
sahilmgandhi 18:6a4db94011d3 53
sahilmgandhi 18:6a4db94011d3 54 #if DEVICE_I2C_ASYNCH
sahilmgandhi 18:6a4db94011d3 55 #define I2C_S(obj) (struct i2c_s *) (&((obj)->i2c))
sahilmgandhi 18:6a4db94011d3 56 #else
sahilmgandhi 18:6a4db94011d3 57 #define I2C_S(obj) (struct i2c_s *) (obj)
sahilmgandhi 18:6a4db94011d3 58 #endif
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 /* Family specific description for I2C */
sahilmgandhi 18:6a4db94011d3 61 #define I2C_NUM (5)
sahilmgandhi 18:6a4db94011d3 62 static I2C_HandleTypeDef* i2c_handles[I2C_NUM];
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 /* Timeout values are based on core clock and I2C clock.
sahilmgandhi 18:6a4db94011d3 65 The BYTE_TIMEOUT is computed as twice the number of cycles it would
sahilmgandhi 18:6a4db94011d3 66 take to send 10 bits over I2C. Most Flags should take less than that.
sahilmgandhi 18:6a4db94011d3 67 This is for immediate FLAG or ACK check.
sahilmgandhi 18:6a4db94011d3 68 */
sahilmgandhi 18:6a4db94011d3 69 #define BYTE_TIMEOUT ((SystemCoreClock / obj_s->hz) * 2 * 10)
sahilmgandhi 18:6a4db94011d3 70 /* Timeout values based on I2C clock.
sahilmgandhi 18:6a4db94011d3 71 The BYTE_TIMEOUT_US is computed as 3x the time in us it would
sahilmgandhi 18:6a4db94011d3 72 take to send 10 bits over I2C. Most Flags should take less than that.
sahilmgandhi 18:6a4db94011d3 73 This is for complete transfers check.
sahilmgandhi 18:6a4db94011d3 74 */
sahilmgandhi 18:6a4db94011d3 75 #define BYTE_TIMEOUT_US ((SystemCoreClock / obj_s->hz) * 3 * 10)
sahilmgandhi 18:6a4db94011d3 76 /* Timeout values for flags and events waiting loops. These timeouts are
sahilmgandhi 18:6a4db94011d3 77 not based on accurate values, they just guarantee that the application will
sahilmgandhi 18:6a4db94011d3 78 not remain stuck if the I2C communication is corrupted.
sahilmgandhi 18:6a4db94011d3 79 */
sahilmgandhi 18:6a4db94011d3 80 #define FLAG_TIMEOUT ((int)0x1000)
sahilmgandhi 18:6a4db94011d3 81
sahilmgandhi 18:6a4db94011d3 82 /* GENERIC INIT and HELPERS FUNCTIONS */
sahilmgandhi 18:6a4db94011d3 83
sahilmgandhi 18:6a4db94011d3 84 #if defined(I2C1_BASE)
sahilmgandhi 18:6a4db94011d3 85 static void i2c1_irq(void)
sahilmgandhi 18:6a4db94011d3 86 {
sahilmgandhi 18:6a4db94011d3 87 I2C_HandleTypeDef * handle = i2c_handles[0];
sahilmgandhi 18:6a4db94011d3 88 HAL_I2C_EV_IRQHandler(handle);
sahilmgandhi 18:6a4db94011d3 89 HAL_I2C_ER_IRQHandler(handle);
sahilmgandhi 18:6a4db94011d3 90 }
sahilmgandhi 18:6a4db94011d3 91 #endif
sahilmgandhi 18:6a4db94011d3 92 #if defined(I2C2_BASE)
sahilmgandhi 18:6a4db94011d3 93 static void i2c2_irq(void)
sahilmgandhi 18:6a4db94011d3 94 {
sahilmgandhi 18:6a4db94011d3 95 I2C_HandleTypeDef * handle = i2c_handles[1];
sahilmgandhi 18:6a4db94011d3 96 HAL_I2C_EV_IRQHandler(handle);
sahilmgandhi 18:6a4db94011d3 97 HAL_I2C_ER_IRQHandler(handle);
sahilmgandhi 18:6a4db94011d3 98 }
sahilmgandhi 18:6a4db94011d3 99 #endif
sahilmgandhi 18:6a4db94011d3 100 #if defined(I2C3_BASE)
sahilmgandhi 18:6a4db94011d3 101 static void i2c3_irq(void)
sahilmgandhi 18:6a4db94011d3 102 {
sahilmgandhi 18:6a4db94011d3 103 I2C_HandleTypeDef * handle = i2c_handles[2];
sahilmgandhi 18:6a4db94011d3 104 HAL_I2C_EV_IRQHandler(handle);
sahilmgandhi 18:6a4db94011d3 105 HAL_I2C_ER_IRQHandler(handle);
sahilmgandhi 18:6a4db94011d3 106 }
sahilmgandhi 18:6a4db94011d3 107 #endif
sahilmgandhi 18:6a4db94011d3 108 #if defined(I2C4_BASE)
sahilmgandhi 18:6a4db94011d3 109 static void i2c4_irq(void)
sahilmgandhi 18:6a4db94011d3 110 {
sahilmgandhi 18:6a4db94011d3 111 I2C_HandleTypeDef * handle = i2c_handles[3];
sahilmgandhi 18:6a4db94011d3 112 HAL_I2C_EV_IRQHandler(handle);
sahilmgandhi 18:6a4db94011d3 113 HAL_I2C_ER_IRQHandler(handle);
sahilmgandhi 18:6a4db94011d3 114 }
sahilmgandhi 18:6a4db94011d3 115 #endif
sahilmgandhi 18:6a4db94011d3 116 #if defined(FMPI2C1_BASE)
sahilmgandhi 18:6a4db94011d3 117 static void i2c5_irq(void)
sahilmgandhi 18:6a4db94011d3 118 {
sahilmgandhi 18:6a4db94011d3 119 I2C_HandleTypeDef * handle = i2c_handles[4];
sahilmgandhi 18:6a4db94011d3 120 HAL_I2C_EV_IRQHandler(handle);
sahilmgandhi 18:6a4db94011d3 121 HAL_I2C_ER_IRQHandler(handle);
sahilmgandhi 18:6a4db94011d3 122 }
sahilmgandhi 18:6a4db94011d3 123 #endif
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125 void i2c_ev_err_enable(i2c_t *obj, uint32_t handler) {
sahilmgandhi 18:6a4db94011d3 126 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 127 IRQn_Type irq_event_n = obj_s->event_i2cIRQ;
sahilmgandhi 18:6a4db94011d3 128 IRQn_Type irq_error_n = obj_s->error_i2cIRQ;
sahilmgandhi 18:6a4db94011d3 129 /* default prio in master case is set to 2 */
sahilmgandhi 18:6a4db94011d3 130 uint32_t prio = 2;
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132 /* Set up ITs using IRQ and handler tables */
sahilmgandhi 18:6a4db94011d3 133 NVIC_SetVector(irq_event_n, handler);
sahilmgandhi 18:6a4db94011d3 134 NVIC_SetVector(irq_error_n, handler);
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 #if DEVICE_I2CSLAVE
sahilmgandhi 18:6a4db94011d3 137 /* Set higher priority to slave device than master.
sahilmgandhi 18:6a4db94011d3 138 * In case a device makes use of both master and slave, the
sahilmgandhi 18:6a4db94011d3 139 * slave needs higher responsiveness.
sahilmgandhi 18:6a4db94011d3 140 */
sahilmgandhi 18:6a4db94011d3 141 if (obj_s->slave) {
sahilmgandhi 18:6a4db94011d3 142 prio = 1;
sahilmgandhi 18:6a4db94011d3 143 }
sahilmgandhi 18:6a4db94011d3 144 #endif
sahilmgandhi 18:6a4db94011d3 145
sahilmgandhi 18:6a4db94011d3 146 NVIC_SetPriority(irq_event_n, prio);
sahilmgandhi 18:6a4db94011d3 147 NVIC_SetPriority(irq_error_n, prio);
sahilmgandhi 18:6a4db94011d3 148 NVIC_EnableIRQ(irq_event_n);
sahilmgandhi 18:6a4db94011d3 149 NVIC_EnableIRQ(irq_error_n);
sahilmgandhi 18:6a4db94011d3 150 }
sahilmgandhi 18:6a4db94011d3 151
sahilmgandhi 18:6a4db94011d3 152 void i2c_ev_err_disable(i2c_t *obj) {
sahilmgandhi 18:6a4db94011d3 153 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 154 IRQn_Type irq_event_n = obj_s->event_i2cIRQ;
sahilmgandhi 18:6a4db94011d3 155 IRQn_Type irq_error_n = obj_s->error_i2cIRQ;
sahilmgandhi 18:6a4db94011d3 156
sahilmgandhi 18:6a4db94011d3 157 HAL_NVIC_DisableIRQ(irq_event_n);
sahilmgandhi 18:6a4db94011d3 158 HAL_NVIC_DisableIRQ(irq_error_n);
sahilmgandhi 18:6a4db94011d3 159 }
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161 uint32_t i2c_get_irq_handler(i2c_t *obj)
sahilmgandhi 18:6a4db94011d3 162 {
sahilmgandhi 18:6a4db94011d3 163 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 164 I2C_HandleTypeDef *handle = &(obj_s->handle);
sahilmgandhi 18:6a4db94011d3 165 uint32_t handler = 0;
sahilmgandhi 18:6a4db94011d3 166
sahilmgandhi 18:6a4db94011d3 167 switch (obj_s->index) {
sahilmgandhi 18:6a4db94011d3 168 #if defined(I2C1_BASE)
sahilmgandhi 18:6a4db94011d3 169 case 0:
sahilmgandhi 18:6a4db94011d3 170 handler = (uint32_t)&i2c1_irq;
sahilmgandhi 18:6a4db94011d3 171 break;
sahilmgandhi 18:6a4db94011d3 172 #endif
sahilmgandhi 18:6a4db94011d3 173 #if defined(I2C2_BASE)
sahilmgandhi 18:6a4db94011d3 174 case 1:
sahilmgandhi 18:6a4db94011d3 175 handler = (uint32_t)&i2c2_irq;
sahilmgandhi 18:6a4db94011d3 176 break;
sahilmgandhi 18:6a4db94011d3 177 #endif
sahilmgandhi 18:6a4db94011d3 178 #if defined(I2C3_BASE)
sahilmgandhi 18:6a4db94011d3 179 case 2:
sahilmgandhi 18:6a4db94011d3 180 handler = (uint32_t)&i2c3_irq;
sahilmgandhi 18:6a4db94011d3 181 break;
sahilmgandhi 18:6a4db94011d3 182 #endif
sahilmgandhi 18:6a4db94011d3 183 #if defined(I2C4_BASE)
sahilmgandhi 18:6a4db94011d3 184 case 3:
sahilmgandhi 18:6a4db94011d3 185 handler = (uint32_t)&i2c4_irq;
sahilmgandhi 18:6a4db94011d3 186 break;
sahilmgandhi 18:6a4db94011d3 187 #endif
sahilmgandhi 18:6a4db94011d3 188 #if defined(FMPI2C1_BASE)
sahilmgandhi 18:6a4db94011d3 189 case 4:
sahilmgandhi 18:6a4db94011d3 190 handler = (uint32_t)&i2c5_irq;
sahilmgandhi 18:6a4db94011d3 191 break;
sahilmgandhi 18:6a4db94011d3 192 #endif
sahilmgandhi 18:6a4db94011d3 193 }
sahilmgandhi 18:6a4db94011d3 194
sahilmgandhi 18:6a4db94011d3 195 i2c_handles[obj_s->index] = handle;
sahilmgandhi 18:6a4db94011d3 196 return handler;
sahilmgandhi 18:6a4db94011d3 197 }
sahilmgandhi 18:6a4db94011d3 198
sahilmgandhi 18:6a4db94011d3 199 void i2c_hw_reset(i2c_t *obj) {
sahilmgandhi 18:6a4db94011d3 200 int timeout;
sahilmgandhi 18:6a4db94011d3 201 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 202 I2C_HandleTypeDef *handle = &(obj_s->handle);
sahilmgandhi 18:6a4db94011d3 203
sahilmgandhi 18:6a4db94011d3 204 handle->Instance = (I2C_TypeDef *)(obj_s->i2c);
sahilmgandhi 18:6a4db94011d3 205
sahilmgandhi 18:6a4db94011d3 206 // wait before reset
sahilmgandhi 18:6a4db94011d3 207 timeout = BYTE_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 208 while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (--timeout != 0));
sahilmgandhi 18:6a4db94011d3 209 #if defined I2C1_BASE
sahilmgandhi 18:6a4db94011d3 210 if (obj_s->i2c == I2C_1) {
sahilmgandhi 18:6a4db94011d3 211 __HAL_RCC_I2C1_FORCE_RESET();
sahilmgandhi 18:6a4db94011d3 212 __HAL_RCC_I2C1_RELEASE_RESET();
sahilmgandhi 18:6a4db94011d3 213 }
sahilmgandhi 18:6a4db94011d3 214 #endif
sahilmgandhi 18:6a4db94011d3 215 #if defined I2C2_BASE
sahilmgandhi 18:6a4db94011d3 216 if (obj_s->i2c == I2C_2) {
sahilmgandhi 18:6a4db94011d3 217 __HAL_RCC_I2C2_FORCE_RESET();
sahilmgandhi 18:6a4db94011d3 218 __HAL_RCC_I2C2_RELEASE_RESET();
sahilmgandhi 18:6a4db94011d3 219 }
sahilmgandhi 18:6a4db94011d3 220 #endif
sahilmgandhi 18:6a4db94011d3 221 #if defined I2C3_BASE
sahilmgandhi 18:6a4db94011d3 222 if (obj_s->i2c == I2C_3) {
sahilmgandhi 18:6a4db94011d3 223 __HAL_RCC_I2C3_FORCE_RESET();
sahilmgandhi 18:6a4db94011d3 224 __HAL_RCC_I2C3_RELEASE_RESET();
sahilmgandhi 18:6a4db94011d3 225 }
sahilmgandhi 18:6a4db94011d3 226 #endif
sahilmgandhi 18:6a4db94011d3 227 #if defined I2C4_BASE
sahilmgandhi 18:6a4db94011d3 228 if (obj_s->i2c == I2C_4) {
sahilmgandhi 18:6a4db94011d3 229 __HAL_RCC_I2C4_FORCE_RESET();
sahilmgandhi 18:6a4db94011d3 230 __HAL_RCC_I2C4_RELEASE_RESET();
sahilmgandhi 18:6a4db94011d3 231 }
sahilmgandhi 18:6a4db94011d3 232 #endif
sahilmgandhi 18:6a4db94011d3 233 #if defined FMPI2C1_BASE
sahilmgandhi 18:6a4db94011d3 234 if (obj_s->i2c == FMPI2C_1) {
sahilmgandhi 18:6a4db94011d3 235 __HAL_RCC_FMPI2C1_FORCE_RESET();
sahilmgandhi 18:6a4db94011d3 236 __HAL_RCC_FMPI2C1_RELEASE_RESET();
sahilmgandhi 18:6a4db94011d3 237 }
sahilmgandhi 18:6a4db94011d3 238 #endif
sahilmgandhi 18:6a4db94011d3 239 }
sahilmgandhi 18:6a4db94011d3 240
sahilmgandhi 18:6a4db94011d3 241 void i2c_sw_reset(i2c_t *obj)
sahilmgandhi 18:6a4db94011d3 242 {
sahilmgandhi 18:6a4db94011d3 243 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 244 I2C_HandleTypeDef *handle = &(obj_s->handle);
sahilmgandhi 18:6a4db94011d3 245 /* SW reset procedure:
sahilmgandhi 18:6a4db94011d3 246 * PE must be kept low during at least 3 APB clock cycles
sahilmgandhi 18:6a4db94011d3 247 * in order to perform the software reset.
sahilmgandhi 18:6a4db94011d3 248 * This is ensured by writing the following software sequence:
sahilmgandhi 18:6a4db94011d3 249 * - Write PE=0
sahilmgandhi 18:6a4db94011d3 250 * - Check PE=0
sahilmgandhi 18:6a4db94011d3 251 * - Write PE=1.
sahilmgandhi 18:6a4db94011d3 252 */
sahilmgandhi 18:6a4db94011d3 253 handle->Instance->CR1 &= ~I2C_CR1_PE;
sahilmgandhi 18:6a4db94011d3 254 while(handle->Instance->CR1 & I2C_CR1_PE);
sahilmgandhi 18:6a4db94011d3 255 handle->Instance->CR1 |= I2C_CR1_PE;
sahilmgandhi 18:6a4db94011d3 256 }
sahilmgandhi 18:6a4db94011d3 257
sahilmgandhi 18:6a4db94011d3 258 void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
sahilmgandhi 18:6a4db94011d3 259
sahilmgandhi 18:6a4db94011d3 260 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 261
sahilmgandhi 18:6a4db94011d3 262 // Determine the I2C to use
sahilmgandhi 18:6a4db94011d3 263 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
sahilmgandhi 18:6a4db94011d3 264 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
sahilmgandhi 18:6a4db94011d3 265 obj_s->sda = sda;
sahilmgandhi 18:6a4db94011d3 266 obj_s->scl = scl;
sahilmgandhi 18:6a4db94011d3 267
sahilmgandhi 18:6a4db94011d3 268 obj_s->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
sahilmgandhi 18:6a4db94011d3 269 MBED_ASSERT(obj_s->i2c != (I2CName)NC);
sahilmgandhi 18:6a4db94011d3 270
sahilmgandhi 18:6a4db94011d3 271 #if defined I2C1_BASE
sahilmgandhi 18:6a4db94011d3 272 // Enable I2C1 clock and pinout if not done
sahilmgandhi 18:6a4db94011d3 273 if (obj_s->i2c == I2C_1) {
sahilmgandhi 18:6a4db94011d3 274 obj_s->index = 0;
sahilmgandhi 18:6a4db94011d3 275 __HAL_RCC_I2C1_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 276 // Configure I2C pins
sahilmgandhi 18:6a4db94011d3 277 pinmap_pinout(sda, PinMap_I2C_SDA);
sahilmgandhi 18:6a4db94011d3 278 pinmap_pinout(scl, PinMap_I2C_SCL);
sahilmgandhi 18:6a4db94011d3 279 pin_mode(sda, OpenDrainPullUp);
sahilmgandhi 18:6a4db94011d3 280 pin_mode(scl, OpenDrainPullUp);
sahilmgandhi 18:6a4db94011d3 281 obj_s->event_i2cIRQ = I2C1_EV_IRQn;
sahilmgandhi 18:6a4db94011d3 282 obj_s->error_i2cIRQ = I2C1_ER_IRQn;
sahilmgandhi 18:6a4db94011d3 283 }
sahilmgandhi 18:6a4db94011d3 284 #endif
sahilmgandhi 18:6a4db94011d3 285 #if defined I2C2_BASE
sahilmgandhi 18:6a4db94011d3 286 // Enable I2C2 clock and pinout if not done
sahilmgandhi 18:6a4db94011d3 287 if (obj_s->i2c == I2C_2) {
sahilmgandhi 18:6a4db94011d3 288 obj_s->index = 1;
sahilmgandhi 18:6a4db94011d3 289 __HAL_RCC_I2C2_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 290 // Configure I2C pins
sahilmgandhi 18:6a4db94011d3 291 pinmap_pinout(sda, PinMap_I2C_SDA);
sahilmgandhi 18:6a4db94011d3 292 pinmap_pinout(scl, PinMap_I2C_SCL);
sahilmgandhi 18:6a4db94011d3 293 pin_mode(sda, OpenDrainPullUp);
sahilmgandhi 18:6a4db94011d3 294 pin_mode(scl, OpenDrainPullUp);
sahilmgandhi 18:6a4db94011d3 295 obj_s->event_i2cIRQ = I2C2_EV_IRQn;
sahilmgandhi 18:6a4db94011d3 296 obj_s->error_i2cIRQ = I2C2_ER_IRQn;
sahilmgandhi 18:6a4db94011d3 297 }
sahilmgandhi 18:6a4db94011d3 298 #endif
sahilmgandhi 18:6a4db94011d3 299 #if defined I2C3_BASE
sahilmgandhi 18:6a4db94011d3 300 // Enable I2C3 clock and pinout if not done
sahilmgandhi 18:6a4db94011d3 301 if (obj_s->i2c == I2C_3) {
sahilmgandhi 18:6a4db94011d3 302 obj_s->index = 2;
sahilmgandhi 18:6a4db94011d3 303 __HAL_RCC_I2C3_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 304 // Configure I2C pins
sahilmgandhi 18:6a4db94011d3 305 pinmap_pinout(sda, PinMap_I2C_SDA);
sahilmgandhi 18:6a4db94011d3 306 pinmap_pinout(scl, PinMap_I2C_SCL);
sahilmgandhi 18:6a4db94011d3 307 pin_mode(sda, OpenDrainPullUp);
sahilmgandhi 18:6a4db94011d3 308 pin_mode(scl, OpenDrainPullUp);
sahilmgandhi 18:6a4db94011d3 309 obj_s->event_i2cIRQ = I2C3_EV_IRQn;
sahilmgandhi 18:6a4db94011d3 310 obj_s->error_i2cIRQ = I2C3_ER_IRQn;
sahilmgandhi 18:6a4db94011d3 311 }
sahilmgandhi 18:6a4db94011d3 312 #endif
sahilmgandhi 18:6a4db94011d3 313 #if defined I2C4_BASE
sahilmgandhi 18:6a4db94011d3 314 // Enable I2C3 clock and pinout if not done
sahilmgandhi 18:6a4db94011d3 315 if (obj_s->i2c == I2C_4) {
sahilmgandhi 18:6a4db94011d3 316 obj_s->index = 3;
sahilmgandhi 18:6a4db94011d3 317 __HAL_RCC_I2C4_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 318 // Configure I2C pins
sahilmgandhi 18:6a4db94011d3 319 pinmap_pinout(sda, PinMap_I2C_SDA);
sahilmgandhi 18:6a4db94011d3 320 pinmap_pinout(scl, PinMap_I2C_SCL);
sahilmgandhi 18:6a4db94011d3 321 pin_mode(sda, OpenDrainPullUp);
sahilmgandhi 18:6a4db94011d3 322 pin_mode(scl, OpenDrainPullUp);
sahilmgandhi 18:6a4db94011d3 323 obj_s->event_i2cIRQ = I2C4_EV_IRQn;
sahilmgandhi 18:6a4db94011d3 324 obj_s->error_i2cIRQ = I2C4_ER_IRQn;
sahilmgandhi 18:6a4db94011d3 325 }
sahilmgandhi 18:6a4db94011d3 326 #endif
sahilmgandhi 18:6a4db94011d3 327 #if defined FMPI2C1_BASE
sahilmgandhi 18:6a4db94011d3 328 // Enable I2C3 clock and pinout if not done
sahilmgandhi 18:6a4db94011d3 329 if (obj_s->i2c == FMPI2C_1) {
sahilmgandhi 18:6a4db94011d3 330 obj_s->index = 4;
sahilmgandhi 18:6a4db94011d3 331 __HAL_RCC_FMPI2C1_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 332 // Configure I2C pins
sahilmgandhi 18:6a4db94011d3 333 pinmap_pinout(sda, PinMap_I2C_SDA);
sahilmgandhi 18:6a4db94011d3 334 pinmap_pinout(scl, PinMap_I2C_SCL);
sahilmgandhi 18:6a4db94011d3 335 pin_mode(sda, OpenDrainPullUp);
sahilmgandhi 18:6a4db94011d3 336 pin_mode(scl, OpenDrainPullUp);
sahilmgandhi 18:6a4db94011d3 337 obj_s->event_i2cIRQ = FMPI2C1_EV_IRQn;
sahilmgandhi 18:6a4db94011d3 338 obj_s->error_i2cIRQ = FMPI2C1_ER_IRQn;
sahilmgandhi 18:6a4db94011d3 339 }
sahilmgandhi 18:6a4db94011d3 340 #endif
sahilmgandhi 18:6a4db94011d3 341
sahilmgandhi 18:6a4db94011d3 342 // I2C configuration
sahilmgandhi 18:6a4db94011d3 343 // Default hz value used for timeout computation
sahilmgandhi 18:6a4db94011d3 344 if(!obj_s->hz)
sahilmgandhi 18:6a4db94011d3 345 obj_s->hz = 100000; // 100 kHz per default
sahilmgandhi 18:6a4db94011d3 346
sahilmgandhi 18:6a4db94011d3 347 // Reset to clear pending flags if any
sahilmgandhi 18:6a4db94011d3 348 i2c_hw_reset(obj);
sahilmgandhi 18:6a4db94011d3 349 i2c_frequency(obj, obj_s->hz );
sahilmgandhi 18:6a4db94011d3 350
sahilmgandhi 18:6a4db94011d3 351 #if DEVICE_I2CSLAVE
sahilmgandhi 18:6a4db94011d3 352 // I2C master by default
sahilmgandhi 18:6a4db94011d3 353 obj_s->slave = 0;
sahilmgandhi 18:6a4db94011d3 354 obj_s->pending_slave_tx_master_rx = 0;
sahilmgandhi 18:6a4db94011d3 355 obj_s->pending_slave_rx_maxter_tx = 0;
sahilmgandhi 18:6a4db94011d3 356 #endif
sahilmgandhi 18:6a4db94011d3 357
sahilmgandhi 18:6a4db94011d3 358 // I2C Xfer operation init
sahilmgandhi 18:6a4db94011d3 359 obj_s->event = 0;
sahilmgandhi 18:6a4db94011d3 360 obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
sahilmgandhi 18:6a4db94011d3 361 #ifdef I2C_IP_VERSION_V2
sahilmgandhi 18:6a4db94011d3 362 obj_s->pending_start = 0;
sahilmgandhi 18:6a4db94011d3 363 #endif
sahilmgandhi 18:6a4db94011d3 364 }
sahilmgandhi 18:6a4db94011d3 365
sahilmgandhi 18:6a4db94011d3 366 void i2c_frequency(i2c_t *obj, int hz)
sahilmgandhi 18:6a4db94011d3 367 {
sahilmgandhi 18:6a4db94011d3 368 int timeout;
sahilmgandhi 18:6a4db94011d3 369 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 370 I2C_HandleTypeDef *handle = &(obj_s->handle);
sahilmgandhi 18:6a4db94011d3 371
sahilmgandhi 18:6a4db94011d3 372 // wait before init
sahilmgandhi 18:6a4db94011d3 373 timeout = BYTE_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 374 while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (--timeout != 0));
sahilmgandhi 18:6a4db94011d3 375
sahilmgandhi 18:6a4db94011d3 376 #ifdef I2C_IP_VERSION_V1
sahilmgandhi 18:6a4db94011d3 377 handle->Init.ClockSpeed = hz;
sahilmgandhi 18:6a4db94011d3 378 handle->Init.DutyCycle = I2C_DUTYCYCLE_2;
sahilmgandhi 18:6a4db94011d3 379 #endif
sahilmgandhi 18:6a4db94011d3 380 #ifdef I2C_IP_VERSION_V2
sahilmgandhi 18:6a4db94011d3 381 /* Only predefined timing for below frequencies are supported */
sahilmgandhi 18:6a4db94011d3 382 MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000));
sahilmgandhi 18:6a4db94011d3 383 handle->Init.Timing = get_i2c_timing(hz);
sahilmgandhi 18:6a4db94011d3 384
sahilmgandhi 18:6a4db94011d3 385 // Enable the Fast Mode Plus capability
sahilmgandhi 18:6a4db94011d3 386 if (hz == 1000000) {
sahilmgandhi 18:6a4db94011d3 387 #if defined(I2C1_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C1)
sahilmgandhi 18:6a4db94011d3 388 if (obj_s->i2c == I2C_1) {
sahilmgandhi 18:6a4db94011d3 389 HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C1);
sahilmgandhi 18:6a4db94011d3 390 }
sahilmgandhi 18:6a4db94011d3 391 #endif
sahilmgandhi 18:6a4db94011d3 392 #if defined(I2C2_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C2)
sahilmgandhi 18:6a4db94011d3 393 if (obj_s->i2c == I2C_2) {
sahilmgandhi 18:6a4db94011d3 394 HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C2);
sahilmgandhi 18:6a4db94011d3 395 }
sahilmgandhi 18:6a4db94011d3 396 #endif
sahilmgandhi 18:6a4db94011d3 397 #if defined(I2C3_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C3)
sahilmgandhi 18:6a4db94011d3 398 if (obj_s->i2c == I2C_3) {
sahilmgandhi 18:6a4db94011d3 399 HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C3);
sahilmgandhi 18:6a4db94011d3 400 }
sahilmgandhi 18:6a4db94011d3 401 #endif
sahilmgandhi 18:6a4db94011d3 402 #if defined(I2C4_BASE) && defined(__HAL_SYSCFG_FASTMODEPLUS_ENABLE) && defined (I2C_FASTMODEPLUS_I2C4)
sahilmgandhi 18:6a4db94011d3 403 if (obj_s->i2c == I2C_4) {
sahilmgandhi 18:6a4db94011d3 404 HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C4);
sahilmgandhi 18:6a4db94011d3 405 }
sahilmgandhi 18:6a4db94011d3 406 #endif
sahilmgandhi 18:6a4db94011d3 407 }
sahilmgandhi 18:6a4db94011d3 408 #endif //I2C_IP_VERSION_V2
sahilmgandhi 18:6a4db94011d3 409
sahilmgandhi 18:6a4db94011d3 410 /*##-1- Configure the I2C clock source. The clock is derived from the SYSCLK #*/
sahilmgandhi 18:6a4db94011d3 411 #if defined(I2C1_BASE) && defined (__HAL_RCC_I2C1_CONFIG)
sahilmgandhi 18:6a4db94011d3 412 if (obj_s->i2c == I2C_1) {
sahilmgandhi 18:6a4db94011d3 413 __HAL_RCC_I2C1_CONFIG(I2CAPI_I2C1_CLKSRC);
sahilmgandhi 18:6a4db94011d3 414 }
sahilmgandhi 18:6a4db94011d3 415 #endif
sahilmgandhi 18:6a4db94011d3 416 #if defined(I2C2_BASE) && defined(__HAL_RCC_I2C2_CONFIG)
sahilmgandhi 18:6a4db94011d3 417 if (obj_s->i2c == I2C_2) {
sahilmgandhi 18:6a4db94011d3 418 __HAL_RCC_I2C2_CONFIG(I2CAPI_I2C2_CLKSRC);
sahilmgandhi 18:6a4db94011d3 419 }
sahilmgandhi 18:6a4db94011d3 420 #endif
sahilmgandhi 18:6a4db94011d3 421 #if defined(I2C3_BASE) && defined(__HAL_RCC_I2C3_CONFIG)
sahilmgandhi 18:6a4db94011d3 422 if (obj_s->i2c == I2C_3) {
sahilmgandhi 18:6a4db94011d3 423 __HAL_RCC_I2C3_CONFIG(I2CAPI_I2C3_CLKSRC);
sahilmgandhi 18:6a4db94011d3 424 }
sahilmgandhi 18:6a4db94011d3 425 #endif
sahilmgandhi 18:6a4db94011d3 426 #if defined(I2C4_BASE) && defined(__HAL_RCC_I2C4_CONFIG)
sahilmgandhi 18:6a4db94011d3 427 if (obj_s->i2c == I2C_4) {
sahilmgandhi 18:6a4db94011d3 428 __HAL_RCC_I2C4_CONFIG(I2CAPI_I2C4_CLKSRC);
sahilmgandhi 18:6a4db94011d3 429 }
sahilmgandhi 18:6a4db94011d3 430 #endif
sahilmgandhi 18:6a4db94011d3 431
sahilmgandhi 18:6a4db94011d3 432 #ifdef I2C_ANALOGFILTER_ENABLE
sahilmgandhi 18:6a4db94011d3 433 /* Enable the Analog I2C Filter */
sahilmgandhi 18:6a4db94011d3 434 HAL_I2CEx_AnalogFilter_Config(handle,I2C_ANALOGFILTER_ENABLE);
sahilmgandhi 18:6a4db94011d3 435 #endif
sahilmgandhi 18:6a4db94011d3 436
sahilmgandhi 18:6a4db94011d3 437 // I2C configuration
sahilmgandhi 18:6a4db94011d3 438 handle->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
sahilmgandhi 18:6a4db94011d3 439 handle->Init.DualAddressMode = I2C_DUALADDRESS_DISABLED;
sahilmgandhi 18:6a4db94011d3 440 handle->Init.GeneralCallMode = I2C_GENERALCALL_DISABLED;
sahilmgandhi 18:6a4db94011d3 441 handle->Init.NoStretchMode = I2C_NOSTRETCH_DISABLED;
sahilmgandhi 18:6a4db94011d3 442 handle->Init.OwnAddress1 = 0;
sahilmgandhi 18:6a4db94011d3 443 handle->Init.OwnAddress2 = 0;
sahilmgandhi 18:6a4db94011d3 444 HAL_I2C_Init(handle);
sahilmgandhi 18:6a4db94011d3 445
sahilmgandhi 18:6a4db94011d3 446 /* store frequency for timeout computation */
sahilmgandhi 18:6a4db94011d3 447 obj_s->hz = hz;
sahilmgandhi 18:6a4db94011d3 448 }
sahilmgandhi 18:6a4db94011d3 449
sahilmgandhi 18:6a4db94011d3 450 i2c_t *get_i2c_obj(I2C_HandleTypeDef *hi2c){
sahilmgandhi 18:6a4db94011d3 451 /* Aim of the function is to get i2c_s pointer using hi2c pointer */
sahilmgandhi 18:6a4db94011d3 452 /* Highly inspired from magical linux kernel's "container_of" */
sahilmgandhi 18:6a4db94011d3 453 /* (which was not directly used since not compatible with IAR toolchain) */
sahilmgandhi 18:6a4db94011d3 454 struct i2c_s *obj_s;
sahilmgandhi 18:6a4db94011d3 455 i2c_t *obj;
sahilmgandhi 18:6a4db94011d3 456
sahilmgandhi 18:6a4db94011d3 457 obj_s = (struct i2c_s *)( (char *)hi2c - offsetof(struct i2c_s,handle));
sahilmgandhi 18:6a4db94011d3 458 obj = (i2c_t *)( (char *)obj_s - offsetof(i2c_t,i2c));
sahilmgandhi 18:6a4db94011d3 459
sahilmgandhi 18:6a4db94011d3 460 return (obj);
sahilmgandhi 18:6a4db94011d3 461 }
sahilmgandhi 18:6a4db94011d3 462
sahilmgandhi 18:6a4db94011d3 463 void i2c_reset(i2c_t *obj) {
sahilmgandhi 18:6a4db94011d3 464 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 465 /* As recommended in i2c_api.h, mainly send stop */
sahilmgandhi 18:6a4db94011d3 466 i2c_stop(obj);
sahilmgandhi 18:6a4db94011d3 467 /* then re-init */
sahilmgandhi 18:6a4db94011d3 468 i2c_init(obj, obj_s->sda, obj_s->scl);
sahilmgandhi 18:6a4db94011d3 469 }
sahilmgandhi 18:6a4db94011d3 470
sahilmgandhi 18:6a4db94011d3 471 /*
sahilmgandhi 18:6a4db94011d3 472 * UNITARY APIS.
sahilmgandhi 18:6a4db94011d3 473 * For very basic operations, direct registers access is needed
sahilmgandhi 18:6a4db94011d3 474 * There are 2 different IPs version that need to be supported
sahilmgandhi 18:6a4db94011d3 475 */
sahilmgandhi 18:6a4db94011d3 476 #ifdef I2C_IP_VERSION_V1
sahilmgandhi 18:6a4db94011d3 477 int i2c_start(i2c_t *obj) {
sahilmgandhi 18:6a4db94011d3 478
sahilmgandhi 18:6a4db94011d3 479 int timeout;
sahilmgandhi 18:6a4db94011d3 480 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 481 I2C_HandleTypeDef *handle = &(obj_s->handle);
sahilmgandhi 18:6a4db94011d3 482
sahilmgandhi 18:6a4db94011d3 483 // Clear Acknowledge failure flag
sahilmgandhi 18:6a4db94011d3 484 __HAL_I2C_CLEAR_FLAG(handle, I2C_FLAG_AF);
sahilmgandhi 18:6a4db94011d3 485
sahilmgandhi 18:6a4db94011d3 486 // Wait the STOP condition has been previously correctly sent
sahilmgandhi 18:6a4db94011d3 487 // This timeout can be avoid in some specific cases by simply clearing the STOP bit
sahilmgandhi 18:6a4db94011d3 488 timeout = FLAG_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 489 while ((handle->Instance->CR1 & I2C_CR1_STOP) == I2C_CR1_STOP) {
sahilmgandhi 18:6a4db94011d3 490 if ((timeout--) == 0) {
sahilmgandhi 18:6a4db94011d3 491 return 1;
sahilmgandhi 18:6a4db94011d3 492 }
sahilmgandhi 18:6a4db94011d3 493 }
sahilmgandhi 18:6a4db94011d3 494
sahilmgandhi 18:6a4db94011d3 495 // Generate the START condition
sahilmgandhi 18:6a4db94011d3 496 handle->Instance->CR1 |= I2C_CR1_START;
sahilmgandhi 18:6a4db94011d3 497
sahilmgandhi 18:6a4db94011d3 498 // Wait the START condition has been correctly sent
sahilmgandhi 18:6a4db94011d3 499 timeout = FLAG_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 500 while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_SB) == RESET) {
sahilmgandhi 18:6a4db94011d3 501 if ((timeout--) == 0) {
sahilmgandhi 18:6a4db94011d3 502 return 1;
sahilmgandhi 18:6a4db94011d3 503 }
sahilmgandhi 18:6a4db94011d3 504 }
sahilmgandhi 18:6a4db94011d3 505
sahilmgandhi 18:6a4db94011d3 506 return 0;
sahilmgandhi 18:6a4db94011d3 507 }
sahilmgandhi 18:6a4db94011d3 508
sahilmgandhi 18:6a4db94011d3 509 int i2c_stop(i2c_t *obj) {
sahilmgandhi 18:6a4db94011d3 510 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 511 I2C_TypeDef *i2c = (I2C_TypeDef *)obj_s->i2c;
sahilmgandhi 18:6a4db94011d3 512
sahilmgandhi 18:6a4db94011d3 513 // Generate the STOP condition
sahilmgandhi 18:6a4db94011d3 514 i2c->CR1 |= I2C_CR1_STOP;
sahilmgandhi 18:6a4db94011d3 515
sahilmgandhi 18:6a4db94011d3 516 /* In case of mixed usage of the APIs (unitary + SYNC)
sahilmgandhi 18:6a4db94011d3 517 * re-init HAL state
sahilmgandhi 18:6a4db94011d3 518 */
sahilmgandhi 18:6a4db94011d3 519 if(obj_s->XferOperation != I2C_FIRST_AND_LAST_FRAME)
sahilmgandhi 18:6a4db94011d3 520 i2c_init(obj, obj_s->sda, obj_s->scl);
sahilmgandhi 18:6a4db94011d3 521
sahilmgandhi 18:6a4db94011d3 522 return 0;
sahilmgandhi 18:6a4db94011d3 523 }
sahilmgandhi 18:6a4db94011d3 524
sahilmgandhi 18:6a4db94011d3 525 int i2c_byte_read(i2c_t *obj, int last) {
sahilmgandhi 18:6a4db94011d3 526
sahilmgandhi 18:6a4db94011d3 527 int timeout;
sahilmgandhi 18:6a4db94011d3 528 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 529 I2C_HandleTypeDef *handle = &(obj_s->handle);
sahilmgandhi 18:6a4db94011d3 530
sahilmgandhi 18:6a4db94011d3 531 if (last) {
sahilmgandhi 18:6a4db94011d3 532 // Don't acknowledge the last byte
sahilmgandhi 18:6a4db94011d3 533 handle->Instance->CR1 &= ~I2C_CR1_ACK;
sahilmgandhi 18:6a4db94011d3 534 } else {
sahilmgandhi 18:6a4db94011d3 535 // Acknowledge the byte
sahilmgandhi 18:6a4db94011d3 536 handle->Instance->CR1 |= I2C_CR1_ACK;
sahilmgandhi 18:6a4db94011d3 537 }
sahilmgandhi 18:6a4db94011d3 538
sahilmgandhi 18:6a4db94011d3 539 // Wait until the byte is received
sahilmgandhi 18:6a4db94011d3 540 timeout = FLAG_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 541 while (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_RXNE) == RESET) {
sahilmgandhi 18:6a4db94011d3 542 if ((timeout--) == 0) {
sahilmgandhi 18:6a4db94011d3 543 return -1;
sahilmgandhi 18:6a4db94011d3 544 }
sahilmgandhi 18:6a4db94011d3 545 }
sahilmgandhi 18:6a4db94011d3 546
sahilmgandhi 18:6a4db94011d3 547 return (int)handle->Instance->DR;
sahilmgandhi 18:6a4db94011d3 548 }
sahilmgandhi 18:6a4db94011d3 549
sahilmgandhi 18:6a4db94011d3 550 int i2c_byte_write(i2c_t *obj, int data) {
sahilmgandhi 18:6a4db94011d3 551
sahilmgandhi 18:6a4db94011d3 552 int timeout;
sahilmgandhi 18:6a4db94011d3 553 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 554 I2C_HandleTypeDef *handle = &(obj_s->handle);
sahilmgandhi 18:6a4db94011d3 555
sahilmgandhi 18:6a4db94011d3 556 handle->Instance->DR = (uint8_t)data;
sahilmgandhi 18:6a4db94011d3 557
sahilmgandhi 18:6a4db94011d3 558 // Wait until the byte (might be the address) is transmitted
sahilmgandhi 18:6a4db94011d3 559 timeout = FLAG_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 560 while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TXE) == RESET) &&
sahilmgandhi 18:6a4db94011d3 561 (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BTF) == RESET) &&
sahilmgandhi 18:6a4db94011d3 562 (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_ADDR) == RESET)) {
sahilmgandhi 18:6a4db94011d3 563 if ((timeout--) == 0) {
sahilmgandhi 18:6a4db94011d3 564 return 2;
sahilmgandhi 18:6a4db94011d3 565 }
sahilmgandhi 18:6a4db94011d3 566 }
sahilmgandhi 18:6a4db94011d3 567
sahilmgandhi 18:6a4db94011d3 568 if (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_ADDR) != RESET)
sahilmgandhi 18:6a4db94011d3 569 {
sahilmgandhi 18:6a4db94011d3 570 __HAL_I2C_CLEAR_ADDRFLAG(handle);
sahilmgandhi 18:6a4db94011d3 571 }
sahilmgandhi 18:6a4db94011d3 572
sahilmgandhi 18:6a4db94011d3 573 return 1;
sahilmgandhi 18:6a4db94011d3 574 }
sahilmgandhi 18:6a4db94011d3 575 #endif //I2C_IP_VERSION_V1
sahilmgandhi 18:6a4db94011d3 576 #ifdef I2C_IP_VERSION_V2
sahilmgandhi 18:6a4db94011d3 577
sahilmgandhi 18:6a4db94011d3 578 int i2c_start(i2c_t *obj) {
sahilmgandhi 18:6a4db94011d3 579 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 580 /* This I2C IP doesn't */
sahilmgandhi 18:6a4db94011d3 581 obj_s->pending_start = 1;
sahilmgandhi 18:6a4db94011d3 582 return 0;
sahilmgandhi 18:6a4db94011d3 583 }
sahilmgandhi 18:6a4db94011d3 584
sahilmgandhi 18:6a4db94011d3 585 int i2c_stop(i2c_t *obj) {
sahilmgandhi 18:6a4db94011d3 586 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 587 I2C_HandleTypeDef *handle = &(obj_s->handle);
sahilmgandhi 18:6a4db94011d3 588 int timeout = FLAG_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 589 #if DEVICE_I2CSLAVE
sahilmgandhi 18:6a4db94011d3 590 if (obj_s->slave) {
sahilmgandhi 18:6a4db94011d3 591 /* re-init slave when stop is requested */
sahilmgandhi 18:6a4db94011d3 592 i2c_init(obj, obj_s->sda, obj_s->scl);
sahilmgandhi 18:6a4db94011d3 593 return 0;
sahilmgandhi 18:6a4db94011d3 594 }
sahilmgandhi 18:6a4db94011d3 595 #endif
sahilmgandhi 18:6a4db94011d3 596 // Disable reload mode
sahilmgandhi 18:6a4db94011d3 597 handle->Instance->CR2 &= (uint32_t)~I2C_CR2_RELOAD;
sahilmgandhi 18:6a4db94011d3 598 // Generate the STOP condition
sahilmgandhi 18:6a4db94011d3 599 handle->Instance->CR2 |= I2C_CR2_STOP;
sahilmgandhi 18:6a4db94011d3 600
sahilmgandhi 18:6a4db94011d3 601 timeout = FLAG_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 602 while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_STOPF)) {
sahilmgandhi 18:6a4db94011d3 603 if ((timeout--) == 0) {
sahilmgandhi 18:6a4db94011d3 604 return I2C_ERROR_BUS_BUSY;
sahilmgandhi 18:6a4db94011d3 605 }
sahilmgandhi 18:6a4db94011d3 606 }
sahilmgandhi 18:6a4db94011d3 607
sahilmgandhi 18:6a4db94011d3 608 /* Clear STOP Flag */
sahilmgandhi 18:6a4db94011d3 609 __HAL_I2C_CLEAR_FLAG(handle, I2C_FLAG_STOPF);
sahilmgandhi 18:6a4db94011d3 610
sahilmgandhi 18:6a4db94011d3 611 /* Erase slave address, this wiil be used as a marker
sahilmgandhi 18:6a4db94011d3 612 * to know when we need to prepare next start */
sahilmgandhi 18:6a4db94011d3 613 handle->Instance->CR2 &= ~I2C_CR2_SADD;
sahilmgandhi 18:6a4db94011d3 614
sahilmgandhi 18:6a4db94011d3 615 /*
sahilmgandhi 18:6a4db94011d3 616 * V2 IP is meant for automatic STOP, not user STOP
sahilmgandhi 18:6a4db94011d3 617 * SW reset the IP state machine before next transaction
sahilmgandhi 18:6a4db94011d3 618 */
sahilmgandhi 18:6a4db94011d3 619 i2c_sw_reset(obj);
sahilmgandhi 18:6a4db94011d3 620
sahilmgandhi 18:6a4db94011d3 621 /* In case of mixed usage of the APIs (unitary + SYNC)
sahilmgandhi 18:6a4db94011d3 622 * re-init HAL state */
sahilmgandhi 18:6a4db94011d3 623 if (obj_s->XferOperation != I2C_FIRST_AND_LAST_FRAME) {
sahilmgandhi 18:6a4db94011d3 624 i2c_init(obj, obj_s->sda, obj_s->scl);
sahilmgandhi 18:6a4db94011d3 625 }
sahilmgandhi 18:6a4db94011d3 626
sahilmgandhi 18:6a4db94011d3 627 return 0;
sahilmgandhi 18:6a4db94011d3 628 }
sahilmgandhi 18:6a4db94011d3 629
sahilmgandhi 18:6a4db94011d3 630 int i2c_byte_read(i2c_t *obj, int last) {
sahilmgandhi 18:6a4db94011d3 631 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 632 I2C_HandleTypeDef *handle = &(obj_s->handle);
sahilmgandhi 18:6a4db94011d3 633 int timeout = FLAG_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 634 uint32_t tmpreg = handle->Instance->CR2;
sahilmgandhi 18:6a4db94011d3 635 char data;
sahilmgandhi 18:6a4db94011d3 636 #if DEVICE_I2CSLAVE
sahilmgandhi 18:6a4db94011d3 637 if (obj_s->slave) {
sahilmgandhi 18:6a4db94011d3 638 return i2c_slave_read(obj, &data, 1);
sahilmgandhi 18:6a4db94011d3 639 }
sahilmgandhi 18:6a4db94011d3 640 #endif
sahilmgandhi 18:6a4db94011d3 641 /* Then send data when there's room in the TX fifo */
sahilmgandhi 18:6a4db94011d3 642 if ((tmpreg & I2C_CR2_RELOAD) != 0) {
sahilmgandhi 18:6a4db94011d3 643 while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TCR)) {
sahilmgandhi 18:6a4db94011d3 644 if ((timeout--) == 0) {
sahilmgandhi 18:6a4db94011d3 645 DEBUG_PRINTF("timeout in byte_read\r\n");
sahilmgandhi 18:6a4db94011d3 646 return -1;
sahilmgandhi 18:6a4db94011d3 647 }
sahilmgandhi 18:6a4db94011d3 648 }
sahilmgandhi 18:6a4db94011d3 649 }
sahilmgandhi 18:6a4db94011d3 650
sahilmgandhi 18:6a4db94011d3 651 /* Enable reload mode as we don't know how many bytes will be sent */
sahilmgandhi 18:6a4db94011d3 652 /* and set transfer size to 1 */
sahilmgandhi 18:6a4db94011d3 653 tmpreg |= I2C_CR2_RELOAD | (I2C_CR2_NBYTES & (1 << 16));
sahilmgandhi 18:6a4db94011d3 654 /* Set the prepared configuration */
sahilmgandhi 18:6a4db94011d3 655 handle->Instance->CR2 = tmpreg;
sahilmgandhi 18:6a4db94011d3 656
sahilmgandhi 18:6a4db94011d3 657 timeout = FLAG_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 658 while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_RXNE)) {
sahilmgandhi 18:6a4db94011d3 659 if ((timeout--) == 0) {
sahilmgandhi 18:6a4db94011d3 660 return -1;
sahilmgandhi 18:6a4db94011d3 661 }
sahilmgandhi 18:6a4db94011d3 662 }
sahilmgandhi 18:6a4db94011d3 663
sahilmgandhi 18:6a4db94011d3 664 /* Then Get Byte */
sahilmgandhi 18:6a4db94011d3 665 data = handle->Instance->RXDR;
sahilmgandhi 18:6a4db94011d3 666
sahilmgandhi 18:6a4db94011d3 667 if (last) {
sahilmgandhi 18:6a4db94011d3 668 /* Disable Address Acknowledge */
sahilmgandhi 18:6a4db94011d3 669 handle->Instance->CR2 |= I2C_CR2_NACK;
sahilmgandhi 18:6a4db94011d3 670 }
sahilmgandhi 18:6a4db94011d3 671
sahilmgandhi 18:6a4db94011d3 672 return data;
sahilmgandhi 18:6a4db94011d3 673 }
sahilmgandhi 18:6a4db94011d3 674
sahilmgandhi 18:6a4db94011d3 675 int i2c_byte_write(i2c_t *obj, int data) {
sahilmgandhi 18:6a4db94011d3 676 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 677 I2C_HandleTypeDef *handle = &(obj_s->handle);
sahilmgandhi 18:6a4db94011d3 678 int timeout = FLAG_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 679 uint32_t tmpreg = handle->Instance->CR2;
sahilmgandhi 18:6a4db94011d3 680 #if DEVICE_I2CSLAVE
sahilmgandhi 18:6a4db94011d3 681 if (obj_s->slave) {
sahilmgandhi 18:6a4db94011d3 682 return i2c_slave_write(obj, (char *) &data, 1);
sahilmgandhi 18:6a4db94011d3 683 }
sahilmgandhi 18:6a4db94011d3 684 #endif
sahilmgandhi 18:6a4db94011d3 685 if (obj_s->pending_start) {
sahilmgandhi 18:6a4db94011d3 686 obj_s->pending_start = 0;
sahilmgandhi 18:6a4db94011d3 687 //* First byte after the start is the address */
sahilmgandhi 18:6a4db94011d3 688 tmpreg |= (uint32_t)((uint32_t)data & I2C_CR2_SADD);
sahilmgandhi 18:6a4db94011d3 689 if (data & 0x01) {
sahilmgandhi 18:6a4db94011d3 690 tmpreg |= I2C_CR2_START | I2C_CR2_RD_WRN;
sahilmgandhi 18:6a4db94011d3 691 } else {
sahilmgandhi 18:6a4db94011d3 692 tmpreg |= I2C_CR2_START;
sahilmgandhi 18:6a4db94011d3 693 tmpreg &= ~I2C_CR2_RD_WRN;
sahilmgandhi 18:6a4db94011d3 694 }
sahilmgandhi 18:6a4db94011d3 695 /* Disable reload first to use it later */
sahilmgandhi 18:6a4db94011d3 696 tmpreg &= ~I2C_CR2_RELOAD;
sahilmgandhi 18:6a4db94011d3 697 /* Disable Autoend */
sahilmgandhi 18:6a4db94011d3 698 tmpreg &= ~I2C_CR2_AUTOEND;
sahilmgandhi 18:6a4db94011d3 699 /* Do not set any transfer size for now */
sahilmgandhi 18:6a4db94011d3 700 tmpreg |= (I2C_CR2_NBYTES & (1 << 16));
sahilmgandhi 18:6a4db94011d3 701 /* Set the prepared configuration */
sahilmgandhi 18:6a4db94011d3 702 handle->Instance->CR2 = tmpreg;
sahilmgandhi 18:6a4db94011d3 703 } else {
sahilmgandhi 18:6a4db94011d3 704 /* Set the prepared configuration */
sahilmgandhi 18:6a4db94011d3 705 tmpreg = handle->Instance->CR2;
sahilmgandhi 18:6a4db94011d3 706
sahilmgandhi 18:6a4db94011d3 707 /* Then send data when there's room in the TX fifo */
sahilmgandhi 18:6a4db94011d3 708 if ((tmpreg & I2C_CR2_RELOAD) != 0) {
sahilmgandhi 18:6a4db94011d3 709 while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TCR)) {
sahilmgandhi 18:6a4db94011d3 710 if ((timeout--) == 0) {
sahilmgandhi 18:6a4db94011d3 711 DEBUG_PRINTF("timeout in byte_write\r\n");
sahilmgandhi 18:6a4db94011d3 712 return 2;
sahilmgandhi 18:6a4db94011d3 713 }
sahilmgandhi 18:6a4db94011d3 714 }
sahilmgandhi 18:6a4db94011d3 715 }
sahilmgandhi 18:6a4db94011d3 716 /* Enable reload mode as we don't know how many bytes will eb sent */
sahilmgandhi 18:6a4db94011d3 717 tmpreg |= I2C_CR2_RELOAD;
sahilmgandhi 18:6a4db94011d3 718 /* Set transfer size to 1 */
sahilmgandhi 18:6a4db94011d3 719 tmpreg |= (I2C_CR2_NBYTES & (1 << 16));
sahilmgandhi 18:6a4db94011d3 720 /* Set the prepared configuration */
sahilmgandhi 18:6a4db94011d3 721 handle->Instance->CR2 = tmpreg;
sahilmgandhi 18:6a4db94011d3 722 /* Prepare next write */
sahilmgandhi 18:6a4db94011d3 723 timeout = FLAG_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 724 while (!__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TXE)) {
sahilmgandhi 18:6a4db94011d3 725 if ((timeout--) == 0) {
sahilmgandhi 18:6a4db94011d3 726 return 2;
sahilmgandhi 18:6a4db94011d3 727 }
sahilmgandhi 18:6a4db94011d3 728 }
sahilmgandhi 18:6a4db94011d3 729 /* Write byte */
sahilmgandhi 18:6a4db94011d3 730 handle->Instance->TXDR = data;
sahilmgandhi 18:6a4db94011d3 731 }
sahilmgandhi 18:6a4db94011d3 732
sahilmgandhi 18:6a4db94011d3 733 return 1;
sahilmgandhi 18:6a4db94011d3 734 }
sahilmgandhi 18:6a4db94011d3 735 #endif //I2C_IP_VERSION_V2
sahilmgandhi 18:6a4db94011d3 736
sahilmgandhi 18:6a4db94011d3 737 /*
sahilmgandhi 18:6a4db94011d3 738 * SYNC APIS
sahilmgandhi 18:6a4db94011d3 739 */
sahilmgandhi 18:6a4db94011d3 740 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
sahilmgandhi 18:6a4db94011d3 741 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 742 I2C_HandleTypeDef *handle = &(obj_s->handle);
sahilmgandhi 18:6a4db94011d3 743 int count = I2C_ERROR_BUS_BUSY, ret = 0;
sahilmgandhi 18:6a4db94011d3 744 uint32_t timeout = 0;
sahilmgandhi 18:6a4db94011d3 745
sahilmgandhi 18:6a4db94011d3 746 if((length == 0) || (data == 0)) {
sahilmgandhi 18:6a4db94011d3 747 if(HAL_I2C_IsDeviceReady(handle, address, 1, 10) == HAL_OK)
sahilmgandhi 18:6a4db94011d3 748 return 0;
sahilmgandhi 18:6a4db94011d3 749 else
sahilmgandhi 18:6a4db94011d3 750 return I2C_ERROR_BUS_BUSY;
sahilmgandhi 18:6a4db94011d3 751 }
sahilmgandhi 18:6a4db94011d3 752
sahilmgandhi 18:6a4db94011d3 753 if ((obj_s->XferOperation == I2C_FIRST_AND_LAST_FRAME) ||
sahilmgandhi 18:6a4db94011d3 754 (obj_s->XferOperation == I2C_LAST_FRAME)) {
sahilmgandhi 18:6a4db94011d3 755 if (stop)
sahilmgandhi 18:6a4db94011d3 756 obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
sahilmgandhi 18:6a4db94011d3 757 else
sahilmgandhi 18:6a4db94011d3 758 obj_s->XferOperation = I2C_FIRST_FRAME;
sahilmgandhi 18:6a4db94011d3 759 } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
sahilmgandhi 18:6a4db94011d3 760 (obj_s->XferOperation == I2C_NEXT_FRAME)) {
sahilmgandhi 18:6a4db94011d3 761 if (stop)
sahilmgandhi 18:6a4db94011d3 762 obj_s->XferOperation = I2C_LAST_FRAME;
sahilmgandhi 18:6a4db94011d3 763 else
sahilmgandhi 18:6a4db94011d3 764 obj_s->XferOperation = I2C_NEXT_FRAME;
sahilmgandhi 18:6a4db94011d3 765 }
sahilmgandhi 18:6a4db94011d3 766
sahilmgandhi 18:6a4db94011d3 767 obj_s->event = 0;
sahilmgandhi 18:6a4db94011d3 768
sahilmgandhi 18:6a4db94011d3 769 /* Activate default IRQ handlers for sync mode
sahilmgandhi 18:6a4db94011d3 770 * which would be overwritten in async mode
sahilmgandhi 18:6a4db94011d3 771 */
sahilmgandhi 18:6a4db94011d3 772 i2c_ev_err_enable(obj, i2c_get_irq_handler(obj));
sahilmgandhi 18:6a4db94011d3 773
sahilmgandhi 18:6a4db94011d3 774 ret = HAL_I2C_Master_Sequential_Receive_IT(handle, address, (uint8_t *) data, length, obj_s->XferOperation);
sahilmgandhi 18:6a4db94011d3 775
sahilmgandhi 18:6a4db94011d3 776 if(ret == HAL_OK) {
sahilmgandhi 18:6a4db94011d3 777 timeout = BYTE_TIMEOUT_US * (length + 1);
sahilmgandhi 18:6a4db94011d3 778 /* transfer started : wait completion or timeout */
sahilmgandhi 18:6a4db94011d3 779 while(!(obj_s->event & I2C_EVENT_ALL) && (--timeout != 0)) {
sahilmgandhi 18:6a4db94011d3 780 wait_us(1);
sahilmgandhi 18:6a4db94011d3 781 }
sahilmgandhi 18:6a4db94011d3 782
sahilmgandhi 18:6a4db94011d3 783 i2c_ev_err_disable(obj);
sahilmgandhi 18:6a4db94011d3 784
sahilmgandhi 18:6a4db94011d3 785 if((timeout == 0) || (obj_s->event != I2C_EVENT_TRANSFER_COMPLETE)) {
sahilmgandhi 18:6a4db94011d3 786 DEBUG_PRINTF(" TIMEOUT or error in i2c_read\r\n");
sahilmgandhi 18:6a4db94011d3 787 /* re-init IP to try and get back in a working state */
sahilmgandhi 18:6a4db94011d3 788 i2c_init(obj, obj_s->sda, obj_s->scl);
sahilmgandhi 18:6a4db94011d3 789 } else {
sahilmgandhi 18:6a4db94011d3 790 count = length;
sahilmgandhi 18:6a4db94011d3 791 }
sahilmgandhi 18:6a4db94011d3 792 } else {
sahilmgandhi 18:6a4db94011d3 793 DEBUG_PRINTF("ERROR in i2c_read:%d\r\n", ret);
sahilmgandhi 18:6a4db94011d3 794 }
sahilmgandhi 18:6a4db94011d3 795
sahilmgandhi 18:6a4db94011d3 796 return count;
sahilmgandhi 18:6a4db94011d3 797 }
sahilmgandhi 18:6a4db94011d3 798
sahilmgandhi 18:6a4db94011d3 799 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
sahilmgandhi 18:6a4db94011d3 800 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 801 I2C_HandleTypeDef *handle = &(obj_s->handle);
sahilmgandhi 18:6a4db94011d3 802 int count = I2C_ERROR_BUS_BUSY, ret = 0;
sahilmgandhi 18:6a4db94011d3 803 uint32_t timeout = 0;
sahilmgandhi 18:6a4db94011d3 804
sahilmgandhi 18:6a4db94011d3 805 if((length == 0) || (data == 0)) {
sahilmgandhi 18:6a4db94011d3 806 if(HAL_I2C_IsDeviceReady(handle, address, 1, 10) == HAL_OK)
sahilmgandhi 18:6a4db94011d3 807 return 0;
sahilmgandhi 18:6a4db94011d3 808 else
sahilmgandhi 18:6a4db94011d3 809 return I2C_ERROR_BUS_BUSY;
sahilmgandhi 18:6a4db94011d3 810 }
sahilmgandhi 18:6a4db94011d3 811
sahilmgandhi 18:6a4db94011d3 812 if ((obj_s->XferOperation == I2C_FIRST_AND_LAST_FRAME) ||
sahilmgandhi 18:6a4db94011d3 813 (obj_s->XferOperation == I2C_LAST_FRAME)) {
sahilmgandhi 18:6a4db94011d3 814 if (stop)
sahilmgandhi 18:6a4db94011d3 815 obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
sahilmgandhi 18:6a4db94011d3 816 else
sahilmgandhi 18:6a4db94011d3 817 obj_s->XferOperation = I2C_FIRST_FRAME;
sahilmgandhi 18:6a4db94011d3 818 } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
sahilmgandhi 18:6a4db94011d3 819 (obj_s->XferOperation == I2C_NEXT_FRAME)) {
sahilmgandhi 18:6a4db94011d3 820 if (stop)
sahilmgandhi 18:6a4db94011d3 821 obj_s->XferOperation = I2C_LAST_FRAME;
sahilmgandhi 18:6a4db94011d3 822 else
sahilmgandhi 18:6a4db94011d3 823 obj_s->XferOperation = I2C_NEXT_FRAME;
sahilmgandhi 18:6a4db94011d3 824 }
sahilmgandhi 18:6a4db94011d3 825
sahilmgandhi 18:6a4db94011d3 826 obj_s->event = 0;
sahilmgandhi 18:6a4db94011d3 827
sahilmgandhi 18:6a4db94011d3 828 i2c_ev_err_enable(obj, i2c_get_irq_handler(obj));
sahilmgandhi 18:6a4db94011d3 829
sahilmgandhi 18:6a4db94011d3 830 ret = HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t *) data, length, obj_s->XferOperation);
sahilmgandhi 18:6a4db94011d3 831
sahilmgandhi 18:6a4db94011d3 832 if(ret == HAL_OK) {
sahilmgandhi 18:6a4db94011d3 833 timeout = BYTE_TIMEOUT_US * (length + 1);
sahilmgandhi 18:6a4db94011d3 834 /* transfer started : wait completion or timeout */
sahilmgandhi 18:6a4db94011d3 835 while(!(obj_s->event & I2C_EVENT_ALL) && (--timeout != 0)) {
sahilmgandhi 18:6a4db94011d3 836 wait_us(1);
sahilmgandhi 18:6a4db94011d3 837 }
sahilmgandhi 18:6a4db94011d3 838
sahilmgandhi 18:6a4db94011d3 839 i2c_ev_err_disable(obj);
sahilmgandhi 18:6a4db94011d3 840
sahilmgandhi 18:6a4db94011d3 841 if((timeout == 0) || (obj_s->event != I2C_EVENT_TRANSFER_COMPLETE)) {
sahilmgandhi 18:6a4db94011d3 842 DEBUG_PRINTF(" TIMEOUT or error in i2c_write\r\n");
sahilmgandhi 18:6a4db94011d3 843 /* re-init IP to try and get back in a working state */
sahilmgandhi 18:6a4db94011d3 844 i2c_init(obj, obj_s->sda, obj_s->scl);
sahilmgandhi 18:6a4db94011d3 845 } else {
sahilmgandhi 18:6a4db94011d3 846 count = length;
sahilmgandhi 18:6a4db94011d3 847 }
sahilmgandhi 18:6a4db94011d3 848 } else {
sahilmgandhi 18:6a4db94011d3 849 DEBUG_PRINTF("ERROR in i2c_read\r\n");
sahilmgandhi 18:6a4db94011d3 850 }
sahilmgandhi 18:6a4db94011d3 851
sahilmgandhi 18:6a4db94011d3 852 return count;
sahilmgandhi 18:6a4db94011d3 853 }
sahilmgandhi 18:6a4db94011d3 854
sahilmgandhi 18:6a4db94011d3 855 void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c){
sahilmgandhi 18:6a4db94011d3 856 /* Get object ptr based on handler ptr */
sahilmgandhi 18:6a4db94011d3 857 i2c_t *obj = get_i2c_obj(hi2c);
sahilmgandhi 18:6a4db94011d3 858 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 859
sahilmgandhi 18:6a4db94011d3 860 #if DEVICE_I2C_ASYNCH
sahilmgandhi 18:6a4db94011d3 861 /* Handle potential Tx/Rx use case */
sahilmgandhi 18:6a4db94011d3 862 if ((obj->tx_buff.length) && (obj->rx_buff.length)) {
sahilmgandhi 18:6a4db94011d3 863 if (obj_s->stop) {
sahilmgandhi 18:6a4db94011d3 864 obj_s->XferOperation = I2C_LAST_FRAME;
sahilmgandhi 18:6a4db94011d3 865 } else {
sahilmgandhi 18:6a4db94011d3 866 obj_s->XferOperation = I2C_NEXT_FRAME;
sahilmgandhi 18:6a4db94011d3 867 }
sahilmgandhi 18:6a4db94011d3 868
sahilmgandhi 18:6a4db94011d3 869 HAL_I2C_Master_Sequential_Receive_IT(hi2c, obj_s->address, (uint8_t*)obj->rx_buff.buffer , obj->rx_buff.length, obj_s->XferOperation);
sahilmgandhi 18:6a4db94011d3 870 }
sahilmgandhi 18:6a4db94011d3 871 else
sahilmgandhi 18:6a4db94011d3 872 #endif
sahilmgandhi 18:6a4db94011d3 873 {
sahilmgandhi 18:6a4db94011d3 874 /* Set event flag */
sahilmgandhi 18:6a4db94011d3 875 obj_s->event = I2C_EVENT_TRANSFER_COMPLETE;
sahilmgandhi 18:6a4db94011d3 876 }
sahilmgandhi 18:6a4db94011d3 877 }
sahilmgandhi 18:6a4db94011d3 878
sahilmgandhi 18:6a4db94011d3 879 void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c){
sahilmgandhi 18:6a4db94011d3 880 /* Get object ptr based on handler ptr */
sahilmgandhi 18:6a4db94011d3 881 i2c_t *obj = get_i2c_obj(hi2c);
sahilmgandhi 18:6a4db94011d3 882 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 883
sahilmgandhi 18:6a4db94011d3 884 /* Set event flag */
sahilmgandhi 18:6a4db94011d3 885 obj_s->event = I2C_EVENT_TRANSFER_COMPLETE;
sahilmgandhi 18:6a4db94011d3 886 }
sahilmgandhi 18:6a4db94011d3 887
sahilmgandhi 18:6a4db94011d3 888 void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c){
sahilmgandhi 18:6a4db94011d3 889 /* Get object ptr based on handler ptr */
sahilmgandhi 18:6a4db94011d3 890 i2c_t *obj = get_i2c_obj(hi2c);
sahilmgandhi 18:6a4db94011d3 891 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 892 #if DEVICE_I2CSLAVE
sahilmgandhi 18:6a4db94011d3 893 I2C_HandleTypeDef *handle = &(obj_s->handle);
sahilmgandhi 18:6a4db94011d3 894 uint32_t address = 0;
sahilmgandhi 18:6a4db94011d3 895 /* Store address to handle it after reset */
sahilmgandhi 18:6a4db94011d3 896 if(obj_s->slave)
sahilmgandhi 18:6a4db94011d3 897 address = handle->Init.OwnAddress1;
sahilmgandhi 18:6a4db94011d3 898 #endif
sahilmgandhi 18:6a4db94011d3 899
sahilmgandhi 18:6a4db94011d3 900 DEBUG_PRINTF("HAL_I2C_ErrorCallback:%d, index=%d\r\n", (int) hi2c->ErrorCode, obj_s->index);
sahilmgandhi 18:6a4db94011d3 901
sahilmgandhi 18:6a4db94011d3 902 /* re-init IP to try and get back in a working state */
sahilmgandhi 18:6a4db94011d3 903 i2c_init(obj, obj_s->sda, obj_s->scl);
sahilmgandhi 18:6a4db94011d3 904
sahilmgandhi 18:6a4db94011d3 905 #if DEVICE_I2CSLAVE
sahilmgandhi 18:6a4db94011d3 906 /* restore slave address */
sahilmgandhi 18:6a4db94011d3 907 if (address != 0) {
sahilmgandhi 18:6a4db94011d3 908 obj_s->slave = 1;
sahilmgandhi 18:6a4db94011d3 909 i2c_slave_address(obj, 0, address, 0);
sahilmgandhi 18:6a4db94011d3 910 }
sahilmgandhi 18:6a4db94011d3 911 #endif
sahilmgandhi 18:6a4db94011d3 912
sahilmgandhi 18:6a4db94011d3 913 /* Keep Set event flag */
sahilmgandhi 18:6a4db94011d3 914 obj_s->event = I2C_EVENT_ERROR;
sahilmgandhi 18:6a4db94011d3 915 }
sahilmgandhi 18:6a4db94011d3 916
sahilmgandhi 18:6a4db94011d3 917 #if DEVICE_I2CSLAVE
sahilmgandhi 18:6a4db94011d3 918 /* SLAVE API FUNCTIONS */
sahilmgandhi 18:6a4db94011d3 919 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
sahilmgandhi 18:6a4db94011d3 920 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 921 I2C_HandleTypeDef *handle = &(obj_s->handle);
sahilmgandhi 18:6a4db94011d3 922
sahilmgandhi 18:6a4db94011d3 923 // I2C configuration
sahilmgandhi 18:6a4db94011d3 924 handle->Init.OwnAddress1 = address;
sahilmgandhi 18:6a4db94011d3 925 HAL_I2C_Init(handle);
sahilmgandhi 18:6a4db94011d3 926
sahilmgandhi 18:6a4db94011d3 927 i2c_ev_err_enable(obj, i2c_get_irq_handler(obj));
sahilmgandhi 18:6a4db94011d3 928
sahilmgandhi 18:6a4db94011d3 929 HAL_I2C_EnableListen_IT(handle);
sahilmgandhi 18:6a4db94011d3 930 }
sahilmgandhi 18:6a4db94011d3 931
sahilmgandhi 18:6a4db94011d3 932 void i2c_slave_mode(i2c_t *obj, int enable_slave) {
sahilmgandhi 18:6a4db94011d3 933
sahilmgandhi 18:6a4db94011d3 934 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 935 I2C_HandleTypeDef *handle = &(obj_s->handle);
sahilmgandhi 18:6a4db94011d3 936
sahilmgandhi 18:6a4db94011d3 937 if (enable_slave) {
sahilmgandhi 18:6a4db94011d3 938 obj_s->slave = 1;
sahilmgandhi 18:6a4db94011d3 939 HAL_I2C_EnableListen_IT(handle);
sahilmgandhi 18:6a4db94011d3 940 } else {
sahilmgandhi 18:6a4db94011d3 941 obj_s->slave = 0;
sahilmgandhi 18:6a4db94011d3 942 HAL_I2C_DisableListen_IT(handle);
sahilmgandhi 18:6a4db94011d3 943 }
sahilmgandhi 18:6a4db94011d3 944 }
sahilmgandhi 18:6a4db94011d3 945
sahilmgandhi 18:6a4db94011d3 946 // See I2CSlave.h
sahilmgandhi 18:6a4db94011d3 947 #define NoData 0 // the slave has not been addressed
sahilmgandhi 18:6a4db94011d3 948 #define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter)
sahilmgandhi 18:6a4db94011d3 949 #define WriteGeneral 2 // the master is writing to all slave
sahilmgandhi 18:6a4db94011d3 950 #define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
sahilmgandhi 18:6a4db94011d3 951
sahilmgandhi 18:6a4db94011d3 952
sahilmgandhi 18:6a4db94011d3 953 void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) {
sahilmgandhi 18:6a4db94011d3 954 /* Get object ptr based on handler ptr */
sahilmgandhi 18:6a4db94011d3 955 i2c_t *obj = get_i2c_obj(hi2c);
sahilmgandhi 18:6a4db94011d3 956 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 957
sahilmgandhi 18:6a4db94011d3 958 /* Transfer direction in HAL is from Master point of view */
sahilmgandhi 18:6a4db94011d3 959 if(TransferDirection == I2C_DIRECTION_RECEIVE) {
sahilmgandhi 18:6a4db94011d3 960 obj_s->pending_slave_tx_master_rx = 1;
sahilmgandhi 18:6a4db94011d3 961 }
sahilmgandhi 18:6a4db94011d3 962
sahilmgandhi 18:6a4db94011d3 963 if(TransferDirection == I2C_DIRECTION_TRANSMIT) {
sahilmgandhi 18:6a4db94011d3 964 obj_s->pending_slave_rx_maxter_tx = 1;
sahilmgandhi 18:6a4db94011d3 965 }
sahilmgandhi 18:6a4db94011d3 966 }
sahilmgandhi 18:6a4db94011d3 967
sahilmgandhi 18:6a4db94011d3 968 void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *I2cHandle){
sahilmgandhi 18:6a4db94011d3 969 /* Get object ptr based on handler ptr */
sahilmgandhi 18:6a4db94011d3 970 i2c_t *obj = get_i2c_obj(I2cHandle);
sahilmgandhi 18:6a4db94011d3 971 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 972 obj_s->pending_slave_tx_master_rx = 0;
sahilmgandhi 18:6a4db94011d3 973 }
sahilmgandhi 18:6a4db94011d3 974
sahilmgandhi 18:6a4db94011d3 975 void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *I2cHandle){
sahilmgandhi 18:6a4db94011d3 976 /* Get object ptr based on handler ptr */
sahilmgandhi 18:6a4db94011d3 977 i2c_t *obj = get_i2c_obj(I2cHandle);
sahilmgandhi 18:6a4db94011d3 978 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 979 obj_s->pending_slave_rx_maxter_tx = 0;
sahilmgandhi 18:6a4db94011d3 980 }
sahilmgandhi 18:6a4db94011d3 981
sahilmgandhi 18:6a4db94011d3 982 void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
sahilmgandhi 18:6a4db94011d3 983 {
sahilmgandhi 18:6a4db94011d3 984 /* restart listening for master requests */
sahilmgandhi 18:6a4db94011d3 985 HAL_I2C_EnableListen_IT(hi2c);
sahilmgandhi 18:6a4db94011d3 986 }
sahilmgandhi 18:6a4db94011d3 987
sahilmgandhi 18:6a4db94011d3 988 int i2c_slave_receive(i2c_t *obj) {
sahilmgandhi 18:6a4db94011d3 989
sahilmgandhi 18:6a4db94011d3 990 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 991 int retValue = NoData;
sahilmgandhi 18:6a4db94011d3 992
sahilmgandhi 18:6a4db94011d3 993 if(obj_s->pending_slave_rx_maxter_tx) {
sahilmgandhi 18:6a4db94011d3 994 retValue = WriteAddressed;
sahilmgandhi 18:6a4db94011d3 995 }
sahilmgandhi 18:6a4db94011d3 996
sahilmgandhi 18:6a4db94011d3 997 if(obj_s->pending_slave_tx_master_rx) {
sahilmgandhi 18:6a4db94011d3 998 retValue = ReadAddressed;
sahilmgandhi 18:6a4db94011d3 999 }
sahilmgandhi 18:6a4db94011d3 1000
sahilmgandhi 18:6a4db94011d3 1001 return (retValue);
sahilmgandhi 18:6a4db94011d3 1002 }
sahilmgandhi 18:6a4db94011d3 1003
sahilmgandhi 18:6a4db94011d3 1004 int i2c_slave_read(i2c_t *obj, char *data, int length) {
sahilmgandhi 18:6a4db94011d3 1005 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 1006 I2C_HandleTypeDef *handle = &(obj_s->handle);
sahilmgandhi 18:6a4db94011d3 1007 int count = 0;
sahilmgandhi 18:6a4db94011d3 1008 int ret = 0;
sahilmgandhi 18:6a4db94011d3 1009 uint32_t timeout = 0;
sahilmgandhi 18:6a4db94011d3 1010
sahilmgandhi 18:6a4db94011d3 1011 /* Always use I2C_NEXT_FRAME as slave will just adapt to master requests */
sahilmgandhi 18:6a4db94011d3 1012 ret = HAL_I2C_Slave_Sequential_Receive_IT(handle, (uint8_t *) data, length, I2C_NEXT_FRAME);
sahilmgandhi 18:6a4db94011d3 1013
sahilmgandhi 18:6a4db94011d3 1014 if(ret == HAL_OK) {
sahilmgandhi 18:6a4db94011d3 1015 timeout = BYTE_TIMEOUT_US * (length + 1);
sahilmgandhi 18:6a4db94011d3 1016 while(obj_s->pending_slave_rx_maxter_tx && (--timeout != 0)) {
sahilmgandhi 18:6a4db94011d3 1017 wait_us(1);
sahilmgandhi 18:6a4db94011d3 1018 }
sahilmgandhi 18:6a4db94011d3 1019
sahilmgandhi 18:6a4db94011d3 1020 if(timeout != 0) {
sahilmgandhi 18:6a4db94011d3 1021 count = length;
sahilmgandhi 18:6a4db94011d3 1022 } else {
sahilmgandhi 18:6a4db94011d3 1023 DEBUG_PRINTF("TIMEOUT or error in i2c_slave_read\r\n");
sahilmgandhi 18:6a4db94011d3 1024 }
sahilmgandhi 18:6a4db94011d3 1025 }
sahilmgandhi 18:6a4db94011d3 1026 return count;
sahilmgandhi 18:6a4db94011d3 1027 }
sahilmgandhi 18:6a4db94011d3 1028
sahilmgandhi 18:6a4db94011d3 1029 int i2c_slave_write(i2c_t *obj, const char *data, int length) {
sahilmgandhi 18:6a4db94011d3 1030 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 1031 I2C_HandleTypeDef *handle = &(obj_s->handle);
sahilmgandhi 18:6a4db94011d3 1032 int count = 0;
sahilmgandhi 18:6a4db94011d3 1033 int ret = 0;
sahilmgandhi 18:6a4db94011d3 1034 uint32_t timeout = 0;
sahilmgandhi 18:6a4db94011d3 1035
sahilmgandhi 18:6a4db94011d3 1036 /* Always use I2C_NEXT_FRAME as slave will just adapt to master requests */
sahilmgandhi 18:6a4db94011d3 1037 ret = HAL_I2C_Slave_Sequential_Transmit_IT(handle, (uint8_t *) data, length, I2C_NEXT_FRAME);
sahilmgandhi 18:6a4db94011d3 1038
sahilmgandhi 18:6a4db94011d3 1039 if(ret == HAL_OK) {
sahilmgandhi 18:6a4db94011d3 1040 timeout = BYTE_TIMEOUT_US * (length + 1);
sahilmgandhi 18:6a4db94011d3 1041 while(obj_s->pending_slave_tx_master_rx && (--timeout != 0)) {
sahilmgandhi 18:6a4db94011d3 1042 wait_us(1);
sahilmgandhi 18:6a4db94011d3 1043 }
sahilmgandhi 18:6a4db94011d3 1044
sahilmgandhi 18:6a4db94011d3 1045 if(timeout != 0) {
sahilmgandhi 18:6a4db94011d3 1046 count = length;
sahilmgandhi 18:6a4db94011d3 1047 } else {
sahilmgandhi 18:6a4db94011d3 1048 DEBUG_PRINTF("TIMEOUT or error in i2c_slave_write\r\n");
sahilmgandhi 18:6a4db94011d3 1049 }
sahilmgandhi 18:6a4db94011d3 1050 }
sahilmgandhi 18:6a4db94011d3 1051
sahilmgandhi 18:6a4db94011d3 1052 return count;
sahilmgandhi 18:6a4db94011d3 1053 }
sahilmgandhi 18:6a4db94011d3 1054 #endif // DEVICE_I2CSLAVE
sahilmgandhi 18:6a4db94011d3 1055
sahilmgandhi 18:6a4db94011d3 1056 #if DEVICE_I2C_ASYNCH
sahilmgandhi 18:6a4db94011d3 1057 /* ASYNCH MASTER API FUNCTIONS */
sahilmgandhi 18:6a4db94011d3 1058 void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c){
sahilmgandhi 18:6a4db94011d3 1059 /* Get object ptr based on handler ptr */
sahilmgandhi 18:6a4db94011d3 1060 i2c_t *obj = get_i2c_obj(hi2c);
sahilmgandhi 18:6a4db94011d3 1061 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 1062 I2C_HandleTypeDef *handle = &(obj_s->handle);
sahilmgandhi 18:6a4db94011d3 1063
sahilmgandhi 18:6a4db94011d3 1064 /* Disable IT. Not always done before calling macro */
sahilmgandhi 18:6a4db94011d3 1065 __HAL_I2C_DISABLE_IT(handle, I2C_IT_ALL);
sahilmgandhi 18:6a4db94011d3 1066 i2c_ev_err_disable(obj);
sahilmgandhi 18:6a4db94011d3 1067
sahilmgandhi 18:6a4db94011d3 1068 /* Set event flag */
sahilmgandhi 18:6a4db94011d3 1069 obj_s->event = I2C_EVENT_ERROR;
sahilmgandhi 18:6a4db94011d3 1070 }
sahilmgandhi 18:6a4db94011d3 1071
sahilmgandhi 18:6a4db94011d3 1072 void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint) {
sahilmgandhi 18:6a4db94011d3 1073
sahilmgandhi 18:6a4db94011d3 1074 // TODO: DMA usage is currently ignored by this way
sahilmgandhi 18:6a4db94011d3 1075 (void) hint;
sahilmgandhi 18:6a4db94011d3 1076
sahilmgandhi 18:6a4db94011d3 1077 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 1078 I2C_HandleTypeDef *handle = &(obj_s->handle);
sahilmgandhi 18:6a4db94011d3 1079
sahilmgandhi 18:6a4db94011d3 1080 /* Update object */
sahilmgandhi 18:6a4db94011d3 1081 obj->tx_buff.buffer = (void *)tx;
sahilmgandhi 18:6a4db94011d3 1082 obj->tx_buff.length = tx_length;
sahilmgandhi 18:6a4db94011d3 1083 obj->tx_buff.pos = 0;
sahilmgandhi 18:6a4db94011d3 1084 obj->tx_buff.width = 8;
sahilmgandhi 18:6a4db94011d3 1085
sahilmgandhi 18:6a4db94011d3 1086 obj->rx_buff.buffer = (void *)rx;
sahilmgandhi 18:6a4db94011d3 1087 obj->rx_buff.length = rx_length;
sahilmgandhi 18:6a4db94011d3 1088 obj->rx_buff.pos = SIZE_MAX;
sahilmgandhi 18:6a4db94011d3 1089 obj->rx_buff.width = 8;
sahilmgandhi 18:6a4db94011d3 1090
sahilmgandhi 18:6a4db94011d3 1091 obj_s->available_events = event;
sahilmgandhi 18:6a4db94011d3 1092 obj_s->event = 0;
sahilmgandhi 18:6a4db94011d3 1093 obj_s->address = address;
sahilmgandhi 18:6a4db94011d3 1094 obj_s->stop = stop;
sahilmgandhi 18:6a4db94011d3 1095
sahilmgandhi 18:6a4db94011d3 1096 i2c_ev_err_enable(obj, handler);
sahilmgandhi 18:6a4db94011d3 1097
sahilmgandhi 18:6a4db94011d3 1098 /* Set operation step depending if stop sending required or not */
sahilmgandhi 18:6a4db94011d3 1099 if ((tx_length && !rx_length) || (!tx_length && rx_length)) {
sahilmgandhi 18:6a4db94011d3 1100 if ((obj_s->XferOperation == I2C_FIRST_AND_LAST_FRAME) ||
sahilmgandhi 18:6a4db94011d3 1101 (obj_s->XferOperation == I2C_LAST_FRAME)) {
sahilmgandhi 18:6a4db94011d3 1102 if (stop)
sahilmgandhi 18:6a4db94011d3 1103 obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
sahilmgandhi 18:6a4db94011d3 1104 else
sahilmgandhi 18:6a4db94011d3 1105 obj_s->XferOperation = I2C_FIRST_FRAME;
sahilmgandhi 18:6a4db94011d3 1106 } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
sahilmgandhi 18:6a4db94011d3 1107 (obj_s->XferOperation == I2C_NEXT_FRAME)) {
sahilmgandhi 18:6a4db94011d3 1108 if (stop)
sahilmgandhi 18:6a4db94011d3 1109 obj_s->XferOperation = I2C_LAST_FRAME;
sahilmgandhi 18:6a4db94011d3 1110 else
sahilmgandhi 18:6a4db94011d3 1111 obj_s->XferOperation = I2C_NEXT_FRAME;
sahilmgandhi 18:6a4db94011d3 1112 }
sahilmgandhi 18:6a4db94011d3 1113
sahilmgandhi 18:6a4db94011d3 1114 if (tx_length > 0) {
sahilmgandhi 18:6a4db94011d3 1115 HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t*)tx, tx_length, obj_s->XferOperation);
sahilmgandhi 18:6a4db94011d3 1116 }
sahilmgandhi 18:6a4db94011d3 1117 if (rx_length > 0) {
sahilmgandhi 18:6a4db94011d3 1118 HAL_I2C_Master_Sequential_Receive_IT(handle, address, (uint8_t*)rx, rx_length, obj_s->XferOperation);
sahilmgandhi 18:6a4db94011d3 1119 }
sahilmgandhi 18:6a4db94011d3 1120 }
sahilmgandhi 18:6a4db94011d3 1121 else if (tx_length && rx_length) {
sahilmgandhi 18:6a4db94011d3 1122 /* Two steps operation, don't modify XferOperation, keep it for next step */
sahilmgandhi 18:6a4db94011d3 1123 if ((obj_s->XferOperation == I2C_FIRST_AND_LAST_FRAME) ||
sahilmgandhi 18:6a4db94011d3 1124 (obj_s->XferOperation == I2C_LAST_FRAME)) {
sahilmgandhi 18:6a4db94011d3 1125 HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t*)tx, tx_length, I2C_FIRST_FRAME);
sahilmgandhi 18:6a4db94011d3 1126 } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
sahilmgandhi 18:6a4db94011d3 1127 (obj_s->XferOperation == I2C_NEXT_FRAME)) {
sahilmgandhi 18:6a4db94011d3 1128 HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t*)tx, tx_length, I2C_NEXT_FRAME);
sahilmgandhi 18:6a4db94011d3 1129 }
sahilmgandhi 18:6a4db94011d3 1130 }
sahilmgandhi 18:6a4db94011d3 1131 }
sahilmgandhi 18:6a4db94011d3 1132
sahilmgandhi 18:6a4db94011d3 1133
sahilmgandhi 18:6a4db94011d3 1134 uint32_t i2c_irq_handler_asynch(i2c_t *obj) {
sahilmgandhi 18:6a4db94011d3 1135
sahilmgandhi 18:6a4db94011d3 1136 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 1137 I2C_HandleTypeDef *handle = &(obj_s->handle);
sahilmgandhi 18:6a4db94011d3 1138
sahilmgandhi 18:6a4db94011d3 1139 HAL_I2C_EV_IRQHandler(handle);
sahilmgandhi 18:6a4db94011d3 1140 HAL_I2C_ER_IRQHandler(handle);
sahilmgandhi 18:6a4db94011d3 1141
sahilmgandhi 18:6a4db94011d3 1142 /* Return I2C event status */
sahilmgandhi 18:6a4db94011d3 1143 return (obj_s->event & obj_s->available_events);
sahilmgandhi 18:6a4db94011d3 1144 }
sahilmgandhi 18:6a4db94011d3 1145
sahilmgandhi 18:6a4db94011d3 1146 uint8_t i2c_active(i2c_t *obj) {
sahilmgandhi 18:6a4db94011d3 1147
sahilmgandhi 18:6a4db94011d3 1148 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 1149 I2C_HandleTypeDef *handle = &(obj_s->handle);
sahilmgandhi 18:6a4db94011d3 1150
sahilmgandhi 18:6a4db94011d3 1151 if (handle->State == HAL_I2C_STATE_READY) {
sahilmgandhi 18:6a4db94011d3 1152 return 0;
sahilmgandhi 18:6a4db94011d3 1153 }
sahilmgandhi 18:6a4db94011d3 1154 else {
sahilmgandhi 18:6a4db94011d3 1155 return 1;
sahilmgandhi 18:6a4db94011d3 1156 }
sahilmgandhi 18:6a4db94011d3 1157 }
sahilmgandhi 18:6a4db94011d3 1158
sahilmgandhi 18:6a4db94011d3 1159 void i2c_abort_asynch(i2c_t *obj) {
sahilmgandhi 18:6a4db94011d3 1160
sahilmgandhi 18:6a4db94011d3 1161 struct i2c_s *obj_s = I2C_S(obj);
sahilmgandhi 18:6a4db94011d3 1162 I2C_HandleTypeDef *handle = &(obj_s->handle);
sahilmgandhi 18:6a4db94011d3 1163
sahilmgandhi 18:6a4db94011d3 1164 /* Abort HAL requires DevAddress, but is not used. Use Dummy */
sahilmgandhi 18:6a4db94011d3 1165 uint16_t Dummy_DevAddress = 0x00;
sahilmgandhi 18:6a4db94011d3 1166
sahilmgandhi 18:6a4db94011d3 1167 HAL_I2C_Master_Abort_IT(handle, Dummy_DevAddress);
sahilmgandhi 18:6a4db94011d3 1168 }
sahilmgandhi 18:6a4db94011d3 1169
sahilmgandhi 18:6a4db94011d3 1170 #endif // DEVICE_I2C_ASYNCH
sahilmgandhi 18:6a4db94011d3 1171
sahilmgandhi 18:6a4db94011d3 1172 #endif // DEVICE_I2C